diff --git a/.gitignore b/.gitignore index 114d074..8673e48 100644 --- a/.gitignore +++ b/.gitignore @@ -1,20 +1,25 @@ -nxpvee-mimxrt595-evk-round-fp/lib/ -nxpvee-mimxrt595-evk-round-configuration/target~/ -nxpvee-mimxrt595-evk-round-configuration/dropins/include/ -nxpvee-mimxrt595-evk-round-configuration/dropins/javaLibs/ -nxpvee-mimxrt595-evk-round-configuration/dropins/mocks/ -nxpvee-mimxrt595-evk-round-configuration/dropins/scripts/ -nxpvee-mimxrt595-evk-round-configuration/dropins/tools/license-checker.jar -nxpvee-mimxrt595-evk-round-configuration/dropins/tools/imagegenerator-vectorimage.jar -nxpvee-mimxrt595-evk-round-configuration/dropins/resources/os/ -nxpvee-mimxrt595-evk-round-configuration/dropins/workbenchExtension_* -nxpvee-mimxrt595-evk-round-bsp/projects/microej/platform/ -MIMXRT595-*-CM4hardfp_GCC48-* -nxpvee-mimxrt595-evk-round-imageGenerator/bin/ -nxpvee-mimxrt595-evk-round-configuration/dropins/scripts/init-microvg/microvginit.xml -nxpvee-mimxrt595-evk-round-bsp/projects/microej/vglite_patch/ +microej/front-panel/lib/ +microej/vee-port-configuration/target~/ +microej/vee-port-configuration/dropins/include/ +microej/vee-port-configuration/dropins/javaLibs/ +microej/vee-port-configuration/dropins/mocks/ +microej/vee-port-configuration/dropins/scripts/ +microej/vee-port-configuration/dropins/tools/license-checker.jar +microej/vee-port-configuration/dropins/tools/imagegenerator-vectorimage.jar +microej/vee-port-configuration/dropins/resources/os/ +microej/vee-port-configuration/dropins/workbenchExtension_* +microej/vee-port-configuration/dropins/scripts/init-microvg/microvginit.xml +microej/imageGenerator/bin/ +microej/apps/launchers/*.properties +microej/MIMXRT595-*-CM4hardfp_GCC48-* -nxpvee-mimxrt595-evk-round-apps/launchers/*.properties +bsp/projects/microej/vglite_patch/ +bsp/projects/microej/platform/ +bsp/projects/nxpvee-ui/armgcc/mcux_include.json +bsp/projects/nxpvee-ui/armgcc/tree_version.c +bsp/mcux-sdk +bsp/projects/nxpvee-ui/armgcc/debug +bsp/projects/nxpvee-ui/armgcc/release # ctags files tags @@ -41,6 +46,3 @@ CMakeCache.txt .ninja_deps build.ninja rules.ninja -nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/tree_version.c -nxpvee-mimxrt595-evk-round-bsp/mcux-sdk -nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/debug diff --git a/.vscode/cmake-kits.json b/.vscode/cmake-kits.json deleted file mode 100644 index ecf8f99..0000000 --- a/.vscode/cmake-kits.json +++ /dev/null @@ -1,11 +0,0 @@ -[ - { - "name": "armgcc", - "keep": true, - "cmakeSettings": { - "LANGUAGE": "C", - "DEBUG_CONSOLE": "UART" - }, - "toolchainFile": "${workspaceFolder}/nxpvee-mimxrt595-evk-round-bsp/mcux-sdk/core/tools/cmake_toolchain_files/armgcc.cmake" - } -] diff --git a/.vscode/cmake-variants.json b/.vscode/cmake-variants.json deleted file mode 100644 index d7a2d1c..0000000 --- a/.vscode/cmake-variants.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "build_type": { - "default": "debug", - "choices": { - "debug": { - "short": "debug", - "buildType": "debug" - }, - "release": { - "short": "release", - "buildType": "release" - } - } - } -} diff --git a/.vscode/launch.json b/.vscode/launch.json index 93786ab..c7a773a 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -16,15 +16,15 @@ ], "program": "", "miDebuggerServerAddress": "", + "miDebuggerPath": "", "variables": { "mcuxStopAtSymbol": "main", - "mcuxSerialNumber": "02280000082d27a600000000000000000000000097969905", "mcuxAttach": "false", - "mcuxRemoteProbeType": "" + "mcuxSerialNumber": "", }, "logging": { "engineLogging": false } } ] -} \ No newline at end of file +} diff --git a/.vscode/mcuxpresso-tools.json b/.vscode/mcuxpresso-tools.json index d6e629f..4227fd1 100644 --- a/.vscode/mcuxpresso-tools.json +++ b/.vscode/mcuxpresso-tools.json @@ -1,26 +1,17 @@ { - "version": "1.1", + "version": "1.4", "toolchainPath": "${env:ARMGCC_DIR}", - "toolchainVersion": "GNU Arm Embedded Toolchain 10.3-2021.10", "linkedProjects": [], "trustZoneType": "none", + "multicoreType": "none", "debug": { "linkserver": { "device": "MIMXRT595S:EVK-MIMXRT595", "core": "primary" }, - "pemicro": {}, "segger": { "device": "MIMXRT595S_M33" } }, - "projectType": "sdk-freestanding", - "sdk": { - "version": "2.12.1", - "path": "${workspaceFolder}/nxpvee-mimxrt595-evk-round-bsp/mcux-sdk", - "boardId": "evkmimxrt595", - "deviceId": "MIMXRT595S", - "coreId": "cm33_MIMXRT595S", - "manifestId": "SDK_2.x_EVK-MIMXRT595_manifest_v3_13" - } + "projectType": "cmake-freestanding" } diff --git a/.vscode/settings.json b/.vscode/settings.json index ead4a0f..b6d7430 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -1,11 +1,7 @@ { "cmake.configureOnOpen": false, "C_Cpp.errorSquiggles": "disabled", - "cmake.preferredGenerators": [ - "Ninja", - "Unix Makefiles", - "MinGW Makefiles" - ], - "cmake.sourceDirectory": "${workspaceFolder}/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc", - "cmake.buildDirectory": "${workspaceFolder}/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/${buildType}" -} \ No newline at end of file + "cmake.sourceDirectory": "${workspaceFolder}/bsp/projects/nxpvee-ui/armgcc", + "cmake.useCMakePresets": "always", + "cmake.buildTask": true +} diff --git a/.vscode/tasks.json b/.vscode/tasks.json new file mode 100644 index 0000000..3ea8f25 --- /dev/null +++ b/.vscode/tasks.json @@ -0,0 +1,36 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "type": "cmake", + "label": "CMake: build", + "command": "build", + "preset": "release", + "targets": [ + "all" + ], + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [], + "detail": "CMake template build task" + }, + { + "type": "cmake", + "label": "CMake: clean", + "command": "clean", + "preset": "release", + "problemMatcher": [], + "detail": "CMake template clean task" + }, + { + "type": "cmake", + "label": "CMake: configure", + "command": "configure", + "preset": "release", + "problemMatcher": [], + "detail": "CMake template configure task" + } + ] +} diff --git a/CHANGELOG.md b/CHANGELOG.md new file mode 100644 index 0000000..8e4cefe --- /dev/null +++ b/CHANGELOG.md @@ -0,0 +1,51 @@ +# Changelog +All notable changes to this project will be documented in this file. + +## [2.0.0] - 2024-10-31 + +### Added + +- Add support for CMakePresets in VSCode +- Add Changelog. +- Add NXP GPIO support. + +### Changed + +- Updated UI pack to v14.0.1 +- Updated VG pack to v1.5.1 +- Updated MCUXpresso SDK to v2.15.100 +- Updated MicroEJ Architecture to flopi4G25#8.1.1 +- Fix MicroEJ SDK 6 builds on Linux. + +## [1.2.0] - 2023-12-05 + +### Added + +- Add VSCode support. +- Add the mock implementation of the MicroEJ Demo-Wearable-VG natives. + +### Removed + +- Remove MCUXPresso IDE support. + +## [1.1.0] - 2023-06-30 + +### Added + +- Add MCUXPresso IDE support. +- Add West for repository management. + +### Changed + +- Update Documentation of the README. + +## [1.0.0] - 2022-11-28 + +### Added + +- Add MicroEJ CORE support. +- Add MicroEJ UI support. +- Add MicroEJ VG support. +- Add Power Management. +- Add Demo applications (AnimatedMascot & SimpleGFX). +- Initial release of the VEE Port. diff --git a/Documentation/pictures/RT595/evk_jtag.jpg b/Documentation/pictures/RT595/evk_jtag.jpg deleted file mode 100644 index 0af444b..0000000 Binary files a/Documentation/pictures/RT595/evk_jtag.jpg and /dev/null differ diff --git a/Documentation/pictures/RT595/evk_running_app.jpg b/Documentation/pictures/RT595/evk_running_app.jpg deleted file mode 100644 index ac8a06e..0000000 Binary files a/Documentation/pictures/RT595/evk_running_app.jpg and /dev/null differ diff --git a/Documentation/pictures/RT595/evk_uart.jpg b/Documentation/pictures/RT595/evk_uart.jpg deleted file mode 100644 index d898264..0000000 Binary files a/Documentation/pictures/RT595/evk_uart.jpg and /dev/null differ diff --git a/Documentation/pictures/RT595/g1120b0mipi.jpg b/Documentation/pictures/RT595/g1120b0mipi.jpg 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You have no distribution rights under this Agreement. -Nevertheless, if you distribute the Licensed Software to the United States -Government, then the Licensed Software is “restricted computer software” -and is subject to FAR 52.227-19. -3.6. You grant to NXP a non-exclusive, non-transferable, irrevocable, -perpetual, worldwide, royalty-free, sublicensable license under your -Intellectual Property Rights to use without restriction and for any purpose any -suggestion, comment or other feedback related to the Licensed Materials -(including, but not limited to, error corrections and bug fixes). -3.7. You may not publish or distribute information, results or data -associated with the use of the Licensed Materials to anyone other than NXP; -however, you must advise NXP of any results obtained including any problems or -suggested improvements thereof. NXP retains the right to use such results and -related information in any manner it deems appropriate. -4. OPEN SOURCE. Open source software included in the Licensed -Software is not licensed under the terms of this Agreement but is instead -licensed under the terms of the applicable open source license(s), such as the -BSD License, Apache License or the GNU Lesser General Public License. Your use -of the open source software is subject to the terms of each applicable license. -You must agree to the terms of each applicable license, or you cannot use the -open source software. -5. INTELLECTUAL PROPERTY RIGHTS. Upon request, you must provide NXP the -source code of any derivative of the Licensed Software. - -Unless prohibited by law, the following paragraph shall apply. Your -modifications to the Licensed Software, and all intellectual property rights -associated with, and title thereto, will be the property of NXP. You agree to -assign all, and hereby do assign all rights, title, and interest to any such -modifications to the Licensed Software to NXP and agree to provide all -assistance reasonably requested by NXP to establish, preserve or enforce such -right. Further, you agree to waive all moral rights relating to your -modifications to the Licensed Software, including, without limitation, all -rights of identification of authorship and all rights of approval, restriction, -or limitation on use or subsequent modification. Notwithstanding the -foregoing, you will have the license rights granted in Section 2 hereto to any -such modifications made by you or your licensees. - -Otherwise, you agree to grant an irrevocable, worldwide, and perpetual license -to NXP to make, have made, use, sell, offer to sell, import, commercialize, -sublicense and reproduce your modifications or derivative works to the Licensed -Software without any payment to Licensee. You agree to provide all assistance -reasonably requested by NXP to establish, preserve or enforce such right. - -6. ESSENTIAL PATENTS. NXP has no obligation to identify or obtain any -license to any Intellectual Property Right of a third-party that may be -necessary for use in connection with technology that is incorporated into the -Authorized System (whether or not as part of the Licensed Materials). -7. TERM AND TERMINATION. This Agreement will remain in effect for the -Evaluation Period, unless terminated earlier in accordance with this Agreement. - -7.1. You may terminate this Agreement immediately upon written notice -to NXP at the address provided below. -7.2. NXP may terminate this Agreement immediately upon written notice -to you. -7.3. Upon termination of this Agreement, all licenses granted under -Section 2 will expire. -7.4. After termination of this Agreement by either party, (a) you will -promptly return to NXP or, at NXP’s discretion, destroy all of the Licensed -Materials and all whole and partial copies of the Licensed Materials within -thirty (30) days after the expiration or termination, (b) you will furnish to -NXP at the address below a written certification that all of the Licensed -Materials including all whole and partial copies, have been (i) destroyed or -returned to NXP, and (ii) erased from all of your storage elements and devices; -and (c) you will not keep any archival copies of the Licensed Materials except -and only to the extent that applicable law notwithstanding this limitation -expressly permits such. -7.5. Notwithstanding the termination of this Agreement for any reason, -the terms of Sections 1 and 3 through 24 will survive. -8. SUPPORT. NXP is not obligated to provide any support, upgrades -or new releases of the Licensed Materials under this Agreement. If you wish, -you may contact NXP and report problems and provide suggestions regarding the -Licensed Materials. NXP has no obligation to respond to such a problem report -or suggestion. NXP may make changes to the Licensed Materials at any time, -without any obligation to notify or provide updated versions of the Licensed -Materials to you. -9. NO WARRANTY. To the maximum extent permitted by law, NXP -expressly disclaims any warranty for the Licensed Materials. The Licensed -Materials are provided “AS IS”, without warranty of any kind, either -express or implied, including without limitation the implied warranties of -merchantability, fitness for a particular purpose, or non-infringement. You -assume the entire risk arising out of the use or performance of the Licensed -Materials, or any systems you design using the Licensed Materials (if any). -10. INDEMNITY. You agree to fully defend and indemnify NXP from all -claims, liabilities, and costs (including reasonable attorney’s fees) related -to (1) your use (including your contractors or sublicensee’s use, if -permitted) of the Licensed Materials or (2) your violation of the terms and -conditions of this Agreement. -11. LIMITATION OF LIABILITY. IN NO EVENT WILL NXP BE LIABLE, WHETHER -IN CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, -CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR -ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, -SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW. -NXP’S TOTAL LIABILITY FOR ALL COSTS, DAMAGES, CLAIMS, OR LOSSES WHATSOEVER -ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT OR PRODUCT(S) SUPPLIED -UNDER THIS AGREEMENT IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP IN -CONNECTION WITH THE LICENSED MATERIALS TO WHICH LOSSES OR DAMAGES ARE CLAIMED. -12. EXPORT COMPLIANCE. Each party will comply with all applicable -export and import control laws and regulations including but not limited to the -US Export Administration Regulation (including restrictions on certain military -end uses and military end users as specified in Section 15 C.F.R. § 744.21 and -prohibited party lists issued by other federal governments), Catch-all -regulations and all national and international embargoes. Each party further -agrees that it will not knowingly transfer, divert, export or re-export, -directly or indirectly, any product, software, including software source code, -or technology restricted by such regulations or by other applicable national -regulations, received from the other party under this Agreement, or any direct -product of such software or technical data to any person, firm, entity, country -or destination to which such transfer, diversion, export or re-export is -restricted or prohibited, without obtaining prior written authorization from -the applicable competent government authorities to the extent required by those -laws. This provision will survive termination or expiration of this Agreement. -13. GOVERNMENT CONTRACT COMPLIANCE. -13.1. You are not permitted to distribute the Licensed Materials under -the terms of this Agreement. Nevertheless, if you sell Authorized Systems -containing the Licensed Materials directly to any government or public entity, -including U.S., state, local, foreign or international governments or public -entities, or indirectly via a prime contractor or subcontractor of such -governments or entities, NXP makes no representations, certifications, or -warranties whatsoever about compliance with government or public entity -acquisition statutes or regulations, including, without limitation, statutes or -regulations that may relate to pricing, quality, origin or content. -13.2. The Licensed Materials has been developed at private expense and is -a “Commercial Item” as defined in 48 C.F.R. Section 2.101, consisting of -“Commercial Computer Software”, and/or “Commercial Computer Software -Documentation,” as such terms are used in 48 C.F.R. Section 12.212 (or 48 -C.F.R. Section 227.7202, as applicable) and may only be licensed to or shared -with U.S. Government end users in object code form as part of, or embedded -within, Authorized Systems. Any agreement pursuant to which you share the -Licensed Materials will include a provision that reiterates the limitations of -this document and requires all sub-agreements to similarly contain such -limitations. -14. CRITICAL APPLICATIONS. In some cases, NXP may promote certain -software for use in the development of, or for incorporation into, products or -services (a) used in applications requiring fail-safe performance or (b) in -which failure could lead to death, personal injury, or severe physical or -environmental damage (these products and services are referred to as "Critical -Applications"). NXP's goal is to educate customers so that they can design -their own end-product solutions to meet applicable functional safety standards -and requirements. Licensee makes the ultimate design decisions regarding its -products and is solely responsible for compliance with all legal, regulatory, -safety, and security related requirements concerning its products, regardless -of any information or support that may be provided by NXP. As such, Licensee -assumes all risk related to use of the Licensed Materials in Critical -Applications and NXP WILL NOT BE LIABLE FOR ANY SUCH USE IN CRITICAL -APPLICATIONS BY LICENSEE. Accordingly, Licensee will indemnify and hold NXP -harmless from any claims, liabilities, damages and associated costs and -expenses (including attorneys' fees) that NXP may incur related to Licensee’s -incorporation of the Licensed Materials in a Critical Application. -15. CHOICE OF LAW; VENUE. This Agreement will be governed by, -construed, and enforced in accordance with the laws of The Netherlands, without -regard to conflicts of laws principles, will apply to all matters relating to -this Agreement or the Licensed Materials, and you agree that any litigation -will be subject to the exclusive jurisdiction of the courts of Amsterdam, The -Netherlands. The United Nations Convention on Contracts for the International -Sale of Goods will not apply to this document. -16. CONFIDENTIAL INFORMATION. Subject to the license grants and -restrictions contained herein, you must treat the Licensed Materials as -confidential information and you agree to retain the Licensed Materials in -confidence perpetually. You may not disclose any part of the Licensed Materials -to anyone other than subcontractors in accordance with Section 2.3, who have a -need to know of the Licensed Materials and who have executed written agreements -obligating them to protect such Licensed Materials to at least the same degree -of confidentiality as in this Agreement. You agree to use the same degree of -care, but no less than a reasonable degree of care, with the Licensed Materials -as you do with your own confidential information. You may disclose Licensed -Materials to the extent required by a court or under operation of law or order -provided that you notify NXP of such requirement prior to disclosure, which you -only disclose the minimum of the required information, and that you allow NXP -the opportunity to object to such court or other legal body requiring such -disclosure. -17. TRADEMARKS. You are not authorized to use any NXP trademarks, -brand names, or logos. -18. ENTIRE AGREEMENT. This Agreement constitutes the entire -agreement between you and NXP regarding the subject matter of this Agreement, -and supersedes all prior communications, negotiations, understandings, -agreements or representations, either written or oral, if any. This Agreement -may only be amended in written form, signed by you and NXP. -19. SEVERABILITY. If any provision of this Agreement is held for any -reason to be invalid or unenforceable, then the remaining provisions of this -Agreement will be unimpaired and, unless a modification or replacement of the -invalid or unenforceable provision is further held to deprive you or NXP of a -material benefit, in which case the Agreement will immediately terminate, the -invalid or unenforceable provision will be replaced with a provision that is -valid and enforceable and that comes closest to the intention underlying the -invalid or unenforceable provision. -20. NO WAIVER. The waiver by NXP of any breach of any provision of -this Agreement will not operate or be construed as a waiver of any other or a -subsequent breach of the same or a different provision. -21. AUDIT. You will keep full, clear and accurate records with -respect to your compliance with the limited license rights granted under this -Agreement for three years following expiration or termination of this -Agreement. NXP will have the right, either itself or through an independent -certified public accountant to examine and audit, at NXP’s expense, not more -than once a year, and during normal business hours, all such records that may -bear upon your compliance with the limited license rights granted above. You -must make prompt adjustment to compensate for any errors and/or omissions -disclosed by such examination or audit. -22. NOTICES. All notices and communications under this -Agreement will be made in writing, and will be effective when received at the -following addresses: - -NXP: NXP B.V. - High Tech Campus 60 - 5656 AG Eindhoven - The Netherlands - ATTN: Legal Department - -You: The address provided at registration will be used. - -23. RELATIONSHIP OF THE PARTIES. The parties are independent -contractors. Nothing in this Agreement will be construed to create any -partnership, joint venture, or similar relationship. Neither party is -authorized to bind the other to any obligations with third parties. -24. SUCCESSION AND ASSIGNMENT. This Agreement will be binding upon -and inure to the benefit of the parties and their permitted successors and -assigns. You may not assign this Agreement, or any part of this Agreement, -without the prior written approval of NXP, which approval will not be -unreasonably withheld or delayed. NXP may assign this Agreement, or any part of -this Agreement, in its sole discretion. - -APPENDIX A -Other License Grants and Restrictions: - -The Licensed Software may include some or all of the following software, which -is either 1) Third Party Software or 2) NXP proprietary software subject to -different terms than those in the Agreement. If the Software Content Register -that accompanies the Licensed Software identifies any of the following Third -Party Software or specific components of the NXP proprietary software, the -following terms apply to the extent they deviate from the terms in the -Agreement: - -CEVA D.S.P. Ltd. and CEVA Technologies Inc. (“CEVA”): The CEVA-SPF2 linear -algebra, CEVA-SPF2 Neural Network Libraries, CEVA-SPF2 Core Libraries, -CEVA-SPF2 OpenAMP and CEVA-SPF2 STL licensed modules are owned by CEVA and such -materials may only be used in connection with an NXP product containing the -S250 or S125 integrated circuits, whether or not the CEVA-SPF2 Core is -physically implemented and/or enabled on such NXP product. diff --git a/LICENSE.txt b/LICENSE.txt new file mode 100644 index 0000000..ac7337f --- /dev/null +++ b/LICENSE.txt @@ -0,0 +1,775 @@ +LA_OPT_NXP_Software_License v57 July 2024 +IMPORTANT. Read the following NXP Software License Agreement ("Agreement") +completely. By selecting the "I Accept" button at the end of this page, or by +downloading, installing, or using the Licensed Software, you indicate that you +accept the terms of the Agreement, and you acknowledge that you have the +authority, for yourself or on behalf of your company, to bind your company to +these terms. You may then download or install the file. In the event of a +conflict between the terms of this Agreement and any license terms and +conditions for NXP’s proprietary software embedded anywhere in the Licensed +Software file, the terms of this Agreement shall control. If a separate +license agreement for the Licensed Software has been signed by you and NXP, +then that agreement shall govern your use of the Licensed Software and shall +supersede this Agreement. + +NXP SOFTWARE LICENSE AGREEMENT +This is a legal agreement between your employer, of which you are an authorized +representative, or, if you have no employer, you as an individual ("you" or +"Licensee"), and and NXP USA, Inc., if Licensee is located within the United +States or NXP Semiconductors Netherlands B.V., if Licensee if located outside +of the United States (“NXP”). It concerns your rights to use the software +provided to you in binary or source code form and any accompanying written +materials (the "Licensed Software"). The Licensed Software may include any +updates or error corrections or documentation relating to the Licensed Software +provided to you by NXP under this Agreement. In consideration for NXP allowing +you to access the Licensed Software, you are agreeing to be bound by the terms +of this Agreement. If you do not agree to all of the terms of this Agreement, +do not download or install the Licensed Software. If you change your mind +later, stop using the Licensed Software and delete all copies of the Licensed +Software in your possession or control. Any copies of the Licensed Software +that you have already distributed, where permitted, and do not destroy will +continue to be governed by this Agreement. Your prior use will also continue to +be governed by this Agreement. +1. DEFINITIONS +1.1. "Affiliate" means, with respect to a party, any corporation or +other legal entity that now or hereafter Controls, is Controlled by or is under +common Control with such party; where "Control" means the direct or indirect +ownership of greater than fifty percent (50%) of the shares or similar +interests entitled to vote for the election of directors or other persons +performing similar functions. An entity is considered an Affiliate only so long +as such Control exists. +1.2 "Authorized System" means either (i) Licensee’s hardware product +which incorporates an NXP Product or (ii) Licensee’s software program which +is used exclusively in connection with an NXP Product and with which the +Licensed Software will be integrated. +1.3. "Derivative Work" means a work based upon one or more pre-existing +works. A work consisting of editorial revisions, annotations, elaborations, or +other modifications which, as a whole, represent an original work of +authorship, is a Derivative Work. +1.4 "Intellectual Property Rights" means any and all rights under statute, +common law or equity in and under copyrights, trade secrets, and patents +(including utility models), and analogous rights throughout the world, +including any applications for and the right to apply for, any of the foregoing. +1.5 "NXP Product" means a hardware product (e.g. a microprocessor, +microcontroller, sensor or digital signal processor) and/or services (e.g. +cloud platform services) supplied directly or indirectly from NXP or an NXP +Affiliate, unless there is a product specified in the Software Content +Register, in which case this definition is limited to such product. +1.6 "Software Content Register" means the documentation which may +accompany the Licensed Software which identifies the contents of the Licensed +Software, including but not limited to identification of any Third Party +Software, if any, and may also contain other related information as whether the +license in 2.3 is applicable. +1.7 "Third Party Software" means, any software included in the Licensed +Software that is not NXP proprietary software, and is not open source software, +and to which different license terms may apply. +2. LICENSE GRANT. +2.1. If you are not expressly granted the distribution license in +Section 2.3 in the Software Content Register, then you are only granted the +rights in Section 2.2 and not in 2.3. If you are expressly granted the +distribution license in Section 2.3 in the Software Content Register, then you +are granted the rights in both Section 2.2 and 2.3. +2.2. Standard License. Subject to the terms and conditions of this +Agreement, NXP grants you a worldwide, personal, non-transferable, +non-exclusive, non-sublicensable license, solely for the development of an +Authorized System: +(a) to use and reproduce the Licensed Software (and its Derivative Works +prepared under the license in Section 2.2(b)) solely in combination with a NXP +Product; and +(b) for Licensed Software provided to you in source code form (human +readable), to prepare Derivative Works of the Licensed Software solely for use +in combination with a NXP Product. +You may not distribute or sublicense the Licensed Software to others under the +license granted in this Section 2.2. +You may demonstrate the Licensed Software to your direct customers as part of +an Authorized System so long as such demonstration is directly controlled by +you and without prior approval by NXP; however, to all other third parties only +if NXP has provided its advance, written approval (e.g. email approval) of your +demonstrating the Licensed Software to specified third parties or at specified +event(s). You may not leave the Licensed Software with a direct customer or +any other third party at any time. +2.3. Additional Distribution License. If expressly authorized in the +Software Content Register, subject to the terms and conditions of this +Agreement, NXP grants you a worldwide, personal, non-transferable, +non-exclusive, non-sublicensable license solely in connection with your +manufacturing and distribution of an Authorized System: +(a) to manufacture (or have manufactured), distribute, and market the +Licensed Software (and its Derivative Works prepared under the license in +2.2(b)) in object code (machine readable format) only as part of, or embedded +within, Authorized Systems and not on a standalone basis solely for use in +combination with a NXP Product. Notwithstanding the foregoing, those files +marked as .h files ("Header files") may be distributed in source or object code +form, but only as part of, or embedded within Authorized Systems; and +(b) to copy and distribute as needed, solely in connection with an +Authorized System and for use in combination with a NXP Product, +non-confidential NXP information provided as part of the Licensed Software for +the purpose of maintaining and supporting Authorized Systems with which the +Licensed Software is integrated. +2.4 Separate license grants to Third Party Software, or other terms +applicable to the Licensed Software if different from those granted in this +Section 2, are contained in Appendix A. The Licensed Software may be +accompanied by a Software Content Register which will identify that portion of +the Licensed Software, if any, that is subject to the different terms in +Appendix A. +2.5. You may use subcontractors to exercise your rights under Section +2.2 and Section 2.3, if any, so long as you have an agreement in place with the +subcontractor containing confidentiality restrictions no less stringent than +those contained in this Agreement. You will remain liable for your +subcontractors’ adherence to the terms of this Agreement and for any and all +acts and omissions of such subcontractors with respect to this Agreement and +the Licensed Software. +3. LICENSE LIMITATIONS AND RESTRICTIONS. +3.1. The licenses granted above in Section 2 only extend to NXP +Intellectual Property Rights that would be infringed by the unmodified Licensed +Software prior to your preparation of any Derivative Work. +3.2. The Licensed Software is licensed to you, not sold. Title to +Licensed Software delivered hereunder remains vested in NXP or NXP’s licensor +and cannot be assigned or transferred. You are expressly forbidden from selling +or otherwise distributing the Licensed Software, or any portion thereof, except +as expressly permitted herein. This Agreement does not grant to you any implied +rights under any NXP or third party Intellectual Property Rights. +3.3. You may not translate, reverse engineer, decompile, or disassemble +the Licensed Software except to the extent applicable law specifically +prohibits such restriction. You must prohibit your subcontractors or customers +(if distribution is permitted) from translating, reverse engineering, +decompiling, or disassembling the Licensed Software except to the extent +applicable law specifically prohibits such restriction. +3.4. You must reproduce any and all of NXP’s (or its third-party +licensor’s) copyright notices and other proprietary legends on copies of +Licensed Software. +3.5. If you distribute the Licensed Software to the United States +Government, then the Licensed Software is "restricted computer software" and is +subject to FAR 52.227-19. +3.6. You grant to NXP a non-exclusive, non-transferable, irrevocable, +perpetual, worldwide, royalty-free, sub-licensable license under your +Intellectual Property Rights to use without restriction and for any purpose any +suggestion, comment or other feedback related to the Licensed Software +(including, but not limited to, error corrections and bug fixes). +3.7. You will not take or fail to take any action that could subject +the Licensed Software to an Excluded License. An Excluded License means any +license that requires, as a condition of use, modification or distribution of +software subject to the Excluded License, that such software or other software +combined and/or distributed with the software be (i) disclosed or distributed +in source code form; (ii) licensed for the purpose of making Derivative Works; +or (iii) redistributable at no charge. +3.8. You may not publish or distribute reports associated with the use +of the Licensed Software to anyone other than NXP. You may advise NXP of any +results obtained from your use of the Licensed Software, including any problems +or suggested improvements thereof, and NXP retains the right to use such +results and related information in any manner it deems appropriate. +4. OPEN SOURCE. Open source software included in the Licensed +Software is not licensed under the terms of this Agreement but is instead +licensed under the terms of the applicable open source license(s), such as the +BSD License, Apache License or the GNU Lesser General Public License. Your use +of the open source software is subject to the terms of each applicable license. +You must agree to the terms of each applicable license, or you cannot use the +open source software. +5. INTELLECTUAL PROPERTY RIGHTS. +Upon request, you must provide NXP the source code of any derivative of the +Licensed Software. +Unless prohibited by law, the following paragraph shall apply. Your +modifications to the Licensed Software, and all intellectual property rights +associated with, and title thereto, will be the property of NXP. You agree to +assign all, and hereby do assign all rights, title, and interest to any such +modifications to the Licensed Software to NXP and agree to provide all +assistance reasonably requested by NXP to establish, preserve or enforce such +right. Further, you agree to waive all moral rights relating to your +modifications to the Licensed Software, including, without limitation, all +rights of identification of authorship and all rights of approval, restriction, +or limitation on use or subsequent modification. Notwithstanding the +foregoing, you will have the license rights granted in Section 2 hereto to any +such modifications made by you or your licensees. +Otherwise, you agree to grant an irrevocable, worldwide, and perpetual license +to NXP to make, have made, use, sell, offer to sell, import, commercialize, +sublicense and reproduce your modifications or derivative works to the Licensed +Software without any payment to Licensee. You agree to provide all assistance +reasonably requested by NXP to establish, preserve or enforce such right. +6. ESSENTIAL PATENTS. NXP has no obligation to identify or obtain any +license to any Intellectual Property Right of a third-party that may be +necessary for use in connection with technology that is incorporated into the +Authorized System (whether or not as part of the Licensed Software). +7. TERM AND TERMINATION. This Agreement will remain in effect unless +terminated as provided in this Section. +7.1. You may terminate this Agreement immediately upon written notice +to NXP at the address provided below. +7.2. Either party may terminate this Agreement if the other party is in +default of any of the terms and conditions of this Agreement, and termination +is effective if the defaulting party fails to correct such default within 30 +days after written notice thereof by the non-defaulting party to the defaulting +party at the address below. +7.3. Notwithstanding the foregoing, NXP may terminate this Agreement +immediately upon written notice if you: breach any of your confidentiality +obligations or the license restrictions under this Agreement; become bankrupt, +insolvent, or file a petition for bankruptcy or insolvency; make an assignment +for the benefit of its creditors; enter proceedings for winding up or +dissolution; are dissolved; or are nationalized or become subject to the +expropriation of all or substantially all of your business or assets. +7.4. Upon termination of this Agreement, all licenses granted under +Section 2 will expire. +7.5. After termination of this Agreement by either party you will +destroy all parts of Licensed Software and its Derivative Works (if any) and +will provide to NXP a statement certifying the same. +7.6. Notwithstanding the termination of this Agreement for any reason, +the terms of Sections 1 and 3 through 24 will survive. +8. SUPPORT. NXP is not obligated to provide any support, upgrades or +new releases of the Licensed Software under this Agreement. If you wish, you +may contact NXP and report problems and provide suggestions regarding the +Licensed Software. NXP has no obligation to respond to such a problem report or +suggestion. NXP may make changes to the Licensed Software at any time, without +any obligation to notify or provide updated versions of the Licensed Software +to you. +9. NO WARRANTY. To the maximum extent permitted by law, NXP expressly +disclaims any warranty for the Licensed Software. The Licensed Software is +provided "AS IS", without warranty of any kind, either express or implied, +including without limitation the implied warranties of merchantability, fitness +for a particular purpose, or non-infringement. You assume the entire risk +arising out of the use or performance of the licensed software, or any systems +you design using the licensed software (if any). +10. INDEMNITY. You agree to fully defend and indemnify NXP from all +claims, liabilities, and costs (including reasonable attorney’s fees) related +to (1) your use (including your subcontractor’s or distributee’s use, if +permitted) of the Licensed Software or (2) your violation of the terms and +conditions of this Agreement. +11. LIMITATION OF LIABILITY. EXCLUDING LIABILITY FOR A BREACH OF +SECTION 2 (LICENSE GRANTS), SECTION 3 (LICENSE LIMITATIONS AND RESTRICTIONS), +SECTION 16 (CONFIDENTIAL INFORMATION), OR CLAIMS UNDER SECTION 10 (INDEMNITY), +IN NO EVENT WILL EITHER PARTY BE LIABLE, WHETHER IN CONTRACT, TORT, OR +OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE +DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF +TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES, TO +THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW. NXP’S TOTAL LIABILITY FOR ALL +COSTS, DAMAGES, CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION +WITH THIS AGREEMENT OR PRODUCT(S) SUPPLIED UNDER THIS AGREEMENT IS LIMITED TO +THE AGGREGATE AMOUNT PAID BY YOU TO NXP IN CONNECTION WITH THE LICENSED +SOFTWARE PROVIDED UNDER THIS AGREEMENT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. +12. EXPORT COMPLIANCE. Each party shall comply with all applicable +export and import control laws and regulations including but not limited to the +US Export Administration Regulation (including restrictions on certain military +end uses and military end users as specified in Section 15 C.F.R. § 744.21 and +prohibited party lists issued by other federal governments), Catch-all +regulations and all national and international embargoes. Each party further +agrees that it will not knowingly transfer, divert, export or re-export, +directly or indirectly, any product, software, including software source code, +or technology restricted by such regulations or by other applicable national +regulations, received from the other party under this Agreement, or any direct +product of such software or technical data to any person, firm, entity, country +or destination to which such transfer, diversion, export or re-export is +restricted or prohibited, without obtaining prior written authorization from +the applicable competent government authorities to the extent required by those +laws. +13. GOVERNMENT CONTRACT COMPLIANCE +13.1. If you sell Authorized Systems directly to any government or public +entity, including U.S., state, local, foreign or international governments or +public entities, or indirectly via a prime contractor or subcontractor of such +governments or entities, NXP makes no representations, certifications, or +warranties whatsoever about compliance with government or public entity +acquisition statutes or regulations, including, without limitation, statutes or +regulations that may relate to pricing, quality, origin or content. +13.2. The Licensed Software has been developed at private expense and is a +"Commercial Item" as defined in 48 C.F.R. Section 2.101, consisting of +"Commercial Computer Software", and/or "Commercial Computer Software +Documentation," as such terms are used in 48 C.F.R. Section 12.212 (or 48 +C.F.R. Section 227.7202, as applicable) and may only be licensed to or shared +with U.S. Government end users in object code form as part of, or embedded +within, Authorized Systems. Any agreement pursuant to which you share the +Licensed Software will include a provision that reiterates the limitations of +this document and requires all sub-agreements to similarly contain such +limitations. +14. CRITICAL APPLICATIONS. In some cases, NXP may promote certain +software for use in the development of, or for incorporation into, products or +services (a) used in applications requiring fail-safe performance or (b) in +which failure could lead to death, personal injury, or severe physical or +environmental damage (these products and services are referred to as "Critical +Applications"). NXP’s goal is to educate customers so that they can design +their own end-product solutions to meet applicable functional safety standards +and requirements. Licensee makes the ultimate design decisions regarding its +products and is solely responsible for compliance with all legal, regulatory, +safety, and security related requirements concerning its products, regardless +of any information or support that may be provided by NXP. As such, Licensee +assumes all risk related to use of the Licensed Software in Critical +Applications and NXP SHALL NOT BE LIABLE FOR ANY SUCH USE IN CRITICAL +APPLICATIONS BY LICENSEE. Accordingly, Licensee will indemnify and hold NXP +harmless from any claims, liabilities, damages and associated costs and +expenses (including attorneys’ fees) that NXP may incur related to +Licensee’s incorporation of the Licensed Software in a Critical Application. +15. CHOICE OF LAW; VENUE. When Software is licensed by NXP USA, Inc., +Licensee agrees that the laws of the State of Texas, USA, without regard to +conflicts of laws principles, will apply to all matters relating to this +Agreement or the Software, and Licensee agrees that any litigation will be +subject to the exclusive jurisdiction of the state or federal courts in Austin, +Texas, USA.. When Software is licensed by NXP Semiconductors Netherlands B.V., +Licensee agrees that the laws of The Netherlands, without regard to conflicts +of laws principles, will apply to all matters relating to this Agreement or the +Software, and Licensee agrees that any litigation will be subject to the +exclusive jurisdiction of the courts in Amsterdam, The Netherlands. +Notwithstanding the foregoing, NXP will always be permitted to bring any action +or proceedings against Licensee in any other court of competent jurisdiction. +The United Nations Convention on Contracts for the International Sale of Goods +will not apply to this document. +16. CONFIDENTIAL INFORMATION. Subject to the license grants and +restrictions contained herein, you must treat the Licensed Software as +confidential information and you agree to retain the Licensed Software in +confidence perpetually. You may not disclose any part of the Licensed Software +to anyone other than distributees in accordance with Section 2.3 and employees, +or subcontractors in accordance with Section 2.5, who have a need to know of +the Licensed Software and who have executed written agreements obligating them +to protect such Licensed Software to at least the same degree of +confidentiality as in this Agreement. You agree to use the same degree of care, +but no less than a reasonable degree of care, with the Licensed Software as you +do with your own confidential information. You may disclose Licensed Software +to the extent required by a court or under operation of law or order provided +that you notify NXP of such requirement prior to disclosure, which you only +disclose the minimum of the required information, and that you allow NXP the +opportunity to object to such court or other legal body requiring such +disclosure. +17. TRADEMARKS. You are not authorized to use any NXP trademarks, brand +names, or logos. +18. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement +between you and NXP regarding the subject matter of this Agreement, and +supersedes all prior communications, negotiations, understandings, agreements +or representations, either written or oral, if any. This Agreement may only be +amended in written form, signed by you and NXP. +19. SEVERABILITY. If any provision of this Agreement is held for any +reason to be invalid or unenforceable, then the remaining provisions of this +Agreement will be unimpaired and, unless a modification or replacement of the +invalid or unenforceable provision is further held to deprive you or NXP of a +material benefit, in which case the Agreement will immediately terminate, the +invalid or unenforceable provision will be replaced with a provision that is +valid and enforceable and that comes closest to the intention underlying the +invalid or unenforceable provision. +20. NO WAIVER. The waiver by NXP of any breach of any provision of this +Agreement will not operate or be construed as a waiver of any other or a +subsequent breach of the same or a different provision. +21. AUDIT. You will keep full, clear and accurate records with respect +to your compliance with the limited license rights granted under this Agreement +for three years following expiration or termination of this Agreement. NXP will +have the right, either itself or through an independent certified public +accountant to examine and audit, at NXP’s expense, not more than once a year, +and during normal business hours, all such records that may bear upon your +compliance with the limited license rights granted above. You must make prompt +adjustment to compensate for any errors and/or omissions disclosed by such +examination or audit. +22. NOTICES. All notices and communications under this +Agreement will be made in writing, and will be effective when received at the +following addresses: +NXP: +NXP B.V. +High Tech Campus 60 +5656 AG Eindhoven +The Netherlands +ATTN: Legal Department + +You: +The address provided at registration will be used. + +23. RELATIONSHIP OF THE PARTIES. The parties are independent +contractors. Nothing in this Agreement will be construed to create any +partnership, joint venture, or similar relationship. Neither party is +authorized to bind the other to any obligations with third parties. +24. SUCCESSION AND ASSIGNMENT. This Agreement will be binding upon and +inure to the benefit of the parties and their permitted successors and assigns. + You may not assign this Agreement, or any part of this Agreement, without the +prior written approval of NXP, which approval will not be unreasonably withheld +or delayed. NXP may assign this Agreement, or any part of this Agreement, in +its sole discretion. +25. PRIVACY. By agreeing to this Agreement and/or utilizing the Licensed +Software, Licensee consents to use of certain personal information, including +but not limited to name, email address, and location, for the purpose of +NXP’s internal analysis regarding future software offerings. NXP’s +complete Privacy Statement can be found at: +https://www.nxp.com/company/our-company/about-nxp/privacy-statement:PRIVACYPRACT +ICES. + +APPENDIX A +Other License Grants and Restrictions: + +The Licensed Software may include some or all of the following software, which +is either 1) Third Party Software or 2) NXP proprietary software subject to +different terms than those in the Agreement. If the Software Content Register +that accompanies the Licensed Software identifies any of the following Third +Party Software or specific components of the NXP proprietary software, the +following terms apply to the extent they deviate from the terms in the +Agreement: + +AGGIOS, Inc.: EnergyLab LITE and Seed software are distributed by NXP under +license from AGGIOS, Inc. Your use of AGGIOS software, as the Licensee, is +subject to the following: (i) use of AGGIOS software is limited to object code +and Authorized System only; (ii) Licensee may not sublicense the AGGIOS +software to any third party; (iii) Licensee is only granted an evaluation +license for the Seed software, defined as license to use the Seed software +internally for own evaluation purposes, limited to three (3) months. Further +rights including but not limited to production deployment must be obtained +directly from AGGIOS, Inc. + +Airbiquity Inc.: The Airbiquity software may only be used in object code and +Licensee may not sublicense the Airbiquity software to any third party. +Licensee’s license to use the Airbiquity software expires on June 30, 2024. + +Amazon: Use of the Amazon software constitutes your acceptance of the terms of +the Amazon Program Materials License Agreement (including the AVS Component +Schedule, if applicable), located at +https://developer.amazon.com/support/legal/pml. All Amazon software is hereby +designated "Amazon confidential". With the exception of the binary library of +the Amazon Wake Word Engine for "Alexa", all Amazon software is also hereby +designated as "Restricted Program Materials". Amazon is a third-party +beneficiary to this Agreement with respect to the Amazon software. + +Amazon Web Services, Inc.: AWS is an intended third-party beneficiary to this +Agreement with respect to the Greengrass software. If you have an account with +AWS that is not in good standing, you may not download, install, use or +distribute the Greengrass software. You will comply with all instructions and +requirements in any integration documents, guidelines, or other documentation +AWS provides. The license to the Greengrass software will immediately terminate +without notice if you (a) fail to comply with this Agreement or any other +agreement with AWS, (b) fail to make timely payment for any AWS service, (c) +fail to implement AWS updates, or (d) bring any action for intellectual +property infringement against AWS or any AWS customer utilizing AWS services. +Any dispute or claim relating to your use of the Greengrass software will be +resolved by binding arbitration, rather than in court, except that you may +assert claims in small claims court if your claims qualify. + +Amazon: AWS Fleetwise software must be used consistent with the terms found +here: https://github.com/aws/aws-iot-fleetwise-edge/blob/main/LICENSE. + +Amphion Semiconductor Ltd.: Distribution of Amphion software must be a part of, +or embedded within, Authorized Systems that include an Amphion Video Decoder. + +Apple MFi Software Development Kit: Use of Apple MFi Software and associated +documentation is restricted to current Apple MFi licensees in accordance with +the terms of their own valid and in-effect license from Apple. + +Aquantia Corp.: You may use Aquantia's API binaries solely to flash the API +software to an NXP Product which mates with an Aquantia device. + +Argus Cyber Security: The Argus software may only be used in object code and +only for evaluation and demonstration purposes. + +Arm Toolkit: This tool is owned by Arm Limited. You may not reverse engineer, +decompile or dissemble any ARM Toolkit. You agree to abide by any third-party +IP requirements, including the relevant license terms where applicable, where +such third-party IP is identified in the documentation provided with the ARM +Toolkit. You may not copy the Arm Toolkit except solely for archival and backup +purposes provided all notices are preserved. Arm disclaims any and all +liability related to your use of the ARM Toolkit. + +Atheros: Use of Atheros software is limited to evaluation and demonstration +only. Permitted distributions must be similarly limited. Further rights must +be obtained directly from Atheros. + +ATI (AMD): Distribution of ATI software must be a part of, or embedded within, +Authorized Systems that include a ATI graphics processor core. + +Au-Zone Technologies: eIQ Portal, Model Tool, DeepViewRT and ModelRunner are +distributed by NXP under license from Au-Zone Technologies. Your use of the +Licensed Software, examples and related documentation is subject to the +following: +(1) Use of Software is limited to Authorized System only +(2) In no event may Licensee Sublicense the Software +(3) AU-ZONE TECHNOLOGIES SHALL NOT BE LIABLE FOR USE OF LICENSED +SOFTWARE IN CRITICAL APPLICATIONS BY LICENSEE + +Broadcom Corporation: Your use of Broadcom Corporation software is restricted +to Authorized Systems that incorporate a compatible integrated circuit device +manufactured or sold by Broadcom. + +Cadence Design Systems: Use of Cadence audio codec software is limited to +distribution only of one copy per single NXP Product. The license granted +herein to the Cadence Design Systems HiFi aacPlus Audio Decoder software does +not include a license to the AAC family of technologies which you or your +customer may need to obtain. Configuration tool outputs may only be distributed +by licensees of the relevant Cadence SDK and distribution is limited to +distribution of one copy embedded in a single NXP Product. Your use of Cadence +NatureDSP Libraries whether in source code or in binary is restricted to NXP +SoC based systems or emulation enablement based on NXP SoC. + +CEVA D.S.P. Ltd. And CEVA Technologies Inc. ("CEVA"): The CEVA-SPF2 linear +algebra, CEVA-SPF2 Neural Network Libraries, CEVA-SPF2 Core Libraries, +CEVA-SPF2 OpenAMP and CEVA-SPF2 STL licensed modules are owned by CEVA and such +materials may only be used in connection with an NXP product containing the +S250 or S125 integrated circuits, whether or not the CEVA-SPF2 Core is +physically implemented and/or enabled on such NXP product + +Cirque Corporation: Use of Cirque Corporation technology is limited to +evaluation, demonstration, or certification testing only. Permitted +distributions must be similarly limited. Further rights, including but not +limited to ANY commercial distribution rights, must be obtained directly from +Cirque Corporation. + +Coding Technologies (Dolby Labs): Use of CTS software is limited to evaluation +and demonstration only. Permitted distributions must be similarly limited. +Further rights must be obtained from Dolby Laboratories. + +Coremark: Use of the Coremark benchmarking software is subject to the +following terms and conditions: +https://github.com/eembc/coremark/blob/main/LICENSE.md + +CSR: Use of Cambridge Silicon Radio, Inc. ("CSR") software is limited to +evaluation and demonstration only. Permitted distributions must be similarly +limited. Further rights must be obtained directly from CSR. + +Crank: Use of Crank Software Inc. software is limited to evaluation and +demonstration only. Permitted distributions must be similarly limited. Further +rights must be obtained directly from Crank Software Inc. + +Cypress Semiconductor Corporation: WWD RTOS source code may only be used in +accordance with the Cypress IOT Community License Agreement obtained directly +from Cypress Semiconductor Corporation. + +Elektrobit Automotive GmbH ("EB"): EB software must be used consistent with the +EB License Terms and Conditions, Version 1.4 (Dec 2019) found here: +https://www.elektrobit.com/legal-notice/ . Licensee is only granted an +evaluation license for the EB software, defined as license to use the EB +software internally for own evaluation purposes, limited to three (3) months. +Production deployment of the EB software using this license is prohibited. See +additionally Section 2.1.1 EB EULA. + +Embedded Systems Academy GmbH (EmSA): Any use of Micro CANopen Plus is subject +to the acceptance of the license conditions described in the LICENSE.INFO file +distributed with all example projects and in the documentation and the +additional clause described below. +Clause 1: Micro CANopen Plus may not be used for any competitive or comparative +purpose, including the publication of any form of run time or compile time +metric, without the express permission of EmSA. + +Fenopix Technologies Private Limited: Under no circumstances may the CanvasJS +software product be used in any way that would compete with any product from +Fenopix. License to the CanvasJS software will terminate immediately without +notice if Licensee fail to comply with any provision of this Agreement. + +Fraunhofer IIS: Fraunhofer MPEG Audio Decoder (Fraunhofer copyright) - If you +are provided MPEG-H decoding functionality, you understand that NXP will +provide Fraunhofer your name and contact information. + +Future Technology Devices International Ltd.: Future Technology Devices +International software must be used consistent with the terms found here: +http://www.ftdichip.com/Drivers/FTDriverLicenceTerms.htm + +Global Locate (Broadcom Corporation): Use of Global Locate, Inc. software is +limited to evaluation and demonstration only. Permitted distributions must be +similarly limited. Further rights must be obtained from Global Locate. + +IAR Systems: Use of IAR flashloader or any IAR source code is subject to the +terms of the IAR Source License located within the IAR zip package. The IAR +Source License applies to linker command files, example projects unless another +license is explicitly stated, the cstartup code, low_level_init.c, and some +other low-level runtime library files. + +LC3plus: the LC3plus Low Complexity Communication Codec Plus (LC3plus) per ETSI +TS 103 634 V1.3.1, is subject to ETSI Intellectual Property Rights Policy, See +https://portal.etsi.org/directives/45_directives_jun_2022.pdf. For application +in an End Product, Fraunhofer communication applies, see +https://www.iis.fraunhofer.de/en/ff/amm/communication/lc3.html + +Lumissil: Use of the Lumissil software constitutes your acceptance of the terms +of the Lumissil Software License Agreement. A link to the agreement is +incorporated as follows: +https://www.lumissil.com/assets/pdf/support/2023%20Lumissil%20IS3xCG5317%20Softw +are%20License%20Agreement%20NXP.pdf . The Run-Time Software and Boot ROM Code +are without warranty of any kind from NXP or Lumissil, either express or +implied, including without limitation the implied warranties of +merchantability, fitness for a particular purpose, or non-infringement. You +assume the entire risk arising out of the use or performance of the Lumissil +software, or any systems you design using the such, if any. For the use of +Lumissil software, Lumissil is as a third-party beneficiary of the this +Agreement with authority to enforce its rights in the Run-Time Software and +Boot ROM Code. + +Microsoft: Except for Microsoft PlayReady software, if the Licensed Software +includes software owned by Microsoft Corporation ("Microsoft"), it is subject +to the terms of your license with Microsoft (the "Microsoft Underlying Licensed +Software") and as such, NXP grants no license to you, beyond evaluation and +demonstration in connection with NXP processors, in the Microsoft Underlying +Licensed Software. You must separately obtain rights beyond evaluation and +demonstration in connection with the Microsoft Underlying Licensed Software +from Microsoft. Microsoft does not provide support services for the components +provided to you through this Agreement. If you have any questions or require +technical assistance, please contact NXP. Microsoft Corporation is a third +party beneficiary to this Agreement with the right to enforce the terms of this +Agreement. TO THE MAXIMUM EXTENT PERMITTED BY LAW, MICROSOFT AND ITS +AFFILIATES DISCLAIM ANY WARRANTIES FOR THE MICROSOFT UNDERLYING LICENSED +SOFTWARE. TO THE MAXIMUM EXTENT PERMITTED BY LAW, NEITHER MICROSOFT NOR ITS +AFFILIATES WILL BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY +DIRECT, INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, +INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, +INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES, ARISING +FROM THE FROM THE USE OF THE MICROSOFT UNDERLYING LICENSED SOFTWARE. With +respect to the Microsoft PlayReady software, you will have the license rights +granted in Section 2, provided that you may not use the Microsoft PlayReady +software unless you have entered into a Microsoft PlayReady Master Agreement +and license directly with Microsoft. + +MindTree: Notwithstanding the terms contained in Section 2.3 (a), if the +Licensed Software includes proprietary software of MindTree in source code +format, Licensee may make modifications and create derivative works only to the +extent necessary for debugging of the Licensed Software. + +MM SOLUTIONS AD: Use of MM SOLUTIONS AEC (Auto Exposure Control) and AWB (Auto +White Balance) software is limited to demonstration, testing, and evaluation +only. In no event may Licensee distribute or sublicense the MM SOLUTIONS +software. Further rights must be obtained directly from MM SOLUTIONS. + +MPEG LA: Use of MPEG LA audio or video codec technology is limited to +evaluation and demonstration only. Permitted distributions must be similarly +limited. Further rights must be obtained directly from MPEG LA. + +MQX RTOS Code: MQX RTOS source code may not be re-distributed by any NXP +Licensee under any circumstance, even by a signed written amendment to this +Agreement. + +NXP Voice Software: VoiceSpot, VoiceSeeker (including AEC), VIT Speech to +Intent, and Conversa may be used for evaluation or demonstration purposes only. +Any commercial distribution rights are subject to a separate royalty agreement +obtained from NXP. + +NXP Wireless Charging Library: License to the Software is limited to use in +inductive coupling or wireless charging applications + +ON Semiconductor: ON Semiconductor AP1302 Image Signal Processor Initialization +Binaries must be used consistent with the terms found here: +https://github.com/ONSemiconductor/ap1302_binaries/blob/main/AP1302%20Software%2 +0License%20Agreement.pdf + +Opus: Use of Opus software must be consistent with the terms of the Opus +license which can be found at: http://www.opus-codec.org/license/ + +Oracle JRE (Java): The Oracle JRE must be used consistent with terms found +here: http://java.com/license + +P&E Micro: P&E Software must be used consistent with the terms found here: +http://www.pemicro.com/licenses/gdbserver/license_gdb.pdf + +Pro Design Electronic: Licensee may not modify, create derivative works based +on, or copy the Pro Design software, documentation, hardware execution key or +the accompanying materials. Licensee shall not use Pro Design's or any of its +licensors names, logos or trademarks to market the Authorized System. Only NXP +customers and distributors are permitted to further redistribute the Pro Design +software and only as part of an Authorized System which contains the Pro Design +software. + +Qualcomm Atheros, Inc.: Notwithstanding anything in this Agreement, Qualcomm +Atheros, Inc. Wi-Fi software must be used strictly in accordance with the +Qualcomm Atheros, Inc. Technology License Agreement that accompanies such +software. Any other use is expressly prohibited. + +Real Networks - GStreamer Optimized Real Format Client Code implementation or +OpenMax Optimized Real Format Client Code: Use of the GStreamer Optimized Real +Format Client Code, or OpenMax Optimized Real Format Client code is restricted +to applications in the automotive market. Licensee must be a final +manufacturer in good standing with a current license with Real Networks for the +commercial use and distribution of products containing the GStreamer Optimized +Real Format Client Code implementation or OpenMax Optimized Real Format Client +Code + +Real-Time Innovations, Inc.: Not withstanding anything in this Agreement, +Real-Time Innovations, Inc. software must be used strictly in accordance with +Real-Time Innovations, Inc.'s Automotive Software Evaluation License Agreement, +available here: +https://www.rti.com/hubfs/_Collateral/Services_and_Support/Automotive_Evaluation +_SLA_90_dayNXP.pdf . Any other use is expressly prohibited. + +RivieraWaves SAS (a member of the CEVA, Inc. family of companies): You may not +use the RivieraWaves intellectual property licensed under this Agreement if you +develop, market, and/or license products similar to such RivieraWaves +intellectual property. Such use constitutes a breach of this Agreement. Any +such use rights must be obtained directly from RivieraWaves. + +SanDisk Corporation: If the Licensed Software includes software developed by +SanDisk Corporation ("SanDisk"), you must separately obtain the rights to +reproduce and distribute this software in source code form from SanDisk. +Please follow these easy steps to obtain the license and software: +(1) Contact your local SanDisk sales representative to obtain the SanDisk +License Agreement. +(2) Sign the license agreement. Fax the signed agreement to SanDisk USA +marketing department at 408-542-0403. The license will be valid when fully +executed by SanDisk. +(3) If you have specific questions, please send an email to sales@sandisk.com +You may only use the SanDisk Corporation Licensed Software on products +compatible with a SanDisk Secure Digital Card. You may not use the SanDisk +Corporation Licensed Software on any memory device product. SanDisk retains +all rights to any modifications or derivative works to the SanDisk Corporation +Licensed Software that you may create. + +SEGGER Microcontroller - emWin Software: Your use of SEGGER emWin software and +components is restricted for development of NXP ARM7, ARM9, Cortex-M0, +Cortex-M3, Cortex-M4, Cortex-M33, Cortex-M7, and Cortex-A7 based products only. + +SEGGER Microcontroller - J-Link/J-Trace Software: Segger software must be used +consistent with the terms found here: http://www.segger.com/jlink-software.html + +SEVENSTAX - Not withstanding anything in this Agreement, SEVENSTAX GmbH +software must be used for evaluation purposes only, in strict accordance with +the SEVENSTAX License Agreement, available here: +https://www.sevenstax.de/fileadmin/documents/SEVENSTAX-NX-ESLA.txt. Any other +use, and embedding the software into commercial products, is expressly +prohibited. +Synopsys/BLE Software: Your use of the Synopsys/BLE Software and related +documentation is subject to the following: +(1) Synopsys is third-party beneficiaries of, and thus may enforce against you, +the license restrictions and confidentiality obligations in this agreement with +respect to their intellectual property and proprietary information. +(2) Your distribution of the Licensed Software shall subject any recipient to a +written agreement at least as protective of the Licensed Software as provided +in this Agreement. + +Synopsys/Target Compiler Technologies: Your use of the Synopsys/Target Compiler +Technologies Licensed Software and related documentation is subject to the +following: +(1) Duration of the license for the Licensed Software is limited to 12 months, +unless otherwise specified in the license file. +(2) The Licensed Software is usable by one user at a time on a single +designated computer, unless otherwise agreed by Synopsys. +(3) Licensed Software and documentation are to be used only on a designated +computer at the designated physical address provided by you on the APEX license +form. +(4) The Licensed Software is not sub-licensable. + +T2 Labs / T2 Software: As a condition to the grant of any license under this +Agreement, you represent and warrant that you will comply with all licenses, +agreements, rules and bylaws of the Bluetooth SIG (Special Interest Group ) +applicable to the licensed software and documentation and its use which may +affect when and if you may take certain actions under licenses granted +hereunder. + +The license grant under this Agreement is conditional to you being (i) a +Bluetooth SIG Associate member until such time as the specifications for the +software are made public to Bluetooth SIG members of any level and (ii) +thereafter a Bluetooth SIG member of any level. + +Notwithstanding the terms contained in Section 2.3 (a), if the licensed +software includes proprietary software in source code format, you may make +modifications and create derivative works only to the extent necessary for +improving the performance of the source code with the NXP products or your +products and for creating enhancements of such products. You may not further +sublicense or otherwise distribute the source code, or any modifications or +derivatives thereof as stand-alone products. You will be responsible for +qualifying any modifications or derivatives with the Bluetooth SIG and any +other qualifying bodies. + +TARA Systems: Use of TARA Systems GUI technology Embedded Wizard is limited to +evaluation and demonstration only. Permitted distributions must be similarly +limited. Further rights must be obtained directly from TARA Systems. + +Teensyduino Core Library: If the Teensyduino Core Library or documentation is +incorporated into a build system that allows selection among a list of target +devices, then similar target devices manufactured by PJRC.com must be included +in the list of target devices and selectable in the same manner. + +Texas Instruments: Your use of Texas Instruments Inc. WiLink8 Licensed Software +is restricted to NXP SoC based systems that include a compatible connectivity +device manufactured by TI. + +TES Electronic Solutions Germany (TES): TES 3D Surround View software and +associated data and documentation may only be used for evaluation purposes and +for demonstration to third parties in integrated form on a board package +containing an NXP S32V234 device. Licensee may not distribute or sublicense the +TES software. Your license to the TES software may be terminated at any time +upon notice. + +Vivante: Distribution of Vivante software must be a part of, or embedded +within, Authorized Systems that include a Vivante Graphics Processing Unit. + +Wittenstein: Your use of the SafeRTOS v9.x and Networking Stack, in object +form, is limited to your internal testing, evaluation, feedback and development +specifically for use with an NXP Product. Licensee’s license to use and +supply the software to you expires on June 25, 2026. Further rights must be +obtained directly from Wittenstein. diff --git a/MIMXRT595-evk_platform-CM4hardfp_GCC48-1.2.0/.project b/MIMXRT595-evk_platform-CM4hardfp_GCC48-1.2.0/.project deleted file mode 100644 index 85faddc..0000000 --- a/MIMXRT595-evk_platform-CM4hardfp_GCC48-1.2.0/.project +++ /dev/null @@ -1,17 +0,0 @@ - - - MIMXRT595-evk_platform-CM4hardfp_GCC48-1.2.0 - - - - - - com.is2t.microej.pro.workbench.jpfBuilder - - - - - - com.is2t.microej.pro.workbench.jpfNature - - diff --git a/Makefile b/Makefile index 9f19bc8..a8b5257 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2023 NXP +# Copyright 2023-2024 NXP # # SPDX-License-Identifier: BSD-3-Clause # @@ -24,20 +24,26 @@ BASE_DIR=$(shell pwd) endif define del_file - $(if $(filter $(OS),Windows_NT),$(if $(wildcard $(1)),cmd /c DEL /f /q $(1),),rm -f $(1)) + $(if $(filter $(OS),Windows_NT),$(if $(wildcard $(1)),cmd /c DEL /f /q $(subst /,\\,$(1)),),rm -f $(1)) endef define del_dir $(if $(filter $(OS),Windows_NT),$(if $(wildcard $(1)),cmd /c RD /s /q $(subst /,\\,$(1)),),rm -fr $(1)) endef -BSP_DIR=$(BASE_DIR)/nxpvee-mimxrt595-evk-round-bsp -PLAT_DIR=$(BASE_DIR)/MIMXRT595-evk_platform-CM4hardfp_GCC48-1.2.0 -APP_DIR=$(BASE_DIR)/nxpvee-mimxrt595-evk-round-apps -FP_DIR=$(BASE_DIR)/nxpvee-mimxrt595-evk-round-fp -MOCK_DIR=$(BASE_DIR)/nxpvee-mimxrt595-evk-round-mock -CONF_DIR=$(BASE_DIR)/nxpvee-mimxrt595-evk-round-configuration -VAL_DIR=$(BASE_DIR)/nxpvee-mimxrt595-evk-round-validation +BSP_DIR=$(BASE_DIR)/bsp +PLAT_DIR=$(BASE_DIR)/microej/MIMXRT595-evk_platform-CM4hardfp_GCC48-2.0.0 +APP_DIR=$(BASE_DIR)/microej/apps +FP_DIR=$(BASE_DIR)/microej/front-panel +MOCK_DIR=$(BASE_DIR)/microej/mock +CONF_DIR=$(BASE_DIR)/microej/vee-port-configuration +VAL_DIR=$(BASE_DIR)/microej/validation + +TEST_DIR.java.test.core=$(VAL_DIR)/core/java-testsuite-runner-core +TEST_DIR.java.test.ui=$(VAL_DIR)/ui/ui3/java-testsuite-runner-ui3 +TEST_DIR.java.test.gpio=$(VAL_DIR)/gpio/gpio-testsuite-runner + +VALIDATIONS?=core gpio ui ifeq ($(ECLIPSE_HOME_VAR),) $(error Define ECLIPSE_HOME_VAR to i.e. ~/MicroEJ/MicroEJ-SDK-21.11/rcp/) @@ -49,8 +55,11 @@ endif ifeq ($(strip $(PUBLISH)),1) PUBLISH_ARTIFACTS=-Dskip.publish=false + PUBLISH_MODE=release + MODULE_REPOSITORY_SETTINGS= else PUBLISH_ARTIFACTS= + PUBLISH_MODE= endif USAGE?=eval @@ -71,7 +80,7 @@ PROJS = nxpvee-ui include Makefile.inc help: - @echo "nxpvee-mimxrt1170-evk build system:" + @echo "nxp-vee-rt595 build system:" @echo "" @echo "Valid targets are:" @echo " nxpvee-ui.prj build complete UI project" @@ -86,7 +95,7 @@ help: @echo "" @echo "Valid options are:" @echo " S2S_TTY set validation serial port i.e. ttyACM0" - @echo " VALIDATIONS='[option]+' overrides validation projetcs to be run + @echo " VALIDATIONS='[option]+' overrides validation projects to be run {core gpio ui}" @echo " VERBOSE=1 compile in verbose mode" @echo " QUIET=1 compile in quiet mode" @echo " USAGE=[eval|prod] compile in eval or prod" diff --git a/Makefile.inc b/Makefile.inc index 1acabad..11b3918 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1,5 +1,5 @@ # -# Copyright 2023 NXP +# Copyright 2023-2024 NXP # # SPDX-License-Identifier: BSD-3-Clause # @@ -8,21 +8,15 @@ ifeq ($(OS),Windows_NT) S2SEXE=$(BSP_DIR)/projects/common/scripts/s2s.bat LINK=&& TOUCH=cmd /c type nul > +FIND_JAVA_FILES_IN_APP_DIR=$(shell cmd /c dir /s /b "$(subst /,\,$(APP_DIR))\*.java") else S2SEXE=$(BSP_DIR)/projects/common/scripts/s2s.sh LINK=; TOUCH=touch +FIND_JAVA_FILES_IN_APP_DIR=$(shell find $(APP_DIR) -name "*.java") endif -.PRECIOUS: .java.fp .java.mock .java.configuration .%.java.app - -.java.fp: - cd $(FP_DIR) $(LINK) $(MICROEJ_BUILDKIT_PATH_VAR)/bin/mmm publish \ - -Declipse.home="$(ECLIPSE_HOME)" \ - -Dcom.microej.platformbuilder.architecture.usage=$(USAGE) \ - $(MODULE_REPOSITORY_SETTINGS) \ - $(JAVA_VERBOSE) - $(TOUCH) $@ +.PRECIOUS: .java.mock .java.configuration .%.java.app .java.mock: cd $(MOCK_DIR) $(LINK) $(MICROEJ_BUILDKIT_PATH_VAR)/bin/mmm publish \ @@ -32,8 +26,8 @@ endif $(JAVA_VERBOSE) $(TOUCH) $@ -.java.configuration: - cd $(CONF_DIR) $(LINK) $(MICROEJ_BUILDKIT_PATH_VAR)/bin/mmm publish \ +.java.configuration: $(CONF_DIR)/module.ivy + cd $(CONF_DIR) $(LINK) $(MICROEJ_BUILDKIT_PATH_VAR)/bin/mmm publish $(PUBLISH_MODE) \ $(PUBLISH_ARTIFACTS) \ -Declipse.home="$(ECLIPSE_HOME)" \ -Dcom.microej.platformbuilder.architecture.usage=$(USAGE) \ @@ -47,27 +41,18 @@ endif javasec.prop : $(MICROEJ_SEC) -.java.test.core: javasec.prop - cd $(VAL_DIR)/core/java-testsuite-runner-core $(LINK) $(MICROEJ_BUILDKIT_PATH_VAR)/bin/mmm publish \ - -Declipse.home="$(ECLIPSE_HOME)" \ - $(MODULE_REPOSITORY_SETTINGS) \ - -Dcom.microej.platformbuilder.architecture.usage=$(USAGE) \ - -Dplatform-loader.target.platform.dir=$(PLAT_DIR)/source \ - -Ddeploy.bsp.root.dir=$(BSP_DIR) \ - -Dlaunch.properties.jvm="-Djava.security.properties=$(BASE_DIR)/javasec.prop" \ - -Dplatform-launcher.platform.dir=$(PLAT_DIR)/source $(JAVA_VERBOSE) - -.java.test.ui: javasec.prop - cd $(VAL_DIR)/ui/ui3/java-testsuite-runner-ui3 $(LINK) $(MICROEJ_BUILDKIT_PATH_VAR)/bin/mmm publish \ +$(addprefix .java.test.,$(VALIDATIONS)): javasec.prop + cd $(TEST_DIR$@) $(LINK) $(EXPORT) TEST_TYPE="ARMGCC" $(LINK) $(MICROEJ_BUILDKIT_PATH_VAR)/bin/mmm publish \ -Declipse.home="$(ECLIPSE_HOME)" \ $(MODULE_REPOSITORY_SETTINGS) \ -Dcom.microej.platformbuilder.architecture.usage=$(USAGE) \ -Dplatform-loader.target.platform.dir=$(PLAT_DIR)/source \ -Ddeploy.bsp.root.dir=$(BSP_DIR) \ -Dlaunch.properties.jvm="-Djava.security.properties=$(BASE_DIR)/javasec.prop" \ + -D"local.repo.url=$(BASE_DIR)/test_results/" \ -Dplatform-launcher.platform.dir=$(PLAT_DIR)/source $(JAVA_VERBOSE) -.%.java.app: javasec.prop +.%.java.app: javasec.prop $(APP_DIR)/module.ivy $(FIND_JAVA_FILES_IN_APP_DIR) cd $(APP_DIR) $(LINK) $(MICROEJ_BUILDKIT_PATH_VAR)/bin/mmm publish \ -Declipse.home="$(ECLIPSE_HOME)" \ $(MODULE_REPOSITORY_SETTINGS) \ @@ -80,10 +65,10 @@ javasec.prop : $(call del_file,.*.java.app) $(TOUCH) $@ -nxpvee-validation.prj: clean .java.fp .java.mock .java.configuration .java.test.s2s .java.test.core .java.test.ui +nxpvee-validation.prj: clean .java.mock .java.configuration .java.test.s2s $(addprefix .java.test.,$(VALIDATIONS)) echo "done" -%.prj: .java.fp .java.mock .java.configuration .%.java.app +%.prj: .java.mock .java.configuration .%.java.app make -C $(BSP_DIR)/projects/$(basename $@)/sdk_makefile $(addsuffix -flash,$(PROJS)): @@ -102,7 +87,7 @@ $(addsuffix -gdb_cmsisdap,$(PROJS)): make $(@:%-gdb_cmsisdap=%).prj make -C $(BSP_DIR)/projects/$(@:%-gdb_cmsisdap=%)/sdk_makefile gdb_cmsisdap -$(addsuffix -java_run,$(PROJS)): .java.fp .java.mock .java.configuration +$(addsuffix -java_run,$(PROJS)): .java.mock .java.configuration cd $(APP_DIR) $(LINK) $(MICROEJ_BUILDKIT_PATH_VAR)/bin/mmm run \ -Declipse.home="$(ECLIPSE_HOME)" \ $(MODULE_REPOSITORY_SETTINGS) \ @@ -111,7 +96,7 @@ $(addsuffix -java_run,$(PROJS)): .java.fp .java.mock .java.configuration -Dapplication.main.class=$(if $(MAIN),$(MAIN),$(MAIN.$(@:%-java_run=%).java.app)) \ -Dplatform-launcher.platform.dir=$(PLAT_DIR)/source $(JAVA_VERBOSE) -$(addsuffix -java_rebuild,$(PROJS)): .java.fp .java.mock .java.configuration +$(addsuffix -java_rebuild,$(PROJS)): .java.mock .java.configuration $(call del_file,.*.java.app) make .$(@:%-java_rebuild=%).java.app diff --git a/README.md b/README.md index 4b29111..dafa854 100644 --- a/README.md +++ b/README.md @@ -1,25 +1,33 @@ -- [NXP VEE for i.MX RT595 EVK v1.2.0](#nxp-vee-for-imx-rt595-evk-v120) +- [NXP Platform Accelerator for i.MX RT595 EVK v2.0.0](#nxp-platform-accelerator-for-imx-rt595-evk-v200) + - [MicroEJ SDK 6](#microej-sdk-6) + - [MicroEJ SDK 5](#microej-sdk-5) - [VEE Port Specifications](#vee-port-specifications) - [Requirements](#requirements) - [Directory structure](#directory-structure) - [Preliminary steps](#preliminary-steps) - - [Get West](#get-west) - [Get the MicroEJ SDK](#get-the-microej-sdk) - - [Get Visual Studio Code](#get-visual-studio-code) - - [Get GNU ARM Embedded Toolchain](#get-gnu-arm-embedded-toolchain) - - [Board Setup](#board-setup) + - [Get Visual Studio Code and MCUXpresso Installer tool](#get-visual-studio-code-and-mcuxpresso-installer-tool) + - [MCUXpresso Installer tool](#mcuxpresso-installer-tool) - [Fetch the source code](#fetch-the-source-code) - - [West : `PermissionError: \[WinError 5\] Access is denied`](#west--permissionerror-winerror-5-access-is-denied) - [MicroEJ IDE project setup](#microej-ide-project-setup) - [Import the project in a new workspace](#import-the-project-in-a-new-workspace) - - [Build the VEE Port](#build-the-vee-port) + - [VEE Port Build](#vee-port-build) + - [Build the mockup](#build-the-mockup) + - [Build the VEE Port](#build-the-vee-port) - [Build and run applications using the MicroEJ SDK IDE](#build-and-run-applications-using-the-microej-sdk-ide) - [Build and run the applications in simulation mode](#build-and-run-the-applications-in-simulation-mode) - [Modify the `AnimatedMascot` application](#modify-the-animatedmascot-application) - - [Build and run applications on your i.MX RT595](#build-and-run-applications-on-your-imx-rt595) + - [Build and run applications on your i.MX RT595 EVK](#build-and-run-applications-on-your-imx-rt595-evk) + - [Board Setup](#board-setup) - [Get an evaluation license](#get-an-evaluation-license) - [Build the applications for target](#build-the-applications-for-target) + - [Output of the build](#output-of-the-build) - [Build the firmware for target hardware using VS Code](#build-the-firmware-for-target-hardware-using-vs-code) + - [Load the project into VS Code](#load-the-project-into-vs-code) + - [Select a Preset](#select-a-preset) + - [Configure the project](#configure-the-project) + - [Configure the bsp features](#configure-the-bsp-features) + - [Build the project](#build-the-project) - [Run Demo Wearable VG application](#run-demo-wearable-vg-application) - [Get the application](#get-the-application) - [Run the application in simulation mode](#run-the-application-in-simulation-mode) @@ -27,122 +35,180 @@ - [Switching to a production license](#switching-to-a-production-license) - [Alternative: build and run from command line](#alternative-build-and-run-from-command-line) - [Requirements for building from command line](#requirements-for-building-from-command-line) + - [C toolchain](#c-toolchain) + - [CMake](#cmake) + - [Make](#make) - [Populate a Build Kit](#populate-a-build-kit) - [Using default evaluation license](#using-default-evaluation-license) - [Needed Environment variables](#needed-environment-variables) - [Explore available options (works on Linux)](#explore-available-options-works-on-linux) - - [compile and flash](#compile-and-flash) - - [debug](#debug) - - [Ninja](#ninja) + - [Compile and flash](#compile-and-flash) + - [Compilation defaults](#compilation-defaults) + - [Compile with just NET support enabled](#compile-with-just-net-support-enabled) + - [Debug](#debug) - [Compile Release image](#compile-release-image) - [Compile using production license](#compile-using-production-license) - [Tutorial: Using native C functions from the high level application](#tutorial-using-native-c-functions-from-the-high-level-application) - [Declaring and using native functions in the Java world](#declaring-and-using-native-functions-in-the-java-world) - [Implementing the native functions in C world](#implementing-the-native-functions-in-c-world) - [Implementing a mockup of the native functions for the simulator](#implementing-a-mockup-of-the-native-functions-for-the-simulator) - - [Get familiar with MICROEJ](#get-familiar-with-microej) + - [Get familiar with MicroEJ](#get-familiar-with-microej) - [Examples](#examples) - - [MICROEJ Documentation](#microej-documentation) + - [MicroEJ Documentation](#microej-documentation) - [Troubleshooting](#troubleshooting) + - [Setup error](#setup-error) + - [West update and "Filename too long" issue](#west-update-and-filename-too-long-issue) + - [West update and "PermissionError: \[WinError 5\] Access is denied" issue](#west-update-and-permissionerror-winerror-5-access-is-denied-issue) - [License Error when building application](#license-error-when-building-application) + - [\[M65\] - License check failed](#m65---license-check-failed) - [Flash config issue for i.MX RT595 EVK Rev. D](#flash-config-issue-for-imx-rt595-evk-rev-d) -# NXP VEE for i.MX RT595 EVK v1.2.0 -This project is used to build an NXP VEE Port for the [i.MX RT595 EVK](https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt595-evaluation-kit:MIMXRT595-EVK) with a display panel [G1120B0MIPI](https://www.nxp.com/part/G1120B0MIPI#/). -![imxrt595evk-g1120b0mipi](Documentation/pictures/RT595/imxrt595evk-g1120b0mipi.jpg) +# NXP Platform Accelerator for i.MX RT595 EVK v2.0.0 +This project is used to build NXP Platform Accelerator for the [i.MX RT595 EVK](https://www.nxp.com/design/design-center/development-boards-and-design/i-mx-evaluation-and-development-boards/i-mx-rt595-evaluation-kit:MIMXRT595-EVK) with a display panel [G1120B0MIPI](https://www.nxp.com/part/G1120B0MIPI#/). -VEE stands for Virtual Execution Environment and provides a hardware abstraction to develop applications in high-level programming languages such as Java. -NXP VEE is built upon [MicroEJ technology](https://www.microej.com/product/vee/). +![imxrt595evk](Documentation/pictures/RT595/imxrt595evk.jpg) +![g1120b0mipi](Documentation/pictures/RT595/g1120b0mipi.jpg) -This release provides: +NXP Platform Accelerator a VEE (Virtual Execution Environment) and provides a hardware abstraction to develop applications in high-level programming languages such as Java. + +NXP Platform Accelerator is built upon [MicroEJ technology](https://www.microej.com/product/vee/). + +This release includes: + +* i.MX RT595 EVK simulator to develop VEE applications and test them on a host PC + * The simulator program has a graphic display of the EVK board and its LCD panel +* The necessary recipes to embed the VEE architecture for GCC +* Various [Foundation Libraries](https://docs.microej.com/en/latest/ApplicationDeveloperGuide/libraries.html) to provide high level libraries to developers. Notable Foundation Libraries part of this release are: + * [MicroUI](https://docs.microej.com/en/latest/ApplicationDeveloperGuide/UI/MicroUI/index.html#section-app-microui) to create user interfaces + + * [MicroVG](https://docs.microej.com/en/latest/ApplicationDeveloperGuide/UI/MicroVG/index.html) to provide accelerated vector drawing capabilities + + + + +* [MCUXpresso SDK](https://mcuxpresso.nxp.com/en/welcome) 2.15.100 for i.MX RT595 EVK +* [FreeRTOS](https://www.freertos.org/index.html) version 10.5.1 +* Sample applications demonstrating NXP VEE: -* an i.MX RT595 EVK simulator to develop VEE applications and test them on a host PC -* a front panel showing the EVK and its display in the simulator -* the necessary recipes to embed the VEE architecture for GCC -* various [Foundation Libraries](https://docs.microej.com/en/latest/ApplicationDeveloperGuide/libraries.html) to provide high level libraries to developers -* in particular, Foundation Libraries [MicroUI](https://docs.microej.com/en/latest/ApplicationDeveloperGuide/UI/MicroUI/index.html#section-app-microui) to create user interfaces and [MicroVG](https://docs.microej.com/en/latest/ApplicationDeveloperGuide/UI/MicroVG/index.html) to provide accelerated vector drawing capabilities -* [MCUXpresso SDK](https://mcuxpresso.nxp.com/en/welcome) 2.12.0 for RT595 -* FreeRTOS version 10.0.0 -* sample applications demonstrating NXP VEE: * SimpleGFX: draw moving NXP coloured boxes using MicroUI + + * AnimatedMascot: draw an animated [Android Vectordrawable](https://developer.android.com/develop/ui/views/graphics/vector-drawable-resources) image using MicroVG -* a [Mock](https://docs.microej.com/en/latest/PlatformDeveloperGuide/mock.html) to give Java implementations for C native functions used by application SimpleGFX + + +* [Mock](https://docs.microej.com/en/latest/PlatformDeveloperGuide/mock.html) support with Java stub implementations to mimick C native functions. Thanks to this mock support, the SimpleGFX application can smoothly run on the simulator + +## MicroEJ SDK 6 + +NXP Platform Accelerator is built on MicroEJ technology. + +MicroEJ SDK 6 is the latest available MicroEJ SDK. +The SDK 6 uses Gradle plugin to compile and package MicroEJ modules. +It allows the user to use his favourite IDE such as Android Studio or IntelliJ IDEA (see [the list of supported IDE](https://docs.microej.com/en/latest/SDK6UserGuide/install.html#install-the-ide)). + +SDK 6 is currently limited to the build, test and simulation of **Applications and Add-on Libraries** (see [Scope and Limitations](https://docs.microej.com/en/latest/SDK6UserGuide/limitations.html#sdk-6-limitations) for more information). +If you need other features, such as **developping a VEE Port**, you have to use the SDK 5. + +If you are an application developer only and do not need to make changes to the VEE Port, you can use the SDK 6. Please click on the button below to access to the SDK 6 Getting Started on the i.MX RT595 EVK. + +[![sdk6-documentation](Documentation/pictures/common/sdk6-button.png)](https://docs.microej.com/en/latest/SDK6UserGuide/gettingStartedIMXRT595.html) + +## MicroEJ SDK 5 + +If you want to modify the VEE Port, make changes to low level source code, please use SDK 5 and continue following this README. ## VEE Port Specifications -The architecture version is ```7.20.1```. +The architecture version is ```8.1.1```. + This VEE Port provides the following Foundation Libraries: |Foundation Library|Version| |------------------|-------| |BON |1.4| +|DEVICE |1.1| |DRAWING |1.0| |EDC |1.3| -|MICROUI |3.1| -|MICROVG |1.1| +|KF |1.7| +|MICROUI |3.5| +|MICROVG |1.4| |SNI |1.4.0| |TRACE |1.1| + +The VEE Port is derived into: +* a Mono-Sandbox VEE Port (default) + + + ## Requirements * PC with Windows 10 or higher, or Linux (tested on Debian 11) * Note for Mac users: this documentation does not cover Mac usage, however it is supported by the MicroEJ tools. If you are interested in Mac support, please [contact MicroEJ](https://www.microej.com/contact/#form_2). -* Java JDK 11 see [Get the MicroEJ SDK](#get-the-microej-sdk) section -* [West](https://docs.zephyrproject.org/latest/develop/west/install.html), a meta-tool to handle git dependencies * Internet connection to [MicroEJ Central Repository](https://developer.microej.com/central-repository/) -* i.MX RT595 EVK board, available [here](https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt595-evaluation-kit:MIMXRT595-EVK) -* G1120B0MIPI display panel, available [here](https://www.nxp.com/part/G1120B0MIPI#/) +* MicroEJ SDK Distribution 23.07 or higher, available [here](https://developer.microej.com/microej-sdk-software-development-kit/) + +* i.MX RT595 EVK board (can be ordered [here](https://www.nxp.com/design/design-center/development-boards-and-design/i-mx-evaluation-and-development-boards/i-mx-rt595-evaluation-kit:MIMXRT595-EVK)) and G1120B0MIPI display panel (can be ordered [here](https://www.nxp.com/part/G1120B0MIPI#/)) + * Optionally: J-Link Debugger to flash the software ## Directory structure ``` nxp-vee-rt595 +├───bsp +│ └── projects +│ ├── common +│ ├── microej +│ └── nxpvee-ui +├── BuildKit.readme.txt +├── CHANGELOG.md ├───Documentation +├───LICENSE.txt ├───Licenses -├───MIMXRT595-evk_platform-CM4hardfp_GCC48-1.2.0 -├───nxpvee-mimxrt595-evk-round-apps -├───nxpvee-mimxrt595-evk-round-bsp -├───nxpvee-mimxrt595-evk-round-configuration -├───nxpvee-mimxrt595-evk-round-fp -├───nxpvee-mimxrt595-evk-round-imageGenerator -├───nxpvee-mimxrt595-evk-round-mock -└───nxpvee-mimxrt595-evk-round-validation +├── Makefile +├── Makefile.inc +├── microej +│ ├── apps +│ ├── front-panel +│ ├── imageGenerator +│ ├── MIMXRT595-evk_platform-CM4hardfp_GCC48-2.0.0 +│ ├── mock +│ ├── validation +│ └── vee-port-configuration +├── README.md +├── SCR-nxpvee-mimxrt595-evk.txt +├── .vscode +└── west.yml ``` Following is a quick introduction to each folder: -* `MIMXRT595-evk_platform-CM4hardfp_GCC48-1.2.0`: This folder contains the VEE runtime files. Initially, this folder is empty, but it will be populated after the building of the VEE Port. -* `nxpvee-mimxrt595-evk-round-apps`: This folder contains two Java demo applications named `AnimatedMascot` and `SimpleGFX`. They are used in this Readme as examples. -* `nxpvee-mimxrt595-evk-round-bsp`: This folder contains the C BSP project of the VEE Port. You will find the C implementation of the libraries used in this VEE Port. -* `nxpvee-mimxrt595-evk-round-configuration`: This folder contains the VEE Port configuration project. Inside it, you will find the [VEE Port Configuration](https://docs.microej.com/en/latest/VEEPortingGuide/platformConcepts.html#microej-platform-configuration) files. -* `nxpvee-mimxrt595-evk-round-fp`: This folder contains the [Front Panel](https://docs.microej.com/en/latest/VEEPortingGuide/frontpanel.html) mock of the VEE Port. It allows applications to be developed and tested in a Simulator rather than on the target device. -* `nxpvee-mimxrt595-evk-round-imageGenerator`: This folder contains the [Extended Mode](https://docs.microej.com/en/latest/VEEPortingGuide/uiImageGenerator.html#extended-mode) of the [Image Generator](https://docs.microej.com/en/latest/VEEPortingGuide/uiImageGenerator.html). -* `nxpvee-mimxrt595-evk-round-mock`: This folder contains the [Mock](https://docs.microej.com/en/latest/VEEPortingGuide/mock.html) where are implemented native method used by `SimpleGFX` application. If you are not familiar with native methods, please have a look at [Native Interface Mechanisms](https://docs.microej.com/en/latest/VEEPortingGuide/native.html) documentation. -* `nxpvee-mimxrt595-evk-round-validation`: This folder contains the Java test suites to validate the VEE Port behavior. You will find the core validation that checks the correct runtime execution of the VEE Port. You will also find the UI validation that checks drivers and implementation of LLAPI `LLUI_DISPLAY_IMPL`. +* `MIMXRT595-evk_platform-CM4hardfp_GCC48-2.0.0`: This folder contains the VEE runtime files. Initially, this folder is empty, but it will be populated after the building of the VEE Port. +* `apps`: This folder contains two Java demo applications named `AnimatedMascot` and `SimpleGFX`. They are used in this Readme as examples. +* `bsp`: This folder contains the C BSP project of the VEE Port. You will find the C implementation of the libraries used in this VEE Port. +* `vee-port-configuration`: This folder contains the VEE Port configuration project. Inside it, you will find the [VEE Port Configuration](https://docs.microej.com/en/latest/VEEPortingGuide/platformConcepts.html#microej-platform-configuration) files. +* `front-panel`: This folder contains the [Front Panel](https://docs.microej.com/en/latest/VEEPortingGuide/frontpanel.html) mock of the VEE Port. It allows applications to be developed and tested in a Simulator rather than on the target device. +* `imageGenerator`: This folder contains the [Extended Mode](https://docs.microej.com/en/latest/VEEPortingGuide/uiImageGenerator.html#extended-mode) of the [Image Generator](https://docs.microej.com/en/latest/VEEPortingGuide/uiImageGenerator.html). +* `mock`: This folder contains the [Mock](https://docs.microej.com/en/latest/VEEPortingGuide/mock.html) where are implemented native method used by `SimpleGFX` application. If you are not familiar with native methods, please have a look at [Native Interface Mechanisms](https://docs.microej.com/en/latest/VEEPortingGuide/native.html) documentation. +* `validation`: This folder contains the Java test suites to validate the VEE Port behavior. You will find the core validation that checks the correct runtime execution of the VEE Port. You will also find the UI validation that checks drivers and implementation of LLAPI `LLUI_DISPLAY_IMPL`. ## Preliminary steps -### Get West -[West](https://docs.zephyrproject.org/latest/develop/west/index.html) is a Zephyr tool for multiple repository management systems. - -It will be used to fetch the code and its dependencies. - -Install West by following [Installing west](https://docs.zephyrproject.org/latest/develop/west/install.html) instructions. - ### Get the MicroEJ SDK -The MICROEJ SDK is an Eclipse-based IDE used to build the VEE Port and the high-level applications. In addition, it is able to run a simulator of the target hardware. +The MicroEJ SDK is an Eclipse-based IDE used to build the VEE Port and the high-level applications. The SDK can be used to run the i.MX RT595 EVK simulator. -The MICROEJ SDK requires Java JDK. JDK version [depends on the MICROEJ SDK version](https://docs.microej.com/en/latest/SDKUserGuide/systemRequirements.html). +The MicroEJ SDK requires Java JDK. JDK version [depends on the MicroEJ SDK version](https://docs.microej.com/en/latest/SDKUserGuide/systemRequirements.html). * Install the JDK. You can download it on the [Java SE 11](https://www.oracle.com/java/technologies/downloads/#java11) page -* Install MICROEJ SDK 23.07. Please refer to [Download and Install – MicroEJ Documentation](https://docs.microej.com/en/latest/SDKUserGuide/installSDKDistributionLatest.html#) and [Installer Repository](https://repository.microej.com/packages/SDK/23.07/) +* Install MicroEJ SDK 23.07. Please refer to [Download and Install – MicroEJ Documentation](https://docs.microej.com/en/latest/SDKUserGuide/installSDKDistributionLatest.html#) and [Installer Repository](https://repository.microej.com/packages/SDK/23.07/) This release has been tested with MicroEJ SDK 23.07 and Java JDK 11. -### Get Visual Studio Code + +### Get Visual Studio Code and MCUXpresso Installer tool VS Code is an IDE used to build, flash and debug embedded projects. In this VEE Port release, VS Code is used to build the firmware that will be flashed to target. VS Code project uses the VEE Port and high level applications built by the MicroEJ SDK. @@ -151,91 +217,41 @@ In this VEE Port release, VS Code is used to build the firmware that will be fla * Start VS Code and install the [MCUXpresso for VS Code](https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-for-visual-studio-code:MCUXPRESSO-VSC?tid=vanMCUXPRESSO-VSC) extension package. * Install the [MCUXpresso VS Code package dependencies](https://github.com/nxp-mcuxpresso/vscode-for-mcux/wiki/Dependency-Installation) to support the full development flow. -### Get GNU ARM Embedded Toolchain -To build an image that runs on target, you need a Cortex-M toolchain. -The toolchain used to validate this release is the [GNU ARM Embedded Toolchain](https://developer.arm.com/downloads/-/gnu-rm). - -**Toolchain for Linux**: [gcc-arm-none-eabi-10.3-2021.10-x86_64-linux.tar.bz2](https://developer.arm.com/-/media/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-x86_64-linux.tar.bz2?rev=78196d3461ba4c9089a67b5f33edf82a&hash=D484B37FF37D6FC3597EBE2877FB666A41D5253B) - -**Toolchain for Windows**: [gcc-arm-none-eabi-10.3-2021.10-win32.exe](https://developer.arm.com/-/media/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-win32.exe?rev=29bb46cfa0434fbda93abb33c1d480e6&hash=3C58D05EA5D32EF127B9E4D13B3244D26188713C) +### MCUXpresso Installer tool -Once installed, the following environment variable must be set to point to the toolchain directory: - -Linux: +Using previously installed MCUXpresso Installer tool, need to install following tools that are used during compilation/debug: -* Open ` ~/.bashrc` file. -* Add the following line at the end of the file: +* CMake, Ninja, West and ARM GNU Toolchain under MCUXpresso SDK Developer +* LinkServer under its own section +* SEGGER J-Link under its own section (if optional J-Link is used) -``` -export ARMGCC_DIR=/opt/gcc-arm-none-eabi-10.3-2021.10/ -``` +These tools can also be installed independently, MCUXpresso installer tool is just providing a convenient way to install them. +In case of standalone installation, following versions need to be installed: -Windows: +* CMake version 3.27 minimum +* ARM GNU Toolchain version 13.2.1 minimum +* LinkServer version 1.6.133 minimum -* Open the `Edit the system environment variables` application on Windows. -* Click on the `Environment Variables…` button. -* Click on the `New…` button under the `User variables` section. -* Set `Variable` Name to `ARMGCC_DIR`. -* Set `Variable Value` to the toolchain directory (e.g. `C:\Program Files (x86)\GNU Arm Embedded Toolchain\10 2021.10`). -* Click on the `Ok` button until it closes `Edit the system environment variables` application. - - -## Board Setup -![Setup](Documentation/pictures/RT595/imxrt595evk-setup.jpg) - -Setup the [i.MX RT595 EVK](https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt595-evaluation-kit:MIMXRT595-EVK): -* Check that the dip switches (SW7) are set to OFF, OFF and ON (ISP0, ISP1, ISP2). -* Ensure jumpers JP18 and JP19 are closed. -* Remove jumper JP4. -* Connect the micro-USB cable to J40 to power the board. - -The USB connection is used as a serial console for the SoC, as a CMSIS-DAP debugger and as a power input for the board. - -MicroEJ VEE Port uses the virtual UART from the i.MX RT595 EVK USB port. A COM port is automatically mounted when the board is plugged into a computer using a USB cable. All board logs are available through this COM port. - -The COM port uses the following parameters: - -| Baudrate | Data bits bits | Parity bits | Stop bits | Flow control | -| -------- | -------- | -------- | -------- | -------- | -| 115200 | 8 | None | 1 | None | ## Fetch the source code -On Windows, fetching the source code may trigger the following fatal error: -```error: unable to create file [...]: Filename too long.``` -To avoid this, git configuration needs to be updated to handle long file names: - -Start Git Bash as Administrator. - -Run following command: -```git config --system core.longpaths true``` - Clone the repository with the following command: ``` -mkdir  nxpvee-mimxrt595-prj +mkdir nxpvee-mimxrt595-prj cd nxpvee-mimxrt595-prj -west init -m https://github.com/nxp-mcuxpresso/nxp-vee-imxrt595-evk.git . +west init -m https://github.com/nxp-mcuxpresso/nxp-vee-imxrt595-evk . west update ``` you will get + ``` .west nxp-vee-rt595 ``` -### West : `PermissionError: [WinError 5] Access is denied` -If you get the error `PermissionError: [WinError 5] Access is denied`, please consider the following procedure : - -``` -rm .west -cd nxp-vee-rt595 -west init -l -cd .. -west update -``` ## MicroEJ IDE project setup ### Import the project in a new workspace @@ -243,9 +259,9 @@ Launch MicroEJ SDK and create a blank workspace. Import the cloned repository as an existing project: -![Import...](Documentation/pictures/RT595/sdk_import.png) +![Import...](Documentation/pictures/common/sdk_import.png) -![Existing Projects Into Workspace](Documentation/pictures/RT595/sdk_existing_project.png) +![Existing Projects Into Workspace](Documentation/pictures/common/sdk_existing_project.png) Then select all projects from the repository. @@ -255,7 +271,7 @@ The package explorer view should look like this: ![Package Explorer](Documentation/pictures/RT595/sdk_package_explorer.png) -### Build the VEE Port +### VEE Port Build The VEE Port for the board is the first thing to build with the IDE. For demonstration purposes, one of the release examples uses a mockup (more details follow in the native functions description). The mockup is a dependency of the VEE Port and must therefore be built beforehand. @@ -266,13 +282,13 @@ Right click on the mockup project and select `Build Module`: ![Build mockup](Documentation/pictures/RT595/sdk_build_mock.png) -#### Build the VEE Port +#### Build the VEE Port Once the mockup dependency is resolved, the VEE Port can be built by using [VEE Port Build](https://docs.microej.com/en/latest/VEEPortingGuide/platformCreation.html#platform-build) instructions. Right-click on the configuration project and select `Build Module`: ![Build platform](Documentation/pictures/RT595/sdk_build_platform.png) -Building the platform will populate the initally empty `MIMXRT595-evk_platform-CM4hardfp_GCC48-1.2.0` project which will be used to build VEE applications. +Building the platform will populate the initally empty `MIMXRT595-evk_platform-CM4hardfp_GCC48-2.0.0` project which will be used to build VEE applications. Under the `source` folder of the VEE Port, you will find the following files: * The C header files of the native needed by the VEE Port libraries are located in the `include` folder. * The Java API of the VEE Port libraries is located in the `javaAPIS` folder. @@ -281,25 +297,32 @@ Under the `source` folder of the VEE Port, you will find the following files: * The VEE core, the MicroJVM, and some tools. ## Build and run applications using the MicroEJ SDK IDE + Two example VEE applications are provided with this release. + Application `SimpleGFX` displays three moving rectangles using the [MicroUI API](https://docs.microej.com/en/latest/ApplicationDeveloperGuide/UI/MicroUI/index.html#section-app-microui). The coordinates of the rectangles are calculated in C native functions. -Application `AnimatedMascot` draws an animated [Android Vectordrawable](https://developer.android.com/develop/ui/views/graphics/vector-drawable-resources) image. It uses the i.MX RT595's GCNanoLite-V as an accelerator. + +Application `AnimatedMascot` draws an animated [Android Vectordrawable](https://developer.android.com/develop/ui/views/graphics/vector-drawable-resources) image. It uses the RT595's GCNanoLite-V as an accelerator. + ### Build and run the applications in simulation mode To run applications in simulation mode, right-click on the apps project and select `Run As -> MicroEJ Application`: ![Run As MicroEJ Application](Documentation/pictures/RT595/sdk_run_as_microej_app.png) + The IDE will prompt which application should be built: either `SimpleGFX` or `AnimatedMascot`: ![Select Java Application](Documentation/pictures/RT595/sdk_choose_app.png) Choose the application. Then run the application in simulation mode by choosing the mode _(SIM)_: + ![Choose build mode](Documentation/pictures/RT595/sdk_choose_app_mode.png) + Here is the `AnimatedMascot` application running in simulation: ![Animated Mascot](Documentation/pictures/RT595/sdk_sim_mascot.png) @@ -309,7 +332,7 @@ Now we will show you how easy it is to modify and test your Java application on To do so, we will modify the background color of the `AnimatedMascot` application: -* Open the `AnimatedMascot.java` file located in the `nxpvee-mimxrt595-evk-round-apps/src/main/java/com/nxp/animatedMascot` folder. +* Open the `AnimatedMascot.java` file located in the `microej/apps/src/main/java/com/nxp/animatedMascot` folder. * It sets the background color line 57. Replace the following line: ``` g.setColor(Colors.BLACK); @@ -325,7 +348,30 @@ Here is the modified `AnimatedMascot` application running in simulation: ![Modified Animated Mascot](Documentation/pictures/RT595/sdk_sim_modified_mascot.png) -## Build and run applications on your i.MX RT595 +## Build and run applications on your i.MX RT595 EVK + + +### Board Setup +![Setup](Documentation/pictures/RT595/imxrt595evk-setup.jpg) + +Setup the [i.MX RT595 EVK](https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt595-evaluation-kit:MIMXRT595-EVK): +* Check that the dip switches (SW7) are set to OFF, OFF and ON (ISP0, ISP1, ISP2). +* Ensure jumpers JP18 and JP19 are closed. +* Remove jumper JP4. +* Connect the micro-USB cable to J40 to power the board. +* To use JLink probe ensure jumpers JP17 and JP19 are open, connect the board using J38. + +The USB connection is used as a serial console for the SoC, as a CMSIS-DAP debugger and as a power input for the board. + +MicroEJ VEE Port uses the virtual UART from the i.MX RT595 EVK USB port. A COM port is automatically mounted when the board is plugged into a computer using a USB cable. All board logs are available through this COM port. + +The COM port uses the following parameters: + +| Baudrate | Data bits bits | Parity bits | Stop bits | Flow control | +| -------- | -------- | -------- | -------- | -------- | +| 115200 | 8 | None | 1 | None | + + ### Get an evaluation license A license is required to build an embedded application. @@ -353,12 +399,13 @@ The build will produce two artifacts: These artifacts are copied to the BSP project in the directory `projects/microej/platform/lib`. ### Build the firmware for target hardware using VS Code -Once the application is ready, the firmware can be built using a C toolchain for Cortex-M. + + #### Load the project into VS Code Launch VS Code IDE and click on `File -> Add Folder to Workspace...` -![Add Folder to Workspace](Documentation/pictures/RT595/vscode_load_project.png) +![Add Folder to Workspace](Documentation/pictures/common/vscode_load_project.jpg) Navigate to the nxp-vee-rt595 path then click `Add`. @@ -366,34 +413,34 @@ From here you can compile and debug the project as any other C project. To do so you need to configure then build the CMake project by following the steps below: -#### Scan for kits to locate all available toolchains -Open the Command Palette (`CTRL + SHIFT + p`) and run `CMake: Scan for kits`. - -![VScode scan for kits](Documentation/pictures/RT595/vscode_scan_for_kits.png) - -#### Select the toolchain that will build the project -Open the Command Palette (`CTRL + SHIFT + p`) and run `CMake: Select a kit` +#### Select a Preset +Open the Command Palette (`CTRL + SHIFT + p`) and run `CMake: Select Configure Preset` to select the build mode you wish to use. -![VScode select a kit](Documentation/pictures/RT595/vscode_select_a_kit-1.png) +By default, you can select `debug` variant. -Choose the compiler `armgcc` in the path of your project. -![VScode select gcc compiler](Documentation/pictures/RT595/vscode_select_a_kit-2.png) +![VScode select build variant](Documentation/pictures/common/vscode_select_preset.jpg) -#### Select a build variant -Open the Command Palette (`CTRL + SHIFT + p`) and run `CMake: Select variant` to select the build mode you wish to use. +This can also be done by using Projects section from MCUXpresso for VS code" view, and choose appropriate build as default. -![VScode select build variant](Documentation/pictures/RT595/vscode_select_variant.png) +![VScode Projects view](Documentation/pictures/common/vscode_projects_view.jpg) #### Configure the project Open the Command Palette (`CTRL + SHIFT + p`) and run `CMake: Configure`. -![VScode select configure](Documentation/pictures/RT595/vscode_select_configure.png) +![VScode select configure](Documentation/pictures/common/vscode_select_configure.jpg) + +#### Configure the bsp features + +Compilation flags are located on `./bsp/projects/nxpvee-ui/armgcc/CMakePresets.json`. +To enable any desired features, please edit `CMakePresets.json` file (and reload preset & re-configure if needed). + + #### Build the project Open the Command Palette (`CTRL + SHIFT + p`) and run `CMake: Build`. -![VScode build project](Documentation/pictures/RT595/vscode_select_build.png) +![VScode build project](Documentation/pictures/common/vscode_select_build.jpg) You can connect VS Code to the board using the Serial Link USB or using a SEGGER J-Link probe. Follow the [Board Hardware User Guide](#board-setup) for more information on how to connect the different debuggers. @@ -402,21 +449,24 @@ Debug session can be started by pressing the `F5` key. It is also possible to build and debug the project via the MCUXpresso plugin: -Right click on the project nxp-vee-rt595, then: +Right click on the project, then: + * `Build Selected` to compile * `Debug` to debug -![VScode MCUXpresso build and debug project](Documentation/pictures/RT595/vscode_mcuxpr_build_debug.png) +![VScode MCUXpresso build and debug project](Documentation/pictures/common/vscode_mcuxpr_build_debug.jpg) Once the firmware is flashed, you should see the application running on the target. -#### Note: +Note: +It is possible to flash (without debug) via the MCUXpresso plugin by selecting `Flash the Selected Target`. In case of connection issue to the target, reset the debug probe selection via the MCUXpresso plugin: + * Select the MCUXpresso plugin in the left banner * Right-click on the project name and select `Reset Probe Selection` * Start the debug again -![VScode MCUXpresso reset probe selection](Documentation/pictures/RT595/vscode_reset_probe_selection.png) +![VScode MCUXpresso reset probe selection](Documentation/pictures/common/vscode_reset_probe_selection.jpg) ## Run Demo Wearable VG application @@ -464,6 +514,8 @@ Then follow [Build the firmware for the target hardware](#build-the-firmware-for ## Switching to a production license To switch to a production license, please contact your NXP representative. + + ## Alternative: build and run from command line This has only been tested on Linux. @@ -483,9 +535,12 @@ If not, you must add it: Linux: ``` -export ARMGCC_DIR=/opt/gcc-arm-none-eabi-10.3-2021.10/ +export ARMGCC_DIR=/arm-gnu-toolchain-13.2.Rel1-x86_64-arm-none-eabi/ ``` +Note: +Need at least ARM GNU toolchain version >= 13.2.1 + #### CMake The build system used to generate the firmware is based on CMake. @@ -494,6 +549,9 @@ Linux: to install CMake on a Debian based distro, run: sudo apt install cmake ``` +Note: +Need at least cmake version >= 3.27 + #### Make Linux: to install GNU Make on a Debian based distro, run: ``` @@ -510,7 +568,7 @@ The Build Kit is bundled with the SDK and can be exported using the following st Click on the Finish button. ``` ### Using default evaluation license -Please follow [Install the License Key](https://docs.microej.com/en/latest/SDKUserGuide/licenses.html#install-the-license-key) to be able to use make with an evaluation key +Please follow [Install the License Key](https://docs.microej.com/en/latest/SDKUserGuide/licenses.html#install-the-license-key) to be able to use make with an evaluation key ### Needed Environment variables In order to compile correctly you will need to export @@ -527,11 +585,12 @@ export MODULE_REPOSITORY_SETTINGS_FILE_VAR=${HOME}/microej/microej-partial-repos if you are using LinkServer to flash your board, append your path with the following command: ``` -export PATH=$PATH:/usr/local/LinkServer_1.3.15/binaries/ +export PATH=$PATH:/usr/local/LinkServer_1.6.133/binaries/:/usr/local/LinkServer_1.6.133/ ``` -#### Note: +Note: Use full path names in above environment variables, do not use special character `~` to represent your home directory. +LinkServer version 1.6.133 is depicted on the command line because this version is working fine, it may work with other versions as well but this is not tested. ### Explore available options (works on Linux) ``` @@ -539,39 +598,48 @@ make # will get you clean # clean all projects -nxpvee-ui-clean # clean UI project -nxpvee-ui-gdb # debug UI project using gdb and jlink -nxpvee-ui-java_run # run simulation, you can override java main using MAIN=com.nxp.animatedMascot.AnimatedMascot make nxpvee-ui-java_run -nxpvee-ui-flash # flash board using jlink -nxpvee-ui-gdb_cmsisdap # debug UI project using gdb and CMSIS nxpvee-ui.prj # build complete UI project +nxpvee-ui-clean # clean UI project +nxpvee-ui-flash # flash board using Jlink nxpvee-ui-flash_cmsisdap # flash board using CMSIS +nxpvee-ui-gdb # debug UI project using gdb and Jlink +nxpvee-ui-gdb_cmsisdap # debug UI project using gdb and CMSIS +nxpvee-ui-java_run # run simulation, you can override java main using MAIN=com.nxp.animatedMascot.AnimatedMascot make nxpvee-ui-java_run nxpvee-ui-java_rebuild # rebuild java app nxpvee-validation.prj # compile and run validation ``` -### compile and flash +### Compile and flash ``` -nxpvee-ui.prj +make nxpvee-ui.prj # flash with a J-Link probe -nxpvee-ui-flash +make nxpvee-ui-flash # or flash with USB using CMSIS-DAP -nxpvee-ui-flash_cmsisdap +make nxpvee-ui-flash_cmsisdap ``` -### debug +### Compilation defaults +Demo app is compiled with +- NET +- SSL +by default + + +### Compile with just NET support enabled ``` -nxpvee-ui-gdb -# or -nxpvee-ui-gdb_cmsisdap +make nxpvee-ui.prj CMAKE_OPTS="-DENABLE_NET=1" ``` -### Ninja -to speed up compilation you can use ninja instead of make + + + +### Debug ``` -MAKE=ninja make nxpvee-ui.prj +make nxpvee-ui-gdb +# or +make nxpvee-ui-gdb_cmsisdap ``` ### Compile Release image @@ -589,6 +657,7 @@ make nxpvee-ui.prj USAGE=prod + ## Tutorial: Using native C functions from the high level application Some functions directly used by the high-level application can be implemented in C. It is called the [Native Interface Mechanism](https://docs.microej.com/en/latest/VEEPortingGuide/native.html). @@ -636,12 +705,12 @@ int Java_com_nxp_application_MyClassNatives_NativeFunction(int a) When you implement a native method, it is recommended to use the type of `sni.h` rather than the native type. This ensures type consistency between Java and C. You could use `jint` instead of `int` in the example above. -The `sni.h` file is located on `nxpvee-mimxrt595-evk-round-bsp/project/microej/platform/inc` folder. +The `sni.h` file is located on `nxp-vee-rt595/bsp/projects/microej/platform/inc` folder. ### Implementing a mockup of the native functions for the simulator Mockup functions are used to simulate the behavior of native functions when using the MicroEJ SDK Simulator. Mockups are detailed in the [MicroEJ website](https://docs.microej.com/en/latest/PlatformDeveloperGuide/mock.html). -They are implementated in a different MicroEJ SDK project (`nxpvee-mimxrt595-evk-round-mock`). +They are implementated in a different MicroEJ SDK project (`microej/mock`). The name of the file containing the mockup functions is supposed to be the same as the one where the native functions are declared in the application project (e.g. `SimpleGFXNatives.java`). @@ -660,17 +729,17 @@ public class MyClassNatives { }; ```` -Please note that this project mockup must be added as a dependency inside the VEE Port's `module.ivy` file. The `module.ivy` file is located in the `nxpvee-mimxrt595-evk-round-configuration` folder. You will find inside all the dependencies used by the VEE Port. +Please note that this project mockup must be added as a dependency inside the VEE Port's `module.ivy` file. The `module.ivy` file is located in the `microej/vee-port-configuration` folder. You will find inside all the dependencies used by the VEE Port. ![Mockup Declaration in platform](Documentation/pictures/RT595/sdk_mockup_declaration_in_platform.png) The `org` and `name` fields can be found inside the mockup's `module.ivy` file (respectively `organisation` and `module`): -![Mockup org and name declaration](Documentation/pictures/RT595/sdk_mockup_org_name_declaration.png) +![Mockup org and name declaration](Documentation/pictures/common/sdk_mockup_org_name_declaration.png) After any modification to the mockup project, you need to rebuild the mock (right click on the mock project and select `Build Module`) and the platform (see [Build the platform](#build-the-vee-port)). -## Get familiar with MICROEJ +## Get familiar with MicroEJ To discover insights about MicroEJ technology, please follow some of the entry points below. In addition, you will find useful links to our documentation and our GitHub. @@ -686,16 +755,44 @@ You can try to run other examples on our VEE Port. Here is an exhaustive list of * Some [Demo projects](https://github.com/orgs/MicroEJ/repositories?q=demo&type=all&language=&sort=). -### MICROEJ Documentation +### MicroEJ Documentation -You can take a look at the MICROEJ development documentation. +You can take a look at the MicroEJ development documentation. Below you can find some important chapters: * [Application Developer Guide](https://docs.microej.com/en/latest/ApplicationDeveloperGuide/index.html): It covers concepts essential to MicroEJ Applications design. -* [MICROEJ VEE Port Developer Guide](https://docs.microej.com/en/latest/VEEPortingGuide/index.html): It covers the main process and configuration of a MicroEJ VEE. +* [MicroEJ VEE Port Developer Guide](https://docs.microej.com/en/latest/VEEPortingGuide/index.html): It covers the main process and configuration of a MicroEJ VEE. * [Tutorials](https://docs.microej.com/en/latest/Tutorials/index.html#): There are multiple tutorials to master different subjects about the MicroEJ environment (including UI development, code quality and debug, CI/CD…). ## Troubleshooting +### Setup error + +#### West update and "Filename too long" issue + +On Windows, fetching the source code may trigger the following fatal error: +```error: unable to create file [...]: Filename too long.``` + +To avoid this, git configuration needs to be updated to handle long file names: + +Start Git Bash as Administrator. + +Run following command: +```git config --system core.longpaths true``` + + +#### West update and "PermissionError: [WinError 5] Access is denied" issue + +If you get the error `PermissionError: [WinError 5] Access is denied`, please consider the following procedure : + +``` +rm .west +cd nxp-vee-rt595 +west init -l +cd .. +west update +``` + + ### License Error when building application #### [M65] - License check failed @@ -718,3 +815,4 @@ By: ``` + diff --git a/SCR-nxpvee-mimxrt595-evk.txt b/SCR-nxpvee-mimxrt595-evk.txt index 326c165..b4557fb 100644 --- a/SCR-nxpvee-mimxrt595-evk.txt +++ b/SCR-nxpvee-mimxrt595-evk.txt @@ -1,7 +1,9 @@ Release Name: NXPVEE-MIMXRT595-EVK -Release Version: 1.2.0 -Date: December 2023 -Package License: EULA_EVAL.txt v21 December 2022 +Release Version: 2.0.0 +Date: October 2024 +Package License: LICENSE.txt +Outgoing License: LA_OPT_NXP_Software_License v57 July 2024, Section 2.3 applies + SDK_Peripheral_Driver Name: SDK Peripheral Driver Version: 2.x.x @@ -11,7 +13,7 @@ SDK_Peripheral_Driver Name: SDK Peripheral Driver Description: Peripheral drivers are designed for the most common use cases identified for the underlying hardware block. - Location: nxpvee-mimxrt595-evk-round-bsp/mcux-sdk/core/devices//drivers + Location: bsp/mcux-sdk/core/devices//drivers Origin: NXP (BSD-3-Clause) SDK_Examples Name: SDK examples @@ -23,7 +25,7 @@ SDK_Examples Name: SDK examples Description: SDK out of box examples to show how to use peripheral drivers and integrate middleware. - Location: nxpvee-mimxrt595-evk-round-bsp/mcux-sdk/core/boards/ + Location: bsp/mcux-sdk/core/boards/ Origin: NXP (BSD-3-Clause) SDK_Device Name: SDK SoC files @@ -33,55 +35,55 @@ SDK_Device Name: SDK SoC files Format: source code, linker files Description: Device system files, template files, IDE related startup and linker files. - Location: nxpvee-mimxrt595-evk-round-bsp/mcux-sdk/core/devices/ + Location: bsp/mcux-sdk/core/devices/ Origin: NXP (BSD-3-Clause) cmsis Name: CMSIS Version: 5.8.0 Outgoing License: Apache License 2.0 - License File: nxpvee-mimxrt595-evk-round-bsp/mcux-sdk/core/CMSIS/LICENSE.txt + License File: bsp/mcux-sdk/core/CMSIS/LICENSE.txt Format: source code Description: Vendor-independent hardware abstraction layer for microcontrollers that are based on Arm Cortex processors, distributed by ARM. cores - Location: nxpvee-mimxrt595-evk-round-bsp/mcux-sdk/core/CMSIS + Location: bsp/mcux-sdk/core/CMSIS Origin: ARM (Apache-2.0) - https://github.com/ARM-software/CMSIS_5/releases/t ag/5.8.0 -freertos_kernel Name: FreeRTOS - Version: 10.2.1 +freertos-kernel Name: FreeRTOS kernel + Version: 10.5.1 Outgoing License: MIT - License File: nxpvee-mimxrt595-evk-round-bsp/mcux-sdk/rtos/freertos/freertos-kernel/LICENSE.md + License File: bsp/mcux-sdk/rtos/freertos/freertos-kernel/LICENSE.md Format: source code Description: Open source RTOS kernel for small devices - Location: nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel + Location: bsp/sdk_overlay/rtos/freertos/freertos-kernel Origin: Amazon (MIT) - Url: https://aws.amazon.com/freertos/ + Url: https://github.com/FreeRTOS/FreeRTOS-Kernel cmsis_drivers Name: SDK CMSIS Peripheral Drivers Version: 2.x.x Outgoing License: Apache License 2.0 - License File: nxpvee-mimxrt595-evk-round-bsp/mcux-sdk/core/CMSIS/LICENSE.txt + License File: bsp/mcux-sdk/core/CMSIS/LICENSE.txt Format: source code Description: CMSIS Peripheral drivers are designed to provide hardware independent APIs which make application reusable across a wide range of supported microcontroller devices. - Location: nxpvee-mimxrt595-evk-round-bsp/mcux-sdk/core/cmsis_drivers + Location: bsp/mcux-sdk/core/cmsis_drivers Origin: NXP (Apache License 2.0) vglite Name: vglite - Version: 3.0.15_rev4 + Version: 3.0.15_rev7 Outgoing License: MIT License File: - nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/LICENSE.txt + bsp/sdk_overlay/middleware/vglite/LICENSE.txt Format: source code Description: VeriSilicon's platform independent VGLite Graphics library - Location: nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite + Location: bsp/sdk_overlay/middleware/vglite Origin: VeriSilicon (http://www.verisilicon.com/) Url: http://www.verisilicon.com/ @@ -89,11 +91,11 @@ mcufont Name: mcufont Version: 1.0 Outgoing License: MIT License File: - nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/LICENSE + bsp/sdk_overlay/middleware/vglite/font/mcufont/LICENSE Format: source code Description: Font rendering library for microcontrollers - Location: nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont + Location: bsp/sdk_overlay/middleware/vglite/font/mcufont Origin: Petteri Aimonen (https://github.com/PetteriAimonen) Url: https://github.com/mcufont/mcufont @@ -102,10 +104,10 @@ FreeType Name: FreeType Version: 2.11 Outgoing License: FTL License File: - nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/FTL.TXT + bsp/projects/microej/thirdparty/freetype/FTL.TXT Format: source code Description: Software library to render fonts - Location: nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype + Location: bsp/projects/microej/thirdparty/freetype Origin: The FreeType Project (http://freetype.org/license.html) Url: https://gitlab.freedesktop.org/freetype/freetype.git @@ -113,10 +115,10 @@ HarfBuzz Name: HarfBuzz Version: 4.2.1 Outgoing License: Old MIT License File: - nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/COPYING + bsp/projects/microej/thirdparty/harfbuzz/COPYING Format: source code Description: Text shaping library - Location: nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz + Location: bsp/projects/microej/thirdparty/harfbuzz Origin: HarfBuzz Project (https://harfbuzz.github.io/) Url: https://github.com/harfbuzz/harfbuzz @@ -124,48 +126,48 @@ SystemView Target Sources Name: SystemView Target Sources Version: 2.52a Outgoing License: SEGGER BSD License File: - nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/LICENSE + bsp/projects/microej/thirdparty/systemview/LICENSE Format: source code Description: Target code for real-time recording and visualization tool - Location: nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview - nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview-freertos + Location: bsp/projects/microej/thirdparty/systemview + bsp/projects/microej/thirdparty/systemview-freertos Origin: SEGGER (https://www.segger.com) Url: https://www.segger.com/downloads/systemview/SystemView_Src_V252a.zip SimpleGFX Name: SimpleGFX Version: 0.1 Outgoing License: BSD-3-Clause - License File: nxpvee-mimxrt595-evk-round-apps/LICENSE.txt + License File: microej/apps/LICENSE.txt Format: source code Description: example of a graphics VEE application - Location: nxpvee-mimxrt595-evk-round-apps/src/main/java/com/nxp/simpleGFX + Location: microej/apps/src/main/java/com/nxp/simpleGFX Origin: NXP (BSD-3-Clause) SimpleGFX MOCK Name: SimpleGFX Mock Version: 0.1 Outgoing License: BSD-3-Clause - License File: nxpvee-mimxrt595-evk-round-mock/LICENSE.txt + License File: microej/mock/LICENSE.txt Format: source code Description: Mock the SimpleGFX natives. - Location: nxpvee-mimxrt595-evk-round-mock/src/main/java/com/nxp/ + Location: microej/mock/src/main/java/com/nxp/ Origin: NXP (BSD-3-Clause) AnimatedMascot Name: AnimatedMascot Version: 0.1 Outgoing License: BSD-3-Clause - License File: nxpvee-mimxrt595-evk-round-apps/LICENSE.txt + License File: microej/apps/LICENSE.txt Format: source code Description: VEE application demonstrating vectorial animation - Location: nxpvee-mimxrt595-evk-round-apps/src/main/java/com/nxp/animatedMascot + Location: microej/apps/src/main/java/com/nxp/animatedMascot Origin: NXP (BSD-3-Clause) DEMO-WEARABLE-VG MOCK Name: Demo-Wearable-VG Mock Version: 1.0.0 Outgoing License: BSD-3-Clause - License File: nxpvee-mimxrt595-evk-round-mock/LICENSE.txt + License File: microej/mock/LICENSE.txt Format: source code Description: Mock the Demo-Wearable-VG natives. - Location: nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/ + Location: microej/mock/src/main/java/com/microej/ Origin: MicroEJ MicroEJ BSP Name: MicroEJ BSP @@ -174,7 +176,7 @@ MicroEJ BSP Name: MicroEJ BSP License File: Licenses/COPYING-BSD-3 Format: source code Description: Board support package for i.MX RT595 - Location: nxpvee-mimxrt595-evk-round-bsp/projects/microej (excluding subdirectory + Location: bsp/projects/microej (excluding subdirectory thirdparty) Origin: MicroEJ (https://www.microej.com/) @@ -184,7 +186,7 @@ MicroEJ EDC Name: Embedded Device Configuration (EDC) License File: Licenses/MICROEJ_SDK_EULA.txt Description: Implementation of the minimal standard runtime environment for embedded devices - Location: dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Location: dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/ApplicationDeveloperGuide/runtime.html?highlight=edc#embedded-device-configuration-edc @@ -193,7 +195,7 @@ MicroEJ BON Name: Beyond Profile (BON) Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Control memory usage and start-up sequences - Location: dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Location: dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/ApplicationDeveloperGuide/runtime.html?highlight=edc#beyond-profile-bon @@ -202,7 +204,7 @@ External Resource Loader Name: External Resource Loader Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Allows use of external resources - Location: dependency of nxpvee-mimxrt595-evk-round-configuration/imxrt595evk.platform + Location: dependency of microej/vee-port-configuration/imxrt595evk.platform Origin: MicroEJ Url: https://docs.microej.com/en/latest/VEEPortingGuide/externalResourceLoader.html @@ -211,44 +213,62 @@ JAVAFX Name: JavaFX Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Library to create Java user interfaces. Used by Demo-Wearable-VG mock. - Location: dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Location: dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/VEEPortingGuide/mock.html#javafx Url: https://openjfx.io/ KF Name: Kernel Features (KF) - Version: 1.6 + Version: 1.7 Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Java implementation of the Multi-Sandbox features - Location: transitive dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Location: transitive dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/VEEPortingGuide/appendix/javalibs/kf.html MicroUI Name: MicroUI - Version: 3.1.0 + Version: 3.5 Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt - Description: Enable the creation of user interface in Java - Location: dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Description: MicroUI API module. + Location: transitive dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/ApplicationDeveloperGuide/UI/MicroUI/index.html?highlight=microui +MicroUI Pack Name: MicroUI Pack + Version: 14.0.1 + Outgoing License: MicroEJ SDK EULA + License File: Licenses/MICROEJ_SDK_EULA.txt + Description: Enable the creation of user interface in Java + Location: dependency of microej/vee-port-configuration/module.ivy + Origin: MicroEJ + Url: https://docs.microej.com/en/latest/VEEPortingGuide/ui.html + MicroVG Name: MicroVG - Version: 1.1.1 + Version: 1.4.0 Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt - Description: Vector drawing library - Location: dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Description: MicroVG API module. + Location: transitive dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/ApplicationDeveloperGuide/UI/MicroVG/index.html?highlight=microvg +MicroVG Pack Name: MicroVG Pack + Version: 1.5.1 + Outgoing License: MicroEJ SDK EULA + License File: Licenses/MICROEJ_SDK_EULA.txt + Description: Vector drawing library + Location: dependency of microej/vee-port-configuration/module.ivy + Origin: MicroEJ + Url: https://docs.microej.com/en/latest/VEEPortingGuide/vg.html + MWT Name: Micro Widget Toolkit Version: 3.2.1 Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Simplify the creation and use of graphical user interface widgets in Java - Location: dependency of nxpvee-mimxrt595-evk-round-apps/module.ivy + Location: dependency of microej/imageGenerator/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/ApplicationDeveloperGuide/UI/MWT/index.html @@ -257,7 +277,7 @@ NLS Name: Native Language Support (NLS) Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Support translation in different languages - Location: transitive dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Location: transitive dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/ApplicationDeveloperGuide/nls.html @@ -266,7 +286,7 @@ PUMP Name: Pump Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Used by MicroUI to manage events - Location: transitive dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Location: transitive dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ RESOURCE MANAGER Name: Resource Manager @@ -274,7 +294,7 @@ RESOURCE MANAGER Name: Resource Manager Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Manage resources - Location: transitive dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Location: transitive dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ SNI Name: Simple Native Interface (SNI) @@ -282,7 +302,7 @@ SNI Name: Simple Native Interface (SNI) Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Allow to call native method from managed code - Location: transitive dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Location: transitive dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/VEEPortingGuide/sni.html @@ -291,7 +311,7 @@ TRACE Name: Trace Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Record integer based events for debugging and monitoring purposes - Location: transitive dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Location: transitive dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/ApplicationDeveloperGuide/trace.html#event-tracing @@ -300,7 +320,7 @@ WATCHDOG Name: Watchdog Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Watchdog used by MicroUI - Location: transitive dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Location: transitive dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ WIDGET Name: Widget Toolkit @@ -308,7 +328,7 @@ WIDGET Name: Widget Toolkit Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Provides very common widgets with basic implementations - Location: dependency of nxpvee-mimxrt595-evk-round-fp/module.ivy + Location: dependency of microej/front-panel/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/ApplicationDeveloperGuide/UI/Widgets/widget.html @@ -317,7 +337,7 @@ DRAWING Name: Drawing Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Contains shapes rendering and image with transformation rendering algorithms - Location: transitive dependency of nxpvee-mimxrt595-evk-round-apps/module.ivy + Location: transitive dependency of microej/imageGenerator/module.ivy Origin: MicroEJ Url: https://repository.microej.com/javadoc/microej_5.x/apis/ej/drawing/package-summary.html @@ -326,7 +346,7 @@ BASICTOOL Name: Basic Tool Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Miscellaneous tools - Location: transitive dependency of nxpvee-mimxrt595-evk-round-apps/module.ivy + Location: transitive dependency of microej/imageGenerator/module.ivy Origin: MicroEJ Url: https://repository.microej.com/javadoc/microej_5.x/apis/ej/basictool/package-summary.html @@ -335,7 +355,7 @@ COLLECTIONS Name: Collections Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Static methods that operate on or return collections - Location: transitive dependency of nxpvee-mimxrt595-evk-round-apps/module.ivy + Location: transitive dependency of microej/imageGenerator/module.ivy Origin: MicroEJ Url: https://repository.microej.com/javadoc/microej_5.x/apis/index.html?java/util/Collections.html @@ -344,7 +364,7 @@ JUNIT Name: Junit Outgoing License: Eclipse Public License - v 1.0 License File: https://spdx.org/licenses/EPL-1.0.html Description: Unit test framework - Location: dependency of nxpvee-mimxrt595-evk-round-apps/module.ivy + Location: dependency of microej/imageGenerator/module.ivy Origin: JUNIT Url: https://junit.org/ @@ -353,7 +373,7 @@ FRONTPANEL Name: Frontpanel Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Frontpanel creation library - Location: dependency of nxpvee-mimxrt595-evk-round-fp/module.ivy + Location: dependency of microej/front-panel/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/PlatformDeveloperGuide/frontpanel.html @@ -362,7 +382,7 @@ MICROVG FRONTPANEL Name: MicroVG Frontpanel Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Provides native implementation of equivalent VectorGraphics classes to Front Panel projects - Location: transitive dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Location: transitive dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ FRAMEWORK Name: Frontpanel Framework Library @@ -370,7 +390,7 @@ FRAMEWORK Name: Frontpanel Framework Library Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Frontpanel framework creation library - Location: dependency of nxpvee-mimxrt595-evk-round-fp/module.ivy + Location: dependency of microej/front-panel/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/PlatformDeveloperGuide/frontpanel.html @@ -378,7 +398,7 @@ HILEngine Name: Hardware In the Loop interface Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Simulates Java-to-C calls. - Location: dependency of nxpvee-mimxrt595-evk-round-mock/module.ivy + Location: dependency of microej/mock/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/PlatformDeveloperGuide/simulation.html @@ -387,15 +407,15 @@ IMAGEGENERATOR Name: Image Generator Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: Off-board tool in charge of generating image data - Location: dependency of nxpvee-mimxrt595-evk-round-imageGenerator/module.ivy + Location: dependency of microej/imageGenerator/module.ivy Origin: MicroEJ Url: https://docs.microej.com/en/latest/PlatformDeveloperGuide/uiImageGenerator.html ARCHITECTURE Name: Microej Architecture Image Generator - Version: flopi4G25-7.20.1 + Version: flopi4G25-8.1.1 Outgoing License: MicroEJ SDK EULA License File: Licenses/MICROEJ_SDK_EULA.txt Description: MicroEJ Architecture for GNU Tools for ARM Embedded Processors 4.8. - Location: dependency of nxpvee-mimxrt595-evk-round-configuration/module.ivy + Location: dependency of microej/vee-port-configuration/module.ivy Origin: MicroEJ - Url: https://repository.microej.com/architectures/com/microej/architecture/CM4/CM4hardfp_GCC48/flopi4G25/7.20.1/ + Url: https://repository.microej.com/architectures/com/microej/architecture/CM4/CM4hardfp_GCC48/flopi4G25/8.1.1/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/.project b/bsp/.project similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/.project rename to bsp/.project diff --git a/bsp/nvee_version.txt b/bsp/nvee_version.txt new file mode 100644 index 0000000..227cea2 --- /dev/null +++ b/bsp/nvee_version.txt @@ -0,0 +1 @@ +2.0.0 diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/common/scripts/s2s.bat b/bsp/projects/common/scripts/s2s.bat similarity index 84% rename from nxpvee-mimxrt595-evk-round-bsp/projects/common/scripts/s2s.bat rename to bsp/projects/common/scripts/s2s.bat index cb5142c..e9e1d99 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/common/scripts/s2s.bat +++ b/bsp/projects/common/scripts/s2s.bat @@ -4,7 +4,7 @@ set S2S_PORT=%2 netstat -an | findstr /RC:":%S2S_PORT% .*LISTENING" if /I %errorlevel% NEQ 0 ( - cd MIMXRT595-evk_platform-CM4hardfp_GCC48-1.2.0/source + cd microej/MIMXRT595-evk_platform-CM4hardfp_GCC48-2.0.0/source start "s2s.bat" cmd /k java ^ -Djava.library.path="resources/os/Windows64" ^ -cp "tools/*" ^ diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/common/scripts/s2s.sh b/bsp/projects/common/scripts/s2s.sh similarity index 85% rename from nxpvee-mimxrt595-evk-round-bsp/projects/common/scripts/s2s.sh rename to bsp/projects/common/scripts/s2s.sh index b45cdf0..b77e703 100755 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/common/scripts/s2s.sh +++ b/bsp/projects/common/scripts/s2s.sh @@ -8,7 +8,7 @@ S2S_PORT=${2} if [ "$(ss -a | grep "\<${S2S_PORT}\>")" == "" ] then - cd MIMXRT595-evk_platform-CM4hardfp_GCC48-1.2.0/source + cd microej/MIMXRT595-evk_platform-CM4hardfp_GCC48-2.0.0/source java \ -Djava.library.path="resources/os/Linux64" \ -cp "tools/*" \ diff --git a/bsp/projects/common/sdk_makefile/Makefile b/bsp/projects/common/sdk_makefile/Makefile new file mode 100644 index 0000000..da648e7 --- /dev/null +++ b/bsp/projects/common/sdk_makefile/Makefile @@ -0,0 +1,90 @@ +# +# Copyright 2023-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# + +COMMON_PATH=../../common/sdk_makefile + +define del_file + $(if $(filter $(OS),Windows_NT),$(if $(wildcard $(1)),cmd /c DEL /f /q $(subst /,\\,$(1)),),rm -f $(1)) +endef + +define del_dir + $(if $(filter $(OS),Windows_NT),$(if $(wildcard $(1)),cmd /c RD /s /q $(subst /,\\,$(1)),),rm -fr $(1)) +endef + +ifeq ($(OS),Windows_NT) +JLINKEXE="$(JLINK_INSTALLATION_DIR)/Jlink.exe" +JLINK_GDB="$(COMMON_PATH)/debug/jlink_gdb.bat" +else +JLINKEXE=JLinkExe +JLINK_GDB="$(COMMON_PATH)"/debug/jlink_gdb.sh +endif + +JLINK_SCRIPT="jlink_flash.script" + +MAKE = ninja +OBJCOPY="$(ARMGCC_DIR)/bin/arm-none-eabi-objcopy" + + +ifeq ($(OS),Windows_NT) +GDB="$(ARMGCC_DIR)/bin/arm-none-eabi-gdb.exe" +NUM_PROC= +CLEAN_SCRIPT="./clean.bat" +else +GDB=gdb-multiarch +NUM_PROC=$(shell nproc) +CLEAN_SCRIPT="./clean.sh" +endif + +ifeq ($(MAKE),make) +MAKE_OP=-j$(NUM_PROC) +endif + +BUILD_DIR=../armgcc/$(FLAVOUR) + +all: $(BUILD_DIR) remake + +ifeq ($(OS),Windows_NT) +BUILD_SCRIPT="./build_$(FLAVOUR).bat" +CMSIS_GDB_TEMP_FOLDER="$(TEMP)"/gdb.cmd +else +BUILD_SCRIPT=./build_$(FLAVOUR).sh +CMSIS_GDB_TEMP_FOLDER=/tmp/gdb.cmd +endif + +$(BUILD_DIR): + cd ../armgcc/ && $(BUILD_SCRIPT) $(MAKE) $(MAKE_OP) + +remake: + $(MAKE) $(MAKE_OP) -C $(BUILD_DIR) + +clean: + $(call_del_dir, $(BUILD_DIR)) + +distclean: + cd ../armgcc/ && $(CLEAN_SCRIPT) + +flash: $(BUILD_DIR) remake + $(call del_file,$(JLINK_SCRIPT)) + echo r > $(JLINK_SCRIPT) + echo loadbin "$(BUILD_DIR)/$(TARGET).bin" $(ADDRESS) >> $(JLINK_SCRIPT) + echo r >> $(JLINK_SCRIPT) + echo g >> $(JLINK_SCRIPT) + echo qc >> $(JLINK_SCRIPT) + $(JLINKEXE) -NoGui 1 -device $(DEVICE) -If SWD -Speed 10000 -CommanderScript $(JLINK_SCRIPT) + $(call del_file,$(JLINK_SCRIPT)) + +flash_cmsisdap: $(BUILD_DIR) remake + LinkServer flash $(LS_DEVICE) load $(BUILD_DIR)/$(TARGET).elf + +gdb_cmsisdap: $(BUILD_DIR) remake + sed "s+FILE_VALUE+$(BUILD_DIR)/$(TARGET).elf+" $(COMMON_PATH)/cmsisdap_support/gdb.commands > $(CMSIS_GDB_TEMP_FOLDER) + $(GDB) --command=$(CMSIS_GDB_TEMP_FOLDER) + +gdb: $(BUILD_DIR) remake + $(JLINK_GDB) $(DEVICE) + $(GDB) --command=$(COMMON_PATH)/debug/jlink.gdb $(BUILD_DIR)/$(TARGET).elf + +.PHONY : all remake clean dist_clean gdb diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/cmsisdap_support/MIMXRT595S.xml b/bsp/projects/common/sdk_makefile/cmsisdap_support/MIMXRT595S.xml similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/cmsisdap_support/MIMXRT595S.xml rename to bsp/projects/common/sdk_makefile/cmsisdap_support/MIMXRT595S.xml diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/cmsisdap_support/MIMXRT595S_part.xml b/bsp/projects/common/sdk_makefile/cmsisdap_support/MIMXRT595S_part.xml similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/cmsisdap_support/MIMXRT595S_part.xml rename to bsp/projects/common/sdk_makefile/cmsisdap_support/MIMXRT595S_part.xml diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/cmsisdap_support/gdb.commands b/bsp/projects/common/sdk_makefile/cmsisdap_support/gdb.commands similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/cmsisdap_support/gdb.commands rename to bsp/projects/common/sdk_makefile/cmsisdap_support/gdb.commands diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/debug/jlink.gdb b/bsp/projects/common/sdk_makefile/debug/jlink.gdb similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/debug/jlink.gdb rename to bsp/projects/common/sdk_makefile/debug/jlink.gdb diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/debug/jlink_gdb.bat b/bsp/projects/common/sdk_makefile/debug/jlink_gdb.bat similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/debug/jlink_gdb.bat rename to bsp/projects/common/sdk_makefile/debug/jlink_gdb.bat diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/debug/jlink_gdb.sh b/bsp/projects/common/sdk_makefile/debug/jlink_gdb.sh similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/debug/jlink_gdb.sh rename to bsp/projects/common/sdk_makefile/debug/jlink_gdb.sh diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/SYSVIEW_RT595.txt b/bsp/projects/microej/SYSVIEW_RT595.txt similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/SYSVIEW_RT595.txt rename to bsp/projects/microej/SYSVIEW_RT595.txt diff --git a/bsp/projects/microej/cco_freetype.properties b/bsp/projects/microej/cco_freetype.properties new file mode 100644 index 0000000..d4ac79e --- /dev/null +++ b/bsp/projects/microej/cco_freetype.properties @@ -0,0 +1,4 @@ +#Fri, 09 Sep 2022 12:50:57 +0200 + +version=2.0.2 +buildLabel=20220909-1249 diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_harfbuzz.properties b/bsp/projects/microej/cco_harfbuzz.properties similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_harfbuzz.properties rename to bsp/projects/microej/cco_harfbuzz.properties diff --git a/bsp/projects/microej/cco_microui-mimxrt595-evk.properties b/bsp/projects/microej/cco_microui-mimxrt595-evk.properties new file mode 100644 index 0000000..56c26b8 --- /dev/null +++ b/bsp/projects/microej/cco_microui-mimxrt595-evk.properties @@ -0,0 +1,4 @@ +#Mon, 17 Jul 2023 17:22:10 +0200 + +version=7.0.0 +buildLabel=20230717-1722 diff --git a/bsp/projects/microej/cco_microui-vglite.properties b/bsp/projects/microej/cco_microui-vglite.properties new file mode 100644 index 0000000..30809c1 --- /dev/null +++ b/bsp/projects/microej/cco_microui-vglite.properties @@ -0,0 +1,4 @@ +#Tue, 09 Apr 2024 10:23:57 +0200 + +version=8.0.1 +buildLabel=20240409-1023 diff --git a/bsp/projects/microej/cco_microui.properties b/bsp/projects/microej/cco_microui.properties new file mode 100644 index 0000000..0c2b83d --- /dev/null +++ b/bsp/projects/microej/cco_microui.properties @@ -0,0 +1,4 @@ +#Tue, 09 Apr 2024 10:15:03 +0200 + +version=4.0.1 +buildLabel=20240409-1015 diff --git a/bsp/projects/microej/cco_microvg-vglite.properties b/bsp/projects/microej/cco_microvg-vglite.properties new file mode 100644 index 0000000..09149be --- /dev/null +++ b/bsp/projects/microej/cco_microvg-vglite.properties @@ -0,0 +1,4 @@ +#Thu, 11 Apr 2024 11:50:50 +0200 + +version=7.0.1 +buildLabel=20240411-1150 diff --git a/bsp/projects/microej/cco_microvg.properties b/bsp/projects/microej/cco_microvg.properties new file mode 100644 index 0000000..82deef7 --- /dev/null +++ b/bsp/projects/microej/cco_microvg.properties @@ -0,0 +1,4 @@ +#Thu, 15 Feb 2024 08:27:09 +0100 + +version=5.0.0 +buildLabel=20240215-0826 diff --git a/bsp/projects/microej/gpio/inc/LLGPIO_mux.h b/bsp/projects/microej/gpio/inc/LLGPIO_mux.h new file mode 100644 index 0000000..cdf4aa8 --- /dev/null +++ b/bsp/projects/microej/gpio/inc/LLGPIO_mux.h @@ -0,0 +1,52 @@ +/** + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef LLGPIO_MUX +#define LLGPIO_MUX + +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPCTL_PIO_FUNC0 0x0000u /*!<@brief Selects pin function 0 */ +#define IOPCTL_PIO_PUPD_DI 0x0000u /*!<@brief Disable pull-up / pull-down function */ +#define IOPCTL_PIO_PUPD_EN 0x0010u /*!<@brief Enable pull-up / pull-down function */ +#define IOPCTL_PIO_PULLDOWN_EN 0x0000u /*!<@brief Enable pull-down function */ +#define IOPCTL_PIO_PULLUP_EN 0x0020u /*!<@brief Enable pull-up function */ +#define IOPCTL_PIO_INBUF_DI 0x0000u /*!<@brief Disable input buffer function */ +#define IOPCTL_PIO_INBUF_EN 0x0040u /*!<@brief Enables input buffer function */ +#define IOPCTL_PIO_SLEW_RATE_NORMAL 0x0000u /*!<@brief Normal mode */ +#define IOPCTL_PIO_SLEW_RATE_SLOW 0x0080u /*!<@brief Slow mode */ +#define IOPCTL_PIO_FULLDRIVE_DI 0x0000u /*!<@brief Normal drive */ +#define IOPCTL_PIO_FULLDRIVE_EN 0x0100u /*!<@brief Full drive enable */ +#define IOPCTL_PIO_ANAMUX_DI 0x0000u /*!<@brief Analog mux is disabled */ +#define IOPCTL_PIO_ANAMUX_EN 0x0200u /*!<@brief Analog mux is enabled */ +#define IOPCTL_PIO_PSEDRAIN_DI 0x0000u /*!<@brief Pseudo Output Drain is disabled */ +#define IOPCTL_PIO_PSEDRAIN_EN 0x0400u /*!<@brief Pseudo Output Drain is enabled */ +#define IOPCTL_PIO_INV_DI 0x0000u /*!<@brief Input function is not inverted */ +#define IOPCTL_PIO_INV_EN 0x0800u /*!<@brief Input function is inverted */ + +#define MAX_PORT_NUMBER 6 +#define GPIO_BANK_SIZE 32 +#define GPIO00 0 +#define GPIO01 1 +#define GPIO02 2 +#define GPIO03 3 +#define GPIO04 4 +#define GPIO05 5 +#define GPIO06 6 +#define GPIO06_MAX_PIN 27 + +typedef enum +{ + kSuccess = 0, + kPortError = -1, + kPinError = -2, +} gpio_init_status; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/projects/microej/gpio/nxp_gpio.cmake b/bsp/projects/microej/gpio/nxp_gpio.cmake new file mode 100644 index 0000000..ded8786 --- /dev/null +++ b/bsp/projects/microej/gpio/nxp_gpio.cmake @@ -0,0 +1,8 @@ +include_guard() +message("nxp/gpio component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/src/LLGPIO_impl.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE ${CMAKE_CURRENT_LIST_DIR}/inc) diff --git a/bsp/projects/microej/gpio/src/LLGPIO_impl.c b/bsp/projects/microej/gpio/src/LLGPIO_impl.c new file mode 100644 index 0000000..97dd196 --- /dev/null +++ b/bsp/projects/microej/gpio/src/LLGPIO_impl.c @@ -0,0 +1,143 @@ +/** + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file + * @brief NXP GPIO low level API + * @author Julien Jouan + * @version 1.0.0 + */ + +#include +#include "LLGPIO_mux.h" +#include "sni.h" +#include "fsl_iopctl.h" +#include "board.h" + +static int8_t check_port_and_pin(uint32_t port, uint32_t pin) +{ + int8_t ret = kPinError; + + switch (port) + { + case GPIO00: + case GPIO01: + case GPIO02: + case GPIO03: + case GPIO04: + case GPIO05: + ret = kSuccess; + break; + case GPIO06: + if (pin <= GPIO06_MAX_PIN) ret = kSuccess; + break; + default: + ret = kPortError; + break; + } + return ret; +} + +int32_t LLGPIO_IMPL_init_gpio_pin(uint32_t pin, uint32_t direction, uint32_t pullConfig) +{ + uint32_t port = pin / GPIO_BANK_SIZE; + pin %= GPIO_BANK_SIZE; + gpio_pin_config_t sw_config = {(gpio_pin_direction_t)direction, 0}; + + /* Check that GPIO port and pin used is existing */ + int8_t portPinStatus = check_port_and_pin(port, pin); + if (portPinStatus == kSuccess) + { + const uint32_t portx_piny_config = (/* Pin is configured as PIO{port}_{pin} */ + IOPCTL_PIO_FUNC0 | + /* Disable pull-up / pull-down function */ + ((pullConfig > 0) ? IOPCTL_PIO_PUPD_EN : IOPCTL_PIO_PUPD_DI) | + /* Enable pull-up/down function */ + ((pullConfig == 1) ? IOPCTL_PIO_PULLUP_EN : IOPCTL_PIO_PULLDOWN_EN) | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + IOPCTL_PinMuxSet(IOPCTL, port, pin, portx_piny_config); + + GPIO_PortInit_noreset(GPIO, port); + GPIO_PinInit(GPIO, port, pin, &sw_config); + } + return portPinStatus; +} + +int32_t LLGPIO_IMPL_read_gpio_pin(uint32_t pin) +{ + uint32_t port = pin / GPIO_BANK_SIZE; + pin %= GPIO_BANK_SIZE; + + /* Check that GPIO port and pin used is existing */ + int8_t portPinStatus = check_port_and_pin(port, pin); + int8_t ret; + + if (portPinStatus == kSuccess) + { + ret = GPIO_PinRead(GPIO, port, pin); + } + else + { + ret = portPinStatus; + } + + return ret; +} + +int32_t LLGPIO_IMPL_write_gpio_pin(uint32_t pin, uint32_t level) +{ + uint32_t port = pin / GPIO_BANK_SIZE; + pin %= GPIO_BANK_SIZE; + + /* Check that GPIO port and pin used is existing */ + int8_t portPinStatus = check_port_and_pin(port, pin); + int8_t ret; + + if (portPinStatus == kSuccess) + { + GPIO_PinWrite(GPIO, port, pin, level); + ret = GPIO_PinRead(GPIO, port, pin); + } + else + { + ret = portPinStatus; + } + + return ret; +} + +int32_t LLGPIO_IMPL_toggle_gpio_pin(uint32_t pin) +{ + uint32_t port = pin / GPIO_BANK_SIZE; + pin %= GPIO_BANK_SIZE; + + /* Check that GPIO port and pin used is existing */ + int8_t portPinStatus = check_port_and_pin(port, pin); + int8_t ret; + + if (portPinStatus == kSuccess) + { + GPIO_PortToggle(GPIO, port, (uint32_t) (1 << pin)); + ret = GPIO_PinRead(GPIO, port, pin); + } + else + { + ret = portPinStatus; + } + + return ret; +} diff --git a/bsp/projects/microej/kf/inc/LLKERNEL_impl.h b/bsp/projects/microej/kf/inc/LLKERNEL_impl.h new file mode 100644 index 0000000..6f2ccd7 --- /dev/null +++ b/bsp/projects/microej/kf/inc/LLKERNEL_impl.h @@ -0,0 +1,40 @@ +/* + * C + * + * Copyright 2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#include +#include + +#ifndef LLKERNEL_IMPL +#define LLKERNEL_IMPL + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t LLKERNEL_IMPL_allocateFeature(int32_t size_ROM, int32_t size_RAM); + +void LLKERNEL_IMPL_freeFeature(int32_t handle); + +int32_t LLKERNEL_IMPL_getAllocatedFeaturesCount(void); + +int32_t LLKERNEL_IMPL_getFeatureHandle(int32_t allocation_index); + +void* LLKERNEL_IMPL_getFeatureAddressRAM(int32_t handle); + +void* LLKERNEL_IMPL_getFeatureAddressROM(int32_t handle); + +int32_t LLKERNEL_IMPL_copyToROM(void* dest_address_ROM, void* src_address, int32_t size); + +int32_t LLKERNEL_IMPL_flushCopyToROM(void); + +int32_t LLKERNEL_IMPL_onFeatureInitializationError(int32_t handle, int32_t error_code); + +#ifdef __cplusplus +} +#endif + +#endif /* LLKERNEL_IMPL */ diff --git a/bsp/projects/microej/kf/src/LLKERNEL_impl.c b/bsp/projects/microej/kf/src/LLKERNEL_impl.c new file mode 100644 index 0000000..e2907a8 --- /dev/null +++ b/bsp/projects/microej/kf/src/LLKERNEL_impl.c @@ -0,0 +1,83 @@ +/* + * C + * + * Copyright 2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#include +#include + +#include "LLKERNEL_impl.h" + +// Your implementation of malloc() +#define KERNEL_MALLOC(size) malloc((size_t)(size)) + +// Your implementation of free() +#define KERNEL_FREE(addr) free((void*)(addr)) + +// Your implementation of 'ASSERT(0)' +#define KERNEL_ASSERT_FAIL() while(1) + +// Utility macros for allocating RAM and ROM areas with required alignment constraints +#define KERNEL_AREA_GET_MAX_SIZE(size, alignment) ((size)+((alignment)-1)) +#define KERNEL_AREA_GET_START_ADDRESS(addr, alignment) ((void*)((((int32_t)(addr))+(alignment)-1)&~((alignment)-1))) + +typedef struct installed_feature{ + void* ROM_area; + void* RAM_area; +} installed_feature_t; + +int32_t LLKERNEL_IMPL_allocateFeature(int32_t size_ROM, int32_t size_RAM) { + int32_t ret = 0; + int total_size = sizeof(installed_feature_t); + total_size += KERNEL_AREA_GET_MAX_SIZE(size_ROM, LLKERNEL_ROM_AREA_ALIGNMENT); + total_size += KERNEL_AREA_GET_MAX_SIZE(size_RAM, LLKERNEL_RAM_AREA_ALIGNMENT); + + void* total_area = KERNEL_MALLOC(total_size); + if(NULL != total_area){ + installed_feature_t* f = (installed_feature_t*)total_area; + f->ROM_area = KERNEL_AREA_GET_START_ADDRESS((void*)(((int32_t)f)+((int32_t)sizeof(installed_feature_t))), LLKERNEL_ROM_AREA_ALIGNMENT); + f->RAM_area = KERNEL_AREA_GET_START_ADDRESS((void*)(((int32_t)f->ROM_area)+size_ROM), LLKERNEL_RAM_AREA_ALIGNMENT); + ret = (int32_t)f; + } // else out of memory + + return ret; +} + +void LLKERNEL_IMPL_freeFeature(int32_t handle) { + KERNEL_FREE(handle); +} + +int32_t LLKERNEL_IMPL_getAllocatedFeaturesCount(void) { + // No persistency support + return 0; +} + +int32_t LLKERNEL_IMPL_getFeatureHandle(int32_t allocation_index) { + // No persistency support + KERNEL_ASSERT_FAIL(); +} + +void* LLKERNEL_IMPL_getFeatureAddressRAM(int32_t handle) { + return ((installed_feature_t*)handle)->RAM_area; +} + +void* LLKERNEL_IMPL_getFeatureAddressROM(int32_t handle) { + return ((installed_feature_t*)handle)->ROM_area; +} + +int32_t LLKERNEL_IMPL_copyToROM(void* dest_address_ROM, void* src_address, int32_t size) { + memcpy(dest_address_ROM, src_address, size); + return LLKERNEL_OK; +} + +int32_t LLKERNEL_IMPL_flushCopyToROM(void) { + return LLKERNEL_OK; +} + +int32_t LLKERNEL_IMPL_onFeatureInitializationError(int32_t handle, int32_t error_code) { + // No persistency support + KERNEL_ASSERT_FAIL(); + return 0; +} diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/lowpower/.gh-copyright.template b/bsp/projects/microej/lowpower/.gh-copyright.template similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/lowpower/.gh-copyright.template rename to bsp/projects/microej/lowpower/.gh-copyright.template diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/lowpower/inc/fsl_tickless_rtc.h b/bsp/projects/microej/lowpower/inc/fsl_tickless_rtc.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/lowpower/inc/fsl_tickless_rtc.h rename to bsp/projects/microej/lowpower/inc/fsl_tickless_rtc.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/lowpower/inc/power_manager.h b/bsp/projects/microej/lowpower/inc/power_manager.h similarity index 94% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/lowpower/inc/power_manager.h rename to bsp/projects/microej/lowpower/inc/power_manager.h index 9730efe..d2db76e 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/lowpower/inc/power_manager.h +++ b/bsp/projects/microej/lowpower/inc/power_manager.h @@ -1,5 +1,5 @@ /* - * Copyright 2020, 2022 NXP + * Copyright 2020, 2022, 2024 NXP * * SPDX-License-Identifier: BSD-3-Clause * @@ -14,7 +14,6 @@ void power_manager_init(void); void GPIO_WakeUp_Enable(void); void GPIO_WakeUp_Disable(void); -static void GPIO_WakeUp_Power_Enable_Update(void); typedef enum { POWER_GLOBAL = 0, diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/lowpower/src/fsl_tickless_rtc.c b/bsp/projects/microej/lowpower/src/fsl_tickless_rtc.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/lowpower/src/fsl_tickless_rtc.c rename to bsp/projects/microej/lowpower/src/fsl_tickless_rtc.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/lowpower/src/power_manager.c b/bsp/projects/microej/lowpower/src/power_manager.c similarity index 98% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/lowpower/src/power_manager.c rename to bsp/projects/microej/lowpower/src/power_manager.c index bfd8ea1..07136b6 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/lowpower/src/power_manager.c +++ b/bsp/projects/microej/lowpower/src/power_manager.c @@ -1,5 +1,5 @@ /* - * Copyright 2020 NXP + * Copyright 2020, 2024 NXP * * SPDX-License-Identifier: BSD-3-Clause * @@ -83,6 +83,8 @@ static uint32_t used_ram_mask = 0; /* Keep track of the framebuffer that is currently transmitted to Display */ static framebuffer_t *framebuffer_to_power_off_address = NULL; +static void GPIO_WakeUp_Power_Enable_Update(void); + /* * Some GPIO pins can be configured to wake up the device from deepsleep mode. * Once the device has been waked up by a GPIO pin event, entering in deepsleep @@ -286,14 +288,10 @@ static void set_active_power_config(void) /* PowerDown clock, RAM, and access to unused peripherals */ CLOCK_AttachClk(kNONE_to_SDIO0_CLK); - POWER_EnablePD(kPDRUNCFG_LP_HSPAD_SDIO0_VDET); - POWER_EnablePD(kPDRUNCFG_PD_HSPAD_SDIO0_REF); POWER_EnablePD(kPDRUNCFG_APD_USDHC0_SRAM); POWER_EnablePD(kPDRUNCFG_PPD_USDHC0_SRAM); /* SDIO1 */ CLOCK_AttachClk(kNONE_to_SDIO1_CLK); - POWER_EnablePD(kPDRUNCFG_LP_HSPAD_SDIO1_VDET); - POWER_EnablePD(kPDRUNCFG_PD_HSPAD_SDIO1_REF); POWER_EnablePD(kPDRUNCFG_APD_USDHC1_SRAM); POWER_EnablePD(kPDRUNCFG_PPD_USDHC1_SRAM); /* CASPER */ @@ -552,7 +550,7 @@ int32_t power_manager_set_profile(uint32_t power_profile) SystemCoreClock = CLOCK_GetFreq(kCLOCK_CoreSysClk); current_power_profile = power_profile; -#if (ENABLE_SVIEW == 1) +#if (ENABLE_SYSTEM_VIEW == 1) SEGGER_SYSVIEW_UpdateTimeStampMultiplier(SystemCoreClock); #endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/microej_freertos.xml b/bsp/projects/microej/microej_freertos.xml similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/microej_freertos.xml rename to bsp/projects/microej/microej_freertos.xml diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/osal/inc/osal.h b/bsp/projects/microej/osal/inc/osal.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/osal/inc/osal.h rename to bsp/projects/microej/osal/inc/osal.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/osal/inc/osal_portmacro.h b/bsp/projects/microej/osal/inc/osal_portmacro.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/osal/inc/osal_portmacro.h rename to bsp/projects/microej/osal/inc/osal_portmacro.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/osal/src/osal_FreeRTOS.c b/bsp/projects/microej/osal/src/osal_FreeRTOS.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/osal/src/osal_FreeRTOS.c rename to bsp/projects/microej/osal/src/osal_FreeRTOS.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/.gitignore b/bsp/projects/microej/scripts/.gitignore similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/.gitignore rename to bsp/projects/microej/scripts/.gitignore diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/Jlink.cmd b/bsp/projects/microej/scripts/Jlink.cmd similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/Jlink.cmd rename to bsp/projects/microej/scripts/Jlink.cmd diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/build.bat b/bsp/projects/microej/scripts/build.bat similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/build.bat rename to bsp/projects/microej/scripts/build.bat diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/build.sh b/bsp/projects/microej/scripts/build.sh similarity index 79% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/build.sh rename to bsp/projects/microej/scripts/build.sh index db4037f..c473a04 100755 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/build.sh +++ b/bsp/projects/microej/scripts/build.sh @@ -6,6 +6,9 @@ CURRENT_DIRECTORY=$(pwd) SCRIPT_DIR=$(dirname "$(realpath "$0")") cd "$SCRIPT_DIR/../../nxpvee-ui/sdk_makefile" || exit 1 +# shell scripts may have lost their execution flag if they come from a zip +chmod -f +x $SCRIPT_DIR/../../nxpvee-ui/armgcc/*.sh || true + make RELEASE=1 || exit 2 cp ../armgcc/release/mimxrt595_freertos-bsp.elf "$CURRENT_DIRECTORY"/application.out || exit 3 diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/run.bat b/bsp/projects/microej/scripts/run.bat similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/run.bat rename to bsp/projects/microej/scripts/run.bat diff --git a/bsp/projects/microej/scripts/run.sh b/bsp/projects/microej/scripts/run.sh new file mode 100755 index 0000000..89d7481 --- /dev/null +++ b/bsp/projects/microej/scripts/run.sh @@ -0,0 +1,15 @@ +#!/bin/sh + +set -e +CURRENT_DIRECTORY=$(pwd) + +# go to directory of script's location +SCRIPT_DIR=$(dirname "$(realpath "$0")") +cd "${SCRIPT_DIR}/../../nxpvee-ui/sdk_makefile/" + +# shell scripts may have lost their execution flag is they come from a zip +chmod -f +x $SCRIPT_DIR/../../nxpvee-ui/armgcc/*.sh || true + +make RELEASE=1 flash_cmsisdap + +cd "$CURRENT_DIRECTORY" diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/segger/inc/SEGGER_RTT_Conf.h b/bsp/projects/microej/segger/inc/SEGGER_RTT_Conf.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/segger/inc/SEGGER_RTT_Conf.h rename to bsp/projects/microej/segger/inc/SEGGER_RTT_Conf.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/stub/src/stub.c b/bsp/projects/microej/stub/src/stub.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/stub/src/stub.c rename to bsp/projects/microej/stub/src/stub.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/CHANGES b/bsp/projects/microej/thirdparty/freetype/CHANGES similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/CHANGES rename to bsp/projects/microej/thirdparty/freetype/CHANGES diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/FTL.TXT b/bsp/projects/microej/thirdparty/freetype/FTL.TXT similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/FTL.TXT rename to bsp/projects/microej/thirdparty/freetype/FTL.TXT diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/GPLv2.TXT b/bsp/projects/microej/thirdparty/freetype/GPLv2.TXT similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/GPLv2.TXT rename to bsp/projects/microej/thirdparty/freetype/GPLv2.TXT diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/LICENSE.TXT b/bsp/projects/microej/thirdparty/freetype/LICENSE.TXT similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/LICENSE.TXT rename to bsp/projects/microej/thirdparty/freetype/LICENSE.TXT diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afblue.h b/bsp/projects/microej/thirdparty/freetype/inc/afblue.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afblue.h rename to bsp/projects/microej/thirdparty/freetype/inc/afblue.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afcjk.h b/bsp/projects/microej/thirdparty/freetype/inc/afcjk.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afcjk.h rename to bsp/projects/microej/thirdparty/freetype/inc/afcjk.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afcover.h b/bsp/projects/microej/thirdparty/freetype/inc/afcover.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afcover.h rename to bsp/projects/microej/thirdparty/freetype/inc/afcover.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afdummy.h b/bsp/projects/microej/thirdparty/freetype/inc/afdummy.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afdummy.h rename to bsp/projects/microej/thirdparty/freetype/inc/afdummy.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/aferrors.h b/bsp/projects/microej/thirdparty/freetype/inc/aferrors.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/aferrors.h rename to bsp/projects/microej/thirdparty/freetype/inc/aferrors.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afglobal.h b/bsp/projects/microej/thirdparty/freetype/inc/afglobal.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afglobal.h rename to bsp/projects/microej/thirdparty/freetype/inc/afglobal.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afhints.h b/bsp/projects/microej/thirdparty/freetype/inc/afhints.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afhints.h rename to bsp/projects/microej/thirdparty/freetype/inc/afhints.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afindic.h b/bsp/projects/microej/thirdparty/freetype/inc/afindic.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afindic.h rename to bsp/projects/microej/thirdparty/freetype/inc/afindic.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/aflatin.h b/bsp/projects/microej/thirdparty/freetype/inc/aflatin.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/aflatin.h rename to bsp/projects/microej/thirdparty/freetype/inc/aflatin.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afloader.h b/bsp/projects/microej/thirdparty/freetype/inc/afloader.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afloader.h rename to bsp/projects/microej/thirdparty/freetype/inc/afloader.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afmodule.h b/bsp/projects/microej/thirdparty/freetype/inc/afmodule.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afmodule.h rename to bsp/projects/microej/thirdparty/freetype/inc/afmodule.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afmparse.h b/bsp/projects/microej/thirdparty/freetype/inc/afmparse.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afmparse.h rename to bsp/projects/microej/thirdparty/freetype/inc/afmparse.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afranges.h b/bsp/projects/microej/thirdparty/freetype/inc/afranges.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afranges.h rename to bsp/projects/microej/thirdparty/freetype/inc/afranges.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afscript.h b/bsp/projects/microej/thirdparty/freetype/inc/afscript.h similarity index 86% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afscript.h rename to bsp/projects/microej/thirdparty/freetype/inc/afscript.h index f8c8cf1..95a81bf 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afscript.h +++ b/bsp/projects/microej/thirdparty/freetype/inc/afscript.h @@ -46,19 +46,19 @@ "Armenian", HB_SCRIPT_ARMENIAN, HINTING_BOTTOM_TO_TOP, - "\xD5\xBD \xD5\x8D" ) /* ս �? */ + "\xD5\xBD \xD5\x8D" ) /* ս �? */ SCRIPT( avst, AVST, "Avestan", HB_SCRIPT_AVESTAN, HINTING_BOTTOM_TO_TOP, - "\xF0\x90\xAC\x9A" ) /* �?�� */ + "\xF0\x90\xAC\x9A" ) /* �?�� */ SCRIPT( bamu, BAMU, "Bamum", HB_SCRIPT_BAMUM, HINTING_BOTTOM_TO_TOP, - "\xEA\x9B\x81 \xEA\x9B\xAF" ) /* �? ꛯ */ + "\xEA\x9B\x81 \xEA\x9B\xAF" ) /* �? ꛯ */ /* there are no simple forms for letters; we thus use two digit shapes */ SCRIPT( beng, BENG, @@ -71,7 +71,7 @@ "Buhid", HB_SCRIPT_BUHID, HINTING_BOTTOM_TO_TOP, - "\xE1\x9D\x8B \xE1\x9D\x8F" ) /* �?� �?? */ + "\xE1\x9D\x8B \xE1\x9D\x8F" ) /* �?� �?? */ SCRIPT( cakm, CAKM, "Chakma", @@ -89,13 +89,13 @@ "Carian", HB_SCRIPT_CARIAN, HINTING_BOTTOM_TO_TOP, - "\xF0\x90\x8A\xAB \xF0\x90\x8B\x89" ) /* �?�� �?�� */ + "\xF0\x90\x8A\xAB \xF0\x90\x8B\x89" ) /* �?�� �?�� */ SCRIPT( cher, CHER, "Cherokee", HB_SCRIPT_CHEROKEE, HINTING_BOTTOM_TO_TOP, - "\xE1\x8E\xA4 \xE1\x8F\x85 \xEA\xAE\x95" ) /* Ꭴ �?� ꮕ */ + "\xE1\x8E\xA4 \xE1\x8F\x85 \xEA\xAE\x95" ) /* Ꭴ �?� ꮕ */ SCRIPT( copt, COPT, "Coptic", @@ -107,7 +107,7 @@ "Cypriot", HB_SCRIPT_CYPRIOT, HINTING_BOTTOM_TO_TOP, - "\xF0\x90\xA0\x85 \xF0\x90\xA0\xA3" ) /* �?�� �?�� */ + "\xF0\x90\xA0\x85 \xF0\x90\xA0\xA3" ) /* �?�� �?�� */ SCRIPT( cyrl, CYRL, "Cyrillic", @@ -125,19 +125,19 @@ "Deseret", HB_SCRIPT_DESERET, HINTING_BOTTOM_TO_TOP, - "\xF0\x90\x90\x84 \xF0\x90\x90\xAC" ) /* �??� �??� */ + "\xF0\x90\x90\x84 \xF0\x90\x90\xAC" ) /* �??� �??� */ SCRIPT( ethi, ETHI, "Ethiopic", HB_SCRIPT_ETHIOPIC, HINTING_BOTTOM_TO_TOP, - "\xE1\x8B\x90" ) /* �? */ + "\xE1\x8B\x90" ) /* �? */ SCRIPT( geor, GEOR, "Georgian (Mkhedruli)", HB_SCRIPT_GEORGIAN, HINTING_BOTTOM_TO_TOP, - "\xE1\x83\x98 \xE1\x83\x94 \xE1\x83\x90 \xE1\xB2\xBF" ) /* ი ე �? Ი */ + "\xE1\x83\x98 \xE1\x83\x94 \xE1\x83\x90 \xE1\xB2\xBF" ) /* ი ე �? Ი */ SCRIPT( geok, GEOK, "Georgian (Khutsuri)", @@ -155,7 +155,7 @@ "Gothic", HB_SCRIPT_GOTHIC, HINTING_TOP_TO_BOTTOM, - "\xF0\x90\x8C\xB4 \xF0\x90\x8C\xBE \xF0\x90\x8D\x83" ) /* �?�� �?�� �??� */ + "\xF0\x90\x8C\xB4 \xF0\x90\x8C\xBE \xF0\x90\x8D\x83" ) /* �?�� �?�� �??� */ SCRIPT( grek, GREK, "Greek", @@ -179,13 +179,13 @@ "Hebrew", HB_SCRIPT_HEBREW, HINTING_BOTTOM_TO_TOP, - "\xD7\x9D" ) /* �? */ + "\xD7\x9D" ) /* �? */ SCRIPT( kali, KALI, "Kayah Li", HB_SCRIPT_KAYAH_LI, HINTING_BOTTOM_TO_TOP, - "\xEA\xA4\x8D \xEA\xA4\x80" ) /* �? ꤀ */ + "\xEA\xA4\x8D \xEA\xA4\x80" ) /* �? ꤀ */ /* only digit zero has a simple shape in the Khmer script */ SCRIPT( khmr, KHMR, @@ -211,7 +211,7 @@ "Lao", HB_SCRIPT_LAO, HINTING_BOTTOM_TO_TOP, - "\xE0\xBB\x90" ) /* �? */ + "\xE0\xBB\x90" ) /* �? */ SCRIPT( latn, LATN, "Latin", @@ -229,7 +229,7 @@ "Latin Superscript Fallback", HB_SCRIPT_INVALID, HINTING_BOTTOM_TO_TOP, - "\xE1\xB5\x92 \xE1\xB4\xBC \xE2\x81\xB0" ) /* ᵒ ᴼ �?� */ + "\xE1\xB5\x92 \xE1\xB4\xBC \xE2\x81\xB0" ) /* ᵒ ᴼ �?� */ SCRIPT( lisu, LISU, "Lisu", @@ -259,7 +259,7 @@ "Myanmar", HB_SCRIPT_MYANMAR, HINTING_BOTTOM_TO_TOP, - "\xE1\x80\x9D \xE1\x80\x84 \xE1\x80\x82" ) /* �? င ဂ */ + "\xE1\x80\x9D \xE1\x80\x84 \xE1\x80\x82" ) /* �? င ဂ */ SCRIPT( nkoo, NKOO, "N'Ko", @@ -283,37 +283,37 @@ "Old Turkic", HB_SCRIPT_OLD_TURKIC, HINTING_BOTTOM_TO_TOP, - "\xF0\x90\xB0\x97" ) /* �?�� */ + "\xF0\x90\xB0\x97" ) /* �?�� */ SCRIPT( osge, OSGE, "Osage", HB_SCRIPT_OSAGE, HINTING_BOTTOM_TO_TOP, - "\xF0\x90\x93\x82 \xF0\x90\x93\xAA" ) /* �?�� �?�� */ + "\xF0\x90\x93\x82 \xF0\x90\x93\xAA" ) /* �?�� �?�� */ SCRIPT( osma, OSMA, "Osmanya", HB_SCRIPT_OSMANYA, HINTING_BOTTOM_TO_TOP, - "\xF0\x90\x92\x86 \xF0\x90\x92\xA0" ) /* �?�� �?�� */ + "\xF0\x90\x92\x86 \xF0\x90\x92\xA0" ) /* �?�� �?�� */ SCRIPT( rohg, ROHG, "Hanifi Rohingya", HB_SCRIPT_HANIFI_ROHINGYA, HINTING_BOTTOM_TO_TOP, - "\xF0\x90\xB4\xB0" ) /* �?�� */ + "\xF0\x90\xB4\xB0" ) /* �?�� */ SCRIPT( saur, SAUR, "Saurashtra", HB_SCRIPT_SAURASHTRA, HINTING_BOTTOM_TO_TOP, - "\xEA\xA2\x9D \xEA\xA3\x90" ) /* �? �? */ + "\xEA\xA2\x9D \xEA\xA3\x90" ) /* �? �? */ SCRIPT( shaw, SHAW, "Shavian", HB_SCRIPT_SHAVIAN, HINTING_BOTTOM_TO_TOP, - "\xF0\x90\x91\xB4" ) /* �?�� */ + "\xF0\x90\x91\xB4" ) /* �?�� */ SCRIPT( sinh, SINH, "Sinhala", @@ -358,7 +358,7 @@ "Thai", HB_SCRIPT_THAI, HINTING_BOTTOM_TO_TOP, - "\xE0\xB8\xB2 \xE0\xB9\x85 \xE0\xB9\x90" ) /* า ๅ �? */ + "\xE0\xB8\xB2 \xE0\xB9\x85 \xE0\xB9\x90" ) /* า ๅ �? */ SCRIPT( vaii, VAII, "Vai", diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afshaper.h b/bsp/projects/microej/thirdparty/freetype/inc/afshaper.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afshaper.h rename to bsp/projects/microej/thirdparty/freetype/inc/afshaper.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afstyles.h b/bsp/projects/microej/thirdparty/freetype/inc/afstyles.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afstyles.h rename to bsp/projects/microej/thirdparty/freetype/inc/afstyles.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/aftypes.h b/bsp/projects/microej/thirdparty/freetype/inc/aftypes.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/aftypes.h rename to bsp/projects/microej/thirdparty/freetype/inc/aftypes.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afwrtsys.h b/bsp/projects/microej/thirdparty/freetype/inc/afwrtsys.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/afwrtsys.h rename to bsp/projects/microej/thirdparty/freetype/inc/afwrtsys.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/bdf.h b/bsp/projects/microej/thirdparty/freetype/inc/bdf.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/bdf.h rename to bsp/projects/microej/thirdparty/freetype/inc/bdf.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/bdfdrivr.h b/bsp/projects/microej/thirdparty/freetype/inc/bdfdrivr.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/bdfdrivr.h rename to bsp/projects/microej/thirdparty/freetype/inc/bdfdrivr.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/bdferror.h b/bsp/projects/microej/thirdparty/freetype/inc/bdferror.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/bdferror.h rename to bsp/projects/microej/thirdparty/freetype/inc/bdferror.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffcmap.h b/bsp/projects/microej/thirdparty/freetype/inc/cffcmap.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffcmap.h rename to bsp/projects/microej/thirdparty/freetype/inc/cffcmap.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffdecode.h b/bsp/projects/microej/thirdparty/freetype/inc/cffdecode.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffdecode.h rename to bsp/projects/microej/thirdparty/freetype/inc/cffdecode.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffdrivr.h b/bsp/projects/microej/thirdparty/freetype/inc/cffdrivr.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffdrivr.h rename to bsp/projects/microej/thirdparty/freetype/inc/cffdrivr.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cfferrs.h b/bsp/projects/microej/thirdparty/freetype/inc/cfferrs.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cfferrs.h rename to bsp/projects/microej/thirdparty/freetype/inc/cfferrs.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffgload.h b/bsp/projects/microej/thirdparty/freetype/inc/cffgload.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffgload.h rename to bsp/projects/microej/thirdparty/freetype/inc/cffgload.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffload.h b/bsp/projects/microej/thirdparty/freetype/inc/cffload.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffload.h rename to bsp/projects/microej/thirdparty/freetype/inc/cffload.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffobjs.h b/bsp/projects/microej/thirdparty/freetype/inc/cffobjs.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffobjs.h rename to bsp/projects/microej/thirdparty/freetype/inc/cffobjs.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffparse.h b/bsp/projects/microej/thirdparty/freetype/inc/cffparse.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cffparse.h rename to bsp/projects/microej/thirdparty/freetype/inc/cffparse.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cfftoken.h b/bsp/projects/microej/thirdparty/freetype/inc/cfftoken.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cfftoken.h rename to bsp/projects/microej/thirdparty/freetype/inc/cfftoken.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ciderrs.h b/bsp/projects/microej/thirdparty/freetype/inc/ciderrs.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ciderrs.h rename to bsp/projects/microej/thirdparty/freetype/inc/ciderrs.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cidgload.h b/bsp/projects/microej/thirdparty/freetype/inc/cidgload.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cidgload.h rename to bsp/projects/microej/thirdparty/freetype/inc/cidgload.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cidload.h b/bsp/projects/microej/thirdparty/freetype/inc/cidload.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cidload.h rename to bsp/projects/microej/thirdparty/freetype/inc/cidload.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cidobjs.h b/bsp/projects/microej/thirdparty/freetype/inc/cidobjs.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cidobjs.h rename to bsp/projects/microej/thirdparty/freetype/inc/cidobjs.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cidparse.h b/bsp/projects/microej/thirdparty/freetype/inc/cidparse.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cidparse.h rename to bsp/projects/microej/thirdparty/freetype/inc/cidparse.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cidriver.h b/bsp/projects/microej/thirdparty/freetype/inc/cidriver.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cidriver.h rename to bsp/projects/microej/thirdparty/freetype/inc/cidriver.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cidtoken.h b/bsp/projects/microej/thirdparty/freetype/inc/cidtoken.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/cidtoken.h rename to bsp/projects/microej/thirdparty/freetype/inc/cidtoken.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/fnterrs.h b/bsp/projects/microej/thirdparty/freetype/inc/fnterrs.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/fnterrs.h rename to bsp/projects/microej/thirdparty/freetype/inc/fnterrs.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftconfig.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftconfig.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftconfig.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftconfig.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftheader.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftheader.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftheader.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftheader.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftmodule.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftmodule.h similarity index 91% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftmodule.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftmodule.h index 847e090..38e3233 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftmodule.h +++ b/bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftmodule.h @@ -8,7 +8,7 @@ * Please read `docs/INSTALL.ANY` and `docs/CUSTOMIZE` how to compile * FreeType without GNU make. * - * Copyright 2019-2022 MicroEJ Corp. This file has been modified by MicroEJ Corp. + * Copyright 2021-2022 MicroEJ Corp. This file has been modified and/or created by MicroEJ Corp. */ #include "microvg_configuration.h" diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftoption.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftoption.h similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftoption.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftoption.h index a04565f..b4e1824 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftoption.h +++ b/bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftoption.h @@ -7,13 +7,14 @@ * Copyright (C) 1996-2021 by * David Turner, Robert Wilhelm, and Werner Lemberg. * + * Copyright 2021-2022 MicroEJ Corp. This file has been modified and/or created by MicroEJ Corp. + * * This file is part of the FreeType project, and may only be used, * modified, and distributed under the terms of the FreeType project * license, LICENSE.TXT. By continuing to use, modify, or distribute * this file you indicate that you have read the license and * understand and accept it fully. * - * Copyright 2019-2022 MicroEJ Corp. This file has been modified by MicroEJ Corp. */ #ifndef FTOPTION_H_ diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftstdlib.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftstdlib.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftstdlib.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/config/ftstdlib.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/integer-types.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/config/integer-types.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/integer-types.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/config/integer-types.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/mac-support.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/config/mac-support.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/mac-support.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/config/mac-support.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/public-macros.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/config/public-macros.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/config/public-macros.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/config/public-macros.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/freetype.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/freetype.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/freetype.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/freetype.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftadvanc.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/ftadvanc.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftadvanc.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/ftadvanc.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbbox.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbbox.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbbox.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbbox.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbdf.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbdf.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbdf.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbdf.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbitmap.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbitmap.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbitmap.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbitmap.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbzip2.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbzip2.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbzip2.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/ftbzip2.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftcache.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/ftcache.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftcache.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/ftcache.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftchapters.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/ftchapters.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftchapters.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/ftchapters.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftcid.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/ftcid.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftcid.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/ftcid.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftcolor.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/ftcolor.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftcolor.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/ftcolor.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftdriver.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/ftdriver.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftdriver.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/ftdriver.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/fterrdef.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/fterrdef.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/fterrdef.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/fterrdef.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/fterrors.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/fterrors.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/fterrors.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/fterrors.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftfntfmt.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/ftfntfmt.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftfntfmt.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/ftfntfmt.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftgasp.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/ftgasp.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftgasp.h rename to bsp/projects/microej/thirdparty/freetype/inc/freetype/ftgasp.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/freetype/ftglyph.h b/bsp/projects/microej/thirdparty/freetype/inc/freetype/ftglyph.h similarity index 100% rename from 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a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftccback.h b/bsp/projects/microej/thirdparty/freetype/inc/ftccback.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftccback.h rename to bsp/projects/microej/thirdparty/freetype/inc/ftccback.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftcerror.h b/bsp/projects/microej/thirdparty/freetype/inc/ftcerror.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftcerror.h rename to bsp/projects/microej/thirdparty/freetype/inc/ftcerror.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftcglyph.h b/bsp/projects/microej/thirdparty/freetype/inc/ftcglyph.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftcglyph.h rename to bsp/projects/microej/thirdparty/freetype/inc/ftcglyph.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftcimage.h b/bsp/projects/microej/thirdparty/freetype/inc/ftcimage.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftcimage.h rename to bsp/projects/microej/thirdparty/freetype/inc/ftcimage.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftcmanag.h b/bsp/projects/microej/thirdparty/freetype/inc/ftcmanag.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftcmanag.h rename to bsp/projects/microej/thirdparty/freetype/inc/ftcmanag.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftcmru.h b/bsp/projects/microej/thirdparty/freetype/inc/ftcmru.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftcmru.h rename to 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bsp/projects/microej/thirdparty/freetype/inc/ftsdf.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftsdfcommon.h b/bsp/projects/microej/thirdparty/freetype/inc/ftsdfcommon.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftsdfcommon.h rename to bsp/projects/microej/thirdparty/freetype/inc/ftsdfcommon.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftsdferrs.h b/bsp/projects/microej/thirdparty/freetype/inc/ftsdferrs.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftsdferrs.h rename to bsp/projects/microej/thirdparty/freetype/inc/ftsdferrs.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftsdfrend.h b/bsp/projects/microej/thirdparty/freetype/inc/ftsdfrend.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftsdfrend.h rename to bsp/projects/microej/thirdparty/freetype/inc/ftsdfrend.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftsmerrs.h b/bsp/projects/microej/thirdparty/freetype/inc/ftsmerrs.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftsmerrs.h rename to bsp/projects/microej/thirdparty/freetype/inc/ftsmerrs.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftsmooth.h b/bsp/projects/microej/thirdparty/freetype/inc/ftsmooth.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftsmooth.h rename to bsp/projects/microej/thirdparty/freetype/inc/ftsmooth.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftvector/ftvector.h b/bsp/projects/microej/thirdparty/freetype/inc/ftvector/ftvector.h similarity index 78% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftvector/ftvector.h rename to bsp/projects/microej/thirdparty/freetype/inc/ftvector/ftvector.h index 8babe90..ecd4a54 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftvector/ftvector.h +++ b/bsp/projects/microej/thirdparty/freetype/inc/ftvector/ftvector.h @@ -1,7 +1,7 @@ /* * C * - * Copyright 2019-2022 MicroEJ Corp. All rights reserved. + * Copyright 2019-2023 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -9,7 +9,7 @@ * @file * @brief Freetype vglite renderer * @author MicroEJ Developer Team -* @version 3.0.0 +* @version 7.0.1 */ #ifndef FTVECTOR_H @@ -22,8 +22,6 @@ #define FT_PARAM_TAG_VGLITE_DESTINATION FT_MAKE_TAG( 'd', 'e', 's', 't' ) #define FT_PARAM_TAG_VGLITE_MATRIX FT_MAKE_TAG( 'm', 'a', 't', 'r' ) -#define FT_PARAM_TAG_VGLITE_QUALITY FT_MAKE_TAG( 'q', 'u', 'a', 'l' ) -#define FT_PARAM_TAG_VGLITE_FORMAT FT_MAKE_TAG( 'f', 'o', 'r', 'm' ) #define FT_PARAM_TAG_VGLITE_BLEND FT_MAKE_TAG( 'b', 'l', 'e', 'n' ) #define FT_PARAM_TAG_VGLITE_COLOR FT_MAKE_TAG( 'c', 'o', 'l', 'o' ) #define FT_PARAM_TAG_VGLITE_GRADIENT FT_MAKE_TAG( 'g', 'r', 'a', 'd' ) @@ -35,21 +33,21 @@ //#define FT_VGLITE_LOG_OUTLINES #define VGLITE_CMD_MOVE_TO 2 -typedef struct path_move_to_16 { +typedef struct { int16_t cmd; int16_t x; int16_t y; } path_move_to_16_t; #define VGLITE_CMD_LINE_TO 4 -typedef struct path_line_to_16 { +typedef struct { int16_t cmd; int16_t x; int16_t y; } path_line_to_16_t; #define VGLITE_CMD_QUAD_TO 6 -typedef struct path_quad_to_16 { +typedef struct { int16_t cmd; int16_t cx; int16_t cy; @@ -58,7 +56,7 @@ typedef struct path_quad_to_16 { } path_quad_to_16_t; #define VGLITE_CMD_CUBIC_TO 8 -typedef struct path_cubic_to_16 { +typedef struct { int16_t cmd; int16_t cx1; int16_t cy1; @@ -69,7 +67,7 @@ typedef struct path_cubic_to_16 { } path_cubic_to_16_t; #define VGLITE_CMD_END 0 -typedef struct path_end_16 { +typedef struct { int16_t cmd; } path_end_16_t; diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftzconf.h b/bsp/projects/microej/thirdparty/freetype/inc/ftzconf.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftzconf.h rename to bsp/projects/microej/thirdparty/freetype/inc/ftzconf.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftzopen.h b/bsp/projects/microej/thirdparty/freetype/inc/ftzopen.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ftzopen.h rename to bsp/projects/microej/thirdparty/freetype/inc/ftzopen.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/gxvalid.h b/bsp/projects/microej/thirdparty/freetype/inc/gxvalid.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/gxvalid.h rename to bsp/projects/microej/thirdparty/freetype/inc/gxvalid.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/gxvcommn.h b/bsp/projects/microej/thirdparty/freetype/inc/gxvcommn.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/gxvcommn.h rename to bsp/projects/microej/thirdparty/freetype/inc/gxvcommn.h diff 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from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/sfwoff2.h rename to bsp/projects/microej/thirdparty/freetype/inc/sfwoff2.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/t1afm.h b/bsp/projects/microej/thirdparty/freetype/inc/t1afm.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/t1afm.h rename to bsp/projects/microej/thirdparty/freetype/inc/t1afm.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/t1cmap.h b/bsp/projects/microej/thirdparty/freetype/inc/t1cmap.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/t1cmap.h rename to bsp/projects/microej/thirdparty/freetype/inc/t1cmap.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/t1decode.h b/bsp/projects/microej/thirdparty/freetype/inc/t1decode.h similarity index 100% rename from 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nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/ttsubpix.h rename to bsp/projects/microej/thirdparty/freetype/inc/ttsubpix.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/winfnt.h b/bsp/projects/microej/thirdparty/freetype/inc/winfnt.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/winfnt.h rename to bsp/projects/microej/thirdparty/freetype/inc/winfnt.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/woff2tags.h b/bsp/projects/microej/thirdparty/freetype/inc/woff2tags.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/woff2tags.h rename to bsp/projects/microej/thirdparty/freetype/inc/woff2tags.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/zlib.h b/bsp/projects/microej/thirdparty/freetype/inc/zlib.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/zlib.h rename to bsp/projects/microej/thirdparty/freetype/inc/zlib.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/zutil.h b/bsp/projects/microej/thirdparty/freetype/inc/zutil.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/inc/zutil.h rename to bsp/projects/microej/thirdparty/freetype/inc/zutil.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/lib/.gitignore b/bsp/projects/microej/thirdparty/freetype/lib/.gitignore similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/lib/.gitignore rename to bsp/projects/microej/thirdparty/freetype/lib/.gitignore diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/lib/freetype.a b/bsp/projects/microej/thirdparty/freetype/lib/freetype.a similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/lib/freetype.a rename to bsp/projects/microej/thirdparty/freetype/lib/freetype.a diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/lib/lib_freetype.ewp b/bsp/projects/microej/thirdparty/freetype/lib/lib_freetype.ewp similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/lib/lib_freetype.ewp rename to bsp/projects/microej/thirdparty/freetype/lib/lib_freetype.ewp diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/adler32.c b/bsp/projects/microej/thirdparty/freetype/src/adler32.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/adler32.c rename to bsp/projects/microej/thirdparty/freetype/src/adler32.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afblue.c b/bsp/projects/microej/thirdparty/freetype/src/afblue.c similarity index 87% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afblue.c rename to bsp/projects/microej/thirdparty/freetype/src/afblue.c index d982aa1..d2c089f 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afblue.c +++ b/bsp/projects/microej/thirdparty/freetype/src/afblue.c @@ -26,7 +26,7 @@ af_blue_strings[] = { /* */ - '\xF0', '\x9E', '\xA4', '\x8C', ' ', '\xF0', '\x9E', '\xA4', '\x85', ' ', '\xF0', '\x9E', '\xA4', '\x88', ' ', '\xF0', '\x9E', '\xA4', '\x8F', ' ', '\xF0', '\x9E', '\xA4', '\x94', ' ', '\xF0', '\x9E', '\xA4', '\x9A', /* 𞤌 𞤅 𞤈 �? 𞤔 𞤚 */ + '\xF0', '\x9E', '\xA4', '\x8C', ' ', '\xF0', '\x9E', '\xA4', '\x85', ' ', '\xF0', '\x9E', '\xA4', '\x88', ' ', '\xF0', '\x9E', '\xA4', '\x8F', ' ', '\xF0', '\x9E', '\xA4', '\x94', ' ', '\xF0', '\x9E', '\xA4', '\x9A', /* 𞤌 𞤅 𞤈 �? 𞤔 𞤚 */ '\0', '\xF0', '\x9E', '\xA4', '\x82', ' ', '\xF0', '\x9E', '\xA4', '\x96', /* 𞤂 𞤖 */ '\0', @@ -40,9 +40,9 @@ '\0', '\xD9', '\x80', /* ـ */ '\0', - '\xD4', '\xB1', ' ', '\xD5', '\x84', ' ', '\xD5', '\x92', ' ', '\xD5', '\x8D', ' ', '\xD4', '\xB2', ' ', '\xD4', '\xB3', ' ', '\xD4', '\xB4', ' ', '\xD5', '\x95', /* Ա Մ Ւ �? Բ Գ Դ Օ */ + '\xD4', '\xB1', ' ', '\xD5', '\x84', ' ', '\xD5', '\x92', ' ', '\xD5', '\x8D', ' ', '\xD4', '\xB2', ' ', '\xD4', '\xB3', ' ', '\xD4', '\xB4', ' ', '\xD5', '\x95', /* Ա Մ Ւ �? Բ Գ Դ Օ */ '\0', - '\xD5', '\x92', ' ', '\xD5', '\x88', ' ', '\xD4', '\xB4', ' ', '\xD5', '\x83', ' ', '\xD5', '\x87', ' ', '\xD5', '\x8D', ' ', '\xD5', '\x8F', ' ', '\xD5', '\x95', /* Ւ Ո Դ Ճ Շ �? �? Օ */ + '\xD5', '\x92', ' ', '\xD5', '\x88', ' ', '\xD4', '\xB4', ' ', '\xD5', '\x83', ' ', '\xD5', '\x87', ' ', '\xD5', '\x8D', ' ', '\xD5', '\x8F', ' ', '\xD5', '\x95', /* Ւ Ո Դ Ճ Շ �? �? Օ */ '\0', '\xD5', '\xA5', ' ', '\xD5', '\xA7', ' ', '\xD5', '\xAB', ' ', '\xD5', '\xB4', ' ', '\xD5', '\xBE', ' ', '\xD6', '\x86', ' ', '\xD5', '\xB3', /* ե է ի մ վ ֆ ճ */ '\0', @@ -50,13 +50,13 @@ '\0', '\xD5', '\xB0', ' ', '\xD5', '\xB8', ' ', '\xD5', '\xB3', ' ', '\xD5', '\xA1', ' ', '\xD5', '\xA5', ' ', '\xD5', '\xAE', ' ', '\xD5', '\xBD', ' ', '\xD6', '\x85', /* հ ո ճ ա ե ծ ս օ */ '\0', - '\xD5', '\xA2', ' ', '\xD5', '\xA8', ' ', '\xD5', '\xAB', ' ', '\xD5', '\xAC', ' ', '\xD5', '\xB2', ' ', '\xD5', '\xBA', ' ', '\xD6', '\x83', ' ', '\xD6', '\x81', /* բ ը ի լ ղ պ փ �? */ + '\xD5', '\xA2', ' ', '\xD5', '\xA8', ' ', '\xD5', '\xAB', ' ', '\xD5', '\xAC', ' ', '\xD5', '\xB2', ' ', '\xD5', '\xBA', ' ', '\xD6', '\x83', ' ', '\xD6', '\x81', /* բ ը ի լ ղ պ փ �? */ '\0', - '\xF0', '\x90', '\xAC', '\x80', ' ', '\xF0', '\x90', '\xAC', '\x81', ' ', '\xF0', '\x90', '\xAC', '\x90', ' ', '\xF0', '\x90', '\xAC', '\x9B', /* �?�� �?�? �?�? �?�� */ + '\xF0', '\x90', '\xAC', '\x80', ' ', '\xF0', '\x90', '\xAC', '\x81', ' ', '\xF0', '\x90', '\xAC', '\x90', ' ', '\xF0', '\x90', '\xAC', '\x9B', /* �?�� �?�? �?�? �?�� */ '\0', - '\xF0', '\x90', '\xAC', '\x80', ' ', '\xF0', '\x90', '\xAC', '\x81', /* �?�� �?�? */ + '\xF0', '\x90', '\xAC', '\x80', ' ', '\xF0', '\x90', '\xAC', '\x81', /* �?�� �?�? */ '\0', - '\xEA', '\x9A', '\xA7', ' ', '\xEA', '\x9A', '\xA8', ' ', '\xEA', '\x9B', '\x9B', ' ', '\xEA', '\x9B', '\x89', ' ', '\xEA', '\x9B', '\x81', ' ', '\xEA', '\x9B', '\x88', ' ', '\xEA', '\x9B', '\xAB', ' ', '\xEA', '\x9B', '\xAF', /* ꚧ ꚨ ꛛ ꛉ �? ꛈ ꛫ ꛯ */ + '\xEA', '\x9A', '\xA7', ' ', '\xEA', '\x9A', '\xA8', ' ', '\xEA', '\x9B', '\x9B', ' ', '\xEA', '\x9B', '\x89', ' ', '\xEA', '\x9B', '\x81', ' ', '\xEA', '\x9B', '\x88', ' ', '\xEA', '\x9B', '\xAB', ' ', '\xEA', '\x9B', '\xAF', /* ꚧ ꚨ ꛛ ꛉ �? ꛈ ꛫ ꛯ */ '\0', '\xEA', '\x9A', '\xAD', ' ', '\xEA', '\x9A', '\xB3', ' ', '\xEA', '\x9A', '\xB6', ' ', '\xEA', '\x9B', '\xAC', ' ', '\xEA', '\x9A', '\xA2', ' ', '\xEA', '\x9A', '\xBD', ' ', '\xEA', '\x9B', '\xAF', ' ', '\xEA', '\x9B', '\xB2', /* ꚭ ꚳ ꚶ ꛬ ꚢ ꚽ ꛯ ꛲ */ '\0', @@ -64,91 +64,91 @@ '\0', '\xE0', '\xA6', '\x87', ' ', '\xE0', '\xA6', '\x9F', ' ', '\xE0', '\xA6', '\xA0', ' ', '\xE0', '\xA6', '\xBF', ' ', '\xE0', '\xA7', '\x80', ' ', '\xE0', '\xA7', '\x88', ' ', '\xE0', '\xA7', '\x97', /* ই ট ঠ ি ী ৈ ৗ */ '\0', - '\xE0', '\xA6', '\x93', ' ', '\xE0', '\xA6', '\x8F', ' ', '\xE0', '\xA6', '\xA1', ' ', '\xE0', '\xA6', '\xA4', ' ', '\xE0', '\xA6', '\xA8', ' ', '\xE0', '\xA6', '\xAC', ' ', '\xE0', '\xA6', '\xB2', ' ', '\xE0', '\xA6', '\x95', /* ও �? ড ত ন ব ল ক */ + '\xE0', '\xA6', '\x93', ' ', '\xE0', '\xA6', '\x8F', ' ', '\xE0', '\xA6', '\xA1', ' ', '\xE0', '\xA6', '\xA4', ' ', '\xE0', '\xA6', '\xA8', ' ', '\xE0', '\xA6', '\xAC', ' ', '\xE0', '\xA6', '\xB2', ' ', '\xE0', '\xA6', '\x95', /* ও �? ড ত ন ব ল ক */ '\0', - '\xE1', '\x9D', '\x90', ' ', '\xE1', '\x9D', '\x88', /* �?? �?� */ + '\xE1', '\x9D', '\x90', ' ', '\xE1', '\x9D', '\x88', /* �?? �?� */ '\0', - '\xE1', '\x9D', '\x85', ' ', '\xE1', '\x9D', '\x8A', ' ', '\xE1', '\x9D', '\x8E', /* �?� �?� �?� */ + '\xE1', '\x9D', '\x85', ' ', '\xE1', '\x9D', '\x8A', ' ', '\xE1', '\x9D', '\x8E', /* �?� �?� �?� */ '\0', - '\xE1', '\x9D', '\x82', ' ', '\xE1', '\x9D', '\x83', ' ', '\xE1', '\x9D', '\x89', ' ', '\xE1', '\x9D', '\x8C', /* �?� �?� �?� �?� */ + '\xE1', '\x9D', '\x82', ' ', '\xE1', '\x9D', '\x83', ' ', '\xE1', '\x9D', '\x89', ' ', '\xE1', '\x9D', '\x8C', /* �?� �?� �?� �?� */ '\0', - '\xE1', '\x9D', '\x80', ' ', '\xE1', '\x9D', '\x83', ' ', '\xE1', '\x9D', '\x86', ' ', '\xE1', '\x9D', '\x89', ' ', '\xE1', '\x9D', '\x8B', ' ', '\xE1', '\x9D', '\x8F', ' ', '\xE1', '\x9D', '\x91', /* �?� �?� �?� �?� �?� �?? �?� */ + '\xE1', '\x9D', '\x80', ' ', '\xE1', '\x9D', '\x83', ' ', '\xE1', '\x9D', '\x86', ' ', '\xE1', '\x9D', '\x89', ' ', '\xE1', '\x9D', '\x8B', ' ', '\xE1', '\x9D', '\x8F', ' ', '\xE1', '\x9D', '\x91', /* �?� �?� �?� �?� �?� �?? �?� */ '\0', - '\xE1', '\x97', '\x9C', ' ', '\xE1', '\x96', '\xB4', ' ', '\xE1', '\x90', '\x81', ' ', '\xE1', '\x92', '\xA3', ' ', '\xE1', '\x91', '\xAB', ' ', '\xE1', '\x91', '\x8E', ' ', '\xE1', '\x94', '\x91', ' ', '\xE1', '\x97', '\xB0', /* ᗜ ᖴ �?? ᒣ ᑫ ᑎ ᔑ ᗰ */ + '\xE1', '\x97', '\x9C', ' ', '\xE1', '\x96', '\xB4', ' ', '\xE1', '\x90', '\x81', ' ', '\xE1', '\x92', '\xA3', ' ', '\xE1', '\x91', '\xAB', ' ', '\xE1', '\x91', '\x8E', ' ', '\xE1', '\x94', '\x91', ' ', '\xE1', '\x97', '\xB0', /* ᗜ ᖴ �?? ᒣ ᑫ ᑎ ᔑ ᗰ */ '\0', - '\xE1', '\x97', '\xB6', ' ', '\xE1', '\x96', '\xB5', ' ', '\xE1', '\x92', '\xA7', ' ', '\xE1', '\x90', '\x83', ' ', '\xE1', '\x91', '\x8C', ' ', '\xE1', '\x92', '\x8D', ' ', '\xE1', '\x94', '\x91', ' ', '\xE1', '\x97', '\xA2', /* ᗶ ᖵ ᒧ �?� ᑌ �? ᔑ ᗢ */ + '\xE1', '\x97', '\xB6', ' ', '\xE1', '\x96', '\xB5', ' ', '\xE1', '\x92', '\xA7', ' ', '\xE1', '\x90', '\x83', ' ', '\xE1', '\x91', '\x8C', ' ', '\xE1', '\x92', '\x8D', ' ', '\xE1', '\x94', '\x91', ' ', '\xE1', '\x97', '\xA2', /* ᗶ ᖵ ᒧ �?� ᑌ �? ᔑ ᗢ */ '\0', '\xE1', '\x93', '\x93', ' ', '\xE1', '\x93', '\x95', ' ', '\xE1', '\x93', '\x80', ' ', '\xE1', '\x93', '\x82', ' ', '\xE1', '\x93', '\x84', ' ', '\xE1', '\x95', '\x84', ' ', '\xE1', '\x95', '\x86', ' ', '\xE1', '\x98', '\xA3', /* ᓓ ᓕ ᓀ ᓂ ᓄ ᕄ ᕆ ᘣ */ '\0', '\xE1', '\x95', '\x83', ' ', '\xE1', '\x93', '\x82', ' ', '\xE1', '\x93', '\x80', ' ', '\xE1', '\x95', '\x82', ' ', '\xE1', '\x93', '\x97', ' ', '\xE1', '\x93', '\x9A', ' ', '\xE1', '\x95', '\x86', ' ', '\xE1', '\x98', '\xA3', /* ᕃ ᓂ ᓀ ᕂ ᓗ ᓚ ᕆ ᘣ */ '\0', - '\xE1', '\x90', '\xAA', ' ', '\xE1', '\x99', '\x86', ' ', '\xE1', '\xA3', '\x98', ' ', '\xE1', '\x90', '\xA2', ' ', '\xE1', '\x92', '\xBE', ' ', '\xE1', '\xA3', '\x97', ' ', '\xE1', '\x94', '\x86', /* �?� ᙆ ᣘ �?� ᒾ ᣗ ᔆ */ + '\xE1', '\x90', '\xAA', ' ', '\xE1', '\x99', '\x86', ' ', '\xE1', '\xA3', '\x98', ' ', '\xE1', '\x90', '\xA2', ' ', '\xE1', '\x92', '\xBE', ' ', '\xE1', '\xA3', '\x97', ' ', '\xE1', '\x94', '\x86', /* �?� ᙆ ᣘ �?� ᒾ ᣗ ᔆ */ '\0', - '\xE1', '\x99', '\x86', ' ', '\xE1', '\x97', '\xAE', ' ', '\xE1', '\x92', '\xBB', ' ', '\xE1', '\x90', '\x9E', ' ', '\xE1', '\x94', '\x86', ' ', '\xE1', '\x92', '\xA1', ' ', '\xE1', '\x92', '\xA2', ' ', '\xE1', '\x93', '\x91', /* ᙆ ᗮ ᒻ �?� ᔆ ᒡ ᒢ ᓑ */ + '\xE1', '\x99', '\x86', ' ', '\xE1', '\x97', '\xAE', ' ', '\xE1', '\x92', '\xBB', ' ', '\xE1', '\x90', '\x9E', ' ', '\xE1', '\x94', '\x86', ' ', '\xE1', '\x92', '\xA1', ' ', '\xE1', '\x92', '\xA2', ' ', '\xE1', '\x93', '\x91', /* ᙆ ᗮ ᒻ �?� ᔆ ᒡ ᒢ ᓑ */ '\0', - '\xF0', '\x90', '\x8A', '\xA7', ' ', '\xF0', '\x90', '\x8A', '\xAB', ' ', '\xF0', '\x90', '\x8A', '\xAC', ' ', '\xF0', '\x90', '\x8A', '\xAD', ' ', '\xF0', '\x90', '\x8A', '\xB1', ' ', '\xF0', '\x90', '\x8A', '\xBA', ' ', '\xF0', '\x90', '\x8A', '\xBC', ' ', '\xF0', '\x90', '\x8A', '\xBF', /* �?�� �?�� �?�� �?�� �?�� �?�� �?�� �?�� */ + '\xF0', '\x90', '\x8A', '\xA7', ' ', '\xF0', '\x90', '\x8A', '\xAB', ' ', '\xF0', '\x90', '\x8A', '\xAC', ' ', '\xF0', '\x90', '\x8A', '\xAD', ' ', '\xF0', '\x90', '\x8A', '\xB1', ' ', '\xF0', '\x90', '\x8A', '\xBA', ' ', '\xF0', '\x90', '\x8A', '\xBC', ' ', '\xF0', '\x90', '\x8A', '\xBF', /* �?�� �?�� �?�� �?�� �?�� �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\x8A', '\xA3', ' ', '\xF0', '\x90', '\x8A', '\xA7', ' ', '\xF0', '\x90', '\x8A', '\xB7', ' ', '\xF0', '\x90', '\x8B', '\x80', ' ', '\xF0', '\x90', '\x8A', '\xAB', ' ', '\xF0', '\x90', '\x8A', '\xB8', ' ', '\xF0', '\x90', '\x8B', '\x89', /* �?�� �?�� �?�� �?�� �?�� �?�� �?�� */ + '\xF0', '\x90', '\x8A', '\xA3', ' ', '\xF0', '\x90', '\x8A', '\xA7', ' ', '\xF0', '\x90', '\x8A', '\xB7', ' ', '\xF0', '\x90', '\x8B', '\x80', ' ', '\xF0', '\x90', '\x8A', '\xAB', ' ', '\xF0', '\x90', '\x8A', '\xB8', ' ', '\xF0', '\x90', '\x8B', '\x89', /* �?�� �?�� �?�� �?�� �?�� �?�� �?�� */ '\0', '\xF0', '\x91', '\x84', '\x83', ' ', '\xF0', '\x91', '\x84', '\x85', ' ', '\xF0', '\x91', '\x84', '\x89', ' ', '\xF0', '\x91', '\x84', '\x99', ' ', '\xF0', '\x91', '\x84', '\x97', /* 𑄃 𑄅 𑄉 𑄙 𑄗 */ '\0', - '\xF0', '\x91', '\x84', '\x85', ' ', '\xF0', '\x91', '\x84', '\x9B', ' ', '\xF0', '\x91', '\x84', '\x9D', ' ', '\xF0', '\x91', '\x84', '\x97', ' ', '\xF0', '\x91', '\x84', '\x93', /* 𑄅 𑄛 �? 𑄗 𑄓 */ + '\xF0', '\x91', '\x84', '\x85', ' ', '\xF0', '\x91', '\x84', '\x9B', ' ', '\xF0', '\x91', '\x84', '\x9D', ' ', '\xF0', '\x91', '\x84', '\x97', ' ', '\xF0', '\x91', '\x84', '\x93', /* 𑄅 𑄛 �? 𑄗 𑄓 */ '\0', '\xF0', '\x91', '\x84', '\x96', '\xF0', '\x91', '\x84', '\xB3', '\xF0', '\x91', '\x84', '\xA2', ' ', '\xF0', '\x91', '\x84', '\x98', '\xF0', '\x91', '\x84', '\xB3', '\xF0', '\x91', '\x84', '\xA2', ' ', '\xF0', '\x91', '\x84', '\x99', '\xF0', '\x91', '\x84', '\xB3', '\xF0', '\x91', '\x84', '\xA2', ' ', '\xF0', '\x91', '\x84', '\xA4', '\xF0', '\x91', '\x84', '\xB3', '\xF0', '\x91', '\x84', '\xA2', ' ', '\xF0', '\x91', '\x84', '\xA5', '\xF0', '\x91', '\x84', '\xB3', '\xF0', '\x91', '\x84', '\xA2', /* 𑄖𑄳𑄢 𑄘𑄳𑄢 𑄙𑄳𑄢 𑄤𑄳𑄢 𑄥𑄳𑄢 */ '\0', - '\xE1', '\x8F', '\x86', ' ', '\xE1', '\x8E', '\xBB', ' ', '\xE1', '\x8E', '\xAC', ' ', '\xE1', '\x8F', '\x83', ' ', '\xE1', '\x8E', '\xA4', ' ', '\xE1', '\x8F', '\xA3', ' ', '\xE1', '\x8E', '\xA6', ' ', '\xE1', '\x8F', '\x95', /* �?� Ꮋ Ꭼ �?� Ꭴ �?� Ꭶ �?� */ + '\xE1', '\x8F', '\x86', ' ', '\xE1', '\x8E', '\xBB', ' ', '\xE1', '\x8E', '\xAC', ' ', '\xE1', '\x8F', '\x83', ' ', '\xE1', '\x8E', '\xA4', ' ', '\xE1', '\x8F', '\xA3', ' ', '\xE1', '\x8E', '\xA6', ' ', '\xE1', '\x8F', '\x95', /* �?� Ꮋ Ꭼ �?� Ꭴ �?� Ꭶ �?� */ '\0', - '\xEA', '\xAE', '\x92', ' ', '\xEA', '\xAE', '\xA4', ' ', '\xEA', '\xAE', '\xB6', ' ', '\xEA', '\xAD', '\xB4', ' ', '\xEA', '\xAD', '\xBE', ' ', '\xEA', '\xAE', '\x97', ' ', '\xEA', '\xAE', '\x9D', ' ', '\xEA', '\xAE', '\xBF', /* ꮒ ꮤ ꮶ ꭴ ꭾ ꮗ �? ꮿ */ + '\xEA', '\xAE', '\x92', ' ', '\xEA', '\xAE', '\xA4', ' ', '\xEA', '\xAE', '\xB6', ' ', '\xEA', '\xAD', '\xB4', ' ', '\xEA', '\xAD', '\xBE', ' ', '\xEA', '\xAE', '\x97', ' ', '\xEA', '\xAE', '\x9D', ' ', '\xEA', '\xAE', '\xBF', /* ꮒ ꮤ ꮶ ꭴ ꭾ ꮗ �? ꮿ */ '\0', '\xEA', '\xAE', '\x96', ' ', '\xEA', '\xAD', '\xBC', ' ', '\xEA', '\xAE', '\x93', ' ', '\xEA', '\xAE', '\xA0', ' ', '\xEA', '\xAE', '\xB3', ' ', '\xEA', '\xAD', '\xB6', ' ', '\xEA', '\xAE', '\xA5', ' ', '\xEA', '\xAE', '\xBB', /* ꮖ ꭼ ꮓ ꮠ ꮳ ꭶ ꮥ ꮻ */ '\0', - '\xE1', '\x8F', '\xB8', ' ', '\xEA', '\xAE', '\x90', ' ', '\xEA', '\xAD', '\xB9', ' ', '\xEA', '\xAD', '\xBB', /* �?� �? ꭹ ꭻ */ + '\xE1', '\x8F', '\xB8', ' ', '\xEA', '\xAE', '\x90', ' ', '\xEA', '\xAD', '\xB9', ' ', '\xEA', '\xAD', '\xBB', /* �?� �? ꭹ ꭻ */ '\0', - '\xE2', '\xB2', '\x8C', ' ', '\xE2', '\xB2', '\x8E', ' ', '\xE2', '\xB2', '\xA0', ' ', '\xE2', '\xB3', '\x9E', ' ', '\xE2', '\xB2', '\x9E', ' ', '\xE2', '\xB2', '\x90', ' ', '\xE2', '\xB2', '\xA4', ' ', '\xE2', '\xB3', '\x8A', /* Ⲍ Ⲏ Ⲡ Ⳟ Ⲟ �? Ⲥ Ⳋ */ + '\xE2', '\xB2', '\x8C', ' ', '\xE2', '\xB2', '\x8E', ' ', '\xE2', '\xB2', '\xA0', ' ', '\xE2', '\xB3', '\x9E', ' ', '\xE2', '\xB2', '\x9E', ' ', '\xE2', '\xB2', '\x90', ' ', '\xE2', '\xB2', '\xA4', ' ', '\xE2', '\xB3', '\x8A', /* Ⲍ Ⲏ Ⲡ Ⳟ Ⲟ �? Ⲥ Ⳋ */ '\0', - '\xE2', '\xB3', '\x90', ' ', '\xE2', '\xB3', '\x98', ' ', '\xE2', '\xB3', '\x9E', ' ', '\xE2', '\xB2', '\x8E', ' ', '\xE2', '\xB2', '\x9E', ' ', '\xE2', '\xB2', '\x90', ' ', '\xE2', '\xB3', '\x9C', ' ', '\xE2', '\xB2', '\xB0', /* �? Ⳙ Ⳟ Ⲏ Ⲟ �? Ⳝ Ⲱ */ + '\xE2', '\xB3', '\x90', ' ', '\xE2', '\xB3', '\x98', ' ', '\xE2', '\xB3', '\x9E', ' ', '\xE2', '\xB2', '\x8E', ' ', '\xE2', '\xB2', '\x9E', ' ', '\xE2', '\xB2', '\x90', ' ', '\xE2', '\xB3', '\x9C', ' ', '\xE2', '\xB2', '\xB0', /* �? Ⳙ Ⳟ Ⲏ Ⲟ �? Ⳝ Ⲱ */ '\0', - '\xE2', '\xB2', '\x8D', ' ', '\xE2', '\xB2', '\x8F', ' ', '\xE2', '\xB2', '\xA1', ' ', '\xE2', '\xB3', '\x9F', ' ', '\xE2', '\xB2', '\x9F', ' ', '\xE2', '\xB2', '\x91', ' ', '\xE2', '\xB2', '\xA5', ' ', '\xE2', '\xB3', '\x8B', /* �? �? ⲡ ⳟ ⲟ ⲑ ⲥ ⳋ */ + '\xE2', '\xB2', '\x8D', ' ', '\xE2', '\xB2', '\x8F', ' ', '\xE2', '\xB2', '\xA1', ' ', '\xE2', '\xB3', '\x9F', ' ', '\xE2', '\xB2', '\x9F', ' ', '\xE2', '\xB2', '\x91', ' ', '\xE2', '\xB2', '\xA5', ' ', '\xE2', '\xB3', '\x8B', /* �? �? ⲡ ⳟ ⲟ ⲑ ⲥ ⳋ */ '\0', - '\xE2', '\xB3', '\x91', ' ', '\xE2', '\xB3', '\x99', ' ', '\xE2', '\xB3', '\x9F', ' ', '\xE2', '\xB2', '\x8F', ' ', '\xE2', '\xB2', '\x9F', ' ', '\xE2', '\xB2', '\x91', ' ', '\xE2', '\xB3', '\x9D', ' ', '\xE2', '\xB3', '\x92', /* ⳑ ⳙ ⳟ �? ⲟ ⲑ �? Ⳓ */ + '\xE2', '\xB3', '\x91', ' ', '\xE2', '\xB3', '\x99', ' ', '\xE2', '\xB3', '\x9F', ' ', '\xE2', '\xB2', '\x8F', ' ', '\xE2', '\xB2', '\x9F', ' ', '\xE2', '\xB2', '\x91', ' ', '\xE2', '\xB3', '\x9D', ' ', '\xE2', '\xB3', '\x92', /* ⳑ ⳙ ⳟ �? ⲟ ⲑ �? Ⳓ */ '\0', - '\xF0', '\x90', '\xA0', '\x8D', ' ', '\xF0', '\x90', '\xA0', '\x99', ' ', '\xF0', '\x90', '\xA0', '\xB3', ' ', '\xF0', '\x90', '\xA0', '\xB1', ' ', '\xF0', '\x90', '\xA0', '\x85', ' ', '\xF0', '\x90', '\xA0', '\x93', ' ', '\xF0', '\x90', '\xA0', '\xA3', ' ', '\xF0', '\x90', '\xA0', '\xA6', /* �?�? �?�� �?�� �?�� �?�� �?�� �?�� �?�� */ + '\xF0', '\x90', '\xA0', '\x8D', ' ', '\xF0', '\x90', '\xA0', '\x99', ' ', '\xF0', '\x90', '\xA0', '\xB3', ' ', '\xF0', '\x90', '\xA0', '\xB1', ' ', '\xF0', '\x90', '\xA0', '\x85', ' ', '\xF0', '\x90', '\xA0', '\x93', ' ', '\xF0', '\x90', '\xA0', '\xA3', ' ', '\xF0', '\x90', '\xA0', '\xA6', /* �?�? �?�� �?�� �?�� �?�� �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\xA0', '\x83', ' ', '\xF0', '\x90', '\xA0', '\x8A', ' ', '\xF0', '\x90', '\xA0', '\x9B', ' ', '\xF0', '\x90', '\xA0', '\xA3', ' ', '\xF0', '\x90', '\xA0', '\xB3', ' ', '\xF0', '\x90', '\xA0', '\xB5', ' ', '\xF0', '\x90', '\xA0', '\x90', /* �?�� �?�� �?�� �?�� �?�� �?�� �?�? */ + '\xF0', '\x90', '\xA0', '\x83', ' ', '\xF0', '\x90', '\xA0', '\x8A', ' ', '\xF0', '\x90', '\xA0', '\x9B', ' ', '\xF0', '\x90', '\xA0', '\xA3', ' ', '\xF0', '\x90', '\xA0', '\xB3', ' ', '\xF0', '\x90', '\xA0', '\xB5', ' ', '\xF0', '\x90', '\xA0', '\x90', /* �?�� �?�� �?�� �?�� �?�� �?�� �?�? */ '\0', - '\xF0', '\x90', '\xA0', '\x88', ' ', '\xF0', '\x90', '\xA0', '\x8F', ' ', '\xF0', '\x90', '\xA0', '\x96', /* �?�� �?�? �?�� */ + '\xF0', '\x90', '\xA0', '\x88', ' ', '\xF0', '\x90', '\xA0', '\x8F', ' ', '\xF0', '\x90', '\xA0', '\x96', /* �?�� �?�? �?�� */ '\0', '\xD0', '\x91', ' ', '\xD0', '\x92', ' ', '\xD0', '\x95', ' ', '\xD0', '\x9F', ' ', '\xD0', '\x97', ' ', '\xD0', '\x9E', ' ', '\xD0', '\xA1', ' ', '\xD0', '\xAD', /* Б В Е П З О С Э */ '\0', '\xD0', '\x91', ' ', '\xD0', '\x92', ' ', '\xD0', '\x95', ' ', '\xD0', '\xA8', ' ', '\xD0', '\x97', ' ', '\xD0', '\x9E', ' ', '\xD0', '\xA1', ' ', '\xD0', '\xAD', /* Б В Е Ш З О С Э */ '\0', - '\xD1', '\x85', ' ', '\xD0', '\xBF', ' ', '\xD0', '\xBD', ' ', '\xD1', '\x88', ' ', '\xD0', '\xB5', ' ', '\xD0', '\xB7', ' ', '\xD0', '\xBE', ' ', '\xD1', '\x81', /* х п н ш е з о �? */ + '\xD1', '\x85', ' ', '\xD0', '\xBF', ' ', '\xD0', '\xBD', ' ', '\xD1', '\x88', ' ', '\xD0', '\xB5', ' ', '\xD0', '\xB7', ' ', '\xD0', '\xBE', ' ', '\xD1', '\x81', /* х п н ш е з о �? */ '\0', '\xD1', '\x80', ' ', '\xD1', '\x83', ' ', '\xD1', '\x84', /* р у ф */ '\0', - '\xF0', '\x90', '\x90', '\x82', ' ', '\xF0', '\x90', '\x90', '\x84', ' ', '\xF0', '\x90', '\x90', '\x8B', ' ', '\xF0', '\x90', '\x90', '\x97', ' ', '\xF0', '\x90', '\x90', '\x91', /* �??� �??� �??� �??� �??� */ + '\xF0', '\x90', '\x90', '\x82', ' ', '\xF0', '\x90', '\x90', '\x84', ' ', '\xF0', '\x90', '\x90', '\x8B', ' ', '\xF0', '\x90', '\x90', '\x97', ' ', '\xF0', '\x90', '\x90', '\x91', /* �??� �??� �??� �??� �??� */ '\0', - '\xF0', '\x90', '\x90', '\x80', ' ', '\xF0', '\x90', '\x90', '\x82', ' ', '\xF0', '\x90', '\x90', '\x84', ' ', '\xF0', '\x90', '\x90', '\x97', ' ', '\xF0', '\x90', '\x90', '\x9B', /* �??� �??� �??� �??� �??� */ + '\xF0', '\x90', '\x90', '\x80', ' ', '\xF0', '\x90', '\x90', '\x82', ' ', '\xF0', '\x90', '\x90', '\x84', ' ', '\xF0', '\x90', '\x90', '\x97', ' ', '\xF0', '\x90', '\x90', '\x9B', /* �??� �??� �??� �??� �??� */ '\0', - '\xF0', '\x90', '\x90', '\xAA', ' ', '\xF0', '\x90', '\x90', '\xAC', ' ', '\xF0', '\x90', '\x90', '\xB3', ' ', '\xF0', '\x90', '\x90', '\xBF', ' ', '\xF0', '\x90', '\x90', '\xB9', /* �??� �??� �??� �??� �??� */ + '\xF0', '\x90', '\x90', '\xAA', ' ', '\xF0', '\x90', '\x90', '\xAC', ' ', '\xF0', '\x90', '\x90', '\xB3', ' ', '\xF0', '\x90', '\x90', '\xBF', ' ', '\xF0', '\x90', '\x90', '\xB9', /* �??� �??� �??� �??� �??� */ '\0', - '\xF0', '\x90', '\x90', '\xA8', ' ', '\xF0', '\x90', '\x90', '\xAA', ' ', '\xF0', '\x90', '\x90', '\xAC', ' ', '\xF0', '\x90', '\x90', '\xBF', ' ', '\xF0', '\x90', '\x91', '\x83', /* �??� �??� �??� �??� �?�� */ + '\xF0', '\x90', '\x90', '\xA8', ' ', '\xF0', '\x90', '\x90', '\xAA', ' ', '\xF0', '\x90', '\x90', '\xAC', ' ', '\xF0', '\x90', '\x90', '\xBF', ' ', '\xF0', '\x90', '\x91', '\x83', /* �??� �??� �??� �??� �?�� */ '\0', '\xE0', '\xA4', '\x95', ' ', '\xE0', '\xA4', '\xA8', ' ', '\xE0', '\xA4', '\xAE', ' ', '\xE0', '\xA4', '\x89', ' ', '\xE0', '\xA4', '\x9B', ' ', '\xE0', '\xA4', '\x9F', ' ', '\xE0', '\xA4', '\xA0', ' ', '\xE0', '\xA4', '\xA1', /* क न म उ छ ट ठ ड */ '\0', - '\xE0', '\xA4', '\x88', ' ', '\xE0', '\xA4', '\x90', ' ', '\xE0', '\xA4', '\x93', ' ', '\xE0', '\xA4', '\x94', ' ', '\xE0', '\xA4', '\xBF', ' ', '\xE0', '\xA5', '\x80', ' ', '\xE0', '\xA5', '\x8B', ' ', '\xE0', '\xA5', '\x8C', /* ई �? ओ औ ि ी ो ौ */ + '\xE0', '\xA4', '\x88', ' ', '\xE0', '\xA4', '\x90', ' ', '\xE0', '\xA4', '\x93', ' ', '\xE0', '\xA4', '\x94', ' ', '\xE0', '\xA4', '\xBF', ' ', '\xE0', '\xA5', '\x80', ' ', '\xE0', '\xA5', '\x8B', ' ', '\xE0', '\xA5', '\x8C', /* ई �? ओ औ ि ी ो ौ */ '\0', '\xE0', '\xA4', '\x95', ' ', '\xE0', '\xA4', '\xAE', ' ', '\xE0', '\xA4', '\x85', ' ', '\xE0', '\xA4', '\x86', ' ', '\xE0', '\xA4', '\xA5', ' ', '\xE0', '\xA4', '\xA7', ' ', '\xE0', '\xA4', '\xAD', ' ', '\xE0', '\xA4', '\xB6', /* क म अ आ थ ध भ श */ '\0', - '\xE0', '\xA5', '\x81', ' ', '\xE0', '\xA5', '\x83', /* �? ृ */ + '\xE0', '\xA5', '\x81', ' ', '\xE0', '\xA5', '\x83', /* �? ृ */ '\0', - '\xE1', '\x88', '\x80', ' ', '\xE1', '\x88', '\x83', ' ', '\xE1', '\x8B', '\x98', ' ', '\xE1', '\x8D', '\x90', ' ', '\xE1', '\x88', '\x9B', ' ', '\xE1', '\x89', '\xA0', ' ', '\xE1', '\x8B', '\x8B', ' ', '\xE1', '\x8B', '\x90', /* ሀ ሃ ዘ �?? ማ በ ዋ �? */ + '\xE1', '\x88', '\x80', ' ', '\xE1', '\x88', '\x83', ' ', '\xE1', '\x8B', '\x98', ' ', '\xE1', '\x8D', '\x90', ' ', '\xE1', '\x88', '\x9B', ' ', '\xE1', '\x89', '\xA0', ' ', '\xE1', '\x8B', '\x8B', ' ', '\xE1', '\x8B', '\x90', /* ሀ ሃ ዘ �?? ማ በ ዋ �? */ '\0', - '\xE1', '\x88', '\x88', ' ', '\xE1', '\x88', '\x90', ' ', '\xE1', '\x89', '\xA0', ' ', '\xE1', '\x8B', '\x98', ' ', '\xE1', '\x88', '\x80', ' ', '\xE1', '\x88', '\xAA', ' ', '\xE1', '\x8B', '\x90', ' ', '\xE1', '\x8C', '\xA8', /* ለ �? በ ዘ ሀ ሪ �? ጨ */ + '\xE1', '\x88', '\x88', ' ', '\xE1', '\x88', '\x90', ' ', '\xE1', '\x89', '\xA0', ' ', '\xE1', '\x8B', '\x98', ' ', '\xE1', '\x88', '\x80', ' ', '\xE1', '\x88', '\xAA', ' ', '\xE1', '\x8B', '\x90', ' ', '\xE1', '\x8C', '\xA8', /* ለ �? በ ዘ ሀ ሪ �? ጨ */ '\0', - '\xE1', '\x83', '\x92', ' ', '\xE1', '\x83', '\x93', ' ', '\xE1', '\x83', '\x94', ' ', '\xE1', '\x83', '\x95', ' ', '\xE1', '\x83', '\x97', ' ', '\xE1', '\x83', '\x98', ' ', '\xE1', '\x83', '\x9D', ' ', '\xE1', '\x83', '\xA6', /* გ დ ე ვ თ ი �? ღ */ + '\xE1', '\x83', '\x92', ' ', '\xE1', '\x83', '\x93', ' ', '\xE1', '\x83', '\x94', ' ', '\xE1', '\x83', '\x95', ' ', '\xE1', '\x83', '\x97', ' ', '\xE1', '\x83', '\x98', ' ', '\xE1', '\x83', '\x9D', ' ', '\xE1', '\x83', '\xA6', /* გ დ ე ვ თ ი �? ღ */ '\0', - '\xE1', '\x83', '\x90', ' ', '\xE1', '\x83', '\x96', ' ', '\xE1', '\x83', '\x9B', ' ', '\xE1', '\x83', '\xA1', ' ', '\xE1', '\x83', '\xA8', ' ', '\xE1', '\x83', '\xAB', ' ', '\xE1', '\x83', '\xAE', ' ', '\xE1', '\x83', '\x9E', /* �? ზ მ ს შ ძ ხ პ */ + '\xE1', '\x83', '\x90', ' ', '\xE1', '\x83', '\x96', ' ', '\xE1', '\x83', '\x9B', ' ', '\xE1', '\x83', '\xA1', ' ', '\xE1', '\x83', '\xA8', ' ', '\xE1', '\x83', '\xAB', ' ', '\xE1', '\x83', '\xAE', ' ', '\xE1', '\x83', '\x9E', /* �? ზ მ ს შ ძ ხ პ */ '\0', '\xE1', '\x83', '\xA1', ' ', '\xE1', '\x83', '\xAE', ' ', '\xE1', '\x83', '\xA5', ' ', '\xE1', '\x83', '\x96', ' ', '\xE1', '\x83', '\x9B', ' ', '\xE1', '\x83', '\xA8', ' ', '\xE1', '\x83', '\xA9', ' ', '\xE1', '\x83', '\xAC', /* ს ხ ქ ზ მ შ ჩ წ */ '\0', @@ -158,17 +158,17 @@ '\0', '\xE1', '\x82', '\xA4', ' ', '\xE1', '\x82', '\xA5', ' ', '\xE1', '\x82', '\xA7', ' ', '\xE1', '\x82', '\xA8', ' ', '\xE1', '\x82', '\xA6', ' ', '\xE1', '\x82', '\xB1', ' ', '\xE1', '\x82', '\xAA', ' ', '\xE1', '\x82', '\xAB', /* Ⴄ Ⴅ Ⴇ Ⴈ Ⴆ Ⴑ Ⴊ Ⴋ */ '\0', - '\xE2', '\xB4', '\x81', ' ', '\xE2', '\xB4', '\x97', ' ', '\xE2', '\xB4', '\x82', ' ', '\xE2', '\xB4', '\x84', ' ', '\xE2', '\xB4', '\x85', ' ', '\xE2', '\xB4', '\x87', ' ', '\xE2', '\xB4', '\x94', ' ', '\xE2', '\xB4', '\x96', /* �? ⴗ ⴂ ⴄ ⴅ ⴇ ⴔ ⴖ */ + '\xE2', '\xB4', '\x81', ' ', '\xE2', '\xB4', '\x97', ' ', '\xE2', '\xB4', '\x82', ' ', '\xE2', '\xB4', '\x84', ' ', '\xE2', '\xB4', '\x85', ' ', '\xE2', '\xB4', '\x87', ' ', '\xE2', '\xB4', '\x94', ' ', '\xE2', '\xB4', '\x96', /* �? ⴗ ⴂ ⴄ ⴅ ⴇ ⴔ ⴖ */ '\0', '\xE2', '\xB4', '\x88', ' ', '\xE2', '\xB4', '\x8C', ' ', '\xE2', '\xB4', '\x96', ' ', '\xE2', '\xB4', '\x8E', ' ', '\xE2', '\xB4', '\x83', ' ', '\xE2', '\xB4', '\x86', ' ', '\xE2', '\xB4', '\x8B', ' ', '\xE2', '\xB4', '\xA2', /* ⴈ ⴌ ⴖ ⴎ ⴃ ⴆ ⴋ ⴢ */ '\0', - '\xE2', '\xB4', '\x90', ' ', '\xE2', '\xB4', '\x91', ' ', '\xE2', '\xB4', '\x93', ' ', '\xE2', '\xB4', '\x95', ' ', '\xE2', '\xB4', '\x99', ' ', '\xE2', '\xB4', '\x9B', ' ', '\xE2', '\xB4', '\xA1', ' ', '\xE2', '\xB4', '\xA3', /* �? ⴑ ⴓ ⴕ ⴙ ⴛ ⴡ ⴣ */ + '\xE2', '\xB4', '\x90', ' ', '\xE2', '\xB4', '\x91', ' ', '\xE2', '\xB4', '\x93', ' ', '\xE2', '\xB4', '\x95', ' ', '\xE2', '\xB4', '\x99', ' ', '\xE2', '\xB4', '\x9B', ' ', '\xE2', '\xB4', '\xA1', ' ', '\xE2', '\xB4', '\xA3', /* �? ⴑ ⴓ ⴕ ⴙ ⴛ ⴡ ⴣ */ '\0', - '\xE2', '\xB4', '\x84', ' ', '\xE2', '\xB4', '\x85', ' ', '\xE2', '\xB4', '\x94', ' ', '\xE2', '\xB4', '\x95', ' ', '\xE2', '\xB4', '\x81', ' ', '\xE2', '\xB4', '\x82', ' ', '\xE2', '\xB4', '\x98', ' ', '\xE2', '\xB4', '\x9D', /* ⴄ ⴅ ⴔ ⴕ �? ⴂ ⴘ �? */ + '\xE2', '\xB4', '\x84', ' ', '\xE2', '\xB4', '\x85', ' ', '\xE2', '\xB4', '\x94', ' ', '\xE2', '\xB4', '\x95', ' ', '\xE2', '\xB4', '\x81', ' ', '\xE2', '\xB4', '\x82', ' ', '\xE2', '\xB4', '\x98', ' ', '\xE2', '\xB4', '\x9D', /* ⴄ ⴅ ⴔ ⴕ �? ⴂ ⴘ �? */ '\0', - '\xE1', '\xB2', '\x9C', ' ', '\xE1', '\xB2', '\x9F', ' ', '\xE1', '\xB2', '\xB3', ' ', '\xE1', '\xB2', '\xB8', ' ', '\xE1', '\xB2', '\x92', ' ', '\xE1', '\xB2', '\x94', ' ', '\xE1', '\xB2', '\x9D', ' ', '\xE1', '\xB2', '\xB4', /* Ნ Ჟ Ჳ Ჸ Გ Ე �? Ჴ */ + '\xE1', '\xB2', '\x9C', ' ', '\xE1', '\xB2', '\x9F', ' ', '\xE1', '\xB2', '\xB3', ' ', '\xE1', '\xB2', '\xB8', ' ', '\xE1', '\xB2', '\x92', ' ', '\xE1', '\xB2', '\x94', ' ', '\xE1', '\xB2', '\x9D', ' ', '\xE1', '\xB2', '\xB4', /* Ნ Ჟ Ჳ Ჸ Გ Ე �? Ჴ */ '\0', - '\xE1', '\xB2', '\x98', ' ', '\xE1', '\xB2', '\xB2', ' ', '\xE1', '\xB2', '\x9D', ' ', '\xE1', '\xB2', '\xA9', ' ', '\xE1', '\xB2', '\x9B', ' ', '\xE1', '\xB2', '\xA8', ' ', '\xE1', '\xB2', '\xAF', ' ', '\xE1', '\xB2', '\xBD', /* Ი Ჲ �? Ჩ Მ Შ Ჯ Ჽ */ + '\xE1', '\xB2', '\x98', ' ', '\xE1', '\xB2', '\xB2', ' ', '\xE1', '\xB2', '\x9D', ' ', '\xE1', '\xB2', '\xA9', ' ', '\xE1', '\xB2', '\x9B', ' ', '\xE1', '\xB2', '\xA8', ' ', '\xE1', '\xB2', '\xAF', ' ', '\xE1', '\xB2', '\xBD', /* Ი Ჲ �? Ჩ Მ Შ Ჯ Ჽ */ '\0', '\xE2', '\xB0', '\x85', ' ', '\xE2', '\xB0', '\x94', ' ', '\xE2', '\xB0', '\xAA', ' ', '\xE2', '\xB0', '\x84', ' ', '\xE2', '\xB0', '\x82', ' ', '\xE2', '\xB0', '\x8A', ' ', '\xE2', '\xB0', '\xAB', ' ', '\xE2', '\xB0', '\x8B', /* Ⰵ Ⱄ Ⱚ Ⰴ Ⰲ Ⰺ Ⱛ Ⰻ */ '\0', @@ -178,9 +178,9 @@ '\0', '\xE2', '\xB0', '\xB5', ' ', '\xE2', '\xB0', '\xB4', ' ', '\xE2', '\xB0', '\xB2', ' ', '\xE2', '\xB1', '\x9A', ' ', '\xE2', '\xB1', '\x8E', ' ', '\xE2', '\xB1', '\x91', ' ', '\xE2', '\xB0', '\xBA', ' ', '\xE2', '\xB1', '\x84', /* ⰵ ⰴ ⰲ ⱚ ⱎ ⱑ ⰺ ⱄ */ '\0', - '\xF0', '\x90', '\x8C', '\xB2', ' ', '\xF0', '\x90', '\x8C', '\xB6', ' ', '\xF0', '\x90', '\x8D', '\x80', ' ', '\xF0', '\x90', '\x8D', '\x84', ' ', '\xF0', '\x90', '\x8C', '\xB4', ' ', '\xF0', '\x90', '\x8D', '\x83', ' ', '\xF0', '\x90', '\x8D', '\x88', ' ', '\xF0', '\x90', '\x8C', '\xBE', /* �?�� �?�� �??� �??� �?�� �??� �??� �?�� */ + '\xF0', '\x90', '\x8C', '\xB2', ' ', '\xF0', '\x90', '\x8C', '\xB6', ' ', '\xF0', '\x90', '\x8D', '\x80', ' ', '\xF0', '\x90', '\x8D', '\x84', ' ', '\xF0', '\x90', '\x8C', '\xB4', ' ', '\xF0', '\x90', '\x8D', '\x83', ' ', '\xF0', '\x90', '\x8D', '\x88', ' ', '\xF0', '\x90', '\x8C', '\xBE', /* �?�� �?�� �??� �??� �?�� �??� �??� �?�� */ '\0', - '\xF0', '\x90', '\x8C', '\xB6', ' ', '\xF0', '\x90', '\x8C', '\xB4', ' ', '\xF0', '\x90', '\x8D', '\x83', ' ', '\xF0', '\x90', '\x8D', '\x88', /* �?�� �?�� �??� �??� */ + '\xF0', '\x90', '\x8C', '\xB6', ' ', '\xF0', '\x90', '\x8C', '\xB4', ' ', '\xF0', '\x90', '\x8D', '\x83', ' ', '\xF0', '\x90', '\x8D', '\x88', /* �?�� �?�� �??� �??� */ '\0', '\xCE', '\x93', ' ', '\xCE', '\x92', ' ', '\xCE', '\x95', ' ', '\xCE', '\x96', ' ', '\xCE', '\x98', ' ', '\xCE', '\x9F', ' ', '\xCE', '\xA9', /* Γ Β Ε Ζ Θ Ο Ω */ '\0', @@ -190,15 +190,15 @@ '\0', '\xCE', '\xB1', ' ', '\xCE', '\xB5', ' ', '\xCE', '\xB9', ' ', '\xCE', '\xBF', ' ', '\xCF', '\x80', ' ', '\xCF', '\x83', ' ', '\xCF', '\x84', ' ', '\xCF', '\x89', /* α ε ι ο π σ τ ω */ '\0', - '\xCE', '\xB2', ' ', '\xCE', '\xB3', ' ', '\xCE', '\xB7', ' ', '\xCE', '\xBC', ' ', '\xCF', '\x81', ' ', '\xCF', '\x86', ' ', '\xCF', '\x87', ' ', '\xCF', '\x88', /* β γ η μ �? φ χ ψ */ + '\xCE', '\xB2', ' ', '\xCE', '\xB3', ' ', '\xCE', '\xB7', ' ', '\xCE', '\xBC', ' ', '\xCF', '\x81', ' ', '\xCF', '\x86', ' ', '\xCF', '\x87', ' ', '\xCF', '\x88', /* β γ η μ �? φ χ ψ */ '\0', '\xE0', '\xAA', '\xA4', ' ', '\xE0', '\xAA', '\xA8', ' ', '\xE0', '\xAA', '\x8B', ' ', '\xE0', '\xAA', '\x8C', ' ', '\xE0', '\xAA', '\x9B', ' ', '\xE0', '\xAA', '\x9F', ' ', '\xE0', '\xAA', '\xB0', ' ', '\xE0', '\xAB', '\xA6', /* ત ન ઋ ઌ છ ટ ર ૦ */ '\0', '\xE0', '\xAA', '\x96', ' ', '\xE0', '\xAA', '\x97', ' ', '\xE0', '\xAA', '\x98', ' ', '\xE0', '\xAA', '\x9E', ' ', '\xE0', '\xAA', '\x87', ' ', '\xE0', '\xAA', '\x88', ' ', '\xE0', '\xAA', '\xA0', ' ', '\xE0', '\xAA', '\x9C', /* ખ ગ ઘ ઞ ઇ ઈ ઠ જ */ '\0', - '\xE0', '\xAA', '\x88', ' ', '\xE0', '\xAA', '\x8A', ' ', '\xE0', '\xAA', '\xBF', ' ', '\xE0', '\xAB', '\x80', ' ', '\xE0', '\xAA', '\xB2', '\xE0', '\xAB', '\x80', ' ', '\xE0', '\xAA', '\xB6', '\xE0', '\xAB', '\x8D', '\xE0', '\xAA', '\x9A', '\xE0', '\xAA', '\xBF', ' ', '\xE0', '\xAA', '\x9C', '\xE0', '\xAA', '\xBF', ' ', '\xE0', '\xAA', '\xB8', '\xE0', '\xAB', '\x80', /* ઈ ઊ િ ી લી શ�?ચિ જિ સી */ + '\xE0', '\xAA', '\x88', ' ', '\xE0', '\xAA', '\x8A', ' ', '\xE0', '\xAA', '\xBF', ' ', '\xE0', '\xAB', '\x80', ' ', '\xE0', '\xAA', '\xB2', '\xE0', '\xAB', '\x80', ' ', '\xE0', '\xAA', '\xB6', '\xE0', '\xAB', '\x8D', '\xE0', '\xAA', '\x9A', '\xE0', '\xAA', '\xBF', ' ', '\xE0', '\xAA', '\x9C', '\xE0', '\xAA', '\xBF', ' ', '\xE0', '\xAA', '\xB8', '\xE0', '\xAB', '\x80', /* ઈ ઊ િ ી લી શ�?ચિ જિ સી */ '\0', - '\xE0', '\xAB', '\x81', ' ', '\xE0', '\xAB', '\x83', ' ', '\xE0', '\xAB', '\x84', ' ', '\xE0', '\xAA', '\x96', '\xE0', '\xAB', '\x81', ' ', '\xE0', '\xAA', '\x9B', '\xE0', '\xAB', '\x83', ' ', '\xE0', '\xAA', '\x9B', '\xE0', '\xAB', '\x84', /* �? ૃ ૄ ખ�? છૃ છૄ */ + '\xE0', '\xAB', '\x81', ' ', '\xE0', '\xAB', '\x83', ' ', '\xE0', '\xAB', '\x84', ' ', '\xE0', '\xAA', '\x96', '\xE0', '\xAB', '\x81', ' ', '\xE0', '\xAA', '\x9B', '\xE0', '\xAB', '\x83', ' ', '\xE0', '\xAA', '\x9B', '\xE0', '\xAB', '\x84', /* �? ૃ ૄ ખ�? છૃ છૄ */ '\0', '\xE0', '\xAB', '\xA6', ' ', '\xE0', '\xAB', '\xA7', ' ', '\xE0', '\xAB', '\xA8', ' ', '\xE0', '\xAB', '\xA9', ' ', '\xE0', '\xAB', '\xAD', /* ૦ ૧ ૨ ૩ ૭ */ '\0', @@ -206,25 +206,25 @@ '\0', '\xE0', '\xA8', '\x95', ' ', '\xE0', '\xA8', '\x97', ' ', '\xE0', '\xA8', '\x99', ' ', '\xE0', '\xA8', '\x9A', ' ', '\xE0', '\xA8', '\x9C', ' ', '\xE0', '\xA8', '\xA4', ' ', '\xE0', '\xA8', '\xA7', ' ', '\xE0', '\xA8', '\xB8', /* ਕ ਗ ਙ ਚ ਜ ਤ ਧ ਸ */ '\0', - '\xE0', '\xA8', '\x87', ' ', '\xE0', '\xA8', '\x88', ' ', '\xE0', '\xA8', '\x89', ' ', '\xE0', '\xA8', '\x8F', ' ', '\xE0', '\xA8', '\x93', ' ', '\xE0', '\xA9', '\xB3', ' ', '\xE0', '\xA8', '\xBF', ' ', '\xE0', '\xA9', '\x80', /* ਇ ਈ ਉ �? ਓ ੳ ਿ ੀ */ + '\xE0', '\xA8', '\x87', ' ', '\xE0', '\xA8', '\x88', ' ', '\xE0', '\xA8', '\x89', ' ', '\xE0', '\xA8', '\x8F', ' ', '\xE0', '\xA8', '\x93', ' ', '\xE0', '\xA9', '\xB3', ' ', '\xE0', '\xA8', '\xBF', ' ', '\xE0', '\xA9', '\x80', /* ਇ ਈ ਉ �? ਓ ੳ ਿ ੀ */ '\0', - '\xE0', '\xA8', '\x85', ' ', '\xE0', '\xA8', '\x8F', ' ', '\xE0', '\xA8', '\x93', ' ', '\xE0', '\xA8', '\x97', ' ', '\xE0', '\xA8', '\x9C', ' ', '\xE0', '\xA8', '\xA0', ' ', '\xE0', '\xA8', '\xB0', ' ', '\xE0', '\xA8', '\xB8', /* ਅ �? ਓ ਗ ਜ ਠ ਰ ਸ */ + '\xE0', '\xA8', '\x85', ' ', '\xE0', '\xA8', '\x8F', ' ', '\xE0', '\xA8', '\x93', ' ', '\xE0', '\xA8', '\x97', ' ', '\xE0', '\xA8', '\x9C', ' ', '\xE0', '\xA8', '\xA0', ' ', '\xE0', '\xA8', '\xB0', ' ', '\xE0', '\xA8', '\xB8', /* ਅ �? ਓ ਗ ਜ ਠ ਰ ਸ */ '\0', '\xE0', '\xA9', '\xA6', ' ', '\xE0', '\xA9', '\xA7', ' ', '\xE0', '\xA9', '\xA8', ' ', '\xE0', '\xA9', '\xA9', ' ', '\xE0', '\xA9', '\xAD', /* ੦ ੧ ੨ ੩ ੭ */ '\0', - '\xD7', '\x91', ' ', '\xD7', '\x93', ' ', '\xD7', '\x94', ' ', '\xD7', '\x97', ' ', '\xD7', '\x9A', ' ', '\xD7', '\x9B', ' ', '\xD7', '\x9D', ' ', '\xD7', '\xA1', /* ב ד ה ח ך כ �? ס */ + '\xD7', '\x91', ' ', '\xD7', '\x93', ' ', '\xD7', '\x94', ' ', '\xD7', '\x97', ' ', '\xD7', '\x9A', ' ', '\xD7', '\x9B', ' ', '\xD7', '\x9D', ' ', '\xD7', '\xA1', /* ב ד ה ח ך כ �? ס */ '\0', - '\xD7', '\x91', ' ', '\xD7', '\x98', ' ', '\xD7', '\x9B', ' ', '\xD7', '\x9D', ' ', '\xD7', '\xA1', ' ', '\xD7', '\xA6', /* ב ט כ �? ס צ */ + '\xD7', '\x91', ' ', '\xD7', '\x98', ' ', '\xD7', '\x9B', ' ', '\xD7', '\x9D', ' ', '\xD7', '\xA1', ' ', '\xD7', '\xA6', /* ב ט כ �? ס צ */ '\0', '\xD7', '\xA7', ' ', '\xD7', '\x9A', ' ', '\xD7', '\x9F', ' ', '\xD7', '\xA3', ' ', '\xD7', '\xA5', /* ק ך ן ף ץ */ '\0', - '\xE0', '\xB2', '\x87', ' ', '\xE0', '\xB2', '\x8A', ' ', '\xE0', '\xB2', '\x90', ' ', '\xE0', '\xB2', '\xA3', ' ', '\xE0', '\xB2', '\xB8', '\xE0', '\xB2', '\xBE', ' ', '\xE0', '\xB2', '\xA8', '\xE0', '\xB2', '\xBE', ' ', '\xE0', '\xB2', '\xA6', '\xE0', '\xB2', '\xBE', ' ', '\xE0', '\xB2', '\xB0', '\xE0', '\xB2', '\xBE', /* ಇ ಊ �? ಣ ಸಾ ನಾ ದಾ ರಾ */ + '\xE0', '\xB2', '\x87', ' ', '\xE0', '\xB2', '\x8A', ' ', '\xE0', '\xB2', '\x90', ' ', '\xE0', '\xB2', '\xA3', ' ', '\xE0', '\xB2', '\xB8', '\xE0', '\xB2', '\xBE', ' ', '\xE0', '\xB2', '\xA8', '\xE0', '\xB2', '\xBE', ' ', '\xE0', '\xB2', '\xA6', '\xE0', '\xB2', '\xBE', ' ', '\xE0', '\xB2', '\xB0', '\xE0', '\xB2', '\xBE', /* ಇ ಊ �? ಣ ಸಾ ನಾ ದಾ ರಾ */ '\0', '\xE0', '\xB2', '\x85', ' ', '\xE0', '\xB2', '\x89', ' ', '\xE0', '\xB2', '\x8E', ' ', '\xE0', '\xB2', '\xB2', ' ', '\xE0', '\xB3', '\xA6', ' ', '\xE0', '\xB3', '\xA8', ' ', '\xE0', '\xB3', '\xAC', ' ', '\xE0', '\xB3', '\xAD', /* ಅ ಉ ಎ ಲ ೦ ೨ ೬ ೭ */ '\0', - '\xEA', '\xA4', '\x85', ' ', '\xEA', '\xA4', '\x8F', ' ', '\xEA', '\xA4', '\x81', ' ', '\xEA', '\xA4', '\x8B', ' ', '\xEA', '\xA4', '\x80', ' ', '\xEA', '\xA4', '\x8D', /* ꤅ �? �? ꤋ ꤀ �? */ + '\xEA', '\xA4', '\x85', ' ', '\xEA', '\xA4', '\x8F', ' ', '\xEA', '\xA4', '\x81', ' ', '\xEA', '\xA4', '\x8B', ' ', '\xEA', '\xA4', '\x80', ' ', '\xEA', '\xA4', '\x8D', /* ꤅ �? �? ꤋ ꤀ �? */ '\0', - '\xEA', '\xA4', '\x88', ' ', '\xEA', '\xA4', '\x98', ' ', '\xEA', '\xA4', '\x80', ' ', '\xEA', '\xA4', '\x8D', ' ', '\xEA', '\xA4', '\xA2', /* ꤈ ꤘ ꤀ �? ꤢ */ + '\xEA', '\xA4', '\x88', ' ', '\xEA', '\xA4', '\x98', ' ', '\xEA', '\xA4', '\x80', ' ', '\xEA', '\xA4', '\x8D', ' ', '\xEA', '\xA4', '\xA2', /* ꤈ ꤘ ꤀ �? ꤢ */ '\0', '\xEA', '\xA4', '\x96', ' ', '\xEA', '\xA4', '\xA1', /* ꤖ ꤡ */ '\0', @@ -232,15 +232,15 @@ '\0', '\xEA', '\xA4', '\x91', '\xEA', '\xA4', '\xAC', ' ', '\xEA', '\xA4', '\x9C', '\xEA', '\xA4', '\xAD', ' ', '\xEA', '\xA4', '\x94', '\xEA', '\xA4', '\xAC', /* ꤑ꤬ ꤜ꤭ ꤔ꤬ */ '\0', - '\xE1', '\x9E', '\x81', ' ', '\xE1', '\x9E', '\x91', ' ', '\xE1', '\x9E', '\x93', ' ', '\xE1', '\x9E', '\xA7', ' ', '\xE1', '\x9E', '\xA9', ' ', '\xE1', '\x9E', '\xB6', /* �? ទ ន ឧ ឩ ា */ + '\xE1', '\x9E', '\x81', ' ', '\xE1', '\x9E', '\x91', ' ', '\xE1', '\x9E', '\x93', ' ', '\xE1', '\x9E', '\xA7', ' ', '\xE1', '\x9E', '\xA9', ' ', '\xE1', '\x9E', '\xB6', /* �? ទ ន ឧ ឩ ា */ '\0', - '\xE1', '\x9E', '\x80', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x80', ' ', '\xE1', '\x9E', '\x80', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x81', ' ', '\xE1', '\x9E', '\x80', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x82', ' ', '\xE1', '\x9E', '\x80', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x90', /* ក្ក ក្�? ក្គ ក្�? */ + '\xE1', '\x9E', '\x80', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x80', ' ', '\xE1', '\x9E', '\x80', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x81', ' ', '\xE1', '\x9E', '\x80', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x82', ' ', '\xE1', '\x9E', '\x80', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x90', /* ក្ក ក្�? ក្គ ក្�? */ '\0', - '\xE1', '\x9E', '\x81', ' ', '\xE1', '\x9E', '\x83', ' ', '\xE1', '\x9E', '\x85', ' ', '\xE1', '\x9E', '\x8B', ' ', '\xE1', '\x9E', '\x94', ' ', '\xE1', '\x9E', '\x98', ' ', '\xE1', '\x9E', '\x99', ' ', '\xE1', '\x9E', '\xB2', /* �? ឃ ច ឋ ប ម យ ឲ */ + '\xE1', '\x9E', '\x81', ' ', '\xE1', '\x9E', '\x83', ' ', '\xE1', '\x9E', '\x85', ' ', '\xE1', '\x9E', '\x8B', ' ', '\xE1', '\x9E', '\x94', ' ', '\xE1', '\x9E', '\x98', ' ', '\xE1', '\x9E', '\x99', ' ', '\xE1', '\x9E', '\xB2', /* �? ឃ ច ឋ ប ម យ ឲ */ '\0', - '\xE1', '\x9E', '\x8F', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x9A', ' ', '\xE1', '\x9E', '\x9A', '\xE1', '\x9F', '\x80', ' ', '\xE1', '\x9E', '\xB2', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x99', ' ', '\xE1', '\x9E', '\xA2', '\xE1', '\x9E', '\xBF', /* �?្រ រៀ ឲ្យ អឿ */ + '\xE1', '\x9E', '\x8F', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x9A', ' ', '\xE1', '\x9E', '\x9A', '\xE1', '\x9F', '\x80', ' ', '\xE1', '\x9E', '\xB2', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x99', ' ', '\xE1', '\x9E', '\xA2', '\xE1', '\x9E', '\xBF', /* �?្រ រៀ ឲ្យ អឿ */ '\0', - '\xE1', '\x9E', '\x93', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x8F', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x9A', '\xE1', '\x9F', '\x83', ' ', '\xE1', '\x9E', '\x84', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x81', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x99', ' ', '\xE1', '\x9E', '\x80', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x94', '\xE1', '\x9F', '\x80', ' ', '\xE1', '\x9E', '\x85', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x9A', '\xE1', '\x9F', '\x80', ' ', '\xE1', '\x9E', '\x93', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x8F', '\xE1', '\x9E', '\xBF', ' ', '\xE1', '\x9E', '\x9B', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x94', '\xE1', '\x9E', '\xBF', /* ន្�?្រៃ ង្�?្យ ក្បៀ ច្រៀ ន្�?ឿ ល្បឿ */ + '\xE1', '\x9E', '\x93', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x8F', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x9A', '\xE1', '\x9F', '\x83', ' ', '\xE1', '\x9E', '\x84', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x81', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x99', ' ', '\xE1', '\x9E', '\x80', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x94', '\xE1', '\x9F', '\x80', ' ', '\xE1', '\x9E', '\x85', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x9A', '\xE1', '\x9F', '\x80', ' ', '\xE1', '\x9E', '\x93', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x8F', '\xE1', '\x9E', '\xBF', ' ', '\xE1', '\x9E', '\x9B', '\xE1', '\x9F', '\x92', '\xE1', '\x9E', '\x94', '\xE1', '\x9E', '\xBF', /* ន្�?្រៃ ង្�?្យ ក្បៀ ច្រៀ ន្�?ឿ ល្បឿ */ '\0', '\xE1', '\xA7', '\xA0', ' ', '\xE1', '\xA7', '\xA1', /* ᧠ ᧡ */ '\0', @@ -248,9 +248,9 @@ '\0', '\xE0', '\xBA', '\xB2', ' ', '\xE0', '\xBA', '\x94', ' ', '\xE0', '\xBA', '\xAD', ' ', '\xE0', '\xBA', '\xA1', ' ', '\xE0', '\xBA', '\xA5', ' ', '\xE0', '\xBA', '\xA7', ' ', '\xE0', '\xBA', '\xA3', ' ', '\xE0', '\xBA', '\x87', /* າ ດ ອ ມ ລ ວ ຣ ງ */ '\0', - '\xE0', '\xBA', '\xB2', ' ', '\xE0', '\xBA', '\xAD', ' ', '\xE0', '\xBA', '\x9A', ' ', '\xE0', '\xBA', '\x8D', ' ', '\xE0', '\xBA', '\xA3', ' ', '\xE0', '\xBA', '\xAE', ' ', '\xE0', '\xBA', '\xA7', ' ', '\xE0', '\xBA', '\xA2', /* າ ອ ບ �? ຣ ຮ ວ ຢ */ + '\xE0', '\xBA', '\xB2', ' ', '\xE0', '\xBA', '\xAD', ' ', '\xE0', '\xBA', '\x9A', ' ', '\xE0', '\xBA', '\x8D', ' ', '\xE0', '\xBA', '\xA3', ' ', '\xE0', '\xBA', '\xAE', ' ', '\xE0', '\xBA', '\xA7', ' ', '\xE0', '\xBA', '\xA2', /* າ ອ ບ �? ຣ ຮ ວ ຢ */ '\0', - '\xE0', '\xBA', '\x9B', ' ', '\xE0', '\xBA', '\xA2', ' ', '\xE0', '\xBA', '\x9F', ' ', '\xE0', '\xBA', '\x9D', /* ປ ຢ ຟ �? */ + '\xE0', '\xBA', '\x9B', ' ', '\xE0', '\xBA', '\xA2', ' ', '\xE0', '\xBA', '\x9F', ' ', '\xE0', '\xBA', '\x9D', /* ປ ຢ ຟ �? */ '\0', '\xE0', '\xBB', '\x82', ' ', '\xE0', '\xBB', '\x84', ' ', '\xE0', '\xBB', '\x83', /* ໂ ໄ ໃ */ '\0', @@ -270,35 +270,35 @@ '\0', '\xE2', '\x82', '\x80', ' ', '\xE2', '\x82', '\x83', ' ', '\xE2', '\x82', '\x85', ' ', '\xE2', '\x82', '\x87', ' ', '\xE2', '\x82', '\x88', /* ₀ ₃ ₅ ₇ ₈ */ '\0', - '\xE2', '\x82', '\x80', ' ', '\xE2', '\x82', '\x81', ' ', '\xE2', '\x82', '\x82', ' ', '\xE2', '\x82', '\x83', ' ', '\xE2', '\x82', '\x88', /* ₀ �? ₂ ₃ ₈ */ + '\xE2', '\x82', '\x80', ' ', '\xE2', '\x82', '\x81', ' ', '\xE2', '\x82', '\x82', ' ', '\xE2', '\x82', '\x83', ' ', '\xE2', '\x82', '\x88', /* ₀ �? ₂ ₃ ₈ */ '\0', '\xE1', '\xB5', '\xA2', ' ', '\xE2', '\xB1', '\xBC', ' ', '\xE2', '\x82', '\x95', ' ', '\xE2', '\x82', '\x96', ' ', '\xE2', '\x82', '\x97', /* ᵢ ⱼ ₕ ₖ ₗ */ '\0', - '\xE2', '\x82', '\x90', ' ', '\xE2', '\x82', '\x91', ' ', '\xE2', '\x82', '\x92', ' ', '\xE2', '\x82', '\x93', ' ', '\xE2', '\x82', '\x99', ' ', '\xE2', '\x82', '\x9B', ' ', '\xE1', '\xB5', '\xA5', ' ', '\xE1', '\xB5', '\xA4', ' ', '\xE1', '\xB5', '\xA3', /* �? ₑ ₒ ₓ ₙ ₛ ᵥ ᵤ ᵣ */ + '\xE2', '\x82', '\x90', ' ', '\xE2', '\x82', '\x91', ' ', '\xE2', '\x82', '\x92', ' ', '\xE2', '\x82', '\x93', ' ', '\xE2', '\x82', '\x99', ' ', '\xE2', '\x82', '\x9B', ' ', '\xE1', '\xB5', '\xA5', ' ', '\xE1', '\xB5', '\xA4', ' ', '\xE1', '\xB5', '\xA3', /* �? ₑ ₒ ₓ ₙ ₛ ᵥ ᵤ ᵣ */ '\0', '\xE1', '\xB5', '\xA6', ' ', '\xE1', '\xB5', '\xA7', ' ', '\xE1', '\xB5', '\xA8', ' ', '\xE1', '\xB5', '\xA9', ' ', '\xE2', '\x82', '\x9A', /* ᵦ ᵧ ᵨ ᵩ ₚ */ '\0', - '\xE2', '\x81', '\xB0', ' ', '\xC2', '\xB3', ' ', '\xE2', '\x81', '\xB5', ' ', '\xE2', '\x81', '\xB7', ' ', '\xE1', '\xB5', '\x80', ' ', '\xE1', '\xB4', '\xB4', ' ', '\xE1', '\xB4', '\xB1', ' ', '\xE1', '\xB4', '\xBC', /* �?� ³ �?� �?� ᵀ ᴴ ᴱ ᴼ */ + '\xE2', '\x81', '\xB0', ' ', '\xC2', '\xB3', ' ', '\xE2', '\x81', '\xB5', ' ', '\xE2', '\x81', '\xB7', ' ', '\xE1', '\xB5', '\x80', ' ', '\xE1', '\xB4', '\xB4', ' ', '\xE1', '\xB4', '\xB1', ' ', '\xE1', '\xB4', '\xBC', /* �?� ³ �?� �?� ᵀ ᴴ ᴱ ᴼ */ '\0', - '\xE2', '\x81', '\xB0', ' ', '\xC2', '\xB9', ' ', '\xC2', '\xB2', ' ', '\xC2', '\xB3', ' ', '\xE1', '\xB4', '\xB1', ' ', '\xE1', '\xB4', '\xB8', ' ', '\xE1', '\xB4', '\xBC', ' ', '\xE1', '\xB5', '\x81', /* �?� ¹ ² ³ ᴱ ᴸ ᴼ �? */ + '\xE2', '\x81', '\xB0', ' ', '\xC2', '\xB9', ' ', '\xC2', '\xB2', ' ', '\xC2', '\xB3', ' ', '\xE1', '\xB4', '\xB1', ' ', '\xE1', '\xB4', '\xB8', ' ', '\xE1', '\xB4', '\xBC', ' ', '\xE1', '\xB5', '\x81', /* �?� ¹ ² ³ ᴱ ᴸ ᴼ �? */ '\0', - '\xE1', '\xB5', '\x87', ' ', '\xE1', '\xB5', '\x88', ' ', '\xE1', '\xB5', '\x8F', ' ', '\xCA', '\xB0', ' ', '\xCA', '\xB2', ' ', '\xE1', '\xB6', '\xA0', ' ', '\xE2', '\x81', '\xB1', /* ᵇ ᵈ �? ʰ ʲ ᶠ �?� */ + '\xE1', '\xB5', '\x87', ' ', '\xE1', '\xB5', '\x88', ' ', '\xE1', '\xB5', '\x8F', ' ', '\xCA', '\xB0', ' ', '\xCA', '\xB2', ' ', '\xE1', '\xB6', '\xA0', ' ', '\xE2', '\x81', '\xB1', /* ᵇ ᵈ �? ʰ ʲ ᶠ �?� */ '\0', '\xE1', '\xB5', '\x89', ' ', '\xE1', '\xB5', '\x92', ' ', '\xCA', '\xB3', ' ', '\xCB', '\xA2', ' ', '\xCB', '\xA3', ' ', '\xE1', '\xB6', '\x9C', ' ', '\xE1', '\xB6', '\xBB', /* ᵉ ᵒ ʳ ˢ ˣ ᶜ ᶻ */ '\0', - '\xE1', '\xB5', '\x96', ' ', '\xCA', '\xB8', ' ', '\xE1', '\xB5', '\x8D', /* ᵖ ʸ �? */ + '\xE1', '\xB5', '\x96', ' ', '\xCA', '\xB8', ' ', '\xE1', '\xB5', '\x8D', /* ᵖ ʸ �? */ '\0', '\xEA', '\x93', '\xA1', ' ', '\xEA', '\x93', '\xA7', ' ', '\xEA', '\x93', '\xB1', ' ', '\xEA', '\x93', '\xB6', ' ', '\xEA', '\x93', '\xA9', ' ', '\xEA', '\x93', '\x9A', ' ', '\xEA', '\x93', '\xB5', ' ', '\xEA', '\x93', '\xB3', /* ꓡ ꓧ ꓱ ꓶ ꓩ ꓚ ꓵ ꓳ */ '\0', '\xEA', '\x93', '\x95', ' ', '\xEA', '\x93', '\x9C', ' ', '\xEA', '\x93', '\x9E', ' ', '\xEA', '\x93', '\xA1', ' ', '\xEA', '\x93', '\x9B', ' ', '\xEA', '\x93', '\xA2', ' ', '\xEA', '\x93', '\xB3', ' ', '\xEA', '\x93', '\xB4', /* ꓕ ꓜ ꓞ ꓡ ꓛ ꓢ ꓳ ꓴ */ '\0', - '\xE0', '\xB4', '\x92', ' ', '\xE0', '\xB4', '\x9F', ' ', '\xE0', '\xB4', '\xA0', ' ', '\xE0', '\xB4', '\xB1', ' ', '\xE0', '\xB4', '\x9A', ' ', '\xE0', '\xB4', '\xAA', ' ', '\xE0', '\xB4', '\x9A', '\xE0', '\xB5', '\x8D', '\xE0', '\xB4', '\x9A', ' ', '\xE0', '\xB4', '\xAA', '\xE0', '\xB5', '\x8D', '\xE0', '\xB4', '\xAA', /* ഒ ട ഠ റ ച പ ച�?ച പ�?പ */ + '\xE0', '\xB4', '\x92', ' ', '\xE0', '\xB4', '\x9F', ' ', '\xE0', '\xB4', '\xA0', ' ', '\xE0', '\xB4', '\xB1', ' ', '\xE0', '\xB4', '\x9A', ' ', '\xE0', '\xB4', '\xAA', ' ', '\xE0', '\xB4', '\x9A', '\xE0', '\xB5', '\x8D', '\xE0', '\xB4', '\x9A', ' ', '\xE0', '\xB4', '\xAA', '\xE0', '\xB5', '\x8D', '\xE0', '\xB4', '\xAA', /* ഒ ട ഠ റ ച പ ച�?ച പ�?പ */ '\0', '\xE0', '\xB4', '\x9F', ' ', '\xE0', '\xB4', '\xA0', ' ', '\xE0', '\xB4', '\xA7', ' ', '\xE0', '\xB4', '\xB6', ' ', '\xE0', '\xB4', '\x98', ' ', '\xE0', '\xB4', '\x9A', ' ', '\xE0', '\xB4', '\xA5', ' ', '\xE0', '\xB4', '\xB2', /* ട ഠ ധ ശ ഘ ച ഥ ല */ '\0', - '\xF0', '\x96', '\xB9', '\x80', ' ', '\xF0', '\x96', '\xB9', '\x81', ' ', '\xF0', '\x96', '\xB9', '\x82', ' ', '\xF0', '\x96', '\xB9', '\x83', ' ', '\xF0', '\x96', '\xB9', '\x8F', ' ', '\xF0', '\x96', '\xB9', '\x9A', ' ', '\xF0', '\x96', '\xB9', '\x9F', /* 𖹀 �? 𖹂 𖹃 �? 𖹚 𖹟 */ + '\xF0', '\x96', '\xB9', '\x80', ' ', '\xF0', '\x96', '\xB9', '\x81', ' ', '\xF0', '\x96', '\xB9', '\x82', ' ', '\xF0', '\x96', '\xB9', '\x83', ' ', '\xF0', '\x96', '\xB9', '\x8F', ' ', '\xF0', '\x96', '\xB9', '\x9A', ' ', '\xF0', '\x96', '\xB9', '\x9F', /* 𖹀 �? 𖹂 𖹃 �? 𖹚 𖹟 */ '\0', - '\xF0', '\x96', '\xB9', '\x80', ' ', '\xF0', '\x96', '\xB9', '\x81', ' ', '\xF0', '\x96', '\xB9', '\x82', ' ', '\xF0', '\x96', '\xB9', '\x83', ' ', '\xF0', '\x96', '\xB9', '\x8F', ' ', '\xF0', '\x96', '\xB9', '\x9A', ' ', '\xF0', '\x96', '\xB9', '\x92', ' ', '\xF0', '\x96', '\xB9', '\x93', /* 𖹀 �? 𖹂 𖹃 �? 𖹚 𖹒 𖹓 */ + '\xF0', '\x96', '\xB9', '\x80', ' ', '\xF0', '\x96', '\xB9', '\x81', ' ', '\xF0', '\x96', '\xB9', '\x82', ' ', '\xF0', '\x96', '\xB9', '\x83', ' ', '\xF0', '\x96', '\xB9', '\x8F', ' ', '\xF0', '\x96', '\xB9', '\x9A', ' ', '\xF0', '\x96', '\xB9', '\x92', ' ', '\xF0', '\x96', '\xB9', '\x93', /* 𖹀 �? 𖹂 𖹃 �? 𖹚 𖹒 𖹓 */ '\0', '\xF0', '\x96', '\xB9', '\xA4', ' ', '\xF0', '\x96', '\xB9', '\xAC', ' ', '\xF0', '\x96', '\xB9', '\xA7', ' ', '\xF0', '\x96', '\xB9', '\xB4', ' ', '\xF0', '\x96', '\xB9', '\xB6', ' ', '\xF0', '\x96', '\xB9', '\xBE', /* 𖹤 𖹬 𖹧 𖹴 𖹶 𖹾 */ '\0', @@ -308,75 +308,75 @@ '\0', '\xF0', '\x96', '\xB9', '\xA5', ' ', '\xF0', '\x96', '\xB9', '\xA8', ' ', '\xF0', '\x96', '\xB9', '\xA9', /* 𖹥 𖹨 𖹩 */ '\0', - '\xF0', '\x96', '\xBA', '\x80', ' ', '\xF0', '\x96', '\xBA', '\x85', ' ', '\xF0', '\x96', '\xBA', '\x88', ' ', '\xF0', '\x96', '\xBA', '\x84', ' ', '\xF0', '\x96', '\xBA', '\x8D', /* 𖺀 𖺅 𖺈 𖺄 �? */ + '\xF0', '\x96', '\xBA', '\x80', ' ', '\xF0', '\x96', '\xBA', '\x85', ' ', '\xF0', '\x96', '\xBA', '\x88', ' ', '\xF0', '\x96', '\xBA', '\x84', ' ', '\xF0', '\x96', '\xBA', '\x8D', /* 𖺀 𖺅 𖺈 𖺄 �? */ '\0', - '\xE1', '\xA0', '\xB3', ' ', '\xE1', '\xA0', '\xB4', ' ', '\xE1', '\xA0', '\xB6', ' ', '\xE1', '\xA0', '\xBD', ' ', '\xE1', '\xA1', '\x82', ' ', '\xE1', '\xA1', '\x8A', ' ', '\xE2', '\x80', '\x8D', '\xE1', '\xA1', '\xA1', '\xE2', '\x80', '\x8D', ' ', '\xE2', '\x80', '\x8D', '\xE1', '\xA1', '\xB3', '\xE2', '\x80', '\x8D', /* ᠳ ᠴ ᠶ ᠽ ᡂ ᡊ �?ᡡ�? �?ᡳ�? */ + '\xE1', '\xA0', '\xB3', ' ', '\xE1', '\xA0', '\xB4', ' ', '\xE1', '\xA0', '\xB6', ' ', '\xE1', '\xA0', '\xBD', ' ', '\xE1', '\xA1', '\x82', ' ', '\xE1', '\xA1', '\x8A', ' ', '\xE2', '\x80', '\x8D', '\xE1', '\xA1', '\xA1', '\xE2', '\x80', '\x8D', ' ', '\xE2', '\x80', '\x8D', '\xE1', '\xA1', '\xB3', '\xE2', '\x80', '\x8D', /* ᠳ ᠴ ᠶ ᠽ ᡂ ᡊ �?ᡡ�? �?ᡳ�? */ '\0', '\xE1', '\xA1', '\x83', /* ᡃ */ '\0', - '\xE1', '\x80', '\x81', ' ', '\xE1', '\x80', '\x82', ' ', '\xE1', '\x80', '\x84', ' ', '\xE1', '\x80', '\x92', ' ', '\xE1', '\x80', '\x9D', ' ', '\xE1', '\x81', '\xA5', ' ', '\xE1', '\x81', '\x8A', ' ', '\xE1', '\x81', '\x8B', /* �? ဂ င ဒ �? �?� �?� �?� */ + '\xE1', '\x80', '\x81', ' ', '\xE1', '\x80', '\x82', ' ', '\xE1', '\x80', '\x84', ' ', '\xE1', '\x80', '\x92', ' ', '\xE1', '\x80', '\x9D', ' ', '\xE1', '\x81', '\xA5', ' ', '\xE1', '\x81', '\x8A', ' ', '\xE1', '\x81', '\x8B', /* �? ဂ င ဒ �? �?� �?� �?� */ '\0', - '\xE1', '\x80', '\x84', ' ', '\xE1', '\x80', '\x8E', ' ', '\xE1', '\x80', '\x92', ' ', '\xE1', '\x80', '\x95', ' ', '\xE1', '\x80', '\x97', ' ', '\xE1', '\x80', '\x9D', ' ', '\xE1', '\x81', '\x8A', ' ', '\xE1', '\x81', '\x8B', /* င ဎ ဒ ပ ဗ �? �?� �?� */ + '\xE1', '\x80', '\x84', ' ', '\xE1', '\x80', '\x8E', ' ', '\xE1', '\x80', '\x92', ' ', '\xE1', '\x80', '\x95', ' ', '\xE1', '\x80', '\x97', ' ', '\xE1', '\x80', '\x9D', ' ', '\xE1', '\x81', '\x8A', ' ', '\xE1', '\x81', '\x8B', /* င ဎ ဒ ပ ဗ �? �?� �?� */ '\0', - '\xE1', '\x80', '\xA9', ' ', '\xE1', '\x80', '\xBC', ' ', '\xE1', '\x81', '\x8D', ' ', '\xE1', '\x81', '\x8F', ' ', '\xE1', '\x81', '\x86', ' ', '\xE1', '\x80', '\xAB', ' ', '\xE1', '\x80', '\xAD', /* ဩ ြ �?? �?? �?� ါ ိ */ + '\xE1', '\x80', '\xA9', ' ', '\xE1', '\x80', '\xBC', ' ', '\xE1', '\x81', '\x8D', ' ', '\xE1', '\x81', '\x8F', ' ', '\xE1', '\x81', '\x86', ' ', '\xE1', '\x80', '\xAB', ' ', '\xE1', '\x80', '\xAD', /* ဩ ြ �?? �?? �?� ါ ိ */ '\0', - '\xE1', '\x80', '\x89', ' ', '\xE1', '\x80', '\x8A', ' ', '\xE1', '\x80', '\xA5', ' ', '\xE1', '\x80', '\xA9', ' ', '\xE1', '\x80', '\xA8', ' ', '\xE1', '\x81', '\x82', ' ', '\xE1', '\x81', '\x85', ' ', '\xE1', '\x81', '\x89', /* ဉ ည ဥ ဩ ဨ �?� �?� �?� */ + '\xE1', '\x80', '\x89', ' ', '\xE1', '\x80', '\x8A', ' ', '\xE1', '\x80', '\xA5', ' ', '\xE1', '\x80', '\xA9', ' ', '\xE1', '\x80', '\xA8', ' ', '\xE1', '\x81', '\x82', ' ', '\xE1', '\x81', '\x85', ' ', '\xE1', '\x81', '\x89', /* ဉ ည ဥ ဩ ဨ �?� �?� �?� */ '\0', - '\xDF', '\x90', ' ', '\xDF', '\x89', ' ', '\xDF', '\x92', ' ', '\xDF', '\x9F', ' ', '\xDF', '\x96', ' ', '\xDF', '\x9C', ' ', '\xDF', '\xA0', ' ', '\xDF', '\xA5', /* �? ߉ ߒ ߟ ߖ ߜ ߠ ߥ */ + '\xDF', '\x90', ' ', '\xDF', '\x89', ' ', '\xDF', '\x92', ' ', '\xDF', '\x9F', ' ', '\xDF', '\x96', ' ', '\xDF', '\x9C', ' ', '\xDF', '\xA0', ' ', '\xDF', '\xA5', /* �? ߉ ߒ ߟ ߖ ߜ ߠ ߥ */ '\0', '\xDF', '\x80', ' ', '\xDF', '\x98', ' ', '\xDF', '\xA1', ' ', '\xDF', '\xA0', ' ', '\xDF', '\xA5', /* ߀ ߘ ߡ ߠ ߥ */ '\0', - '\xDF', '\x8F', ' ', '\xDF', '\x9B', ' ', '\xDF', '\x8B', /* �? ߛ ߋ */ + '\xDF', '\x8F', ' ', '\xDF', '\x9B', ' ', '\xDF', '\x8B', /* �? ߛ ߋ */ '\0', - '\xDF', '\x8E', ' ', '\xDF', '\x8F', ' ', '\xDF', '\x9B', ' ', '\xDF', '\x8B', /* ߎ �? ߛ ߋ */ + '\xDF', '\x8E', ' ', '\xDF', '\x8F', ' ', '\xDF', '\x9B', ' ', '\xDF', '\x8B', /* ߎ �? ߛ ߋ */ '\0', - '\xE1', '\xB1', '\x9B', ' ', '\xE1', '\xB1', '\x9C', ' ', '\xE1', '\xB1', '\x9D', ' ', '\xE1', '\xB1', '\xA1', ' ', '\xE1', '\xB1', '\xA2', ' ', '\xE1', '\xB1', '\xA5', /* ᱛ ᱜ �? ᱡ ᱢ ᱥ */ + '\xE1', '\xB1', '\x9B', ' ', '\xE1', '\xB1', '\x9C', ' ', '\xE1', '\xB1', '\x9D', ' ', '\xE1', '\xB1', '\xA1', ' ', '\xE1', '\xB1', '\xA2', ' ', '\xE1', '\xB1', '\xA5', /* ᱛ ᱜ �? ᱡ ᱢ ᱥ */ '\0', - '\xF0', '\x90', '\xB0', '\x97', ' ', '\xF0', '\x90', '\xB0', '\x98', ' ', '\xF0', '\x90', '\xB0', '\xA7', /* �?�� �?�� �?�� */ + '\xF0', '\x90', '\xB0', '\x97', ' ', '\xF0', '\x90', '\xB0', '\x98', ' ', '\xF0', '\x90', '\xB0', '\xA7', /* �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\xB0', '\x89', ' ', '\xF0', '\x90', '\xB0', '\x97', ' ', '\xF0', '\x90', '\xB0', '\xA6', ' ', '\xF0', '\x90', '\xB0', '\xA7', /* �?�� �?�� �?�� �?�� */ + '\xF0', '\x90', '\xB0', '\x89', ' ', '\xF0', '\x90', '\xB0', '\x97', ' ', '\xF0', '\x90', '\xB0', '\xA6', ' ', '\xF0', '\x90', '\xB0', '\xA7', /* �?�� �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\x92', '\xBE', ' ', '\xF0', '\x90', '\x93', '\x8D', ' ', '\xF0', '\x90', '\x93', '\x92', ' ', '\xF0', '\x90', '\x93', '\x93', ' ', '\xF0', '\x90', '\x92', '\xBB', ' ', '\xF0', '\x90', '\x93', '\x82', ' ', '\xF0', '\x90', '\x92', '\xB5', ' ', '\xF0', '\x90', '\x93', '\x86', /* �?�� �?�? �?�� �?�� �?�� �?�� �?�� �?�� */ + '\xF0', '\x90', '\x92', '\xBE', ' ', '\xF0', '\x90', '\x93', '\x8D', ' ', '\xF0', '\x90', '\x93', '\x92', ' ', '\xF0', '\x90', '\x93', '\x93', ' ', '\xF0', '\x90', '\x92', '\xBB', ' ', '\xF0', '\x90', '\x93', '\x82', ' ', '\xF0', '\x90', '\x92', '\xB5', ' ', '\xF0', '\x90', '\x93', '\x86', /* �?�� �?�? �?�� �?�� �?�� �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\x92', '\xB0', ' ', '\xF0', '\x90', '\x93', '\x8D', ' ', '\xF0', '\x90', '\x93', '\x82', ' ', '\xF0', '\x90', '\x92', '\xBF', ' ', '\xF0', '\x90', '\x93', '\x8E', ' ', '\xF0', '\x90', '\x92', '\xB9', /* �?�� �?�? �?�� �?�� �?�� �?�� */ + '\xF0', '\x90', '\x92', '\xB0', ' ', '\xF0', '\x90', '\x93', '\x8D', ' ', '\xF0', '\x90', '\x93', '\x82', ' ', '\xF0', '\x90', '\x92', '\xBF', ' ', '\xF0', '\x90', '\x93', '\x8E', ' ', '\xF0', '\x90', '\x92', '\xB9', /* �?�� �?�? �?�� �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\x92', '\xBC', ' ', '\xF0', '\x90', '\x92', '\xBD', ' ', '\xF0', '\x90', '\x92', '\xBE', /* �?�� �?�� �?�� */ + '\xF0', '\x90', '\x92', '\xBC', ' ', '\xF0', '\x90', '\x92', '\xBD', ' ', '\xF0', '\x90', '\x92', '\xBE', /* �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\x93', '\xB5', ' ', '\xF0', '\x90', '\x93', '\xB6', ' ', '\xF0', '\x90', '\x93', '\xBA', ' ', '\xF0', '\x90', '\x93', '\xBB', ' ', '\xF0', '\x90', '\x93', '\x9D', ' ', '\xF0', '\x90', '\x93', '\xA3', ' ', '\xF0', '\x90', '\x93', '\xAA', ' ', '\xF0', '\x90', '\x93', '\xAE', /* �?�� �?�� �?�� �?�� �?�? �?�� �?�� �?�� */ + '\xF0', '\x90', '\x93', '\xB5', ' ', '\xF0', '\x90', '\x93', '\xB6', ' ', '\xF0', '\x90', '\x93', '\xBA', ' ', '\xF0', '\x90', '\x93', '\xBB', ' ', '\xF0', '\x90', '\x93', '\x9D', ' ', '\xF0', '\x90', '\x93', '\xA3', ' ', '\xF0', '\x90', '\x93', '\xAA', ' ', '\xF0', '\x90', '\x93', '\xAE', /* �?�� �?�� �?�� �?�� �?�? �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\x93', '\x98', ' ', '\xF0', '\x90', '\x93', '\x9A', ' ', '\xF0', '\x90', '\x93', '\xA3', ' ', '\xF0', '\x90', '\x93', '\xB5', ' ', '\xF0', '\x90', '\x93', '\xA1', ' ', '\xF0', '\x90', '\x93', '\xA7', ' ', '\xF0', '\x90', '\x93', '\xAA', ' ', '\xF0', '\x90', '\x93', '\xB6', /* �?�� �?�� �?�� �?�� �?�� �?�� �?�� �?�� */ + '\xF0', '\x90', '\x93', '\x98', ' ', '\xF0', '\x90', '\x93', '\x9A', ' ', '\xF0', '\x90', '\x93', '\xA3', ' ', '\xF0', '\x90', '\x93', '\xB5', ' ', '\xF0', '\x90', '\x93', '\xA1', ' ', '\xF0', '\x90', '\x93', '\xA7', ' ', '\xF0', '\x90', '\x93', '\xAA', ' ', '\xF0', '\x90', '\x93', '\xB6', /* �?�� �?�� �?�� �?�� �?�� �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\x93', '\xA4', ' ', '\xF0', '\x90', '\x93', '\xA6', ' ', '\xF0', '\x90', '\x93', '\xB8', ' ', '\xF0', '\x90', '\x93', '\xB9', ' ', '\xF0', '\x90', '\x93', '\x9B', /* �?�� �?�� �?�� �?�� �?�� */ + '\xF0', '\x90', '\x93', '\xA4', ' ', '\xF0', '\x90', '\x93', '\xA6', ' ', '\xF0', '\x90', '\x93', '\xB8', ' ', '\xF0', '\x90', '\x93', '\xB9', ' ', '\xF0', '\x90', '\x93', '\x9B', /* �?�� �?�� �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\x93', '\xA4', ' ', '\xF0', '\x90', '\x93', '\xA5', ' ', '\xF0', '\x90', '\x93', '\xA6', /* �?�� �?�� �?�� */ + '\xF0', '\x90', '\x93', '\xA4', ' ', '\xF0', '\x90', '\x93', '\xA5', ' ', '\xF0', '\x90', '\x93', '\xA6', /* �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\x92', '\x86', ' ', '\xF0', '\x90', '\x92', '\x89', ' ', '\xF0', '\x90', '\x92', '\x90', ' ', '\xF0', '\x90', '\x92', '\x92', ' ', '\xF0', '\x90', '\x92', '\x98', ' ', '\xF0', '\x90', '\x92', '\x9B', ' ', '\xF0', '\x90', '\x92', '\xA0', ' ', '\xF0', '\x90', '\x92', '\xA3', /* �?�� �?�� �?�? �?�� �?�� �?�� �?�� �?�� */ + '\xF0', '\x90', '\x92', '\x86', ' ', '\xF0', '\x90', '\x92', '\x89', ' ', '\xF0', '\x90', '\x92', '\x90', ' ', '\xF0', '\x90', '\x92', '\x92', ' ', '\xF0', '\x90', '\x92', '\x98', ' ', '\xF0', '\x90', '\x92', '\x9B', ' ', '\xF0', '\x90', '\x92', '\xA0', ' ', '\xF0', '\x90', '\x92', '\xA3', /* �?�� �?�� �?�? �?�� �?�� �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\x92', '\x80', ' ', '\xF0', '\x90', '\x92', '\x82', ' ', '\xF0', '\x90', '\x92', '\x86', ' ', '\xF0', '\x90', '\x92', '\x88', ' ', '\xF0', '\x90', '\x92', '\x8A', ' ', '\xF0', '\x90', '\x92', '\x92', ' ', '\xF0', '\x90', '\x92', '\xA0', ' ', '\xF0', '\x90', '\x92', '\xA9', /* �?�� �?�� �?�� �?�� �?�� �?�� �?�� �?�� */ + '\xF0', '\x90', '\x92', '\x80', ' ', '\xF0', '\x90', '\x92', '\x82', ' ', '\xF0', '\x90', '\x92', '\x86', ' ', '\xF0', '\x90', '\x92', '\x88', ' ', '\xF0', '\x90', '\x92', '\x8A', ' ', '\xF0', '\x90', '\x92', '\x92', ' ', '\xF0', '\x90', '\x92', '\xA0', ' ', '\xF0', '\x90', '\x92', '\xA9', /* �?�� �?�� �?�� �?�� �?�� �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\xB4', '\x83', ' ', '\xF0', '\x90', '\xB4', '\x80', ' ', '\xF0', '\x90', '\xB4', '\x86', ' ', '\xF0', '\x90', '\xB4', '\x96', ' ', '\xF0', '\x90', '\xB4', '\x95', /* �?�� �?�� �?�� �?�� �?�� */ + '\xF0', '\x90', '\xB4', '\x83', ' ', '\xF0', '\x90', '\xB4', '\x80', ' ', '\xF0', '\x90', '\xB4', '\x86', ' ', '\xF0', '\x90', '\xB4', '\x96', ' ', '\xF0', '\x90', '\xB4', '\x95', /* �?�� �?�� �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\xB4', '\x94', ' ', '\xF0', '\x90', '\xB4', '\x96', ' ', '\xF0', '\x90', '\xB4', '\x95', ' ', '\xF0', '\x90', '\xB4', '\x91', ' ', '\xF0', '\x90', '\xB4', '\x90', /* �?�� �?�� �?�� �?�� �?�? */ + '\xF0', '\x90', '\xB4', '\x94', ' ', '\xF0', '\x90', '\xB4', '\x96', ' ', '\xF0', '\x90', '\xB4', '\x95', ' ', '\xF0', '\x90', '\xB4', '\x91', ' ', '\xF0', '\x90', '\xB4', '\x90', /* �?�� �?�� �?�� �?�� �?�? */ '\0', '\xD9', '\x80', /* ـ */ '\0', - '\xEA', '\xA2', '\x9C', ' ', '\xEA', '\xA2', '\x9E', ' ', '\xEA', '\xA2', '\xB3', ' ', '\xEA', '\xA2', '\x82', ' ', '\xEA', '\xA2', '\x96', ' ', '\xEA', '\xA2', '\x92', ' ', '\xEA', '\xA2', '\x9D', ' ', '\xEA', '\xA2', '\x9B', /* ꢜ ꢞ ꢳ ꢂ ꢖ ꢒ �? ꢛ */ + '\xEA', '\xA2', '\x9C', ' ', '\xEA', '\xA2', '\x9E', ' ', '\xEA', '\xA2', '\xB3', ' ', '\xEA', '\xA2', '\x82', ' ', '\xEA', '\xA2', '\x96', ' ', '\xEA', '\xA2', '\x92', ' ', '\xEA', '\xA2', '\x9D', ' ', '\xEA', '\xA2', '\x9B', /* ꢜ ꢞ ꢳ ꢂ ꢖ ꢒ �? ꢛ */ '\0', '\xEA', '\xA2', '\x82', ' ', '\xEA', '\xA2', '\xA8', ' ', '\xEA', '\xA2', '\xBA', ' ', '\xEA', '\xA2', '\xA4', ' ', '\xEA', '\xA2', '\x8E', /* ꢂ ꢨ ꢺ ꢤ ꢎ */ '\0', - '\xF0', '\x90', '\x91', '\x95', ' ', '\xF0', '\x90', '\x91', '\x99', /* �?�� �?�� */ + '\xF0', '\x90', '\x91', '\x95', ' ', '\xF0', '\x90', '\x91', '\x99', /* �?�� �?�� */ '\0', - '\xF0', '\x90', '\x91', '\x94', ' ', '\xF0', '\x90', '\x91', '\x96', ' ', '\xF0', '\x90', '\x91', '\x97', ' ', '\xF0', '\x90', '\x91', '\xB9', ' ', '\xF0', '\x90', '\x91', '\xBB', /* �?�� �?�� �?�� �?�� �?�� */ + '\xF0', '\x90', '\x91', '\x94', ' ', '\xF0', '\x90', '\x91', '\x96', ' ', '\xF0', '\x90', '\x91', '\x97', ' ', '\xF0', '\x90', '\x91', '\xB9', ' ', '\xF0', '\x90', '\x91', '\xBB', /* �?�� �?�� �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\x91', '\x9F', ' ', '\xF0', '\x90', '\x91', '\xA3', /* �?�� �?�� */ + '\xF0', '\x90', '\x91', '\x9F', ' ', '\xF0', '\x90', '\x91', '\xA3', /* �?�� �?�� */ '\0', - '\xF0', '\x90', '\x91', '\xB1', ' ', '\xF0', '\x90', '\x91', '\xB2', ' ', '\xF0', '\x90', '\x91', '\xB3', ' ', '\xF0', '\x90', '\x91', '\xB4', ' ', '\xF0', '\x90', '\x91', '\xB8', ' ', '\xF0', '\x90', '\x91', '\xBA', ' ', '\xF0', '\x90', '\x91', '\xBC', /* �?�� �?�� �?�� �?�� �?�� �?�� �?�� */ + '\xF0', '\x90', '\x91', '\xB1', ' ', '\xF0', '\x90', '\x91', '\xB2', ' ', '\xF0', '\x90', '\x91', '\xB3', ' ', '\xF0', '\x90', '\x91', '\xB4', ' ', '\xF0', '\x90', '\x91', '\xB8', ' ', '\xF0', '\x90', '\x91', '\xBA', ' ', '\xF0', '\x90', '\x91', '\xBC', /* �?�� �?�� �?�� �?�� �?�� �?�� �?�� */ '\0', - '\xF0', '\x90', '\x91', '\xB4', ' ', '\xF0', '\x90', '\x91', '\xBB', ' ', '\xF0', '\x90', '\x91', '\xB9', /* �?�� �?�� �?�� */ + '\xF0', '\x90', '\x91', '\xB4', ' ', '\xF0', '\x90', '\x91', '\xBB', ' ', '\xF0', '\x90', '\x91', '\xB9', /* �?�� �?�� �?�� */ '\0', - '\xE0', '\xB6', '\x89', ' ', '\xE0', '\xB6', '\x9A', ' ', '\xE0', '\xB6', '\x9D', ' ', '\xE0', '\xB6', '\xB3', ' ', '\xE0', '\xB6', '\xB4', ' ', '\xE0', '\xB6', '\xBA', ' ', '\xE0', '\xB6', '\xBD', ' ', '\xE0', '\xB7', '\x86', /* ඉ ක �? ඳ ප ය ල ෆ */ + '\xE0', '\xB6', '\x89', ' ', '\xE0', '\xB6', '\x9A', ' ', '\xE0', '\xB6', '\x9D', ' ', '\xE0', '\xB6', '\xB3', ' ', '\xE0', '\xB6', '\xB4', ' ', '\xE0', '\xB6', '\xBA', ' ', '\xE0', '\xB6', '\xBD', ' ', '\xE0', '\xB7', '\x86', /* ඉ ක �? ඳ ප ය ල ෆ */ '\0', - '\xE0', '\xB6', '\x91', ' ', '\xE0', '\xB6', '\x94', ' ', '\xE0', '\xB6', '\x9D', ' ', '\xE0', '\xB6', '\xA2', ' ', '\xE0', '\xB6', '\xA7', ' ', '\xE0', '\xB6', '\xAE', ' ', '\xE0', '\xB6', '\xB0', ' ', '\xE0', '\xB6', '\xBB', /* එ ඔ �? ජ ට ථ ධ ර */ + '\xE0', '\xB6', '\x91', ' ', '\xE0', '\xB6', '\x94', ' ', '\xE0', '\xB6', '\x9D', ' ', '\xE0', '\xB6', '\xA2', ' ', '\xE0', '\xB6', '\xA7', ' ', '\xE0', '\xB6', '\xAE', ' ', '\xE0', '\xB6', '\xB0', ' ', '\xE0', '\xB6', '\xBB', /* එ ඔ �? ජ ට ථ ධ ර */ '\0', '\xE0', '\xB6', '\xAF', ' ', '\xE0', '\xB6', '\xB3', ' ', '\xE0', '\xB6', '\x8B', ' ', '\xE0', '\xB6', '\xBD', ' ', '\xE0', '\xB6', '\xAD', '\xE0', '\xB7', '\x96', ' ', '\xE0', '\xB6', '\xAD', '\xE0', '\xB7', '\x94', ' ', '\xE0', '\xB6', '\xB6', '\xE0', '\xB7', '\x94', ' ', '\xE0', '\xB6', '\xAF', '\xE0', '\xB7', '\x94', /* ද ඳ උ ල තූ තු බු දු */ '\0', @@ -398,62 +398,62 @@ '\0', '\xE0', '\xB0', '\x85', ' ', '\xE0', '\xB0', '\x95', ' ', '\xE0', '\xB0', '\x9A', ' ', '\xE0', '\xB0', '\xB0', ' ', '\xE0', '\xB0', '\xBD', ' ', '\xE0', '\xB1', '\xA8', ' ', '\xE0', '\xB1', '\xAC', /* అ క చ ర ఽ ౨ ౬ */ '\0', - '\xE0', '\xB8', '\x9A', ' ', '\xE0', '\xB9', '\x80', ' ', '\xE0', '\xB9', '\x81', ' ', '\xE0', '\xB8', '\xAD', ' ', '\xE0', '\xB8', '\x81', ' ', '\xE0', '\xB8', '\xB2', /* บ เ �? อ �? า */ + '\xE0', '\xB8', '\x9A', ' ', '\xE0', '\xB9', '\x80', ' ', '\xE0', '\xB9', '\x81', ' ', '\xE0', '\xB8', '\xAD', ' ', '\xE0', '\xB8', '\x81', ' ', '\xE0', '\xB8', '\xB2', /* บ เ �? อ �? า */ '\0', '\xE0', '\xB8', '\x9A', ' ', '\xE0', '\xB8', '\x9B', ' ', '\xE0', '\xB8', '\xA9', ' ', '\xE0', '\xB8', '\xAF', ' ', '\xE0', '\xB8', '\xAD', ' ', '\xE0', '\xB8', '\xA2', ' ', '\xE0', '\xB8', '\xAE', /* บ ป ษ ฯ อ ย ฮ */ '\0', - '\xE0', '\xB8', '\x9B', ' ', '\xE0', '\xB8', '\x9D', ' ', '\xE0', '\xB8', '\x9F', /* ป �? ฟ */ + '\xE0', '\xB8', '\x9B', ' ', '\xE0', '\xB8', '\x9D', ' ', '\xE0', '\xB8', '\x9F', /* ป �? ฟ */ '\0', '\xE0', '\xB9', '\x82', ' ', '\xE0', '\xB9', '\x83', ' ', '\xE0', '\xB9', '\x84', /* โ ใ ไ */ '\0', - '\xE0', '\xB8', '\x8E', ' ', '\xE0', '\xB8', '\x8F', ' ', '\xE0', '\xB8', '\xA4', ' ', '\xE0', '\xB8', '\xA6', /* ฎ �? ฤ ฦ */ + '\xE0', '\xB8', '\x8E', ' ', '\xE0', '\xB8', '\x8F', ' ', '\xE0', '\xB8', '\xA4', ' ', '\xE0', '\xB8', '\xA6', /* ฎ �? ฤ ฦ */ '\0', - '\xE0', '\xB8', '\x8D', ' ', '\xE0', '\xB8', '\x90', /* �? �? */ + '\xE0', '\xB8', '\x8D', ' ', '\xE0', '\xB8', '\x90', /* �? �? */ '\0', - '\xE0', '\xB9', '\x90', ' ', '\xE0', '\xB9', '\x91', ' ', '\xE0', '\xB9', '\x93', /* �? ๑ ๓ */ + '\xE0', '\xB9', '\x90', ' ', '\xE0', '\xB9', '\x91', ' ', '\xE0', '\xB9', '\x93', /* �? ๑ ๓ */ '\0', '\xE2', '\xB5', '\x94', ' ', '\xE2', '\xB5', '\x99', ' ', '\xE2', '\xB5', '\x9B', ' ', '\xE2', '\xB5', '\x9E', ' ', '\xE2', '\xB4', '\xB5', ' ', '\xE2', '\xB4', '\xBC', ' ', '\xE2', '\xB4', '\xB9', ' ', '\xE2', '\xB5', '\x8E', /* ⵔ ⵙ ⵛ ⵞ ⴵ ⴼ ⴹ ⵎ */ '\0', - '\xEA', '\x97', '\x8D', ' ', '\xEA', '\x98', '\x96', ' ', '\xEA', '\x98', '\x99', ' ', '\xEA', '\x98', '\x9C', ' ', '\xEA', '\x96', '\x9C', ' ', '\xEA', '\x96', '\x9D', ' ', '\xEA', '\x94', '\x85', ' ', '\xEA', '\x95', '\xA2', /* �? ꘖ ꘙ ꘜ ꖜ �? ꔅ ꕢ */ + '\xEA', '\x97', '\x8D', ' ', '\xEA', '\x98', '\x96', ' ', '\xEA', '\x98', '\x99', ' ', '\xEA', '\x98', '\x9C', ' ', '\xEA', '\x96', '\x9C', ' ', '\xEA', '\x96', '\x9D', ' ', '\xEA', '\x94', '\x85', ' ', '\xEA', '\x95', '\xA2', /* �? ꘖ ꘙ ꘜ ꖜ �? ꔅ ꕢ */ '\0', - '\xEA', '\x97', '\x8D', ' ', '\xEA', '\x98', '\x96', ' ', '\xEA', '\x98', '\x99', ' ', '\xEA', '\x97', '\x9E', ' ', '\xEA', '\x94', '\x85', ' ', '\xEA', '\x95', '\xA2', ' ', '\xEA', '\x96', '\x9C', ' ', '\xEA', '\x94', '\x86', /* �? ꘖ ꘙ ꗞ ꔅ ꕢ ꖜ ꔆ */ + '\xEA', '\x97', '\x8D', ' ', '\xEA', '\x98', '\x96', ' ', '\xEA', '\x98', '\x99', ' ', '\xEA', '\x97', '\x9E', ' ', '\xEA', '\x94', '\x85', ' ', '\xEA', '\x95', '\xA2', ' ', '\xEA', '\x96', '\x9C', ' ', '\xEA', '\x94', '\x86', /* �? ꘖ ꘙ ꗞ ꔅ ꕢ ꖜ ꔆ */ #ifdef AF_CONFIG_OPTION_CJK '\0', '\xE4', '\xBB', '\x96', ' ', '\xE4', '\xBB', '\xAC', ' ', '\xE4', '\xBD', '\xA0', ' ', '\xE4', '\xBE', '\x86', ' ', '\xE5', '\x80', '\x91', ' ', '\xE5', '\x88', '\xB0', ' ', '\xE5', '\x92', '\x8C', ' ', '\xE5', '\x9C', '\xB0', /* 他 们 你 來 們 到 和 地 */ - ' ', '\xE5', '\xAF', '\xB9', ' ', '\xE5', '\xB0', '\x8D', ' ', '\xE5', '\xB0', '\xB1', ' ', '\xE5', '\xB8', '\xAD', ' ', '\xE6', '\x88', '\x91', ' ', '\xE6', '\x97', '\xB6', ' ', '\xE6', '\x99', '\x82', ' ', '\xE6', '\x9C', '\x83', /* 对 �? 就 席 我 时 時 會 */ - ' ', '\xE6', '\x9D', '\xA5', ' ', '\xE7', '\x82', '\xBA', ' ', '\xE8', '\x83', '\xBD', ' ', '\xE8', '\x88', '\xB0', ' ', '\xE8', '\xAA', '\xAA', ' ', '\xE8', '\xAF', '\xB4', ' ', '\xE8', '\xBF', '\x99', ' ', '\xE9', '\x80', '\x99', /* �?� 為 能 舰 說 说 这 這 */ + ' ', '\xE5', '\xAF', '\xB9', ' ', '\xE5', '\xB0', '\x8D', ' ', '\xE5', '\xB0', '\xB1', ' ', '\xE5', '\xB8', '\xAD', ' ', '\xE6', '\x88', '\x91', ' ', '\xE6', '\x97', '\xB6', ' ', '\xE6', '\x99', '\x82', ' ', '\xE6', '\x9C', '\x83', /* 对 �? 就 席 我 时 時 會 */ + ' ', '\xE6', '\x9D', '\xA5', ' ', '\xE7', '\x82', '\xBA', ' ', '\xE8', '\x83', '\xBD', ' ', '\xE8', '\x88', '\xB0', ' ', '\xE8', '\xAA', '\xAA', ' ', '\xE8', '\xAF', '\xB4', ' ', '\xE8', '\xBF', '\x99', ' ', '\xE9', '\x80', '\x99', /* �?� 為 能 舰 說 说 这 這 */ ' ', '\xE9', '\xBD', '\x8A', ' ', '|', /* 齊 | */ - ' ', '\xE5', '\x86', '\x9B', ' ', '\xE5', '\x90', '\x8C', ' ', '\xE5', '\xB7', '\xB2', ' ', '\xE6', '\x84', '\xBF', ' ', '\xE6', '\x97', '\xA2', ' ', '\xE6', '\x98', '\x9F', ' ', '\xE6', '\x98', '\xAF', ' ', '\xE6', '\x99', '\xAF', /* 军 �?� 已 愿 既 星 是 景 */ - ' ', '\xE6', '\xB0', '\x91', ' ', '\xE7', '\x85', '\xA7', ' ', '\xE7', '\x8E', '\xB0', ' ', '\xE7', '\x8F', '\xBE', ' ', '\xE7', '\x90', '\x86', ' ', '\xE7', '\x94', '\xA8', ' ', '\xE7', '\xBD', '\xAE', ' ', '\xE8', '\xA6', '\x81', /* 民 照 现 �?� �?� 用 置 �? */ - ' ', '\xE8', '\xBB', '\x8D', ' ', '\xE9', '\x82', '\xA3', ' ', '\xE9', '\x85', '\x8D', ' ', '\xE9', '\x87', '\x8C', ' ', '\xE9', '\x96', '\x8B', ' ', '\xE9', '\x9B', '\xB7', ' ', '\xE9', '\x9C', '\xB2', ' ', '\xE9', '\x9D', '\xA2', /* �? 那 �? 里 開 雷 露 �?� */ + ' ', '\xE5', '\x86', '\x9B', ' ', '\xE5', '\x90', '\x8C', ' ', '\xE5', '\xB7', '\xB2', ' ', '\xE6', '\x84', '\xBF', ' ', '\xE6', '\x97', '\xA2', ' ', '\xE6', '\x98', '\x9F', ' ', '\xE6', '\x98', '\xAF', ' ', '\xE6', '\x99', '\xAF', /* 军 �?� 已 愿 既 星 是 景 */ + ' ', '\xE6', '\xB0', '\x91', ' ', '\xE7', '\x85', '\xA7', ' ', '\xE7', '\x8E', '\xB0', ' ', '\xE7', '\x8F', '\xBE', ' ', '\xE7', '\x90', '\x86', ' ', '\xE7', '\x94', '\xA8', ' ', '\xE7', '\xBD', '\xAE', ' ', '\xE8', '\xA6', '\x81', /* 民 照 现 �?� �?� 用 置 �? */ + ' ', '\xE8', '\xBB', '\x8D', ' ', '\xE9', '\x82', '\xA3', ' ', '\xE9', '\x85', '\x8D', ' ', '\xE9', '\x87', '\x8C', ' ', '\xE9', '\x96', '\x8B', ' ', '\xE9', '\x9B', '\xB7', ' ', '\xE9', '\x9C', '\xB2', ' ', '\xE9', '\x9D', '\xA2', /* �? 那 �? 里 開 雷 露 �?� */ ' ', '\xE9', '\xA1', '\xBE', /* 顾 */ '\0', '\xE4', '\xB8', '\xAA', ' ', '\xE4', '\xB8', '\xBA', ' ', '\xE4', '\xBA', '\xBA', ' ', '\xE4', '\xBB', '\x96', ' ', '\xE4', '\xBB', '\xA5', ' ', '\xE4', '\xBB', '\xAC', ' ', '\xE4', '\xBD', '\xA0', ' ', '\xE4', '\xBE', '\x86', /* 个 为 人 他 以 们 你 來 */ - ' ', '\xE5', '\x80', '\x8B', ' ', '\xE5', '\x80', '\x91', ' ', '\xE5', '\x88', '\xB0', ' ', '\xE5', '\x92', '\x8C', ' ', '\xE5', '\xA4', '\xA7', ' ', '\xE5', '\xAF', '\xB9', ' ', '\xE5', '\xB0', '\x8D', ' ', '\xE5', '\xB0', '\xB1', /* 個 們 到 和 大 对 �? 就 */ - ' ', '\xE6', '\x88', '\x91', ' ', '\xE6', '\x97', '\xB6', ' ', '\xE6', '\x99', '\x82', ' ', '\xE6', '\x9C', '\x89', ' ', '\xE6', '\x9D', '\xA5', ' ', '\xE7', '\x82', '\xBA', ' ', '\xE8', '\xA6', '\x81', ' ', '\xE8', '\xAA', '\xAA', /* 我 时 時 有 �?� 為 �? 說 */ + ' ', '\xE5', '\x80', '\x8B', ' ', '\xE5', '\x80', '\x91', ' ', '\xE5', '\x88', '\xB0', ' ', '\xE5', '\x92', '\x8C', ' ', '\xE5', '\xA4', '\xA7', ' ', '\xE5', '\xAF', '\xB9', ' ', '\xE5', '\xB0', '\x8D', ' ', '\xE5', '\xB0', '\xB1', /* 個 們 到 和 大 对 �? 就 */ + ' ', '\xE6', '\x88', '\x91', ' ', '\xE6', '\x97', '\xB6', ' ', '\xE6', '\x99', '\x82', ' ', '\xE6', '\x9C', '\x89', ' ', '\xE6', '\x9D', '\xA5', ' ', '\xE7', '\x82', '\xBA', ' ', '\xE8', '\xA6', '\x81', ' ', '\xE8', '\xAA', '\xAA', /* 我 时 時 有 �?� 為 �? 說 */ ' ', '\xE8', '\xAF', '\xB4', ' ', '|', /* 说 | */ - ' ', '\xE4', '\xB8', '\xBB', ' ', '\xE4', '\xBA', '\x9B', ' ', '\xE5', '\x9B', '\xA0', ' ', '\xE5', '\xAE', '\x83', ' ', '\xE6', '\x83', '\xB3', ' ', '\xE6', '\x84', '\x8F', ' ', '\xE7', '\x90', '\x86', ' ', '\xE7', '\x94', '\x9F', /* 主 些 因 它 想 �? �?� 生 */ - ' ', '\xE7', '\x95', '\xB6', ' ', '\xE7', '\x9C', '\x8B', ' ', '\xE7', '\x9D', '\x80', ' ', '\xE7', '\xBD', '\xAE', ' ', '\xE8', '\x80', '\x85', ' ', '\xE8', '\x87', '\xAA', ' ', '\xE8', '\x91', '\x97', ' ', '\xE8', '\xA3', '\xA1', /* 當 看 �?� 置 者 自 著 裡 */ - ' ', '\xE8', '\xBF', '\x87', ' ', '\xE8', '\xBF', '\x98', ' ', '\xE8', '\xBF', '\x9B', ' ', '\xE9', '\x80', '\xB2', ' ', '\xE9', '\x81', '\x8E', ' ', '\xE9', '\x81', '\x93', ' ', '\xE9', '\x82', '\x84', ' ', '\xE9', '\x87', '\x8C', /* 过 还 进 進 �?� �?� 還 里 */ - ' ', '\xE9', '\x9D', '\xA2', /* �?� */ + ' ', '\xE4', '\xB8', '\xBB', ' ', '\xE4', '\xBA', '\x9B', ' ', '\xE5', '\x9B', '\xA0', ' ', '\xE5', '\xAE', '\x83', ' ', '\xE6', '\x83', '\xB3', ' ', '\xE6', '\x84', '\x8F', ' ', '\xE7', '\x90', '\x86', ' ', '\xE7', '\x94', '\x9F', /* 主 些 因 它 想 �? �?� 生 */ + ' ', '\xE7', '\x95', '\xB6', ' ', '\xE7', '\x9C', '\x8B', ' ', '\xE7', '\x9D', '\x80', ' ', '\xE7', '\xBD', '\xAE', ' ', '\xE8', '\x80', '\x85', ' ', '\xE8', '\x87', '\xAA', ' ', '\xE8', '\x91', '\x97', ' ', '\xE8', '\xA3', '\xA1', /* 當 看 �?� 置 者 自 著 裡 */ + ' ', '\xE8', '\xBF', '\x87', ' ', '\xE8', '\xBF', '\x98', ' ', '\xE8', '\xBF', '\x9B', ' ', '\xE9', '\x80', '\xB2', ' ', '\xE9', '\x81', '\x8E', ' ', '\xE9', '\x81', '\x93', ' ', '\xE9', '\x82', '\x84', ' ', '\xE9', '\x87', '\x8C', /* 过 还 进 進 �?� �?� 還 里 */ + ' ', '\xE9', '\x9D', '\xA2', /* �?� */ #ifdef AF_CONFIG_OPTION_CJK_BLUE_HANI_VERT '\0', ' ', '\xE4', '\xBA', '\x9B', ' ', '\xE4', '\xBB', '\xAC', ' ', '\xE4', '\xBD', '\xA0', ' ', '\xE4', '\xBE', '\x86', ' ', '\xE5', '\x80', '\x91', ' ', '\xE5', '\x88', '\xB0', ' ', '\xE5', '\x92', '\x8C', ' ', '\xE5', '\x9C', '\xB0', /* 些 们 你 來 們 到 和 地 */ ' ', '\xE5', '\xA5', '\xB9', ' ', '\xE5', '\xB0', '\x86', ' ', '\xE5', '\xB0', '\x87', ' ', '\xE5', '\xB0', '\xB1', ' ', '\xE5', '\xB9', '\xB4', ' ', '\xE5', '\xBE', '\x97', ' ', '\xE6', '\x83', '\x85', ' ', '\xE6', '\x9C', '\x80', /* 她 将 將 就 年 得 情 最 */ - ' ', '\xE6', '\xA0', '\xB7', ' ', '\xE6', '\xA8', '\xA3', ' ', '\xE7', '\x90', '\x86', ' ', '\xE8', '\x83', '\xBD', ' ', '\xE8', '\xAA', '\xAA', ' ', '\xE8', '\xAF', '\xB4', ' ', '\xE8', '\xBF', '\x99', ' ', '\xE9', '\x80', '\x99', /* 样 樣 �?� 能 說 说 这 這 */ + ' ', '\xE6', '\xA0', '\xB7', ' ', '\xE6', '\xA8', '\xA3', ' ', '\xE7', '\x90', '\x86', ' ', '\xE8', '\x83', '\xBD', ' ', '\xE8', '\xAA', '\xAA', ' ', '\xE8', '\xAF', '\xB4', ' ', '\xE8', '\xBF', '\x99', ' ', '\xE9', '\x80', '\x99', /* 样 樣 �?� 能 說 说 这 這 */ ' ', '\xE9', '\x80', '\x9A', ' ', '|', /* 通 | */ - ' ', '\xE5', '\x8D', '\xB3', ' ', '\xE5', '\x90', '\x97', ' ', '\xE5', '\x90', '\xA7', ' ', '\xE5', '\x90', '\xAC', ' ', '\xE5', '\x91', '\xA2', ' ', '\xE5', '\x93', '\x81', ' ', '\xE5', '\x93', '\x8D', ' ', '\xE5', '\x97', '\x8E', /* �?� �?� �?� �?� 呢 �? �? 嗎 */ + ' ', '\xE5', '\x8D', '\xB3', ' ', '\xE5', '\x90', '\x97', ' ', '\xE5', '\x90', '\xA7', ' ', '\xE5', '\x90', '\xAC', ' ', '\xE5', '\x91', '\xA2', ' ', '\xE5', '\x93', '\x81', ' ', '\xE5', '\x93', '\x8D', ' ', '\xE5', '\x97', '\x8E', /* �?� �?� �?� �?� 呢 �? �? 嗎 */ ' ', '\xE5', '\xB8', '\x88', ' ', '\xE5', '\xB8', '\xAB', ' ', '\xE6', '\x94', '\xB6', ' ', '\xE6', '\x96', '\xAD', ' ', '\xE6', '\x96', '\xB7', ' ', '\xE6', '\x98', '\x8E', ' ', '\xE7', '\x9C', '\xBC', ' ', '\xE9', '\x96', '\x93', /* 师 師 收 断 斷 明 眼 間 */ - ' ', '\xE9', '\x97', '\xB4', ' ', '\xE9', '\x99', '\x85', ' ', '\xE9', '\x99', '\x88', ' ', '\xE9', '\x99', '\x90', ' ', '\xE9', '\x99', '\xA4', ' ', '\xE9', '\x99', '\xB3', ' ', '\xE9', '\x9A', '\x8F', ' ', '\xE9', '\x9A', '\x9B', /* 间 际 陈 �? 除 陳 �? 際 */ + ' ', '\xE9', '\x97', '\xB4', ' ', '\xE9', '\x99', '\x85', ' ', '\xE9', '\x99', '\x88', ' ', '\xE9', '\x99', '\x90', ' ', '\xE9', '\x99', '\xA4', ' ', '\xE9', '\x99', '\xB3', ' ', '\xE9', '\x9A', '\x8F', ' ', '\xE9', '\x9A', '\x9B', /* 间 际 陈 �? 除 陳 �? 際 */ ' ', '\xE9', '\x9A', '\xA8', /* 隨 */ '\0', - '\xE4', '\xBA', '\x8B', ' ', '\xE5', '\x89', '\x8D', ' ', '\xE5', '\xAD', '\xB8', ' ', '\xE5', '\xB0', '\x86', ' ', '\xE5', '\xB0', '\x87', ' ', '\xE6', '\x83', '\x85', ' ', '\xE6', '\x83', '\xB3', ' ', '\xE6', '\x88', '\x96', /* 事 �? 學 将 將 情 想 或 */ + '\xE4', '\xBA', '\x8B', ' ', '\xE5', '\x89', '\x8D', ' ', '\xE5', '\xAD', '\xB8', ' ', '\xE5', '\xB0', '\x86', ' ', '\xE5', '\xB0', '\x87', ' ', '\xE6', '\x83', '\x85', ' ', '\xE6', '\x83', '\xB3', ' ', '\xE6', '\x88', '\x96', /* 事 �? 學 将 將 情 想 或 */ ' ', '\xE6', '\x94', '\xBF', ' ', '\xE6', '\x96', '\xAF', ' ', '\xE6', '\x96', '\xB0', ' ', '\xE6', '\xA0', '\xB7', ' ', '\xE6', '\xA8', '\xA3', ' ', '\xE6', '\xB0', '\x91', ' ', '\xE6', '\xB2', '\x92', ' ', '\xE6', '\xB2', '\xA1', /* 政 斯 新 样 樣 民 沒 没 */ - ' ', '\xE7', '\x84', '\xB6', ' ', '\xE7', '\x89', '\xB9', ' ', '\xE7', '\x8E', '\xB0', ' ', '\xE7', '\x8F', '\xBE', ' ', '\xE7', '\x90', '\x83', ' ', '\xE7', '\xAC', '\xAC', ' ', '\xE7', '\xB6', '\x93', ' ', '\xE8', '\xB0', '\x81', /* 然 特 现 �?� �?� 第 經 �? */ + ' ', '\xE7', '\x84', '\xB6', ' ', '\xE7', '\x89', '\xB9', ' ', '\xE7', '\x8E', '\xB0', ' ', '\xE7', '\x8F', '\xBE', ' ', '\xE7', '\x90', '\x83', ' ', '\xE7', '\xAC', '\xAC', ' ', '\xE7', '\xB6', '\x93', ' ', '\xE8', '\xB0', '\x81', /* 然 特 现 �?� �?� 第 經 �? */ ' ', '\xE8', '\xB5', '\xB7', ' ', '|', /* 起 | */ - ' ', '\xE4', '\xBE', '\x8B', ' ', '\xE5', '\x88', '\xA5', ' ', '\xE5', '\x88', '\xAB', ' ', '\xE5', '\x88', '\xB6', ' ', '\xE5', '\x8A', '\xA8', ' ', '\xE5', '\x8B', '\x95', ' ', '\xE5', '\x90', '\x97', ' ', '\xE5', '\x97', '\x8E', /* 例 別 别 制 动 動 �?� 嗎 */ - ' ', '\xE5', '\xA2', '\x9E', ' ', '\xE6', '\x8C', '\x87', ' ', '\xE6', '\x98', '\x8E', ' ', '\xE6', '\x9C', '\x9D', ' ', '\xE6', '\x9C', '\x9F', ' ', '\xE6', '\x9E', '\x84', ' ', '\xE7', '\x89', '\xA9', ' ', '\xE7', '\xA1', '\xAE', /* 增 指 明 �? 期 构 物 确 */ - ' ', '\xE7', '\xA7', '\x8D', ' ', '\xE8', '\xAA', '\xBF', ' ', '\xE8', '\xB0', '\x83', ' ', '\xE8', '\xB2', '\xBB', ' ', '\xE8', '\xB4', '\xB9', ' ', '\xE9', '\x82', '\xA3', ' ', '\xE9', '\x83', '\xBD', ' ', '\xE9', '\x96', '\x93', /* �? 調 调 費 费 那 都 間 */ + ' ', '\xE4', '\xBE', '\x8B', ' ', '\xE5', '\x88', '\xA5', ' ', '\xE5', '\x88', '\xAB', ' ', '\xE5', '\x88', '\xB6', ' ', '\xE5', '\x8A', '\xA8', ' ', '\xE5', '\x8B', '\x95', ' ', '\xE5', '\x90', '\x97', ' ', '\xE5', '\x97', '\x8E', /* 例 別 别 制 动 動 �?� 嗎 */ + ' ', '\xE5', '\xA2', '\x9E', ' ', '\xE6', '\x8C', '\x87', ' ', '\xE6', '\x98', '\x8E', ' ', '\xE6', '\x9C', '\x9D', ' ', '\xE6', '\x9C', '\x9F', ' ', '\xE6', '\x9E', '\x84', ' ', '\xE7', '\x89', '\xA9', ' ', '\xE7', '\xA1', '\xAE', /* 增 指 明 �? 期 构 物 确 */ + ' ', '\xE7', '\xA7', '\x8D', ' ', '\xE8', '\xAA', '\xBF', ' ', '\xE8', '\xB0', '\x83', ' ', '\xE8', '\xB2', '\xBB', ' ', '\xE8', '\xB4', '\xB9', ' ', '\xE9', '\x82', '\xA3', ' ', '\xE9', '\x83', '\xBD', ' ', '\xE9', '\x96', '\x93', /* �? 調 调 費 费 那 都 間 */ ' ', '\xE9', '\x97', '\xB4', /* 间 */ #endif /* AF_CONFIG_OPTION_CJK_BLUE_HANI_VERT */ #endif /* AF_CONFIG_OPTION_CJK */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afcjk.c b/bsp/projects/microej/thirdparty/freetype/src/afcjk.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afcjk.c rename to bsp/projects/microej/thirdparty/freetype/src/afcjk.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afdummy.c b/bsp/projects/microej/thirdparty/freetype/src/afdummy.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afdummy.c rename to bsp/projects/microej/thirdparty/freetype/src/afdummy.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afglobal.c b/bsp/projects/microej/thirdparty/freetype/src/afglobal.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afglobal.c rename to bsp/projects/microej/thirdparty/freetype/src/afglobal.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afhints.c b/bsp/projects/microej/thirdparty/freetype/src/afhints.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afhints.c rename to bsp/projects/microej/thirdparty/freetype/src/afhints.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afindic.c b/bsp/projects/microej/thirdparty/freetype/src/afindic.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afindic.c rename to bsp/projects/microej/thirdparty/freetype/src/afindic.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/aflatin.c b/bsp/projects/microej/thirdparty/freetype/src/aflatin.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/aflatin.c rename to bsp/projects/microej/thirdparty/freetype/src/aflatin.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afloader.c b/bsp/projects/microej/thirdparty/freetype/src/afloader.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afloader.c rename to bsp/projects/microej/thirdparty/freetype/src/afloader.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afmodule.c b/bsp/projects/microej/thirdparty/freetype/src/afmodule.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afmodule.c rename to bsp/projects/microej/thirdparty/freetype/src/afmodule.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afmparse.c b/bsp/projects/microej/thirdparty/freetype/src/afmparse.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afmparse.c rename to bsp/projects/microej/thirdparty/freetype/src/afmparse.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afranges.c b/bsp/projects/microej/thirdparty/freetype/src/afranges.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afranges.c rename to bsp/projects/microej/thirdparty/freetype/src/afranges.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afshaper.c b/bsp/projects/microej/thirdparty/freetype/src/afshaper.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/afshaper.c rename to bsp/projects/microej/thirdparty/freetype/src/afshaper.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/apinames.c b/bsp/projects/microej/thirdparty/freetype/src/apinames.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/apinames.c rename to bsp/projects/microej/thirdparty/freetype/src/apinames.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/autofit.c b/bsp/projects/microej/thirdparty/freetype/src/autofit.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/autofit.c rename to bsp/projects/microej/thirdparty/freetype/src/autofit.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/bdf.c b/bsp/projects/microej/thirdparty/freetype/src/bdf.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/bdf.c rename to bsp/projects/microej/thirdparty/freetype/src/bdf.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/bdfdrivr.c b/bsp/projects/microej/thirdparty/freetype/src/bdfdrivr.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/bdfdrivr.c rename to bsp/projects/microej/thirdparty/freetype/src/bdfdrivr.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/bdflib.c b/bsp/projects/microej/thirdparty/freetype/src/bdflib.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/bdflib.c rename to bsp/projects/microej/thirdparty/freetype/src/bdflib.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cff.c b/bsp/projects/microej/thirdparty/freetype/src/cff.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cff.c rename to bsp/projects/microej/thirdparty/freetype/src/cff.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffcmap.c b/bsp/projects/microej/thirdparty/freetype/src/cffcmap.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffcmap.c rename to bsp/projects/microej/thirdparty/freetype/src/cffcmap.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffdecode.c b/bsp/projects/microej/thirdparty/freetype/src/cffdecode.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffdecode.c rename to bsp/projects/microej/thirdparty/freetype/src/cffdecode.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffdrivr.c b/bsp/projects/microej/thirdparty/freetype/src/cffdrivr.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffdrivr.c rename to bsp/projects/microej/thirdparty/freetype/src/cffdrivr.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffgload.c b/bsp/projects/microej/thirdparty/freetype/src/cffgload.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffgload.c rename to bsp/projects/microej/thirdparty/freetype/src/cffgload.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffload.c b/bsp/projects/microej/thirdparty/freetype/src/cffload.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffload.c rename to bsp/projects/microej/thirdparty/freetype/src/cffload.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffobjs.c b/bsp/projects/microej/thirdparty/freetype/src/cffobjs.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffobjs.c rename to bsp/projects/microej/thirdparty/freetype/src/cffobjs.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffparse.c b/bsp/projects/microej/thirdparty/freetype/src/cffparse.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cffparse.c rename to bsp/projects/microej/thirdparty/freetype/src/cffparse.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cidgload.c b/bsp/projects/microej/thirdparty/freetype/src/cidgload.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cidgload.c rename to bsp/projects/microej/thirdparty/freetype/src/cidgload.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cidload.c b/bsp/projects/microej/thirdparty/freetype/src/cidload.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cidload.c rename to bsp/projects/microej/thirdparty/freetype/src/cidload.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cidobjs.c b/bsp/projects/microej/thirdparty/freetype/src/cidobjs.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cidobjs.c rename to bsp/projects/microej/thirdparty/freetype/src/cidobjs.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cidparse.c b/bsp/projects/microej/thirdparty/freetype/src/cidparse.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cidparse.c rename to bsp/projects/microej/thirdparty/freetype/src/cidparse.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cidriver.c b/bsp/projects/microej/thirdparty/freetype/src/cidriver.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/cidriver.c rename to bsp/projects/microej/thirdparty/freetype/src/cidriver.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/dlgwrap.c b/bsp/projects/microej/thirdparty/freetype/src/dlgwrap.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/dlgwrap.c rename to bsp/projects/microej/thirdparty/freetype/src/dlgwrap.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftadvanc.c b/bsp/projects/microej/thirdparty/freetype/src/ftadvanc.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftadvanc.c rename to bsp/projects/microej/thirdparty/freetype/src/ftadvanc.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftbase.c b/bsp/projects/microej/thirdparty/freetype/src/ftbase.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftbase.c rename to bsp/projects/microej/thirdparty/freetype/src/ftbase.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftbbox.c b/bsp/projects/microej/thirdparty/freetype/src/ftbbox.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftbbox.c rename to bsp/projects/microej/thirdparty/freetype/src/ftbbox.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftbdf.c b/bsp/projects/microej/thirdparty/freetype/src/ftbdf.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftbdf.c rename to bsp/projects/microej/thirdparty/freetype/src/ftbdf.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftbitmap.c b/bsp/projects/microej/thirdparty/freetype/src/ftbitmap.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftbitmap.c rename to bsp/projects/microej/thirdparty/freetype/src/ftbitmap.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftbsdf.c b/bsp/projects/microej/thirdparty/freetype/src/ftbsdf.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftbsdf.c rename to bsp/projects/microej/thirdparty/freetype/src/ftbsdf.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftbzip2.c b/bsp/projects/microej/thirdparty/freetype/src/ftbzip2.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftbzip2.c rename to bsp/projects/microej/thirdparty/freetype/src/ftbzip2.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcache.c b/bsp/projects/microej/thirdparty/freetype/src/ftcache.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcache.c rename to bsp/projects/microej/thirdparty/freetype/src/ftcache.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcalc.c b/bsp/projects/microej/thirdparty/freetype/src/ftcalc.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcalc.c rename to bsp/projects/microej/thirdparty/freetype/src/ftcalc.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcbasic.c b/bsp/projects/microej/thirdparty/freetype/src/ftcbasic.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcbasic.c rename to bsp/projects/microej/thirdparty/freetype/src/ftcbasic.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftccache.c b/bsp/projects/microej/thirdparty/freetype/src/ftccache.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftccache.c rename to bsp/projects/microej/thirdparty/freetype/src/ftccache.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftccmap.c b/bsp/projects/microej/thirdparty/freetype/src/ftccmap.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftccmap.c rename to bsp/projects/microej/thirdparty/freetype/src/ftccmap.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcglyph.c b/bsp/projects/microej/thirdparty/freetype/src/ftcglyph.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcglyph.c rename to bsp/projects/microej/thirdparty/freetype/src/ftcglyph.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcid.c b/bsp/projects/microej/thirdparty/freetype/src/ftcid.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcid.c rename to bsp/projects/microej/thirdparty/freetype/src/ftcid.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcimage.c b/bsp/projects/microej/thirdparty/freetype/src/ftcimage.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcimage.c rename to bsp/projects/microej/thirdparty/freetype/src/ftcimage.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcmanag.c b/bsp/projects/microej/thirdparty/freetype/src/ftcmanag.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcmanag.c rename to bsp/projects/microej/thirdparty/freetype/src/ftcmanag.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcmru.c b/bsp/projects/microej/thirdparty/freetype/src/ftcmru.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcmru.c rename to bsp/projects/microej/thirdparty/freetype/src/ftcmru.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcolor.c b/bsp/projects/microej/thirdparty/freetype/src/ftcolor.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcolor.c rename to bsp/projects/microej/thirdparty/freetype/src/ftcolor.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcsbits.c b/bsp/projects/microej/thirdparty/freetype/src/ftcsbits.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftcsbits.c rename to bsp/projects/microej/thirdparty/freetype/src/ftcsbits.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftdbgmem.c b/bsp/projects/microej/thirdparty/freetype/src/ftdbgmem.c similarity index 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similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftgxval.c rename to bsp/projects/microej/thirdparty/freetype/src/ftgxval.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftgzip.c b/bsp/projects/microej/thirdparty/freetype/src/ftgzip.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftgzip.c rename to bsp/projects/microej/thirdparty/freetype/src/ftgzip.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/fthash.c b/bsp/projects/microej/thirdparty/freetype/src/fthash.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/fthash.c rename to bsp/projects/microej/thirdparty/freetype/src/fthash.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftinit.c b/bsp/projects/microej/thirdparty/freetype/src/ftinit.c similarity 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from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftraster.c rename to bsp/projects/microej/thirdparty/freetype/src/ftraster.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftrend1.c b/bsp/projects/microej/thirdparty/freetype/src/ftrend1.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftrend1.c rename to bsp/projects/microej/thirdparty/freetype/src/ftrend1.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftrfork.c b/bsp/projects/microej/thirdparty/freetype/src/ftrfork.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftrfork.c rename to bsp/projects/microej/thirdparty/freetype/src/ftrfork.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsdf.c b/bsp/projects/microej/thirdparty/freetype/src/ftsdf.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsdf.c rename to bsp/projects/microej/thirdparty/freetype/src/ftsdf.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsdfcommon.c b/bsp/projects/microej/thirdparty/freetype/src/ftsdfcommon.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsdfcommon.c rename to bsp/projects/microej/thirdparty/freetype/src/ftsdfcommon.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsdfrend.c b/bsp/projects/microej/thirdparty/freetype/src/ftsdfrend.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsdfrend.c rename to bsp/projects/microej/thirdparty/freetype/src/ftsdfrend.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsmooth.c b/bsp/projects/microej/thirdparty/freetype/src/ftsmooth.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsmooth.c rename to bsp/projects/microej/thirdparty/freetype/src/ftsmooth.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsnames.c b/bsp/projects/microej/thirdparty/freetype/src/ftsnames.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsnames.c rename to bsp/projects/microej/thirdparty/freetype/src/ftsnames.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftstream.c b/bsp/projects/microej/thirdparty/freetype/src/ftstream.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftstream.c rename to bsp/projects/microej/thirdparty/freetype/src/ftstream.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftstroke.c b/bsp/projects/microej/thirdparty/freetype/src/ftstroke.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftstroke.c rename to bsp/projects/microej/thirdparty/freetype/src/ftstroke.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsynth.c b/bsp/projects/microej/thirdparty/freetype/src/ftsynth.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsynth.c rename to bsp/projects/microej/thirdparty/freetype/src/ftsynth.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsystem/ftsystem.c b/bsp/projects/microej/thirdparty/freetype/src/ftsystem/ftsystem.c similarity index 95% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsystem/ftsystem.c rename to bsp/projects/microej/thirdparty/freetype/src/ftsystem/ftsystem.c index 10190e0..faea39e 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftsystem/ftsystem.c +++ b/bsp/projects/microej/thirdparty/freetype/src/ftsystem/ftsystem.c @@ -7,13 +7,13 @@ * Copyright (C) 1996-2021 by * David Turner, Robert Wilhelm, and Werner Lemberg. * + * Copyright 2021-2022 MicroEJ Corp. This file has been modified and/or created by MicroEJ Corp. + * * This file is part of the FreeType project, and may only be used, * modified, and distributed under the terms of the FreeType project * license, LICENSE.TXT. By continuing to use, modify, or distribute * this file you indicate that you have read the license and * understand and accept it fully. - * - * Copyright 2019-2022 MicroEJ Corp. This file has been modified by MicroEJ Corp. */ /************************************************************************** diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/fttrigon.c b/bsp/projects/microej/thirdparty/freetype/src/fttrigon.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/fttrigon.c rename to bsp/projects/microej/thirdparty/freetype/src/fttrigon.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/fttype1.c b/bsp/projects/microej/thirdparty/freetype/src/fttype1.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/fttype1.c rename to bsp/projects/microej/thirdparty/freetype/src/fttype1.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftutil.c b/bsp/projects/microej/thirdparty/freetype/src/ftutil.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftutil.c rename to bsp/projects/microej/thirdparty/freetype/src/ftutil.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftvector/ftvector.c b/bsp/projects/microej/thirdparty/freetype/src/ftvector/ftvector.c similarity index 84% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftvector/ftvector.c rename to bsp/projects/microej/thirdparty/freetype/src/ftvector/ftvector.c index 4985c8a..841f2d4 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftvector/ftvector.c +++ b/bsp/projects/microej/thirdparty/freetype/src/ftvector/ftvector.c @@ -1,7 +1,7 @@ /* * C * - * Copyright 2019-2022 MicroEJ Corp. All rights reserved. + * Copyright 2019-2023 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -9,7 +9,7 @@ * @file * @brief Freetype vglite renderer * @author MicroEJ Developer Team -* @version 3.0.0 +* @version 7.0.1 */ #define FT_MAKE_OPTION_SINGLE_OBJECT @@ -43,32 +43,8 @@ #define FT_MEM_ZERO( dest, count ) FT_MEM_SET( dest, 0, count ) #endif -#include "trace_vglite.h" -#include "display_vglite.h" -#include "vglite_path.h" #include "microvg_helper.h" - -/* - * @brief Logs an init gpu start event - * - * @param[in] operation: The VGLite operation sent to the GPU - */ -// cppcheck-suppress [misra-c2012-20.10] -#define FT_VGLITE_TRACE_INIT_GPU_START(operation) \ - TRACE_PLATFORM_START_U32( \ - VGLITE, \ - VGLITE_TRACE_INIT_GPU, \ - VGLITE_TRACE_OP_ ## operation \ - ); - -/* - * @brief Logs an init gpu end event - */ -#define FT_VGLITE_TRACE_INIT_GPU_END() \ - TRACE_PLATFORM_END_VOID( \ - VGLITE, \ - VGLITE_TRACE_INIT_GPU \ - ); +#include "vg_drawing_vglite.h" /* * @brief INIT_GPU event identifier @@ -91,7 +67,7 @@ typedef struct vglite_TWorker_ { FT_Outline outline; - void* vglite_dest; + VG_DRAWING_VGLITE_draw_glyph_t vglite_dest; vg_lite_matrix_t* vglite_matrix; vg_lite_path_t vglite_path; uint32_t vglite_path_pool_size; @@ -346,28 +322,15 @@ vglite_convert_glyph( void ) FT_TRACE7(("horiBearingX: %d\n", _worker.metrics->horiBearingX)); FT_TRACE7(("horiBearingY: %d\n", _worker.metrics->horiBearingY)); - // FIXME the commented code break characters alignment on the baseline. - // I guess they were added to fix wrong positions. - // int offX = _worker.metrics->horiBearingX; - // int offY = _worker.metrics->horiBearingY - _worker.metrics->height; - // Get fill rule from outline vg_lite_fill_t vg_lite_fill_rule = (_worker.outline.flags & FT_OUTLINE_EVEN_ODD_FILL) ? VG_LITE_FILL_EVEN_ODD : VG_LITE_FILL_NON_ZERO; - // vg_lite_translate(offX, offY, _worker.vglite_matrix); - if(_worker.vg_lite_gradient == MICROVG_HELPER_NULL_GRADIENT){ - FT_VGLITE_TRACE_INIT_GPU_START(DRAW); - void* target = _worker.vglite_dest; - VG_DRAWER_draw_path(target, &_worker.vglite_path, vg_lite_fill_rule, _worker.vglite_matrix, _worker.vg_lite_blend, _worker.vg_lite_color); - FT_VGLITE_TRACE_INIT_GPU_END(); - } - else { - FT_VGLITE_TRACE_INIT_GPU_START(DRAW_GRAD); - void* target = _worker.vglite_dest; - VG_DRAWER_draw_gradient(target, &_worker.vglite_path, vg_lite_fill_rule, _worker.vglite_matrix, _worker.vg_lite_gradient, _worker.vg_lite_blend); - FT_VGLITE_TRACE_INIT_GPU_END(); + VG_DRAWING_VGLITE_draw_glyph_t drawer = (VG_DRAWING_VGLITE_draw_glyph_t)(_worker.vglite_dest); + jint llvg_error = (*drawer)(&_worker.vglite_path, vg_lite_fill_rule, _worker.vglite_matrix, _worker.vg_lite_blend, _worker.vg_lite_color, _worker.vg_lite_gradient); + + if (LLVG_SUCCESS != llvg_error) { + error = (LLVG_OUT_OF_MEMORY == llvg_error) ? FT_ERR( Out_Of_Memory ) : FT_ERR( Cannot_Render_Glyph ) ; } - // vg_lite_translate(0, offY, _worker.vglite_matrix); } } @@ -416,12 +379,18 @@ vglite_reset( FT_Raster raster, _worker.vglite_matrix = NULL; _worker.vglite_path_pool_size = 0; - (void)memset(&_worker.vglite_path, 0, sizeof(_worker.vglite_path)); - - _worker.vglite_path.bounding_box[0] = -4000; // Left - _worker.vglite_path.bounding_box[1] = -4000; // Top - _worker.vglite_path.bounding_box[2] = 4000; // Right - _worker.vglite_path.bounding_box[3] = 4000; // Bottom + vg_lite_init_path( + &_worker.vglite_path, + VG_LITE_S16, + VG_LITE_HIGH, + 0, + NULL, + -4000, // Left + -4000, // Top + 4000, // Right + 4000 // Bottom + ); + _worker.vglite_path.path_type = VG_LITE_DRAW_FILL_PATH; } @@ -485,7 +454,7 @@ static FT_Error ft_vglite_set_mode(FT_Renderer render, FT_ULong mode_tag, FT_Po switch (mode_tag){ case FT_PARAM_TAG_VGLITE_DESTINATION:{ - _worker.vglite_dest = data; + _worker.vglite_dest = (VG_DRAWING_VGLITE_draw_glyph_t)data; ret = FT_ERR(Ok); break; } @@ -494,16 +463,6 @@ static FT_Error ft_vglite_set_mode(FT_Renderer render, FT_ULong mode_tag, FT_Po ret = FT_ERR(Ok); break; } - case FT_PARAM_TAG_VGLITE_QUALITY:{ - _worker.vglite_path.quality = (vg_lite_quality_t) (uint32_t) data; - ret = FT_ERR(Ok); - break; - } - case FT_PARAM_TAG_VGLITE_FORMAT:{ - _worker.vglite_path.format = (vg_lite_format_t) (uint32_t) data; - ret = FT_ERR(Ok); - break; - } case FT_PARAM_TAG_VGLITE_BLEND:{ _worker.vg_lite_blend = (vg_lite_blend_t) (uint32_t) data; ret = FT_ERR(Ok); @@ -512,15 +471,11 @@ static FT_Error ft_vglite_set_mode(FT_Renderer render, FT_ULong mode_tag, FT_Po case FT_PARAM_TAG_VGLITE_COLOR:{ // convert the color only once, see FT_PARAM_TAG_VGLITE_DESTINATION _worker.vg_lite_color = (uint32_t) data; - VG_DRAWER_update_color(_worker.vglite_dest, &_worker.vg_lite_color, _worker.vg_lite_blend); ret = FT_ERR(Ok); break; } case FT_PARAM_TAG_VGLITE_GRADIENT:{ _worker.vg_lite_gradient = data; - if (MICROVG_HELPER_NULL_GRADIENT != data) { - VG_DRAWER_update_gradient(_worker.vglite_dest, _worker.vg_lite_gradient, _worker.vg_lite_blend); - } ret = FT_ERR(Ok); break; } @@ -552,7 +507,7 @@ ft_vglite_transform( FT_Renderer render, if (NULL != delta ){ FT_Outline_Translate( &slot->outline, delta->x, delta->y ); } - error = FT_Err_Ok; + error = FT_ERR( Ok ); } else { error = FT_THROW( Invalid_Argument ); diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftwinfnt.c b/bsp/projects/microej/thirdparty/freetype/src/ftwinfnt.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftwinfnt.c rename to bsp/projects/microej/thirdparty/freetype/src/ftwinfnt.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftzopen.c b/bsp/projects/microej/thirdparty/freetype/src/ftzopen.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ftzopen.c rename to bsp/projects/microej/thirdparty/freetype/src/ftzopen.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/gxvalid.c b/bsp/projects/microej/thirdparty/freetype/src/gxvalid.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/gxvalid.c rename to bsp/projects/microej/thirdparty/freetype/src/gxvalid.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/gxvbsln.c b/bsp/projects/microej/thirdparty/freetype/src/gxvbsln.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/gxvbsln.c rename to bsp/projects/microej/thirdparty/freetype/src/gxvbsln.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/gxvcommn.c b/bsp/projects/microej/thirdparty/freetype/src/gxvcommn.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/gxvcommn.c rename to bsp/projects/microej/thirdparty/freetype/src/gxvcommn.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/gxvfeat.c b/bsp/projects/microej/thirdparty/freetype/src/gxvfeat.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/gxvfeat.c rename to bsp/projects/microej/thirdparty/freetype/src/gxvfeat.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/gxvfgen.c b/bsp/projects/microej/thirdparty/freetype/src/gxvfgen.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/gxvfgen.c rename to bsp/projects/microej/thirdparty/freetype/src/gxvfgen.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/gxvjust.c b/bsp/projects/microej/thirdparty/freetype/src/gxvjust.c similarity index 100% rename from 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a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/otvmod.c b/bsp/projects/microej/thirdparty/freetype/src/otvmod.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/otvmod.c rename to bsp/projects/microej/thirdparty/freetype/src/otvmod.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/pcf.c b/bsp/projects/microej/thirdparty/freetype/src/pcf.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/pcf.c rename to bsp/projects/microej/thirdparty/freetype/src/pcf.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/pcfdrivr.c b/bsp/projects/microej/thirdparty/freetype/src/pcfdrivr.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/pcfdrivr.c rename to bsp/projects/microej/thirdparty/freetype/src/pcfdrivr.c diff --git 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rename to bsp/projects/microej/thirdparty/freetype/src/ttbdf.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttcmap.c b/bsp/projects/microej/thirdparty/freetype/src/ttcmap.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttcmap.c rename to bsp/projects/microej/thirdparty/freetype/src/ttcmap.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttcolr.c b/bsp/projects/microej/thirdparty/freetype/src/ttcolr.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttcolr.c rename to bsp/projects/microej/thirdparty/freetype/src/ttcolr.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttcpal.c b/bsp/projects/microej/thirdparty/freetype/src/ttcpal.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttcpal.c rename to bsp/projects/microej/thirdparty/freetype/src/ttcpal.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttdriver.c b/bsp/projects/microej/thirdparty/freetype/src/ttdriver.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttdriver.c rename to bsp/projects/microej/thirdparty/freetype/src/ttdriver.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttgload.c b/bsp/projects/microej/thirdparty/freetype/src/ttgload.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttgload.c rename to bsp/projects/microej/thirdparty/freetype/src/ttgload.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttgxvar.c b/bsp/projects/microej/thirdparty/freetype/src/ttgxvar.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttgxvar.c rename to bsp/projects/microej/thirdparty/freetype/src/ttgxvar.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttinterp.c b/bsp/projects/microej/thirdparty/freetype/src/ttinterp.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttinterp.c rename to bsp/projects/microej/thirdparty/freetype/src/ttinterp.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttkern.c b/bsp/projects/microej/thirdparty/freetype/src/ttkern.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttkern.c rename to bsp/projects/microej/thirdparty/freetype/src/ttkern.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttload.c b/bsp/projects/microej/thirdparty/freetype/src/ttload.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttload.c rename to bsp/projects/microej/thirdparty/freetype/src/ttload.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttmtx.c b/bsp/projects/microej/thirdparty/freetype/src/ttmtx.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttmtx.c rename to bsp/projects/microej/thirdparty/freetype/src/ttmtx.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttobjs.c b/bsp/projects/microej/thirdparty/freetype/src/ttobjs.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttobjs.c rename to bsp/projects/microej/thirdparty/freetype/src/ttobjs.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttpload.c b/bsp/projects/microej/thirdparty/freetype/src/ttpload.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttpload.c rename to bsp/projects/microej/thirdparty/freetype/src/ttpload.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttpost.c b/bsp/projects/microej/thirdparty/freetype/src/ttpost.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttpost.c rename to bsp/projects/microej/thirdparty/freetype/src/ttpost.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttsbit.c b/bsp/projects/microej/thirdparty/freetype/src/ttsbit.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttsbit.c rename to bsp/projects/microej/thirdparty/freetype/src/ttsbit.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttsubpix.c b/bsp/projects/microej/thirdparty/freetype/src/ttsubpix.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/ttsubpix.c rename to bsp/projects/microej/thirdparty/freetype/src/ttsubpix.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/type1.c b/bsp/projects/microej/thirdparty/freetype/src/type1.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/type1.c rename to bsp/projects/microej/thirdparty/freetype/src/type1.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/type1cid.c b/bsp/projects/microej/thirdparty/freetype/src/type1cid.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/type1cid.c rename to bsp/projects/microej/thirdparty/freetype/src/type1cid.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/type42.c b/bsp/projects/microej/thirdparty/freetype/src/type42.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/type42.c rename to bsp/projects/microej/thirdparty/freetype/src/type42.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/winfnt.c b/bsp/projects/microej/thirdparty/freetype/src/winfnt.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/winfnt.c rename to bsp/projects/microej/thirdparty/freetype/src/winfnt.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/woff2tags.c b/bsp/projects/microej/thirdparty/freetype/src/woff2tags.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/woff2tags.c rename to bsp/projects/microej/thirdparty/freetype/src/woff2tags.c diff --git a/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_base_wrapper.c b/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_base_wrapper.c new file mode 100644 index 0000000..76d9200 --- /dev/null +++ b/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_base_wrapper.c @@ -0,0 +1,28 @@ +/* + * Copyright 2022 MicroEJ Corp. This file has been modified and/or created by MicroEJ Corp. + * + * This file is part of the FreeType project, and may only be used, + * modified, and distributed under the terms of the FreeType project + * license, LICENSE.TXT. By continuing to use, modify, or distribute + * this file you indicate that you have read the license and + * understand and accept it fully. + */ + +/** +* @file +* @brief MicroEJ Freetype wrapper on freetype c files +* @author MicroEJ Developer Team +* @version 2.0.2 +*/ + +#include "microvg_configuration.h" +#if defined (VG_FEATURE_FONT) + +#include "../ftbase.c" +#include "../ftinit.c" +#include "../autofit.c" +#include "../pshinter.c" +#include "../sfnt.c" +#include "../ftsystem/ftsystem.c" + +#endif // defined (VG_FEATURE_FONT) diff --git a/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_bitmap_wrapper.c b/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_bitmap_wrapper.c new file mode 100644 index 0000000..1244e51 --- /dev/null +++ b/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_bitmap_wrapper.c @@ -0,0 +1,27 @@ +/* + * C + * + * Copyright 2022 MicroEJ Corp. This file has been modified and/or created by MicroEJ Corp. + * + * This file is part of the FreeType project, and may only be used, + * modified, and distributed under the terms of the FreeType project + * license, LICENSE.TXT. By continuing to use, modify, or distribute + * this file you indicate that you have read the license and + * understand and accept it fully. + */ + +/** +* @file +* @brief MicroEJ Freetype wrapper on freetype c files +* @author MicroEJ Developer Team +* @version 2.0.2 +*/ + +#include "microvg_configuration.h" + +#if defined (VG_FEATURE_FONT) && defined (VG_FEATURE_FONT_FREETYPE_BITMAP) && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_BITMAP) +#include "../ftsmooth.c" +#include "../ftgrays.c" +#include "../ftdebug.c" +#endif // defined (VG_FEATURE_FONT) && defined (VG_FEATURE_FONT_FREETYPE_BITMAP) && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_BITMAP) + diff --git a/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_otf_wrapper.c b/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_otf_wrapper.c new file mode 100644 index 0000000..987b219 --- /dev/null +++ b/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_otf_wrapper.c @@ -0,0 +1,29 @@ +/* + * C + * + * Copyright 2022 MicroEJ Corp. This file has been modified and/or created by MicroEJ Corp. + * + * This file is part of the FreeType project, and may only be used, + * modified, and distributed under the terms of the FreeType project + * license, LICENSE.TXT. By continuing to use, modify, or distribute + * this file you indicate that you have read the license and + * understand and accept it fully. + */ + +/** +* @file +* @brief MicroEJ Freetype wrapper on freetype c files +* @author MicroEJ Developer Team +* @version 2.0.2 +*/ + +#include "microvg_configuration.h" +#if defined (VG_FEATURE_FONT) + +#ifdef VG_FEATURE_FREETYPE_OTF +#include "../cff.c" +#include "../psaux.c" +#include "../psnames.c" +#endif // VG_FEATURE_FREETYPE_OTF + +#endif // defined (VG_FEATURE_FONT) diff --git a/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_ttf_wrapper.c b/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_ttf_wrapper.c new file mode 100644 index 0000000..089ebb6 --- /dev/null +++ b/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_ttf_wrapper.c @@ -0,0 +1,27 @@ +/* + * C + * + * Copyright 2022 MicroEJ Corp. This file has been modified and/or created by MicroEJ Corp. + * + * This file is part of the FreeType project, and may only be used, + * modified, and distributed under the terms of the FreeType project + * license, LICENSE.TXT. By continuing to use, modify, or distribute + * this file you indicate that you have read the license and + * understand and accept it fully. + */ + +/** +* @file +* @brief MicroEJ Freetype wrapper on freetype c files +* @author MicroEJ Developer Team +* @version 2.0.2 +*/ + +#include "microvg_configuration.h" +#if defined (VG_FEATURE_FONT) + +#ifdef VG_FEATURE_FREETYPE_TTF +#include "../truetype.c" +#endif // VG_FEATURE_FREETYPE_TTF + +#endif // defined (VG_FEATURE_FONT) diff --git a/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_vector_wrapper.c b/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_vector_wrapper.c new file mode 100644 index 0000000..d0b4e16 --- /dev/null +++ b/bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_vector_wrapper.c @@ -0,0 +1,24 @@ +/* + * C + * + * Copyright 2022 MicroEJ Corp. This file has been modified and/or created by MicroEJ Corp. + * + * This file is part of the FreeType project, and may only be used, + * modified, and distributed under the terms of the FreeType project + * license, LICENSE.TXT. By continuing to use, modify, or distribute + * this file you indicate that you have read the license and + * understand and accept it fully. + */ + +/** +* @file +* @brief MicroEJ Freetype wrapper on freetype c files +* @author MicroEJ Developer Team +* @version 2.0.2 +*/ + +#include "microvg_configuration.h" + +#if defined (VG_FEATURE_FONT) && defined (VG_FEATURE_FONT_FREETYPE_VECTOR) && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_VECTOR) +#include "../ftvector/ftvector.c" +#endif // defined (VG_FEATURE_FONT) && defined (VG_FEATURE_FONT_FREETYPE_VECTOR) && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_VECTOR) diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/zutil.c b/bsp/projects/microej/thirdparty/freetype/src/zutil.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/zutil.c rename to bsp/projects/microej/thirdparty/freetype/src/zutil.c diff --git a/bsp/projects/microej/thirdparty/freetype/thirdparty_freetype.cmake b/bsp/projects/microej/thirdparty/freetype/thirdparty_freetype.cmake new file mode 100644 index 0000000..791a513 --- /dev/null +++ b/bsp/projects/microej/thirdparty/freetype/thirdparty_freetype.cmake @@ -0,0 +1,11 @@ +include_guard() +message("microej/thirdparty/freetype component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/src/wrappers/ft_base_wrapper.c + ${CMAKE_CURRENT_LIST_DIR}/src/wrappers/ft_otf_wrapper.c + ${CMAKE_CURRENT_LIST_DIR}/src/wrappers/ft_ttf_wrapper.c + ${CMAKE_CURRENT_LIST_DIR}/src/wrappers/ft_vector_wrapper.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE ${CMAKE_CURRENT_LIST_DIR}/inc) diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/COPYING b/bsp/projects/microej/thirdparty/harfbuzz/COPYING similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/COPYING rename to bsp/projects/microej/thirdparty/harfbuzz/COPYING diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/AlternateSet.hh b/bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/AlternateSet.hh similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/AlternateSet.hh rename to bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/AlternateSet.hh diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/AlternateSubst.hh b/bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/AlternateSubst.hh similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/AlternateSubst.hh rename to bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/AlternateSubst.hh diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/AlternateSubstFormat1.hh b/bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/AlternateSubstFormat1.hh similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/AlternateSubstFormat1.hh rename to bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/AlternateSubstFormat1.hh diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/ChainContextSubst.hh b/bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/ChainContextSubst.hh similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/ChainContextSubst.hh rename to bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/ChainContextSubst.hh diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/Common.hh b/bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/Common.hh similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/Common.hh rename to bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/Common.hh diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/ContextSubst.hh b/bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/ContextSubst.hh similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/ContextSubst.hh rename to bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/ContextSubst.hh diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/ExtensionSubst.hh b/bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/ExtensionSubst.hh similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/ExtensionSubst.hh rename to bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/ExtensionSubst.hh diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/GSUB.hh b/bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/GSUB.hh similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/GSUB.hh rename to bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/GSUB.hh diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/Ligature.hh b/bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/Ligature.hh similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/Ligature.hh rename to bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/Ligature.hh diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/LigatureSet.hh b/bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/LigatureSet.hh similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/LigatureSet.hh rename to bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/LigatureSet.hh diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/LigatureSubst.hh b/bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/LigatureSubst.hh similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/LigatureSubst.hh rename to bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/LigatureSubst.hh diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/inc/OT/Layout/GSUB/LigatureSubstFormat1.hh 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bsp/projects/microej/thirdparty/harfbuzz/inc/hb.hh diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/.gitignore b/bsp/projects/microej/thirdparty/harfbuzz/lib/.gitignore similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/.gitignore rename to bsp/projects/microej/thirdparty/harfbuzz/lib/.gitignore diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/README.md b/bsp/projects/microej/thirdparty/harfbuzz/lib/README.md similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/README.md rename to bsp/projects/microej/thirdparty/harfbuzz/lib/README.md diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/iarprebuild.c b/bsp/projects/microej/thirdparty/harfbuzz/lib/iarprebuild.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/iarprebuild.c rename to bsp/projects/microej/thirdparty/harfbuzz/lib/iarprebuild.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/iarprebuild.cmd b/bsp/projects/microej/thirdparty/harfbuzz/lib/iarprebuild.cmd similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/iarprebuild.cmd rename to bsp/projects/microej/thirdparty/harfbuzz/lib/iarprebuild.cmd diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/lib_harfbuzz.ewp b/bsp/projects/microej/thirdparty/harfbuzz/lib/lib_harfbuzz.ewp similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/lib_harfbuzz.ewp rename to bsp/projects/microej/thirdparty/harfbuzz/lib/lib_harfbuzz.ewp diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/makefile b/bsp/projects/microej/thirdparty/harfbuzz/lib/makefile similarity index 93% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/makefile rename to bsp/projects/microej/thirdparty/harfbuzz/lib/makefile index 43f1f63..9a49ae0 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/makefile +++ b/bsp/projects/microej/thirdparty/harfbuzz/lib/makefile @@ -54,7 +54,7 @@ ARCHFLAGS := -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb CFLAGS := $(ARCHFLAGS) CFLAGS += -D__NEWLIB__ -O3 -g3 -Wall -fmessage-length=0 -CFLAGS += -ffunction-sections -fdata-sections -ffreestanding -fno-builtin +CFLAGS += -ffunction-sections -fdata-sections -fno-builtin CFLAGS += -specs=nano.specs -fpermissive # Some LIBC and LIBGCC files are needed in the harfbuzz.a library diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/harfbuzz.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/harfbuzz.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/harfbuzz.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/harfbuzz.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-aat-layout.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-aat-layout.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-aat-layout.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-aat-layout.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-aat-map.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-aat-map.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-aat-map.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-aat-map.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-alloc.c b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-alloc.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-alloc.c rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-alloc.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-blob.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-blob.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-blob.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-blob.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-buffer-serialize.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-buffer-serialize.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-buffer-serialize.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-buffer-serialize.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-buffer-verify.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-buffer-verify.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-buffer-verify.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-buffer-verify.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-buffer.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-buffer.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-buffer.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-buffer.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-common.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-common.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-common.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-common.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-coretext.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-coretext.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-coretext.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-coretext.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-directwrite.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-directwrite.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-directwrite.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-directwrite.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-draw.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-draw.cc similarity index 100% rename from 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b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-font.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-font.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-font.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ft.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ft.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ft.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ft.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-gdi.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-gdi.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-gdi.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-gdi.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-glib.cc 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a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-icu.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-icu.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-icu.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-icu.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-map.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-map.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-map.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-map.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-number.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-number.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-number.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-number.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-cff1-table.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-cff1-table.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-cff1-table.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-cff1-table.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-cff2-table.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-cff2-table.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-cff2-table.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-cff2-table.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-color.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-color.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-color.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-color.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-face.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-face.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-face.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-face.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-font.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-font.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-font.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-font.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-layout.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-layout.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-layout.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-layout.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-map.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-map.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-map.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-map.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-math.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-math.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-math.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-math.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-meta.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-meta.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-meta.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-meta.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-metrics.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-metrics.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-metrics.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-metrics.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-name.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-name.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-name.cc rename to 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a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-hangul.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-hangul.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-hangul.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-hangul.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-hebrew.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-hebrew.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-hebrew.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-hebrew.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-indic-table.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-indic-table.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-indic-table.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-indic-table.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-indic.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-indic.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-indic.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-indic.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-khmer.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-khmer.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-khmer.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-khmer.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-myanmar.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-myanmar.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-myanmar.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-myanmar.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-syllabic.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-syllabic.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-syllabic.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-syllabic.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-thai.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-thai.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-thai.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-thai.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-use.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-use.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-use.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-use.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-vowel-constraints.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-vowel-constraints.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-vowel-constraints.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-complex-vowel-constraints.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-fallback.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-fallback.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-fallback.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-fallback.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-normalize.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-normalize.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-normalize.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape-normalize.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-shape.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-tag.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-tag.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-tag.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-tag.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-var.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-var.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-var.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ot-var.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-set.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-set.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-set.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-set.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-shape-plan.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-shape-plan.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-shape-plan.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-shape-plan.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-shape.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-shape.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-shape.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-shape.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-shaper.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-shaper.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-shaper.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-shaper.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-static.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-static.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-static.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-static.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-style.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-style.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-style.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-style.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-cff-common.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-cff-common.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-cff-common.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-cff-common.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-cff1.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-cff1.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-cff1.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-cff1.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-cff2.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-cff2.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-cff2.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-cff2.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-input.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-input.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-input.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-input.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-plan.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-plan.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-plan.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-plan.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-repacker.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-repacker.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-repacker.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset-repacker.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-subset.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ucd.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-ucd.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-ucd.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-ucd.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-unicode.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-unicode.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-unicode.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-unicode.cc diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-uniscribe.cc b/bsp/projects/microej/thirdparty/harfbuzz/src/hb-uniscribe.cc similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/src/hb-uniscribe.cc rename to bsp/projects/microej/thirdparty/harfbuzz/src/hb-uniscribe.cc diff --git a/bsp/projects/microej/thirdparty/harfbuzz/thirdparty_harfbuzz.cmake b/bsp/projects/microej/thirdparty/harfbuzz/thirdparty_harfbuzz.cmake new file mode 100644 index 0000000..d07764d --- /dev/null +++ b/bsp/projects/microej/thirdparty/harfbuzz/thirdparty_harfbuzz.cmake @@ -0,0 +1,9 @@ +include_guard() +message("microej/thirdparty/harfbuzz component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/src/harfbuzz.cc + ${CMAKE_CURRENT_LIST_DIR}/src/hb-alloc.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE ${CMAKE_CURRENT_LIST_DIR}/inc) diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview-freertos/LICENSE b/bsp/projects/microej/thirdparty/systemview-freertos/LICENSE similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview-freertos/LICENSE rename to bsp/projects/microej/thirdparty/systemview-freertos/LICENSE diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview-freertos/inc/SEGGER_SYSVIEW_FreeRTOS.h b/bsp/projects/microej/thirdparty/systemview-freertos/inc/SEGGER_SYSVIEW_FreeRTOS.h similarity index 93% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview-freertos/inc/SEGGER_SYSVIEW_FreeRTOS.h rename to bsp/projects/microej/thirdparty/systemview-freertos/inc/SEGGER_SYSVIEW_FreeRTOS.h index 69cd544..51e96cb 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview-freertos/inc/SEGGER_SYSVIEW_FreeRTOS.h +++ b/bsp/projects/microej/thirdparty/systemview-freertos/inc/SEGGER_SYSVIEW_FreeRTOS.h @@ -153,19 +153,19 @@ Revision: $Rev: 7745 $ #define apiID_XSTREAMBUFFERRECEIVE (110u) #define apiID_XSTREAMBUFFERRECEIVEFROMISR (111u) -#define traceTASK_NOTIFY_TAKE() SEGGER_SYSVIEW_RecordU32x2(apiID_OFFSET + apiID_ULTASKNOTIFYTAKE, xClearCountOnExit, xTicksToWait) +#define traceTASK_NOTIFY_TAKE(uxIndexToWait) SEGGER_SYSVIEW_RecordU32x2(apiID_OFFSET + apiID_ULTASKNOTIFYTAKE, xClearCountOnExit, xTicksToWait) #define traceTASK_DELAY() SEGGER_SYSVIEW_RecordU32 (apiID_OFFSET + apiID_VTASKDELAY, xTicksToDelay) #define traceTASK_DELAY_UNTIL(xTimeToWake) SEGGER_SYSVIEW_RecordVoid (apiID_OFFSET + apiID_VTASKDELAYUNTIL) -#define traceTASK_NOTIFY_GIVE_FROM_ISR() SEGGER_SYSVIEW_RecordU32x2(apiID_OFFSET + apiID_VTASKNOTIFYGIVEFROMISR, SEGGER_SYSVIEW_ShrinkId((U32)pxTCB), (U32)pxHigherPriorityTaskWoken) +#define traceTASK_NOTIFY_GIVE_FROM_ISR(uxIndexToNotify) SEGGER_SYSVIEW_RecordU32x2(apiID_OFFSET + apiID_VTASKNOTIFYGIVEFROMISR, SEGGER_SYSVIEW_ShrinkId((U32)pxTCB), (U32)pxHigherPriorityTaskWoken) #define traceTASK_PRIORITY_INHERIT( pxTCB, uxPriority ) SEGGER_SYSVIEW_RecordU32 (apiID_OFFSET + apiID_VTASKPRIORITYINHERIT, (U32)pxMutexHolder) #define traceTASK_RESUME( pxTCB ) SEGGER_SYSVIEW_RecordU32 (apiID_OFFSET + apiID_VTASKRESUME, SEGGER_SYSVIEW_ShrinkId((U32)pxTCB)) #define traceINCREASE_TICK_COUNT( xTicksToJump ) SEGGER_SYSVIEW_RecordU32 (apiID_OFFSET + apiID_VTASKSTEPTICK, xTicksToJump) #define traceTASK_SUSPEND( pxTCB ) SEGGER_SYSVIEW_RecordU32 (apiID_OFFSET + apiID_VTASKSUSPEND, SEGGER_SYSVIEW_ShrinkId((U32)pxTCB)) #define traceTASK_PRIORITY_DISINHERIT( pxTCB, uxBasePriority ) SEGGER_SYSVIEW_RecordU32 (apiID_OFFSET + apiID_XTASKPRIORITYDISINHERIT, (U32)pxMutexHolder) #define traceTASK_RESUME_FROM_ISR( pxTCB ) SEGGER_SYSVIEW_RecordU32 (apiID_OFFSET + apiID_XTASKRESUMEFROMISR, SEGGER_SYSVIEW_ShrinkId((U32)pxTCB)) -#define traceTASK_NOTIFY() SEGGER_SYSVIEW_RecordU32x4(apiID_OFFSET + apiID_XTASKGENERICNOTIFY, SEGGER_SYSVIEW_ShrinkId((U32)pxTCB), ulValue, eAction, (U32)pulPreviousNotificationValue) -#define traceTASK_NOTIFY_FROM_ISR() SEGGER_SYSVIEW_RecordU32x5(apiID_OFFSET + apiID_XTASKGENERICNOTIFYFROMISR, SEGGER_SYSVIEW_ShrinkId((U32)pxTCB), ulValue, eAction, (U32)pulPreviousNotificationValue, (U32)pxHigherPriorityTaskWoken) -#define traceTASK_NOTIFY_WAIT() SEGGER_SYSVIEW_RecordU32x4(apiID_OFFSET + apiID_XTASKNOTIFYWAIT, ulBitsToClearOnEntry, ulBitsToClearOnExit, (U32)pulNotificationValue, xTicksToWait) +#define traceTASK_NOTIFY(uxIndexToNotify) SEGGER_SYSVIEW_RecordU32x4(apiID_OFFSET + apiID_XTASKGENERICNOTIFY, SEGGER_SYSVIEW_ShrinkId((U32)pxTCB), ulValue, eAction, (U32)pulPreviousNotificationValue) +#define traceTASK_NOTIFY_FROM_ISR(uxIndexToNotify) SEGGER_SYSVIEW_RecordU32x5(apiID_OFFSET + apiID_XTASKGENERICNOTIFYFROMISR, SEGGER_SYSVIEW_ShrinkId((U32)pxTCB), ulValue, eAction, (U32)pulPreviousNotificationValue, (U32)pxHigherPriorityTaskWoken) +#define traceTASK_NOTIFY_WAIT(uxIndexToWait) SEGGER_SYSVIEW_RecordU32x4(apiID_OFFSET + apiID_XTASKNOTIFYWAIT, ulBitsToClearOnEntry, ulBitsToClearOnExit, (U32)pulNotificationValue, xTicksToWait) #define traceQUEUE_CREATE( pxNewQueue ) SEGGER_SYSVIEW_RecordU32x3(apiID_OFFSET + apiID_XQUEUEGENERICCREATE, uxQueueLength, uxItemSize, ucQueueType) #define traceQUEUE_DELETE( pxQueue ) SEGGER_SYSVIEW_RecordU32 (apiID_OFFSET + apiID_VQUEUEDELETE, SEGGER_SYSVIEW_ShrinkId((U32)pxQueue)) diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview-freertos/src/SEGGER_SYSVIEW_FreeRTOS.c b/bsp/projects/microej/thirdparty/systemview-freertos/src/SEGGER_SYSVIEW_FreeRTOS.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview-freertos/src/SEGGER_SYSVIEW_FreeRTOS.c rename to bsp/projects/microej/thirdparty/systemview-freertos/src/SEGGER_SYSVIEW_FreeRTOS.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/LICENSE b/bsp/projects/microej/thirdparty/systemview/LICENSE similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/LICENSE rename to bsp/projects/microej/thirdparty/systemview/LICENSE diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/Global.h b/bsp/projects/microej/thirdparty/systemview/inc/Global.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/Global.h rename to bsp/projects/microej/thirdparty/systemview/inc/Global.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER.h b/bsp/projects/microej/thirdparty/systemview/inc/SEGGER.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER.h rename to bsp/projects/microej/thirdparty/systemview/inc/SEGGER.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER_RTT.h b/bsp/projects/microej/thirdparty/systemview/inc/SEGGER_RTT.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER_RTT.h rename to bsp/projects/microej/thirdparty/systemview/inc/SEGGER_RTT.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER_RTT_configuration.h b/bsp/projects/microej/thirdparty/systemview/inc/SEGGER_RTT_configuration.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER_RTT_configuration.h rename to bsp/projects/microej/thirdparty/systemview/inc/SEGGER_RTT_configuration.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW.h b/bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW.h rename to bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW_ConfDefaults.h b/bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW_ConfDefaults.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW_ConfDefaults.h rename to bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW_ConfDefaults.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW_Int.h b/bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW_Int.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW_Int.h rename to bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW_Int.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW_configuration.h b/bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW_configuration.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW_configuration.h rename to bsp/projects/microej/thirdparty/systemview/inc/SEGGER_SYSVIEW_configuration.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/src/SEGGER_RTT.c b/bsp/projects/microej/thirdparty/systemview/src/SEGGER_RTT.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/src/SEGGER_RTT.c rename to bsp/projects/microej/thirdparty/systemview/src/SEGGER_RTT.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/src/SEGGER_SYSVIEW.c b/bsp/projects/microej/thirdparty/systemview/src/SEGGER_SYSVIEW.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/src/SEGGER_SYSVIEW.c rename to bsp/projects/microej/thirdparty/systemview/src/SEGGER_SYSVIEW.c index 507fc5d..be2fecb 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/systemview/src/SEGGER_SYSVIEW.c +++ b/bsp/projects/microej/thirdparty/systemview/src/SEGGER_SYSVIEW.c @@ -156,6 +156,7 @@ Additional information: #include #include #include +#include /********************************************************************* * diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/trace/inc/LLMJVM_MONITOR_sysview.h b/bsp/projects/microej/trace/inc/LLMJVM_MONITOR_sysview.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/trace/inc/LLMJVM_MONITOR_sysview.h rename to bsp/projects/microej/trace/inc/LLMJVM_MONITOR_sysview.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/trace/inc/LLTRACE_sysview_configuration.h b/bsp/projects/microej/trace/inc/LLTRACE_sysview_configuration.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/trace/inc/LLTRACE_sysview_configuration.h rename to bsp/projects/microej/trace/inc/LLTRACE_sysview_configuration.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/trace/src/LLMJVM_MONITOR_sysview.c b/bsp/projects/microej/trace/src/LLMJVM_MONITOR_sysview.c similarity index 95% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/trace/src/LLMJVM_MONITOR_sysview.c rename to bsp/projects/microej/trace/src/LLMJVM_MONITOR_sysview.c index 963ccdd..d0670b3 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/trace/src/LLMJVM_MONITOR_sysview.c +++ b/bsp/projects/microej/trace/src/LLMJVM_MONITOR_sysview.c @@ -2,6 +2,7 @@ * C * * Copyright 2017-2021 MicroEJ Corp. All rights reserved. + * Copyright 2024 NXP * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -17,7 +18,7 @@ #include #include -#include +#include #include #include #include @@ -99,7 +100,7 @@ void LLMJVM_MONITOR_SYSTEMVIEW_send_task_list(void) { void LLMJVM_MONITOR_IMPL_initialize(bool auto_start) { if(auto_start == true){ - TRACE_start(); + LLTRACE_start(); } SEGGER_SYSVIEW_OnTaskCreate(THREAD_GC_UID); LLMJVM_MONITOR_SYSTEMVIEW_send_gc_thread_info(); diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/trace/src/LLTRACE_sysview.c b/bsp/projects/microej/trace/src/LLTRACE_sysview.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/trace/src/LLTRACE_sysview.c rename to bsp/projects/microej/trace/src/LLTRACE_sysview.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/trace/systemview/SYSVIEW_MicroEJ.txt b/bsp/projects/microej/trace/systemview/SYSVIEW_MicroEJ.txt similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/trace/systemview/SYSVIEW_MicroEJ.txt rename to bsp/projects/microej/trace/systemview/SYSVIEW_MicroEJ.txt diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/buttons_helper.h b/bsp/projects/microej/ui/inc/buttons_helper.h similarity index 84% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/buttons_helper.h rename to bsp/projects/microej/ui/inc/buttons_helper.h index 0e57785..3b15bb1 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/buttons_helper.h +++ b/bsp/projects/microej/ui/inc/buttons_helper.h @@ -2,7 +2,8 @@ * C * * Copyright 2015-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ #if !defined BUTTONS_HELPER_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/buttons_helper_configuration.h b/bsp/projects/microej/ui/inc/buttons_helper_configuration.h similarity index 79% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/buttons_helper_configuration.h rename to bsp/projects/microej/ui/inc/buttons_helper_configuration.h index 262e6a9..4714e7d 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/buttons_helper_configuration.h +++ b/bsp/projects/microej/ui/inc/buttons_helper_configuration.h @@ -2,7 +2,8 @@ * C * * Copyright 2019-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ #if !defined BUTTONS_HELPER_CONFIGURATION_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/buttons_manager.h b/bsp/projects/microej/ui/inc/buttons_manager.h similarity index 82% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/buttons_manager.h rename to bsp/projects/microej/ui/inc/buttons_manager.h index ddef1ba..248b5e9 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/buttons_manager.h +++ b/bsp/projects/microej/ui/inc/buttons_manager.h @@ -2,7 +2,8 @@ * C * * Copyright 2015-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ #if !defined BUTTONS_MANAGER_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/color.h b/bsp/projects/microej/ui/inc/color.h similarity index 92% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/color.h rename to bsp/projects/microej/ui/inc/color.h index 78a5048..fccd170 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/color.h +++ b/bsp/projects/microej/ui/inc/color.h @@ -1,15 +1,16 @@ /* * C * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. + * Copyright 2020-2024 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ /* * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite + * @brief MicroEJ MicroUI library low level API: implementation over VGLite. Provides + * a set of defines to manipulate colors. * @author MicroEJ Developer Team - * @version 3.0.0 + * @version 8.0.1 */ #if !defined COLOR_H diff --git a/bsp/projects/microej/ui/inc/display_configuration.h b/bsp/projects/microej/ui/inc/display_configuration.h new file mode 100644 index 0000000..216c985 --- /dev/null +++ b/bsp/projects/microej/ui/inc/display_configuration.h @@ -0,0 +1,86 @@ +/* + * C + * + * Copyright 2019-2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief Implementation of MicroEJ MicroUI library low level API "LLUI_DISPLAY_impl.h" + * for the NXP MIMXRT595-EVK board. Provides a set of defines to configure the implementation. + * @author MicroEJ Developer Team + */ + +#if !defined DISPLAY_CONFIGURATION_H +# define DISPLAY_CONFIGURATION_H + +#if defined __cplusplus +extern "C" { +#endif + +//#error "This header must be customized with platform specific configuration. Remove this #error when done. This file is not modified when a new version of the CCO is installed." + +/** + * @brief Compatibility sanity check value. + * This define value is checked in the implementation to validate that the version of this configuration + * is compatible with the implementation. + * + * This value must not be changed by the user of the CCO. + * This value must be incremented by the implementor of the CCO when a configuration define is added, deleted or modified. + */ +#define DISPLAY_CONFIGURATION_VERSION (3) + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +/* + * @brief Width of the display panel + */ +#define DISPLAY_PANEL_WIDTH (400) + +/* + * @brief Height of the display panel + */ +#define DISPLAY_PANEL_HEIGHT (392) + +/* + * @brief Width of the frame buffers + */ +#define FRAME_BUFFER_WIDTH (392) + +/* + * @brief Height of the frame buffers + */ +#define FRAME_BUFFER_HEIGHT (392) + +/* + * @brief Source image line alignment (in bytes), required by VGLite library + * when an image is used as source: 32 bits for RGB565 format + * (see _check_source_aligned() in vg_lite.c). + */ +#define VGLITE_IMAGE_LINE_ALIGN_BYTE (32) + +/* + * @brief Frame buffer line alignment (in bytes), required by VGLite library + * when frame buffer is used as source. + * Note: Set (1) to not use the frame buffer as source image. + * Note 2: Require a patch in fsl_dc_fb_dsi_cmd.c + */ +#define FRAME_BUFFER_LINE_ALIGN_BYTE (1) /* 1 | VGLITE_IMAGE_LINE_ALIGN_BYTE */ + +/* + * @brief Available number of frame buffers + */ +#define FRAME_BUFFER_COUNT (2) + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // !defined DISPLAY_CONFIGURATION_H diff --git a/bsp/projects/microej/ui/inc/display_dma.h b/bsp/projects/microej/ui/inc/display_dma.h new file mode 100644 index 0000000..4b411ad --- /dev/null +++ b/bsp/projects/microej/ui/inc/display_dma.h @@ -0,0 +1,88 @@ +/* + * C + * + * Copyright 2020-2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief Implementation of MicroEJ MicroUI library low level API "LLUI_DISPLAY_impl.h" + * for the NXP MIMXRT595-EVK board. Provides a set of functions to drive a DMA (to use + * it as "framebuffer backcopy"). + * @author MicroEJ Developer Team + * @version 7.0.0 + */ + +#if !defined DISPLAY_DMA_H +#define DISPLAY_DMA_H + +#if defined __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include "display_framebuffer.h" +#include "ui_display_brs.h" + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +#if UI_DISPLAY_BRS == UI_DISPLAY_BRS_LEGACY +#define DISPLAY_DMA_ENABLED ( FRAME_BUFFER_COUNT > 1 ) +#endif + +// -------------------------------------------------------------------------------- +// Optional functions to implement (already implemented as weak functions) +// -------------------------------------------------------------------------------- + +/* + * @brief Notifies the DMA will be used just after this call. The implementation + * must ensure the DMA can be used (power management, clocks, etc.). + * + * Default implementation does nothing. + */ +void DISPLAY_DMA_IMPL_notify_dma_start(void) ; + +/* + * @brief Notifies the DMA is not used anymore by the library until the next call to + * DISPLAY_DMA_IMPL_notify_dma_start(). + * + * Default implementation does nothing. + */ +void DISPLAY_DMA_IMPL_notify_dma_stop(void) ; + +// ----------------------------------------------------------------------------- +// API +// ----------------------------------------------------------------------------- + +/* + * @brief: Initialize the DMA synchronization between the framebuffers + * + * @param[in] framebuffers: display framebuffers + */ +void DISPLAY_DMA_initialize(const framebuffer_t * framebuffers[]); + +/* + * @brief: Starts a DMA transfert + * + * @param[in] src: source framebuffer + * @param[in] dst: destination framebuffer + * @param[in] ymin: first line to transfert + * @param[in] ymax: last line to transfert + 1 + */ +void DISPLAY_DMA_start(framebuffer_t *src, framebuffer_t *dst, int ymin, int ymax); + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // !defined DISPLAY_DMA_H diff --git a/bsp/projects/microej/ui/inc/display_framebuffer.h b/bsp/projects/microej/ui/inc/display_framebuffer.h new file mode 100644 index 0000000..3fc4ed2 --- /dev/null +++ b/bsp/projects/microej/ui/inc/display_framebuffer.h @@ -0,0 +1,113 @@ +/* + * C + * + * Copyright 2020-2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief Implementation of MicroEJ MicroUI library low level API "LLUI_DISPLAY_impl.h" + * for the NXP MIMXRT595-EVK board. Provides a set of types to manipulate the frame and + * back buffers. + * @author MicroEJ Developer Team + * @version 7.0.0 + */ + +#if !defined DISPLAY_FRAMEBUFFER_H +#define DISPLAY_FRAMEBUFFER_H + +#if defined __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include + +#include "display_configuration.h" + +// ----------------------------------------------------------------------------- +// Configuration Sanity Check +// ----------------------------------------------------------------------------- + +/** + * Sanity check between the expected version of the configuration and the actual version of + * the configuration. + * If an error is raised here, it means that a new version of the CCO has been installed and + * the configuration display_configuration.h must be updated based on the one provided + * by the new CCO version. + */ + +#if !defined DISPLAY_CONFIGURATION_VERSION +#error "Undefined DISPLAY_CONFIGURATION_VERSION, it must be defined in display_configuration.h" +#endif + +#if defined DISPLAY_CONFIGURATION_VERSION && DISPLAY_CONFIGURATION_VERSION != 3 +#error "Version of the configuration file display_configuration.h is not compatible with this implementation." +#endif + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +/* + * @brief Available number of bytes per pixels (RGB565) + */ +#define FRAME_BUFFER_BYTE_PER_PIXEL (2) + +/* + * @brief Frame buffer alignment. + * - 4 bits are required by SMARTDMA + * - 64 bits are required by DMA + * Note: Full frame buffer memory size is a value aligned on 64 too; + * so next allocation behind frame buffer memory is aligned on 64 too. + */ +#define FRAME_BUFFER_ALIGN (64) + +/* + * @brief Macro to align data + */ +#define ALIGN(value, align) (((value) + (align) - 1) & ~((align) - 1)) + +/* + * @brief Frame buffer line size in bytes (stride), according to FRAME_BUFFER_LINE_ALIGN + */ +#define FRAME_BUFFER_STRIDE_BYTE ALIGN(FRAME_BUFFER_WIDTH * FRAME_BUFFER_BYTE_PER_PIXEL, FRAME_BUFFER_LINE_ALIGN_BYTE) + +/* + * @brief Frame buffer line size in pixels (stride), according to FRAME_BUFFER_LINE_ALIGN + */ +#define FRAME_BUFFER_STRIDE_PIXELS (FRAME_BUFFER_STRIDE_BYTE / FRAME_BUFFER_BYTE_PER_PIXEL) + +// ----------------------------------------------------------------------------- +// Types +// ----------------------------------------------------------------------------- + +/* + * @brief Frame buffer structure definition + */ +typedef struct s_framebuffer { + uint16_t p[FRAME_BUFFER_HEIGHT][FRAME_BUFFER_STRIDE_PIXELS]; +} framebuffer_t; + +// ----------------------------------------------------------------------------- +// Variables +// ----------------------------------------------------------------------------- + +/* + * @brief Frame buffer address array + */ +extern const framebuffer_t * s_frameBufferAddress[FRAME_BUFFER_COUNT]; + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // !defined DISPLAY_FRAMEBUFFER_H diff --git a/bsp/projects/microej/ui/inc/display_impl.h b/bsp/projects/microej/ui/inc/display_impl.h new file mode 100644 index 0000000..c5b70ec --- /dev/null +++ b/bsp/projects/microej/ui/inc/display_impl.h @@ -0,0 +1,70 @@ +/* + * C + * + * Copyright 2022-2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief Implementation of MicroEJ MicroUI library low level API "LLUI_DISPLAY_impl.h" + * for the NXP MIMXRT595-EVK board. Provides a set of functions to extend the implementation. + * @author MicroEJ Developer Team + * @version 7.0.0 + * + * @brief This file lists a set of functions called by the display*.c files. First functions + * are mandatory; optional functions are listed in a second time. + * + * These functions are + * optional and a stub implementation is already available in the CCO (see display_stub.c). + */ + +#if !defined DISPLAY_IMPL_H +#define DISPLAY_IMPL_H + +#if defined __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include +#include + +#include "display_framebuffer.h" + +// -------------------------------------------------------------------------------- +// Optional functions to implement (already implemented as weak functions) +// -------------------------------------------------------------------------------- + +/* + * @brief Notifies the LLUI_DISPLAY_IMPL is initialized. The implementation can + * initialize 3rd-party elements. + * + * Default implementation does nothing. + */ +void DISPLAY_IMPL_initialized(void) ; + +/* + * @brief Notifies the first frame buffer will be used just after this call and + * the second frame buffer will not be used anymore until the next call to + * DISPLAY_IMPL_update_frame_buffer_status(). + * + * Default implementation does nothing. + * + * @param[in] frame_buffer_on: the frame buffer that will be used + * @param[in] frame_buffer_off: the frame buffer that not used anymore + */ +void DISPLAY_IMPL_update_frame_buffer_status(framebuffer_t* frame_buffer_on, framebuffer_t* frame_buffer_off); + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // !defined DISPLAY_IMPL_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/event_generator.h b/bsp/projects/microej/ui/inc/event_generator.h similarity index 93% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/event_generator.h rename to bsp/projects/microej/ui/inc/event_generator.h index f538886..c980de8 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/event_generator.h +++ b/bsp/projects/microej/ui/inc/event_generator.h @@ -2,7 +2,8 @@ * C * * Copyright 2014-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ /* diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/framerate.h b/bsp/projects/microej/ui/inc/framerate.h similarity index 86% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/framerate.h rename to bsp/projects/microej/ui/inc/framerate.h index d539912..a3fa5a9 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/framerate.h +++ b/bsp/projects/microej/ui/inc/framerate.h @@ -2,7 +2,8 @@ * C * * Copyright 2014-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ #if !defined FRAMERATE_H #define FRAMERATE_H diff --git a/bsp/projects/microej/ui/inc/framerate_conf.h b/bsp/projects/microej/ui/inc/framerate_conf.h new file mode 100644 index 0000000..1f6388d --- /dev/null +++ b/bsp/projects/microej/ui/inc/framerate_conf.h @@ -0,0 +1,22 @@ +/* + * C + * + * Copyright 2014-2020 MicroEJ Corp. All rights reserved. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. + */ +#if !defined FRAMERATE_CONF_H +#define FRAMERATE_CONF_H + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +/* + * @brief Change value to disable/enable the framerate monitoring: + * 0: Disables the framerate monitoring + * 1: Enables the framerate monitoring + */ +#define FRAMERATE_ENABLED 1 + +#endif // !defined FRAMERATE_CONF_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/framerate_impl.h b/bsp/projects/microej/ui/inc/framerate_impl.h similarity index 82% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/framerate_impl.h rename to bsp/projects/microej/ui/inc/framerate_impl.h index 5de3df8..0f7398c 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/framerate_impl.h +++ b/bsp/projects/microej/ui/inc/framerate_impl.h @@ -2,7 +2,8 @@ * C * * Copyright 2014-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ /* diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/microui_event_decoder.h b/bsp/projects/microej/ui/inc/microui_event_decoder.h similarity index 91% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/microui_event_decoder.h rename to bsp/projects/microej/ui/inc/microui_event_decoder.h index 6140069..e53705d 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/microui_event_decoder.h +++ b/bsp/projects/microej/ui/inc/microui_event_decoder.h @@ -1,7 +1,7 @@ /* * C * - * Copyright 2021-2022 MicroEJ Corp. All rights reserved. + * Copyright 2021-2024 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -9,13 +9,12 @@ * @file * @brief See microui_event_decoder.c. * @author MicroEJ Developer Team - * @version 2.0.0 - * @date 22 July 2022 + * @version 4.0.1 * @since MicroEJ UI Pack 13.1.0 */ #if !defined MICROUI_EVENT_DECODER_H -# define MICROUI_EVENT_DECODER_H +#define MICROUI_EVENT_DECODER_H // ----------------------------------------------------------------------------- // Includes @@ -32,7 +31,7 @@ extern "C" { #endif #ifdef MICROUIEVENTDECODER_ENABLED - + // ----------------------------------------------------------------------------- // Types // ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/microui_event_decoder_conf.h b/bsp/projects/microej/ui/inc/microui_event_decoder_conf.h similarity index 93% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/microui_event_decoder_conf.h rename to bsp/projects/microej/ui/inc/microui_event_decoder_conf.h index 37342d7..0d8cbf6 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/microui_event_decoder_conf.h +++ b/bsp/projects/microej/ui/inc/microui_event_decoder_conf.h @@ -1,7 +1,7 @@ /* * C * - * Copyright 2021-2022 MicroEJ Corp. All rights reserved. + * Copyright 2021-2024 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -9,13 +9,12 @@ * @file * @brief This file allows to configure the implementation of microui_event_decoder.c. * @author MicroEJ Developer Team - * @version 2.0.0 - * @date 22 July 2022 + * @version 4.0.1 * @since MicroEJ UI Pack 13.1.0 */ #if !defined MICROUI_EVENT_DECODER_CONF_H -# define MICROUI_EVENT_DECODER_CONF_H +#define MICROUI_EVENT_DECODER_CONF_H // ----------------------------------------------------------------------------- // Includes diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/microui_heap.h b/bsp/projects/microej/ui/inc/microui_heap.h similarity index 90% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/microui_heap.h rename to bsp/projects/microej/ui/inc/microui_heap.h index 665d5fb..70393f3 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/microui_heap.h +++ b/bsp/projects/microej/ui/inc/microui_heap.h @@ -1,7 +1,7 @@ /* * C * - * Copyright 2021-2022 MicroEJ Corp. All rights reserved. + * Copyright 2021-2024 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -9,13 +9,12 @@ * @file * @brief See LLUI_DISPLAY_HEAP_impl.c. * @author MicroEJ Developer Team - * @version 2.0.0 - * @date 22 July 2022 + * @version 4.0.1 * @since MicroEJ UI Pack 13.1.0 */ #if !defined MICROUI_HEAP_H -# define MICROUI_HEAP_H +#define MICROUI_HEAP_H // ----------------------------------------------------------------------------- // Includes diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/touch_helper.h b/bsp/projects/microej/ui/inc/touch_helper.h similarity index 81% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/touch_helper.h rename to bsp/projects/microej/ui/inc/touch_helper.h index 6fda552..c0bbb62 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/touch_helper.h +++ b/bsp/projects/microej/ui/inc/touch_helper.h @@ -2,7 +2,8 @@ * C * * Copyright 2015-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ #if !defined TOUCH_HELPER_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/touch_helper_configuration.h b/bsp/projects/microej/ui/inc/touch_helper_configuration.h similarity index 76% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/touch_helper_configuration.h rename to bsp/projects/microej/ui/inc/touch_helper_configuration.h index 26fd85b..97060da 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/touch_helper_configuration.h +++ b/bsp/projects/microej/ui/inc/touch_helper_configuration.h @@ -2,7 +2,8 @@ * C * * Copyright 2019-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ #if !defined TOUCH_HELPER_CONFIGURATION_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/touch_manager.h b/bsp/projects/microej/ui/inc/touch_manager.h similarity index 78% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/touch_manager.h rename to bsp/projects/microej/ui/inc/touch_manager.h index 2b38f1a..76ae8ed 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/touch_manager.h +++ b/bsp/projects/microej/ui/inc/touch_manager.h @@ -2,7 +2,8 @@ * C * * Copyright 2015-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ #if !defined TOUCH_MANAGER_H diff --git a/bsp/projects/microej/ui/inc/ui_display_brs.h b/bsp/projects/microej/ui/inc/ui_display_brs.h new file mode 100644 index 0000000..a99e9d6 --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_display_brs.h @@ -0,0 +1,105 @@ +/* + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#ifndef UI_DISPLAY_BRS_H +#define UI_DISPLAY_BRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @file + * @brief Provides some implementations of the LLUI_DISPLAY_impl.h functions relating + * to the display buffer strategy (BRS). + * + * A BRS + * - implements the LLUI_DISPLAY_impl.h's API LLUI_DISPLAY_IMPL_refresh() and + * LLUI_DISPLAY_IMPL_newDrawingRegion(). + * - calls the LLUI_DISPLAY_impl.h's API LLUI_DISPLAY_IMPL_flush() to let the display + * driver transmit / copy / flush back buffer data to the front buffer or swap back and + * front buffer (double or triple buffer management). + * - ensures the coherence of the back buffer's content before and after a flush. + * + * Several BRS are available in ui_display_brs_configuration.h (the implementation has + * to select one of them). + * + * @author MicroEJ Developer Team + * @version 4.0.1 + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include + +#include "ui_util.h" +#include "ui_display_brs_configuration.h" +#include "ui_log.h" + +// ----------------------------------------------------------------------------- +// Configuration Sanity Check +// ----------------------------------------------------------------------------- + +/** + * Sanity check between the expected version of the configuration and the actual version of + * the configuration. + * If an error is raised here, it means that a new version of the CCO has been installed and + * the configuration ui_display_brs_configuration.h must be updated based on the one provided + * by the new CCO version. + */ + +#if !defined UI_DISPLAY_BRS_CONFIGURATION_VERSION +#error "Undefined UI_DISPLAY_BRS_CONFIGURATION_VERSION, it must be defined in ui_display_brs_configuration.h" +#endif + +#if defined UI_DISPLAY_BRS_CONFIGURATION_VERSION && UI_DISPLAY_BRS_CONFIGURATION_VERSION != 1 +#error "Version of the configuration file ui_display_brs_configuration.h is not compatible with this implementation." +#endif + +// ----------------------------------------------------------------------------- +// Macros and defines +// ----------------------------------------------------------------------------- + +/* + * @brief Logs a region (a rectangle) + */ +#define LOG_REGION(log,rect) LLTRACE_record_event_u32x4((LLUI_EVENT_group), (LLUI_EVENT_offset) + (log), (rect)->x1, (rect)->y1, (rect)->x2, (rect)->y2) + + +// -------------------------------------------------------------------------------- +// Display BRS public API +// -------------------------------------------------------------------------------- + +/* + * @brief Restores (copies) the given rectangular region from old back buffer to the graphics + * context's current buffer (the destination buffer can be retrieved thanks + * LLUI_DISPLAY_getBufferAddress(&gc->image)). + * + * When the copy is synchronous (immediate), the implementation has to return + * DRAWING_DONE. When the copy is asynchronous (performed by a DMA for instance), the + * the implementation has to return DRAWING_RUNNING. As the end of the asynchronous + * copy, the implementation has to call LLUI_DISPLAY_notifyAsynchronousDrawingEnd() + * to unlock the caller of this function. + * + * The implementation of this function is optional; a weak function provides a simple + * implementation using memcpy(). + * + * @param[in] gc the MicroUI GraphicsContext that targets the current back buffer + * @param[in] old_back_buffer a MicroUI Image that symbolizes (targets) the old back buffer. + * @param[in] rect the rectangular region to copy from old back buffer to new back + * buffer. + */ +DRAWING_Status UI_DISPLAY_BRS_restore(MICROUI_GraphicsContext* gc, MICROUI_Image* old_back_buffer, ui_rect_t* rect); + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif // UI_DISPLAY_BRS_H diff --git a/bsp/projects/microej/ui/inc/ui_display_brs_configuration.h b/bsp/projects/microej/ui/inc/ui_display_brs_configuration.h new file mode 100644 index 0000000..9d83a14 --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_display_brs_configuration.h @@ -0,0 +1,144 @@ +/* + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#ifndef UI_DISPLAY_BRS_CONFIGURATION_H +#define UI_DISPLAY_BRS_CONFIGURATION_H +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @file + * @brief Provides some implementations of the LLUI_DISPLAY_impl.h functions relating + * to the display buffer strategy (BRS). + * + * Several BRS are available. This header file allows to select an existing BRS or to + * let the BSP implements its own strategy. Note that if no strategy is used, the default + * Graphics Engine's strategy is used that consists to only called LLUI_DISPLAY_IMPL_flush() + * (always full screen, no restore). + * + * @author MicroEJ Developer Team + * @version 4.0.1 + */ + +//#error "This header must be customized with VEE Port specific configuration. Remove this #error when done. This file is not modified when a new version of the CCO is installed." + +/* + * @brief Compatibility sanity check value. + * This define value is checked in the implementation to validate that the version of this configuration + * is compatible with the implementation. + * + * This value must not be changed by the user of the CCO. + * This value must be incremented by the implementor of the CCO when a configuration define is added, deleted or modified. + */ +#define UI_DISPLAY_BRS_CONFIGURATION_VERSION (1) + +// ----------------------------------------------------------------------------- +// Display Buffer Refresh Strategies (BRS) +// ----------------------------------------------------------------------------- + +/* + * @brief Defines the "legacy" strategy (equivalent to the one available in UI Packs 13.x) + * dedicated to the buffer policy SWAP (see MicroEJ documentation). + */ +#define UI_DISPLAY_BRS_LEGACY (0u) + +/* + * @brief Defines the "single" strategy dedicated to the display with one buffer on the MCU side + * and one buffer on the display side (the front buffer is not mapped to the MCU address + * space). The refresh consists in transmitting the back buffer data to the front buffer. The + * content to transmit is a list of rectangles that have been modified since last flush or an + * unique rectangle that encapsulates all regions (see the option UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE). + * + * Note: the maximum number of rectangles given as parameter to the function + * LLUI_DISPLAY_IMPL_flush() is equal to UI_RECT_COLLECTION_MAX_LENGTH. + */ +#define UI_DISPLAY_BRS_SINGLE (1u) + +/* + * @brief Defines the "predraw" strategy that consists in restoring the back buffer with the + * content of the previous drawings (the past) just before the very first drawing after a + * flush (and not just after the flush). + * + * This strategy requires the available number of back buffers (i.e. the number of buffers + * where the drawings can be performed): + * + * #define UI_DISPLAY_BRS_DRAWING_BUFFER_COUNT (2u) + * + * This strategy manages, by default, two or three back buffers. Its implementation can be + * easily modified to manage more back buffers. An error is thrown if the code is not modified + * and the number of back buffers is higher than three. + * + * A warning is thrown if there is only one back buffer because this strategy is optimized + * for two or more back buffers. However, this strategy works with only one buffer but it + * is a little bit too complex for this use case. + * + * Notes: + * - The maximum number of rectangles given as parameter to the function LLUI_DISPLAY_IMPL_flush() + * is equal to UI_RECT_COLLECTION_MAX_LENGTH. + * - This BRS takes in consideration the option UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE. + */ +#define UI_DISPLAY_BRS_PREDRAW (2u) + +// ----------------------------------------------------------------------------- +// Display BRS Implementation and Options +// ----------------------------------------------------------------------------- + +/* + * @brief Defines the display buffer strategy (BRS) to use: one of the strategies above, + * the Graphics Engine's default flush strategy or a BSP's custom flush strategy. + * + * When not set, the BSP has to implement the LLUI_DISPLAY_impl.h's API to define its custom + * display buffer strategy (otherwise the basic Graphics Engine's strategy will be used, see + * file comment). + */ +#ifndef UI_DISPLAY_BRS +#define UI_DISPLAY_BRS (UI_DISPLAY_BRS_PREDRAW) +#endif + +/* + * @brief Defines the available number of drawing buffers; in other words, the number of buffers the + * Graphics Engine can use to draw into. According to the display BRS and the LCD connection, a drawing + * buffer can be alternatively a back buffer (the buffer currently used by the Graphics Engine), a + * front buffer (the buffer currently used by the LCD driver to map the LCD device), a transmission + * buffer (the buffer currently used by the LCD driver to transmit the data to the LCD device) or a free + * buffer (a buffer currently unused). + * + * Warning: This counter only defines the buffers the Graphics Engine can use and not the buffer reserved + * to the LCD device (mapped or or not on the MCU address space). + */ +#ifndef UI_DISPLAY_BRS_DRAWING_BUFFER_COUNT +#define UI_DISPLAY_BRS_DRAWING_BUFFER_COUNT (2u) +#endif + +/* + * @brief Defines the number of rectangles the strategy uses when calling LLUI_DISPLAY_IMPL_flush(). + * When set, the strategy gives only one rectangle that includes all dirty regions (a rectangle that + * encapsulates all rectangles). When not set, the strategy gives all rectangles. + * + * When the implementation of LLUI_DISPLAY_IMPL_flush() only consists to swap the back buffers, the + * rectangles list is useless. + * + * When the implementation of LLUI_DISPLAY_IMPL_flush() consists to transmit an unique portion of the + * back buffer (for instance: the back buffer is transmitted to the LCD through a DSI bus), the single + * rectangle mode is useful. + * + * When the implementation of LLUI_DISPLAY_IMPL_flush() consists to transmit several portions of the back + * buffer (for instance: the back buffer is transmitted to the LCD through a SPI bus), the rectangle list + * is useful. + * + * By default, the rectangles list is given as-is (the option is not enabled). + * @see the strategies comments to have more information on the use of this option. + */ +//#define UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif // UI_DISPLAY_BRS_CONFIGURATION_H diff --git a/bsp/projects/microej/ui/inc/ui_drawing.h b/bsp/projects/microej/ui/inc/ui_drawing.h new file mode 100644 index 0000000..464f3d9 --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_drawing.h @@ -0,0 +1,844 @@ +/* + * Copyright 2020-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#if !defined UI_DRAWING_H +#define UI_DRAWING_H +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @brief Provides drawing functions called by MicroUI native drawing functions. + * + * Default MicroUI native drawing functions implementations manage the synchronization + * with the Graphics Engine and allow a third party drawer perform the drawings. + * + * This header file lists all drawing functions to implement. This cut between MicroUI + * native functions default implementation and this file allows to simplify the + * writing of drawing functions: a drawing function has just to consider the drawing + * itself and not the synchronization with the Graphics Engine. + * + * The drawer has the responsibility to check the graphics context (when not disabled + * by caller) and to update the new flush dirty region. + * + * This cut simplifies the MicroUI native function implementation, which becomes: + * + * void _drawing_native_xxx(MICROUI_GraphicsContext* gc, ...) { + * // tell to the Graphics Engine if drawing can be performed + * if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&_drawing_native_xxx)) { + * // perform the drawings and set drawing status + * LLUI_DISPLAY_setDrawingStatus(_drawing_xxx(gc, ...)); + * } + * // else: refused drawing + * } + * + * When clip is checked very early, the native implementation becomes: + * + * void _drawing_native_xxx(MICROUI_GraphicsContext* gc, ...) { + * // tell to the Graphics Engine if drawing can be performed + * if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&_drawing_native_xxx)) { + * DRAWING_Status status; + * + * if (LLUI_DISPLAY_isInClip(gc, ...)) { + * // perform the drawings + * status = _drawing_xxx(gc, ...); + * } + * else { + * // drawing is out of clip: nothing to draw + * status = DRAWING_DONE; + * } + * + * // set drawing status + * LLUI_DISPLAY_setDrawingStatus(status); + * } + * // else: refused drawing + * } + * + * This cut allows to use a third party drawer like a dedicated CPU (hardware accelerator). + * However, all drawing functions are already implemented in ui_drawing.c as + * weak implementation. This allows to override one or several functions without + * the need to override all functions. Default ui_drawing.c implementation calls the + * Graphics Engine software algorithms. + * + * The Graphics Engine software algorithms are listed in ui_drawing_soft.h. + * This allows to the ui_drawing.h to test if it is able to perform a drawing and + * if not, to call the software algorithm instead. For instance a GPU may be able + * to draw an image applying a rotation but it can't apply this rotation and an opacity + * at the same time. In this case, the drawing implementation function has to check + * the parameter "alpha" and calls or not Graphics Engine software algorithm. + * + * The implementation of these drawings must respect the graphics context clip and + * the flush dirty region as explained in LLUI_PAINTER_impl.h. + * + * @author MicroEJ Developer Team + * @version 4.0.1 + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include +#include + +// -------------------------------------------------------------------------------- +// Defines +// -------------------------------------------------------------------------------- + +/* + * @brief Concat two defines + */ +#ifndef CONCAT +#define CONCAT0(p,s) p ## s +#define CONCAT(p,s) CONCAT0(p,s) +#endif + +// -------------------------------------------------------------------------------- +// API +// -------------------------------------------------------------------------------- + +#if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +/* + * @brief Tells if drawer "1" matches the destination format. The VEE port must implement + * this function when it includes the support to target the destination format. It not, the + * default weak implementation in ui_drawing.c redirects all the drawings for this destination + * format in the stub implementation. + */ +bool UI_DRAWING_is_drawer_1(jbyte image_format); + +#if (LLUI_GC_SUPPORTED_FORMATS > 2) +/* + * @brief Tells drawer "2" matches the destination format. See UI_DRAWING_is_drawer_1. + */ +bool UI_DRAWING_is_drawer_2(jbyte image_format); + +#endif // #if (LLUI_GC_SUPPORTED_FORMATS > 2) + +#endif // #if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +/* + * @brief Returns the new image row stride in bytes. + * + * @param[in] image_format the new RAW image format. The format is one value from the + * MICROUI_ImageFormat enumeration. + * @param[in] image_width the new image width (in pixels). + * @param[in] image_height the new image height (in pixels). + * @param[in] default_stride the minimal row stride (in bytes) + * + * @return expected row stride (in bytes) + * + * @see LLUI_DISPLAY_IMPL_getNewImageStrideInBytes() + */ +uint32_t UI_DRAWING_getNewImageStrideInBytes(jbyte image_format, uint32_t image_width, uint32_t image_height, uint32_t default_stride); + +/* + * @brief Adjusts the new image characteristics: data size and alignment. + * + * @param[in] image_format the new RAW image format. The format is one value from the + * MICROUI_ImageFormat enumeration. + * @param[in] width the new image width (in pixels). + * @param[in] height the new image height (in pixels). + * @param[in/out] data_size the minimal data size (in bytes). + * @param[in/out] data_alignment the minimal data alignment to respect (in bytes). + * + * @see LLUI_DISPLAY_IMPL_adjustNewImageCharacteristics() + */ +void UI_DRAWING_adjustNewImageCharacteristics(jbyte image_format, uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment); + +/* + * @brief Initializes the image's buffer. + * + * @param[in] image the MicroUI Image to initialize. + * + * @see LLUI_DISPLAY_IMPL_initializeNewImage() + */ +void UI_DRAWING_initializeNewImage(MICROUI_Image* image); + +/* + * @brief Frees the image's resources (if any). This function is called just before releasing + * the image buffer and closing the image. + * + * @param[in] image the MicroUI Image to close. + * + * @see LLUI_DISPLAY_IMPL_freeImageResources() + */ +void UI_DRAWING_freeImageResources(MICROUI_Image* image); + +/* + * @brief Draws a pixel at given position. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the pixel X coordinate. + * @param[in] y the pixel Y coordinate. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_writePixel(MICROUI_GraphicsContext* gc, jint x, jint y); + +/* + * @brief Draws a line at between points startX,startY (included) and endX,endY (included). + * Note: startX may be higher than endX (and/or startY may be higher than endY). + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] startX the first pixel line X coordinate. + * @param[in] startY the first pixel line Y coordinate. + * @param[in] endX the last pixel line X coordinate. + * @param[in] endY the last pixel line Y coordinate. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY); + +/* + * @brief Draws a horizontal line at between points x1,y (included) and x2,y (included). + * Caller ensures that x1 <= x2. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x1 the first pixel line X coordinate. + * @param[in] x2 the last pixel line X coordinate. + * @param[in] y the both pixels line Y coordinate. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawHorizontalLine(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y); + +/* + * @brief Draws a vertical line at between points x,y1 (included) and x,y2 (included). + * Caller ensures that y1 <= y2. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the both pixels line X coordinate. + * @param[in] y1 the first pixel line Y coordinate. + * @param[in] y2 the last pixel line Y coordinate. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawVerticalLine(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2); + +/* + * @brief Draws an orthogonal rectangle at from top-left point x1,y1 (included) and bottom-right + * point x2,y2 (included). + * Caller ensures that x1 <= x2 and y1 <= y2. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x1 the top-left pixel X coordinate. + * @param[in] y1 the top-left pixel Y coordinate. + * @param[in] x2 the bottom-right pixel X coordinate. + * @param[in] y2 the top-right pixel Y coordinate. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); + +/* + * @brief Fills a rectangle at from top-left point x1,y1 (included) and bottom-right + * point x2,y2 (included). + * Caller ensures that x1 <= x2 and y1 <= y2. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x1 the top-left pixel X coordinate. + * @param[in] y1 the top-left pixel Y coordinate. + * @param[in] x2 the bottom-right pixel X coordinate. + * @param[in] y2 the top-right pixel Y coordinate. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_fillRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); + +/* + * @brief Draws a rounded rectangle at from top-left point x,y (included) and bottom-right + * point x+width-1,y+height-1 (included). + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the top-left pixel X coordinate. + * @param[in] y the top-left pixel Y coordinate. + * @param[in] width the rectangle width. + * @param[in] height the rectangle height. + * @param[in] cornerEllipseWidth the horizontal diameter of the arc at the corners. + * @param[in] cornerEllipseHeight the vertical diameter of the arc at the corners. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); + +/* + * @brief Fills a rounded rectangle at from top-left point x,y (included) and bottom-right + * point x+width-1,y+height-1 (included). + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the top-left pixel X coordinate. + * @param[in] y the top-left pixel Y coordinate. + * @param[in] width the rectangle width. + * @param[in] height the rectangle height. + * @param[in] cornerEllipseWidth the horizontal diameter of the arc at the corners. + * @param[in] cornerEllipseHeight the vertical diameter of the arc at the corners. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_fillRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); + +/* + * @brief Draws a circular arc covering the square defined by top-left point x,y (included) + * and bottom-right point x+diameter-1,y+diameter-1 (included). + * + * The arc is drawn from startAngle up to arcAngle degrees. The center of the arc is + * defined as the center of the square whose origin is at (x,y) (upper-left corner) + * and whose dimension is given by width and height. + * + * Angles are interpreted such that 0 degrees is at the 3 o'clock position. A positive + * value indicates a counter-clockwise rotation while a negative value indicates + * a clockwise rotation. + * + * If either the given diameter is negative or zero, or if arcAngle is zero, + * nothing is drawn. + * + * The angles are given relative to the square. For instance an angle of 45 + * degrees is always defined by the line from the center of the square to the + * upper right corner of the square. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the top-left pixel X coordinate. + * @param[in] y the top-left pixel Y coordinate. + * @param[in] square the diameter of the arc to draw. + * @param[in] startAngle the beginning angle of the arc to draw + * @param[in] arcAngle the angular extent of the arc from startAngle + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Draws an elliptical arc covering the rectangle defined by top-left point x,y (included) + * and bottom-right point x+width-1,y+height-1 (included). + * + * The arc is drawn from startAngle up to arcAngle degrees. The center of the arc is + * defined as the center of the rectangle whose origin is at (x,y) (upper-left corner) + * and whose dimension is given by width and height. + * + * Angles are interpreted such that 0 degrees is at the 3 o'clock position. A positive + * value indicates a counter-clockwise rotation while a negative value indicates + * a clockwise rotation. + * + * If either the given width or height is negative or zero, or if arcAngle is zero, + * nothing is drawn. + * + * The angles are given relative to the rectangle. For instance an angle of 45 + * degrees is always defined by the line from the center of the rectangle to the + * upper right corner of the rectangle. Thus for a non squared rectangle + * angles are skewed along either height or width. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the top-left pixel X coordinate. + * @param[in] y the top-left pixel Y coordinate. + * @param[in] width the rectangle width. + * @param[in] height the rectangle height. + * @param[in] startAngle the beginning angle of the arc to draw + * @param[in] arcAngle the angular extent of the arc from startAngle + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Fills a circular arc covering the square defined by top-left point x,y (included) + * and bottom-right point x+diameter-1,y+diameter-1 (included). + * + * The arc is drawn from startAngle up to arcAngle degrees. The center of the arc is + * defined as the center of the rectangle whose origin is at (x,y) (upper-left corner) + * and whose dimension is given by width and height. + * + * Angles are interpreted such that 0 degrees is at the 3 o'clock position. A positive + * value indicates a counter-clockwise rotation while a negative value indicates + * a clockwise rotation. + * + * If either the given diameter is negative or zero, or if arcAngle is zero, + * nothing is drawn. + * + * The angles are given relative to the square. For instance an angle of 45 + * degrees is always defined by the line from the center of the square to the + * upper right corner of the square. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the top-left pixel X coordinate. + * @param[in] y the top-left pixel Y coordinate. + * @param[in] diameter the diameter of the arc to draw. + * @param[in] startAngle the beginning angle of the arc to draw + * @param[in] arcAngle the angular extent of the arc from startAngle + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_fillCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Fills an elliptical arc covering the rectangle defined by top-left point x,y (included) + * and bottom-right point x+width-1,y+height-1 (included). + * + * The arc is drawn from startAngle up to arcAngle degrees. The center of the arc is + * defined as the center of the rectangle whose origin is at (x,y) (upper-left corner) + * and whose dimension is given by width and height. + * + * Angles are interpreted such that 0 degrees is at the 3 o'clock position. A positive + * value indicates a counter-clockwise rotation while a negative value indicates + * a clockwise rotation. + * + * If either the given width or height is negative or zero, or if arcAngle is zero, + * nothing is drawn. + * + * The angles are given relative to the rectangle. For instance an angle of 45 + * degrees is always defined by the line from the center of the rectangle to the + * upper right corner of the rectangle. Thus for a non squared rectangle + * angles are skewed along either height or width. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the top-left pixel X coordinate. + * @param[in] y the top-left pixel Y coordinate. + * @param[in] width the rectangle width. + * @param[in] height the rectangle height. + * @param[in] startAngle the beginning angle of the arc to draw + * @param[in] arcAngle the angular extent of the arc from startAngle + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_fillEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Draws an ellipse covering the rectangle defined by top-left point x,y (included) + * and bottom-right point x+width-1,y+height-1 (included). Ellipses which focal points are not + * on the same axis are not supported. + * + * If either the given width or height is negative or zero, nothing is drawn. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the top-left pixel X coordinate. + * @param[in] y the top-left pixel Y coordinate. + * @param[in] width the ellipse width. + * @param[in] height the ellipse height. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); + +/* + * @brief Fills an ellipse covering the rectangle defined by top-left point x,y (included) + * and bottom-right point x+width-1,y+height-1 (included). + * + * If either the given width or height is negative or zero, nothing is drawn. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the top-left pixel X coordinate. + * @param[in] y the top-left pixel Y coordinate. + * @param[in] width the ellipse width. + * @param[in] height the ellipse height. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_fillEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); + +/* + * @brief Draws a circle covering the square defined by top-left point x,y (included) + * and bottom-right point x+diameter-1,y+diameter-1 (included). + * + * If the given diameter is negative or zero, nothing is drawn. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the top-left pixel X coordinate. + * @param[in] y the top-left pixel Y coordinate. + * @param[in] diameter the circle square size. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); + +/* + * @brief Fills a circle covering the square defined by top-left point x,y (included) + * and bottom-right point x+diameter-1,y+diameter-1 (included) + * + * If the given diameter is negative or zero, nothing is drawn. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the top-left pixel X coordinate. + * @param[in] y the top-left pixel Y coordinate. + * @param[in] diameter the circle square size. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_fillCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); + +/* + * @brief Draws a region of an image. + * + * The image and the destination (MICROUI_GraphicsContext) never target the same image. See + * UI_DRAWING_copyImage() and UI_DRAWING_drawRegion(). + * + * The region of the image to draw is given relative to the image (origin at the + * upper-left corner) as a rectangle. + * + * If the specified source region exceeds the image bounds, the copied region is + * limited to the image boundary. If the copied region goes out of the bounds of + * the graphics context area, pixels out of the range will not be drawn. + * + * A global opacity value is given. When this value is 0xff (255, opaque), that means the image + * is drawn on the graphics context without managing an extra opacity. Only the image transparent + * pixels must have been merged with destination. All image opaque pixels override destination. + * + * When this value is a value between 0 and 0xff, that means each pixel of the image must be merged + * with destination in addition with the image transparent pixels. An image opaque pixel becomes + * transparent (its opacity is the given alpha) and the opacity of an image transparent pixel becomes + * (alpha * alpha(pixel)) / 255. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] img the MicroUI Image to draw. + * @param[in] regionX the x coordinate of the upper-left corner of the region to copy. + * @param[in] regionY the y coordinate of the upper-left corner of the region to copy. + * @param[in] width the width of the region to copy. + * @param[in] height the height of the region to copy. + * @param[in] x the x coordinate of the top-left point in the destination. + * @param[in] y the y coordinate of the top-left point in the destination. + * @param[in] alpha the opacity level to apply to the region. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); + +/* + * @brief Copy a region of an image in another image with the same pixel format. + * + * Contrary to UI_DRAWING_drawImage(), the opacity is not an option. As the source and destination + * have the same pixel representation, this function has just to perform a "memory copy". + * + * The region of the image to draw is given relative to the image (origin at the + * upper-left corner) as a rectangle. + * + * If the specified source region exceeds the image bounds, the copied region is + * limited to the image boundary. If the copied region goes out of the bounds of + * the graphics context area, pixels out of the range will not be drawn. + * + * The image and the destination (MICROUI_GraphicsContext) may target the same image. By consequence, + * the implementation has to check the "overlap" use-case: the region to copy overlaps the destination + * region. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] img the MicroUI Image to copy. + * @param[in] regionX the x coordinate of the upper-left corner of the region to copy. + * @param[in] regionY the y coordinate of the upper-left corner of the region to copy. + * @param[in] width the width of the region to copy. + * @param[in] height the height of the region to copy. + * @param[in] x the x coordinate of the top-left point in the destination. + * @param[in] y the y coordinate of the top-left point in the destination. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_copyImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); + +/* + * @brief Draw a region of an image in the same image. + * + * Contrary to UI_DRAWING_drawImage(), the implementation has to check the "overlap" use-case: + * the region to copy overlaps the destination region. + * + * The region of the image to draw is given relative to the image (origin at the + * upper-left corner) as a rectangle. + * + * If the specified source region exceeds the image bounds, the copied region is + * limited to the image boundary. If the copied region goes out of the bounds of + * the graphics context area, pixels out of the range will not be drawn. + * + * @param[in] gc the MicroUI GraphicsContext source and target. + * @param[in] regionX the x coordinate of the upper-left corner of the region to copy. + * @param[in] regionY the y coordinate of the upper-left corner of the region to copy. + * @param[in] width the width of the region to copy. + * @param[in] height the height of the region to copy. + * @param[in] x the x coordinate of the top-left point in the destination. + * @param[in] y the y coordinate of the top-left point in the destination. + * @param[in] alpha the opacity level to apply to the region. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawRegion(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); + +/* + * @brief Draws a thick point with fade at given position. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the point X coordinate. + * @param[in] y the point Y coordinate. + * @param[in] thickness the point thickness. + * @param[in] fade the fade to apply. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawThickFadedPoint(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade); + +/* + * @brief Draws a thick line with fade between given points. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] startX the x coordinate of the start of the line + * @param[in] startY the y coordinate of the start of the line + * @param[in] endX the x coordinate of the end of the line + * @param[in] endY the y coordinate of the end of the line + * @param[in] thickness the line thickness. + * @param[in] fade the fade to apply. + * @param[in] startCap cap representation of start of shape + * @param[in] endCap cap representation of end of shape + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawThickFadedLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap); + +/* + * @brief Draws a thick circle with fade covering the square specified by its diameter. + * + * If diameter is negative or zero, nothing is drawn. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the x coordinate of the upper-left corner of the square where the circle is drawn + * @param[in] y the y coordinate of the upper-left corner of the square where the circle is drawn + * @param[in] diameter the diameter of the circle to draw + * @param[in] thickness the circle thickness. + * @param[in] fade the fade to apply. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawThickFadedCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade); + +/* + * @brief Draws a thick circle with fade arc covering the specified square. + * + * The arc is drawn from startAngle up to arcAngle degrees. The center of the arc + * is defined as the center of the square whose origin is at (x,y) (upper-left + * corner) and whose dimension is given by diameter. + * + * Angles are interpreted such that 0 degrees is at the 3 o'clock position. A positive + * value indicates a counter-clockwise rotation while a negative value indicates + * a clockwise rotation. + * + * If diameter is negative or zero, nothing is drawn. + * + * The angles are given relative to the square. For instance an angle of 45 degrees + * is always defined by the line from the center of the square to the upper right + * corner of the square. Thus for a non squared square angles are skewed along + * either height or width. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the x coordinate of the upper-left corner of the square where the arc is drawn + * @param[in] y the y coordinate of the upper-left corner of the square where the arc is drawn + * @param[in] diameter the diameter of the circle to draw + * @param[in] startAngle the beginning angle of the arc to draw + * @param[in] arcAngle the angular extent of the arc from startAngle + * @param[in] thickness the arc thickness. + * @param[in] fade the fade to apply. + * @param[in] start cap representation of start of shape + * @param[in] end cap representation of end of shape + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawThickFadedCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end); + +/* + * @brief Draws a thick ellipse with fade covering the specified rectangle. + * + * The center of the ellipse is defined as the center of the rectangle whose origin + * is at (x,y) (upper-left corner) and whose dimension is given by width and height. + * + * If either width or height is negative or zero, nothing is drawn. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the x coordinate of the upper-left corner of the rectangle where the ellipse is drawn + * @param[in] y the y coordinate of the upper-left corner of the rectangle where the ellipse is drawn + * @param[in] width the width of the ellipse to draw + * @param[in] height the height of the ellipse to draw + * @param[in] thickness the ellipse thickness. + * @param[in] fade the fade to apply. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawThickFadedEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade); + +/* + * @brief Draws a thick line between given points. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] startX the x coordinate of the start of the line + * @param[in] startY the y coordinate of the start of the line + * @param[in] endX the x coordinate of the end of the line + * @param[in] endY the y coordinate of the end of the line + * @param[in] thickness the line thickness. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawThickLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness); + +/* + * @brief Draws a thick circle covering the square specified by its diameter. + * + * If diameter is negative or zero, nothing is drawn. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the x coordinate of the upper-left corner of the square where the circle is drawn + * @param[in] y the y coordinate of the upper-left corner of the square where the circle is drawn + * @param[in] diameter the diameter of the circle to draw + * @param[in] thickness the circle thickness. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawThickCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness); + +/* + * @brief Draws a thick ellipse covering the specified rectangle. + * + * The center of the ellipse is defined as the center of the rectangle whose origin + * is at (x,y) (upper-left corner) and whose dimension is given by width and height. + * + * If either width or height is negative or zero, nothing is drawn. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the x coordinate of the upper-left corner of the square where the circle is drawn + * @param[in] y the y coordinate of the upper-left corner of the square where the circle is drawn + * @param[in] width the width of the ellipse to draw + * @param[in] height the height of the ellipse to draw + * @param[in] thickness the circle thickness. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawThickEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness); + +/* + * @brief Draws a thick arc covering the square specified by its diameter. + * + * The arc is drawn from startAngle up to arcAngle degrees. The center of the arc is + * defined as the center of the square whose origin is at (x,y) (upper-left corner) + * and whose dimension is given by diameter. + * + * Angles are interpreted such that 0 degrees is at the 3 o'clock position. A positive + * value indicates a counter-clockwise rotation while a negative value indicates a + * clockwise rotation. + * + * If diameter is negative, nothing is drawn. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] x the x coordinate of the upper-left corner of the square where the arc is drawn + * @param[in] y the y coordinate of the upper-left corner of the square where the arc is drawn + * @param[in] diameter the diameter of the circle to draw + * @param[in] startAngle the beginning angle of the arc to draw + * @param[in] arcAngle the angular extent of the arc from startAngle + * @param[in] thickness the arc thickness. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawThickCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness); + +/* + * @brief Draws an image applying a flip (0, 90, 180 or 270 degrees with or without + * mirror). + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] img the MicroUI Image to draw. + * @param[in] regionX the x coordinate of the upper-left corner of the region to draw. + * @param[in] regionY the y coordinate of the upper-left corner of the region to draw. + * @param[in] width the width of the region to copy. + * @param[in] height the height of the region to copy. + * @param[in] x the x coordinate of the top-left point in the destination. + * @param[in] y the y coordinate of the top-left point in the destination. + * @param[in] transformation the flip to apply. + * @param[in] alpha the opacity level to apply to the region. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawFlippedImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); + +/* + * @brief Draws an image applying a free rotation (0 to 360 degrees). + * + * The rotation is specified by the center and the angle. The reference point is + * the graphical object top-left corner. The rotation point is relative where the + * graphical object will be drawn. + * + * This method uses the nearest neighbor algorithm to render the content. This algorithm + * is faster than bilinear algorithm but its rendering is faster. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] img the MicroUI Image to draw. + * @param[in] x the x coordinate of the image reference anchor top-left point. + * @param[in] y the y coordinate of the image reference anchor top-left point. + * @param[in] rotationX the x coordinate of the rotation center. + * @param[in] rotationY the y coordinate of the rotation center. + * @param[in] angle the rotation angle. + * @param[in] alpha the opacity level to apply to the region. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawRotatedImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); + +/* + * @brief Draws an image applying a free rotation (0 to 360 degrees). + * + * The rotation is specified by the center and the angle. The reference point is + * the graphical object top-left corner. The rotation point is relative where the + * graphical object will be drawn. + * + * This method uses the bilinear algorithm to render the content. This algorithm + * performs better rendering than nearest neighbor algorithm but it is slower to + * apply. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] img the MicroUI Image to draw. + * @param[in] x the x coordinate of the image reference anchor top-left point. + * @param[in] y the y coordinate of the image reference anchor top-left point. + * @param[in] rotationX the x coordinate of the rotation center. + * @param[in] rotationY the y coordinate of the rotation center. + * @param[in] angle the rotation angle. + * @param[in] alpha the opacity level to apply to the region. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawRotatedImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); + +/* + * @brief Draws an image applying a scaling. + * + * This method uses the nearest neighbor algorithm to render the content. This algorithm + * is faster than bilinear algorithm but its rendering is faster. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] img the MicroUI Image to draw. + * @param[in] x the x coordinate of the image reference anchor top-left point. + * @param[in] y the y coordinate of the image reference anchor top-left point. + * @param[in] factorX scaling X factor. + * @param[in] factorY scaling Y factor. + * @param[in] alpha the opacity level to apply to the region. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawScaledImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +/* + * @brief Draws an image applying a scaling. + * + * This method uses the bilinear algorithm to render the content. This algorithm + * performs better rendering than nearest neighbor algorithm but it is slower to + * apply. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] img the MicroUI Image to draw. + * @param[in] x the x coordinate of the image reference anchor top-left point. + * @param[in] y the y coordinate of the image reference anchor top-left point. + * @param[in] factorX scaling X factor. + * @param[in] factorY scaling Y factor. + * @param[in] alpha the opacity level to apply to the region. + * + * @return the drawing status. + */ +DRAWING_Status UI_DRAWING_drawScaledImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif // UI_DRAWING_H diff --git a/bsp/projects/microej/ui/inc/ui_drawing_bvi.h b/bsp/projects/microej/ui/inc/ui_drawing_bvi.h new file mode 100644 index 0000000..9bae930 --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_drawing_bvi.h @@ -0,0 +1,254 @@ +/* + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#if !defined UI_DRAWING_BVI_H +#define UI_DRAWING_BVI_H +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @file + * @brief Implementation of a set of ui_drawing.h drawing functions (MicroUI and + * Drawing libraries). These are implementations over a BufferedVectorImage and + * the destination buffer format is the BufferedVectorImage format. When the drawing + * cannot be performed for any reason, the stub implementation is used instead. + * @author MicroEJ Developer Team + * @version 5.0.0 + */ + +#include "microvg_configuration.h" +#if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include + +#include "ui_drawing.h" + +// -------------------------------------------------------------------------------- +// Defines +// -------------------------------------------------------------------------------- + +/* + * @brief Redirects all ui_drawing.h functions to the BufferedVectorImage functions + */ + +#define UI_DRAWING_BVI_is_drawer CONCAT(UI_DRAWING_is_drawer_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_adjustNewImageCharacteristics CONCAT(UI_DRAWING_adjustNewImageCharacteristics_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_initializeNewImage CONCAT(UI_DRAWING_initializeNewImage_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_freeImageResources CONCAT(UI_DRAWING_freeImageResources_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) + +#define UI_DRAWING_BVI_drawLine CONCAT(UI_DRAWING_drawLine_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawHorizontalLine CONCAT(UI_DRAWING_drawHorizontalLine_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawVerticalLine CONCAT(UI_DRAWING_drawVerticalLine_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_fillRectangle CONCAT(UI_DRAWING_fillRectangle_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawRoundedRectangle CONCAT(UI_DRAWING_drawRoundedRectangle_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_fillRoundedRectangle CONCAT(UI_DRAWING_fillRoundedRectangle_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawCircleArc CONCAT(UI_DRAWING_drawCircleArc_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawEllipseArc CONCAT(UI_DRAWING_drawEllipseArc_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_fillCircleArc CONCAT(UI_DRAWING_fillCircleArc_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_fillEllipseArc CONCAT(UI_DRAWING_fillEllipseArc_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawEllipse CONCAT(UI_DRAWING_drawEllipse_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_fillEllipse CONCAT(UI_DRAWING_fillEllipse_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawCircle CONCAT(UI_DRAWING_drawCircle_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_fillCircle CONCAT(UI_DRAWING_fillCircle_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawThickFadedPoint CONCAT(UI_DRAWING_drawThickFadedPoint_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawThickFadedLine CONCAT(UI_DRAWING_drawThickFadedLine_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawThickFadedCircle CONCAT(UI_DRAWING_drawThickFadedCircle_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawThickFadedCircleArc CONCAT(UI_DRAWING_drawThickFadedCircleArc_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawThickFadedEllipse CONCAT(UI_DRAWING_drawThickFadedEllipse_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawThickLine CONCAT(UI_DRAWING_drawThickLine_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawThickCircle CONCAT(UI_DRAWING_drawThickCircle_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawThickEllipse CONCAT(UI_DRAWING_drawThickEllipse_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define UI_DRAWING_BVI_drawThickCircleArc CONCAT(UI_DRAWING_drawThickCircleArc_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) + +// -------------------------------------------------------------------------------- +// ui_drawing.h API +// (the function names differ according to the available number of destination formats) +// -------------------------------------------------------------------------------- + +/* + * @brief Implementation of adjustNewImageCharacteristics for a BufferedVectorImage. See ui_drawing.h + */ +void UI_DRAWING_BVI_adjustNewImageCharacteristics(jbyte image_format, uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment); + +/* + * @brief Implementation of initializeNewImage for a BufferedVectorImage. See ui_drawing.h + */ +void UI_DRAWING_BVI_initializeNewImage(MICROUI_Image* image); + +/* + * @brief Implementation of freeImageResources for a BufferedVectorImage. See ui_drawing.h + */ +void UI_DRAWING_BVI_freeImageResources(MICROUI_Image* image) ; + +/* + * @brief Implementation of drawLine over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY); + +/* + * @brief Implementation of drawHorizontalLine over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawHorizontalLine(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y); + +/* + * @brief Implementation of drawVerticalLine over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawVerticalLine(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2); + +/* + * @brief Implementation of fillRectangle over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_fillRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); + +/* + * @brief Implementation of drawRoundedRectangle over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); + +/* + * @brief Implementation of fillRoundedRectangle over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_fillRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); + +/* + * @brief Implementation of drawCircleArc over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Implementation of drawEllipseArc over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Implementation of fillCircleArc over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_fillCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Implementation of fillEllipseArc over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_fillEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Implementation of drawEllipse over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); + +/* + * @brief Implementation of fillEllipse over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_fillEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); + +/* + * @brief Implementation of drawCircle over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); + +/* + * @brief Implementation of fillCircle over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_fillCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); + +/* + * @brief Implementation of drawImage over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); + +/* + * @brief Implementation of copyImage over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_copyImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); + +/* + * @brief Implementation of drawRegion over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawRegion(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); + +/* + * @brief Implementation of drawThickFadedPoint over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawThickFadedPoint(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade); + +/* + * @brief Implementation of drawThickFadedLine over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawThickFadedLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap); + +/* + * @brief Implementation of drawThickFadedCircle over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawThickFadedCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade); + +/* + * @brief Implementation of drawThickFadedCircleArc over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawThickFadedCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end); + +/* + * @brief Implementation of drawThickFadedEllipse over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawThickFadedEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade); + +/* + * @brief Implementation of drawThickLine over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawThickLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness); + +/* + * @brief Implementation of drawThickCircle over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawThickCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness); + +/* + * @brief Implementation of drawThickEllipse over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawThickEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness); + +/* + * @brief Implementation of drawThickCircleArc over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawThickCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness); + +/* + * @brief Implementation of drawFlippedImage over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawFlippedImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); + +/* + * @brief Implementation of drawRotatedImageNearestNeighbor over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawRotatedImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); + +/* + * @brief Implementation of drawRotatedImageBilinear over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawRotatedImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); + +/* + * @brief Implementation of drawScaledImageNearestNeighbor over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawScaledImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +/* + * @brief Implementation of drawScaledImageBilinear over a BufferedVectorImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_BVI_drawScaledImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#endif // #if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +#ifdef __cplusplus +} +#endif +#endif // UI_DRAWING_BVI_H diff --git a/bsp/projects/microej/ui/inc/ui_drawing_stub.h b/bsp/projects/microej/ui/inc/ui_drawing_stub.h new file mode 100644 index 0000000..4033181 --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_drawing_stub.h @@ -0,0 +1,204 @@ +/* + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#ifndef UI_DRAWING_STUB_H +#define UI_DRAWING_STUB_H +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @file + * @brief Implementation of all drawing functions of ui_drawing.h (MicroUI and Drawing libraries). + * These are stubbed implementations, there is no error but the drawings are not performed. Useful to + * stub a drawing on a custom destination (custom GraphicsContext format not supported by the Graphics + * Engine). + * @author MicroEJ Developer Team + * @version 4.0.1 + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include "ui_drawing.h" + +// -------------------------------------------------------------------------------- +// Public API +// -------------------------------------------------------------------------------- + +/* + * @brief Stubbed implementation of writePixel. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_writePixel(MICROUI_GraphicsContext* gc, jint x, jint y); + +/* + * @brief Stubbed implementation of drawLine. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY); + +/* + * @brief Stubbed implementation of drawHorizontalLine. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawHorizontalLine(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y); + +/* + * @brief Stubbed implementation of drawVerticalLine. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawVerticalLine(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2); + +/* + * @brief Stubbed implementation of drawRectangle. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); + +/* + * @brief Stubbed implementation of fillRectangle. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_fillRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); + +/* + * @brief Stubbed implementation of drawRoundedRectangle. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); + +/* + * @brief Stubbed implementation of fillRoundedRectangle. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_fillRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); + +/* + * @brief Stubbed implementation of drawCircleArc. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Stubbed implementation of drawEllipseArc. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Stubbed implementation of fillCircleArc. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_fillCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Stubbed implementation of fillEllipseArc. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_fillEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Stubbed implementation of drawEllipse. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); + +/* + * @brief Stubbed implementation of fillEllipse. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_fillEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); + +/* + * @brief Stubbed implementation of drawCircle. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); + +/* + * @brief Stubbed implementation of fillCircle. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_fillCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); + +/* + * @brief Stubbed implementation of drawImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); + +/* + * @brief Stubbed implementation of copyImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_copyImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); + +/* + * @brief Stubbed implementation of drawRegion. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawRegion(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); + +/* + * @brief Stubbed implementation of drawThickFadedPoint. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawThickFadedPoint(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade); + +/* + * @brief Stubbed implementation of drawThickFadedLine. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawThickFadedLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap); + +/* + * @brief Stubbed implementation of drawThickFadedCircle. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawThickFadedCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade); + +/* + * @brief Stubbed implementation of drawThickFadedCircleArc. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawThickFadedCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end); + +/* + * @brief Stubbed implementation of drawThickFadedEllipse. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawThickFadedEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade); + +/* + * @brief Stubbed implementation of drawThickLine. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawThickLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness); + +/* + * @brief Stubbed implementation of drawThickCircle. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawThickCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness); + +/* + * @brief Stubbed implementation of drawThickEllipse. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawThickEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness); + +/* + * @brief Stubbed implementation of drawThickCircleArc. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawThickCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness); + +/* + * @brief Stubbed implementation of drawFlippedImage. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawFlippedImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); + +/* + * @brief Stubbed implementation of drawRotatedImageNearestNeighbor. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawRotatedImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); + +/* + * @brief Stubbed implementation of drawRotatedImageBilinear. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawRotatedImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); + +/* + * @brief Stubbed implementation of drawScaledImageNearestNeighbor. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawScaledImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +/* + * @brief Stubbed implementation of drawScaledImageBilinear. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_STUB_drawScaledImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif // UI_DRAWING_STUB_H diff --git a/bsp/projects/microej/ui/inc/ui_drawing_vglite.h b/bsp/projects/microej/ui/inc/ui_drawing_vglite.h new file mode 100644 index 0000000..4b12a4c --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_drawing_vglite.h @@ -0,0 +1,289 @@ +/* + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#if !defined UI_DRAWING_VGLITE_H +#define UI_DRAWING_VGLITE_H +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @file + * @brief Implementation of a set of ui_drawing.h drawing functions (MicroUI and Drawing libraries). + * These are implementations over VGLite and the destination buffer format is the format specified + * in the VEE port. When the drawing cannot be performed by the GPU, the software implementation + * is used instead. + * @author MicroEJ Developer Team + * @version 8.0.1 + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include "ui_drawing.h" + +#include "vg_lite.h" + +// -------------------------------------------------------------------------------- +// Defines +// -------------------------------------------------------------------------------- + +#if !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +/* + * The functions UI_DRAWING_VGLITE_xxx() are directly called by LLUI_PAINTER_impl.c + * and LLDW_PAINTER_impl.c. This file overrides each function independently to use the + * VGLite GPU. + */ + +#define UI_DRAWING_VGLITE_writePixel UI_DRAWING_writePixel +#define UI_DRAWING_VGLITE_drawLine UI_DRAWING_drawLine +#define UI_DRAWING_VGLITE_drawHorizontalLine UI_DRAWING_drawHorizontalLine +#define UI_DRAWING_VGLITE_drawVerticalLine UI_DRAWING_drawVerticalLine +#define UI_DRAWING_VGLITE_drawRectangle UI_DRAWING_drawRectangle +#define UI_DRAWING_VGLITE_fillRectangle UI_DRAWING_fillRectangle +#define UI_DRAWING_VGLITE_drawRoundedRectangle UI_DRAWING_drawRoundedRectangle +#define UI_DRAWING_VGLITE_fillRoundedRectangle UI_DRAWING_fillRoundedRectangle +#define UI_DRAWING_VGLITE_drawCircleArc UI_DRAWING_drawCircleArc +#define UI_DRAWING_VGLITE_drawEllipseArc UI_DRAWING_drawEllipseArc +#define UI_DRAWING_VGLITE_fillCircleArc UI_DRAWING_fillCircleArc +#define UI_DRAWING_VGLITE_fillEllipseArc UI_DRAWING_fillEllipseArc +#define UI_DRAWING_VGLITE_drawEllipse UI_DRAWING_drawEllipse +#define UI_DRAWING_VGLITE_fillEllipse UI_DRAWING_fillEllipse +#define UI_DRAWING_VGLITE_drawCircle UI_DRAWING_drawCircle +#define UI_DRAWING_VGLITE_fillCircle UI_DRAWING_fillCircle +#define UI_DRAWING_VGLITE_drawImage UI_DRAWING_drawImage +#define UI_DRAWING_VGLITE_copyImage UI_DRAWING_copyImage +#define UI_DRAWING_VGLITE_drawRegion UI_DRAWING_drawRegion + +#define UI_DRAWING_VGLITE_drawThickFadedPoint UI_DRAWING_drawThickFadedPoint +#define UI_DRAWING_VGLITE_drawThickFadedLine UI_DRAWING_drawThickFadedLine +#define UI_DRAWING_VGLITE_drawThickFadedCircle UI_DRAWING_drawThickFadedCircle +#define UI_DRAWING_VGLITE_drawThickFadedCircleArc UI_DRAWING_drawThickFadedCircleArc +#define UI_DRAWING_VGLITE_drawThickFadedEllipse UI_DRAWING_drawThickFadedEllipse +#define UI_DRAWING_VGLITE_drawThickLine UI_DRAWING_drawThickLine +#define UI_DRAWING_VGLITE_drawThickCircle UI_DRAWING_drawThickCircle +#define UI_DRAWING_VGLITE_drawThickEllipse UI_DRAWING_drawThickEllipse +#define UI_DRAWING_VGLITE_drawThickCircleArc UI_DRAWING_drawThickCircleArc +#define UI_DRAWING_VGLITE_drawFlippedImage UI_DRAWING_drawFlippedImage +#define UI_DRAWING_VGLITE_drawRotatedImageNearestNeighbor UI_DRAWING_drawRotatedImageNearestNeighbor +#define UI_DRAWING_VGLITE_drawRotatedImageBilinear UI_DRAWING_drawRotatedImageBilinear +#define UI_DRAWING_VGLITE_drawScaledImageNearestNeighbor UI_DRAWING_drawScaledImageNearestNeighbor +#define UI_DRAWING_VGLITE_drawScaledImageBilinear UI_DRAWING_drawScaledImageBilinear + +#else // !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +/* + * The functions UI_DRAWING_VGLITE_xxx() are indirectly called through some tables. + * The functions have got the identifier "0" as suffix. This file overrides each function + * independently to use the VGLite GPU. + */ + +#define UI_DRAWING_VGLITE_writePixel UI_DRAWING_writePixel_0 +#define UI_DRAWING_VGLITE_drawLine UI_DRAWING_drawLine_0 +#define UI_DRAWING_VGLITE_drawHorizontalLine UI_DRAWING_drawHorizontalLine_0 +#define UI_DRAWING_VGLITE_drawVerticalLine UI_DRAWING_drawVerticalLine_0 +#define UI_DRAWING_VGLITE_drawRectangle UI_DRAWING_drawRectangle_0 +#define UI_DRAWING_VGLITE_fillRectangle UI_DRAWING_fillRectangle_0 +#define UI_DRAWING_VGLITE_drawRoundedRectangle UI_DRAWING_drawRoundedRectangle_0 +#define UI_DRAWING_VGLITE_fillRoundedRectangle UI_DRAWING_fillRoundedRectangle_0 +#define UI_DRAWING_VGLITE_drawCircleArc UI_DRAWING_drawCircleArc_0 +#define UI_DRAWING_VGLITE_drawEllipseArc UI_DRAWING_drawEllipseArc_0 +#define UI_DRAWING_VGLITE_fillCircleArc UI_DRAWING_fillCircleArc_0 +#define UI_DRAWING_VGLITE_fillEllipseArc UI_DRAWING_fillEllipseArc_0 +#define UI_DRAWING_VGLITE_drawEllipse UI_DRAWING_drawEllipse_0 +#define UI_DRAWING_VGLITE_fillEllipse UI_DRAWING_fillEllipse_0 +#define UI_DRAWING_VGLITE_drawCircle UI_DRAWING_drawCircle_0 +#define UI_DRAWING_VGLITE_fillCircle UI_DRAWING_fillCircle_0 +#define UI_DRAWING_VGLITE_drawImage UI_DRAWING_drawImage_0 +#define UI_DRAWING_VGLITE_copyImage UI_DRAWING_copyImage_0 +#define UI_DRAWING_VGLITE_drawRegion UI_DRAWING_drawRegion_0 + +#define UI_DRAWING_VGLITE_drawThickFadedPoint UI_DRAWING_drawThickFadedPoint_0 +#define UI_DRAWING_VGLITE_drawThickFadedLine UI_DRAWING_drawThickFadedLine_0 +#define UI_DRAWING_VGLITE_drawThickFadedCircle UI_DRAWING_drawThickFadedCircle_0 +#define UI_DRAWING_VGLITE_drawThickFadedCircleArc UI_DRAWING_drawThickFadedCircleArc_0 +#define UI_DRAWING_VGLITE_drawThickFadedEllipse UI_DRAWING_drawThickFadedEllipse_0 +#define UI_DRAWING_VGLITE_drawThickLine UI_DRAWING_drawThickLine_0 +#define UI_DRAWING_VGLITE_drawThickCircle UI_DRAWING_drawThickCircle_0 +#define UI_DRAWING_VGLITE_drawThickEllipse UI_DRAWING_drawThickEllipse_0 +#define UI_DRAWING_VGLITE_drawThickCircleArc UI_DRAWING_drawThickCircleArc_0 +#define UI_DRAWING_VGLITE_drawFlippedImage UI_DRAWING_drawFlippedImage_0 +#define UI_DRAWING_VGLITE_drawRotatedImageNearestNeighbor UI_DRAWING_drawRotatedImageNearestNeighbor_0 +#define UI_DRAWING_VGLITE_drawRotatedImageBilinear UI_DRAWING_drawRotatedImageBilinear_0 +#define UI_DRAWING_VGLITE_drawScaledImageNearestNeighbor UI_DRAWING_drawScaledImageNearestNeighbor_0 +#define UI_DRAWING_VGLITE_drawScaledImageBilinear UI_DRAWING_drawScaledImageBilinear_0 + +#endif // !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +// -------------------------------------------------------------------------------- +// ui_drawing.h API +// (the function names differ according to the available number of destination formats) +// -------------------------------------------------------------------------------- + +/* + * @brief Implementation of drawLine over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY); + +/* + * @brief Implementation of drawHorizontalLine over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawHorizontalLine(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y); + +/* + * @brief Implementation of drawVerticalLine over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawVerticalLine(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2); + +/* + * @brief Implementation of fillRectangle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_fillRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); + +/* + * @brief Implementation of drawRoundedRectangle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); + +/* + * @brief Implementation of fillRoundedRectangle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_fillRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); + +/* + * @brief Implementation of drawCircleArc over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Implementation of drawEllipseArc over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Implementation of fillCircleArc over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_fillCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Implementation of fillEllipseArc over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_fillEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Implementation of drawEllipse over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); + +/* + * @brief Implementation of fillEllipse over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_fillEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); + +/* + * @brief Implementation of drawCircle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); + +/* + * @brief Implementation of fillCircle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_fillCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); + +/* + * @brief Implementation of drawImage over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); + +/* + * @brief Implementation of copyImage over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_copyImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); + +/* + * @brief Implementation of drawRegion over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawRegion(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); + +/* + * @brief Implementation of drawThickFadedPoint over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawThickFadedPoint(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade); + +/* + * @brief Implementation of drawThickFadedLine over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawThickFadedLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap); + +/* + * @brief Implementation of drawThickFadedCircle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawThickFadedCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade); + +/* + * @brief Implementation of drawThickFadedCircleArc over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawThickFadedCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end); + +/* + * @brief Implementation of drawThickFadedEllipse over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawThickFadedEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade); + +/* + * @brief Implementation of drawThickLine over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawThickLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness); + +/* + * @brief Implementation of drawThickCircle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawThickCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness); + +/* + * @brief Implementation of drawThickEllipse over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawThickEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness); + +/* + * @brief Implementation of drawThickCircleArc over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawThickCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness); + +/* + * @brief Implementation of drawFlippedImage over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawFlippedImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); + +/* + * @brief Implementation of drawRotatedImageNearestNeighbor over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawRotatedImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); + +/* + * @brief Implementation of drawRotatedImageBilinear over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawRotatedImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); + +/* + * @brief Implementation of drawScaledImageNearestNeighbor over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawScaledImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +/* + * @brief Implementation of drawScaledImageBilinear over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_drawScaledImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif // UI_DRAWING_VGLITE_H diff --git a/bsp/projects/microej/ui/inc/ui_drawing_vglite_path.h b/bsp/projects/microej/ui/inc/ui_drawing_vglite_path.h new file mode 100644 index 0000000..c65ac20 --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_drawing_vglite_path.h @@ -0,0 +1,474 @@ +/* + * C + * + * Copyright 2019-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief MicroEJ MicroUI library low level API: implementation over VGLite. Provides + * a set of defines and functions to compute some shapes in VGLite paths. + * @author MicroEJ Developer Team + * @version 8.0.1 + */ + +#if !defined UI_DRAWING_VGLITE_PATH_H +#define UI_DRAWING_VGLITE_PATH_H + +#if defined __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include +#include + +#include "mej_math.h" + +#include "vg_lite.h" + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +/* + * @brief Length of a VGLite line path + */ +#define MEJ_VGLITE_PATH_LINE_LENGTH(t) \ + (0 \ + + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ + + 6 * MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) /* line have 6 sides */ \ + + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ + ) + +/* + * @brief Length of a VGLite thick shape line path + */ +#define MEJ_VGLITE_PATH_THICK_SHAPE_LINE_LENGTH(t) \ + (0 \ + + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ + + 2 * MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) /* line have 6 sides */ \ + + 2 * MEJ_MAX( MEJ_VGLITE_PATH_ROUNDED_CAP_LENGTH(t), \ + MEJ_VGLITE_PATH_NO_CAP_LENGTH(t)) /* CAPS */ \ + + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ + ) + +/* + * @brief Length of a VGLite ellipse path + */ +#define MEJ_VGLITE_PATH_CIRCLE_LENGTH(t) \ + (0 \ + + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ + + 4 * MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(t) /* 4 sections per ellipse */ \ + + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ + ) + +/* + * @brief Length of a VGLite ellipse path + */ +#define MEJ_VGLITE_PATH_CIRCLE_ARC_OUTLINE_MAX_LENGTH(t) \ + (0 \ + + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ + + 2 * MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) /* 2 ends */ \ + + 8 * MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(t) /* 4 sections per ellipse */ \ + + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ + ) + +/* + * @brief Length of a VGLite filled rectangle path + */ +#define MEJ_VGLITE_PATH_RECT_LENGTH(t) \ + (0 \ + + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ + + 4 * MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) /* 4 sides */ \ + + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ + ) + +/* + * @brief Length of a VGLite filled rounded rectangle path + */ +#define MEJ_VGLITE_PATH_ROUND_RECT_LENGTH(t) \ + (0 \ + + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ + + 4 * MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) /* 4 sides */ \ + + 4 * MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(t) /* 4 corners */ \ + + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ + ) + +/* + * @brief Maximum length of a VGLite filled ellipse arc path + */ +#define MEJ_VGLITE_PATH_CIRCLE_ARC_MAX_LENGTH(t) \ + (0 \ + + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ + + 2 * MEJ_MAX( MEJ_VGLITE_PATH_ROUNDED_CAP_LENGTH(t), \ + MEJ_VGLITE_PATH_NO_CAP_LENGTH(t)) /* CAPS */ \ + + 8 * MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(t) /* Up to 4 sections per curve in and out */ \ + + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ + ) + +/* + * @brief Size of a rounded cap: 2 cubic curves + */ +#define MEJ_VGLITE_PATH_ROUNDED_CAP_LENGTH(t) (2 * MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(t)) + +/* + * @brief Size of a "no cap": 1 line + */ +#define MEJ_VGLITE_PATH_NO_CAP_LENGTH(t) MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) + +/* + * @brief Size of a move_to command + */ +#define MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) (sizeof(path_move_to_ ## t)) + +/* + * @brief Size of a line_to command + */ +#define MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) (sizeof(path_line_to_ ## t)) + +/* + * @brief Size of a cubic_to command + */ +#define MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(t) (sizeof(path_cubic_to_ ## t)) + +/* + * @brief Size of a end command + */ +#define MEJ_VGLITE_PATH_END_LENGTH(t) (sizeof(path_end_ ## t)) + +/* + * @brief Position of the starting cap in the caps bitfield + */ +#define MEJ_VGLITE_PATH_CAPS_START_SHIFT 0 + +/* + * @brief Position of the ending cap in the caps bitfield + */ +#define MEJ_VGLITE_PATH_CAPS_END_SHIFT 2 + +/* + * @brief Mask of a cap in the caps bitfield + */ +#define MEJ_VGLITE_PATH_CAPS_MASK 0x03 + +/* + * @brief Sets the starting cap in the bitfield + */ +#define MEJ_VGLITE_PATH_SET_CAPS_START(x) (((x) & MEJ_VGLITE_PATH_CAPS_MASK) << MEJ_VGLITE_PATH_CAPS_START_SHIFT) + +/* + * @brief Sets the ending cap in the bitfield + */ +#define MEJ_VGLITE_PATH_SET_CAPS_END(x) (((x) & MEJ_VGLITE_PATH_CAPS_MASK) << MEJ_VGLITE_PATH_CAPS_END_SHIFT) + +/* + * @brief Gets the starting cap from the bitfield + */ +#define MEJ_VGLITE_PATH_GET_CAPS_START(x) (((x) >> MEJ_VGLITE_PATH_CAPS_START_SHIFT) & MEJ_VGLITE_PATH_CAPS_MASK) + +/* + * @brief Gets the ending cap from the bitfield + */ +#define MEJ_VGLITE_PATH_GET_CAPS_END(x) (((x) >> MEJ_VGLITE_PATH_CAPS_END_SHIFT) & MEJ_VGLITE_PATH_CAPS_MASK) + +/* + * @brief Scale factor to improve drawing quality in vector mode + */ +#define DRAWING_SCALE_FACTOR (2.f) +#define DRAWING_SCALE_DIV (1.0 / (vg_lite_float_t)DRAWING_SCALE_FACTOR) + +// ----------------------------------------------------------------------------- +// Types +// ----------------------------------------------------------------------------- + +/* + * @brief VGLite S16 move to command + */ +typedef struct path_move_to_s16 { + int16_t cmd; // @brief Command + int16_t x; // @brief Horizontal coordinate of the position to move to + int16_t y; // @brief Vertical coordinate of the position to move to +} path_move_to_s16_t; + +/* + * @brief VGLite S16 line to command + */ +typedef struct path_line_s16 { + int16_t cmd; // @brief Command + int16_t x; // @brief Horizontal coordinate of the position to move to + int16_t y; // @brief Vertical coordinate of the position to move to +} path_line_to_s16_t; + +/* + * @brief VGLite S16 cubic to command + */ +typedef struct path_cubic_s16 { + int16_t cmd; // @brief command + int16_t cx1; // @brief Horizontal coordinate of the first control point + int16_t cy1; // @brief Vertical coordinate of the first control point + int16_t cx2; // @brief Horizontal coordinate of the second control point + int16_t cy2; // @brief Vertical coordinate of the second control point + int16_t x; // @brief Horizontal coordinate of the end of the curve + int16_t y; // @brief Vertical coordinate of the end of the curve +} path_cubic_to_s16_t; + +/* + * @brief VGLite S16 end command + */ +typedef struct path_end_s16 { + int16_t cmd; // @brief command +} path_end_s16_t; + +/* + * @brief Fixed array size to store a line path + */ +typedef uint8_t vglite_path_line_t[MEJ_VGLITE_PATH_LINE_LENGTH(s16_t)]; + +/* + * @brief Fixed array size to store a thick shape line path + */ +typedef uint8_t vglite_path_thick_shape_line_t[MEJ_VGLITE_PATH_THICK_SHAPE_LINE_LENGTH(s16_t)]; + +/* + * @brief Fixed array size to store a ellipse + */ +typedef uint8_t vglite_path_ellipse_t[MEJ_VGLITE_PATH_CIRCLE_LENGTH(s16_t)]; + +/* + * @brief Fixed array size to store a ellipse arc + */ +typedef uint8_t vglite_path_ellipse_arc_t[MEJ_VGLITE_PATH_CIRCLE_ARC_OUTLINE_MAX_LENGTH(s16_t)]; + +/* + * @brief Fixed array size to store a rectangle path + */ +typedef uint8_t vglite_path_rectangle_t[MEJ_VGLITE_PATH_RECT_LENGTH(s16_t)]; + +/* + * @brief Fixed array size to store a line path + */ +typedef uint8_t vglite_path_rounded_rectangle_t[MEJ_VGLITE_PATH_ROUND_RECT_LENGTH(s16_t)]; + +/* + * @brief Fixed array size to store a thick ellipse arc path + */ +typedef uint8_t vglite_path_thick_ellipse_arc_t[MEJ_VGLITE_PATH_CIRCLE_ARC_MAX_LENGTH(s16_t)]; + +// ----------------------------------------------------------------------------- +// API +// ----------------------------------------------------------------------------- + +/* + * @brief Computes a ellipse arc + * + * This function uses bezier curves to apporoximate the ellipse arcs + * The path computed by this function is intended to be used with VGLite + * The function supports the followin caps: DRAWING_ENDOFLINE_NONE and DRAWING_ENDOFLINE_ROUNDED. + * DRAWING_ENDOFLINE_PERPENDICULAR is considered as DRAWING_ENDOFLINE_NONE. + * @param[out] thick_shape_ellipse_arc: the vg_lite path to compute + * @param[in]: radius_out_w: the horizontal inner radius of the ellipse arc + * @param[in]: radius_out_h: the vertical inner radius of the ellipse arc + * @param[in]: radius_in_w: the horizontal outer radius of the ellipse arc + * @param[in]: radius_in_h: the vertical outer radius of the ellipse arc + * @param[in]: start_angle_degree: the start angle of the ellipse arc in degrees + * @param[in]: arc_angle_degree: the arc angle of the ellipse arc in degrees + * @param[in] fill: the flag indicating if the ellipse arc will be filled + * - true: the ellipse arc will be filled + * - false: the ellipse arc will not be filled + * + * @return: + * -1: an error occured, + * otherwise: number of bytes written in the path + */ +int UI_DRAWING_VGLITE_PATH_compute_ellipse_arc( + vg_lite_path_t *thick_ellipse_arc_shape, + int radius_out_w, + int radius_out_h, + int radius_in_w, + int radius_in_h, + float32_t start_angle_degree, + float32_t arc_angle_degree, + bool fill); + +/* + * @brief Computes a thick ellipse arc shape + * + * This function uses bezier curves to apporoximate the ellipse arcs + * The path computed by this function is intended to be used with VGLite + * The function supports the followin caps: DRAWING_ENDOFLINE_NONE and DRAWING_ENDOFLINE_ROUNDED. + * DRAWING_ENDOFLINE_PERPENDICULAR is considered as DRAWING_ENDOFLINE_NONE. + * @param[out] thick_shape_ellipse_arc: vg_lite path to compute + * @param[in]: diameter_w: diameter of the ellipse arc + * @param[in]: diameter_h: diameter of the ellipse arc + * @param[in]: thickness: thickness of the ellipse arc + * @param[in]: start_angle_degree: starting angle of the ellipse arc in degrees + * @param[in]: arc_angle_degree: angle of the ellipse arc in degrees + * @param[in]: caps of the start and end of the ellipse arc, bits [0:1] contains the starting cap, bits [2:3] contains the ending cap. + * + * @return: + * -1: an error occured, + * otherwise: number of bytes written in the path + */ +int UI_DRAWING_VGLITE_PATH_compute_thick_shape_ellipse_arc( + vg_lite_path_t *thick_ellipse_arc_shape, + int diameter_w, + int diameter_h, + int thickness, + float32_t start_angle_degree, + float32_t arc_angle_degree, + int caps); + +/* + * @brief Computes a ellipse + * + * This function uses bezier curves to apporoximate the ellipse + * The path computed by this function is intended to be used with VGLite + * @param[out] point_shape: vg_lite path to compute + * @param[in] thickness: thickness (diameter) of the point + * @param[in,out] matrix: transformation matrix (updated to scale the point) + * + * @return: + * -1: an error occured, + * otherwise: number of bytes written in the path + */ +int UI_DRAWING_VGLITE_PATH_compute_ellipse( + vg_lite_path_t *point_shape, + int path_offset, + int radius_w, + int radius_h, + bool end_path); + +/* + * @brief Computes a plain ellipse + * + * This function uses a hard coded path of a thircle of diameter 200. + * The matrix is updated to scale the ellipse to match the diameter. + * + * This function uses bezier curves to apporoximate the ellipse + * The path computed by this function is intended to be used with VGLite + * @param[out] point_shape: vg_lite path to compute + * @param[in] radius_w: the horizontal radius of the ellipse. + * @param[in] radius_h: the vertical radius of the ellipse. + * @param[in,out] matrix: transformation matrix (updated to scale the point) + * + * @return: + * -1: an error occured, + * otherwise: number of bytes written in the path + */ +int UI_DRAWING_VGLITE_PATH_compute_filled_ellipse( + vg_lite_path_t *point_shape, + int radius_w, + int radius_h, + vg_lite_matrix_t *matrix); + +/* + * @brief Computes a rectangle + * + * The path computed by this function is intended to be used with VGLite + * @param[out] rectangle_shape: vg_lite path to compute + * @param[in] path_offset: offset in the path buffer + * @param[in] x: horizontal coordinate of the left side of the shape + * @param[in] y: vertical coordinate of the top side of the shape + * @param[in] width: width of the rectangle + * @param[in] height: height of the rectangle + * @param[in] end_path: true to end the path, false to leave path open + * + * @return: + * -1: an error occured, + * otherwise: number of bytes written in the path + */ +int UI_DRAWING_VGLITE_PATH_compute_rectangle( + vg_lite_path_t *rounded_rectangle_shape, + int path_offset, + int x, + int y, + int width, + int height, + bool end_path); + +/* + * @brief Computes a rounded rectangle + * + * This function uses bezier curves to apporoximate the corners + * The path computed by this function is intended to be used with VGLite + * @param[out] rounded_rectangle_shape: vg_lite path to compute + * @param[in] path_offset: offset in the path buffer + * @param[in] x: horizontal coordinate of the left side of the shape + * @param[in] y: vertical coordinate of the top side of the shape + * @param[in] height: height of the rounded rectangle + * @param[in] width: width of the rounded rectangle + * @param[in] height: height of the rounded rectangle + * @param[in] arc_width: horizontal diameter of the rounded corner arc + * @param[in] arc_height: vertical diameter of the rounded corner arc + * @param[in] end_path: true to end the path, false to leave path open + * + * @return: + * -1: an error occured, + * otherwise: number of bytes written in the path + */ +int UI_DRAWING_VGLITE_PATH_compute_rounded_rectangle( + vg_lite_path_t *rounded_rectangle_shape, + int path_offset, + int x, + int y, + int width, + int height, + int arc_width, + int arc_height, + bool end_path); + +/* + * @brief Computes a line + * + * The path computed by this function is intended to be used with VGLite + * The line will be computed from origin (0,0) to (x,y) + * @param[out] line_shape: vg_lite path to compute + * @param[in]: x: horizontal coordinate of the end point of the line + * @param[in]: y: vertical coordinate of the end point of the line + * + * @return: + * -1: an error occured, + * otherwise: number of bytes written in the path + */ +int UI_DRAWING_VGLITE_PATH_compute_line(vg_lite_path_t *line_shape, int x, int y); + +/* + * @brief Computes a thick shape line + * + * The path computed by this function is intended to be used with VGLite + * This function will compute an horizontal line and update a matrix to rotate it + * The line will be computed from origin (0,0) to sqrt(x^2,y^2) + * The matrix will be updated to rotate it by atan2(y, x) + * @param[out] line_shape: vg_lite path to compute + * @param[in]: x: horizontal coordinate of the end point of the line + * @param[in]: y: vertical coordinate of the end point of the line + * @param[in]: thickness: thickness (diameter) of the point + * @param[in]: caps: caps of the start and end of the ellipse arc, bits [0:1] contains the starting cap, bits [2:3] contains the ending cap. + * @param[out]: matrix: matrix to be updated with rotation atan2(y, x) + * + * @return: + * -1: an error occured, + * otherwise: number of bytes written in the path + */ +int UI_DRAWING_VGLITE_PATH_compute_thick_shape_line( + vg_lite_path_t *thick_line_shape, + int x, + int y, + int thickness, + int caps, + vg_lite_matrix_t *matrix); + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // !defined UI_DRAWING_VGLITE_PATH_H diff --git a/bsp/projects/microej/ui/inc/ui_drawing_vglite_process.h b/bsp/projects/microej/ui/inc/ui_drawing_vglite_process.h new file mode 100644 index 0000000..dd59902 --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_drawing_vglite_process.h @@ -0,0 +1,247 @@ +/* + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#if !defined UI_DRAWING_VGLITE_PROCESS_H +#define UI_DRAWING_VGLITE_PROCESS_H +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @file + * @brief MicroEJ MicroUI library low level API: implementation over VGLite. Provides + * a set of drawing functions over the VGLite library. First the MicroUI parameters + * are converted to VGLite objects and then a drawing function is called to render the + * drawing. + * @author MicroEJ Developer Team + * @version 8.0.1 + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include "ui_drawing.h" +#include "ui_vglite.h" + +#include "vg_lite.h" + +// -------------------------------------------------------------------------------- +// Defines +// -------------------------------------------------------------------------------- + +/* + * @brief A fade higher than 1 is not compatible with VGLite + */ +#define UI_DRAWING_VGLITE_IS_COMPATIBLE_FADE(f) ((f) <= 1) + +/* + * @brief Gets the thickness according to a thickness (t) and a fade (f). + */ +#define UI_DRAWING_VGLITE_GET_THICKNESS(t, f) ((t) + (f)) + +// -------------------------------------------------------------------------------- +// Typedef +// -------------------------------------------------------------------------------- + +/* + * @brief Function to draw a path. + * + * @see vg_lite_draw() + */ +typedef DRAWING_Status (* UI_DRAWING_VGLITE_PROCESS_draw_path_t) ( + MICROUI_GraphicsContext* gc, + vg_lite_path_t * path, + vg_lite_fill_t fill_rule, + vg_lite_matrix_t * matrix, + vg_lite_blend_t blend, + vg_lite_color_t color); + +/* + * @brief Function to blit a part of the source. + * + * @see vg_lite_blit_rect() + */ +typedef DRAWING_Status (* UI_DRAWING_VGLITE_PROCESS_blit_rect_t)( + MICROUI_GraphicsContext* gc, + vg_lite_buffer_t *source, + uint32_t *rect, + vg_lite_matrix_t *matrix, + vg_lite_blend_t blend, + vg_lite_color_t color, + vg_lite_filter_t filter); + +/* + * @brief Function to clear the source. + * + * @see vg_lite_clear() + */ +typedef DRAWING_Status (* UI_DRAWING_VGLITE_PROCESS_clear_t)( + MICROUI_GraphicsContext* gc, + vg_lite_rectangle_t * rect, + vg_lite_color_t color); + +// -------------------------------------------------------------------------------- +// Public API +// -------------------------------------------------------------------------------- + +/* + * @brief Tells if the source is GPU compatible. If yes, configures the given matrix, + * blit rectangle and color and returns a VGLite source buffer to draw a raster image. + * Returns NULL if the image cannot be drawn (image format not supported by the GPU) + * or if the image region to draw is fully outside the clip. + * + * @return a VGLite source buffer if the GPU can be used to draw the image. + */ +vg_lite_buffer_t* UI_DRAWING_VGLITE_PROCESS_prepare_draw_image(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x_src, jint y_src, jint width, jint height, jint x_dest, jint y_dest, jint alpha, vg_lite_color_t* color, vg_lite_matrix_t* matrix, uint32_t* blit_rect); + +/* + * @brief Implementation of drawLine over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawLine(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY); + +/* + * @brief Implementation of drawHorizontalLine over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawHorizontalLine(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y); + +/* + * @brief Implementation of drawVerticalLine over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawVerticalLine(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2); + +/* + * @brief Implementation of fillRectangle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_fillRectangle(UI_DRAWING_VGLITE_PROCESS_clear_t drawer, MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); + +/* + * @brief Implementation of drawRoundedRectangle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawRoundedRectangle(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); + +/* + * @brief Implementation of fillRoundedRectangle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_fillRoundedRectangle(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); + +/* + * @brief Implementation of drawCircleArc over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawCircleArc(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Implementation of drawEllipseArc over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawEllipseArc(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Implementation of fillCircleArc over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_fillCircleArc(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Implementation of fillEllipseArc over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_fillEllipseArc(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); + +/* + * @brief Implementation of drawEllipse over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawEllipse(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); + +/* + * @brief Implementation of fillEllipse over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_fillEllipse(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); + +/* + * @brief Implementation of drawCircle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawCircle(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); + +/* + * @brief Implementation of fillCircle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_fillCircle(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); + +/* + * @brief Implementation of drawThickFadedPoint over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickFadedPoint(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness); + +/* + * @brief Implementation of drawThickFadedLine over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickFadedLine(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, DRAWING_Cap startCap, DRAWING_Cap endCap); + +/* + * @brief Implementation of drawThickFadedCircle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickFadedCircle(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness); + +/* + * @brief Implementation of drawThickFadedCircleArc over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickFadedCircleArc(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, DRAWING_Cap start, DRAWING_Cap end); + +/* + * @brief Implementation of drawThickFadedEllipse over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickFadedEllipse(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness); + +/* + * @brief Implementation of drawThickLine over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickLine(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness); + +/* + * @brief Implementation of drawThickCircle over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickCircle(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness); + +/* + * @brief Implementation of drawThickEllipse over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickEllipse(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness); + +/* + * @brief Implementation of drawThickCircleArc over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickCircleArc(UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness); + +/* + * @brief Implementation of drawFlippedImage over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawFlippedImage(UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha, bool* is_gpu_compatible); + +/* + * @brief Implementation of drawRotatedImageNearestNeighbor over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawRotatedImageNearestNeighbor(UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha, bool* is_gpu_compatible); + +/* + * @brief Implementation of drawRotatedImageBilinear over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawRotatedImageBilinear(UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha, bool* is_gpu_compatible); + +/* + * @brief Implementation of drawScaledImageNearestNeighbor over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawScaledImageNearestNeighbor(UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha, bool* is_gpu_compatible); + +/* + * @brief Implementation of drawScaledImageBilinear over VGLite. See ui_drawing.h + */ +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawScaledImageBilinear(UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha, bool* is_gpu_compatible); + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif // UI_DRAWING_VGLITE_PROCESS_H diff --git a/bsp/projects/microej/ui/inc/ui_image_drawing.h b/bsp/projects/microej/ui/inc/ui_image_drawing.h new file mode 100644 index 0000000..bd4ef28 --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_image_drawing.h @@ -0,0 +1,113 @@ +/* + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#if !defined UI_IMAGE_DRAWING_H +#define UI_IMAGE_DRAWING_H +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @brief Provides image drawing functions called by ui_drawing.c. + * + * The default weak functions of ui_drawing.c call the ui_image_drawing.h functions to draw + * the image. According to the kind of image (standard or custom), the implementation + * of ui_image_drawing.h calls the right image manager functions. + * + * When the image is a standard image, the implementation calls the Graphics Engine + * software algorithms. + * + * When the image is a custom image, the associated image manager is mandatory (the + * Graphics Engine is not able to decode this custom image). The implementation + * dispatches the image drawing to this image manager (the custom image manager is + * retrieved thanks to the custom image format: MICROUI_IMAGE_FORMAT_CUSTOM_0 to + * MICROUI_IMAGE_FORMAT_CUSTOM_7). + * + * Several cases: + * + * 1- The image manager is available and it is able to draw in the given Graphics + * Context: it has to decode the image and draw into the Graphics Context. + * + * 2- The image manager is available and the given Graphics Context format is the + * same format as the image: the image should be copied in the destination. + * + * 3- The image manager is available and it is not able to draw in the given Graphics + * Context (unknown ouput format) but it is able to draw the image into the Graphics + * Context by using the ui_drawing.h functions. + * + * 4- The image manager is available, it is not able to draw in the given Graphics + * Context (unknown ouput format) and it is not able to call standard ui_drawing.h + * functions to draw the image: it has to call the stub implementation. + * + * @author MicroEJ Developer Team + * @version 4.0.1 + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include "ui_drawing.h" + +// -------------------------------------------------------------------------------- +// API +// -------------------------------------------------------------------------------- + +/* + * @brief Draws a region of an image. + * @see UI_DRAWING_drawImage + */ +DRAWING_Status UI_IMAGE_DRAWING_draw(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); + +/* + * @brief Copy a region of an image in another image with the same pixel format. + * @see UI_DRAWING_copyImage + */ +DRAWING_Status UI_IMAGE_DRAWING_copy(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); + +/* + * @brief Draw a region of an image in the same image. + * @see UI_DRAWING_drawRegion + */ +DRAWING_Status UI_IMAGE_DRAWING_drawRegion(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); + +/* + * @brief Draws an image applying a flip. + * @see UI_DRAWING_drawFlippedImage + */ +DRAWING_Status UI_IMAGE_DRAWING_drawFlipped(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); + +/* + * @brief Draws an image applying a free rotation (0 to 360 degrees). + * @see UI_DRAWING_drawRotatedImageNearestNeighbor + */ +DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); + +/* + * @brief Draws an image applying a free rotation (0 to 360 degrees). + * @see UI_DRAWING_drawRotatedImageBilinear + */ +DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); + +/* + * @brief Draws an image applying a scaling. + * @see UI_DRAWING_drawScaledImageNearestNeighbor + */ +DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +/* + * @brief Draws an image applying a scaling. + * @see UI_DRAWING_drawScaledImageBilinear + */ +DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif // UI_IMAGE_DRAWING_H diff --git a/bsp/projects/microej/ui/inc/ui_log.h b/bsp/projects/microej/ui/inc/ui_log.h new file mode 100644 index 0000000..060265b --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_log.h @@ -0,0 +1,113 @@ +/* + * Copyright 2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#if !defined UI_LOG_H +#define UI_LOG_H +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @brief Provides elements that allow to log some external events in the MicroUI event + * group. + * + * The MicroUI event group is identified by the global LLUI_EVENT_group. The events are + * 0-based and have to start at the offset LLUI_EVENT_offset. + * + * Notes: + * - The number of events is 100 (fixed by MicroUI). + * - The event 0 is reserved to log the drawings. It is used by the MicroUI CCO and by + * the MicroUI Graphics Engine (to log the internal drawings). + * - The events [10,20] are reserved to log the buffer refresh strategies (BRS) events. + * + * Example: + * + * #include "ui_log.h" + * LLTRACE_record_event_u32(LLUI_EVENT_group, LLUI_EVENT_offset + MY_EVENT_OFFSET, my_event_data); + * + * @author MicroEJ Developer Team + * @version 4.0.1 + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + + +/* + * @brief Includes right header file according the Architecture. + * - Architecture 7: include "trace.h" + * - Architecture 8: include "LLTRACE.h" + */ +#define UI_LOG_LLTRACE __has_include("LLTRACE.h") +#if UI_LOG_LLTRACE == (0u) +#include +#else +#include +#endif + +// -------------------------------------------------------------------------------- +// Defines +// -------------------------------------------------------------------------------- + +/* + * @brief Identifies the log for the drawings (known by the MicroUI CCO and by the + * MicroUI Graphics Engine). + */ +#define UI_LOG_DRAW (0) + +/* + * @brief Identifies the logs for the Buffer Refresh Strategies (BRS). + */ +#define UI_LOG_BRS_NewDrawing (10) // New drawing region (%u,%u) to (%u,%u) +#define UI_LOG_BRS_FlushSingle (11) // Flush LCD (id=%u buffer=%p) single region (%u,%u) to (%u,%u) +#define UI_LOG_BRS_FlushMulti (12) // Flush LCD (id=%u buffer=%p) %u regions +#define UI_LOG_BRS_AddRegion (13) // Add region (%u,%u) to (%u,%u) +#define UI_LOG_BRS_RemoveRegion (14) // Remove region (%u,%u) to (%u,%u) +#define UI_LOG_BRS_RestoreRegion (15) // Restore region (%u,%u) to (%u,%u) +#define UI_LOG_BRS_ClearList (16) // Clear the list of regions + +/* + * @brief Compatibility of Architecture 7 with Architecture 8: use the prototypes + * of LLTRACE.h (Architecture 8). + */ +#if UI_LOG_LLTRACE == (0u) +#define LLTRACE_record_event_void TRACE_record_event_void +#define LLTRACE_record_event_u32 TRACE_record_event_u32 +#define LLTRACE_record_event_u32x2 TRACE_record_event_u32x2 +#define LLTRACE_record_event_u32x3 TRACE_record_event_u32x3 +#define LLTRACE_record_event_u32x4 TRACE_record_event_u32x4 +#define LLTRACE_record_event_u32x5 TRACE_record_event_u32x5 +#define LLTRACE_record_event_u32x6 TRACE_record_event_u32x6 +#define LLTRACE_record_event_u32x7 TRACE_record_event_u32x7 +#define LLTRACE_record_event_u32x8 TRACE_record_event_u32x8 +#define LLTRACE_record_event_u32x9 TRACE_record_event_u32x9 +#define LLTRACE_record_event_u32x10 TRACE_record_event_u32x10 +#define LLTRACE_record_event_end TRACE_record_event_end +#define LLTRACE_record_event_end_u32 TRACE_record_event_end_u32 +#endif + +// -------------------------------------------------------------------------------- +// Fields +// -------------------------------------------------------------------------------- + +/* + * @brief Identifies the MicroUI group to log an event. + */ +extern int32_t LLUI_EVENT_group; + +/* + * @brief Identifies the offset in the MicroUI group to log an event. + */ +extern int32_t LLUI_EVENT_offset; + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif // UI_LOG_H diff --git a/bsp/projects/microej/ui/inc/ui_rect_collection.h b/bsp/projects/microej/ui/inc/ui_rect_collection.h new file mode 100644 index 0000000..2f2425a --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_rect_collection.h @@ -0,0 +1,176 @@ +/* + * C + * + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#ifndef UI_RECT_COLLECTION_H +#define UI_RECT_COLLECTION_H +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @brief Exposes the ui_rect_collection_t type that handles unordered ui_rect_t collections + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include + +#include "ui_rect.h" + +// -------------------------------------------------------------------------------- +// Defines +// -------------------------------------------------------------------------------- + +/* + * @brief Defines the number of rectangles that collections can contain. + */ +#ifndef UI_RECT_COLLECTION_MAX_LENGTH +#define UI_RECT_COLLECTION_MAX_LENGTH 8u +#endif + +// -------------------------------------------------------------------------------- +// Typedefs +// -------------------------------------------------------------------------------- + +/* + * @brief A rectangle collection contains an array of rectangles and a pointer to + * the latest rectangle. + */ +typedef struct ui_rect_collection_t { + ui_rect_t data[UI_RECT_COLLECTION_MAX_LENGTH]; + size_t length; +} ui_rect_collection_t; + +// -------------------------------------------------------------------------------- +// Public functions +// -------------------------------------------------------------------------------- + +/* + * @brief Clears the collection: the latest rectangle points on the first rectangle. + * + * @param[in] collection the collection to clear + */ +static inline void UI_RECT_COLLECTION_clear(ui_rect_collection_t* collection) { + collection->length = 0; +} + +/* + * @brief Initializes the collection. + * + * @param[in] collection the collection to initialize + */ +static inline void UI_RECT_COLLECTION_init(ui_rect_collection_t* collection) { + UI_RECT_COLLECTION_clear(collection); +} + +/* + * @brief Gets the number of rectangles that have been added to the collection. + * + * @param[in] collection the collection to check + * + * @return the available number of rectangles in the collection + */ +static inline size_t UI_RECT_COLLECTION_get_length(const ui_rect_collection_t* collection) { + return collection->length; +} + +/* + * @brief Tells if the collection is full. + * + * @param[in] collection the collection to check + * + * @return true when the collection is full + */ +static inline bool UI_RECT_COLLECTION_is_full(const ui_rect_collection_t* collection) { + return UI_RECT_COLLECTION_get_length(collection) >= UI_RECT_COLLECTION_MAX_LENGTH; +} + +/* + * @brief Tells if the collection is empty. + * + * @param[in] collection the collection to check + * + * @return true when the collection is empty + */ +static inline bool UI_RECT_COLLECTION_is_empty(const ui_rect_collection_t* collection) { + return collection->length == 0u; +} + +/* + * @brief Gets the last rectangle added to the collection or NULL if the collection is empty. + * + * @param[in] collection the collection where retrieve latest element + * + * @return a rectangle or NULL + */ +static inline ui_rect_t* UI_RECT_COLLECTION_get_last(ui_rect_collection_t* collection) { + return UI_RECT_COLLECTION_is_empty(collection) ? NULL : (collection->data + collection->length - 1u); +} + +/* + * @brief Gets a pointer to the address after the last rectangle in the collection. + * + * @param[in] collection the collection + * + * @return a pointer to the address after the last element in the collection + */ +static inline ui_rect_t* UI_RECT_COLLECTION_get_end(ui_rect_collection_t* collection) { + return collection->data + collection->length; +} + +/* + * @brief Adds a rectangle in the collection. The implementation assumes that caller ensure that + * the collection is not full. The rectangle is copied to the collection. + * + * @param[in] collection the collection where copying the rectangle + * @param[in] element the rectangle to add + */ +static inline void UI_RECT_COLLECTION_add_rect(ui_rect_collection_t* collection, const ui_rect_t element) { + assert(!UI_RECT_COLLECTION_is_full(collection)); + collection->data[collection->length] = element; + collection->length++; +} + +/* + * @brief Removes a rectangle from the collection. The behavior is undefined if the rectangle is not part of the collection. + * + * @param[in] collection the collection which contains the rectangle + * @param[in] element the rectangle to remove + */ +static inline void UI_RECT_COLLECTION_remove_rect(ui_rect_collection_t* collection, ui_rect_t* element) { + assert(!UI_RECT_COLLECTION_is_empty(collection)); + assert(element >= collection->data); + assert(element < (collection->data + collection->length)); + *element = *UI_RECT_COLLECTION_get_last(collection); + collection->length--; +} + +/* + * @brief Removes all empty rectangles from the collection. + * + * @param[in] collection the collection + */ +static inline void UI_RECT_COLLECTION_remove_empty_rects(ui_rect_collection_t* collection) { + for (size_t i = 0; i < collection->length;) { + if (UI_RECT_is_empty(&collection->data[i])) { + UI_RECT_COLLECTION_remove_rect(collection, &collection->data[i]); + } else { + i++; + } + } +} + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif // UI_RECT_COLLECTION_H diff --git a/bsp/projects/microej/ui/inc/ui_rect_util.h b/bsp/projects/microej/ui/inc/ui_rect_util.h new file mode 100644 index 0000000..1e8cd54 --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_rect_util.h @@ -0,0 +1,88 @@ +/* + * C + * + * Copyright 2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#ifndef UI_RECT_UTIL_H +#define UI_RECT_UTIL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include + +#include "ui_rect.h" +#include "ui_util.h" + +// -------------------------------------------------------------------------------- +// Constants +// -------------------------------------------------------------------------------- + +#define UI_RECT_EMPTY { 1u, 1u, 0u, 0u } + +// -------------------------------------------------------------------------------- +// Functions +// -------------------------------------------------------------------------------- + +/* + * @brief Computes the minimum bounding rectangle of an array of two rectangles + * + * The behavior is undefined if the array is empty. + * + * @param[in] first the first rectangle + * @param[in] second the second rectangle + * @return the minimum bounding rectangle + */ +static inline ui_rect_t UI_RECT_get_minimum_bounding_rect_two_rects(const ui_rect_t* first, const ui_rect_t* second) { + return UI_RECT_new_xyxy(MIN(first->x1, second->x1), MIN(first->y1, second->y1), MAX(first->x2, second->x2), MAX(first->y2, second->y2)); +} + +/* + * @brief Computes the minimum bounding rectangle of an array of rectangles + * + * The behavior is undefined if the array is empty. + * + * @param[in] rects the array of rectangles + * @param[in] count the length of the array + * @return the minimum bounding rectangle + */ +ui_rect_t UI_RECT_get_minimum_bounding_rect(const ui_rect_t rects[], const size_t count); + +/* + * @brief Computes the union of two rectangles + * + * @param[out] output rectangles defining the union of the parameters + * @param[in] first the first rectangle + * @param[in] second the second rectangle + * + * @return the number of resulting rectangles. Some of them may be empty. + */ +uint32_t UI_RECT_union(ui_rect_t output[3], const ui_rect_t* first, const ui_rect_t* second); + +/* + * @brief Computes the difference between two rectangles + * + * @param[out] rectangles defining the difference between the parameters + * @param[in] first the original rectangle + * @param[in] second the rectangle that will be removed from the original one + * + * @return the number of resulting rectangles. Some of them may be empty. + */ +uint32_t UI_RECT_subtract(ui_rect_t output[4], const ui_rect_t* first, const ui_rect_t* second); + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // UI_RECT_UTIL_H diff --git a/bsp/projects/microej/ui/inc/ui_util.h b/bsp/projects/microej/ui/inc/ui_util.h new file mode 100644 index 0000000..399dcaf --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_util.h @@ -0,0 +1,41 @@ +/* + * C + * + * Copyright 2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#ifndef UI_UTIL_H +#define UI_UTIL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Macros and defines +// ----------------------------------------------------------------------------- + +/* + * @brief Gets the lowest value. + */ +#ifndef MIN +#define MIN(a,b) ((a) < (b) ? (a) : (b)) +#endif + +/* + * @brief Gets the highest value. + */ +#ifndef MAX +#define MAX(a,b) ((a) > (b) ? (a) : (b)) +#endif + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // UI_UTIL_H diff --git a/bsp/projects/microej/ui/inc/ui_vglite.h b/bsp/projects/microej/ui/inc/ui_vglite.h new file mode 100644 index 0000000..131c568 --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_vglite.h @@ -0,0 +1,306 @@ +/* + * C + * + * Copyright 2019-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief MicroEJ MicroUI library low level API: implementation over VGLite. Provides + * a set of helper functions to target the VGLite library. + * @author MicroEJ Developer Team + * @version 8.0.1 + */ + +#if !defined UI_VGLITE_H +#define UI_VGLITE_H + +#if defined __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include +#include + +#include "ui_vglite_configuration.h" +#include "vg_lite.h" + +// ----------------------------------------------------------------------------- +// Configuration Sanity Check +// ----------------------------------------------------------------------------- + +#ifndef VG_DRIVER_SINGLE_THREAD +#error "This define must be set in the BSP pre-processor options." +#endif + +/** + * Sanity check between the expected version of the configuration and the actual version of + * the configuration. + * If an error is raised here, it means that a new version of the CCO has been installed and + * the configuration ui_vglite_configuration.h must be updated based on the one provided + * by the new CCO version. + */ + +#if !defined UI_VGLITE_CONFIGURATION_VERSION +#error "Undefined UI_VGLITE_CONFIGURATION_VERSION, it must be defined in ui_vglite_configuration.h" +#endif + +#if defined UI_VGLITE_CONFIGURATION_VERSION && UI_VGLITE_CONFIGURATION_VERSION != 1 +#error "Version of the configuration file ui_vglite_configuration.h is not compatible with this implementation." +#endif + +// ----------------------------------------------------------------------------- +// API +// ----------------------------------------------------------------------------- + +/* + * @brief Initializes the VGLite library. + * + * @param[in] binary_semaphore: pointer to a binary semaphore; the semaphore must + * be configured in a state such that the semaphore must first be 'given' before it + * can be 'taken'. + */ +void UI_VGLITE_init(void* binary_semaphore); + +/* + * @brief The VEE Port must call this function in the GPU interrupt routine, just + * after calling vg_lite_IRQHandler() (often implemented in vglite_support.c). + */ +void UI_VGLITE_IRQHandler(void); + +/* + * @brief Flush the GPU operations. + * + * @param[in] wakeup_graphics_engine: true to wakeup the graphics engine as soon as + * the drawing is performed, false to perform an active waiting until the GPU interrupt + * is thrown + */ +void UI_VGLITE_start_operation(bool wakeup_graphics_engine); + +/* + * @brief Operation to perform after a VGLite drawing operation. + * On success, the asynchronous drawing is launched. This function does not wait for the end + * of the drawing. + * On error, an error message is displayed, the error flags in the graphics context are set, + * the drawing is considered as done (there is nothing to draw), and a call to UI_VGLITE_IMPL_notify_gpu_stop() + * is made to request GPU deactivation (if the function is implemented). + * + * @param[in] gc: the graphics context holding the error flags. + * @param[in] vg_lite_error: the VGLite drawing operation's return code. + * + * @return: the MicroUI status according to the drawing operation status. + */ +DRAWING_Status UI_VGLITE_post_operation(MICROUI_GraphicsContext* gc, vg_lite_error_t vg_lite_error); + +/* + * @brief Enables hardware rendering + * @see VGLITE_OPTION_TOGGLE_GPU + */ +void UI_VGLITE_enable_hardware_rendering(void); + +/* + * @brief Disables hardware rendering + * @see VGLITE_OPTION_TOGGLE_GPU + */ +void UI_VGLITE_disable_hardware_rendering(void); + +/* + * @brief Checks if hardware rendering is enabled + * + * @return: true if hardware rendering is enabled, false otherwise + * @see VGLITE_OPTION_TOGGLE_GPU + */ +bool UI_VGLITE_is_hardware_rendering_enabled(void); + +/* + * @brief Toggles hardware rendering + * @see VGLITE_OPTION_TOGGLE_GPU + */ +void UI_VGLITE_toggle_hardware_rendering(void); + +/* + * Because of VGLite library implementation, + * a buffer located at the same address should not be modified and reused + * as the VGLite library check if the buffer address match with the one + * stored in its context. If matching is successfull, render target will not + * be updated. + * This function rotate over an array of vg_lite_buffers to give a different + * buffer address at each call and configures it from a MICROUI_Image. + * The caller MUST send it to the vg_lite library to update its context. + * + * @param[in] gc: graphics context of destination + * + * @return a vg_lite buffer that should not match vg_lite library render context + */ +vg_lite_buffer_t* UI_VGLITE_configure_destination(MICROUI_GraphicsContext* gc); + +/* + * This function configures a source buffer from a MICROUI_Image. + * + * The blend mode in MicroUI is always SRC_OVER. VG_LITE_IMAGE_TRANSPARENT + * ignores fully transparent pixels, which is not a problem with this blend mode. + * + * In the case an other blend mode is used and drawing fully transparent pixels is + * needed, the caller could set buffer->transparency_mode to VG_LITE_IMAGE_OPAQUE + * after this function returns true, at the cost of a slight performance drop. + * + * @param[in] buffer: source buffer + * @param[in] image: source image + * + * @return false if source image format is not supported by vg_lite, true on success + */ +bool UI_VGLITE_configure_source(vg_lite_buffer_t *buffer, MICROUI_Image* image); + +/* + * @brief Premultiplies color components with the opacity to be compatible with VGLite GPU. + * + * @param[in] color: the color in non-premultiplied xRGB8888 format ('A' is ignored) + * @param[in] alpha: the opacity to apply + * @return the color in premultiplied ARGB8888 format + */ +uint32_t UI_VGLITE_premultiply_alpha(uint32_t color, uint8_t alpha); + +/* + * @brief Converts a non-premultiplied color into a premultiplied color. + * + * @param[in] color: the color in non-premultiplied ARGB8888 format + * @return the color in premultiplied ARGB8888 format + */ +uint32_t UI_VGLITE_premultiply(uint32_t color); + +/* + * @brief Tells if the GPU requires a pre-multiplied color (means the color components are multiplied by the alpha component). + * + * @return false if the GPU can manage non pre-multiplied colors. + */ +bool UI_VGLITE_need_to_premultiply(void); + +/* + * @brief Get color to give to VGLite library according to destination's foreground + * color, image format and opacity level. + * + * @param[in] gc: the MicroUI GraphicsContext of destination + * @param[in] img: the MicroUI Image of source + * @param[in] alpha: the application opacity + * + * @return The VGLite color + */ +vg_lite_color_t UI_VGLITE_get_vglite_color(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint alpha); + +/* + * @brief Configures the vg_lite's scissor according to the MicroUI clip. + * + * If the clip is disabled or empty, the drawing is useless and this function + * returns false. + * + * Otherwise the VGLite scissor is configured to match the MicroUI clip. + * + * @param[in] gc: the destination where performing the drawing (MicroUI Graphics Context) + * + * @return false when the drawing is useless (bounds out of clip) + */ +bool UI_VGLITE_enable_vg_lite_scissor(MICROUI_GraphicsContext* gc); + +/* + * @brief Configures the vg_lite's scissor according to the MicroUI clip and + * the given region. + * + * If the clip is disabled or empty or if the region is fully outside the clip, + * the drawing is useless and this function returns false. + * + * Otherwise the VGLite scissor is configured to match the intersection of the + * MicroUI clip and the region. + * + * @param[in] gc: the destination where performing the drawing (MicroUI Graphics Context) + * @param[in] x1..y2: the region + * + * @return false when the drawing is useless (bounds out of clip) + */ +bool UI_VGLITE_enable_vg_lite_scissor_region(MICROUI_GraphicsContext* gc, int x1, int y1, int x2, int y2); + +/* + * @brief Configures the vg_lite's scissor according to the MicroUI clip and + * the given area, transformed with the given matrix. + * + * If the clip is disabled or empty or if the area is fully outside the clip, + * the drawing is useless and this function returns false. + * + * Otherwise the VGLite scissor is configured to match the intersection of the + * MicroUI clip and the transformed area. + * + * @param[in] gc: the destination where performing the drawing (MicroUI Graphics Context) + * @param[in] width, height: the area size + * @param[in] matrix: the transformation to apply on the area + * + * @return false when the drawing is useless (bounds out of clip) + */ +bool UI_VGLITE_enable_vg_lite_scissor_area(MICROUI_GraphicsContext* gc, jfloat width, jfloat height, jfloat* matrix); + +/* + * @brief Returns the bit per pixel from a MicroUI image format + * + * @param[in] image_format: The MicroUI format of the image + * + * @return The bit per pixel of the image, or -1 if the image format is unknown + */ +int32_t UI_VGLITE_get_bpp(MICROUI_ImageFormat image_format); + +/* + * @brief Sets the drawing log flags matching a VGLite error code. + * + * The error will be reported to UI_VGLITE_IMPL_error(). + * + * @see LLUI_DISPLAY_reportError + * + * @param[in] gc: the graphics context holding the drawing log flags. + * @param[in] vg_lite_error: the VGLite error code. + * + * @return the drawing status that should be return by the calling drawing function. + */ +DRAWING_Status UI_VGLITE_report_vglite_error(MICROUI_GraphicsContext* gc, vg_lite_error_t vg_lite_error) ; + +// ----------------------------------------------------------------------------- +// Low Level API +// ----------------------------------------------------------------------------- + +/* + * @brief Notifies the GPU will be used just after this call. The implementation + * must ensure the GPU can be used (power management, clocks, etc.). + * + * Default implementation does nothing. + */ +void UI_VGLITE_IMPL_notify_gpu_start(void) ; + +/* + * @brief Notifies the GPU is not used anymore by the library until the next call to + * UI_VGLITE_IMPL_notify_gpu_start(). + * + * Default implementation does nothing. + */ +void UI_VGLITE_IMPL_notify_gpu_stop(void) ; + +/* + * @brief Notifies an error has occurred. This error may be critical, in this case, + * the implementation must stop the application execution (message + infinite loop). + * + * On error, default implementation loops indefinitely on error. + * + * @param[in] critical: tell whether the error is critical or not. + * @param[in] format: the error message and its arguments + */ +void UI_VGLITE_IMPL_error(bool critical, const char* format, ...); + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // !defined UI_VGLITE_H diff --git a/bsp/projects/microej/ui/inc/ui_vglite_configuration.h b/bsp/projects/microej/ui/inc/ui_vglite_configuration.h new file mode 100644 index 0000000..4e3b19a --- /dev/null +++ b/bsp/projects/microej/ui/inc/ui_vglite_configuration.h @@ -0,0 +1,94 @@ +/* + * C + * + * Copyright 2019-2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite. Provides + * a set of defines to configure the implementation. + * @author MicroEJ Developer Team + */ + +#if !defined UI_VGLITE_CONFIGURATION_H +# define UI_VGLITE_CONFIGURATION_H + +#if defined __cplusplus +extern "C" { +#endif + +//#error "This header must be customized with platform specific configuration. Remove this #error when done. This file is not modified when a new version of the CCO is installed." + +/** + * @brief Compatibility sanity check value. + * This define value is checked in the implementation to validate that the version of this configuration + * is compatible with the implementation. + * + * This value must not be changed by the user of the CCO. + * This value must be incremented by the implementor of the CCO when a configuration define is added, deleted or modified. + */ +#define UI_VGLITE_CONFIGURATION_VERSION (1) + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +/* + * @brief Width of the Tesselation window + * + * @Warning: this impacts the VGLite allocation size + */ +#define VGLITE_TESSELATION_WIDTH 256 + +/* + * @brief Height of the Tesselation window + * + * @Warning: this impacts the VGLite allocation size + */ +#define VGLITE_TESSELATION_HEIGHT 256 + +/* + * @brief GPU is less efficient than CPU to perform simple aliased drawings (line, rectangle etc.) + * + * This define forces to use the GPU. Comment it to use the software algorithms instead. + */ +#define VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +/* + * @brief GPU is less efficient than CPU to perform a simple "draw image": when the image to render has + * the same pixel definition than the destination buffer and no alpha blending is required. + * + * This defines forces to use the GPU to draw RGB565 images. Comment it to use the software algorithms + * instead. + */ +//#define VGLITE_USE_GPU_FOR_RGB565_IMAGES + +/* + * @brief GCNanoLite-V does not support MSAA. By consequence the "draw image" functions (with or without + * transformation like rotation or scale) cannot use GPU when the image to render contains transparent + * pixels. + * + * This defines forces to use the GPU to draw transparent images. Comment it to use the software algorithms + * instead. + */ +//#define VGLITE_USE_GPU_FOR_TRANSPARENT_IMAGES + +/* + * @brief Option to enable and disable the use of the GPU (toggle) at runtime. When the option is disabled, + * the calls to UI_VGLITE_xxx_hardware_rendering have no effect. + * + * This defines forces to enable the option. Comment it to disable the option. + */ +//#define VGLITE_OPTION_TOGGLE_GPU + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // !defined UI_VGLITE_CONFIGURATION_H diff --git a/bsp/projects/microej/ui/src/LLDW_PAINTER_impl.c b/bsp/projects/microej/ui/src/LLDW_PAINTER_impl.c new file mode 100644 index 0000000..f84a65c --- /dev/null +++ b/bsp/projects/microej/ui/src/LLDW_PAINTER_impl.c @@ -0,0 +1,195 @@ + +/* + * Copyright 2020-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief This file implements all "Drawing" (MicroUI extended library) drawing native functions. + * @see LLDW_PAINTER_impl.h file comment + * @author MicroEJ Developer Team + * @version 4.0.1 + * @since MicroEJ UI Pack 13.0.0 + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +// implements LLDW_PAINTER_impl functions +#include + +// use graphical engine functions to synchronize drawings +#include + +// calls ui_drawing functions +#include "ui_drawing.h" + +// logs the drawings +#include "ui_log.h" + +// -------------------------------------------------------------------------------- +// Macros and Defines +// -------------------------------------------------------------------------------- + +// macros to log a drawing +#define LOG_DRAW_START(fn) LLTRACE_record_event_u32(LLUI_EVENT_group, LLUI_EVENT_offset + UI_LOG_DRAW, CONCAT_DEFINES(LOG_DRAW_, fn)) +#define LOG_DRAW_END(s) LLTRACE_record_event_end_u32(LLUI_EVENT_group, LLUI_EVENT_offset + UI_LOG_DRAW, (s)) + +/* + * LOG_DRAW_EVENT logs identifiers + */ +#define LOG_DRAW_drawThickFadedPoint 100 +#define LOG_DRAW_drawThickFadedLine 101 +#define LOG_DRAW_drawThickFadedCircle 102 +#define LOG_DRAW_drawThickFadedCircleArc 103 +#define LOG_DRAW_drawThickFadedEllipse 104 +#define LOG_DRAW_drawThickLine 105 +#define LOG_DRAW_drawThickCircle 106 +#define LOG_DRAW_drawThickEllipse 107 +#define LOG_DRAW_drawThickCircleArc 108 + +#define LOG_DRAW_drawFlippedImage 200 +#define LOG_DRAW_drawRotatedImageNearestNeighbor 201 +#define LOG_DRAW_drawRotatedImageBilinear 202 +#define LOG_DRAW_drawScaledImageNearestNeighbor 203 +#define LOG_DRAW_drawScaledImageBilinear 204 + +// -------------------------------------------------------------------------------- +// LLDW_PAINTER_impl.h functions +// -------------------------------------------------------------------------------- + +void LLDW_PAINTER_IMPL_drawThickFadedPoint(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade) { + if (((thickness > 0) || (fade > 0)) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickFadedPoint)) { + LOG_DRAW_START(drawThickFadedPoint); + DRAWING_Status status = UI_DRAWING_drawThickFadedPoint(gc, x, y, thickness, fade); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +void LLDW_PAINTER_IMPL_drawThickFadedLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap) { + if (((thickness > 0) || (fade > 0)) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickFadedLine)) { + LOG_DRAW_START(drawThickFadedLine); + DRAWING_Status status = UI_DRAWING_drawThickFadedLine(gc, startX, startY, endX, endY, thickness, fade, startCap, endCap); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +void LLDW_PAINTER_IMPL_drawThickFadedCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade) { + if (((thickness > 0) || (fade > 0)) && (diameter > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickFadedCircle)) { + LOG_DRAW_START(drawThickFadedCircle); + DRAWING_Status status = UI_DRAWING_drawThickFadedCircle(gc, x, y, diameter, thickness, fade); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +void LLDW_PAINTER_IMPL_drawThickFadedCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end) { + if (((thickness > 0) || (fade > 0)) && (diameter > 0) && ((int32_t)arcAngle != 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickFadedCircleArc)) { + LOG_DRAW_START(drawThickFadedCircleArc); + DRAWING_Status status = UI_DRAWING_drawThickFadedCircleArc(gc, x, y, diameter, startAngle, arcAngle, thickness, fade, start, end); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +void LLDW_PAINTER_IMPL_drawThickFadedEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade) { + if (((thickness > 0) || (fade > 0)) && (width > 0) && (height > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickFadedEllipse)) { + LOG_DRAW_START(drawThickFadedEllipse); + DRAWING_Status status = UI_DRAWING_drawThickFadedEllipse(gc, x, y, width, height, thickness, fade); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +void LLDW_PAINTER_IMPL_drawThickLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness) { + if ((thickness > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickLine)) { + LOG_DRAW_START(drawThickLine); + DRAWING_Status status = UI_DRAWING_drawThickLine(gc, startX, startY, endX, endY, thickness); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +void LLDW_PAINTER_IMPL_drawThickCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness) { + if ((thickness > 0) && (diameter > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickCircle)) { + LOG_DRAW_START(drawThickCircle); + DRAWING_Status status = UI_DRAWING_drawThickCircle(gc, x, y, diameter, thickness); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +void LLDW_PAINTER_IMPL_drawThickEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness) { + if ((thickness > 0) && (width > 0) && (height > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickEllipse)) { + LOG_DRAW_START(drawThickEllipse); + DRAWING_Status status = UI_DRAWING_drawThickEllipse(gc, x, y, width, height, thickness); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +void LLDW_PAINTER_IMPL_drawThickCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness) { + if ((thickness > 0) && (diameter > 0) && ((int32_t)arcAngle != 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickCircleArc)) { + LOG_DRAW_START(drawThickCircleArc); + DRAWING_Status status = UI_DRAWING_drawThickCircleArc(gc, x, y, diameter, startAngle, arcAngle, thickness); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +void LLDW_PAINTER_IMPL_drawFlippedImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha) { + if (!LLUI_DISPLAY_isClosed(img) && (alpha > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawFlippedImage)) { + LOG_DRAW_START(drawFlippedImage); + DRAWING_Status status = UI_DRAWING_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +void LLDW_PAINTER_IMPL_drawRotatedImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha) { + if (!LLUI_DISPLAY_isClosed(img) && (alpha > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawRotatedImageNearestNeighbor)) { + LOG_DRAW_START(drawRotatedImageNearestNeighbor); + DRAWING_Status status = UI_DRAWING_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +void LLDW_PAINTER_IMPL_drawRotatedImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha) { + if (!LLUI_DISPLAY_isClosed(img) && (alpha > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawRotatedImageBilinear)) { + LOG_DRAW_START(drawRotatedImageBilinear); + DRAWING_Status status = UI_DRAWING_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +void LLDW_PAINTER_IMPL_drawScaledImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha) { + if (!LLUI_DISPLAY_isClosed(img) && (alpha > 0) && (factorX > 0.f) && (factorY > 0.f) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawScaledImageNearestNeighbor)) { + LOG_DRAW_START(drawScaledImageNearestNeighbor); + DRAWING_Status status = UI_DRAWING_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +void LLDW_PAINTER_IMPL_drawScaledImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha) { + if (!LLUI_DISPLAY_isClosed(img) && (alpha > 0) && (factorX > 0.f) && (factorY > 0.f) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawScaledImageBilinear)) { + LOG_DRAW_START(drawScaledImageBilinear); + DRAWING_Status status = UI_DRAWING_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); + } +} + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_DISPLAY_HEAP_impl.c b/bsp/projects/microej/ui/src/LLUI_DISPLAY_HEAP_impl.c similarity index 86% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_DISPLAY_HEAP_impl.c rename to bsp/projects/microej/ui/src/LLUI_DISPLAY_HEAP_impl.c index 3da0b1a..77a76e8 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_DISPLAY_HEAP_impl.c +++ b/bsp/projects/microej/ui/src/LLUI_DISPLAY_HEAP_impl.c @@ -1,7 +1,7 @@ /* * C * - * Copyright 2021-2022 MicroEJ Corp. All rights reserved. + * Copyright 2021-2024 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -13,8 +13,7 @@ * * @see LLUI_DISPLAY_impl.h file comment * @author MicroEJ Developer Team - * @version 2.0.0 - * @date 22 July 2022 + * @version 4.0.1 * @since MicroEJ UI Pack 13.1.0 */ @@ -25,10 +24,6 @@ #include "microui_heap.h" #include "BESTFIT_ALLOCATOR.h" -#ifdef __cplusplus -extern "C" { -#endif - // -------------------------------------------------------------------------------- // Macros and Defines // -------------------------------------------------------------------------------- @@ -75,14 +70,14 @@ uint32_t MICROUI_HEAP_number_of_allocated_blocks(void) { // -------------------------------------------------------------------------------- -void LLUI_DISPLAY_IMPL_image_heap_initialize(uint8_t* heap_start, uint8_t* heap_limit) { +void LLUI_DISPLAY_IMPL_imageHeapInitialize(uint8_t* heap_start, uint8_t* heap_limit) { heap_size = heap_limit - heap_start - BESTFITALLOCATOR_HEADER_SIZE; free_space = heap_size; BESTFIT_ALLOCATOR_new(&image_heap); BESTFIT_ALLOCATOR_initialize(&image_heap, (int32_t)heap_start, (int32_t)heap_limit); } -uint8_t* LLUI_DISPLAY_IMPL_image_heap_allocate(uint32_t size) { +uint8_t* LLUI_DISPLAY_IMPL_imageHeapAllocate(uint32_t size) { uint8_t* addr = (uint8_t*)BESTFIT_ALLOCATOR_allocate(&image_heap, (int32_t)size); if ((uint8_t*)0 != addr) { @@ -92,7 +87,7 @@ uint8_t* LLUI_DISPLAY_IMPL_image_heap_allocate(uint32_t size) { return addr; } -void LLUI_DISPLAY_IMPL_image_heap_free(uint8_t* block) { +void LLUI_DISPLAY_IMPL_imageHeapFree(uint8_t* block) { free_space += BESTFITALLOCATOR_BLOCK_SIZE(block); allocated_blocks_number--; BESTFIT_ALLOCATOR_free(&image_heap, (void*)block); @@ -102,6 +97,3 @@ void LLUI_DISPLAY_IMPL_image_heap_free(uint8_t* block) { // EOF // -------------------------------------------------------------------------------- -#ifdef __cplusplus -} -#endif diff --git a/bsp/projects/microej/ui/src/LLUI_DISPLAY_impl.c b/bsp/projects/microej/ui/src/LLUI_DISPLAY_impl.c new file mode 100644 index 0000000..7e7a44a --- /dev/null +++ b/bsp/projects/microej/ui/src/LLUI_DISPLAY_impl.c @@ -0,0 +1,359 @@ +/* + * C + * + * Copyright 2020-2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief Implementation of MicroEJ MicroUI library low level API "LLUI_DISPLAY_impl.h" + * for the NXP MIMXRT595-EVK board. + * @author MicroEJ Developer Team + * @version 7.0.0 + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include + +#include + +#include +#include + +#include "bsp_util.h" +#include "display_dma.h" +#include "ui_vglite.h" +#include "display_impl.h" +#include "framerate.h" +#include "ui_display_brs.h" +#include "power_manager.h" + +#include "vglite_window.h" + +#include "fsl_debug_console.h" +#include "fsl_dc_fb_dsi_cmd.h" + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +#if (CUSTOM_VGLITE_MEMORY_CONFIG != 1) +#error "Application must be compiled with CUSTOM_VGLITE_MEMORY_CONFIG=1" +#else +#define VGLITE_COMMAND_BUFFER_SZ (128 * 1024) +#define VGLITE_HEAP_SZ 0x100000 +#endif + +#define DISPLAY_STACK_SIZE (8 * 1024) +#define DISPLAY_TASK_PRIORITY (12) /** Should be > tskIDLE_PRIORITY & < configTIMER_TASK_PRIORITY */ +#define DISPLAY_TASK_STACK_SIZE (DISPLAY_STACK_SIZE / 4) + +// ----------------------------------------------------------------------------- +// Global Variables +// ----------------------------------------------------------------------------- + +/* Allocate the heap and set the command buffer(s) size */ +AT_NONCACHEABLE_SECTION_ALIGN(uint8_t vglite_heap[VGLITE_HEAP_SZ], 64); + +void *vglite_heap_base = &vglite_heap; +uint32_t vglite_heap_size = VGLITE_HEAP_SZ; +uint32_t vglite_cmd_buff_size = VGLITE_COMMAND_BUFFER_SZ; + +/* + * @brief: Semaphore to synchronize the display flush with MicroUI + */ +static SemaphoreHandle_t sync_flush; +static uint8_t* dirty_area_addr; // Address of the source framebuffer +static uint8_t dirty_area_flush; // Identifier of the flush + +#if UI_DISPLAY_BRS == UI_DISPLAY_BRS_LEGACY +static int32_t dirty_area_ymin; // Top-most coordinate of the area to synchronize +static int32_t dirty_area_ymax; // Bottom-most coordinate of the area to synchronize +#endif + +/* + * @brief VGLite display context + */ +static vg_lite_display_t display; + +/* + * @brief VGLite window context + */ +static vg_lite_window_t window; + +// ----------------------------------------------------------------------------- +// Private functions +// ----------------------------------------------------------------------------- + +/* + * @brief: Task to manage display flushes and synchronize with hardware rendering + * operations + */ +static void __display_task(void * pvParameters) { + (void)pvParameters; + + do { + + xSemaphoreTake(sync_flush, portMAX_DELAY); + + // save the flush conf: can be modified by the next call to flush() as soon as LLUI_DISPLAY_setDrawingBuffer() will wake up the Graphics Engine + uint8_t* flush_addr = dirty_area_addr; +#if UI_DISPLAY_BRS == UI_DISPLAY_BRS_PREDRAW + uint8_t flush_identifier = dirty_area_flush; +#endif + + // Two actions: + // 1- wait for the end of previous swap (if not already done): wait the + // end of sending of current frame buffer to display + // 2- start sending of current_buffer to display (without waiting the + // end) + VGLITE_SwapBuffers(&window); + + // Increment framerate + framerate_increment(); + +#if defined (FRAME_BUFFER_COUNT) && (FRAME_BUFFER_COUNT > 1) + vg_lite_buffer_t *current_buffer = VGLITE_GetRenderTarget(&window); + + // Configure frame buffer powering; at that point current_buffer is back buffer + // cppcheck-suppress [misra-c2012-11.3] cast to (framebuffer_t *) is valid + DISPLAY_IMPL_update_frame_buffer_status(current_buffer->memory, (framebuffer_t *)flush_addr); + +#if UI_DISPLAY_BRS == UI_DISPLAY_BRS_LEGACY +#if defined (DISPLAY_DMA_ENABLED) && (DISPLAY_DMA_ENABLED != 0) + DISPLAY_DMA_start( + (void *) flush_addr, + current_buffer->memory, + dirty_area_ymin, + dirty_area_ymax); + // back buffer currently in restoration; wait for restoration before unlocking next drawing +#else + memcpy( + &((uint8_t*) current_buffer->memory)[dirty_area_ymin * current_buffer->stride], + &((uint8_t*) flush_addr)[dirty_area_ymin * current_buffer->stride], + (dirty_area_ymax - dirty_area_ymin + 1) * current_buffer->stride + ); + // back buffer restored can be used for next drawing + if (!LLUI_DISPLAY_setDrawingBuffer(flush_identifier, current_buffer->memory, false)) { + // end of flush not expected; the Graphics Engine keeps using previous back buffer; + // have to cancel the buffers swap + VGLITE_CancelSwapBuffers(); + } +#endif // defined DISPLAY_DMA_ENABLED +#elif UI_DISPLAY_BRS == UI_DISPLAY_BRS_PREDRAW + + // back buffer not restored but can be used for next drawing + if (LLUI_DISPLAY_setDrawingBuffer(flush_identifier, current_buffer->memory, false)) { + + // wait for LCD refresh + (void)FBDEV_GetFrameBuffer(&(display.g_fbdev), 0); + + // here: back buffer sent to the LCD, the buffer can be used again for next drawing + // in case of no new drawing has been already performed in new back buffer + + // if another flush is already pending: xxx + + // reuse same back buffer if no drawing has been already performed + if (LLUI_DISPLAY_setDrawingBuffer(flush_identifier, flush_addr, false)){ + // new back buffer set: cancel the previous swap to synchronoze the driver with the Graphics Engine + // PRINTF("reuse 0x%x\n", flush_addr); + VGLITE_CancelSwapBuffers(); + } + // else: too late to set this old LCD buffer back buffer; nothing to do + } + else { + // end of flush not expected; the Graphics Engine keeps using previous back buffer; + // have to cancel the buffers swap + VGLITE_CancelSwapBuffers(); + } + + +#endif // UI_DISPLAY_BRS +#else // FRAME_BUFFER_COUNT + // buffer being sent, should not be used for next drawing until end of drawing + (void)FBDEV_GetFrameBuffer(&(display.g_fbdev), 0); +#endif // FRAME_BUFFER_COUNT + + + + } while (1); +} + +// ----------------------------------------------------------------------------- +// Low Level API [optional]: weak functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void DISPLAY_IMPL_initialized(void) { + // does nothing by default +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void DISPLAY_IMPL_update_frame_buffer_status(framebuffer_t* frame_buffer_on, framebuffer_t* frame_buffer_off) { + // does nothing by default + (void)frame_buffer_on; + (void)frame_buffer_off; +} + +/* + * @brief Asks to the CCO MicroUI-VGLite to initialize the VG-Lite library. When this CCO + * is not installed / available, the default function is used and does nothing. + */ +BSP_DECLARE_WEAK_FCNT void UI_VGLITE_init(void* sem) { + // does nothing by default + vSemaphoreDelete((SemaphoreHandle_t) sem); +} + +// ----------------------------------------------------------------------------- +// LLUI_DISPLAY_impl.h functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +void DISPLAY_DMA_IMPL_notify_dma_stop(void) { +#if UI_DISPLAY_BRS == UI_DISPLAY_BRS_PREDRAW + LLUI_DISPLAY_notifyAsynchronousDrawingEnd(true); +#else + // restoration done -> use the previous LCD buffer (== VGLITE_GetRenderTarget()) as new back buffer + vg_lite_buffer_t *current_buffer = VGLITE_GetRenderTarget(&window); + if (!LLUI_DISPLAY_setDrawingBuffer(dirty_area_flush, current_buffer->memory, true)) { + // end of flush not expected; the Graphics Engine keeps using previous back buffer; + // have to cancel the buffers swap + VGLITE_CancelSwapBuffers(); + } +#endif +} + +// See the header file for the function documentation +void LLUI_DISPLAY_IMPL_initialize(LLUI_DISPLAY_SInitData* init_data) { + + /*************** + * Init VGLite * + ***************/ + + if (kStatus_Success != BOARD_PrepareVGLiteController()) { + UI_VGLITE_IMPL_error(true, "Prepare VGlite controlor error"); + } + + vg_lite_error_t ret = VG_LITE_SUCCESS; + + if (VG_LITE_SUCCESS != VGLITE_CreateDisplay(&display)) { + UI_VGLITE_IMPL_error(true, "VGLITE_CreateDisplay failed: VGLITE_CreateDisplay() returned error %d", ret); + } + + // Initialize the window. + if (VG_LITE_SUCCESS != VGLITE_CreateWindow(&display, &window)) { + UI_VGLITE_IMPL_error(true, "VGLITE_CreateWindow failed: VGLITE_CreateWindow() returned error %d", ret); + } + + // force to empty the counter + for (uint8_t i = 0; i < window.bufferCount; i++) { + (void)FBDEV_GetFrameBuffer(&(display.g_fbdev), 0); + } + + UI_VGLITE_init((void*)xSemaphoreCreateBinary()); + + /************ + * Init DMA * + ************/ + +#if defined (DISPLAY_DMA_ENABLED) && (DISPLAY_DMA_ENABLED != 0) + DISPLAY_DMA_initialize(s_frameBufferAddress); +#endif // defined DISPLAY_DMA_ENABLED + + /************* + * Init task * + *************/ + + sync_flush = xSemaphoreCreateBinary(); + if (pdPASS != xTaskCreate( + __display_task, + "Display", + DISPLAY_TASK_STACK_SIZE, + NULL, + DISPLAY_TASK_PRIORITY, + NULL)){ + UI_VGLITE_IMPL_error(true, "failed to create task __display\n"); + } + + /**************** + * Init MicroUI * + ****************/ + + vg_lite_buffer_t *buffer = VGLITE_GetRenderTarget(&window); + init_data->binary_semaphore_0 = (void*)xSemaphoreCreateBinary(); + init_data->binary_semaphore_1 = (void*)xSemaphoreCreateBinary(); + init_data->lcd_width = window.width; + init_data->lcd_height = window.height; + init_data->memory_width = FRAME_BUFFER_STRIDE_PIXELS; + init_data->back_buffer_address = (uint8_t*)buffer->memory; + + // notify that the display is initialized + DISPLAY_IMPL_initialized(); +} + +// See the header file for the function documentation +void LLUI_DISPLAY_IMPL_flush(MICROUI_GraphicsContext* gc, uint8_t flush_identifier, const ui_rect_t areas[], size_t length) { + + uint8_t* addr = LLUI_DISPLAY_getBufferAddress(&gc->image); + + // store dirty area to restore after the flush + dirty_area_addr = addr; + dirty_area_flush = flush_identifier; + +#if UI_DISPLAY_BRS == UI_DISPLAY_BRS_LEGACY + dirty_area_ymin = areas[0].y1; + dirty_area_ymax = areas[0].y2; +#endif + + // wakeup display task + xSemaphoreGive(sync_flush); +} + +// See the header file for the function documentation +void LLUI_DISPLAY_IMPL_binarySemaphoreTake(void* sem) { + xSemaphoreTake((SemaphoreHandle_t)sem, portMAX_DELAY); +} + +// See the header file for the function documentation +void LLUI_DISPLAY_IMPL_binarySemaphoreGive(void* sem, bool under_isr) { + + if (under_isr) { + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + xSemaphoreGiveFromISR((SemaphoreHandle_t)sem, &xHigherPriorityTaskWoken); + if(xHigherPriorityTaskWoken != pdFALSE ) { + // Force a context switch here. + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } + } + else { + xSemaphoreGive((SemaphoreHandle_t)sem); + } +} + +// See the header file for the function documentation +void UI_VGLITE_IMPL_notify_gpu_start(void) { + power_manager_enable_low_power(POWER_GPU, LOW_POWER_FORBIDDEN); +} + +// See the header file for the function documentation +void UI_VGLITE_IMPL_notify_gpu_stop(void) { + power_manager_enable_low_power(POWER_GPU, LOW_POWER_AUTHORIZED); +} + +// See the header file for the function documentation +void UI_VGLITE_IMPL_error(bool critical, const char* format, ...) { + (void)format; + va_list arg; + va_start (arg, format); + PRINTF(format, arg); + va_end (arg); + while (critical){} +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_INPUT_LOG_impl.c b/bsp/projects/microej/ui/src/LLUI_INPUT_LOG_impl.c similarity index 92% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_INPUT_LOG_impl.c rename to bsp/projects/microej/ui/src/LLUI_INPUT_LOG_impl.c index 2bd9619..feb46b1 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_INPUT_LOG_impl.c +++ b/bsp/projects/microej/ui/src/LLUI_INPUT_LOG_impl.c @@ -1,7 +1,7 @@ /* * C * - * Copyright 2021-2022 MicroEJ Corp. All rights reserved. + * Copyright 2021-2024 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -17,8 +17,7 @@ * * @see LLUI_INPUT_impl.h file comment * @author MicroEJ Developer Team - * @version 2.0.0 - * @date 22 July 2022 + * @version 4.0.1 * @since MicroEJ UI Pack 13.1.0 */ @@ -30,15 +29,11 @@ #include // implements some LLUI_INPUT_impl functions -#include "LLUI_INPUT_impl.h" +#include // deport event description to another file #include "microui_event_decoder.h" -#ifdef __cplusplus -extern "C" { -#endif - #ifdef MICROUIEVENTDECODER_ENABLED // ----------------------------------------------------------------------------- @@ -182,7 +177,3 @@ void LLUI_INPUT_IMPL_log_dump(bool log_type, uint32_t log, uint32_t index) { // EOF // ----------------------------------------------------------------------------- -#ifdef __cplusplus -} -#endif - diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_INPUT_impl.c b/bsp/projects/microej/ui/src/LLUI_INPUT_impl.c similarity index 90% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_INPUT_impl.c rename to bsp/projects/microej/ui/src/LLUI_INPUT_impl.c index 07e7c89..701faea 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_INPUT_impl.c +++ b/bsp/projects/microej/ui/src/LLUI_INPUT_impl.c @@ -2,7 +2,8 @@ * C * * Copyright 2019-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ // ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_PAINTER_impl.c b/bsp/projects/microej/ui/src/LLUI_PAINTER_impl.c similarity index 84% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_PAINTER_impl.c rename to bsp/projects/microej/ui/src/LLUI_PAINTER_impl.c index 5b7c6f1..97ed224 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_PAINTER_impl.c +++ b/bsp/projects/microej/ui/src/LLUI_PAINTER_impl.c @@ -1,6 +1,6 @@ /* - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. + * Copyright 2020-2024 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -9,8 +9,7 @@ * @brief This file implements all MicroUI drawing native functions. * @see LLUI_PAINTER_impl.h file comment * @author MicroEJ Developer Team - * @version 2.0.0 - * @date 22 July 2022 + * @version 4.0.1 * @since MicroEJ UI Pack 13.0.0 */ @@ -19,25 +18,31 @@ // -------------------------------------------------------------------------------- // implements LLUI_PAINTER_impl functions -#include "LLUI_PAINTER_impl.h" +#include + +// use graphical engine functions to synchronize drawings +#include + +// check UI Pack version +#include // calls ui_drawing functions #include "ui_drawing.h" -// use graphical engine functions to synchronize drawings -#include "LLUI_DISPLAY.h" - -#ifdef __cplusplus -extern "C" { -#endif +// logs the drawings +#include "ui_log.h" // -------------------------------------------------------------------------------- // Macros and Defines // -------------------------------------------------------------------------------- +#if (defined(LLUI_MAJOR_VERSION) && (LLUI_MAJOR_VERSION != 14)) || (defined(LLUI_MINOR_VERSION) && (LLUI_MINOR_VERSION < 0)) +#error "This CCO is only compatible with UI Pack [14.0.0,15.0.0[" +#endif + // macros to log a drawing -#define LOG_DRAW_START(fn) LLUI_DISPLAY_logDrawingStart(CONCAT_DEFINES(LOG_DRAW_, fn)) -#define LOG_DRAW_END(fn) LLUI_DISPLAY_logDrawingEnd(CONCAT_DEFINES(LOG_DRAW_, fn)) +#define LOG_DRAW_START(fn) LLTRACE_record_event_u32(LLUI_EVENT_group, LLUI_EVENT_offset + UI_LOG_DRAW, CONCAT_DEFINES(LOG_DRAW_, fn)) +#define LOG_DRAW_END(s) LLTRACE_record_event_end_u32(LLUI_EVENT_group, LLUI_EVENT_offset + UI_LOG_DRAW, (s)) /* * LOG_DRAW_EVENT logs identifiers @@ -85,6 +90,7 @@ static inline void _check_bound(jint max, jint* bound, jint* size, jint* origin) // LLUI_PAINTER_impl.h functions // -------------------------------------------------------------------------------- +// See the header file for the function documentation void LLUI_PAINTER_IMPL_writePixel(MICROUI_GraphicsContext* gc, jint x, jint y) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_writePixel)) { DRAWING_Status status; @@ -98,21 +104,22 @@ void LLUI_PAINTER_IMPL_writePixel(MICROUI_GraphicsContext* gc, jint x, jint y) { status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(writePixel); + LOG_DRAW_END(status); } - // else: pixel out of clip: nothing to do (requestDrawing() has not been called) } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_drawLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_drawLine)) { LOG_DRAW_START(drawLine); // cannot reduce/clip line: may be endX < startX and / or endY < startY - LLUI_DISPLAY_setDrawingStatus(UI_DRAWING_drawLine(gc, startX, startY, endX, endY)); - LOG_DRAW_END(drawLine); + DRAWING_Status status = UI_DRAWING_drawLine(gc, startX, startY, endX, endY); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_DRAW_END(status); } - // else: refused drawing } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_drawHorizontalLine(MICROUI_GraphicsContext* gc, jint x, jint y, jint length) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_drawHorizontalLine)) { DRAWING_Status status; @@ -131,11 +138,11 @@ void LLUI_PAINTER_IMPL_drawHorizontalLine(MICROUI_GraphicsContext* gc, jint x, j status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(drawHorizontalLine); + LOG_DRAW_END(status); } - // else: line out of clip: nothing to do (requestDrawing() has not been called) } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_drawVerticalLine(MICROUI_GraphicsContext* gc, jint x, jint y, jint length) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_drawVerticalLine)) { DRAWING_Status status; @@ -154,11 +161,11 @@ void LLUI_PAINTER_IMPL_drawVerticalLine(MICROUI_GraphicsContext* gc, jint x, jin status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(drawVerticalLine); + LOG_DRAW_END(status); } - // else: line out of clip: nothing to do (requestDrawing() has not been called) } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_drawRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_drawRectangle)) { DRAWING_Status status; @@ -180,11 +187,11 @@ void LLUI_PAINTER_IMPL_drawRectangle(MICROUI_GraphicsContext* gc, jint x, jint y status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(drawRectangle); + LOG_DRAW_END(status); } - // else: refused drawing } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_fillRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_fillRectangle)) { DRAWING_Status status; @@ -196,20 +203,21 @@ void LLUI_PAINTER_IMPL_fillRectangle(MICROUI_GraphicsContext* gc, jint x, jint y jint y2 = y + height - 1; // tests on size and clip are performed after suspend to prevent to perform it several times - if ((width > 0) && (height) > 0 && LLUI_DISPLAY_clipRectangle(gc, &x1, &y1, &x2, &y2)) { + if ((width > 0) && (height > 0) && LLUI_DISPLAY_clipRectangle(gc, &x1, &y1, &x2, &y2)) { LLUI_DISPLAY_configureClip(gc, false /* rectangle has been clipped */); status = UI_DRAWING_fillRectangle(gc, x1, y1, x2, y2); + } else { // requestDrawing() has been called and accepted: notify the end of empty drawing status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(fillRectangle); + LOG_DRAW_END(status); } - // else: rectangle out of clip: nothing to do (requestDrawing() has not been called) } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_drawRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_drawRoundedRectangle)) { DRAWING_Status status; @@ -226,11 +234,11 @@ void LLUI_PAINTER_IMPL_drawRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(drawRoundedRectangle); + LOG_DRAW_END(status); } - // else: refused drawing } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_fillRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_fillRoundedRectangle)) { DRAWING_Status status; @@ -247,11 +255,11 @@ void LLUI_PAINTER_IMPL_fillRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(fillRoundedRectangle); + LOG_DRAW_END(status); } - // else: refused drawing } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_drawCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_drawCircleArc)) { DRAWING_Status status; @@ -268,11 +276,11 @@ void LLUI_PAINTER_IMPL_drawCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(drawCircleArc); + LOG_DRAW_END(status); } - // else: refused drawing } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_drawEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_drawEllipseArc)) { DRAWING_Status status; @@ -289,11 +297,11 @@ void LLUI_PAINTER_IMPL_drawEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(drawEllipseArc); + LOG_DRAW_END(status); } - // else: refused drawing } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_fillCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_fillCircleArc)) { DRAWING_Status status; @@ -310,11 +318,11 @@ void LLUI_PAINTER_IMPL_fillCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(fillCircleArc); + LOG_DRAW_END(status); } - // else: refused drawing } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_fillEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_fillEllipseArc)) { DRAWING_Status status; @@ -331,11 +339,11 @@ void LLUI_PAINTER_IMPL_fillEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(fillEllipseArc); + LOG_DRAW_END(status); } - // else: refused drawing } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_drawEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_drawEllipse)) { DRAWING_Status status; @@ -352,11 +360,11 @@ void LLUI_PAINTER_IMPL_drawEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(drawEllipse); + LOG_DRAW_END(status); } - // else: refused drawing } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_fillEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_fillEllipse)) { DRAWING_Status status; @@ -373,11 +381,11 @@ void LLUI_PAINTER_IMPL_fillEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(fillEllipse); + LOG_DRAW_END(status); } - // else: refused drawing } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_drawCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_drawCircle)) { DRAWING_Status status; @@ -394,11 +402,11 @@ void LLUI_PAINTER_IMPL_drawCircle(MICROUI_GraphicsContext* gc, jint x, jint y, j status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(drawCircle); + LOG_DRAW_END(status); } - // else: refused drawing } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_fillCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_fillCircle)) { DRAWING_Status status; @@ -415,11 +423,11 @@ void LLUI_PAINTER_IMPL_fillCircle(MICROUI_GraphicsContext* gc, jint x, jint y, j status = DRAWING_DONE; } LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(fillCircle); + LOG_DRAW_END(status); } - // else: refused drawing } +// See the header file for the function documentation void LLUI_PAINTER_IMPL_drawImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha) { if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLUI_PAINTER_IMPL_drawImage)) { DRAWING_Status status = DRAWING_DONE; @@ -446,9 +454,11 @@ void LLUI_PAINTER_IMPL_drawImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img if (gc->image.format == img->format) { // source & destination have got the same pixels memory representation - if (0xff /* fully opaque */ == l_alpha && !LLUI_DISPLAY_isTransparent(img)) { + MICROUI_Image* image = LLUI_DISPLAY_getSourceImage(img); + + if ((0xff /* fully opaque */ == l_alpha) && !LLUI_DISPLAY_isTransparent(img)) { // copy source on destination without applying an opacity (beware about the overlapping) - status = UI_DRAWING_copyImage(gc, img, regionX, regionY, width, height, x, y); + status = UI_DRAWING_copyImage(gc, image, regionX, regionY, width, height, x, y); } else if (img == &gc->image){ // blend source on itself applying an opacity (beware about the overlapping) @@ -456,7 +466,7 @@ void LLUI_PAINTER_IMPL_drawImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img } else { // blend source on destination applying an opacity - status = UI_DRAWING_drawImage(gc, img, regionX, regionY, width, height, x, y, l_alpha); + status = UI_DRAWING_drawImage(gc, image, regionX, regionY, width, height, x, y, l_alpha); } } else { @@ -470,15 +480,10 @@ void LLUI_PAINTER_IMPL_drawImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img // requestDrawing() has been called and accepted: notify the end of empty drawing LLUI_DISPLAY_setDrawingStatus(status); - LOG_DRAW_END(drawImage); + LOG_DRAW_END(status); } - // else: refused drawing } // -------------------------------------------------------------------------------- // EOF // -------------------------------------------------------------------------------- - -#ifdef __cplusplus -} -#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/buttons_helper.c b/bsp/projects/microej/ui/src/buttons_helper.c similarity index 92% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/buttons_helper.c rename to bsp/projects/microej/ui/src/buttons_helper.c index d4c7ebd..ea1f0c3 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/buttons_helper.c +++ b/bsp/projects/microej/ui/src/buttons_helper.c @@ -2,7 +2,8 @@ * C * * Copyright 2015-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ /* diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/buttons_manager.c b/bsp/projects/microej/ui/src/buttons_manager.c similarity index 93% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/buttons_manager.c rename to bsp/projects/microej/ui/src/buttons_manager.c index 92e973c..16db6c2 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/buttons_manager.c +++ b/bsp/projects/microej/ui/src/buttons_manager.c @@ -2,7 +2,8 @@ * C * * Copyright 2013-2021 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ // ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_dma.c b/bsp/projects/microej/ui/src/display_dma.c similarity index 79% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_dma.c rename to bsp/projects/microej/ui/src/display_dma.c index 118d2a3..06ef884 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_dma.c +++ b/bsp/projects/microej/ui/src/display_dma.c @@ -1,15 +1,16 @@ /* * C * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. + * Copyright 2020-2024 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ /* * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite + * @brief Implementation of MicroEJ MicroUI library low level API "LLUI_DISPLAY_impl.h" + * for the NXP MIMXRT595-EVK board. * @author MicroEJ Developer Team - * @version 3.0.0 + * @version 7.0.0 */ // ----------------------------------------------------------------------------- @@ -21,6 +22,8 @@ #include "display_dma.h" #include "display_impl.h" #include "vglite_window.h" +#include "bsp_util.h" +#include "interrupts.h" #include "fsl_dma.h" @@ -61,11 +64,11 @@ static dma_handle_t g_DMA_Handle; #if defined(__ICCARM__) #pragma data_alignment = 16U -static dma_descriptor_t dma_descriptors[2 * DISPLAY_DMA_NB_DESCS]; +static dma_descriptor_t dma_descriptors[FRAME_BUFFER_COUNT * DISPLAY_DMA_NB_DESCS]; #elif defined(__CC_ARM) -static dma_descriptor_t __attribute__((aligned(16U))) dma_descriptors[2 * DISPLAY_DMA_NB_DESCS]; +static dma_descriptor_t __attribute__((aligned(16U))) dma_descriptors[FRAME_BUFFER_COUNT * DISPLAY_DMA_NB_DESCS]; #elif defined(__GNUC__) -static dma_descriptor_t __attribute__((aligned(16U))) dma_descriptors[2 * DISPLAY_DMA_NB_DESCS]; +static dma_descriptor_t __attribute__((aligned(16U))) dma_descriptors[FRAME_BUFFER_COUNT * DISPLAY_DMA_NB_DESCS]; #endif #endif // DISPLAY_DMA_ENABLED != 0 @@ -74,6 +77,7 @@ static dma_descriptor_t __attribute__((aligned(16U))) dma_descriptors[2 * DISPLA // Internal function definitions // ----------------------------------------------------------------------------- +#if defined (DISPLAY_DMA_ENABLED) && (DISPLAY_DMA_ENABLED != 0) /* * @brief: Callback called when a DMA transfer is done * @@ -82,6 +86,21 @@ static dma_descriptor_t __attribute__((aligned(16U))) dma_descriptors[2 * DISPLA * @param[in] transfer_done: Flag indicating if the current transfer is done */ static void __dma_callback(dma_handle_t *handle, void *param, bool transfer_done, uint32_t tcds); +#endif // DISPLAY_DMA_ENABLED != 0 + +// ----------------------------------------------------------------------------- +// Low Level API [optional]: weak functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void DISPLAY_DMA_IMPL_notify_dma_start(void) { + // does nothing by default +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void DISPLAY_DMA_IMPL_notify_dma_stop(void) { + // does nothing by default +} // ----------------------------------------------------------------------------- // display_dma.h @@ -97,9 +116,9 @@ void DISPLAY_DMA_initialize(const framebuffer_t * framebuffers[]) { DMA_SetCallback(&g_DMA_Handle, __dma_callback, NULL); // Initialize the dma descriptors - for (int i = 0; i < 2; i++) { + for (int i = 0; i < FRAME_BUFFER_COUNT; i++) { framebuffer_t const * fb_src = framebuffers[i]; - framebuffer_t const * fb_dst = framebuffers[1-i]; + framebuffer_t const * fb_dst = framebuffers[(FRAME_BUFFER_COUNT == (i+1) ? 0 : (i+1))]; int offset = i*DISPLAY_DMA_NB_DESCS; int y; int d; @@ -107,12 +126,12 @@ void DISPLAY_DMA_initialize(const framebuffer_t * framebuffers[]) { d = offset; do { - y = DISPLAY_DMA_NB_LINES * (d - offset); - if (d >= (offset+(DISPLAY_DMA_NB_DESCS-1))) { break; } + y = DISPLAY_DMA_NB_LINES * (d - offset); + DMA_SetupDescriptor( &(dma_descriptors[d]), DMA_CHANNEL_XFER( @@ -181,7 +200,7 @@ void DISPLAY_DMA_start(framebuffer_t *src, framebuffer_t *dst, int ymin, int yma dma_descriptor_t *p_dma_desc; - DISPLAY_IMPL_notify_dma_start(); + DISPLAY_DMA_IMPL_notify_dma_start(); if (src == s_frameBufferAddress[1]) { p_dma_desc = &dma_descriptors[DISPLAY_DMA_NB_DESCS]; @@ -207,8 +226,11 @@ static void __dma_callback(dma_handle_t *handle, void *param, bool transfer_done if (transfer_done) { uint8_t it = interrupt_enter(); - LLUI_DISPLAY_flushDone(true); - DISPLAY_IMPL_notify_dma_stop(); + + // use the notification to let LLUI_DISPLAY_impl.c calls the right Grpahics Engine + // function according to the display buffer refresh strategy + DISPLAY_DMA_IMPL_notify_dma_stop(); + interrupt_leave(it); } } diff --git a/bsp/projects/microej/ui/src/display_framebuffer.c b/bsp/projects/microej/ui/src/display_framebuffer.c new file mode 100644 index 0000000..2375a21 --- /dev/null +++ b/bsp/projects/microej/ui/src/display_framebuffer.c @@ -0,0 +1,54 @@ +/* + * C + * + * Copyright 2020-2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief Implementation of MicroEJ MicroUI library low level API "LLUI_DISPLAY_impl.h" + * for the NXP MIMXRT595-EVK board. + * @author MicroEJ Developer Team + * @version 7.0.0 + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include "display_framebuffer.h" + +#include "fsl_dc_fb.h" + +// ----------------------------------------------------------------------------- +// Global Variables +// ----------------------------------------------------------------------------- + +_Pragma( "location = \"framebuffer0\"") static framebuffer_t s_frameBuffer0; +#define FRAME_BUFFER0_ADDR &s_frameBuffer0 + +#if defined (FRAME_BUFFER_COUNT) && (FRAME_BUFFER_COUNT > 1) +_Pragma( "location = \"framebuffer1\"") static framebuffer_t s_frameBuffer1; +#define FRAME_BUFFER1_ADDR &s_frameBuffer1 +#endif + +#if defined (FRAME_BUFFER_COUNT) && (FRAME_BUFFER_COUNT > 2) +_Pragma( "location = \"framebuffer2\"") static framebuffer_t s_frameBuffer2; +#define FRAME_BUFFER2_ADDR &s_frameBuffer2 +#endif + +// cppcheck-suppress [misra-c2012-9.3] array is fully initialized +const framebuffer_t * s_frameBufferAddress[FRAME_BUFFER_COUNT] = { + FRAME_BUFFER0_ADDR, +#if defined (FRAME_BUFFER_COUNT) && (FRAME_BUFFER_COUNT > 1) + FRAME_BUFFER1_ADDR, +#endif +#if defined (FRAME_BUFFER_COUNT) && (FRAME_BUFFER_COUNT > 2) + FRAME_BUFFER2_ADDR +#endif + }; + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_impl.c b/bsp/projects/microej/ui/src/display_impl.c similarity index 85% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_impl.c rename to bsp/projects/microej/ui/src/display_impl.c index dc226b4..4843247 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_impl.c +++ b/bsp/projects/microej/ui/src/display_impl.c @@ -1,133 +1,133 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @brief Implementation of "display_impl.h" - */ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include "display_impl.h" -#include "display_vglite.h" - -#include "fsl_debug_console.h" -#include "power_manager.h" -#include "trace_platform.h" -#include "event_generator.h" -#include "mej_log.h" - -#include - -// ----------------------------------------------------------------------------- -// Internal function definitions -// ----------------------------------------------------------------------------- - -/* - * @brief Special function that manages overlay and rendering mode. - * - * @param[in] params: contain which button is pressed when triggering the special function - */ -static void __vglite_special_function(void *params); - -// ----------------------------------------------------------------------------- -// display_impl.h functions -// ----------------------------------------------------------------------------- - -void DISPLAY_IMPL_initialized(void) { - - // registers callback to event generator to enable / disable hardware rendering - EVENT_GENERATOR_register_special_cb(__vglite_special_function, 0); -} - -void DISPLAY_IMPL_error(bool critical, const char* format, ...) { - va_list arg; - va_start (arg, format); - MEJ_LOG_PRINTF(format, arg); - va_end (arg); - while (critical){} -} - -void DISPLAY_IMPL_notify_gpu_start(void) { - power_manager_enable_low_power(POWER_GPU, LOW_POWER_FORBIDDEN); -} - -void DISPLAY_IMPL_notify_gpu_stop(void) { - power_manager_enable_low_power(POWER_GPU, LOW_POWER_AUTHORIZED); -} - -void DISPLAY_IMPL_notify_dma_start(void) { - power_manager_enable_low_power(POWER_DMA, LOW_POWER_FORBIDDEN); - - TRACE_HW_TASK_START(HW_TASK_DMA_ID); -} - -void DISPLAY_IMPL_notify_dma_stop(void) { - power_manager_enable_low_power(POWER_DMA, LOW_POWER_AUTHORIZED); - - // Request power_manager to power down this buffer - power_manager_framebuffer_request_power_off(); - - TRACE_HW_TASK_STOP(HW_TASK_DMA_ID); -} - -void DISPLAY_IMPL_update_frame_buffer_status(framebuffer_t* frame_buffer_on, framebuffer_t* frame_buffer_off) { - power_manager_framebuffer_power_on(frame_buffer_on); - power_manager_framebuffer_set_next_off(frame_buffer_off); -} - -// ----------------------------------------------------------------------------- -// NHardwareRendering functions -// ----------------------------------------------------------------------------- - -/* - * @brief Checks if hardware rendering is enabled - * - * @return true if hardware rendering is enabled, false otherwise - * Updates current Graphics Context with vglite's rendering area - */ -jboolean Java_com_microej_display_utils_NHardwareRendering_isEnabled(void) { - return DISPLAY_VGLITE_is_hardware_rendering_enabled(); -} - -/* - * @brief Checks if hardware rendering is disabled - * - * @return true if hardware rendering is disabled, false otherwise - */ -jboolean Java_com_microej_display_utils_NHardwareRendering_isDisabled(void) { - return !DISPLAY_VGLITE_is_hardware_rendering_enabled(); -} - -/* - * @brief Disables hardware rendering - */ -void Java_com_microej_display_utils_NHardwareRendering_disable(void) { - DISPLAY_VGLITE_disable_hardware_rendering(); -} - -/* - * @brief Enables hardware rendering - */ -void Java_com_microej_display_utils_NHardwareRendering_enable(void) { - DISPLAY_VGLITE_enable_hardware_rendering(); -} - -// ----------------------------------------------------------------------------- -// Internal functions -// ----------------------------------------------------------------------------- - -// See the section 'Internal function definitions' for the function documentation -static void __vglite_special_function(void *params) { - DISPLAY_VGLITE_toggle_hardware_rendering(); -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - +/* + * C + * + * Copyright 2022 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @brief Implementation of "display_impl.h" + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include "display_impl.h" + +#include "fsl_debug_console.h" +#include "power_manager.h" +#include "trace_platform.h" +#include "event_generator.h" +#include "mej_log.h" +#include "sni.h" + +#include + +// ----------------------------------------------------------------------------- +// Internal function definitions +// ----------------------------------------------------------------------------- + +/* + * @brief Special function that manages overlay and rendering mode. + * + * @param[in] params: contain which button is pressed when triggering the special function + */ +static void __vglite_special_function(void *params); + +// ----------------------------------------------------------------------------- +// display_impl.h functions +// ----------------------------------------------------------------------------- + +void DISPLAY_IMPL_initialized(void) { + + // registers callback to event generator to enable / disable hardware rendering + EVENT_GENERATOR_register_special_cb(__vglite_special_function, 0); +} + +void UI_VGLITE_IMPL_error(bool critical, const char* format, ...) { + va_list arg; + va_start (arg, format); + MEJ_LOG_PRINTF(format, arg); + va_end (arg); + while (critical){} +} + +void UI_VGLITE_IMPL_notify_gpu_start(void) { + power_manager_enable_low_power(POWER_GPU, LOW_POWER_FORBIDDEN); +} + +void UI_VGLITE_IMPL_notify_gpu_stop(void) { + power_manager_enable_low_power(POWER_GPU, LOW_POWER_AUTHORIZED); +} + +void DISPLAY_DMA_IMPL_notify_dma_start(void) { + power_manager_enable_low_power(POWER_DMA, LOW_POWER_FORBIDDEN); + + TRACE_HW_TASK_START(HW_TASK_DMA_ID); +} + +void DISPLAY_DMA_IMPL_notify_dma_stop(void) { + power_manager_enable_low_power(POWER_DMA, LOW_POWER_AUTHORIZED); + + // Request power_manager to power down this buffer + power_manager_framebuffer_request_power_off(); + + TRACE_HW_TASK_STOP(HW_TASK_DMA_ID); +} + +void DISPLAY_IMPL_update_frame_buffer_status(framebuffer_t* frame_buffer_on, framebuffer_t* frame_buffer_off) { + power_manager_framebuffer_power_on(frame_buffer_on); + power_manager_framebuffer_set_next_off(frame_buffer_off); +} + +// ----------------------------------------------------------------------------- +// NHardwareRendering functions +// ----------------------------------------------------------------------------- + +/* + * @brief Checks if hardware rendering is enabled + * + * @return true if hardware rendering is enabled, false otherwise + * Updates current Graphics Context with vglite's rendering area + */ +jboolean Java_com_microej_display_utils_NHardwareRendering_isEnabled(void) { + return UI_VGLITE_is_hardware_rendering_enabled(); +} + +/* + * @brief Checks if hardware rendering is disabled + * + * @return true if hardware rendering is disabled, false otherwise + */ +jboolean Java_com_microej_display_utils_NHardwareRendering_isDisabled(void) { + return !UI_VGLITE_is_hardware_rendering_enabled(); +} + +/* + * @brief Disables hardware rendering + */ +void Java_com_microej_display_utils_NHardwareRendering_disable(void) { + UI_VGLITE_disable_hardware_rendering(); +} + +/* + * @brief Enables hardware rendering + */ +void Java_com_microej_display_utils_NHardwareRendering_enable(void) { + UI_VGLITE_enable_hardware_rendering(); +} + +// ----------------------------------------------------------------------------- +// Internal functions +// ----------------------------------------------------------------------------- + +// See the section 'Internal function definitions' for the function documentation +static void __vglite_special_function(void *params) { + UI_VGLITE_toggle_hardware_rendering(); +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/event_generator.c b/bsp/projects/microej/ui/src/event_generator.c similarity index 93% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/event_generator.c rename to bsp/projects/microej/ui/src/event_generator.c index 89946ff..a5506a9 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/event_generator.c +++ b/bsp/projects/microej/ui/src/event_generator.c @@ -2,7 +2,8 @@ * C * * Copyright 2019-2021 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ /* diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/framerate.c b/bsp/projects/microej/ui/src/framerate.c similarity index 90% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/framerate.c rename to bsp/projects/microej/ui/src/framerate.c index c578076..680f4de 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/framerate.c +++ b/bsp/projects/microej/ui/src/framerate.c @@ -2,7 +2,8 @@ * C * * Copyright 2014-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ // ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/framerate_impl_FreeRTOS.c b/bsp/projects/microej/ui/src/framerate_impl_FreeRTOS.c similarity index 89% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/framerate_impl_FreeRTOS.c rename to bsp/projects/microej/ui/src/framerate_impl_FreeRTOS.c index 0b22090..c1259ee 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/framerate_impl_FreeRTOS.c +++ b/bsp/projects/microej/ui/src/framerate_impl_FreeRTOS.c @@ -2,7 +2,8 @@ * C * * Copyright 2015-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ /* diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/microui_event_decoder.c b/bsp/projects/microej/ui/src/microui_event_decoder.c similarity index 94% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/microui_event_decoder.c rename to bsp/projects/microej/ui/src/microui_event_decoder.c index 28953c3..2c3332d 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/microui_event_decoder.c +++ b/bsp/projects/microej/ui/src/microui_event_decoder.c @@ -1,7 +1,7 @@ /* * C * - * Copyright 2021-2022 MicroEJ Corp. All rights reserved. + * Copyright 2021-2024 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -12,8 +12,7 @@ * * @see LLUI_INPUT_LOG_impl.c file comment * @author MicroEJ Developer Team - * @version 2.0.0 - * @date 22 July 2022 + * @version 4.0.1 * @since MicroEJ UI Pack 13.1.0 */ @@ -24,10 +23,6 @@ // calls Microui events decoder functions #include "microui_event_decoder.h" -#ifdef __cplusplus -extern "C" { -#endif - #ifdef MICROUIEVENTDECODER_ENABLED // ----------------------------------------------------------------------------- @@ -314,6 +309,7 @@ static void decode_event_user_data(uint32_t event, uint32_t data, uint32_t index } static void decode_event_user(uint32_t event, uint32_t index, MICROUI_EVENT_DECODER_decode_event_data* fct_data_decoder) { + (void)index; LLUI_DEBUG_TRACE("User input event"); uint8_t size = (uint8_t)USEREVENT_SIZE(event); @@ -421,6 +417,3 @@ void MICROUI_EVENT_DECODER_decode_event(uint32_t event, uint32_t index, MICROUI_ // EOF // ----------------------------------------------------------------------------- -#ifdef __cplusplus -} -#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/touch_helper.c b/bsp/projects/microej/ui/src/touch_helper.c similarity index 92% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/touch_helper.c rename to bsp/projects/microej/ui/src/touch_helper.c index c7689e6..0ed3bc7 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/touch_helper.c +++ b/bsp/projects/microej/ui/src/touch_helper.c @@ -2,7 +2,8 @@ * C * * Copyright 2015-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ /* diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/touch_manager.c b/bsp/projects/microej/ui/src/touch_manager.c similarity index 91% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/touch_manager.c rename to bsp/projects/microej/ui/src/touch_manager.c index af59a42..9a9d267 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/touch_manager.c +++ b/bsp/projects/microej/ui/src/touch_manager.c @@ -1,11 +1,9 @@ /* - * C + * C * - * Copyright 2019-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - * - * Copyright 2023 NXP - * SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019-2020 MicroEJ Corp. All rights reserved. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ // ----------------------------------------------------------------------------- @@ -168,7 +166,7 @@ static void __touch_manager_task(void *pvParameters) while (1) { /* Suspend ourselves */ - (void)xSemaphoreTake(touch_interrupt_sem, portMAX_DELAY); + xSemaphoreTake(touch_interrupt_sem, portMAX_DELAY); /* We have been woken up, lets work ! */ __touch_manager_read(); diff --git a/bsp/projects/microej/ui/src/ui_display_brs.c b/bsp/projects/microej/ui/src/ui_display_brs.c new file mode 100644 index 0000000..13572a5 --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_display_brs.c @@ -0,0 +1,77 @@ + +/* + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief This file implements is the common part of all display buffer strategies (BRS). + * @author MicroEJ Developer Team + * @version 4.0.1 + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include + +#include "ui_display_brs.h" +#include "bsp_util.h" +#include "ui_drawing.h" + +// -------------------------------------------------------------------------------- +// ui_display_brs.h API +// -------------------------------------------------------------------------------- + +/* + * @brief Provides a simple implementation of the restore: use memcpy(). + * See the header file for the function documentation + */ +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DISPLAY_BRS_restore(MICROUI_GraphicsContext* gc, MICROUI_Image* old_back_buffer, ui_rect_t* rect) { + + DRAWING_Status ret; + uint32_t bpp = LLUI_DISPLAY_getImageBPP(old_back_buffer); + uint32_t width = UI_RECT_get_width(rect); + uint32_t height = UI_RECT_get_height(rect); + + if (8u > bpp) { + // this weak function is not designed to target this kind of buffer + // -> let the standard function copyImage() performing the job + ret = UI_DRAWING_copyImage(gc, old_back_buffer, rect->x1, rect->y1, width, height, rect->x1, rect->y1); + } + else { + + uint8_t* dst = LLUI_DISPLAY_getBufferAddress(&gc->image); + uint8_t* src = LLUI_DISPLAY_getBufferAddress(old_back_buffer); + uint32_t stride = LLUI_DISPLAY_getStrideInBytes(&gc->image); + + dst += rect->y1 * stride; + src += rect->y1 * stride; + + if ((0 == rect->x1) && (old_back_buffer->width == width)) { + // a simple memcpy is required! + (void)memcpy(dst, src, stride * height); + } + else { + // have to perform one memcpy per line + dst += rect->x1 * bpp / 8u; + src += rect->x1 * bpp / 8u; + uint32_t size = width * bpp / 8u; + + for (uint32_t y = 0; y < height; y++) { + (void)memcpy(dst, src, size); + dst += stride; + src += stride; + } + } + + ret = DRAWING_DONE; + } + return ret; +} + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- diff --git a/bsp/projects/microej/ui/src/ui_display_brs_legacy.c b/bsp/projects/microej/ui/src/ui_display_brs_legacy.c new file mode 100644 index 0000000..3f5cb89 --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_display_brs_legacy.c @@ -0,0 +1,64 @@ + +/* + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief This file implements all the LLUI_DISPLAY_impl.h functions relating to the + * display buffer strategy (BRS) "legacy" + * @see UI_DISPLAY_BRS_LEGACY comment + * @author MicroEJ Developer Team + * @version 4.0.1 + */ + +#include "ui_display_brs.h" +#if defined UI_DISPLAY_BRS && UI_DISPLAY_BRS == UI_DISPLAY_BRS_LEGACY + +// -------------------------------------------------------------------------------- +// Private fields +// -------------------------------------------------------------------------------- + +static ui_rect_t flush_bounds = { + .x1 = INT16_MAX, + .y1 = INT16_MAX, + .x2 = 0, + .y2 = 0, +}; + +// -------------------------------------------------------------------------------- +// LLUI_DISPLAY_impl.h API +// -------------------------------------------------------------------------------- + +// See the header file for the function documentation +DRAWING_Status LLUI_DISPLAY_IMPL_newDrawingRegion(MICROUI_GraphicsContext* gc, ui_rect_t* region, bool drawing_now) { + (void)gc; + (void)drawing_now; + flush_bounds.x1 = MIN(flush_bounds.x1, region->x1); + flush_bounds.y1 = MIN(flush_bounds.y1, region->y1); + flush_bounds.x2 = MAX(flush_bounds.x2, region->x2); + flush_bounds.y2 = MAX(flush_bounds.y2, region->y2); + return DRAWING_DONE; +} + +DRAWING_Status LLUI_DISPLAY_IMPL_refresh(MICROUI_GraphicsContext* gc, uint8_t flushIdentifier) { + + LLTRACE_record_event_u32x6(LLUI_EVENT_group, LLUI_EVENT_offset + UI_LOG_BRS_FlushSingle, flushIdentifier, (uint32_t)LLUI_DISPLAY_getBufferAddress(&gc->image), flush_bounds.x1, flush_bounds.y1, flush_bounds.x2, flush_bounds.y2); + + LLUI_DISPLAY_IMPL_flush(gc, flushIdentifier, &flush_bounds, 1); + + // reset flush bounds to no flush again if there is no drawing until next flush + flush_bounds.x1 = INT16_MAX; + flush_bounds.y1 = INT16_MAX; + flush_bounds.x2 = 0; + flush_bounds.y2 = 0; + + return DRAWING_DONE; +} + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#endif // UI_DISPLAY_BRS_LEGACY diff --git a/bsp/projects/microej/ui/src/ui_display_brs_predraw.c b/bsp/projects/microej/ui/src/ui_display_brs_predraw.c new file mode 100644 index 0000000..1ed7a34 --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_display_brs_predraw.c @@ -0,0 +1,348 @@ + +/* + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief This file implements all the LLUI_DISPLAY_impl.h functions relating to the + * display buffer strategy (BRS) "pre draw" + * @see UI_DISPLAY_BRS_PREDRAW comment + * @author MicroEJ Developer Team + * @version 4.0.1 + */ + +#include "ui_display_brs.h" +#if defined UI_DISPLAY_BRS && UI_DISPLAY_BRS == UI_DISPLAY_BRS_PREDRAW + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include "ui_rect_collection.h" +#include "ui_rect_util.h" + +// -------------------------------------------------------------------------------- +// Defines +// -------------------------------------------------------------------------------- + +/* + * @brief This strategy requires the available number of back buffers. + * @see the comment of UI_DISPLAY_BRS_PREDRAW. + */ +#ifndef UI_DISPLAY_BRS_DRAWING_BUFFER_COUNT +#error "Require the available number of display buffers (back and front buffers)." +#elif UI_DISPLAY_BRS_DRAWING_BUFFER_COUNT < 2 +#warning "This strategy is not optimized for less than two buffers." +#endif + +// -------------------------------------------------------------------------------- +// Private fields +// -------------------------------------------------------------------------------- + +/* + * @brief A collection of dirty regions is kept for each back buffers. + */ +#if UI_DISPLAY_BRS_DRAWING_BUFFER_COUNT > 1u +static ui_rect_collection_t dirty_regions[UI_DISPLAY_BRS_DRAWING_BUFFER_COUNT - 1u] = {0}; +#else +static ui_rect_collection_t dirty_regions[1u] = {0}; +#endif + +/* + * @brief Index of the back buffer's collection to restore in the new back buffer. + */ +static uint32_t index_dirty_region_to_restore = 0; + +static bool backbuffer_ready = true; + +ui_rect_t diff[4] = { UI_RECT_EMPTY, UI_RECT_EMPTY, UI_RECT_EMPTY, UI_RECT_EMPTY } ; + +#ifdef UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + +/* + * @brief Rectangle given to LLUI_DISPLAY_IMPL_flush(): it includes all dirty regions since + * last call to flush(). + */ +static ui_rect_t flush_bounds = { + .x1 = INT16_MAX, + .y1 = INT16_MAX, + .x2 = 0, + .y2 = 0, +}; + +#endif // UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + +// -------------------------------------------------------------------------------- +// Private functions +// -------------------------------------------------------------------------------- + +/* + * This function removes all regions saved in the next collection to restore in the + * new back buffer if they are included in the new region. + */ +static void _remove_drawing_regions(MICROUI_GraphicsContext* gc, ui_rect_t* region) { + (void)gc; + + for(uint32_t i = 0u; i < (UI_DISPLAY_BRS_DRAWING_BUFFER_COUNT - 1u); i++) { + ui_rect_t* r = dirty_regions[i].data; + while (r != UI_RECT_COLLECTION_get_end(&dirty_regions[i])) { + if (!UI_RECT_is_empty(r) && UI_RECT_contains_rect(region, r)) { + // this region will be re-drawn: remove it from the restoration array + LOG_REGION(UI_LOG_BRS_RemoveRegion, r); + UI_RECT_mark_empty(r); + } + r++; + } + } +} + +/* + * This function adds the region to the regions to restore. + */ +static void _add_drawing_region(MICROUI_GraphicsContext* gc, ui_rect_t* region) { + + for(uint32_t i = 0u; i < (UI_DISPLAY_BRS_DRAWING_BUFFER_COUNT - 1u); i++) { + ui_rect_t* previous = UI_RECT_COLLECTION_get_last(&dirty_regions[i]); + if ((NULL == previous) || !UI_RECT_contains_rect(previous, region)){ + // add the dirty region if and only if previous dirty region does not + // include the new dirty region + ui_rect_t new_region; + if (!UI_RECT_COLLECTION_is_full(&dirty_regions[i])) { + new_region = *region; + } + else { + // too many rectangles: replace them by only one whose fits the full display + LLTRACE_record_event_void(LLUI_EVENT_group, LLUI_EVENT_offset + UI_LOG_BRS_ClearList); + UI_RECT_COLLECTION_clear(&dirty_regions[i]); + new_region = UI_RECT_new_xyxy(0, 0, gc->image.width - 1, gc->image.height - 1); + } + LOG_REGION(UI_LOG_BRS_AddRegion, &new_region); + UI_RECT_COLLECTION_add_rect(&dirty_regions[i], new_region); + } + } + +#ifdef UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + flush_bounds.x1 = MIN(flush_bounds.x1, region->x1); + flush_bounds.y1 = MIN(flush_bounds.y1, region->y1); + flush_bounds.x2 = MAX(flush_bounds.x2, region->x2); + flush_bounds.y2 = MAX(flush_bounds.y2, region->y2); +#endif // UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE +} + +/* + * @brief Checks if the past has to be restored and if the collection that represents + * the past has to be cleared. + * + * The past may be not restored if the new drawing region includes the past (no need to + * restore) or if the current back buffer is the same buffer than before last flush() + * (because it already contains the past). + * + * @param[in] gc the MicroUI GraphicsContext that targets the current back buffer + * @param[in] dirty_region the region of the next drawing. + * @param[out] clear_past true if the caller has to clear the past collection. + * @return true if the past has to be restored. + */ +static bool _check_restore(MICROUI_GraphicsContext* gc, ui_rect_t* dirty_region, bool* clear_past) { + + bool restore; + *clear_past = false; + + if (!UI_RECT_COLLECTION_is_empty(&dirty_regions[index_dirty_region_to_restore])) { + // remains something to restore + restore = true; + + if (!UI_RECT_is_empty(dirty_regions[index_dirty_region_to_restore].data)) { + // very first call after a flush (not a SNI callback) + + if (LLUI_DISPLAY_getBufferAddress(LLUI_DISPLAY_getSourceImage(&gc->image)) != LLUI_DISPLAY_getBufferAddress(&gc->image)) { + // target a new buffer + + if ((dirty_region->x1 == 0) && (dirty_region->y1 == 0) && (dirty_region->x2 == (gc->image.width - 1)) && (dirty_region->y2 == (gc->image.height - 1))) { + // new dirty region fits the full screen; the "past" is useless + *clear_past = true; + restore = false; + } + } + else { + // target the same buffer: restore is useless and just add the new dirty region (do not clear the past) + restore = false; + } + } + // else: continue the restore + } + else { + // nothing to restore + restore = false; + } + return restore; +} + +/* + * @brief Restores the rectangles stored in the array of 4 rectangles (a region previously splitted in four + * rectangles). + * + * @param[in] gc the MicroUI GraphicsContext that targets the current back buffer + * @param[in] previous_buffer the MicroUI Image that targets the current front buffer + * @return DRAWING_RUNNING if the a restoration is step is running or DRAWING_DONE if the restoration + * is fully completed. + */ +static DRAWING_Status _restore_sub_rect(MICROUI_GraphicsContext* gc, MICROUI_Image* previous_buffer) { + DRAWING_Status restore_status = DRAWING_DONE; + int ri = 0; + do { + ui_rect_t* r = &diff[ri]; + if (!UI_RECT_is_empty(r)) { + LOG_REGION(UI_LOG_BRS_RestoreRegion, r); + restore_status = UI_DISPLAY_BRS_restore(gc, previous_buffer, r); + UI_RECT_mark_empty(r); + } + ri++; + } while((DRAWING_DONE == restore_status) && (ri < 4)); + return restore_status; +} + +/* + * @brief Prepares the back buffer before the very first drawing, which consists to + * restore the past if it is required (see _check_restore()). + * + * The restoration steps are symbolized by a collection of rectangles. The restoration + * of one rectangle might be asynchronous. In that case, this function launches a + * restoration step and returns false. The complete restoration will be completed + * until this function returns true. + * + * @param[in] gc the MicroUI GraphicsContext that targets the current back buffer + * @param[in] dirty_region the region of the next drawing. + * @return DRAWING_RUNNING if the a restoration is step is running or DRAWING_DONE if the restoration + * is fully completed and the region added as region to restore + */ +static DRAWING_Status _prepare_back_buffer(MICROUI_GraphicsContext* gc, ui_rect_t* dirty_region) { + + DRAWING_Status restore_status = DRAWING_DONE; + bool clear_past = false; + + if (_check_restore(gc, dirty_region, &clear_past)) { + MICROUI_Image* previous_buffer = LLUI_DISPLAY_getSourceImage(&gc->image); + LLUI_DISPLAY_configureClip(gc, false); // regions to restore can be fully out of clip + + // restore sub parts of previous restoration (if any) + restore_status = _restore_sub_rect(gc, previous_buffer); + + if (DRAWING_DONE == restore_status) { + ui_rect_t* r = dirty_regions[index_dirty_region_to_restore].data; + while ((DRAWING_DONE == restore_status) && (r != UI_RECT_COLLECTION_get_end(&dirty_regions[index_dirty_region_to_restore]))) { + if (!UI_RECT_is_empty(r)) { + + // split (if required) the current region in sub-parts + if (0u < UI_RECT_subtract(diff, r, dirty_region)) { + // restore sub-part(s) + restore_status = _restore_sub_rect(gc, previous_buffer); + } + + // current region is now restored or is currently in restore (thanks to array of sub-parts) + UI_RECT_mark_empty(r); + } + r++; + } + + // do not clear the past if a restoration step is running + clear_past = DRAWING_DONE == restore_status; + } + // else: the restoration of a sub-part is running + } + + if (clear_past) { + UI_RECT_COLLECTION_clear(&dirty_regions[index_dirty_region_to_restore]); +#if UI_DISPLAY_BRS_DRAWING_BUFFER_COUNT > 1 + index_dirty_region_to_restore++; + index_dirty_region_to_restore %= (uint32_t) UI_DISPLAY_BRS_DRAWING_BUFFER_COUNT - 1u; +#endif + } + + if (DRAWING_DONE == restore_status) { + // back buffer is considered as ready when it is fully restored + backbuffer_ready = true; + + // add the new region as a region to restore + _add_drawing_region(gc, dirty_region); + } + + return restore_status; +} + +// -------------------------------------------------------------------------------- +// LLUI_DISPLAY_impl.h API +// -------------------------------------------------------------------------------- +/* + * @brief See the header file for the function documentation. + * + * This function restores the back buffer if required and store the new region as new + * region to restore after next call to flush(). + */ +DRAWING_Status LLUI_DISPLAY_IMPL_newDrawingRegion(MICROUI_GraphicsContext* gc, ui_rect_t* region, bool drawing_now) { + + LOG_REGION(UI_LOG_BRS_NewDrawing, region); + + DRAWING_Status ret = DRAWING_DONE; + + if (!backbuffer_ready) { + + if (!drawing_now) { + _remove_drawing_regions(gc, region); + } + else { + ret = _prepare_back_buffer(gc, region); + } + } + else { + _add_drawing_region(gc, region); // don't care if drawing now or not + } + + return ret; +} + +/* + * @brief See the header file for the function documentation. + * + * This function calls LLUI_DISPLAY_IMPL_flush() with the rectangle that includes all dirty regions. + */ +DRAWING_Status LLUI_DISPLAY_IMPL_refresh(MICROUI_GraphicsContext* gc, uint8_t flushIdentifier) { + +#ifdef UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + + LLTRACE_record_event_u32x6(LLUI_EVENT_group, LLUI_EVENT_offset + UI_LOG_BRS_FlushSingle, flushIdentifier, (uint32_t)LLUI_DISPLAY_getBufferAddress(&gc->image), flush_bounds.x1, flush_bounds.y1, flush_bounds.x2, flush_bounds.y2); + + // refresh the LCD; use the flush_bounds as dirty region (includes all dirty regions) + LLUI_DISPLAY_IMPL_flush(gc, flushIdentifier, &flush_bounds, 1); + + // reset flush bounds to no flush again if there is no drawing until next flush + flush_bounds.x1 = INT16_MAX; + flush_bounds.y1 = INT16_MAX; + flush_bounds.x2 = 0; + flush_bounds.y2 = 0; + +#else // UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + + size_t size = UI_RECT_COLLECTION_get_length(&dirty_regions[index_dirty_region_to_restore]); + if (1u == size) { + ui_rect_t* rect = &dirty_regions[index_dirty_region_to_restore].data[0]; + LLTRACE_record_event_u32x6(LLUI_EVENT_group, LLUI_EVENT_offset + UI_LOG_BRS_FlushSingle, flushIdentifier, (uint32_t)LLUI_DISPLAY_getBufferAddress(&gc->image), rect->x1, rect->y1, rect->x2, rect->y2); + } + else { + LLTRACE_record_event_u32x3(LLUI_EVENT_group, LLUI_EVENT_offset + UI_LOG_BRS_FlushMulti, flushIdentifier, (uint32_t)LLUI_DISPLAY_getBufferAddress(&gc->image), size); + } + + LLUI_DISPLAY_IMPL_flush(gc, flushIdentifier, dirty_regions[index_dirty_region_to_restore].data, UI_RECT_COLLECTION_get_length(&dirty_regions[index_dirty_region_to_restore])); + +#endif // UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + + backbuffer_ready = false; + return DRAWING_DONE; +} + +#endif // UI_DISPLAY_BRS_PREDRAW + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- diff --git a/bsp/projects/microej/ui/src/ui_display_brs_single.c b/bsp/projects/microej/ui/src/ui_display_brs_single.c new file mode 100644 index 0000000..b4605cf --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_display_brs_single.c @@ -0,0 +1,152 @@ + +/* + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief This file implements all the LLUI_DISPLAY_impl.h functions relating to the + * display buffer strategy (BRS) "single" + * @see UI_DISPLAY_BRS_SINGLE comment + * @author MicroEJ Developer Team + * @version 4.0.1 + */ + +#include "ui_display_brs.h" +#if defined UI_DISPLAY_BRS && UI_DISPLAY_BRS == UI_DISPLAY_BRS_SINGLE + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include "ui_rect_collection.h" + +// -------------------------------------------------------------------------------- +// Defines +// -------------------------------------------------------------------------------- + +/* + * @brief This strategy uses only one buffer + * @see the comment of UI_DISPLAY_BRS_SINGLE. + */ +#if defined UI_DISPLAY_BRS_DRAWING_BUFFER_COUNT && UI_DISPLAY_BRS_DRAWING_BUFFER_COUNT != 1 +#error "This strategy uses always the same back buffer." +#endif + +// -------------------------------------------------------------------------------- +// Private fields +// -------------------------------------------------------------------------------- + +#ifndef UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + +/* + * @brief A collection of rectangles to transmit to the LCD + */ +static ui_rect_collection_t dirty_regions; + +#else // UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + +/* + * @brief Rectangle given to LLUI_DISPLAY_IMPL_flush(): it includes all dirty regions since + * last call to flush(). + */ +static ui_rect_t flush_bounds = { + .x1 = INT16_MAX, + .y1 = INT16_MAX, + .x2 = 0, + .y2 = 0, +}; + +#endif // UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + +// -------------------------------------------------------------------------------- +// LLUI_DISPLAY_impl.h API +// -------------------------------------------------------------------------------- + +/* + * @brief See the header file for the function documentation. + * + * This function stores the new region as new region to transmit to the LCD at next call to flush(). + */ +DRAWING_Status LLUI_DISPLAY_IMPL_newDrawingRegion(MICROUI_GraphicsContext* gc, ui_rect_t* region, bool drawing_now) { + (void)drawing_now; + + LOG_REGION(UI_LOG_BRS_NewDrawing, region); + +#ifndef UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + + ui_rect_t* previous = UI_RECT_COLLECTION_get_last(&dirty_regions); + if ((NULL == previous) || !UI_RECT_contains_rect(previous, region)){ + // add the dirty region if and only if previous dirty region does not + // include the new dirty region + ui_rect_t new_region; + if (!UI_RECT_COLLECTION_is_full(&dirty_regions)) { + new_region = *region; + } + else { + // too many rectangles: replace them by only one whose fits the full display + LLTRACE_record_event_void(LLUI_EVENT_group, LLUI_EVENT_offset + UI_LOG_BRS_ClearList); + UI_RECT_COLLECTION_clear(&dirty_regions); + new_region = UI_RECT_new_xyxy(0, 0, gc->image.width - 1, gc->image.height - 1); + } + LOG_REGION(UI_LOG_BRS_AddRegion, &new_region); + UI_RECT_COLLECTION_add_rect(&dirty_regions, new_region); + } +#else // UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + (void)gc; + + flush_bounds.x1 = MIN(flush_bounds.x1, region->x1); + flush_bounds.y1 = MIN(flush_bounds.y1, region->y1); + flush_bounds.x2 = MAX(flush_bounds.x2, region->x2); + flush_bounds.y2 = MAX(flush_bounds.y2, region->y2); + +#endif // UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + + return DRAWING_DONE; +} + +/* + * @brief See the header file for the function documentation. + * + * This function calls LLUI_DISPLAY_IMPL_flush() with the rectangle that includes all dirty regions. + */ +DRAWING_Status LLUI_DISPLAY_IMPL_refresh(MICROUI_GraphicsContext* gc, uint8_t flushIdentifier) { + +#ifndef UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + + size_t size = UI_RECT_COLLECTION_get_length(&dirty_regions); + if (1u == size) { + ui_rect_t* rect = &dirty_regions.data[0]; + LLTRACE_record_event_u32x6(LLUI_EVENT_group, LLUI_EVENT_offset + UI_LOG_BRS_FlushSingle, flushIdentifier, (uint32_t)LLUI_DISPLAY_getBufferAddress(&gc->image), rect->x1, rect->y1, rect->x2, rect->y2); + } + else { + LLTRACE_record_event_u32x3(LLUI_EVENT_group, LLUI_EVENT_offset + UI_LOG_BRS_FlushMulti, flushIdentifier, (uint32_t)LLUI_DISPLAY_getBufferAddress(&gc->image), size); + } + + LLUI_DISPLAY_IMPL_flush(gc, flushIdentifier, dirty_regions.data, UI_RECT_COLLECTION_get_length(&dirty_regions)); + UI_RECT_COLLECTION_clear(&dirty_regions); + +#else // UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + + LLTRACE_record_event_u32x6(LLUI_EVENT_group, LLUI_EVENT_offset + UI_LOG_BRS_FlushSingle, flushIdentifier, (uint32_t)LLUI_DISPLAY_getBufferAddress(&gc->image), flush_bounds.x1, flush_bounds.y1, flush_bounds.x2, flush_bounds.y2); + + // refresh the LCD; use the flush_bounds as dirty region (includes all dirty regions) + LLUI_DISPLAY_IMPL_flush(gc, flushIdentifier, &flush_bounds, 1); + + // reset flush bounds to no flush again if there is no drawing until next flush + flush_bounds.x1 = INT16_MAX; + flush_bounds.y1 = INT16_MAX; + flush_bounds.x2 = 0; + flush_bounds.y2 = 0; + +#endif // UI_DISPLAY_BRS_FLUSH_SINGLE_RECTANGLE + + return DRAWING_DONE; +} + +#endif // UI_DISPLAY_BRS_PREDRAW + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- diff --git a/bsp/projects/microej/ui/src/ui_drawing.c b/bsp/projects/microej/ui/src/ui_drawing.c new file mode 100644 index 0000000..f82f394 --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_drawing.c @@ -0,0 +1,1635 @@ +/* + * C + * + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief Redirection of all MicroUI and Drawing libraries drawing functions. This file + * is required (must be compiled in the C project) but should not be modified (except when + * the VEE port uses more than 3 destination formats, see below). + * + * According to the available number of destination formats, this file redirects all drawings + * to the Graphics Engine software algorithms or uses some tables to target the right drawer + * according to the destination format. + * + * When only one destination format is available and no hardware acceleration (GPU) is + * available, the C compiler must just include this file. The default weak implementations + * call the Graphics Engine sofware algorithms. + * + * When only one destination format is available and a hardware acceleration (GPU) is + * available, a custom implementation over the GPU must override a set of these default + * weak implementations (function UI_DRAWING_xxx()). This allows to override only a set + * of functions which are GPU compatible. + * + * When several destination formats are available, this file uses some tables to target + * the right drawer. Each drawer (that targets a specific destination format) has to + * specify the table index and has to override a maximum of drawing functions. When a + * function is not overridden for a given destination format, the default weak implementation + * is used. This implementation uses the stub implementation. + * + * The BSP should specify the define "LLUI_GC_SUPPORTED_FORMATS". When not set or smaller than + * "2", this file considers only one destination format is available: the same format than + * the buffer of the display. + * + * When this define is "2" or "3", this file uses the tables indirections. The format "0" is + * reserved for the display buffer format (and for the GraphicsContext that uses the same + * format). The formats "1" and "2" are specific to the VEE Port. + * + * This file does not manages more than 3 destination formats ("0" == display buffer format + * and custom formats "1" and "2"). However the file can be easily modified to target more + * than 3 destination formats. See format "2" support and apply same patterns to add the + * format "3". + * + * @author MicroEJ Developer Team + * @version 4.0.1 + * @see ui_drawing.h + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include + +#include "ui_drawing.h" +#include "ui_drawing_stub.h" +#include "ui_drawing_soft.h" +#include "dw_drawing_soft.h" +#include "ui_image_drawing.h" +#include "bsp_util.h" + +// -------------------------------------------------------------------------------- +// Defines +// -------------------------------------------------------------------------------- + +#if !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +/* + * The functions UI_DRAWING_DEFAULT_xxx() are directly called by LLUI_DISPLAY_impl.c, + * LLUI_PAINTER_impl.c and LLDW_PAINTER_impl.c. Other files can override each weak + * function independently to use a GPU. + */ + +#define UI_DRAWING_DEFAULT_writePixel UI_DRAWING_writePixel +#define UI_DRAWING_DEFAULT_drawLine UI_DRAWING_drawLine +#define UI_DRAWING_DEFAULT_drawHorizontalLine UI_DRAWING_drawHorizontalLine +#define UI_DRAWING_DEFAULT_drawVerticalLine UI_DRAWING_drawVerticalLine +#define UI_DRAWING_DEFAULT_drawRectangle UI_DRAWING_drawRectangle +#define UI_DRAWING_DEFAULT_fillRectangle UI_DRAWING_fillRectangle +#define UI_DRAWING_DEFAULT_drawRoundedRectangle UI_DRAWING_drawRoundedRectangle +#define UI_DRAWING_DEFAULT_fillRoundedRectangle UI_DRAWING_fillRoundedRectangle +#define UI_DRAWING_DEFAULT_drawCircleArc UI_DRAWING_drawCircleArc +#define UI_DRAWING_DEFAULT_drawEllipseArc UI_DRAWING_drawEllipseArc +#define UI_DRAWING_DEFAULT_fillCircleArc UI_DRAWING_fillCircleArc +#define UI_DRAWING_DEFAULT_fillEllipseArc UI_DRAWING_fillEllipseArc +#define UI_DRAWING_DEFAULT_drawEllipse UI_DRAWING_drawEllipse +#define UI_DRAWING_DEFAULT_fillEllipse UI_DRAWING_fillEllipse +#define UI_DRAWING_DEFAULT_drawCircle UI_DRAWING_drawCircle +#define UI_DRAWING_DEFAULT_fillCircle UI_DRAWING_fillCircle +#define UI_DRAWING_DEFAULT_drawImage UI_DRAWING_drawImage +#define UI_DRAWING_DEFAULT_copyImage UI_DRAWING_copyImage +#define UI_DRAWING_DEFAULT_drawRegion UI_DRAWING_drawRegion + +#define UI_DRAWING_DEFAULT_drawThickFadedPoint UI_DRAWING_drawThickFadedPoint +#define UI_DRAWING_DEFAULT_drawThickFadedLine UI_DRAWING_drawThickFadedLine +#define UI_DRAWING_DEFAULT_drawThickFadedCircle UI_DRAWING_drawThickFadedCircle +#define UI_DRAWING_DEFAULT_drawThickFadedCircleArc UI_DRAWING_drawThickFadedCircleArc +#define UI_DRAWING_DEFAULT_drawThickFadedEllipse UI_DRAWING_drawThickFadedEllipse +#define UI_DRAWING_DEFAULT_drawThickLine UI_DRAWING_drawThickLine +#define UI_DRAWING_DEFAULT_drawThickCircle UI_DRAWING_drawThickCircle +#define UI_DRAWING_DEFAULT_drawThickEllipse UI_DRAWING_drawThickEllipse +#define UI_DRAWING_DEFAULT_drawThickCircleArc UI_DRAWING_drawThickCircleArc +#define UI_DRAWING_DEFAULT_drawFlippedImage UI_DRAWING_drawFlippedImage +#define UI_DRAWING_DEFAULT_drawRotatedImageNearestNeighbor UI_DRAWING_drawRotatedImageNearestNeighbor +#define UI_DRAWING_DEFAULT_drawRotatedImageBilinear UI_DRAWING_drawRotatedImageBilinear +#define UI_DRAWING_DEFAULT_drawScaledImageNearestNeighbor UI_DRAWING_drawScaledImageNearestNeighbor +#define UI_DRAWING_DEFAULT_drawScaledImageBilinear UI_DRAWING_drawScaledImageBilinear + +#else // !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +/* + * The functions UI_DRAWING_DEFAULT_xxx() are indirectly called through some tables. + * The functions have got the identifier "0" as suffix. Another file can override + * each weak function independently to use a GPU. + */ + +#define UI_DRAWING_DEFAULT_writePixel UI_DRAWING_writePixel_0 +#define UI_DRAWING_DEFAULT_drawLine UI_DRAWING_drawLine_0 +#define UI_DRAWING_DEFAULT_drawHorizontalLine UI_DRAWING_drawHorizontalLine_0 +#define UI_DRAWING_DEFAULT_drawVerticalLine UI_DRAWING_drawVerticalLine_0 +#define UI_DRAWING_DEFAULT_drawRectangle UI_DRAWING_drawRectangle_0 +#define UI_DRAWING_DEFAULT_fillRectangle UI_DRAWING_fillRectangle_0 +#define UI_DRAWING_DEFAULT_drawRoundedRectangle UI_DRAWING_drawRoundedRectangle_0 +#define UI_DRAWING_DEFAULT_fillRoundedRectangle UI_DRAWING_fillRoundedRectangle_0 +#define UI_DRAWING_DEFAULT_drawCircleArc UI_DRAWING_drawCircleArc_0 +#define UI_DRAWING_DEFAULT_drawEllipseArc UI_DRAWING_drawEllipseArc_0 +#define UI_DRAWING_DEFAULT_fillCircleArc UI_DRAWING_fillCircleArc_0 +#define UI_DRAWING_DEFAULT_fillEllipseArc UI_DRAWING_fillEllipseArc_0 +#define UI_DRAWING_DEFAULT_drawEllipse UI_DRAWING_drawEllipse_0 +#define UI_DRAWING_DEFAULT_fillEllipse UI_DRAWING_fillEllipse_0 +#define UI_DRAWING_DEFAULT_drawCircle UI_DRAWING_drawCircle_0 +#define UI_DRAWING_DEFAULT_fillCircle UI_DRAWING_fillCircle_0 +#define UI_DRAWING_DEFAULT_drawImage UI_DRAWING_drawImage_0 +#define UI_DRAWING_DEFAULT_copyImage UI_DRAWING_copyImage_0 +#define UI_DRAWING_DEFAULT_drawRegion UI_DRAWING_drawRegion_0 + +#define UI_DRAWING_DEFAULT_drawThickFadedPoint UI_DRAWING_drawThickFadedPoint_0 +#define UI_DRAWING_DEFAULT_drawThickFadedLine UI_DRAWING_drawThickFadedLine_0 +#define UI_DRAWING_DEFAULT_drawThickFadedCircle UI_DRAWING_drawThickFadedCircle_0 +#define UI_DRAWING_DEFAULT_drawThickFadedCircleArc UI_DRAWING_drawThickFadedCircleArc_0 +#define UI_DRAWING_DEFAULT_drawThickFadedEllipse UI_DRAWING_drawThickFadedEllipse_0 +#define UI_DRAWING_DEFAULT_drawThickLine UI_DRAWING_drawThickLine_0 +#define UI_DRAWING_DEFAULT_drawThickCircle UI_DRAWING_drawThickCircle_0 +#define UI_DRAWING_DEFAULT_drawThickEllipse UI_DRAWING_drawThickEllipse_0 +#define UI_DRAWING_DEFAULT_drawThickCircleArc UI_DRAWING_drawThickCircleArc_0 +#define UI_DRAWING_DEFAULT_drawFlippedImage UI_DRAWING_drawFlippedImage_0 +#define UI_DRAWING_DEFAULT_drawRotatedImageNearestNeighbor UI_DRAWING_drawRotatedImageNearestNeighbor_0 +#define UI_DRAWING_DEFAULT_drawRotatedImageBilinear UI_DRAWING_drawRotatedImageBilinear_0 +#define UI_DRAWING_DEFAULT_drawScaledImageNearestNeighbor UI_DRAWING_drawScaledImageNearestNeighbor_0 +#define UI_DRAWING_DEFAULT_drawScaledImageBilinear UI_DRAWING_drawScaledImageBilinear_0 + +#endif // !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +// -------------------------------------------------------------------------------- +// Extern functions +// -------------------------------------------------------------------------------- + +#if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +/* + * @brief Set of drawing functions according to the index of the destination format in + * the drawing tables ("0", "1" or "2"). + * + * These functions must be declared in other H files. + */ + +#if (LLUI_GC_SUPPORTED_FORMATS > 3) +#error "Increase the number of following functions and update the next tables" +#endif + +extern DRAWING_Status UI_DRAWING_writePixel_0(MICROUI_GraphicsContext* gc, jint x, jint y); +extern DRAWING_Status UI_DRAWING_drawLine_0(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY); +extern DRAWING_Status UI_DRAWING_drawHorizontalLine_0(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y); +extern DRAWING_Status UI_DRAWING_drawVerticalLine_0(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2); +extern DRAWING_Status UI_DRAWING_drawRectangle_0(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); +extern DRAWING_Status UI_DRAWING_fillRectangle_0(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); +extern DRAWING_Status UI_DRAWING_drawRoundedRectangle_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); +extern DRAWING_Status UI_DRAWING_fillRoundedRectangle_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); +extern DRAWING_Status UI_DRAWING_drawCircleArc_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); +extern DRAWING_Status UI_DRAWING_drawEllipseArc_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); +extern DRAWING_Status UI_DRAWING_fillCircleArc_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); +extern DRAWING_Status UI_DRAWING_fillEllipseArc_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); +extern DRAWING_Status UI_DRAWING_drawEllipse_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); +extern DRAWING_Status UI_DRAWING_fillEllipse_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); +extern DRAWING_Status UI_DRAWING_drawCircle_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); +extern DRAWING_Status UI_DRAWING_fillCircle_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); +extern DRAWING_Status UI_DRAWING_drawImage_0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_DRAWING_copyImage_0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); +extern DRAWING_Status UI_DRAWING_drawRegion_0(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_DRAWING_drawThickFadedPoint_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade); +extern DRAWING_Status UI_DRAWING_drawThickFadedLine_0(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap); +extern DRAWING_Status UI_DRAWING_drawThickFadedCircle_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade); +extern DRAWING_Status UI_DRAWING_drawThickFadedCircleArc_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end); +extern DRAWING_Status UI_DRAWING_drawThickFadedEllipse_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade); +extern DRAWING_Status UI_DRAWING_drawThickLine_0(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness); +extern DRAWING_Status UI_DRAWING_drawThickCircle_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness); +extern DRAWING_Status UI_DRAWING_drawThickEllipse_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness); +extern DRAWING_Status UI_DRAWING_drawThickCircleArc_0(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness); +extern DRAWING_Status UI_DRAWING_drawFlippedImage_0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); +extern DRAWING_Status UI_DRAWING_drawRotatedImageNearestNeighbor_0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_DRAWING_drawRotatedImageBilinear_0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_DRAWING_drawScaledImageNearestNeighbor_0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_DRAWING_drawScaledImageBilinear_0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +extern uint32_t UI_DRAWING_getNewImageStrideInBytes_1(jbyte image_format, uint32_t width, uint32_t height, uint32_t default_stride); +extern void UI_DRAWING_adjustNewImageCharacteristics_1(jbyte image_format, uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment); +extern void UI_DRAWING_initializeNewImage_1(MICROUI_Image* image); +extern void UI_DRAWING_freeImageResources_1(MICROUI_Image* image); +extern DRAWING_Status UI_DRAWING_writePixel_1(MICROUI_GraphicsContext* gc, jint x, jint y); +extern DRAWING_Status UI_DRAWING_drawLine_1(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY); +extern DRAWING_Status UI_DRAWING_drawHorizontalLine_1(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y); +extern DRAWING_Status UI_DRAWING_drawVerticalLine_1(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2); +extern DRAWING_Status UI_DRAWING_drawRectangle_1(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); +extern DRAWING_Status UI_DRAWING_fillRectangle_1(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); +extern DRAWING_Status UI_DRAWING_drawRoundedRectangle_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); +extern DRAWING_Status UI_DRAWING_fillRoundedRectangle_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); +extern DRAWING_Status UI_DRAWING_drawCircleArc_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); +extern DRAWING_Status UI_DRAWING_drawEllipseArc_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); +extern DRAWING_Status UI_DRAWING_fillCircleArc_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); +extern DRAWING_Status UI_DRAWING_fillEllipseArc_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); +extern DRAWING_Status UI_DRAWING_drawEllipse_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); +extern DRAWING_Status UI_DRAWING_fillEllipse_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); +extern DRAWING_Status UI_DRAWING_drawCircle_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); +extern DRAWING_Status UI_DRAWING_fillCircle_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); +extern DRAWING_Status UI_DRAWING_drawImage_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_DRAWING_copyImage_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); +extern DRAWING_Status UI_DRAWING_drawRegion_1(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_DRAWING_drawThickFadedPoint_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade); +extern DRAWING_Status UI_DRAWING_drawThickFadedLine_1(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap); +extern DRAWING_Status UI_DRAWING_drawThickFadedCircle_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade); +extern DRAWING_Status UI_DRAWING_drawThickFadedCircleArc_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end); +extern DRAWING_Status UI_DRAWING_drawThickFadedEllipse_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade); +extern DRAWING_Status UI_DRAWING_drawThickLine_1(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness); +extern DRAWING_Status UI_DRAWING_drawThickCircle_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness); +extern DRAWING_Status UI_DRAWING_drawThickEllipse_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness); +extern DRAWING_Status UI_DRAWING_drawThickCircleArc_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness); +extern DRAWING_Status UI_DRAWING_drawFlippedImage_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); +extern DRAWING_Status UI_DRAWING_drawRotatedImageNearestNeighbor_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_DRAWING_drawRotatedImageBilinear_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_DRAWING_drawScaledImageNearestNeighbor_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_DRAWING_drawScaledImageBilinear_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +#if (LLUI_GC_SUPPORTED_FORMATS > 2) +extern uint32_t UI_DRAWING_getNewImageStrideInBytes_2(jbyte image_format, uint32_t width, uint32_t height, uint32_t default_stride); +extern void UI_DRAWING_adjustNewImageCharacteristics_2(jbyte image_format, uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment); +extern void UI_DRAWING_initializeNewImage_2(MICROUI_Image* image); +extern void UI_DRAWING_freeImageResources_2(MICROUI_Image* image); +extern DRAWING_Status UI_DRAWING_writePixel_2(MICROUI_GraphicsContext* gc, jint x, jint y); +extern DRAWING_Status UI_DRAWING_drawLine_2(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY); +extern DRAWING_Status UI_DRAWING_drawHorizontalLine_2(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y); +extern DRAWING_Status UI_DRAWING_drawVerticalLine_2(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2); +extern DRAWING_Status UI_DRAWING_drawRectangle_2(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); +extern DRAWING_Status UI_DRAWING_fillRectangle_2(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); +extern DRAWING_Status UI_DRAWING_drawRoundedRectangle_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); +extern DRAWING_Status UI_DRAWING_fillRoundedRectangle_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); +extern DRAWING_Status UI_DRAWING_drawCircleArc_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); +extern DRAWING_Status UI_DRAWING_drawEllipseArc_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); +extern DRAWING_Status UI_DRAWING_fillCircleArc_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); +extern DRAWING_Status UI_DRAWING_fillEllipseArc_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); +extern DRAWING_Status UI_DRAWING_drawEllipse_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); +extern DRAWING_Status UI_DRAWING_fillEllipse_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); +extern DRAWING_Status UI_DRAWING_drawCircle_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); +extern DRAWING_Status UI_DRAWING_fillCircle_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); +extern DRAWING_Status UI_DRAWING_drawImage_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_DRAWING_copyImage_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); +extern DRAWING_Status UI_DRAWING_drawRegion_2(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_DRAWING_drawThickFadedPoint_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade); +extern DRAWING_Status UI_DRAWING_drawThickFadedLine_2(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap); +extern DRAWING_Status UI_DRAWING_drawThickFadedCircle_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade); +extern DRAWING_Status UI_DRAWING_drawThickFadedCircleArc_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end); +extern DRAWING_Status UI_DRAWING_drawThickFadedEllipse_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade); +extern DRAWING_Status UI_DRAWING_drawThickLine_2(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness); +extern DRAWING_Status UI_DRAWING_drawThickCircle_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness); +extern DRAWING_Status UI_DRAWING_drawThickEllipse_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness); +extern DRAWING_Status UI_DRAWING_drawThickCircleArc_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness); +extern DRAWING_Status UI_DRAWING_drawFlippedImage_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); +extern DRAWING_Status UI_DRAWING_drawRotatedImageNearestNeighbor_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_DRAWING_drawRotatedImageBilinear_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_DRAWING_drawScaledImageNearestNeighbor_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_DRAWING_drawScaledImageBilinear_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +#endif // (LLUI_GC_SUPPORTED_FORMATS > 2) + +#endif // defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +// -------------------------------------------------------------------------------- +// Typedef of drawing functions +// -------------------------------------------------------------------------------- + +#if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +/* + * @brief Typedef used by next tables. See the function comments in ui_drawing.h + */ + +typedef uint32_t (* UI_DRAWING_getNewImageStrideInBytes_t) (jbyte image_format, uint32_t width, uint32_t height, uint32_t default_stride); +typedef void (* UI_DRAWING_adjustNewImageCharacteristics_t) (jbyte image_format, uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment); +typedef void (* UI_DRAWING_initializeNewImage_t) (MICROUI_Image* image); +typedef void (* UI_DRAWING_freeImageResources_t) (MICROUI_Image* image); +typedef DRAWING_Status (* UI_DRAWING_writePixel_t) (MICROUI_GraphicsContext* gc, jint x, jint y); +typedef DRAWING_Status (* UI_DRAWING_drawLine_t) (MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY); +typedef DRAWING_Status (* UI_DRAWING_drawHorizontalLine_t) (MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y); +typedef DRAWING_Status (* UI_DRAWING_drawVerticalLine_t) (MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2); +typedef DRAWING_Status (* UI_DRAWING_drawRectangle_t) (MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); +typedef DRAWING_Status (* UI_DRAWING_fillRectangle_t) (MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2); +typedef DRAWING_Status (* UI_DRAWING_drawRoundedRectangle_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); +typedef DRAWING_Status (* UI_DRAWING_fillRoundedRectangle_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight); +typedef DRAWING_Status (* UI_DRAWING_drawCircleArc_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); +typedef DRAWING_Status (* UI_DRAWING_drawEllipseArc_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); +typedef DRAWING_Status (* UI_DRAWING_fillCircleArc_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle); +typedef DRAWING_Status (* UI_DRAWING_fillEllipseArc_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle); +typedef DRAWING_Status (* UI_DRAWING_drawEllipse_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); +typedef DRAWING_Status (* UI_DRAWING_fillEllipse_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height); +typedef DRAWING_Status (* UI_DRAWING_drawCircle_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); +typedef DRAWING_Status (* UI_DRAWING_fillCircle_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter); +typedef DRAWING_Status (* UI_DRAWING_drawImage_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +typedef DRAWING_Status (* UI_DRAWING_copyImage_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); +typedef DRAWING_Status (* UI_DRAWING_drawRegion_t) (MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +typedef DRAWING_Status (* UI_DRAWING_drawThickFadedPoint_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade); +typedef DRAWING_Status (* UI_DRAWING_drawThickFadedLine_t) (MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap); +typedef DRAWING_Status (* UI_DRAWING_drawThickFadedCircle_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade); +typedef DRAWING_Status (* UI_DRAWING_drawThickFadedCircleArc_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end); +typedef DRAWING_Status (* UI_DRAWING_drawThickFadedEllipse_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade); +typedef DRAWING_Status (* UI_DRAWING_drawThickLine_t) (MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness); +typedef DRAWING_Status (* UI_DRAWING_drawThickCircle_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness); +typedef DRAWING_Status (* UI_DRAWING_drawThickEllipse_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness); +typedef DRAWING_Status (* UI_DRAWING_drawThickCircleArc_t) (MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness); +typedef DRAWING_Status (* UI_DRAWING_drawFlippedImage_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); +typedef DRAWING_Status (* UI_DRAWING_drawRotatedImageNearestNeighbor_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +typedef DRAWING_Status (* UI_DRAWING_drawRotatedImageBilinear_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +typedef DRAWING_Status (* UI_DRAWING_drawScaledImageNearestNeighbor_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +typedef DRAWING_Status (* UI_DRAWING_drawScaledImageBilinear_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +#endif // #if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +// -------------------------------------------------------------------------------- +// Tables according to the destination format. +// -------------------------------------------------------------------------------- + +#if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +static const UI_DRAWING_getNewImageStrideInBytes_t UI_DRAWER_getNewImageStrideInBytes[] = { + &UI_DRAWING_getNewImageStrideInBytes, + &UI_DRAWING_getNewImageStrideInBytes_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_getNewImageStrideInBytes_2, +#endif +}; + +static const UI_DRAWING_adjustNewImageCharacteristics_t UI_DRAWER_adjustNewImageCharacteristics[] = { + &UI_DRAWING_adjustNewImageCharacteristics, + &UI_DRAWING_adjustNewImageCharacteristics_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_adjustNewImageCharacteristics_2, +#endif +}; + +static const UI_DRAWING_initializeNewImage_t UI_DRAWER_initializeNewImage[] = { + &UI_DRAWING_initializeNewImage, + &UI_DRAWING_initializeNewImage_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_initializeNewImage_2, +#endif +}; + +static const UI_DRAWING_freeImageResources_t UI_DRAWER_freeImageResources[] = { + &UI_DRAWING_freeImageResources, + &UI_DRAWING_freeImageResources_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_freeImageResources_2, +#endif +}; + +static const UI_DRAWING_writePixel_t UI_DRAWER_writePixel[] = { + &UI_DRAWING_writePixel_0, + &UI_DRAWING_writePixel_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_writePixel_2, +#endif +}; + +static const UI_DRAWING_drawLine_t UI_DRAWER_drawLine[] = { + &UI_DRAWING_drawLine_0, + &UI_DRAWING_drawLine_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawLine_2, +#endif +}; + +static const UI_DRAWING_drawHorizontalLine_t UI_DRAWER_drawHorizontalLine[] = { + &UI_DRAWING_drawHorizontalLine_0, + &UI_DRAWING_drawHorizontalLine_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawHorizontalLine_2, +#endif +}; + +static const UI_DRAWING_drawVerticalLine_t UI_DRAWER_drawVerticalLine[] = { + &UI_DRAWING_drawVerticalLine_0, + &UI_DRAWING_drawVerticalLine_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawVerticalLine_2, +#endif +}; + +static const UI_DRAWING_drawRectangle_t UI_DRAWER_drawRectangle[] = { + &UI_DRAWING_drawRectangle_0, + &UI_DRAWING_drawRectangle_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawRectangle_2, +#endif +}; + +static const UI_DRAWING_fillRectangle_t UI_DRAWER_fillRectangle[] = { + &UI_DRAWING_fillRectangle_0, + &UI_DRAWING_fillRectangle_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_fillRectangle_2, +#endif +}; + +static const UI_DRAWING_drawRoundedRectangle_t UI_DRAWER_drawRoundedRectangle[] = { + &UI_DRAWING_drawRoundedRectangle_0, + &UI_DRAWING_drawRoundedRectangle_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawRoundedRectangle_2, +#endif +}; + +static const UI_DRAWING_fillRoundedRectangle_t UI_DRAWER_fillRoundedRectangle[] = { + &UI_DRAWING_fillRoundedRectangle_0, + &UI_DRAWING_fillRoundedRectangle_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_fillRoundedRectangle_2, +#endif +}; + +static const UI_DRAWING_drawCircleArc_t UI_DRAWER_drawCircleArc[] = { + &UI_DRAWING_drawCircleArc_0, + &UI_DRAWING_drawCircleArc_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawCircleArc_2, +#endif +}; + +static const UI_DRAWING_drawEllipseArc_t UI_DRAWER_drawEllipseArc[] = { + &UI_DRAWING_drawEllipseArc_0, + &UI_DRAWING_drawEllipseArc_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawEllipseArc_2, +#endif +}; + +static const UI_DRAWING_fillCircleArc_t UI_DRAWER_fillCircleArc[] = { + &UI_DRAWING_fillCircleArc_0, + &UI_DRAWING_fillCircleArc_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_fillCircleArc_2, +#endif +}; + +static const UI_DRAWING_fillEllipseArc_t UI_DRAWER_fillEllipseArc[] = { + &UI_DRAWING_fillEllipseArc_0, + &UI_DRAWING_fillEllipseArc_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_fillEllipseArc_2, +#endif +}; + +static const UI_DRAWING_drawEllipse_t UI_DRAWER_drawEllipse[] = { + &UI_DRAWING_drawEllipse_0, + &UI_DRAWING_drawEllipse_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawEllipse_2, +#endif +}; + +static const UI_DRAWING_fillEllipse_t UI_DRAWER_fillEllipse[] = { + &UI_DRAWING_fillEllipse_0, + &UI_DRAWING_fillEllipse_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_fillEllipse_2, +#endif +}; + +static const UI_DRAWING_drawCircle_t UI_DRAWER_drawCircle[] = { + &UI_DRAWING_drawCircle_0, + &UI_DRAWING_drawCircle_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawCircle_2, +#endif +}; + +static const UI_DRAWING_fillCircle_t UI_DRAWER_fillCircle[] = { + &UI_DRAWING_fillCircle_0, + &UI_DRAWING_fillCircle_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_fillCircle_2, +#endif +}; + +static const UI_DRAWING_drawImage_t UI_DRAWER_drawImage[] = { + &UI_DRAWING_drawImage_0, + &UI_DRAWING_drawImage_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawImage_2, +#endif +}; + +static const UI_DRAWING_copyImage_t UI_DRAWER_copyImage[] = { + &UI_DRAWING_copyImage_0, + &UI_DRAWING_copyImage_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_copyImage_2, +#endif +}; + +static const UI_DRAWING_drawRegion_t UI_DRAWER_drawRegion[] = { + &UI_DRAWING_drawRegion_0, + &UI_DRAWING_drawRegion_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawRegion_2, +#endif +}; + +static const UI_DRAWING_drawThickFadedPoint_t UI_DRAWER_drawThickFadedPoint[] = { + &UI_DRAWING_drawThickFadedPoint_0, + &UI_DRAWING_drawThickFadedPoint_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawThickFadedPoint_2, +#endif +}; + +static const UI_DRAWING_drawThickFadedLine_t UI_DRAWER_drawThickFadedLine[] = { + &UI_DRAWING_drawThickFadedLine_0, + &UI_DRAWING_drawThickFadedLine_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawThickFadedLine_2, +#endif +}; + +static const UI_DRAWING_drawThickFadedCircle_t UI_DRAWER_drawThickFadedCircle[] = { + &UI_DRAWING_drawThickFadedCircle_0, + &UI_DRAWING_drawThickFadedCircle_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawThickFadedCircle_2, +#endif +}; + +static const UI_DRAWING_drawThickFadedCircleArc_t UI_DRAWER_drawThickFadedCircleArc[] = { + &UI_DRAWING_drawThickFadedCircleArc_0, + &UI_DRAWING_drawThickFadedCircleArc_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawThickFadedCircleArc_2, +#endif +}; + +static const UI_DRAWING_drawThickFadedEllipse_t UI_DRAWER_drawThickFadedEllipse[] = { + &UI_DRAWING_drawThickFadedEllipse_0, + &UI_DRAWING_drawThickFadedEllipse_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawThickFadedEllipse_2, +#endif +}; + +static const UI_DRAWING_drawThickLine_t UI_DRAWER_drawThickLine[] = { + &UI_DRAWING_drawThickLine_0, + &UI_DRAWING_drawThickLine_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawThickLine_2, +#endif +}; + +static const UI_DRAWING_drawThickCircle_t UI_DRAWER_drawThickCircle[] = { + &UI_DRAWING_drawThickCircle_0, + &UI_DRAWING_drawThickCircle_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawThickCircle_2, +#endif +}; + +static const UI_DRAWING_drawThickEllipse_t UI_DRAWER_drawThickEllipse[] = { + &UI_DRAWING_drawThickEllipse_0, + &UI_DRAWING_drawThickEllipse_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawThickEllipse_2, +#endif +}; + +static const UI_DRAWING_drawThickCircleArc_t UI_DRAWER_drawThickCircleArc[] = { + &UI_DRAWING_drawThickCircleArc_0, + &UI_DRAWING_drawThickCircleArc_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawThickCircleArc_2, +#endif +}; + +static const UI_DRAWING_drawFlippedImage_t UI_DRAWER_drawFlippedImage[] = { + &UI_DRAWING_drawFlippedImage_0, + &UI_DRAWING_drawFlippedImage_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawFlippedImage_2, +#endif +}; + +static const UI_DRAWING_drawRotatedImageNearestNeighbor_t UI_DRAWER_drawRotatedImageNearestNeighbor[] = { + &UI_DRAWING_drawRotatedImageNearestNeighbor_0, + &UI_DRAWING_drawRotatedImageNearestNeighbor_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawRotatedImageNearestNeighbor_2, +#endif +}; + +static const UI_DRAWING_drawRotatedImageBilinear_t UI_DRAWER_drawRotatedImageBilinear[] = { + &UI_DRAWING_drawRotatedImageBilinear_0, + &UI_DRAWING_drawRotatedImageBilinear_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawRotatedImageBilinear_2, +#endif +}; + +static const UI_DRAWING_drawScaledImageNearestNeighbor_t UI_DRAWER_drawScaledImageNearestNeighbor[] = { + &UI_DRAWING_drawScaledImageNearestNeighbor_0, + &UI_DRAWING_drawScaledImageNearestNeighbor_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawScaledImageNearestNeighbor_2, +#endif +}; + +static const UI_DRAWING_drawScaledImageBilinear_t UI_DRAWER_drawScaledImageBilinear[] = { + &UI_DRAWING_drawScaledImageBilinear_0, + &UI_DRAWING_drawScaledImageBilinear_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &UI_DRAWING_drawScaledImageBilinear_2, +#endif +}; + +#endif // defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +// -------------------------------------------------------------------------------- +// LLUI_DISPLAY_impl.h functions that depend on image format +// (the functions are redirected to ui_drawing.h) +// -------------------------------------------------------------------------------- + +#if !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +/* + * The VEE port supports only one destination format: the display buffer format. The + * application mutable images have the same format as the display buffer. + */ + +// See the header file for the function documentation +int32_t LLUI_DISPLAY_IMPL_getDrawerIdentifier(jbyte image_format) { + return LLUI_DISPLAY_isDisplayFormat(image_format) ? 0 /* no error */ : -1 /* means invalid */; +} + +// See the header file for the function documentation +uint32_t LLUI_DISPLAY_IMPL_getNewImageStrideInBytes(jbyte image_format, uint32_t width, uint32_t height, uint32_t default_stride) { + // just make an indirection (useful for multi destination formats) + return UI_DRAWING_getNewImageStrideInBytes(image_format, width, height, default_stride); +} + +// See the header file for the function documentation +void LLUI_DISPLAY_IMPL_adjustNewImageCharacteristics(jbyte image_format, uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment) { + // just make an indirection (useful for multi destination formats) + UI_DRAWING_adjustNewImageCharacteristics(image_format, width, height, data_size, data_alignment); +} + +// See the header file for the function documentation +void LLUI_DISPLAY_IMPL_initializeNewImage(MICROUI_Image* image) { + // just make an indirection (useful for multi destination formats) + UI_DRAWING_initializeNewImage(image); +} + +// See the header file for the function documentation +void LLUI_DISPLAY_IMPL_freeImageResources(MICROUI_Image* image) { + // just make an indirection (useful for multi destination formats) + UI_DRAWING_freeImageResources(image); +} + +#else // #if !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +/* + * The VEE port supports several destination formats. All drawing functions use a + * dedicated table to redirect to the right implementation. The VEE Port must implement + * the functions UI_DRAWING_is_drawer_X() to identify the right drawer according to + * the destination format. + * + * The "DEFAULT" functions (see below) are used as element "0" of the tables (this is the + * display buffer format). + */ + +int32_t LLUI_DISPLAY_IMPL_getDrawerIdentifier(jbyte image_format) { + + int32_t index; + + if (LLUI_DISPLAY_isDisplayFormat(image_format)) { + index = 0; + } else if (UI_DRAWING_is_drawer_1(image_format)) { + index = 1; +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + } else if (UI_DRAWING_is_drawer_2(image_format)) { + index = 2; +#endif + } + else { + // unknown format + index = -1; + } + + return index; +} + +/* + * @brief See the header file for the function documentation + * + * Implementation details: The new image to create is an immutable image or a mutable image. + * + * - If it is a mutable image, that means a drawer is able to draw into it (see + * LLUI_DISPLAY_IMPL_getDrawerIdentifier()). In this case, this function redirects the + * implementation to the drawer (that should be able to adjust image characteristics if + * required). + * + * - If it is an immutable image (PNG decoder, automatic image format convert, etc.), that + * means (most of the time) no drawer can manage this image format. In such case, this function + * redirects the implementation to the default implementation (the indirection table + * UI_DRAWER_getNewImageStrideInBytes points to the default function at index 0). + * + * - In the case a drawer is available for this new immutable image, this function redirects + * to the drawer. + */ +uint32_t LLUI_DISPLAY_IMPL_getNewImageStrideInBytes(jbyte image_format, uint32_t width, uint32_t height, uint32_t default_stride) { + int32_t drawer = LLUI_DISPLAY_IMPL_getDrawerIdentifier(image_format); + drawer = (drawer >= 0) ? drawer : 0; + return (*UI_DRAWER_getNewImageStrideInBytes[drawer])(image_format, width, height, default_stride); +} + +// See the header file foar the function documentation and implementation of +// LLUI_DISPLAY_IMPL_getNewImageStrideInBytes +void LLUI_DISPLAY_IMPL_adjustNewImageCharacteristics(jbyte image_format, uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment) { + int32_t drawer = LLUI_DISPLAY_IMPL_getDrawerIdentifier(image_format); + drawer = (drawer >= 0) ? drawer : 0; + (*UI_DRAWER_adjustNewImageCharacteristics[drawer])(image_format, width, height, data_size, data_alignment); +} + +// See the header file for the function documentation and implementation of +// LLUI_DISPLAY_IMPL_getNewImageStrideInBytes +void LLUI_DISPLAY_IMPL_initializeNewImage(MICROUI_Image* image) { + int32_t drawer = LLUI_DISPLAY_IMPL_getDrawerIdentifier(image->format); + drawer = (drawer >= 0) ? drawer : 0; + (*UI_DRAWER_initializeNewImage[drawer])(image); +} + +// See the header file for the function documentation and implementation of +// LLUI_DISPLAY_IMPL_getNewImageStrideInBytes +void LLUI_DISPLAY_IMPL_freeImageResources(MICROUI_Image* image) { + int32_t drawer = LLUI_DISPLAY_IMPL_getDrawerIdentifier(image->format); + drawer = (drawer >= 0) ? drawer : 0; + (*UI_DRAWER_freeImageResources[drawer])(image); +} + +#endif // #if !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +// -------------------------------------------------------------------------------- +// ui_drawing.h functions +// (the function names don't differ regardless of the available number of destination formats) +// -------------------------------------------------------------------------------- + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT uint32_t UI_DRAWING_getNewImageStrideInBytes(jbyte image_format, uint32_t width, uint32_t height, uint32_t default_stride) { + (void)image_format; + (void)width; + (void)height; + // no specific stride by default + return default_stride; +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void UI_DRAWING_adjustNewImageCharacteristics(jbyte image_format, uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment){ + (void)image_format; + (void)width; + (void)height; + (void)data_size; + (void)data_alignment; + // nothing to adjust by default +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void UI_DRAWING_initializeNewImage(MICROUI_Image* image){ + (void)image; + // nothing to initialize by default +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void UI_DRAWING_freeImageResources(MICROUI_Image* image){ + (void)image; + // nothing to initialize by default +} + +// -------------------------------------------------------------------------------- +// ui_drawing.h functions +// (the function names differ according to the available number of destination formats) +// -------------------------------------------------------------------------------- + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_writePixel(MICROUI_GraphicsContext* gc, jint x, jint y){ + return UI_DRAWING_SOFT_writePixel(gc, x, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY){ + return UI_DRAWING_SOFT_drawLine(gc, startX, startY, endX, endY); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawHorizontalLine(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y){ + return UI_DRAWING_SOFT_drawHorizontalLine(gc, x1, x2, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawVerticalLine(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2){ + return UI_DRAWING_SOFT_drawVerticalLine(gc, x, y1, y2); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2){ + return UI_DRAWING_SOFT_drawRectangle(gc, x1, y1, x2, y2); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_fillRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2){ + return UI_DRAWING_SOFT_fillRectangle(gc, x1, y1, x2, y2); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + return UI_DRAWING_SOFT_drawRoundedRectangle(gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_fillRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + return UI_DRAWING_SOFT_fillRoundedRectangle(gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_SOFT_drawCircleArc(gc, x, y, diameter, startAngle, arcAngle); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_SOFT_drawEllipseArc(gc, x, y, width, height, startAngle, arcAngle); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_fillCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_SOFT_fillCircleArc(gc, x, y, diameter, startAngle, arcAngle); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_fillEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_SOFT_fillEllipseArc(gc, x, y, width, height, startAngle, arcAngle); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + return UI_DRAWING_SOFT_drawEllipse(gc, x, y, width, height); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_fillEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + return UI_DRAWING_SOFT_fillEllipse(gc, x, y, width, height); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + return UI_DRAWING_SOFT_drawCircle(gc, x, y, diameter); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_fillCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + return UI_DRAWING_SOFT_fillCircle(gc, x, y, diameter); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ +#if !defined(LLUI_IMAGE_CUSTOM_FORMATS) + return UI_DRAWING_SOFT_drawImage(gc, img, regionX, regionY, width, height, x, y, alpha); +#else + return UI_IMAGE_DRAWING_draw(gc, img, regionX, regionY, width, height, x, y, alpha); +#endif +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_copyImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ +#if !defined(LLUI_IMAGE_CUSTOM_FORMATS) + return UI_DRAWING_SOFT_copyImage(gc, img, regionX, regionY, width, height, x, y); +#else + return UI_IMAGE_DRAWING_copy(gc, img, regionX, regionY, width, height, x, y); +#endif +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawRegion(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ +#if !defined(LLUI_IMAGE_CUSTOM_FORMATS) + return UI_DRAWING_SOFT_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +#else + return UI_IMAGE_DRAWING_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +#endif +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawThickFadedPoint(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade){ + return DW_DRAWING_SOFT_drawThickFadedPoint(gc, x, y, thickness, fade); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawThickFadedLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap){ + return DW_DRAWING_SOFT_drawThickFadedLine(gc, startX, startY, endX, endY, thickness, fade, startCap, endCap); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawThickFadedCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade){ + return DW_DRAWING_SOFT_drawThickFadedCircle(gc, x, y, diameter, thickness, fade); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawThickFadedCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end){ + return DW_DRAWING_SOFT_drawThickFadedCircleArc(gc, x, y, diameter, startAngle, arcAngle, thickness, fade, start, end); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawThickFadedEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade){ + return DW_DRAWING_SOFT_drawThickFadedEllipse(gc, x, y, width, height, thickness, fade); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawThickLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness){ + return DW_DRAWING_SOFT_drawThickLine(gc, startX, startY, endX, endY, thickness); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawThickCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness){ + return DW_DRAWING_SOFT_drawThickCircle(gc, x, y, diameter, thickness); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawThickEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness){ + return DW_DRAWING_SOFT_drawThickEllipse(gc, x, y, width, height, thickness); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawThickCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness){ + return DW_DRAWING_SOFT_drawThickCircleArc(gc, x, y, diameter, startAngle, arcAngle, thickness); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawFlippedImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ +#if !defined(LLUI_IMAGE_CUSTOM_FORMATS) + return DW_DRAWING_SOFT_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +#else + return UI_IMAGE_DRAWING_drawFlipped(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +#endif +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawRotatedImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ +#if !defined(LLUI_IMAGE_CUSTOM_FORMATS) + return DW_DRAWING_SOFT_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); +#else + return UI_IMAGE_DRAWING_drawRotatedNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); +#endif +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawRotatedImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ +#if !defined(LLUI_IMAGE_CUSTOM_FORMATS) + return DW_DRAWING_SOFT_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); +#else + return UI_IMAGE_DRAWING_drawRotatedBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); +#endif +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawScaledImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ +#if !defined(LLUI_IMAGE_CUSTOM_FORMATS) + return DW_DRAWING_SOFT_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); +#else + return UI_IMAGE_DRAWING_drawScaledNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); +#endif +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_DEFAULT_drawScaledImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ +#if !defined(LLUI_IMAGE_CUSTOM_FORMATS) + return DW_DRAWING_SOFT_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); +#else + return UI_IMAGE_DRAWING_drawScaledBilinear(gc, img, x, y, factorX, factorY, alpha); +#endif +} + +#if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +/* + * The VEE port supports several destination formats. All drawing functions use a + * dedicated table to redirect to the right implementation. The VEE Port must implement + * the functions UI_DRAWING_is_drawer_X() to identify the right drawer according to + * the destination format. + * + * The "DEFAULT" functions (see above) are used as element "0" of the tables (== display + * buffer format). + */ + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_writePixel(MICROUI_GraphicsContext* gc, jint x, jint y){ + return (*UI_DRAWER_writePixel[gc->drawer])(gc, x, y); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY){ + return (*UI_DRAWER_drawLine[gc->drawer])(gc, startX, startY, endX, endY); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawHorizontalLine(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y){ + return (*UI_DRAWER_drawHorizontalLine[gc->drawer])(gc, x1, x2, y); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawVerticalLine(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2){ + return (*UI_DRAWER_drawVerticalLine[gc->drawer])(gc, x, y1, y2); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2){ + return (*UI_DRAWER_drawRectangle[gc->drawer])(gc, x1, y1, x2, y2); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_fillRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2){ + return (*UI_DRAWER_fillRectangle[gc->drawer])(gc, x1, y1, x2, y2); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + return (*UI_DRAWER_drawRoundedRectangle[gc->drawer])(gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_fillRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + return (*UI_DRAWER_fillRoundedRectangle[gc->drawer])(gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + return (*UI_DRAWER_drawCircleArc[gc->drawer])(gc, x, y, diameter, startAngle, arcAngle); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + return (*UI_DRAWER_drawEllipseArc[gc->drawer])(gc, x, y, width, height, startAngle, arcAngle); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_fillCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + return (*UI_DRAWER_fillCircleArc[gc->drawer])(gc, x, y, diameter, startAngle, arcAngle); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_fillEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + return (*UI_DRAWER_fillEllipseArc[gc->drawer])(gc, x, y, width, height, startAngle, arcAngle); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + return (*UI_DRAWER_drawEllipse[gc->drawer])(gc, x, y, width, height); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_fillEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + return (*UI_DRAWER_fillEllipse[gc->drawer])(gc, x, y, width, height); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + return (*UI_DRAWER_drawCircle[gc->drawer])(gc, x, y, diameter); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_fillCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + return (*UI_DRAWER_fillCircle[gc->drawer])(gc, x, y, diameter); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return (*UI_DRAWER_drawImage[gc->drawer])(gc, img, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_copyImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + return (*UI_DRAWER_copyImage[gc->drawer])(gc, img, regionX, regionY, width, height, x, y); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawRegion(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return (*UI_DRAWER_drawRegion[gc->drawer])(gc, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawThickFadedPoint(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade){ + return (*UI_DRAWER_drawThickFadedPoint[gc->drawer])(gc, x, y, thickness, fade); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawThickFadedLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap){ + return (*UI_DRAWER_drawThickFadedLine[gc->drawer])(gc, startX, startY, endX, endY, thickness, fade, startCap, endCap); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawThickFadedCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade){ + return (*UI_DRAWER_drawThickFadedCircle[gc->drawer])(gc, x, y, diameter, thickness, fade); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawThickFadedCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end){ + return (*UI_DRAWER_drawThickFadedCircleArc[gc->drawer])(gc, x, y, diameter, startAngle, arcAngle, thickness, fade, start, end); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawThickFadedEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade){ + return (*UI_DRAWER_drawThickFadedEllipse[gc->drawer])(gc, x, y, width, height, thickness, fade); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawThickLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness){ + return (*UI_DRAWER_drawThickLine[gc->drawer])(gc, startX, startY, endX, endY, thickness); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawThickCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness){ + return (*UI_DRAWER_drawThickCircle[gc->drawer])(gc, x, y, diameter, thickness); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawThickEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness){ + return (*UI_DRAWER_drawThickEllipse[gc->drawer])(gc, x, y, width, height, thickness); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawThickCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness){ + return (*UI_DRAWER_drawThickCircleArc[gc->drawer])(gc, x, y, diameter, startAngle, arcAngle, thickness); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawFlippedImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + return (*UI_DRAWER_drawFlippedImage[gc->drawer])(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawRotatedImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return (*UI_DRAWER_drawRotatedImageNearestNeighbor[gc->drawer])(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawRotatedImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return (*UI_DRAWER_drawRotatedImageBilinear[gc->drawer])(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawScaledImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return (*UI_DRAWER_drawScaledImageNearestNeighbor[gc->drawer])(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_drawScaledImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return (*UI_DRAWER_drawScaledImageBilinear[gc->drawer])(gc, img, x, y, factorX, factorY, alpha); +} + +/* + * The next functions are used as elements "1" of the tables. They call STUB functions and should be + * overridden by the drawer that manages the format identified by the index "1". + * + * Only the functions UI_DRAWING_adjustNewImageCharacteristics_1() and UI_DRAWING_initializeNewImage_1() + * are mandatory. If the drawing engine (for the format identified by the index "1") does not override these + * functions, the application will not be able to open an image with the associated format (the default functions + * are implemented as weak functions in case there is no drawing engine for this format). + * + * If no engine supports the format identified by the index "1", the application will not be able to open + * an image with the associated format. + */ + +BSP_DECLARE_WEAK_FCNT bool UI_DRAWING_is_drawer_1(jbyte image_format) { + (void)image_format; + // default behavior: format is not supported + return false; +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT uint32_t UI_DRAWING_getNewImageStrideInBytes_1(jbyte image_format, uint32_t width, uint32_t height, uint32_t default_stride){ + (void)image_format; + (void)width; + (void)height; + // does nothing and will throw an error if the application tries to open this kind of image. + // see above. + return default_stride; +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void UI_DRAWING_adjustNewImageCharacteristics_1(jbyte image_format, uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment){ + (void)image_format; + (void)width; + (void)height; + (void)data_size; + (void)data_alignment; + // does nothing and will throw an error if the application tries to open this kind of image. + // see above. +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void UI_DRAWING_initializeNewImage_1(MICROUI_Image* image){ + (void)image; + // nothing to do +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void UI_DRAWING_freeImageResources_1(MICROUI_Image* image){ + (void)image; + // nothing to do +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_writePixel_1(MICROUI_GraphicsContext* gc, jint x, jint y){ + return UI_DRAWING_STUB_writePixel(gc, x, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawLine_1(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY){ + return UI_DRAWING_STUB_drawLine(gc, startX, startY, endX, endY); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawHorizontalLine_1(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y){ + return UI_DRAWING_STUB_drawHorizontalLine(gc, x1, x2, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawVerticalLine_1(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2){ + return UI_DRAWING_STUB_drawVerticalLine(gc, x, y1, y2); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawRectangle_1(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2){ + return UI_DRAWING_STUB_drawRectangle(gc, x1, y1, x2, y2); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_fillRectangle_1(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2){ + return UI_DRAWING_STUB_fillRectangle(gc, x1, y1, x2, y2); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawRoundedRectangle_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + return UI_DRAWING_STUB_drawRoundedRectangle(gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_fillRoundedRectangle_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + return UI_DRAWING_STUB_fillRoundedRectangle(gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawCircleArc_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_STUB_drawCircleArc(gc, x, y, diameter, startAngle, arcAngle); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawEllipseArc_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_STUB_drawEllipseArc(gc, x, y, width, height, startAngle, arcAngle); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_fillCircleArc_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_STUB_fillCircleArc(gc, x, y, diameter, startAngle, arcAngle); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_fillEllipseArc_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_STUB_fillEllipseArc(gc, x, y, width, height, startAngle, arcAngle); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawEllipse_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + return UI_DRAWING_STUB_drawEllipse(gc, x, y, width, height); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_fillEllipse_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + return UI_DRAWING_STUB_fillEllipse(gc, x, y, width, height); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawCircle_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + return UI_DRAWING_STUB_drawCircle(gc, x, y, diameter); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_fillCircle_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + return UI_DRAWING_STUB_fillCircle(gc, x, y, diameter); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawImage_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_IMAGE_DRAWING_draw(gc, img, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_copyImage_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + return UI_IMAGE_DRAWING_copy(gc, img, regionX, regionY, width, height, x, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawRegion_1(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_IMAGE_DRAWING_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickFadedPoint_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade){ + return UI_DRAWING_STUB_drawThickFadedPoint(gc, x, y, thickness, fade); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickFadedLine_1(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap){ + return UI_DRAWING_STUB_drawThickFadedLine(gc, startX, startY, endX, endY, thickness, fade, startCap, endCap); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickFadedCircle_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade){ + return UI_DRAWING_STUB_drawThickFadedCircle(gc, x, y, diameter, thickness, fade); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickFadedCircleArc_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end){ + return UI_DRAWING_STUB_drawThickFadedCircleArc(gc, x, y, diameter, startAngle, arcAngle, thickness, fade, start, end); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickFadedEllipse_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade){ + return UI_DRAWING_STUB_drawThickFadedEllipse(gc, x, y, width, height, thickness, fade); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickLine_1(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness){ + return UI_DRAWING_STUB_drawThickLine(gc, startX, startY, endX, endY, thickness); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickCircle_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness){ + return UI_DRAWING_STUB_drawThickCircle(gc, x, y, diameter, thickness); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickEllipse_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness){ + return UI_DRAWING_STUB_drawThickEllipse(gc, x, y, width, height, thickness); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickCircleArc_1(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness){ + return UI_DRAWING_STUB_drawThickCircleArc(gc, x, y, diameter, startAngle, arcAngle, thickness); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawFlippedImage_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + return UI_IMAGE_DRAWING_drawFlipped(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawRotatedImageNearestNeighbor_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_IMAGE_DRAWING_drawRotatedNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawRotatedImageBilinear_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_IMAGE_DRAWING_drawRotatedBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawScaledImageNearestNeighbor_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_IMAGE_DRAWING_drawScaledNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawScaledImageBilinear_1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_IMAGE_DRAWING_drawScaledBilinear(gc, img, x, y, factorX, factorY, alpha); +} + +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + +/* + * The next functions are used as elements "2" of the tables. They call STUB functions and should be + * overridden by the drawer that manages the format identified by the index "2". + * + * Only the functions UI_DRAWING_adjustNewImageCharacteristics_2() and UI_DRAWING_initializeNewImage_2() + * are mandatory. If the drawing engine (for the format identified by the index "2") does not override these + * functions, the application will not be able to open an image with the associated format (the default functions + * are implemented as weak functions in case there is no drawing engine for this format). + * + * If no engine supports the format identified by the index "2", the application will not be able to open + * an image with the associated format. + */ + +BSP_DECLARE_WEAK_FCNT bool UI_DRAWING_is_drawer_2(jbyte image_format) { + (void)image_format; + // default behavior: format is not supported + return false; +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT uint32_t UI_DRAWING_getNewImageStrideInBytes_2(jbyte image_format, uint32_t width, uint32_t height, uint32_t default_stride){ + (void)image_format; + (void)width; + (void)height; + // does nothing and will throw an error if the application tries to open this kind of image. + // see above. + return default_stride; +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void UI_DRAWING_adjustNewImageCharacteristics_2(jbyte image_format, uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment){ + (void)image_format; + (void)width; + (void)height; + (void)data_size; + (void)data_alignment; + // does nothing and will throw an error if the application tries to open this kind of image. + // see above. +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void UI_DRAWING_initializeNewImage_2(MICROUI_Image* image){ + (void)image; + // nothing to do +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void UI_DRAWING_freeImageResources_2(MICROUI_Image* image){ + (void)image; + // nothing to do +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_writePixel_2(MICROUI_GraphicsContext* gc, jint x, jint y){ + return UI_DRAWING_STUB_writePixel(gc, x, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawLine_2(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY){ + return UI_DRAWING_STUB_drawLine(gc, startX, startY, endX, endY); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawHorizontalLine_2(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y){ + return UI_DRAWING_STUB_drawHorizontalLine(gc, x1, x2, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawVerticalLine_2(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2){ + return UI_DRAWING_STUB_drawVerticalLine(gc, x, y1, y2); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawRectangle_2(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2){ + return UI_DRAWING_STUB_drawRectangle(gc, x1, y1, x2, y2); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_fillRectangle_2(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2){ + return UI_DRAWING_STUB_fillRectangle(gc, x1, y1, x2, y2); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawRoundedRectangle_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + return UI_DRAWING_STUB_drawRoundedRectangle(gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_fillRoundedRectangle_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + return UI_DRAWING_STUB_fillRoundedRectangle(gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawCircleArc_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_STUB_drawCircleArc(gc, x, y, diameter, startAngle, arcAngle); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawEllipseArc_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_STUB_drawEllipseArc(gc, x, y, width, height, startAngle, arcAngle); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_fillCircleArc_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_STUB_fillCircleArc(gc, x, y, diameter, startAngle, arcAngle); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_fillEllipseArc_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_STUB_fillEllipseArc(gc, x, y, width, height, startAngle, arcAngle); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawEllipse_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + return UI_DRAWING_STUB_drawEllipse(gc, x, y, width, height); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_fillEllipse_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + return UI_DRAWING_STUB_fillEllipse(gc, x, y, width, height); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawCircle_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + return UI_DRAWING_STUB_drawCircle(gc, x, y, diameter); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_fillCircle_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + return UI_DRAWING_STUB_fillCircle(gc, x, y, diameter); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawImage_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_IMAGE_DRAWING_draw(gc, img, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_copyImage_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + return UI_IMAGE_DRAWING_copy(gc, img, regionX, regionY, width, height, x, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawRegion_2(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_IMAGE_DRAWING_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickFadedPoint_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade){ + return UI_DRAWING_STUB_drawThickFadedPoint(gc, x, y, thickness, fade); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickFadedLine_2(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap){ + return UI_DRAWING_STUB_drawThickFadedLine(gc, startX, startY, endX, endY, thickness, fade, startCap, endCap); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickFadedCircle_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade){ + return UI_DRAWING_STUB_drawThickFadedCircle(gc, x, y, diameter, thickness, fade); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickFadedCircleArc_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end){ + return UI_DRAWING_STUB_drawThickFadedCircleArc(gc, x, y, diameter, startAngle, arcAngle, thickness, fade, start, end); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickFadedEllipse_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade){ + return UI_DRAWING_STUB_drawThickFadedEllipse(gc, x, y, width, height, thickness, fade); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickLine_2(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness){ + return UI_DRAWING_STUB_drawThickLine(gc, startX, startY, endX, endY, thickness); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickCircle_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness){ + return UI_DRAWING_STUB_drawThickCircle(gc, x, y, diameter, thickness); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickEllipse_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness){ + return UI_DRAWING_STUB_drawThickEllipse(gc, x, y, width, height, thickness); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawThickCircleArc_2(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness){ + return UI_DRAWING_STUB_drawThickCircleArc(gc, x, y, diameter, startAngle, arcAngle, thickness); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawFlippedImage_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + return UI_IMAGE_DRAWING_drawFlipped(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawRotatedImageNearestNeighbor_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_IMAGE_DRAWING_drawRotatedNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawRotatedImageBilinear_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_IMAGE_DRAWING_drawRotatedBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawScaledImageNearestNeighbor_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_IMAGE_DRAWING_drawScaledNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_DRAWING_drawScaledImageBilinear_2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_IMAGE_DRAWING_drawScaledBilinear(gc, img, x, y, factorX, factorY, alpha); +} + +#endif // (LLUI_GC_SUPPORTED_FORMATS > 2) + +#else // #if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +/* + * The VEE port supports only one destination format: the display buffer format. The + * application can only create immutable images or mutable images with the same format as + * the display buffer. All drawing functions are redirected to the software implementation + * by default. A third party implementation (often on a GPU) can replace each weak function + * independently. + * + * The VEE Port can tune the new image characteristics to add a header before the pixel + * array for instance. + */ + +#endif // #if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- diff --git a/bsp/projects/microej/ui/src/ui_drawing_argb8888.c b/bsp/projects/microej/ui/src/ui_drawing_argb8888.c new file mode 100644 index 0000000..4469bef --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_drawing_argb8888.c @@ -0,0 +1,34 @@ +/* + * Copyright 2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#include + +#include "ui_drawing_vglite.h" +#include "vg_drawing_vglite.h" + +/* + * The current VEE port supports two output formats: BufferedVectorImage (see the MicroVG CCO) and ARGB8888 (this file). + * To add another output format, add the same mechanism as in the UI testsuite VEE port (see ui_drawing_composite.c) and modify this file accordingly. + */ + +#define UI_DRAWING_IDENTIFIER_ARGB8888_FORMAT 2 // fake identifier to not overlap ui_drawing_composite +#define VG_DRAWING_IDENTIFIER_ARGB8888_FORMAT UI_DRAWING_IDENTIFIER_ARGB8888_FORMAT + +#define UI_DRAWING_ARGB8888_is_drawer CONCAT(UI_DRAWING_is_drawer_, UI_DRAWING_IDENTIFIER_ARGB8888_FORMAT) +#define UI_DRAWING_ARGB8888_getNewImageStrideInBytes CONCAT(UI_DRAWING_getNewImageStrideInBytes_, UI_DRAWING_IDENTIFIER_ARGB8888_FORMAT) +#define VG_DRAWING_ARGB8888_drawPath CONCAT(VG_DRAWING_drawPath_, VG_DRAWING_IDENTIFIER_ARGB8888_FORMAT) + + +bool UI_DRAWING_ARGB8888_is_drawer(jbyte image_format) { + return image_format == MICROUI_IMAGE_FORMAT_ARGB8888; +} + +uint32_t UI_DRAWING_ARGB8888_getNewImageStrideInBytes(jbyte image_format, uint32_t image_width, uint32_t image_height, uint32_t default_stride) { + return UI_DRAWING_getNewImageStrideInBytes(image_format, image_width, image_height, default_stride); +} + +DRAWING_Status VG_DRAWING_ARGB8888_drawPath(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color) { + return VG_DRAWING_drawPath_0(gc, path, x, y, matrix, fillRule, blend, color); +} diff --git a/bsp/projects/microej/ui/src/ui_drawing_bvi.c b/bsp/projects/microej/ui/src/ui_drawing_bvi.c new file mode 100644 index 0000000..9c55471 --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_drawing_bvi.c @@ -0,0 +1,256 @@ +/* + * C + * + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief Implementation of a set of ui_drawing.h drawing functions (MicroUI and Drawing libraries). + * These are implementations over VGLite and the destination buffer format is the BufferedVectorImage + * format (VEE Port specific). When the drawing cannot be performed by the GPU, the stub implementation + * is used insted. + * + * Like ui_drawing_vglite.c, this file just configures the destination buffer and redirects all drawings + * to drawing_vglite.c. The file drawing_vglite.c converts the MicroUI drawing in a path can call a specific + * function to draw the path; it does not perform the drawing itself and let the caller do it. This + * drawing function is specified by ui_drawing_bvi.c to target BufferedVectorImage buffer. + * + * @author MicroEJ Developer Team + * @version 7.0.1 + * @see ui_drawing_vglite.c + */ + +#include "microvg_configuration.h" +#if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include + +#include "ui_drawing_bvi.h" +#include "bvi_vglite.h" +#include "ui_drawing_stub.h" +#include "ui_drawing_vglite_process.h" +#include "ui_drawing_vglite_path.h" +#include "microvg_vglite_helper.h" + +// -------------------------------------------------------------------------------- +// Private functions +// -------------------------------------------------------------------------------- + +static DRAWING_Status _add_path(MICROUI_GraphicsContext* gc, vg_lite_path_t * path, vg_lite_fill_t fill_rule, vg_lite_matrix_t * matrix, vg_lite_blend_t blend, vg_lite_color_t color) { + jint err = BVI_VGLITE_add_draw_path(MAP_BVI_ON_GC(gc), path, fill_rule, matrix, blend, color); + MICROVG_VGLITE_handle_error(gc, err); + return DRAWING_DONE; +} + +static DRAWING_Status _add_clear(MICROUI_GraphicsContext* gc, vg_lite_rectangle_t * rect, vg_lite_color_t color) { + + // Compute the rectangle shape path + vg_lite_path_t shape_vg_path; + vglite_path_rectangle_t rectangle_path; + shape_vg_path.path = &rectangle_path; + shape_vg_path.path_length = sizeof(rectangle_path); + int path_offset = UI_DRAWING_VGLITE_PATH_compute_rectangle(&shape_vg_path, 0, rect->x, rect->y, rect->width, rect->height, true); + + if (0 < path_offset) { + vg_lite_matrix_t matrix; + vg_lite_identity(&matrix); + jint err = BVI_VGLITE_add_draw_path(MAP_BVI_ON_GC(gc), &shape_vg_path, VG_LITE_FILL_EVEN_ODD, &matrix, VG_LITE_BLEND_SRC_OVER, color); + MICROVG_VGLITE_handle_error(gc, err); + } + else { + LLUI_DISPLAY_reportError(gc, DRAWING_LOG_LIBRARY_INCIDENT); + } + return DRAWING_DONE; +} + +// -------------------------------------------------------------------------------- +// ui_drawing.h functions +// (the function names differ according to the index of destination format) +// -------------------------------------------------------------------------------- + +// See the header file for the function documentation +bool UI_DRAWING_BVI_is_drawer(jbyte image_format) { + return BVI_FORMAT == (MICROUI_ImageFormat)image_format; +} + +// See the header file for the function documentation +void UI_DRAWING_BVI_adjustNewImageCharacteristics(jbyte image_format, uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment) { + (void)image_format; + BVI_VGLITE_adjust_new_image_characteristics(width, height, data_size, data_alignment); +} + +// See the header file for the function documentation +void UI_DRAWING_BVI_initializeNewImage(MICROUI_Image* image) { + BVI_VGLITE_initialize_new_image(image); +} + +// See the header file for the function documentation +void UI_DRAWING_BVI_freeImageResources(MICROUI_Image* image) { + BVI_VGLITE_free_resources(image); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY){ + return UI_DRAWING_VGLITE_PROCESS_drawLine(&_add_path, gc, startX, startY, endX, endY); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawHorizontalLine(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y){ + return UI_DRAWING_VGLITE_PROCESS_drawHorizontalLine(&_add_path, gc, x1, x2, y); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawVerticalLine(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2){ + return UI_DRAWING_VGLITE_PROCESS_drawVerticalLine(&_add_path, gc, x, y1, y2); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_fillRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2){ + return UI_DRAWING_VGLITE_PROCESS_fillRectangle(&_add_clear, gc, x1, y1, x2, y2); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + return UI_DRAWING_VGLITE_PROCESS_drawRoundedRectangle(&_add_path, gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_fillRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + return UI_DRAWING_VGLITE_PROCESS_fillRoundedRectangle(&_add_path, gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_VGLITE_PROCESS_drawCircleArc(&_add_path, gc, x, y, diameter, startAngle, arcAngle); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_fillCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_VGLITE_PROCESS_fillCircleArc(&_add_path, gc, x, y, diameter, startAngle, arcAngle); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_VGLITE_PROCESS_drawEllipseArc(&_add_path, gc, x, y, width, height, startAngle, arcAngle); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_fillEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + return UI_DRAWING_VGLITE_PROCESS_fillEllipseArc(&_add_path, gc, x, y, width, height, startAngle, arcAngle); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + return UI_DRAWING_VGLITE_PROCESS_drawCircle(&_add_path, gc, x, y, diameter); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_fillCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + return UI_DRAWING_VGLITE_PROCESS_fillCircle(&_add_path, gc, x, y, diameter); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + return UI_DRAWING_VGLITE_PROCESS_drawEllipse(&_add_path, gc, x, y, width, height); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_fillEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + return UI_DRAWING_VGLITE_PROCESS_fillEllipse(&_add_path, gc, x, y, width, height); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawThickFadedPoint(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade){ + DRAWING_Status status; + if (!UI_DRAWING_VGLITE_IS_COMPATIBLE_FADE(fade)) { + status = UI_DRAWING_STUB_drawThickFadedPoint(gc, x, y, thickness, fade); + } + else { + status = UI_DRAWING_VGLITE_PROCESS_drawThickFadedPoint(&_add_path, gc, x, y, UI_DRAWING_VGLITE_GET_THICKNESS(thickness, fade)); + } + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawThickFadedLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap){ + DRAWING_Status status; + if (!UI_DRAWING_VGLITE_IS_COMPATIBLE_FADE(fade)) { + status = UI_DRAWING_STUB_drawThickFadedLine(gc, startX, startY, endX, endY, thickness, fade, startCap, endCap); + } + else { + status = UI_DRAWING_VGLITE_PROCESS_drawThickFadedLine(&_add_path, gc, startX, startY, endX, endY, UI_DRAWING_VGLITE_GET_THICKNESS(thickness, fade), startCap, endCap); + } + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawThickFadedCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade){ + DRAWING_Status status; + if (!UI_DRAWING_VGLITE_IS_COMPATIBLE_FADE(fade)) { + status = UI_DRAWING_STUB_drawThickFadedCircle(gc, x, y, diameter, thickness, fade); + } + else { + status = UI_DRAWING_VGLITE_PROCESS_drawThickFadedCircle(&_add_path, gc, x, y, diameter, UI_DRAWING_VGLITE_GET_THICKNESS(thickness, fade)); + } + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawThickFadedCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end){ + DRAWING_Status status; + if (!UI_DRAWING_VGLITE_IS_COMPATIBLE_FADE(fade)) { + status = UI_DRAWING_STUB_drawThickFadedCircleArc(gc, x, y, diameter, startAngle, arcAngle, thickness, fade, start, end); + } + else { + status = UI_DRAWING_VGLITE_PROCESS_drawThickFadedCircleArc(&_add_path, gc, x, y, diameter, startAngle, arcAngle, UI_DRAWING_VGLITE_GET_THICKNESS(thickness, fade), start, end); + } + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawThickFadedEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade){ + DRAWING_Status status; + if (!UI_DRAWING_VGLITE_IS_COMPATIBLE_FADE(fade)) { + status = UI_DRAWING_STUB_drawThickFadedEllipse(gc, x, y, width, height, thickness, fade); + } + else { + status = UI_DRAWING_VGLITE_PROCESS_drawThickFadedEllipse(&_add_path, gc, x, y, width, height, UI_DRAWING_VGLITE_GET_THICKNESS(thickness, fade)); + } + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawThickLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness){ + return UI_DRAWING_VGLITE_PROCESS_drawThickLine(&_add_path, gc, startX, startY, endX, endY, thickness); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawThickCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness){ + return UI_DRAWING_VGLITE_PROCESS_drawThickCircle(&_add_path, gc, x, y, diameter, thickness); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawThickEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness){ + return UI_DRAWING_VGLITE_PROCESS_drawThickEllipse(&_add_path, gc, x, y, width, height, thickness); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_BVI_drawThickCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness){ + return UI_DRAWING_VGLITE_PROCESS_drawThickCircleArc(&_add_path, gc, x, y, diameter, startAngle, arcAngle, thickness); +} + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#endif // #if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE diff --git a/bsp/projects/microej/ui/src/ui_drawing_stub.c b/bsp/projects/microej/ui/src/ui_drawing_stub.c new file mode 100644 index 0000000..06d8241 --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_drawing_stub.c @@ -0,0 +1,414 @@ +/* + * C + * + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief Implementation of all drawing functions of ui_drawing_stub.h. + * @author MicroEJ Developer Team + * @version 4.0.1 + * @see ui_drawing_stub.h + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include + +#include "ui_drawing_stub.h" + +// -------------------------------------------------------------------------------- +// Private functions +// -------------------------------------------------------------------------------- + +static inline DRAWING_Status not_implemented(MICROUI_GraphicsContext* gc){ + LLUI_DISPLAY_reportError(gc, DRAWING_LOG_NOT_IMPLEMENTED); + return DRAWING_DONE; +} + +// -------------------------------------------------------------------------------- +// ui_drawing_stub.h functions +// -------------------------------------------------------------------------------- + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_writePixel(MICROUI_GraphicsContext* gc, jint x, jint y){ + (void)gc; + (void)x; + (void)y; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY){ + (void)gc; + (void)startX; + (void)startY; + (void)endX; + (void)endY; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawHorizontalLine(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y){ + (void)gc; + (void)x1; + (void)x2; + (void)y; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawVerticalLine(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2){ + (void)gc; + (void)x; + (void)y1; + (void)y2; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2){ + (void)gc; + (void)x1; + (void)y1; + (void)x2; + (void)y2; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_fillRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2){ + (void)gc; + (void)x1; + (void)y1; + (void)x2; + (void)y2; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + (void)gc; + (void)x; + (void)y; + (void)width; + (void)height; + (void)cornerEllipseWidth; + (void)cornerEllipseHeight; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_fillRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + (void)gc; + (void)x; + (void)y; + (void)width; + (void)height; + (void)cornerEllipseWidth; + (void)cornerEllipseHeight; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + (void)gc; + (void)x; + (void)y; + (void)diameter; + (void)startAngle; + (void)arcAngle; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + (void)gc; + (void)x; + (void)y; + (void)width; + (void)height; + (void)startAngle; + (void)arcAngle; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_fillCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + (void)gc; + (void)x; + (void)y; + (void)diameter; + (void)startAngle; + (void)arcAngle; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_fillEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + (void)gc; + (void)x; + (void)y; + (void)width; + (void)height; + (void)startAngle; + (void)arcAngle; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + (void)gc; + (void)x; + (void)y; + (void)width; + (void)height; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_fillEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + (void)gc; + (void)x; + (void)y; + (void)width; + (void)height; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + (void)gc; + (void)x; + (void)y; + (void)diameter; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_fillCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + (void)gc; + (void)x; + (void)y; + (void)diameter; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + (void)gc; + (void)img; + (void)regionX; + (void)regionY; + (void)width; + (void)height; + (void)x; + (void)y; + (void)alpha; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_copyImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + (void)gc; + (void)img; + (void)regionX; + (void)regionY; + (void)width; + (void)height; + (void)x; + (void)y; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawRegion(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + (void)gc; + (void)regionX; + (void)regionY; + (void)width; + (void)height; + (void)x; + (void)y; + (void)alpha; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawThickFadedPoint(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade){ + (void)gc; + (void)x; + (void)y; + (void)thickness; + (void)fade; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawThickFadedLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap){ + (void)gc; + (void)startX; + (void)startY; + (void)endX; + (void)endY; + (void)thickness; + (void)fade; + (void)startCap; + (void)endCap; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawThickFadedCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade){ + (void)gc; + (void)x; + (void)y; + (void)diameter; + (void)thickness; + (void)fade; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawThickFadedCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end){ + (void)gc; + (void)x; + (void)y; + (void)diameter; + (void)startAngle; + (void)arcAngle; + (void)thickness; + (void)fade; + (void)start; + (void)end; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawThickFadedEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade){ + (void)gc; + (void)x; + (void)y; + (void)width; + (void)height; + (void)thickness; + (void)fade; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawThickLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness){ + (void)gc; + (void)startX; + (void)startY; + (void)endX; + (void)endY; + (void)thickness; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawThickCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness){ + (void)gc; + (void)x; + (void)y; + (void)diameter; + (void)thickness; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawThickEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness){ + (void)gc; + (void)x; + (void)y; + (void)width; + (void)height; + (void)thickness; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawThickCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness){ + (void)gc; + (void)x; + (void)y; + (void)diameter; + (void)startAngle; + (void)arcAngle; + (void)thickness; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawFlippedImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + (void)gc; + (void)img; + (void)regionX; + (void)regionY; + (void)width; + (void)height; + (void)x; + (void)y; + (void)transformation; + (void)alpha; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawRotatedImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + (void)gc; + (void)img; + (void)x; + (void)y; + (void)rotationX; + (void)rotationY; + (void)angle; + (void)alpha; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawRotatedImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + (void)gc; + (void)img; + (void)x; + (void)y; + (void)rotationX; + (void)rotationY; + (void)angle; + (void)alpha; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawScaledImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + (void)gc; + (void)img; + (void)x; + (void)y; + (void)factorX; + (void)factorY; + (void)alpha; + return not_implemented(gc); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_STUB_drawScaledImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + (void)gc; + (void)img; + (void)x; + (void)y; + (void)factorX; + (void)factorY; + (void)alpha; + return not_implemented(gc); +} + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- diff --git a/bsp/projects/microej/ui/src/ui_drawing_vglite.c b/bsp/projects/microej/ui/src/ui_drawing_vglite.c new file mode 100644 index 0000000..54f8bdf --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_drawing_vglite.c @@ -0,0 +1,901 @@ +/* + * C + * + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief Implementation of a set of ui_drawing.h drawing functions (MicroUI and Drawing libraries). + * These are implementations over VGLite and the destination buffer format is the format specified + * in the VEE port. When the drawing cannot be performed by the GPU, the software implementation + * is used insted. + * + * This file just configures the destination buffer and redirects all drawings to drawing_vglite.c. + * The file drawing_vglite.c converts the MicroUI drawing in a path can call a specific function to + * draw the path; it does not perform the drawing itself and let the caller do it. This drawing function + * is specified by ui_drawing_vglite.c to target standard destination buffers (display buffer and all + * MicroUI BufferedImage). + * + * Some MicroUI and Drawing drawing functions are disabled for performance reasons or rendering quality + * reasons. See ui_vglite_configuration.h to force the use of the GPU. + * + * @author MicroEJ Developer Team + * @version 8.0.1 + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include "ui_drawing_vglite.h" +#include "ui_drawing_soft.h" +#include "dw_drawing_soft.h" +#include "ui_image_drawing.h" +#include "ui_drawing_vglite_process.h" + +// -------------------------------------------------------------------------------- +// Private functions +// -------------------------------------------------------------------------------- + +static DRAWING_Status _draw_path(MICROUI_GraphicsContext* gc, vg_lite_path_t * path, vg_lite_fill_t fill_rule, vg_lite_matrix_t * matrix, vg_lite_blend_t blend, vg_lite_color_t color) { + vg_lite_buffer_t* target = UI_VGLITE_configure_destination(gc); + vg_lite_error_t err = vg_lite_draw(target, path, fill_rule, matrix, blend, color); + return UI_VGLITE_post_operation(gc, err); +} + +#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +static DRAWING_Status _clear(MICROUI_GraphicsContext* gc, vg_lite_rectangle_t * rect, vg_lite_color_t color) { + vg_lite_buffer_t* target = UI_VGLITE_configure_destination(gc); + vg_lite_error_t err = vg_lite_clear(target, rect, color); + return UI_VGLITE_post_operation(gc, err); +} + +#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +static DRAWING_Status _blit_rect(MICROUI_GraphicsContext* gc, vg_lite_buffer_t *source, uint32_t *rect, vg_lite_matrix_t *matrix, vg_lite_blend_t blend, vg_lite_color_t color, vg_lite_filter_t filter) { + vg_lite_buffer_t* target = UI_VGLITE_configure_destination(gc); + vg_lite_error_t err = vg_lite_blit_rect(target, source, rect, matrix, blend, color, filter); + return UI_VGLITE_post_operation(gc, err); +} + +static DRAWING_Status _draw_region(MICROUI_GraphicsContext* gc, vg_lite_buffer_t* source, uint32_t* rect, vg_lite_matrix_t* matrix, vg_lite_blend_t blend, vg_lite_color_t color, vg_lite_filter_t filter, uint32_t element_index) { + + vg_lite_buffer_t* target = UI_VGLITE_configure_destination(gc); + DRAWING_Status ret = DRAWING_RUNNING; + + // rect[x,y,w,h] + uint32_t rect_index = element_index + (uint32_t)2; + + // retrieve band's size (width or height) + jint size = rect[rect_index]; + rect[rect_index] = (uint32_t)(matrix->m[element_index][2] - rect[element_index]); + + // go to x + band size + rect[element_index] += size; + matrix->m[element_index][2] = rect[element_index] + rect[rect_index]; + + while (size > 0) { + + // adjust band's size + if (size < rect[rect_index]){ + rect[rect_index] = size; + } + + // adjust src & dest positions + rect[element_index] -= rect[rect_index]; + matrix->m[element_index][2] -= rect[rect_index]; + + size -= rect[rect_index]; + + if (VG_LITE_SUCCESS != vg_lite_blit_rect(target, source, rect, matrix, blend, color, filter)) { + LLUI_DISPLAY_reportError(gc, DRAWING_LOG_LIBRARY_INCIDENT); + ret = DRAWING_DONE; + size = 0; // stop the loop + } + else { + // wakeup task only for the last iteration, otherwise waits the end of the drawing before continue + UI_VGLITE_start_operation(size <= 0); + } + } + + return ret; +} + +// -------------------------------------------------------------------------------- +// ui_drawing.h / ui_drawing_vglite.h functions +// (the function names differ according to the available number of destination formats) +// -------------------------------------------------------------------------------- + +#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_drawLine(gc, startX, startY, endX, endY); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_drawLine(&_draw_path, gc, startX, startY, endX, endY); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawHorizontalLine(MICROUI_GraphicsContext* gc, jint x1, jint x2, jint y){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_drawHorizontalLine(gc, x1, x2, y); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_drawHorizontalLine(&_draw_path, gc, x1, x2, y); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawVerticalLine(MICROUI_GraphicsContext* gc, jint x, jint y1, jint y2){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_drawVerticalLine(gc, x, y1, y2); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_drawVerticalLine(&_draw_path, gc, x, y1, y2); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_fillRectangle(MICROUI_GraphicsContext* gc, jint x1, jint y1, jint x2, jint y2){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_fillRectangle(gc, x1, y1, x2, y2); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_fillRectangle(&_clear, gc, x1, y1, x2, y2); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_drawRoundedRectangle(gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_drawRoundedRectangle(&_draw_path, gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_fillRoundedRectangle(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint cornerEllipseWidth, jint cornerEllipseHeight){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_fillRoundedRectangle(gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_fillRoundedRectangle(&_draw_path, gc, x, y, width, height, cornerEllipseWidth, cornerEllipseHeight); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_drawCircleArc(gc, x, y, diameter, startAngle, arcAngle); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_drawCircleArc(&_draw_path, gc, x, y, diameter, startAngle, arcAngle); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_drawEllipseArc(gc, x, y, width, height, startAngle, arcAngle); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_drawEllipseArc(&_draw_path, gc, x, y, width, height, startAngle, arcAngle); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_fillCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_fillCircleArc(gc, x, y, diameter, startAngle, arcAngle); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_fillCircleArc(&_draw_path, gc, x, y, diameter, startAngle, arcAngle); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_fillEllipseArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jfloat startAngle, jfloat arcAngle){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_fillEllipseArc(gc, x, y, width, height, startAngle, arcAngle); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_fillEllipseArc(&_draw_path, gc, x, y, width, height, startAngle, arcAngle); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_drawEllipse(gc, x, y, width, height); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_drawEllipse(&_draw_path, gc, x, y, width, height); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_fillEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_fillEllipse(gc, x, y, width, height); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_fillEllipse(&_draw_path, gc, x, y, width, height); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_drawCircle(gc, x, y, diameter); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_drawCircle(&_draw_path, gc, x, y, diameter); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_fillCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = UI_DRAWING_SOFT_fillCircle(gc, x, y, diameter); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_fillCircle(&_draw_path, gc, x, y, diameter); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { +#if !defined(LLUI_IMAGE_CUSTOM_FORMATS) + status = UI_DRAWING_SOFT_drawImage(gc, img, regionX, regionY, width, height, x, y, alpha); +#else + status = UI_IMAGE_DRAWING_draw(gc, img, regionX, regionY, width, height, x, y, alpha); +#endif + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + vg_lite_color_t color; + vg_lite_matrix_t matrix; + uint32_t blit_rect[4]; + + vg_lite_buffer_t* source_buffer = UI_DRAWING_VGLITE_PROCESS_prepare_draw_image(gc, img, regionX, regionY, width, height, x, y, alpha, &color, &matrix, blit_rect); + + if (NULL != source_buffer){ + status = _blit_rect(gc, source_buffer, blit_rect, &matrix, VG_LITE_BLEND_SRC_OVER, color, VG_LITE_FILTER_POINT); + } + else { +#if !defined(LLUI_IMAGE_CUSTOM_FORMATS) + status = UI_DRAWING_SOFT_drawImage(gc, img, regionX, regionY, width, height, x, y, alpha); +#else + status = UI_IMAGE_DRAWING_draw(gc, img, regionX, regionY, width, height, x, y, alpha); +#endif + } + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#ifdef VGLITE_USE_GPU_FOR_RGB565_IMAGES + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_copyImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { +#if !defined(LLUI_IMAGE_CUSTOM_FORMATS) + status = UI_DRAWING_SOFT_copyImage(gc, img, regionX, regionY, width, height, x, y); +#else + status = UI_IMAGE_DRAWING_copy(gc, img, regionX, regionY, width, height, x, y); +#endif + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = (img == &gc->image) ? + // have to manage the overlap + UI_DRAWING_VGLITE_drawRegion(gc, regionX, regionY, width, height, x, y, 0xff) + // no overlap: draw image as usual + : UI_DRAWING_VGLITE_drawImage(gc, img, regionX, regionY, width, height, x, y, 0xff); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +#endif // VGLITE_USE_GPU_FOR_RGB565_IMAGES + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawRegion(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { +#if !defined(LLUI_IMAGE_CUSTOM_FORMATS) + status = UI_DRAWING_SOFT_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +#else + status = UI_IMAGE_DRAWING_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +#endif + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + vg_lite_color_t color; + vg_lite_matrix_t matrix; + uint32_t blit_rect[4]; + + vg_lite_buffer_t* source_buffer = UI_DRAWING_VGLITE_PROCESS_prepare_draw_image(gc, &gc->image, regionX, regionY, width, height, x, y, alpha, &color, &matrix, blit_rect); + + if (NULL != source_buffer){ + + if ((y == regionY) && (x > regionX) && (x < (regionX + width))){ + // draw with overlap: cut the drawings in several widths + status = _draw_region(gc, source_buffer, blit_rect, &matrix, VG_LITE_BLEND_SRC_OVER, color, VG_LITE_FILTER_POINT, 0); + } + else if ((y > regionY) && (y < (regionY + height))){ + // draw with overlap: cut the drawings in several heights + status = _draw_region(gc, source_buffer, blit_rect, &matrix, VG_LITE_BLEND_SRC_OVER, color, VG_LITE_FILTER_POINT, 1); + } + else { + // draw in one shot + status = _blit_rect(gc, source_buffer, blit_rect, &matrix, VG_LITE_BLEND_SRC_OVER, color, VG_LITE_FILTER_POINT); + } + } + else { +#if !defined(LLUI_IMAGE_CUSTOM_FORMATS) + status = UI_DRAWING_SOFT_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +#else + status = UI_IMAGE_DRAWING_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +#endif + } + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawThickFadedPoint(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade){ + + DRAWING_Status status; + + if (!UI_DRAWING_VGLITE_IS_COMPATIBLE_FADE(fade) +#ifdef VGLITE_OPTION_TOGGLE_GPU + || !UI_VGLITE_is_hardware_rendering_enabled() +#endif // VGLITE_OPTION_TOGGLE_GPU + ) { + DW_DRAWING_SOFT_drawThickFadedPoint(gc, x, y, thickness, fade); + status = DRAWING_DONE; + } + else { + status = UI_DRAWING_VGLITE_PROCESS_drawThickFadedPoint(&_draw_path, gc, x, y, UI_DRAWING_VGLITE_GET_THICKNESS(thickness, fade)); + } + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawThickFadedLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap){ + + DRAWING_Status status; + + if (!UI_DRAWING_VGLITE_IS_COMPATIBLE_FADE(fade) +#ifdef VGLITE_OPTION_TOGGLE_GPU + || !UI_VGLITE_is_hardware_rendering_enabled() +#endif // VGLITE_OPTION_TOGGLE_GPU + ) { + DW_DRAWING_SOFT_drawThickFadedLine(gc, startX, startY, endX, endY, thickness, fade, startCap, endCap); + status = DRAWING_DONE; + } + else { + status = UI_DRAWING_VGLITE_PROCESS_drawThickFadedLine(&_draw_path, gc, startX, startY, endX, endY, UI_DRAWING_VGLITE_GET_THICKNESS(thickness, fade), startCap, endCap); + } + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawThickFadedCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade){ + + DRAWING_Status status; + + if (!UI_DRAWING_VGLITE_IS_COMPATIBLE_FADE(fade) +#ifdef VGLITE_OPTION_TOGGLE_GPU + || !UI_VGLITE_is_hardware_rendering_enabled() +#endif // VGLITE_OPTION_TOGGLE_GPU + ) { + DW_DRAWING_SOFT_drawThickFadedCircle(gc, x, y, diameter, thickness, fade); + status = DRAWING_DONE; + } + else { + status = UI_DRAWING_VGLITE_PROCESS_drawThickFadedCircle(&_draw_path, gc, x, y, diameter, UI_DRAWING_VGLITE_GET_THICKNESS(thickness, fade)); + } + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawThickFadedCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end){ + + DRAWING_Status status; + + if (!UI_DRAWING_VGLITE_IS_COMPATIBLE_FADE(fade) +#ifdef VGLITE_OPTION_TOGGLE_GPU + || !UI_VGLITE_is_hardware_rendering_enabled() +#endif // VGLITE_OPTION_TOGGLE_GPU + ) { + DW_DRAWING_SOFT_drawThickFadedCircleArc(gc, x, y, diameter, startAngle, arcAngle, thickness, fade, start, end); + status = DRAWING_DONE; + } + else { + status = UI_DRAWING_VGLITE_PROCESS_drawThickFadedCircleArc(&_draw_path, gc, x, y, diameter, startAngle, arcAngle, UI_DRAWING_VGLITE_GET_THICKNESS(thickness, fade), start, end); + } + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawThickFadedEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade){ + + DRAWING_Status status; + + if (!UI_DRAWING_VGLITE_IS_COMPATIBLE_FADE(fade) +#ifdef VGLITE_OPTION_TOGGLE_GPU + || !UI_VGLITE_is_hardware_rendering_enabled() +#endif // VGLITE_OPTION_TOGGLE_GPU + ) { + DW_DRAWING_SOFT_drawThickFadedEllipse(gc, x, y, width, height, thickness, fade); + status = DRAWING_DONE; + } + else { + + status = UI_DRAWING_VGLITE_PROCESS_drawThickFadedEllipse(&_draw_path, gc, x, y, width, height, UI_DRAWING_VGLITE_GET_THICKNESS(thickness, fade)); + } + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawThickLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = DW_DRAWING_SOFT_drawThickLine(gc, startX, startY, endX, endY, thickness); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_drawThickLine(&_draw_path, gc, startX, startY, endX, endY, thickness); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawThickCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = DW_DRAWING_SOFT_drawThickCircle(gc, x, y, diameter, thickness); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_drawThickCircle(&_draw_path, gc, x, y, diameter, thickness); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawThickEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = DW_DRAWING_SOFT_drawThickEllipse(gc, x, y, width, height, thickness); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_drawThickEllipse(&_draw_path, gc, x, y, width, height, thickness); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawThickCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = DW_DRAWING_SOFT_drawThickCircleArc(gc, x, y, diameter, startAngle, arcAngle, thickness); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + status = UI_DRAWING_VGLITE_PROCESS_drawThickCircleArc(&_draw_path, gc, x, y, diameter, startAngle, arcAngle, thickness); + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawFlippedImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = DW_DRAWING_SOFT_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + +#ifndef VGLITE_USE_GPU_FOR_RGB565_IMAGES + // CPU (memcpy) is faster than GPU + if((MICROUI_IMAGE_FORMAT_RGB565 == img->format) && (DRAWING_FLIP_NONE == transformation) && (0xff == alpha)) { + DW_DRAWING_SOFT_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); + status = DRAWING_DONE; + } + else { +#endif // VGLITE_USE_GPU_FOR_RGB565_IMAGES + + bool is_gpu_compatible; + status = UI_DRAWING_VGLITE_PROCESS_drawFlippedImage(&_blit_rect, gc, img, regionX, regionY, width, height, x, y, transformation, alpha, &is_gpu_compatible); + + if (!is_gpu_compatible) { + DW_DRAWING_SOFT_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); + status = DRAWING_DONE; + } + +#ifndef VGLITE_USE_GPU_FOR_RGB565_IMAGES + } +#endif // VGLITE_USE_GPU_FOR_RGB565_IMAGES + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawRotatedImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = DW_DRAWING_SOFT_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + bool is_gpu_compatible; + status = UI_DRAWING_VGLITE_PROCESS_drawRotatedImageNearestNeighbor(&_blit_rect, gc, img, x, y, rotationX, rotationY, angle, alpha, &is_gpu_compatible); + + if (!is_gpu_compatible) { + DW_DRAWING_SOFT_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); + status = DRAWING_DONE; + } + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawRotatedImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = DW_DRAWING_SOFT_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + bool is_gpu_compatible; + status = UI_DRAWING_VGLITE_PROCESS_drawRotatedImageBilinear(&_blit_rect, gc, img, x, y, rotationX, rotationY, angle, alpha, &is_gpu_compatible); + + if (!is_gpu_compatible) { + DW_DRAWING_SOFT_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); + status = DRAWING_DONE; + } + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawScaledImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = DW_DRAWING_SOFT_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + bool is_gpu_compatible; + status = UI_DRAWING_VGLITE_PROCESS_drawScaledImageNearestNeighbor(&_blit_rect, gc, img, x, y, factorX, factorY, alpha, &is_gpu_compatible); + + if (!is_gpu_compatible) { + DW_DRAWING_SOFT_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); + status = DRAWING_DONE; + } + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_drawScaledImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + + DRAWING_Status status; + +#ifdef VGLITE_OPTION_TOGGLE_GPU + if (!UI_VGLITE_is_hardware_rendering_enabled()) { + status = DW_DRAWING_SOFT_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); + } + else { +#endif // VGLITE_OPTION_TOGGLE_GPU + + bool is_gpu_compatible; + status = UI_DRAWING_VGLITE_PROCESS_drawScaledImageBilinear(&_blit_rect, gc, img, x, y, factorX, factorY, alpha, &is_gpu_compatible); + + if (!is_gpu_compatible) { + DW_DRAWING_SOFT_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); + status = DRAWING_DONE; + } + +#ifdef VGLITE_OPTION_TOGGLE_GPU + } +#endif // VGLITE_OPTION_TOGGLE_GPU + + return status; +} + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- diff --git a/bsp/projects/microej/ui/src/ui_drawing_vglite_path.c b/bsp/projects/microej/ui/src/ui_drawing_vglite_path.c new file mode 100644 index 0000000..744a40e --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_drawing_vglite_path.c @@ -0,0 +1,1292 @@ +/* + * C + * + * Copyright 2019-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief MicroEJ MicroUI library low level API: implementation over ui_drawing_vglite_path.h. + * @author MicroEJ Developer Team + * @version 8.0.1 + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include +#include + +#include "ui_drawing_vglite_path.h" +#include "ui_drawing.h" +#include "ui_vglite.h" + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +/* + * Precomputation of tangente for rounded caps + */ +#define CAP_TAN 1.3333333333333333 +#define QUARTER_TAN 0.5522847498307933 + +#define COS_0 1.0 +#define COS_90 0.0 +#define COS_180 -1.0 +#define COS_270 0.0 + +#define SIN_0 0.0 +#define SIN_90 1.0 +#define SIN_180 0.0 +#define SIN_270 -1.0 + +/* + * Constant used to compute the ellipse path + */ + +#define CIRCLE_RADIUS 200 // radius +#define CIRCLE_CP 111 // control point + +#define VGLITE_END_CMD 0 +#define VGLITE_MOVE_CMD 2 +#define VGLITE_LINE_CMD 4 +#define VGLITE_CUBIC_CMD 8 + +// ----------------------------------------------------------------------------- +// Types +// ----------------------------------------------------------------------------- + +/* + * @brief enumeration that identifies the direction of a quarter curve + */ +typedef enum { + __horizontal = 0, // The quarter curve starts horizontaly + __vertical, // The quarter curve starts verticaly +} __axis_t; + +/* + * @brief data to draw a quarter curve + */ +typedef struct { + int x; + int y; +} __quarter_curve_data_t; + +/* + * @brief drawing context + */ +static struct { + uint8_t *path; // Current path buffer + int offset; // Offset in the path buffer + int x; // Current horizontal coordinate + int y; // Current vertical coordinate + float32_t sin; // Last computed sinus + float32_t cos; // Last computed cosinus + float32_t tangent; // Last computed tangent + int center_x; // horizontal coordinate of the current ellipse center + int center_y; // vertical coordinate of the current ellipse center + float32_t control_x; // horizontal coordinate of the last control point + float32_t control_y; // vertical coordinate of the last control point + __axis_t tangent_axis; // Last tangent (if last command was a quarter curve) +} __ctxt; + +// ----------------------------------------------------------------------------- +// Constants +// ----------------------------------------------------------------------------- + +/* + * Circle path + * This path can be used to draw a circle of anysize anywhere with the proper + * transformation matrix + */ +static const int16_t __circle_s16[] = { + VGLITE_MOVE_CMD, // move to (r, 0) + CIRCLE_RADIUS, 0, + + VGLITE_CUBIC_CMD, // cubic to (r, -4/3 * tan(pi/8), 4/3 * tan(pi/8), -r, 0, -r) + CIRCLE_RADIUS, -CIRCLE_CP, CIRCLE_CP, -CIRCLE_RADIUS, 0, -CIRCLE_RADIUS, + + VGLITE_CUBIC_CMD, // cubic to (-4/3 * tan(pi/8), -r, -r, -4/3 * tan(pi/8), -r, 0) + -CIRCLE_CP, -CIRCLE_RADIUS, -CIRCLE_RADIUS, -CIRCLE_CP, -CIRCLE_RADIUS, 0, + + VGLITE_CUBIC_CMD, // cubic to (-r, 4/3 * tan(pi/8), -4/3 * tan(pi/8), r, 0, r) + -CIRCLE_RADIUS, CIRCLE_CP, -CIRCLE_CP, CIRCLE_RADIUS, 0, CIRCLE_RADIUS, + + VGLITE_CUBIC_CMD, // cubic to (4/3 * tan(pi/8), r, r, 4/3 * tan(pi/8), r, 0) + CIRCLE_CP, CIRCLE_RADIUS, CIRCLE_RADIUS, CIRCLE_CP, CIRCLE_RADIUS, 0, + + VGLITE_END_CMD, // end +}; + +/* + * @brief data to draw all the quarter curves + */ +static __quarter_curve_data_t __quarter_curve_data[4] = { + { SIN_0, COS_0, }, + { SIN_90, COS_90, }, + { SIN_180, COS_180, }, + { SIN_270, COS_270, }, +}; + +// ----------------------------------------------------------------------------- +// Internal function definitions +// ----------------------------------------------------------------------------- + +/* + * @brief Sets the center for ellipse drawing + * + * @param[out]: x: the horizontal coordinate of the point to compute + * @param[out]: y: the vertical coordinate of the point to compute + */ +static inline void __set_center(int x, int y) { + __ctxt.center_x = x; + __ctxt.center_y = y; +} + +/* + * @brief Computes the control point to approximate an ellipse arc + * + * @param[out]: x: the horizontal coordinate of the point to compute + * @param[out]: y: the vertical coordinate of the point to compute + * @param[in]: point_angle: the angle of the point to control in radians + * @param[in]: section_angle: the section angle in radians + */ +static inline void __compute_control_point( + float32_t *x, + float32_t *y, + float32_t point_angle, + float32_t section_angle) { + + __ctxt.tangent = 4 * mej_tan_f32(section_angle/4) / 3; + + __ctxt.control_x = __ctxt.tangent * arm_cos_f32(point_angle); + __ctxt.control_y = __ctxt.tangent * arm_sin_f32(point_angle); + *x = __ctxt.control_x; + *y = __ctxt.control_y; +} + +/* + * @brief Initializes the drawing context + * + * @param[in] path: vg_lite path to use for drawing + * @param[in] offset: offset in the vg_lite path + */ +static void __init_drawing(vg_lite_path_t *path, int offset); + +/* + * @brief Computes a "move_to" VGLite command + * + * @param[in] x: x coordinate of the destination + * @param[in] y: y coordinate of the destination + * + * @return: -1 if there is not enough memory in the buffer, otherwise the new path_offset + */ +static int __move_to(int16_t x, int16_t y); + +/* + * @brief Computes a "line_to" VGLite command + * + * @param[in] x: horizontal coordinate of the destination + * @param[in] y: vertical coordinate of the destination + * + * @return: -1 if there is not enough memory in the buffer, otherwise the new path_offset + */ +static int __line_to(int16_t x, int16_t y); + +/* + * @brief Computes a "cubic_to" VGLite command + * + * @param[in] cy1: y coordinate of the first control point + * @param[in] cx2: x coordinate of the second control point + * @param[in] cy2: y coordinate of the second control point + * @param[in] x: x coordinate of the destination + * @param[in] y: y coordinate of the destination + * + * @return: -1 if there is not enough memory in the buffer, otherwise the new path_offset + */ +static int __cubic_to( + int16_t cx1, + int16_t cy1, + int16_t cx2, + int16_t cy2, + int16_t x, + int16_t y); + +/* + * @brief Computes an "end" VGLite command + * + * @return: + * - 1: not enough memory in the path buffer. + * - otherwise: the updated path offset + */ +static int __end(void); + +/* + * @brief Updates a path structure + * + * @param[in,out] path: pointer to the path to update. + * @param[in] first_path: + * - if true: the bounding box is set, the offset is set to zero. + * - otherwise: the bounding box is increased. + * @param[in] last_path: + * - if true: the path is closed calling __end + * and the path_length will be set to the current offset. + * @param[in] left: left most coordinate of the shape. + * @param[in] top: top most coordinate of the shape. + * @param[in] right: right most coordinate of the shape. + * @param[in] bottom: bottom most coordinate of the shape. + * + * @return: + * - 1: not enough memory in the path buffer. + * - otherwise: the updated path offset + */ +static int __update_path(vg_lite_path_t *path, + bool first_path, + bool last_path, + int left, + int top, + int right, + int bottom); + +/* + * @brief Computes an approximation of an ellipse arc + * This computation uses multiple calls to __approximate_ellipse_arc_fragment_to + * The center point stored in the context must be set before calling this function. + * + * @param[in] radius_w: the width radius of the ellipse, sign indicates the direction: + * - if negative, drawing to the left of current point. + * - if positive, drawing to the righ of the current point. + * @param[in] radius_h: the height radius of the ellipse, sign indicates the direction: + * - if negative, drawing to the top of the current point. + * - if positive, drawing to the bottom of the current point. + * @param[in] start_angle: the angle of the start point in radians. + * @param[in] end_angle: the angle of the end point in radians. + * + * @return: + * - 1: not enough memory in the path buffer. + * - otherwise: the updated path offset + */ +static int __approximate_ellipse_arc_to( + int radius_w, + int radius_h, + float32_t start_angle, + float32_t end_angle); + +/* + * @brief Computes an approximation of an ellipse arc fragment + * This computation uses one VGLite cubic_to command * (bezier curves of 3rd order) + * This algorithm is implemented from the following source: + * https://stackoverflow.com/questions/1734745/how-to-create-circle-with-b%c3%a9zier-curves + * The approximation is acceptable if the angle is less than PI/2. + * For ellipse arcs with angles bigger than PI/2, multiple fragments should be computed + * A is the starting point + * B is the ending point + * C and D are the control points + * The computed arc will start from start_angle until end_angle + * The center point stored in the context must be set before calling this function. + * + * @param[in] radius_w: the width radius of the ellipse, sign indicates the direction: + * - if negative, drawing to the left of current point. + * - if positive, drawing to the righ of the current point. + * @param[in] radius_h: the height radius of the ellipse, sign indicates the direction: + * - if negative, drawing to the top of the current point. + * - if positive, drawing to the bottom of the current point. + * @param[in] start_angle: the angle of the start point in radians. + * @param[in] end_angle: the angle of the end point in radians. + * + * @return: + * - 1: not enough memory in the path buffer. + * - otherwise: the updated path offset + */ +static int __approximate_ellipse_arc_fragment_to( + int radius_w, + int radius_h, + float32_t start_angle, + float32_t end_angle); + +/* + * @brief Computes an approximation of a ellipse arc fragment + * This computation uses one VGLite cubic_to command * (bezier curves of 3rd order) + * This algorithm is implemented from the following source: + * https://stackoverflow.com/questions/1734745/how-to-create-circle-with-b%c3%a9zier-curves + * The approximation is acceptable if the angle is less than 90 degrees. + * For ellipse arcs with angles bigger than 90 degrees, multiple fragments should be computed + * A is the starting point + * B is the ending point + * C and D are the control points + * + * @param[in] center_x: the horizontal coordinate of the center of the ellipse + * @param[in] center_y: the vetical coordinate of the center of the ellipse + * @param[in] radius_w: the horizontal radius of the ellipse + * @param[in] radius_h: the vertical radius of the ellipse + * @param[in] start_angle_rad: the angle of the beginning of the ellipse in radians + * @param[in] end_angle_rad: the angle of the end of the ellipse in radians + * @param[in] tangent: the tangent of 1/4 th of the angle (end_angle_rad - start_angle_rad) as described + * by the algorithm (see source mentionned previously), this must be computed by the caller + * as the computation is heavy and can be reused. + * @param[in] revert: + * - 0: angle is drawn from start_angle_rad to end_angle_rad + * - 1: angle is drawn from end_angle_rad to start_angle_rad + * + * @return: + * - 1: not enough memory in the path buffer. + * - otherwise: the updated path offset + */ +static int __approximate_ellipse_arc_fragment( + uint16_t center_x, + uint16_t center_y, + int radius_w, + int radius_h, + float32_t start_angle_rad, + float32_t end_angle_rad, + float32_t tangent, + int revert); + +/* + * @brief Sets the tangent for the quarter curve algorithm. + * + * @param tangent: the orientation (tangent) of the beginning of the curve + */ +static inline void __set_quarter_curve_tangent_axis(__axis_t tangent_axis) { + __ctxt.tangent_axis = tangent_axis; +} + +/* + * @brief Computes a path fragment for a quarter curve from current context position to + * the given destination coordinates + * + * @param x: the horizontal coordinate of the destination point + * @param y: the vertical coordinate of the destination point + * + * @return: + * - 1: not enough memory in the path buffer. + * - otherwise: the updated path offset + */ +static int __quarter_curve_to(int x, int y); + +/* + * @brief Computes a path fragment for multiple quarter curve from current context position. + * This function approximates ellipse quarters with bezier curves. + * + * @param radius_w: the width radius of the curves, the sign indicates the direction to draw: + * - negative, draw to the left of the current point. + * - positive, draw to the right of the current point. + * @param radius_h: the height radius of the curves, the sign indeicates the direction to draw: + * - negative, draw to the top of the current point. + * - positive, draw to the bottom of the current point. + * @param start: the first quarter to draw (between 1 to 4). + * - 0: from 0 to 90 deg + * - 1: from 90 to 180 deg + * - 2: from 180 to 270 deg + * - 3: from 270 to 360 deg + * @param number: the number of quarters to draw + * - positive: clockwise + * - negative: counter clockwise + * + * @return: + * - 1: not enough memory in the path buffer. + * - otherwise: the updated path offset + */ +static int __multiple_quarter_curve_to( + int radius_w, + int radius_h, + int start, + int number); + +/* + * @brief Computes an approximation of an ellipse arc + * + * This computation is based on the function __approximate_ellipse_arc_fragment + * + * The computed path is always centered to (0, 0), the caller can use matrix + * to position the ellipse arc + * + * @param[in]: radius_out_w: the horizontal radius of the outer edge of the ellipse arc + * @param[in]: radius_out_h: the vertical radius of the outer edge of the ellipse arc + * @param[in]: radius_in_w: the horizontal radius of the inner edge of the ellipse arc + * @param[in]: radius_in_h: the vertical radius of the inner edge of the ellipse arc + * @param[in]: start_angle_rad: the angle of the beginning of the ellipse in degrees + * @param[in]: end_angle_rad: the angle of the end of the ellipse in degrees + * @param[in]: caps: the cap representation of the start and the end of the ellipse arc + * This is a bit field that can be manipulated with macros MEJ_VGLITE_PATH_CAPS_XXX, + * MEJ_VGLITE_PATH_SET_CAPS_XXX and MEJ_VGLITE_PATH_GET_CAPS_XXX, + * bits[0-1] represent the cap of the start of the shape, + * bits[2-3] represent the cap of the end of the shape, + * See DRAWING_ENDOFLINE_XXX for caps values + * + * @return: -1 if there is not enough memory in the buffer, otherwise the new path_offset + */ +static int __approximate_ellipse_arc( + int radius_out_w, + int radius_out_h, + int radius_in_w, + int radius_in_h, + float32_t start_angle_rad, + float32_t arc_angle_rad, + int caps); + +/* + * @brief Normalize an angle so that it is in the range [0, 360[ + * + * @param[in] angle_deg: the angle to normalize in degrees + * + * @return: the normalized angle + */ +static float32_t __normalize_angle(float32_t angle_deg); + +// ----------------------------------------------------------------------------- +// ui_drawing_vglite_path.h functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +int UI_DRAWING_VGLITE_PATH_compute_line(vg_lite_path_t *line_shape, int x, int y) { + // Initialize the drawing context + __init_drawing(line_shape, 0); + + int xs; + int ys; + int xi; + int yi; + + if (x >= 0) { + xs = 0; + xi = 1; + } else { + xs = 1; + xi = -1; + } + + if (y >= 0) { + ys = 0; + yi = 1; + } else { + ys = 1; + yi = -1; + } + + const int xe = xs + x + xi; + const int ye = ys + y + yi; + + // Move to beginning + (void)__move_to(xs, ys); + + // Compute edges of the line + (void)__line_to(xs + xi, ys); + (void)__line_to(xe, ye - yi); + (void)__line_to(xe, ye); + (void)__line_to(xe - xi, ye); + (void)__line_to(xs, ys + yi); + + return __update_path(line_shape, true, true, xs, ys, xe, ye); +} + +// See the header file for the function documentation +int UI_DRAWING_VGLITE_PATH_compute_rectangle( + vg_lite_path_t *rectangle_shape, + int path_offset, + int x, int y, + int width, int height, + bool end_path) { + bool first_path = (path_offset == 0); + + // Precompute all necessary coordinates + int left = x; + int right = left + width; + int top = y; + int bottom = top + height; + + // Initialize the drawing context + __init_drawing(rectangle_shape, path_offset); + + // Move to beginning (beginning of top side) + (void)__move_to(left, top); + + // Compute top side + (void)__line_to(right, top); + + // Compute right side + (void)__line_to(right, bottom); + + // Compute bottom side + (void)__line_to(left, bottom); + + // Compute left side + (void)__line_to(left, top); + + return __update_path(rectangle_shape, first_path, end_path, + left, top, right, bottom); +} + +// See the header file for the function documentation +int UI_DRAWING_VGLITE_PATH_compute_rounded_rectangle( + vg_lite_path_t *rounded_rectangle_shape, + int path_offset, + int x, int y, + int width, int height, + int arc_width, int arc_height, + bool end_path) { + bool first_path = (path_offset == 0); + + // Convert diameter to radius + int radius_width = (arc_width <= 0) ? 0 : (arc_width / 2); + int radius_height = (arc_height <= 0) ? 0 : (arc_height / 2); + + // Precompute all necessary coordinates + int left = x; + int right = left + width; + int top = y; + int bottom = top + height; + int left_radius = left + radius_width; + int right_radius = right - radius_width; + int top_radius = top + radius_height; + int bottom_radius = bottom - radius_height; + + // Initialize the drawing context + __init_drawing(rounded_rectangle_shape, path_offset); + + // Move to beginning (beginning of top side) + (void)__move_to(left_radius, top); + + // Compute top side + (void)__line_to(right_radius, top); + + // Compute top right corner + __set_quarter_curve_tangent_axis(__horizontal); + (void)__quarter_curve_to(right, top_radius); + + // Compute right side + (void)__line_to(right, bottom_radius); + + // Compute bottom right corner + (void)__quarter_curve_to(right_radius, bottom); + + // Compute bottom side + (void)__line_to(left_radius, bottom); + + // Compute bottom left corner + (void)__quarter_curve_to(left, bottom_radius); + + // Compute left side + (void)__line_to(left, top_radius); + + // Compute top left corner + (void)__quarter_curve_to(left_radius, top); + + return __update_path(rounded_rectangle_shape, first_path, end_path, + left, top, right, bottom); +} + +// See the header file for the function documentation +int UI_DRAWING_VGLITE_PATH_compute_ellipse_arc( + vg_lite_path_t *ellipse_arc, + int radius_out_w, + int radius_out_h, + int radius_in_w, + int radius_in_h, + float32_t start_angle_degree, + float32_t arc_angle_degree, + bool fill) { + float32_t start_angle; + float32_t end_angle; + float32_t arc_angle; + + arc_angle = MEJ_DEG2RAD(arc_angle_degree); + + start_angle = MEJ_DEG2RAD(start_angle_degree); + end_angle = start_angle + arc_angle; + + // Initialize the drawing context + __init_drawing(ellipse_arc, 0); + + // Move to start + __set_center(0, 0); + __ctxt.x = (int) (radius_out_w * arm_sin_f32(start_angle)); + __ctxt.y = (int) (-radius_out_h * arm_cos_f32(start_angle)); + + (void)__move_to(__ctxt.x, __ctxt.y); + + // Draw outer ellipse + (void)__approximate_ellipse_arc_to(radius_out_w, radius_out_h, start_angle, end_angle); + + if (fill == false) { + // Line to inner ellipse start + (void)__line_to( + (int) (__ctxt.center_x + (__ctxt.sin * radius_in_w)), + (int) (__ctxt.center_y - (__ctxt.cos * radius_in_h))); + + // Draw inner ellipse + (void)__approximate_ellipse_arc_to(radius_in_w, radius_in_h, end_angle, start_angle); + } else { + (void)__line_to(0, 0); + } + + (void)__end(); + + return __update_path(ellipse_arc, true, true, + -radius_out_w, -radius_out_h, radius_out_w, radius_out_h); +} + +// See the header file for the function documentation +int UI_DRAWING_VGLITE_PATH_compute_ellipse( + vg_lite_path_t *ellipse_shape, + int path_offset, + int radius_w, + int radius_h, + bool end_path) { + bool first_path = (path_offset == 0); + + // Initialize the drawing context + __init_drawing(ellipse_shape, path_offset); + + // Move to top + (void)__move_to(0, -radius_h); + + (void)__multiple_quarter_curve_to(radius_w, radius_h, 0, 4); + + return __update_path(ellipse_shape, first_path, end_path, + -radius_w, -radius_h, radius_w, radius_h); +} + +// See the header file for the function documentation +int UI_DRAWING_VGLITE_PATH_compute_filled_ellipse( + vg_lite_path_t *point_shape, + int radius_w, + int radius_h, + vg_lite_matrix_t *matrix) { + + // cppcheck-suppress [misra-c2012-11.8] cast to (void *) is valid + point_shape->path = (void *) __circle_s16; + vg_lite_float_t scale_w = (float32_t) radius_w / CIRCLE_RADIUS; + vg_lite_float_t scale_h = (float32_t) radius_h / CIRCLE_RADIUS; + + vg_lite_scale(scale_w, scale_h, matrix); + + point_shape->path_length = sizeof(__circle_s16); + + return __update_path(point_shape, true, false, + -CIRCLE_RADIUS, + -CIRCLE_RADIUS, + +CIRCLE_RADIUS, + +CIRCLE_RADIUS); +} + +// See the header file for the function documentation +int UI_DRAWING_VGLITE_PATH_compute_thick_shape_line( + vg_lite_path_t *thick_line_shape, + int x, + int y, + int thickness, + int caps, + vg_lite_matrix_t *matrix) { + int length; + int top; + int bottom; + int cap; + + // Compute the length of the line: sqrt(dx^2 + dy^2) + length = (int) (mej_sqrt_f32((x*x) + (y*y)) + DRAWING_SCALE_FACTOR); + + // Compute line angle with x axis + vg_lite_translate(1, 1, matrix); + vg_lite_rotate(MEJ_RAD2DEG(atan2(y, x)), matrix); + vg_lite_translate(-1, -1, matrix); + + int half_thickness = thickness / 2; + top = -half_thickness + 1; + bottom = half_thickness + 1; + + // Initialize the drawing context + __init_drawing(thick_line_shape, 0); + + // Move to top + (void)__move_to(0, top); + + // Line to upper end side + (void)__line_to(length, top); + + cap = MEJ_VGLITE_PATH_GET_CAPS_END(caps); + switch(cap) { + case DRAWING_ENDOFLINE_ROUNDED:{ + // Cubics for end cap + __set_quarter_curve_tangent_axis(__horizontal); + (void)__quarter_curve_to(length + half_thickness, 0); + (void)__quarter_curve_to(length, bottom); + break; + } + case DRAWING_ENDOFLINE_NONE: + case DRAWING_ENDOFLINE_PERPENDICULAR:{ + // Compute line cap + (void)__line_to(length, bottom); + break; + } + default: + UI_VGLITE_IMPL_error(false, "Unknown cap: %d", cap); + break; + } + + // Line to bottom origin + (void)__line_to(0, bottom); + + // Cubics for start cap + cap = MEJ_VGLITE_PATH_GET_CAPS_START(caps); + switch(cap) { + case DRAWING_ENDOFLINE_ROUNDED:{ + // Cubics for end cap + __set_quarter_curve_tangent_axis(__horizontal); + (void)__quarter_curve_to(-half_thickness, 0); + (void)__quarter_curve_to(0, top); + break; + } + case DRAWING_ENDOFLINE_NONE: + case DRAWING_ENDOFLINE_PERPENDICULAR:{ + // Compute line cap + (void)__line_to(0, top); + break; + } + default: + UI_VGLITE_IMPL_error(false, "Unknown cap: %d", cap); + break; + } + + return __update_path(thick_line_shape, true, true, + -half_thickness, top, length + half_thickness, bottom); +} + +// See the header file for the function documentation +int UI_DRAWING_VGLITE_PATH_compute_thick_shape_ellipse_arc( + vg_lite_path_t *thick_ellipse_arc_shape, + int diameter_w, + int diameter_h, + int thickness, + float32_t start_angle_deg, + float32_t arc_angle_deg, + int caps) { + int path_length; + + float32_t l_arc_angle_deg = arc_angle_deg; + float32_t l_start_angle_deg = start_angle_deg; + int l_caps = caps; + + if (l_arc_angle_deg < 0) { + // invert start angle and end angle + l_start_angle_deg += l_arc_angle_deg; + l_arc_angle_deg = -l_arc_angle_deg; + int cap1 = MEJ_VGLITE_PATH_GET_CAPS_START(l_caps); + int cap2 = MEJ_VGLITE_PATH_GET_CAPS_END(l_caps); + l_caps = 0; + l_caps |= MEJ_VGLITE_PATH_SET_CAPS_START(cap2); + l_caps |= MEJ_VGLITE_PATH_SET_CAPS_END(cap1); + } + + if (l_arc_angle_deg > 360) { + l_arc_angle_deg = 360; + } + l_start_angle_deg = __normalize_angle(l_start_angle_deg); + + float32_t start_angle_rad = MEJ_DEG2RAD(l_start_angle_deg); + float32_t arc_angle_rad = MEJ_DEG2RAD(l_arc_angle_deg); + + int radius_out_w = (diameter_w + thickness)/2; + int radius_out_h = (diameter_h + thickness)/2; + int radius_in_w = ((diameter_w - thickness)/2) - 1; + int radius_in_h = ((diameter_h - thickness)/2) - 1; + + // Initialize the drawing context + __init_drawing(thick_ellipse_arc_shape, 0); + + path_length = __approximate_ellipse_arc( + radius_out_w, + radius_out_h, + radius_in_w, + radius_in_h, + start_angle_rad, + arc_angle_rad, + l_caps); + + thick_ellipse_arc_shape->path_length = path_length; + + return __update_path(thick_ellipse_arc_shape, true, true, + -radius_out_w, + -radius_out_h, + +radius_out_w, + +radius_out_h); +} + +// ----------------------------------------------------------------------------- +// Internal functions +// ----------------------------------------------------------------------------- + +// See the section 'Internal function definitions' for the function documentation +static void __init_drawing(vg_lite_path_t *path, int offset) { + __ctxt.path = path->path; + __ctxt.offset = offset; +} + +// See the section 'Internal function definitions' for the function documentation +static int __move_to(int16_t x, int16_t y) { + uint8_t *path = __ctxt.path; + + // cppcheck-suppress [misra-c2012-11.3] cast to (path_move_to_s16_t *) is valid + path_move_to_s16_t *move_to = (path_move_to_s16_t *) &path[__ctxt.offset]; + + move_to->cmd = VGLITE_MOVE_CMD; + move_to->x = x; + move_to->y = y; + + __ctxt.x = x; + __ctxt.y = y; + __ctxt.offset += (int)MEJ_VGLITE_PATH_MOVE_TO_LENGTH(s16_t); + + return __ctxt.offset; +} + +// See the section 'Internal function definitions' for the function documentation +static int __line_to(int16_t x, int16_t y) { + // cppcheck-suppress [misra-c2012-11.3] cast to (path_line_to_s16_t *) is valid + path_line_to_s16_t *line_to = (path_line_to_s16_t *) &__ctxt.path[__ctxt.offset]; + + line_to->cmd = VGLITE_LINE_CMD; + line_to->x = x; + line_to->y = y; + + __ctxt.x = x; + __ctxt.y = y; + __ctxt.offset += (int)MEJ_VGLITE_PATH_LINE_TO_LENGTH(s16_t); + + return __ctxt.offset; +} + +// See the section 'Internal function definitions' for the function documentation +static int __quarter_curve_to(int x, int y) { + int radius_h = x - __ctxt.x; + int radius_v = y - __ctxt.y; + int control_h = (int) (QUARTER_TAN * radius_h); + int control_v = (int) (QUARTER_TAN * radius_v); + int c1_x; + int c1_y; + int c2_x; + int c2_y; + + if (__horizontal == __ctxt.tangent_axis) { + c1_x = __ctxt.x + control_h; + c1_y = __ctxt.y; + + c2_x = x; + c2_y = y - control_v; + + __ctxt.tangent_axis = __vertical; + } else { + c1_x = __ctxt.x; + c1_y = __ctxt.y + control_v; + + c2_x = x - control_h; + c2_y = y; + + __ctxt.tangent_axis = __horizontal; + } + + // Start tangeant to horizontal + (void)__cubic_to(c1_x, c1_y, c2_x, c2_y, x, y); + + __ctxt.x = x; + __ctxt.y = y; + + return __ctxt.offset; +} + +// See the section 'Internal function definitions' for the function documentation +static int __multiple_quarter_curve_to( + int radius_w, + int radius_h, + int start, + int number) { + int data_idx; + + data_idx = start; + int l_number = number; + int l_radius_w = radius_w; + int l_radius_h = radius_h; + + if (l_number < 0) { + l_number = -l_number; + + if (1 == (data_idx & 1)) { + l_radius_h = -l_radius_h; + } else { + l_radius_w = -l_radius_w; + } + } + + if (1 == (data_idx & 1)) { + __set_quarter_curve_tangent_axis(__vertical); + } else { + __set_quarter_curve_tangent_axis(__horizontal); + } + + // Compute center + __ctxt.center_x = __ctxt.x - (l_radius_w * __quarter_curve_data[data_idx & (4 - 1)].x); + __ctxt.center_y = __ctxt.y + (l_radius_h * __quarter_curve_data[data_idx & (4 - 1)].y); + + while (0 != l_number) { + data_idx = (data_idx + 1) & (4 - 1); + + int next_x = __ctxt.center_x + (l_radius_w * __quarter_curve_data[data_idx & (4 - 1)].x); + int next_y = __ctxt.center_y - (l_radius_h * __quarter_curve_data[data_idx & (4 - 1)].y); + + (void)__quarter_curve_to(next_x, next_y); + --l_number; + } + + return __ctxt.offset; +} + +// See the section 'Internal function definitions' for the function documentation +static int __approximate_ellipse_arc( + int radius_out_w, + int radius_out_h, + int radius_in_w, + int radius_in_h, + float32_t start_angle_rad, + float32_t arc_angle_rad, + int caps) { + + // Number of sections per curve. + // CircleArc approximation from Bezier curves is acceptable if the arc angle is less than 90 degrees. + // If the caller require and arc angle bigger than 90 degrees, + // the curve should be splited in sections of less than 90 degrees. + int nb_sections = (int) ceil(arc_angle_rad / (PI / 2)); + + // angle of one section + float32_t section_angle = arc_angle_rad / nb_sections; + + float32_t cos_start_angle = arm_cos_f32(start_angle_rad); + float32_t sin_start_angle = arm_sin_f32(start_angle_rad); + float32_t cos_end_angle = arm_cos_f32(start_angle_rad + arc_angle_rad); + float32_t sin_end_angle = arm_sin_f32(start_angle_rad + arc_angle_rad); + + float32_t tangent = 4 * mej_tan_f32(section_angle/4) / 3; + + // Compute outside start point + int16_t out_start_x = (int16_t) (+radius_out_w * cos_start_angle); + int16_t out_start_y = (int16_t) (-radius_out_h * sin_start_angle); + + // Compute inside start point + int16_t in_start_x = (int16_t) (+radius_in_w * cos_start_angle); + int16_t in_start_y = (int16_t) (-radius_in_h * sin_start_angle); + + // Compute outside end point + int16_t out_end_x = (int16_t) (+radius_out_w * cos_end_angle); + int16_t out_end_y = (int16_t) (-radius_out_h * sin_end_angle); + + // Compute inside end point + int16_t in_end_x = (int16_t) (+radius_in_w * cos_end_angle); + int16_t in_end_y = (int16_t) (-radius_in_h * sin_end_angle); + + // Move to beginning + (void)__move_to(out_start_x, out_start_y); + + // Compute first (going) curve + for (int i = 0; i < nb_sections; i++) { + float32_t section_start_angle = start_angle_rad + (i * section_angle); + float32_t section_end_angle = start_angle_rad + (i+1) * section_angle; + (void)__approximate_ellipse_arc_fragment( + 0, 0, + radius_out_w, radius_out_h, + section_start_angle, section_end_angle, tangent, 0); + } + + // Compute end cap + int cap = MEJ_VGLITE_PATH_GET_CAPS_END(caps); + switch(cap) { + case DRAWING_ENDOFLINE_ROUNDED:{ + // Compute rounded cap + float32_t cap_start_angle = start_angle_rad + arc_angle_rad; + float32_t cap_end_angle = start_angle_rad + arc_angle_rad + PI; + uint16_t cap_x = (in_end_x + out_end_x) / 2; + uint16_t cap_y = (in_end_y + out_end_y) / 2; + // FIXME radius should depend on position of start/end points + int cap_radius = (radius_out_w - radius_in_w) / 2; + (void)__approximate_ellipse_arc_fragment( + cap_x, cap_y, + (uint16_t)cap_radius, (uint16_t)cap_radius, + cap_start_angle, cap_end_angle, CAP_TAN, 0); + break; + } + case DRAWING_ENDOFLINE_NONE: + case DRAWING_ENDOFLINE_PERPENDICULAR:{ + // Compute line cap + (void)__line_to(in_end_x, in_end_y); + break; + } + default: + UI_VGLITE_IMPL_error(false, "Unknown cap: %d", cap); + break; + } + + // Compute second (return) curve + for (int i = 0; i < nb_sections; i++) { + float32_t section_start_angle = start_angle_rad + (nb_sections-1-i) * section_angle; + float32_t section_end_angle = start_angle_rad + (nb_sections-i) * section_angle; + (void)__approximate_ellipse_arc_fragment( + 0, 0, radius_in_w, radius_in_h, + section_start_angle, section_end_angle, tangent, 1); + } + + // Compute start cap + cap = MEJ_VGLITE_PATH_GET_CAPS_START(caps); + switch(cap) { + case DRAWING_ENDOFLINE_ROUNDED:{ + // Compute rounded cap + float32_t cap_start_angle = start_angle_rad + PI; + float32_t cap_end_angle = start_angle_rad; + uint16_t cap_x = (in_start_x + out_start_x) / 2; + uint16_t cap_y = (in_start_y + out_start_y) / 2; + // FIXME radius should depend on position of start/end points + int cap_radius = (radius_out_w - radius_in_w) / 2; + (void)__approximate_ellipse_arc_fragment( + cap_x, cap_y, + (uint16_t)cap_radius, (uint16_t)cap_radius, + cap_start_angle, cap_end_angle, CAP_TAN, 0); + break; + } + case DRAWING_ENDOFLINE_NONE: + case DRAWING_ENDOFLINE_PERPENDICULAR: + // Compute line cap + (void)__line_to(out_start_x, out_start_y); + break; + default: + UI_VGLITE_IMPL_error(false, "Unknown cap: %d", cap); + break; + } + + // End path + return __end(); +} + +// See the section 'Internal function definitions' for the function documentation +static int __approximate_ellipse_arc_to( + int radius_w, + int radius_h, + float32_t start_angle, + float32_t end_angle) { + float32_t start_angle_temp; + float32_t end_angle_temp; + float32_t arc_angle; + float32_t arc_angle_temp; + float32_t arc_angle_abs; + + arc_angle = end_angle - start_angle; + + start_angle_temp = start_angle; + + arc_angle_abs = MEJ_ABS(arc_angle); + + while (arc_angle_abs > 0) { + arc_angle_temp = end_angle - start_angle_temp; + arc_angle_temp = MEJ_BOUNDS(arc_angle_temp, -(PI/2), +(PI/2)); + end_angle_temp = start_angle_temp + arc_angle_temp; + + (void)__approximate_ellipse_arc_fragment_to( + radius_w, radius_h, + start_angle_temp, + end_angle_temp); + + start_angle_temp += arc_angle_temp; + + arc_angle_abs -= PI/2; + } + + return __ctxt.offset; +} + +// See the section 'Internal function definitions' for the function documentation +static int __approximate_ellipse_arc_fragment_to( + int radius_w, + int radius_h, + float32_t start_angle, + float32_t end_angle) { + // End point angle + float32_t section_angle; + float32_t temp_x; + float32_t temp_y; + + // End point coordinates + int end_x; + int end_y; + + // Control point 1 coordinates + int c1_x; + int c1_y; + + // Control point 2 coordinates + int c2_x; + int c2_y; + + section_angle = end_angle - start_angle; + + // Compute start point + __compute_control_point( + &temp_x, &temp_y, + start_angle, + section_angle); + + c1_x = __ctxt.x + (int) (temp_x * radius_w); + c1_y = __ctxt.y + (int) (temp_y * radius_h); + + // Compute end point + __ctxt.sin = arm_sin_f32(end_angle); + __ctxt.cos = arm_cos_f32(end_angle); + + end_x = (int) (__ctxt.center_x + (radius_w * __ctxt.sin)); + end_y = (int) (__ctxt.center_y + (radius_h * -__ctxt.cos)); + + __compute_control_point( + &temp_x, &temp_y, + end_angle, + -section_angle); + + c2_x = end_x + (int) (temp_x * radius_w); + c2_y = end_y + (int) (temp_y * radius_h); + + return __cubic_to(c1_x, c1_y, c2_x, c2_y, end_x, end_y); +} + +// See the section 'Internal function definitions' for the function documentation +static int __approximate_ellipse_arc_fragment( + uint16_t center_x, uint16_t center_y, + int radius_w, int radius_h, + float32_t start_angle_rad, + float32_t end_angle_rad, + float32_t tangent, + int revert) { + float32_t tx; + float32_t ty; + + // Compute start point A1 & A2 + int16_t Ax = (int16_t) (radius_w * arm_cos_f32(start_angle_rad)); + int16_t Ay = (int16_t) (radius_h * -arm_sin_f32(start_angle_rad)); // minus because y axis is inverted (0,0 is top left) + + // Compute end point B1 & B2 + int16_t Bx = (int16_t) (radius_w * arm_cos_f32(end_angle_rad)); + int16_t By = (int16_t) (radius_h * -arm_sin_f32(end_angle_rad)); + + // Compute control point C + tx = tangent * arm_cos_f32(start_angle_rad + (PI/2)); + ty = tangent * -arm_sin_f32(start_angle_rad + (PI/2)); + + int16_t Cx = (int16_t) (Ax + (radius_w * tx)); + int16_t Cy = (int16_t) (Ay + (radius_h * ty)); + + // Compute control point D + tx = tangent * arm_cos_f32(end_angle_rad - (PI/2)); + ty = tangent * -arm_sin_f32(end_angle_rad - (PI/2)); + + int16_t Dx = (int16_t) (Bx + (radius_w * tx)); + int16_t Dy = (int16_t) (By + (radius_h * ty)); + + Ax += (int16_t)center_x; + Ay += (int16_t)center_y; + Bx += (int16_t)center_x; + By += (int16_t)center_y; + Cx += (int16_t)center_x; + Cy += (int16_t)center_y; + Dx += (int16_t)center_x; + Dy += (int16_t)center_y; + + // Compute path + return (revert == 0) ? + __cubic_to(Cx, Cy, Dx, Dy, Bx, By) : + __cubic_to(Dx, Dy, Cx, Cy, Ax, Ay); +} + +// See the section 'Internal function definitions' for the function documentation +int __cubic_to( + int16_t cx1, + int16_t cy1, + int16_t cx2, + int16_t cy2, + int16_t x, + int16_t y) { + // cppcheck-suppress [misra-c2012-11.3] cast to (path_cubic_to_s16_t *) is valid + path_cubic_to_s16_t *cubic_to = (path_cubic_to_s16_t *) &__ctxt.path[__ctxt.offset]; + + cubic_to->cmd = VGLITE_CUBIC_CMD; + cubic_to->cx1 = cx1; // control point 1 + cubic_to->cy1 = cy1; // control point 1 + cubic_to->cx2 = cx2; // control point 2 + cubic_to->cy2 = cy2; // control point 2 + cubic_to->x = x; // curve end + cubic_to->y = y; // curve end + + __ctxt.x = x; + __ctxt.y = y; + __ctxt.offset += (int)MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(s16_t); + + return __ctxt.offset; +} + +// See the section 'Internal function definitions' for the function documentation +int __end(void) { + // cppcheck-suppress [misra-c2012-11.3] cast to (path_end_s16_t *) is valid + path_end_s16_t *end = (path_end_s16_t *) &__ctxt.path[__ctxt.offset]; + end->cmd = VGLITE_END_CMD; + + __ctxt.offset += (int)MEJ_VGLITE_PATH_END_LENGTH(s16_t); + + return __ctxt.offset; +} + +// See the section 'Internal function definitions' for the function documentation +int __update_path(vg_lite_path_t *path, + bool first_path, + bool last_path, + int left, + int top, + int right, + int bottom) { + + if (first_path) { + // use VGLite API to reset the path + int32_t path_length = path->path_length; + void *path_data = path->path; + vg_lite_init_path( + path, + VG_LITE_S16, + VG_LITE_HIGH, + path_length, + path_data, + left, + top, + right, + bottom + ); + path->path_type = VG_LITE_DRAW_FILL_PATH; + } + else { + // not first path and maybe not the last one + path->bounding_box[0] = (int) MEJ_MIN(path->bounding_box[0], left); + path->bounding_box[1] = (int) MEJ_MIN(path->bounding_box[1], top); + path->bounding_box[2] = (int) MEJ_MAX(path->bounding_box[2], right); + path->bounding_box[3] = (int) MEJ_MAX(path->bounding_box[3], bottom); + } + + if (last_path) { + (void)__end(); + path->path_length = __ctxt.offset; + } + + return __ctxt.offset; +} + +// See the section 'Internal function definitions' for the function documentation +static float32_t __normalize_angle(float32_t angle) { + float32_t l_angle = fmod(angle, 360); + return (l_angle >= 0) ? l_angle : (l_angle + 360); +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- diff --git a/bsp/projects/microej/ui/src/ui_drawing_vglite_process.c b/bsp/projects/microej/ui/src/ui_drawing_vglite_process.c new file mode 100644 index 0000000..c828af2 --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_drawing_vglite_process.c @@ -0,0 +1,1563 @@ +/* + * C + * + * Copyright 2019-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief MicroEJ MicroUI library low level API: implementation of ui_drawing_vglite_process.h. + * @author MicroEJ Developer Team + * @version 8.0.1 + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include + +#include "ui_drawing_vglite_process.h" +#include "ui_drawing_vglite_path.h" + +// ----------------------------------------------------------------------------- +// Types +// ----------------------------------------------------------------------------- + +/* + * @brief Variable to store the vglite pathes during the GPU computation. + * + * MicroUI design must ensure that only one computation is done at a time. + */ +static union { + vglite_path_line_t line; // line + vglite_path_thick_shape_line_t thick_shape_line; // thick shape line + vglite_path_ellipse_t ellipse[2]; // ellipse (in & out) + vglite_path_ellipse_arc_t ellipse_arc; // ellipse arc + vglite_path_rounded_rectangle_t rounded_rectangle[2]; // round rect (in & out) + vglite_path_thick_ellipse_arc_t thick_ellipse_arc; // anti aliased ellipse arc +} __shape_paths; + +// ----------------------------------------------------------------------------- +// Global Variables +// ----------------------------------------------------------------------------- + +/* + * @brief Unique path used to render the shape (there is only one shape to render at any time). + */ +static vg_lite_path_t shape_vg_path; + +/* + * @brief Variable to target a vglite source buffer (there is only one source at any time) + */ +static vg_lite_buffer_t source_buffer; + +// ----------------------------------------------------------------------------- +// Internal function definitions +// ----------------------------------------------------------------------------- + +/* + * @brief Draws an ellipse arc covering the square specified by its diameter. + * See DRAWING_impl.h for more information + * + * @param[in] gc: the MicroUI GraphicsContext target. + * @param[in] x: the x coordinate of the upper-left corner of the square where the ellipse arc is drawn + * @param[in] y: the y coordinate of the upper-left corner of the square where the ellipse arc is drawn + * @param[in] diameter_w: the horizontal diameter of the ellipse arc to draw + * @param[in] diameter_h: the vertical diameter of the ellipse arc to draw + * @param[in] start_angle_deg: the beginning angle of the arc to draw + * @param[in] arc_angle_deg: the angular extent of the arc from start_angle_deg + * @param[in] fill: the flag indicating if the ellipse arc will be filled + * - true: the ellipse arc will be filled + * - false: the ellipse arc will not be filled + * + * @return the drawing status. + */ +static DRAWING_Status __draw_ellipse_arc( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + int x, + int y, + int diameter_w, + int diameter_h, + float start_angle, + float arc_angle, + bool fill); + +/* + * @brief Draws a ellipse covering the square specified by its diameter. + * See DRAWING_impl.h for more information + * + * @param[in] gc: the MicroUI GraphicsContext target. + * @param[in] x: the x coordinate of the upper-left corner of the square where the ellipse is drawn + * @param[in] y: the y coordinate of the upper-left corner of the square where the ellipse is drawn + * @param[in] diameter_out_w: the horizontal outer diameter of the ellipse to draw + * @param[in] diameter_out_h: the vertical outer diameter of the ellipse to draw + * @param[in] diameter_in_w: the horizontal inner diameter of the ellipse to draw + * @param[in] diameter_in_h: the vertical inner diameter of the ellipse to draw + * + * @return the drawing status. + */ +static DRAWING_Status __draw_ellipse( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + float x, + float y, + int diameter_out_w, + int diameter_out_h, + int diameter_in_w, + int diameter_in_h); + +/* + * @brief Fills a ellipse covering the square specified by its diameter. + * See DRAWING_impl.h for more information + * + * @param[in] gc: the MicroUI GraphicsContext target. + * @param[in] x: the x coordinate of the upper-left corner of the square where the ellipse is drawn + * @param[in] y: the y coordinate of the upper-left corner of the square where the ellipse is drawn + * @param[in] diameter_w: the horizontal diameter of the ellipse to draw + * @param[in] diameter_h: the vertical diameter of the ellipse to draw + * + * @return the drawing status. + */ +static DRAWING_Status __fill_ellipse( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + float x, + float y, + int diameter_w, + int diameter_h); + +/* + * @brief Draws a line between two points + * See DRAWING_impl.h for more information + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] xs: the horizontal coordinate of the start of the line + * @param[in] ys: the vertical coordinate of start of the line + * @param[in] xe: the horizontal coordinate of the end of the line + * @param[in] ye: the vertical coordinate of end of the line + * + * @return the drawing status. + */ +static DRAWING_Status __draw_line( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + int xs, + int ys, + int xe, + int ye); + +/* + * @brief Draws a thick line between two points + * See DRAWING_impl.h for more information + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] xs: the horizontal coordinate of the start of the line + * @param[in] ys: the vertical coordinate of start of the line + * @param[in] xe: the horizontal coordinate of the end of the line + * @param[in] ye: the vertical coordinate of end of the line + * @param[in] thickness: the line thickness. + * @param[in] start cap representation of start of the line + * @param[in] end cap representation of end of the line + * + * @return the drawing status. + */ +static DRAWING_Status __thick_line( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + int xs, + int ys, + int xe, + int ye, + int thickness, + DRAWING_Cap start, + DRAWING_Cap end); + +/* + * @brief Draws a thick arc covering the square specified by its diameter. + * See dw_drawing.h for more information + * + * @param[in] gc: the MicroUI GraphicsContext target. + * @param[in] x: the x coordinate of the upper-left corner of the square where the arc is drawn + * @param[in] y: the y coordinate of the upper-left corner of the square where the arc is drawn + * @param[in] diameter_w: the horizontal diameter of the ellipse arc to draw + * @param[in] diameter_h: the vertical diameter of the ellipse arc to draw + * @param[in] start_angle_deg: the beginning angle of the arc to draw + * @param[in] arc_angle_deg: the angular extent of the arc from start_angle_deg + * @param[in] thickness: the arc thickness. + * @param[in] start: cap representation of start of shape + * @param[in] end: cap representation of end of shape + * + * @return the drawing status. + */ +static DRAWING_Status __draw_thick_shape_ellipse_arc( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + int x, + int y, + int diameter_w, + int diameter_h, + float start_angle_deg, + float arc_angle, + int thickness, + DRAWING_Cap start, + DRAWING_Cap end); + +/* + * @brief Rotates an image using the GPU + * + * @param[in] gc: Graphics context where to draw + * @param[in] img: Source image to draw + * @param[in] src: Source buffer + * @param[in] x: Horizontal coordinate of the image reference anchor top-left point. + * @param[in] y: Vertical coordinate of the image reference anchor top-left point. + * @param[in] xRotation: Horizontal coordinate of the rotation center + * @param[in] yRotation: Vertical coordinate of the rotation center + * @param[in] angle: Angle that must be used to rotate the image + * @param[in] alpha: The opacity level to apply while drawing the rotated image + * @param[in] filter: Quality of drawing. + * + * @return The drawing status. + */ +static DRAWING_Status __rotate_image( + UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, + MICROUI_GraphicsContext* gc, + MICROUI_Image* img, + vg_lite_buffer_t* src, + int x, + int y, + int xRotation, + int yRotation, + float angle_deg, + int alpha, + vg_lite_filter_t filter); + +/* + * @brief Scales an image using the GPU + * + * @param[in] gc: Graphics context where to draw. + * @param[in] img: Source image to draw. + * @param[in] src: Source buffer + * @param[in] x: Horizontal coordinate of the image reference anchor top-left point. + * @param[in] y: Vertical coordinate of the image reference anchor top-left point. + * @param[in] factorX: Horizontal scaling factor. + * @param[in] yRotation: Vertical scaling factor. + * @param[in] alpha: The opacity level to apply while drawing the image + * @param[in] filter: Quality of drawing. + * + * @return The drawing status. + */ +static DRAWING_Status __scale_image( + UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, + MICROUI_GraphicsContext* gc, + MICROUI_Image* img, + vg_lite_buffer_t* src, + int x, + int y, + float factorX, + float factorY, + int alpha, + vg_lite_filter_t filter); + +// ----------------------------------------------------------------------------- +// Public functions +// ----------------------------------------------------------------------------- + +// See the section 'Internal function definitions' for the function documentation +vg_lite_buffer_t* UI_DRAWING_VGLITE_PROCESS_prepare_draw_image(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x_src, jint y_src, jint width, jint height, jint x_dest, jint y_dest, jint alpha, vg_lite_color_t* color, vg_lite_matrix_t* matrix, uint32_t* blit_rect){ + + vg_lite_buffer_t* ret; + + if(UI_VGLITE_configure_source(&source_buffer, img) && UI_VGLITE_enable_vg_lite_scissor_region(gc, x_dest, y_dest, x_dest + width - 1, y_dest + height - 1)) { + + *color = UI_VGLITE_get_vglite_color(gc, img, alpha); + + vg_lite_identity(matrix); + matrix->m[0][2] = x_dest; + matrix->m[1][2] = y_dest; + + blit_rect[0] = x_src; + blit_rect[1] = y_src; + blit_rect[2] = width; + blit_rect[3] = height; + + ret = &source_buffer; + } + else{ + ret = NULL; + } + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawLine( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x1, jint y1, + jint x2, jint y2) { + + DRAWING_Status ret; + + // Check if there is something to draw and clip drawing limits + // TODO try to crop region (x1 may lower than x2 and y1 may be lower than y2) + if (UI_VGLITE_enable_vg_lite_scissor_region( + gc, + 0, 0, + gc->image.width, gc->image.height)) { + ret = __draw_line(drawer, gc, x1, y1, x2, y2); + } + else { + // nothing to draw + ret = DRAWING_DONE; + } + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawHorizontalLine( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x1, jint x2, jint y) { + + DRAWING_Status ret; + + // Check if there is something to draw and clip drawing limits + if (UI_VGLITE_enable_vg_lite_scissor_region(gc, x1, y, x2, y)) { + ret = __draw_line(drawer, gc, x1, y, x2, y); + } + else { + // nothing to draw + ret = DRAWING_DONE; + } + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawVerticalLine( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, jint y1, jint y2) { + + DRAWING_Status ret; + + // Check if there is something to draw and clip drawing limits + if (UI_VGLITE_enable_vg_lite_scissor_region(gc, x, y1, x, y2)) { + ret = __draw_line(drawer, gc, x, y1, x, y2); + } + else { + // nothing to draw + ret = DRAWING_DONE; + } + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_fillRectangle( + UI_DRAWING_VGLITE_PROCESS_clear_t drawer, + MICROUI_GraphicsContext* gc, + jint x1, jint y1, jint x2, jint y2) { + + DRAWING_Status ret = DRAWING_DONE; + + // Check if there is something to draw and clip drawing limits + if (UI_VGLITE_enable_vg_lite_scissor_region(gc, x1, y1, x2, y2)) { + + vg_lite_rectangle_t shape_vg_rectangle; + shape_vg_rectangle.x = x1; + shape_vg_rectangle.y = y1; + shape_vg_rectangle.width = (x2-x1+1); + shape_vg_rectangle.height = (y2-y1+1); + + ret = (*drawer)(gc, &shape_vg_rectangle, gc->foreground_color); + } + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawRoundedRectangle( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, jint y, + jint width, jint height, + jint arc_width, jint arc_height) { + + vg_lite_matrix_t matrix; + DRAWING_Status ret; + + // Check if there is something to draw and clip drawing limits + if (UI_VGLITE_enable_vg_lite_scissor_region(gc, x, y, x + width, y + height)) { + + jint l_arc_width = (arc_width > width) ? width : arc_width; + jint l_arc_height = (arc_height > height) ? height : arc_height; + + vg_lite_identity(&matrix); + // Compute the rounded rectangle shape path + shape_vg_path.path = &__shape_paths.rounded_rectangle[0]; + shape_vg_path.path_length = sizeof(__shape_paths.rounded_rectangle); + int path_offset = 0; + path_offset = UI_DRAWING_VGLITE_PATH_compute_rounded_rectangle( + &shape_vg_path, path_offset, + x, y, width, height, l_arc_width, l_arc_height, false); + + path_offset = UI_DRAWING_VGLITE_PATH_compute_rounded_rectangle( + &shape_vg_path, path_offset, + x + 1, y + 1, + width - 2, height - 2, + l_arc_width - 1, l_arc_height - 1, + true); + + if (0 > path_offset) { + UI_VGLITE_IMPL_error(false, "Error during path computation"); + LLUI_DISPLAY_reportError(gc, DRAWING_LOG_LIBRARY_INCIDENT); + ret = DRAWING_DONE; + } + else { + // Draw the point with the GPU + ret = (*drawer)( + gc, + &shape_vg_path, + VG_LITE_FILL_EVEN_ODD, + &matrix, + VG_LITE_BLEND_SRC_OVER, + gc->foreground_color + ); + } + } + else { + ret = DRAWING_DONE; + } + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_fillRoundedRectangle( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, jint y, + jint width, jint height, + jint arc_width, jint arc_height) { + + vg_lite_matrix_t matrix; + DRAWING_Status ret; + + // Check if there is something to draw and clip drawing limits + if (UI_VGLITE_enable_vg_lite_scissor_region(gc, x, y, x + width, y + height)) { + + jint l_arc_width = (arc_width > width) ? width : arc_width; + jint l_arc_height = (arc_height > height) ? height : arc_height; + + vg_lite_identity(&matrix); + // Compute the rounded rectangle shape path + shape_vg_path.path = &__shape_paths.rounded_rectangle[0]; + shape_vg_path.path_length = sizeof(__shape_paths.rounded_rectangle); + int path_offset = UI_DRAWING_VGLITE_PATH_compute_rounded_rectangle(&shape_vg_path, 0, + x, y, width, height, l_arc_width, l_arc_height, true); + + if (0 > path_offset) { + UI_VGLITE_IMPL_error(false, "Error during path computation"); + LLUI_DISPLAY_reportError(gc, DRAWING_LOG_LIBRARY_INCIDENT); + ret = DRAWING_DONE; + } + else { + // Draw the point with the GPU + ret = (*drawer)( + gc, + &shape_vg_path, + VG_LITE_FILL_EVEN_ODD, + &matrix, + VG_LITE_BLEND_SRC_OVER, + gc->foreground_color + ); + } + } + else { + ret = DRAWING_DONE; + } + + return ret; +} + + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawCircle( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter) { + DRAWING_Status ret; + + ret = __draw_ellipse( + drawer, + gc, + x, y, + diameter, diameter, + diameter - 2, diameter - 2); + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawCircleArc( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, + jint y, + jint diameter, + jfloat start_angle, + jfloat arc_angle) { + DRAWING_Status ret; + + if (MEJ_ABS(arc_angle) >= 360) { + ret = UI_DRAWING_VGLITE_PROCESS_drawCircle(drawer, gc, x, y, diameter); + } + else { + ret = __draw_ellipse_arc( + drawer, + gc, + x - 1, y - 1, + diameter, diameter, + start_angle, arc_angle, + false); + } + return ret; +} + + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_fillEllipse( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, jint y, + jint width, jint height) { + DRAWING_Status ret; + + ret = __fill_ellipse(drawer, gc, x, y, width, height); + + return ret; +} + + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawEllipse( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, jint y, + jint width, jint height) { + DRAWING_Status ret; + + ret = __draw_ellipse(drawer, gc, x, y, width, height, width - 2, height - 2); + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_fillCircle( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter) { + DRAWING_Status ret; + + ret = __fill_ellipse(drawer, gc, x, y, diameter, diameter); + + return ret; +} + + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawEllipseArc( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, + jint y, + jint width, + jint height, + jfloat start_angle, + jfloat arc_angle) { + DRAWING_Status ret; + + if (MEJ_ABS(arc_angle) >= 360) { + ret = UI_DRAWING_VGLITE_PROCESS_drawEllipse(drawer, gc, x, y, width, height); + } + else { + ret = __draw_ellipse_arc( + drawer, + gc, + x - 1, y - 1, + width, height, + start_angle, arc_angle, + false); + } + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_fillCircleArc( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, jint y, + jint diameter, + jfloat start_angle, jfloat arc_angle) { + DRAWING_Status ret; + + if (MEJ_ABS(arc_angle) >= 360) { + ret = UI_DRAWING_VGLITE_PROCESS_fillCircle(drawer, gc, x, y, diameter); + } + else { + ret = __draw_ellipse_arc( + drawer, + gc, + x, y, + diameter, diameter, + start_angle, arc_angle, + true); + } + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_fillEllipseArc( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, jint y, + jint width, jint height, + jfloat start_angle, jfloat arc_angle) { + DRAWING_Status ret; + + if (MEJ_ABS(arc_angle) >= 360) { + ret = UI_DRAWING_VGLITE_PROCESS_fillEllipse( + drawer, + gc, + x, y, + width, height); + } + else { + ret = __draw_ellipse_arc( + drawer, + gc, + x, y, + width, height, + start_angle, arc_angle, + true); + } + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickFadedPoint( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, + jint y, + jint thickness) { + float dx = x + 0.5f; + float dy = y + 0.5f; + float ft = thickness; + ft /= 2.f; + return __fill_ellipse(drawer, gc, dx - ft, dy - ft, thickness, thickness); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickFadedLine( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x1, + jint y1, + jint x2, + jint y2, + jint thickness, + DRAWING_Cap start, + DRAWING_Cap end) { + return __thick_line( + drawer, + gc, + x1, + y1, + x2, + y2, + thickness, + start, + end); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickFadedCircle( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, jint y, + jint diameter, jint thickness) { + + int diameter_out; + int diameter_in; + + diameter_out = diameter + thickness; + diameter_in = diameter - thickness; + float dx = x; + float dy = y; + float ft = thickness; + ft /= 2.f; + + return __draw_ellipse( + drawer, + gc, + dx - ft, dy - ft, + diameter_out, diameter_out, + diameter_in, diameter_in); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickFadedCircleArc( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, + jint y, + jint diameter, + jfloat start_angle_deg, + jfloat arc_angle, + jint thickness, + DRAWING_Cap start, + DRAWING_Cap end) { + return __draw_thick_shape_ellipse_arc( + drawer, + gc, + x, y, + diameter, diameter, + start_angle_deg, arc_angle, + thickness, + start, end); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickFadedEllipse( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, jint y, + jint width, jint height, + jint thickness) { + + int diameter_out_w; + int diameter_out_h; + int diameter_in_w; + int diameter_in_h; + + diameter_out_w = width + thickness; + diameter_out_h = height + thickness; + diameter_in_w = width - thickness; + diameter_in_h = height - thickness; + + float dx = x; + float dy = y; + float ft = thickness; + ft /= 2.f; + + return __draw_ellipse( + drawer, + gc, + dx - ft, dy - ft, + diameter_out_w, diameter_out_h, + diameter_in_w, diameter_in_h); +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickLine( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x1, + jint y1, + jint x2, + jint y2, + jint thickness) { + DRAWING_Status ret; + + ret = __thick_line( + drawer, + gc, + x1, + y1, + x2, + y2, + thickness, + DRAWING_ENDOFLINE_NONE, + DRAWING_ENDOFLINE_NONE); + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickCircle( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, + jint y, + jint diameter, + jint thickness) { + + int diameter_out; + int diameter_in; + DRAWING_Status ret; + + diameter_out = diameter + thickness; + diameter_in = diameter - thickness; + float dx = x; + float dy = y; + float ft = thickness; + ft /= 2.f; + + ret = __draw_ellipse( + drawer, + gc, + dx - ft, dy - ft, + diameter_out, diameter_out, + diameter_in, diameter_in); + + return ret; +} + +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickEllipse( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, jint y, + jint width, jint height, + jint thickness) { + + int diameter_out_w; + int diameter_out_h; + int diameter_in_w; + int diameter_in_h; + DRAWING_Status ret; + + + diameter_out_w = width + thickness; + diameter_out_h = height + thickness; + diameter_in_w = width - thickness; + diameter_in_h = height - thickness; + + float dx = x; + float dy = y; + float ft = thickness; + ft /= 2.f; + + ret = __draw_ellipse( + drawer, + gc, + dx - ft, dy - ft, + diameter_out_w, diameter_out_h, + diameter_in_w, diameter_in_h); + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawThickCircleArc( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + jint x, + jint y, + jint diameter, + jfloat start_angle_deg, + jfloat arc_angle, + jint thickness) { + DRAWING_Status ret; + + ret = __draw_thick_shape_ellipse_arc( + drawer, + gc, + x, y, + diameter, diameter, + start_angle_deg, arc_angle, + thickness, + DRAWING_ENDOFLINE_NONE, + DRAWING_ENDOFLINE_NONE); + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawFlippedImage( + UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, + MICROUI_GraphicsContext* gc, + MICROUI_Image* img, + jint region_x, + jint region_y, + jint width, + jint height, + jint x, + jint y, + DRAWING_Flip transformation, + jint alpha, bool* is_gpu_compatible) { + + // the next algorithm does not support another origin than (0,0) but MicroUI never uses this condition + assert(0 == region_x); + assert(0 == region_y); + + DRAWING_Status ret; + *is_gpu_compatible = UI_VGLITE_configure_source(&source_buffer, img); + + if(*is_gpu_compatible) { + + uint32_t dest_width = 0; + uint32_t dest_height = 0; + + switch (transformation) { + case DRAWING_FLIP_NONE: + case DRAWING_FLIP_180: + case DRAWING_FLIP_MIRROR: + case DRAWING_FLIP_MIRROR_180: + dest_width = img->width; + dest_height = img->height; + break; + case DRAWING_FLIP_90: + case DRAWING_FLIP_270: + case DRAWING_FLIP_MIRROR_90: + case DRAWING_FLIP_MIRROR_270: + dest_width = img->height; + dest_height = img->width; + break; + default: + UI_VGLITE_IMPL_error(false, "Unexpected transformation: %d\n", transformation); + break; + } + + // Check if there is something to draw and clip drawing limits + if ((dest_width > 0) && (dest_height > 0) && UI_VGLITE_enable_vg_lite_scissor_region( + gc, + x, y, + (x + dest_width - 1), (y + dest_height - 1))) { + + // Exclude bottom right region + source_buffer.width = width; + source_buffer.height = height; + + vg_lite_matrix_t matrix; + vg_lite_identity(&matrix); + vg_lite_translate(x + (dest_width / 2), y + (dest_height / 2), &matrix); + + switch (transformation) { + default: + case DRAWING_FLIP_NONE: + // nothing to do + break; + case DRAWING_FLIP_90: + vg_lite_rotate(-90, &matrix); + break; + case DRAWING_FLIP_180: + vg_lite_rotate(-180, &matrix); + break; + case DRAWING_FLIP_270: + vg_lite_rotate(-270, &matrix); + break; + case DRAWING_FLIP_MIRROR: + vg_lite_scale(-1, 1, &matrix); + break; + case DRAWING_FLIP_MIRROR_90: + vg_lite_rotate(90, &matrix); + vg_lite_scale(1, -1, &matrix); + break; + case DRAWING_FLIP_MIRROR_180: + vg_lite_rotate(180, &matrix); + vg_lite_scale(-1, 1, &matrix); + break; + case DRAWING_FLIP_MIRROR_270: + vg_lite_rotate(270, &matrix); + vg_lite_scale(1, -1, &matrix); + break; + } + + vg_lite_translate(-img->width/2, -img->height/2, &matrix); + + uint32_t blit_rect[4]; + blit_rect[0] = 0; + blit_rect[1] = 0; + blit_rect[2] = img->width; + blit_rect[3] = img->height; + + ret = (*drawer)( + gc, + &source_buffer, + blit_rect, + &matrix, VG_LITE_BLEND_SRC_OVER, + UI_VGLITE_get_vglite_color(gc, img, alpha), + VG_LITE_FILTER_BI_LINEAR); + } + else { + // no error: the drawing is just "out of clip" + ret = DRAWING_DONE; + } + } + else { + // no error: the drawing is just "not performed" + ret = DRAWING_DONE; + } + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawRotatedImageNearestNeighbor( + UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, + MICROUI_GraphicsContext* gc, + MICROUI_Image* img, + jint x, + jint y, + jint xRotation, + jint yRotation, + jfloat angle, + jint alpha, bool* is_gpu_compatible) { + DRAWING_Status ret; + *is_gpu_compatible = UI_VGLITE_configure_source(&source_buffer, img); + + if(*is_gpu_compatible) { + // The GCNanoLiteV limitation: Same rendering around 90 degrees (89.0, 89.1 ... 90.9, 91) + // Render is acceptable since vglite 3.0.4-rev4 + ret = __rotate_image(drawer, gc, img, &source_buffer, x, y, xRotation, yRotation, angle, alpha, VG_LITE_FILTER_POINT); + } + else { + // no error: the drawing is just "not performed" + ret = DRAWING_DONE; + } + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawRotatedImageBilinear( + UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, + MICROUI_GraphicsContext* gc, + MICROUI_Image* img, + jint x, + jint y, + jint xRotation, + jint yRotation, + jfloat angle, + jint alpha, bool* is_gpu_compatible) { + DRAWING_Status ret; + *is_gpu_compatible = UI_VGLITE_configure_source(&source_buffer, img); + + if(*is_gpu_compatible) { + // The GCNanoLiteV limitation: Same rendering around 90 degrees (89.0, 89.1 ... 90.9, 91) + // Render is acceptable since vglite 3.0.4-rev4 + ret = __rotate_image(drawer, gc, img, &source_buffer, x, y, xRotation, yRotation, angle, alpha, VG_LITE_FILTER_BI_LINEAR); + } + else { + // no error: the drawing is just "not performed" + ret = DRAWING_DONE; + } + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawScaledImageNearestNeighbor( + UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, + MICROUI_GraphicsContext* gc, + MICROUI_Image* img, + jint x, + jint y, + jfloat factorX, + jfloat factorY, + jint alpha, bool* is_gpu_compatible) { + DRAWING_Status ret; + *is_gpu_compatible = UI_VGLITE_configure_source(&source_buffer, img); + + if(*is_gpu_compatible) { + ret =__scale_image(drawer, gc, img, &source_buffer, x, y, factorX, factorY, alpha, VG_LITE_FILTER_POINT); + } + else { + // no error: the drawing is just "not performed" + ret = DRAWING_DONE; + } + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status UI_DRAWING_VGLITE_PROCESS_drawScaledImageBilinear( + UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, + MICROUI_GraphicsContext* gc, + MICROUI_Image* img, + jint x, + jint y, + jfloat factorX, + jfloat factorY, + jint alpha, bool* is_gpu_compatible) { + DRAWING_Status ret; + *is_gpu_compatible = UI_VGLITE_configure_source(&source_buffer, img); + + if(*is_gpu_compatible) { + // when the factor is 1x1, the filter "point" draws something closer than draw_image + vg_lite_filter_t filter = ((1.0f == factorX) && (1.0f == factorY)) ? VG_LITE_FILTER_POINT : VG_LITE_FILTER_BI_LINEAR; + ret = __scale_image(drawer, gc, img, &source_buffer, x, y, factorX, factorY, alpha, filter); + } + else { + // no error: the drawing is just "not performed" + ret = DRAWING_DONE; + } + + return ret; +} + +// ----------------------------------------------------------------------------- +// Internal functions +// ----------------------------------------------------------------------------- + +// See the section 'Internal function definitions' for the function documentation +static DRAWING_Status __draw_ellipse_arc( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + int x, + int y, + int diameter_w, + int diameter_h, + float start_angle_deg, + float arc_angle_deg, + bool fill) { + + vg_lite_matrix_t matrix; + DRAWING_Status ret; + + // Check if there is something to draw and clip drawing limits + // +/- 1: consider 1 pixel of antialiasing + if (UI_VGLITE_enable_vg_lite_scissor_region(gc, x - 1, y - 1, x + diameter_w, y + diameter_h)) { + + vg_lite_identity(&matrix); + + float radius_out_w = (float)diameter_w; + float radius_out_h = (float)diameter_h; + radius_out_w /= 2.f; + radius_out_h /= 2.f; + float radius_in_w = radius_out_w - 1.f; + float radius_in_h = radius_out_h - 1.f; + + vg_lite_translate(x + radius_out_w, y + radius_out_h, &matrix); + + radius_out_w *= DRAWING_SCALE_FACTOR; + radius_out_h *= DRAWING_SCALE_FACTOR; + radius_in_w *= DRAWING_SCALE_FACTOR; + radius_in_h *= DRAWING_SCALE_FACTOR; + + vg_lite_scale(DRAWING_SCALE_DIV, DRAWING_SCALE_DIV, &matrix); + + shape_vg_path.path = &__shape_paths.ellipse_arc; + shape_vg_path.path_length = sizeof(__shape_paths.ellipse_arc); + int path_offset = UI_DRAWING_VGLITE_PATH_compute_ellipse_arc( + &shape_vg_path, + (int)radius_out_w, (int)radius_out_h, + (int)radius_in_w, (int)radius_in_h, + + // 0 degrees: + // - MicroUI: 3 o'clock. + // - RT595 VGLite implementation : 0 o'clock. + 90.f - start_angle_deg, + + -arc_angle_deg, fill); + + if (0 > path_offset) { + UI_VGLITE_IMPL_error(false, "Error during path computation"); + LLUI_DISPLAY_reportError(gc, DRAWING_LOG_LIBRARY_INCIDENT); + ret = DRAWING_DONE; + } + else { + + // Draw the point with the GPU + ret = (*drawer)( + gc, + &shape_vg_path, + VG_LITE_FILL_EVEN_ODD, + &matrix, + VG_LITE_BLEND_SRC_OVER, + gc->foreground_color + ); + } + } + else { + ret = DRAWING_DONE; + } + return ret; +} + +// See the section 'Internal function definitions' for the function documentation +static DRAWING_Status __draw_ellipse( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + float x, float y, + int diameter_out_w, int diameter_out_h, + int diameter_in_w, int diameter_in_h) { + + vg_lite_matrix_t matrix; + DRAWING_Status ret; + + // Check if there is something to draw and clip drawing limits + // +/- 1: consider 1 pixel of antialiasing + if (UI_VGLITE_enable_vg_lite_scissor_region(gc, (int)(x - 1), (int)(y - 1), (int)(x + diameter_out_w), (int)(y + diameter_out_h))) { + + vg_lite_identity(&matrix); + + float radius_w = (float)diameter_out_w ; + float radius_h = (float)diameter_out_h ; + + radius_w /= 2.f; + radius_h /= 2.f; + + vg_lite_translate(x + radius_w, y + radius_h, &matrix); + + radius_w *= DRAWING_SCALE_FACTOR; + radius_h *= DRAWING_SCALE_FACTOR; + + vg_lite_scale(DRAWING_SCALE_DIV, DRAWING_SCALE_DIV, &matrix); + // Compute the rounded rectangle shape path + shape_vg_path.path = &__shape_paths.ellipse[0]; + shape_vg_path.path_length = sizeof(__shape_paths.ellipse); + int path_offset = UI_DRAWING_VGLITE_PATH_compute_ellipse( + &shape_vg_path, 0, + (int)radius_w, (int)radius_h, + false); + + radius_w = (float)diameter_in_w ; + radius_h = (float)diameter_in_h ; + + radius_w /= 2.f; + radius_h /= 2.f; + + radius_w *= DRAWING_SCALE_FACTOR; + radius_h *= DRAWING_SCALE_FACTOR; + + path_offset = UI_DRAWING_VGLITE_PATH_compute_ellipse( + &shape_vg_path, + path_offset, + (int)radius_w, (int)radius_h, + true); + + if (0 > path_offset) { + UI_VGLITE_IMPL_error(false, "Error during path computation"); + LLUI_DISPLAY_reportError(gc, DRAWING_LOG_LIBRARY_INCIDENT); + ret = DRAWING_DONE; + } + else { + // Draw the point with the GPU + ret = (*drawer)( + gc, + &shape_vg_path, + VG_LITE_FILL_EVEN_ODD, + &matrix, + VG_LITE_BLEND_SRC_OVER, + gc->foreground_color + ); + } + } + else { + ret = DRAWING_DONE; + } + return ret; +} + +// See the section 'Internal function definitions' for the function documentation +static DRAWING_Status __fill_ellipse( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + float x, float y, + int diameter_w, int diameter_h) { + + vg_lite_matrix_t matrix; + DRAWING_Status ret; + + // Check if there is something to draw and clip drawing limits + // +/- 1: consider 1 pixel of antialiasing + if (UI_VGLITE_enable_vg_lite_scissor_region( gc, + (int)(x - 1), + (int)(y - 1), + (int)(x + diameter_w), + (int)(y + diameter_h))) { + + float radius_w = (float)diameter_w ; + float radius_h = (float)diameter_h ; + radius_w /= 2.f; + radius_h /= 2.f; + + vg_lite_identity(&matrix); + vg_lite_translate(x + radius_w, y + radius_h, &matrix); + + radius_w *= DRAWING_SCALE_FACTOR; + radius_h *= DRAWING_SCALE_FACTOR; + + vg_lite_scale(DRAWING_SCALE_DIV, DRAWING_SCALE_DIV, &matrix); + + // Compute the thick shape path + shape_vg_path.path = &__shape_paths.ellipse; + shape_vg_path.path_length = sizeof(__shape_paths.ellipse); + (void)UI_DRAWING_VGLITE_PATH_compute_filled_ellipse(&shape_vg_path, (int)radius_w, (int)radius_h, &matrix); + + // Draw the point with the GPU + ret = (*drawer)( + gc, + &shape_vg_path, + VG_LITE_FILL_NON_ZERO, + &matrix, + VG_LITE_BLEND_SRC_OVER, + gc->foreground_color + ); + } + else { + ret = DRAWING_DONE; + } + return ret; +} + +// See the section 'Internal function definitions' for the function documentation +static DRAWING_Status __draw_line( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + int xs, int ys, + int xe, int ye) { + + // Translate to the line starting point + vg_lite_matrix_t matrix; + vg_lite_identity(&matrix); + vg_lite_translate(xs, ys, &matrix); + + // Compute the thick shape path + shape_vg_path.path = &__shape_paths.line; + shape_vg_path.path_length = sizeof(__shape_paths.line); + (void)UI_DRAWING_VGLITE_PATH_compute_line(&shape_vg_path, xe - xs, ye - ys); + + // Draw the line with the GPU + return (*drawer)( + gc, + &shape_vg_path, + VG_LITE_FILL_NON_ZERO, + &matrix, + VG_LITE_BLEND_SRC_OVER, + gc->foreground_color + ); +} + +// See the section 'Internal function definitions' for the function documentation +static DRAWING_Status __thick_line( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + int xs, + int ys, + int xe, + int ye, + int thickness, + DRAWING_Cap start, + DRAWING_Cap end) { + + vg_lite_matrix_t matrix; + DRAWING_Status ret; + + int min_x = MEJ_MIN(xs, xe); + int min_y = MEJ_MIN(ys, ye); + int max_x = MEJ_MAX(xs, xe); + int max_y = MEJ_MAX(ys, ye); + + // Check if there is something to draw and clip drawing limits + if (UI_VGLITE_enable_vg_lite_scissor_region( + gc, + min_x - (thickness / 2), + min_y - (thickness / 2), + max_x + (thickness / 2), + max_y + (thickness / 2))) { + + // Translate to the line starting point + vg_lite_identity(&matrix); + vg_lite_translate(xs, ys, &matrix); + + vg_lite_scale(DRAWING_SCALE_DIV, DRAWING_SCALE_DIV, &matrix); + + shape_vg_path.path = &__shape_paths.thick_shape_line; + shape_vg_path.path_length = sizeof(__shape_paths.thick_shape_line); + + int caps = 0; + caps |= MEJ_VGLITE_PATH_SET_CAPS_START(start); + caps |= MEJ_VGLITE_PATH_SET_CAPS_END(end); + + (void)UI_DRAWING_VGLITE_PATH_compute_thick_shape_line( + &shape_vg_path, + (int)(DRAWING_SCALE_FACTOR * (xe - xs)), + (int)(DRAWING_SCALE_FACTOR * (ye - ys)), + (int)(DRAWING_SCALE_FACTOR * thickness), + caps, + &matrix); + + ret = (*drawer)( + gc, + &shape_vg_path, + VG_LITE_FILL_NON_ZERO, + &matrix, + VG_LITE_BLEND_SRC_OVER, + gc->foreground_color); + } + else { + ret = DRAWING_DONE; + } + return ret; +} + +// See the section 'Internal function definitions' for the function documentation +static DRAWING_Status __draw_thick_shape_ellipse_arc( + UI_DRAWING_VGLITE_PROCESS_draw_path_t drawer, + MICROUI_GraphicsContext* gc, + int x, + int y, + int diameter_w, + int diameter_h, + float start_angle_deg, + float arc_angle, + int thickness, + DRAWING_Cap start, + DRAWING_Cap end) { + + DRAWING_Status ret; + + // Check if there is something to draw and clip drawing limits + if (UI_VGLITE_enable_vg_lite_scissor_region( + gc, + x - thickness, + y - thickness, + x + diameter_w + (2 * thickness) - 1, + y + diameter_h + (2 * thickness) - 1)) { + + float translate_x = (float)diameter_w; + float translate_y = (float)diameter_h; + translate_x /= 2.f; + translate_y /= 2.f; + + vg_lite_matrix_t matrix; + vg_lite_identity(&matrix); + vg_lite_translate(x + translate_x, y + translate_y, &matrix); + vg_lite_rotate(-start_angle_deg, &matrix); + vg_lite_scale(DRAWING_SCALE_DIV, DRAWING_SCALE_DIV, &matrix); + + int caps = 0; + caps |= MEJ_VGLITE_PATH_SET_CAPS_START(start); + caps |= MEJ_VGLITE_PATH_SET_CAPS_END(end); + + // Compute the thick shape path + shape_vg_path.path = &__shape_paths.thick_ellipse_arc; + shape_vg_path.path_length = sizeof(__shape_paths.thick_ellipse_arc); + + (void)UI_DRAWING_VGLITE_PATH_compute_thick_shape_ellipse_arc( + &shape_vg_path, + (int)(DRAWING_SCALE_FACTOR * diameter_w), + (int)(DRAWING_SCALE_FACTOR * diameter_h), + (int)(DRAWING_SCALE_FACTOR * thickness), + 0, + arc_angle, + caps); + + ret = (*drawer)( + gc, + &shape_vg_path, + VG_LITE_FILL_NON_ZERO, + &matrix, + VG_LITE_BLEND_SRC_OVER, + gc->foreground_color); + } + else { + ret = DRAWING_DONE; + } + return ret; +} + +// See the section 'Internal function definitions' for the function documentation +static DRAWING_Status __rotate_image( + UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, + MICROUI_GraphicsContext* gc, + MICROUI_Image* img, + vg_lite_buffer_t* src, + int x, + int y, + int xRotation, + int yRotation, + float angle_deg, + int alpha, + vg_lite_filter_t filter) { + + DRAWING_Status ret; + + // Check if there is something to draw and clip drawing limits + // TODO try to crop region + if (UI_VGLITE_enable_vg_lite_scissor_region( + gc, + 0, 0, + gc->image.width, gc->image.height)) { + + vg_lite_matrix_t matrix; + vg_lite_identity(&matrix); + vg_lite_translate(xRotation, yRotation, &matrix); + vg_lite_rotate(-angle_deg, &matrix); + vg_lite_translate(x-xRotation, y-yRotation, &matrix); + + uint32_t blit_rect[4]; + blit_rect[0] = 0; + blit_rect[1] = 0; + blit_rect[2] = img->width; + blit_rect[3] = img->height; + + ret = (*drawer)( + gc, + src, + blit_rect, + &matrix, VG_LITE_BLEND_SRC_OVER, + UI_VGLITE_get_vglite_color(gc, img, alpha), + filter); + } + else { + ret = DRAWING_DONE; + } + return ret; +} + +// See the section 'Internal function definitions' for the function documentation +static DRAWING_Status __scale_image( + UI_DRAWING_VGLITE_PROCESS_blit_rect_t drawer, + MICROUI_GraphicsContext* gc, + MICROUI_Image* img, + vg_lite_buffer_t* src, + int x, + int y, + float factorX, + float factorY, + int alpha, + vg_lite_filter_t filter) { + + DRAWING_Status ret; + + // Check if there is something to draw and clip drawing limits + if (UI_VGLITE_enable_vg_lite_scissor_region( + gc, x, y, + (int) (x + (factorX * img->width)), + (int) (y + (factorY * img->height)))) { + + vg_lite_matrix_t matrix; + vg_lite_identity(&matrix); + vg_lite_translate(x, y, &matrix); + vg_lite_scale(factorX, factorY, &matrix); + + uint32_t blit_rect[4]; + blit_rect[0] = 0; + blit_rect[1] = 0; + blit_rect[2] = img->width; + blit_rect[3] = img->height; + + ret = (*drawer)( + gc, + src, + blit_rect, + &matrix, VG_LITE_BLEND_SRC_OVER, + UI_VGLITE_get_vglite_color(gc, img, alpha), + filter); + } + else { + ret = DRAWING_DONE; + } + return ret; +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- diff --git a/bsp/projects/microej/ui/src/ui_image_drawing.c b/bsp/projects/microej/ui/src/ui_image_drawing.c new file mode 100644 index 0000000..a0f9c91 --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_image_drawing.c @@ -0,0 +1,741 @@ +/* + * C + * + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief Implementation of all drawing functions of ui_image_drawing.h. + * @author MicroEJ Developer Team + * @version 4.0.1 + * @see ui_image_drawing.h + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include + +#include "ui_image_drawing.h" +#include "ui_drawing_soft.h" +#include "dw_drawing_soft.h" +#include "ui_drawing_stub.h" +#include "bsp_util.h" + +#if defined(LLUI_IMAGE_CUSTOM_FORMATS) + +/* + * VEE Port supports several images formats: standard (ARGB8888, A8, etc) and one or + * several custom formats. The next functions and tables redirect the image drawing + * to the right image manager (stub, soft or custom). + * + * VEE Port may support several destination formats: display format, one or several + * standard formats and one or several custom formats. See _get_table_index(). + * + * Note: The functions are called by ui_drawing.c. The use of GPU should be checked + * in ui_drawing.c and not here. + */ + +// -------------------------------------------------------------------------------- +// Defines +// -------------------------------------------------------------------------------- + +/* + * @brief Indices in the tables UI_IMAGE_DRAWING_xxx_custom[] + */ +#define TABLE_INDEX_STUB 0 // index to call functions stub +#define TABLE_INDEX_SOFT 1 // index to call functions in software +#define TABLE_INDEX_CUSTOM_OFFSET 2 // index to call VEE Port functions + +#define GET_CUSTOM_IMAGE_INDEX(img) (((uint8_t)TABLE_INDEX_CUSTOM_OFFSET) + ((uint8_t)MICROUI_IMAGE_FORMAT_CUSTOM_0) - ((uint8_t)((img)->format))) + +// -------------------------------------------------------------------------------- +// Extern functions +// -------------------------------------------------------------------------------- + +/* + * @brief Set of drawing functions according to the source image format. + * + * These functions must be declared in other H files. + */ + +extern DRAWING_Status UI_IMAGE_DRAWING_draw_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_draw_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_draw_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_draw_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_draw_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_draw_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_draw_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_draw_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); + +extern DRAWING_Status UI_IMAGE_DRAWING_copy_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); +extern DRAWING_Status UI_IMAGE_DRAWING_copy_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); +extern DRAWING_Status UI_IMAGE_DRAWING_copy_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); +extern DRAWING_Status UI_IMAGE_DRAWING_copy_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); +extern DRAWING_Status UI_IMAGE_DRAWING_copy_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); +extern DRAWING_Status UI_IMAGE_DRAWING_copy_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); +extern DRAWING_Status UI_IMAGE_DRAWING_copy_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); +extern DRAWING_Status UI_IMAGE_DRAWING_copy_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); + +extern DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom0(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom1(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom2(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom3(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom4(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom5(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom6(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom7(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); + +extern DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); + +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); + +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); + +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +extern DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +// -------------------------------------------------------------------------------- +// Typedef of drawing functions +// -------------------------------------------------------------------------------- + +typedef DRAWING_Status (* UI_IMAGE_DRAWING_draw_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +typedef DRAWING_Status (* UI_IMAGE_DRAWING_copy_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y); +typedef DRAWING_Status (* UI_IMAGE_DRAWING_drawRegion_t) (MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha); +typedef DRAWING_Status (* UI_IMAGE_DRAWING_drawFlipped_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha); +typedef DRAWING_Status (* UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +typedef DRAWING_Status (* UI_IMAGE_DRAWING_drawRotatedBilinear_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha); +typedef DRAWING_Status (* UI_IMAGE_DRAWING_drawScaledNearestNeighbor_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); +typedef DRAWING_Status (* UI_IMAGE_DRAWING_drawScaledBilinear_t) (MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha); + +// -------------------------------------------------------------------------------- +// Tables according to the source image format. +// -------------------------------------------------------------------------------- + +static const UI_IMAGE_DRAWING_draw_t UI_IMAGE_DRAWING_draw_custom[] = { + &UI_DRAWING_STUB_drawImage, + &UI_DRAWING_SOFT_drawImage, + &UI_IMAGE_DRAWING_draw_custom0, + &UI_IMAGE_DRAWING_draw_custom1, + &UI_IMAGE_DRAWING_draw_custom2, + &UI_IMAGE_DRAWING_draw_custom3, + &UI_IMAGE_DRAWING_draw_custom4, + &UI_IMAGE_DRAWING_draw_custom5, + &UI_IMAGE_DRAWING_draw_custom6, + &UI_IMAGE_DRAWING_draw_custom7, +}; + +static const UI_IMAGE_DRAWING_copy_t UI_IMAGE_DRAWING_copy_custom[] = { + UI_DRAWING_STUB_copyImage, + UI_DRAWING_SOFT_copyImage, + &UI_IMAGE_DRAWING_copy_custom0, + &UI_IMAGE_DRAWING_copy_custom1, + &UI_IMAGE_DRAWING_copy_custom2, + &UI_IMAGE_DRAWING_copy_custom3, + &UI_IMAGE_DRAWING_copy_custom4, + &UI_IMAGE_DRAWING_copy_custom5, + &UI_IMAGE_DRAWING_copy_custom6, + &UI_IMAGE_DRAWING_copy_custom7, +}; + +static const UI_IMAGE_DRAWING_drawRegion_t UI_IMAGE_DRAWING_drawRegion_custom[] = { + UI_DRAWING_STUB_drawRegion, + UI_DRAWING_SOFT_drawRegion, + &UI_IMAGE_DRAWING_drawRegion_custom0, + &UI_IMAGE_DRAWING_drawRegion_custom1, + &UI_IMAGE_DRAWING_drawRegion_custom2, + &UI_IMAGE_DRAWING_drawRegion_custom3, + &UI_IMAGE_DRAWING_drawRegion_custom4, + &UI_IMAGE_DRAWING_drawRegion_custom5, + &UI_IMAGE_DRAWING_drawRegion_custom6, + &UI_IMAGE_DRAWING_drawRegion_custom7, +}; + +static const UI_IMAGE_DRAWING_drawFlipped_t UI_IMAGE_DRAWING_drawFlipped_custom[] = { + UI_DRAWING_STUB_drawFlippedImage, + DW_DRAWING_SOFT_drawFlippedImage, + &UI_IMAGE_DRAWING_drawFlipped_custom0, + &UI_IMAGE_DRAWING_drawFlipped_custom1, + &UI_IMAGE_DRAWING_drawFlipped_custom2, + &UI_IMAGE_DRAWING_drawFlipped_custom3, + &UI_IMAGE_DRAWING_drawFlipped_custom4, + &UI_IMAGE_DRAWING_drawFlipped_custom5, + &UI_IMAGE_DRAWING_drawFlipped_custom6, + &UI_IMAGE_DRAWING_drawFlipped_custom7, +}; + +static const UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_t UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom[] = { + UI_DRAWING_STUB_drawRotatedImageNearestNeighbor, + DW_DRAWING_SOFT_drawRotatedImageNearestNeighbor, + &UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom0, + &UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom1, + &UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom2, + &UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom3, + &UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom4, + &UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom5, + &UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom6, + &UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom7, +}; + +static const UI_IMAGE_DRAWING_drawRotatedBilinear_t UI_IMAGE_DRAWING_drawRotatedBilinear_custom[] = { + UI_DRAWING_STUB_drawRotatedImageBilinear, + DW_DRAWING_SOFT_drawRotatedImageBilinear, + &UI_IMAGE_DRAWING_drawRotatedBilinear_custom0, + &UI_IMAGE_DRAWING_drawRotatedBilinear_custom1, + &UI_IMAGE_DRAWING_drawRotatedBilinear_custom2, + &UI_IMAGE_DRAWING_drawRotatedBilinear_custom3, + &UI_IMAGE_DRAWING_drawRotatedBilinear_custom4, + &UI_IMAGE_DRAWING_drawRotatedBilinear_custom5, + &UI_IMAGE_DRAWING_drawRotatedBilinear_custom6, + &UI_IMAGE_DRAWING_drawRotatedBilinear_custom7, +}; + +static const UI_IMAGE_DRAWING_drawScaledNearestNeighbor_t UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom[] = { + UI_DRAWING_STUB_drawScaledImageNearestNeighbor, + DW_DRAWING_SOFT_drawScaledImageNearestNeighbor, + &UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom0, + &UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom1, + &UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom2, + &UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom3, + &UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom4, + &UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom5, + &UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom6, + &UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom7, +}; + +static const UI_IMAGE_DRAWING_drawScaledBilinear_t UI_IMAGE_DRAWING_drawScaledBilinear_custom[] = { + UI_DRAWING_STUB_drawScaledImageBilinear, + DW_DRAWING_SOFT_drawScaledImageBilinear, + &UI_IMAGE_DRAWING_drawScaledBilinear_custom0, + &UI_IMAGE_DRAWING_drawScaledBilinear_custom1, + &UI_IMAGE_DRAWING_drawScaledBilinear_custom2, + &UI_IMAGE_DRAWING_drawScaledBilinear_custom3, + &UI_IMAGE_DRAWING_drawScaledBilinear_custom4, + &UI_IMAGE_DRAWING_drawScaledBilinear_custom5, + &UI_IMAGE_DRAWING_drawScaledBilinear_custom6, + &UI_IMAGE_DRAWING_drawScaledBilinear_custom7, +}; + +// -------------------------------------------------------------------------------- +// Private functions +// -------------------------------------------------------------------------------- + +static inline uint32_t _get_table_index(MICROUI_GraphicsContext* gc, MICROUI_Image* img) { + uint32_t index; + if (!LLUI_DISPLAY_isCustomFormat(img->format)) { +#if !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + (void)gc; + // standard image in display GC -> can use soft algo + index = TABLE_INDEX_SOFT; +#else + index = LLUI_DISPLAY_isDisplayFormat(gc->image.format) ? TABLE_INDEX_SOFT : TABLE_INDEX_STUB; +#endif + } + else { + // use the specific image manager to draw the custom image + // (this manager must check the destination format) + // cppcheck-suppress [misra-c2012-10.6] convert image format to an index + index = GET_CUSTOM_IMAGE_INDEX(img); + } + return index; +} + +// -------------------------------------------------------------------------------- +// ui_image_drawing.h functions +// -------------------------------------------------------------------------------- + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_draw(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return (*UI_IMAGE_DRAWING_draw_custom[_get_table_index(gc, img)])(gc, img, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_copy(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + return (*UI_IMAGE_DRAWING_copy_custom[_get_table_index(gc, img)])(gc, img, regionX, regionY, width, height, x, y); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_drawRegion(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return (*UI_IMAGE_DRAWING_drawRegion_custom[_get_table_index(gc, &gc->image)])(gc, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_drawFlipped(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + return (*UI_IMAGE_DRAWING_drawFlipped_custom[_get_table_index(gc, img)])(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return (*UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom[_get_table_index(gc, img)])(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return (*UI_IMAGE_DRAWING_drawRotatedBilinear_custom[_get_table_index(gc, img)])(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return (*UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom[_get_table_index(gc, img)])(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return (*UI_IMAGE_DRAWING_drawScaledBilinear_custom[_get_table_index(gc, img)])(gc, img, x, y, factorX, factorY, alpha); +} + +// -------------------------------------------------------------------------------- +// Table weak functions +// -------------------------------------------------------------------------------- + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_draw_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawImage(gc, img, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_draw_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawImage(gc, img, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_draw_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawImage(gc, img, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_draw_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawImage(gc, img, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_draw_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawImage(gc, img, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_draw_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawImage(gc, img, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_draw_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawImage(gc, img, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_draw_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawImage(gc, img, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_copy_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + return UI_DRAWING_STUB_copyImage(gc, img, regionX, regionY, width, height, x, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_copy_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + return UI_DRAWING_STUB_copyImage(gc, img, regionX, regionY, width, height, x, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_copy_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + return UI_DRAWING_STUB_copyImage(gc, img, regionX, regionY, width, height, x, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_copy_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + return UI_DRAWING_STUB_copyImage(gc, img, regionX, regionY, width, height, x, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_copy_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + return UI_DRAWING_STUB_copyImage(gc, img, regionX, regionY, width, height, x, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_copy_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + return UI_DRAWING_STUB_copyImage(gc, img, regionX, regionY, width, height, x, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_copy_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + return UI_DRAWING_STUB_copyImage(gc, img, regionX, regionY, width, height, x, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_copy_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + return UI_DRAWING_STUB_copyImage(gc, img, regionX, regionY, width, height, x, y); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom0(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom1(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom2(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom3(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom4(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom5(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom6(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRegion_custom7(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return UI_DRAWING_STUB_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + return UI_DRAWING_STUB_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + return UI_DRAWING_STUB_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + return UI_DRAWING_STUB_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + return UI_DRAWING_STUB_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + return UI_DRAWING_STUB_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + return UI_DRAWING_STUB_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + return UI_DRAWING_STUB_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawFlipped_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + return UI_DRAWING_STUB_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return UI_DRAWING_STUB_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom0(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom1(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom2(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom3(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom4(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom5(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom6(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear_custom7(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return UI_DRAWING_STUB_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); +} + +#else // #if defined(LLUI_IMAGE_CUSTOM_FORMATS) + +/* + * VEE Port supports only standard images formats: standard (ARGB8888, A8, etc). The + * next functions redirect the image drawing to the software algorithms. + * + * VEE Port may support several destination formats: display format and one or several + * standard formats. + * + * Note: The functions are called by ui_drawing.c. The use of GPU should be checked + * in ui_drawing.c and not here. + */ + +// -------------------------------------------------------------------------------- +// Private functions +// -------------------------------------------------------------------------------- + +static inline bool _can_call_soft_algo(MICROUI_GraphicsContext* gc) { +#if !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + (void)gc; + // standard image in display GC -> can use soft algo + return true; +#else + return LLUI_DISPLAY_isDisplayFormat(gc->image.format); +#endif +} + +// -------------------------------------------------------------------------------- +// ui_image_drawing.h functions +// -------------------------------------------------------------------------------- + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_draw(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return _can_call_soft_algo(gc) ? + UI_DRAWING_SOFT_drawImage(gc, img, regionX, regionY, width, height, x, y, alpha) + : UI_DRAWING_STUB_drawImage(gc, img, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_copy(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y){ + return _can_call_soft_algo(gc) ? + UI_DRAWING_SOFT_copyImage(gc, img, regionX, regionY, width, height, x, y) + : UI_DRAWING_STUB_copyImage(gc, img, regionX, regionY, width, height, x, y); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_drawRegion(MICROUI_GraphicsContext* gc, jint regionX, jint regionY, jint width, jint height, jint x, jint y, jint alpha){ + return _can_call_soft_algo(gc) ? + UI_DRAWING_SOFT_drawRegion(gc, regionX, regionY, width, height, x, y, alpha) + : UI_DRAWING_STUB_drawRegion(gc, regionX, regionY, width, height, x, y, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_drawFlipped(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha){ + return _can_call_soft_algo(gc) ? + DW_DRAWING_SOFT_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha) + : UI_DRAWING_STUB_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_drawRotatedNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return _can_call_soft_algo(gc) ? + DW_DRAWING_SOFT_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha) + : UI_DRAWING_STUB_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_drawRotatedBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha){ + return _can_call_soft_algo(gc) ? + DW_DRAWING_SOFT_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha) + : UI_DRAWING_STUB_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_drawScaledNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return _can_call_soft_algo(gc) ? + DW_DRAWING_SOFT_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha) + : UI_DRAWING_STUB_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); +} + +// See the header file for the function documentation +DRAWING_Status UI_IMAGE_DRAWING_drawScaledBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha){ + return _can_call_soft_algo(gc) ? + DW_DRAWING_SOFT_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha) + : UI_DRAWING_STUB_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); +} + +#endif // #if defined(LLUI_IMAGE_CUSTOM_FORMATS) + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- diff --git a/bsp/projects/microej/ui/src/ui_rect_util.c b/bsp/projects/microej/ui/src/ui_rect_util.c new file mode 100644 index 0000000..c57ad53 --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_rect_util.c @@ -0,0 +1,106 @@ +/* + * C + * + * Copyright 2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include + +#include "ui_util.h" +#include "ui_rect_util.h" + +// -------------------------------------------------------------------------------- +// Functions +// -------------------------------------------------------------------------------- + +// See the header file for the function documentation +ui_rect_t UI_RECT_get_minimum_bounding_rect(const ui_rect_t rects[], const size_t count) { + assert(count > 0u); + ui_rect_t result = rects[0]; + for (size_t i=1; iy1 < second->y1) ? first : second; + const ui_rect_t* top_below = (first->y1 < second->y1) ? second : first; + const ui_rect_t* bottom_below = (first->y2 > second->y2) ? first : second; + const ui_rect_t* bottom_above = (first->y2 > second->y2) ? second : first; + + uint32_t count = 0u; + + output[count] = UI_RECT_new_xyxy(top_above->x1, top_above->y1, top_above->x2, top_below->y1-1); + if (!UI_RECT_is_empty(output)) { + count++; + } + + output[count] = UI_RECT_new_xyxy(MIN(first->x1, second->x1), top_below->y1, MAX(first->x2, second->x2), bottom_above->y2); + if (!UI_RECT_is_empty(output)) { + count++; + } + + output[count] = UI_RECT_new_xyxy(bottom_below->x1, bottom_above->y2+1, bottom_below->x2, bottom_below->y2); + if (!UI_RECT_is_empty(output)) { + count++; + } + + ret = count; + } + return ret; +} + +// See the header file for the function documentation +uint32_t UI_RECT_subtract(ui_rect_t output[4], const ui_rect_t* first, const ui_rect_t* second) { + uint32_t ret; + if (UI_RECT_contains_rect(first, second)) { + output[0] = UI_RECT_new_xyxy(first->x1, first->y1, first->x2, second->y1-1); // Top + output[1] = UI_RECT_new_xyxy(first->x1, second->y1, second->x1-1, second->y2); // Left + output[2] = UI_RECT_new_xyxy(second->x2+1, second->y1, first->x2, second->y2); // Right + output[3] = UI_RECT_new_xyxy(first->x1, second->y2+1, first->x2, first->y2); // Bottom + ret = 4u; + } else if (UI_RECT_contains_rect(second, first)) { + UI_RECT_mark_empty(&output[0]); + UI_RECT_mark_empty(&output[1]); + UI_RECT_mark_empty(&output[2]); + UI_RECT_mark_empty(&output[3]); + ret = 0u; + } else if (!UI_RECT_intersects_rect(first, second)) { + output[0] = *first; + UI_RECT_mark_empty(&output[1]); + UI_RECT_mark_empty(&output[2]); + UI_RECT_mark_empty(&output[3]); + ret = 1u; + } else { + output[0] = UI_RECT_new_xyxy(first->x1, first->y1, first->x2, second->y1-1); // Top + output[1] = UI_RECT_new_xyxy(first->x1, MAX(first->y1, second->y1), second->x1-1, MIN(first->y2, second->y2)); // Left + output[2] = UI_RECT_new_xyxy(second->x2+1, MAX(first->y1, second->y1), first->x2, MIN(first->y2, second->y2)); // Right + output[3] = UI_RECT_new_xyxy(first->x1, second->y2+1, first->x2, first->y2); // Bottom + ret = 4u; + } + return ret; +} diff --git a/bsp/projects/microej/ui/src/ui_vglite.c b/bsp/projects/microej/ui/src/ui_vglite.c new file mode 100644 index 0000000..8b56960 --- /dev/null +++ b/bsp/projects/microej/ui/src/ui_vglite.c @@ -0,0 +1,753 @@ +/* + * C + * + * Copyright 2020-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief MicroEJ MicroUI library low level API: implementation of ui_vglite.h. + * @author MicroEJ Developer Team + * @version 8.0.1 + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include + +#include "ui_vglite.h" +#include "color.h" +#include "mej_math.h" +#include "bsp_util.h" +#include "interrupts.h" + +#include "vg_lite_hal.h" + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +/* + * @brief Unknown display format + */ +#define DISPLAY_UNKNOWN_FORMAT -1 + +/* + * @brief To check if the image format is known + */ +#define VG_LITE_UNKNOWN_FORMAT ((vg_lite_buffer_format_t) (DISPLAY_UNKNOWN_FORMAT)) + +/* + * @brief Macro to align data + */ +#define ALIGN(value, align) (((value) + (align) - 1) & ~((align) - 1)) + +// ----------------------------------------------------------------------------- +// Typedef +// ----------------------------------------------------------------------------- + +/* + * @brief Action to perform during the GPU interrupt. + */ +typedef enum { + + /* + * @brief Nothing to do, the interrupt occurs during a drawing + */ + IRQ_BYPASS, + + /* + * @brief Wakes-up the drawer to continue the drawing + */ + IRQ_WAKEUP_TASK, + + /* + * @brief Wakes-up the MicroUI Graphics Engine + */ + IRQ_WAKEUP_GRAPHICS_ENGINE, + +} vglite_irq_post_operation_t; + +// ----------------------------------------------------------------------------- +// Global Variables +// ----------------------------------------------------------------------------- + +/* + * @brief VGLite destination buffer (there is only one destination at any time) + */ +static vg_lite_buffer_t destination_buffer; + +#ifdef VGLITE_OPTION_TOGGLE_GPU +/* + * @brief flag to enable/disable hardware rendering + */ +static bool hardware_rendering; +#endif + +/* + * @brief IRQ operation + */ +static volatile vglite_irq_post_operation_t vg_lite_irq_operation; + +/* + * @brief vglite operation semaphore + */ +static void* vg_lite_operation_semaphore; + +// ----------------------------------------------------------------------------- +// Static Constants +// ----------------------------------------------------------------------------- + +/* + * @brief LUT to convert MicroUI image format to VGLite image format + */ +const vg_lite_buffer_format_t __microui_to_vg_lite_format[] = { + VG_LITE_RGB565, // MICROUI_IMAGE_FORMAT_LCD = 0, + VG_LITE_UNKNOWN_FORMAT, // UNKNOWN = 1, + VG_LITE_RGBA8888, // MICROUI_IMAGE_FORMAT_ARGB8888 = 2, + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_RGB888 = 3, unsupported + VG_LITE_RGB565, // MICROUI_IMAGE_FORMAT_RGB565 = 4, + VG_LITE_RGBA5551, // MICROUI_IMAGE_FORMAT_ARGB1555 = 5 + VG_LITE_RGBA4444, // MICROUI_IMAGE_FORMAT_ARGB4444 = 6, + VG_LITE_A4, // MICROUI_IMAGE_FORMAT_A4 = 7, + VG_LITE_A8, // MICROUI_IMAGE_FORMAT_A8 = 8, + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_LRGB888 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_LARGB8888 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_A2 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_A1 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_C4 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_C2 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_C1 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_AC44 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_AC22 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_AC11 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_F8 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_F4 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_F2 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_F1 + VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_A8_RLE + VG_LITE_RGBA8888, // MICROUI_IMAGE_FORMAT_ARGB8888_PRE + VG_LITE_RGBA5551, // MICROUI_IMAGE_FORMAT_ARGB1555_PRE + VG_LITE_RGBA4444, // MICROUI_IMAGE_FORMAT_ARGB4444_PRE + // outside of the table ... MICROUI_IMAGE_FORMAT_CUSTOM = 255, +}; + +/* + * @brief Look Up Table to translate MicroUI image to BPP + */ +static const int __microui_to_bpp[] = { + (5+6+5), // MICROUI_IMAGE_FORMAT_LCD = 0 = RGB565, + DISPLAY_UNKNOWN_FORMAT, // UNKNOWN = 1, + (4*8), // MICROUI_IMAGE_FORMAT_ARGB8888 = 2, + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_RGB888 = 3, unsupported + (5+6+5), // MICROUI_IMAGE_FORMAT_RGB565 = 4, + (1+(3*5)), // MICROUI_IMAGE_FORMAT_ARGB1555 = 5, + (4*4), // MICROUI_IMAGE_FORMAT_ARGB4444 = 6, + 4, // MICROUI_IMAGE_FORMAT_A4 = 7, + 8, // MICROUI_IMAGE_FORMAT_A8 = 8, + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_LRGB888 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_LARGB8888 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_A2 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_A1 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_C4 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_C2 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_C1 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_AC44 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_AC22 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_AC11 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_F8 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_F4 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_F2 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_F1 + DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_A8_RLE + (4*8), // MICROUI_IMAGE_FORMAT_ARGB8888_PRE + (1+(3*5)), // MICROUI_IMAGE_FORMAT_ARGB1555_PRE + (4*4), // MICROUI_IMAGE_FORMAT_ARGB4444_PRE + // outside of the table ... MICROUI_IMAGE_FORMAT_CUSTOM = 255, +}; + +/* + * @brief Look Up Table to enable the premultiplication according to MicroUI image format + */ +static const bool __microui_to_premul[] = { + false, // MICROUI_IMAGE_FORMAT_LCD = 0 = RGB565, + false, // UNKNOWN = 1, + true, // MICROUI_IMAGE_FORMAT_ARGB8888 = 2, + false, // MICROUI_IMAGE_FORMAT_RGB888 = 3, unsupported + false, // MICROUI_IMAGE_FORMAT_RGB565 = 4, + true, // MICROUI_IMAGE_FORMAT_ARGB1555 = 5, + true, // MICROUI_IMAGE_FORMAT_ARGB4444 = 6, + // outside of the table ... false, +}; + +// ----------------------------------------------------------------------------- +// Private functions +// ----------------------------------------------------------------------------- + +/* + * @brief Configures a vg_lite buffer for a RGB565 image + * + * @param[in] b: buffer to configure + */ +static void __buffer_default_configuration(vg_lite_buffer_t* b) { + /* Reset planar. */ + b->yuv.uv_planar = 0; + b->yuv.v_planar = 0; + b->yuv.alpha_planar = 0; + + b->tiled = VG_LITE_LINEAR; + b->format = VG_LITE_RGB565; + b->handle = NULL; + b->memory = NULL; + b->address = 0; + b->yuv.swizzle = VG_LITE_SWIZZLE_UV; + b->image_mode = VG_LITE_NORMAL_IMAGE_MODE; + b->transparency_mode = VG_LITE_IMAGE_OPAQUE; +} + +/* + * @brief Configures and return current vg_lite buffer for the given image (address and size) + * + * @param[in] image: image from which buffer should be configured + * @param[in] b: buffer to configure + */ +static void __buffer_set_address_and_size(MICROUI_Image* image, vg_lite_buffer_t* b) { + b->width = image->width; + b->height = image->height; + b->stride = LLUI_DISPLAY_getStrideInBytes(image); + b->memory = (void*)LLUI_DISPLAY_getBufferAddress(image); + b->address = (uint32_t)LLUI_DISPLAY_getBufferAddress(image); +} + +/* + * @brief Convert MICROUI_ImageFormat to vg_lite_buffer_format_t + * + * @param[in] microui_format: MicroUI image format + */ +static vg_lite_buffer_format_t __convert_format(MICROUI_ImageFormat microui_format) { + vg_lite_buffer_format_t vg_lite_format = VG_LITE_UNKNOWN_FORMAT; + if (microui_format < (sizeof(__microui_to_vg_lite_format) / sizeof(__microui_to_vg_lite_format[0]))) { + vg_lite_format = __microui_to_vg_lite_format[microui_format]; + } + + return vg_lite_format; +} + +static vg_lite_buffer_format_t __convert_input_format(MICROUI_Image* image) { + MICROUI_ImageFormat microui_format = (MICROUI_ImageFormat)image->format; + vg_lite_buffer_format_t vg_lite_format = __convert_format(microui_format); + + if (VG_LITE_UNKNOWN_FORMAT != vg_lite_format) { + + // check if the image pixels must be pre-multiplied with the opacity + bool premul_required; + if (LLUI_DISPLAY_isTransparent(image) && (microui_format < (sizeof(__microui_to_premul) / sizeof(__microui_to_premul[0])))) { + premul_required = __microui_to_premul[microui_format]; + } + else { + premul_required = false; + } + + if (premul_required) { + if (VG_LITE_SUCCESS != vg_lite_enable_premultiply()) { + // pre-multiplication cannot be enabled or unsupported +#ifndef VGLITE_USE_GPU_FOR_TRANSPARENT_IMAGES + // cannot draw a transparent image without applying a pre-multiplication + vg_lite_format = VG_LITE_UNKNOWN_FORMAT; +#endif // VGLITE_USE_GPU_FOR_TRANSPARENT_IMAGES + } + } + else if (!UI_VGLITE_need_to_premultiply() && (VG_LITE_SUCCESS != vg_lite_disable_premultiply())) { + // have to disable the premultiplication but cannot + UI_VGLITE_IMPL_error(false, "vg_lite engine premultiply error: cannot disable the pre multiplication"); + } + else { + // premultiplication useless and nothing to disable + // -> nothing to do + } + } + + return vg_lite_format; +} + +// ----------------------------------------------------------------------------- +// Low Level API [optional]: weak functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void UI_VGLITE_IMPL_notify_gpu_start(void) { + // does nothing by default +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void UI_VGLITE_IMPL_notify_gpu_stop(void) { + // does nothing by default +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void UI_VGLITE_IMPL_error(bool critical, const char* format, ...) { + (void)format; + while (critical){} +} + +// ----------------------------------------------------------------------------- +// ui_vglite.h functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +void UI_VGLITE_init(void* binary_semaphore) { + vg_lite_error_t ret = VG_LITE_SUCCESS; + + // Initialize the VGLite library and it's tesselation buffer. + ret = vg_lite_init(VGLITE_TESSELATION_WIDTH, VGLITE_TESSELATION_HEIGHT); + if (VG_LITE_SUCCESS != ret) { + UI_VGLITE_IMPL_error(true, "vg_lite engine init failed: vg_lite_init() returned error %d", ret); + } + + // Configures the vg_lite destination buffer for a RGB565 image + __buffer_default_configuration(&destination_buffer); + + // Enable by default hardware rendering + UI_VGLITE_enable_hardware_rendering(); + + vg_lite_operation_semaphore = binary_semaphore; +} + +void UI_VGLITE_enable_hardware_rendering(void) { +#ifdef VGLITE_OPTION_TOGGLE_GPU + hardware_rendering = true; +#endif +} + +// See the header file for the function documentation +void UI_VGLITE_disable_hardware_rendering(void) { +#ifdef VGLITE_OPTION_TOGGLE_GPU + hardware_rendering = false; +#endif +} + +// See the header file for the function documentation +void UI_VGLITE_toggle_hardware_rendering(void) { +#ifdef VGLITE_OPTION_TOGGLE_GPU + hardware_rendering = !hardware_rendering; +#endif +} + +// See the header file for the function documentation +bool UI_VGLITE_is_hardware_rendering_enabled(void) { +#ifdef VGLITE_OPTION_TOGGLE_GPU + return hardware_rendering; +#else + return true; +#endif +} + +// See the header file for the function documentation +vg_lite_buffer_t* UI_VGLITE_configure_destination(MICROUI_GraphicsContext* gc) { + MICROUI_Image* image = &gc->image; + + if (!LLUI_DISPLAY_isLCD(image) || ((uint32_t)LLUI_DISPLAY_getBufferAddress(image) != destination_buffer.address)) { + // we target an image or the previous destination was not the display + // -> have to use another context to force vg_lite to reload the new context + __buffer_set_address_and_size(image, &destination_buffer); + destination_buffer.format = __convert_format((MICROUI_ImageFormat)image->format); + } + // else: we target the display which is the same destination as for the previous drawing: nothing to do + + vg_lite_irq_operation = IRQ_BYPASS; // do nothing in the IRQ routine + UI_VGLITE_IMPL_notify_gpu_start(); + + return &destination_buffer; +} + +// See the header file for the function documentation +bool UI_VGLITE_configure_source(vg_lite_buffer_t *buffer, MICROUI_Image* image) { + + bool ret = false; + + uint32_t stride = LLUI_DISPLAY_getStrideInBytes(image); + + if (LLUI_DISPLAY_IMPL_getNewImageStrideInBytes(image->format, image->width, image->height, stride) == stride){ + vg_lite_buffer_format_t format = __convert_input_format(image); + + if (VG_LITE_UNKNOWN_FORMAT != format) { + + __buffer_default_configuration(buffer); + __buffer_set_address_and_size(image, buffer); + + buffer->image_mode = VG_LITE_MULTIPLY_IMAGE_MODE; // image only + buffer->transparency_mode = VG_LITE_IMAGE_TRANSPARENT; + buffer->format = format; + buffer->stride = stride; + ret = true; + } + } + // else: frame buffer does not respect VGLite alignment + + return ret; +} + +// See the header file for the function documentation +void UI_VGLITE_start_operation(bool wakeup_graphics_engine) { + vg_lite_irq_operation = wakeup_graphics_engine ? IRQ_WAKEUP_GRAPHICS_ENGINE : IRQ_WAKEUP_TASK; + + // VG drawing has been added to the GPU commands list: ask to submit VG operation + vg_lite_flush(); + + if (!wakeup_graphics_engine) { + // active waiting until the GPU interrupt is thrown + LLUI_DISPLAY_IMPL_binarySemaphoreTake(vg_lite_operation_semaphore); + } +} + +// See the header file for the function documentation +DRAWING_Status UI_VGLITE_post_operation(MICROUI_GraphicsContext* gc, vg_lite_error_t vg_lite_error) { + DRAWING_Status ret; + if (VG_LITE_SUCCESS != vg_lite_error) { + // GPU is useless now, can be disabled. No GPU access should be done after this line + UI_VGLITE_IMPL_notify_gpu_stop(); + ret = UI_VGLITE_report_vglite_error(gc, vg_lite_error); + } else { + // start GPU operation and do not wait for it to end + UI_VGLITE_start_operation(true); + ret = DRAWING_RUNNING; + } + + if (!UI_VGLITE_need_to_premultiply() && (VG_LITE_SUCCESS != vg_lite_enable_premultiply())) { + // cannot restore premultiplication + UI_VGLITE_IMPL_error(false, "vg_lite engine premultiply error: cannot restore the pre multiplication"); + } + + return ret; +} + +// See the header file for the function documentation +uint32_t UI_VGLITE_premultiply_alpha(uint32_t color, uint8_t alpha) { + uint32_t ret; + + if (alpha == (uint8_t)0) { + ret = 0; + } + else if(alpha == (uint8_t)0xff) { + ret = color; + } + else { + uint8_t red = (uint8_t)( + (uint32_t)(alpha * COLOR_GET_CHANNEL(color, ARGB8888, RED)) + / (uint32_t)0xff); + uint8_t green = (uint8_t)( + (uint32_t)(alpha * COLOR_GET_CHANNEL(color, ARGB8888, GREEN)) + / (uint32_t)0xff); + uint8_t blue = (uint8_t)( + (uint32_t)(alpha * COLOR_GET_CHANNEL(color, ARGB8888, BLUE)) + / (uint32_t)0xff); + ret = COLOR_SET_COLOR(alpha, red, green, blue, ARGB8888); + } + return ret; +} + +// See the header file for the function documentation +uint32_t UI_VGLITE_premultiply(uint32_t color) { + uint8_t alpha = COLOR_GET_CHANNEL(color, ARGB8888, ALPHA); + return UI_VGLITE_premultiply_alpha(color, alpha); +} + +// See the header file for the function documentation +bool UI_VGLITE_need_to_premultiply(void) { + return !vg_lite_query_feature(gcFEATURE_BIT_VG_PE_PREMULTIPLY); +} + +// See the header file for the function documentation +vg_lite_color_t UI_VGLITE_get_vglite_color(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint alpha) { + jint fc; + + switch(img->format) { + case MICROUI_IMAGE_FORMAT_A4: + case MICROUI_IMAGE_FORMAT_A8: + if (UI_VGLITE_need_to_premultiply()) { + // hardware does not manage the pre-multiplication: the src color must be pre-multiplied + fc = UI_VGLITE_premultiply_alpha(gc->foreground_color, alpha); + } + else { + // hardware manages the pre-multiplication (even if it has been disabled because not applicable + // for the "picto" images): the src color must stay as is + fc = (alpha << 24) | (gc->foreground_color & 0xFFFFFF); + } + break; + default: + if (UI_VGLITE_need_to_premultiply()) { + // hardware does not manage the pre-multiplication: the color is used as "pre-multiplied" factor + // for all pixel components (A-R-G-B) + fc = alpha * 0x01010101; + } + else { + // hardware manages the pre-multiplication + // - pre-multiplication enabled: keep the image pixels values and use the opacity as + // "pre-multiplied" factor + // - pre-multiplication disabled: the image pixels are already pre-multiplied: keep the image + // pixels values and use the opacity as "pre-multiplied" factor + fc = (alpha << 24) | 0xFFFFFF; + } + break; + } + + return (vg_lite_color_t)fc; +} + +// See the header file for the function documentation +void UI_VGLITE_IRQHandler(void) { + + // retrieve the post operation to perform and reset it + vglite_irq_post_operation_t operation = vg_lite_irq_operation; + vg_lite_irq_operation = IRQ_BYPASS; + + switch(operation) { + + default: // should not occur + case IRQ_BYPASS: { + // Nothing to do: an automatic flush() has been made by the vg_lite engine to free the command buffer. + // After this interrupt, the vg_lite engine is waked-up (see vg_lite_os_wait_interrupt()) and fills the + // command buffer with the new pending command (command added by a VEE drawing). + break; + } + + case IRQ_WAKEUP_TASK :{ + // The intermediate drawing of a "big" drawing is performed: wakes-up the drawer (the caller of + // UI_VGLITE_start_operation()) to draw the next steps of this "big" drawing (text, raw image, + // bvi, etc.). + LLUI_DISPLAY_IMPL_binarySemaphoreGive(vg_lite_operation_semaphore, true); + break; + } + + case IRQ_WAKEUP_GRAPHICS_ENGINE :{ + uint8_t it = interrupt_enter(); + + // The "simple" drawing or the last step of the "big" drawing is made: wakes-up the Graphics Engine to + // notify the end of the drawing and unlock the next application drawing. + LLUI_DISPLAY_notifyAsynchronousDrawingEnd(true); + + // GPU is useless now, can be disabled. No GPU access should be done after this line + UI_VGLITE_IMPL_notify_gpu_stop(); + + interrupt_leave(it); + + break; + } + } +} + +// See the header file for the function documentation +bool UI_VGLITE_enable_vg_lite_scissor(MICROUI_GraphicsContext* gc) { + + bool ret; + int32_t width = UI_RECT_get_width(&gc->clip); + int32_t height = UI_RECT_get_height(&gc->clip); + + if (LLUI_DISPLAY_isClipEnabled(gc)) { + + if ((width > 0) && (height > 0)) { + // not "empty" clip + + // enable scissor for next vglite drawing + vg_lite_enable_scissor(); + vg_lite_set_scissor(gc->clip.x1, gc->clip.y1, width, height); + + // perform drawing + ret = true; + } + else { + // empty clip: nothing to draw + ret = false; + } + } + else { + // clip is disabled : + + // disable scissor (vglite lib already crops to the buffer bounds) + vg_lite_disable_scissor(); + + // perform drawing + ret = true; + } + + return ret; +} + +// See the header file for the function documentation +bool UI_VGLITE_enable_vg_lite_scissor_region(MICROUI_GraphicsContext* gc, int x1, int y1, int x2, int y2) { + + bool ret; + + if (LLUI_DISPLAY_isClipEnabled(gc)) { + + if (LLUI_DISPLAY_clipRectangle(gc, (jint*)&x1, (jint*)&y1, (jint*)&x2, (jint*)&y2)) { + // drawing fully or partially fits the clip: + + // enable scissor for next vglite drawing + vg_lite_enable_scissor(); + vg_lite_set_scissor(gc->clip.x1, gc->clip.y1, gc->clip.x2 - gc->clip.x1 + 1, gc->clip.y2 - gc->clip.y1 + 1); + + // perform drawing + ret = true; + } + else { + // drawing is fully outside the clip, nothing to draw + ret = false; + } + } + else { + // clip is disabled : + + // disable scissor (vglite lib already crops to the buffer bounds) + vg_lite_disable_scissor(); + + // perform drawing + ret = true; + } + + return ret; +} + +// See the header file for the function documentation +bool UI_VGLITE_enable_vg_lite_scissor_area(MICROUI_GraphicsContext* gc, jfloat width, jfloat height, jfloat* matrix) { + + bool ret; + + if (LLUI_DISPLAY_isClipEnabled(gc)) { + + // Transform each corners points of the image viewbox + // top/left, not impacted by scale and rotate + int x0 = (int) matrix[2]; + int y0 = (int) matrix[5]; + + // top/right + int x1 = (int) ((width * matrix[0]) + x0); + int y1 = (int) ((width * matrix[3]) + y0); + + // bottom/Left + int x2 = (int) ((height * matrix[1]) + x0); + int y2 = (int) ((height * matrix[4]) + y0); + + // bottom/right + int x3 = (int) (x2 + x1 - x0); + int y3 = (int) (y2 + y1 - y0); + + // Compute the clipping area from all points + int render_area_x = MEJ_MIN(x0, MEJ_MIN(x1, MEJ_MIN(x2, x3))); + int render_area_y = MEJ_MIN(y0, MEJ_MIN(y1, MEJ_MIN(y2, y3))); + int render_area_width = MEJ_MAX(x0, MEJ_MAX(x1, MEJ_MAX(x2, x3))) - render_area_x ; + int render_area_height = MEJ_MAX(y0, MEJ_MAX(y1, MEJ_MAX(y2, y3))) - render_area_y; + + // get GC clip + int master_clip_x = gc->clip.x1; + int master_clip_y = gc->clip.y1; + int master_clip_width = UI_RECT_get_width(&gc->clip); + int master_clip_height = UI_RECT_get_height(&gc->clip); + + // crop x + if (render_area_x < master_clip_x) { + //-> decrease width and set x to the minimum coordinate + render_area_width -= master_clip_x - render_area_x; + render_area_x = master_clip_x; + } + + // crop y + if (render_area_y < master_clip_y) { + //-> decrease height and set y to the minimum coordinate + render_area_height -= master_clip_y - render_area_y; + render_area_y = master_clip_y; + } + + int master_clip_outside_x = master_clip_x + master_clip_width; + int master_clip_outside_y = master_clip_y + master_clip_height; + + if (render_area_x >= master_clip_outside_x) { + // expected X is out of clip on the right: set an empty clip + render_area_width = 0; + } else { + // crop x+width, width is set to 0 if negative (empty clip) + render_area_width = MEJ_MAX(0, MEJ_MIN(render_area_width, master_clip_outside_x - render_area_x)); + } + + if (render_area_y >= master_clip_outside_y) { + // expected Y is out of clip on the bottom: set an empty clip + render_area_height = 0; + } else { + // crop y+height, height is set to 0 if negative (empty clip) + render_area_height = MEJ_MAX(0, MEJ_MIN(render_area_height, master_clip_outside_y - render_area_y)); + } + + if ((0 < render_area_width) && (0 < render_area_height)) { + vg_lite_enable_scissor(); + vg_lite_set_scissor(render_area_x, render_area_y, render_area_width, render_area_height); + + // perform drawing + ret = true; + } + else { + // drawing is fully outside the clip, nothing to draw + ret = false; + } + } + else { + // clip is disabled : + + // disable scissor (vglite lib already crops to the buffer bounds) + vg_lite_disable_scissor(); + + // perform drawing + ret = true; + } + + return ret; +} + +// See the header file for the function documentation +int32_t UI_VGLITE_get_bpp(MICROUI_ImageFormat image_format) { + int bpp = DISPLAY_UNKNOWN_FORMAT; + + if ((int) image_format < (int)(sizeof(__microui_to_bpp) / sizeof(__microui_to_bpp[0]))) { + bpp = __microui_to_bpp[image_format]; + } + + return (DISPLAY_UNKNOWN_FORMAT == bpp) ? -1 : bpp; +} + +// See the header file for the function documentation +DRAWING_Status UI_VGLITE_report_vglite_error(MICROUI_GraphicsContext* gc, vg_lite_error_t vg_lite_error) { + UI_VGLITE_IMPL_error(false, "vg_lite operation failed with error: %d\n", vg_lite_error); + LLUI_DISPLAY_reportError(gc, DRAWING_LOG_LIBRARY_INCIDENT | ((VG_LITE_OUT_OF_MEMORY == vg_lite_error) ? DRAWING_LOG_OUT_OF_MEMORY : 0)); + return DRAWING_DONE; +} + +// ----------------------------------------------------------------------------- +// ui_drawing.h functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +uint32_t UI_DRAWING_getNewImageStrideInBytes(jbyte image_format, uint32_t image_width, uint32_t image_height, uint32_t default_stride) { + + (void)image_height; + + uint32_t bpp = UI_VGLITE_get_bpp((MICROUI_ImageFormat)image_format); + uint32_t ret; + + if (-1 != bpp) { + // VGLite library requires a stride on 16 pixels + uint32_t stride = ALIGN(image_width, 16u); + ret = (stride * bpp) / 8u; + } + else { + // unsupported format + ret = default_stride; + } + + return ret; +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/inc/mej_debug.h b/bsp/projects/microej/util/inc/mej_debug.h similarity index 84% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/inc/mej_debug.h rename to bsp/projects/microej/util/inc/mej_debug.h index e46b270..c6aae13 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/inc/mej_debug.h +++ b/bsp/projects/microej/util/inc/mej_debug.h @@ -2,7 +2,8 @@ * C * * Copyright 2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ #if !defined __MEJ_DEBUG_H__ diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/inc/mej_disable.h b/bsp/projects/microej/util/inc/mej_disable.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/inc/mej_disable.h rename to bsp/projects/microej/util/inc/mej_disable.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/inc/mej_log.h b/bsp/projects/microej/util/inc/mej_log.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/inc/mej_log.h rename to bsp/projects/microej/util/inc/mej_log.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/inc/mej_math.h b/bsp/projects/microej/util/inc/mej_math.h similarity index 92% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/inc/mej_math.h rename to bsp/projects/microej/util/inc/mej_math.h index 133b941..c2cf54a 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/inc/mej_math.h +++ b/bsp/projects/microej/util/inc/mej_math.h @@ -1,15 +1,15 @@ /* * C * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. + * Copyright 2020-2024 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ /* * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite + * @brief MicroEJ MicroUI library low level API: implementation over VGLite * @author MicroEJ Developer Team - * @version 3.0.0 + * @version 8.0.1 */ #if !defined MEJ_MATH_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/inc/pool.h b/bsp/projects/microej/util/inc/pool.h similarity index 85% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/inc/pool.h rename to bsp/projects/microej/util/inc/pool.h index fc65217..060af3e 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/inc/pool.h +++ b/bsp/projects/microej/util/inc/pool.h @@ -1,10 +1,13 @@ + /* * C * * Copyright 2014-2021 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ + /* * The module provide function to simply manage a * Fixed memory pool size. diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/src/mej_debug.c b/bsp/projects/microej/util/src/mej_debug.c similarity index 78% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/src/mej_debug.c rename to bsp/projects/microej/util/src/mej_debug.c index 7dad098..2a1b80a 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/src/mej_debug.c +++ b/bsp/projects/microej/util/src/mej_debug.c @@ -2,7 +2,8 @@ * C * * Copyright 2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ // ----------------------------------------------------------------------------- @@ -31,4 +32,4 @@ void MEJ_DEBUG_enable(int level) { void MEJ_DEBUG_disable(int level) { __mej_debug_lvls &= ~(level); -} +} \ No newline at end of file diff --git a/bsp/projects/microej/util/src/mej_math.c b/bsp/projects/microej/util/src/mej_math.c new file mode 100644 index 0000000..6bcb030 --- /dev/null +++ b/bsp/projects/microej/util/src/mej_math.c @@ -0,0 +1,70 @@ +/* + * C + * + * Copyright 2019-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief MicroEJ MicroUI library low level API: implementation over VGLite + * @author MicroEJ Developer Team + * @version 8.0.1 + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include "mej_math.h" + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +/* + * @brief Enables the use of power quad (if available). + * + * If this feature is enabled, mathematic operations use the power quad. + * If this feature is disabled, mathematic operations use the compiler C library. + */ +#ifndef VG_FEATURE_POWERQUAD +#define VG_FEATURE_POWERQUAD __has_include("fsl_powerquad.h") +#if defined VG_FEATURE_POWERQUAD && VG_FEATURE_POWERQUAD +#include "fsl_powerquad.h" +#else +#include +#endif +#endif + +// ----------------------------------------------------------------------------- +// mej_math.h functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +float32_t mej_tan_f32(float32_t value) { +#if defined VG_FEATURE_POWERQUAD && VG_FEATURE_POWERQUAD + float32_t cos; + float32_t sin; + PQ_CosF32(&value, &cos); + PQ_SinF32(&value, &sin); + PQ_DivF32(&sin, &cos, &value); + return value; +#else + return tanf(value); +#endif +} + +// See the header file for the function documentation +float32_t mej_sqrt_f32(float32_t value) { +#if defined VG_FEATURE_POWERQUAD && VG_FEATURE_POWERQUAD + PQ_SqrtF32(&value, &value); + return value; +#else + return sqrtf(value); +#endif +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/src/pool.c b/bsp/projects/microej/util/src/pool.c similarity index 86% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/src/pool.c rename to bsp/projects/microej/util/src/pool.c index dfd9674..5fe4e7b 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/src/pool.c +++ b/bsp/projects/microej/util/src/pool.c @@ -2,7 +2,8 @@ * C * * Copyright 2014-2021 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. + * This library is provided in source code for use, modification and test, subject to license terms. + * Any modification of the source code will break MicroEJ Corp. warranties on the whole library. */ #include diff --git a/bsp/projects/microej/vg/inc/bvi_vglite.h b/bsp/projects/microej/vg/inc/bvi_vglite.h new file mode 100644 index 0000000..dba4150 --- /dev/null +++ b/bsp/projects/microej/vg/inc/bvi_vglite.h @@ -0,0 +1,122 @@ +/* + * C + * + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief Provides some functions to draw VGLite elements on a BufferedVectorImage + * (in VGLite internal format). + * + * @author MicroEJ Developer Team + * @version 7.0.1 + */ + +#if !defined BVI_VGLITE_H +#define BVI_VGLITE_H + +#if defined __cplusplus +extern "C" { +#endif + +#include "microvg_configuration.h" +#if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include + +#include "vg_lite.h" + +// -------------------------------------------------------------------------------- +// Public API +// -------------------------------------------------------------------------------- + +/* + * @brief Adjusts the image data size to store the implementation of the BufferedVectorImage. + * + * @see See ui_drawing.h + */ +void BVI_VGLITE_adjust_new_image_characteristics(uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment) ; + +/* + * @brief Initializes the BufferedVectorImage. + * + * @see See ui_drawing.h + */ +void BVI_VGLITE_initialize_new_image(MICROUI_Image* image); + +/* + * @brief Closes the BufferedVectorImage's resources. + * + * @see See ui_drawing.h + */ +void BVI_VGLITE_free_resources(MICROUI_Image* image); + +/* + * @brief Adds an operation "draw path with a color" in the BufferedVectorImage. + * + * @param[in] target: the BufferedVectorImage. + * + * @return MicroVG error code + * + * @see vg_lite_draw() + */ +jint BVI_VGLITE_add_draw_path( + void* target, + vg_lite_path_t * path, + vg_lite_fill_t fill_rule, + vg_lite_matrix_t * matrix, + vg_lite_blend_t blend, + vg_lite_color_t color); + +/* + * @brief Adds an operation "draw path with a gradient" in the BufferedVectorImage. + * + * @param[in] target: the BufferedVectorImage. + * + * @return MicroVG error code + * + * @see vg_lite_draw_gradient() + */ +jint BVI_VGLITE_add_draw_gradient( + void* target, + vg_lite_path_t * path, + vg_lite_fill_t fill_rule, + vg_lite_matrix_t * matrix, + vg_lite_linear_gradient_t * grad, + vg_lite_blend_t blend) ; + +/* + * @brief Adds an operation "draw VG image" in the BufferedVectorImage. If the image + * is a BufferedVectorImage, the all its operations are copied into the destination. + * If the image is an image in flash, an operation that points on the image is added. + * + * @param[in] target: the BufferedVectorImage. + * + * @return MicroVG error code + * + * @see vg_drawing.h + */ +jint BVI_VGLITE_add_draw_image( + void* target, + void* image, + jfloat* drawing_matrix, + jint alpha, + jlong elapsed, + const float color_matrix[]); + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#endif // #if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +#ifdef __cplusplus +} +#endif +#endif // !defined BVI_VGLITE_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_configuration.h b/bsp/projects/microej/vg/inc/microvg_configuration.h similarity index 81% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_configuration.h rename to bsp/projects/microej/vg/inc/microvg_configuration.h index a9c59b7..646848f 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_configuration.h +++ b/bsp/projects/microej/vg/inc/microvg_configuration.h @@ -1,7 +1,7 @@ /* * C * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. + * Copyright 2020-2023 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -10,7 +10,6 @@ * @brief MicroEJ MicroVG library low level API: enable some features according to * the hardware capacities. * @author MicroEJ Developer Team -* @version 1.0.0 */ #if !defined MICROVG_CONFIGURATION_H @@ -30,7 +29,7 @@ extern "C" { * This value must not be changed by the user of the CCO. * This value must be incremented by the implementor of the CCO when a configuration define is added, deleted or modified. */ -#define MICROVG_CONFIGURATION_VERSION (1) +#define MICROVG_CONFIGURATION_VERSION (2) // ----------------------------------------------------------------------------- // MicroVG's LinearGradient Options @@ -182,6 +181,36 @@ extern "C" { #define VG_FEATURE_FONT_COMPLEX_LAYOUT_HEAP_SIZE ( 80 * 1024 ) #endif +/* + * @brief Set this define to enable the support of MicroVG BufferedVectorImage. + * This feature requires the available number of supported GraphicsContext formats + * is higher than 1. + * + * Comment the define VG_FEATURE_BUFFERED_VECTOR_IMAGE to remove the support of + * BufferedVectorImage (even if the available number of supported GraphicsContext + * formats is higher than 1). + */ +#if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +/* + * @brief Comment the define VG_FEATURE_BUFFERED_VECTOR_IMAGE to remove the support + * of BufferedVectorImage (even if the available number of supported GraphicsContext + * formats is higher than 1). + */ +#define VG_FEATURE_BUFFERED_VECTOR_IMAGE + +/* + * @brief The drawing functions to target the BufferedVectorImage have by default the + * identifier 1. + */ +#ifndef UI_DRAWING_IDENTIFIER_BVI_FORMAT +#define UI_DRAWING_IDENTIFIER_BVI_FORMAT 1 +#endif + +#elif defined(VG_FEATURE_BUFFERED_VECTOR_IMAGE) +#error "The BufferedVectorImage feature requires the support of several Graphics Context formats". +#endif + // ----------------------------------------------------------------------------- // EOF // ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_font_freetype.h b/bsp/projects/microej/vg/inc/microvg_font_freetype.h similarity index 92% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_font_freetype.h rename to bsp/projects/microej/vg/inc/microvg_font_freetype.h index d16b3e7..36d25c2 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_font_freetype.h +++ b/bsp/projects/microej/vg/inc/microvg_font_freetype.h @@ -1,7 +1,7 @@ /* * C * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. + * Copyright 2020-2023 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -9,7 +9,7 @@ * @file * @brief MicroEJ MicroVG library low level API: implementation over FreeType. * @author MicroEJ Developer Team -* @version 2.0.0 +* @version 5.0.0 */ #if !defined MICROVG_FONT_FREETYPE_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_gradient.h b/bsp/projects/microej/vg/inc/microvg_gradient.h similarity index 89% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_gradient.h rename to bsp/projects/microej/vg/inc/microvg_gradient.h index d51b698..69570e0 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_gradient.h +++ b/bsp/projects/microej/vg/inc/microvg_gradient.h @@ -1,7 +1,7 @@ /* * C * - * Copyright 2022 MicroEJ Corp. All rights reserved. + * Copyright 2022-2023 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -9,7 +9,7 @@ * @file * @brief MicroEJ MicroVG library low level API: implementation of LinearGradient. * @author MicroEJ Developer Team - * @version 2.0.0 + * @version 5.0.0 */ #if !defined MICROVG_GRADIENT_H @@ -37,13 +37,12 @@ extern "C" { // Structs // ----------------------------------------------------------------------------- +#if (VG_FEATURE_GRADIENT == VG_FEATURE_GRADIENT_FULL) + /* * @brief Map a jint array that represents a linear gradient */ -typedef struct MICROVG_GRADIENT_HEADER -{ - -#if (VG_FEATURE_GRADIENT == VG_FEATURE_GRADIENT_FULL) +typedef struct { jint count; // number of colors and positions jfloat x; jfloat y; @@ -51,13 +50,8 @@ typedef struct MICROVG_GRADIENT_HEADER jfloat length; jint colors_offset; jint positions_offset; -#else - jint color; // only one color -#endif } MICROVG_GRADIENT_HEADER_t; -#if (VG_FEATURE_GRADIENT == VG_FEATURE_GRADIENT_FULL) - // ----------------------------------------------------------------------------- // Specific gradient formatting functions [mandatory] // ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_helper.h b/bsp/projects/microej/vg/inc/microvg_helper.h similarity index 84% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_helper.h rename to bsp/projects/microej/vg/inc/microvg_helper.h index 70b0412..383b059 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_helper.h +++ b/bsp/projects/microej/vg/inc/microvg_helper.h @@ -1,7 +1,7 @@ /* * C * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. + * Copyright 2020-2023 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -10,7 +10,7 @@ * @brief MicroEJ MicroVG library low level API: helper to implement library natives * methods. * @author MicroEJ Developer Team -* @version 2.0.0 +* @version 5.0.0 */ #if !defined MICROVG_HELPER_H @@ -86,7 +86,16 @@ extern "C" { void MICROVG_HELPER_initialize(void); /** - * @brief Gets the next UTF character from a text buffer. + * @brief Gets the UTF character from a text buffer at the given offset and updates + * the offset to point to the next character. + * + * Some characters have some special values; they are made up of two Unicode characters + * in two specific ranges such that the first Unicode character is in one range (for + * example 0xD800-0xD8FF) and the second Unicode character is in the second range (for + * example 0xDC00-0xDCFF). This is called a surrogate pair. + * + * If a surrogate pair is incomplete (missing second character), this function returns + * "0" (error) and does not update the offset. * * @param[in] text: text buffer encoded in UTF16 where to read UTF character. * @param[in] length: lenght of the text buffer. @@ -97,7 +106,6 @@ void MICROVG_HELPER_initialize(void); */ int MICROVG_HELPER_get_utf(unsigned short *text, int length, int *offset); - /* * @brief Configures the font layouter with a font and a text * diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_path.h b/bsp/projects/microej/vg/inc/microvg_path.h similarity index 91% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_path.h rename to bsp/projects/microej/vg/inc/microvg_path.h index 387ae7e..b69d895 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_path.h +++ b/bsp/projects/microej/vg/inc/microvg_path.h @@ -1,7 +1,7 @@ /* * C * - * Copyright 2022 MicroEJ Corp. All rights reserved. + * Copyright 2022-2023 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -9,7 +9,7 @@ * @file * @brief MicroEJ MicroVG library low level API: implementation of Path. * @author MicroEJ Developer Team -* @version 2.0.0 +* @version 5.0.0 */ #if !defined MICROVG_PATH_H @@ -36,10 +36,8 @@ extern "C" { /* * @brief Map a jbyte array that represents a path */ -typedef struct MICROVG_PATH_HEADER -{ - uint16_t data_size; /* data size (without header) */ - uint16_t data_offset; +typedef struct MICROVG_PATH_HEADER { + uint32_t data_size; /* data size (without header) */ uint8_t format; uint8_t padding1; uint8_t padding2; @@ -75,6 +73,13 @@ uint32_t MICROVG_PATH_convert_path_command(jint command); // Specific path formatting functions [optional] // ----------------------------------------------------------------------------- +/* + * @brief Initializes the path builder. + * + * The default implementation does nothing. + */ +void MICROVG_PATH_initialize(void); + /* * @brief Gets the path's array header size. * diff --git a/bsp/projects/microej/vg/inc/microvg_trace.h b/bsp/projects/microej/vg/inc/microvg_trace.h new file mode 100644 index 0000000..9319bf1 --- /dev/null +++ b/bsp/projects/microej/vg/inc/microvg_trace.h @@ -0,0 +1,132 @@ +/* + * C + * + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + + +#if !defined MICROVG_TRACE_H +#define MICROVG_TRACE_H + +#if defined __cplusplus +extern "C" { +#endif + +/* + * @file + * @brief Provides the logs of the CCO MicroVG. + * @author MicroEJ Developer Team + * @version 5.0.0 + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include "LLTRACE_impl.h" + +// ----------------------------------------------------------------------------- +// Defines +// ----------------------------------------------------------------------------- + +/* + * @brief Available number of events: IMAGE, FONT and DRAWING + */ +#define LOG_MICROVG_EVENTS 3 + +/* + * Events identifiers + */ +#define LOG_MICROVG_IMAGE_ID 0 +#define LOG_MICROVG_FONT_ID 1 +#define LOG_MICROVG_DRAWING_ID 2 + +/* + * @brief Types of Image events + */ +#define LOG_MICROVG_IMAGE_load 0 +#define LOG_MICROVG_IMAGE_create 1 +#define LOG_MICROVG_IMAGE_close 2 + +/* + * @brief Types of Font events + */ +#define LOG_MICROVG_FONT_load 0 +#define LOG_MICROVG_FONT_baseline 1 +#define LOG_MICROVG_FONT_height 2 +#define LOG_MICROVG_FONT_stringWidth 3 +#define LOG_MICROVG_FONT_stringHeight 4 + +/* + * @brief Types of Drawing events + */ +#define LOG_MICROVG_DRAW_path 0 +#define LOG_MICROVG_DRAW_pathGradient 1 +#define LOG_MICROVG_DRAW_string 2 +#define LOG_MICROVG_DRAW_stringGradient 3 +#define LOG_MICROVG_DRAW_stringOnCircle 4 +#define LOG_MICROVG_DRAW_stringOnCircleGradient 5 +#define LOG_MICROVG_DRAW_image 6 + +/* + * @brief Useful macros to concatenate easily some strings and defines. + */ +#define CONCAT_STRINGS(p, s) p ## s +#define CONCAT_DEFINES(p, s) CONCAT_STRINGS(p,s) + +/* + * @brief Macro to add an event and its type. + */ +#define LOG_MICROVG_START(event, type) LLTRACE_IMPL_record_event_u32(vg_trace_group_id, event, type); + +/* + * @brief Macro to notify the end of an event and its type. + */ +#define LOG_MICROVG_END(event, type) LLTRACE_IMPL_record_event_end_u32(vg_trace_group_id, event, type); + +/* The following lines must be added to a SYSVIEW_MicroVG.txt file + in the /Description folder + +NamedType VGImage 0=LOAD_IMAGE +NamedType VGImage 1=CREATE_IMAGE +NamedType VGImage 2=CLOSE_IMAGE + +NamedType VGFont 0=LOAD_FONT +NamedType VGFont 1=FONT_BASELINE +NamedType VGFont 2=FONT_HEIGHT +NamedType VGFont 3=STRING_WIDTH +NamedType VGFont 4=STRING_HEIGHT + +NamedType VGDraw 0=DRAW_PATH +NamedType VGDraw 1=DRAW_PATH_GRADIENT +NamedType VGDraw 2=DRAW_STRING +NamedType VGDraw 3=DRAW_STRING_GRADIENT +NamedType VGDraw 4=DRAW_STRING_ON_CIRCLE +NamedType VGDraw 5=DRAW_STRING_ON_CIRCLE_GRADIENT +NamedType VGDraw 6=DRAW_IMAGE + +0 VG_ImageEvent (MicroVG) Execute image event %VGImage | (MicroVG) Image event %VGImage done +1 VG_FontEvent (MicroVG) Execute font event %VGFont | (MicroVG) Font event %VGFont done +2 VG_DrawingEvent (MicroVG) Execute drawing event %VGDraw | (MicroVG) Drawing event %VGDraw done + + */ + +// ----------------------------------------------------------------------------- +// Extern symbols +// ----------------------------------------------------------------------------- + +/* + * @brief External variable that contains the id for each trace group. + */ +extern int32_t vg_trace_group_id; + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // !defined MICROVG_TRACE_H diff --git a/bsp/projects/microej/vg/inc/microvg_vglite_helper.h b/bsp/projects/microej/vg/inc/microvg_vglite_helper.h new file mode 100644 index 0000000..5576f9e --- /dev/null +++ b/bsp/projects/microej/vg/inc/microvg_vglite_helper.h @@ -0,0 +1,120 @@ +/* + * C + * + * Copyright 2022-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#if !defined MICROVG_VGLITE_HELPER_H +#define MICROVG_VGLITE_HELPER_H + +/** +* @file +* @brief MicroVG library low level API. Provides helper defines and functions to +* manipulates the VGLite objects. +* @author MicroEJ Developer Team +* @version 7.0.1 +*/ + +#if defined __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include +#include + +#include "vg_lite.h" + +/* + * @brief Sets the drawing log flags matching a MicroVG error code. + * + * @see LLUI_DISPLAY_reportError + * + * @param[in] gc: the graphics context holding the drawing log flags. + * @param[in] error: the MicroVG error code. + * + * @return the drawing status that should be return by the calling drawing function. + */ +static inline DRAWING_Status MICROVG_VGLITE_report_error(MICROUI_GraphicsContext* gc, jint error) { + LLUI_DISPLAY_reportError(gc, DRAWING_LOG_LIBRARY_INCIDENT | ((LLVG_OUT_OF_MEMORY == error) ? DRAWING_LOG_OUT_OF_MEMORY : 0)); + return DRAWING_DONE; +} + +/* + * @brief Processes a MicroVG status code and reports the error if needed. + * + * @see MICROVG_VGLITE_report_error + * + * @param[in] gc: the graphics context holding the drawing log flags. + * @param[in] vg_lite_error: the MicroVG status code. + */ +static inline void MICROVG_VGLITE_handle_error(MICROUI_GraphicsContext* gc, jint status) { + if (LLVG_SUCCESS != status) { + (void) MICROVG_VGLITE_report_error(gc, status); + } +} + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +/* + * @brief The vglite matrix can be mapped on a float array + */ +#define MAP_VGLITE_MATRIX(h) ((float*)(((vg_lite_matrix_t*)(h))->m)) + +/* + * @brief The vglite gradient matrix can be mapped on a float array + */ +#define MAP_VGLITE_GRADIENT_MATRIX(h) MAP_VGLITE_MATRIX(&(((vg_lite_linear_gradient_t*)(h))->matrix)) + +// ----------------------------------------------------------------------------- +// API +// ----------------------------------------------------------------------------- + +/* + * @brief Converts the MicroVG blend in a VGLite blend. + * + * @param[in] blend: the drawing's blending + * + * @return the VGLite blend + */ +vg_lite_blend_t MICROVG_VGLITE_HELPER_get_blend(jint blend); + +/* + * @brief Converts the MicroVG fill rule in a VGLite rule. + * + * @param[in] blend: the drawing's fill rule + * + * @return the VGLite fill rule + */ +vg_lite_fill_t MICROVG_VGLITE_HELPER_get_fill_rule(jint fill_type); + +/* + * @brief Converts a MicroVG LinearGradient in a VGLite gradient according to + * the drawing parameters. After this call, the gradient is ready to be updated + * by calling vg_lite_update_grad() + * + * @param[in] gradient: the gradient destination (VGLite gradient) + * @param[in] gradientData: the gradient source + * @param[in] matrix: the gradient source's matrix + * @param[in] globalMatrix: the drawing's matrix + * @param[in] globalAlpha: the drawing's opacity + * + * @return a VGLite error code + */ +vg_lite_error_t MICROVG_VGLITE_HELPER_to_vg_lite_gradient(vg_lite_linear_gradient_t* gradient, jint* gradientData, jfloat* matrix, jfloat* globalMatrix, jint globalAlpha); + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // !defined MICROVG_VGLITE_HELPER_H diff --git a/bsp/projects/microej/vg/inc/vg_drawing.h b/bsp/projects/microej/vg/inc/vg_drawing.h new file mode 100644 index 0000000..e5c8b79 --- /dev/null +++ b/bsp/projects/microej/vg/inc/vg_drawing.h @@ -0,0 +1,182 @@ +/* + * Copyright 2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#if !defined VG_DRAWING_H +#define VG_DRAWING_H +#ifdef __cplusplus +extern "C" { +#endif + + +/* + * @brief Provides drawing functions called by MicroVG native drawing functions. + * + * This header file follows strictly the same concept as ui_drawing.h but for MicroVG + * library. + * + * @see ui_drawing.h + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include + +#include "ui_drawing.h" + +// -------------------------------------------------------------------------------- +// API +// -------------------------------------------------------------------------------- + +/* + * @brief Gets the image size. The image structure format is VEE Port specific. + * + * @param[in] image: the image + * @param[out] width: the image width + * @param[out] height: the image height + */ +void VG_DRAWING_get_image_size(void* image, float* width, float* height); + +/* + * @brief Draws a path filled with the specified color (not the one of the Graphics Context). + * + * @param[in] gc: the destination + * @param[in] path: the path's data + * @param[in] x: the destination X coordinate + * @param[in] y: the destination Y coordinate + * @param[in] matrix: the deformation to apply + * @param[in] fillRule: the fill type + * @param[in] blend: the blend mode + * @param[in] color: the color to apply (with an opacity) + * + * @return the drawing status. + */ +DRAWING_Status VG_DRAWING_drawPath(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color); + +/* + * @brief Draws a path filled with a linear gradient. + * + * @param[in] gc: the destination + * @param[in] path: the path's data + * @param[in] x: the destination X coordinate + * @param[in] y: the destination Y coordinate + * @param[in] matrix: the deformation to apply + * @param[in] fillRule: the fill type + * @param[in] alpha: the global opacity to apply + * @param[in] blend: the blend mode + * @param[in] gradient: the gradient to apply + * @param[in] gradientMatrix: the gradient deformation, may be null (means identity) + * + * @return the drawing status. + */ +DRAWING_Status VG_DRAWING_drawGradient(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradient, jfloat* gradientMatrix); + +/* + * @brief Draws a string with the color of the Graphics Context. + * + * The top/left position of the first drawn character is placed at + * coordinate x/y. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] text the array of characters to draw. + * @param[in] faceHandle the font reference handle. + * @param[in] size the height of the font in pixels. + * @param[in] x the horizontal coordinate of the top/left of the first drawn character. + * @param[in] y the vertical coordinate of the top/left of the first drawn character. + * @param[in] matrix: deformation matrix, may be null (means identity) + * @param[in] alpha the opacity level to apply to the character. + * @param[in] blend the blend mode to use + * @param[in] letterSpacing the extra letter spacing to use + * + * @return the drawing status. + */ +DRAWING_Status VG_DRAWING_drawString(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing); + +/* + * @brief Draws a string with a linear gradient. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] text the array of characters to draw. + * @param[in] faceHandle the font reference handle. + * @param[in] size the height of the font in pixels. + * @param[in] x the horizontal coordinate of the top/left of the first drawn character. + * @param[in] y the vertical coordinate of the top/left of the first drawn character. + * @param[in] matrix: deformation matrix, may be null (means identity) + * @param[in] alpha the opacity level to apply to the character. + * @param[in] blend the blend mode to use + * @param[in] letterSpacing the extra letter spacing to use + * @param[in] gradientData the gradient to apply + * @param[in] gradientMatrix the gradient deformation, may be null (means identity) + * + * @return the drawing status. + */ +DRAWING_Status VG_DRAWING_drawStringGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix); + +/* + * @brief Draws a string along a circle, with the color of the Graphics Context. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] text the array of characters to draw. + * @param[in] faceHandle the font reference handle. + * @param[in] size the height of the font in pixels. + * @param[in] x the horizontal coordinate of the top/left of the first drawn character. + * @param[in] y the vertical coordinate of the top/left of the first drawn character. + * @param[in] matrix: deformation matrix, may be null (means identity) + * @param[in] alpha the opacity level to apply to the character. + * @param[in] blend the blend mode to use + * @param[in] letterSpacing the extra letter spacing to use + * @param[in] radius the radius of the circle + * @param[in] direction the direction of the text along the circle + * + * @return the drawing status. + */ +DRAWING_Status VG_DRAWING_drawStringOnCircle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction); + +/* + * @brief Draws a string along a circle, with a linear gradient. + * + * @param[in] gc the MicroUI GraphicsContext target. + * @param[in] text the array of characters to draw. + * @param[in] faceHandle the font reference handle. + * @param[in] size the height of the font in pixels. + * @param[in] x the horizontal coordinate of the top/left of the first drawn character. + * @param[in] y the vertical coordinate of the top/left of the first drawn character. + * @param[in] matrix: deformation matrix, may be null (means identity) + * @param[in] alpha the opacity level to apply to the character. + * @param[in] blend the blend mode to use + * @param[in] letterSpacing the extra letter spacing to use + * @param[in] radius the radius of the circle + * @param[in] direction the direction of the text along the circle + * @param[in] gradientData the gradient to apply + * @param[in] gradientMatrix the gradient deformation, may be null (means identity) + * + * @return the drawing status. + */ +DRAWING_Status VG_DRAWING_drawStringOnCircleGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix); + +/* + * @brief Draws an image with transformation and opacity. Optionally apply an animation and / or a color filtering. + * + * @param[in] gc the graphics context to draw on + * @param[in] image the image to draw + * @param[in] matrix the transformation matrix to apply + * @param[in] alpha the global opacity rendering value + * @param[in] elapsedTime the elapsed time since the beginning of the animation, in milliseconds + * @param[in] colorMatrix the color matrix used to transform colors, may be null (means no color deformation) + * @param[out] errno the error code to return to MicroVG. + * + * @return the drawing status. + */ +DRAWING_Status VG_DRAWING_drawImage(MICROUI_GraphicsContext* gc, void* image, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno) ; + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif // VG_DRAWING_H diff --git a/bsp/projects/microej/vg/inc/vg_drawing_bvi.h b/bsp/projects/microej/vg/inc/vg_drawing_bvi.h new file mode 100644 index 0000000..e5a5b99 --- /dev/null +++ b/bsp/projects/microej/vg/inc/vg_drawing_bvi.h @@ -0,0 +1,99 @@ +/* + * Copyright 2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#if !defined VG_DRAWING_BVI_H +#define VG_DRAWING_BVI_H +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @file + * @brief Implementation of a set of vg_drawing.h drawing functions (library MicroVG). + * These are implementations over a BufferedVectorImage and the destination buffer format + * is the BufferedVectorImage format. When the drawing cannot be performed for any reason, + * the stub implementation is used insted. + * @author MicroEJ Developer Team + * @version 5.0.0 + * @see ui_drawing_bvi.h + */ + +#include "microvg_configuration.h" +#if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include + +#include "vg_drawing.h" +#include "ui_drawing.h" + +// -------------------------------------------------------------------------------- +// Defines +// -------------------------------------------------------------------------------- + +/* + * @brief Redirects all vg_drawing.h functions to the BufferedVectorImage functions + */ +#define VG_DRAWING_BVI_drawPath CONCAT(VG_DRAWING_drawPath_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define VG_DRAWING_BVI_drawGradient CONCAT(VG_DRAWING_drawGradient_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define VG_DRAWING_BVI_drawString CONCAT(VG_DRAWING_drawString_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define VG_DRAWING_BVI_drawStringGradient CONCAT(VG_DRAWING_drawStringGradient_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define VG_DRAWING_BVI_drawStringOnCircle CONCAT(VG_DRAWING_drawStringOnCircle_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define VG_DRAWING_BVI_drawStringOnCircleGradient CONCAT(VG_DRAWING_drawStringOnCircleGradient_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) +#define VG_DRAWING_BVI_drawImage CONCAT(VG_DRAWING_drawImage_, UI_DRAWING_IDENTIFIER_BVI_FORMAT) + +// -------------------------------------------------------------------------------- +// vg_drawing.h API +// (the function names differ according to the available number of destination formats) +// -------------------------------------------------------------------------------- + +/* + * @brief Implementation of drawPath over a BufferedVectorImage. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_BVI_drawPath(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color); + +/* + * @brief Implementation of drawGradient over a BufferedVectorImage. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_BVI_drawGradient(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradient, jfloat* gradientMatrix); + +/* + * @brief Implementation of drawString over a BufferedVectorImage. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_BVI_drawString(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing); + +/* + * @brief Implementation of drawStringGradient over a BufferedVectorImage. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_BVI_drawStringGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix); + +/* + * @brief Implementation of drawStringOnCircle over a BufferedVectorImage. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_BVI_drawStringOnCircle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction); + +/* + * @brief Implementation of drawStringOnCircleGradient over a BufferedVectorImage. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_BVI_drawStringOnCircleGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix); + +/* + * @brief Implementation of drawImage over a BufferedVectorImage. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_BVI_drawImage(MICROUI_GraphicsContext* gc, void* image, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno); + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#endif // #if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +#ifdef __cplusplus +} +#endif +#endif // VG_DRAWING_BVI_H diff --git a/bsp/projects/microej/vg/inc/vg_drawing_stub.h b/bsp/projects/microej/vg/inc/vg_drawing_stub.h new file mode 100644 index 0000000..655802d --- /dev/null +++ b/bsp/projects/microej/vg/inc/vg_drawing_stub.h @@ -0,0 +1,75 @@ +/* + * Copyright 2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#if !defined VG_DRAWING_STUB_H +#define VG_DRAWING_STUB_H +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @file + * @brief Implementation of all drawing functions of vg_drawing.h (library MicroVG). + * These are stubbed implementations, there is no error but the drawings are not + * performed. Useful to stub a drawing on a custom destination (custom GraphicsContext + * format not supported by the Graphics Engine). + * @author MicroEJ Developer Team + * @version 5.0.0 + * @see ui_drawing_stub.h + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include "vg_drawing.h" + +// -------------------------------------------------------------------------------- +// Public API +// -------------------------------------------------------------------------------- + +/* + * @brief Stubbed implementation of drawPath. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_STUB_drawPath(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color); + +/* + * @brief Stubbed implementation of drawGradient. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_STUB_drawGradient(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradient, jfloat* gradientMatrix); + +/* + * @brief Stubbed implementation of drawString. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_STUB_drawString(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing); + +/* + * @brief Stubbed implementation of drawStringGradient. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_STUB_drawStringGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix); + +/* + * @brief Stubbed implementation of drawStringOnCircle. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_STUB_drawStringOnCircle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction); + +/* + * @brief Stubbed implementation of drawStringOnCircleGradient. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_STUB_drawStringOnCircleGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix); + +/* + * @brief Stubbed implementation of drawImage. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_STUB_drawImage(MICROUI_GraphicsContext* gc, void* image, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno); + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif // VG_DRAWING_STUB_H diff --git a/bsp/projects/microej/vg/inc/vg_drawing_vglite.h b/bsp/projects/microej/vg/inc/vg_drawing_vglite.h new file mode 100644 index 0000000..0aaf419 --- /dev/null +++ b/bsp/projects/microej/vg/inc/vg_drawing_vglite.h @@ -0,0 +1,248 @@ +/* + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +#if !defined VG_DRAWING_VGLITE_H +#define VG_DRAWING_VGLITE_H +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @file + * @brief Implementation of a set of vg_drawing.h drawing functions (library MicroVG). + * These are implementations over VGLite and the destination buffer format is the + * format specified in the VEE port. When the drawing cannot be performed by the GPU, + * the software implementation is used insted. + * @author MicroEJ Developer Team + * @version 7.0.1 + * @see ui_drawing_vglite.h + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include "vg_drawing.h" +#include "microvg_path.h" + +#include "vg_lite.h" + +// -------------------------------------------------------------------------------- +// Defines +// -------------------------------------------------------------------------------- + +#if !defined VG_FEATURE_FONT || (VG_FEATURE_FONT != VG_FEATURE_FONT_FREETYPE_VECTOR) +#error "This drawer requires Freetype". +#endif + +#if !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +/* + * The fonction VG_DRAWING_VGLITE_xxx() are directly called by LLVG_PAINTER_impl.c + * This file overrides each function independently to use the VGLite GPU. + */ + +#define VG_DRAWING_VGLITE_drawPath VG_DRAWING_drawPath +#define VG_DRAWING_VGLITE_drawGradient VG_DRAWING_drawGradient +#define VG_DRAWING_VGLITE_drawString VG_DRAWING_drawString +#define VG_DRAWING_VGLITE_drawStringGradient VG_DRAWING_drawStringGradient +#define VG_DRAWING_VGLITE_drawStringOnCircle VG_DRAWING_drawStringOnCircle +#define VG_DRAWING_VGLITE_drawStringOnCircleGradient VG_DRAWING_drawStringOnCircleGradient +#define VG_DRAWING_VGLITE_drawImage VG_DRAWING_drawImage + +#else // !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +/* + * The functions VG_DRAWING_VGLITE_xxx() are indirectly called through some tables. + * The functions have got the identifier "0" as suffix. This file overrides each + * function independently to use the VGLite GPU. + */ + +#define VG_DRAWING_VGLITE_drawPath VG_DRAWING_drawPath_0 +#define VG_DRAWING_VGLITE_drawGradient VG_DRAWING_drawGradient_0 +#define VG_DRAWING_VGLITE_drawString VG_DRAWING_drawString_0 +#define VG_DRAWING_VGLITE_drawStringGradient VG_DRAWING_drawStringGradient_0 +#define VG_DRAWING_VGLITE_drawStringOnCircle VG_DRAWING_drawStringOnCircle_0 +#define VG_DRAWING_VGLITE_drawStringOnCircleGradient VG_DRAWING_drawStringOnCircleGradient_0 +#define VG_DRAWING_VGLITE_drawImage VG_DRAWING_drawImage_0 + +#endif // !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +// -------------------------------------------------------------------------------- +// Typedef +// -------------------------------------------------------------------------------- + +/* + * @brief Function to draw a character element: a glyph. A glyph is a vectorial path + * and the function parameters are similar to vg_lite_draw() and vg_lite_draw_gradient(). + * + * @param[in] color the color to apply if gradient is NULL + * @param[in] gradient the gradient to apply or NULL + * + * @see vg_lite_draw() + * @see vg_lite_draw_gradient() + * + * @return: the MicroVG error code + */ +typedef jint (* VG_DRAWING_VGLITE_draw_glyph_t) ( + vg_lite_path_t * path, + vg_lite_fill_t fill_rule, + vg_lite_matrix_t * matrix, + vg_lite_blend_t blend, + vg_lite_color_t color, + vg_lite_linear_gradient_t* grad); + +/* + * @brief Function to draw an image element. An image element is a vectorial path + * and the function parameters are similar to vg_lite_draw() and vg_lite_draw_gradient(). + * + * @param[in] color the color to apply if gradient is NULL + * @param[in] gradient the gradient to apply or NULL + * @param[in] is_new_gradient is true when the given gradient is different than the one + * of the previous call (with a non-null gradient). + * + * @see vg_lite_draw() + * + * @return: the MicroVG error code + */ +typedef jint (* VG_DRAWING_VGLITE_draw_image_element_t) ( + vg_lite_path_t * path, + vg_lite_fill_t fill_rule, + vg_lite_matrix_t * matrix, + vg_lite_blend_t blend, + vg_lite_color_t color, + vg_lite_linear_gradient_t* grad, + bool is_new_gradient); + +// -------------------------------------------------------------------------------- +// Public API +// -------------------------------------------------------------------------------- + +/* + * @brief Converts a MicroVG matrix in a VGLite matrix applying a translation. + * + * @param[out] vg_lite_matrix the VGLite matrix to set + * @param[in] x the X translation to apply + * @param[in] y the Y translation to apply + * @param[in] matrix the MicroVG transformation to apply + */ +void VG_DRAWING_VGLITE_prepare_matrix(vg_lite_matrix_t* vg_lite_matrix, jfloat x, jfloat y, jfloat* matrix) ; + +/* + * @brief Converts a MicroVG LinearGradient in a VGLite gradient according to + * the drawing parameters. After this call, the gradient is ready to be updated + * by calling vg_lite_update_grad(). + * + * This function is similar to MICROVG_VGLITE_HELPER_to_vg_lite_gradient() but + * the gradientMatrix may be NULL (identity matrix is used instead). + * + * @see MICROVG_VGLITE_HELPER_to_vg_lite_gradient() + */ +vg_lite_error_t VG_DRAWING_VGLITE_prepare_gradient(vg_lite_linear_gradient_t* vg_lite_gradient, jint* gradientData, jfloat* gradientMatrix, vg_lite_matrix_t* vg_lite_matrix, int alpha) ; + +/* + * @brief Clears the VGLite gradient data: vg_lite_init_grad() allocates a buffer + * in VGLite buffer, this function frees it. + * + * @param[in] gradient the VGLite gradient to clear + */ +void VG_DRAWING_VGLITE_clear_gradient(vg_lite_linear_gradient_t* gradient) ; + +/* + * @brief Converts a MicroVG path in a VGLite path. The same VGLite path is returned, by + * consequence only one path can be converted at any time. + * + * @param[in] path the MicroVG path to convert + * + * @return the VGLite path + */ +vg_lite_path_t* VG_DRAWING_VGLITE_to_vglite_path(MICROVG_PATH_HEADER_t* path); + +/* + * @brief Generic function to prepare the drawing of a string along a line or a circle, + * with a color or a linear gradient. The implementation does not draw, it calls the + * drawer function for each glyph. + * + * @param[in] drawer the function to draw a glyph. + * @param[in] text the array of characters to draw. + * @param[in] faceHandle the font reference handle. + * @param[in] size the height of the font in pixels. + * @param[in] vgGlobalMatrix: deformation matrix + * @param[in] blend the blend mode to use + * @param[in] color the color to apply if gradient is NULL + * @param[in] gradient the gradient to apply or NULL + * @param[in] letterSpacing the extra letter spacing to use + * @param[in] radius the radius of the circle (0 to draw along a line) + * @param[in] direction the direction of the text along the circle (0 to draw along a line) + * @param[out] rendered true if something has been drawn + * + * @return LLVG_SUCCESS if something has been drawn, an different value otherwise + */ +jint VG_DRAWING_VGLITE_draw_string(VG_DRAWING_VGLITE_draw_glyph_t drawer, jchar* text, jint faceHandle, jfloat size, vg_lite_matrix_t* vgGlobalMatrix, vg_lite_blend_t blend, int color, vg_lite_linear_gradient_t *gradient, jfloat letterSpacing, jfloat radius, jint direction, bool* rendered); + +/* + * @brief Generic function to prepare the drawing of an image. The implementation does + * not draw, it calls the drawer function for each image element. + * + * @param[in] drawer the function to draw an image element. + * @param[in] image the destination. + * @param[in] matrix the transformation matrix to apply + * @param[in] alpha the global opacity rendering value + * @param[in] elapsedTime the elapsed time since the beginning of the animation, in milliseconds + * @param[in] colorMatrix the color matrix used to transform colors, may be null (means no color deformation) + * @param[out] rendered true if something has been drawn + * + * @return LLVG_SUCCESS on a success, a different value otherwise + */ +jint VG_DRAWING_VGLITE_draw_image(VG_DRAWING_VGLITE_draw_image_element_t drawer, void* image, jfloat* drawing_matrix, jint alpha, jlong elapsed, const float color_matrix[], bool* rendered); + +// -------------------------------------------------------------------------------- +// vg_drawing.h API +// (the function names differ according to the available number of destination formats) +// -------------------------------------------------------------------------------- + +/* + * @brief Implementation of drawPath over VGLite. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_VGLITE_drawPath(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color); + +/* + * @brief Implementation of drawGradient over VGLite. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_VGLITE_drawGradient(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradient, jfloat* gradientMatrix); + +/* + * @brief Implementation of drawString over VGLite. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_VGLITE_drawString(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing); + +/* + * @brief Implementation of drawStringGradient over VGLite. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_VGLITE_drawStringGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix); + +/* + * @brief Implementation of drawStringOnCircle over VGLite. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_VGLITE_drawStringOnCircle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction); + +/* + * @brief Implementation of drawStringOnCircleGradient over VGLite. See vg_drawing.h + */ +DRAWING_Status VG_DRAWING_VGLITE_drawStringOnCircleGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix); + +/* + * @brief Implementation of drawImage over VGLite. See ui_drawing.h + */ +DRAWING_Status VG_DRAWING_VGLITE_drawImage(MICROUI_GraphicsContext* gc, void* image, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno); + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif // VG_DRAWING_VGLITE_H diff --git a/bsp/projects/microej/vg/src/LLVG_BVI_stub.c b/bsp/projects/microej/vg/src/LLVG_BVI_stub.c new file mode 100644 index 0000000..7bab108 --- /dev/null +++ b/bsp/projects/microej/vg/src/LLVG_BVI_stub.c @@ -0,0 +1,47 @@ +/* + * C + * + * Copyright 2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/** + * @file + * @brief MicroVG library low level API: stubbed implementation of LLVG_BVI_impl.h. + * + * @author MicroEJ Developer Team + * @version 5.0.0 + */ + +#include "microvg_configuration.h" + +#ifndef VG_FEATURE_BUFFERED_VECTOR_IMAGE + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include + +// ----------------------------------------------------------------------------- +// LLVG_BVI_impl.h functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +void LLVG_BVI_IMPL_map_context(MICROUI_Image* ui, void* vg) { + (void)ui; + (void)vg; + // nothing to do +} + +// See the header file for the function documentation +void LLVG_BVI_IMPL_clear(MICROUI_GraphicsContext* gc) { + (void)gc; + // nothing to do +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#endif // VG_FEATURE_BUFFERED_VECTOR_IMAGE diff --git a/bsp/projects/microej/vg/src/LLVG_FONT_PAINTER_freetype_vglite.c b/bsp/projects/microej/vg/src/LLVG_FONT_PAINTER_freetype_vglite.c new file mode 100644 index 0000000..838e27e --- /dev/null +++ b/bsp/projects/microej/vg/src/LLVG_FONT_PAINTER_freetype_vglite.c @@ -0,0 +1,316 @@ +/* + * C + * + * Copyright 2020-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/** +* @file +* @brief MicroEJ MicroVG library low level API: implementation over Freetype and VGLite. +* @author MicroEJ Developer Team +* @version 7.0.1 +*/ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include "microvg_configuration.h" + +#if defined VG_FEATURE_FONT && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_VECTOR) + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include "microvg_helper.h" +#include "microvg_font_freetype.h" +#include "microvg_vglite_helper.h" +#include "vg_lite.h" +#include "ftvector/ftvector.h" +#include "vg_drawing_vglite.h" + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +#define FT_COLOR_TO_INT(x) (*((int*) &(x))) +#define INT_TO_FT_COLOR(x) (*((FT_Color*) &(x))) + +#define DIRECTION_CLOCK_WISE 0 + +// ----------------------------------------------------------------------------- +// Extern Variables +// ----------------------------------------------------------------------------- + +extern FT_Library library; +extern FT_Renderer renderer; + +// ----------------------------------------------------------------------------- +// Global Variables +// ----------------------------------------------------------------------------- +static FT_Color *palette; + +// ----------------------------------------------------------------------------- +// Internal function definitions +// ----------------------------------------------------------------------------- + +/* + * @brief Computes the scale to apply to the font. + * + * @param[in] size: the font size + * @param[in] face: the face of the font + */ +static inline float __get_scale(jfloat size, FT_Face face); + +/* + * @brief Sets renderer parameters. + * + * @param[in] gc: the graphic context + * @param[in] matrix: the transformation matrix + * @param[in] alpha: the opacity of the string (from 0 to 255) + * @param[in] gradient: the gradient to apply + */ +static void __set_renderer(VG_DRAWING_VGLITE_draw_glyph_t drawer, vg_lite_matrix_t* matrix, int color, vg_lite_linear_gradient_t* gradient, vg_lite_blend_t blend); + +/* + * @brief Sets renderer color parameter. + * + * @param[in] color: the color to use to render the glyph + */ +static void __set_color(int color); + +/* + * @brief Updates the angle to use for the next glyph when drawn on an arc. + * When drawing on an arc, the glyph position is defined by its angle. We thus + * convert the advance (distance to the next glyph) to an angle. + */ +static float __get_angle(float advance, float radius); + +/** + * @brief load and render the selected glyph. If the glyph is a multilayer glyph, + * this function will retrieve the different layers glyphs with theirs colors and + * update the renderer to draw the glyph with the correct color. + * + * @param[in] face: the face of the font. + * @param[in] glyph: the glyph index. + * @param[in] glyph: the original color of the string index. + * @param[in,out] matrix: the transformation matrix. + * + * @return FT_ERR( Ok ) on a success, a different value otherwise. + */ +static FT_Error __render_glyph(FT_Face face, FT_UInt glyph_index, FT_Color color); + +// ----------------------------------------------------------------------------- +// Internal functions +// ----------------------------------------------------------------------------- + +static inline float __get_scale(jfloat size, FT_Face face){ + return size / face->units_per_EM; +} + +static void __set_renderer(VG_DRAWING_VGLITE_draw_glyph_t drawer, vg_lite_matrix_t* matrix, int color, vg_lite_linear_gradient_t* gradient, vg_lite_blend_t blend){ + FT_Parameter vglite_params[5]; + + vglite_params[0].tag = FT_PARAM_TAG_VGLITE_DESTINATION; + // cppcheck-suppress [misra-c2012-11.1] pointer conversion to store the drawer + vglite_params[0].data = (void *) drawer; + + vglite_params[1].tag = FT_PARAM_TAG_VGLITE_MATRIX; + vglite_params[1].data = matrix; + + vglite_params[2].tag = FT_PARAM_TAG_VGLITE_BLEND; + vglite_params[2].data = (void *) blend; + + vglite_params[3].tag = FT_PARAM_TAG_VGLITE_COLOR; + // cppcheck-suppress [misra-c2012-11.6] pointer conversion to store the color + vglite_params[3].data = (void *) color; + + vglite_params[4].tag = FT_PARAM_TAG_VGLITE_GRADIENT; + vglite_params[4].data = (void *) gradient; + + FT_Set_Renderer(library, renderer, 5, &vglite_params[0]); +} + +static void __set_color(int color) { + + FT_Renderer renderer = FT_Get_Renderer(library, FT_GLYPH_FORMAT_OUTLINE); + FT_Renderer_SetModeFunc set_mode = renderer->clazz->set_mode; + + // cppcheck-suppress [misra-c2012-11.6] pointer conversion to pass color + set_mode(renderer, FT_PARAM_TAG_VGLITE_COLOR, (void *)color); +} + +static float __get_angle(float advance, float radius){ + return (advance/radius) * 180.0f / M_PI; +} + +static FT_Error __render_glyph(FT_Face face, FT_UInt glyph_index, FT_Color color) { + FT_LayerIterator iterator; + + FT_Bool have_layers; + FT_UInt layer_glyph_index; + FT_UInt layer_color_index; + + FT_Error error = FT_ERR( Ok ); + bool color_updated = false; + + iterator.p = NULL; + have_layers = FT_Get_Color_Glyph_Layer(face, glyph_index, + &layer_glyph_index, &layer_color_index, &iterator); + + do { + if (palette && have_layers) { + // Update renderer color with layer_color + if (layer_color_index == 0xFFFF){ + __set_color(FT_COLOR_TO_INT(color)); + } + else { + __set_color(FT_COLOR_TO_INT(palette[layer_color_index])); + color_updated = true; + } + } + else { + // Use main glyph_index as layer_glyph_index + layer_glyph_index = glyph_index; + } + + if(layer_glyph_index != glyph_index){ + error = FT_Load_Glyph(face, layer_glyph_index, FT_LOAD_NO_SCALE); + } + + if (FT_ERR( Ok ) == error) { + // convert to an anti-aliased bitmap + error = FT_Render_Glyph(face->glyph, FT_RENDER_MODE_NORMAL); + } + else { + MEJ_LOG_ERROR_MICROVG("Error while loading glyphid %d: 0x%x, refer to fterrdef.h\n",layer_glyph_index, error); + } + } + while ((layer_glyph_index != glyph_index) && (FT_ERR( Ok ) == error) && (FT_ERR( Ok ) != FT_Get_Color_Glyph_Layer(face, glyph_index, + &layer_glyph_index, &layer_color_index, &iterator))); + + if ((FT_ERR( Ok ) == error) && color_updated) { + // Revert renderer color to original color in case it has been modified. + __set_color(FT_COLOR_TO_INT(color)); + } + + return error; +} + +// ----------------------------------------------------------------------------- +// vg_drawing_vglite.h painter functions +// ----------------------------------------------------------------------------- + +jint VG_DRAWING_VGLITE_draw_string(VG_DRAWING_VGLITE_draw_glyph_t drawer, jchar* text, jint faceHandle, jfloat size, vg_lite_matrix_t* vgGlobalMatrix, vg_lite_blend_t blend, int color, vg_lite_linear_gradient_t *gradient, jfloat letterSpacing, jfloat radius, jint direction, bool* rendered){ + FT_Face face = (FT_Face) faceHandle; + jint result = LLVG_SUCCESS; + *rendered = false; + + // Select palette + if (0 != FT_Palette_Select(face, 0, &palette)){ + palette = NULL; + } + + float scale = __get_scale(size, face); + float letterSpacingScaled = letterSpacing / scale; + float radiusScaled = radius / scale; + + // baselineposition + short baselineposition = face->ascender; + + jfloat* vgLocalMatrix = MAP_VGLITE_MATRIX(vgGlobalMatrix); + LLVG_MATRIX_IMPL_scale(vgLocalMatrix, scale, scale); + + vg_lite_matrix_t localGlyphMatrix; + jfloat* vglocalGlyphMatrix = MAP_VGLITE_MATRIX(&localGlyphMatrix); + + __set_renderer(drawer, &localGlyphMatrix, color, gradient, blend); + + // Layout variables + int glyph_index ; // current glyph index + + int length = (int)SNI_getArrayLength(text); + + if (0 < length) { + + int glyph_offset_y; + int glyph_advance_x; + int glyph_advance_y; + int glyph_offset_x; + int advance_x = 0; + int advance_Y = 0; + int previous_glyph_index = 0; // previous glyph index for kerning + + MICROVG_HELPER_layout_configure(faceHandle, text, length); + + while((LLVG_SUCCESS == result) && (MICROVG_HELPER_layout_load_glyph(&glyph_index, &glyph_advance_x, &glyph_advance_y, &glyph_offset_x, &glyph_offset_y))) { + // At that point the current glyph has been loaded by Freetype + + int charWidth = glyph_advance_x; + + if (0 == previous_glyph_index){ + // first glyph: remove the first blank line + if( 0 == face->glyph->metrics.width) { + advance_x -= charWidth; + } + else { + advance_x -= face->glyph->metrics.horiBearingX; + } + } + + LLVG_MATRIX_IMPL_copy(vglocalGlyphMatrix, vgLocalMatrix); + + if(0.f == radius) { + LLVG_MATRIX_IMPL_translate(vglocalGlyphMatrix, advance_x + glyph_offset_x, baselineposition + advance_Y + glyph_offset_y); + } else { + float sign = (DIRECTION_CLOCK_WISE != direction) ? -1.f : 1.f; + + // Space characters joining bboxes at baseline + float angleDegrees = 90 + __get_angle(advance_x + glyph_offset_x, radiusScaled) + __get_angle(charWidth / 2, radiusScaled); + + // Rotate to angle + LLVG_MATRIX_IMPL_rotate(vglocalGlyphMatrix, sign * angleDegrees); + + // Translate left to center of bbox + // Translate baseline over circle + LLVG_MATRIX_IMPL_translate(vglocalGlyphMatrix, -charWidth / 2, -sign * radiusScaled); + } + + // Draw the glyph + FT_Error error = __render_glyph(face, glyph_index, INT_TO_FT_COLOR(color)); + if (FT_ERR( Ok ) != error) { + MEJ_LOG_ERROR_MICROVG("Error while rendering glyphid %d: 0x%x, refer to fterrdef.h\n",glyph_index, error); + result = (FT_ERR( Out_Of_Memory ) == error) ? LLVG_OUT_OF_MEMORY : LLVG_DATA_INVALID; + continue; + } + + // at least one glyph has been drawn + *rendered = true; + + // Compute advance to next glyph + advance_x += charWidth; + advance_x += (int)letterSpacingScaled; + + advance_Y += glyph_advance_y; + + previous_glyph_index = glyph_index; + } + } + + return result; +} + +#endif // defined VG_FEATURE_FONT && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_VECTOR) + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_FONT_freetype.c b/bsp/projects/microej/vg/src/LLVG_FONT_freetype.c similarity index 86% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_FONT_freetype.c rename to bsp/projects/microej/vg/src/LLVG_FONT_freetype.c index 855b32f..e935f0d 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_FONT_freetype.c +++ b/bsp/projects/microej/vg/src/LLVG_FONT_freetype.c @@ -1,7 +1,7 @@ /* * C * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. + * Copyright 2020-2024 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -9,7 +9,7 @@ * @file * @brief MicroEJ MicroVG library low level API: implementation over FreeType * @author MicroEJ Developer Team - * @version 2.0.0 + * @version 5.0.0 */ #include "microvg_configuration.h" @@ -23,7 +23,7 @@ // ----------------------------------------------------------------------------- #include - +#include #include #include @@ -36,6 +36,7 @@ #include "microvg_font_freetype.h" #include "microvg_helper.h" +#include "microvg_trace.h" #include "mej_math.h" // ----------------------------------------------------------------------------- @@ -47,6 +48,13 @@ */ #define GET_SCALE(s,f) ((s) / (f)->units_per_EM) + +/* + * @brief Macro to add a FONT event and its type. + */ +#define LOG_MICROVG_FONT_START(fn) LOG_MICROVG_START(LOG_MICROVG_FONT_ID, CONCAT_DEFINES(LOG_MICROVG_FONT_, fn)) +#define LOG_MICROVG_FONT_END(fn) LOG_MICROVG_END(LOG_MICROVG_FONT_ID, CONCAT_DEFINES(LOG_MICROVG_FONT_, fn)) + // ----------------------------------------------------------------------------- // Types // ----------------------------------------------------------------------------- @@ -103,8 +111,14 @@ static FT_Error __load_memory_font(FT_Face* face, void* data, int length); */ static FT_Error __load_internal_font(FT_Face* face, jchar* font_name); +/* + * @brief Gets the description of the given native resource: a vector font. + * @see SNI_getDescriptionFunction + */ +static void __register_font_description(void* resource, char* buffer, uint32_t bufferLength); #if defined (VG_FEATURE_FONT_EXTERNAL) + /* * @brief Opens a font that has not been compiled with the application. * @@ -117,8 +131,6 @@ static FT_Error __load_internal_font(FT_Face* face, jchar* font_name); */ static FT_Error __load_external_font(FT_Face* face, jchar* font_name); - - /* * @brief Reads a chunk from an external resource. * @@ -187,6 +199,8 @@ void MICROVG_FONT_FREETYPE_initialize(void) { // See the header file for the function documentation jint LLVG_FONT_IMPL_load_font(jchar* font_name, jboolean complex_layout) { + LOG_MICROVG_FONT_START(load); + FT_Face face = 0; jint ret = LLVG_FONT_UNLOADED; @@ -210,7 +224,7 @@ jint LLVG_FONT_IMPL_load_font(jchar* font_name, jboolean complex_layout) { FT_Select_Charmap(face , ft_encoding_unicode); MEJ_LOG_INFO_MICROVG("Freetype font loaded: %s\n", (const char*)font_name); - SNI_registerResource((void*)face, (SNI_closeFunction)&_dispose_registered_font, JNULL); + SNI_registerResource((void*)face, (SNI_closeFunction)&_dispose_registered_font, &__register_font_description); #if defined (VG_FEATURE_FONT_COMPLEX_LAYOUT) if(JTRUE == complex_layout){ @@ -228,12 +242,15 @@ jint LLVG_FONT_IMPL_load_font(jchar* font_name, jboolean complex_layout) { } } + + LOG_MICROVG_FONT_END(load); return ret; } // See the header file for the function documentation jfloat LLVG_FONT_IMPL_string_width(jchar* text, jint faceHandle, jfloat size, jfloat letterSpacing) { + LOG_MICROVG_FONT_START(stringWidth); jfloat ret; if (LLVG_FONT_UNLOADED == faceHandle) { @@ -255,7 +272,8 @@ jfloat LLVG_FONT_IMPL_string_width(jchar* text, jint faceHandle, jfloat size, jf int previous_glyph_index = 0; // previous glyph index for kerning int advance_x; - int previous_advance_x; + int previous_advance_x = 0; + int previous_offset_x = 0; int advance_y; int offset_x; int offset_y; @@ -263,7 +281,7 @@ jfloat LLVG_FONT_IMPL_string_width(jchar* text, jint faceHandle, jfloat size, jf int length = (int)SNI_getArrayLength(text); MICROVG_HELPER_layout_configure(faceHandle, text, length); - while(0 != MICROVG_HELPER_layout_load_glyph(&glyph_index, &advance_x, &advance_y, &offset_x, &offset_y)) { + while(MICROVG_HELPER_layout_load_glyph(&glyph_index, &advance_x, &advance_y, &offset_x, &offset_y)) { // At that point the current glyph has been loaded by Freetype if (0 == previous_glyph_index){ // first glyph: remove the first blank line @@ -278,8 +296,10 @@ jfloat LLVG_FONT_IMPL_string_width(jchar* text, jint faceHandle, jfloat size, jf unscaled_width += advance_x; previous_glyph_index = glyph_index; nb_chars ++; - // Last call to MICROVG_HELPER_layout_load_glyph clear advance_x, we need to keep. + // Last call to MICROVG_HELPER_layout_load_glyph clear advance_x and offset_x. + // We need to keep them for last glyph measurement previous_advance_x = advance_x; + previous_offset_x = offset_x; } // last glyph: remove the last blank line @@ -287,6 +307,7 @@ jfloat LLVG_FONT_IMPL_string_width(jchar* text, jint faceHandle, jfloat size, jf unscaled_width -= previous_advance_x; unscaled_width += face->glyph->metrics.horiBearingX; // glyph's left blank line unscaled_width += face->glyph->metrics.width; // glyph's width + unscaled_width += previous_offset_x; // glyph's offset_x } else { if(0 != unscaled_width){ @@ -299,12 +320,14 @@ jfloat LLVG_FONT_IMPL_string_width(jchar* text, jint faceHandle, jfloat size, jf ret = scaled_width; } + LOG_MICROVG_FONT_END(stringWidth); return ret; } // See the header file for the function documentation jfloat LLVG_FONT_IMPL_string_height(jchar* text, jint faceHandle, jfloat size) { + LOG_MICROVG_FONT_START(stringHeight); jfloat ret; if (LLVG_FONT_UNLOADED == faceHandle) { @@ -333,7 +356,7 @@ jfloat LLVG_FONT_IMPL_string_height(jchar* text, jint faceHandle, jfloat size) { int length = (int)SNI_getArrayLength(text); MICROVG_HELPER_layout_configure(faceHandle, text, length); - while(0 != MICROVG_HELPER_layout_load_glyph(&glyph_index, &advance_x, &advance_y, &offset_x, &offset_y)) { + while(MICROVG_HELPER_layout_load_glyph(&glyph_index, &advance_x, &advance_y, &offset_x, &offset_y)) { // At that point the current glyph has been loaded by Freetype FT_Pos yBottom = face->glyph->metrics.horiBearingY - face->glyph->metrics.height; @@ -349,12 +372,14 @@ jfloat LLVG_FONT_IMPL_string_height(jchar* text, jint faceHandle, jfloat size) { ret = scaled_height; } + LOG_MICROVG_FONT_END(stringHeight); return ret; } // See the header file for the function documentation jfloat LLVG_FONT_IMPL_get_baseline_position(jint faceHandle, jfloat size) { + LOG_MICROVG_FONT_START(baseline); jfloat ret; if (LLVG_FONT_UNLOADED == faceHandle) { @@ -372,12 +397,14 @@ jfloat LLVG_FONT_IMPL_get_baseline_position(jint faceHandle, jfloat size) { ret = advance_y; } + LOG_MICROVG_FONT_END(baseline); return ret; } // See the header file for the function documentation jfloat LLVG_FONT_IMPL_get_height(jint faceHandle, jfloat size) { + LOG_MICROVG_FONT_START(height); jfloat ret; if (LLVG_FONT_UNLOADED == faceHandle) { @@ -389,6 +416,7 @@ jfloat LLVG_FONT_IMPL_get_height(jint faceHandle, jfloat size) { ret = face->height * scale; } + LOG_MICROVG_FONT_END(height); return ret; } @@ -413,6 +441,9 @@ bool LLVG_FONT_IMPL_has_complex_layouter(void){ static void _dispose_registered_font(void* faceHandle) { FT_Face face = (FT_Face) faceHandle; + // unregister the resource since the VEE does not need to call it anymore + SNI_unregisterResource((void*)face, (SNI_closeFunction)&_dispose_registered_font); + #if defined (VG_FEATURE_FONT_EXTERNAL) // FT_Done_Face() sets the stream to NULL: have to save it to close the // external resource @@ -519,6 +550,15 @@ static void __close_external_resource(FT_Stream stream) { } #endif // VG_FEATURE_FONT_EXTERNAL + +static void __register_font_description(void* resource, char* buffer, uint32_t bufferLength) { + (void)resource; + const char descEF[] = "Vector Font"; + if (bufferLength >= sizeof(descEF)) { + memcpy(buffer, descEF, sizeof(descEF)); + } +} + // cppcheck-suppress [misra-c2012-3.2] #endif // defined VG_FEATURE_FONT && \ // (defined VG_FEATURE_FONT_FREETYPE_VECTOR || defined VG_FEATURE_FONT_FREETYPE_BITMAP) && \ diff --git a/bsp/projects/microej/vg/src/LLVG_FONT_stub.c b/bsp/projects/microej/vg/src/LLVG_FONT_stub.c new file mode 100644 index 0000000..bff2bc9 --- /dev/null +++ b/bsp/projects/microej/vg/src/LLVG_FONT_stub.c @@ -0,0 +1,82 @@ +/* + * C + * + * Copyright 2020-2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/** + * @file + * @brief MicroEJ MicroVG library low level API: implementation over FreeType + * @author MicroEJ Developer Team + * @version 5.0.0 + */ + +#include "microvg_configuration.h" + +#ifndef VG_FEATURE_FONT + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include +#include + +// ----------------------------------------------------------------------------- +// LLVG_FONT_impl.h functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +jint LLVG_FONT_IMPL_load_font(jchar* font_name, jboolean complex_layout) { + (void)font_name; + (void)complex_layout; + return 0; +} + +// See the header file for the function documentation +jfloat LLVG_FONT_IMPL_string_width(jchar* text, jint faceHandle, jfloat size, jfloat letterSpacing) { + (void)text; + (void)faceHandle; + (void)size; + (void)letterSpacing; + return 0; +} + +// See the header file for the function documentation +jfloat LLVG_FONT_IMPL_string_height(jchar* text, jint faceHandle, jfloat size) { + (void)text; + (void)faceHandle; + (void)size; + return 0; +} + +// See the header file for the function documentation +jfloat LLVG_FONT_IMPL_get_baseline_position(jint faceHandle, jfloat size) { + (void)faceHandle; + (void)size; + return 0; +} + +// See the header file for the function documentation +jfloat LLVG_FONT_IMPL_get_height(jint faceHandle, jfloat size) { + (void)faceHandle; + (void)size; + return 0; +} + +// See the header file for the function documentation +void LLVG_FONT_IMPL_dispose(jint faceHandle) { + (void)faceHandle; +} + +// See the header file for the function documentation +bool LLVG_FONT_IMPL_has_complex_layouter(void){ + return false; +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#endif // VG_FEATURE_FONT diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_GRADIENT_impl.c b/bsp/projects/microej/vg/src/LLVG_GRADIENT_impl.c similarity index 95% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_GRADIENT_impl.c rename to bsp/projects/microej/vg/src/LLVG_GRADIENT_impl.c index f783a37..8a8e022 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_GRADIENT_impl.c +++ b/bsp/projects/microej/vg/src/LLVG_GRADIENT_impl.c @@ -1,7 +1,7 @@ /* * C * - * Copyright 2022 MicroEJ Corp. All rights reserved. + * Copyright 2022-2023 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -13,7 +13,7 @@ * positions. * * @author MicroEJ Developer Team - * @version 2.0.0 + * @version 5.0.0 */ #include "microvg_configuration.h" diff --git a/bsp/projects/microej/vg/src/LLVG_MATRIX_impl.c b/bsp/projects/microej/vg/src/LLVG_MATRIX_impl.c new file mode 100644 index 0000000..3706720 --- /dev/null +++ b/bsp/projects/microej/vg/src/LLVG_MATRIX_impl.c @@ -0,0 +1,195 @@ +/* + * C + * + * Copyright 2021-2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/** + * @file + * @brief MicroEJ MicroVG library low level API: basic implementation + * of matrix APIs. + * @author MicroEJ Developer Team + * @version 5.0.0 + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include +#include + +#include + +#include "microvg_helper.h" + +// ----------------------------------------------------------------------------- +// LLVG_MATRIX_impl.h functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_identity(jfloat* matrix) { + LLVG_MATRIX_IMPL_setTranslate(matrix, 0, 0); +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_copy(jfloat* dest, jfloat* src) { + (void)memcpy((void*)dest, (void*)src, sizeof(float) * LLVG_MATRIX_SIZE); +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_multiply(jfloat* dest, jfloat* a, jfloat* b) { + + dest[0] = (a[0] * b[0]) + (a[1] * b[3]) + (a[2] * b[6]); + dest[1] = (a[0] * b[1]) + (a[1] * b[4]) + (a[2] * b[7]); + dest[2] = (a[0] * b[2]) + (a[1] * b[5]) + (a[2] * b[8]); + + dest[3] = (a[3] * b[0]) + (a[4] * b[3]) + (a[5] * b[6]); + dest[4] = (a[3] * b[1]) + (a[4] * b[4]) + (a[5] * b[7]); + dest[5] = (a[3] * b[2]) + (a[4] * b[5]) + (a[5] * b[8]); + + dest[6] = (a[6] * b[0]) + (a[7] * b[3]) + (a[8] * b[6]); + dest[7] = (a[6] * b[1]) + (a[7] * b[4]) + (a[8] * b[7]); + dest[8] = (a[6] * b[2]) + (a[7] * b[5]) + (a[8] * b[8]); +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_setTranslate(jfloat* matrix, jfloat x, jfloat y) { + matrix[0] = 1.0f; + matrix[1] = 0.0f; + matrix[2] = x; + matrix[3] = 0.0f; + matrix[4] = 1.0f; + matrix[5] = y; + matrix[6] = 0.0f; + matrix[7] = 0.0f; + matrix[8] = 1.0f; +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_setScale(jfloat* matrix, jfloat sx, jfloat sy) { + LLVG_MATRIX_IMPL_identity(matrix); + LLVG_MATRIX_IMPL_scale(matrix, sx, sy); +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_setRotate(jfloat* matrix, jfloat degrees) { + LLVG_MATRIX_IMPL_identity(matrix); + LLVG_MATRIX_IMPL_rotate(matrix, degrees); +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_setConcat(jfloat* dest, jfloat* a, jfloat* b) { + if(dest == a) { + // cppcheck-suppress [misra-c2012-18.8] the size is a define + float temp[LLVG_MATRIX_SIZE]; + LLVG_MATRIX_IMPL_copy(temp, a); + LLVG_MATRIX_IMPL_multiply(dest, temp, b); + } + else if (dest == b) { + // cppcheck-suppress [misra-c2012-18.8] the size is a define + float temp[LLVG_MATRIX_SIZE]; + LLVG_MATRIX_IMPL_copy(temp, b); + LLVG_MATRIX_IMPL_multiply(dest, a, temp); + } + else { + LLVG_MATRIX_IMPL_multiply(dest, a, b); + } +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_translate(jfloat* matrix, jfloat x, jfloat y) { + matrix[2] = (matrix[0] * x) + (matrix[1] * y) + matrix[2]; + matrix[5] = (matrix[3] * x) + (matrix[4] * y) + matrix[5]; + matrix[8] = (matrix[6] * x) + (matrix[7] * y) + matrix[8]; +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_scale(jfloat* matrix, jfloat scaleX, jfloat scaleY) { + matrix[0] *= scaleX; + matrix[1] *= scaleY; + matrix[3] *= scaleX; + matrix[4] *= scaleY; + matrix[6] *= scaleX; + matrix[7] *= scaleY; +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_rotate(jfloat* matrix, jfloat angleDegrees) { + + float angleRadians = DEG_TO_RAD(angleDegrees); + + // computes cosine and sine values. + float cosAngle = cosf(angleRadians); + float sinAngle = sinf(angleRadians); + + float tmp; + + tmp = (cosAngle * matrix[0]) + (sinAngle * matrix[1]); + matrix[1] = (cosAngle * matrix[1]) - (sinAngle * matrix[0]); + matrix[0] = tmp; + + tmp = (cosAngle * matrix[3]) + (sinAngle * matrix[4]); + matrix[4] = (cosAngle * matrix[4]) - (sinAngle * matrix[3]); + matrix[3] = tmp; + + tmp = (cosAngle * matrix[6]) + (sinAngle * matrix[7]); + matrix[7] = (cosAngle * matrix[7]) - (sinAngle * matrix[6]); + matrix[6] = tmp; +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_concatenate(jfloat* matrix, jfloat* other) { + // cppcheck-suppress [misra-c2012-18.8] the size is a define + float temp[LLVG_MATRIX_SIZE]; + LLVG_MATRIX_IMPL_copy(temp, matrix); + LLVG_MATRIX_IMPL_multiply(matrix, temp, other); +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_postTranslate(jfloat* matrix, jfloat dx, jfloat dy) { + // cppcheck-suppress [misra-c2012-18.8] the size is a define + float a[LLVG_MATRIX_SIZE]; + // cppcheck-suppress [misra-c2012-18.8] the size is a define + float b[LLVG_MATRIX_SIZE]; + LLVG_MATRIX_IMPL_setTranslate(a, dx, dy); + LLVG_MATRIX_IMPL_copy(b, matrix); + LLVG_MATRIX_IMPL_multiply(matrix, a, b); +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_postScale(jfloat* matrix, jfloat sx, jfloat sy) { + // cppcheck-suppress [misra-c2012-18.8] the size is a define + float a[LLVG_MATRIX_SIZE]; + // cppcheck-suppress [misra-c2012-18.8] the size is a define + float b[LLVG_MATRIX_SIZE]; + LLVG_MATRIX_IMPL_identity(a); + LLVG_MATRIX_IMPL_scale(a, sx, sy); + LLVG_MATRIX_IMPL_copy(b, matrix); + LLVG_MATRIX_IMPL_multiply(matrix, a, b); +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_postRotate(jfloat* matrix, jfloat degrees) { + // cppcheck-suppress [misra-c2012-18.8] the size is a define + float a[LLVG_MATRIX_SIZE]; + // cppcheck-suppress [misra-c2012-18.8] the size is a define + float b[LLVG_MATRIX_SIZE]; + LLVG_MATRIX_IMPL_identity(a); + LLVG_MATRIX_IMPL_rotate(a, degrees); + LLVG_MATRIX_IMPL_copy(b, matrix); + LLVG_MATRIX_IMPL_multiply(matrix, a, b); +} + +// See the header file for the function documentation +void LLVG_MATRIX_IMPL_postConcat(jfloat* matrix, jfloat* other) { + // cppcheck-suppress [misra-c2012-18.8] the size is a define + float a[LLVG_MATRIX_SIZE]; + LLVG_MATRIX_IMPL_copy(a, matrix); + LLVG_MATRIX_IMPL_multiply(matrix, other, a); +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- diff --git a/bsp/projects/microej/vg/src/LLVG_PAINTER_impl.c b/bsp/projects/microej/vg/src/LLVG_PAINTER_impl.c new file mode 100644 index 0000000..b7222fc --- /dev/null +++ b/bsp/projects/microej/vg/src/LLVG_PAINTER_impl.c @@ -0,0 +1,192 @@ +/* + * C + * + * Copyright 2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/** + * @file + * @brief This file implements all MicroVG drawing native functions. + * @see LLVG_PAINTER_impl.h file comment + * @author MicroEJ Developer Team + * @version 5.0.0 + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +// implements LLVG_PAINTER_impl functions +#include + +// use graphical engine functions to synchronize drawings +#include + +#include +#include + +// calls vg_drawing functions +#include "vg_drawing.h" +#include "microvg_trace.h" + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +/* + * @brief Macro to add a DRAWING event and its type. + */ +#define LOG_MICROVG_DRAWING_START(fn) LOG_MICROVG_START(LOG_MICROVG_DRAWING_ID, CONCAT_DEFINES(LOG_MICROVG_DRAW_, fn)) +#define LOG_MICROVG_DRAWING_END(fn) LOG_MICROVG_END(LOG_MICROVG_DRAWING_ID, CONCAT_DEFINES(LOG_MICROVG_DRAW_, fn)) + +// ----------------------------------------------------------------------------- +// LLVG_PAINTER_impl.h functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +jint LLVG_PAINTER_IMPL_drawPath(MICROUI_GraphicsContext* gc, jbyte* pathData, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color) { + if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLVG_PAINTER_IMPL_drawPath)) { + LOG_MICROVG_DRAWING_START(path); + DRAWING_Status status = VG_DRAWING_drawPath(gc, pathData, x, y, matrix, fillRule, blend, color); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_MICROVG_DRAWING_END(path); + } + return LLVG_SUCCESS; +} + +// See the header file for the function documentation +jint LLVG_PAINTER_IMPL_drawGradient(MICROUI_GraphicsContext* gc, jbyte* pathData, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradientData, jfloat* gradientMatrix) { + if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLVG_PAINTER_IMPL_drawGradient)) { + LOG_MICROVG_DRAWING_START(pathGradient); + DRAWING_Status status = VG_DRAWING_drawGradient(gc, pathData, x, y, matrix, fillRule, alpha, blend, gradientData, gradientMatrix); + LLUI_DISPLAY_setDrawingStatus(status); + LOG_MICROVG_DRAWING_END(pathGradient); + } + return LLVG_SUCCESS; +} + +// See the header file for the function documentation +jint LLVG_PAINTER_IMPL_drawString(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing){ + + jint ret; + if (LLVG_FONT_UNLOADED == faceHandle) { + ret = (jint)LLVG_RESOURCE_CLOSED; + } + else { + if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&(LLVG_PAINTER_IMPL_drawString))){ + LOG_MICROVG_DRAWING_START(string); + LLUI_DISPLAY_setDrawingStatus(VG_DRAWING_drawString(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing)); + LOG_MICROVG_DRAWING_END(string); + } + ret = (jint)LLVG_SUCCESS; + } + return ret; +} + +// See the header file for the function documentation +jint LLVG_PAINTER_IMPL_drawStringGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix){ + + jint ret; + + if (LLVG_FONT_UNLOADED == faceHandle) { + ret = (jint)LLVG_RESOURCE_CLOSED; + } + else { + if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&(LLVG_PAINTER_IMPL_drawStringGradient))){ + LOG_MICROVG_DRAWING_START(stringGradient); + LLUI_DISPLAY_setDrawingStatus(VG_DRAWING_drawStringGradient(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, gradientData, gradientMatrix)); + LOG_MICROVG_DRAWING_END(stringGradient); + } + ret = (jint)LLVG_SUCCESS; + } + + return ret; +} + +// See the header file for the function documentation +jint LLVG_PAINTER_IMPL_drawStringOnCircle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction){ + + jint ret; + + if (LLVG_FONT_UNLOADED == faceHandle) { + ret = (jint)LLVG_RESOURCE_CLOSED; + } + else { + if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&(LLVG_PAINTER_IMPL_drawStringOnCircle))){ + LOG_MICROVG_DRAWING_START(stringOnCircle); + LLUI_DISPLAY_setDrawingStatus(VG_DRAWING_drawStringOnCircle(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, radius, direction)); + LOG_MICROVG_DRAWING_END(stringOnCircle); + } + ret = (jint)LLVG_SUCCESS; + } + + return ret; +} + +// See the header file for the function documentation +jint LLVG_PAINTER_IMPL_drawStringOnCircleGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix){ + + jint ret; + + if (LLVG_FONT_UNLOADED == faceHandle) { + ret = (jint)LLVG_RESOURCE_CLOSED; + } + else { + if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&(LLVG_PAINTER_IMPL_drawStringOnCircleGradient))){ + LOG_MICROVG_DRAWING_START(stringOnCircleGradient); + LLUI_DISPLAY_setDrawingStatus(VG_DRAWING_drawStringOnCircleGradient(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, radius, direction, gradientData, gradientMatrix)); + LOG_MICROVG_DRAWING_END(stringOnCircleGradient); + } + ret = (jint)LLVG_SUCCESS; + } + + return ret; +} + +// See the header file for the function documentation +jint LLVG_PAINTER_IMPL_drawImage(MICROUI_GraphicsContext* gc, void* image, jint x, jint y, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[]){ + + jint error = LLVG_SUCCESS; + + if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLVG_PAINTER_IMPL_drawImage)) { + DRAWING_Status status; + LOG_MICROVG_DRAWING_START(image); + if (alpha > (uint32_t)0){ + + // cppcheck-suppress [misra-c2012-18.8] LLVG_MATRIX_SIZE is a fixed size + jfloat local_matrix[LLVG_MATRIX_SIZE]; + jfloat* drawing_matrix; + + if((0 != x) || (0 != y)) { + // Create translate matrix for initial x,y translation from graphicscontext. + LLVG_MATRIX_IMPL_setTranslate(local_matrix, x, y); + LLVG_MATRIX_IMPL_concatenate(local_matrix, matrix); + drawing_matrix = local_matrix; + } + else { + // use original matrix + drawing_matrix = matrix; + } + + status = VG_DRAWING_drawImage(gc, image, drawing_matrix, alpha, elapsed, color_matrix, &error); + + /* FIXME LLVG_OUT_OF_MEMORY errors are not returned as they are reported with error flags. + * See M0092MEJAUI-2908. + */ + if (LLVG_OUT_OF_MEMORY == error) { + error = LLVG_SUCCESS; + } + } + else { + status = DRAWING_DONE; + } + LLUI_DISPLAY_setDrawingStatus(status); + LOG_MICROVG_DRAWING_END(image); + } + return error; +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- diff --git a/bsp/projects/microej/vg/src/LLVG_PATH_impl.c b/bsp/projects/microej/vg/src/LLVG_PATH_impl.c new file mode 100644 index 0000000..134d7d3 --- /dev/null +++ b/bsp/projects/microej/vg/src/LLVG_PATH_impl.c @@ -0,0 +1,255 @@ +/* + * C + * + * Copyright 2022-2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/** + * @file + * @brief MicroVG library low level API: implementation of path. + * + * This implementation uses a 32-bit "integer" value to store a path command and + * a 32-bit "float" value to store each command parameter. + * + * The encoding can be overridden, see "[optional]: weak functions" in "microvg_path.h" + * + * @author MicroEJ Developer Team + * @version 5.0.0 + */ + +#include "microvg_configuration.h" + +#ifdef VG_FEATURE_PATH + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include +#include + +#include + +#include "microvg_path.h" +#include "microvg_helper.h" +#include "bsp_util.h" + +// ----------------------------------------------------------------------------- +// Private functions +// ----------------------------------------------------------------------------- + +/* + * @brief Extends the path to be able to store the command and its parameters. + * + * @return the offset in path buffer where the command will be stored. If the path + * buffer is not large enough to contain the requested command, returns a negative + * number corresponding to size the buffer must be enlarged for this command. + */ +static int32_t _extend_path(MICROVG_PATH_HEADER_t* path, jint length, jint cmd, uint32_t nb_fields) { + uint32_t index = MICROVG_PATH_get_path_header_size() + path->data_size; + uint32_t extra_size = MICROVG_PATH_get_path_command_size(cmd, nb_fields); + int32_t ret; + + if (length >= (index + extra_size)) { + path->data_size += extra_size; + + // return next free space (return a positive value) + ret = index; + } + else { + // too small buffer, ret is the required extra size + // (return a negative value) + ret = -extra_size; + } + + return ret; +} + +static int32_t _close_path(MICROVG_PATH_HEADER_t* path, jint length, jfloat x1, jfloat y1, jfloat x2, jfloat y2) { + int32_t index = _extend_path(path, length, LLVG_PATH_CMD_CLOSE, 0); + int32_t ret = LLVG_SUCCESS; + if (index > 0) { + // finalizes the path by storing the path's bounds + path->bounds_xmin = x1; + path->bounds_xmax = x2; + path->bounds_ymin = y1; + path->bounds_ymax = y2; + (void)MICROVG_PATH_append_path_command0((jbyte*)path, (uint32_t)index, LLVG_PATH_CMD_CLOSE); + } + else { + // too small buffer, ret is the required extra size * -1 + ret = -index; + } + return ret; +} + +// ----------------------------------------------------------------------------- +// Specific path format functions [optional]: weak functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT void MICROVG_PATH_initialize(void) { + // nothing to do +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT uint32_t MICROVG_PATH_get_path_header_size(void) { + return sizeof(MICROVG_PATH_HEADER_t); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT uint32_t MICROVG_PATH_get_path_command_size(jint command, uint32_t nbParams) { + (void)command; + return (nbParams + (uint32_t)1 /* command */) * sizeof(uint32_t); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT uint32_t MICROVG_PATH_append_path_command0(jbyte* path, uint32_t offset, jint cmd) { + uint32_t* data = (uint32_t*)(path + offset); + *data = MICROVG_PATH_convert_path_command(cmd); + return sizeof(uint32_t); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT uint32_t MICROVG_PATH_append_path_command1(jbyte* path, uint32_t offset, jint cmd, jfloat x, jfloat y) { + uint32_t* data = (uint32_t*)(path + offset); + *data = MICROVG_PATH_convert_path_command(cmd); + ++data; + *data = JFLOAT_TO_UINT32_t(x); + ++data; + *data = JFLOAT_TO_UINT32_t(y); + return (uint32_t)3 * sizeof(uint32_t); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT uint32_t MICROVG_PATH_append_path_command2(jbyte* path, uint32_t offset, jint cmd, jfloat x1, jfloat y1, jfloat x2, jfloat y2) { + uint32_t* data = (uint32_t*)(path + offset); + *data = MICROVG_PATH_convert_path_command(cmd); + ++data; + *data = JFLOAT_TO_UINT32_t(x1); + ++data; + *data = JFLOAT_TO_UINT32_t(y1); + ++data; + *data = JFLOAT_TO_UINT32_t(x2); + ++data; + *data = JFLOAT_TO_UINT32_t(y2); + return (uint32_t)5 * sizeof(uint32_t); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT uint32_t MICROVG_PATH_append_path_command3(jbyte* path, uint32_t offset, jint cmd, jfloat x1, jfloat y1, jfloat x2, jfloat y2, + jfloat x3, jfloat y3) { + uint32_t* data = (uint32_t*)(path + offset); + *data = MICROVG_PATH_convert_path_command(cmd); + ++data; + *data = JFLOAT_TO_UINT32_t(x1); + ++data; + *data = JFLOAT_TO_UINT32_t(y1); + ++data; + *data = JFLOAT_TO_UINT32_t(x2); + ++data; + *data = JFLOAT_TO_UINT32_t(y2); + ++data; + *data = JFLOAT_TO_UINT32_t(x3); + ++data; + *data = JFLOAT_TO_UINT32_t(y3); + return (uint32_t)7 * sizeof(uint32_t); +} + +// ----------------------------------------------------------------------------- +// LLVG_PATH_impl.h functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +jint LLVG_PATH_IMPL_initializePath(jbyte* jpath, jint length) { + + MICROVG_PATH_HEADER_t* path = (MICROVG_PATH_HEADER_t*)jpath; + uint32_t header_size = MICROVG_PATH_get_path_header_size(); + jint ret = LLVG_SUCCESS; + + if (length >= header_size) { + path->data_size = 0; + path->format = MICROVG_PATH_get_path_encoder_format(); + } + else { + // the given byte array is too small + ret = header_size; + } + + return ret; +} + +// See the header file for the function documentation +jint LLVG_PATH_IMPL_appendPathCommand1(jbyte* jpath, jint length, jint cmd, jfloat x, jfloat y) { + + MICROVG_PATH_HEADER_t* path = (MICROVG_PATH_HEADER_t*)jpath; + jint ret = LLVG_SUCCESS; + + int32_t index = _extend_path(path, length, cmd, 2); + if (index > 0) { + (void)MICROVG_PATH_append_path_command1((jbyte*)path, (uint32_t)index, cmd, x, y); + } + else { + // too small buffer, ret is the required extra size * -1 + ret = -index; + } + + return ret; +} + +// See the header file for the function documentation +jint LLVG_PATH_IMPL_appendPathCommand2(jbyte* jpath, jint length, jint cmd, jfloat x1, jfloat y1, jfloat x2, + jfloat y2) { + + MICROVG_PATH_HEADER_t* path = (MICROVG_PATH_HEADER_t*)jpath; + jint ret = LLVG_SUCCESS; + + if (LLVG_PATH_CMD_CLOSE == cmd) { + // parameters are path's bounds + ret = _close_path(path, length, x1, y1, x2, y2); + } + else { + int32_t index = _extend_path(path, length, cmd, 4); + if (index > 0) { + (void)MICROVG_PATH_append_path_command2((jbyte*)path, (uint32_t)index, cmd, x1, y1, x2, y2); + } + else { + // too small buffer, ret is the required extra size * -1 + ret = -index; + } + } + + return ret; +} + +// See the header file for the function documentation +jint LLVG_PATH_IMPL_appendPathCommand3(jbyte* jpath, jint length, jint cmd, jfloat x1, jfloat y1, jfloat x2, + jfloat y2, jfloat x3, jfloat y3) { + + MICROVG_PATH_HEADER_t* path = (MICROVG_PATH_HEADER_t*)jpath; + jint ret = LLVG_SUCCESS; + + int32_t index = _extend_path(path, length, cmd, 6); + if (index > 0) { + (void)MICROVG_PATH_append_path_command3((jbyte*)path, (uint32_t)index, cmd, x1, y1, x2, y2, x3, y3); + } + else { + // too small buffer, ret is the required extra size * -1 + ret = -index; + } + + return ret; +} + +// See the header file for the function documentation +void LLVG_PATH_IMPL_reopenPath(jbyte* jpath) { + MICROVG_PATH_HEADER_t* path = (MICROVG_PATH_HEADER_t*)jpath; + path->data_size -= MICROVG_PATH_get_path_command_size(LLVG_PATH_CMD_CLOSE, 0); +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#endif // VG_FEATURE_PATH diff --git a/bsp/projects/microej/vg/src/LLVG_PATH_stub.c b/bsp/projects/microej/vg/src/LLVG_PATH_stub.c new file mode 100644 index 0000000..469036b --- /dev/null +++ b/bsp/projects/microej/vg/src/LLVG_PATH_stub.c @@ -0,0 +1,86 @@ +/* + * C + * + * Copyright 2022-2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/** + * @file + * @brief MicroVG library low level API: stubbed implementation of LLVG_PATH_impl.h + * and LLVG_PATH_PAINTER_impl.h. + * + * @author MicroEJ Developer Team + * @version 5.0.0 + */ + +#include "microvg_configuration.h" + +#ifndef VG_FEATURE_PATH + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include + +// ----------------------------------------------------------------------------- +// LLVG_PATH_impl.h functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +jint LLVG_PATH_IMPL_initializePath(jbyte* jpath, jint length) { + (void)jpath; + (void)length; + return LLVG_SUCCESS; +} + +// See the header file for the function documentation +jint LLVG_PATH_IMPL_appendPathCommand1(jbyte* jpath, jint length, jint cmd, jfloat x, jfloat y) { + (void)jpath; + (void)length; + (void)cmd; + (void)x; + (void)y; + return LLVG_SUCCESS; +} + +// See the header file for the function documentation +jint LLVG_PATH_IMPL_appendPathCommand2(jbyte* jpath, jint length, jint cmd, jfloat x1, jfloat y1, jfloat x2, + jfloat y2) { + (void)jpath; + (void)length; + (void)cmd; + (void)x1; + (void)y1; + (void)x2; + (void)y2; + return LLVG_SUCCESS; +} + +// See the header file for the function documentation +jint LLVG_PATH_IMPL_appendPathCommand3(jbyte* jpath, jint length, jint cmd, jfloat x1, jfloat y1, jfloat x2, + jfloat y2, jfloat x3, jfloat y3) { + (void)jpath; + (void)length; + (void)cmd; + (void)x1; + (void)y1; + (void)x2; + (void)y2; + (void)x3; + (void)y3; + return LLVG_SUCCESS; +} + +// See the header file for the function documentation +void LLVG_PATH_IMPL_reopenPath(jbyte* jpath) { + // nothing to do + (void)jpath; +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#endif // VG_FEATURE_PATH diff --git a/bsp/projects/microej/vg/src/LLVG_RAW_impl.c b/bsp/projects/microej/vg/src/LLVG_RAW_impl.c new file mode 100644 index 0000000..0b5449e --- /dev/null +++ b/bsp/projects/microej/vg/src/LLVG_RAW_impl.c @@ -0,0 +1,2745 @@ +/* + * C + * + * Copyright 2022-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/** + * @file + * @brief MicroEJ MicroVG library low level API: image management.This file draws an + * image and can fill a BufferedVectorImage. + * @author MicroEJ Developer Team + * @version 7.0.1 + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "bsp_util.h" +#include "color.h" +#include "vg_lite.h" +#include "vg_lite_kernel.h" +#include "microvg_configuration.h" +#include "microvg_path.h" +#include "microvg_vglite_helper.h" +#include "microvg_helper.h" +#include "microvg_trace.h" +#include "mej_math.h" +#include "vg_drawing_vglite.h" +#include "ui_drawing_bvi.h" +#include "bvi_vglite.h" + +#include "fsl_debug_console.h" + +// ----------------------------------------------------------------------------- +// Macros and Defines +// ----------------------------------------------------------------------------- + +/* + * @brief Enables loading of vector image files from an external resource system. + * + * If this feature is enabled, when an image file is not available in the application classpath, the implementation tries to load it from an external resource system. + * If this feature is disabled, only the resources compiled with the application are used. + * + * This feature will be enabled if the Platform embeds the module "External Resource" and the BSP implements the functions declared in "LLEXT_RES_impl.h". + */ +#ifndef VG_FEATURE_RAW_EXTERNAL +#define VG_FEATURE_RAW_EXTERNAL __has_include("LLEXT_RES_impl.h") +#if VG_FEATURE_RAW_EXTERNAL +#include "LLEXT_RES_impl.h" +#endif +#endif + +/* + * @brief RAW format + */ +#define LLVG_RAW_VERSION (1) + +/* + * @brief Allocator management + */ +#define MALLOC(s) (LLUI_DISPLAY_IMPL_imageHeapAllocate(VG_LITE_ALIGN((s), 4))) +#define FREE(s) (LLUI_DISPLAY_IMPL_imageHeapFree(s)) +//#define DEBUG_ALLOCATOR + +#define TIMERATIO_RANGE 65535 +#define TIMERATIO_OFFSET ((TIMERATIO_RANGE / 2) + 1) + +/* + * @brief Gamma value typically lies between 2.2 and 2.5 for CRT monitors, Android chose 2.2. + */ +#define GAMMA_VALUE 2.2f + +#define COLOR_MATRIX_WIDTH (5) +#define COLOR_MATRIX_HEIGHT (4) +#define COLOR_MATRIX_SIZE ((COLOR_MATRIX_WIDTH) * (COLOR_MATRIX_HEIGHT)) +#define RED_OFFSET (0) +#define GREEN_OFFSET (1) +#define BLUE_OFFSET (2) +#define ALPHA_OFFSET (3) +#define CONSTANT_OFFSET (4) +#define RED_LINE (COLOR_MATRIX_WIDTH * RED_OFFSET) +#define GREEN_LINE (COLOR_MATRIX_WIDTH * GREEN_OFFSET) +#define BLUE_LINE (COLOR_MATRIX_WIDTH * BLUE_OFFSET) +#define ALPHA_LINE (COLOR_MATRIX_WIDTH * ALPHA_OFFSET) + +/* + * @brief Copy the gradient content but not the image that renders the gradient + * + * /!\ the VGLite gradient is constitued of the gradient header (colors and positions) and a VGLite image. + * A VGLite image is a header + a pixel buffer. This image is made at runtime by VGLite library according + * to the gradient data. The RAW format only embbeds the gradient header, not the "image" part to win some + * footprint. By consequence the gradient data to copy from ROM to RAM is: + * sizeof(gradient) == sizeof(vg_lite_linear_gradient_t) - sizeof(vg_lite_buffer_t) + */ +#define GRADIENT_COPY_SIZE (sizeof(vg_lite_linear_gradient_t) - sizeof(vg_lite_buffer_t)) +#define GRADIENT_CMP_SIZE (GRADIENT_COPY_SIZE - sizeof(vg_lite_matrix_t)) + +/* + * @brief Macro to add an IMAGE event and its type. + */ +#define LOG_MICROVG_IMAGE_START(fn) LOG_MICROVG_START(LOG_MICROVG_IMAGE_ID, CONCAT_DEFINES(LOG_MICROVG_IMAGE_, fn)) +#define LOG_MICROVG_IMAGE_END(fn) LOG_MICROVG_END(LOG_MICROVG_IMAGE_ID, CONCAT_DEFINES(LOG_MICROVG_IMAGE_, fn)) + + +// ----------------------------------------------------------------------------- +// Java library constants (static final) +// ----------------------------------------------------------------------------- + +#define RAW_OFFSET_F32_WIDTH (0) +#define RAW_OFFSET_F32_HEIGHT (1) +#define RAW_OFFSET_U32_DURATION (2) +#define RAW_OFFSET_U32_FLAGS (3) + +#define RAW_FLAG_OVERLAP_PATH (0x01) +#define RAW_FLAG_FREE_MEMORY_ON_CLOSE (0x02) + +// ----------------------------------------------------------------------------- +// Typedef +// ----------------------------------------------------------------------------- + +/* + * @brief RAW and BVI + */ +typedef struct vector_image vector_image_t; +typedef struct vector_buffered_image vector_buffered_image_t; + +/* + * @brief Image blocks + */ +typedef enum vg_block_kind vg_block_kind_t; +typedef struct vg_flags vg_flags_t; +typedef struct vg_block vg_block_t; +typedef struct vg_path_desc vg_path_desc_t; +typedef struct vg_block_path vg_block_path_t; +typedef struct vg_block_group_transform vg_block_group_transform_t; +typedef struct vg_block_group_animation vg_block_group_animation_t; +typedef struct vg_block_group_end vg_block_group_end_t; +typedef struct vg_block_color vg_block_color_t; +typedef struct vg_block_gradient vg_block_gradient_t; +typedef struct vg_block_bvi_color vg_block_bvi_color_t; +typedef struct vg_block_bvi_gradient vg_block_bvi_gradient_t; +typedef struct vg_block_bvi_image vg_block_bvi_image_t; +typedef struct vg_block_animate_color vg_block_animate_color_t; +typedef struct vg_block_animate_gradient vg_block_animate_gradient_t; + +/* + * @brief Image animations + */ +typedef struct vg_path_interpolator vg_path_interpolator_t; +typedef struct vg_animation_header vg_animation_header_t; +typedef struct vg_animation_translate vg_animation_translate_t; +typedef struct vg_animation_translate_xy vg_animation_translate_xy_t; +typedef struct vg_animation_rotate vg_animation_rotate_t; +typedef struct vg_animation_scale vg_animation_scale_t; +typedef struct vg_animation_color vg_animation_color_t; +typedef struct vg_animation_alpha vg_animation_alpha_t; +typedef struct vg_animation_path_data vg_animation_path_data_t; + +/* + * @brief Image drawing data + */ +typedef struct vg_transformation vg_transformation_t; +typedef struct vg_drawing vg_drawing_t; + +/* + * @brief Internal MicroJVM element to retrieve a resource in the microejapp.o. + */ +typedef struct { + void* data; + uint32_t size; +} SNIX_resource; + +/* + * @brief Function to update a matrix according to an animation + * + * @param[in/out]: inout: the data to update + * @param[in]: elapsed_time: the time elapsed within this animation. + * @param[in]: last: true when the final frame is reached + * + * @return: nothing + */ +typedef void (* VG_RAW_apply_animation_t) ( + vg_animation_header_t* animation, + void* inout, + jlong elapsed_time, + size_t memory_offset, + bool last +); + +// ----------------------------------------------------------------------------- +// Enum +// ----------------------------------------------------------------------------- + +/* + * @brief Types of image's blocks. + */ +enum vg_block_kind { + + // respect the order (hardcoded in VectorImage converter) + + // RAW & BVI + VG_BLOCK_LAST, + + // RAW only + VG_BLOCK_PATH_COLOR, + VG_BLOCK_RAW_GRADIENT, + VG_BLOCK_GROUP_TRANSFORM, + VG_BLOCK_GROUP_ANIMATE, + VG_BLOCK_GROUP_END, + VG_BLOCK_PATH_COLOR_ANIMATE, + VG_BLOCK_PATH_GRADIENT_ANIMATE, + +#if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + // BVI only + VG_BLOCK_BVI_COLOR, + VG_BLOCK_BVI_GRADIENT, + VG_BLOCK_BVI_IMAGE, +#endif // #if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +}; + +// ----------------------------------------------------------------------------- +// Struct +// ----------------------------------------------------------------------------- + +/* + * @brief Flags of RAW image + * + * (u1) overlapping + * (u1) rom | ram (resp. 0 | 1) + * (u1) relative | absolute (resp. 0 | 1) + * (u5) padding + * (u24) duration + */ +struct vg_flags { + uint32_t duration : 24; + // cppcheck-suppress [unusedStructMember] padding is not used + uint32_t : 5; // padding + uint32_t absolute : 1; // 0: addresses are relative (blocks, paths, etc.); 1: absolute + uint32_t ram : 1; // 0: image in RAM; 1: image in ROM + uint32_t overlapping : 1; +}; + +/* + * @brief Defines an image block. A block is identified by its kind. + */ +struct vg_block { + + // block's kind (see vg_block_xxx) + vg_block_kind_t kind; + + // warning: aligned on 1 byte is known by "sub" struct + +} __attribute__((packed)); + +/* + * @brief Defines the description of a path. In a RAW image, the same path can + * be shared between several operation "draw path". + */ +struct vg_path_desc { + float bounding_box[4]; // left, top, right, bottom + uint32_t length; + vg_lite_format_t format; + uint8_t padding0; + uint8_t padding1; + uint8_t padding2; + + // + array of data of path + +}; + +/* + * @brief Defines a block "path"; useful for all operations that draw a path. + */ +struct vg_block_path { + + vg_block_t block; + + // common block's data for all VG drawings + vg_lite_fill_t fill_rule; + vg_lite_blend_t blend; // useless for static RAW images + uint8_t padding0; + + vg_path_desc_t* desc; + +}; + +/* + * @brief Defines a block "group with transformation" + */ +struct vg_block_group_transform { + + vg_block_t block; + + uint8_t padding0; + uint8_t padding1; + uint8_t padding2; + vg_lite_matrix_t matrix; + +}; + +/* + * @brief Defines a block "group with animation" + */ +struct vg_block_group_animation { + + vg_block_t block; + + uint8_t padding; + uint16_t block_size; + + uint8_t nb_translates; + uint8_t nb_translates_xy; + uint8_t nb_rotates; + uint8_t nb_scales; + + float scale_x; + float scale_y; + float translate_x; + float translate_y; + float pivot_x; + float pivot_y; + float rotation; + + // + array of vg_animation_translate_t + // + array of vg_animation_rotate_t + // + array of vg_animation_scale_t + +}; + +/* + * @brief Defines a block "end of current group" + */ +struct vg_block_group_end { + + vg_block_t block; + + uint8_t padding0; + uint8_t padding1; + uint8_t padding2; + +}; + +/* + * @brief Defines a block "path with a color". + */ +struct vg_block_color { + + vg_block_path_t path; + uint32_t color; + +}; + +/* + * @brief Defines a block "path with a gradient". + */ +struct vg_block_gradient { + + vg_block_path_t path; + + // /!\ the VGLite gradient is only constitued of the gradient header (colors and positions) + // see GRADIENT_COPY_SIZE + vg_lite_linear_gradient_t* gradient; + +}; + +/* + * @brief Defines a block "path with a color in a buffered image" + */ +struct vg_block_bvi_color { + vg_block_color_t header; + vg_lite_matrix_t path_deformation; + int32_t scissor[4]; + vg_block_t* next; +}; + +/* + * @brief Defines a block "path with a gradient in a buffered image" + */ +struct vg_block_bvi_gradient { + vg_block_gradient_t header; + vg_lite_matrix_t path_deformation; + int32_t scissor[4]; + vg_block_t* next; + bool shared_gradient; // if true, means the gradient is shared with another block (must not free it) +}; + +/* + * @brief Defines a block "raw image in a buffered image" + */ +struct vg_block_bvi_image { + + vg_block_t block; + + uint8_t flags; // 0 == color_matrix is null + jchar alpha; // prevent to use the mask "& 0xff" + + vector_image_t* image; + jfloat matrix[9]; + int32_t scissor[4]; + jfloat color_matrix[COLOR_MATRIX_SIZE]; + jint elapsed_msb; // prevent unalignment access + jint elapsed_lsb; + + vg_block_t* next; + +}; + +/* + * @brief Defines a block "animate color of a path". + */ +struct vg_block_animate_color { + + vg_block_color_t header; + + uint8_t nb_colors; + uint8_t nb_alphas; + uint8_t nb_path_datas; + uint8_t padding0; + + uint16_t block_size; + uint16_t padding1; + + // + array of vg_animation_color_t + // + array of vg_animation_alpha_t + // + array of vg_animation_path_data_t + +}; + +/* + * @brief Defines a block "animate gradient of a path". + */ +struct vg_block_animate_gradient { + + vg_block_gradient_t header; + + uint8_t nb_alphas; + uint8_t nb_path_datas; + uint16_t block_size; + + // + array of vg_animation_alpha_t + // + array of vg_animation_path_data_t + +}; + +/* + * @brief Defines a "path interpolator" + */ +struct vg_path_interpolator { + + uint32_t size; + + // + array of end_time_ratio (short) + // + optional padding + // + array of start_x (float) + // + array of start_y (float) + +}; + +/* + * @brief Defines the header of an animation. + */ +struct vg_animation_header { + + int32_t duration; + int32_t begin; + int32_t keep_duration; + vg_path_interpolator_t* offset_path_interpolator; + +}; + +/* + * @brief Defines an animation "Translate" + */ +struct vg_animation_translate { + + vg_animation_header_t header; + float start_x; + float start_y; + float translation_x; + float translation_y; + +}; + +/* + * @brief Defines an animation "Translate XY" + */ +struct vg_animation_translate_xy { + + vg_animation_header_t header; + vg_path_interpolator_t* offset_path_interpolator; + +}; + +/* + * @brief Defines an animation "Rotate" + */ +struct vg_animation_rotate { + + vg_animation_header_t header; + float start_angle; + float rotation_angle; + float start_rotation_center_x; + float start_rotation_center_y; + float rotation_translation_center_x; + float rotation_translation_center_y; + +}; + +/* + * @brief Defines an animation "Scale" + */ +struct vg_animation_scale { + + vg_animation_header_t header; + float scale_x_from; + float scale_x_to; + float scale_y_from; + float scale_y_to; + float pivot_x; + float pivot_y; + +}; + +/* + * @brief Defines an animation "Color" + */ +struct vg_animation_color { + + vg_animation_header_t header; + uint32_t start_color; + uint32_t end_color; + +}; + +/* + * @brief Defines an animation "Alpha" + */ +struct vg_animation_alpha { + + vg_animation_header_t header; + uint8_t start_alpha; + uint8_t end_alpha; + +}; + +/* + * @brief Defines an animation "Path data" + */ +struct vg_animation_path_data { + + vg_animation_header_t header; + vg_path_desc_t* from; + vg_path_desc_t* to; + +}; + +/* + * @brief Defines a RAW image + */ +struct vector_image { + + uint32_t signature_msb; + uint32_t signature_lsb; + + float width; + float height; + + vg_flags_t flags; + vg_block_t* first_block; + +}; + +/* + * @brief Defines a buffered image + */ +struct vector_buffered_image { + + /* + * @brief RAW image header + */ + vector_image_t header; + + /* + * @brief Pointer to vg_block_t* of last stored block. + */ + vg_block_t** latest_data; + + /* + * @brief Last block of image. + */ + vg_block_t last_block; + + /* + * @brief Pointer to last stored gradient in the bvi; to share same gradient + * between several consecutive drawings (very useful when drawing a string). + */ + vg_lite_linear_gradient_t* last_stored_gradient; + +}; + +/* + * @brief Element of a chained list: a transformation + */ +struct vg_transformation { + + struct vg_transformation* parent; + vg_lite_matrix_t matrix; + +}; + +/* + * @brief + */ +struct vg_drawing { + + /* + * @brief First image block to render. + */ + vg_block_t* first_block; + + /* + * @brief Offset to apply on each block data address. + */ + size_t memory_offset; + + /* + * @brief First transformation to apply when rendering an image. This + * transformation only holds the image transformation: it does not hold + * the final transformation: the image translation. + * + * This transformation is not stored in the heap to be sure to apply at + * least this transformation when drawing an image even if the heap is + * full. + */ + vg_transformation_t first_transformation; + + /* + * @brief At the end of the image drawing, tells if something has been + * drawn or not (empty or cleared image). + */ + bool drawing_running; + +}; + +// ----------------------------------------------------------------------------- +// Extern functions & fields +// ----------------------------------------------------------------------------- + +/* + * @brief Internal MicroJVM function to retrieve a resource in the microejapp.o. + * + * @param[in] path: the path of the resource to retrieve + * @param[out] resource: the resource metadata + */ +extern int32_t SNIX_get_resource(char* path, SNIX_resource* resource); + +/* + * @brief Function to retrieve the current scissor. + */ +extern uint32_t vg_lite_get_scissor(int32_t** scissor); + +// ----------------------------------------------------------------------------- +// Global Variables +// ----------------------------------------------------------------------------- + +const uint8_t signature[] = {(uint8_t)'M', (uint8_t)'E', (uint8_t)'J', (uint8_t)'_', (uint8_t)'M', (uint8_t)'V', (uint8_t)'G', (uint8_t)LLVG_RAW_VERSION}; + +static bool initialiazed = false; + +/* + * @brief Gradient used for all drawings with gradient (only one image allocation, + * does not alterate the original gradient's matrix and colors, etc.). + */ +static vg_lite_linear_gradient_t render_gradient; + +/* + * @brief Path used for all drawings. + */ +static vg_lite_path_t render_path; + +/* + * @brief Working data to draw an image (RAW or BVI) + */ +static vg_drawing_t drawing_data; + + +#if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +/* + * @brief Working data to draw a RAW image stored in a BVI. + */ +static vg_drawing_t raw_in_bvi_drawing_data; + +/* + * @brief BVI destination when rendering an image in a BVI + */ +static void* bvi_target; + +/* + * @brief Color matrix used to combine user matrix and RAW image matrix inside the BVI. + */ +static const float CONSTANT_ROW[5] = { 0.0f, 0.0f, 0.0f, 0.0f, 1.0f }; +static float combined_color_matrices[COLOR_MATRIX_SIZE]; + +#endif + +#ifdef DEBUG_ALLOCATOR +static uint32_t cumul = 0; +static uint32_t max = 0; +#endif + +// ----------------------------------------------------------------------------- +// Private functions +// ----------------------------------------------------------------------------- + +static inline void* get_addr(void* addr, size_t memory_offset){ + assert(NULL != addr); + // cppcheck-suppress [misra-c2012-11.5,misra-c2012-18.4] go to the expected address + return (void*)(((uint8_t*)addr) + memory_offset); +} + +static inline void* get_path_data_addr(vg_path_desc_t* path){ + return get_addr(path, sizeof(vg_path_desc_t)); +} + +static inline vg_path_desc_t* get_path_addr(vg_path_desc_t* path, size_t memory_offset){ + // cppcheck-suppress [misra-c2012-11.5] cast to vg_path_desc_t* is valid for sure + return (vg_path_desc_t*)get_addr(path, memory_offset); +} + +static inline vg_lite_linear_gradient_t* get_gradient_addr(vg_lite_linear_gradient_t* gradient, size_t memory_offset){ + return (vg_lite_linear_gradient_t*)get_addr(gradient, memory_offset); +} + +static inline vg_path_interpolator_t* get_path_interpolator_addr(vg_path_interpolator_t* interpolator, size_t memory_offset){ + // cppcheck-suppress [misra-c2012-11.5] cast to vg_path_interpolator_t* is valid for sure + return (vg_path_interpolator_t*)get_addr(interpolator, memory_offset); +} + +/* + * @brief Frees the given data from the heap or does nothing + * when targets RO memory. + * + * @param[in] data: pointer on the data to free. + */ +static void _free_data(void* data) { + if (NULL != data) { +#ifdef DEBUG_ALLOCATOR + // cppcheck-suppress [misra-c2012-11.5] data is aligned on 32-bit for sure + uint32_t* addr = (uint32_t*)data; + --addr; + uint32_t size = *addr; + cumul -= size; + PRINTF("free %u\t0x%x\t(%u/%u)\n", size, addr, cumul, max); + FREE((uint8_t*)addr); +#else + FREE(data); +#endif + } +} + +/* + * @brief Allocates the given size in the heap. + * + * @param[in] size: the data's size (in bytes). + * + * @return the pointer to the stored data. + */ +static inline uint8_t* _alloc_data(uint32_t size) { + +#ifdef DEBUG_ALLOCATOR + size += 4; + cumul += size; + max = (cumul > max) ? cumul : max; +#endif + + uint8_t* ret = MALLOC(size); + if (NULL == ret) { + MEJ_LOG_ERROR_MICROVG("OOM\n"); + } + +#ifdef DEBUG_ALLOCATOR + PRINTF("alloc %u\t0x%x\t(%u/%u)\n", size, ret, cumul, max); + *((uint32_t*)ret) = size; + ret += 4; +#endif + + return ret; +} + +/* + * @brief Stores the given data in the heap. + * + * @param[in] data: pointer on the data to store. + * @param[in] size: the data's size. + * + * @return the pointer to the stored data or NULL (OOM). + */ +static uint8_t* _store_data(void* data, size_t size) { + uint8_t* ret = _alloc_data(size); + if (NULL != ret){ + (void)memcpy((void*)ret, data, size); + } + return ret; +} + +static inline void _tag_image_in_ram(vector_image_t* image) { + image->flags.ram = (uint32_t)1; +} + +/* + * @brief Tells if the image addresses (blocks, paths, etc.) are relative + */ +static inline bool _is_image_address_relative(vector_image_t* image) { + return ((uint32_t)0) == image->flags.absolute; +} + +/* + * @brief Tells if the image is a buffered vector image. + * We use the flag "absolute" which is only true for the BVI. + */ +static inline bool _is_image_bvi(vector_image_t* image) { + return !_is_image_address_relative(image); +} + +/* + * @brief Stores the given transformation in the heap. + * + * @param[in] transformation: pointer on the transformation to store. + * + * @return the pointer to the stored transformation or NULL (OOM). + */ +static vg_transformation_t* _store_vg_transformation(vg_transformation_t * transformation) { + // cppcheck-suppress [misra-c2012-11.3] the stored data is a vg_transformation_t for sure + return (vg_transformation_t*)_store_data(transformation, sizeof(vg_transformation_t)); +} + +static void _free_vg_transformation(vg_transformation_t * transformation) { + _free_data(transformation); +} + +/** + * @brief Gets a filter color by applying a color transformation. + * + * @param[in] red, green, blue, alpha: the color to transform + * @param[in] color_matrix: the transformation to apply + * @param[in] start_index: the transformation index in the matrix + * + * @return the filtered color + */ +static uint32_t _filter_color_component(uint32_t red, uint32_t green, uint32_t blue, uint32_t alpha, const float color_matrix[], uint32_t start_index) { + float redFactor = color_matrix[start_index + (uint32_t)RED_OFFSET] * (float)red; + float greenFactor = color_matrix[start_index + (uint32_t)GREEN_OFFSET] * (float)green; + float blueFactor = color_matrix[start_index + (uint32_t)BLUE_OFFSET] * (float)blue; + float alphaFactor = color_matrix[start_index + (uint32_t)ALPHA_OFFSET] * (float)alpha; + float hardcodedColor = color_matrix[start_index + (uint32_t)CONSTANT_OFFSET]; + float factors = redFactor + greenFactor + blueFactor + alphaFactor + hardcodedColor; + int32_t ret = (int32_t) factors; + return (uint32_t)((ret < 0x0) ? 0x0 : ((ret > 0xff) ? 0xff : ret)); +} + +static uint32_t _filter_color(uint32_t color, const float color_matrix[]) { + + uint32_t red = COLOR_GET_CHANNEL(color, ARGB8888, RED); + uint32_t green = COLOR_GET_CHANNEL(color, ARGB8888, GREEN); + uint32_t blue = COLOR_GET_CHANNEL(color, ARGB8888, BLUE); + uint32_t alpha = COLOR_GET_CHANNEL(color, ARGB8888, ALPHA); + + uint32_t resultRed = _filter_color_component(red, green, blue, alpha, color_matrix, RED_LINE); + uint32_t resultGreen = _filter_color_component(red, green, blue, alpha, color_matrix, GREEN_LINE); + uint32_t resultBlue = _filter_color_component(red, green, blue, alpha, color_matrix, BLUE_LINE); + uint32_t resultAlpha = _filter_color_component(red, green, blue, alpha, color_matrix, ALPHA_LINE); + + return COLOR_SET_COLOR(resultAlpha, resultRed, resultGreen, resultBlue, ARGB8888); +} + +static void _filter_gradient(vg_lite_linear_gradient_t* gradient, const float color_matrix[]) { + uint32_t* colors = (uint32_t*)gradient->colors; + for(int i = 0; i < gradient->count; i++) { + colors[i] = _filter_color(colors[i], color_matrix); + } +} + +static uint8_t _filter_alpha(uint8_t alpha, const float color_matrix[]) { + uint32_t color = alpha; + color <<= 24; + color = _filter_color(color, color_matrix); + return (uint8_t)(color >> 24); +} + +static uint32_t _prepare_render_color(uint32_t color, uint32_t alpha, const float color_matrix[]) { + uint32_t ret = color; + if (NULL != color_matrix) { + assert((uint32_t)0xff == alpha); // filter mode does not use global alpha (see MicroVG spec) + ret = _filter_color(color, color_matrix); + } + else if (alpha != (uint32_t)0xff) { + ret = MICROVG_HELPER_apply_alpha(color, alpha); + } + else { + // nothing to change + } + return ret; +} + +static void _prepare_gradient_colors(vg_lite_linear_gradient_t* gradient, uint32_t alpha, const float color_matrix[]) { + + if (NULL != color_matrix) { + assert((uint32_t)0xff == alpha); // filter mode does not use global alpha + _filter_gradient(gradient, color_matrix); + } + else if (alpha != (uint32_t)0xff) { + uint32_t* colors = (uint32_t*)gradient->colors; + for(int i = 0; i < gradient->count; i++) { + colors[i] = MICROVG_HELPER_apply_alpha(colors[i], alpha); + } + } + else { + // nothing to change + } +} + +static float _get_path_interpolator_at_time(vg_path_interpolator_t* interpolator, float time, bool apply_x_transformation) { + + // retrieve arrays addresses + uint8_t* data_offset = (uint8_t*)interpolator; + // cppcheck-suppress [misra-c2012-18.4] points after the interpolator + data_offset += sizeof(vg_path_interpolator_t); + // cppcheck-suppress [misra-c2012-11.3] data_offset points on a 16-bit array for sure + int16_t* end_time_ratio = (int16_t*)data_offset; + uint32_t ratio_array_length = interpolator->size + (uint32_t)1; + ratio_array_length &= ~1; + // cppcheck-suppress [misra-c2012-18.4] points after the ratio array + data_offset += ratio_array_length * sizeof(int16_t); + // cppcheck-suppress [misra-c2012-11.3,invalidPointerCast] data_offset points on a float array for sure + float* start_x = (float*)data_offset; + // cppcheck-suppress [misra-c2012-18.4] points after the start X array + data_offset += interpolator->size * sizeof(float); + // cppcheck-suppress [misra-c2012-11.3,invalidPointerCast] data_offset points on a float array for sure + float* start_y = (float*)data_offset; + + // get the values to apply + float* values = apply_x_transformation ? start_x : start_y; + + // get a ratio between 0x0000 and 0xffff (TIMERATIO_RANGE) + int32_t time_ratio = (int32_t) (MEJ_MIN(MEJ_MAX(time, 0.f), 1.f) * (float)TIMERATIO_RANGE); + + int32_t origin = 0; + float ret = 0.f; + bool done = false; + + // Last cells of arrays store the ending positions of last segment + for (uint32_t i = 0; !done && (i < (interpolator->size - (uint32_t)1)); i++) { + + int32_t end = end_time_ratio[i] + TIMERATIO_OFFSET; + + if (time_ratio <= end) { + float segPosition = ((float)time_ratio - (float)origin) / ((float)end - (float)origin); + float segStartValue = values[i]; + float segEndValue = values[i + (uint32_t)1]; + ret = ((segStartValue * (1.f - segPosition)) + (segEndValue * segPosition)); + done = true; + } + origin = end; + } + + return ret; +} + +static float _get_transformation_ratio_at_time(vg_animation_header_t* animation, vg_path_interpolator_t* interpolator, jlong time) { + float time_ratio; + + if (0 == animation->duration) { + time_ratio = 1.f; + } else { + time_ratio = (float) time / animation->duration; + } + + return _get_path_interpolator_at_time(interpolator, time_ratio, true); +} + +static void _apply_group_animation_translate(vg_animation_header_t* animation, void* data, jlong atTime, size_t memory_offset, bool last) { + (void)last; + // cppcheck-suppress [misra-c2012-11.3] animations is a vg_animation_translate_t for sure + vg_animation_translate_t* animation_translate = (vg_animation_translate_t*)animation; + vg_path_interpolator_t* interpolator = get_path_interpolator_addr(animation->offset_path_interpolator, memory_offset); + // cppcheck-suppress [misra-c2012-11.5] data is a float array for sure + float* matrix = (float*)data; + float transformRatio = _get_transformation_ratio_at_time(animation, interpolator, atTime); + LLVG_MATRIX_IMPL_translate(matrix, animation_translate->start_x + (animation_translate->translation_x * transformRatio), + animation_translate->start_y + (animation_translate->translation_y * transformRatio)); +} + +static void _apply_group_animation_translate_xy(vg_animation_header_t* animation, void* data, jlong atTime, size_t memory_offset, bool last) { + (void)last; + // cppcheck-suppress [misra-c2012-11.3] animations is a vg_animation_translate_xy_t for sure + vg_animation_translate_xy_t* animation_translate = (vg_animation_translate_xy_t*)animation; + vg_path_interpolator_t* interpolator = get_path_interpolator_addr(animation->offset_path_interpolator, memory_offset); + // cppcheck-suppress [misra-c2012-11.5] data is a float array for sure + float* matrix = (float*)data; + vg_path_interpolator_t* translation = get_path_interpolator_addr(animation_translate->offset_path_interpolator, memory_offset); + float transformRatio = _get_transformation_ratio_at_time(animation, interpolator, atTime); + float translateX = _get_path_interpolator_at_time(translation, transformRatio, true); + float translateY = _get_path_interpolator_at_time(translation, transformRatio, false); + LLVG_MATRIX_IMPL_translate(matrix, translateX, translateY); +} + +static void _apply_group_animation_rotate(vg_animation_header_t* animation, void* data, jlong atTime, size_t memory_offset, bool last) { + (void)last; + // cppcheck-suppress [misra-c2012-11.3] animations is a vg_animation_rotate_t for sure + vg_animation_rotate_t* animation_rotate = (vg_animation_rotate_t*)animation; + vg_path_interpolator_t* interpolator = get_path_interpolator_addr(animation->offset_path_interpolator, memory_offset); + // cppcheck-suppress [misra-c2012-11.5] data is a float array for sure + float* matrix = (float*)data; + float transformRatio = _get_transformation_ratio_at_time(animation, interpolator, atTime); + LLVG_MATRIX_IMPL_translate(matrix, animation_rotate->start_rotation_center_x + (animation_rotate->rotation_translation_center_x * transformRatio), + animation_rotate->start_rotation_center_y + (animation_rotate->rotation_translation_center_y * transformRatio)); + LLVG_MATRIX_IMPL_rotate(matrix, animation_rotate->start_angle + (animation_rotate->rotation_angle * transformRatio)); + LLVG_MATRIX_IMPL_translate(matrix, -animation_rotate->start_rotation_center_x - (animation_rotate->rotation_translation_center_x * transformRatio), + -animation_rotate->start_rotation_center_y - (animation_rotate->rotation_translation_center_y * transformRatio)); +} + +static inline float _get_scale(float from, float to, float transformRatio) { + float ret; + if (from < to) { + ret = (float) (from * powf(to / from, transformRatio)); + } else { + ret = (float) (to * powf(from / to, 1.f - transformRatio)); + } + return ret; +} + +static void _apply_group_animation_scale(vg_animation_header_t* animation, void* data, jlong atTime, size_t memory_offset, bool last) { + (void)last; + // cppcheck-suppress [misra-c2012-11.3] animations is a vg_animation_scale_t for sure + vg_animation_scale_t* animation_scale = (vg_animation_scale_t*)animation; + vg_path_interpolator_t* interpolator = get_path_interpolator_addr(animation->offset_path_interpolator, memory_offset); + // cppcheck-suppress [misra-c2012-11.5] data is a float array for sure + float* matrix = (float*)data; + float transformRatio = _get_transformation_ratio_at_time(animation, interpolator, atTime); + float scaleX = _get_scale(animation_scale->scale_x_from, animation_scale->scale_x_to, transformRatio); + float scaleY = _get_scale(animation_scale->scale_y_from, animation_scale->scale_y_to, transformRatio); + LLVG_MATRIX_IMPL_translate(matrix, animation_scale->pivot_x, animation_scale->pivot_y); + LLVG_MATRIX_IMPL_scale(matrix, scaleX, scaleY); + LLVG_MATRIX_IMPL_translate(matrix, -animation_scale->pivot_x, -animation_scale->pivot_y); +} + +/* + * This function returns the calculated in-between value for a color given integers that represent the start and end + * values in the four bytes of the 32-bit int. Each channel is separately linearly interpolated and the resulting + * calculated values are recombined into the return value. + * + * @param fraction + * The fraction from the starting to the ending values + * @param start_color + * A 32-bit int value representing colors in the separate bytes of the parameter + * @param end_color + * A 32-bit int value representing colors in the separate bytes of the parameter + * @return A value that is calculated to be the linearly interpolated result, derived by separating the start and + * end values into separate color channels and interpolating each one separately, recombining the resulting + * values in the same way. + */ +static uint32_t _interpolate_color(float fraction, uint32_t start_color, uint32_t end_color) { + + float startA = ((float) (COLOR_GET_CHANNEL(start_color, ARGB8888, ALPHA))) / COLOR_ARGB8888_CHANNEL_MASK; + float startR = ((float) (COLOR_GET_CHANNEL(start_color, ARGB8888, RED))) / COLOR_ARGB8888_CHANNEL_MASK; + float startG = ((float) (COLOR_GET_CHANNEL(start_color, ARGB8888, GREEN))) / COLOR_ARGB8888_CHANNEL_MASK; + float startB = ((float) (COLOR_GET_CHANNEL(start_color, ARGB8888, BLUE))) / COLOR_ARGB8888_CHANNEL_MASK; + + float endA = ((float) (COLOR_GET_CHANNEL(end_color, ARGB8888, ALPHA))) / COLOR_ARGB8888_CHANNEL_MASK; + float endR = ((float) (COLOR_GET_CHANNEL(end_color, ARGB8888, RED))) / COLOR_ARGB8888_CHANNEL_MASK; + float endG = ((float) (COLOR_GET_CHANNEL(end_color, ARGB8888, GREEN))) / COLOR_ARGB8888_CHANNEL_MASK; + float endB = ((float) (COLOR_GET_CHANNEL(end_color, ARGB8888, BLUE))) / COLOR_ARGB8888_CHANNEL_MASK; + + // convert from sRGB to linear + startR = (float) powf(startR, GAMMA_VALUE); + startG = (float) powf(startG, GAMMA_VALUE); + startB = (float) powf(startB, GAMMA_VALUE); + + endR = (float) powf(endR, GAMMA_VALUE); + endG = (float) powf(endG, GAMMA_VALUE); + endB = (float) powf(endB, GAMMA_VALUE); + + // compute the interpolated color in linear space + float a = startA + (fraction * (endA - startA)); + float r = startR + (fraction * (endR - startR)); + float g = startG + (fraction * (endG - startG)); + float b = startB + (fraction * (endB - startB)); + + // convert back to sRGB in the [0..255] range + a = a * COLOR_ARGB8888_CHANNEL_MASK; + r = (float) powf(r, 1.0 / GAMMA_VALUE) * COLOR_ARGB8888_CHANNEL_MASK; + g = (float) powf(g, 1.0 / GAMMA_VALUE) * COLOR_ARGB8888_CHANNEL_MASK; + b = (float) powf(b, 1.0 / GAMMA_VALUE) * COLOR_ARGB8888_CHANNEL_MASK; + + return COLOR_SET_COLOR((uint32_t)roundf(a), (uint32_t)roundf(r), (uint32_t)roundf(g), (uint32_t)roundf(b), ARGB8888); +} + +static void _apply_path_animation_color(vg_animation_header_t* animation, void* data, jlong atTime, size_t memory_offset, bool last) { + // cppcheck-suppress [misra-c2012-11.3] animations is a vg_animation_color_t for sure + vg_animation_color_t* animation_color = (vg_animation_color_t*)animation; + + // cppcheck-suppress [misra-c2012-11.5] data is a 32-bit array for sure + uint32_t* color = (uint32_t*)data; + if (!last){ + vg_path_interpolator_t* interpolator = get_path_interpolator_addr(animation->offset_path_interpolator, memory_offset); + float transformRatio = _get_transformation_ratio_at_time(animation, interpolator, atTime); + *color = _interpolate_color(transformRatio, animation_color->start_color, animation_color->end_color); + } + else { + *color = animation_color->end_color; + } +} + +static void _apply_path_animation_alpha(vg_animation_header_t* animation, void* data, jlong atTime, size_t memory_offset, bool last) { + // cppcheck-suppress [misra-c2012-11.3] animations is a vg_animation_alpha_t for sure + vg_animation_alpha_t* animation_alpha = (vg_animation_alpha_t*)animation; + + // cppcheck-suppress [misra-c2012-11.5] data is a 8-bit array for sure + uint8_t* alpha = (uint8_t*)data; + if (!last){ + vg_path_interpolator_t* interpolator = get_path_interpolator_addr(animation->offset_path_interpolator, memory_offset); + float transformRatio = _get_transformation_ratio_at_time(animation, interpolator, atTime); + float end_alpha = ((uint8_t)0xff & animation_alpha->end_alpha); + float start_alpha = ((uint8_t)0xff & animation_alpha->start_alpha); + float result = (end_alpha * transformRatio) + (start_alpha * (1.0f - transformRatio)); + *alpha = (uint8_t)result; + } + else { + *alpha = animation_alpha->end_alpha; + } +} + +/* + * @brief Merges 2 paths with same commands. + * + * For each source path points a new point is calculated based on the source paths points + * coordinates and a ratio. + * If ratio = 0, resulting point will equal the first path point. + * If ratio = 1, resulting point will equal the second path point. + * + * @param[out] pathDest: the path array to update. + * @param[in] pathSrc1: the first path array to merge. + * @param[in] pathSrc2: the second path array to merge. + * @param[in] ratio: the merge ratio between paths points. + */ +static void _interpolate_paths(vg_lite_path_t* pathDest, vg_path_desc_t* pathSrc1, vg_path_desc_t* pathSrc2, float ratio) { + + float remaining = (1.f - ratio); + + // Compute bounds + float fSrc1 = pathSrc1->bounding_box[0]; + float fSrc2 = pathSrc2->bounding_box[0]; + float fDest = MEJ_MIN(fSrc1, fSrc2); + pathDest->bounding_box[0] = fDest; + + fSrc1 = pathSrc1->bounding_box[1]; + fSrc2 = pathSrc2->bounding_box[1]; + fDest = MEJ_MIN(fSrc1, fSrc2); + pathDest->bounding_box[1] = fDest; + + fSrc1 = pathSrc1->bounding_box[2]; + fSrc2 = pathSrc2->bounding_box[2]; + fDest = MEJ_MAX(fSrc1, fSrc2); + pathDest->bounding_box[2] = fDest; + + fSrc1 = pathSrc1->bounding_box[3]; + fSrc2 = pathSrc2->bounding_box[3]; + fDest = MEJ_MAX(fSrc1, fSrc2); + pathDest->bounding_box[3] = fDest; + + // Compute commands + uint32_t* dataDest = (uint32_t*)pathDest->path; + // cppcheck-suppress [misra-c2012-11.5] path is a 32-bit array for sure + uint32_t* dataSrc1 = (uint32_t*)get_path_data_addr(pathSrc1); + // cppcheck-suppress [misra-c2012-11.5] path is a 32-bit array for sure + uint32_t* dataSrc2 = (uint32_t*)get_path_data_addr(pathSrc2); + + // cppcheck-suppress [misra-c2012-11.4] path is a 32-bit array for sure + uint32_t* dataDestEnd = (uint32_t*)(((uint32_t)pathDest->path) + pathSrc1->length); + + while (dataDest < dataDestEnd) { + + uint32_t cmdSrc1 = *dataSrc1; + + uint32_t nb_parameters = MICROVG_PATH_get_command_parameter_number(cmdSrc1); + + *dataDest = cmdSrc1; + dataSrc1++; + dataSrc2++; + dataDest++; + + for(uint32_t j=0; joffset_path_interpolator, memory_offset); + float transformRatio = _get_transformation_ratio_at_time(animation, interpolator, atTime); + _interpolate_paths( + dest, + get_path_addr(animation_path_data->from, memory_offset), + get_path_addr(animation_path_data->to, memory_offset), + transformRatio + ); + } + else { + // last path (== path "to") + vg_path_desc_t* to = get_path_addr(animation_path_data->to, memory_offset); + dest->path = get_path_data_addr(to); + (void)memcpy((void*)&(dest->bounding_box), (void*)&(to->bounding_box), (size_t)4 * sizeof(float)); + } + + // the command buffer length is now equal to the animation path length + dest->path_length = get_path_addr(animation_path_data->from, memory_offset)->length; +} + +static void _apply_get_path_animation_path_length(vg_animation_header_t* animation, void* data, jlong atTime, size_t memory_offset, bool last) { + (void)atTime; + (void)last; + // cppcheck-suppress [misra-c2012-11.3] animations is a vg_animation_path_data_t for sure + vg_animation_path_data_t* animation_path_data = (vg_animation_path_data_t*)animation; + // cppcheck-suppress [misra-c2012-11.5] data is a uint32_t* for sure + uint32_t* path_length = (uint32_t*)data; + *path_length = MEJ_MAX(*path_length, get_path_addr(animation_path_data->from, memory_offset)->length); +} + +static void _apply_animation(vg_animation_header_t* animation, void* data, jlong atTime, VG_RAW_apply_animation_t _animation_fct, size_t memory_offset) { + int32_t begin = animation->begin; + int32_t duration = animation->duration; + int32_t keep_duration = animation->keep_duration; + + if (atTime >= begin) { + if (atTime < (begin + duration)) { + // the current frame isn't the last one + _animation_fct(animation, data, (atTime - begin), memory_offset, false); + } else if (atTime < (begin + duration + keep_duration) || (-1 == keep_duration)) { + // the final frame reached + _animation_fct(animation, data, duration, memory_offset, true); + } else { + // nothing to animate + } + } +} + +static void* _apply_group_animations_translate(float* matrix, jlong elapsed_time, vg_animation_translate_t* animations, uint32_t size, size_t memory_offset) { + vg_animation_translate_t* anims = animations; + for(uint32_t i = 0; i < size; i++) { + // cppcheck-suppress [misra-c2012-11.3] animations can be casted as vg_animation_header_t + _apply_animation((vg_animation_header_t*)anims, (void*)matrix, elapsed_time, &_apply_group_animation_translate, memory_offset); + anims++; // go to next animation + } + return (void*)anims; +} + +static void* _apply_group_animations_translate_xy(float* matrix, jlong elapsed_time, vg_animation_translate_xy_t* animations, uint32_t size, size_t memory_offset) { + vg_animation_translate_xy_t* anims = animations; + for(uint32_t i = 0; i < size; i++) { + // cppcheck-suppress [misra-c2012-11.3] animations can be casted as vg_animation_header_t + _apply_animation((vg_animation_header_t*)anims, (void*)matrix, elapsed_time, &_apply_group_animation_translate_xy, memory_offset); + anims++; // go to next animation + } + return (void*)anims; +} + +static void* _apply_group_animations_rotate(float* matrix, jlong elapsed_time, vg_animation_rotate_t* animations, uint32_t size, size_t memory_offset) { + vg_animation_rotate_t* anims = animations; + for(uint32_t i = 0; i < size; i++) { + // cppcheck-suppress [misra-c2012-11.3] animations can be casted as vg_animation_header_t + _apply_animation((vg_animation_header_t*)anims, (void*)matrix, elapsed_time, &_apply_group_animation_rotate, memory_offset); + anims++; // go to next animation + } + return (void*)anims; +} + +static void* _apply_group_animations_scale(float* matrix, jlong elapsed_time, vg_animation_scale_t* animations, uint32_t size, size_t memory_offset) { + vg_animation_scale_t* anims = animations; + for(uint32_t i = 0; i < size; i++) { + // cppcheck-suppress [misra-c2012-11.3] animations can be casted as vg_animation_header_t + _apply_animation((vg_animation_header_t*)anims, (void*)matrix, elapsed_time, &_apply_group_animation_scale, memory_offset); + anims++; // go to next animation + } + return (void*)anims; +} + +static void* _apply_path_animations_color(uint32_t* color, jlong elapsed_time, vg_animation_color_t* animations, uint32_t size, size_t memory_offset) { + vg_animation_color_t* anims = animations; + for(uint32_t i = 0; i < size; i++) { + // cppcheck-suppress [misra-c2012-11.3] animations can be casted as vg_animation_header_t + _apply_animation((vg_animation_header_t*)anims, (void*)color, elapsed_time, &_apply_path_animation_color, memory_offset); + anims++; // go to next animation + } + *color &= 0xffffff; + return (void*)anims; +} + +static void* _derive_path_animations_color(vg_animation_color_t* animations, uint32_t size, const float color_matrix[]) { + vg_animation_color_t* anims = animations; + for(uint32_t i = 0; i < size; i++) { + anims->start_color = _filter_color(anims->start_color, color_matrix); + anims->end_color = _filter_color(anims->end_color, color_matrix); + anims++; // go to next animation + } + return (void*)anims; +} + +static void* _apply_path_animations_alpha(uint8_t* alpha, jlong elapsed_time, vg_animation_alpha_t* animations, uint32_t size, size_t memory_offset) { + vg_animation_alpha_t* anims = animations; + for(uint32_t i = 0; i < size; i++) { + // cppcheck-suppress [misra-c2012-11.3] animations can be casted as vg_animation_header_t + _apply_animation((vg_animation_header_t*)anims, (void*)alpha, elapsed_time, &_apply_path_animation_alpha, memory_offset); + anims++; // go to next animation + } + return (void*)anims; +} + +static void* _derive_path_animations_alpha(vg_animation_alpha_t* animations, uint32_t size, const float color_matrix[]) { + vg_animation_alpha_t* anims = animations; + for(uint32_t i = 0; i < size; i++) { + anims->start_alpha = _filter_alpha(anims->start_alpha, color_matrix); + anims->end_alpha = _filter_alpha(anims->end_alpha, color_matrix); + anims++; // go to next animation + } + return (void*)anims; +} + +static void* _apply_path_animations_path_data(vg_lite_path_t* path, jlong elapsed_time, vg_animation_path_data_t* animations, uint32_t size, size_t memory_offset) { + vg_animation_path_data_t* anims = animations; + for(uint32_t i = 0; i < size; i++) { + // cppcheck-suppress [misra-c2012-11.3] animations can be casted as vg_animation_header_t + _apply_animation((vg_animation_header_t*)anims, (void*)path, elapsed_time, &_apply_path_animation_path_data, memory_offset); + anims++; // go to next animation + } + return (void*)anims; +} + +static uint32_t _get_path_animations_path_max_length(vg_lite_path_t* path, jlong elapsed_time, vg_animation_path_data_t* animations, uint32_t size, size_t memory_offset) { + vg_animation_path_data_t* anims = animations; + uint32_t length = path->path_length; + for(uint32_t i = 0; i < size; i++) { + // cppcheck-suppress [misra-c2012-11.3] animations can be casted as vg_animation_header_t + _apply_animation((vg_animation_header_t*)anims, (void*)&length, elapsed_time, &_apply_get_path_animation_path_length, memory_offset); + anims++; // go to next animation + } + return length; +} +/* + * @brief path is in ROM (RAW): have to copy the path in a local structure and update the address + * (replace the path data offset by the absolute address in ROM). + */ +static void _prepare_render_path(vg_drawing_t* drawing_data, vg_path_desc_t* image_path) { + vg_path_desc_t* path = get_path_addr(image_path, drawing_data->memory_offset); + vg_lite_init_path( + &render_path, + path->format, + VG_LITE_HIGH, + path->length, + get_path_data_addr(path), + path->bounding_box[0], + path->bounding_box[1], + path->bounding_box[2], + path->bounding_box[3] + ); + render_path.path_type = VG_LITE_DRAW_FILL_PATH; +} + +static inline jint _draw_render_path(VG_DRAWING_VGLITE_draw_image_element_t drawer, vg_lite_matrix_t* matrix, vg_block_path_t* op, uint32_t color) { + return (*drawer)(&render_path, op->fill_rule, matrix, VG_LITE_BLEND_SRC_OVER, color, NULL, false); +} + +static inline jint _draw_render_gradient(VG_DRAWING_VGLITE_draw_image_element_t drawer, vg_lite_matrix_t* matrix, vg_lite_fill_t fill_rule, bool is_new_gradient) { + return (*drawer)(&render_path, fill_rule, matrix, VG_LITE_BLEND_SRC_OVER, 0, &render_gradient, is_new_gradient); +} + +static bool _prepare_render_gradient(vg_drawing_t* drawing_data, vg_block_gradient_t* op, uint8_t alpha, const float color_matrix[], vg_lite_matrix_t* transformation) { + + // copy op's gradient in a local gradient to apply the opacity + vg_lite_linear_gradient_t local_gradient; + vg_lite_linear_gradient_t* op_gradient = get_gradient_addr(op->gradient, drawing_data->memory_offset); + (void)memcpy(&local_gradient, op_gradient, GRADIENT_COPY_SIZE); + _prepare_gradient_colors(&local_gradient, alpha, color_matrix); + + vg_lite_linear_gradient_t* p_render_gradient = &render_gradient; + bool is_new_gradient = (0 != memcmp(p_render_gradient, &local_gradient, GRADIENT_CMP_SIZE)); + + if (is_new_gradient) { + // copy the new gradient data in shared gradient + (void)memcpy(p_render_gradient, &local_gradient, GRADIENT_COPY_SIZE); + } + + // update the gradient's matrix + LLVG_MATRIX_IMPL_multiply( + MAP_VGLITE_MATRIX(&(p_render_gradient->matrix)), + MAP_VGLITE_MATRIX(transformation), + MAP_VGLITE_MATRIX(&op_gradient->matrix) + ); + + return is_new_gradient; +} + +static uint8_t* _animate_render_path(jlong elapsed_time, vg_animation_path_data_t* first_animation, uint32_t nb_animations, size_t memory_offset, jint* error) { + + uint8_t* command_buffer; + + *error = LLVG_SUCCESS; + + if ((uint8_t)0 < nb_animations) { + + // allocate a command buffer where "from" and "to" will be merged + uint32_t size = _get_path_animations_path_max_length(&render_path, elapsed_time, first_animation, nb_animations, memory_offset); + command_buffer = _alloc_data(size); + + if (NULL != command_buffer) { + + void* original_commands = render_path.path; + int32_t original_commands_length = render_path.path_length; + + // update the destination commands buffer address + render_path.path = (void*)command_buffer; + render_path.path_length = 0; + + // update path commands, the path length and the bounding box + (void)_apply_path_animations_path_data(&render_path, elapsed_time, first_animation, nb_animations, memory_offset); + + if (0 == render_path.path_length) { + + // no animation has been applied: restore the original path + render_path.path = original_commands; + render_path.path_length = original_commands_length; + + // free the useless command buffer + _free_data(command_buffer); + command_buffer = NULL; + } + } + else { + *error = LLVG_OUT_OF_MEMORY; + } + // else not enough memory in heap: use original path + } + else { + // nothing to do: use path asis + command_buffer = NULL; + } + + return command_buffer; +} + +static inline void _animation_path_end(uint8_t* command_buffer) { + if (NULL != command_buffer) { + _free_data(command_buffer); + } +} + +static inline vg_block_t* _go_to_next_block(vg_block_t* block, size_t size) { + // cppcheck-suppress [misra-c2012-11.3,misra-c2012-18.4] cast the block in a u8 address and points to the next block + return (vg_block_t*)(((uint8_t*)block) + size); +} + +static jint _manage_block_gradient(vg_drawing_t* drawing_data, VG_DRAWING_VGLITE_draw_image_element_t target, vg_block_t* block, vg_lite_matrix_t* matrix, uint32_t alpha, const float color_matrix[], vg_lite_matrix_t* gradient_deformation) { + + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_gradient_t for sure + vg_block_gradient_t* op = (vg_block_gradient_t*)block; + + // prepare the gradient + _prepare_render_path(drawing_data, op->path.desc); + bool is_new_gradient = _prepare_render_gradient(drawing_data, op, alpha, color_matrix, gradient_deformation); + + return _draw_render_gradient(target, matrix, op->path.fill_rule, is_new_gradient); +} + +static void _get_image_parameters(vector_image_t* image, vg_drawing_t* drawing_data) { + + if (!_is_image_address_relative(image)) { + // the addresses are absolute: no memory offset + drawing_data->memory_offset = 0; + } + else { + // the addresses are relative: the memory offset is tehe image address + // cppcheck-suppress [misra-c2012-11.4] save the image address as the memory offset to apply on each address + drawing_data->memory_offset = (size_t)image; + } + + uint8_t* first_block_addr = (uint8_t*)image->first_block; + + // cppcheck-suppress [misra-c2012-18.4] adds the absolute memory offset + first_block_addr += drawing_data->memory_offset; + + // cppcheck-suppress [misra-c2012-11.3] address points to the first block for sure + drawing_data->first_block = (vg_block_t*)first_block_addr; + + drawing_data->drawing_running = false; +} + +// ----------------------------------------------------------------------------- +// BufferedVectorImage (BVI) Management +// ----------------------------------------------------------------------------- + +#if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +/* + * @brief Tells if the image is in ROM. + */ +static inline bool _bvi_is_image_in_rom(vector_image_t* image) { + return 0u == image->flags.ram; +} + +static inline void _bvi_tag_image_as_absolute(vector_image_t* image) { + image->flags.absolute = 1u; +} + +static vg_path_desc_t* _bvi_store_vglite_path(vg_lite_path_t* path) { + // cppcheck-suppress [misra-c2012-11.3] the allocated data is a vg_path_desc_t for sure + vg_path_desc_t* data = (vg_path_desc_t*)_alloc_data(sizeof(vg_path_desc_t) + path->path_length); + + if (NULL != data) { + uint8_t* cmd_addr = (uint8_t*)data; + + // cppcheck-suppress [misra-c2012-18.4] points after the path description + cmd_addr += sizeof(vg_path_desc_t); + + (void)memcpy((void*)&(data->bounding_box), (void*)&(path->bounding_box), (size_t)4 * sizeof(float)); + (void)memcpy((void*)cmd_addr, path->path, path->path_length); + data->format = path->format; + data->length = path->path_length; + } + + return data; +} + +static inline vg_lite_linear_gradient_t* _bvi_store_vglite_gradient(vg_lite_linear_gradient_t * grad) { + return (vg_lite_linear_gradient_t*)_store_data(grad, GRADIENT_COPY_SIZE); +} + +static inline vg_block_t* _bvi_free_operation_color(vg_block_bvi_color_t* op) { + vg_block_t* ret = op->next; + _free_data(op->header.path.desc); + _free_data(op); + return ret; +} + +static inline vg_block_t* _bvi_free_operation_gradient(vg_block_bvi_gradient_t* op) { + vg_block_t* ret = op->next; + _free_data(op->header.path.desc); + if (!op->shared_gradient) { + _free_data(op->header.gradient); + } + _free_data(op); + return ret; +} + +static inline vg_block_t* _bvi_free_operation_image(vg_block_bvi_image_t* op) { + vg_block_t* ret = op->next; + _free_data(op); + return ret; +} + +static vg_block_t* _bvi_free_block(vg_block_t* block) { + vg_block_t* ret; + switch(block->kind) { + case VG_BLOCK_BVI_COLOR: + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_bvi_color_t for sure + ret = _bvi_free_operation_color((vg_block_bvi_color_t*)block); + break; + case VG_BLOCK_BVI_GRADIENT: + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_bvi_gradient_t for sure + ret = _bvi_free_operation_gradient((vg_block_bvi_gradient_t*)block); + break; + case VG_BLOCK_BVI_IMAGE: + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_bvi_image_t for sure + ret = _bvi_free_operation_image((vg_block_bvi_image_t*)block); + break; + case VG_BLOCK_GROUP_TRANSFORM: + case VG_BLOCK_GROUP_END: + case VG_BLOCK_LAST: + case VG_BLOCK_GROUP_ANIMATE: + case VG_BLOCK_RAW_GRADIENT: + case VG_BLOCK_PATH_COLOR_ANIMATE: + case VG_BLOCK_PATH_GRADIENT_ANIMATE: + default: + // a BVI cannot free this kind of block: never here + ret = block; + break; + } + return ret; +} + +static inline jint _bvi_link_operations(vector_buffered_image_t* raw, vg_block_t* op, vg_block_t** op_next_block, bool oom) { + + jint ret; + + if (!oom) { + if (NULL == raw->latest_data) { + // very first block + raw->header.first_block = op; + } + else { + *(raw->latest_data) = op; + } + raw->latest_data = op_next_block; + *(op_next_block) = &(raw->last_block); + + ret = LLVG_SUCCESS; + } + else { + (void)_bvi_free_block(op); + ret = LLVG_OUT_OF_MEMORY; + } + + return ret; +} + +static void _bvi_save_current_vglite_scissor(int32_t* dest) { + int32_t* scissor; + if (0u != vg_lite_get_scissor(&scissor)) { + (void)memcpy((void*)dest, (void*)scissor, 4u * sizeof(int32_t)); + } + else { + // no clip: -1 is not a valid X clip value + dest[0] = -1; + } +} + +static inline vector_buffered_image_t* _bvi_get_bvi_from_target(void* target) { + // cppcheck-suppress [misra-c2012-11.5] cast is possible (the target stored in drawer is a vector_buffered_image_t* for sure) + return (vector_buffered_image_t*)target; +} + +static jint _bvi_add_draw_raw_image( + vector_buffered_image_t* dest, + vector_image_t* source, + jfloat *matrix, + jint alpha, + jlong elapsed, + const float color_matrix[] +) { + + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_bvi_image_t for sure + vg_block_bvi_image_t* op = (vg_block_bvi_image_t*)_alloc_data(sizeof(vg_block_bvi_image_t)); + jint ret = LLVG_OUT_OF_MEMORY; + + if (NULL != op) { + + op->block.kind = VG_BLOCK_BVI_IMAGE; + op->alpha = (jchar)alpha; + op->image = source; + (void)memcpy((void*)&(op->matrix), (void*)matrix, (size_t)LLVG_MATRIX_SIZE * sizeof(jfloat)); + _bvi_save_current_vglite_scissor(op->scissor); + if (NULL != color_matrix) { + // required size is checked by Java library + (void)memcpy((void*)&(op->color_matrix), color_matrix, (size_t)COLOR_MATRIX_SIZE * sizeof(jfloat)); + op->flags = 1u; + } + else { + op->flags = 0u; + } + op->elapsed_msb = (jint)elapsed; + op->elapsed_lsb = (jint)(elapsed >> 32); + + // cppcheck-suppress [misra-c2012-11.3] operation is a vg_block_t + ret = _bvi_link_operations(dest, (vg_block_t*)op, &(op->next), false); + } + + return ret; +} + +/* + * @brief Function type is "VG_DRAWING_VGLITE_draw_image_element_t" (called by _draw_raw_image()). + */ +static jint _bvi_add_image_element(vg_lite_path_t * path, vg_lite_fill_t fill_rule, vg_lite_matrix_t * matrix, vg_lite_blend_t blend, vg_lite_color_t color, vg_lite_linear_gradient_t * grad, bool is_new_gradient) { + (void)is_new_gradient; + jint ret; + if (NULL == grad) { + ret = BVI_VGLITE_add_draw_path(bvi_target, path, fill_rule, matrix, blend, color); + } + else { + ret = BVI_VGLITE_add_draw_gradient(bvi_target, path, fill_rule, matrix, grad, blend); + } + return ret; +} + +/* + * @brief Transform a 2D point by a given matrix. + * + * Copy from vg_lite.c + */ +static void _bvi_transform_point(vg_lite_point_t * result, vg_lite_float_t x, vg_lite_float_t y, vg_lite_matrix_t * matrix) { + + /* Transform w. */ + vg_lite_float_t pt_w = (x * matrix->m[2][0]) + (y * matrix->m[2][1]) + matrix->m[2][2]; + if (pt_w <= 0.0f) { + result->x = 0; + result->y = 0; + } + else { + /* Transform x and y. */ + vg_lite_float_t pt_x = (x * matrix->m[0][0]) + (y * matrix->m[0][1]) + matrix->m[0][2]; + vg_lite_float_t pt_y = (x * matrix->m[1][0]) + (y * matrix->m[1][1]) + matrix->m[1][2]; + + /* Compute projected x and y. */ + result->x = (int)(pt_x / pt_w); + result->y = (int)(pt_y / pt_w); + } +} + +/* + * @brief Applies the scissor. The scissor is adjusted with the given matrix (image's matrix) + * and the current scissor (master scissor). + * + * @param[in] scissor: pointer to the scissor to apply or NULL. + * @param[in] matrix: pointer to the matrix to apply to the scissor. + * @param[in/out] current_scissor: pointer to the current scissor, set to NULL when the scissor is modified and has to be restored after the drawing. + * + * @return false when no drawing should be performed (empty scissor), true otherise. + */ +static bool _bvi_apply_scissor(int32_t* scissor, vg_lite_matrix_t *matrix, int32_t** current_scissor) { + + bool draw = true; + + if (scissor[0] >= 0) { + vg_lite_point_t top_left; + vg_lite_point_t bottom_right; + + // get the top-left and bottom-right scissor points adjusted with the given matrix. + _bvi_transform_point(&top_left, (vg_lite_float_t)scissor[0], (vg_lite_float_t)scissor[1], matrix); + _bvi_transform_point(&bottom_right, (vg_lite_float_t)(scissor[0] + scissor[2] - 1), (vg_lite_float_t)(scissor[1] + scissor[3] - 1), matrix); + + if ((*current_scissor) != NULL) { + + int32_t cx1 = (*current_scissor)[0]; + int32_t cy1 = (*current_scissor)[1]; + int32_t cx2 = cx1 + (*current_scissor)[2] - 1; + int32_t cy2 = cy1 + (*current_scissor)[3] - 1; + + if (top_left.x < cx1) { + top_left.x = cx1; + } + if (top_left.y < cy1) { + top_left.y = cy1; + } + if (bottom_right.x >= cx2) { + bottom_right.x = cx2; + } + if (bottom_right.y >= cy2) { + bottom_right.y = cy2; + } + } + + if ((top_left.x <= bottom_right.x) && (top_left.y <= bottom_right.y)) { + vg_lite_enable_scissor(); + vg_lite_set_scissor(top_left.x, top_left.y, bottom_right.x - top_left.x + 1, bottom_right.y - top_left.y + 1); + *current_scissor = NULL; // have to restore the clip + } + else { + // empty clip: nothing to restore and nothing to draw + draw = false; + } + + } + // else: no local clip: nothing to restore + + return draw; +} + +static int32_t* _bvi_restore_scissor(int32_t* original_scissor, int32_t* current_scissor) { + if (original_scissor != current_scissor) { + // the scissor has been modified: restore the original one + if (NULL != original_scissor) { + vg_lite_enable_scissor(); + vg_lite_set_scissor(original_scissor[0], original_scissor[1], original_scissor[2], original_scissor[3]); + } + else { + vg_lite_disable_scissor(); + } + } + return original_scissor; +} + +static vg_block_t* _bvi_clear_blocks(vector_buffered_image_t* image) { + vg_block_t* block = image->header.first_block; + while(VG_BLOCK_LAST != block->kind) { + block = _bvi_free_block(block); + } + return block; +} + +/* + * @brief Combines two color matrices into a single one. + *

+ * The application of the returned matrix is equivalent to the successive application of the two given matrices. + *

+ * The algorithm used in this method is based on to the computation of the matrix multiplication B x A + * where a 5th row of values (0, 0, 0, 0, 1) would be appended to the matrix A. + *

+ * - Matrix a can be null, in such case, matrix b is returned, + * - Matrix b can be null, in such case, matrix a is returned, + * - Both matrices can be null, in such case, NULL is returned, + * - if not null, the result is stored in the global matrix "combined_color_matrices" (old content is overwritten) + * and returned + * + * @param a + * the operation matrix. + * @param b + * the transformation to apply. + * @return the combined matrix. + */ +static float* _combine_color_matrices(float* a, float* b) { + + float* dest; + + if (NULL != a) { + // operation holds a color matrix (image matrix) + if (NULL != b) { + // draw with another matrix + + // -> need to combine user matrix and operation matrix + // use the shared array + dest = combined_color_matrices; + (void)memset(dest, 0, (size_t)COLOR_MATRIX_SIZE * sizeof(float)); + + for (int y = 0; y < COLOR_MATRIX_HEIGHT; y++) { + int y5 = y * COLOR_MATRIX_WIDTH; + for (int x = 0; x < COLOR_MATRIX_WIDTH; x++) { + // here (x,y) is the cell to compute + for (int i = 0; i < COLOR_MATRIX_WIDTH; i++) { + if (i < COLOR_MATRIX_HEIGHT) { + int i5 = i * COLOR_MATRIX_WIDTH; + dest[y5 + x] += b[y5 + i] * a[i5 + x]; + } else { + dest[y5 + x] += b[y5 + i] * CONSTANT_ROW[x]; + } + } + } + } + } + else { + // use the operation matrix + dest = a; + } + } + else if (NULL != b){ + // use the user matrix + dest = b; + } + else { + // no color matrix to apply + dest = NULL; + } + + return dest; +} + +#endif // #if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +static jint _draw_raw_image(vg_drawing_t* drawing_data, VG_DRAWING_VGLITE_draw_image_element_t target, jfloat* matrix, uint32_t alpha, jlong elapsedTime, const float color_matrix[]) { + + vg_block_t* block = drawing_data->first_block; + bool animate = elapsedTime >= 0; + jlong elapsed_time = animate ? elapsedTime : 0; // default time when there is no animation + + // create initial transformation with application's matrix + drawing_data->first_transformation.parent = NULL; + (void)memcpy((void*)&(drawing_data->first_transformation.matrix), (void*)matrix, sizeof(vg_lite_matrix_t)); + vg_transformation_t* p_render_transformation = &(drawing_data->first_transformation); + + +#if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + + int32_t original_scissor[4]; + int32_t* p_original_scissor; + int32_t* p_current_scissor; + if (0u != vg_lite_get_scissor(&p_original_scissor)) { + // p_original_scissor points to vglite scissor + + // save vglite scissor in "original scissor" + original_scissor[0] = p_original_scissor[0]; + original_scissor[1] = p_original_scissor[1]; + original_scissor[2] = p_original_scissor[2]; + original_scissor[3] = p_original_scissor[3]; + + // now p_original_scissor points to the local array + p_original_scissor = original_scissor; + p_current_scissor = original_scissor; + } + else { + // no current scissor + p_original_scissor = NULL; + p_current_scissor = NULL; + } + +#endif // #if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + + jint ret = LLVG_SUCCESS; + bool done = false; + while(!done) { + + switch(block->kind) { + + case VG_BLOCK_LAST:{ + done = true; + } + break; + + case VG_BLOCK_GROUP_TRANSFORM:{ + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_group_transform_t for sure + vg_block_group_transform_t* op = (vg_block_group_transform_t*)block; + + // copy current transformation + vg_transformation_t* parent_transformation = p_render_transformation; + p_render_transformation = _store_vg_transformation(parent_transformation); + + if (NULL != p_render_transformation){ + p_render_transformation->parent = parent_transformation; + + // concatenate first transformation with new operation transformation + LLVG_MATRIX_IMPL_concatenate(MAP_VGLITE_MATRIX(&(p_render_transformation->matrix)), MAP_VGLITE_MATRIX(&(op->matrix))); + } + else { + ret = LLVG_OUT_OF_MEMORY; + // Cannot apply a new transformation: keep the current one. + } + + block = _go_to_next_block(block, sizeof(vg_block_group_transform_t)); + } + break; + + case VG_BLOCK_GROUP_END:{ + if (NULL != p_render_transformation->parent){ + + // back to parent transformation + vg_transformation_t* transformation_to_remove = p_render_transformation; + p_render_transformation = transformation_to_remove->parent; + _free_vg_transformation(transformation_to_remove); + } + + block = _go_to_next_block(block, sizeof(vg_block_group_end_t)); + } + break; + + case VG_BLOCK_GROUP_ANIMATE:{ + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_group_animation_t for sure + vg_block_group_animation_t* op = (vg_block_group_animation_t*)block; + + // copy current transformation + vg_transformation_t* parent_transformation = p_render_transformation; + p_render_transformation = _store_vg_transformation(parent_transformation); + + if (NULL != p_render_transformation){ + p_render_transformation->parent = parent_transformation; + + float* mapped_matrix = MAP_VGLITE_MATRIX(&(p_render_transformation->matrix)); + // cppcheck-suppress [misra-c2012-18.4] points after the operation + void* animations_offset = ((uint8_t*)op) + sizeof(vg_block_group_animation_t); + + if (animate) { + // cppcheck-suppress [misra-c2012-11.5] animations_offset points on a vg_animation_translate_t for sure + animations_offset = _apply_group_animations_translate(mapped_matrix, elapsed_time, (vg_animation_translate_t*)animations_offset, op->nb_translates, drawing_data->memory_offset); + // cppcheck-suppress [misra-c2012-11.5] animations_offset points on a vg_animation_translate_xy_t for sure + animations_offset = _apply_group_animations_translate_xy(mapped_matrix, elapsed_time, (vg_animation_translate_xy_t*)animations_offset, op->nb_translates_xy, drawing_data->memory_offset); + } + + LLVG_MATRIX_IMPL_translate(mapped_matrix, op->translate_x, op->translate_y); + + if (animate) { + // cppcheck-suppress [misra-c2012-11.5] animations_offset points on a vg_animation_rotate_t for sure + animations_offset = _apply_group_animations_rotate(mapped_matrix, elapsed_time, (vg_animation_rotate_t*)animations_offset, op->nb_rotates, drawing_data->memory_offset); + } + + LLVG_MATRIX_IMPL_translate(mapped_matrix, op->pivot_x, op->pivot_y); + LLVG_MATRIX_IMPL_rotate(mapped_matrix, op->rotation); + LLVG_MATRIX_IMPL_translate(mapped_matrix, -op->pivot_x, -op->pivot_y); + + if (animate) { + // cppcheck-suppress [misra-c2012-11.5] animations_offset points on a vg_animation_scale_t for sure + /*animations_offset =*/ (void)_apply_group_animations_scale(mapped_matrix, elapsed_time, (vg_animation_scale_t*)animations_offset, op->nb_scales, drawing_data->memory_offset); + } + + LLVG_MATRIX_IMPL_translate(mapped_matrix, op->pivot_x, op->pivot_y); + LLVG_MATRIX_IMPL_scale(mapped_matrix, op->scale_x, op->scale_y); + LLVG_MATRIX_IMPL_translate(mapped_matrix, -op->pivot_x, -op->pivot_y); + } + else { + ret = LLVG_OUT_OF_MEMORY; + // Cannot apply a new transformation: keep the current one. + } + + block = _go_to_next_block(block, op->block_size); + } + break; + + case VG_BLOCK_PATH_COLOR_ANIMATE: { + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_animate_color_t for sure + vg_block_animate_color_t* op = (vg_block_animate_color_t*)block; + // cppcheck-suppress [misra-c2012-18.4] points after the operation + void* animations_offset = ((uint8_t*)op) + sizeof(vg_block_animate_color_t); + + // update color & alpha + uint32_t color = op->header.color; + uint8_t color_alpha = COLOR_GET_CHANNEL(color, ARGB8888, ALPHA); + // cppcheck-suppress [misra-c2012-11.5] animations_offset points on a vg_animation_color_t for sure + animations_offset = _apply_path_animations_color(&color, elapsed_time, (vg_animation_color_t*)animations_offset, op->nb_colors, drawing_data->memory_offset); + // cppcheck-suppress [misra-c2012-11.5] animations_offset points on a vg_animation_alpha_t for sure + animations_offset = _apply_path_animations_alpha(&color_alpha, elapsed_time, (vg_animation_alpha_t*)animations_offset, op->nb_alphas, drawing_data->memory_offset); + color |= (color_alpha << COLOR_ARGB8888_ALPHA_OFFSET); + color = _prepare_render_color(color, alpha, color_matrix); + + // prepare & animate the path + _prepare_render_path(drawing_data, op->header.path.desc); + jint error; + // cppcheck-suppress [misra-c2012-11.5] animations_offset points on a vg_animation_path_data_t for sure + uint8_t* command_buffer = _animate_render_path(elapsed_time, (vg_animation_path_data_t*)animations_offset, op->nb_path_datas, drawing_data->memory_offset, &error); + if (LLVG_SUCCESS != error) { + ret = error; + } + + error = _draw_render_path(target, &(p_render_transformation->matrix), &(op->header.path), color); + if (LLVG_SUCCESS != error) { + ret = error; + } + drawing_data->drawing_running = true; + + _animation_path_end(command_buffer); + + block = _go_to_next_block(block, op->block_size); + } + break; + + case VG_BLOCK_PATH_GRADIENT_ANIMATE: { + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_animate_gradient_t for sure + vg_block_animate_gradient_t* op = (vg_block_animate_gradient_t*)block; + // cppcheck-suppress [misra-c2012-18.4] points after the operation + void* animations_offset = ((uint8_t*)op) + sizeof(vg_block_animate_gradient_t); + + uint32_t alpha_to_apply = alpha; + if ((uint8_t)0 < op->nb_alphas) { + // update alpha + uint8_t alpha_anim = (uint8_t)0xff; + // cppcheck-suppress [misra-c2012-11.5] animations_offset points on a vg_animation_alpha_t for sure + animations_offset = _apply_path_animations_alpha(&alpha_anim, elapsed_time, (vg_animation_alpha_t*)animations_offset, op->nb_alphas, drawing_data->memory_offset); + alpha_to_apply *= alpha_anim; + alpha_to_apply /= 255; + } + + // prepare & animate the path + _prepare_render_path(drawing_data, op->header.path.desc); + jint error; + // cppcheck-suppress [misra-c2012-11.5] animations_offset points on a vg_animation_path_data_t for sure + uint8_t* command_buffer = _animate_render_path(elapsed_time, (vg_animation_path_data_t*)animations_offset, op->nb_path_datas, drawing_data->memory_offset, &error); + if (LLVG_SUCCESS != error) { + ret = error; + } + + // prepare the gradient + bool is_new_gradient = _prepare_render_gradient(drawing_data, &(op->header), alpha_to_apply, color_matrix, &(p_render_transformation->matrix)); + + error = _draw_render_gradient(target, &(p_render_transformation->matrix), op->header.path.fill_rule, is_new_gradient); + if (LLVG_SUCCESS != error) { + ret = error; + } + drawing_data->drawing_running = true; + + _animation_path_end(command_buffer); + + block = _go_to_next_block(block, op->block_size); + } + break; + + case VG_BLOCK_PATH_COLOR: { + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_color_t for sure + vg_block_color_t* op = (vg_block_color_t*)block; + _prepare_render_path(drawing_data, op->path.desc); + uint32_t color = _prepare_render_color(op->color, alpha, color_matrix); + jint error = _draw_render_path(target, &(p_render_transformation->matrix), &(op->path), color); + if (LLVG_SUCCESS != error) { + ret = error; + } + drawing_data->drawing_running = true; + block = _go_to_next_block(block, sizeof(vg_block_color_t)); + } + break; + + case VG_BLOCK_RAW_GRADIENT: { + // apply same deformation on path and gradient + jint error = _manage_block_gradient(drawing_data, target, block, &(p_render_transformation->matrix), alpha, color_matrix, &(p_render_transformation->matrix)); + if (LLVG_SUCCESS != error) { + ret = error; + } + drawing_data->drawing_running = true; + block = _go_to_next_block(block, sizeof(vg_block_gradient_t)); + } + break; + +#if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + + case VG_BLOCK_BVI_COLOR: { + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_bvi_color_t for sure + vg_block_bvi_color_t* op = (vg_block_bvi_color_t*)block; + + if (_bvi_apply_scissor(op->scissor, &(p_render_transformation->matrix), &p_current_scissor)) { + + // concatenate first transformation with new operation transformation + vg_lite_matrix_t temp; + LLVG_MATRIX_IMPL_multiply(MAP_VGLITE_MATRIX(&temp), MAP_VGLITE_MATRIX(&(p_render_transformation->matrix)), MAP_VGLITE_MATRIX(&(op->path_deformation))); + + _prepare_render_path(drawing_data, op->header.path.desc); + uint32_t color = _prepare_render_color(op->header.color, alpha, color_matrix); + jint error = _draw_render_path(target, &temp, &(op->header.path), color); + if (LLVG_SUCCESS != error) { + ret = error; + } + drawing_data->drawing_running = true; + + // the clip may have been modified: restore the original one + p_current_scissor = _bvi_restore_scissor(p_original_scissor, p_current_scissor); + } + block = op->next; + } + break; + + case VG_BLOCK_BVI_GRADIENT: { + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_bvi_gradient_t for sure + vg_block_bvi_gradient_t* op = (vg_block_bvi_gradient_t*)block; + + if (_bvi_apply_scissor(op->scissor, &(p_render_transformation->matrix), &p_current_scissor)) { + + // concatenate first transformation with new operation transformation + vg_lite_matrix_t temp; + LLVG_MATRIX_IMPL_multiply(MAP_VGLITE_MATRIX(&temp), MAP_VGLITE_MATRIX(&(p_render_transformation->matrix)), MAP_VGLITE_MATRIX(&(op->path_deformation))); + + // do not apply same deformation on path and gradient (gradient already "has" the path's deformation) + jint error = _manage_block_gradient(drawing_data, target, block, &temp, alpha, color_matrix, &(p_render_transformation->matrix)); + if (LLVG_SUCCESS != error) { + ret = error; + } + drawing_data->drawing_running = true; + + // the clip may have been modified: restore the original one + p_current_scissor = _bvi_restore_scissor(p_original_scissor, p_current_scissor); + } + block = op->next; + } + break; + + case VG_BLOCK_BVI_IMAGE: { + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_bvi_image_t for sure + vg_block_bvi_image_t* op = (vg_block_bvi_image_t*)block; + + if (_bvi_apply_scissor(op->scissor, &(p_render_transformation->matrix), &p_current_scissor)) { + + _get_image_parameters(op->image, &raw_in_bvi_drawing_data); + + // retrieve elapsed time + jlong elapsedTime_msb = op->elapsed_msb; + jlong elapsedTime_lsb = op->elapsed_lsb; + elapsedTime_msb <<= 32; + elapsedTime_lsb &= 0xfffffffful; + jlong raw_elapsed_time = (elapsedTime_msb | elapsedTime_lsb); + + // merge operation's color matrix with global color matrix + float* image_color_matrix = (1u == op->flags) ? (float*)op->color_matrix : NULL; + // cppcheck-suppress [misra-c2012-11.8] allow cast to float* + image_color_matrix = _combine_color_matrices(image_color_matrix, (float*)color_matrix); + + // merge operation's alpha with global alpha + uint32_t image_alpha = op->alpha; + image_alpha *= alpha; + image_alpha /= 255; + + // concatenate first transformation with new operation transformation + vg_lite_matrix_t temp; + LLVG_MATRIX_IMPL_multiply(MAP_VGLITE_MATRIX(&temp), MAP_VGLITE_MATRIX(&(p_render_transformation->matrix)), MAP_VGLITE_MATRIX(&(op->matrix))); + + // cppcheck-suppress [misra-c2012-17.2] only one level of recursion + jint error = _draw_raw_image(&raw_in_bvi_drawing_data, target, MAP_VGLITE_MATRIX(&temp), image_alpha, raw_elapsed_time, image_color_matrix); + if (LLVG_SUCCESS != error) { + ret = error; + } + drawing_data->drawing_running |= raw_in_bvi_drawing_data.drawing_running; + } + + block = op->next; + } + break; + +#endif // #if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + + default: + MEJ_LOG_ERROR_MICROVG("unknown operation: %u\n", block->kind); + ret = LLVG_DATA_INVALID; + done = true; + break; + } + } + + return ret; +} + +static void _derive_raw_image(vg_drawing_t* drawing_data, const float color_matrix[]) { + + bool done = false; + vg_block_t* block = drawing_data->first_block; + + while(!done) { + + switch(block->kind) { + + case VG_BLOCK_LAST:{ + done = true; + } + break; + + case VG_BLOCK_GROUP_TRANSFORM: { + // nothing to do + block = _go_to_next_block(block, sizeof(vg_block_group_transform_t)); + } + break; + + case VG_BLOCK_GROUP_END: { + // nothing to do + block = _go_to_next_block(block, sizeof(vg_block_group_end_t)); + } + break; + + case VG_BLOCK_GROUP_ANIMATE: { + // nothing to do + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_group_animation_t for sure + vg_block_group_animation_t* op = (vg_block_group_animation_t*)block; + block = _go_to_next_block(block, op->block_size); + } + break; + + case VG_BLOCK_PATH_COLOR_ANIMATE: { + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_animate_color_t for sure + vg_block_animate_color_t* op = (vg_block_animate_color_t*)block; + // cppcheck-suppress [misra-c2012-18.4] points after the operation + void* animations_offset = ((uint8_t*)op) + sizeof(vg_block_animate_color_t); + op->header.color = _filter_color(op->header.color, color_matrix); + // cppcheck-suppress [misra-c2012-11.5] animations_offset points on a vg_animation_color_t for sure + animations_offset = _derive_path_animations_color((vg_animation_color_t*)animations_offset, op->nb_colors, color_matrix); + // cppcheck-suppress [misra-c2012-11.5] animations_offset points on a vg_animation_alpha_t for sure + /*animations_offset =*/ (void)_derive_path_animations_alpha((vg_animation_alpha_t*)animations_offset, op->nb_alphas, color_matrix); + block = _go_to_next_block(block, op->block_size); + } + break; + + case VG_BLOCK_PATH_GRADIENT_ANIMATE: { + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_animate_gradient_t for sure + vg_block_animate_gradient_t* op = (vg_block_animate_gradient_t*)block; + vg_lite_linear_gradient_t* gradient = get_gradient_addr(op->header.gradient, drawing_data->memory_offset); + _filter_gradient(gradient, color_matrix); + block = _go_to_next_block(block, op->block_size); + } + break; + + case VG_BLOCK_PATH_COLOR: { + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_color_t for sure + vg_block_color_t* op = (vg_block_color_t*)block; + op->color = _filter_color(op->color, color_matrix); + block = _go_to_next_block(block, sizeof(vg_block_color_t)); + } + break; + + case VG_BLOCK_RAW_GRADIENT: { + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_gradient_t for sure + vg_block_gradient_t* op = (vg_block_gradient_t*)block; + vg_lite_linear_gradient_t* gradient = get_gradient_addr(op->gradient, drawing_data->memory_offset); + _filter_gradient(gradient, color_matrix); + block = _go_to_next_block(block, sizeof(vg_block_gradient_t)); + } + break; + +#if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + + case VG_BLOCK_BVI_COLOR: + case VG_BLOCK_BVI_GRADIENT: + case VG_BLOCK_BVI_IMAGE: + // must not occur: can only derive from a RAW image (see BufferedVectorImage.filterImage()) + +#endif // #if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + + default: + MEJ_LOG_ERROR_MICROVG("unknown operation: %u\n", block->kind); + done = true; + break; + } + } +} + +static void _initialize(void) { + if (!initialiazed) { + + // prepare the gradient used by all draw_gradient + (void)memset(&(render_gradient), 0, sizeof(vg_lite_linear_gradient_t)); + (void)vg_lite_init_grad(&(render_gradient)); // always success + render_gradient.image.format = VG_LITE_RGBA8888; // fix color format + + initialiazed = true; + } +} + +/* + * @brief Tells if the byte array denotes a RAW image. A RAW image is identified + * by its signature. + */ +static inline bool _is_raw_image(uint8_t* image) { + return 0 == memcmp(image, signature, sizeof(signature)); +} + +static inline void _store_image_metadata(const vector_image_t* image, jint extra_flags, jint* metadata) { + metadata[RAW_OFFSET_F32_WIDTH] = JFLOAT_TO_UINT32_t(image->width); + metadata[RAW_OFFSET_F32_HEIGHT] = JFLOAT_TO_UINT32_t(image->height); + metadata[RAW_OFFSET_U32_DURATION] = image->flags.duration; + metadata[RAW_OFFSET_U32_FLAGS] = (image->flags.overlapping ? RAW_FLAG_OVERLAP_PATH : 0) | extra_flags; +} + +#if VG_FEATURE_RAW_EXTERNAL + +static inline void _store_image_resource(vector_image_t* image, int32_t resource_size, SNIX_resource* resource) { + resource->data = (void*) image; + resource->size = resource_size; +} + +/* + * @brief Loads a RAW vector image from external memory + * + * The resource is opened from external memory if it exists. Its address, size and metadata are stored in the output parameters. + * If the resource exists in a byte-addressable area, the output address will be that of this memory area. + * Otherwise, a RAM area will be allocated on the MicroUI image heap, the resource will be copied into that area, and the output address will be that of the newly allocated memory area. + * In the latter case, metadata will contain a RAW_FLAG_FREE_MEMORY_ON_CLOSE. The caller is responsible for properly deallocating the memory. + * + * @param[in] image_name: name of the image to be opened + * @param[in] allocation_allowed: true to allow an allocation in the images heap, false when forbidden + * @param[out] resource: structure to save the address and size of the image + * @param[out] metadata: integer array to save the width, height, animation duration and flags of the image + * + * @return LLVG_SUCCESS on a successful loading, any other value on a failure. + */ +static int _load_external_image(char const* image_name, bool allocation_allowed, SNIX_resource* resource, jint* metadata) { + int result = LLVG_SUCCESS; + + // Ignore the leading '/' in the path. + char const* image_external_path = image_name; + image_external_path ++; + + // Open the resource matching the provided path. + RES_ID resource_id = LLEXT_RES_open(image_external_path); + if (0 > resource_id) { + result = LLVG_DATA_INVALID_PATH; + } + else { + // Retrieve the address and size of the resource. + int32_t resource_size = LLEXT_RES_available(resource_id); + int32_t base_address = LLEXT_RES_getBaseAddress(resource_id); + + vector_image_t* image = NULL; + + // Initialize the library (if needed) + _initialize(); + + if (-1 != base_address) { + // The resource is located in a byte-addressable memory area. This will be the output address. + // cppcheck-suppress [misra-c2012-11.4] base_address is a vector_image_t for sure + image = (vector_image_t*) base_address; + + // Put the address, size and metadata in the ouptut parameters. + _store_image_resource(image, resource_size, resource); + + result = LLVG_SUCCESS; + } + else if (!allocation_allowed) { + // image is available but required a copy in the images heap + result = LLVG_DATA_INVALID_PATH; + } + else { + // The resource is located in a memory area that cannot be byte-addressed. + + // Allocate memory on the MicroUI image heap to store the image. Its address will be the output address. + image = (vector_image_t*) LLUI_DISPLAY_IMPL_imageHeapAllocate(resource_size); + if (NULL == image) { + // Out of memory. + result = LLVG_OUT_OF_MEMORY; + } + else { + // Copy the image from the external memory into the allocated area. + if (LLEXT_RES_OK != LLEXT_RES_read(resource_id, (void*) image, &resource_size)) { + result = LLVG_DATA_INVALID; + } + else if (!_is_raw_image((uint8_t*)image)){ + // it is not a RAW image -> free it + LLUI_DISPLAY_IMPL_imageHeapFree((uint8_t* )image); + result = LLVG_DATA_INVALID; + } + else { + /* Put the address, size and metadata in the ouptut parameters. + * RAW_FLAG_FREE_MEMORY_ON_CLOSE flags the image as requiring to be deallocated. + */ + _store_image_resource(image, resource_size, resource); + _store_image_metadata(image, RAW_FLAG_FREE_MEMORY_ON_CLOSE, metadata); + _tag_image_in_ram(image); + + result = LLVG_SUCCESS; + } + } + } + + // Close the resource. + LLEXT_RES_close(resource_id); + } + + return result; +} + +#endif // VG_FEATURE_RAW_EXTERNAL + +// ----------------------------------------------------------------------------- +// BufferedVectorImage (BVI) Management +// ----------------------------------------------------------------------------- + +#if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +void BVI_VGLITE_adjust_new_image_characteristics(uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment) { + (void)width; + (void)height; + (void)data_alignment; + *data_size += sizeof(vector_buffered_image_t); +} + +void BVI_VGLITE_initialize_new_image(MICROUI_Image* image) { + + _initialize(); + + vector_buffered_image_t* bvi = MAP_BVI_ON_IMAGE(image); + + bvi->header.width = (float)image->width; + bvi->header.height = (float)image->height; + bvi->header.flags.duration = 0; + bvi->header.flags.overlapping = 0; + bvi->header.first_block = &(bvi->last_block); + + bvi->last_block.kind = VG_BLOCK_LAST; + bvi->latest_data = NULL; // very first block + bvi->last_stored_gradient = NULL; + + // cppcheck-suppress [misra-c2012-11.3] bvi is a vector_image_t for sure + vector_image_t* raw = (vector_image_t*)bvi; + _tag_image_in_ram(raw); + _bvi_tag_image_as_absolute(raw); +} + +void BVI_VGLITE_free_resources(MICROUI_Image* image) { + (void)_bvi_clear_blocks(MAP_BVI_ON_IMAGE(image)); +} + +jint BVI_VGLITE_add_draw_path( + void* target, + vg_lite_path_t * path, + vg_lite_fill_t fill_rule, + vg_lite_matrix_t * matrix, + vg_lite_blend_t blend, + vg_lite_color_t color) { + + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_bvi_color_t for sure + vg_block_bvi_color_t* op = (vg_block_bvi_color_t*)_alloc_data(sizeof(vg_block_bvi_color_t)); + jint ret = LLVG_OUT_OF_MEMORY; + + if (NULL != op) { + vector_buffered_image_t* image = _bvi_get_bvi_from_target(target); + + op->header.path.block.kind = VG_BLOCK_BVI_COLOR; + op->header.path.fill_rule = fill_rule; + op->header.path.blend = blend; + op->header.path.desc = _bvi_store_vglite_path(path); + op->header.color = (uint32_t)color; + _bvi_save_current_vglite_scissor(op->scissor); + (void)memcpy((void*)&(op->path_deformation), (void*)matrix, sizeof(vg_lite_matrix_t)); + + // cppcheck-suppress [misra-c2012-11.3] operation is a vg_block_t + ret = _bvi_link_operations(image, (vg_block_t*)op, &(op->next), (NULL == op->header.path.desc)); + } + + return ret; +} + +jint BVI_VGLITE_add_draw_gradient( + void* target, + vg_lite_path_t * path, + vg_lite_fill_t fill_rule, + vg_lite_matrix_t * matrix, + vg_lite_linear_gradient_t * grad, + vg_lite_blend_t blend) { + + // cppcheck-suppress [misra-c2012-11.3] block is a vg_block_bvi_gradient_t for sure + vg_block_bvi_gradient_t* op = (vg_block_bvi_gradient_t*)_alloc_data(sizeof(vg_block_bvi_gradient_t)); + jint ret = LLVG_OUT_OF_MEMORY; + + if (NULL != op) { + vector_buffered_image_t* image = _bvi_get_bvi_from_target(target); + + op->header.path.block.kind = VG_BLOCK_BVI_GRADIENT; + op->header.path.fill_rule = fill_rule; + op->header.path.blend = blend; + op->header.path.desc = _bvi_store_vglite_path(path); + + if ((NULL != image->last_stored_gradient) && (0 == memcmp(grad, image->last_stored_gradient, GRADIENT_COPY_SIZE))) { + // the both gradient operations use the same gradient + // -> second operation can link the gradient of first operation + op->header.gradient = image->last_stored_gradient; + op->shared_gradient = true; // do not free it! + } + else { + op->header.gradient = _bvi_store_vglite_gradient(grad); + op->shared_gradient = false; // have to free it + image->last_stored_gradient = op->header.gradient; + } + + _bvi_save_current_vglite_scissor(op->scissor); + (void)memcpy((void*)&(op->path_deformation), (void*)matrix, sizeof(vg_lite_matrix_t)); + + // cppcheck-suppress [misra-c2012-11.3] operation is a vg_block_t + ret = _bvi_link_operations(image, (vg_block_t*)op, &(op->next), ((NULL == op->header.path.desc) || (NULL == op->header.gradient))); + } + + return ret; +} + +jint BVI_VGLITE_add_draw_image(void* target, void* sni_context, jfloat* drawing_matrix, jint alpha, jlong elapsed, const float color_matrix[]){ + + // cppcheck-suppress [misra-c2012-11.5] sni_context is a vector image for sure + vector_image_t* image = (vector_image_t*)((SNIX_resource*)sni_context)->data; + jint ret; + + if (_bvi_is_image_in_rom(image)) { + // no need to parse the image: just add a block in the BVI + vector_buffered_image_t* dest = _bvi_get_bvi_from_target(target); + ret = _bvi_add_draw_raw_image(dest, image, drawing_matrix, alpha, elapsed, color_matrix); + } + else { + // have to copy all image elements in the destination (== a bvi) + // if the source image holds a RAW image block (points to a RAW image), each element of this + // RAW image is drawn in the destination. + + _get_image_parameters(image, &drawing_data); + bvi_target = target; + ret = _draw_raw_image(&drawing_data, &_bvi_add_image_element, drawing_matrix, alpha, elapsed, color_matrix); + + /* + * When the target is a BufferedVectorImage, the data of render_gradient has been updated but not the VGLite image + * (it is useless and time consuming). However the image may be required later (if the new drawing's gradient data + * is equal to the stored gradient data). In this case, the VGLite image will be out of date (not synchronized with + * the gradient data) but will not be updated. + * A simple solution consists to ensure that next gradient comparison will fail. + */ + (void)memset(&render_gradient, 0, GRADIENT_CMP_SIZE); + } + + return ret; +} + +void LLVG_BVI_IMPL_map_context(MICROUI_Image* ui, void* sni_context) { + // cppcheck-suppress [misra-c2012-11.5] sni_context is a SNIX_resource for sure + SNIX_resource* vg = (SNIX_resource*)sni_context; + vg->data = (void*)MAP_BVI_ON_IMAGE(ui); + vg->size = sizeof(vector_buffered_image_t); +} + +void LLVG_BVI_IMPL_clear(MICROUI_GraphicsContext* gc) { + + if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLVG_BVI_IMPL_clear)) { + + // map a struct on graphics context's pixel area + vector_buffered_image_t* image = MAP_BVI_ON_GC(gc); + + image->header.first_block = _bvi_clear_blocks(image); // reset first block + image->latest_data = NULL; // reset to identify the very first block + + LLUI_DISPLAY_setDrawingStatus(DRAWING_DONE); + } +} + +#endif // #if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +// ----------------------------------------------------------------------------- +// Java library natives +// ----------------------------------------------------------------------------- + +void VG_DRAWING_get_image_size(void* sni_context, float* width, float* height) { + // cppcheck-suppress [misra-c2012-11.5] data is a vector image for sure + vector_image_t* image = (vector_image_t*)((SNIX_resource*)sni_context)->data; + *width = image->width; + *height = image->height; +} + +jint Java_ej_microvg_VectorGraphicsNatives_getImage(char* path, jint path_length, SNIX_resource* res, jint* metadata) { + + LOG_MICROVG_IMAGE_START(load); + + (void)path_length; + + _initialize(); + + jint ret; + int32_t sni_ret = SNIX_get_resource(path, res); + +#if VG_FEATURE_RAW_EXTERNAL + // image not found in the application resource list + if ((sni_ret < 0) && (LLVG_SUCCESS == _load_external_image(path, false, res, metadata))) { + // image found available in external memory which is byte addressable + sni_ret = 0; + } +#endif // VG_FEATURE_RAW_EXTERNAL + + if (sni_ret < 0) { + ret = LLVG_DATA_INVALID_PATH; + } + // cppcheck-suppress [misra-c2012-11.5] cast the resource in a u8 address + else if (!_is_raw_image((uint8_t*)res->data)) { + ret = LLVG_DATA_INVALID; + } + else { + + // cppcheck-suppress [misra-c2012-11.5] resource is a vector image for sure + vector_image_t* image = (vector_image_t*)res->data; + + // metadata used by the Java library during image opening + _store_image_metadata(image, 0, metadata); + + ret = LLVG_SUCCESS; + } + + LOG_MICROVG_IMAGE_END(load); + return ret; +} + +jint Java_ej_microvg_VectorGraphicsNatives_loadImage(char* path, jint path_length, SNIX_resource* res, jint* metadata) { + jint result = Java_ej_microvg_VectorGraphicsNatives_getImage(path, path_length, res, metadata); + +#if VG_FEATURE_RAW_EXTERNAL + if (LLVG_DATA_INVALID_PATH == result) { + // try to load a non-byte addressable image (copy in ui heap) + result = _load_external_image(path, true, res, metadata); + } +#endif + + return result; +} + +jint VG_DRAWING_VGLITE_draw_image(VG_DRAWING_VGLITE_draw_image_element_t drawer, void* sni_context, jfloat* drawing_matrix, jint alpha, jlong elapsed, const float color_matrix[], bool* rendered){ + // cppcheck-suppress [misra-c2012-11.5] sni_context is a vector image for sure + vector_image_t* image = (vector_image_t*)((SNIX_resource*)sni_context)->data; + _get_image_parameters(image, &drawing_data); + jint error = _draw_raw_image(&drawing_data, drawer, drawing_matrix, alpha, elapsed, color_matrix); + *rendered = (LLVG_SUCCESS == error) && drawing_data.drawing_running; + return error; +} + +jint Java_ej_microvg_VectorGraphicsNatives_createImage(SNIX_resource* source, SNIX_resource* dest, const float color_matrix[]) { + + LOG_MICROVG_IMAGE_START(create); + + // cppcheck-suppress [misra-c2012-11.5] source is a vector image for sure + vector_image_t* image = (vector_image_t*)source->data; + + // the source is a RAW image (in ROM or RAM) but not a BVI (see BufferedVectorImage.filterImage()) + assert(!_is_image_bvi(image)); + + dest->data = (void*)LLUI_DISPLAY_IMPL_imageHeapAllocate(source->size); + jint ret; + + if (NULL != dest->data){ + (void)memcpy(dest->data, source->data, source->size); + dest->size = source->size; + + // cppcheck-suppress [misra-c2012-11.5] destination is a vector image for sure + image = (vector_image_t*)dest->data; + _tag_image_in_ram(image); + + _get_image_parameters(image, &drawing_data); + _derive_raw_image(&drawing_data, color_matrix); + + ret = LLVG_SUCCESS; + } + else { + ret = LLVG_OUT_OF_MEMORY; + } + + LOG_MICROVG_IMAGE_END(create); + return ret; +} + +void Java_ej_microvg_VectorGraphicsNatives_closeImage(SNIX_resource* res) { + if ((NULL != res) && (NULL != res->data) && ((uint32_t)0 < res->size)) { + + LOG_MICROVG_IMAGE_START(close); + + // cppcheck-suppress [misra-c2012-11.5] cast res->data as uint8_t* is allowed + if (_is_raw_image((uint8_t*)res->data)) { + // have to free to vector resource image data + // cppcheck-suppress [misra-c2012-11.5] cast the resource in a u8 address + LLUI_DISPLAY_IMPL_imageHeapFree((uint8_t* )res->data); + } + // else: it is an image allocated on the Java heap or in a BVI: nothing to free + + LOG_MICROVG_IMAGE_END(close); + + res->data = NULL; + res->size = 0; + } +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + diff --git a/bsp/projects/microej/vg/src/LLVG_impl.c b/bsp/projects/microej/vg/src/LLVG_impl.c new file mode 100644 index 0000000..3082ac4 --- /dev/null +++ b/bsp/projects/microej/vg/src/LLVG_impl.c @@ -0,0 +1,67 @@ +/* + * C + * + * Copyright 2022-2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/** + * @file + * @brief Initializes the MicroVG implementation. + * @author MicroEJ Developer Team + * @version 5.0.0 + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include +#include + +#include "microvg_configuration.h" +#include "microvg_helper.h" +#include "microvg_font_freetype.h" +#include "microvg_path.h" +#include "microvg_trace.h" + +// ----------------------------------------------------------------------------- +// Defines +// ----------------------------------------------------------------------------- + +#if (defined(LLVG_MAJOR_VERSION) && (LLVG_MAJOR_VERSION != 1)) || (defined(LLVG_MINOR_VERSION) && (LLVG_MINOR_VERSION < 3)) +#error "This CCO is only compatible with VG Pack [1.3.0,2.0.0[" +#endif + +// ----------------------------------------------------------------------------- +// Globals +// ----------------------------------------------------------------------------- + +/* + * microvg_trace.h logs group identifier + */ +int32_t vg_trace_group_id; + +// ----------------------------------------------------------------------------- +// LLVG_impl.h functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +void LLVG_IMPL_initialize(void) { + + vg_trace_group_id = LLTRACE_IMPL_declare_event_group("MicroVG", LOG_MICROVG_EVENTS); + + MICROVG_HELPER_initialize(); + +#if defined VG_FEATURE_FONT && \ + (defined VG_FEATURE_FONT_FREETYPE_VECTOR || defined VG_FEATURE_FONT_FREETYPE_BITMAP) && \ + (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_VECTOR || VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_BITMAP) + + MICROVG_FONT_FREETYPE_initialize(); +#endif + +#ifdef VG_FEATURE_PATH + MICROVG_PATH_initialize(); +#endif +} + diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_vglite.c b/bsp/projects/microej/vg/src/LLVG_vglite.c similarity index 83% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_vglite.c rename to bsp/projects/microej/vg/src/LLVG_vglite.c index cbb5fe7..67a507b 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_vglite.c +++ b/bsp/projects/microej/vg/src/LLVG_vglite.c @@ -1,15 +1,15 @@ /* * C * - * Copyright 2022 MicroEJ Corp. All rights reserved. + * Copyright 2022-2024 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ /** * @file - * @brief MicroVG library low level API over VG-Lite. + * @brief MicroVG library low level API over VGLite. * @author MicroEJ Developer Team - * @version 3.0.0 + * @version 7.0.1 */ // ----------------------------------------------------------------------------- @@ -28,7 +28,6 @@ #include "microvg_vglite_helper.h" #include "vg_lite.h" #include "color.h" -#include "display_vglite.h" #include "bsp_util.h" // ----------------------------------------------------------------------------- @@ -39,7 +38,6 @@ #error "This implementation is only compatible with VG_FEATURE_GRADIENT_FULL" #endif -#define ALPHA_SHIFT 24 #define VGLITE_GRADIENT_SIZE 256 // ----------------------------------------------------------------------------- @@ -135,6 +133,12 @@ vg_lite_blend_t MICROVG_VGLITE_HELPER_get_blend(jint blend) { case LLVG_BLEND_DST_IN: ret = VG_LITE_BLEND_DST_IN; break; + case LLVG_BLEND_DST_OUT: + ret = VG_LITE_BLEND_SUBTRACT; + break; + case LLVG_BLEND_PLUS: + ret = VG_LITE_BLEND_ADDITIVE; + break; case LLVG_BLEND_SCREEN: ret = VG_LITE_BLEND_SCREEN; break; @@ -145,27 +149,6 @@ vg_lite_blend_t MICROVG_VGLITE_HELPER_get_blend(jint blend) { return ret; } -// See the header file for the function documentation -bool MICROVG_VGLITE_HELPER_enable_vg_lite_scissor(MICROUI_GraphicsContext* gc) -{ - int32_t width = gc->clip_x2 - gc->clip_x1 + 1; - int32_t height = gc->clip_y2 - gc->clip_y1 + 1; - - bool ret; - if ((width > 0) && (height > 0)) - { - vg_lite_enable_scissor(); - vg_lite_set_scissor(gc->clip_x1, gc->clip_y1, width, height); - ret = true; - } - else { - // drawing is useless - LLUI_DISPLAY_setDrawingStatus(DRAWING_DONE); - ret = false; - } - return ret; -} - // ----------------------------------------------------------------------------- // microvg_gradient.h functions // ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/microvg_helper.c b/bsp/projects/microej/vg/src/microvg_helper.c similarity index 86% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/microvg_helper.c rename to bsp/projects/microej/vg/src/microvg_helper.c index 663e207..4b3c4a9 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/microvg_helper.c +++ b/bsp/projects/microej/vg/src/microvg_helper.c @@ -1,7 +1,7 @@ /* * C * - * Copyright 2022 MicroEJ Corp. All rights reserved. + * Copyright 2022-2023 MicroEJ Corp. All rights reserved. * Use of this source code is governed by a BSD-style license that can be found with this software. */ @@ -10,7 +10,7 @@ * @brief MicroEJ MicroVG library low level API: helper to implement library natives * methods. * @author MicroEJ Developer Team -* @version 2.0.0 +* @version 5.0.0 */ // ----------------------------------------------------------------------------- @@ -18,11 +18,14 @@ // ----------------------------------------------------------------------------- #include -#include #include "microvg_helper.h" #include "microvg_configuration.h" +#if defined VG_FEATURE_FONT +#include +#endif + // ----------------------------------------------------------------------------- // Configuration Sanity Check // ----------------------------------------------------------------------------- @@ -39,7 +42,7 @@ #error "Undefined MICROVG_CONFIGURATION_VERSION, it must be defined in microvg_configuration.h" #endif -#if defined MICROVG_CONFIGURATION_VERSION && MICROVG_CONFIGURATION_VERSION != 1 +#if defined MICROVG_CONFIGURATION_VERSION && MICROVG_CONFIGURATION_VERSION != 2 #error "Version of the configuration file microvg_configuration.h is not compatible with this implementation." #endif @@ -72,6 +75,7 @@ static jfloat g_identity_matrix[LLVG_MATRIX_SIZE]; +#if defined VG_FEATURE_FONT static FT_Face face; // Freetype layout variables @@ -79,6 +83,7 @@ static unsigned short *current_text; static unsigned int current_length; static int current_offset; static FT_UInt previous_glyph_index; // previous glyph index for kerning +#endif #if defined VG_FEATURE_FONT_COMPLEX_LAYOUT // Harfbuzz layout variables @@ -87,7 +92,7 @@ static hb_glyph_position_t *glyph_pos; static unsigned int glyph_count; static int current_glyph; static hb_buffer_t *buf; -#endif +#endif // ----------------------------------------------------------------------------- // Public functions // ----------------------------------------------------------------------------- @@ -101,34 +106,38 @@ void MICROVG_HELPER_initialize(void) { int MICROVG_HELPER_get_utf(unsigned short *textCharRam, int length, int *offset) { unsigned short highPart = GET_NEXT_CHARACTER(textCharRam, length, *offset); - int ret = 0; + int ret = 0; // means "error" (see doc) - if (((highPart >= MIN_HIGH_SURROGATE) && (highPart <= MAX_HIGH_SURROGATE)) - && (*offset < (length - 1))) { + if ((highPart >= MIN_HIGH_SURROGATE) && (highPart <= MAX_HIGH_SURROGATE)) { - unsigned short lowPart = GET_NEXT_CHARACTER(textCharRam, length, *(offset) + 1); + if (*offset < (length - 1)) { - if ((lowPart >= MIN_LOW_SURROGATE) && (lowPart <= MAX_LOW_SURROGATE)) { - *offset += 2; + unsigned short lowPart = GET_NEXT_CHARACTER(textCharRam, length, *(offset) + 1); - ret = 0; - ret += ((int)highPart - (int)MIN_HIGH_SURROGATE); - ret <<= (int)10; - ret += ((int)lowPart - (int)MIN_LOW_SURROGATE); - ret += (int)MIN_SUPPLEMENTARY_CODE_POINT; + if ((lowPart >= MIN_LOW_SURROGATE) && (lowPart <= MAX_LOW_SURROGATE)) { + *offset += 2; + + ret = 0; + ret += ((int)highPart - (int)MIN_HIGH_SURROGATE); + ret <<= (int)10; + ret += ((int)lowPart - (int)MIN_LOW_SURROGATE); + ret += (int)MIN_SUPPLEMENTARY_CODE_POINT; + } + // else: invalid surrogate pair } + // else: missing second part of surrogate pair } else { *offset += 1; - // standard character or missing low part + // standard character ret = 0x0000FFFF & (int)highPart; } return ret; } - +#if defined VG_FEATURE_FONT // See the header file for the function documentation void MICROVG_HELPER_layout_configure(int faceHandle, unsigned short *text, int length){ face = (FT_Face) faceHandle; @@ -172,7 +181,9 @@ void MICROVG_HELPER_layout_configure(int faceHandle, unsigned short *text, int l #endif // VG_FEATURE_FONT_COMPLEX_LAYOUT } } +#endif +#if defined VG_FEATURE_FONT // See the header file for the function documentation bool MICROVG_HELPER_layout_load_glyph(int *glyph_idx, int *x_advance, int *y_advance, int *x_offset, int *y_offset){ // Initiate return value with default values @@ -244,6 +255,7 @@ bool MICROVG_HELPER_layout_load_glyph(int *glyph_idx, int *x_advance, int *y_adv return ret; } +#endif // See the header file for the function documentation jfloat* MICROVG_HELPER_check_matrix(jfloat* matrix) { diff --git a/bsp/projects/microej/vg/src/vg_drawing.c b/bsp/projects/microej/vg/src/vg_drawing.c new file mode 100644 index 0000000..d6ca4bf --- /dev/null +++ b/bsp/projects/microej/vg/src/vg_drawing.c @@ -0,0 +1,363 @@ +/* + * C + * + * Copyright 2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief Redirection of all MicroVG library drawing functions. This file is required + * (must be compiled in the C project) but should not be modified (except when the VEE + * port uses more than 3 destination formats, see below). + * + * This file follows strictly the same concept as ui_drawing.c but for MicroVG + * library. + * + * @author MicroEJ Developer Team + * @version 5.0.0 + * @see ui_drawing.c + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include "vg_drawing.h" +#include "vg_drawing_stub.h" +#include "bsp_util.h" + +// -------------------------------------------------------------------------------- +// Defines +// -------------------------------------------------------------------------------- + +#if !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +/* + * The function VG_DRAWING_DEFAULT_xxx() are directly called by LLVG_PAINTER_impl.c + * Another file can override each weak function independently to use a GPU. + */ + +#define VG_DRAWING_DEFAULT_drawPath VG_DRAWING_drawPath +#define VG_DRAWING_DEFAULT_drawGradient VG_DRAWING_drawGradient +#define VG_DRAWING_DEFAULT_drawString VG_DRAWING_drawString +#define VG_DRAWING_DEFAULT_drawStringGradient VG_DRAWING_drawStringGradient +#define VG_DRAWING_DEFAULT_drawStringOnCircle VG_DRAWING_drawStringOnCircle +#define VG_DRAWING_DEFAULT_drawStringOnCircleGradient VG_DRAWING_drawStringOnCircleGradient +#define VG_DRAWING_DEFAULT_drawImage VG_DRAWING_drawImage + +#else // !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +/* + * The functions VG_DRAWING_DEFAULT_xxx() are indirectly called through some tables. + * The functions have got the identifier "0" as suffix. Another file can override + * each weak function independently to use a GPU. + */ + +#define VG_DRAWING_DEFAULT_drawPath VG_DRAWING_drawPath_0 +#define VG_DRAWING_DEFAULT_drawGradient VG_DRAWING_drawGradient_0 +#define VG_DRAWING_DEFAULT_drawString VG_DRAWING_drawString_0 +#define VG_DRAWING_DEFAULT_drawStringGradient VG_DRAWING_drawStringGradient_0 +#define VG_DRAWING_DEFAULT_drawStringOnCircle VG_DRAWING_drawStringOnCircle_0 +#define VG_DRAWING_DEFAULT_drawStringOnCircleGradient VG_DRAWING_drawStringOnCircleGradient_0 +#define VG_DRAWING_DEFAULT_drawImage VG_DRAWING_drawImage_0 + +#endif // !defined(LLUI_GC_SUPPORTED_FORMATS) || (LLUI_GC_SUPPORTED_FORMATS <= 1) + +// -------------------------------------------------------------------------------- +// Extern functions +// -------------------------------------------------------------------------------- + +#if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +/* + * @brief Set of drawing functions according to the index of the destination format in + * the drawing tables ("0", "1" or "2"). + * + * These functions must be declared in other H files. + */ + +#if (LLUI_GC_SUPPORTED_FORMATS > 3) +#error "Increase the number of following functions and update the next tables" +#endif + +extern DRAWING_Status VG_DRAWING_drawPath_0(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color); +extern DRAWING_Status VG_DRAWING_drawGradient_0(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradient, jfloat* gradientMatrix); +extern DRAWING_Status VG_DRAWING_drawString_0(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing); +extern DRAWING_Status VG_DRAWING_drawStringGradient_0(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix); +extern DRAWING_Status VG_DRAWING_drawStringOnCircle_0(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction); +extern DRAWING_Status VG_DRAWING_drawStringOnCircleGradient_0(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix); +extern DRAWING_Status VG_DRAWING_drawImage_0(MICROUI_GraphicsContext* gc, void* image, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno); + +extern DRAWING_Status VG_DRAWING_drawPath_1(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color); +extern DRAWING_Status VG_DRAWING_drawGradient_1(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradient, jfloat* gradientMatrix); +extern DRAWING_Status VG_DRAWING_drawString_1(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing); +extern DRAWING_Status VG_DRAWING_drawStringGradient_1(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix); +extern DRAWING_Status VG_DRAWING_drawStringOnCircle_1(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction); +extern DRAWING_Status VG_DRAWING_drawStringOnCircleGradient_1(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix); +extern DRAWING_Status VG_DRAWING_drawImage_1(MICROUI_GraphicsContext* gc, void* image, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno); + +#if (LLUI_GC_SUPPORTED_FORMATS > 2) +extern DRAWING_Status VG_DRAWING_drawPath_2(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color); +extern DRAWING_Status VG_DRAWING_drawGradient_2(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradient, jfloat* gradientMatrix); +extern DRAWING_Status VG_DRAWING_drawString_2(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing); +extern DRAWING_Status VG_DRAWING_drawStringGradient_2(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix); +extern DRAWING_Status VG_DRAWING_drawStringOnCircle_2(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction); +extern DRAWING_Status VG_DRAWING_drawStringOnCircleGradient_2(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix); +extern DRAWING_Status VG_DRAWING_drawImage_2(MICROUI_GraphicsContext* gc, void* image, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno); +#endif // (LLUI_GC_SUPPORTED_FORMATS > 2) + +#endif // defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +// -------------------------------------------------------------------------------- +// Typedef of drawing functions +// -------------------------------------------------------------------------------- + +#if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +/* + * @brief Typedef used by next tables. See the functions comments in vg_drawing.h + */ + +typedef DRAWING_Status (* VG_DRAWING_drawPath_t) (MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color); +typedef DRAWING_Status (* VG_DRAWING_drawGradient_t) (MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradient, jfloat* gradientMatrix); +typedef DRAWING_Status (* VG_DRAWING_drawString_t) (MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing); +typedef DRAWING_Status (* VG_DRAWING_drawStringGradient_t) (MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix); +typedef DRAWING_Status (* VG_DRAWING_drawStringOnCircle_t) (MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction); +typedef DRAWING_Status (* VG_DRAWING_drawStringOnCircleGradient_t) (MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix); +typedef DRAWING_Status (* VG_DRAWING_drawImage_t) (MICROUI_GraphicsContext* gc, void* image, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno); + +#endif // #if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + + +// -------------------------------------------------------------------------------- +// Tables according to the destination format. +// -------------------------------------------------------------------------------- + +#if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +static const VG_DRAWING_drawPath_t VG_DRAWER_drawPath[] = { + &VG_DRAWING_drawPath_0, + &VG_DRAWING_drawPath_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &VG_DRAWING_drawPath_2, +#endif +}; + +static const VG_DRAWING_drawGradient_t VG_DRAWER_drawGradient[] = { + &VG_DRAWING_drawGradient_0, + &VG_DRAWING_drawGradient_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &VG_DRAWING_drawGradient_2, +#endif +}; + +static const VG_DRAWING_drawString_t VG_DRAWER_drawString[] = { + &VG_DRAWING_drawString_0, + &VG_DRAWING_drawString_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &VG_DRAWING_drawString_2, +#endif +}; + +static const VG_DRAWING_drawStringGradient_t VG_DRAWER_drawStringGradient[] = { + &VG_DRAWING_drawStringGradient_0, + &VG_DRAWING_drawStringGradient_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &VG_DRAWING_drawStringGradient_2, +#endif +}; + +static const VG_DRAWING_drawStringOnCircle_t VG_DRAWER_drawStringOnCircle[] = { + &VG_DRAWING_drawStringOnCircle_0, + &VG_DRAWING_drawStringOnCircle_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &VG_DRAWING_drawStringOnCircle_2, +#endif +}; + +static const VG_DRAWING_drawStringOnCircleGradient_t VG_DRAWER_drawStringOnCircleGradient[] = { + &VG_DRAWING_drawStringOnCircleGradient_0, + &VG_DRAWING_drawStringOnCircleGradient_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &VG_DRAWING_drawStringOnCircleGradient_2, +#endif +}; + +static const VG_DRAWING_drawImage_t VG_DRAWER_drawImage[] = { + &VG_DRAWING_drawImage_0, + &VG_DRAWING_drawImage_1, +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + &VG_DRAWING_drawImage_2, +#endif +}; + +#endif + +// -------------------------------------------------------------------------------- +// vg_drawing.h functions +// (the function names differ according to the available number of destination formats) +// -------------------------------------------------------------------------------- + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_DEFAULT_drawPath(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color){ + return VG_DRAWING_STUB_drawPath(gc, path, x, y, matrix, fillRule, blend, color); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_DEFAULT_drawGradient(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradient, jfloat* gradientMatrix){ + return VG_DRAWING_STUB_drawGradient(gc, path, x, y, matrix, fillRule, alpha, blend, gradient, gradientMatrix); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_DEFAULT_drawString(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing){ + return VG_DRAWING_STUB_drawString(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_DEFAULT_drawStringGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix){ + return VG_DRAWING_STUB_drawStringGradient(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, gradientData, gradientMatrix); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_DEFAULT_drawStringOnCircle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction){ + return VG_DRAWING_STUB_drawStringOnCircle(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, radius, direction); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_DEFAULT_drawStringOnCircleGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix){ + return VG_DRAWING_STUB_drawStringOnCircleGradient(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, radius, direction, gradientData, gradientMatrix); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_DEFAULT_drawImage(MICROUI_GraphicsContext* gc, void* sni_context, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno) { + return VG_DRAWING_STUB_drawImage(gc, sni_context, matrix, alpha, elapsed, color_matrix, errno); +} + +#if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +/* + * The VEE port supports several destination formats. All drawing functions use a + * dedicated table to redirect to the right implementation. + * + * The "DEFAULT" functions (see upper) are used as element "0" of the tables (== display + * buffer format). + */ + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT inline DRAWING_Status VG_DRAWING_drawPath(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color){ + return (*VG_DRAWER_drawPath[gc->drawer])(gc, path, x, y, matrix, fillRule, blend, color); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT inline DRAWING_Status VG_DRAWING_drawGradient(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradient, jfloat* gradientMatrix){ + return (*VG_DRAWER_drawGradient[gc->drawer])(gc, path, x, y, matrix, fillRule, alpha, blend, gradient, gradientMatrix); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawString(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing){ + return (*VG_DRAWER_drawString[gc->drawer])(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawStringGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix){ + return (*VG_DRAWER_drawStringGradient[gc->drawer])(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, gradientData, gradientMatrix); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawStringOnCircle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction){ + return (*VG_DRAWER_drawStringOnCircle[gc->drawer])(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, radius, direction); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawStringOnCircleGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix){ + return (*VG_DRAWER_drawStringOnCircleGradient[gc->drawer])(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, radius, direction, gradientData, gradientMatrix); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT inline DRAWING_Status VG_DRAWING_drawImage(MICROUI_GraphicsContext* gc, void* image, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno) { + return (*VG_DRAWER_drawImage[gc->drawer])(gc, image, matrix, alpha, elapsed, color_matrix, errno); +} + +/* + * The next functions are used as elements "1" of the tables. They call STUB functions and should be + * overridden by the drawer that manages the format "1". + */ + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawPath_1(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color){ + return VG_DRAWING_STUB_drawPath(gc, path, x, y, matrix, fillRule, blend, color); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawGradient_1(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradient, jfloat* gradientMatrix){ + return VG_DRAWING_STUB_drawGradient(gc, path, x, y, matrix, fillRule, alpha, blend, gradient, gradientMatrix); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawString_1(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing){ + return VG_DRAWING_STUB_drawString(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawStringGradient_1(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix){ + return VG_DRAWING_STUB_drawStringGradient(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, gradientData, gradientMatrix); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawStringOnCircle_1(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction){ + return VG_DRAWING_STUB_drawStringOnCircle(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, radius, direction); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawStringOnCircleGradient_1(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix){ + return VG_DRAWING_STUB_drawStringOnCircleGradient(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, radius, direction, gradientData, gradientMatrix); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawImage_1(MICROUI_GraphicsContext* gc, void* sni_context, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno) { + return VG_DRAWING_STUB_drawImage(gc, sni_context, matrix, alpha, elapsed, color_matrix, errno); +} + + +#if (LLUI_GC_SUPPORTED_FORMATS > 2) + +/* + * The next functions are used as elements "2" of the tables. They call STUB functions and should be + * overridden by the drawer that manages the format "2". + */ + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawPath_2(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color){ + return VG_DRAWING_STUB_drawPath(gc, path, x, y, matrix, fillRule, blend, color); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawGradient_2(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradient, jfloat* gradientMatrix){ + return VG_DRAWING_STUB_drawGradient(gc, path, x, y, matrix, fillRule, alpha, blend, gradient, gradientMatrix); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawString_2(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing){ + return VG_DRAWING_STUB_drawString(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawStringGradient_2(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix){ + return VG_DRAWING_STUB_drawStringGradient(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, gradientData, gradientMatrix); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawStringOnCircle_2(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction){ + return VG_DRAWING_STUB_drawStringOnCircle(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, radius, direction); +} + +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawStringOnCircleGradient_2(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix){ + return VG_DRAWING_STUB_drawStringOnCircleGradient(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, radius, direction, gradientData, gradientMatrix); +} + +// See the header file for the function documentation +BSP_DECLARE_WEAK_FCNT DRAWING_Status VG_DRAWING_drawImage_2(MICROUI_GraphicsContext* gc, void* sni_context, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno) { + return VG_DRAWING_STUB_drawImage(gc, sni_context, matrix, alpha, elapsed, color_matrix, errno); +} + +#endif // (LLUI_GC_SUPPORTED_FORMATS > 2) + +#else // #if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +/* + * The VEE port supports only one destination format: the display buffer format. All + * drawing functions are redirected to the stub implementation by default. A + * third party implementation (often on a GPU) should replace each weak function independently. + */ + +#endif // #if defined(LLUI_GC_SUPPORTED_FORMATS) && (LLUI_GC_SUPPORTED_FORMATS > 1) + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- diff --git a/bsp/projects/microej/vg/src/vg_drawing_bvi.c b/bsp/projects/microej/vg/src/vg_drawing_bvi.c new file mode 100644 index 0000000..e96fe8f --- /dev/null +++ b/bsp/projects/microej/vg/src/vg_drawing_bvi.c @@ -0,0 +1,222 @@ +/* + * C + * + * Copyright 2023-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/** + * @file + * @brief Implementation of a set of vg_drawing.h drawing functions (library MicroVG). + * These are implementations over VGLite and the destination buffer format is the BufferedVectorImage + * format (VEE Port specific). When the drawing cannot be performed by the GPU, the stub implementation + * is used insted. + * + * Like vg_drawing_vglite.c, this file redirects the drawings of the strings and the images to some + * third-party files. These files don't perform the drawing themselves and let the caller do it. The + * drawing function is specified by vg_drawing_bvi.c to target BufferedVectorImage buffer. + * + * @author MicroEJ Developer Team + * @version 7.0.1 + * @see vg_drawing_vglite.c + * @see ui_drawing_bvi.c + */ + +#include "microvg_configuration.h" +#if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include "vg_drawing_bvi.h" +#include "bvi_vglite.h" +#include "ui_vglite.h" +#include "vg_drawing_vglite.h" +#include "microvg_helper.h" +#include "microvg_vglite_helper.h" + +// ----------------------------------------------------------------------------- +// Private globals +// ----------------------------------------------------------------------------- + +/** + * @brief Current BufferedVectorImage to update + */ +static void* target; + +// ----------------------------------------------------------------------------- +// Private functions +// ----------------------------------------------------------------------------- + +// VG_DRAWING_VGLITE_draw_glyph_t +static jint _add_glyph_color(vg_lite_path_t * path, vg_lite_fill_t fill_rule, vg_lite_matrix_t * matrix, vg_lite_blend_t blend, vg_lite_color_t color, vg_lite_linear_gradient_t * grad) { + (void)grad; + return BVI_VGLITE_add_draw_path(target, path, fill_rule, matrix, blend, color); +} + +// VG_DRAWING_VGLITE_draw_glyph_t +static jint _add_glyph_gradient(vg_lite_path_t * path, vg_lite_fill_t fill_rule, vg_lite_matrix_t * matrix, vg_lite_blend_t blend, vg_lite_color_t color, vg_lite_linear_gradient_t * grad) { + (void)color; + return BVI_VGLITE_add_draw_gradient(target, path, fill_rule, matrix, grad, blend); +} + +static DRAWING_Status _draw_string_on_circle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction){ + + if (UI_VGLITE_enable_vg_lite_scissor(gc)) { + + // prepare matrix + vg_lite_matrix_t vglite_matrix; + VG_DRAWING_VGLITE_prepare_matrix(&vglite_matrix, x, y, matrix); + + // prepare color + vg_lite_blend_t vglite_blend = MICROVG_VGLITE_HELPER_get_blend(blend); + vg_lite_color_t vglite_color = (vg_lite_color_t)((gc->foreground_color & 0x00FFFFFF) + (int)(((unsigned int) alpha) << 24)); + + // add operation + bool rendered; + target = MAP_BVI_ON_GC(gc); + jint error = VG_DRAWING_VGLITE_draw_string(&_add_glyph_color, text, faceHandle, size, &vglite_matrix, vglite_blend, vglite_color, MICROVG_HELPER_NULL_GRADIENT, letterSpacing, radius, direction, &rendered); + MICROVG_VGLITE_handle_error(gc, error); + } + // else no error: the drawing is just "not performed" + + return DRAWING_DONE; +} + +static DRAWING_Status _draw_string_on_circle_gradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix){ + DRAWING_Status ret = DRAWING_DONE; + + if (UI_VGLITE_enable_vg_lite_scissor(gc)) { + + // prepare matrix + vg_lite_matrix_t vglite_matrix; + VG_DRAWING_VGLITE_prepare_matrix(&vglite_matrix, x, y, matrix); + + // parepare gradient + vg_lite_blend_t vglite_blend = MICROVG_VGLITE_HELPER_get_blend(blend); + vg_lite_linear_gradient_t vglite_gradient; + vg_lite_error_t vglite_error = VG_DRAWING_VGLITE_prepare_gradient(&vglite_gradient, gradientData, gradientMatrix, &vglite_matrix, alpha); + + if (VG_LITE_SUCCESS == vglite_error) { + + // add operation + bool rendered; + target = MAP_BVI_ON_GC(gc); + jint error = VG_DRAWING_VGLITE_draw_string(&_add_glyph_gradient, text, faceHandle, size, &vglite_matrix, vglite_blend, 0, &vglite_gradient, letterSpacing, radius, direction, &rendered); + MICROVG_VGLITE_handle_error(gc, error); + + // post operation + VG_DRAWING_VGLITE_clear_gradient(&vglite_gradient); + } + else { + ret = UI_VGLITE_report_vglite_error(gc, vglite_error); + } + } + // else no error: the drawing is just "not performed" + + return ret; +} + +// -------------------------------------------------------------------------------- +// vg_drawing_bvi.h functions +// (the function names differ according to the index of destination format) +// -------------------------------------------------------------------------------- + +// See the header file for the function documentation +DRAWING_Status VG_DRAWING_BVI_drawPath(MICROUI_GraphicsContext* gc, jbyte* pathData, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color) { + + if (UI_VGLITE_enable_vg_lite_scissor(gc)) { + + // prepare path + vg_lite_path_t* vglite_path = VG_DRAWING_VGLITE_to_vglite_path((MICROVG_PATH_HEADER_t*)pathData); + vg_lite_blend_t vglite_blend = MICROVG_VGLITE_HELPER_get_blend(blend); + vg_lite_fill_t vglite_fill = MICROVG_VGLITE_HELPER_get_fill_rule(fillRule); + + // prepare matrix + vg_lite_matrix_t vglite_matrix; + VG_DRAWING_VGLITE_prepare_matrix(&vglite_matrix, x, y, matrix); + + // add operation + jint ret = BVI_VGLITE_add_draw_path(MAP_BVI_ON_GC(gc), vglite_path, vglite_fill, &vglite_matrix, vglite_blend, (vg_lite_color_t)color); + MICROVG_VGLITE_handle_error(gc, ret); + } + // else no error: the drawing is just "not performed" + + return DRAWING_DONE; +} + +// See the header file for the function documentation +DRAWING_Status VG_DRAWING_BVI_drawGradient(MICROUI_GraphicsContext* gc, jbyte* pathData, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradientData, jfloat* gradientMatrix){ + + if (UI_VGLITE_enable_vg_lite_scissor(gc)) { + + // prepare path + vg_lite_path_t* vglite_path = VG_DRAWING_VGLITE_to_vglite_path((MICROVG_PATH_HEADER_t*)pathData); + vg_lite_blend_t vglite_blend = MICROVG_VGLITE_HELPER_get_blend(blend); + vg_lite_fill_t vglite_fill = MICROVG_VGLITE_HELPER_get_fill_rule(fillRule); + + // prepare matrix + vg_lite_matrix_t vglite_matrix; + VG_DRAWING_VGLITE_prepare_matrix(&vglite_matrix, x, y, matrix); + + // parepare gradient + vg_lite_linear_gradient_t vglite_gradient; + vg_lite_error_t vglite_error = VG_DRAWING_VGLITE_prepare_gradient(&vglite_gradient, gradientData, gradientMatrix, &vglite_matrix, alpha); + + if (VG_LITE_SUCCESS == vglite_error) { + + // add operation + jint ret = BVI_VGLITE_add_draw_gradient(MAP_BVI_ON_GC(gc), vglite_path, vglite_fill, &vglite_matrix, &vglite_gradient, vglite_blend); + MICROVG_VGLITE_handle_error(gc, ret); + + // post operation + VG_DRAWING_VGLITE_clear_gradient(&vglite_gradient); + } + else { + UI_VGLITE_report_vglite_error(gc, vglite_error); + } + + } + // else no error: the drawing is just "not performed" + + return DRAWING_DONE; +} + +DRAWING_Status VG_DRAWING_BVI_drawString(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing){ + return _draw_string_on_circle(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, (jfloat)0, (jint)0); +} + +DRAWING_Status VG_DRAWING_BVI_drawStringGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix){ + return _draw_string_on_circle_gradient(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, (jfloat)0, (jint)0, gradientData, gradientMatrix); +} + +DRAWING_Status VG_DRAWING_BVI_drawStringOnCircle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction){ + return _draw_string_on_circle(gc, text, faceHandle, size, (jfloat)x, (jfloat)y, matrix, alpha, blend, letterSpacing, radius, direction); +} + +DRAWING_Status VG_DRAWING_BVI_drawStringOnCircleGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix){ + return _draw_string_on_circle_gradient(gc, text, faceHandle, size, (jfloat)x, (jfloat)y, matrix, alpha, blend, letterSpacing, radius, direction, gradientData, gradientMatrix); +} + +DRAWING_Status VG_DRAWING_BVI_drawImage(MICROUI_GraphicsContext* gc, void* image, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno){ + + float width; + float height; + VG_DRAWING_get_image_size(image, &width, &height); + + if (UI_VGLITE_enable_vg_lite_scissor_area(gc, width, height, matrix)) { + *errno = BVI_VGLITE_add_draw_image(MAP_BVI_ON_GC(gc), image, matrix, alpha, elapsed, color_matrix); + MICROVG_VGLITE_handle_error(gc, *errno); + } + // nothing to draw + + return DRAWING_DONE; +} + + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- + +#endif // #if defined VG_FEATURE_BUFFERED_VECTOR_IMAGE diff --git a/bsp/projects/microej/vg/src/vg_drawing_stub.c b/bsp/projects/microej/vg/src/vg_drawing_stub.c new file mode 100644 index 0000000..4e619c8 --- /dev/null +++ b/bsp/projects/microej/vg/src/vg_drawing_stub.c @@ -0,0 +1,140 @@ +/* + * C + * + * Copyright 2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * @file + * @brief + * @brief Implementation of all drawing functions of vg_drawing_stub.h. + * @author MicroEJ Developer Team + * @version 5.0.0 + * @see vg_drawing_stub.h + */ + +// -------------------------------------------------------------------------------- +// Includes +// -------------------------------------------------------------------------------- + +#include "vg_drawing_stub.h" + +// -------------------------------------------------------------------------------- +// Private functions +// -------------------------------------------------------------------------------- + +static inline DRAWING_Status not_implemented(MICROUI_GraphicsContext* gc){ + LLUI_DISPLAY_reportError(gc, DRAWING_LOG_NOT_IMPLEMENTED); + return DRAWING_DONE; +} + +// -------------------------------------------------------------------------------- +// vg_drawing_stub.h functions +// -------------------------------------------------------------------------------- + +// See the header file for the function documentation +DRAWING_Status VG_DRAWING_STUB_drawPath(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color){ + (void)gc; + (void)path; + (void)x; + (void)y; + (void)matrix; + (void)fillRule; + (void)blend; + (void)color; + return not_implemented(gc); +} + +DRAWING_Status VG_DRAWING_STUB_drawGradient(MICROUI_GraphicsContext* gc, jbyte* path, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradient, jfloat* gradientMatrix){ + (void)gc; + (void)path; + (void)x; + (void)y; + (void)matrix; + (void)fillRule; + (void)alpha; + (void)blend; + (void)gradient; + (void)gradientMatrix; + return not_implemented(gc); +} + +DRAWING_Status VG_DRAWING_STUB_drawString(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing){ + (void)gc; + (void)text; + (void)faceHandle; + (void)size; + (void)x; + (void)y; + (void)matrix; + (void)alpha; + (void)blend; + (void)letterSpacing; + return not_implemented(gc); +} + +DRAWING_Status VG_DRAWING_STUB_drawStringGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix){ + (void)gc; + (void)text; + (void)faceHandle; + (void)size; + (void)x; + (void)y; + (void)matrix; + (void)alpha; + (void)blend; + (void)letterSpacing; + (void)*gradientData; + (void)*gradientMatrix; + return not_implemented(gc); +} + +DRAWING_Status VG_DRAWING_STUB_drawStringOnCircle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction){ + (void)gc; + (void)text; + (void)faceHandle; + (void)size; + (void)x; + (void)y; + (void)matrix; + (void)alpha; + (void)blend; + (void)letterSpacing; + (void)radius; + (void)direction; + return not_implemented(gc); +} + +DRAWING_Status VG_DRAWING_STUB_drawStringOnCircleGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix){ + (void)gc; + (void)text; + (void)faceHandle; + (void)size; + (void)x; + (void)y; + (void)matrix; + (void)alpha; + (void)blend; + (void)letterSpacing; + (void)radius; + (void)direction; + (void)*gradientData; + (void)*gradientMatrix; + return not_implemented(gc); +} + +DRAWING_Status VG_DRAWING_STUB_drawImage(MICROUI_GraphicsContext* gc, void* image, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno){ + (void)gc; + (void)image; + (void)*matrix; + (void)alpha; + (void)elapsed; + (void)color_matrix; + (void)errno; + return not_implemented(gc); +} + +// -------------------------------------------------------------------------------- +// EOF +// -------------------------------------------------------------------------------- diff --git a/bsp/projects/microej/vg/src/vg_drawing_vglite.c b/bsp/projects/microej/vg/src/vg_drawing_vglite.c new file mode 100644 index 0000000..7ae8ba3 --- /dev/null +++ b/bsp/projects/microej/vg/src/vg_drawing_vglite.c @@ -0,0 +1,507 @@ +/* + * C + * + * Copyright 2021-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/** + * @file + * @brief Implementation of a set of vg_drawing.h drawing functions (library MicroVG). + * These are implementations over VGLite and the destination buffer format is the format specified + * in the VEE port. + * + * This file redirects the drawings of the strings and the images to some third-party files. + * These files don't perform the drawing themselves and let the caller do it. The drawing function + * is specified by vg_drawing_vglite.c to target standard destination buffers (display buffer and all + * MicroUI BufferedImage). + * + * @author MicroEJ Developer Team + * @version 7.0.1 + */ + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- + +#include + +#include +#include + +#include "vg_drawing_vglite.h" +#include "ui_drawing_vglite.h" +#include "microvg_helper.h" +#include "microvg_vglite_helper.h" +#include "color.h" +#include "ui_vglite.h" + +// ----------------------------------------------------------------------------- +// Defines +// ----------------------------------------------------------------------------- + +#ifndef VG_FEATURE_PATH +#error "This implementation is only compatible when VG_FEATURE_PATH is set" +#endif + +/* + * @brief Specific error code when VGLite library throws an error. + */ +#define RET_ERROR_VGLITE -1 + +/* + * @brief Specific error code when gradient data is invalid. + */ +#define RET_ERROR_GRADIENT -2 + +// ----------------------------------------------------------------------------- +// Private globals +// ----------------------------------------------------------------------------- + +static vg_lite_path_t render_path; +static vg_lite_buffer_t* render_buffer; +static bool draw_gradient_flushed; + +// ----------------------------------------------------------------------------- +// Private functions +// ----------------------------------------------------------------------------- + +static inline DRAWING_Status _post_operation(MICROUI_GraphicsContext* gc, jint error, bool rendered) { + DRAWING_Status ret; + if (LLVG_SUCCESS != error) { + ret = MICROVG_VGLITE_report_error(gc, error); + } + else if (rendered) { + // start GPU operation and do not wait for it to end + UI_VGLITE_start_operation(true); + ret = DRAWING_RUNNING; + } + else { + // else: nothing has been drawn (empty drawing, out of clip, etc.): not an error + ret = DRAWING_DONE; + } + if (DRAWING_RUNNING != ret) { + // GPU is useless now, can be disabled. No GPU access should be done after this line + UI_VGLITE_IMPL_notify_gpu_stop(); + } + if (!UI_VGLITE_need_to_premultiply() && (VG_LITE_SUCCESS != vg_lite_enable_premultiply())) { + // cannot restore premultiplication + UI_VGLITE_IMPL_error(false, "vg_lite engine premultiply error: cannot restore the pre multiplication"); + } + return ret; +} + +inline static bool _need_to_premultiply(vg_lite_blend_t blend) { + bool need_to_premultiply = UI_VGLITE_need_to_premultiply(); + if (!need_to_premultiply) { + switch (blend) { + case VG_LITE_BLEND_NONE: + case VG_LITE_BLEND_SRC_IN: + case VG_LITE_BLEND_DST_IN: + case VG_LITE_BLEND_SUBTRACT: + if (VG_LITE_SUCCESS != vg_lite_disable_premultiply()) { + // have to disable the premultiplication but cannot + UI_VGLITE_IMPL_error(false, "vg_lite engine premultiply error: cannot disable the pre multiplication"); + } + else { + need_to_premultiply = true; + } + break; + default: + // use the GPU premultiplication + break; + } + } + return need_to_premultiply; +} + +inline static void _update_color(vg_lite_color_t* color, vg_lite_blend_t blend) { + if (_need_to_premultiply(blend)) { + // premultiply color + *color = UI_VGLITE_premultiply(*color); + } +} + +static void _update_gradient(vg_lite_linear_gradient_t* gradient, vg_lite_blend_t blend) { + if (_need_to_premultiply(blend)) { + // premultiply each color + uint32_t count = gradient->count; + uint32_t* colors = gradient->colors; + for (uint32_t i = 0; i < count; i++) { + colors[i] = UI_VGLITE_premultiply(colors[i]); + } + } + + // update the VGLite internal image that represents the gradient + (void)vg_lite_update_grad(gradient); // always success +} + +static inline jint _convert_vglite_error_to_llvg_error(vg_lite_error_t vg_lite_error) { + jint ret; + switch (vg_lite_error) { + case VG_LITE_SUCCESS: + ret = LLVG_SUCCESS; + break; + case VG_LITE_OUT_OF_MEMORY: + ret = LLVG_OUT_OF_MEMORY; + break; + default: + ret = LLVG_DATA_INVALID; + break; + } + return ret; +} + +// VG_DRAWING_VGLITE_draw_image_element_t +static jint _draw_image_element(vg_lite_path_t * path, vg_lite_fill_t fill_rule, vg_lite_matrix_t * matrix, vg_lite_blend_t blend, vg_lite_color_t color, vg_lite_linear_gradient_t * grad, bool is_new_gradient) { + vg_lite_error_t ret; + if (NULL == grad) { + _update_color(&color, blend); + ret = vg_lite_draw(render_buffer, path, fill_rule, matrix, blend, color); + } + else { + + if (is_new_gradient) { + // not same gradient than previous: have to: + + // 1- flush the previous gradient drawings because we will update the shared gradient's image + if (!draw_gradient_flushed) { + UI_VGLITE_start_operation(false); + } + + // 2- update the shared gradient's image. + _update_gradient(grad, blend); + } + // else: same gradient than previous: no need to update gradient's image again + + ret = vg_lite_draw_gradient(render_buffer, path, fill_rule, matrix, grad, blend); + draw_gradient_flushed = false; + } + return _convert_vglite_error_to_llvg_error(ret); +} + +// VG_DRAWING_VGLITE_draw_glyph_t +static jint _draw_glyph_color(vg_lite_path_t * path, vg_lite_fill_t fill_rule, vg_lite_matrix_t * matrix, vg_lite_blend_t blend, vg_lite_color_t color, vg_lite_linear_gradient_t * grad) { + (void)grad; + return _convert_vglite_error_to_llvg_error(vg_lite_draw(render_buffer, path, fill_rule, matrix, blend, color)); +} + +// VG_DRAWING_VGLITE_draw_glyph_t +static jint _draw_glyph_gradient(vg_lite_path_t * path, vg_lite_fill_t fill_rule, vg_lite_matrix_t * matrix, vg_lite_blend_t blend, vg_lite_color_t color, vg_lite_linear_gradient_t * grad) { + (void)color; + return _convert_vglite_error_to_llvg_error(vg_lite_draw_gradient(render_buffer, path, fill_rule, matrix, grad, blend)); +} + +static DRAWING_Status _draw_string_on_circle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction){ + DRAWING_Status ret = DRAWING_DONE; + + if (UI_VGLITE_enable_vg_lite_scissor(gc)) { + + // prepare matrix + vg_lite_matrix_t vglite_matrix; + VG_DRAWING_VGLITE_prepare_matrix(&vglite_matrix, x, y, matrix); + + // prepare color + vg_lite_blend_t vglite_blend = MICROVG_VGLITE_HELPER_get_blend(blend); + vg_lite_color_t vglite_color = (vg_lite_color_t)((gc->foreground_color & 0x00FFFFFF) + (int)(((unsigned int) alpha) << 24)); + _update_color(&vglite_color, vglite_blend); + + // draw + bool rendered; + render_buffer = UI_VGLITE_configure_destination(gc); + jint error = VG_DRAWING_VGLITE_draw_string(&_draw_glyph_color, text, faceHandle, size, &vglite_matrix, vglite_blend, vglite_color, MICROVG_HELPER_NULL_GRADIENT, letterSpacing, radius, direction, &rendered); + ret = _post_operation(gc, error, rendered); + } + // else no error: the drawing is just "not performed" + + return ret; +} + +static DRAWING_Status _draw_string_on_circle_gradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix){ + DRAWING_Status ret = DRAWING_DONE; + + if (UI_VGLITE_enable_vg_lite_scissor(gc)) { + + // prepare matrix + vg_lite_matrix_t vglite_matrix; + VG_DRAWING_VGLITE_prepare_matrix(&vglite_matrix, x, y, matrix); + + // parepare gradient + vg_lite_linear_gradient_t vglite_gradient; + vg_lite_error_t vglite_error = VG_DRAWING_VGLITE_prepare_gradient(&vglite_gradient, gradientData, gradientMatrix, &vglite_matrix, alpha); + + if (VG_LITE_SUCCESS == vglite_error) { + + // create the gradient image + vg_lite_blend_t vglite_blend = MICROVG_VGLITE_HELPER_get_blend(blend); + _update_gradient(&vglite_gradient, vglite_blend); + + // draw + bool rendered; + render_buffer = UI_VGLITE_configure_destination(gc); + jint error = VG_DRAWING_VGLITE_draw_string(&_draw_glyph_gradient, text, faceHandle, size, &vglite_matrix, vglite_blend, 0, &vglite_gradient, letterSpacing, radius, direction, &rendered); + ret = _post_operation(gc, error, rendered); + + VG_DRAWING_VGLITE_clear_gradient(&vglite_gradient); + } + else { + ret = UI_VGLITE_report_vglite_error(gc, vglite_error); + } + } + // else no error: the drawing is just "not performed" + + return ret; +} + +// ----------------------------------------------------------------------------- +// microvg_path.h functions +// ----------------------------------------------------------------------------- + +// See the header file for the function documentation +void MICROVG_PATH_initialize(void) { + vg_lite_init_path( + &render_path, + (vg_lite_format_t)MICROVG_PATH_get_path_encoder_format(), // default value + VG_LITE_HIGH, + 0, + NULL, + -4000, // Left + -4000, // Top + 4000, // Right + 4000 // Bottom + ); + render_path.path_type = VG_LITE_DRAW_FILL_PATH; +} + +// See the header file for the function documentation +uint8_t MICROVG_PATH_get_path_encoder_format(void) { + return VG_LITE_FP32; +} + +// See the header file for the function documentation +uint32_t MICROVG_PATH_convert_path_command(jint command) { + uint32_t ret; + switch (command) { + default: // unknown -> close (should not occur) + case LLVG_PATH_CMD_CLOSE: + ret = VLC_OP_END; + break; + case LLVG_PATH_CMD_MOVE: + ret = VLC_OP_MOVE; + break; + case LLVG_PATH_CMD_MOVE_REL: + ret = VLC_OP_MOVE_REL; + break; + case LLVG_PATH_CMD_LINE: + ret = VLC_OP_LINE; + break; + case LLVG_PATH_CMD_LINE_REL: + ret = VLC_OP_LINE_REL; + break; + case LLVG_PATH_CMD_QUAD: + ret = VLC_OP_QUAD; + break; + case LLVG_PATH_CMD_QUAD_REL: + ret = VLC_OP_QUAD_REL; + break; + case LLVG_PATH_CMD_CUBIC: + ret = VLC_OP_CUBIC; + break; + case LLVG_PATH_CMD_CUBIC_REL: + ret = VLC_OP_CUBIC_REL; + break; + } + return ret; +} + +// See the header file for the function documentation +uint32_t MICROVG_PATH_get_command_parameter_number(jint command) { + uint32_t ret; + switch (command) { + default: // unknown -> close (should not occur) + case VLC_OP_END: + case VLC_OP_CLOSE: + ret = 0; + break; + case VLC_OP_MOVE: + case VLC_OP_MOVE_REL: + case VLC_OP_LINE: + case VLC_OP_LINE_REL: + ret = 2; + break; + case VLC_OP_QUAD: + case VLC_OP_QUAD_REL: + ret = 4; + break; + case VLC_OP_CUBIC: + case VLC_OP_CUBIC_REL: + ret = 6; + break; + } + return ret; +} + +// -------------------------------------------------------------------------------- +// vg_drawing_vglite.h functions +// -------------------------------------------------------------------------------- + +void VG_DRAWING_VGLITE_prepare_matrix(vg_lite_matrix_t* vg_lite_matrix, jfloat x, jfloat y, jfloat* matrix) { + jfloat* local_matrix = MICROVG_HELPER_check_matrix(matrix); + jfloat* mapped_matrix = MAP_VGLITE_MATRIX(vg_lite_matrix); + + if((0 != x) || (0 != y)) { + // Create translate matrix for initial x,y translation from graphicscontext. + LLVG_MATRIX_IMPL_setTranslate(mapped_matrix, x, y); + LLVG_MATRIX_IMPL_concatenate(mapped_matrix, local_matrix); + } + else { + // use original matrix + LLVG_MATRIX_IMPL_copy(mapped_matrix, local_matrix); + } +} + +vg_lite_error_t VG_DRAWING_VGLITE_prepare_gradient(vg_lite_linear_gradient_t* gradient, jint* gradientData, jfloat* gradientMatrix, vg_lite_matrix_t* vg_lite_matrix, int alpha) { + jfloat* local_gradient_matrix = MICROVG_HELPER_check_matrix(gradientMatrix); + return MICROVG_VGLITE_HELPER_to_vg_lite_gradient(gradient, gradientData, local_gradient_matrix, MAP_VGLITE_MATRIX(vg_lite_matrix), alpha); +} + +/* + * @brief vg_lite_init_grad allocates a buffer in VGLite buffer, we must free it. + * No error even if init_grad is never called because vg_lite_clear_grad + * checks the allocation. + */ +void VG_DRAWING_VGLITE_clear_gradient(vg_lite_linear_gradient_t* gradient) { + vg_lite_clear_grad(gradient); +} + +/* + * @brief Fills a VGLite path with RAW path data + */ +vg_lite_path_t* VG_DRAWING_VGLITE_to_vglite_path(MICROVG_PATH_HEADER_t* p){ + render_path.bounding_box[0] = (vg_lite_float_t)(p->bounds_xmin); + render_path.bounding_box[1] = (vg_lite_float_t)(p->bounds_ymin); + render_path.bounding_box[2] = (vg_lite_float_t)(p->bounds_xmax); + render_path.bounding_box[3] = (vg_lite_float_t)(p->bounds_ymax); + render_path.format = (vg_lite_format_t)(p->format); + render_path.path_length = (int32_t)(p->data_size); + render_path.path = (void*)&(((uint8_t*)p)[MICROVG_PATH_get_path_header_size()]); + render_path.path_changed = 1; + return &render_path; +} + +// -------------------------------------------------------------------------------- +// vg_drawing_vglite.h functions +// (the function names differ according to the available number of destination formats) +// -------------------------------------------------------------------------------- + +// See the header file for the function documentation +DRAWING_Status VG_DRAWING_VGLITE_drawPath(MICROUI_GraphicsContext* gc, jbyte* pathData, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color) { + DRAWING_Status ret = DRAWING_DONE; + + if (UI_VGLITE_enable_vg_lite_scissor(gc)) { + + // prepare path + vg_lite_path_t* vglite_path = VG_DRAWING_VGLITE_to_vglite_path((MICROVG_PATH_HEADER_t*)pathData); + vg_lite_blend_t vglite_blend = MICROVG_VGLITE_HELPER_get_blend(blend); + vg_lite_fill_t vglite_fill = MICROVG_VGLITE_HELPER_get_fill_rule(fillRule); + + // prepare matrix + vg_lite_matrix_t vglite_matrix; + VG_DRAWING_VGLITE_prepare_matrix(&vglite_matrix, x, y, matrix); + + // prepare color + vg_lite_color_t vglite_color = (vg_lite_color_t)color; + _update_color(&vglite_color, vglite_blend); + + // draw + render_buffer = UI_VGLITE_configure_destination(gc); + vg_lite_error_t vglite_error = vg_lite_draw(render_buffer, vglite_path, vglite_fill, &vglite_matrix, vglite_blend, vglite_color); + + // post operation + ret = UI_VGLITE_post_operation(gc, vglite_error); + } + // else no error: the drawing is just "not performed" + + return ret; +} + +// See the header file for the function documentation +DRAWING_Status VG_DRAWING_VGLITE_drawGradient(MICROUI_GraphicsContext* gc, jbyte* pathData, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradientData, jfloat* gradientMatrix){ + DRAWING_Status ret = DRAWING_DONE; + + if (UI_VGLITE_enable_vg_lite_scissor(gc)) { + + // prepare path + vg_lite_path_t* vglite_path = VG_DRAWING_VGLITE_to_vglite_path((MICROVG_PATH_HEADER_t*)pathData); + vg_lite_blend_t vglite_blend = MICROVG_VGLITE_HELPER_get_blend(blend); + vg_lite_fill_t vglite_fill = MICROVG_VGLITE_HELPER_get_fill_rule(fillRule); + + // prepare matrix + vg_lite_matrix_t vglite_matrix; + VG_DRAWING_VGLITE_prepare_matrix(&vglite_matrix, x, y, matrix); + + // parepare gradient + vg_lite_linear_gradient_t vglite_gradient; + vg_lite_error_t vglite_error = VG_DRAWING_VGLITE_prepare_gradient(&vglite_gradient, gradientData, gradientMatrix, &vglite_matrix, alpha); + + if (VG_LITE_SUCCESS == vglite_error) { + + // create the gradient image + _update_gradient(&vglite_gradient, vglite_blend); + + // draw + render_buffer = UI_VGLITE_configure_destination(gc); + vglite_error = vg_lite_draw_gradient(render_buffer, vglite_path, vglite_fill, &vglite_matrix, &vglite_gradient, vglite_blend); + + // post operation + ret = UI_VGLITE_post_operation(gc, vglite_error); + VG_DRAWING_VGLITE_clear_gradient(&vglite_gradient); + } + else { + ret = UI_VGLITE_report_vglite_error(gc, vglite_error); + } + + } + // else no error: the drawing is just "not performed" + + return ret; +} + +DRAWING_Status VG_DRAWING_VGLITE_drawString(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing){ + return _draw_string_on_circle(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, (jfloat)0, (jint)0); +} + +DRAWING_Status VG_DRAWING_VGLITE_drawStringGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, float* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix){ + return _draw_string_on_circle_gradient(gc, text, faceHandle, size, x, y, matrix, alpha, blend, letterSpacing, (jfloat)0, (jint)0, gradientData, gradientMatrix); +} + +DRAWING_Status VG_DRAWING_VGLITE_drawStringOnCircle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction){ + return _draw_string_on_circle(gc, text, faceHandle, size, (jfloat)x, (jfloat)y, matrix, alpha, blend, letterSpacing, radius, direction); +} + +DRAWING_Status VG_DRAWING_VGLITE_drawStringOnCircleGradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix){ + return _draw_string_on_circle_gradient(gc, text, faceHandle, size, (jfloat)x, (jfloat)y, matrix, alpha, blend, letterSpacing, radius, direction, gradientData, gradientMatrix); +} + +DRAWING_Status VG_DRAWING_VGLITE_drawImage(MICROUI_GraphicsContext* gc, void* image, jfloat *matrix, jint alpha, jlong elapsed, const float color_matrix[], jint* errno){ + + DRAWING_Status ret = DRAWING_DONE; + float width; + float height; + VG_DRAWING_get_image_size(image, &width, &height); + + if (UI_VGLITE_enable_vg_lite_scissor_area(gc, width, height, matrix)) { + render_buffer = UI_VGLITE_configure_destination(gc); + draw_gradient_flushed = true; // no drawing with gradient has been added yet + bool rendered; + *errno = VG_DRAWING_VGLITE_draw_image(&_draw_image_element, image, matrix, alpha, elapsed, color_matrix, &rendered); + ret = _post_operation(gc, *errno, rendered); + } + // nothing to draw + + return ret; +} + +// ----------------------------------------------------------------------------- +// EOF +// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vglite_support/vglite_support.c b/bsp/projects/microej/vglite_support/vglite_support.c similarity index 85% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/vglite_support/vglite_support.c rename to bsp/projects/microej/vglite_support/vglite_support.c index cfb01c0..50c2c73 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vglite_support/vglite_support.c +++ b/bsp/projects/microej/vglite_support/vglite_support.c @@ -4,16 +4,7 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * Copyright 2020-2022 MicroEJ Corp. This file has been modified by MicroEJ Corp. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - * - * see vglite_support.h + * Copyright 2020-2023 MicroEJ Corp. This file has been modified by MicroEJ Corp. */ #include "vglite_support.h" @@ -21,6 +12,9 @@ #include "fsl_power.h" #include "vg_lite.h" #include "vg_lite_platform.h" +#include "ui_vglite.h" +#include "bsp_util.h" + /******************************************************************************* * Definitions ******************************************************************************/ @@ -58,9 +52,19 @@ uint32_t vglite_cmd_buff_size = VG_LITE_COMMAND_BUFFER_SIZE; /******************************************************************************* * Code ******************************************************************************/ + +/* + * @brief Notifies the CCO MicroUI-VGLite about the GPU interrupt. When this CCO + * is not installed / available, the default function is used and does nothing. + */ +BSP_DECLARE_WEAK_FCNT void UI_VGLITE_IRQHandler(void) { + // does nothing by default +} + void GPU_DriverIRQHandler(void) { vg_lite_IRQHandler(); + UI_VGLITE_IRQHandler(); } // modified by MicroEJ @@ -76,6 +80,7 @@ status_t BOARD_InitVGliteClock(void) RESET_ClearPeripheralReset(kGPU_RST_SHIFT_RSTn); RESET_ClearPeripheralReset(kAXI_SWITCH_RST_SHIFT_RSTn); + NVIC_SetPriority(GPU_IRQn, 3); EnableIRQ((IRQn_Type)GPU_IRQn); return kStatus_Success; diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vglite_support/vglite_support.h b/bsp/projects/microej/vglite_support/vglite_support.h similarity index 89% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/vglite_support/vglite_support.h rename to bsp/projects/microej/vglite_support/vglite_support.h index b38cd4b..aab2870 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vglite_support/vglite_support.h +++ b/bsp/projects/microej/vglite_support/vglite_support.h @@ -4,14 +4,14 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * Copyright 2020-2022 MicroEJ Corp. This file has been modified by MicroEJ Corp. + * Copyright 2020-2023 MicroEJ Corp. This file has been modified by MicroEJ Corp. */ /* * @file * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite * @author MicroEJ Developer Team - * @version 3.0.0 + * @version 7.0.0 * * 1- make BOARD_InitVGliteClock function as public * 2- add BOARD_StopVGliteClock, BOARD_StartVGliteClock diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vglite_window/vglite_window.c b/bsp/projects/microej/vglite_window/vglite_window.c similarity index 90% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/vglite_window/vglite_window.c rename to bsp/projects/microej/vglite_window/vglite_window.c index ef82dc3..0f3f7e6 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vglite_window/vglite_window.c +++ b/bsp/projects/microej/vglite_window/vglite_window.c @@ -4,14 +4,14 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * Copyright 2019-2022 MicroEJ Corp. This file has been modified by MicroEJ Corp. + * Copyright 2019-2023 MicroEJ Corp. This file has been modified by MicroEJ Corp. */ /* * @file * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite * @author MicroEJ Developer Team - * @version 3.0.0 + * @version 7.0.0 * * See vglite_windows.h */ @@ -170,3 +170,12 @@ void VGLITE_SwapBuffers(vg_lite_window_t *window) void *b = FBDEV_GetFrameBuffer(&window->display->g_fbdev, 0); #endif } + +void VGLITE_CancelSwapBuffers(void) +{ + // does not work: (-1) % 2 = 1 and gives -1 +// fb_idx--; +// fb_idx %= APP_BUFFER_COUNT; + fb_idx = fb_idx == 0 ? (APP_BUFFER_COUNT - 1) : (fb_idx ) - 1; +} + diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vglite_window/vglite_window.h b/bsp/projects/microej/vglite_window/vglite_window.h similarity index 91% rename from nxpvee-mimxrt595-evk-round-bsp/projects/microej/vglite_window/vglite_window.h rename to bsp/projects/microej/vglite_window/vglite_window.h index dc28fb5..430fff5 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vglite_window/vglite_window.h +++ b/bsp/projects/microej/vglite_window/vglite_window.h @@ -4,14 +4,14 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * Copyright 2019-2022 MicroEJ Corp. This file has been modified by MicroEJ Corp. + * Copyright 2019-2023 MicroEJ Corp. This file has been modified by MicroEJ Corp. */ /* * @file * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite * @author MicroEJ Developer Team - * @version 3.0.0 + * @version 7.0.0 * * 1. Add VGLITE_GetBuffers and VGLITE_GetNextBuffer functions. * 2. Redirect APP_BUFFER_COUNT to FRAME_BUFFER_COUNT defined @@ -78,6 +78,7 @@ vg_lite_buffer_t *VGLITE_GetNextBuffer(vg_lite_window_t *window); void VGLITE_SwapBuffers(vg_lite_window_t *window); +void VGLITE_CancelSwapBuffers(void); #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/.gitignore b/bsp/projects/nxpvee-ui/armgcc/.gitignore similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/.gitignore rename to bsp/projects/nxpvee-ui/armgcc/.gitignore diff --git a/bsp/projects/nxpvee-ui/armgcc/CMakeLists.txt b/bsp/projects/nxpvee-ui/armgcc/CMakeLists.txt new file mode 100644 index 0000000..c31c9f6 --- /dev/null +++ b/bsp/projects/nxpvee-ui/armgcc/CMakeLists.txt @@ -0,0 +1,328 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.27.0) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +if (NOT DEFINED SdkOverlayRootDirPath) + SET(SdkOverlayRootDirPath ${ProjDirPath}/../../../sdk_overlay/) +endif() + +if (NOT DEFINED VeeSdkRootDirPath) + SET(VeeSdkRootDirPath ${ProjDirPath}/../../../mcux-sdk/core/) +endif() + +if (NOT DEFINED RtosRootDirPath) + SET(RtosRootDirPath ${ProjDirPath}/../../../mcux-sdk/rtos/) +endif() + +if (NOT DEFINED MicroejDirPath) + SET(MicroejDirPath ${ProjDirPath}/../../microej/) +endif() + + +find_package(Git) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +project(mimxrt595_freertos-bsp) + +file (STRINGS "${ProjDirPath}/../../../nvee_version.txt" VEE_VERSION) + +set(MCUX_DEVICE MIMXRT595S_cm33) +set(PROJECT_NAME mimxrt595_freertos-bsp) +set(MCUX_SDK_PROJECT_NAME ${PROJECT_NAME}.elf) +cmake_path(GET MCUX_SDK_PROJECT_NAME STEM MCUX_SDK_PROJECT_NAME_NO_EXT) + +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart true) +set(CONFIG_USE_driver_flexcomm_usart true) + +include (${ProjDirPath}/flags.cmake) + +execute_process(COMMAND + "${GIT_EXECUTABLE}" describe --always --abbrev=8 --dirty + WORKING_DIRECTORY "${ProjDirPath}" + OUTPUT_VARIABLE GIT_SHA_1 + ERROR_QUIET OUTPUT_STRIP_TRAILING_WHITESPACE) + +configure_file("${ProjDirPath}/../main/src/tree_version.c.in" "${CMAKE_CURRENT_BINARY_DIR}/tree_version.c" @ONLY) + +add_executable(${MCUX_SDK_PROJECT_NAME} + "${ProjDirPath}/../board/src/board.c" + "${ProjDirPath}/../board/src/clock_config.c" + "${ProjDirPath}/../board/src/display_support.c" + "${ProjDirPath}/../board/src/pin_mux.c" + "${ProjDirPath}/../freertos/src/SEGGER_SYSVIEW_Config_FreeRTOS.c" + "${ProjDirPath}/../simple_gfx_app/src/simple_gfx_app_imp.c" + "${ProjDirPath}/../main/src/core_test_natives.c" + "${ProjDirPath}/../main/src/cpuload.c" + "${ProjDirPath}/../main/src/cpuload_impl_FreeRTOS.c" + "${ProjDirPath}/../main/src/fault_handlers.c" + "${ProjDirPath}/../main/src/interrupts.c" + "${ProjDirPath}/../main/src/LLBSP.c" + "${ProjDirPath}/../main/src/LLEXT_RES_impl.c" + "${ProjDirPath}/../main/src/LLMJVM_FreeRTOS.c" + "${ProjDirPath}/../main/src/main.c" + "${ProjDirPath}/../main/src/microjvm_main.c" + "${ProjDirPath}/../main/src/monitor.c" + "${ProjDirPath}/../main/src/os_support.c" + "${ProjDirPath}/../main/src/stack_overflow_impl_FreeRTOS.c" + "${ProjDirPath}/../main/src/time_hardware_timer.c" + "${ProjDirPath}/../main/src/trace_platform.c" + "${MicroejDirPath}/osal/src/osal_FreeRTOS.c" + "${MicroejDirPath}/lowpower/src/power_manager.c" + "${MicroejDirPath}/lowpower/src/fsl_tickless_rtc.c" + "${MicroejDirPath}/thirdparty/freetype/src/wrappers/ft_base_wrapper.c" + "${MicroejDirPath}/thirdparty/freetype/src/wrappers/ft_otf_wrapper.c" + "${MicroejDirPath}/thirdparty/freetype/src/wrappers/ft_ttf_wrapper.c" + "${MicroejDirPath}/thirdparty/freetype/src/wrappers/ft_vector_wrapper.c" + "${MicroejDirPath}/thirdparty/harfbuzz/src/hb-alloc.c" + "${MicroejDirPath}/thirdparty/systemview/src/SEGGER_RTT.c" + "${MicroejDirPath}/thirdparty/systemview/src/SEGGER_SYSVIEW.c" + "${MicroejDirPath}/thirdparty/systemview-freertos/src/SEGGER_SYSVIEW_FreeRTOS.c" + "${MicroejDirPath}/trace/src/LLMJVM_MONITOR_sysview.c" + "${MicroejDirPath}/trace/src/LLTRACE_sysview.c" + "${MicroejDirPath}/ui/src/buttons_helper.c" + "${MicroejDirPath}/ui/src/buttons_manager.c" + "${MicroejDirPath}/ui/src/display_dma.c" + "${MicroejDirPath}/ui/src/display_framebuffer.c" + "${MicroejDirPath}/ui/src/event_generator.c" + "${MicroejDirPath}/ui/src/framerate.c" + "${MicroejDirPath}/ui/src/framerate_impl_FreeRTOS.c" + "${MicroejDirPath}/ui/src/LLDW_PAINTER_impl.c" + "${MicroejDirPath}/ui/src/LLUI_DISPLAY_impl.c" + "${MicroejDirPath}/ui/src/LLUI_INPUT_impl.c" + "${MicroejDirPath}/ui/src/LLUI_PAINTER_impl.c" + "${MicroejDirPath}/ui/src/touch_helper.c" + "${MicroejDirPath}/ui/src/touch_manager.c" + "${MicroejDirPath}/ui/src/ui_display_brs.c" + "${MicroejDirPath}/ui/src/ui_display_brs_legacy.c" + "${MicroejDirPath}/ui/src/ui_display_brs_predraw.c" + "${MicroejDirPath}/ui/src/ui_display_brs_single.c" + "${MicroejDirPath}/ui/src/ui_drawing.c" + "${MicroejDirPath}/ui/src/ui_drawing_vglite.c" + "${MicroejDirPath}/ui/src/ui_drawing_vglite_path.c" + "${MicroejDirPath}/ui/src/ui_drawing_vglite_process.c" + "${MicroejDirPath}/ui/src/ui_rect_util.c" + "${MicroejDirPath}/ui/src/ui_vglite.c" + "${MicroejDirPath}/util/src/mej_debug.c" + "${MicroejDirPath}/util/src/mej_math.c" + "${MicroejDirPath}/util/src/pool.c" + "${MicroejDirPath}/vg/src/LLVG_PAINTER_impl.c" + "${MicroejDirPath}/vg/src/vg_drawing_bvi.c" + "${MicroejDirPath}/vg/src/vg_drawing_stub.c" + "${MicroejDirPath}/vg/src/vg_drawing_vglite.c" + "${MicroejDirPath}/vg/src/vg_drawing.c" + "${MicroejDirPath}/vg/src/LLVG_BVI_stub.c" + "${MicroejDirPath}/vg/src/LLVG_FONT_freetype.c" + "${MicroejDirPath}/vg/src/LLVG_FONT_PAINTER_freetype_vglite.c" + "${MicroejDirPath}/vg/src/LLVG_FONT_stub.c" + "${MicroejDirPath}/vg/src/LLVG_GRADIENT_impl.c" + "${MicroejDirPath}/vg/src/LLVG_impl.c" + "${MicroejDirPath}/vg/src/LLVG_MATRIX_impl.c" + "${MicroejDirPath}/vg/src/LLVG_PATH_impl.c" + "${MicroejDirPath}/vg/src/LLVG_PATH_stub.c" + "${MicroejDirPath}/vg/src/LLVG_RAW_impl.c" + "${MicroejDirPath}/vg/src/LLVG_vglite.c" + "${MicroejDirPath}/vg/src/microvg_helper.c" + "${MicroejDirPath}/vglite_support/vglite_support.c" + "${MicroejDirPath}/vglite_window/vglite_window.c" + "${MicroejDirPath}/stub/src/stub.c" + "${VeeSdkRootDirPath}/devices/MIMXRT595S/mcuxpresso/startup_mimxrt595s_cm33.c" + ${CMAKE_CURRENT_BINARY_DIR}/tree_version.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${ProjDirPath}/.. + ${ProjDirPath}/../board/inc + ${ProjDirPath}/../freertos/inc + ${ProjDirPath}/../main/inc + ${MicroejDirPath}/lowpower/inc + ${MicroejDirPath}/trace/inc + ${MicroejDirPath}/ui/inc + ${MicroejDirPath}/util/inc + ${MicroejDirPath}/vg/inc + ${MicroejDirPath}/thirdparty/systemview/inc + ${MicroejDirPath}/thirdparty/systemview-freertos/inc + ${MicroejDirPath}/thirdparty/freetype/inc + ${MicroejDirPath}/thirdparty/harfbuzz/inc + ${MicroejDirPath}/osal/inc + ${MicroejDirPath}/platform/inc + ${MicroejDirPath}/vglite_support + ${MicroejDirPath}/vglite_window +) + +add_definitions( + -D__USE_CMSIS + -DDEBUG + -DFSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1 + -DBOOT_HEADER_ENABLE=1 + -DCPU_MIMXRT595SFFOB_cm33 + -DBOARD_ENABLE_PSRAM_CACHE=0 + -DFLEXIO_MCULCD_DATA_BUS_WIDTH=8 + -DDBI_FLEXIO_USE_SMARTDMA=1 + -DCUSTOM_VGLITE_MEMORY_CONFIG=1 + -DVG_RESOLVE_ENGINE=0 + -DVG_PE_COLOR_KEY=0 + -DVG_IM_INDEX_FORMAT=0 + -DVG_AYUV_INPUT_OUTPUT=0 + -DVG_DOUBLE_IMAGE=0 + -DVG_RECTANGLE_STRIP_MODE=0 + -DVG_MMU=0 + -DVG_DRIVER_SINGLE_THREAD=1 + -DVG_IM_FILTER=0 + -DVG_IM_YUV_PACKET=1 + -DVG_IM_YUV_PLANAR=0 + -DVG_PE_YUV_PACKET=1 + -DVG_TARGET_TILED=1 + -DVG_COMMAND_CALL=1 + -DVG_SHARE_BUFFER_IM_16K=0 + -DVG_OFFLINE_MODE=0 + -DVG_RESOLUTION_2880=0 + -DVG_PE_PREMULTIPLY=0 + -DVG_POST_CONVERTER=0 + -DVG_PRE_CONVERTER=0 + -DVG_RENDER_BY_MESH=0 + -DVG_TARGET_FAST_CLEAR=0 + -DVG_BUFFER_NUMBER_OF_TARGET=0 + -DVG_VIDEO_CLEAR_CONTROL=0 + -DVG_VIDEO_CONTROL=0 + -DVGLITE_TST_FIRMWARE=0 + -DVG_LITE_SYS_GPU_CTRL=0 + -DSERIAL_PORT_TYPE_UART=1 + -DFSL_RTOS_FREE_RTOS + -DPRINTF_FLOAT_ENABLE=1 + -DPRINTF_ADVANCED_ENABLE=1 + -DENABLE_SYSTEM_VIEW=1 + -DSDK_I2C_BASED_COMPONENT_USED=1 + -D_VG_LITE_IRQ_CALLBACK=1 + -DSL_WFX_PROD_KEY=1 + -DLWIP_2_1_2 + -DSDK_DEBUGCONSOLE_UART + -DFT_CONFIG_MODULES_H=\"freetype/config/ftmodule.h\" + -DFT2_BUILD_LIBRARY + -DRTT_USE_ASM=0 +) + +SET(CMAKE_MODULE_PATH + ${MicroejDirPath}/gpio + ${VeeSdkRootDirPath}/boards/evkmimxrt595/flash_config/ + ${VeeSdkRootDirPath}/components/ft3267 + ${VeeSdkRootDirPath}/components/serial_manager + ${VeeSdkRootDirPath}/components/pca9420 + ${VeeSdkRootDirPath}/components/lists + ${VeeSdkRootDirPath}/components/uart + ${VeeSdkRootDirPath}/components/video + ${VeeSdkRootDirPath}/components/video/display + ${VeeSdkRootDirPath}/components/video/display/dbi + ${VeeSdkRootDirPath}/components/video/display/dbi/flexio + ${VeeSdkRootDirPath}/components/video/display/dc + ${VeeSdkRootDirPath}/components/video/display/dc/ssd1963 + ${VeeSdkRootDirPath}/components/video/display/dc/lcdif + ${VeeSdkRootDirPath}/components/video/display/dc/dsi_cmd + ${VeeSdkRootDirPath}/components/video/display/fbdev + ${VeeSdkRootDirPath}/components/video/display/mipi_dsi_cmd + ${VeeSdkRootDirPath}/components/video/display/rm67162 + ${VeeSdkRootDirPath}/components/video/display/rm68191 + ${VeeSdkRootDirPath}/components/video/display/rm68200 + ${VeeSdkRootDirPath}/CMSIS/Core/Include + ${VeeSdkRootDirPath}/CMSIS/DSP + ${VeeSdkRootDirPath}/devices/MIMXRT595S + ${VeeSdkRootDirPath}/devices/MIMXRT595S/drivers/ + ${VeeSdkRootDirPath}/devices/MIMXRT595S/utilities/ + ${VeeSdkRootDirPath}/devices/MIMXRT595S/utilities/debug_console/ + ${VeeSdkRootDirPath}/drivers/common/ + ${VeeSdkRootDirPath}/drivers/flexcomm/ + ${VeeSdkRootDirPath}/drivers/mipi_dsi/ + ${VeeSdkRootDirPath}/drivers/lpc_dma/ + ${VeeSdkRootDirPath}/drivers/flexio/ + ${VeeSdkRootDirPath}/drivers/flexspi/ + ${VeeSdkRootDirPath}/drivers/inputmux/ + ${VeeSdkRootDirPath}/drivers/lpc_gpio/ + ${VeeSdkRootDirPath}/drivers/powerquad/ + ${VeeSdkRootDirPath}/drivers/lpc_rtc/ + ${VeeSdkRootDirPath}/drivers/smartdma/ + ${VeeSdkRootDirPath}/drivers/trng/ + ${VeeSdkRootDirPath}/drivers/ + ${VeeSdkRootDirPath}/utilities/debug_console/ + ${VeeSdkRootDirPath}/utilities/misc_utilities/ + ${VeeSdkRootDirPath}/utilities/assert/ + ${VeeSdkRootDirPath}/utilities/ + ${VeeSdkRootDirPath}/drivers/cache/cache64/ + ${VeeSdkRootDirPath}/drivers/ctimer/ + ${VeeSdkRootDirPath}/drivers/lpc_iopctl/ + ${VeeSdkRootDirPath}/drivers/pint/ + ${SdkOverlayRootDirPath}/rtos/freertos/freertos-kernel/ + ${SdkOverlayRootDirPath}/middleware/vglite/ + ${MicroejDirPath}/thirdparty/freetype/ + ${MicroejDirPath}/thirdparty/harfbuzz/ +) + +# include modules +include(driver_pca9420) +include(component_usart_adapter) +include(component_lists) +include(component_serial_manager) +include(component_serial_manager_uart) +include(device_CMSIS) +include(driver_cache_cache64) +include(driver_clock) +include(driver_common) +include(driver_ctimer) +include(driver_dbi_flexio_smartdma) +include(driver_dc-fb-dsi-cmd) +include(driver_display-rm67162) +include(driver_display-rm68191) +include(driver_display-rm68200) +include(driver_fbdev) +include(driver_flash_config_evkmimxrt595) +include(driver_flexcomm_i2c) +include(driver_flexcomm) +include(driver_flexcomm_usart_dma) +include(driver_flexcomm_usart) +include(driver_flexio) +include(driver_flexio_spi) +include(driver_flexspi) +include(driver_ft3267) +include(driver_iap) +include(driver_inputmux) +include(driver_lpc_dma) +include(driver_lpc_gpio) +include(driver_lpc_rtc) +include(driver_lpc_smartdma) +include(driver_mipi_dsi) +include(driver_mipi_dsi_smartdma) +include(driver_power) +include(driver_powerquad_cmsis) +include(driver_powerquad) +include(driver_reset) +include(driver_trng) +include(driver_video-common) +include(middleware_freertos-kernel_cm33_nonsecure_port) +include(middleware_freertos-kernel_heap_4) +include(middleware_freertos-kernel_MIMXRT595S_cm33) +include(middleware_vglite) +include(nxp_gpio) +include(utilities_misc_utilities_MIMXRT595S_cm33) +include(utility_assert) +include(utility_debug_console) +include(driver_lpc_iopctl) +include(driver_pint) +include(thirdparty_freetype) +include(thirdparty_harfbuzz) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${MicroejDirPath}/platform/lib/microejapp.o + ${MicroejDirPath}/platform/lib/microejruntime.a +) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ./${MCUX_SDK_PROJECT_NAME} ./${MCUX_SDK_PROJECT_NAME_NO_EXT}.bin) +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Oihex ./${MCUX_SDK_PROJECT_NAME} ./${MCUX_SDK_PROJECT_NAME_NO_EXT}.hex) + +SET_TARGET_PROPERTIES(${MCUX_SDK_PROJECT_NAME} PROPERTIES ADDITIONAL_CLEAN_FILES ./${MCUX_SDK_PROJECT_NAME_NO_EXT}.bin) +SET_TARGET_PROPERTIES(${MCUX_SDK_PROJECT_NAME} PROPERTIES ADDITIONAL_CLEAN_FILES ./${MCUX_SDK_PROJECT_NAME_NO_EXT}.hex) diff --git a/bsp/projects/nxpvee-ui/armgcc/CMakePresets.json b/bsp/projects/nxpvee-ui/armgcc/CMakePresets.json new file mode 100644 index 0000000..0302e38 --- /dev/null +++ b/bsp/projects/nxpvee-ui/armgcc/CMakePresets.json @@ -0,0 +1,54 @@ +{ + "version": 7, + "cmakeMinimumRequired": { + "major": 3, + "minor": 27 + }, + "configurePresets": [ + { + "name": "preset-env", + "displayName": "present-env", + "hidden": true, + "toolchainFile": "../../../../mcux-sdk/core/tools/cmake_toolchain_files/armgcc.cmake", + "environment": { + "ARMGCC_DIR": "$penv{ARMGCC_DIR}", + "SdkRootDirPath": "${sourceDir}/../../../mcux-sdk/" + }, + "generator": "Ninja", + "binaryDir": "${sourceDir}/${presetName}", + "cacheVariables": { + "DEBUG_CONSOLE": "UART", + "LANGUAGE": "C", + "LIBRARY_TYPE": "NOLIB" + } + }, + { + "name": "debug", + "displayName": "debug", + "inherits": "preset-env", + "cacheVariables": { + "CMAKE_BUILD_TYPE": "debug" + } + }, + { + "name": "release", + "displayName": "release", + "inherits": "preset-env", + "cacheVariables": { + "CMAKE_BUILD_TYPE": "release" + } + } + ], + "buildPresets": [ + { + "name": "debug", + "displayName": "debug", + "configurePreset": "debug" + }, + { + "name": "release", + "displayName": "release", + "configurePreset": "release" + } + ] +} diff --git a/bsp/projects/nxpvee-ui/armgcc/build_all.bat b/bsp/projects/nxpvee-ui/armgcc/build_all.bat new file mode 100644 index 0000000..a03d9c3 --- /dev/null +++ b/bsp/projects/nxpvee-ui/armgcc/build_all.bat @@ -0,0 +1,11 @@ +SET CMD=ninja + +if not exist debug mkdir debug +cd debug +cmake --preset debug .. +%CMD% + +if not exist release mkdir release +cd release +cmake --preset release .. +%CMD% diff --git a/bsp/projects/nxpvee-ui/armgcc/build_all.sh b/bsp/projects/nxpvee-ui/armgcc/build_all.sh new file mode 100755 index 0000000..05bf434 --- /dev/null +++ b/bsp/projects/nxpvee-ui/armgcc/build_all.sh @@ -0,0 +1,10 @@ +#!/bin/sh +CMD='ninja' + +mkdir -p debug && cd debug +cmake --preset debug .. +${CMD} + +mkdir -p release && cd release +cmake --preset release .. +${CMD} diff --git a/bsp/projects/nxpvee-ui/armgcc/build_debug.bat b/bsp/projects/nxpvee-ui/armgcc/build_debug.bat new file mode 100644 index 0000000..e48595a --- /dev/null +++ b/bsp/projects/nxpvee-ui/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +SET CMD=ninja + +if not exist debug mkdir debug +cd debug +cmake -DCMAKE_TOOLCHAIN_FILE="../../../mcux-sdk/core/tools/cmake_toolchain_files/armgcc.cmake" -G "%FLAVOUR%" -DCMAKE_BUILD_TYPE=debug .. +%CMD% diff --git a/bsp/projects/nxpvee-ui/armgcc/build_debug.sh b/bsp/projects/nxpvee-ui/armgcc/build_debug.sh new file mode 100755 index 0000000..c8eb303 --- /dev/null +++ b/bsp/projects/nxpvee-ui/armgcc/build_debug.sh @@ -0,0 +1,6 @@ +#!/bin/sh +CMD='ninja' + +mkdir -p debug && cd debug +cmake --preset debug .. +${CMD} diff --git a/bsp/projects/nxpvee-ui/armgcc/build_release.bat b/bsp/projects/nxpvee-ui/armgcc/build_release.bat new file mode 100644 index 0000000..bb8e96e --- /dev/null +++ b/bsp/projects/nxpvee-ui/armgcc/build_release.bat @@ -0,0 +1,6 @@ +SET CMD=ninja + +if not exist release mkdir release +cd release +cmake -DCMAKE_TOOLCHAIN_FILE="../../../mcux-sdk/core/tools/cmake_toolchain_files/armgcc.cmake" -G "%FLAVOUR%" -DCMAKE_BUILD_TYPE=release .. +%CMD% diff --git a/bsp/projects/nxpvee-ui/armgcc/build_release.sh b/bsp/projects/nxpvee-ui/armgcc/build_release.sh new file mode 100755 index 0000000..2effebc --- /dev/null +++ b/bsp/projects/nxpvee-ui/armgcc/build_release.sh @@ -0,0 +1,6 @@ +#!/bin/sh +CMD='ninja' + +mkdir -p release && cd release +cmake --preset release .. +${CMD} diff --git a/bsp/projects/nxpvee-ui/armgcc/clean.bat b/bsp/projects/nxpvee-ui/armgcc/clean.bat new file mode 100644 index 0000000..e9ed2a4 --- /dev/null +++ b/bsp/projects/nxpvee-ui/armgcc/clean.bat @@ -0,0 +1,2 @@ +IF EXIST debug RD /s /Q debug +IF EXIST release RD /s /Q release diff --git a/bsp/projects/nxpvee-ui/armgcc/clean.sh b/bsp/projects/nxpvee-ui/armgcc/clean.sh new file mode 100755 index 0000000..d5e1c12 --- /dev/null +++ b/bsp/projects/nxpvee-ui/armgcc/clean.sh @@ -0,0 +1,2 @@ +#!/bin/sh +rm -rf debug release diff --git a/bsp/projects/nxpvee-ui/armgcc/flags.cmake b/bsp/projects/nxpvee-ui/armgcc/flags.cmake new file mode 100644 index 0000000..dd7fb68 --- /dev/null +++ b/bsp/projects/nxpvee-ui/armgcc/flags.cmake @@ -0,0 +1,100 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +SET(ASM_COMMON_FLAGS " \ + -D__STARTUP_CLEAR_BSS \ + -mcpu=cortex-m33 \ + -mthumb \ + ${FPU} \ +") + +SET(C_COMMON_FLAGS " \ + -DCPU_MIMXRT595SFFOC_cm33 \ + -mcpu=cortex-m33 \ + -mthumb -nostdlib \ + -fno-common \ + -g3 \ + -Wall \ + -ffunction-sections \ + -fdata-sections \ + -fno-builtin-specs=nano.specs \ + -MMD \ + -MP \ + ${FPU} \ + -DVG_BLIT_WORKAROUND=0 \ +") + +SET(CXX_COMMON_FLAGS " \ + -DCPU_MIMXRT595SFFOC_cm33 \ + -mcpu=cortex-m33 \ + -mthumb -nostdlib \ + -fno-common \ + -g3 \ + -Wall \ + -ffunction-sections \ + -fdata-sections \ + -fno-builtin-specs=nano.specs \ + -MMD \ + -MP \ + ${FPU} \ + -DVG_BLIT_WORKAROUND=0 \ +") + +SET(EXE_LINKER_COMMON_FLAGS " \ + -Xlinker --gc-sections \ + -Xlinker -print-memory-usage \ + -Xlinker --sort-section=alignment \ + -Xlinker -Map=${ProjDirPath}/${CMAKE_BUILD_TYPE}/${PROJECT_NAME}.map \ + -u _printf_float \ + -L${ProjDirPath} \ + -T${ProjDirPath}/mimxrt595_freertos-bsp_Debug.ld \ +") + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + ${ASM_COMMON_FLAGS} \ + -DDEBUG \ +") + +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + ${C_COMMON_FLAGS} \ + -DDEBUG \ + -O0 \ +") + +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + ${CXX_COMMON_FLAGS} \ + -DDEBUG \ + -O0 \ +") + +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + ${EXE_LINKER_COMMON_FLAGS} \ +") + +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + ${ASM_COMMON_FLAGS} \ + -DNDEBUG \ +") + +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + ${C_COMMON_FLAGS} \ + -O3 \ +") + +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + ${CXX_COMMON_FLAGS} \ + -O3 \ +") + +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + ${EXE_LINKER_COMMON_FLAGS} \ +") diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug.ld b/bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug.ld similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug.ld rename to bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug.ld index ba36c25..900b870 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug.ld +++ b/bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug.ld @@ -142,10 +142,10 @@ SECTIONS *(.bss*) *(COMMON) . = ALIGN(8) ; - *(ICETEA_HEAP) + *(.bss.microej.runtime) . = ALIGN(4) ; - *(_java_heap) - *(_java_immortals) + *(.bss.microej.heap) + *(.bss.microej.immortals) _ebss = .; PROVIDE(__end_bss_RAM = .) ; @@ -184,11 +184,7 @@ SECTIONS } > SRAM _StackSize = 0x1000; - /* Reserve space in memory for Stack */ - .heap2stackfill : - { - . += _StackSize; - } > SRAM + /* Locate actual Stack in memory map */ .stack : ALIGN(4) { diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug_library.ld b/bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug_library.ld similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug_library.ld rename to bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug_library.ld diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug_memory.ld b/bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug_memory.ld similarity index 89% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug_memory.ld rename to bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug_memory.ld index 10fff98..fbe01e0 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug_memory.ld +++ b/bsp/projects/nxpvee-ui/armgcc/mimxrt595_freertos-bsp_Debug_memory.ld @@ -19,7 +19,7 @@ MEMORY __top_Flash = 0x8000000 + 0x800000 ; /* 8M bytes */ __base_SRAM = 0x20000000 ; /* SRAM */ __base_RAM = 0x20000000 ; /* RAM */ - __top_SRAM = 0x20000000 + 0x300000 ; /* 3M bytes */ - __top_RAM = 0x20000000 + 0x300000 ; /* 3M bytes */ + __top_SRAM = 0x20000000 + 0x500000 ; /* 5M bytes */ + __top_RAM = 0x20000000 + 0x500000 ; /* 5M bytes */ __base_EXTRAM = 0x28000000 ; /* EXTRAM */ __top_EXTRAM = 0x28800000 ; diff --git a/nxpvee-mimxrt595-evk-round-apps/src/main/java/.gitkeep b/bsp/projects/nxpvee-ui/armgcc/obj/.gitkeep similarity index 100% rename from nxpvee-mimxrt595-evk-round-apps/src/main/java/.gitkeep rename to bsp/projects/nxpvee-ui/armgcc/obj/.gitkeep diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/inc/board.h b/bsp/projects/nxpvee-ui/board/inc/board.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/inc/board.h rename to bsp/projects/nxpvee-ui/board/inc/board.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/inc/clock_config.h b/bsp/projects/nxpvee-ui/board/inc/clock_config.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/inc/clock_config.h rename to bsp/projects/nxpvee-ui/board/inc/clock_config.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/inc/display_support.h b/bsp/projects/nxpvee-ui/board/inc/display_support.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/inc/display_support.h rename to bsp/projects/nxpvee-ui/board/inc/display_support.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/inc/pin_mux.h b/bsp/projects/nxpvee-ui/board/inc/pin_mux.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/inc/pin_mux.h rename to bsp/projects/nxpvee-ui/board/inc/pin_mux.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/inc/probe.h b/bsp/projects/nxpvee-ui/board/inc/probe.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/inc/probe.h rename to bsp/projects/nxpvee-ui/board/inc/probe.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/src/board.c b/bsp/projects/nxpvee-ui/board/src/board.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/src/board.c rename to bsp/projects/nxpvee-ui/board/src/board.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/src/clock_config.c b/bsp/projects/nxpvee-ui/board/src/clock_config.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/src/clock_config.c rename to bsp/projects/nxpvee-ui/board/src/clock_config.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/src/display_support.c b/bsp/projects/nxpvee-ui/board/src/display_support.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/src/display_support.c rename to bsp/projects/nxpvee-ui/board/src/display_support.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/src/pin_mux.c b/bsp/projects/nxpvee-ui/board/src/pin_mux.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/board/src/pin_mux.c rename to bsp/projects/nxpvee-ui/board/src/pin_mux.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/freertos/inc/FreeRTOSConfig.h b/bsp/projects/nxpvee-ui/freertos/inc/FreeRTOSConfig.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/freertos/inc/FreeRTOSConfig.h rename to bsp/projects/nxpvee-ui/freertos/inc/FreeRTOSConfig.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/freertos/src/SEGGER_SYSVIEW_Config_FreeRTOS.c b/bsp/projects/nxpvee-ui/freertos/src/SEGGER_SYSVIEW_Config_FreeRTOS.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/freertos/src/SEGGER_SYSVIEW_Config_FreeRTOS.c rename to bsp/projects/nxpvee-ui/freertos/src/SEGGER_SYSVIEW_Config_FreeRTOS.c index ad0372d..fb8fb20 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/freertos/src/SEGGER_SYSVIEW_Config_FreeRTOS.c +++ b/bsp/projects/nxpvee-ui/freertos/src/SEGGER_SYSVIEW_Config_FreeRTOS.c @@ -102,7 +102,7 @@ extern const SEGGER_SYSVIEW_OS_API SYSVIEW_X_OS_TraceAPI; * Function description * Sends SystemView description strings. */ -#if (ENABLE_SVIEW == 1) +#if (ENABLE_SYSTEM_VIEW == 1) static void _cbSendSystemDesc(void) { SEGGER_SYSVIEW_SendSysDesc("N="SYSVIEW_APP_NAME",D="SYSVIEW_DEVICE_NAME",O=FreeRTOS"); SEGGER_SYSVIEW_SendSysDesc("N="SYSVIEW_APP_NAME",D="SYSVIEW_DEVICE_NAME",O=MicroEJ"); @@ -118,7 +118,7 @@ static void _cbSendSystemDesc(void) { ********************************************************************** */ -#if (ENABLE_SVIEW == 1) +#if (ENABLE_SYSTEM_VIEW == 1) SEGGER_SYSVIEW_OS_API SYSVIEW_MICROEJ_X_OS_TraceAPI; static void SYSVIEW_MICROEJ_X_OS_SendTaskList(void){ SYSVIEW_X_OS_TraceAPI.pfSendTaskList(); @@ -129,7 +129,7 @@ static void SYSVIEW_MICROEJ_X_OS_SendTaskList(void){ void SEGGER_SYSVIEW_Conf(void) { -#if (ENABLE_SVIEW == 1) +#if (ENABLE_SYSTEM_VIEW == 1) SYSVIEW_MICROEJ_X_OS_TraceAPI.pfGetTime = SYSVIEW_X_OS_TraceAPI.pfGetTime; SYSVIEW_MICROEJ_X_OS_TraceAPI.pfSendTaskList = SYSVIEW_MICROEJ_X_OS_SendTaskList; SEGGER_SYSVIEW_Init(SYSVIEW_TIMESTAMP_FREQ, SYSVIEW_CPU_FREQ, diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/bsp_util.h b/bsp/projects/nxpvee-ui/main/inc/bsp_util.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/bsp_util.h rename to bsp/projects/nxpvee-ui/main/inc/bsp_util.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/cpuload.h b/bsp/projects/nxpvee-ui/main/inc/cpuload.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/cpuload.h rename to bsp/projects/nxpvee-ui/main/inc/cpuload.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/cpuload_conf.h b/bsp/projects/nxpvee-ui/main/inc/cpuload_conf.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/cpuload_conf.h rename to bsp/projects/nxpvee-ui/main/inc/cpuload_conf.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/cpuload_impl.h b/bsp/projects/nxpvee-ui/main/inc/cpuload_impl.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/cpuload_impl.h rename to bsp/projects/nxpvee-ui/main/inc/cpuload_impl.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/fault_handlers.h b/bsp/projects/nxpvee-ui/main/inc/fault_handlers.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/fault_handlers.h rename to bsp/projects/nxpvee-ui/main/inc/fault_handlers.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/interrupts.h b/bsp/projects/nxpvee-ui/main/inc/interrupts.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/interrupts.h rename to bsp/projects/nxpvee-ui/main/inc/interrupts.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/microej.h b/bsp/projects/nxpvee-ui/main/inc/microej.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/microej.h rename to bsp/projects/nxpvee-ui/main/inc/microej.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/microjvm_main.h b/bsp/projects/nxpvee-ui/main/inc/microjvm_main.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/microjvm_main.h rename to bsp/projects/nxpvee-ui/main/inc/microjvm_main.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/monitor.h b/bsp/projects/nxpvee-ui/main/inc/monitor.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/monitor.h rename to bsp/projects/nxpvee-ui/main/inc/monitor.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/os_support.h b/bsp/projects/nxpvee-ui/main/inc/os_support.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/os_support.h rename to bsp/projects/nxpvee-ui/main/inc/os_support.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/time_hardware_timer.h b/bsp/projects/nxpvee-ui/main/inc/time_hardware_timer.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/time_hardware_timer.h rename to bsp/projects/nxpvee-ui/main/inc/time_hardware_timer.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/trace_platform.h b/bsp/projects/nxpvee-ui/main/inc/trace_platform.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/inc/trace_platform.h rename to bsp/projects/nxpvee-ui/main/inc/trace_platform.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/LLBSP.c b/bsp/projects/nxpvee-ui/main/src/LLBSP.c similarity index 87% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/LLBSP.c rename to bsp/projects/nxpvee-ui/main/src/LLBSP.c index 3a8a582..f92b531 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/LLBSP.c +++ b/bsp/projects/nxpvee-ui/main/src/LLBSP.c @@ -57,15 +57,6 @@ extern uint32_t __top_EXTRAM; // defined in linker script // Java Low Level APIs // ----------------------------------------------------------------------------- -// See the header file for the function documentation -uint8_t LLBSP_IMPL_isInReadOnlyMemory(void* ptr) { - if (LLBSP_IS_PTR_IN_RAM(ptr)) { - return MICROEJ_FALSE; - } else { - return MICROEJ_TRUE; - } -} - // See the header file for the function documentation void LLBSP_IMPL_putchar(int32_t c) { PUTCHAR(c); diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/LLEXT_RES_impl.c b/bsp/projects/nxpvee-ui/main/src/LLEXT_RES_impl.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/LLEXT_RES_impl.c rename to bsp/projects/nxpvee-ui/main/src/LLEXT_RES_impl.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/LLMJVM_FreeRTOS.c b/bsp/projects/nxpvee-ui/main/src/LLMJVM_FreeRTOS.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/LLMJVM_FreeRTOS.c rename to bsp/projects/nxpvee-ui/main/src/LLMJVM_FreeRTOS.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/LLSP_FreeRTOS.c b/bsp/projects/nxpvee-ui/main/src/LLSP_FreeRTOS.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/LLSP_FreeRTOS.c rename to bsp/projects/nxpvee-ui/main/src/LLSP_FreeRTOS.c diff --git a/bsp/projects/nxpvee-ui/main/src/core_test_natives.c b/bsp/projects/nxpvee-ui/main/src/core_test_natives.c new file mode 100644 index 0000000..289a181 --- /dev/null +++ b/bsp/projects/nxpvee-ui/main/src/core_test_natives.c @@ -0,0 +1,127 @@ +/* + * C + * + * Copyright 2018-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ + +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "sni.h" + +jfloat Java_com_microej_core_tests_MicroejCoreValidation_testFloat (jfloat a, jfloat b) { + return a * b; +} +jdouble Java_com_microej_core_tests_MicroejCoreValidation_testDouble (jdouble a, jdouble b) { + return a * b; +} +jint Java_com_microej_core_tests_MicroejCoreValidation_testNativeArguments01(jint i1, jint i2, jint i3, jint i4, jint i5, jint i6, jint i7, jint i8, jint i9, jint i10){ + if(i1==0x01020304 && + i2==0x05060708 && + i3==0x090A0B0C && + i4==0x0D0E0F10 && + i5==0x11121314 && + i6==0x15161718 && + i7==0x191A1B1C && + i8==0x1D1E1F20 && + i9==0x21222324 && + i10==0x25262728){ + return 0x292A2B2C; + } + else { + return 0; + } + } + +jlong Java_com_microej_core_tests_MicroejCoreValidation_testNativeArguments02(jlong l1, jlong l2, jlong l3, jlong l4, jlong l5, jlong l6, jlong l7, jlong l8, jlong l9, jlong l10){ + if(l1==0x2D2E2F3031323334ll && + l2==0x35363738393A3B3Cll && + l3==0x3D3E3F4041424344ll && + l4==0x45464748494A4B4Cll && + l5==0x4D4E4F5051525354ll && + l6==0x55565758595A5B5Cll && + l7==0x5D5E5F6061626364ll && + l8==0x65666768696A6B6Cll && + l9==0x6D6E6F7071727374ll && + l10==0x75767778797A7B7Cll){ + return 0x7D7E7F8081828384ll; + } + else { + return 0ll; + } + } + +jlong Java_com_microej_core_tests_MicroejCoreValidation_testNativeArguments03(jint i1, jlong l2, jint i3, jlong l4, jint i5, jlong l6, jint i7, jlong l8, jint i9, jlong l10){ + if(i1==0x85868788 && + l2==0x898A8B8C8D8E8F90ll && + i3==0x91929394 && + l4==0x95969798999A9B9Cll && + i5==0x9D9E9FA0 && + l6==0xA1A2A3A4A5A6A7A8ll && + i7==0xA9AAABAC && + l8==0xADAEAFB0B1B2B3B4ll && + i9==0xB5B6B7B8 && + l10==0xB9BABBBCBDBEBFC0ll){ + return 0xC1C2C3C4C5C6C7C8ll; + } + else { + return 0ll; + } + } + +jfloat Java_com_microej_core_tests_MicroejCoreValidation_testNativeArguments04(jfloat f1, jfloat f2, jfloat f3, jfloat f4, jfloat f5, jfloat f6, jfloat f7, jfloat f8, jfloat f9, jfloat f10){ + if(f1==1.0f && + f2==1.1f && + f3==1.2f && + f4==1.3f && + f5==1.4f && + f6==1.5f && + f7==1.6f && + f8==1.7f && + f9==1.8f && + f10==1.9f){ + return 2.0f; + } + else { + return 0.0f; + } + } + +jdouble Java_com_microej_core_tests_MicroejCoreValidation_testNativeArguments05(jdouble d1, jdouble d2, jdouble d3, jdouble d4, jdouble d5, jdouble d6, jdouble d7, jdouble d8, jdouble d9, jdouble d10){ + if(d1==2.0 && + d2==2.1 && + d3==2.2 && + d4==2.3 && + d5==2.4 && + d6==2.5 && + d7==2.6 && + d8==2.7 && + d9==2.8 && + d10==2.9){ + return 3.0; + } + else { + return 0.0; + } + } + +jdouble Java_com_microej_core_tests_MicroejCoreValidation_testNativeArguments06(jfloat f1, jdouble d2, jfloat f3, jdouble d4, jfloat f5, jdouble d6, jfloat f7, jdouble d8, jfloat f9, jdouble d10){ + if(f1==3.0f && + d2==3.1 && + f3==3.2f && + d4==3.3 && + f5==3.4f && + d6==3.5 && + f7==3.6f && + d8==3.7 && + f9==3.8f && + d10==3.9){ + return 4.0; + } + else { + return 0.0; + } + } diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/cpuload.c b/bsp/projects/nxpvee-ui/main/src/cpuload.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/cpuload.c rename to bsp/projects/nxpvee-ui/main/src/cpuload.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/cpuload_impl_FreeRTOS.c b/bsp/projects/nxpvee-ui/main/src/cpuload_impl_FreeRTOS.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/cpuload_impl_FreeRTOS.c rename to bsp/projects/nxpvee-ui/main/src/cpuload_impl_FreeRTOS.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/fault_handlers.c b/bsp/projects/nxpvee-ui/main/src/fault_handlers.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/fault_handlers.c rename to bsp/projects/nxpvee-ui/main/src/fault_handlers.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/fault_handlers_asm.s b/bsp/projects/nxpvee-ui/main/src/fault_handlers_asm.s similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/fault_handlers_asm.s rename to bsp/projects/nxpvee-ui/main/src/fault_handlers_asm.s diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/interrupts.c b/bsp/projects/nxpvee-ui/main/src/interrupts.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/interrupts.c rename to bsp/projects/nxpvee-ui/main/src/interrupts.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/main.c b/bsp/projects/nxpvee-ui/main/src/main.c similarity index 87% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/main.c rename to bsp/projects/nxpvee-ui/main/src/main.c index 3001ffc..86f3288 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/main.c +++ b/bsp/projects/nxpvee-ui/main/src/main.c @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023-2024 NXP * * SPDX-License-Identifier: BSD-3-Clause * @@ -32,7 +32,7 @@ #include "power_manager.h" -#if (ENABLE_SVIEW == 1) +#if (ENABLE_SYSTEM_VIEW == 1) #include "SEGGER_SYSVIEW.h" #endif @@ -126,7 +126,7 @@ int main(void) { MEJ_LOG_MODULE_INFO(MAIN, "Silicon revision: %X.%X\n", silicon_rev_major, silicon_rev_minor); /* Enable Trace */ -#if (ENABLE_SVIEW == 1) +#if (ENABLE_SYSTEM_VIEW == 1) SEGGER_SYSVIEW_Conf(); trace_platform_initialize(); #endif @@ -135,14 +135,10 @@ int main(void) { TaskHandle_t pvCreatedTask; BaseType_t ret = xTaskCreate(xJavaTaskFunction, "MEJ32 Core Engine", JAVA_TASK_STACK_SIZE, NULL, JAVA_TASK_PRIORITY, &pvCreatedTask); -#if (ENABLE_SVIEW == 1) +#if (ENABLE_SYSTEM_VIEW == 1) SEGGER_SYSVIEW_setMicroJVMTask((U32)pvCreatedTask); #endif vTaskStartScheduler(); } -/* Functions used in Core Validation test */ -#include "sni.h" -jfloat Java_com_microej_core_tests_MicroejCoreValidation_testFloat (jfloat a, jfloat b) {return a * b;} -jdouble Java_com_microej_core_tests_MicroejCoreValidation_testDouble (jdouble a, jdouble b) {return a * b;} diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/microjvm_main.c b/bsp/projects/nxpvee-ui/main/src/microjvm_main.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/microjvm_main.c rename to bsp/projects/nxpvee-ui/main/src/microjvm_main.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/monitor.c b/bsp/projects/nxpvee-ui/main/src/monitor.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/monitor.c rename to bsp/projects/nxpvee-ui/main/src/monitor.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/os_support.c b/bsp/projects/nxpvee-ui/main/src/os_support.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/os_support.c rename to bsp/projects/nxpvee-ui/main/src/os_support.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/stack_overflow_impl_FreeRTOS.c b/bsp/projects/nxpvee-ui/main/src/stack_overflow_impl_FreeRTOS.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/stack_overflow_impl_FreeRTOS.c rename to bsp/projects/nxpvee-ui/main/src/stack_overflow_impl_FreeRTOS.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/time_hardware_timer.c b/bsp/projects/nxpvee-ui/main/src/time_hardware_timer.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/time_hardware_timer.c rename to bsp/projects/nxpvee-ui/main/src/time_hardware_timer.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/trace_platform.c b/bsp/projects/nxpvee-ui/main/src/trace_platform.c similarity index 94% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/trace_platform.c rename to bsp/projects/nxpvee-ui/main/src/trace_platform.c index cf5d04e..ed218b1 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/trace_platform.c +++ b/bsp/projects/nxpvee-ui/main/src/trace_platform.c @@ -96,7 +96,7 @@ void trace_HW_tasks_send_task_list(void) */ void trace_HW_task_start(uint32_t HW_task_id) { -#if (ENABLE_SVIEW == 1) +#if (ENABLE_SYSTEM_VIEW == 1) SEGGER_SYSVIEW_OnTaskStartReady(HW_task_id); #endif } @@ -106,7 +106,7 @@ void trace_HW_task_start(uint32_t HW_task_id) */ void trace_HW_task_stop(uint32_t HW_task_id) { -#if (ENABLE_SVIEW == 1) +#if (ENABLE_SYSTEM_VIEW == 1) U32 currentTaskId = SEGGER_SYSVIEW_currentTaskId; SEGGER_SYSVIEW_OnTaskStartExec(HW_task_id); SEGGER_SYSVIEW_OnTaskStopReady(HW_task_id, 0); diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/tree_version.c.in b/bsp/projects/nxpvee-ui/main/src/tree_version.c.in similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/tree_version.c.in rename to bsp/projects/nxpvee-ui/main/src/tree_version.c.in diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/tree_version.h b/bsp/projects/nxpvee-ui/main/src/tree_version.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/main/src/tree_version.h rename to bsp/projects/nxpvee-ui/main/src/tree_version.h diff --git a/bsp/projects/nxpvee-ui/sdk_makefile/Makefile b/bsp/projects/nxpvee-ui/sdk_makefile/Makefile new file mode 100644 index 0000000..498f8ac --- /dev/null +++ b/bsp/projects/nxpvee-ui/sdk_makefile/Makefile @@ -0,0 +1,16 @@ +# +# Copyright 2023 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# +TARGET=mimxrt595_freertos-bsp +DEVICE=MIMXRT595S_M33 +LS_DEVICE=MIMXRT595S:EVK-MIMXRT595 +ADDRESS=0x08000000 +FLAVOUR=debug + +ifeq ($(strip $(RELEASE)),1) +FLAVOUR=release +endif + +include ../../common/sdk_makefile/Makefile diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/sdk_makefile/jlink_flash.script b/bsp/projects/nxpvee-ui/sdk_makefile/jlink_flash.script similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/sdk_makefile/jlink_flash.script rename to bsp/projects/nxpvee-ui/sdk_makefile/jlink_flash.script diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/simple_gfx_app/src/simple_gfx_app_imp.c b/bsp/projects/nxpvee-ui/simple_gfx_app/src/simple_gfx_app_imp.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/simple_gfx_app/src/simple_gfx_app_imp.c rename to bsp/projects/nxpvee-ui/simple_gfx_app/src/simple_gfx_app_imp.c diff --git a/bsp/sdk_overlay/middleware/vglite/ChangeLogKSDK.txt b/bsp/sdk_overlay/middleware/vglite/ChangeLogKSDK.txt new file mode 100644 index 0000000..c7a7554 --- /dev/null +++ b/bsp/sdk_overlay/middleware/vglite/ChangeLogKSDK.txt @@ -0,0 +1,281 @@ +/*! +@page middleware_log Middleware Change Log + +@section vglite VGLite GPU Driver + The current version of the VGLite GPU Driver is 3.0.15_rev7. + - version 3.0.15_rev7 + - Fixed: + - (MCUX-54842) Fixed build warnings + - version 3.0.15_rev6 + - Fixed: + - Fixed incorrect scissoring issue in single thread mode + - Optimized line stroking to reduce memory consumption + - Extended blit output quality workaround to "vg_lite_blit_rect" + - (IMX-3008) Fixed driver reporting incorrect version number + - (IMX-2848) Allocated path stroking parameters dynamically + - (IMX-3010) Fixed scissoring window check with large tessellation buffers + - Changed: + - (IMX-2907) Removed obsolete "vg_lite_perspective" API + - version 3.0.15_rev5 + - Fixed: + - (IMX-2867) Fixed hang when processing vector paths with zero length + - (IMX-2959) Fixed GPU using garbage data during image filtering + - (IMX-2900) Restructured source code for better single thread & multithread modes maintenance + - Changed: + - (MCUX-52922) Disable GPU auto clock gating by default. Feature can be enabled from build config + - version 3.0.15_rev4 + - Changed: + - (IMX-2900) Renamed build switch for disabling driver multithread support + - version 3.0.15_rev3 + - Fixed: + - Relocated centerX/Y definitions in vg_lite.c + - (IMX-2918) Reduced vg_lite_finish() delay when it has nothing to do + - (IMX-2901) Fixed reversed red and blue channels in colour gradients fill colour + - (IMX-2901) Fixed linear gradient matrix transformation error + - (IMX-2901) Fixed radial gradient render error + - Changed: + - (IMX-2799) Enabled GPU auto clock gating by default + - (IMX-2799) Added build switch to disable GPU auto clock gating + - Added: + - (IMX-2900) Added initial support for single thread mode + - version 3.0.15_rev2 + - Fixed: + - (IMX-2881) Fixed memory leaks in vector path stroking implementation + - (IMX-2863) Fixed stroked polygons rendering issue + - (IMX-2842) Fixed system hang when drawing circular arcs + - (MGG-897) Use OS heap instead of application heap for stroked vector polygons + - (MGG-897) Use OS heap instead of application heap for ciecular arc rendering + - Changed: + - (IMX-2863) Allow users to configure fill colour for stroked & filled vector paths + - version 3.0.15_rev1 + - Fixed: + - (IMX-2844) Fixed missing path descriptor initialization in "vg_lite_init_arc_path" + - (IMX-2837) Fixed arc drawing direction + - (IMX-2811) Added VGPE flush after buffer clear + - Changed: + - (IMX-2835) Optimized storage of radial gradients params to allow memory saving + - Added: + - Added dithering support for RT11xx platforms + - Added color keying support for RT11xx platforms + - (IMX-2817) Added vector path stroking + - (IMX-2692) Added support for HW accelerated linear gradients on RT11xx platforms + - version 3.0.13_rev2 + - Fixed: + - (MGG-793) Fixed clipping issue when using the RT500 blit output quality workaround + - (MGG-830) Disabled RT500 blit output quality workaround for non-affine graphic transformations + - (IMX-2701) Fixed memory leak in vector arc drawing API + - (IMX-2699) Fixed build warnings in vector arc drawing API + - (MGG-836) Fixed the font/text support via main VGLite driver API + - Changed: + - (IMX-1724) Changed image width 16 pixels alignment to stride 16 byte alignment + - (MCUX-46210) Dropped useless "const" qualifier for the "name" attribute of "vg_lite_font_params_t" data structure + - (MGG-836) Reordered "vg_lite_draw_text" API arguments + - version 3.0.13_rev1 + - Fixed: + - (IMX-2577) Fixed support for colour palettes (CLUT) in multithread mode + - (MGG-735) Fixed Elementary library instability caused by using calloc/free in ElmWrapBuffer + - Changed: + - (IMX-2600) Updated "vg_lite_finish" to wait for all frames previously submitted with "vg_lite_flush" + - Aligned "vg_lite_radial_gradient_parameter" data struct with parameters in Elementary EVO object + - Added: + - Added support for drawing vector arcs/circles + - Added support for i.MXRT6Q GPU + - Added support for GCNanoliteV GPU Rev. 0x1322 + - Added vector arcs support in Elementary library + - version 3.0.11_rev3 + - Fixed: + - Fix async event reset after being initialized + - (IMX-2604) Fix polygon's rendering regression in multitasking scenarios + - Avoid "vg_lite_blit" modifying user's transformation matrix + - version 3.0.11_rev2 + - Fixed: + - (MGG-685) Added workaround to improve "blit" output quality for RT500 + - (MCUX-43004) Fixed clipping window regression issue introduced by VGLite 3.0.11.1 + - (MGG-764) Fixed VGLite heap useless splitting of memory nodes + - (MGG-765) Fixed regression issue introduced by VGLite 3.0.11.1 when loading graphic resources using Elementary library + - (IMX-2506) Fixed "vg_lite_update_rad_grad" not checking the result of memory allocation + - (MCUX-42992) Fixed IAR toolchain not recognizing optimization directive + - (MGG-763) Remove risk of out-of-bounds read in "vg_lite_update_rad_grad" function + - Changed: + - (IMX-2527) Improved memory footprint by using a common tessellation buffer for all drawing tasks + - (MGG-712) Restructured OS abstraction layer to allow easier integration with popular OSes + - version 3.0.11_rev1 + - Fixed: + - (IMX-2502) Fixed GPU command buffer overflow when copying context data + - (IMX-2503) Fixed additional colour ring incorrectly appearing at the edge of radial gradients + - (IMX-2487) Fixed risk of memory leak in "vg_lite_upload_path" + - (IMX-2429) Fixed incorrect blending of A4 and A8 images (regression since VGLite 3.0.4.x) + - (MGG-687) Fixed build warning when VG_RENDER_TEXT feature is disabled + - Changed: + - (IMX-2354) Added support for dynamic command buffer size management + - Added: + - (IMX-2435) Added new API function - vg_lite_get_transform_matrix - to calculate parameters for 2D perspective transformations + - (IMX-2411) Added support for radial gradients in Elementary library + - (IMX-2026) Added support for images embedded in EVO data in Elementary library + - (IMX-2026) Added support for patterns embedded in EVO data in Elementary library + - version 3.0.9_rev2 + - Fixed: + - (MCUX-40557) Fixed build warnings + - version 3.0.9_rev1 + - Fixed: + - (MGG-648) Fixed rendered text overlapping issue + - (MGG-650) Fixed memory leak caused by failure to unload RLE font data + - (IMX-2395) Fixed incorrect reporting of indexed images as "supported" for GC355 GPU (RT1170) + - Changed: + - (IMX-2370) Refactored GPU driver HAL and OS layers + - (MGG-646) Configured a vector font as default font + - version 3.0.9 + - Fixed: + - (IMX-2361) Fixed tessellation bounds computation error + - Changed: + - (IMX-2367) Enabled alpha channel premultiplication by default for GC355 GPU (RT1170) + - (IMX-2261) Added Elementary library input data address alignment verification + - Added: + - (IMX-2323) Added support for radial colour gradients for GC355 GPU (RT1170) + - (IMX-2317) Upgraded the Elementary library to be thread safe + - version 3.0.6_rev4 + - Fixed: + - (IMX-2357) Fixed rendering performance degradation since the implementation of the multithread/multicontext support + - (MGG-576) Elementary: Fixed hard fault when resetting translation of EVO object + - (MCUX-38672) Fixed font and text support build warnings + - (MGG-596) Fixed memory leak in raster font loading + - (MGG-596) Font and text support: Fixed out of range memory access in Elementary library + - Changed: + - (MGG-596) "VG_RENDER_TEXT=1" build symbol now required to enable font and text support + - (MGG-594) Updated font and text support to allow easy decoupling from GPU driver and Elementary when not needed + - (MGG-533) Removed "is_tspan" attribute from "vg_lite_font_attributes_t" + - (MGG-533) Added new attribute "tspan_has_dx_dy" to "vg_lite_font_attributes_t" + - (MGG-533) Added new argument "matrix" to "vg_lite_draw_text" API function + - (MGG-592) Renamed "eFontTypes_t" enum to "eFontType_t" + - (MGG-592) Renamed "eFontVectorType" identifier to "eFontTypeVector" + - (MGG-592) Renamed "eFontRasterType" identifier to "eFontTypeRaster" + - (MGG-596) Changed "vg_lite_draw_text" function return value from "int" to "vg_lite_error_t" + - Added: + - (MGG-596) Added "vg_lite_find_font" API function + - (MGG-596) Added 2 new error codes for "vg_lite_error_t": VG_LITE_ALREADY_EXISTS and VG_LITE_NOT_ALIGNED + - (IMX-2357) Allow users to override command queue task priority at build time using QUEUE_TASK_PRIO build symbol + - (MGG-551) Added text wrapping support for vector fonts + - (MGG-533) Added support for text right alignment + - version 3.0.6_rev3 + - Added: + - (MGG-551) Added support for font and text rendering + - version 3.0.6_rev2 + - Fixed: + - (IMX-2292) Fixed command buffer flushing after draw + - (IMX-2293) Fixed copy of register status when command buffer was not full + - (IMX-2305) Fixed scissor window taking no effect + - (IMX-2324) Fixed GPU feature table reset when calling "vg_lite_close" + - (IMX-2358) Fixed misuse of address operator in checking colour channel premultiplication flag + - (MGG-542) Cleaned up useless "memset" in "vg_lite_init" + - version 3.0.6_rev1 + - Fixed: + - (IMX-2295) Initialize task context to zero in vg_lite_init() + - version 3.0.6 + - Fixed: + - (MGG-525) Fixed "vg_lite_init_path" not properly initializating the "path" data structure + - Changed: + - (IMX-2255) Updated "vg_lite_set_scissor" arguments to (x, y, width, height) instead of (x0, y0, x1, y1) + - Added: + - (IMX-2104) Added API to enable/disable colour channel pre-multiplication at runtime on RT1170 + - version 3.0.5 + - Fixed: + - (IMX-2252) Reset global mutex when it is destroyed + - (IMX-2252) Fixed reset of task local context in vg_lite_close() + - Changed: + - (MGG-333) Enabled scissoring for GC255 GPU (i.MXRT500) + - Added: + - (IMX-1729) Added support for drawing from multiple threads + - version 3.0.4_rev5 + - Changed: + - (IMX-2104) Disabled by default colour channel pre-multiplication on RT1170 platform + - (MGG-517) Updated "vg_lite_draw_pattern" function to return VG_LITE_NOT_SUPPORT for A4/A8 patterns + - Fixed: + - (IMX-2155) Fixed hard coded image mode in "vg_lite_draw_pattern" + - (IMX-2153) Updated "vg_lite_draw_pattern" to take into account pattern transparency + - (KPSDK-37093) Elementary library - Fixed bad free in "load_evo" + - (KPSDK-37093) Elementary library - Avoid resource leak in "ElmCreateBuffer" + - version 3.0.4_rev4 + - Fixed: + - Fixed empty function argument lists definition for scissoring related API functions + - (IMX-1995) Extended RT500 image rotation fix to vg_lite_blit_rect, vg_lite_draw_pattern + - (IMX-1995) Isolated RT500 image rotation fix effects to RT500 platform only + - version 3.0.4_rev3 + - Fixed: + - (IMX-1995) Compensated for RT500 image shift effect when rotation is approaching multiples of 90 dgs + - version 3.0.4_rev2 + - Fixed: + - Fixed integration issue of "vg_lite_mem_avail" API + - version 3.0.4_rev1 + - Changed: + - (IMX-1768) Enabled users to query, at runtime, the support for VG_LITE_UPPER draw quality + - Fixed: + - (IMX-2074) Fixed GPU exception handling issue + - Added: + - (IMX-2045) Added API to provide available heap memory + - version 3.0.4 + - Changed: + - (IMX-1957) Enabled users to query, at runtime, the support for BORDER_CULLING and SCISSOR features + - Enable users to query, at runtime, the support for RGBA 2 bits-per-channel image formats + - Fixed: + - (IMX-1934) Fixed image stride alignment verification for TILED images + - Fix GC355 GPU (i.MXRT1170) draw error when tessellation window width is not aligned to 128 + - Added: + - (MGG-333) Added support for GC355 GPU (i.MXRT1170) scissoring + - version 3.0.1_rev1 + - Fixed: + - (MGG-250) Fixed GPU hang after a random time (mostly reproduced on RT1170 platforms) + - (KPSDK-33132) Fixed Elementary library memory leaks in case of failed EBO loading + - (MGG-336) Allow use of blend modes not affected by the border culling limitation + - (MGG-18) Fixed Elementary library memory leaks when loading EVO/EBO/EGO objects + - (MGG-353) Fixed linear colour gradient rendering error when loading EVOs using the Elementary library + - version 3.0.1 + - Changed: + - Removed "vg_lite_blit2" API function due to lack of hardware support + - Removed "vg_lite_scanline" API function due to lack of harware support + - Aggregated "vg_lite_error.h" API header file content into "vg_lite.h" + - Aggregated "vg_lite_features.h" API header file content into "vg_lite.h" + - Aggregated "vg_lite_matrix.h" API header file content into "vg_lite.h" + - Aggregated "vg_lite_path.h" API header file content into "vg_lite.h" + - Aggregated "vg_lite_util.h" API header file content into "vg_lite.h" + - (IMX-1861) Added return code to the "vg_lite_flush" API function + - Changed VGLite GPU driver license from proprietary to MIT + - Fixed: + - Fixed definition of "elm_alloc" function in Elementary toolkit + - (IMX-1869) Fixed initialization of aligned bytes in the command buffer + - (IMX-1821) Fixed inverted background colours when using "vg_lite_draw_pattern" + - Fixed hang when calling "vg_lite_flush" repeatedly + - (IMX-1861) Fix propagation of return codes from "stall", "submit", "vg_lite_flush" function calls + - version 2.0.14_rev1 + - Changed: + - (IMX-1809) Fixed misspelling of "vg_lite_buffer_transparency_mode" + - (IMX-1778) Added verification of colour gradients parameters + - (IMX-1813) Added return code to the "vg_lite_hal_allocate_contiguous" function + - (MGG-204) Added return code to "vg_lite_finish" + - Fixed: + - (IMX-1808) Fixed "vg_lite_blit" failure on dynamically allocated buffers + - (IMX-1773) Fixed failure to create 16 colours gradients + - (IMX-1790) Fixed driver incorrectly reporting available heap space + - (IMX-1810) Fixed verification of raster image stride alignment + - (IMX-1810) Fixed verification of raster image colour depth + - (IMX-1816) Fixed "vg_lite_close" not releasing memory allocated from OS heap + - (MGG-201) Fixed hard fault caused by command buffer management + - (MGG-202) Fixed "vg_lite_hal_wait_interrupt" function ignoring the timeout + - (MGG-203) Fixed "vg_lite_draw" function always returning success + - version 2.0.13_rev2 + - Fixed: + - (MGG-102) Fixed incorrect colour gradient clipping issue when using "vg_lite_draw_gradient" API + - (MGG-140) Fixed "vg_lite_draw_gradient" error when gradient is not covering the entire shape + - version 2.0.13_rev1 + - Added: + - (MGG-88) Support for operating with BGRA2222, ABGR2222, ARGB2222 type images + - (MGG-88) Support for operating with ABGR4444, ARGB4444 type images + - (MGG-88) Support for operating with ABGR8888, ARGB8888 type images + - (MGG-88) Support for operating with XBGR8888, XRGB8888 type images + - (MGG-52) Improved GPU bus error reporting by using weak functions + - Changed: + - (MGG-66) Restructured GPU driver by exposing the HAL source code for easier integration with operating systems + - Fixed: + - (MGG-72) Fixed rough edges of vector artefacts when using the "vg_lite_draw_pattern" API + - (MGG-58) Fixed "vg_lite_blit_rect" API not supporting a zero Y coordinate + - version 2.0.13_rev0 +*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/LICENSE.txt b/bsp/sdk_overlay/middleware/vglite/LICENSE.txt similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/LICENSE.txt rename to bsp/sdk_overlay/middleware/vglite/LICENSE.txt diff --git a/bsp/sdk_overlay/middleware/vglite/VGLite/nxp_support.c b/bsp/sdk_overlay/middleware/vglite/VGLite/nxp_support.c new file mode 100644 index 0000000..d024b81 --- /dev/null +++ b/bsp/sdk_overlay/middleware/vglite/VGLite/nxp_support.c @@ -0,0 +1,35 @@ +/**************************************************************************** +* +* The MIT License (MIT) +* +* Copyright 2023 NXP +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to +* deal in the Software without restriction, including without limitation the +* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +* sell copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +* IN THE SOFTWARE. +* +*****************************************************************************/ + +#include "nxp_support.h" + +#if (defined(__REDLIB__)) +float hypotf (float x, float y) +{ + return sqrtf(x*x + y*y); +} +#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/rtos/vg_lite_os.c b/bsp/sdk_overlay/middleware/vglite/VGLite/rtos/vg_lite_os.c similarity index 91% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/rtos/vg_lite_os.c rename to bsp/sdk_overlay/middleware/vglite/VGLite/rtos/vg_lite_os.c index dbf3cbf..12882c5 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/rtos/vg_lite_os.c +++ b/bsp/sdk_overlay/middleware/vglite/VGLite/rtos/vg_lite_os.c @@ -1,16 +1,18 @@ #include "vg_lite_os.h" #include "FreeRTOS.h" -#if !defined(VG_DRIVER_SINGLE_THREAD) #include "semphr.h" +#if !defined(VG_DRIVER_SINGLE_THREAD) #include "task.h" #include "queue.h" +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ #include "vg_lite_hw.h" #include "vg_lite_hal.h" /* If bit31 is activated this indicates a bus error */ #define IS_AXI_BUS_ERR(x) ((x)&(1U << 31)) +#if !defined(VG_DRIVER_SINGLE_THREAD) #define ISR_WAIT_TIME 0x1FFFF #define MAX_MUTEX_TIME 100 #define TASK_WAIT_TIME 20 @@ -51,9 +53,10 @@ static vg_lite_os_t os_obj = {0}; SemaphoreHandle_t semaphore[TASK_LENGTH] = {NULL}; SemaphoreHandle_t command_semaphore = NULL; +uint32_t curContext; +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ SemaphoreHandle_t int_queue; volatile uint32_t int_flags; -uint32_t curContext; void __attribute__((weak)) vg_lite_bus_error_handler() { @@ -65,6 +68,7 @@ void __attribute__((weak)) vg_lite_bus_error_handler() return; } +#if !defined(VG_DRIVER_SINGLE_THREAD) /* command queue function */ void command_queue(void * parameters) { @@ -181,6 +185,7 @@ void vg_lite_os_reset_tls() { vTaskSetThreadLocalStoragePointer(NULL, 0, NULL); } +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ void vg_lite_os_sleep(uint32_t msec) { @@ -189,12 +194,15 @@ void vg_lite_os_sleep(uint32_t msec) int32_t vg_lite_os_initialize(void) { +#if !defined(VG_DRIVER_SINGLE_THREAD) static int task_number = 0; BaseType_t ret; +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ int_queue = xSemaphoreCreateBinary(); int_flags = 0; +#if !defined(VG_DRIVER_SINGLE_THREAD) if(mutex == NULL) { mutex = xSemaphoreCreateMutex(); @@ -221,18 +229,22 @@ int32_t vg_lite_os_initialize(void) return VG_LITE_SUCCESS; } } +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ return VG_LITE_SUCCESS; } void vg_lite_os_deinitialize(void) { /* TODO: Remove clock. */ +#if !defined(VG_DRIVER_SINGLE_THREAD) vSemaphoreDelete(mutex); mutex = 0; +#endif /* VG_DRIVER_SINGLE_THREAD */ vSemaphoreDelete(int_queue); /* TODO: Remove power. */ } +#if !defined(VG_DRIVER_SINGLE_THREAD) int32_t vg_lite_os_lock() { if(mutex == NULL) @@ -302,6 +314,7 @@ int32_t vg_lite_os_wait(uint32_t timeout, vg_lite_os_async_event_t *event) } return VG_LITE_TIMEOUT; } +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ void vg_lite_os_IRQHandler(void) { @@ -359,6 +372,7 @@ int32_t vg_lite_os_wait_interrupt(uint32_t timeout, uint32_t mask, uint32_t * va #endif } +#if !defined(VG_DRIVER_SINGLE_THREAD) int32_t vg_lite_os_init_event(vg_lite_os_async_event_t *event, uint32_t semaphore_id, int32_t state) diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/rtos/vg_lite_os.h b/bsp/sdk_overlay/middleware/vglite/VGLite/rtos/vg_lite_os.h similarity index 82% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/rtos/vg_lite_os.h rename to bsp/sdk_overlay/middleware/vglite/VGLite/rtos/vg_lite_os.h index d527b76..6b852f2 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/rtos/vg_lite_os.h +++ b/bsp/sdk_overlay/middleware/vglite/VGLite/rtos/vg_lite_os.h @@ -2,7 +2,8 @@ #define _VG_LITE_OS_H #include -#if !defined(SINGLE_THREAD_DRIVER) + +#if !defined(VG_DRIVER_SINGLE_THREAD) #define vg_lite_os_set_event_state(event, state) (event)->signal = state @@ -30,7 +31,8 @@ int32_t vg_lite_os_set_tls(void* tls); @brief Get the current task’s thread local storage array. */ void * vg_lite_os_get_tls( ); -#endif /* not defined(SINGLE_THREAD_DRIVER) */ + +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ /*! @brief Memory allocate. @@ -42,12 +44,12 @@ void * vg_lite_os_malloc(uint32_t size); */ void vg_lite_os_free(void * memory); -#if !defined(SINGLE_THREAD_DRIVER) +#if !defined(VG_DRIVER_SINGLE_THREAD) /*! @brief Reset the value in a task’s thread local storage array. */ void vg_lite_os_reset_tls(); - +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ /*! @brief sleep a number of milliseconds. @@ -64,6 +66,7 @@ int32_t vg_lite_os_initialize(); */ void vg_lite_os_deinitialize(); +#if !defined(VG_DRIVER_SINGLE_THREAD) /*! @brief Mutex semaphore take. */ @@ -83,17 +86,19 @@ int32_t vg_lite_os_submit(uint32_t context, uint32_t physical, uint32_t offset, @brief Wait for the current command buffer to be executed. */ int32_t vg_lite_os_wait(uint32_t timeout, vg_lite_os_async_event_t *event); +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ /*! @brief IRQ Handler. */ -void vg_lite_os_IRQHandler(); +void vg_lite_os_IRQHandler(void); /*! @brief Wait until an interrupt from the VGLite graphics hardware has been received. */ int32_t vg_lite_os_wait_interrupt(uint32_t timeout, uint32_t mask, uint32_t * value); +#if !defined(VG_DRIVER_SINGLE_THREAD) /*! @brief */ @@ -121,5 +126,5 @@ int32_t vg_lite_os_signal_event(vg_lite_os_async_event_t *event); */ int8_t vg_lite_os_query_context_switch(uint32_t context); +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ #endif -#endif /* not defined(SINGLE_THREAD_DRIVER) */ diff --git a/bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite.c b/bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite.c new file mode 100644 index 0000000..c563ff6 --- /dev/null +++ b/bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite.c @@ -0,0 +1,10924 @@ +/**************************************************************************** +* +* The MIT License (MIT) +* +* Copyright 2012 - 2020 Vivante Corporation, Santa Clara, California. +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Copyright 2020-2023 MicroEJ Corp. This file has been modified by MicroEJ Corp. +* 1. Add a weak the function "vg_lite_draw_notify_render_area()" +* 2. Add "vg_lite_get_scissor()" +* +*****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include "vg_lite.h" +#include "vg_lite_kernel.h" +#if !defined(VG_DRIVER_SINGLE_THREAD) +#include "vg_lite_os.h" +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ +#if (VG_RENDER_TEXT==1) +#include "vg_lite_text.h" +#endif /* VG_RENDER_TEXT */ +#include "vg_lite_flat.h" + +/* + * Stop IAR compiler from warning about implicit conversions from float to + * double + */ +#if (defined(__ICCARM__)) +#pragma diag_suppress = Pa205 +#endif + +/* This is the function to call from the VGLite driver to interface with the GPU. */ +vg_lite_error_t vg_lite_kernel(vg_lite_kernel_command_t command, void * data); + + +/*** Command buffer dump ***/ +#ifndef DUMP_COMMAND +#define DUMP_COMMAND 0 +#endif + +#ifndef DUMP_IMAGE +#define DUMP_IMAGE 0 + +#else +#ifndef DUMP_COMMAND +#define DUMP_COMMAND 0 +#endif + +#ifndef DUMP_IMAGE +#define DUMP_IMAGE 0 +#endif +#endif + +#define VG_TARGET_FC_DUMP 0 + +/* Fast clear is not used by default,if SOC should use this ,set this macro to 1. */ +#ifndef VG_TARGET_FAST_CLEAR + #define VG_TARGET_FAST_CLEAR 0 +#endif /* VG_TARGET_FAST_CLEAR */ + +#if DUMP_COMMAND || DUMP_IMAGE +#ifdef __linux__ +#include +#endif +#endif + +#if defined(VG_DRIVER_SINGLE_THREAD) +/*** Global Context Access ***/ +#define GET_CONTEXT() &s_context +#endif /* VG_DRIVER_SINGLE_THREAD */ + +/*** Command buffer configurations, double buffer support ***/ +#define VG_LITE_COMMAND_BUFFER_SIZE (64 << 10) +#define CMDBUF_BUFFER(context) (context).command_buffer[(context).command_buffer_current] +#define CMDBUF_INDEX(context) (context).command_buffer_current +#define CMDBUF_SIZE(context) (context).command_buffer_size +#define CMDBUF_OFFSET(context) (context).command_offset[(context).command_buffer_current] +#define CMDBUF_SWAP(context) (context).command_buffer_current = \ + ((context).command_buffer_current + 1) % CMDBUF_COUNT + +#if !defined(VG_DRIVER_SINGLE_THREAD) +#ifndef CMDBUF_IN_QUEUE +#define CMDBUF_IN_QUEUE(context, id) \ + (vg_lite_os_event_state(&(context)->async_event[(id)]) == VG_LITE_IN_QUEUE) +#endif + +#define RESERVE_BYTES_IN_CMDBUF(context) \ + {\ + ((uint32_t *) (CMDBUF_BUFFER((context)) + CMDBUF_OFFSET((context))))[0] = VG_LITE_STATE(0x0a00);\ + ((uint32_t *) (CMDBUF_BUFFER((context)) + CMDBUF_OFFSET((context))))[1] = 0;\ + CMDBUF_OFFSET((context)) += 8;\ + } +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + +#define VG_LITE_RETURN_ERROR(func) \ +if ((error = func) != VG_LITE_SUCCESS) \ +return error + +#define VG_LITE_BREAK_ERROR(func) \ +if ((error = func) != VG_LITE_SUCCESS) \ +break + +#define VG_LITE_ERROR_HANDLER(func) \ +if ((error = func) != VG_LITE_SUCCESS) \ +goto ErrorHandler + +/*** Command macros ***/ + +#define VG_LITE_END(interrupt) (0x00000000 | interrupt) +#define VG_LITE_SEMAPHORE(id) (0x10000000 | id) +#define VG_LITE_STALL(id) (0x20000000 | id) +#define VG_LITE_STATE(address) (0x30010000 | address) +#define VG_LITE_STATES(count, address) (0x30000000 | ((count) << 16) | address) +#define VG_LITE_DATA(count) (0x40000000 | count) +#define VG_LITE_CALL(count) (0x60000000 | count) +#define VG_LITE_RETURN() (0x70000000) +#define VG_LITE_NOP() (0x80000000) + +/*** Shortcuts. ***/ +#define A(color) (color) >> 24 +#define R(color) ((color) & 0x00ff0000) >> 16 +#define G(color) ((color) & 0x0000ff00) >> 8 +#define B(color) ((color) & 0xff) +#define ARGB(a, r, g, b) ((a) << 24) | ((r) << 16) | ((g) << 8 ) | (b) +#define ARGB4(a, r, g, b) (((a) & 0xf0) << 8) | (((r) & 0xf0) << 4) | (((g) & 0xf0)) | ((b) >> 4) + +#define FC_BURST_BYTES 64 +#define FC_BIT_TO_BYTES 64 + +#define MIN(a, b) ((a) > (b) ? (b) : (a)) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) + +static uint32_t command_buffer_size = VG_LITE_COMMAND_BUFFER_SIZE; + +#define FORMAT_ALIGNMENT(stride,align) \ + { \ + if((stride) % (align) != 0) \ + return VG_LITE_INVALID_ARGUMENT; \ + return VG_LITE_SUCCESS; \ + } + +#define DEST_ALIGNMENT_LIMITATION 64 /* To match hardware alignment requirement */ +#if !defined(VG_DRIVER_SINGLE_THREAD) +#define TS_STATE_COUNT 20 /* Initial state count for tessellation buffer. */ +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + +#define MATRIX_ROWS 3 +#define GET_MATRIX_VALUES(Pointer) ((float *) (Pointer)) +#define MAT(Matrix, Row, Column) (GET_MATRIX_VALUES(Matrix)[Row * MATRIX_ROWS + Column]) + +#define COLOR_FROM_RAMP(ColorRamp) (((vg_lite_float_t *) ColorRamp) + 1) +#define CLAMP(x, min, max) (((x) < (min)) ? (min) : \ + ((x) > (max)) ? (max) : (x)) +#define LERP(v1, v2, w) ((v1) * (w) + (v2) * (1.0f - (w))) + +#define PI 3.141592653589793238462643383279502f +#define SINF(x) ((vg_lite_float_t) sin(x)) +#define COSF(x) ((vg_lite_float_t) cos(x)) +#define FABSF(x) ((vg_lite_float_t) fabs(x)) +#define SQRTF(x) ((vg_lite_float_t) sqrt(x)) +#define CLAMP(x, min, max) (((x) < (min)) ? (min) : \ + ((x) > (max)) ? (max) : (x)) +#define ACOSF(x) ((vg_lite_float_t) acos(x)) +#define FMODF(x, y) ((vg_lite_float_t) fmod((x), (y))) +#define CEILF(x) ((vg_lite_float_t) ceil(x)) +#define FALSE 0 +#define TURE 1 +#define SIZEOF(a) \ +( \ + (size_t) (sizeof(a)) \ +) + +typedef uintptr_t UINTPTR_T; + +#define PTR2SIZE(p) \ +( \ + (UINTPTR_T) (p) \ +) + +#define GETINCREMENT(pointer, datatype_size) \ + (datatype_size - (PTR2SIZE(pointer) & (datatype_size - 1))) + +#define SKIPTODATA(pointer, datatype_size, SIZE) \ + /* Determine the increment value. */ \ + increment = GETINCREMENT(pointer, datatype_size); \ + /* Skip to the data. */ \ + pointer += increment; \ + SIZE -= increment + +#define VGSL_GETVALUE(X) \ + X = get_value(data_pointer); \ + data_pointer += data_type_size; \ + size -= data_type_size + +#define VGSL_GETCOORDXY(X, Y) \ + VGSL_GETVALUE(X); \ + VGSL_GETVALUE(Y); \ + if (is_relative) { X += ox; Y += oy; } + +#define FLOAT_EPSILON 0.001f + +#define SWING_NO 0 +#define SWING_OUT 1 +#define SWING_IN 2 + +/* Point curve type for generated stroke path. */ +#define CURVE_LINE 0 +#define CURVE_QUAD_CONTROL 1 +#define CURVE_QUAD_ANCHOR 2 +#define CURVE_ARC_SCCW 3 +#define CURVE_ARC_SCCW_HALF 4 + +#define FLOAT_PI 3.141592654f +#define FLOAT_PI_TWO 6.283185307f +#define FLOAT_PI_THREE_QUARTER 2.356194490f +#define FLOAT_PI_HALF 1.570796327f +#define FLOAT_PI_QUARTER 0.7853981634f +#define FLOAT_PI_EIGHTH 0.3926990817f +/* cos(PI/8) */ +#define FLOAT_COS_PI_EIGHTH 0.9238795325f + +#define centerX tangentX +#define centerY tangentY + +#define FLOAT_DIFF_EPSILON 0.125f +#define FLOAT_SWING_CENTER_RANGE 0.125f +#define FLOAT_ANGLE_EPSILON 0.0045f +#define FLOAT_ANGLE_EPSILON_COS 0.99999f +#define FLOAT_MIN_ARC_ANGLE 0.044f +#define FLOAT_MIN_ARC_ANGLE_COS 0.999f +/* Float constants. */ +#define gcvMAX_POS_FLOAT ((vg_lite_float_t) 3.4028235e+038) +#define gcvMAX_NEG_FLOAT ((vg_lite_float_t) -3.4028235e+038) +#define FLOAT_MIN gcvMAX_NEG_FLOAT +#define FLOAT_MAX gcvMAX_POS_FLOAT + +#define FLOAT_FAT_LINE_WIDTH 2.5f + +/* Point flatten type for flattened line segments. */ +#define vgcFLATTEN_NO 0 +#define vgcFLATTEN_START 1 +#define vgcFLATTEN_MIDDLE 2 +#define vgcFLATTEN_END 3 + +/* Command size calculation shortcuts. */ +#define COMMANDSIZE(CoordinateCount, CoordinateType) \ + ((1+CoordinateCount) * SIZEOF(CoordinateType)) + +#define ABS(x) (((x) < 0) ? -(x) : (x)) +#define EPS 2.2204460492503131e-14 +#if !defined(VG_DRIVER_SINGLE_THREAD) +/* VG:24 + TS:28 + IM:345 + PE:9 + RS:16 +Debug:2 */ +#define STATES_COUNT 424 +/* STATES_COUNT size + return command size */ +#define CONTEXT_BUFFER_SIZE STATES_COUNT * 2 * 4 + 8 +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + +#define UPDATE_BOUNDING_BOX(bbx, point) \ + do { \ + if ((point).x < (bbx).x) { \ + (bbx).width += (bbx).x - (point).x; \ + (bbx).x = (point).x; \ + } \ + if ((point).y < (bbx).y) { \ + (bbx).height += (bbx).y - (point).y; \ + (bbx).y = (point).y; \ + } \ + if ((point).x > (bbx).x + (bbx).width) \ + (bbx).width = (point).x - (bbx).x; \ + if ((point).y > (bbx).y + (bbx).height) \ + (bbx).height = (point).y - (bbx).y; \ + } while(0) + +typedef vg_lite_float_t FLOATVECTOR4[4]; + +typedef struct vg_lite_ftable { + uint32_t ftable[gcFEATURE_COUNT]; + uint32_t ftflag; +} vg_lite_ftable_t; + +#if !defined(VG_DRIVER_SINGLE_THREAD) +typedef struct vg_lite_states { + uint32_t state; + uint8_t init; +}vg_lite_states_t; + +typedef struct vg_lite_hardware { + vg_lite_states_t hw_states[STATES_COUNT]; +} vg_lite_hardware_t; + +static vg_lite_hardware_t hw = {0}; +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + +typedef struct vg_lite_context { + vg_lite_kernel_context_t context; + vg_lite_capabilities_t capabilities; + uint8_t * command_buffer[CMDBUF_COUNT]; + uint32_t command_buffer_size; + uint32_t command_offset[CMDBUF_COUNT]; + uint32_t command_buffer_current; +#if !defined(VG_DRIVER_SINGLE_THREAD) + uint8_t * context_buffer[CMDBUF_COUNT]; + uint32_t context_buffer_size; + uint32_t context_buffer_offset[CMDBUF_COUNT]; +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + vg_lite_tsbuffer_info_t tsbuffer; + vg_lite_buffer_t * rtbuffer; /* DDRLess: this is used as composing buffer. */ + +#if VG_TARGET_FAST_CLEAR + vg_lite_buffer_t fcBuffer; /* Buffer used for fast clear cache. */ + uint32_t clearValue; +#endif + + uint32_t scissor_enabled; +#if defined(VG_DRIVER_SINGLE_THREAD) + uint32_t scissor_dirty; /* Indicates whether scissor states are changed or not. e.g., scissors[4] or scissor_enabled. */ +#endif /* VG_DRIVER_SINGLE_THREAD */ + int32_t scissor[4]; /* Scissor area: x, y, width, height. */ + +#if !defined(VG_DRIVER_SINGLE_THREAD) + uint32_t start_offset; + uint32_t end_offset; + uint32_t ts_init; /* Indicates whether tessellation buffer states are initialized or not. */ + uint32_t ts_record[TS_STATE_COUNT]; /* Tessellation buffer initial states record. */ + uint32_t ts_init_used; + uint32_t ts_init_use; + uint32_t ts_dirty; + +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + + uint32_t chip_id; + uint32_t chip_rev; + + uint32_t premultiply_enabled; + +#if defined(VG_DRIVER_SINGLE_THREAD) + uint32_t premultiply_dirty; + uint8_t init; +#else + uint32_t semaphore_id; + + uint32_t * colors[4]; /* index colors. */ + uint32_t clut_dirty[4]; /* clut dirty flag. */ + uint32_t index_format; /* check if use index. */ + uint32_t clut_used[4]; /* check if used index. */ +#endif /* VG_DRIVER_SINGLE_THREAD */ + vg_lite_ftable_t s_ftable; +} vg_lite_context_t; + +#if !defined(VG_DRIVER_SINGLE_THREAD) +typedef struct vg_lite_tls{ + /* currently just contains struct vg_lite_context_t */ + vg_lite_context_t t_context; +}vg_lite_tls_t; +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + +typedef struct vg_lite_feature_database{ + uint32_t chip_id; + uint32_t chip_version; + uint32_t cid; + uint32_t vg_im_index_format:1; + uint32_t vg_pe_premultiply:1; + uint32_t vg_border_culling:1; + uint32_t vg_rgba2_format:1; + uint32_t vg_quality_8x:1; + uint32_t vg_radial_gradient:1; + uint32_t vg_linear_gradient_ext:1; + uint32_t vg_dither:1; + uint32_t vg_color_key:1; +} vg_lite_feature_database_t; + +static vg_lite_feature_database_t VGFeatureInfos[] = { + /* vg255 */ + { + GPU_CHIP_ID_GCNanoliteV, /* ChipID */ + 0x1311, /* ChipRevision */ + 0x404, /* CID */ + 0x0, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ + 0x0, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ + 0x1, /* gcFEATURE_BIT_VG_BORDER_CULLING */ + 0x1, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ + 0X0, /* gcFEATURE_BIT_VG_QUALITY_8X */ + 0X0, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ + 0x0, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ + 0x0, /* gcFEATURE_BIT_VG_DITHER */ + 0x0, /* gcFEATURE_BIT_VG_COLOR_KEY */ + }, + /* vg255 */ + { + GPU_CHIP_ID_GCNanoliteV, /* ChipID */ + 0x1311, /* ChipRevision */ + 0x40a, /* CID */ + 0x1, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ + 0x0, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ + 0x1, /* gcFEATURE_BIT_VG_BORDER_CULLING */ + 0x1, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ + 0X1, /* gcFEATURE_BIT_VG_QUALITY_8X */ + 0X0, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ + 0x0, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ + 0x0, /* gcFEATURE_BIT_VG_DITHER */ + 0x0, /* gcFEATURE_BIT_VG_COLOR_KEY */ + }, + /* vg255 */ + { + GPU_CHIP_ID_GCNanoliteV, /* ChipID */ + 0x1311, /* ChipRevision */ + 0x40b, /* CID */ + 0x1, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ + 0x0, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ + 0x1, /* gcFEATURE_BIT_VG_BORDER_CULLING */ + 0x1, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ + 0X1, /* gcFEATURE_BIT_VG_QUALITY_8X */ + 0X0, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ + 0x0, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ + 0x0, /* gcFEATURE_BIT_VG_DITHER */ + 0x0, /* gcFEATURE_BIT_VG_COLOR_KEY */ + }, + /* vg255 */ + { + GPU_CHIP_ID_GCNanoliteV, /* ChipID */ + 0x1311, /* ChipRevision */ + 0x40d, /* CID */ + 0x1, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ + 0x0, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ + 0x1, /* gcFEATURE_BIT_VG_BORDER_CULLING */ + 0x1, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ + 0X1, /* gcFEATURE_BIT_VG_QUALITY_8X */ + 0X0, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ + 0x0, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ + 0x0, /* gcFEATURE_BIT_VG_DITHER */ + 0x0, /* gcFEATURE_BIT_VG_COLOR_KEY */ + }, + /* vg255 */ + { + GPU_CHIP_ID_GCNanoliteV, /* ChipID */ + 0x1322, /* ChipRevision */ + 0x403, /* CID */ + 0x1, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ + 0x0, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ + 0x1, /* gcFEATURE_BIT_VG_BORDER_CULLING */ + 0x1, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ + 0X1, /* gcFEATURE_BIT_VG_QUALITY_8X */ + 0X0, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ + 0x0, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ + 0x0, /* gcFEATURE_BIT_VG_DITHER */ + 0x0, /* gcFEATURE_BIT_VG_COLOR_KEY */ + }, + /* vg355 */ + { + GPU_CHIP_ID_GC355, /* ChipID */ + 0x1217, /* ChipRevision */ + 0x408, /* CID */ + 0x0, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ + 0x1, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ + 0x0, /* gcFEATURE_BIT_VG_BORDER_CULLING */ + 0x0, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ + 0X0, /* gcFEATURE_BIT_VG_QUALITY_8X */ + 0X1, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ + 0x1, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ + 0x1, /* gcFEATURE_BIT_VG_DITHER */ + 0x0, /* gcFEATURE_BIT_VG_COLOR_KEY */ + }, + /* vg355 */ + { + GPU_CHIP_ID_GC355, /* ChipID */ + 0x1216, /* ChipRevision */ + 0x0, /* CID */ + 0x0, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ + 0x1, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ + 0x0, /* gcFEATURE_BIT_VG_BORDER_CULLING */ + 0x0, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ + 0X0, /* gcFEATURE_BIT_VG_QUALITY_8X */ + 0X1, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ + 0x1, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ + 0x1, /* gcFEATURE_BIT_VG_DITHER */ + 0x0, /* gcFEATURE_BIT_VG_COLOR_KEY */ + }, + /* vg355 */ + { + GPU_CHIP_ID_GC355, /* ChipID */ + 0x1215, /* ChipRevision */ + 0x0, /* CID */ + 0x0, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ + 0x1, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ + 0x0, /* gcFEATURE_BIT_VG_BORDER_CULLING */ + 0x0, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ + 0X0, /* gcFEATURE_BIT_VG_QUALITY_8X */ + 0X1, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ + 0x1, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ + 0x1, /* gcFEATURE_BIT_VG_DITHER */ + 0x1, /* gcFEATURE_BIT_VG_COLOR_KEY */ + } +}; + +#if defined(VG_DRIVER_SINGLE_THREAD) +vg_lite_context_t s_context = {0}; +#endif /* VG_DRIVER_SINGLE_THREAD */ + +#if DUMP_COMMAND +FILE * fp; +char filename[30]; +#endif + +int submit_flag = 0; + +static vg_lite_float_t _GetS8_NS_NB(int8_t * Data) +{ + int8_t x0 = *((int8_t *) Data); + vg_lite_float_t x = (vg_lite_float_t) x0; + + return x; +} + +static vg_lite_float_t _GetS16_NS_NB(int8_t * Data) +{ + int16_t x0 = *((int16_t *) Data); + vg_lite_float_t x = (vg_lite_float_t) x0; + + return x; +} + +static vg_lite_float_t _GetS32_NS_NB(int8_t * Data) +{ + int32_t x0 = *((int32_t *) Data); + vg_lite_float_t x = (vg_lite_float_t) x0; + + return x; +} + +static vg_lite_float_t _GetF_NS_NB(int8_t * Data) +{ + vg_lite_float_t x = *((vg_lite_float_t *) Data); + + return x; +} + +typedef vg_lite_float_t (* vg_value_getter) (int8_t * Data); + +typedef struct vg_lite_control_coord +{ + vg_lite_float_t startX; + vg_lite_float_t startY; + vg_lite_float_t lastX; + vg_lite_float_t lastY; + vg_lite_float_t controlX; + vg_lite_float_t controlY; +} +vg_lite_control_coord_t; + +static uint32_t _commandSize_float[] = +{ + COMMANDSIZE(0, vg_lite_float_t), /* 0: END */ + COMMANDSIZE(0, vg_lite_float_t), /* 1: CLOSE */ + COMMANDSIZE(2, vg_lite_float_t), /* 2: MOVE */ + COMMANDSIZE(2, vg_lite_float_t), /* 3: MOVE_REL */ + COMMANDSIZE(2, vg_lite_float_t), /* 4: LINE */ + COMMANDSIZE(2, vg_lite_float_t), /* 5: LINE_REL */ + COMMANDSIZE(4, vg_lite_float_t), /* 6: QUAD */ + COMMANDSIZE(4, vg_lite_float_t), /* 7: QUAD_REL */ + COMMANDSIZE(6, vg_lite_float_t), /* 8: CUBIC */ + COMMANDSIZE(6, vg_lite_float_t), /* 9: CUBIC_REL */ + COMMANDSIZE(5, vg_lite_float_t), /* 10: SCCWARC */ + COMMANDSIZE(5, vg_lite_float_t), /* 11: SCCWARC_REL */ + COMMANDSIZE(5, vg_lite_float_t), /* 12: SCWARC */ + COMMANDSIZE(5, vg_lite_float_t), /* 13: SCWARC_REL */ + COMMANDSIZE(5, vg_lite_float_t), /* 14: LCCWARC */ + COMMANDSIZE(5, vg_lite_float_t), /* 15: LCCWARC_REL */ + COMMANDSIZE(5, vg_lite_float_t), /* 16: LCWARC */ + COMMANDSIZE(5, vg_lite_float_t), /* 17: LCWARC_REL */ +}; + +/* Special sqrt(1.0f + x) for quick calculation when 0 <= x <= 1. */ +static vg_lite_float_t _Sqrt( + vg_lite_float_t X + ) +{ + vg_lite_float_t x = X; + vg_lite_float_t s = 1.0f; + + s += x * 0.5f; + x *= X; + s -= x * 0.12445995211601257f; + x *= X; + s += x * 0.058032196015119553f; + x *= X; + s -= x * 0.025314478203654289f; + x *= X; + s += x * 0.0059584137052297592f; + + return s; +} + +static vg_lite_error_t _set_point_tangent( + vg_lite_path_point_ptr Point, + vg_lite_float_t Dx, + vg_lite_float_t Dy + ) +{ + if(!Point) + return VG_LITE_INVALID_ARGUMENT; + + if (Dx == 0.0f) + { + if (Dy == 0.0f) + { + if (Point->prev) + { + Point->length = 0.0f; + Point->tangentX = Point->prev->tangentX; + Point->tangentY = Point->prev->tangentY; + } + else + { + Point->length = 0.0f; + Point->tangentX = 0.0f; + Point->tangentY = 0.0f; + } + } + else + { + Point->tangentX = 0.0f; + if (Dy > 0.0f) + { + Point->length = Dy; + Point->tangentY = 1.0f; + } + else + { + Point->length = -Dy; + Point->tangentY = -1.0f; + } + } + } + else if (Dy == 0.0f) + { + Point->tangentY = 0.0f; + if (Dx > 0.0f) + { + Point->length = Dx; + Point->tangentX = 1.0f; + } + else + { + Point->length = -Dx; + Point->tangentX = -1.0f; + } + } + else + { + vg_lite_float_t l, tx, ty; + + vg_lite_float_t dx, dy; + vg_lite_float_t t, t2; + + dx = (Dx >= 0.0f ? Dx : -Dx); + dy = (Dy >= 0.0f ? Dy : -Dy); + if (dx >= dy) + { + t = dy / dx; + t2 = t * t; + l = _Sqrt(t2); + Point->length = l * dx; + + tx = 1.0f / l; + ty = tx * t; + } + else + { + t = dx / dy; + t2 = t * t; + l = _Sqrt(t2); + Point->length = l * dy; + + ty = 1.0f / l; + tx = ty * t; + } + if (Dx < 0.0f) tx = -tx; + if (Dy < 0.0f) ty = -ty; + + tx = CLAMP(tx, -1.0f, 1.0f); + ty = CLAMP(ty, -1.0f, 1.0f); + Point->tangentX = tx; + Point->tangentY = ty; + } + return VG_LITE_SUCCESS; +} + +vg_lite_error_t _add_point_to_point_list_wdelta( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_float_t X, + vg_lite_float_t Y, + vg_lite_float_t DX, + vg_lite_float_t DY, + uint8_t flatten_flag + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_path_point_ptr last_point; + vg_lite_path_point_ptr point; + + if(!stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + last_point = stroke_conversion->path_last_point; + point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); + + if(!point) + return VG_LITE_OUT_OF_RESOURCES; + + memset(point, 0, sizeof(*point)); + + point->x = X; + point->y = Y; + point->flatten_flag = flatten_flag; + + /* Calculate tangent for last_point. */ + VG_LITE_ERROR_HANDLER(_set_point_tangent(last_point, DX, DY)); + + last_point->next = point; + stroke_conversion->path_last_point = point; + point->prev = last_point; + stroke_conversion->point_count++; + + return error; +ErrorHandler: + + vg_lite_os_free(point); + point = NULL; + return error; +} + +vg_lite_error_t _add_point_to_point_list( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_float_t X, + vg_lite_float_t Y, + uint8_t flatten_flag + ) +{ + vg_lite_error_t status = VG_LITE_SUCCESS; + vg_lite_path_point_ptr last_point; + vg_lite_path_point_ptr point; + + if(!stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + last_point = stroke_conversion->path_last_point; + if (last_point == NULL) + { + point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); + if(!point) + return VG_LITE_OUT_OF_RESOURCES; + memset(point, 0, sizeof(*point)); + + point->x = X; + point->y = Y; + point->flatten_flag = flatten_flag; + point->prev = NULL; + stroke_conversion->path_last_point = stroke_conversion->path_point_list = point; + stroke_conversion->point_count++; + status = VG_LITE_SUCCESS; + } + else + { + vg_lite_float_t dX = X - last_point->x; + vg_lite_float_t dY = Y - last_point->y; + vg_lite_float_t deltaX = (dX >= 0.0f ? dX : -dX); + vg_lite_float_t deltaY = (dY >= 0.0f ? dY : -dY); + + /* Check for degenerated line. */ + if (deltaX == 0.0f && deltaY == 0.0f) + { + /* Skip degenerated line. */ + status = VG_LITE_SUCCESS; + goto ErrorHandler; + } + if (deltaX < FLOAT_EPSILON && deltaY < FLOAT_EPSILON) + { + vg_lite_float_t ratioX, ratioY; + + if (deltaX == 0.0f) + { + ratioX = 0.0f; + } + else if (X == 0.0f) + { + ratioX = deltaX; + } + else + { + ratioX = deltaX / X; + if (ratioX < 0.0f) ratioX = -ratioX; + } + if (deltaY == 0.0f) + { + ratioY = 0.0f; + } + else if (Y == 0.0f) + { + ratioY = deltaY; + } + else + { + ratioY = deltaY / Y; + if (ratioY < 0.0f) ratioY = -ratioY; + } + if (ratioX < 1.0e-6f && ratioY < 1.0e-6f) + { + /* Skip degenerated line. */ + status = VG_LITE_SUCCESS; + goto ErrorHandler; + } + } + + status = _add_point_to_point_list_wdelta(stroke_conversion, X, Y, dX, dY, flatten_flag); + } + +ErrorHandler: + return status; +} + +static vg_lite_error_t _flatten_path( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_path_t *path + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint32_t increment; + uint8_t is_relative; + uint32_t size; + uint32_t path_command; + uint32_t prev_command; + uint8_t data_type_size; + int8_t* data_pointer = NULL; + vg_lite_float_t sx, sy; + vg_lite_float_t ox, oy; + vg_lite_float_t x0, y0, x1, y1, x2, y2; + vg_value_getter get_value = NULL; + + if(!stroke_conversion || !path) + return VG_LITE_INVALID_ARGUMENT; + + sx = sy = ox = oy = 0.0f; + + prev_command = VLC_OP_MOVE; + + /* Determine the data size. */ + size = path->path_length; + + /* Determine the beginning of the path data. */ + data_pointer = (int8_t*)path->path; + + /* Select the data picker. */ + switch (path->format) + { + case VG_LITE_S8: + data_type_size = 1; + get_value = _GetS8_NS_NB; + break; + + case VG_LITE_S16: + data_type_size = 2; + get_value = _GetS16_NS_NB; + break; + + case VG_LITE_S32: + data_type_size = 4; + get_value = _GetS32_NS_NB; + break; + + case VG_LITE_FP32: + data_type_size = 4; + get_value = _GetF_NS_NB; + break; + + default: + error = VG_LITE_INVALID_ARGUMENT; + goto ErrorHandler; + } + /* Add an extra gcvVGCMD_MOVE 0.0 0.0 to handle the case the first command is not gcvVGCMD_MOVE. */ + if (*data_pointer != VLC_OP_MOVE) + { + /* Add first point to subpath. */ + VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, sx, sy, vgcFLATTEN_NO)); + } + + while (size > 0) + { + /* Get the command. */ + path_command = *data_pointer & 0x1F; + + /* Assume absolute. */ + is_relative = FALSE; + + switch (path_command) + { + case VLC_OP_END: + /* Skip the command. */ + size -= 1; + + if (prev_command == VLC_OP_END) + { + /* Continuous gcvVGCMD_CLOSE - do nothing. */ + break; + } + + /* Check if subPath is already closed. */ + if (ox != sx || oy != sy) + { + /* Add a line from current point to the first point of current subpath. */ + VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, sx, sy,vgcFLATTEN_NO)); + } + if (stroke_conversion->path_point_list != stroke_conversion->path_last_point) + { + /* Copy tangent data from first point to last_point. */ + vg_lite_path_point_ptr first_point = stroke_conversion->path_point_list; + vg_lite_path_point_ptr last_point = stroke_conversion->path_last_point; + last_point->length = first_point->length; + last_point->tangentX = first_point->tangentX; + last_point->tangentY = first_point->tangentY; + } + else + { + /* Single point path. */ + vg_lite_path_point_ptr point = stroke_conversion->path_point_list; + point->tangentX = 0.0f; + point->tangentY = 0.0f; + point->length = 0.0f; + } + stroke_conversion->closed = 1; + stroke_conversion->path_last_point->next = NULL; + break; + + case VLC_OP_MOVE_REL: + is_relative = 1; + + case VLC_OP_MOVE: /* Indicate the beginning of a new sub-path. */ + /* Skip to the data. */ + SKIPTODATA(data_pointer, data_type_size, size); + VGSL_GETCOORDXY(x0, y0); + + /* First command is gcvVGCMD_MOVE. */ + /* Add first point to subpath. */ + VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, x0, y0, vgcFLATTEN_NO)); + + sx = ox = x0; + sy = oy = y0; + break; + + case VLC_OP_LINE_REL: + is_relative = 1; + + case VLC_OP_LINE: + /* Skip to the data. */ + SKIPTODATA(data_pointer, data_type_size, size); + VGSL_GETCOORDXY(x0, y0); + + /* Add a point to subpath. */ + VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, x0, y0, vgcFLATTEN_NO)); + + ox = x0; + oy = y0; + break; + + case VLC_OP_QUAD_REL: + is_relative = 1; + + case VLC_OP_QUAD: + /* Skip to the data. */ + SKIPTODATA(data_pointer, data_type_size, size); + VGSL_GETCOORDXY(x0, y0); + VGSL_GETCOORDXY(x1, y1); + + if ((ox == x0 && oy == y0) && (ox == x1 && oy == y1)) + { + /* Degenerated Bezier curve. Becomes a point. */ + /* Discard zero-length segments. */ + } + else if ((ox == x0 && oy == y0) || (x0 == x1 && y0 == y1)) + { + /* Degenerated Bezier curve. Becomes a line. */ + /* Add a point to subpath. */ + VG_LITE_ERROR_HANDLER(_add_point_to_point_list( stroke_conversion, x1, y1, vgcFLATTEN_NO)); + } + else + { + VG_LITE_ERROR_HANDLER(_flatten_quad_bezier(stroke_conversion, ox, oy, x0, y0, x1, y1)); + } + + ox = x1; + oy = y1; + break; + + case VLC_OP_CUBIC_REL: + is_relative = 1; + + case VLC_OP_CUBIC: + /* Skip to the data. */ + SKIPTODATA(data_pointer, data_type_size, size); + VGSL_GETCOORDXY(x0, y0); + VGSL_GETCOORDXY(x1, y1); + VGSL_GETCOORDXY(x2, y2); + + if ((ox == x0 && oy == y0) && (ox == x1 && oy == y1) && (ox == x2 && oy == y2)) + { + /* Degenerated Bezier curve. Becomes a point. */ + /* Discard zero-length segments. */ + } + else + { + VG_LITE_ERROR_HANDLER(_flatten_cubic_bezier(stroke_conversion, ox, oy, x0, y0, x1, y1, x2, y2)); + } + + ox = x2; + oy = y2; + break; + + default: + error = VG_LITE_INVALID_ARGUMENT; + goto ErrorHandler; + } + prev_command = path_command; + } + + if ((prev_command != VLC_OP_END)) + { + stroke_conversion->path_last_point->next = NULL; + if (stroke_conversion->point_count == 1) + { + /* Single point path. */ + vg_lite_path_point_ptr point = stroke_conversion->path_point_list; + point->tangentX = 0.0f; + point->tangentY = 0.0f; + point->length = 0.0f; + } + } + +ErrorHandler: + return error; +} + +static vg_lite_error_t +_add_point_to_right_stroke_point_list_tail( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_float_t X, + vg_lite_float_t Y + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_path_point_ptr point; + + if(!stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); + if(!point) + return VG_LITE_OUT_OF_RESOURCES; + + memset(point, 0, sizeof(*point)); + + point->x = X; + point->y = Y; + point->curve_type = CURVE_LINE; + point->prev = stroke_conversion->last_right_stroke_point; + point->next = NULL; + stroke_conversion->last_right_stroke_point->next = point; + stroke_conversion->last_right_stroke_point = point; + stroke_conversion->stroke_point_count++; + + stroke_conversion->last_stroke_sub_path->point_count++; + + return error; +} + +static vg_lite_error_t +_add_point_to_left_stroke_point_list_head( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_float_t X, + vg_lite_float_t Y + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_path_point_ptr point; + + if(!stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); + + if(!point) + return VG_LITE_OUT_OF_RESOURCES; + + memset(point, 0, sizeof(*point)); + + point->x = X; + point->y = Y; + point->curve_type = CURVE_LINE; + point->next = stroke_conversion->left_stroke_point; + point->prev = NULL; + stroke_conversion->left_stroke_point->prev = point; + stroke_conversion->left_stroke_point = point; + stroke_conversion->stroke_point_count++; + + stroke_conversion->last_stroke_sub_path->point_count++; + + return error; +} + +static vg_lite_error_t _add_stroke_sub_path( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_sub_path_ptr *sub_path + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + + if(!stroke_conversion || !sub_path) + return VG_LITE_INVALID_ARGUMENT; + + *sub_path = (vg_lite_sub_path_ptr)vg_lite_os_malloc(sizeof(**sub_path)); + + if(!*sub_path) + return VG_LITE_OUT_OF_RESOURCES; + + memset(*sub_path, 0, sizeof(**sub_path)); + + if (stroke_conversion->last_stroke_sub_path != NULL) + { + stroke_conversion->last_stroke_sub_path->next = *sub_path; + stroke_conversion->last_stroke_sub_path = *sub_path; + } + else + { + stroke_conversion->last_stroke_sub_path = stroke_conversion->stroke_sub_path_list = *sub_path; + } + + return error; +} + +static vg_lite_error_t +_add_zero_length_stroke_sub_path( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_sub_path_ptr *stroke_subpath + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_path_point_ptr new_point,Point; + vg_lite_sub_path_ptr stroke_sub_path; + vg_lite_float_t half_width; + + if(!stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + half_width = stroke_conversion->half_line_width; + Point = stroke_conversion->path_point_list; + if (stroke_conversion->stroke_cap_style == VG_LITE_CAP_BUTT) + { + /* No need to draw zero-length subPath for gcvCAP_BUTT. */ + error = VG_LITE_SUCCESS; + goto ErrorHandler; + } + + VG_LITE_ERROR_HANDLER(_add_stroke_sub_path(stroke_conversion, &stroke_sub_path)); + + if (stroke_conversion->stroke_cap_style == VG_LITE_CAP_SQUARE) + { + /* Draw a square along the point's direction. */ + vg_lite_float_t dx, dy; + + if (Point->tangentX == 0.0f || Point->tangentY == 0.0f) + { + dx = half_width; + dy = 0.0f; + } + else + { + dx = Point->tangentY * half_width; + dy = -Point->tangentX * half_width; + } + + new_point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*new_point)); + + if(!new_point) + return VG_LITE_OUT_OF_RESOURCES; + memset(new_point, 0, sizeof(*new_point)); + + new_point->x = Point->x + dx + dy; + new_point->y = Point->y - dx + dy; + new_point->curve_type = CURVE_LINE; + stroke_sub_path->point_list = stroke_conversion->last_right_stroke_point = new_point; + stroke_sub_path->point_count = 1; + + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, + Point->x + dx - dy, Point->y + dx + dy)); + + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, + Point->x - dx - dy, Point->y + dx - dy)); + + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, + Point->x - dx + dy, Point->y - dx - dy)); + } + else + { + /* Draw a circle. */ + new_point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*new_point)); + + if(!new_point) + return VG_LITE_OUT_OF_RESOURCES; + memset(new_point, 0, sizeof(*new_point)); + + new_point->x = Point->x + half_width; + new_point->y = Point->y; + new_point->curve_type = CURVE_LINE; + stroke_sub_path->point_list = stroke_conversion->last_right_stroke_point = new_point; + stroke_sub_path->point_count = 1; + + /* Add upper half circle. */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, + Point->x - half_width, Point->y)); + + stroke_conversion->last_right_stroke_point->curve_type = CURVE_ARC_SCCW_HALF; + stroke_conversion->last_right_stroke_point->centerX = Point->x; + stroke_conversion->last_right_stroke_point->centerY = Point->y; + + /* Add lower half circle. */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, + Point->x + half_width, Point->y)); + + stroke_conversion->last_right_stroke_point->curve_type = CURVE_ARC_SCCW_HALF; + stroke_conversion->last_right_stroke_point->centerX = Point->x; + stroke_conversion->last_right_stroke_point->centerY = Point->y; + } + + stroke_sub_path->last_point = stroke_conversion->last_right_stroke_point; + stroke_sub_path->last_point->next = NULL; + +ErrorHandler: + return error; +} + +/* Special asin(x) for quick calculation when -sqrt(0.5) <= x <= sqrt(0.5). */ +static vg_lite_float_t _Asin( + vg_lite_float_t X + ) +{ + vg_lite_float_t x = X; + vg_lite_float_t x2 = X * X; + vg_lite_float_t s = X; + + x *= x2; + s += x * 0.1660510562575219f; + x *= x2; + s += x * 0.084044676143618186f; + x *= x2; + s += x * 0.0023776176698039313f; + x *= x2; + s += x * 0.10211922020091345f; + + return s; +} +/* Special cos(x) for quick calculation when -PI <= x <= PI. */ +static vg_lite_float_t _Cos( + vg_lite_float_t X + ) +{ + vg_lite_float_t x2 = X * X; + vg_lite_float_t x = x2; + vg_lite_float_t s = 1.0f; + + s -= x * 0.49985163079668843f; + x *= x2; + s += x * 0.041518066216932693f; + x *= x2; + s -= x * 0.0013422997970712939f; + x *= x2; + s += x * 0.000018930111278021357f; + + return s; +} +/* Special sin(x) for quick calculation when -PI <= x <= PI. */ +static vg_lite_float_t _Sine( + vg_lite_float_t X + ) +{ + vg_lite_float_t x = X; + vg_lite_float_t x2 = X * X; + vg_lite_float_t s = X; + + x *= x2; + s -= x * 0.16664527099620879f; + x *= x2; + s += x * 0.0083154803736487041f; + x *= x2; + s -= x * 0.00019344151251408578f; + x *= x2; + s += x * 0.0000021810214160988925f; + + return s; +} + +static vg_lite_float_t +_Angle( + vg_lite_float_t X, + vg_lite_float_t Y, + vg_lite_float_t Length + ) +{ + vg_lite_float_t angle; + vg_lite_float_t ux = (X >= 0.0f ? X : -X); + vg_lite_float_t uy = (Y >= 0.0f ? Y : -Y); + + if (ux > uy) + { + angle = ((uy > 0.0f && ux < Length) ? _Asin(uy / Length) : 0.0f); + } + else + { + angle = ((ux > 0.0f && uy < Length) ? (FLOAT_PI_HALF - _Asin(ux / Length)) : FLOAT_PI_HALF); + } + + if (X < 0.0f) angle = FLOAT_PI - angle; + if (Y < 0.0f) angle = -angle; + + return angle; +} + +/* The arc is always counter clockwise and less than half circle (small). */ +static vg_lite_error_t +_convert_circle_arc( + vg_lite_stroke_conversion_t *stroke_conversion, + vg_lite_float_t Radius, + vg_lite_float_t CenterX, + vg_lite_float_t CenterY, + vg_lite_float_t StartX, + vg_lite_float_t StartY, + vg_lite_float_t EndX, + vg_lite_float_t EndY, + uint8_t Half_circle, + vg_lite_path_point_ptr *point_list + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + /*gceVGCMD segmentCommand;*/ + vg_lite_float_t theta1, theta_span; + uint32_t segs; + vg_lite_float_t theta, theta_half, theta2; + vg_lite_float_t cos_theta_half; + vg_lite_float_t control_ratio; + vg_lite_float_t controlX, controlY, anchorX, anchorY; + /*gctFLOAT lastX, lastY;*/ + vg_lite_path_point_ptr point, start_point, last_point; + + if(!stroke_conversion || !point_list) + return VG_LITE_INVALID_ARGUMENT; + + /* Converting. */ + theta1 = _Angle(StartX - CenterX, StartY - CenterY, Radius); + if (Half_circle) + { + theta_span = FLOAT_PI; + segs = 4; + theta = FLOAT_PI_QUARTER; + theta_half = FLOAT_PI_EIGHTH; + cos_theta_half = FLOAT_COS_PI_EIGHTH; + } + else + { + theta_span = _Angle(EndX - CenterX, EndY - CenterY, Radius) - theta1; + if (theta_span == 0.0f) + { + /* Handle specail case for huge scaling. */ + *point_list = NULL; + error = VG_LITE_SUCCESS; + return error; + } + + if ((theta_span < 0)) + { + theta_span += FLOAT_PI_TWO; + } + + /* Calculate the number of quadratic Bezier curves. */ + /* Assumption: most of angles are small angles. */ + if (theta_span <= FLOAT_PI_QUARTER) segs = 1; + else if (theta_span <= FLOAT_PI_HALF) segs = 2; + else if (theta_span <= FLOAT_PI_THREE_QUARTER) segs = 3; + else segs = 4; + + theta = theta_span / segs; + theta_half = theta / 2.0f; + cos_theta_half = _Cos(theta_half); + } + + /* Determine the segment command. */ + /*egmentCommand = gcvVGCMD_ARC_QUAD;*/ + + /* Generate quadratic Bezier curves. */ + start_point = last_point = NULL; + control_ratio = Radius / cos_theta_half; + while (segs-- > 0) + { + theta1 += theta; + + theta2 = theta1 - theta_half; + if (theta2 > FLOAT_PI) theta2 -= FLOAT_PI_TWO; + controlX = CenterX + _Cos(theta2) * control_ratio; + controlY = CenterY + _Sine(theta2) * control_ratio; + + theta2 = theta1; + if (theta2 > FLOAT_PI) theta2 -= FLOAT_PI_TWO; + anchorX = CenterX + _Cos(theta2) * Radius; + anchorY = CenterY + _Sine(theta2) * Radius; + + if (segs == 0) + { + /* Use end point directly to avoid accumulated errors. */ + anchorX = EndX; + anchorY = EndY; + } + + /* Add control point. */ + point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); + + if(!point) + return VG_LITE_OUT_OF_RESOURCES; + + memset(point, 0, sizeof(*point)); + + point->x = controlX; + point->y = controlY; + point->curve_type = CURVE_QUAD_CONTROL; + if (last_point) + { + last_point->next = point; + last_point = point; + } + else + { + start_point = last_point = point; + } + + /* Add anchor point. */ + point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); + + if(!point) { + error = VG_LITE_OUT_OF_RESOURCES; + goto ErrorHandler; + } + + memset(point, 0, sizeof(*point)); + + point->x = anchorX; + point->y = anchorY; + point->curve_type = CURVE_QUAD_ANCHOR; + last_point->next = point; + last_point = point; + } + + last_point->next = NULL; + *point_list = start_point; + + return error; +ErrorHandler: + /* Return status. */ + while (start_point) + { + point = start_point; + start_point = start_point->next; + vg_lite_os_free(point); + } + start_point = last_point = point = NULL; + return error; +} + +static vg_lite_error_t +_start_new_stroke_sub_path( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_float_t X, + vg_lite_float_t Y, + vg_lite_float_t Dx, + vg_lite_float_t Dy, + uint8_t add_end_cap, + vg_lite_sub_path_ptr *stroke_subpath + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + + vg_lite_sub_path_ptr stroke_sub_path; + vg_lite_path_point_ptr new_point; + + if(!stroke_conversion || !stroke_subpath) + return VG_LITE_INVALID_ARGUMENT; + + VG_LITE_ERROR_HANDLER(_add_stroke_sub_path(stroke_conversion, &stroke_sub_path)); + + new_point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*new_point)); + if(!new_point) + return VG_LITE_OUT_OF_RESOURCES; + + memset(new_point, 0, sizeof(*new_point)); + new_point->x = X + Dx; + new_point->y = Y + Dy; + new_point->prev = NULL; + new_point->curve_type = CURVE_LINE; + stroke_conversion->stroke_point_list = stroke_conversion->last_right_stroke_point = new_point; + + stroke_sub_path->point_list = stroke_conversion->last_right_stroke_point = new_point; + + new_point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*new_point)); + if(!new_point) + return VG_LITE_OUT_OF_RESOURCES; + + memset(new_point, 0, sizeof(*new_point)); + new_point->x = X - Dx; + new_point->y = Y - Dy; + new_point->curve_type = CURVE_LINE; + new_point->next = NULL; + stroke_conversion->stroke_last_point = stroke_conversion->left_stroke_point = new_point; + + stroke_conversion->stroke_point_count = 2; + + stroke_sub_path->last_point = stroke_conversion->left_stroke_point = new_point; + stroke_sub_path->point_count = 2; + + if (add_end_cap) + { + /* Add end cap if the subPath is not closed. */ + switch (stroke_conversion->stroke_cap_style) + { + case VG_LITE_CAP_BUTT: + /* No adjustment needed. */ + break; + case VG_LITE_CAP_ROUND: + /* Add curve. */ + /* Add the starting point again as arc. */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, + stroke_sub_path->point_list->x, stroke_sub_path->point_list->y)); + stroke_conversion->last_right_stroke_point->curve_type = CURVE_ARC_SCCW_HALF; + stroke_conversion->last_right_stroke_point->centerX = X; + stroke_conversion->last_right_stroke_point->centerY = Y; + /* Change the starting point to end point. */ + stroke_sub_path->point_list->x = stroke_sub_path->last_point->x; + stroke_sub_path->point_list->y = stroke_sub_path->last_point->y; + break; + case VG_LITE_CAP_SQUARE: + stroke_conversion->last_right_stroke_point->x += Dy; + stroke_conversion->last_right_stroke_point->y -= Dx; + stroke_conversion->left_stroke_point->x += Dy; + stroke_conversion->left_stroke_point->y -= Dx; + break; + } + } + + *stroke_subpath = stroke_sub_path; + +ErrorHandler: + return error; +} + +static void +_adjust_joint_point( + vg_lite_path_point_ptr Point, + vg_lite_path_point_ptr join_point, + vg_lite_float_t X, + vg_lite_float_t Y, + vg_lite_float_t Ratio + ) +{ + vg_lite_float_t mx = (join_point->x + X) / 2.0f; + vg_lite_float_t my = (join_point->y + Y) / 2.0f; + vg_lite_float_t dx = mx - Point->x; + vg_lite_float_t dy = my - Point->y; + + dx = dx * Ratio; + dy = dy * Ratio; + join_point->x = Point->x + dx; + join_point->y = Point->y + dy; +} + +static uint8_t +_is_angle_span_acute( + vg_lite_float_t Ux, + vg_lite_float_t Uy, + vg_lite_float_t Vx, + vg_lite_float_t Vy + ) +{ + return ((Ux * Vx + Uy * Vy) > 0.0f ? 1 : 0); +} + +static vg_lite_error_t +_draw_swing_pie_area( + vg_lite_stroke_conversion_t *stroke_conversion, + vg_lite_path_point_ptr center_point, + uint8_t end_at_prev_point + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + + if(!stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + if (stroke_conversion->swing_counter_clockwise) + { + vg_lite_path_point_ptr start_point = stroke_conversion->swing_start_stroke_point; + vg_lite_path_point_ptr end_point = NULL, real_end_point = NULL; + vg_lite_path_point_ptr point, prev_point; + uint32_t count = 0; + + { + if (end_at_prev_point) + { + /* Detach the end point from leftStrokePoint. */ + /* The end point will be added back later. */ + real_end_point = stroke_conversion->left_stroke_point; + stroke_conversion->left_stroke_point = real_end_point->next; + stroke_conversion->left_stroke_point->prev = NULL; + } + + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, + center_point->x, center_point->y)); + end_point = stroke_conversion->left_stroke_point; + + /* Reverse the point list from startPoint to endPoint. */ + for (point = start_point; point; point = prev_point) + { + prev_point = point->prev; + point->prev = point->next; + point->next = prev_point; + count++; + } + end_point->next = start_point->prev; + start_point->prev->prev = end_point; + start_point->prev = NULL; + stroke_conversion->left_stroke_point = start_point; + + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, + center_point->x, center_point->y)); + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, + stroke_conversion->swing_start_point->x, + stroke_conversion->swing_start_point->y)); + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, + end_point->prev->x, end_point->prev->y)); + + if (end_at_prev_point) + { + real_end_point->next = stroke_conversion->left_stroke_point; + stroke_conversion->left_stroke_point->prev = real_end_point; + stroke_conversion->left_stroke_point = real_end_point; + } + } + } + else + { + vg_lite_path_point_ptr start_point = stroke_conversion->swing_start_stroke_point; + vg_lite_path_point_ptr end_point = NULL, real_end_point = NULL; + vg_lite_path_point_ptr point, next_point; + uint32_t count = 0; + + { + if (end_at_prev_point) + { + /* Detach the end point from leftStrokePoint. */ + /* The end point will be added back later. */ + real_end_point = stroke_conversion->last_right_stroke_point; + stroke_conversion->last_right_stroke_point = real_end_point->prev; + stroke_conversion->last_right_stroke_point->next = NULL; + } + + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, + center_point->x, center_point->y)); + end_point = stroke_conversion->last_right_stroke_point; + + /* Reverse the point list from startPoint to endPoint. */ + for (point = start_point; point; point = next_point) + { + next_point = point->next; + point->next = point->prev; + point->prev = next_point; + count++; + } + end_point->prev = start_point->next; + start_point->next->next = end_point; + start_point->next = NULL; + stroke_conversion->last_right_stroke_point = start_point; + + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, + center_point->x, center_point->y)); + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, + stroke_conversion->swing_start_point->x, + stroke_conversion->swing_start_point->y)); + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, + end_point->next->x, end_point->next->y)); + + if (end_at_prev_point) + { + real_end_point->prev = stroke_conversion->last_right_stroke_point; + stroke_conversion->last_right_stroke_point->next = real_end_point; + stroke_conversion->last_right_stroke_point = real_end_point; + } + } + } + + stroke_conversion->swing_handling = SWING_NO; + +ErrorHandler: + + return error; +} + +static vg_lite_error_t +_process_line_joint( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_path_point_ptr Point, + vg_lite_float_t Length, + vg_lite_float_t prev_length, + uint32_t Swing_handling, + vg_lite_float_t X1, + vg_lite_float_t Y1, + vg_lite_float_t X2, + vg_lite_float_t Y2 + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_join_style_t stroke_join_style = stroke_conversion->stroke_join_style; + vg_lite_float_t half_width = stroke_conversion->half_line_width; + vg_lite_float_t ratio; + vg_lite_float_t min_length_square; + vg_lite_float_t cos_theta; + uint8_t counter_clockwise; + uint8_t fat_line = stroke_conversion->is_fat; + uint32_t swing_handling = SWING_NO; + uint8_t handle_short_line = 0; + + if(!stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + if (stroke_conversion->swing_accu_length < half_width) + { + if (stroke_conversion->swing_need_to_handle) + { + swing_handling = SWING_OUT; + } + else + { + handle_short_line = 1; + } + } + else if (stroke_conversion->stroke_path_length - stroke_conversion->swing_accu_length < half_width) + { + if (stroke_conversion->swing_need_to_handle) + { + swing_handling = SWING_IN; + } + else + { + handle_short_line = 1; + } + } + + if (swing_handling != Swing_handling) + { + error = VG_LITE_INVALID_ARGUMENT; + goto ErrorHandler; + } + + /* For flattened curves/arcs, the join style is always round. */ + if ((Point->flatten_flag != vgcFLATTEN_NO) && fat_line) + { + stroke_join_style = VG_LITE_JOIN_ROUND; + } + + /* First, determine the turn is clockwise or counter-clockwise. */ + cos_theta = Point->prev->tangentX * Point->tangentX + Point->prev->tangentY * Point->tangentY; + + if (cos_theta > FLOAT_ANGLE_EPSILON_COS) + { + /* Straight line or semi-straight line--no need to handle join. */ + if (stroke_conversion->swing_handling !=SWING_NO) + { + /* Begin to swing to the opposite direction. */ + /* Draw the swing area (pie area). */ + VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, Point->prev, 1)); + } + + /* Add the new stroke points. */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); + if (stroke_conversion->swing_handling != SWING_NO) + { + stroke_conversion->swing_count++; + } + + goto endCheck; + } + else if (cos_theta < -FLOAT_ANGLE_EPSILON_COS) + { + /* Almost 180 degree turn. */ + counter_clockwise = 1; + ratio = FLOAT_MAX; + min_length_square = FLOAT_MAX; + } + else + { + vg_lite_float_t angleSign = Point->prev->tangentX * Point->tangentY - Point->prev->tangentY * Point->tangentX; + counter_clockwise = (angleSign >= 0.0f ? 1 : 0); + ratio = 2.0f / (1.0f + cos_theta); + min_length_square = half_width * half_width * (1.0f - cos_theta) / (1.0f + cos_theta) + 0.02f; + } + + if (stroke_conversion->swing_handling != SWING_NO) + { + if (counter_clockwise != stroke_conversion->swing_counter_clockwise) + { + /* Swing to the opposite direction. */ + /* Draw the swing area (pie area). */ + VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, Point->prev, 1)); + } + } + + if (counter_clockwise) + { + if (stroke_conversion->swing_handling != SWING_NO) + { + vg_lite_path_point_ptr prev_point = stroke_conversion->left_stroke_point->next; /* Skip the line segment movement. */ + vg_lite_float_t deltaX = X2 - prev_point->x; + vg_lite_float_t deltaY = Y2 - prev_point->y; + if (_is_angle_span_acute(stroke_conversion->swing_stroke_deltax, + stroke_conversion->swing_stroke_deltay, + deltaX, deltaY)) + { + /* Continue swinging. */ + stroke_conversion->swing_stroke_deltax = deltaX; + stroke_conversion->swing_stroke_deltay = deltaY; + } + else + { + /* Swing to the max. */ + /* Draw the swing area (pie area). */ + VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, Point->prev, 1)); + } + } + + /* Check if the miter length is too long for inner intersection. */ + if (stroke_conversion->swing_handling == SWING_NO + && ! handle_short_line + && min_length_square <= Length * Length + && min_length_square <= prev_length * prev_length) + { + /* Adjust leftStrokePoint to the intersection point. */ + _adjust_joint_point(Point, stroke_conversion->left_stroke_point, X2, Y2, ratio); + } + else if (stroke_conversion->swing_handling == SWING_NO && Point->flatten_flag == vgcFLATTEN_NO) + { + /* Add the point to avoid incorrect sharp angle. */ + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, Point->x, Point->y)); + /* Add the point to form a loop to avoid out-of-bound problem. */ + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); + } + else if (stroke_conversion->swing_handling == SWING_NO && (! fat_line || Swing_handling == SWING_NO)) + { + /* Flattened line segments should not have sharp angle. */ + /* Add the point to form a loop to avoid out-of-bound problem. */ + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); + } + else + { + if (stroke_conversion->swing_handling == SWING_NO) + { + vg_lite_path_point_ptr prev_point = stroke_conversion->left_stroke_point; + + /* Start swing handling. */ + stroke_conversion->swing_handling = Swing_handling; + stroke_conversion->swing_counter_clockwise = 1; + stroke_conversion->swing_start_point = Point; + stroke_conversion->swing_center_length = 0.0f; + stroke_conversion->swing_count= 0; + + /* Save stroking path delta. */ + stroke_conversion->swing_stroke_deltax = X2 - prev_point->x; + stroke_conversion->swing_stroke_deltay = Y2 - prev_point->y; + + /* Add extra center point for swing out pie area. */ + /* VIV: [todo] Should adjust prev_point, instead of adding new point? */ + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, Point->x, Point->y)); + + /* Add extra start stroke point for swing out pie area. */ + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, prev_point->x, prev_point->y)); + + stroke_conversion->swing_start_stroke_point = stroke_conversion->left_stroke_point; + } + +#if USE_MIN_ARC_FILTER + if (cosTheta > FLOAT_MIN_ARC_ANGLE_COS) + { + /* Add a point. */ + gcmERR_GOTO(_add_point_to_left_stroke_point_list_head(Context, stroke_conversion, X2, Y2)); + + VGSL_STAT_COUNTER_INCREASE(vgStrokeFilteredByMinArcAngleCount); + } + else +#endif + { + /* Add curve. */ + /* Note that the curve will be reversed, so the direction is CW. */ + /* Then, left side is in reversed order, so the direction is CCW. */ + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); + stroke_conversion->left_stroke_point->curve_type = CURVE_ARC_SCCW; + stroke_conversion->left_stroke_point->centerX = Point->x; + stroke_conversion->left_stroke_point->centerY = Point->y; + } + stroke_conversion->swing_count++; + } + + switch (stroke_join_style) + { + case VG_LITE_JOIN_ROUND: + if (cos_theta > FLOAT_MIN_ARC_ANGLE_COS) + { + /* Add a point. */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); + } + else + { + /* Add curve. */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); + stroke_conversion->last_right_stroke_point->curve_type = CURVE_ARC_SCCW; + stroke_conversion->last_right_stroke_point->centerX = Point->x; + stroke_conversion->last_right_stroke_point->centerY = Point->y; + } + break; + case VG_LITE_JOIN_MITER: + if (ratio <= stroke_conversion->stroke_miter_limit_square) + { + /* Adjust lastRightStrokePoint to the outer intersection point. */ + _adjust_joint_point(Point, stroke_conversion->last_right_stroke_point, X1, Y1, ratio); + break; + } + /* Else use Bevel join style. */ + case VG_LITE_JOIN_BEVEL: + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); + break; + } + } + else + { + if (stroke_conversion->swing_handling != SWING_NO) + { + vg_lite_path_point_ptr prev_point = stroke_conversion->last_right_stroke_point->prev; /* Skip the line segment movement. */ + vg_lite_float_t deltaX = X1 - prev_point->x; + vg_lite_float_t deltaY = Y1 - prev_point->y; + if (_is_angle_span_acute(stroke_conversion->swing_stroke_deltax, + stroke_conversion->swing_stroke_deltay, + deltaX, deltaY)) + { + /* Continue swinging. */ + stroke_conversion->swing_stroke_deltax = deltaX; + stroke_conversion->swing_stroke_deltay = deltaY; + } + else + { + /* Swing to the max. */ + /* Draw the swing area (pie area). */ + VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, Point->prev, 1)); + } + } + + /* Check if the miter length is too long for inner intersection. */ + if (stroke_conversion->swing_handling == SWING_NO + && ! handle_short_line + && min_length_square <= Length * Length + && min_length_square <= prev_length * prev_length) + { + /* Adjust lastRightStrokePoint to the intersection point. */ + _adjust_joint_point(Point, stroke_conversion->last_right_stroke_point, X1, Y1, ratio); + } + else if (stroke_conversion->swing_handling == SWING_NO && Point->flatten_flag == vgcFLATTEN_NO) + { + /* Add the point to avoid incorrect sharp angle. */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, Point->x, Point->y)); + /* Add the point to form a loop to avoid out-of-bound problem. */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); + } + else if (stroke_conversion->swing_handling == SWING_NO && (! fat_line || Swing_handling == SWING_NO)) + { + /* Flattened line segments should not have sharp angle. */ + /* Add the point to form a loop to avoid out-of-bound problem. */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); + } + else + { + if (stroke_conversion->swing_handling == SWING_NO) + { + vg_lite_path_point_ptr prev_point = stroke_conversion->last_right_stroke_point; + + /* Start swing handling. */ + stroke_conversion->swing_handling = Swing_handling; + stroke_conversion->swing_counter_clockwise = 0; + stroke_conversion->swing_start_point = Point; + stroke_conversion->swing_center_length = 0.0f; + stroke_conversion->swing_count= 0; + + /* Save stroking path delta. */ + stroke_conversion->swing_stroke_deltax = X1 - prev_point->x; + stroke_conversion->swing_stroke_deltay = Y1 - prev_point->y; + + /* Add extra center point for swing out pie area. */ + /* VIV: [todo] Should adjust prev_point, instead of adding new point? */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, Point->x, Point->y)); + + /* Add extra start stroke point for swing out pie area. */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, prev_point->x, prev_point->y)); + + stroke_conversion->swing_start_stroke_point = stroke_conversion->last_right_stroke_point; + } + + if (cos_theta > FLOAT_MIN_ARC_ANGLE_COS) + { + /* Add a point. */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); + } + else + { + /* Add curve. */ + /* Note that the curve will be reversed, so the direction is CCW. */ + stroke_conversion->last_right_stroke_point->curve_type = CURVE_ARC_SCCW; + stroke_conversion->last_right_stroke_point->centerX = Point->x; + stroke_conversion->last_right_stroke_point->centerY = Point->y; + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); + } + stroke_conversion->swing_count++; + } + + switch (stroke_join_style) + { + case VG_LITE_JOIN_ROUND: + if (cos_theta > FLOAT_MIN_ARC_ANGLE_COS) + { + /* Add a point. */ + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); + } + else + { + /* Add curve. */ + stroke_conversion->left_stroke_point->curve_type = CURVE_ARC_SCCW; + stroke_conversion->left_stroke_point->centerX = Point->x; + stroke_conversion->left_stroke_point->centerY = Point->y; + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); + } + break; + case VG_LITE_JOIN_MITER: + if (ratio <= stroke_conversion->stroke_miter_limit_square) + { + /* Adjust leftStrokePoint to the outer intersection point. */ + _adjust_joint_point(Point, stroke_conversion->left_stroke_point, X2, Y2, ratio); + break; + } + /* Else use Bevel join style. */ + case VG_LITE_JOIN_BEVEL: + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); + break; + } + } + +endCheck: + if (stroke_conversion->swing_need_to_handle) + { + stroke_conversion->swing_accu_length += Point->length; + } + if (stroke_conversion->swing_handling != SWING_NO) + { + if (Point->flatten_flag == vgcFLATTEN_END || + (stroke_conversion->swing_handling == SWING_OUT && + stroke_conversion->swing_accu_length > half_width)) + { + /* Draw the swing area (pie area). */ + VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, Point, 0)); + } + else + { + /* Check if center line will move too far. */ + stroke_conversion->swing_center_length += Point->length; + if (stroke_conversion->swing_center_length > FLOAT_SWING_CENTER_RANGE) + { +#if USE_NEW_SWING_HANDLE_FOR_END + if (stroke_conversion->currentSubPath->length < half_width || + Point->next->flatten_flag == vgcFLATTEN_END) +#endif + { + /* Draw the swing area (pie area). */ + VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, Point, 0)); + } + } + } + } + +ErrorHandler: + + return error; +} + +static vg_lite_error_t +_close_stroke_sub_path( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_path_point_ptr Point, + vg_lite_float_t Length, + vg_lite_float_t prev_length, + uint8_t Swing_handling, + vg_lite_path_point_ptr first_stroke_point, + vg_lite_path_point_ptr last_stroke_point + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + if(!stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + /* Handle line joint style for the first/last point in closed path. */ + VG_LITE_ERROR_HANDLER(_process_line_joint( + stroke_conversion, Point, + Length, prev_length, Swing_handling, + first_stroke_point->x, first_stroke_point->y, + last_stroke_point->x, last_stroke_point->y + )); + + /* Adjust the two end ponts of the first point. */ + first_stroke_point->x = stroke_conversion->last_right_stroke_point->x; + first_stroke_point->y = stroke_conversion->last_right_stroke_point->y; + last_stroke_point->x = stroke_conversion->left_stroke_point->x; + last_stroke_point->y = stroke_conversion->left_stroke_point->y; + + /* Concatnate right and left point lists. */ + stroke_conversion->last_right_stroke_point->next = stroke_conversion->left_stroke_point; + stroke_conversion->left_stroke_point->prev = stroke_conversion->last_right_stroke_point; + + /*gcmERROR_RETURN(_CheckStrokeSubPath(stroke_conversion->lastStrokeSubPath));*/ + +ErrorHandler: + return error; +} + +static vg_lite_error_t _end_stroke_sub_path( + vg_lite_stroke_conversion_t *stroke_conversion, + vg_lite_float_t X, + vg_lite_float_t Y, + vg_lite_float_t Dx, + vg_lite_float_t Dy + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + + if(!stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + /* Add points for end of line. */ + VG_LITE_RETURN_ERROR(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X + Dx, Y + Dy)); + VG_LITE_RETURN_ERROR(_add_point_to_left_stroke_point_list_head(stroke_conversion, X - Dx, Y - Dy)); + + /* Add end cap if the subPath is not closed. */ + switch (stroke_conversion->stroke_cap_style) + { + case VG_LITE_CAP_BUTT: + /* No adjustment needed. */ + break; + case VG_LITE_CAP_ROUND: + /* Add curve. */ + stroke_conversion->left_stroke_point->curve_type = CURVE_ARC_SCCW_HALF; + stroke_conversion->left_stroke_point->centerX = X; + stroke_conversion->left_stroke_point->centerY = Y; + break; + case VG_LITE_CAP_SQUARE: + stroke_conversion->last_right_stroke_point->x -= Dy; + stroke_conversion->last_right_stroke_point->y += Dx; + stroke_conversion->left_stroke_point->x -= Dy; + stroke_conversion->left_stroke_point->y += Dx; + break; + } + + /* Concatnate right and left point lists. */ + stroke_conversion->last_right_stroke_point->next = stroke_conversion->left_stroke_point; + stroke_conversion->left_stroke_point->prev = stroke_conversion->last_right_stroke_point; + + /*gcmERROR_RETURN(_CheckStrokeSubPath(stroke_conversion->lastStrokeSubPath));*/ + return error; +} + +static vg_lite_error_t _get_next_dash_length( + vg_lite_stroke_conversion_t * stroke_conversion, + uint32_t * dash_index, + vg_lite_float_t * dash_length + ) +{ + if(!stroke_conversion || !dash_index || !dash_length) + return VG_LITE_INVALID_ARGUMENT; + + (*dash_index)++; + if (*dash_index == stroke_conversion->stroke_dash_pattern_count) + { + *dash_index = 0; + } + *dash_length = stroke_conversion->stroke_dash_pattern[*dash_index]; + + return VG_LITE_SUCCESS; +} + +static vg_lite_error_t +_create_stroke_path( + vg_lite_stroke_conversion_t * stroke_conversion + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_sub_path_ptr stroke_sub_path = NULL,first_stroke_sub_path = NULL; + vg_lite_path_point_ptr point, next_point; + vg_lite_float_t half_width; + vg_lite_float_t x, y; + vg_lite_float_t dx, dy, ux, uy; + vg_lite_float_t length, prev_length, first_length; + vg_lite_float_t dash_length; + uint32_t dash_index; + uint8_t dashing; + uint8_t add_end_cap; + uint8_t need_to_handle_swing = 1 /* (stroke_conversion->strokeCapStyle == gcvCAP_BUTT) */; + + vg_lite_path_point_ptr first_right_point = NULL; + vg_lite_path_point_ptr last_left_point = NULL; + vg_lite_float_t first_dx = 0.0f, first_dy = 0.0f; + uint8_t drawing = 0; + vg_lite_float_t total_length = 0.0f; + vg_lite_float_t accu_length = 0.0f; + uint32_t swing_handling = SWING_NO; + + if(!stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + half_width = stroke_conversion->half_line_width; + dashing = stroke_conversion->stroke_dash_pattern_count > 0 ? 1 : 0; + dash_index = stroke_conversion->stroke_dash_initial_index; + dash_length = stroke_conversion->stroke_dash_initial_length; + + /* VIV: [todo] Need to check/debug closed stroke path. */ + need_to_handle_swing = (stroke_conversion->stroke_cap_style == VG_LITE_CAP_BUTT || stroke_conversion->closed); + if (need_to_handle_swing) + { + uint8_t reallyneed_to_handle_swing = 0; + + /* Calculate the total length. */ + for (point = stroke_conversion->path_point_list; point; point = point->next) + { + total_length += point->length; + + if (point->flatten_flag != vgcFLATTEN_NO) + { + reallyneed_to_handle_swing = 1; + } + } + stroke_conversion->stroke_path_length = total_length; + if (reallyneed_to_handle_swing) + { + swing_handling = SWING_OUT; + } + else + { + need_to_handle_swing = 0; + swing_handling = SWING_NO; + } + } + stroke_conversion->swing_need_to_handle = need_to_handle_swing; + + point = stroke_conversion->path_point_list; + next_point = point->next; + if (next_point == NULL) + { + if (!dashing || ((dash_index & 0x1) == 0)) + { + /* Single point (zero-length) subpath. */ + /* Note that one-MOVE_TO subpaths are removed during parsing. */ + VG_LITE_ERROR_HANDLER(_add_zero_length_stroke_sub_path(stroke_conversion, &stroke_sub_path)); + } + goto ErrorHandler; + } + + /* Adjust closed status for dashing. */ + if (dashing && stroke_conversion->closed && ((dash_index & 0x1) == 1)) + { + stroke_conversion->closed = FALSE; + } + + /* Set add_end_cap. */ + add_end_cap = dashing ? 1: (stroke_conversion->closed ? 0 : 1); + + /* Process first line. */ + first_length = point->length; + ux = point->tangentX; + uy = point->tangentY; + dx = uy * half_width; + dy = -ux * half_width; + if (need_to_handle_swing) + { + stroke_conversion->swing_accu_length = first_length; + } + + if (dashing) + { + vg_lite_float_t delta_length; + + /* Draw dashes. */ + x = point->x; + y = point->y; + do + { + if ((dash_index & 0x1) == 0) + { + VG_LITE_ERROR_HANDLER(_start_new_stroke_sub_path( + stroke_conversion, + x, y, + dx, dy, add_end_cap, + &stroke_sub_path + )); + + drawing = 1; + add_end_cap = 1; + if (stroke_conversion->closed && (first_stroke_sub_path == NULL)) + { + first_stroke_sub_path = stroke_conversion->last_stroke_sub_path; + first_right_point = stroke_conversion->last_right_stroke_point; + last_left_point = stroke_conversion->left_stroke_point; + first_dx = dx; + first_dy = dy; + } + } + + delta_length = first_length - dash_length; + if (delta_length >= FLOAT_EPSILON) + { + /* Move (x, y) forward along the line by dash_length. */ + x += ux * dash_length; + y += uy * dash_length; + + if ((dash_index & 0x1) == 0) + { + VG_LITE_ERROR_HANDLER(_end_stroke_sub_path( + stroke_conversion, + x, y, + dx, dy + )); + + drawing = 0; + } + + VG_LITE_ERROR_HANDLER(_get_next_dash_length(stroke_conversion, &dash_index, &dash_length)); + first_length = delta_length; + } + else if (delta_length <= -FLOAT_EPSILON) + { + dash_length = -delta_length; + break; + } + else + { + if ((dash_index & 0x1) == 0) + { + VG_LITE_ERROR_HANDLER(_end_stroke_sub_path( + stroke_conversion, + next_point->x, next_point->y, + dx, dy + )); + + drawing = 0; + } + + VG_LITE_ERROR_HANDLER(_get_next_dash_length(stroke_conversion, &dash_index, &dash_length)); + first_length = 0; + break; + } + } + while (1); + } + else + { + VG_LITE_ERROR_HANDLER(_start_new_stroke_sub_path( + stroke_conversion, + point->x, point->y, + dx, dy, add_end_cap, + &stroke_sub_path + )); + + drawing = 1; + add_end_cap = 1; + } + + /* Process the rest of lines. */ + prev_length = first_length; + for (point = next_point, next_point = point->next; next_point; + point = next_point, next_point = point->next) + { + if (!dashing || ((dash_index & 0x1) == 0 && drawing)) + { + /* Add points for end of line for line join process with next line. */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, + point->x + dx, point->y + dy)); + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, + point->x - dx, point->y - dy)); + } + + length = point->length; + ux = point->tangentX; + uy = point->tangentY; + dx = uy * half_width; + dy = -ux * half_width; + if (need_to_handle_swing) + { + accu_length += point->prev->length; + stroke_conversion->swing_accu_length = accu_length; + if (accu_length < half_width) + { + swing_handling = SWING_OUT; + } + else if (total_length - accu_length < half_width) + { + swing_handling = SWING_IN; + } + else + { + swing_handling = SWING_NO; + } + } + + if (!dashing) + { + /* Handle line joint style. */ + VG_LITE_ERROR_HANDLER(_process_line_joint( + stroke_conversion, point, + length, prev_length, swing_handling, + point->x + dx, point->y + dy, + point->x - dx, point->y - dy + )); + } + else + { + vg_lite_float_t delta_length; + + /* Draw dashes. */ + x = point->x; + y = point->y; + if ((dash_index & 0x1) == 0) + { + if (drawing) + { + /* Handle line joint style. */ + VG_LITE_ERROR_HANDLER(_process_line_joint( + stroke_conversion, point, + dash_length, prev_length, swing_handling, + x + dx, y + dy, + x - dx, y - dy + )); + } + else + { + /* Start a new sub path. */ + VG_LITE_ERROR_HANDLER(_start_new_stroke_sub_path( + stroke_conversion, + x, y, + dx, dy, add_end_cap, + &stroke_sub_path + )); + + drawing = 1; + add_end_cap = 1; + } + } + do + { + delta_length = length - dash_length; + if (delta_length >= FLOAT_EPSILON) + { + /* Move (x, y) forward along the line by dash_length. */ + x += ux * dash_length; + y += uy * dash_length; + + if ((dash_index & 0x1) == 0) + { + VG_LITE_ERROR_HANDLER(_end_stroke_sub_path( + stroke_conversion, + x, y, dx, dy + )); + + drawing = 0; + } + + VG_LITE_ERROR_HANDLER(_get_next_dash_length(stroke_conversion, &dash_index, &dash_length)); + length = delta_length; + } + else if (delta_length <= -FLOAT_EPSILON) + { + dash_length = -delta_length; + break; + } + else + { + if ((dash_index & 0x1) == 0) + { + VG_LITE_ERROR_HANDLER(_end_stroke_sub_path( + stroke_conversion, + next_point->x, next_point->y, + dx, dy + )); + + drawing = 0; + } + + VG_LITE_ERROR_HANDLER(_get_next_dash_length(stroke_conversion, &dash_index, &dash_length)); + length = 0; + break; + } + + if ((dash_index & 0x1) == 0) + { + VG_LITE_ERROR_HANDLER(_start_new_stroke_sub_path( + stroke_conversion, + x, y, + dx, dy, add_end_cap, + &stroke_sub_path + )); + + drawing = 1; + add_end_cap = 1; + } + } + while (1); + } + + prev_length = length; + } + + if (need_to_handle_swing) + { + accu_length += point->prev->length; + stroke_conversion->swing_accu_length = accu_length; + if (accu_length < half_width) + { + swing_handling = SWING_OUT; + } + else if (total_length - accu_length < half_width) + { + swing_handling = SWING_IN; + } + else + { + swing_handling = SWING_NO; + } + } + + if (stroke_conversion->swing_handling != SWING_NO) + { + /* Draw the swing area (pie area). */ + VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, stroke_conversion->path_last_point, FALSE)); + } + + if (stroke_conversion->closed) + { + if (! dashing || drawing) + { + /* Add points for end of line. */ + VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, + point->x + dx, point->y + dy)); + VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, + point->x - dx, point->y - dy)); + + if (! dashing) + { + /* Handle line joint style for the first/last point in closed path. */ + VG_LITE_ERROR_HANDLER(_close_stroke_sub_path( + stroke_conversion, point, + first_length, prev_length, swing_handling, + stroke_sub_path->point_list, stroke_sub_path->last_point + )); + } + else + { + /* Handle line joint style for the first/last point in closed path. */ + VG_LITE_ERROR_HANDLER(_close_stroke_sub_path( + stroke_conversion, point, + first_length, prev_length, swing_handling, + first_right_point, last_left_point + )); + } + } + else if (stroke_conversion->stroke_cap_style != VG_LITE_CAP_BUTT) + { + /* No closing join need. Add end cap for the starting point. */ + + if (stroke_conversion->stroke_cap_style == VG_LITE_CAP_SQUARE) + { + first_right_point->x += first_dy; + first_right_point->y -= first_dx; + last_left_point->x += first_dy; + last_left_point->y -= first_dx; + } + else + { + vg_lite_sub_path_ptr last_stroke_sub_path = stroke_conversion->last_stroke_sub_path; + vg_lite_path_point_ptr start_point = last_stroke_sub_path->point_list; + vg_lite_path_point_ptr point; + + /* Add curve. */ + /* Add extra point to the beginning with end point's coordinates. */ + point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); + if(!point) + return VG_LITE_INVALID_ARGUMENT; + memset(point, 0, sizeof(*point)); + + point->x = last_stroke_sub_path->last_point->x; + point->y = last_stroke_sub_path->last_point->y; + point->next = start_point; + start_point->prev = point; + start_point->curve_type = CURVE_ARC_SCCW; + start_point->centerX = stroke_conversion->path_point_list->x; + start_point->centerY = stroke_conversion->path_point_list->y; + last_stroke_sub_path->point_list = point; + } + } + } + else if (! dashing || + (((dash_index & 0x1) == 0) && (dash_length < stroke_conversion->stroke_dash_pattern[dash_index]))) + { + /* Add end cap if the subPath is not closed. */ + VG_LITE_ERROR_HANDLER(_end_stroke_sub_path( + stroke_conversion, + point->x, point->y, + dx, dy + )); + + drawing = 0; + } + + +ErrorHandler: + return error; +} + +static vg_lite_error_t _copy_stroke_path( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_path_t *path + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_path_point_ptr point,prev_point,tmp_point; + uint32_t totalsize = 0,real_size = 0; + float *pfloat; + char *cpath = NULL; + char last_opcode = 0; + void *temp_stroke_path_data = NULL; + uint32_t temp_stroke_path_size; + vg_lite_sub_path_ptr sub_path; + vg_lite_float_t half_width; + + if(!stroke_conversion || !path) + return VG_LITE_INVALID_ARGUMENT; + + half_width = stroke_conversion->half_line_width; + sub_path = stroke_conversion->stroke_sub_path_list; + + if(!stroke_conversion || !path || !sub_path) + return VG_LITE_INVALID_ARGUMENT; + + while (sub_path) + { + tmp_point = prev_point = point = sub_path->point_list; + totalsize += _commandSize_float[VLC_OP_LINE] * sub_path->point_count + _commandSize_float[VLC_OP_CLOSE]; + for(;tmp_point;tmp_point = tmp_point->next) + { + if(tmp_point->curve_type == CURVE_ARC_SCCW || tmp_point->curve_type == CURVE_ARC_SCCW_HALF) { + totalsize += 4 * _commandSize_float[VLC_OP_QUAD]; + } + } + + temp_stroke_path_data = path->stroke_path_data; + temp_stroke_path_size = path->stroke_path_size; + + path->stroke_path_size += totalsize; + if(path->stroke_path_size == 0) { + error = VG_LITE_INVALID_ARGUMENT; + goto ErrorHandler; + } + path->stroke_path_data = (void *)vg_lite_os_malloc(path->stroke_path_size); + if(!path->stroke_path_data) { + error = VG_LITE_OUT_OF_RESOURCES; + goto ErrorHandler; + } + + memset(path->stroke_path_data, 0, path->stroke_path_size); + + if(temp_stroke_path_data) { + memcpy(path->stroke_path_data,temp_stroke_path_data,temp_stroke_path_size); + vg_lite_os_free(temp_stroke_path_data); + temp_stroke_path_data = NULL; + } + + pfloat = (vg_lite_float_t *)((char *)path->stroke_path_data + temp_stroke_path_size); + if(last_opcode == VLC_OP_CLOSE) { + cpath = (char *)(pfloat - 1) + 1; + *cpath++ = VLC_OP_MOVE; + cpath = (char *)pfloat; + } + else { + cpath = (char *)pfloat; + *cpath = VLC_OP_MOVE; + pfloat++; + } + + *pfloat++ = point->x; + *pfloat++ = point->y; + real_size += _commandSize_float[VLC_OP_MOVE]; + if(last_opcode == VLC_OP_CLOSE) + real_size -= 4; + + for (point = point->next; point; prev_point = point, point = point->next) + { + if (point->curve_type == CURVE_LINE) + { + if (point->x == prev_point->x && point->y == prev_point->y) + { + path->stroke_path_size -= _commandSize_float[VLC_OP_LINE]; + /* Skip zero-length lines. */ + continue; + } + + /* Add new command. */ + cpath = (char *)pfloat; + *cpath = VLC_OP_LINE; + pfloat++; + + /* Set the coordinates. */ + *pfloat++ = point->x; + *pfloat++ = point->y; + real_size += _commandSize_float[VLC_OP_LINE]; + } + else if (point->curve_type == CURVE_QUAD_CONTROL) + { + /* Add new command. */ + cpath = (char *)pfloat; + *cpath = VLC_OP_QUAD; + pfloat++; + + /* Set the coordinates. */ + prev_point = point, point = point->next; + *pfloat++ = prev_point->x; + *pfloat++ = prev_point->y; + *pfloat++ = point->x; + *pfloat++ = point->y; + + real_size += _commandSize_float[VLC_OP_QUAD]; + } + else + { + vg_lite_path_point_ptr point_list, p, nextP; + vg_lite_path_point_ptr p2; + + if (point->curve_type == CURVE_ARC_SCCW) + { + /* Convert an arc to Bezier curves. */ + VG_LITE_ERROR_HANDLER(_convert_circle_arc(stroke_conversion, half_width, + point->centerX, point->centerY, + prev_point->x, prev_point->y, + point->x, point->y, + 0, &point_list)); + } + else + { + /* Convert a half circle to Bezier curves. */ + VG_LITE_ERROR_HANDLER(_convert_circle_arc(stroke_conversion, half_width, + point->centerX, point->centerY, + prev_point->x, prev_point->y, + point->x, point->y, + 1, &point_list)); + + } + + if (point_list) + { + for (p = point_list; p; p = nextP) + { + /* Add new command. */ + cpath = (char *)pfloat; + *cpath = VLC_OP_QUAD; + pfloat++; + + /* Set the coordinates. */ + p2 = p->next; + nextP = p2->next; + + *pfloat++ = p->x; + *pfloat++ = p->y; + *pfloat++ = p2->x; + *pfloat++ = p2->y; + real_size += _commandSize_float[VLC_OP_QUAD]; + vg_lite_os_free(p); + vg_lite_os_free(p2); + } + } + else + { + /* Handle special case of huge scaling. */ + /* Add new command. */ + cpath = (char *)pfloat; + *cpath = VLC_OP_LINE; + pfloat++; + + /* Set the coordinates. */ + *pfloat++ = point->x; + *pfloat++ = point->y; + real_size += _commandSize_float[VLC_OP_LINE]; + } + } + } + + /* Create a CLOSE_PATH command at the end. */ + cpath = (char *)pfloat; + if(sub_path->next) + *cpath = VLC_OP_CLOSE; + else + *cpath = VLC_OP_END; + real_size += _commandSize_float[VLC_OP_CLOSE]; + path->stroke_path_size = temp_stroke_path_size + real_size; + totalsize = 0; + real_size = 0; + sub_path = sub_path->next; + last_opcode = *cpath; + } + +ErrorHandler: + + if(temp_stroke_path_data) { + vg_lite_os_free(temp_stroke_path_data); + temp_stroke_path_data = NULL; + } + + return error; +} + +static vg_lite_error_t _initialize_stroke_dash_parameters( + vg_lite_stroke_conversion_t * stroke_conversion + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint32_t count; + uint32_t i; + vg_lite_float_t *pattern_src; + vg_lite_float_t *pattern,*temp_pattern; + vg_lite_float_t length; + + if(!stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + count = stroke_conversion->stroke_dash_pattern_count; + if (count == 0 || !stroke_conversion->stroke_dash_pattern) + return error; + + length = stroke_conversion->stroke_dash_phase; + + /* The last pattern is ignored if the number is odd. */ + if (count & 0x1) count--; + + pattern = (vg_lite_float_t *)vg_lite_os_malloc(count * sizeof(vg_lite_float_t)); + if(!pattern) + return VG_LITE_OUT_OF_RESOURCES; + + temp_pattern = pattern; + stroke_conversion->stroke_dash_pattern_length = 0.0f; + pattern_src = stroke_conversion->stroke_dash_pattern; + + for (i = 0; i < count; i++, pattern++, pattern_src++) + { + if (*pattern_src < 0.0f) + { + *pattern = 0.0f; + } + else + { + *pattern = *pattern_src; + } + stroke_conversion->stroke_dash_pattern_length += *pattern; + } + + if (stroke_conversion->stroke_dash_pattern_length < FLOAT_EPSILON) + { + stroke_conversion->stroke_dash_pattern_count = 0; + vg_lite_os_free(temp_pattern); + temp_pattern = NULL; + return error; + } + + while (length < 0.0f) + { + length += stroke_conversion->stroke_dash_pattern_length; + } + + while (length >= stroke_conversion->stroke_dash_pattern_length) + { + length -= stroke_conversion->stroke_dash_pattern_length; + } + + pattern = stroke_conversion->stroke_dash_pattern; + for (i = 0; i < stroke_conversion->stroke_dash_pattern_count; i++, pattern++) + { + if (length <= *pattern) break; + + length -= *pattern; + } + + stroke_conversion->stroke_dash_initial_index = i; + stroke_conversion->stroke_dash_initial_length = *pattern - length; + + vg_lite_os_free(temp_pattern); + temp_pattern = NULL; + + return error; +} + +vg_lite_error_t vg_lite_update_stroke( + vg_lite_path_t *path + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_stroke_conversion_t * stroke_conversion; + + if(!path) + return VG_LITE_INVALID_ARGUMENT; + + if(!path->path_length) + return VG_LITE_SUCCESS; + + if(!path->path) + return VG_LITE_INVALID_ARGUMENT; + + if (!path->stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + stroke_conversion = path->stroke_conversion; + + /* Free the stroke. */ + if (path->stroke_path_data) + { + vg_lite_os_free(path->stroke_path_data); + /* Reset the stroke. */ + path->stroke_path_data = NULL; + } + + if (stroke_conversion->stroke_line_width >= FLOAT_FAT_LINE_WIDTH + && stroke_conversion->stroke_line_width >= 1.0f) + { + stroke_conversion->is_fat = 1; + } + VG_LITE_RETURN_ERROR(_initialize_stroke_dash_parameters(stroke_conversion)); + VG_LITE_RETURN_ERROR(_flatten_path(stroke_conversion, path)); + VG_LITE_RETURN_ERROR(_create_stroke_path(stroke_conversion)); + VG_LITE_RETURN_ERROR(_copy_stroke_path(stroke_conversion, path)); + + return error; +} + +vg_lite_error_t vg_lite_set_stroke( + vg_lite_path_t *path, + vg_lite_cap_style_t stroke_cap_style, + vg_lite_join_style_t stroke_join_style, + vg_lite_float_t stroke_line_width, + vg_lite_float_t stroke_miter_limit, + vg_lite_float_t *stroke_dash_pattern, + uint32_t stroke_dash_pattern_count, + vg_lite_float_t stroke_dash_phase, + vg_lite_color_t stroke_color + ) +{ + if(!path || stroke_line_width <= 0) + return VG_LITE_INVALID_ARGUMENT; + + if(stroke_miter_limit < 1.0f) + stroke_miter_limit = 1.0f; + + if (!path->stroke_conversion) { + path->stroke_conversion = (vg_lite_stroke_conversion_t *)vg_lite_os_malloc(sizeof(vg_lite_stroke_conversion_t)); + if (!path->stroke_conversion) + return VG_LITE_OUT_OF_RESOURCES; + memset(path->stroke_conversion, 0, sizeof(vg_lite_stroke_conversion_t)); + } + + path->stroke_conversion->stroke_cap_style = stroke_cap_style; + path->stroke_conversion->stroke_join_style = stroke_join_style; + path->stroke_conversion->stroke_line_width = stroke_line_width; + path->stroke_conversion->stroke_miter_limit = stroke_miter_limit; + path->stroke_conversion->half_line_width = stroke_line_width / 2.0f; + path->stroke_conversion->stroke_miter_limit_square = path->stroke_conversion->stroke_miter_limit * path->stroke_conversion->stroke_miter_limit; + path->stroke_conversion->stroke_dash_pattern = stroke_dash_pattern; + path->stroke_conversion->stroke_dash_pattern_count = stroke_dash_pattern_count; + path->stroke_conversion->stroke_dash_phase = stroke_dash_phase; + path->stroke_color = stroke_color; + + return VG_LITE_SUCCESS; +} + +static inline vg_lite_error_t transform_bounding_box(vg_lite_rectangle_t *in_bbx, + vg_lite_matrix_t *matrix, + vg_lite_rectangle_t *clip, + vg_lite_rectangle_t *out_bbx, + vg_lite_point_t *origin); + +#if (VG_BLIT_WORKAROUND == 1) +/* + * Calculates the minimal possible target buffer starting from a given target + * buffer and considering a source texture (to blit), graphic transformations + * and clipping window. + */ +static vg_lite_error_t config_new_target(vg_lite_buffer_t *target, + vg_lite_buffer_t *source, + vg_lite_matrix_t *matrix, + vg_lite_rectangle_t *clip, + vg_lite_buffer_t *new_target); +#endif /* VG_BLIT_WORKAROUND */ + +static vg_lite_error_t swap(float *a,float *b) +{ + float temp; + if(a == NULL || b == NULL) + return VG_LITE_INVALID_ARGUMENT; + temp = *a; + *a = *b; + *b = temp; + return VG_LITE_SUCCESS; +} + +static vg_lite_float_t _angle( + vg_lite_float_t Ux, + vg_lite_float_t Uy, + vg_lite_float_t Vx, + vg_lite_float_t Vy + ) +{ + + vg_lite_float_t dot, length, angle, cosVal; + int32_t sign; + + dot = Ux * Vx + Uy * Vy; + length = SQRTF(Ux * Ux + Uy * Uy) * SQRTF(Vx * Vx + Vy * Vy); + sign = (Ux * Vy - Uy * Vx < 0) ? -1 : 1; + cosVal = dot / length; + cosVal = CLAMP(cosVal, -1.0f, 1.0f); + angle = sign * ACOSF(cosVal); + return angle; +} + +/*! + @discussion + Convert arc to multi-segment bezier curve. + @param HorRadius + Major axis radius. + @param VerRadius + minor axis radius. + @param RotAngle + Rotation angle. + @param EndX + End coordinate x. + @param EndX + End coordinate y. + @param CounterClockwise + If this is 0,anticlockwise rotation,if this is 1,clockwise rotation. + @param Large + 1 means big arc,0 means little arc. + @param Relative + 1 means absolute coordinates,0 means relative coordinates. + @param coords + Including the start point coordinates of the path,the control point of the last segment of the path, + and the end point of the last segment of the path. + @param path_data + Path data usr for internal conversion. + @param offset + The offset of path_data. + @param last_size + The remain unconverted size of the original path data. + @result + Error code. VG_LITE_INVALID_ARGUMENTS to indicate the parameters are wrong. +*/ +vg_lite_error_t _convert_arc( + vg_lite_float_t HorRadius, + vg_lite_float_t VerRadius, + vg_lite_float_t RotAngle, + vg_lite_float_t EndX, + vg_lite_float_t EndY, + uint8_t CounterClockwise, + uint8_t Large, + uint8_t Relative, + vg_lite_control_coord_t* coords, + void ** path_data, + uint32_t *offset, + uint32_t last_size + ) +{ + vg_lite_float_t endX, endY; + uint8_t segmentCommand; + vg_lite_float_t phi, cosPhi, sinPhi; + vg_lite_float_t dxHalf, dyHalf; + vg_lite_float_t x1Prime, y1Prime; + vg_lite_float_t rx, ry; + vg_lite_float_t x1PrimeSquare, y1PrimeSquare; + vg_lite_float_t lambda; + vg_lite_float_t rxSquare, rySquare; + int32_t sign; + vg_lite_float_t sq, signedSq; + vg_lite_float_t cxPrime, cyPrime; + vg_lite_float_t theta1, thetaSpan; + int32_t segs; + vg_lite_float_t theta, ax, ay, x, y; + vg_lite_float_t controlX, controlY, anchorX, anchorY; + vg_lite_float_t lastX, lastY; + uint32_t bufferSize; + char *pchar, *arcPath; + vg_lite_float_t *pfloat; + /******************************************************************* + ** Converting. + */ + if(path_data == NULL || *path_data == NULL || offset == NULL || coords == NULL) + return VG_LITE_INVALID_ARGUMENT; + + if (Relative) + { + endX = EndX + coords->lastX; + endY = EndY + coords->lastY; + } + else + { + endX = EndX; + endY = EndY; + } + + phi = RotAngle / 180.0f * PI; + cosPhi = COSF(phi); + sinPhi = SINF(phi); + + if (Relative) + { + dxHalf = - EndX / 2.0f; + dyHalf = - EndY / 2.0f; + } + else + { + dxHalf = (coords->lastX - endX) / 2.0f; + dyHalf = (coords->lastY - endY) / 2.0f; + } + + x1Prime = cosPhi * dxHalf + sinPhi * dyHalf; + y1Prime = -sinPhi * dxHalf + cosPhi * dyHalf; + + rx = FABSF(HorRadius); + ry = FABSF(VerRadius); + + x1PrimeSquare = x1Prime * x1Prime; + y1PrimeSquare = y1Prime * y1Prime; + + lambda = x1PrimeSquare / (rx * rx) + y1PrimeSquare / (ry * ry); + if (lambda > 1.0f) + { + rx *= SQRTF(lambda); + ry *= SQRTF(lambda); + } + + rxSquare = rx * rx; + rySquare = ry * ry; + + sign = (Large == CounterClockwise) ? -1 : 1; + sq = ( rxSquare * rySquare + - rxSquare * y1PrimeSquare + - rySquare * x1PrimeSquare + ) + / + ( rxSquare * y1PrimeSquare + + rySquare * x1PrimeSquare + ); + signedSq = sign * ((sq < 0) ? 0 : SQRTF(sq)); + cxPrime = signedSq * (rx * y1Prime / ry); + cyPrime = signedSq * -(ry * x1Prime / rx); + + theta1 = _angle(1, 0, (x1Prime - cxPrime) / rx, (y1Prime - cyPrime) / ry); + theta1 = FMODF(theta1, 2 * PI); + + thetaSpan = _angle(( x1Prime - cxPrime) / rx, ( y1Prime - cyPrime) / ry, + (-x1Prime - cxPrime) / rx, (-y1Prime - cyPrime) / ry); + + if (!CounterClockwise && (thetaSpan > 0)) + { + thetaSpan -= 2 * PI; + } + else if (CounterClockwise && (thetaSpan < 0)) + { + thetaSpan += 2 * PI; + } + + thetaSpan = FMODF(thetaSpan, 2 * PI); + + + /******************************************************************* + ** Drawing. + */ + + segs = (int32_t) (CEILF(FABSF(thetaSpan) / (45.0f / 180.0f * PI))); + + theta = thetaSpan / segs; + + ax = coords->lastX - COSF(theta1) * rx; + ay = coords->lastY - SINF(theta1) * ry; + + /* Determine the segment command. */ + segmentCommand = Relative + ? VLC_OP_QUAD_REL + : VLC_OP_QUAD; + + /* Determine the size of the buffer required. */ + bufferSize = (1 + 2 * 2) * SIZEOF(vg_lite_float_t) * segs; + + arcPath = (char *)vg_lite_os_malloc(*offset + bufferSize + last_size); + if (arcPath == NULL) + return VG_LITE_OUT_OF_MEMORY; + memset(arcPath, 0, *offset + bufferSize + last_size); + memcpy(arcPath,(char *)*path_data,*offset); + vg_lite_os_free(*path_data); + + *path_data = arcPath; + + pchar = arcPath + *offset; + pfloat = (vg_lite_float_t *)pchar; + + /* Set initial last point. */ + lastX = coords->lastX; + lastY = coords->lastY; + + while (segs-- > 0) + { + theta1 += theta; + + controlX = ax + COSF(theta1 - (theta / 2.0f)) * rx / COSF(theta / 2.0f); + controlY = ay + SINF(theta1 - (theta / 2.0f)) * ry / COSF(theta / 2.0f); + + anchorX = ax + COSF(theta1) * rx; + anchorY = ay + SINF(theta1) * ry; + + if (RotAngle != 0) + { + x = coords->lastX + cosPhi * (controlX - coords->lastX) - sinPhi * (controlY - coords->lastY); + y = coords->lastY + sinPhi * (controlX - coords->lastX) + cosPhi * (controlY - coords->lastY); + controlX = x; + controlY = y; + + x = coords->lastX + cosPhi * (anchorX - coords->lastX) - sinPhi * (anchorY - coords->lastY); + y = coords->lastY + sinPhi * (anchorX - coords->lastX) + cosPhi * (anchorY - coords->lastY); + anchorX = x; + anchorY = y; + } + + if (segs == 0) + { + /* Use end point directly to avoid accumulated errors. */ + anchorX = endX; + anchorY = endY; + } + + /* Adjust relative coordinates. */ + if (Relative) + { + vg_lite_float_t nextLastX = anchorX; + vg_lite_float_t nextLastY = anchorY; + + controlX -= lastX; + controlY -= lastY; + + anchorX -= lastX; + anchorY -= lastY; + + lastX = nextLastX; + lastY = nextLastY; + } + pchar = (char*)pfloat; + *pchar = segmentCommand ; + pfloat++; + *pfloat++ = controlX; + *pfloat++ = controlY; + *pfloat++ = anchorX; + *pfloat++ = anchorY; + *offset += (1 + 2 * 2) * SIZEOF(vg_lite_float_t); + } + + /* Update the control coordinates. */ + coords->lastX = endX; + coords->lastY = endY; + coords->controlX = endX; + coords->controlY = endY; + + return VG_LITE_SUCCESS; +} + +// added by MicroEJ +void __attribute__((weak)) vg_lite_draw_notify_render_area(uint32_t x, uint32_t y, uint32_t right, uint32_t bottom) +{ + /* + * Default implementation does nothing. Application can override this handler if it requires to be notified + * by the vglite rendering area. + */ + return; +} + +vg_lite_error_t _allocate_command_buffer(uint32_t size) +{ + vg_lite_kernel_allocate_t allocate; + vg_lite_error_t error = VG_LITE_SUCCESS; +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t *tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif + + if(size == 0) + return VG_LITE_SUCCESS; + + allocate.bytes = size; + allocate.contiguous = 1; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); + + ctx->context.command_buffer[0] = allocate.memory_handle; + ctx->context.command_buffer_logical[0] = allocate.memory; + ctx->context.command_buffer_physical[0] = allocate.memory_gpu; + + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); + + ctx->context.command_buffer[1] = allocate.memory_handle; + ctx->context.command_buffer_logical[1] = allocate.memory; + ctx->context.command_buffer_physical[1] = allocate.memory_gpu; + + ctx->command_buffer[0] = ctx->context.command_buffer_logical[0]; + ctx->command_buffer[1] = ctx->context.command_buffer_logical[1]; + + ctx->command_buffer_size = size; + ctx->command_offset[0] = 0; + ctx->command_offset[1] = 0; + ctx->command_buffer_current = 0; + +#if !defined(VG_DRIVER_SINGLE_THREAD) + ctx->start_offset = 0; + ctx->end_offset = 0; + ctx->ts_init = 0; + memset(ctx->ts_record, 0, sizeof(ctx->ts_record)); +#endif + + return error; +} + +vg_lite_error_t _free_command_buffer() +{ + vg_lite_kernel_free_t free; + vg_lite_error_t error = VG_LITE_SUCCESS; + +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif + + if(ctx->context.command_buffer[0]){ + free.memory_handle = ctx->context.command_buffer[0]; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &free)); + ctx->context.command_buffer[0] = 0; + ctx->context.command_buffer_logical[0] = 0; + } + + if(ctx->context.command_buffer[1]){ + free.memory_handle = ctx->context.command_buffer[1]; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &free)); + ctx->context.command_buffer[1] = 0; + ctx->context.command_buffer_logical[1] = 0; + } + + return error; +} + +static void ClampColor(FLOATVECTOR4 Source,FLOATVECTOR4 Target,uint8_t Premultiplied) +{ + vg_lite_float_t colorMax; + /* Clamp the alpha channel. */ + Target[3] = CLAMP(Source[3], 0.0f, 1.0f); + + /* Determine the maximum value for the color channels. */ + colorMax = Premultiplied ? Target[3] : 1.0f; + + /* Clamp the color channels. */ + Target[0] = CLAMP(Source[0], 0.0f, colorMax); + Target[1] = CLAMP(Source[1], 0.0f, colorMax); + Target[2] = CLAMP(Source[2], 0.0f, colorMax); +} + +static uint8_t PackColorComponent(vg_lite_float_t value) +{ + /* Compute the rounded normalized value. */ + vg_lite_float_t rounded = value * 255.0f + 0.5f; + + /* Get the integer part. */ + int32_t roundedInt = (int32_t) rounded; + + /* Clamp to 0..1 range. */ + uint8_t clamped = (uint8_t) CLAMP(roundedInt, 0, 255); + + /* Return result. */ + return clamped; +} + +#if !defined(VG_DRIVER_SINGLE_THREAD) +static void command_buffer_copy(void *new_cmd, void *old_cmd, uint32_t start, uint32_t end, uint32_t *cmd_count) +{ + uint32_t i = start,j; + uint32_t *p_new_cmd32,*p_cmd32,*temp; + uint32_t data_count = 0; + + memset(&hw,0,sizeof(vg_lite_hardware_t)); + temp = NULL; + p_new_cmd32 = (uint32_t *)new_cmd; + p_cmd32 = (uint32_t *)old_cmd; + while(i < end) + { + /* data command is 0x40000000 | count, and count = databytes / 8 ,and data command and databytes should align to 8 */ + if((*p_cmd32 & 0xF0000000) == 0x40000000) { + data_count = *p_cmd32 & 0x0FFFFFFF; + data_count++; + p_cmd32 += 2 * data_count; + i += data_count * 8; + /* SEMAPHORE command is 0x10000000 | id,stall command is 0x20000000 | id , call command is is 0x20000000 | count, + and this three command should occupy 8bytes*/ + }else if((*p_cmd32 & 0xF0000000) == 0x20000000 || (*p_cmd32 & 0xF0000000) == 0x10000000 + || (*p_cmd32 & 0xF0000000) == 0x60000000 || (*p_cmd32 & 0xF0000000) == 0x80000000){ + p_cmd32 += 2; + i += 8; + /* register command is 0x30000000 | ((count) << 16) | address, + and the bytes of this command add register count should align to 8 */ + }else if((*p_cmd32 & 0xF0000000) == 0x30000000) { + /* get register data count */ + data_count = (*p_cmd32 & 0x0FFFFFFF) >> 16; + if(data_count == 1) + { + temp = p_cmd32 + 1; + if(hw.hw_states[*p_cmd32 & 0xff].state != *temp || !hw.hw_states[*p_cmd32 & 0xff].init){ + hw.hw_states[*p_cmd32 & 0xff].state = *temp; + hw.hw_states[*p_cmd32 & 0xff].init = 1; + for(j = 0; j < 2; j++) { + *p_new_cmd32 = *p_cmd32; + p_new_cmd32++; + p_cmd32++; + *cmd_count += 4; + i += 4; + } + } + else + { + p_cmd32 += 2; + i += 8; + } + }else{ + /* the bytes of register count add register command */ + data_count++; + if(data_count % 2 != 0) + data_count++; + for(j = 0; j < data_count; j++) { + *p_new_cmd32 = *p_cmd32; + p_new_cmd32++; + p_cmd32++; + *cmd_count += 4; + i += 4; + } + } + } + } +} +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + +static void _memset(void *p, unsigned char value, int size) +{ + int i; + for (i = 0; i < size; i++) { + ((unsigned char*) p)[i] = value; + } +} + +static int has_valid_command_buffer(vg_lite_context_t *context) +{ + if(context == NULL) + return 0; + if(context->command_buffer_current >= CMDBUF_COUNT) + return 0; + if(context->command_buffer[context->command_buffer_current] == NULL) + return 0; + + return 1; +} + +#if !defined(VG_DRIVER_SINGLE_THREAD) +static int has_valid_context_buffer(vg_lite_context_t *context) +{ + if(context == NULL) + return 0; + + return 1; +} +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + +#if DUMP_IMAGE +static void dump_img(void * memory, int width, int height, vg_lite_buffer_format_t format) +{ + FILE * fp; + char imgname[255] = {'\0'}; + int i; + static int num = 1; + unsigned int* pt = (unsigned int*) memory; + + sprintf(imgname, "img_pid%d_%d.txt", getpid(), num++); + + fp = fopen(imgname, "w"); + + if (fp == NULL) + printf("error!\n"); + + + switch (format) { + case VG_LITE_INDEX_1: + for(i = 0; i < width * height / 32; ++i) + { + fprintf(fp, "0x%08x\n",pt[i]); + } + break; + + case VG_LITE_INDEX_2: + for(i = 0; i < width * height / 16; ++i) + { + fprintf(fp, "0x%08x\n",pt[i]); + } + break; + + case VG_LITE_INDEX_4: + for(i = 0; i < width * height / 8; ++i) + { + fprintf(fp, "0x%08x\n",pt[i]); + } + break; + + case VG_LITE_INDEX_8: + for(i = 0; i < width * height / 4; ++i) + { + fprintf(fp, "0x%08x\n",pt[i]); + } + break; + + case VG_LITE_RGBA2222: + for(i = 0; i < width * height / 4; ++i) + { + fprintf(fp, "0x%08x\n",pt[i]); + } + break; + + case VG_LITE_RGBA4444: + case VG_LITE_BGRA4444: + case VG_LITE_RGB565: + case VG_LITE_BGR565: + for(i = 0; i < width * height / 2; ++i) + { + fprintf(fp, "0x%08x\n",pt[i]); + } + break; + + case VG_LITE_RGBA8888: + case VG_LITE_BGRA8888: + case VG_LITE_RGBX8888: + case VG_LITE_BGRX8888: + for(i = 0; i < width * height; ++i) + { + fprintf(fp, "0x%08x\n",pt[i]); + } + break; + + default: + break; + } + fclose(fp); + fp = NULL; +} +#endif + +/* Convert VGLite data format to HW value. */ +static uint32_t convert_path_format(vg_lite_format_t format) +{ + switch (format) { + case VG_LITE_S8: + return 0; + + case VG_LITE_S16: + return 0x100000; + + case VG_LITE_S32: + return 0x200000; + + case VG_LITE_FP32: + return 0x300000; + + default: + return 0; + } +} + +/* Convert VGLite quality enums to HW values. */ +static uint32_t convert_path_quality(vg_lite_quality_t quality) +{ + switch (quality) { + case VG_LITE_HIGH: + return 0x3; + + case VG_LITE_UPPER: + return 0x2; + + case VG_LITE_MEDIUM: + return 0x1; + + default: + return 0x0; + } +} + +static uint32_t rgb_to_l(uint32_t color) +{ + uint32_t l = (uint32_t)((0.2126f * (vg_lite_float_t)(color & 0xFF)) + + (0.7152f * (vg_lite_float_t)((color >> 8) & 0xFF)) + + (0.0722f * (vg_lite_float_t)((color >> 16) & 0xFF))); + return l | (l << 24); +} + +/* Get the bpp information of a color format. */ +static void get_format_bytes(vg_lite_buffer_format_t format, + uint32_t *mul, + uint32_t *div, + uint32_t *bytes_align) +{ + *mul = *div = 1; + *bytes_align = 4; + switch (format) { + case VG_LITE_L8: + case VG_LITE_A8: + *bytes_align = 16; + break; + + case VG_LITE_A4: + *div = 2; + *bytes_align = 8; + break; + + case VG_LITE_ABGR1555: + case VG_LITE_ARGB1555: + case VG_LITE_BGRA5551: + case VG_LITE_RGBA5551: + case VG_LITE_RGBA4444: + case VG_LITE_BGRA4444: + case VG_LITE_ABGR4444: + case VG_LITE_ARGB4444: + case VG_LITE_RGB565: + case VG_LITE_BGR565: + case VG_LITE_YUYV: + case VG_LITE_YUY2: + case VG_LITE_YUY2_TILED: + /* AYUY2 buffer memory = YUY2 + alpha. */ + case VG_LITE_AYUY2: + case VG_LITE_AYUY2_TILED: + *mul = 2; + *bytes_align = 32; + break; + + case VG_LITE_RGBA8888: + case VG_LITE_BGRA8888: + case VG_LITE_ABGR8888: + case VG_LITE_ARGB8888: + case VG_LITE_RGBX8888: + case VG_LITE_BGRX8888: + case VG_LITE_XBGR8888: + case VG_LITE_XRGB8888: + *mul = 4; + *bytes_align = 64; + break; + + case VG_LITE_NV12: + case VG_LITE_NV12_TILED: + *mul = 3; + *bytes_align = 32; + break; + + case VG_LITE_ANV12: + case VG_LITE_ANV12_TILED: + *mul = 4; + *bytes_align = 64; + break; + + case VG_LITE_INDEX_1: + *div = 8; + *bytes_align = 8; + break; + + case VG_LITE_INDEX_2: + *div = 4; + *bytes_align = 8; + break; + + case VG_LITE_INDEX_4: + *div = 2; + *bytes_align = 8; + break; + + case VG_LITE_INDEX_8: + *bytes_align = 16; + break; + + case VG_LITE_RGBA2222: + case VG_LITE_BGRA2222: + case VG_LITE_ABGR2222: + case VG_LITE_ARGB2222: + *mul = 1; + *bytes_align = 8; + break; + + default: + break; + } +} + +/* Convert VGLite target color format to HW value. */ +static uint32_t convert_target_format(vg_lite_buffer_format_t format, vg_lite_capabilities_t caps) +{ + switch (format) { + case VG_LITE_A8: + return 0x0; + + case VG_LITE_L8: + return 0x6; + + case VG_LITE_ABGR4444: + return 0x14; + + case VG_LITE_ARGB4444: + return 0x34; + + case VG_LITE_RGBA4444: + return 0x24; + + case VG_LITE_BGRA4444: + return 0x4; + + case VG_LITE_RGB565: + return 0x21; + + case VG_LITE_BGR565: + return 0x1; + + case VG_LITE_ABGR8888: + return 0x13; + + case VG_LITE_ARGB8888: + return 0x33; + + case VG_LITE_RGBA8888: + return 0x23; + + case VG_LITE_BGRA8888: + return 0x3; + + case VG_LITE_RGBX8888: + return 0x22; + + case VG_LITE_BGRX8888: + return 0x2; + + case VG_LITE_XBGR8888: + return 0x12; + + case VG_LITE_XRGB8888: + return 0x32; + + case VG_LITE_ABGR1555: + return 0x15; + + case VG_LITE_RGBA5551: + return 0x25; + + case VG_LITE_ARGB1555: + return 0x35; + + case VG_LITE_BGRA5551: + return 0x5; + + case VG_LITE_YUYV: + case VG_LITE_YUY2: + case VG_LITE_YUY2_TILED: + return 0x8; + + case VG_LITE_NV12: + case VG_LITE_NV12_TILED: + return 0xB; + + case VG_LITE_ANV12: + case VG_LITE_ANV12_TILED: + return 0xE; + + case VG_LITE_BGRA2222: + return 0x7; + + case VG_LITE_RGBA2222: + return 0x27; + + case VG_LITE_ABGR2222: + return 0x17; + + case VG_LITE_ARGB2222: + return 0x37; + + case VG_LITE_AYUY2: + case VG_LITE_AYUY2_TILED: + default: + return 0xF; + } +} + +/* determine source IM is aligned by specified bytes */ +static vg_lite_error_t _check_source_aligned(vg_lite_buffer_format_t format,uint32_t stride) +{ + switch (format) { + case VG_LITE_A4: + case VG_LITE_INDEX_1: + case VG_LITE_INDEX_2: + case VG_LITE_INDEX_4: + FORMAT_ALIGNMENT(stride,8); + break; + + case VG_LITE_L8: + case VG_LITE_A8: + case VG_LITE_INDEX_8: + case VG_LITE_RGBA2222: + case VG_LITE_BGRA2222: + case VG_LITE_ABGR2222: + case VG_LITE_ARGB2222: + FORMAT_ALIGNMENT(stride,16); + break; + + case VG_LITE_RGBA4444: + case VG_LITE_BGRA4444: + case VG_LITE_ABGR4444: + case VG_LITE_ARGB4444: + case VG_LITE_RGB565: + case VG_LITE_BGR565: + case VG_LITE_BGRA5551: + case VG_LITE_RGBA5551: + case VG_LITE_ABGR1555: + case VG_LITE_ARGB1555: + case VG_LITE_YUYV: + case VG_LITE_YUY2: + case VG_LITE_NV12: + case VG_LITE_YV12: + case VG_LITE_YV24: + case VG_LITE_YV16: + case VG_LITE_NV16: + FORMAT_ALIGNMENT(stride,32); + break; + + case VG_LITE_RGBA8888: + case VG_LITE_BGRA8888: + case VG_LITE_ABGR8888: + case VG_LITE_ARGB8888: + case VG_LITE_RGBX8888: + case VG_LITE_BGRX8888: + case VG_LITE_XBGR8888: + case VG_LITE_XRGB8888: + FORMAT_ALIGNMENT(stride,64); + break; + + default: + return VG_LITE_SUCCESS; + } +} + +/* Convert VGLite source color format to HW values. */ +static uint32_t convert_source_format(vg_lite_buffer_format_t format) +{ + switch (format) { + case VG_LITE_L8: + return 0x0; + + case VG_LITE_A4: + return 0x1; + + case VG_LITE_A8: + return 0x2; + + case VG_LITE_RGBA4444: + return 0x23; + + case VG_LITE_BGRA4444: + return 0x3; + + case VG_LITE_ABGR4444: + return 0x13; + + case VG_LITE_ARGB4444: + return 0x33; + + case VG_LITE_RGB565: + return 0x25; + + case VG_LITE_BGR565: + return 0x5; + + case VG_LITE_RGBA8888: + return 0x27; + + case VG_LITE_BGRA8888: + return 0x7; + + case VG_LITE_ABGR8888: + return 0x17; + + case VG_LITE_ARGB8888: + return 0x37; + + case VG_LITE_RGBX8888: + return 0x26; + + case VG_LITE_BGRX8888: + return 0x6; + + case VG_LITE_XBGR8888: + return 0x16; + + case VG_LITE_XRGB8888: + return 0x36; + + case VG_LITE_BGRA5551: + return 0x4; + + case VG_LITE_RGBA5551: + return 0x24; + + case VG_LITE_ABGR1555: + return 0x14; + + case VG_LITE_ARGB1555: + return 0x34; + + case VG_LITE_YUYV: + return 0x8; + + case VG_LITE_YUY2: + case VG_LITE_YUY2_TILED: + return 0x8; + + case VG_LITE_NV12: + case VG_LITE_NV12_TILED: + return 0xB; + + case VG_LITE_ANV12: + case VG_LITE_ANV12_TILED: + return 0xE; + + case VG_LITE_YV12: + return 0x9; + + case VG_LITE_YV24: + return 0xD; + + case VG_LITE_YV16: + return 0xC; + + case VG_LITE_NV16: + return 0xA; + + case VG_LITE_AYUY2: + case VG_LITE_AYUY2_TILED: + default: + return 0xF; + + case VG_LITE_INDEX_1: + return 0x200; + + case VG_LITE_INDEX_2: + return 0x400; + + case VG_LITE_INDEX_4: + return 0x600; + + case VG_LITE_INDEX_8: + return 0x800; + + case VG_LITE_RGBA2222: + return 0xA20; + + case VG_LITE_BGRA2222: + return 0xA00; + + case VG_LITE_ABGR2222: + return 0xA10; + + case VG_LITE_ARGB2222: + return 0xA30; + } +} + +/* Convert VGLite blend modes to HW values. */ +static uint32_t convert_blend(vg_lite_blend_t blend) +{ + switch (blend) { + case VG_LITE_BLEND_SRC_OVER: + return 0x00000100; + + case VG_LITE_BLEND_DST_OVER: + return 0x00000200; + + case VG_LITE_BLEND_SRC_IN: + return 0x00000300; + + case VG_LITE_BLEND_DST_IN: + return 0x00000400; + + case VG_LITE_BLEND_SCREEN: + return 0x00000600; + + case VG_LITE_BLEND_MULTIPLY: + return 0x00000500; + + case VG_LITE_BLEND_ADDITIVE: + return 0x00000900; + + case VG_LITE_BLEND_SUBTRACT: + return 0x00000A00; + + default: + return 0; + } +} + +/* Convert VGLite uv swizzle enums to HW values. */ +static uint32_t convert_uv_swizzle(vg_lite_swizzle_t swizzle) +{ + switch (swizzle) { + case VG_LITE_SWIZZLE_UV: + return 0x00000040; + break; + + case VG_LITE_SWIZZLE_VU: + return 0x00000050; + + default: + return 0; + break; + } +} + +/* Convert VGLite yuv standard enums to HW values. */ +static uint32_t convert_yuv2rgb(vg_lite_yuv2rgb_t yuv) +{ + switch (yuv) { + case VG_LITE_YUV601: + return 0; + break; + + case VG_LITE_YUV709: + return 0x00008000; + + default: + return 0; + break; + } +} + +/* Initialize the feature table of a chip. */ +static vg_lite_error_t fill_feature_table(uint32_t * feature) +{ + uint16_t size = sizeof(VGFeatureInfos) / sizeof(VGFeatureInfos[0]); + uint16_t i; + uint32_t cid = 0; + +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif + + /* Clear all bits. */ + _memset(feature, 0, sizeof(uint32_t) * gcFEATURE_COUNT); + vg_lite_get_product_info(NULL,&ctx->chip_id,&ctx->chip_rev); + if(ctx->chip_id == GPU_CHIP_ID_GC355) + ctx->premultiply_enabled = 1; + vg_lite_get_register(0x30, &cid); + + for(i = 0;i < size; i++){ + if ((VGFeatureInfos[i].chip_id == ctx->chip_id) + && (VGFeatureInfos[i].chip_version == ctx->chip_rev) + && (VGFeatureInfos[i].cid == cid) + ) + { + feature[gcFEATURE_BIT_VG_IM_INDEX_FORMAT] = VGFeatureInfos[i].vg_im_index_format; + feature[gcFEATURE_BIT_VG_PE_PREMULTIPLY] = VGFeatureInfos[i].vg_pe_premultiply; + feature[gcFEATURE_BIT_VG_BORDER_CULLING] = VGFeatureInfos[i].vg_border_culling; + feature[gcFEATURE_BIT_VG_RGBA2_FORMAT] = VGFeatureInfos[i].vg_rgba2_format; + feature[gcFEATURE_BIT_VG_QUALITY_8X] = VGFeatureInfos[i].vg_quality_8x; + feature[gcFEATURE_BIT_VG_RADIAL_GRADIENT] = VGFeatureInfos[i].vg_radial_gradient; + feature[gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT] = VGFeatureInfos[i].vg_linear_gradient_ext; + feature[gcFEATURE_BIT_VG_DITHER] = VGFeatureInfos[i].vg_dither; + feature[gcFEATURE_BIT_VG_COLOR_KEY] = VGFeatureInfos[i].vg_color_key; + break; + } + } + + if(i == size) { + return VG_LITE_INVALID_ARGUMENT; + } + ctx->s_ftable.ftflag = 1; + + return VG_LITE_SUCCESS; +} + +#if !defined(VG_DRIVER_SINGLE_THREAD) +static vg_lite_error_t flush(vg_lite_context_t *context); +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ +static vg_lite_error_t submit(vg_lite_context_t * context); +#if defined(VG_DRIVER_SINGLE_THREAD) +static vg_lite_error_t stall(vg_lite_context_t * context, uint32_t time_ms, uint32_t mask); +#else +static vg_lite_error_t stall(vg_lite_context_t * context, uint32_t time_ms); +#endif /* VG_DRIVER_SINGLE_THREAD */ + +#if !defined(VG_DRIVER_SINGLE_THREAD) +/* Push a state array into context buffer. */ +static vg_lite_error_t push_states_to_context(vg_lite_context_t * context, uint32_t address, uint32_t count, uint32_t *data) +{ + uint32_t i, command_id; + vg_lite_error_t error; + if (!has_valid_context_buffer(context)) + return VG_LITE_NO_CONTEXT; + + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + /* Reserve enough space in the context buffer for flush and submit */ + if (context->context_buffer_offset[command_id] + 8 >= context->context_buffer_size) { + return VG_LITE_OUT_OF_RESOURCES; + } + + ((uint32_t *) (context->context_buffer[command_id] + context->context_buffer_offset[command_id]))[0] = VG_LITE_STATES(count, address); + + for (i = 0; i < count; i++) { + ((uint32_t *) (context->context_buffer[command_id] + context->context_buffer_offset[command_id]))[1 + i] = data[i]; + } + if (i%2 == 0) { + ((uint32_t *) (context->context_buffer[command_id] + context->context_buffer_offset[command_id]))[1 + i] = VG_LITE_NOP(); + } + + context->context_buffer_offset[command_id] += VG_LITE_ALIGN(count + 1, 2) * 4; + + return VG_LITE_SUCCESS; +} + +static vg_lite_error_t update_context_buffer() +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_kernel_context_switch_t check; + vg_lite_tls_t* tls; + uint32_t command_id; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + command_id = CMDBUF_INDEX(tls->t_context); + check.context =(uint32_t)&tls->t_context.context; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_QUERY_CONTEXT_SWITCH, &check)); + /* if context have been switched and this task need use index. */ + if(check.isContextSwitched && tls->t_context.index_format) + { + uint32_t clut_addr[4]={0x0A98,0x0A9C,0x0AA0,0x0B00}; + uint32_t clut_count[4]={2,4,16,256}; + + for(int i = 0; i < 4; i++) + { + /* check which index colors would be use in this task. */ + if(tls->t_context.colors[i] && tls->t_context.clut_used[i]){ + VG_LITE_RETURN_ERROR(push_states_to_context(&tls->t_context, clut_addr[i], clut_count[i], tls->t_context.colors[i])); + tls->t_context.clut_used[i] = 0; + } + } + tls->t_context.index_format = 0; + } + + /* Set tessellation buffer states */ + if(check.isContextSwitched && tls->t_context.ts_init && !tls->t_context.ts_init_used && tls->t_context.ts_init_use){ + /* Reserve enough space in the context buffer for flush and submit */ + if (tls->t_context.context_buffer_offset[command_id] + 80 >= tls->t_context.context_buffer_size) { + return VG_LITE_OUT_OF_RESOURCES; + } + memcpy(tls->t_context.context_buffer[command_id] + tls->t_context.context_buffer_offset[command_id], tls->t_context.ts_record, 80); + tls->t_context.ts_init = 0; + tls->t_context.ts_init_used = 0; + tls->t_context.ts_init_use = 0; + tls->t_context.context_buffer_offset[command_id] += 80; + } + + if(tls->t_context.context_buffer_offset[command_id]){ + ((uint32_t *) (tls->t_context.context_buffer[command_id] + tls->t_context.context_buffer_offset[command_id]))[0] = VG_LITE_RETURN(); + ((uint32_t *) (tls->t_context.context_buffer[command_id] + tls->t_context.context_buffer_offset[command_id]))[1] = 0; + tls->t_context.context_buffer_offset[command_id] += 8; + ((uint32_t *) CMDBUF_BUFFER(tls->t_context))[0] = VG_LITE_CALL((tls->t_context.context_buffer_offset[command_id] + 7) / 8); + ((uint32_t *) CMDBUF_BUFFER(tls->t_context))[1] = tls->t_context.context.context_buffer_physical[command_id]; + tls->t_context.context_buffer_offset[command_id] = 0; + } + + return error; +} +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + +#if defined(VG_DRIVER_SINGLE_THREAD) +/* Push a state array into current command buffer. */ +static vg_lite_error_t push_states(vg_lite_context_t * context, uint32_t address, uint32_t count, uint32_t *data) +{ + uint32_t i; + vg_lite_error_t error; + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + if (CMDBUF_OFFSET(*context) + 8 + VG_LITE_ALIGN(count + 1, 2) * 4 >= CMDBUF_SIZE(*context)) { + VG_LITE_RETURN_ERROR(submit(context)); + VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); + } + + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATES(count, address); + + for (i = 0; i < count; i++) { + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1 + i] = data[i]; + } + if (i%2 == 0) { + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1 + i] = VG_LITE_NOP(); + } + + CMDBUF_OFFSET(*context) += VG_LITE_ALIGN(count + 1, 2) * 4; + + return VG_LITE_SUCCESS; +} + +/* Push a single state command into the current command buffer. */ +static vg_lite_error_t push_state(vg_lite_context_t * context, uint32_t address, uint32_t data) +{ + vg_lite_error_t error; + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + if (CMDBUF_OFFSET(*context) + 16 >= CMDBUF_SIZE(*context)) { + VG_LITE_RETURN_ERROR(submit(context)); + VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); + } + + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATE(address); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = data; + + CMDBUF_OFFSET(*context) += 8; + + return VG_LITE_SUCCESS; +} + +/* Push a single state command with given address. */ +static vg_lite_error_t push_state_ptr(vg_lite_context_t * context, uint32_t address, void * data_ptr) +{ + vg_lite_error_t error; + uint32_t data = *(uint32_t *) data_ptr; + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + if (CMDBUF_OFFSET(*context) + 16 >= CMDBUF_SIZE(*context)) { + VG_LITE_RETURN_ERROR(submit(context)); + VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); + } + + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATE(address); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = data; + + CMDBUF_OFFSET(*context) += 8; + + return VG_LITE_SUCCESS; +} + +/* Push a "call" command into the current command buffer. */ +static vg_lite_error_t push_call(vg_lite_context_t * context, uint32_t address, uint32_t bytes) +{ + vg_lite_error_t error; + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + if (CMDBUF_OFFSET(*context) + 16 >= CMDBUF_SIZE(*context)) { + VG_LITE_RETURN_ERROR(submit(context)); + VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); + } + + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_CALL((bytes + 7) / 8); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = address; + + CMDBUF_OFFSET(*context) += 8; + + return VG_LITE_SUCCESS; +} + +/* Push a rectangle command into the current command buffer. */ +static vg_lite_error_t push_rectangle(vg_lite_context_t * context, int x, int y, int width, int height) +{ + vg_lite_error_t error; + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + if (CMDBUF_OFFSET(*context) + 16 >= CMDBUF_SIZE(*context)) { + VG_LITE_RETURN_ERROR(submit(context)); + VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); + } + + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_DATA(1); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; + ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[4] = (uint16_t)x; + ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[5] = (uint16_t)y; + ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[6] = (uint16_t)width; + ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[7] = (uint16_t)height; + + CMDBUF_OFFSET(*context) += 16; + + return VG_LITE_SUCCESS; +} + +/* Push a data array into the current command buffer. */ +static vg_lite_error_t push_data(vg_lite_context_t * context, int size, void * data) +{ + vg_lite_error_t error; + int bytes = VG_LITE_ALIGN(size, 8); + + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + if (CMDBUF_OFFSET(*context) + 16 + bytes >= CMDBUF_SIZE(*context)) { + VG_LITE_RETURN_ERROR(submit(context)); + VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); + } + + ((uint64_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(bytes / 8)] = 0; + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_DATA(bytes / 8); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; + memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context) + 8, data, size); + + CMDBUF_OFFSET(*context) += 8 + bytes; + + return VG_LITE_SUCCESS; +} + +/* Push a "stall" command into the current command buffer. */ +static vg_lite_error_t push_stall(vg_lite_context_t * context, uint32_t module) +{ + vg_lite_error_t error; + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + if (CMDBUF_OFFSET(*context) + 16 >= CMDBUF_SIZE(*context)) { + VG_LITE_RETURN_ERROR(submit(context)); + VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); + } + + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_SEMAPHORE(module); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[2] = VG_LITE_STALL(module); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[3] = 0; + + CMDBUF_OFFSET(*context) += 16; + + return VG_LITE_SUCCESS; +} + +#else + +/* Push a state array into current command buffer. */ +static vg_lite_error_t push_states(vg_lite_context_t * context, uint32_t address, uint32_t count, uint32_t *data) +{ + uint32_t i, command_id, index; + vg_lite_error_t error; + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + /* Reserve enough space in the command buffer for flush and submit */ + if (CMDBUF_OFFSET(*context) + 40 + VG_LITE_ALIGN(count + 1, 2) * 4 >= CMDBUF_SIZE(*context)) { + uint32_t cmd_count = 0,start_offset = 0; + context->end_offset = CMDBUF_OFFSET(*context); + start_offset = context->start_offset; + VG_LITE_RETURN_ERROR(flush(context)); + VG_LITE_RETURN_ERROR(submit(context)); + CMDBUF_SWAP(*context); + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + RESERVE_BYTES_IN_CMDBUF(*context); + + if(context->ts_init){ + memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); + CMDBUF_OFFSET(*context) += 80; + context->ts_init_used = 1; + } + + /* update start offset */ + context->start_offset = CMDBUF_OFFSET(*context); + + index = (command_id? 0 : 1); + command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), + start_offset, context->end_offset, &cmd_count); + CMDBUF_OFFSET(*context) += cmd_count; + } + + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATES(count, address); + + for (i = 0; i < count; i++) { + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1 + i] = data[i]; + } + if (i%2 == 0) { + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1 + i] = VG_LITE_NOP(); + } + +#if DUMP_COMMAND + { + uint32_t loops; + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, ", + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0]); + + for (loops = 0; loops < count / 2; loops++) { + fprintf(fp, "0x%08x,\nCommand buffer: 0x%08x, ", + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(loops + 1) * 2 - 1], + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(loops + 1) * 2]); + } + + fprintf(fp, "0x%08x,\n", + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(loops + 1) * 2 - 1]); + + fclose(fp); + fp = NULL; + } +#endif + + CMDBUF_OFFSET(*context) += VG_LITE_ALIGN(count + 1, 2) * 4; + + return VG_LITE_SUCCESS; +} + +/* Push a single state command into the current command buffer. */ +static vg_lite_error_t push_state(vg_lite_context_t * context, uint32_t address, uint32_t data) +{ + vg_lite_error_t error; + uint32_t command_id, index; + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + /* Reserve enough space in the command buffer for flush and submit */ + if (CMDBUF_OFFSET(*context) + 56 >= CMDBUF_SIZE(*context)) { + uint32_t cmd_count = 0,start_offset = 0; + context->end_offset = CMDBUF_OFFSET(*context); + start_offset = context->start_offset; + VG_LITE_RETURN_ERROR(flush(context)); + VG_LITE_RETURN_ERROR(submit(context)); + CMDBUF_SWAP(*context); + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + RESERVE_BYTES_IN_CMDBUF(*context); + + if(context->ts_init){ + memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); + CMDBUF_OFFSET(*context) += 80; + context->ts_init_used = 1; + } + + /* update start offset */ + context->start_offset = CMDBUF_OFFSET(*context); + + index = (command_id? 0 : 1); + command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), + start_offset, context->end_offset, &cmd_count); + CMDBUF_OFFSET(*context) += cmd_count; + } + + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATE(address); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = data; + +#if DUMP_COMMAND + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1]); + + fclose(fp); + fp = NULL; +#endif + + CMDBUF_OFFSET(*context) += 8; + + return VG_LITE_SUCCESS; +} + +/* Push a single state command with given address. */ +static vg_lite_error_t push_state_ptr(vg_lite_context_t * context, uint32_t address, void * data_ptr) +{ + vg_lite_error_t error; + uint32_t command_id, index; + uint32_t data = *(uint32_t *) data_ptr; + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + /* Reserve enough space in the command buffer for flush and submit */ + if (CMDBUF_OFFSET(*context) + 56 >= CMDBUF_SIZE(*context)) { + uint32_t cmd_count = 0,start_offset = 0; + context->end_offset = CMDBUF_OFFSET(*context); + start_offset = context->start_offset; + VG_LITE_RETURN_ERROR(flush(context)); + VG_LITE_RETURN_ERROR(submit(context)); + CMDBUF_SWAP(*context); + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + RESERVE_BYTES_IN_CMDBUF(*context); + + if(context->ts_init){ + memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); + CMDBUF_OFFSET(*context) += 80; + context->ts_init_used = 1; + } + + /* update start offset */ + context->start_offset = CMDBUF_OFFSET(*context); + + index = (command_id? 0 : 1); + command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), + start_offset, context->end_offset, &cmd_count); + CMDBUF_OFFSET(*context) += cmd_count; + } + + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATE(address); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = data; + +#if DUMP_COMMAND + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1]); + + fclose(fp); + fp = NULL; +#endif + + CMDBUF_OFFSET(*context) += 8; + + return VG_LITE_SUCCESS; +} + +/* Push a "call" command into the current command buffer. */ +static vg_lite_error_t push_call(vg_lite_context_t * context, uint32_t address, uint32_t bytes) +{ + vg_lite_error_t error; + uint32_t command_id, index; + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + /* Reserve enough space in the command buffer for flush and submit */ + if (CMDBUF_OFFSET(*context) + 56 >= CMDBUF_SIZE(*context)) { + uint32_t cmd_count = 0,start_offset = 0; + context->end_offset = CMDBUF_OFFSET(*context); + start_offset = context->start_offset; + VG_LITE_RETURN_ERROR(flush(context)); + VG_LITE_RETURN_ERROR(submit(context)); + CMDBUF_SWAP(*context); + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + RESERVE_BYTES_IN_CMDBUF(*context); + + if(context->ts_init){ + memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); + CMDBUF_OFFSET(*context) += 80; + context->ts_init_used = 1; + } + + /* update start offset */ + context->start_offset = CMDBUF_OFFSET(*context); + + index = (command_id? 0 : 1); + command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), + start_offset, context->end_offset, &cmd_count); + CMDBUF_OFFSET(*context) += cmd_count; + } + + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_CALL((bytes + 7) / 8); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = address; + +#if DUMP_COMMAND + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1]); + + fclose(fp); + fp = NULL; +#endif + + CMDBUF_OFFSET(*context) += 8; + + return VG_LITE_SUCCESS; +} + +/* Push a rectangle command into the current command buffer. */ +static vg_lite_error_t push_rectangle(vg_lite_context_t * context, int x, int y, int width, int height) +{ + vg_lite_error_t error; + uint32_t command_id, index; + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + /* Reserve enough space in the command buffer for flush and submit */ + if (CMDBUF_OFFSET(*context) + 56 >= CMDBUF_SIZE(*context)) { + uint32_t cmd_count = 0,start_offset = 0; + context->end_offset = CMDBUF_OFFSET(*context); + start_offset = context->start_offset; + VG_LITE_RETURN_ERROR(flush(context)); + VG_LITE_RETURN_ERROR(submit(context)); + CMDBUF_SWAP(*context); + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + RESERVE_BYTES_IN_CMDBUF(*context); + + if(context->ts_init){ + memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); + CMDBUF_OFFSET(*context) += 80; + context->ts_init_used = 1; + } + + /* update start offset */ + context->start_offset = CMDBUF_OFFSET(*context); + + index = (command_id? 0 : 1); + command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), + start_offset, context->end_offset, &cmd_count); + CMDBUF_OFFSET(*context) += cmd_count; + } + + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_DATA(1); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; + ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[4] = (uint16_t)x; + ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[5] = (uint16_t)y; + ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[6] = (uint16_t)width; + ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[7] = (uint16_t)height; + +#if DUMP_COMMAND + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], 0); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[5] << 16 | + ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[4], + ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[7] << 16 | + ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[6]); + + fclose(fp); + fp = NULL; +#endif + + CMDBUF_OFFSET(*context) += 16; + + return VG_LITE_SUCCESS; +} + +/* Push a data array into the current command buffer. */ +static vg_lite_error_t push_data(vg_lite_context_t * context, int size, void * data) +{ + vg_lite_error_t error; + uint32_t command_id, index; + int bytes = VG_LITE_ALIGN(size, 8); + + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + /* Reserve enough space in the command buffer for flush and submit */ + if (CMDBUF_OFFSET(*context) + 48 + bytes >= CMDBUF_SIZE(*context)) { + uint32_t cmd_count = 0,start_offset = 0; + context->end_offset = CMDBUF_OFFSET(*context); + start_offset = context->start_offset; + VG_LITE_RETURN_ERROR(flush(context)); + VG_LITE_RETURN_ERROR(submit(context)); + CMDBUF_SWAP(*context); + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + RESERVE_BYTES_IN_CMDBUF(*context); + + if(context->ts_init){ + memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); + CMDBUF_OFFSET(*context) += 80; + context->ts_init_used = 1; + } + + /* update start offset */ + context->start_offset = CMDBUF_OFFSET(*context); + index = (command_id? 0 : 1); + command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), + start_offset, context->end_offset, &cmd_count); + CMDBUF_OFFSET(*context) += cmd_count; + } + + ((uint64_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(bytes / 8)] = 0; + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_DATA(bytes / 8); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; + memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context) + 8, data, size); + +#if DUMP_COMMAND + { + int loops; + + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], 0); + for (loops = 0; loops < bytes / 8; loops++) { + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(loops + 1) * 2], + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(loops + 1) * 2 + 1]); + } + + fclose(fp); + fp = NULL; + } +#endif + + CMDBUF_OFFSET(*context) += 8 + bytes; + + return VG_LITE_SUCCESS; +} + +/* Push a "stall" command into the current command buffer. */ +static vg_lite_error_t push_stall(vg_lite_context_t * context, uint32_t module) +{ + vg_lite_error_t error; + uint32_t command_id, index; + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + /* Reserve enough space in the command buffer for flush and submit */ + if (CMDBUF_OFFSET(*context) + 56 >= CMDBUF_SIZE(*context)) { + uint32_t cmd_count = 0,start_offset = 0; + context->end_offset = CMDBUF_OFFSET(*context); + start_offset = context->start_offset; + VG_LITE_RETURN_ERROR(flush(context)); + VG_LITE_RETURN_ERROR(submit(context)); + CMDBUF_SWAP(*context); + command_id = CMDBUF_INDEX(*context); + if(CMDBUF_IN_QUEUE(&context->context, command_id)) + VG_LITE_RETURN_ERROR(stall(context, 0)); + + RESERVE_BYTES_IN_CMDBUF(*context); + + if(context->ts_init){ + memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); + CMDBUF_OFFSET(*context) += 80; + context->ts_init_used = 1; + } + + /* update start offset */ + context->start_offset = CMDBUF_OFFSET(*context); + + index = (command_id? 0 : 1); + command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), + start_offset, context->end_offset, &cmd_count); + CMDBUF_OFFSET(*context) += cmd_count; + } + + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_SEMAPHORE(module); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[2] = VG_LITE_STALL(module); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[3] = 0; + +#if DUMP_COMMAND + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], 0); + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[2], 0); + + fclose(fp); + fp = NULL; +#endif + + CMDBUF_OFFSET(*context) += 16; + + return VG_LITE_SUCCESS; +} + +static vg_lite_error_t flush(vg_lite_context_t *context) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint32_t address0 = 0x0A34; + uint32_t address1 = 0x0A1B; + uint32_t data0 = 0; + uint32_t data1 = 0x00000001; + uint32_t module = 7; + + /* Check if there is a valid context and an allocated command buffer. */ + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + /* Check if there is anything to flush. */ + if (CMDBUF_OFFSET(*context) == 0) + return VG_LITE_INVALID_ARGUMENT; + + /* Check if there is enough space in the command buffer. */ + if (CMDBUF_OFFSET(*context) + 32 > CMDBUF_SIZE(*context)) { + return VG_LITE_OUT_OF_RESOURCES; + } + + /* Finialize command buffer. */ + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATE(address0); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = data0; + + /* flush target */ + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[2] = VG_LITE_STATE(address1); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[3] = data1; + + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[4] = VG_LITE_SEMAPHORE(module); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[5] = 0; + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[6] = VG_LITE_STALL(module); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[7] = 0; + + CMDBUF_OFFSET(*context) += 32; + + return error; +} +#endif /* VG_DRIVER_SINGLE_THREAD */ + +/* Submit the current command buffer to HW and reset the current command buffer offset. */ +static vg_lite_error_t submit(vg_lite_context_t *context) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_kernel_submit_t submit; + + /* Check if there is a valid context and an allocated command buffer. */ + if (!has_valid_command_buffer(context)) + return VG_LITE_NO_CONTEXT; + + /* Check if there is anything to submit. */ + if (CMDBUF_OFFSET(*context) == 0) + return VG_LITE_INVALID_ARGUMENT; + + /* Check if there is enough space in the command buffer for the END. */ + if (CMDBUF_OFFSET(*context) + 8 > CMDBUF_SIZE(*context)) { + /* Reset command buffer offset. */ + CMDBUF_OFFSET(*context) = 0; + return VG_LITE_OUT_OF_RESOURCES; + } + + /* Append END command into the command buffer. */ + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_END(0); + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; + +#if DUMP_COMMAND + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], 0); + + fprintf(fp, "Command buffer addr is : %p,\n", CMDBUF_BUFFER(*context)); + fprintf(fp, "Command buffer offset is : %d,\n", CMDBUF_OFFSET(*context) + 8); + + fclose(fp); + fp = NULL; +#endif + + CMDBUF_OFFSET(*context) += 8; + + /* Submit the command buffer. */ + submit.context = &context->context; + submit.commands = CMDBUF_BUFFER(*context); + submit.command_size = CMDBUF_OFFSET(*context); + submit.command_id = CMDBUF_INDEX(*context); + +#if defined(VG_DRIVER_SINGLE_THREAD) + /* Wait if GPU has not completed previous CMD buffer */ + if (submit_flag) { + VG_LITE_RETURN_ERROR(stall(&s_context, 0, (uint32_t)~0)); + } +#endif /* VG_DRIVER_SINGLE_THREAD */ + + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_SUBMIT, &submit)); +#if defined(VG_DRIVER_SINGLE_THREAD) + submit_flag = 1; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + vglitemDUMP_BUFFER("command", (unsigned int)CMDBUF_BUFFER(*context), + submit.context->command_buffer_logical[CMDBUF_INDEX(*context)], 0, submit.command_size); + vglitemDUMP("@[commit]"); + + /* Reset command buffer. */ + CMDBUF_OFFSET(*context) = 0; + + return error; +} + +/* Wait for the HW to finish the current execution. */ +#if defined(VG_DRIVER_SINGLE_THREAD) +static vg_lite_error_t stall(vg_lite_context_t *context, uint32_t time_ms, uint32_t mask) +#else +static vg_lite_error_t stall(vg_lite_context_t *context, uint32_t time_ms) +#endif /* VG_DRIVER_SINGLE_THREAD */ +{ + vg_lite_error_t error; + vg_lite_kernel_wait_t wait; + + vglitemDUMP("@[stall]"); + /* Wait until GPU is ready. */ + wait.context = &context->context; +#if defined(VG_DRIVER_SINGLE_THREAD) + wait.timeout_ms = time_ms > 0 ? time_ms : VG_LITE_INFINITE; + wait.event_mask = mask; +#else + wait.timeout_ms = time_ms > 0 ? time_ms : VG_LITE_MAX_WAIT_TIME; + wait.command_id = CMDBUF_INDEX(*context); +#endif /* VG_DRIVER_SINGLE_THREAD */ + + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_WAIT, &wait)); +#if defined(VG_DRIVER_SINGLE_THREAD) + submit_flag = 0; +#endif /* VG_DRIVER_SINGLE_THREAD */ + return VG_LITE_SUCCESS; +} + +/* Get the inversion of a matrix. */ +VG_LITE_OPTIMIZE(LOW) static int inverse(vg_lite_matrix_t * result, vg_lite_matrix_t * matrix) +{ + vg_lite_float_t det00, det01, det02; + vg_lite_float_t d; + int isAffine; + + /* Test for identity matrix. */ + if (matrix == NULL) { + result->m[0][0] = 1.0f; + result->m[0][1] = 0.0f; + result->m[0][2] = 0.0f; + result->m[1][0] = 0.0f; + result->m[1][1] = 1.0f; + result->m[1][2] = 0.0f; + result->m[2][0] = 0.0f; + result->m[2][1] = 0.0f; + result->m[2][2] = 1.0f; + + /* Success. */ + return 1; + } + + det00 = (matrix->m[1][1] * matrix->m[2][2]) - (matrix->m[2][1] * matrix->m[1][2]); + det01 = (matrix->m[2][0] * matrix->m[1][2]) - (matrix->m[1][0] * matrix->m[2][2]); + det02 = (matrix->m[1][0] * matrix->m[2][1]) - (matrix->m[2][0] * matrix->m[1][1]); + + /* Compute determinant. */ + d = (matrix->m[0][0] * det00) + (matrix->m[0][1] * det01) + (matrix->m[0][2] * det02); + + /* Return 0 if there is no inverse matrix. */ + if (d == 0.0f) + return 0; + + /* Compute reciprocal. */ + d = 1.0f / d; + + /* Determine if the matrix is affine. */ + isAffine = (matrix->m[2][0] == 0.0f) && (matrix->m[2][1] == 0.0f) && (matrix->m[2][2] == 1.0f); + + result->m[0][0] = d * det00; + result->m[0][1] = d * ((matrix->m[2][1] * matrix->m[0][2]) - (matrix->m[0][1] * matrix->m[2][2])); + result->m[0][2] = d * ((matrix->m[0][1] * matrix->m[1][2]) - (matrix->m[1][1] * matrix->m[0][2])); + result->m[1][0] = d * det01; + result->m[1][1] = d * ((matrix->m[0][0] * matrix->m[2][2]) - (matrix->m[2][0] * matrix->m[0][2])); + result->m[1][2] = d * ((matrix->m[1][0] * matrix->m[0][2]) - (matrix->m[0][0] * matrix->m[1][2])); + result->m[2][0] = isAffine ? 0.0f : d * det02; + result->m[2][1] = isAffine ? 0.0f : d * ((matrix->m[2][0] * matrix->m[0][1]) - (matrix->m[0][0] * matrix->m[2][1])); + result->m[2][2] = isAffine ? 1.0f : d * ((matrix->m[0][0] * matrix->m[1][1]) - (matrix->m[1][0] * matrix->m[0][1])); + + /* Success. */ + return 1; +} + +/* Transform a 2D point by a given matrix. */ +static int transform(vg_lite_point_t * result, vg_lite_float_t x, vg_lite_float_t y, vg_lite_matrix_t * matrix) +{ + vg_lite_float_t pt_x; + vg_lite_float_t pt_y; + vg_lite_float_t pt_w; + + /* Test for identity matrix. */ + if (matrix == NULL) { + result->x = (int)x; + result->y = (int)y; + + /* Success. */ + return 1; + } + + /* Transform x, y, and w. */ + pt_x = (x * matrix->m[0][0]) + (y * matrix->m[0][1]) + matrix->m[0][2]; + pt_y = (x * matrix->m[1][0]) + (y * matrix->m[1][1]) + matrix->m[1][2]; + pt_w = (x * matrix->m[2][0]) + (y * matrix->m[2][1]) + matrix->m[2][2]; + + if (pt_w <= 0.0f) + return 0; + + /* Compute projected x and y. */ + result->x = (int)(pt_x / pt_w); + result->y = (int)(pt_y / pt_w); + + /* Success. */ + return 1; +} + +/*! + Flush specific VG module. + */ +static vg_lite_error_t flush_target() +{ + vg_lite_error_t error = VG_LITE_SUCCESS; +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + do { + VG_LITE_BREAK_ERROR(push_state(ctx, 0x0A1B, 0x00000001)); + VG_LITE_BREAK_ERROR(push_stall(ctx, 7)); + } while (0); + + return error; +} + +/****************** FAST_CLEAR feature implementation. ***************/ +#if VG_TARGET_FAST_CLEAR +static vg_lite_error_t convert_color(vg_lite_buffer_format_t format, uint32_t value, uint32_t *result, int *bpp) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint32_t r, g, b, a; + int Bpp = 0; + + r = B(value); + g = G(value); + b = R(value); + a = A(value); + + do { + switch (format) { + case VG_LITE_RGBA8888: + *result = ARGB(a, b, g, r); + Bpp = 32; + break; + + case VG_LITE_BGRA8888: + *result = ARGB(a, r, g, b); + Bpp = 32; + break; + + case VG_LITE_RGBX8888: + *result = ARGB(0xff, b, g, r); + Bpp = 32; + break; + + case VG_LITE_BGRX8888: + *result = ARGB(0xff, r, g, b); + Bpp = 32; + break; + + case VG_LITE_RGBA4444: + *result = ARGB4(a, b, g, r); + Bpp = 16; + break; + + case VG_LITE_BGRA4444: + *result = ARGB4(a, r, g, b); + Bpp = 16; + break; + + case VG_LITE_RGB565: + *result = ((b & 0xf8) << 8) | + ((g & 0xfc) << 3) | + ((r & 0xf8) >> 3); + Bpp = 16; + break; + + case VG_LITE_BGR565: + *result = ((r & 0xf8) << 8) | + ((g & 0xfc) << 3) | + ((b & 0xf8) >> 3); + Bpp = 16; + break; + + case VG_LITE_BGRA5551: + *result = ((b & 0xf8) << 8) | + ((g & 0xf8) << 3) | + ((r & 0xf8) >> 2) | + ((a & 0x80) >> 7); + Bpp = 16; + break; + + case VG_LITE_A8: + *result = ARGB(a, a, a, a); + Bpp = 8; + break; + + case VG_LITE_L8: + *result = ARGB(r, r, r, r); + Bpp = 8; + break; + + default: + error = VG_LITE_NOT_SUPPORT; + break; + } + } while (0); + + if (bpp != NULL) { + *bpp = Bpp; + } + + if (Bpp == 16) { + *result = ((*result) << 16) | (*result); + } + return error; +} + +/* Fill Target buffer by FC buffer. Only used in cmodel/fpga for verification. */ +#if defined(DEBUG) || defined(_DEBUG) +static vg_lite_error_t fill_fc_target(vg_lite_buffer_t *target, vg_lite_buffer_t *fcb) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint8_t *fc = (uint8_t *)fcb->memory; + uint16_t *target16; + uint32_t *target32; + uint8_t *target8; + uint32_t clear32; + int byte_done = 0; + int i, j, k; + int bpp; + + do { + convert_color(target->format, s_context.clearValue, &clear32, &bpp); + + if (bpp == 32) { + target32 = (uint32_t *)target->memory; + for (i = 0; i < fcb->width; i++) { + + for (j = 0; j < 8; j++) { /* Loop the bits*/ + + if (!(((*fc) >> j) & 1)) { + for (k = 0; k < 64 / 4; k++) { + target32[k] = clear32; + byte_done+=4; + if (byte_done >= target->stride * target->height) { + return error; + } + } + } + + target32 += 64/4; + } + + fc++; + } + } + else if (bpp == 16){ + target16 = (uint16_t *)target->memory; + for (i = 0; i < fcb->width; i++) { + + for (j = 0; j < 8; j++) { /* Loop the bits*/ + + if (!(((*fc) >> j) & 1)) { + for (k = 0; k < 64 / 2; k++) { + target16[k] = (uint16_t)clear32; + byte_done+=2; + if (byte_done >= target->stride * target->height) { + return error; + } + } + } + + target16 += 64/2; + } + + fc++; + } + } + else if (bpp == 8) { + target8 = (uint8_t *)target->memory; + for (i = 0; i < fcb->width; i++) { + + for (j = 0; j < 8; j++) { /* Loop the bits*/ + + if (!(((*fc) >> j) & 1)) { + for (k = 0; k < 64; k++) { + target8[k] = (uint8_t)clear32; + byte_done++; + if (byte_done >= target->stride * target->height) { + return error; + } + } + } + + target8 += 64; + } + + fc++; + } + } + } while (0); + + return error; +} +#endif + +/* Update the fast_clear buffer when render target switched. */ +static vg_lite_error_t update_fc_buffer(vg_lite_buffer_t *target) +{ + int rt_bytes; + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_context_t *context = GET_CONTEXT(); + vg_lite_kernel_allocate_t allocate; + + do { + if (target == NULL) { + error = VG_LITE_INVALID_ARGUMENT; + break; + } + + rt_bytes = target->stride * target->height; + rt_bytes = VG_LITE_ALIGN(rt_bytes, (FC_BIT_TO_BYTES * 8)); + rt_bytes = rt_bytes / FC_BIT_TO_BYTES / 8; + /* Only allocate new buffer when the allocated is not big enough. Yes*/ + if (rt_bytes > context->fcBuffer.stride ) { + vg_lite_free(&context->fcBuffer); + + context->fcBuffer.width = rt_bytes; /* The actually used bytes. */ + rt_bytes = VG_LITE_ALIGN(rt_bytes, FC_BURST_BYTES); /* The allocated aligned bytes. */ + context->fcBuffer.stride = rt_bytes; + allocate.bytes = rt_bytes; + allocate.contiguous = 1; + + VG_LITE_BREAK_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); + context->fcBuffer.handle = allocate.memory_handle; + context->fcBuffer.memory = allocate.memory; + context->fcBuffer.address = allocate.memory_gpu; + } + else { + /* Just update the fc buffer size. */ + context->fcBuffer.width = rt_bytes; + } + memset(context->fcBuffer.memory, 0xff, context->fcBuffer.stride); + } while (0); + + return error; +} + +/* Update FC registers and clear FC buffer. */ +static vg_lite_error_t clear_fc(uint32_t value) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_context_t *context = GET_CONTEXT(); + uint32_t bytes_to_clear = context->fcBuffer.stride / FC_BURST_BYTES; + + do { + VG_LITE_BREAK_ERROR(push_state(context, 0x0A9A, context->fcBuffer.address)); /* FC buffer address. */ + VG_LITE_BREAK_ERROR(push_state(context, 0x0A9B, value)); /* FC clear value. */ + VG_LITE_BREAK_ERROR(push_state(context, 0x0AB0, 0x80000000 | bytes_to_clear)); /* FC clear command. */ + } while (0); + + return error; +} + +#if VG_TARGET_FC_DUMP +static int fc_buf_dump(vg_lite_buffer_t *target, vg_lite_buffer_t *fcb) +{ + int error = VG_LITE_SUCCESS; + uint8_t *fc = (uint8_t *)fcb->memory; + uint8_t *target8; + int byte_done = 0; + int target_bytes; + int i, j; + + static unsigned s_cnt; + unsigned cnt = s_cnt; + + FILE *fpFCBuf; + FILE *fpTargetBuf; + FILE *fpTargetBufInfo; + char buf[256]; + + s_cnt++; + + sprintf(buf, "vg255v2.fc_buf.f%04d.txt", cnt); + fpFCBuf = fopen(buf, "wt"); + if (NULL == fpFCBuf) { + fprintf(stderr, "[Warning] Open file \'%s\' fail.\n", buf); + return -1; + } + + sprintf(buf, "vg255v2.target_buf_info.f%04d.txt", cnt); + fpTargetBufInfo = fopen(buf, "wt"); + if (NULL == fpTargetBufInfo) { + fprintf(stderr, "[Warning] Open file \'%s\' fail.\n", buf); + fclose(fpFCBuf); + return -1; + } else { + fprintf(fpTargetBufInfo, "%-12s: %d\n", "format", target->format); + fprintf(fpTargetBufInfo, "%-12s: %d\n", "tiled", target->tiled); + fprintf(fpTargetBufInfo, "%-12s: %d\n", "width", target->width); + fprintf(fpTargetBufInfo, "%-12s: %d\n", "height", target->height); + fprintf(fpTargetBufInfo, "%-12s: %d\n", "stride", target->stride); + + fclose(fpTargetBufInfo); + } + + sprintf(buf, "vg255v2.target_buf.f%04d.txt", cnt); + fpTargetBuf = fopen(buf, "wt"); + if (NULL == fpTargetBuf) { + fprintf(stderr, "[Warning] Open file \'%s\' fail.\n", buf); + fclose(fpFCBuf); + return -1; + } + + /* Dump FC buffer & Dump target buffer */ + target8 = (uint8_t *)target->memory; + target_bytes = target->stride * target->height; + + for (i = 0; i < fcb->width; ++i) + { + fprintf(fpFCBuf, "%02x\n", fc[i]); + /* 1 byte of fc related with 512 bytes of target buffer */ + for (j = 0; j < 128; ++j) { + fprintf(fpTargetBuf, "%02x", byte_done < target_bytes ? target8[0] : 0); + byte_done++; + + fprintf(fpTargetBuf, "%02x", byte_done < target_bytes ? target8[1] : 0); + byte_done++; + + fprintf(fpTargetBuf, "%02x", byte_done < target_bytes ? target8[2] : 0); + byte_done++; + + fprintf(fpTargetBuf, "%02x\n", byte_done < target_bytes ? target8[3] : 0); + byte_done++; + + target8 += 4; + } + } + + fclose(fpFCBuf); + fclose(fpTargetBuf); + + return error; +} +#endif /* VG_TARGET_FC_DUMP */ + +#endif + +/* Set the current render target. */ +#if defined(VG_DRIVER_SINGLE_THREAD) +static vg_lite_error_t set_render_target(vg_lite_buffer_t *target) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint32_t yuv2rgb = 0; + uint32_t uv_swiz = 0; + int32_t tiled; + int32_t dst_align_width; + uint32_t mul, div, align; + if(target == NULL) { + return VG_LITE_INVALID_ARGUMENT; + } else if(s_context.scissor_enabled && (s_context.scissor[2] <= 0 || s_context.scissor[3] <= 0)) { + /* Check scissoring rectangle dimensions + A scissoring rectangle with width <= 0 or height <= 0 must be + ignored. If scissoring is enabled and no valid scissoring rectangles + are present, no drawing occurs. */ + return VG_LITE_NO_CONTEXT; + } + /* Skip if render target and scissor are not changed. */ + if ((s_context.rtbuffer != NULL) && + !(memcmp(s_context.rtbuffer,target,sizeof(vg_lite_buffer_t))) && + (s_context.scissor_dirty == 0) && (s_context.premultiply_dirty == 0)) + { + return VG_LITE_SUCCESS; + } + + if ((target != NULL) && + (target->format == VG_LITE_YUY2 || + target->format == VG_LITE_AYUY2 || + target->format == VG_LITE_YUY2_TILED || + target->format == VG_LITE_AYUY2_TILED)) + { + return VG_LITE_NOT_SUPPORT; + } + + +#if VG_TARGET_FAST_CLEAR + /* Flush target if necessary when switching. */ + if (s_context.rtbuffer&& s_context.rtbuffer->memory) { /* If it's not the first time to set target. */ + vg_lite_finish(); + } + update_fc_buffer(target); +#else + if (s_context.rtbuffer && s_context.rtbuffer->memory) { + /* Flush the old target. */ + vg_lite_finish(); + } +#endif + + tiled = (target->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0; + + if (((target->format >= VG_LITE_YUY2) && + (target->format <= VG_LITE_AYUY2)) || + ((target->format >= VG_LITE_YUY2_TILED) && + (target->format <= VG_LITE_AYUY2_TILED))) { + yuv2rgb = convert_yuv2rgb(target->yuv.yuv2rgb); + uv_swiz = convert_uv_swizzle(target->yuv.swizzle); + } + + /* Program render target. */ + if (s_context.premultiply_dirty || s_context.rtbuffer != target || memcmp(s_context.rtbuffer,target,sizeof(vg_lite_buffer_t)) ) { + if(target->tiled == VG_LITE_TILED) { + if((target->stride % DEST_ALIGNMENT_LIMITATION) != 0) + return VG_LITE_INVALID_ARGUMENT; + } + if(s_context.premultiply_enabled) { + VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A10, + convert_target_format(target->format, s_context.capabilities) | 0x00010000 | uv_swiz | yuv2rgb)); + }else { + VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A10, + convert_target_format(target->format, s_context.capabilities) | 0x00010000 | uv_swiz | yuv2rgb | 0x100)); + } + if (target->yuv.uv_planar) + { /* Program uv plane address if necessary. */ + VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A5C, target->yuv.uv_planar)); + } + if (target->yuv.alpha_planar) { + VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A5D, target->yuv.alpha_planar)); + } + VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A11, target->address)); + VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A12, target->stride | tiled)); + s_context.premultiply_dirty = 0; + } + + get_format_bytes(target->format, &mul, &div, &align); + dst_align_width = target->stride * div / mul; + + if (s_context.scissor_dirty != 0) { + if (s_context.scissor_enabled) { + VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A13, (s_context.scissor[0] + s_context.scissor[2]) | ((s_context.scissor[1] + s_context.scissor[3]) << 16))); + } + else { + VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A13, dst_align_width | (target->height << 16))); + } + s_context.scissor_dirty = 0; + } + else { + VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A13, dst_align_width | (target->height << 16))); + } + + memcpy(s_context.rtbuffer, target, sizeof(vg_lite_buffer_t)); + + return error; +} +#else +static vg_lite_error_t set_render_target(vg_lite_buffer_t *target) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint32_t yuv2rgb = 0; + uint32_t uv_swiz = 0; + int32_t tiled; + vg_lite_tls_t* tls; + int32_t dst_align_width; + uint32_t mul, div, align; + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + if(target == NULL) { + return VG_LITE_INVALID_ARGUMENT; + } else if(tls->t_context.scissor_enabled && (tls->t_context.scissor[2] <= 0 || tls->t_context.scissor[3] <= 0)) { + /* Check scissoring rectangle dimensions + A scissoring rectangle with width <= 0 or height <= 0 must be + ignored. If scissoring is enabled and no valid scissoring rectangles + are present, no drawing occurs. */ + return VG_LITE_NO_CONTEXT; + } + + tls->t_context.start_offset = CMDBUF_OFFSET(tls->t_context); + + if ((target != NULL) && + (target->format == VG_LITE_YUY2 || + target->format == VG_LITE_AYUY2 || + target->format == VG_LITE_YUY2_TILED || + target->format == VG_LITE_AYUY2_TILED)) + { + return VG_LITE_NOT_SUPPORT; + } + +#if VG_TARGET_FAST_CLEAR + /* Flush target if necessary when switching. */ + if (tls->t_context.rtbuffer != NULL) { /* If it's not the first time to set target. */ + vg_lite_finish(); + } + update_fc_buffer(target); +#endif + + tiled = (target->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0; + + if (((target->format >= VG_LITE_YUY2) && + (target->format <= VG_LITE_AYUY2)) || + ((target->format >= VG_LITE_YUY2_TILED) && + (target->format <= VG_LITE_AYUY2_TILED))) { + yuv2rgb = convert_yuv2rgb(target->yuv.yuv2rgb); + uv_swiz = convert_uv_swizzle(target->yuv.swizzle); + } + + /* Program render target. */ + if(target->tiled == VG_LITE_TILED) { + if((target->stride % DEST_ALIGNMENT_LIMITATION) != 0) + return VG_LITE_INVALID_ARGUMENT; + } + + if(tls->t_context.premultiply_enabled) { + VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A10, + convert_target_format(target->format, tls->t_context.capabilities) | 0x00010000 | uv_swiz | yuv2rgb)); + } else { + VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A10, + convert_target_format(target->format, tls->t_context.capabilities) | 0x00010000 | uv_swiz | yuv2rgb | 0x100)); + } + if (target->yuv.uv_planar) + { /* Program uv plane address if necessary. */ + VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A5C, target->yuv.uv_planar)); + } + if (target->yuv.alpha_planar) { + VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A5D, target->yuv.alpha_planar)); + } + VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A11, target->address)); + VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A12, target->stride | tiled)); + get_format_bytes(target->format, &mul, &div, &align); + dst_align_width = target->stride * div / mul; + + if (tls->t_context.scissor_enabled) { + VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A13, (tls->t_context.scissor[0] + tls->t_context.scissor[2]) | ((tls->t_context.scissor[1] + tls->t_context.scissor[3]) << 16))); + } + else { + VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A13, dst_align_width | (target->height << 16))); + } + + tls->t_context.rtbuffer = target; + + return error; +} +#endif /* VG_DRIVER_SINGLE_THREAD */ + +static inline vg_lite_error_t transform_bounding_box(vg_lite_rectangle_t *in_bbx, + vg_lite_matrix_t *matrix, + vg_lite_rectangle_t *clip, + vg_lite_rectangle_t *out_bbx, + vg_lite_point_t *origin) +{ + vg_lite_point_t temp; + + memset(out_bbx, 0, sizeof(vg_lite_rectangle_t)); + + /* Transform image point (x, y). */ + if (!transform(&temp, in_bbx->x, in_bbx->y, matrix)) + return VG_LITE_INVALID_ARGUMENT; + out_bbx->x = temp.x; + out_bbx->y = temp.y; + + /* Provide position of the new origin to the caller if requested. */ + if (origin != NULL) { + origin->x = temp.x; + origin->y = temp.y; + } + + /* Transform image point (x, y+height). */ + if (!transform(&temp, in_bbx->x, (in_bbx->y + in_bbx->height), matrix)) + return VG_LITE_INVALID_ARGUMENT; + UPDATE_BOUNDING_BOX(*out_bbx, temp); + + /* Transform image point (x+width, y+height). */ + if (!transform(&temp, (in_bbx->x + in_bbx->width), (in_bbx->y + in_bbx->height), + matrix)) + return VG_LITE_INVALID_ARGUMENT; + UPDATE_BOUNDING_BOX(*out_bbx, temp); + + /* Transform image point (x+width, y). */ + if (!transform(&temp, (in_bbx->x + in_bbx->width), in_bbx->y, matrix)) + return VG_LITE_INVALID_ARGUMENT; + UPDATE_BOUNDING_BOX(*out_bbx, temp); + + /* Clip is required */ + if (clip) { + out_bbx->x = MAX(out_bbx->x, clip->x); + out_bbx->y = MAX(out_bbx->y, clip->y); + out_bbx->width = MIN((out_bbx->x + out_bbx->width), (clip->x + clip->width)) - out_bbx->x; + out_bbx->height = MIN((out_bbx->y + out_bbx->height), (clip->y + clip->height)) - out_bbx->y; + } + + return VG_LITE_SUCCESS; +} + +#if (VG_BLIT_WORKAROUND == 1) +/* + * Calculates the minimal possible target buffer starting from a given target + * buffer and considering a source texture (to blit), graphic transformations + * and clipping window. + */ +static vg_lite_error_t config_new_target(vg_lite_buffer_t *target, + vg_lite_buffer_t *source, + vg_lite_matrix_t *matrix, + vg_lite_rectangle_t *bbx, + vg_lite_buffer_t *new_target) +{ + uint8_t *p; + vg_lite_point_t origin; + vg_lite_rectangle_t src_bbx, bounding_box, clip; + int tx, ty; + uint32_t mul, div, required_align, align; + + /* + * Acquire the bounding box of the transformed source image and the location + * of its origin. + */ + memset(&src_bbx, 0, sizeof(vg_lite_rectangle_t)); + src_bbx.width = source->width; + src_bbx.height = source->height; + if (bbx == NULL) { + /* + * If no clipping rectangle provided, just configure the clip bounds to + * be as big as the target + */ + memset(&clip, 0, sizeof(vg_lite_rectangle_t)); + clip.width = target->width; + clip.height = target->height; + } else { + /* Otherwise clip according to the bounding box specified by the caller */ + memcpy(&clip, bbx, sizeof(vg_lite_rectangle_t)); + } + transform_bounding_box(&src_bbx, matrix, &clip, &bounding_box, &origin); + + /* Calculate the data address of the new target */ + get_format_bytes(target->format, &mul, &div, &required_align); + p = target->memory; + p += bounding_box.y * target->stride + bounding_box.x * (mul / div); + align = (uint32_t)p & (required_align - 1); + p -= align; + + /* + * Update pixel coordinate of the base address. The width of the target will + * increase, since the x coordinate of the bounding box decreases to + * accomodate the image data alignment. + */ + tx = align / (mul / div); + bounding_box.x -= tx; + bounding_box.width += tx; + + /* Update bounding box if provided by the caller */ + if (bbx) { + bbx->x = tx; + bbx->y = 0; + } + + /* Calculate translation from the source image origin to the target origin. */ + tx = origin.x - bounding_box.x; + ty = origin.y - bounding_box.y; + + /* Copy content of the target buffer descriptor into the new target. */ + memcpy(new_target, target, sizeof(vg_lite_buffer_t)); + + /* Update the new buffer */ + new_target->memory = p; + new_target->address = (uint32_t) p; + new_target->width = bounding_box.width; + new_target->height = bounding_box.height; + + /* Update matrix */ + matrix->m[0][2] = tx; + matrix->m[1][2] = ty; + + return VG_LITE_SUCCESS; +} +#endif /* VG_BLIT_WORKAROUND */ + +static vg_lite_error_t set_interpolation_steps(vg_lite_buffer_t *target, + vg_lite_float_t s_width, + vg_lite_float_t s_height, + vg_lite_matrix_t *matrix) +{ + vg_lite_matrix_t im; + vg_lite_rectangle_t src_bbx, bounding_box, clip; + vg_lite_float_t xs[3], ys[3], cs[3]; + vg_lite_error_t error = VG_LITE_SUCCESS; + float dx = 0.0f, dy = 0.0f; +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t *tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + #define ERR_LIMIT 0.0000610351562f + + /* Get bounding box. */ + memset(&src_bbx, 0, sizeof(vg_lite_rectangle_t)); + memset(&clip, 0, sizeof(vg_lite_rectangle_t)); + src_bbx.width = (int32_t)s_width; + src_bbx.height = (int32_t)s_height; + + if (ctx->scissor_enabled) { + clip.x = ctx->scissor[0]; + clip.y = ctx->scissor[1]; + clip.width = ctx->scissor[2]; + clip.height = ctx->scissor[3]; + } else { + clip.x = clip.y = 0; + clip.width = ctx->rtbuffer->width; + clip.height = ctx->rtbuffer->height; + } + transform_bounding_box(&src_bbx, matrix, &clip, &bounding_box, NULL); + + /* Compute inverse matrix. */ + if (!inverse(&im, matrix)) + return VG_LITE_INVALID_ARGUMENT; + /* Compute interpolation steps. */ + /* X step */ + xs[0] = im.m[0][0] / s_width; + xs[1] = im.m[1][0] / s_height; + xs[2] = im.m[2][0]; + /* Y step */ + ys[0] = im.m[0][1] / s_width; + ys[1] = im.m[1][1] / s_height; + ys[2] = im.m[2][1]; + /* C step 2 */ + cs[2] = 0.5f * (im.m[2][0] + im.m[2][1]) + im.m[2][2]; + /* Keep track of the rounding errors (underflow) */ + if (ctx->chip_id == GPU_CHIP_ID_GCNanoliteV) { + /* Check if matrix has rotation or perspective transformations */ + if (matrix != NULL && + (matrix->m[0][1] != 0.0f || matrix->m[1][0] != 0.0f || + matrix->m[2][0] != 0.0f || matrix->m[2][1] != 0.0f || + matrix->m[2][2] != 1.0f)) { + if (xs[0] != 0.0f && -ERR_LIMIT < xs[0] && xs[0] < ERR_LIMIT) + dx = 0.5f * (2 * bounding_box.x + bounding_box.width) * im.m[0][0]; + else if (ys[0] != 0.0f && -ERR_LIMIT < ys[0] && ys[0] < ERR_LIMIT) + dx = 0.5f * (2 * bounding_box.y + bounding_box.height) * im.m[0][1]; + if (xs[1] != 0.0f && -ERR_LIMIT < xs[1] && xs[1] < ERR_LIMIT) + dy = 0.5f * (2 * bounding_box.x + bounding_box.width) * im.m[1][0]; + else if (ys[1] != 0.0f && -ERR_LIMIT < ys[1] && ys[1] < ERR_LIMIT) + dy = 0.5f * (2 * bounding_box.y + bounding_box.height) * im.m[1][1]; + } + } + /* C step 0, 1*/ + cs[0] = (0.5f * (im.m[0][0] + im.m[0][1]) + im.m[0][2] + dx) / s_width; + cs[1] = (0.5f * (im.m[1][0] + im.m[1][1]) + im.m[1][2] + dy) / s_height; + /* Set command buffer */ + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A18, (void *)&cs[0])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A19, (void *)&cs[1])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A1A, (void *)&cs[2])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A1C, (void *)&xs[0])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A1D, (void *)&xs[1])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A1E, (void *)&xs[2])); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A1F, 0x00000001)); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A20, (void *)&ys[0])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A21, (void *)&ys[1])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A22, (void *)&ys[2])); + + return VG_LITE_SUCCESS; +} + +/*************** API Functions ***********************************************/ +vg_lite_error_t vg_lite_get_transform_matrix(vg_lite_point4_t src, vg_lite_point4_t dst,vg_lite_matrix_t *mat) +{ + float a[8][8],b[9],A[64]; + int i, j, k, m = 8, n = 1; + int astep = 8,bstep = 1; + float d; + + if(src == NULL || dst == NULL || mat == NULL) + return VG_LITE_INVALID_ARGUMENT; + + for(i = 0; i < 4; ++i ) + { + a[i][0] = a[i+4][3] = src[i].x; + a[i][1] = a[i+4][4] = src[i].y; + a[i][2] = a[i+4][5] = 1; + a[i][3] = a[i][4] = a[i][5] = + a[i+4][0] = a[i+4][1] = a[i+4][2] = 0; + a[i][6] = -src[i].x*dst[i].x; + a[i][7] = -src[i].y*dst[i].x; + a[i+4][6] = -src[i].x*dst[i].y; + a[i+4][7] = -src[i].y*dst[i].y; + b[i] = dst[i].x; + b[i+4] = dst[i].y; + } + for(i = 0; i < 8; ++i ) + { + for(j = 0; j < 8; ++j ) + { + A[8 * i + j] = a[i][j]; + } + } + + for (i = 0; i < m; i++) + { + k = i; + for (j = i + 1; j < m; j++) + if (ABS(A[j*astep + i]) > ABS(A[k*astep + i])) + k = j; + if (ABS(A[k*astep + i]) < EPS) + return VG_LITE_INVALID_ARGUMENT; + if (k != i) + { + for (j = i; j < m; j++) + swap(&A[i*astep + j], &A[k*astep + j]); + for (j = 0; j < n; j++) + swap(&b[i*bstep + j], &b[k*bstep + j]); + } + d = -1 / A[i*astep + i]; + for (j = i + 1; j < m; j++) + { + float alpha = A[j*astep + i] * d; + for (k = i + 1; k < m; k++) + A[j*astep + k] += alpha * A[i*astep + k]; + for (k = 0; k < n; k++) + b[j*bstep + k] += alpha * b[i*bstep + k]; + } + } + + for (i = m - 1; i >= 0; i--) + for (j = 0; j < n; j++) + { + float s = b[i*bstep + j]; + for (k = i + 1; k < m; k++) + s -= A[i*astep + k] * b[k*bstep + j]; + b[i*bstep + j] = s / A[i*astep + i]; + } + b[8] = 1; + + for(i = 0; i < 3; ++i ) + { + for(j = 0; j < 3; ++j ) + { + mat->m[i][j] = b[i* 3 + j]; + } + } + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_clear(vg_lite_buffer_t * target, + vg_lite_rectangle_t * rectangle, + vg_lite_color_t color) +{ + vg_lite_error_t error; + int32_t x, y, width, height; + uint32_t color32; +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + error = set_render_target(target); + if (error != VG_LITE_SUCCESS) { + return error; + } else if (error == VG_LITE_NO_CONTEXT) { + /* If scissoring is enabled and no valid scissoring rectangles + are present, no drawing occurs */ + return VG_LITE_SUCCESS; + } + + /* Get rectangle. */ + x = (rectangle != NULL) ? rectangle->x : 0; + y = (rectangle != NULL) ? rectangle->y : 0; + width = (rectangle != NULL) ? rectangle->width : ctx->rtbuffer->width; + height = (rectangle != NULL) ? rectangle->height : ctx->rtbuffer->height; + + /* Compute the valid rectangle. */ + if (x < 0) + { + width += x; + x = 0; + } + if (y < 0) + { + height += y; + y = 0; + } + + if (ctx->scissor_enabled) + { + int right, bottom; + right = x + width; + bottom = y + height; + + /* Bounds check. */ + if ((ctx->scissor[0] >= x + width) || + (ctx->scissor[0] + ctx->scissor[2] <= x) || + (ctx->scissor[1] >= y + height) || + (ctx->scissor[1] + ctx->scissor[3] <= y)) + { + /* Do nothing. */ + return VG_LITE_SUCCESS; + } + /* Intersects the scissor and the rectangle. */ + x = (x > ctx->scissor[0] ? x : ctx->scissor[0]); + y = (y > ctx->scissor[1] ? y : ctx->scissor[1]); + right = (right < ctx->scissor[0] + ctx->scissor[2] ? right : ctx->scissor[0] + ctx->scissor[2]); + bottom = (bottom < ctx->scissor[1] + ctx->scissor[3] ? bottom : ctx->scissor[1] + ctx->scissor[3]); + width = right - x; + height = bottom - y; + } + + /* Get converted color when target is in L8 format. */ + color32 = (target->format == VG_LITE_L8) ? rgb_to_l(color) : color; + +#if VG_TARGET_FAST_CLEAR + if ((rectangle == NULL) || + ((x == 0) && (y == 0) && + (width == ctx->rtbuffer->width) && + (height == ctx->rtbuffer->height))) { + ctx->clearValue = color32; + convert_color(ctx->rtbuffer->format, color32, &color32, NULL); + clear_fc((uint32_t)color32); + } + else +#endif + { + /* Setup the command buffer. */ + if(ctx->premultiply_enabled) { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, 0x00000001)); + } else { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, 0x10000001)); + } + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A02, color32)); + VG_LITE_RETURN_ERROR(push_rectangle(ctx, x, y, width, height)); + + /* Notify rendering area (added by MicroEJ) */ + vg_lite_draw_notify_render_area(x, y, x + width-1, y + height-1); + + VG_LITE_RETURN_ERROR(flush_target()); + } + + /* Success. */ + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_blit(vg_lite_buffer_t * target, + vg_lite_buffer_t * source, + vg_lite_matrix_t * matrix, + vg_lite_blend_t blend, + vg_lite_color_t color, + vg_lite_filter_t filter) +{ + vg_lite_error_t error; + vg_lite_rectangle_t src_bbx, bounding_box, clip; + uint32_t imageMode; + uint32_t blend_mode; + uint32_t transparency_mode = 0; + vg_lite_blend_t forced_blending = blend; + uint32_t conversion = 0; + uint32_t tiled_source; +#if (VG_BLIT_WORKAROUND == 1) + vg_lite_matrix_t new_matrix; + vg_lite_buffer_t new_target; +#endif /* VG_BLIT_WORKAROUND */ + +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t *tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + /* Calculate bounding box */ + memset(&src_bbx, 0, sizeof(vg_lite_rectangle_t)); + memset(&clip, 0, sizeof(vg_lite_rectangle_t)); + src_bbx.width = source->width; + src_bbx.height = source->height; + if (ctx->scissor_enabled) { + clip.x = ctx->scissor[0]; + clip.y = ctx->scissor[1]; + clip.width = ctx->scissor[2]; + clip.height = ctx->scissor[3]; + } else { + clip.width = target->width; + clip.height = target->height; + } + transform_bounding_box(&src_bbx, matrix, &clip, &bounding_box, NULL); + + /* Notify rendering area (added by MicroEJ) */ + vg_lite_draw_notify_render_area(bounding_box.x, bounding_box.y, bounding_box.x + bounding_box.width-1, bounding_box.y + bounding_box.height-1); + +#if (VG_BLIT_WORKAROUND==1) + /* + * The blit output quality workaround works only for afine transformations + * because it is based on the process of cumulating translations into the + * matrix. This process is not possible for non-affine transformations, such + * as the perspective projections. + */ + if ((matrix->m[2][0] == 0) && (matrix->m[2][1] == 0)) { + /* + * Make a local copy of the transformation matrix in order not to mess + * up the user's matrix. + */ + memcpy(&new_matrix, matrix, sizeof(vg_lite_matrix_t)); + matrix = &new_matrix; + + config_new_target(target, source, matrix, &bounding_box, &new_target); + target = &new_target; + } +#endif /* VG_BLIT_WORKAROUND */ + error = set_render_target(target); + if (error != VG_LITE_SUCCESS) { + return error; + } else if (error == VG_LITE_NO_CONTEXT) { + /* If scissoring is enabled and no valid scissoring rectangles + are present, no drawing occurs */ + return VG_LITE_SUCCESS; + } + + transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); + /* Check if the specified matrix has rotation or perspective. */ + if ( (matrix != NULL) + && ( (matrix->m[0][1] != 0.0f) + || (matrix->m[1][0] != 0.0f) + || (matrix->m[2][0] != 0.0f) + || (matrix->m[2][1] != 0.0f) + || (matrix->m[2][2] != 1.0f) + ) + && ( blend == VG_LITE_BLEND_NONE + || blend == VG_LITE_BLEND_SRC_IN + || blend == VG_LITE_BLEND_DST_IN + ) + ) { + if(vg_lite_query_feature(gcFEATURE_BIT_VG_BORDER_CULLING)) { + /* Mark that we have rotation. */ + transparency_mode = 0x8000; + }else + { + blend_mode = VG_LITE_BLEND_SRC_OVER; + } + + } + + /* Check whether L8 is supported or not. */ + if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { + conversion = 0x80000000; + } + + /* determine if source specify bytes are aligned */ + error = _check_source_aligned(source->format,source->stride); + if (error != VG_LITE_SUCCESS) { + return error; + } + + /* Determine image mode (NORMAL, NONE or MULTIPLY) depending on the color. */ + imageMode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; + blend_mode = convert_blend(forced_blending); + tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; + +#if !defined(VG_DRIVER_SINGLE_THREAD) + /* Setup the command buffer. */ + if(source->format >= VG_LITE_INDEX_1 && source->format <= VG_LITE_INDEX_8) + { + /* this task will use index format,set index_flag to 1. */ + ctx->index_format = 1; + switch (source->format) { + case VG_LITE_INDEX_8: + if(ctx->clut_dirty[3]){ + VG_LITE_RETURN_ERROR(push_states(ctx, 0x0B00, 256, tls->t_context.colors[3])); + tls->t_context.clut_dirty[3] = 0; + } + else + { + ctx->clut_used[3] = 1; + } + break; + + case VG_LITE_INDEX_4: + if(ctx->clut_dirty[2]){ + VG_LITE_RETURN_ERROR(push_states(ctx, 0x0AA0, 16, ctx->colors[2])); + ctx->clut_dirty[2] = 0; + } + else + { + ctx->clut_used[2] = 1; + } + break; + + case VG_LITE_INDEX_2: + if(ctx->clut_dirty[1]){ + VG_LITE_RETURN_ERROR(push_states(ctx, 0x0A9C, 4, ctx->colors[1])); + ctx->clut_dirty[1] = 0; + } + else + { + ctx->clut_used[1] = 1; + } + break; + + default: + if(ctx->clut_dirty[0]){ + VG_LITE_RETURN_ERROR(push_states(ctx, 0x0A98, 2, ctx->colors[0])); + ctx->clut_dirty[0] = 0; + } + else + { + ctx->clut_used[0] = 1; + } + } + } +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + + if(!ctx->premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, 0x10000001 | imageMode | blend_mode | transparency_mode)); + } else { + /* enable pre-multiplied from VG to VGPE */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, 0x00000001 | imageMode | blend_mode | transparency_mode)); + } + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A02, color)); + VG_LITE_RETURN_ERROR(set_interpolation_steps(target, source->width, source->height, matrix)); + + if(!ctx->premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { + if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A25, convert_source_format(source->format) | filter | conversion | 0x01000100)); + } else { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A25, convert_source_format(source->format) | filter | conversion | 0x00000100)); + } + } else { + /* enable pre-multiplied in imager unit */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A25, convert_source_format(source->format) | filter | conversion)); + } + + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A27, 0)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A29, source->address)); + + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2B, source->stride | tiled_source)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2D, 0)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2F, source->width | (source->height << 16))); + VG_LITE_RETURN_ERROR(push_rectangle(ctx, bounding_box.x, bounding_box.y, bounding_box.width, + bounding_box.height)); + + error = flush_target(); + vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); + +#if DUMP_IMAGE + dump_img(source->memory, source->width, source->height, source->format); +#endif + + return error; +} + +vg_lite_error_t vg_lite_blit_rect(vg_lite_buffer_t * target, + vg_lite_buffer_t * source, + uint32_t * rect, + vg_lite_matrix_t * matrix, + vg_lite_blend_t blend, + vg_lite_color_t color, + vg_lite_filter_t filter) +{ + vg_lite_error_t error; + vg_lite_rectangle_t src_bbx, bounding_box, clip; + uint32_t imageMode; + uint32_t transparency_mode = 0; + uint32_t blend_mode; + vg_lite_blend_t forced_blending = blend; + uint32_t conversion = 0; + uint32_t tiled_source; + uint32_t rect_x = 0, rect_y = 0, rect_w = 0, rect_h = 0; + int32_t src_align_width; + uint32_t mul, div, align; +#if (VG_BLIT_WORKAROUND == 1) + vg_lite_matrix_t new_matrix; + vg_lite_buffer_t new_target; +#endif /* VG_BLIT_WORKAROUND */ +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t *tls; + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); + /* Check if the specified matrix has rotation or perspective. */ + if ( (matrix != NULL) + && ( (matrix->m[0][1] != 0.0f) + || (matrix->m[1][0] != 0.0f) + || (matrix->m[2][0] != 0.0f) + || (matrix->m[2][1] != 0.0f) + || (matrix->m[2][2] != 1.0f) + ) + && ( blend == VG_LITE_BLEND_NONE + || blend == VG_LITE_BLEND_SRC_IN + || blend == VG_LITE_BLEND_DST_IN + ) + ) { + if(vg_lite_query_feature(gcFEATURE_BIT_VG_BORDER_CULLING)) { + /* Mark that we have rotation. */ + transparency_mode = 0x8000; + }else + { + blend_mode = VG_LITE_BLEND_SRC_OVER; + } + + } + + /* Check whether L8 is supported or not. */ + if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { + conversion = 0x80000000; + } + + /* determine if source specify bytes are aligned */ + error = _check_source_aligned(source->format,source->stride); + if (error != VG_LITE_SUCCESS) { + return error; + } + get_format_bytes(source->format, &mul, &div, &align); + src_align_width = source->stride * div / mul; + memset(&src_bbx, 0, sizeof(vg_lite_rectangle_t)); + /* Set source region. */ + if (rect != NULL) { + rect_x = rect[0]; + rect_y = rect[1]; + rect_w = rect[2]; + rect_h = rect[3]; + + if ((rect_x > (uint32_t)src_align_width) || (rect_y > (uint32_t)source->height) || + (rect_w == 0) || (rect_h == 0)) + { + /*No intersection*/ + return VG_LITE_INVALID_ARGUMENT; + } + + if (rect_x + rect_w > (uint32_t)src_align_width) + { + rect_w = src_align_width - rect_x; + } + + if (rect_y + rect_h > (uint32_t)source->height) + { + rect_h = source->height - rect_y; + } + + src_bbx.width = rect_w; + src_bbx.height = rect_h; + } + else { + rect_x = rect_y = 0; + rect_w = src_bbx.width = src_align_width; + rect_h = src_bbx.height = source->height; + } + + /* Calculate bounding box. */ + memset(&clip, 0, sizeof(vg_lite_rectangle_t)); + if (ctx->scissor_enabled) { + clip.x = ctx->scissor[0]; + clip.y = ctx->scissor[1]; + clip.width = ctx->scissor[2]; + clip.height = ctx->scissor[3]; + } else { + clip.x = clip.y = 0; + clip.width = target->width; + clip.height = target->height; + } + transform_bounding_box(&src_bbx, matrix, &clip, &bounding_box, NULL); + + /* Notify rendering area (added by MicroEJ) */ + vg_lite_draw_notify_render_area(bounding_box.x, bounding_box.y, bounding_box.x + bounding_box.width-1, bounding_box.y + bounding_box.height-1); + +#if (VG_BLIT_WORKAROUND==1) + /* + * The blit output quality workaround works only for afine transformations + * because it is based on the process of cumulating translations into the + * matrix. This process is not possible for non-affine transformations, such + * as the perspective projections. + */ + if ((matrix->m[2][0] == 0) && (matrix->m[2][1] == 0)) { + /* + * Make a local copy of the transformation matrix in order not to mess + * up the user's matrix. + */ + memcpy(&new_matrix, matrix, sizeof(vg_lite_matrix_t)); + matrix = &new_matrix; + + config_new_target(target, source, matrix, &bounding_box, &new_target); + target = &new_target; + } +#endif /* VG_BLIT_WORKAROUND */ + + error = set_render_target(target); + if (error != VG_LITE_SUCCESS) { + return error; + } else if (error == VG_LITE_NO_CONTEXT) { + /* If scissoring is enabled and no valid scissoring rectangles + are present, no drawing occurs */ + return VG_LITE_SUCCESS; + } + + /* Determine image mode (NORMAL, NONE or MULTIPLY) depending on the color. */ + imageMode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; + blend_mode = convert_blend(forced_blending); + tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; + +#if !defined(VG_DRIVER_SINGLE_THREAD) + /* Setup the command buffer. */ + if(source->format >= VG_LITE_INDEX_1 && source->format <= VG_LITE_INDEX_8) + { + /* this task will use index format,set index_flag to 1. */ + ctx->index_format = 1; + switch (source->format) { + case VG_LITE_INDEX_8: + if(tls->t_context.clut_dirty[3]){ + VG_LITE_RETURN_ERROR(push_states(ctx, 0x0B00, 256, ctx->colors[3])); + ctx->clut_dirty[3] = 0; + } + else + { + tls->t_context.clut_used[3] = 1; + } + break; + + case VG_LITE_INDEX_4: + if(tls->t_context.clut_dirty[2]){ + VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0AA0, 16, tls->t_context.colors[2])); + tls->t_context.clut_dirty[2] = 0; + } + else + { + tls->t_context.clut_used[2] = 1; + } + break; + + case VG_LITE_INDEX_2: + if(tls->t_context.clut_dirty[1]){ + VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0A9C, 4, tls->t_context.colors[1])); + tls->t_context.clut_dirty[1] = 0; + } + else + { + tls->t_context.clut_used[1] = 1; + } + break; + + default: + if(tls->t_context.clut_dirty[0]){ + VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0A98, 2, tls->t_context.colors[0])); + tls->t_context.clut_dirty[0] = 0; + } + else + { + tls->t_context.clut_used[0] = 1; + } + } + } +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + + if(!ctx->premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, 0x10000001 | imageMode | blend_mode | transparency_mode)); + } else { + /* enable pre-multiplied from VG to VGPE */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, 0x00000001 | imageMode | blend_mode | transparency_mode)); + } + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A02, color)); + + VG_LITE_RETURN_ERROR(set_interpolation_steps(target, rect_w, rect_h, matrix)); + + if(!ctx->premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { + if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A25, convert_source_format(source->format) | filter | conversion | 0x01000100)); + } else { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A25, convert_source_format(source->format) | filter | conversion | 0x00000100)); + } + } else { + /* enable pre-multiplied in imager unit */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A25, convert_source_format(source->format) | filter | conversion)); + } + + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A27, 0)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A29, source->address)); + + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2B, source->stride | tiled_source)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2D, rect_x | (rect_y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2F, rect_w | (rect_h << 16))); + VG_LITE_RETURN_ERROR(push_rectangle(ctx, bounding_box.x, bounding_box.y, bounding_box.width, + bounding_box.height)); + error = flush_target(); + + vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); +#if DUMP_IMAGE + dump_img(source->memory, src_align_width, source->height, source->format); +#endif + + return error; +} + +/* Program initial states for tessellation buffer. */ +static vg_lite_error_t program_tessellation(vg_lite_context_t *context) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint32_t tessellation_size; +#if !defined(VG_DRIVER_SINGLE_THREAD) + uint32_t offset; +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + + tessellation_size = ( context->tsbuffer.tessellation_buffer_size[2] + ? context->tsbuffer.tessellation_buffer_size[2] + : context->tsbuffer.tessellation_buffer_size[1] + ); +#if !defined(VG_DRIVER_SINGLE_THREAD) + offset = CMDBUF_OFFSET(*context); +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + + /* Since TS buffer won't change during runtime, we program it here in initialization. */ + /* Program tessellation buffer: input for VG module. */ + VG_LITE_RETURN_ERROR(push_state(context, 0x0A30, context->tsbuffer.tessellation_buffer_gpu[0])); /* Tessellation buffer address. */ + VG_LITE_RETURN_ERROR(push_state(context, 0x0A31, context->tsbuffer.tessellation_buffer_gpu[1])); /* L1 address of tessellation buffer. */ + VG_LITE_RETURN_ERROR(push_state(context, 0x0A32, context->tsbuffer.tessellation_buffer_gpu[2])); /* L2 address of tessellation buffer. */ + VG_LITE_RETURN_ERROR(push_state(context, 0x0A33, context->tsbuffer.tessellation_stride)); + /* Program tessellation control: for TS module. */ + VG_LITE_RETURN_ERROR(push_state(context, 0x0A35, context->tsbuffer.tessellation_buffer_gpu[0])); + VG_LITE_RETURN_ERROR(push_state(context, 0x0A36, context->tsbuffer.tessellation_buffer_gpu[1])); + VG_LITE_RETURN_ERROR(push_state(context, 0x0A37, context->tsbuffer.tessellation_buffer_gpu[2])); + VG_LITE_RETURN_ERROR(push_state(context, 0x0A38, context->tsbuffer.tessellation_stride)); + VG_LITE_RETURN_ERROR(push_state(context, 0x0A3A, context->tsbuffer.tessellation_width_height)); + + VG_LITE_RETURN_ERROR(push_state(context, 0x0A3D, tessellation_size / 64)); + +#if !defined(VG_DRIVER_SINGLE_THREAD) + /* Backup tessellation buffer states. */ + context->ts_init_used = 0; + context->ts_init_use = 0; + context->ts_dirty = 1; + memcpy(context->ts_record, (CMDBUF_BUFFER(*context) + offset), 80); + CMDBUF_OFFSET(*context) = 0; +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + + return error; +} + +#if defined(VG_DRIVER_SINGLE_THREAD) +vg_lite_error_t vg_lite_init(int32_t tessellation_width, + int32_t tessellation_height) +{ + vg_lite_error_t error; + vg_lite_kernel_initialize_t initialize; + + s_context.rtbuffer = (vg_lite_buffer_t *)malloc(sizeof(vg_lite_buffer_t)); + if(!s_context.rtbuffer) + return VG_LITE_OUT_OF_RESOURCES; + memset(s_context.rtbuffer, 0, sizeof(vg_lite_buffer_t)); + + if (tessellation_width <= 0) { + tessellation_width = 0; + tessellation_height = 0; + } + if (tessellation_height <= 0) { + tessellation_height = 0; + tessellation_width = 0; + } + tessellation_width = VG_LITE_ALIGN(tessellation_width, 16); + +#if VG_TARGET_FAST_CLEAR + vg_lite_get_product_info(NULL,&s_context.chip_id,&s_context.chip_rev); + vg_lite_get_register(0x30, &cid); + if(s_context.chip_id == 0x255 && s_context.chip_rev == 0x1311 && cid == 0x404) + { + tessellation_width = 64; + tessellation_height = 64; + } +#endif + + /* Allocate a command buffer and a tessellation buffer. */ + initialize.command_buffer_size = command_buffer_size; + initialize.tessellation_width = tessellation_width; + initialize.tessellation_height = tessellation_height; + initialize.context = &s_context.context; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_INITIALIZE, &initialize)); + + /* Save draw context. */ + s_context.capabilities = initialize.capabilities; + s_context.command_buffer[0] = (uint8_t *)initialize.command_buffer[0]; + s_context.command_buffer[1] = (uint8_t *)initialize.command_buffer[1]; + s_context.command_buffer_size = initialize.command_buffer_size; + s_context.command_offset[0] = 0; + s_context.command_offset[1] = 0; + + if ((tessellation_width > 0) && + (tessellation_height > 0)) + { + /* Set and Program Tessellation Buffer states. */ + s_context.tsbuffer.tessellation_buffer_gpu[0] = initialize.tessellation_buffer_gpu[0]; + s_context.tsbuffer.tessellation_buffer_gpu[1] = initialize.tessellation_buffer_gpu[1]; + s_context.tsbuffer.tessellation_buffer_gpu[2] = initialize.tessellation_buffer_gpu[2]; + s_context.tsbuffer.tessellation_buffer_logic[0] = initialize.tessellation_buffer_logic[0]; + s_context.tsbuffer.tessellation_buffer_logic[1] = initialize.tessellation_buffer_logic[1]; + s_context.tsbuffer.tessellation_buffer_logic[2] = initialize.tessellation_buffer_logic[2]; + s_context.tsbuffer.tessellation_stride = initialize.tessellation_stride; + s_context.tsbuffer.tessellation_width_height = initialize.tessellation_width_height; + s_context.tsbuffer.tessellation_buffer_size[0] = initialize.tessellation_buffer_size[0]; + s_context.tsbuffer.tessellation_buffer_size[1] = initialize.tessellation_buffer_size[1]; + s_context.tsbuffer.tessellation_buffer_size[2] = initialize.tessellation_buffer_size[2]; + s_context.tsbuffer.tessellation_shift = initialize.tessellation_shift; + + VG_LITE_RETURN_ERROR(program_tessellation(&s_context)); + } + + /* Fill feature table. */ + if (!s_context.s_ftable.ftflag){ + VG_LITE_RETURN_ERROR(fill_feature_table(s_context.s_ftable.ftable)); + } + +#if VG_TARGET_FAST_CLEAR + /* Reset the FAST_CLEAR buffer. */ + memset(&s_context.fcBuffer, 0, sizeof(s_context.fcBuffer)); + s_context.fcBuffer.format = VG_LITE_A8; + s_context.fcBuffer.height = 1; + s_context.clearValue = 0; +#endif + + /* Init scissor rect. */ + s_context.scissor[0] = + s_context.scissor[1] = + s_context.scissor[2] = + s_context.scissor[3] = 0; +#if DUMP_CAPTURE + _SetDumpFileInfo(); +#endif + +#if (VG_RENDER_TEXT==1) + vg_lite_text_init(); +#endif /* VG_RENDER_TEXT */ + + return VG_LITE_SUCCESS; +} +#else +vg_lite_error_t vg_lite_init(int32_t tessellation_width, + int32_t tessellation_height) +{ + vg_lite_error_t error; + vg_lite_kernel_initialize_t initialize; + vg_lite_tls_t* task_tls; + + task_tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(task_tls) + return VG_LITE_SUCCESS; + + task_tls = (vg_lite_tls_t *) vg_lite_os_malloc(sizeof(vg_lite_tls_t)); + if(!task_tls) + return VG_LITE_OUT_OF_RESOURCES; + memset(task_tls,0,sizeof(vg_lite_tls_t)); + error = (vg_lite_error_t)vg_lite_os_set_tls((void *) task_tls); + if(error != VG_LITE_SUCCESS) + return error; + + task_tls->t_context.rtbuffer = NULL; + + if (tessellation_width <= 0) { + tessellation_width = 0; + tessellation_height = 0; + } + if (tessellation_height <= 0) { + tessellation_height = 0; + tessellation_width = 0; + } + tessellation_width = VG_LITE_ALIGN(tessellation_width, 16); + + /* Allocate a command buffer and a tessellation buffer. */ + initialize.command_buffer_size = command_buffer_size; + initialize.context_buffer_size = CONTEXT_BUFFER_SIZE; + initialize.tessellation_width = tessellation_width; + initialize.tessellation_height = tessellation_height; + initialize.context = &task_tls->t_context.context; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_INITIALIZE, &initialize)); + + /* Save draw context. */ + task_tls->t_context.capabilities = initialize.capabilities; + task_tls->t_context.command_buffer[0] = (uint8_t *)initialize.command_buffer[0]; + task_tls->t_context.command_buffer[1] = (uint8_t *)initialize.command_buffer[1]; + task_tls->t_context.command_buffer_size = initialize.command_buffer_size; + task_tls->t_context.command_offset[0] = 0; + task_tls->t_context.command_offset[1] = 0; + task_tls->t_context.command_buffer_current = 0; + task_tls->t_context.context_buffer[0] = (uint8_t *)initialize.context_buffer[0]; + task_tls->t_context.context_buffer[1] = (uint8_t *)initialize.context_buffer[1]; + task_tls->t_context.context_buffer_size = initialize.context_buffer_size; + task_tls->t_context.context_buffer_offset[0] = 0; + task_tls->t_context.context_buffer_offset[1] = 0; + task_tls->t_context.start_offset = 0; + task_tls->t_context.end_offset = 0; + task_tls->t_context.ts_init = 0; + memset(task_tls->t_context.ts_record, 0, sizeof(task_tls->t_context.ts_record)); + + if ((tessellation_width > 0) && + (tessellation_height > 0)) + { + /* Set and Program Tessellation Buffer states. */ + task_tls->t_context.tsbuffer.tessellation_buffer_gpu[0] = initialize.tessellation_buffer_gpu[0]; + task_tls->t_context.tsbuffer.tessellation_buffer_gpu[1] = initialize.tessellation_buffer_gpu[1]; + task_tls->t_context.tsbuffer.tessellation_buffer_gpu[2] = initialize.tessellation_buffer_gpu[2]; + task_tls->t_context.tsbuffer.tessellation_buffer_logic[0] = initialize.tessellation_buffer_logic[0]; + task_tls->t_context.tsbuffer.tessellation_buffer_logic[1] = initialize.tessellation_buffer_logic[1]; + task_tls->t_context.tsbuffer.tessellation_buffer_logic[2] = initialize.tessellation_buffer_logic[2]; + task_tls->t_context.tsbuffer.tessellation_stride = initialize.tessellation_stride; + task_tls->t_context.tsbuffer.tessellation_width_height = initialize.tessellation_width_height; + task_tls->t_context.tsbuffer.tessellation_buffer_size[0] = initialize.tessellation_buffer_size[0]; + task_tls->t_context.tsbuffer.tessellation_buffer_size[1] = initialize.tessellation_buffer_size[1]; + task_tls->t_context.tsbuffer.tessellation_buffer_size[2] = initialize.tessellation_buffer_size[2]; + task_tls->t_context.tsbuffer.tessellation_shift = initialize.tessellation_shift; + + VG_LITE_RETURN_ERROR(program_tessellation(&task_tls->t_context)); + } + + VG_LITE_RETURN_ERROR(push_state(&task_tls->t_context, 0x0A00, 0x0)); + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_LOCK, NULL)); + /* Fill feature table. */ + if (!task_tls->t_context.s_ftable.ftflag){ + VG_LITE_RETURN_ERROR(fill_feature_table(task_tls->t_context.s_ftable.ftable)); + } + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_UNLOCK, NULL)); + +#if VG_TARGET_FAST_CLEAR + /* Reset the FAST_CLEAR buffer. */ + memset(&task_tls->t_context.fcBuffer, 0, sizeof(task_tls->t_context.fcBuffer)); + task_tls->t_context.fcBuffer.format = VG_LITE_A8; + task_tls->t_context.fcBuffer.height = 1; + task_tls->t_context.clearValue = 0; +#endif + + /* Init scissor rect. */ + task_tls->t_context.scissor[0] = + task_tls->t_context.scissor[1] = + task_tls->t_context.scissor[2] = + task_tls->t_context.scissor[3] = 0; +#if DUMP_CAPTURE + _SetDumpFileInfo(); +#endif + +#if (VG_RENDER_TEXT==1) + vg_lite_text_init(); +#endif /* VG_RENDER_TEXT */ + + return VG_LITE_SUCCESS; +} +#endif /* VG_DRIVER_SINGLE_THREAD */ + +vg_lite_error_t vg_lite_set_draw_path_type(vg_lite_path_t * path,vg_lite_draw_path_type_t path_type) +{ + if(!path || (path_type > VG_LITE_DRAW_STROKE_PATH + 1)) + return VG_LITE_INVALID_ARGUMENT; + + path->path_type = path_type; + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_draw(vg_lite_buffer_t * target, + vg_lite_path_t * path, + vg_lite_fill_t fill_rule, + vg_lite_matrix_t * matrix, + vg_lite_blend_t blend, + vg_lite_color_t color) +{ + uint32_t blend_mode; + uint32_t format, quality, tiling, fill; + uint32_t tessellation_size; + vg_lite_error_t error; + vg_lite_point_t point_min = {0}, point_max = {0}, temp = {0}; + int x, y, width, height; + uint8_t ts_is_fullscreen = 0; +#if DUMP_COMMAND + uint32_t return_offset = 0; + vg_lite_kernel_allocate_t memory; +#endif + int32_t dst_align_width; + uint32_t mul, div, align; +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t *tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + if(!path) + return VG_LITE_INVALID_ARGUMENT; + + if(!path->path_length) + return VG_LITE_SUCCESS; + + if(!path->path) + return VG_LITE_INVALID_ARGUMENT; + + if(!vg_lite_query_feature(gcFEATURE_BIT_VG_QUALITY_8X) && path->quality == VG_LITE_UPPER){ + return VG_LITE_NOT_SUPPORT; + } + + error = set_render_target(target); + if (error != VG_LITE_SUCCESS) { + return error; + } else if (error == VG_LITE_NO_CONTEXT) { + /* If scissoring is enabled and no valid scissoring rectangles + are present, no drawing occurs */ + return VG_LITE_SUCCESS; + } + + width = ctx->tsbuffer.tessellation_width_height & 0xFFFF; + height = ctx->tsbuffer.tessellation_width_height >> 16; + get_format_bytes(target->format, &mul, &div, &align); + dst_align_width = target->stride * div / mul; + if(width == 0 || height == 0) + return VG_LITE_NO_CONTEXT; + if ((dst_align_width <= width) && (target->height <= height)) + { + ts_is_fullscreen = 1; + point_min.x = 0; + point_min.y = 0; + point_max.x = dst_align_width; + point_max.y = target->height; + } + + if (ts_is_fullscreen == 0){ + transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[1], matrix); + point_min = point_max = temp; + + transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[1], matrix); + if (temp.x < point_min.x) point_min.x = temp.x; + if (temp.y < point_min.y) point_min.y = temp.y; + if (temp.x > point_max.x) point_max.x = temp.x; + if (temp.y > point_max.y) point_max.y = temp.y; + + transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[3], matrix); + if (temp.x < point_min.x) point_min.x = temp.x; + if (temp.y < point_min.y) point_min.y = temp.y; + if (temp.x > point_max.x) point_max.x = temp.x; + if (temp.y > point_max.y) point_max.y = temp.y; + + transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[3], matrix); + if (temp.x < point_min.x) point_min.x = temp.x; + if (temp.y < point_min.y) point_min.y = temp.y; + if (temp.x > point_max.x) point_max.x = temp.x; + if (temp.y > point_max.y) point_max.y = temp.y; + + if (point_min.x < 0) point_min.x = 0; + if (point_min.y < 0) point_min.y = 0; + if (point_max.x > dst_align_width) point_max.x = dst_align_width; + if (point_max.y > target->height) point_max.y = target->height; + } + + if (ctx->scissor_enabled) { + point_min.x = MAX(point_min.x, ctx->scissor[0]); + point_min.y = MAX(point_min.y, ctx->scissor[1]); + point_max.x = MIN(point_max.x, ctx->scissor[0] + ctx->scissor[2]); + point_max.y = MIN(point_max.y, ctx->scissor[1] + ctx->scissor[3]); + } + + /* Convert states into hardware values. */ + blend_mode = convert_blend(blend); + format = convert_path_format(path->format); + quality = convert_path_quality(path->quality); + tiling = (ctx->capabilities.cap.tiled == 2) ? 0x2000000 : 0; + fill = (fill_rule == VG_LITE_FILL_EVEN_ODD) ? 0x10 : 0; + tessellation_size = ( ctx->tsbuffer.tessellation_buffer_size[2] + ? ctx->tsbuffer.tessellation_buffer_size[2] + : ctx->tsbuffer.tessellation_buffer_size[1] + ); + +#if !defined(VG_DRIVER_SINGLE_THREAD) + if(ctx->ts_dirty){ + memcpy(CMDBUF_BUFFER(*ctx) + CMDBUF_OFFSET(*ctx), ctx->ts_record, 80); + CMDBUF_OFFSET(*ctx) += 80; + ctx->ts_dirty = 0; + ctx->ts_init_used = 1; + } + else + { + ctx->ts_init_use = 1; + } +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + + /* Setup the command buffer. */ + /* Program color register. */ + if(ctx->premultiply_enabled) { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, ctx->capabilities.cap.tiled | blend_mode)); + } else { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, 0x10000000 | ctx->capabilities.cap.tiled | blend_mode)); + } + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A02, color)); + /* Program tessellation control: for TS module. */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A34, 0x01000200 | format | quality | tiling | fill)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3B, 0x3F800000)); /* Path tessellation SCALE. */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3C, 0x00000000)); /* Path tessellation BIAS. */ + /* Program matrix. */ + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A40, (void *) &matrix->m[0][0])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A41, (void *) &matrix->m[0][1])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A42, (void *) &matrix->m[0][2])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A43, (void *) &matrix->m[1][0])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A44, (void *) &matrix->m[1][1])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A45, (void *) &matrix->m[1][2])); + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { + vglitemDUMP_BUFFER("path", path->uploaded.address, (uint8_t *)(path->uploaded.memory), 0, path->uploaded.bytes); + } + vglitemDUMP("@[memory 0x%08X 0x%08X]", ctx->tsbuffer.tessellation_buffer_gpu[0], ctx->tsbuffer.tessellation_buffer_size[0]); + /* Setup tessellation loop. */ + if((path->path_type & 0x1) == VG_LITE_DRAW_FILL_PATH) { + for (y = point_min.y; y < point_max.y; y += height) { + for (x = point_min.x; x < point_max.x; x += width) { + /* Tessellate path. */ + VG_LITE_RETURN_ERROR(push_stall(ctx, 15)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A1B, 0x00011000)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A01, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A39, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3D, tessellation_size / 64)); + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { + VG_LITE_RETURN_ERROR(push_call(ctx, path->uploaded.address, path->uploaded.bytes)); +#if (DUMP_COMMAND) + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[0], 0); + + unsigned char* pt = (unsigned char*) memory.memory; + + for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) + { + if (i % 8 == 0) + fprintf(fp, "Command buffer: "); + + if (i % 4 == 0) + fprintf(fp, "0x"); + + for (int j = 3; j >= 0; --j) + fprintf(fp, "%02x", pt[i + j]); + + if ((i / 4 + 1) % 2 == 0) + fprintf(fp, ",\n"); + else + fprintf(fp, ", "); + } + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[return_offset], 0); + + fclose(fp); + fp = NULL; +#endif + } else { + push_data(ctx, path->path_length, path->path); + } + } + } + } + /* Setup tessellation loop. */ + if(path->path_type == VG_LITE_DRAW_STROKE_PATH || path->path_type == VG_LITE_DRAW_FILL_STROKE_PATH) { + for (y = point_min.y; y < point_max.y; y += height) { + for (x = point_min.x; x < point_max.x; x += width) { + /* Tessellate path. */ + VG_LITE_RETURN_ERROR(push_stall(ctx, 15)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A1B, 0x00011000)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A01, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A39, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3D, tessellation_size / 64)); + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { + VG_LITE_RETURN_ERROR(push_call(ctx, path->uploaded.address, path->uploaded.bytes)); +#if (DUMP_COMMAND) + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[0], 0); + + unsigned char* pt = (unsigned char*) memory.memory; + + for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) + { + if (i % 8 == 0) + fprintf(fp, "Command buffer: "); + + if (i % 4 == 0) + fprintf(fp, "0x"); + + for (int j = 3; j >= 0; --j) + fprintf(fp, "%02x", pt[i + j]); + + if ((i / 4 + 1) % 2 == 0) + fprintf(fp, ",\n"); + else + fprintf(fp, ", "); + } + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[return_offset], 0); + + fclose(fp); + fp = NULL; +#endif + } else { + format = convert_path_format(VG_LITE_FP32); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A34, 0x01000200 | format | quality | tiling | 0x0)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A02, path->stroke_color)); + push_data(ctx, path->stroke_path_size, path->stroke_path_data); + } + } + } + } + + /* Finialize command buffer. */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A34, 0)); + + /* Notify rendering area (added by MicroEJ) */ + vg_lite_draw_notify_render_area(point_min.x, point_min.y, point_max.x, point_max.y); + + VG_LITE_RETURN_ERROR(flush_target()); +#if !defined(VG_DRIVER_SINGLE_THREAD) + ctx->ts_init = 1; +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + return error; +} + +vg_lite_error_t vg_lite_close(void) +{ + vg_lite_error_t error; + vg_lite_kernel_terminate_t terminate; +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + +#if VG_TARGET_FAST_CLEAR + if (ctx->fcBuffer.handle != NULL) { + vg_lite_free(&ctx->fcBuffer); + } +#endif + + /* Termnate the draw context. */ + terminate.context = &ctx->context; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_TERMINATE, &terminate)); + +#if defined(VG_DRIVER_SINGLE_THREAD) + if(ctx->rtbuffer) + free(ctx->rtbuffer); + + submit_flag = 0; + + /* Reset the draw context. */ + _memset(ctx, 0, sizeof(s_context)); + + /* Reset the s_ftable. */ + _memset(&ctx->s_ftable, 0, sizeof(ctx->s_ftable)); + + ctx->init = 0; +#else + /* Reset the draw context. */ + free(ctx->colors[0]); + free(ctx->colors[1]); + free(ctx->colors[2]); + free(ctx->colors[3]); + + _memset(ctx, 0, sizeof(*ctx)); + + vg_lite_os_reset_tls(); + vg_lite_os_free((void *) tls); +#endif /* VG_DRIVER_SINGLE_THREAD */ + +#if DUMP_CAPTURE + _SetDumpFileInfo(); +#endif + + return VG_LITE_SUCCESS; +} + +/* Handle tiled & yuv allocation. Currently including NV12, ANV12, YV12, YV16, NV16, YV24. */ +static vg_lite_error_t _allocate_tiled_yuv_planar(vg_lite_buffer_t *buffer) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint32_t yplane_size = 0; + vg_lite_kernel_allocate_t allocate, uv_allocate, v_allocate; + + if ((buffer->format < VG_LITE_NV12) || (buffer->format > VG_LITE_ANV12_TILED) + || (buffer->format == VG_LITE_AYUY2) || (buffer->format == VG_LITE_YUY2_TILED)) + { + return error; + } + + /* For NV12, there are 2 planes (Y, UV); + For ANV12, there are 3 planes (Y, UV, Alpha). + Each plane must be aligned by (4, 8). + Then Y plane must be aligned by (8, 8). + For YVxx, there are 3 planes (Y, U, V). + YV12 is similar to NV12, both YUV420 format. + YV16 and NV16 are YUV422 format. + YV24 is YUV444 format. + */ + buffer->width = VG_LITE_ALIGN(buffer->width, 8); + buffer->height = VG_LITE_ALIGN(buffer->height, 8); + buffer->stride = VG_LITE_ALIGN(buffer->width, 128); + + switch (buffer->format) { + case VG_LITE_NV12: + case VG_LITE_ANV12: + case VG_LITE_NV12_TILED: + case VG_LITE_ANV12_TILED: + buffer->yuv.uv_stride = buffer->stride; + buffer->yuv.alpha_stride = buffer->stride; + buffer->yuv.uv_height = buffer->height / 2; + break; + + case VG_LITE_NV16: + buffer->yuv.uv_stride = buffer->stride; + buffer->yuv.uv_height = buffer->height; + break; + + case VG_LITE_YV12: + buffer->yuv.uv_stride = + buffer->yuv.v_stride = buffer->stride / 2; + buffer->yuv.uv_height = + buffer->yuv.v_height = buffer->height / 2; + break; + + case VG_LITE_YV16: + buffer->yuv.uv_stride = + buffer->yuv.v_stride = buffer->stride; + buffer->yuv.uv_height = + buffer->yuv.v_height = buffer->height / 2; + break; + + case VG_LITE_YV24: + buffer->yuv.uv_stride = + buffer->yuv.v_stride = buffer->stride; + buffer->yuv.uv_height = + buffer->yuv.v_height = buffer->height; + break; + + default: + return error; + } + + yplane_size = buffer->stride * buffer->height; + + /* Allocate buffer memory: Y. */ + allocate.bytes = yplane_size; + allocate.contiguous = 1; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); + + /* Save the allocation. */ + buffer->handle = allocate.memory_handle; + buffer->memory = allocate.memory; + buffer->address = allocate.memory_gpu; + + if ((buffer->format == VG_LITE_NV12) || (buffer->format == VG_LITE_ANV12) + || (buffer->format == VG_LITE_NV16) || (buffer->format == VG_LITE_NV12_TILED) + || (buffer->format == VG_LITE_ANV12_TILED)) { + /* Allocate buffer memory: UV. */ + uv_allocate.bytes = buffer->yuv.uv_stride * buffer->yuv.uv_height; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &uv_allocate)); + buffer->yuv.uv_handle = uv_allocate.memory_handle; + buffer->yuv.uv_memory = uv_allocate.memory; + buffer->yuv.uv_planar = uv_allocate.memory_gpu; + + if ((buffer->format == VG_LITE_ANV12) || (buffer->format == VG_LITE_ANV12_TILED)) { + uv_allocate.bytes = yplane_size; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &uv_allocate)); + buffer->yuv.alpha_planar = uv_allocate.memory_gpu; + } + } else { + /* Allocate buffer memory: U, V. */ + uv_allocate.bytes = buffer->yuv.uv_stride * buffer->yuv.uv_height; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &uv_allocate)); + buffer->yuv.uv_handle = uv_allocate.memory_handle; + buffer->yuv.uv_memory = uv_allocate.memory; + buffer->yuv.uv_planar = uv_allocate.memory_gpu; + + v_allocate.bytes = buffer->yuv.v_stride * buffer->yuv.v_height; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &v_allocate)); + buffer->yuv.v_handle = v_allocate.memory_handle; + buffer->yuv.v_memory = v_allocate.memory; + buffer->yuv.v_planar = v_allocate.memory_gpu; + } + + return error; +} + +vg_lite_error_t vg_lite_allocate(vg_lite_buffer_t * buffer) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_kernel_allocate_t allocate; + + /* Reset planar. */ + buffer->yuv.uv_planar = + buffer->yuv.v_planar = + buffer->yuv.alpha_planar = 0; + + /* Align height in case format is tiled. */ + if (buffer->format >= VG_LITE_YUY2 && buffer->format <= VG_LITE_NV16) { + buffer->height = VG_LITE_ALIGN(buffer->height, 4); + buffer->yuv.swizzle = VG_LITE_SWIZZLE_UV; + } + + if (buffer->format >= VG_LITE_YUY2_TILED && buffer->format <= VG_LITE_AYUY2_TILED) { + buffer->height = VG_LITE_ALIGN(buffer->height, 4); + buffer->tiled = VG_LITE_TILED; + buffer->yuv.swizzle = VG_LITE_SWIZZLE_UV; + } + + if ((buffer->format >= VG_LITE_NV12 && buffer->format <= VG_LITE_ANV12_TILED + && buffer->format != VG_LITE_AYUY2 && buffer->format != VG_LITE_YUY2_TILED)) { + _allocate_tiled_yuv_planar(buffer); + } + else { + /* Driver need compute the stride always with RT500 project. */ + uint32_t mul, div, align; +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + get_format_bytes(buffer->format, &mul, &div, &align); + vg_lite_get_product_info(NULL,&ctx->chip_id,NULL); + buffer->stride = VG_LITE_ALIGN((buffer->width * mul / div), align); + /* Allocate the buffer. */ + allocate.bytes = buffer->stride * buffer->height; +#if VG_TARGET_FAST_CLEAR + allocate.bytes = VG_LITE_ALIGN(allocate.bytes, 64); +#endif + allocate.contiguous = 1; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); + + /* Save the buffer allocation. */ + buffer->handle = allocate.memory_handle; + buffer->memory = allocate.memory; + buffer->address = allocate.memory_gpu; + + if ((buffer->format == VG_LITE_AYUY2) || (buffer->format == VG_LITE_AYUY2_TILED)) { + allocate.bytes = buffer->stride * buffer->height; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); + buffer->yuv.alpha_planar = allocate.memory_gpu; + } + + } + + return VG_LITE_SUCCESS; +} + +#if defined(VG_DRIVER_SINGLE_THREAD) +vg_lite_error_t vg_lite_free(vg_lite_buffer_t * buffer) +{ + vg_lite_error_t error; + vg_lite_kernel_free_t free, uv_free, v_free; + + if(buffer == NULL) + return VG_LITE_INVALID_ARGUMENT; + if (!(memcmp(s_context.rtbuffer,buffer,sizeof(vg_lite_buffer_t))) ) { + if (VG_LITE_SUCCESS == submit(&s_context)) { + VG_LITE_RETURN_ERROR(stall(&s_context, 0, ~0)); + } + vglitemDUMP("@[swap 0x%08X %dx%d +%u]", + s_context.rtbuffer->address, + s_context.rtbuffer->width, s_context.rtbuffer->height, + s_context.rtbuffer->stride); + vglitemDUMP_BUFFER( + "framebuffer", + s_context.rtbuffer->address,s_context.rtbuffer->memory, + 0, + s_context.rtbuffer->stride*(s_context.rtbuffer->height)); + + memset(s_context.rtbuffer, 0, sizeof(vg_lite_buffer_t)); + } + + if (buffer->yuv.uv_planar) { + /* Free UV(U) planar buffer. */ + uv_free.memory_handle = buffer->yuv.uv_handle; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &uv_free)); + + /* Mark the buffer as freed. */ + buffer->yuv.uv_handle = NULL; + buffer->yuv.uv_memory = NULL; + } + + if (buffer->yuv.v_planar) { + /* Free V planar buffer. */ + v_free.memory_handle = buffer->yuv.v_handle; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &v_free)); + + /* Mark the buffer as freed. */ + buffer->yuv.v_handle = NULL; + buffer->yuv.v_memory = NULL; + } + + /* Make sure we have a valid memory handle. */ + if (buffer->handle == NULL) { + return VG_LITE_INVALID_ARGUMENT; + } + + /* Free the buffer. */ + free.memory_handle = buffer->handle; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &free)); + + /* Mark the buffer as freed. */ + buffer->handle = NULL; + buffer->memory = NULL; + + return VG_LITE_SUCCESS; +} +#else +vg_lite_error_t vg_lite_free(vg_lite_buffer_t * buffer) +{ + vg_lite_error_t error; + vg_lite_kernel_free_t free, uv_free, v_free; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + if(buffer == NULL) + return VG_LITE_INVALID_ARGUMENT; + if (tls->t_context.rtbuffer == buffer && !(memcmp(tls->t_context.rtbuffer,buffer,sizeof(vg_lite_buffer_t))) ) { + if (VG_LITE_SUCCESS == submit(&tls->t_context)) { + VG_LITE_RETURN_ERROR(stall(&tls->t_context, 0)); + } + vglitemDUMP("@[swap 0x%08X %dx%d +%u]", + tls->t_context.rtbuffer->address, + tls->t_context.rtbuffer->width, tls->t_context.rtbuffer->height, + tls->t_context.rtbuffer->stride); + vglitemDUMP_BUFFER( + "framebuffer", + tls->t_context.rtbuffer->address,tls->t_context.rtbuffer->memory, + 0, + tls->t_context.rtbuffer->stride*(tls->t_context.rtbuffer->height)); + + memset(tls->t_context.rtbuffer, 0, sizeof(vg_lite_buffer_t)); + } + + if (buffer->yuv.uv_planar) { + /* Free UV(U) planar buffer. */ + uv_free.memory_handle = buffer->yuv.uv_handle; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &uv_free)); + + /* Mark the buffer as freed. */ + buffer->yuv.uv_handle = NULL; + buffer->yuv.uv_memory = NULL; + } + + if (buffer->yuv.v_planar) { + /* Free V planar buffer. */ + v_free.memory_handle = buffer->yuv.v_handle; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &v_free)); + + /* Mark the buffer as freed. */ + buffer->yuv.v_handle = NULL; + buffer->yuv.v_memory = NULL; + } + + /* Make sure we have a valid memory handle. */ + if (buffer->handle == NULL) { + return VG_LITE_INVALID_ARGUMENT; + } + + /* Free the buffer. */ + free.memory_handle = buffer->handle; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &free)); + + /* Mark the buffer as freed. */ + buffer->handle = NULL; + buffer->memory = NULL; + + return VG_LITE_SUCCESS; +} +#endif /* VG_DRIVER_SINGLE_THREAD */ + +vg_lite_error_t vg_lite_map(vg_lite_buffer_t * buffer) +{ + vg_lite_error_t error; + vg_lite_kernel_map_t map; + + /* We either need a logical or physical address. */ + if (buffer->memory == NULL && buffer->address == 0) { + return VG_LITE_INVALID_ARGUMENT; + } + + /* Check if we need to compute the stride. Usually map a pre-allocated memory, so the stride + usually should be set*/ + if (buffer->stride == 0) { + uint32_t mul, div, align; + get_format_bytes(buffer->format, &mul, &div, &align); + /* Compute the stride to be aligned. */ + buffer->stride = VG_LITE_ALIGN((buffer->width * mul / div), align); + } + + /* Map the buffer. */ + map.bytes = buffer->stride * buffer->height; + map.logical = buffer->memory; + map.physical = buffer->address; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_MAP, &map)); + + /* Save the buffer allocation. */ + buffer->handle = map.memory_handle; + buffer->address = map.memory_gpu; + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_unmap(vg_lite_buffer_t * buffer) +{ + vg_lite_error_t error; + vg_lite_kernel_unmap_t unmap; + + /* Make sure we have a valid memory handle. */ + if (buffer->handle == NULL) { + return VG_LITE_INVALID_ARGUMENT; + } + + /* Unmap the buffer. */ + unmap.memory_handle = buffer->handle; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_UNMAP, &unmap)); + + /* Mark the buffer as freed. */ + buffer->handle = NULL; + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_get_register(uint32_t address, uint32_t * result) +{ + vg_lite_error_t error; + vg_lite_kernel_info_t data; + + /* Get input register address. */ + data.addr = address; + + /* Get register info. */ + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_CHECK, &data)); + + /* Return register info. */ + *result = data.reg; + + return VG_LITE_SUCCESS; +} + +void vg_lite_get_info(vg_lite_info_t *info) +{ + if (info != NULL) + { + info->api_version = VGLITE_API_VERSION_2_0; + info->header_version = VGLITE_HEADER_VERSION; + info->release_version = VGLITE_RELEASE_VERSION; + info->reserved = 0; + } +} + +uint32_t vg_lite_get_product_info(char *name, uint32_t *chip_id, uint32_t *chip_rev) +{ + const char *product_name = "GCNanoLiteV"; + uint32_t name_len; + uint32_t rev = 0, id = 0; + + vg_lite_get_register(0x24, &rev); + vg_lite_get_register(0x20, &id); + + name_len = strlen(product_name) + 1; + if (name != NULL) + { + memcpy(name, product_name, name_len); + } + + if (chip_id != NULL) + { + *chip_id = id; + } + + if (chip_rev != NULL) + { + *chip_rev = rev; + } + return name_len; +} + +uint32_t vg_lite_query_feature(vg_lite_feature_t feature) +{ + uint32_t result; +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t *tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if (tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + if (feature < gcFEATURE_COUNT) + result = ctx->s_ftable.ftable[feature]; + else + result = 0; + + return result; +} + +#if defined(VG_DRIVER_SINGLE_THREAD) +vg_lite_error_t vg_lite_finish() +{ + vg_lite_error_t error; + + /* Return if there is nothing to submit. */ + if (CMDBUF_OFFSET(s_context) == 0) + { + if(submit_flag) + VG_LITE_RETURN_ERROR(stall(&s_context, 0, (uint32_t)~0)); + return VG_LITE_SUCCESS; + } + + /* Flush is moved from each draw to here. */ + VG_LITE_RETURN_ERROR(flush_target()); + VG_LITE_RETURN_ERROR(submit(&s_context)); + VG_LITE_RETURN_ERROR(stall(&s_context, 0, (uint32_t)~0)); + +#if VG_TARGET_FAST_CLEAR + /*Only used in cmodel/fpga. In final SOC this SW FC decoder should be removed. */ + if (s_context.rtbuffer != NULL) { +#if VG_TARGET_FC_DUMP + fc_buf_dump(s_context.rtbuffer, &s_context.fcBuffer); +#endif /* VG_TARGET_FC_DUMP */ + } +#endif + + CMDBUF_SWAP(s_context); + /* Reset command buffer. */ + CMDBUF_OFFSET(s_context) = 0; + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_flush(void) +{ + vg_lite_error_t error; + + /* Return if there is nothing to submit. */ + if (CMDBUF_OFFSET(s_context) == 0) + return VG_LITE_SUCCESS; + + /* Wait if GPU has not completed previous CMD buffer */ + if (submit_flag) + { + VG_LITE_RETURN_ERROR(stall(&s_context, 0, (uint32_t)~0)); + } + + /* Submit the current command buffer. */ + VG_LITE_RETURN_ERROR(flush_target()); + VG_LITE_RETURN_ERROR(submit(&s_context)); + CMDBUF_SWAP(s_context); + /* Reset command buffer. */ + CMDBUF_OFFSET(s_context) = 0; + + return VG_LITE_SUCCESS; +} +#else +vg_lite_error_t vg_lite_finish() +{ + vg_lite_error_t error; + vg_lite_tls_t* tls; + uint32_t command_id, index; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + command_id = CMDBUF_INDEX(tls->t_context); + index = command_id ? 0 : 1; + + if (CMDBUF_OFFSET(tls->t_context) <= 8){ + /* Return if there is nothing to submit. */ + if (!CMDBUF_IN_QUEUE(&tls->t_context.context, 0) && !CMDBUF_IN_QUEUE(&tls->t_context.context, 1) ) + return VG_LITE_SUCCESS; + /* This frame has unfinished command. */ + else if(CMDBUF_IN_QUEUE(&tls->t_context.context, index)) + { + CMDBUF_SWAP(tls->t_context); + VG_LITE_RETURN_ERROR(stall(&tls->t_context, 0)); + } + /* This frame has unfinished command. */ + else if(CMDBUF_IN_QUEUE(&tls->t_context.context, command_id)) + { + VG_LITE_RETURN_ERROR(stall(&tls->t_context, 0)); + } + CMDBUF_OFFSET(tls->t_context) = 0; + VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x0)); + return VG_LITE_SUCCESS; + } + else + { + /* Flush is moved from each draw to here. */ + VG_LITE_RETURN_ERROR(flush_target()); + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_LOCK, NULL)); + /* if context have been switched and this task need use index. */ + VG_LITE_RETURN_ERROR(update_context_buffer()); + VG_LITE_RETURN_ERROR(submit(&tls->t_context)); + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_UNLOCK, NULL)); + VG_LITE_RETURN_ERROR(stall(&tls->t_context, 0)); + } + +#if VG_TARGET_FAST_CLEAR + /*Only used in cmodel/fpga. In final SOC this SW FC decoder should be removed. */ + if (tls->t_context.rtbuffer != NULL) { +#if VG_TARGET_FC_DUMP + fc_buf_dump(tls->t_context.rtbuffer, &tls->t_context.fcBuffer); +#endif /* VG_TARGET_FC_DUMP */ + } +#endif + + CMDBUF_SWAP(tls->t_context); + CMDBUF_OFFSET(tls->t_context) = 0; + VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x0)); + tls->t_context.ts_init_used = 0; + tls->t_context.ts_init_use = 0; + tls->t_context.ts_init = 0; + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_flush(void) +{ + vg_lite_error_t error; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + /* Return if there is nothing to submit. */ + if (CMDBUF_OFFSET(tls->t_context) == 0) + return VG_LITE_SUCCESS; + + /* Submit the current command buffer. */ + VG_LITE_RETURN_ERROR(flush_target()); + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_LOCK, NULL)); + /* if context have been switched and this task need use index. */ + VG_LITE_RETURN_ERROR(update_context_buffer()); + VG_LITE_RETURN_ERROR(submit(&tls->t_context)); + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_UNLOCK, NULL)); + + CMDBUF_SWAP(tls->t_context); + CMDBUF_OFFSET(tls->t_context) = 0; + VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x0)); + tls->t_context.ts_init_used = 0; + tls->t_context.ts_init_use = 0; + tls->t_context.ts_init = 0; + + return VG_LITE_SUCCESS; +} +#endif /* VG_DRIVER_SINGLE_THREAD */ + +vg_lite_error_t vg_lite_init_arc_path(vg_lite_path_t * path, + vg_lite_format_t data_format, + vg_lite_quality_t quality, + uint32_t path_length, + void * path_data, + vg_lite_float_t min_x, vg_lite_float_t min_y, + vg_lite_float_t max_x, vg_lite_float_t max_y) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint32_t i = 0,command = 0,offset = 0; + vg_lite_float_t moveToX,moveToY,lineToX,lineToY,controlX, controlY,quadToX, quadToY; + vg_lite_float_t controlX1, controlY1,controlX2, controlY2,cubicToX, cubicToY; + vg_lite_float_t horRadius,verRadius,rotAngle,endX,endY; + float *pfloat,*fpath; + char *cpath,*pathdata; + vg_lite_control_coord_t coords; + + if(path == NULL || path_data == NULL || data_format != VG_LITE_FP32) + return VG_LITE_INVALID_ARGUMENT; + + memset(path, 0, sizeof(*path)); + + if(!path_length) + { + path->format = data_format; + path->quality = quality; + path->bounding_box[0] = min_x; + path->bounding_box[1] = min_y; + path->bounding_box[2] = max_x; + path->bounding_box[3] = max_y; + + path->path_length = 0; + path->path = NULL; + path->pdata_internal = 1; + path->path_changed = 1; + path->uploaded.address = 0; + path->uploaded.bytes = 0; + path->uploaded.handle = NULL; + path->uploaded.memory = NULL; + return VG_LITE_SUCCESS; + } + + memset(&coords, 0, sizeof(vg_lite_control_coord_t)); + pathdata = (char *)vg_lite_os_malloc(path_length); + if (pathdata == NULL) + return VG_LITE_OUT_OF_MEMORY; + memset(pathdata, 0, path_length); + pfloat = (vg_lite_float_t *)path_data; + while(i < path_length) + { + cpath = (char *)pfloat; + command = (uint32_t)*cpath; + pfloat++; + switch (command) + { + case VLC_OP_END: + cpath = (char *)pathdata + offset; + fpath = (vg_lite_float_t *)cpath; + *cpath = VLC_OP_END; + offset += _commandSize_float[VLC_OP_END]; + i += _commandSize_float[VLC_OP_END]; + break; + case VLC_OP_CLOSE: + /* Update the control coordinates. */ + coords.lastX = coords.startX; + coords.lastY = coords.startY; + coords.controlX = coords.startX; + coords.controlY = coords.startY; + + cpath = (char *)pathdata + offset; + fpath = (vg_lite_float_t *)cpath; + *cpath = VLC_OP_CLOSE; + offset += _commandSize_float[VLC_OP_CLOSE]; + i += _commandSize_float[VLC_OP_CLOSE]; + break; + case VLC_OP_MOVE: + moveToX = *pfloat++; + moveToY = *pfloat++; + + /* Update the control coordinates. */ + coords.startX = moveToX; + coords.startY = moveToY; + coords.lastX = moveToX; + coords.lastY = moveToY; + coords.controlX = moveToX; + coords.controlY = moveToY; + + cpath = (char *)pathdata + offset; + fpath = (vg_lite_float_t *)cpath; + *cpath = VLC_OP_MOVE; + fpath++; + *fpath++ = moveToX; + *fpath++ = moveToY; + offset += _commandSize_float[VLC_OP_MOVE]; + i += _commandSize_float[VLC_OP_MOVE]; + break; + case VLC_OP_MOVE_REL: + moveToX = *pfloat++; + moveToY = *pfloat++; + + cpath = (char *)pathdata + offset; + fpath = (vg_lite_float_t *)cpath; + *cpath = VLC_OP_MOVE_REL; + fpath++; + *fpath++ = moveToX; + *fpath++ = moveToY; + offset += _commandSize_float[VLC_OP_MOVE_REL]; + i += _commandSize_float[VLC_OP_MOVE_REL]; + + /* Determine the absolute coordinates. */ + moveToX += coords.lastX; + moveToY += coords.lastY; + + /* Update the control coordinates. */ + coords.startX = moveToX; + coords.startY = moveToY; + coords.lastX = moveToX; + coords.lastY = moveToY; + coords.controlX = moveToX; + coords.controlY = moveToY; + break; + case VLC_OP_LINE: + lineToX = *pfloat++; + lineToY = *pfloat++; + + /* Update the control coordinates. */ + coords.lastX = lineToX; + coords.lastY = lineToY; + coords.controlX = lineToX; + coords.controlY = lineToY; + + cpath = (char *)pathdata + offset; + fpath = (vg_lite_float_t *)cpath; + *cpath = VLC_OP_LINE; + fpath++; + *fpath++ = lineToX; + *fpath++ = lineToY; + offset += _commandSize_float[VLC_OP_LINE]; + i += _commandSize_float[VLC_OP_LINE]; + break; + case VLC_OP_LINE_REL: + lineToX = *pfloat++; + lineToY = *pfloat++; + + cpath = (char *)pathdata + offset; + fpath = (vg_lite_float_t *)cpath; + *cpath = VLC_OP_LINE_REL; + fpath++; + *fpath++ = lineToX; + *fpath++ = lineToY; + offset += _commandSize_float[VLC_OP_LINE_REL]; + i += _commandSize_float[VLC_OP_LINE_REL]; + + /* Determine the absolute coordinates. */ + lineToX += coords.lastX; + lineToY += coords.lastY; + + /* Update the control coordinates. */ + coords.lastX = lineToX; + coords.lastY = lineToY; + coords.controlX = lineToX; + coords.controlY = lineToY; + break; + case VLC_OP_QUAD: + controlX = *pfloat++; + controlY = *pfloat++; + quadToX = *pfloat++; + quadToY = *pfloat++; + + /* Update the control coordinates. */ + coords.lastX = quadToX; + coords.lastY = quadToY; + coords.controlX = controlX; + coords.controlY = controlY; + + cpath = (char *)pathdata + offset; + fpath = (vg_lite_float_t *)cpath; + *cpath = VLC_OP_QUAD; + fpath++; + *fpath++ = controlX; + *fpath++ = controlY; + *fpath++ = quadToX; + *fpath++ = quadToY; + offset += _commandSize_float[VLC_OP_QUAD]; + i += _commandSize_float[VLC_OP_QUAD]; + break; + case VLC_OP_QUAD_REL: + controlX = *pfloat++; + controlY = *pfloat++; + quadToX = *pfloat++; + quadToY = *pfloat++; + + cpath = (char *)pathdata + offset; + fpath = (vg_lite_float_t *)cpath; + *cpath = VLC_OP_QUAD_REL; + fpath++; + *fpath++ = controlX; + *fpath++ = controlY; + *fpath++ = quadToX; + *fpath++ = quadToY; + offset += _commandSize_float[VLC_OP_QUAD_REL]; + i += _commandSize_float[VLC_OP_QUAD_REL]; + + /* Determine the absolute coordinates. */ + controlX += coords.lastX; + controlY += coords.lastY; + quadToX += coords.lastX; + quadToY += coords.lastY; + + /* Update the control coordinates. */ + coords.lastX = quadToX; + coords.lastY = quadToY; + coords.controlX = controlX; + coords.controlY = controlY; + break; + case VLC_OP_CUBIC: + controlX1 = *pfloat++; + controlY1 = *pfloat++; + controlX2 = *pfloat++; + controlY2 = *pfloat++; + cubicToX = *pfloat++; + cubicToY = *pfloat++; + + /* Update the control coordinates. */ + coords.lastX = cubicToX; + coords.lastY = cubicToY; + coords.controlX = controlX2; + coords.controlY = controlY2; + + cpath = (char *)pathdata + offset; + fpath = (vg_lite_float_t *)cpath; + *cpath = VLC_OP_CUBIC; + fpath++; + *fpath++ = controlX1; + *fpath++ = controlY1; + *fpath++ = controlX2; + *fpath++ = controlY2; + *fpath++ = cubicToX; + *fpath++ = cubicToY; + offset += _commandSize_float[VLC_OP_CUBIC]; + i += _commandSize_float[VLC_OP_CUBIC]; + break; + case VLC_OP_CUBIC_REL: + controlX1 = *pfloat++; + controlY1 = *pfloat++; + controlX2 = *pfloat++; + controlY2 = *pfloat++; + cubicToX = *pfloat++; + cubicToY = *pfloat++; + + cpath = (char *)pathdata + offset; + fpath = (vg_lite_float_t *)cpath; + *cpath = VLC_OP_CUBIC_REL; + fpath++; + *fpath++ = controlX1; + *fpath++ = controlY1; + *fpath++ = controlX2; + *fpath++ = controlY2; + *fpath++ = cubicToX; + *fpath++ = cubicToY; + offset += _commandSize_float[VLC_OP_CUBIC_REL]; + i += _commandSize_float[VLC_OP_CUBIC_REL]; + + /* Determine the absolute coordinates. */ + controlX2 += coords.lastX; + controlY2 += coords.lastY; + cubicToX += coords.lastX; + cubicToY += coords.lastY; + + /* Update the control coordinates. */ + coords.lastX = cubicToX; + coords.lastY = cubicToY; + coords.controlX = controlX2; + coords.controlY = controlY2; + break; + case VLC_OP_SCCWARC: + horRadius = *pfloat++; + verRadius = *pfloat++; + rotAngle = *pfloat++; + endX = *pfloat++; + endY = *pfloat++; + i += _commandSize_float[VLC_OP_SCCWARC]; + VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,FALSE,FALSE,FALSE,&coords,(void *)&pathdata,&offset,path_length - i)); + break; + case VLC_OP_SCCWARC_REL: + horRadius = *pfloat++; + verRadius = *pfloat++; + rotAngle = *pfloat++; + endX = *pfloat++; + endY = *pfloat++; + i += _commandSize_float[VLC_OP_SCCWARC_REL]; + VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,FALSE,FALSE,TURE,&coords,(void *)&pathdata,&offset,path_length - i)); + break; + case VLC_OP_SCWARC: + horRadius = *pfloat++; + verRadius = *pfloat++; + rotAngle = *pfloat++; + endX = *pfloat++; + endY = *pfloat++; + i += _commandSize_float[VLC_OP_SCCWARC_REL]; + VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,TURE,FALSE,FALSE,&coords,(void *)&pathdata,&offset,path_length - i)); + break; + case VLC_OP_SCWARC_REL: + horRadius = *pfloat++; + verRadius = *pfloat++; + rotAngle = *pfloat++; + endX = *pfloat++; + endY = *pfloat++; + i += _commandSize_float[VLC_OP_SCCWARC_REL]; + VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,TURE,FALSE,TURE,&coords,(void *)&pathdata,&offset,path_length - i)); + break; + case VLC_OP_LCCWARC: + horRadius = *pfloat++; + verRadius = *pfloat++; + rotAngle = *pfloat++; + endX = *pfloat++; + endY = *pfloat++; + i += _commandSize_float[VLC_OP_SCCWARC_REL]; + VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,FALSE,TURE,FALSE,&coords,(void *)&pathdata,&offset,path_length - i)); + break; + case VLC_OP_LCCWARC_REL: + horRadius = *pfloat++; + verRadius = *pfloat++; + rotAngle = *pfloat++; + endX = *pfloat++; + endY = *pfloat++; + i += _commandSize_float[VLC_OP_SCCWARC_REL]; + VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,FALSE,TURE,TURE,&coords,(void *)&pathdata,&offset,path_length - i)); + break; + case VLC_OP_LCWARC: + horRadius = *pfloat++; + verRadius = *pfloat++; + rotAngle = *pfloat++; + endX = *pfloat++; + endY = *pfloat++; + i += _commandSize_float[VLC_OP_SCCWARC_REL]; + VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,TURE,TURE,FALSE,&coords,(void *)&pathdata,&offset,path_length - i)); + break; + case VLC_OP_LCWARC_REL: + horRadius = *pfloat++; + verRadius = *pfloat++; + rotAngle = *pfloat++; + endX = *pfloat++; + endY = *pfloat++; + i += _commandSize_float[VLC_OP_SCCWARC_REL]; + VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,TURE,TURE,TURE,&coords,(void *)&pathdata,&offset,path_length - i)); + break; + default: + break; + } + } + + path->format = data_format; + path->quality = quality; + path->bounding_box[0] = min_x; + path->bounding_box[1] = min_y; + path->bounding_box[2] = max_x; + path->bounding_box[3] = max_y; + + path->path_length = offset; + path->path = pathdata; + path->pdata_internal = 1; + path->path_changed = 1; + path->uploaded.address = 0; + path->uploaded.bytes = 0; + path->uploaded.handle = NULL; + path->uploaded.memory = NULL; + + return VG_LITE_SUCCESS; + +ErrorHandler: + vg_lite_os_free(pathdata); + pathdata = NULL; + return error; +} + +vg_lite_error_t vg_lite_init_path(vg_lite_path_t * path, + vg_lite_format_t data_format, + vg_lite_quality_t quality, + uint32_t path_length, + void * path_data, + vg_lite_float_t min_x, vg_lite_float_t min_y, + vg_lite_float_t max_x, vg_lite_float_t max_y) +{ + if(path == NULL) + return VG_LITE_INVALID_ARGUMENT; + + memset(path, 0, sizeof(*path)); + path->format = data_format; + path->quality = quality; + path->bounding_box[0] = min_x; + path->bounding_box[1] = min_y; + path->bounding_box[2] = max_x; + path->bounding_box[3] = max_y; + + path->path_length = path_length; + path->path = path_data; + + path->path_changed = 1; + path->uploaded.address = 0; + path->uploaded.bytes = 0; + path->uploaded.handle = NULL; + path->uploaded.memory = NULL; + path->uploaded.property = 0; + path->pdata_internal = 0; + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_clear_path(vg_lite_path_t * path) +{ + vg_lite_error_t error; + if (path->uploaded.handle != NULL) + { + vg_lite_kernel_free_t free_cmd; + free_cmd.memory_handle = path->uploaded.handle; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &free_cmd)); + } + + path->uploaded.address = 0; + path->uploaded.bytes = 0; + path->uploaded.handle = NULL; + path->uploaded.memory = NULL; + + if(path->pdata_internal == 1 && path->path != NULL){ + vg_lite_os_free(path->path); + } + path->path = NULL; + + if(path->stroke_path_data) { + vg_lite_os_free(path->stroke_path_data); + path->stroke_path_data = NULL; + } + + if (path->stroke_conversion) { + if(path->stroke_conversion->path_point_list) { + vg_lite_path_point_ptr temp_point; + while(path->stroke_conversion->path_point_list) { + temp_point = path->stroke_conversion->path_point_list->next; + vg_lite_os_free(path->stroke_conversion->path_point_list); + path->stroke_conversion->path_point_list = temp_point; + } + temp_point = NULL; + } + + if(path->stroke_conversion->stroke_sub_path_list) { + vg_lite_sub_path_ptr temp_sub_path; + while(path->stroke_conversion->stroke_sub_path_list) { + temp_sub_path = path->stroke_conversion->stroke_sub_path_list->next; + if(path->stroke_conversion->stroke_sub_path_list->point_list) { + vg_lite_path_point_ptr temp_point; + while(path->stroke_conversion->stroke_sub_path_list->point_list) { + temp_point = path->stroke_conversion->stroke_sub_path_list->point_list->next; + vg_lite_os_free(path->stroke_conversion->stroke_sub_path_list->point_list); + path->stroke_conversion->stroke_sub_path_list->point_list = temp_point; + } + temp_point = NULL; + } + vg_lite_os_free(path->stroke_conversion->stroke_sub_path_list); + path->stroke_conversion->stroke_sub_path_list = temp_sub_path; + } + temp_sub_path = NULL; + } + + vg_lite_os_free(path->stroke_conversion); + path->stroke_conversion = NULL; + } + return VG_LITE_SUCCESS; +} + +#if defined(VG_DRIVER_SINGLE_THREAD) +vg_lite_error_t vg_lite_set_CLUT(uint32_t count, + uint32_t * colors) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + + uint32_t addr = 0x0B00; + + if(!s_context.s_ftable.ftable[gcFEATURE_BIT_VG_IM_INDEX_FORMAT]) + return VG_LITE_NOT_SUPPORT; + + switch (count) { + case 256: + addr = 0x0B00; + break; + + case 16: + addr = 0x0AA0; + break; + + case 4: + addr = 0x0A9C; + break; + + case 2: + addr = 0x0A98; + break; + + default: + error = VG_LITE_INVALID_ARGUMENT; + return error; + break; + } + + VG_LITE_RETURN_ERROR(push_states(&s_context, addr, count, colors)); + + return error; +} +#else +vg_lite_error_t vg_lite_set_CLUT(uint32_t count, + uint32_t * colors) +{ + vg_lite_tls_t* tls; + vg_lite_error_t error = VG_LITE_SUCCESS; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + if(!tls->t_context.s_ftable.ftable[gcFEATURE_BIT_VG_IM_INDEX_FORMAT]) + return VG_LITE_NOT_SUPPORT; + + switch (count) { + case 2: + tls->t_context.clut_dirty[0] = 1; + tls->t_context.clut_used[0] = 0; + if(!tls->t_context.colors[0]) + tls->t_context.colors[0] = (uint32_t *)malloc(count * sizeof(uint32_t)); + memcpy(tls->t_context.colors[0], colors, count * sizeof(uint32_t)); + break; + case 4: + tls->t_context.clut_dirty[1] = 1; + tls->t_context.clut_used[1] = 0; + if(!tls->t_context.colors[1]) + tls->t_context.colors[1] = (uint32_t *)malloc(count * sizeof(uint32_t)); + memcpy(tls->t_context.colors[1], colors, count * sizeof(uint32_t)); + break; + case 16: + tls->t_context.clut_dirty[2] = 1; + tls->t_context.clut_used[2] = 0; + if(!tls->t_context.colors[2]) + tls->t_context.colors[2] = (uint32_t *)malloc(count * sizeof(uint32_t)); + memcpy(tls->t_context.colors[2], colors, count * sizeof(uint32_t)); + break; + case 256: + tls->t_context.clut_dirty[3] = 1; + tls->t_context.clut_used[3] = 0; + if(!tls->t_context.colors[3]) + tls->t_context.colors[3] = (uint32_t *)malloc(count * sizeof(uint32_t)); + memcpy(tls->t_context.colors[3], colors, count * sizeof(uint32_t)); + break; + + default: + error = VG_LITE_INVALID_ARGUMENT; + return error; + break; + } + + return error; +} +#endif /* VG_DRIVER_SINGLE_THREAD */ + +vg_lite_error_t vg_lite_draw_pattern(vg_lite_buffer_t * target, + vg_lite_path_t * path, + vg_lite_fill_t fill_rule, + vg_lite_matrix_t * matrix0, + vg_lite_buffer_t * source, + vg_lite_matrix_t * matrix1, + vg_lite_blend_t blend, + vg_lite_pattern_mode_t pattern_mode, + vg_lite_color_t pattern_color, + vg_lite_filter_t filter) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint32_t imageMode; + uint32_t blend_mode; + uint32_t conversion = 0; + uint32_t tiled_source; + vg_lite_matrix_t * matrix = matrix1; + uint32_t pattern_tile = 0; + uint32_t transparency_mode = 0; + int32_t dst_align_width; + uint32_t mul, div, align; + +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t *tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + if(!path) + return VG_LITE_INVALID_ARGUMENT; + + if(!path->path_length) + return VG_LITE_SUCCESS; + + if(!path->path) + return VG_LITE_INVALID_ARGUMENT; + + /* The following code is from "draw path" */ + uint32_t format, quality, tiling, fill; + uint32_t tessellation_size; +#if DUMP_COMMAND + vg_lite_kernel_allocate_t memory; + uint32_t return_offset = 0; +#endif + vg_lite_point_t point_min = {0}, point_max = {0}, temp = {0}; + int x, y, width, height; + uint8_t ts_is_fullscreen = 0; + + if(!vg_lite_query_feature(gcFEATURE_BIT_VG_QUALITY_8X) && path->quality == VG_LITE_UPPER){ + return VG_LITE_NOT_SUPPORT; + } + + if(source->format == VG_LITE_A4 || source->format == VG_LITE_A8) { + return VG_LITE_NOT_SUPPORT; + } + + error = set_render_target(target); + if (error != VG_LITE_SUCCESS) { + return error; + } else if (error == VG_LITE_NO_CONTEXT) { + /* If scissoring is enabled and no valid scissoring rectangles + are present, no drawing occurs */ + return VG_LITE_SUCCESS; + } + + transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); + width = ctx->tsbuffer.tessellation_width_height & 0xFFFF; + height = ctx->tsbuffer.tessellation_width_height >> 16; + get_format_bytes(target->format, &mul, &div, &align); + dst_align_width = target->stride * div / mul; + + if(width == 0 || height == 0) + return VG_LITE_NO_CONTEXT; + if ((dst_align_width <= width) && (target->height <= height)) + { + ts_is_fullscreen = 1; + point_min.x = 0; + point_min.y = 0; + point_max.x = dst_align_width; + point_max.y = target->height; + } + + /* If target is L8 and source is in YUV or RGB (not L8 or A8) then we have to convert RGB into L8. */ + if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { + conversion = 0x80000000; + } + + /* Determine image mode (NORMAL or MULTIPLY) depending on the color. */ + imageMode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; + tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; + + if (pattern_mode == VG_LITE_PATTERN_COLOR) + { + uint8_t a,r,g,b; + pattern_tile = 0; + a = pattern_color >> 24; + r = pattern_color >> 16; + g = pattern_color >> 8; + b = pattern_color; + pattern_color = (a << 24) | (b << 16) | (g << 8) | r; + } + else if (pattern_mode == VG_LITE_PATTERN_PAD) + { + pattern_tile = 0x1000; + } + else + { + return VG_LITE_INVALID_ARGUMENT; + } + +#if !defined(VG_DRIVER_SINGLE_THREAD) + if(ctx->ts_dirty){ + memcpy(CMDBUF_BUFFER(*ctx) + CMDBUF_OFFSET(*ctx), ctx->ts_record, 80); + CMDBUF_OFFSET(*ctx) += 80; + ctx->ts_dirty = 0; + ctx->ts_init_used = 1; + } + else + { + ctx->ts_init_use = 1; + } + + /* Setup the command buffer. */ + if(source->format >= VG_LITE_INDEX_1 && source->format <= VG_LITE_INDEX_8) + { + /* this task will use index format,set index_flag to 1. */ + ctx->index_format = 1; + switch (source->format) { + case VG_LITE_INDEX_8: + if(ctx->clut_dirty[3]){ + VG_LITE_RETURN_ERROR(push_states(ctx, 0x0B00, 256, ctx->colors[3])); + ctx->clut_dirty[3] = 0; + } + else + { + ctx->clut_used[3] = 1; + } + break; + + case VG_LITE_INDEX_4: + if(ctx->clut_dirty[2]){ + VG_LITE_RETURN_ERROR(push_states(ctx, 0x0AA0, 16, ctx->colors[2])); + ctx->clut_dirty[2] = 0; + } + else + { + ctx->clut_used[2] = 1; + } + break; + + case VG_LITE_INDEX_2: + if(ctx->clut_dirty[1]){ + VG_LITE_RETURN_ERROR(push_states(ctx, 0x0A9C, 4, ctx->colors[1])); + ctx->clut_dirty[1] = 0; + } + else + { + ctx->clut_used[1] = 1; + } + break; + + default: + if(ctx->clut_dirty[0]){ + VG_LITE_RETURN_ERROR(push_states(ctx, 0x0A98, 2, ctx->colors[0])); + ctx->clut_dirty[0] = 0; + } + else + { + ctx->clut_used[0] = 1; + } + } + } +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + + VG_LITE_RETURN_ERROR(set_interpolation_steps(target, source->width, source->height, matrix)); + + if(!ctx->premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { + if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A25, convert_source_format(source->format) | + filter | pattern_tile | conversion | 0x01000100)); + } else { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A25, convert_source_format(source->format) | + filter | pattern_tile | conversion | 0x00000100)); + } + } else { + /* enable pre-multiplied in imager unit */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A25, convert_source_format(source->format) | + filter | pattern_tile | conversion)); + } + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A27, pattern_color)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A29, source->address)); + + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2B, source->stride | tiled_source)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2D, 0)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2F, source->width | (source->height << 16))); + + /* Work on path states. */ + matrix = matrix0; + + if (ts_is_fullscreen == 0){ + transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[1], matrix); + point_min = point_max = temp; + + transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[1], matrix); + if (temp.x < point_min.x) point_min.x = temp.x; + if (temp.y < point_min.y) point_min.y = temp.y; + if (temp.x > point_max.x) point_max.x = temp.x; + if (temp.y > point_max.y) point_max.y = temp.y; + + transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[3], matrix); + if (temp.x < point_min.x) point_min.x = temp.x; + if (temp.y < point_min.y) point_min.y = temp.y; + if (temp.x > point_max.x) point_max.x = temp.x; + if (temp.y > point_max.y) point_max.y = temp.y; + + transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[3], matrix); + if (temp.x < point_min.x) point_min.x = temp.x; + if (temp.y < point_min.y) point_min.y = temp.y; + if (temp.x > point_max.x) point_max.x = temp.x; + if (temp.y > point_max.y) point_max.y = temp.y; + + point_min.x = MAX(point_min.x, 0); + point_min.y = MAX(point_min.y, 0); + point_max.x = MIN(point_max.x, dst_align_width); + point_max.y = MIN(point_max.y, target->height); + } + + if (ctx->scissor_enabled) { + point_min.x = MAX(point_min.x, ctx->scissor[0]); + point_min.y = MAX(point_min.y, ctx->scissor[1]); + point_max.x = MIN(point_max.x, ctx->scissor[0] + ctx->scissor[2]); + point_max.y = MIN(point_max.y, ctx->scissor[1] + ctx->scissor[3]); + } + + /* Convert states into hardware values. */ + blend_mode = convert_blend(blend); + format = convert_path_format(path->format); + quality = convert_path_quality(path->quality); + tiling = (ctx->capabilities.cap.tiled == 2) ? 0x2000000 : 0; + fill = (fill_rule == VG_LITE_FILL_EVEN_ODD) ? 0x10 : 0; + tessellation_size = ( ctx->tsbuffer.tessellation_buffer_size[2] + ? ctx->tsbuffer.tessellation_buffer_size[2] + : ctx->tsbuffer.tessellation_buffer_size[1] + ); + + /* Setup the command buffer. */ + /* Program color register. */ + if(!ctx->premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, 0x10000000 | ctx->capabilities.cap.tiled | 0x00000002 | imageMode | blend_mode | transparency_mode)); + } else { + /* enable pre-multiplied from VG to VGPE */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, ctx->capabilities.cap.tiled | 0x00000002 | imageMode | blend_mode | transparency_mode)); + } + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A34, 0x01000400 | format | quality | tiling | fill)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3B, 0x3F800000)); /* Path tessellation SCALE. */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3C, 0x00000000)); /* Path tessellation BIAS. */ + /* Program matrix. */ + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A40, (void *) &matrix->m[0][0])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A41, (void *) &matrix->m[0][1])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A42, (void *) &matrix->m[0][2])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A43, (void *) &matrix->m[1][0])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A44, (void *) &matrix->m[1][1])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A45, (void *) &matrix->m[1][2])); + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { + + vglitemDUMP_BUFFER("path", path->uploaded.address, (uint8_t *)(path->uploaded.memory), 0, path->uploaded.bytes); + } + + vglitemDUMP("@[memory 0x%08X 0x%08X]", ctx->tsbuffer.tessellation_buffer_gpu[0], ctx->tsbuffer.tessellation_buffer_size[0]); + + /* Setup tessellation loop. */ + if((path->path_type & 0x1) == VG_LITE_DRAW_FILL_PATH) { + for (y = point_min.y; y < point_max.y; y += height) { + for (x = point_min.x; x < point_max.x; x += width) { + /* Tessellate path. */ + VG_LITE_RETURN_ERROR(push_stall(ctx, 15)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A1B, 0x00011000)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A01, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A39, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3D, tessellation_size / 64)); + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { + VG_LITE_RETURN_ERROR(push_call(ctx, path->uploaded.address, path->uploaded.bytes)); +#if (DUMP_COMMAND) + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[0], 0); + + unsigned char* pt = (unsigned char*) memory.memory; + + for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) + { + if (i % 8 == 0) + fprintf(fp, "Command buffer: "); + + if (i % 4 == 0) + fprintf(fp, "0x"); + + for (int j = 3; j >= 0; --j) + fprintf(fp, "%02x", pt[i + j]); + + if ((i / 4 + 1) % 2 == 0) + fprintf(fp, ",\n"); + else + fprintf(fp, ", "); + } + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[return_offset], 0); + + fclose(fp); + fp = NULL; +#endif + } else { + push_data(ctx, path->path_length, path->path); + } + } + } + } + /* Setup tessellation loop. */ + if(path->path_type == VG_LITE_DRAW_STROKE_PATH || path->path_type == VG_LITE_DRAW_FILL_STROKE_PATH) { + for (y = point_min.y; y < point_max.y; y += height) { + for (x = point_min.x; x < point_max.x; x += width) { + /* Tessellate path. */ + VG_LITE_RETURN_ERROR(push_stall(ctx, 15)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A1B, 0x00011000)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A01, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A39, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3D, tessellation_size / 64)); + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { + VG_LITE_RETURN_ERROR(push_call(ctx, path->uploaded.address, path->uploaded.bytes)); +#if (DUMP_COMMAND) + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[0], 0); + + unsigned char* pt = (unsigned char*) memory.memory; + + for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) + { + if (i % 8 == 0) + fprintf(fp, "Command buffer: "); + + if (i % 4 == 0) + fprintf(fp, "0x"); + + for (int j = 3; j >= 0; --j) + fprintf(fp, "%02x", pt[i + j]); + + if ((i / 4 + 1) % 2 == 0) + fprintf(fp, ",\n"); + else + fprintf(fp, ", "); + } + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[return_offset], 0); + + fclose(fp); + fp = NULL; +#endif + } else { + format = convert_path_format(VG_LITE_FP32); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A34, 0x01000200 | format | quality | tiling | 0x0)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A02, path->stroke_color)); + push_data(ctx, path->stroke_path_size, path->stroke_path_data); + } + } + } + } + + /* Finialize command buffer. */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A34, 0)); + VG_LITE_RETURN_ERROR(flush_target()); + + vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); +#if DUMP_IMAGE + dump_img(source->memory, source->width, source->height, source->format); +#endif + +#if !defined(VG_DRIVER_SINGLE_THREAD) + tls->t_context.ts_init = 1; +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + return error; +} + +vg_lite_error_t vg_lite_draw_linear_gradient(vg_lite_buffer_t * target, + vg_lite_path_t * path, + vg_lite_fill_t fill_rule, + vg_lite_matrix_t * path_matrix, + vg_lite_linear_gradient_ext_t *grad, + vg_lite_color_t paint_color, + vg_lite_blend_t blend, + vg_lite_filter_t filter) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint32_t image_mode; + uint32_t blend_mode; + uint32_t conversion = 0; + uint32_t tiled_source; + int32_t dst_align_width; + uint32_t mul, div, align; + vg_lite_matrix_t inverse_matrix; + vg_lite_buffer_t * source = &grad->image; + vg_lite_matrix_t * matrix = &grad->matrix; + uint32_t linear_tile = 0; + uint32_t transparency_mode = 0; + void *data; + + /* The following code is from "draw path" */ + uint32_t format, quality, tiling, fill; + uint32_t tessellation_size; + + vg_lite_kernel_allocate_t memory; + vg_lite_kernel_free_t free_memory; + uint32_t return_offset = 0; + + vg_lite_point_t point_min = {0}, point_max = {0}, temp = {0}; + int x, y, width, height; + uint8_t ts_is_fullscreen = 0; + + vg_lite_float_t dx, dy, dxdx_dydy; + vg_lite_float_t lg_step_x_lin, lg_step_y_lin, lg_constant_lin; + +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if (tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + if(!path) + return VG_LITE_INVALID_ARGUMENT; + + if(!path->path_length) + return VG_LITE_SUCCESS; + + if(!path->path) + return VG_LITE_INVALID_ARGUMENT; + + if(!vg_lite_query_feature(gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT)) + return VG_LITE_NOT_SUPPORT; + + if(!vg_lite_query_feature(gcFEATURE_BIT_VG_QUALITY_8X) && path->quality == VG_LITE_UPPER){ + return VG_LITE_NOT_SUPPORT; + } + + if(source->format == VG_LITE_A4 || source->format == VG_LITE_A8) { + return VG_LITE_NOT_SUPPORT; + } + + error = set_render_target(target); + if (error != VG_LITE_SUCCESS) { + return error; + } else if (error == VG_LITE_NO_CONTEXT) { + /* If scissoring is enabled and no valid scissoring rectangles + are present, no drawing occurs */ + return VG_LITE_SUCCESS; + } + + transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); + width = ctx->tsbuffer.tessellation_width_height & 0xFFFF; + height = ctx->tsbuffer.tessellation_width_height >> 16; + get_format_bytes(target->format, &mul, &div, &align); + dst_align_width = target->stride * div / mul; + if(width == 0 || height == 0) + return VG_LITE_NO_CONTEXT; + if ((dst_align_width <= width) && (target->height <= height)) + { + ts_is_fullscreen = 1; + point_min.x = 0; + point_min.y = 0; + point_max.x = dst_align_width; + point_max.y = target->height; + } + + /* If target is L8 and source is in YUV or RGB (not L8 or A8) then we have to convert RGB into L8. */ + if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { + conversion = 0x80000000; + } + + /* Determine image mode (NORMAL or MULTIPLY) depending on the color. */ + image_mode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; + tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; + + linear_tile = (grad->spread_mode == VG_LITE_RADIAL_GRADIENT_SPREAD_FILL) ? 0 : + (grad->spread_mode == VG_LITE_RADIAL_GRADIENT_SPREAD_PAD) ? 0x1000 : + (grad->spread_mode == VG_LITE_RADIAL_GRADIENT_SPREAD_REPEAT) ? 0x2000 : 0x3000; + + if (grad->spread_mode == VG_LITE_RADIAL_GRADIENT_SPREAD_FILL) + { + uint8_t a,r,g,b; + a = paint_color >> 24; + r = paint_color >> 16; + g = paint_color >> 8; + b = paint_color; + paint_color = (a << 24) | (b << 16) | (g << 8) | r; + } + + /* compute radial gradient paremeters */ + + if (!inverse(&inverse_matrix, matrix)) + return VG_LITE_INVALID_ARGUMENT; + + dx = grad->linear_gradient.X1 - grad->linear_gradient.X0; + dy = grad->linear_gradient.Y1 - grad->linear_gradient.Y0; + dxdx_dydy = dx * dx + dy * dy; + + /* + ** dx (T(x) - x0) + dy (T(y) - y0) + ** g = ------------------------------- + ** dx^2 + dy^2 + ** + ** where + ** + ** dx := x1 - x0 + ** dy := y1 - y1 + ** T(x) := (x + 0.5) m00 + (y + 0.5) m01 + m02 + ** = x m00 + y m01 + 0.5 (m00 + m01) + m02 + ** T(y) := (x + 0.5) m10 + (y + 0.5) m11 + m12 + ** = x m10 + y m11 + 0.5 (m10 + m11) + m12. + ** + ** We can factor the top line into: + ** + ** = dx (x m00 + y m01 + 0.5 (m00 + m01) + m02 - x0) + ** + dy (x m10 + y m11 + 0.5 (m10 + m11) + m12 - y0) + ** + ** = x (dx m00 + dy m10) + ** + y (dx m01 + dy m11) + ** + dx (0.5 (m00 + m01) + m02 - x0) + ** + dy (0.5 (m10 + m11) + m12 - y0). + */ + + lg_step_x_lin + = (dx * MAT(&inverse_matrix, 0, 0) + dy * MAT(&inverse_matrix, 1, 0)) + / dxdx_dydy; + + lg_step_y_lin + = (dx * MAT(&inverse_matrix, 0, 1) + dy * MAT(&inverse_matrix, 1, 1)) + / dxdx_dydy; + + lg_constant_lin = + ( + ( + 0.5f * ( MAT(&inverse_matrix, 0, 0) + MAT(&inverse_matrix, 0, 1) ) + + MAT(&inverse_matrix, 0, 2) - grad->linear_gradient.X0 + ) * dx + + + + + ( + 0.5f * ( MAT(&inverse_matrix, 1, 0) + MAT(&inverse_matrix, 1, 1) ) + + MAT(&inverse_matrix, 1, 2) - grad->linear_gradient.Y0 + ) * dy + ) + / dxdx_dydy; + +#if !defined(VG_DRIVER_SINGLE_THREAD) + if(ctx->ts_dirty){ + memcpy(CMDBUF_BUFFER(*ctx) + CMDBUF_OFFSET(*ctx), ctx->ts_record, 80); + CMDBUF_OFFSET(*ctx) += 80; + ctx->ts_dirty = 0; + ctx->ts_init_used = 1; + } + else + { + ctx->ts_init_use = 1; + } +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + + /* Setup the command buffer. */ + + /* linear gradient parameters*/ + data = &lg_constant_lin; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A04,*(uint32_t*) data)); + data = &lg_step_x_lin; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A06,*(uint32_t*) data)); + data = &lg_step_y_lin; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A08,*(uint32_t*) data)); + + VG_LITE_RETURN_ERROR(set_interpolation_steps(target, source->width, source->height, matrix)); + + if(!ctx->premultiply_enabled) { + if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A24, convert_source_format(source->format) | + filter | linear_tile | conversion | 0x01000100)); + } else { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A24, convert_source_format(source->format) | + filter | linear_tile | conversion | 0x00000100)); + } + } else { + /* enable pre-multiplied in imager unit */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A24, convert_source_format(source->format) | + filter | linear_tile | conversion)); + } + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A26, paint_color)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A28, source->address)); + + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2A, tiled_source)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2C, 0)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2E, source->width)); + + /* Work on path states. */ + matrix = path_matrix; + + if (ts_is_fullscreen == 0){ + transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[1], matrix); + point_min = point_max = temp; + + transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[1], matrix); + if (temp.x < point_min.x) point_min.x = temp.x; + if (temp.y < point_min.y) point_min.y = temp.y; + if (temp.x > point_max.x) point_max.x = temp.x; + if (temp.y > point_max.y) point_max.y = temp.y; + + transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[3], matrix); + if (temp.x < point_min.x) point_min.x = temp.x; + if (temp.y < point_min.y) point_min.y = temp.y; + if (temp.x > point_max.x) point_max.x = temp.x; + if (temp.y > point_max.y) point_max.y = temp.y; + + transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[3], matrix); + if (temp.x < point_min.x) point_min.x = temp.x; + if (temp.y < point_min.y) point_min.y = temp.y; + if (temp.x > point_max.x) point_max.x = temp.x; + if (temp.y > point_max.y) point_max.y = temp.y; + + point_min.x = MAX(point_min.x, 0); + point_min.y = MAX(point_min.y, 0); + point_max.x = MIN(point_max.x, dst_align_width); + point_max.y = MIN(point_max.y, target->height); + } + + if (ctx->scissor_enabled) { + point_min.x = MAX(point_min.x, ctx->scissor[0]); + point_min.y = MAX(point_min.y, ctx->scissor[1]); + point_max.x = MIN(point_max.x, ctx->scissor[0] + ctx->scissor[2]); + point_max.y = MIN(point_max.y, ctx->scissor[1] + ctx->scissor[3]); + } + + /* Convert states into hardware values. */ + blend_mode = convert_blend(blend); + format = convert_path_format(path->format); + quality = convert_path_quality(path->quality); + tiling = (ctx->capabilities.cap.tiled == 2) ? 0x2000000 : 0; + fill = (fill_rule == VG_LITE_FILL_EVEN_ODD) ? 0x10 : 0; + tessellation_size = ( ctx->tsbuffer.tessellation_buffer_size[2] + ? ctx->tsbuffer.tessellation_buffer_size[2] + : ctx->tsbuffer.tessellation_buffer_size[1] + ); + + /* Setup the command buffer. */ + /* Program color register. */ + if(!ctx->premultiply_enabled) { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, 0x11000000 | ctx->capabilities.cap.tiled | 0x00000002 | image_mode | blend_mode | transparency_mode)); + } else { + /* enable pre-multiplied from VG to VGPE */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, 0x01000000 | ctx->capabilities.cap.tiled | 0x00000002 | image_mode | blend_mode | transparency_mode)); + } + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A34, 0x01000400 | format | quality | tiling | fill)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3B, 0x3F800000)); /* Path tessellation SCALE. */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3C, 0x00000000)); /* Path tessellation BIAS. */ + /* Program matrix. */ + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A40, (void *) &matrix->m[0][0])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A41, (void *) &matrix->m[0][1])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A42, (void *) &matrix->m[0][2])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A43, (void *) &matrix->m[1][0])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A44, (void *) &matrix->m[1][1])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A45, (void *) &matrix->m[1][2])); + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) + { + if (path->path_changed != 0) { + if (path->uploaded.handle != NULL) { + free_memory.memory_handle = path->uploaded.handle; + vg_lite_kernel(VG_LITE_FREE, &free_memory); + path->uploaded.address = 0; + path->uploaded.memory = NULL; + path->uploaded.handle = NULL; + } + /* Allocate memory for the path data. */ + memory.bytes = 16 + VG_LITE_ALIGN(path->path_length, 8); + return_offset = (8 + VG_LITE_ALIGN(path->path_length, 8)) / 4; + memory.contiguous = 1; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &memory)); + ((uint64_t *) memory.memory)[(path->path_length + 7) / 8] = 0; + ((uint32_t *) memory.memory)[0] = VG_LITE_DATA((path->path_length + 7) / 8); + ((uint32_t *) memory.memory)[1] = 0; + memcpy((uint8_t *) memory.memory + 8, path->path, path->path_length); + ((uint32_t *) memory.memory)[return_offset] = VG_LITE_RETURN(); + ((uint32_t *) memory.memory)[return_offset + 1] = 0; + + path->uploaded.handle = memory.memory_handle; + path->uploaded.memory = memory.memory; + path->uploaded.address = memory.memory_gpu; + path->uploaded.bytes = memory.bytes; + path->path_changed = 0; + } + } + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { + + vglitemDUMP_BUFFER("path", path->uploaded.address, (uint8_t *)(path->uploaded.memory), 0, path->uploaded.bytes); + } + + vglitemDUMP("@[memory 0x%08X 0x%08X]", ctx->tsbuffer.tessellation_buffer_gpu[0], ctx->tsbuffer.tessellation_buffer_size[0]); + + /* Setup tessellation loop. */ + if((path->path_type & 0x1) == VG_LITE_DRAW_FILL_PATH) { + for (y = point_min.y; y < point_max.y; y += height) { + for (x = point_min.x; x < point_max.x; x += width) { + /* Tessellate path. */ + VG_LITE_RETURN_ERROR(push_stall(ctx, 15)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A1B, 0x00011000)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A01, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A39, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3D, tessellation_size / 64)); + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { + VG_LITE_RETURN_ERROR(push_call(ctx, path->uploaded.address, path->uploaded.bytes)); +#if (DUMP_COMMAND) + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[0], 0); + + unsigned char* pt = (unsigned char*) memory.memory; + + for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) + { + if (i % 8 == 0) + fprintf(fp, "Command buffer: "); + + if (i % 4 == 0) + fprintf(fp, "0x"); + + for (int j = 3; j >= 0; --j) + fprintf(fp, "%02x", pt[i + j]); + + if ((i / 4 + 1) % 2 == 0) + fprintf(fp, ",\n"); + else + fprintf(fp, ", "); + } + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[return_offset], 0); + + fclose(fp); + fp = NULL; +#endif + } else { + push_data(ctx, path->path_length, path->path); + } + } + } + } + /* Setup tessellation loop. */ + if(path->path_type == VG_LITE_DRAW_STROKE_PATH || path->path_type == VG_LITE_DRAW_FILL_STROKE_PATH) { + for (y = point_min.y; y < point_max.y; y += height) { + for (x = point_min.x; x < point_max.x; x += width) { + /* Tessellate path. */ + VG_LITE_RETURN_ERROR(push_stall(ctx, 15)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A1B, 0x00011000)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A01, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A39, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3D, tessellation_size / 64)); + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { + VG_LITE_RETURN_ERROR(push_call(ctx, path->uploaded.address, path->uploaded.bytes)); +#if (DUMP_COMMAND) + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[0], 0); + + unsigned char* pt = (unsigned char*) memory.memory; + + for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) + { + if (i % 8 == 0) + fprintf(fp, "Command buffer: "); + + if (i % 4 == 0) + fprintf(fp, "0x"); + + for (int j = 3; j >= 0; --j) + fprintf(fp, "%02x", pt[i + j]); + + if ((i / 4 + 1) % 2 == 0) + fprintf(fp, ",\n"); + else + fprintf(fp, ", "); + } + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[return_offset], 0); + + fclose(fp); + fp = NULL; +#endif + } else { + format = convert_path_format(VG_LITE_FP32); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A34, 0x01000200 | format | quality | tiling | 0x0)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A02, path->stroke_color)); + push_data(ctx, path->stroke_path_size, path->stroke_path_data); + } + } + } + } + + /* Finialize command buffer. */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A34, 0)); + + vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); +#if DUMP_IMAGE + dump_img(source->memory, source->width, source->height, source->format); +#endif + +#if !defined(VG_DRIVER_SINGLE_THREAD) + tls->t_context.ts_init = 1; +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + return error; +} + +vg_lite_error_t vg_lite_draw_radial_gradient(vg_lite_buffer_t * target, + vg_lite_path_t * path, + vg_lite_fill_t fill_rule, + vg_lite_matrix_t * path_matrix, + vg_lite_radial_gradient_t *grad, + vg_lite_color_t paint_color, + vg_lite_blend_t blend, + vg_lite_filter_t filter) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint32_t imageMode; + uint32_t blend_mode; + uint32_t conversion = 0; + uint32_t tiled_source; + int32_t dst_align_width; + uint32_t mul, div, align; + vg_lite_matrix_t inverse_matrix; + vg_lite_buffer_t * source = &grad->image; + vg_lite_matrix_t * matrix = &grad->matrix; + uint32_t rad_tile = 0; + uint32_t transparency_mode = 0; + void *data; + + /* The following code is from "draw path" */ + uint32_t format, quality, tiling, fill; + uint32_t tessellation_size; + + vg_lite_kernel_allocate_t memory; + vg_lite_kernel_free_t free_memory; + uint32_t return_offset = 0; + + vg_lite_point_t point_min = {0}, point_max = {0}, temp = {0}; + int x, y, width, height; + uint8_t ts_is_fullscreen = 0; + + vg_lite_float_t radius; + + vg_lite_float_t centerX, centerY; + vg_lite_float_t focalX, focalY; + vg_lite_float_t fx, fy; + vg_lite_float_t fxfy_2; + vg_lite_float_t radius2; + vg_lite_float_t r2_fx2, r2_fy2; + vg_lite_float_t r2_fx2_2, r2_fy2_2; + vg_lite_float_t r2_fx2_fy2; + vg_lite_float_t r2_fx2_fy2sq; + vg_lite_float_t cx, cy; + + vg_lite_float_t rgConstantLin, rgStepXLin, rgStepYLin; + vg_lite_float_t rgConstantRad, rgStepXRad, rgStepYRad; + vg_lite_float_t rgStepXXRad, rgStepYYRad, rgStepXYRad; + +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + if(!path) + return VG_LITE_INVALID_ARGUMENT; + + if(!path->path_length) + return VG_LITE_SUCCESS; + + if(!path->path) + return VG_LITE_INVALID_ARGUMENT; + + if(!vg_lite_query_feature(gcFEATURE_BIT_VG_RADIAL_GRADIENT)) + return VG_LITE_NOT_SUPPORT; + + if(!vg_lite_query_feature(gcFEATURE_BIT_VG_QUALITY_8X) && path->quality == VG_LITE_UPPER){ + return VG_LITE_NOT_SUPPORT; + } + + if(source->format == VG_LITE_A4 || source->format == VG_LITE_A8) { + return VG_LITE_NOT_SUPPORT; + } + + radius = grad->radialGradient.r; + if(radius <= 0) + return VG_LITE_INVALID_ARGUMENT; + + error = set_render_target(target); + if (error != VG_LITE_SUCCESS) { + return error; + } else if (error == VG_LITE_NO_CONTEXT) { + /* If scissoring is enabled and no valid scissoring rectangles + are present, no drawing occurs */ + return VG_LITE_SUCCESS; + } + + transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); + width = ctx->tsbuffer.tessellation_width_height & 0xFFFF; + height = ctx->tsbuffer.tessellation_width_height >> 16; + get_format_bytes(target->format, &mul, &div, &align); + dst_align_width = target->stride * div / mul; + if(width == 0 || height == 0) + return VG_LITE_NO_CONTEXT; + if ((dst_align_width <= width) && (target->height <= height)) + { + ts_is_fullscreen = 1; + point_min.x = 0; + point_min.y = 0; + point_max.x = dst_align_width; + point_max.y = target->height; + } + + /* If target is L8 and source is in YUV or RGB (not L8 or A8) then we have to convert RGB into L8. */ + if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { + conversion = 0x80000000; + } + + /* Determine image mode (NORMAL or MULTIPLY) depending on the color. */ + imageMode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; + tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; + + rad_tile = (grad->SpreadMode == VG_LITE_RADIAL_GRADIENT_SPREAD_FILL) ? 0 : + (grad->SpreadMode == VG_LITE_RADIAL_GRADIENT_SPREAD_PAD) ? 0x1000 : + (grad->SpreadMode == VG_LITE_RADIAL_GRADIENT_SPREAD_REPEAT) ? 0x2000 : 0x3000; + + if (grad->SpreadMode == VG_LITE_RADIAL_GRADIENT_SPREAD_FILL) + { + uint8_t a,r,g,b; + a = paint_color >> 24; + r = paint_color >> 16; + g = paint_color >> 8; + b = paint_color; + paint_color = (a << 24) | (b << 16) | (g << 8) | r; + } + + /* compute radial gradient paremeters */ + + /* Compute inverse matrix. */ + if (!inverse(&inverse_matrix, matrix)) + return VG_LITE_INVALID_ARGUMENT; + + /* Make shortcuts to the gradient information. */ + centerX = grad->radialGradient.cx; + centerY = grad->radialGradient.cy; + focalX = grad->radialGradient.fx; + focalY = grad->radialGradient.fy; + + /* Compute constants of the equation. */ + fx = focalX - centerX; + fy = focalY - centerY; + radius2 = radius * radius; + if (fx*fx + fy*fy > radius2) + { + /* If the focal point is outside the circle, let's move it + to inside the circle. Per vg11 spec pg125 "If (fx, fy) lies outside ... + For here, we set it at 0.9 ratio to the center. + */ + vg_lite_float_t fr = (vg_lite_float_t)sqrt(fx*fx + fy*fy); + fx = radius * fx / fr * 0.9f; + fy = radius * fy / fr * 0.9f; + focalX = grad->radialGradient.fx + fx; + focalY = grad->radialGradient.fy + fy; + } + + fxfy_2 = 2.0f * fx * fy; + r2_fx2 = radius2 - fx * fx; + r2_fy2 = radius2 - fy * fy; + r2_fx2_2 = 2.0f * r2_fx2; + r2_fy2_2 = 2.0f * r2_fy2; + r2_fx2_fy2 = r2_fx2 - fy * fy; + r2_fx2_fy2sq = r2_fx2_fy2 * r2_fx2_fy2; + + /* _____________________________________ + ** dx fx + dy fy + \/r^2 (dx^2 + dy^2) - (dx fy - dy fx)^2 + ** g = ------------------------------------------------------- + ** r^2 - fx^2 - fy^2 + ** + ** Where + ** + ** dx := F(x) - focalX + ** dy := F(y) - focalY + ** fx := focalX - centerX + ** fy := focalX - centerY + ** + ** and + ** + ** F(x) := (x + 0.5) m00 + (y + 0.5) m01 + m02 + ** F(y) := (x + 0.5) m10 + (y + 0.5) m11 + m12 + ** + ** So, dx can be factored into + ** + ** dx = (x + 0.5) m00 + (y + 0.5) m01 + m02 - focalX + ** = x m00 + y m01 + 0.5 m00 + 0.5 m01 + m02 - focalX + ** + ** = x m00 + y m01 + cx + ** + ** where + ** + ** cx := 0.5 m00 + 0.5 m01 + m02 - focalX + ** + ** The same way we can factor dy into + ** + ** dy = x m10 + y m11 + cy + ** + ** where + ** + ** cy := 0.5 m10 + 0.5 m11 + m12 - focalY. + ** + ** Now we can rewrite g as + ** ______________________________________ + ** dx fx + dy fy / r^2 (dx^2 + dy^2) - (dx fy - dy fx)^2 + ** g = ----------------- + \ / ------------------------------------- + ** r^2 - fx^2 - fy^2 \/ (r^2 - fx^2 - fy^2)^2 + ** ____ + ** = gLin + \/gRad + ** + ** where + ** + ** dx fx + dy fy + ** gLin := ----------------- + ** r^2 - fx^2 - fy^2 + ** + ** r^2 (dx^2 + dy^2) - (dx fy - dy fx)^2 + ** gRad := ------------------------------------- + ** (r^2 - fx^2 - fy^2)^2 + */ + + cx + = 0.5f * ( MAT(&inverse_matrix, 0, 0) + MAT(&inverse_matrix, 0, 1) ) + + MAT(&inverse_matrix, 0, 2) + - focalX; + + cy + = 0.5f * ( MAT(&inverse_matrix, 1, 0) + MAT(&inverse_matrix, 1, 1) ) + + MAT(&inverse_matrix, 1, 2) + - focalY; + + /* + ** dx fx + dy fy + ** gLin := ----------------- + ** r^2 - fx^2 - fy^2 + ** + ** We can factor the top half into + ** + ** = (x m00 + y m01 + cx) fx + (x m10 + y m11 + cy) fy + ** + ** = x (m00 fx + m10 fy) + ** + y (m01 fx + m11 fy) + ** + cx fx + cy fy. + */ + + rgStepXLin + = ( MAT(&inverse_matrix, 0, 0) * fx + MAT(&inverse_matrix, 1, 0) * fy ) + / r2_fx2_fy2; + + rgStepYLin + = ( MAT(&inverse_matrix, 0, 1) * fx + MAT(&inverse_matrix, 1, 1) * fy ) + / r2_fx2_fy2; + + rgConstantLin = ( cx * fx + cy * fy ) / r2_fx2_fy2; + + /* + ** r^2 (dx^2 + dy^2) - (dx fy - dy fx)^2 + ** gRad := ------------------------------------- + ** (r^2 - fx^2 - fy^2)^2 + ** + ** r^2 (dx^2 + dy^2) - dx^2 fy^2 - dy^2 fx^2 + 2 dx dy fx fy + ** := --------------------------------------------------------- + ** (r^2 - fx^2 - fy^2)^2 + ** + ** dx^2 (r^2 - fy^2) + dy^2 (r^2 - fx^2) + 2 dx dy fx fy + ** := ----------------------------------------------------- + ** (r^2 - fx^2 - fy^2)^2 + ** + ** First, lets factor dx^2 into + ** + ** dx^2 = (x m00 + y m01 + cx)^2 + ** = x^2 m00^2 + y^2 m01^2 + 2 x y m00 m01 + ** + 2 x m00 cx + 2 y m01 cx + cx^2 + ** + ** = x^2 (m00^2) + ** + y^2 (m01^2) + ** + x y (2 m00 m01) + ** + x (2 m00 cx) + ** + y (2 m01 cx) + ** + cx^2. + ** + ** The same can be done for dy^2: + ** + ** dy^2 = x^2 (m10^2) + ** + y^2 (m11^2) + ** + x y (2 m10 m11) + ** + x (2 m10 cy) + ** + y (2 m11 cy) + ** + cy^2. + ** + ** Let's also factor dx dy into + ** + ** dx dy = (x m00 + y m01 + cx) (x m10 + y m11 + cy) + ** = x^2 m00 m10 + y^2 m01 m11 + x y m00 m11 + x y m01 m10 + ** + x m00 cy + x m10 cx + y m01 cy + y m11 cx + cx cy + ** + ** = x^2 (m00 m10) + ** + y^2 (m01 m11) + ** + x y (m00 m11 + m01 m10) + ** + x (m00 cy + m10 cx) + ** + y (m01 cy + m11 cx) + ** + cx cy. + ** + ** Now that we have all this, lets look at the top of gRad. + ** + ** = dx^2 (r^2 - fy^2) + dy^2 (r^2 - fx^2) + 2 dx dy fx fy + ** = x^2 m00^2 (r^2 - fy^2) + y^2 m01^2 (r^2 - fy^2) + ** + x y 2 m00 m01 (r^2 - fy^2) + x 2 m00 cx (r^2 - fy^2) + ** + y 2 m01 cx (r^2 - fy^2) + cx^2 (r^2 - fy^2) + ** + x^2 m10^2 (r^2 - fx^2) + y^2 m11^2 (r^2 - fx^2) + ** + x y 2 m10 m11 (r^2 - fx^2) + x 2 m10 cy (r^2 - fx^2) + ** + y 2 m11 cy (r^2 - fx^2) + cy^2 (r^2 - fx^2) + ** + x^2 m00 m10 2 fx fy + y^2 m01 m11 2 fx fy + ** + x y (m00 m11 + m01 m10) 2 fx fy + ** + x (m00 cy + m10 cx) 2 fx fy + y (m01 cy + m11 cx) 2 fx fy + ** + cx cy 2 fx fy + ** + ** = x^2 ( m00^2 (r^2 - fy^2) + ** + m10^2 (r^2 - fx^2) + ** + m00 m10 2 fx fy + ** ) + ** + y^2 ( m01^2 (r^2 - fy^2) + ** + m11^2 (r^2 - fx^2) + ** + m01 m11 2 fx fy + ** ) + ** + x y ( 2 m00 m01 (r^2 - fy^2) + ** + 2 m10 m11 (r^2 - fx^2) + ** + (m00 m11 + m01 m10) 2 fx fy + ** ) + ** + x ( 2 m00 cx (r^2 - fy^2) + ** + 2 m10 cy (r^2 - fx^2) + ** + (m00 cy + m10 cx) 2 fx fy + ** ) + ** + y ( 2 m01 cx (r^2 - fy^2) + ** + 2 m11 cy (r^2 - fx^2) + ** + (m01 cy + m11 cx) 2 fx fy + ** ) + ** + cx^2 (r^2 - fy^2) + cy^2 (r^2 - fx^2) + cx cy 2 fx fy. + */ + + rgStepXXRad = + ( + MAT(&inverse_matrix, 0, 0) * MAT(&inverse_matrix, 0, 0) * r2_fy2 + + MAT(&inverse_matrix, 1, 0) * MAT(&inverse_matrix, 1, 0) * r2_fx2 + + MAT(&inverse_matrix, 0, 0) * MAT(&inverse_matrix, 1, 0) * fxfy_2 + ) + / r2_fx2_fy2sq; + + rgStepYYRad = + ( + MAT(&inverse_matrix, 0, 1) * MAT(&inverse_matrix, 0, 1) * r2_fy2 + + MAT(&inverse_matrix, 1, 1) * MAT(&inverse_matrix, 1, 1) * r2_fx2 + + MAT(&inverse_matrix, 0, 1) * MAT(&inverse_matrix, 1, 1) * fxfy_2 + ) + / r2_fx2_fy2sq; + + rgStepXYRad = + ( + MAT(&inverse_matrix, 0, 0) * MAT(&inverse_matrix, 0, 1) * r2_fy2_2 + + MAT(&inverse_matrix, 1, 0) * MAT(&inverse_matrix, 1, 1) * r2_fx2_2 + + ( + MAT(&inverse_matrix, 0, 0) * MAT(&inverse_matrix, 1, 1) + + MAT(&inverse_matrix, 0, 1) * MAT(&inverse_matrix, 1, 0) + ) + * fxfy_2 + ) + / r2_fx2_fy2sq; + + rgStepXRad = + ( + MAT(&inverse_matrix, 0, 0) * cx * r2_fy2_2 + + MAT(&inverse_matrix, 1, 0) * cy * r2_fx2_2 + + ( + MAT(&inverse_matrix, 0, 0) * cy + + MAT(&inverse_matrix, 1, 0) * cx + ) + * fxfy_2 + ) + / r2_fx2_fy2sq; + + rgStepYRad = + ( + MAT(&inverse_matrix, 0, 1) * cx * r2_fy2_2 + + MAT(&inverse_matrix, 1, 1) * cy * r2_fx2_2 + + ( + MAT(&inverse_matrix, 0, 1) * cy + + MAT(&inverse_matrix, 1, 1) * cx + ) + * fxfy_2 + ) + / r2_fx2_fy2sq; + + rgConstantRad = + ( + cx * cx * r2_fy2 + + cy * cy * r2_fx2 + + cx * cy * fxfy_2 + ) + / r2_fx2_fy2sq; + +#if !defined(VG_DRIVER_SINGLE_THREAD) + if(ctx->ts_dirty){ + memcpy(CMDBUF_BUFFER(*ctx) + CMDBUF_OFFSET(*ctx), ctx->ts_record, 80); + CMDBUF_OFFSET(*ctx) += 80; + ctx->ts_dirty = 0; + ctx->ts_init_used = 1; + } + else + { + ctx->ts_init_use = 1; + } +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + + /* Setup the command buffer. */ + + /* rad gradient parameters*/ + data = &rgConstantLin; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A04,*(uint32_t*) data)); + data = &rgStepXLin; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A06,*(uint32_t*) data)); + data = &rgStepYLin; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A08,*(uint32_t*) data)); + data = &rgConstantRad; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A05,*(uint32_t*) data)); + data = &rgStepXRad; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A07,*(uint32_t*) data)); + data = &rgStepYRad; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A09,*(uint32_t*) data)); + data = &rgStepXXRad; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A03,*(uint32_t*) data)); + data = &rgStepYYRad; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A0A,*(uint32_t*) data)); + data = &rgStepXYRad; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A0B,*(uint32_t*) data)); + VG_LITE_RETURN_ERROR(set_interpolation_steps(target, source->width, source->height, matrix)); + + if(!ctx->premultiply_enabled) { + if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A24, convert_source_format(source->format) | + filter | rad_tile | conversion | 0x01000100)); + } else { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A24, convert_source_format(source->format) | + filter | rad_tile | conversion | 0x00000100)); + } + } else { + /* enable pre-multiplied in imager unit */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A24, convert_source_format(source->format) | + filter | rad_tile | conversion)); + } + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A26, paint_color)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A28, source->address)); + + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2A, tiled_source)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2C, 0)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A2E, source->width)); + + /* Work on path states. */ + matrix = path_matrix; + + if (ts_is_fullscreen == 0){ + transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[1], matrix); + point_min = point_max = temp; + + transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[1], matrix); + if (temp.x < point_min.x) point_min.x = temp.x; + if (temp.y < point_min.y) point_min.y = temp.y; + if (temp.x > point_max.x) point_max.x = temp.x; + if (temp.y > point_max.y) point_max.y = temp.y; + + transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[3], matrix); + if (temp.x < point_min.x) point_min.x = temp.x; + if (temp.y < point_min.y) point_min.y = temp.y; + if (temp.x > point_max.x) point_max.x = temp.x; + if (temp.y > point_max.y) point_max.y = temp.y; + + transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[3], matrix); + if (temp.x < point_min.x) point_min.x = temp.x; + if (temp.y < point_min.y) point_min.y = temp.y; + if (temp.x > point_max.x) point_max.x = temp.x; + if (temp.y > point_max.y) point_max.y = temp.y; + + point_min.x = MAX(point_min.x, 0); + point_min.y = MAX(point_min.y, 0); + point_max.x = MIN(point_max.x, dst_align_width); + point_max.y = MIN(point_max.y, target->height); + } + + if (ctx->scissor_enabled) { + point_min.x = MAX(point_min.x, ctx->scissor[0]); + point_min.y = MAX(point_min.y, ctx->scissor[1]); + point_max.x = MIN(point_max.x, ctx->scissor[0] + ctx->scissor[2]); + point_max.y = MIN(point_max.y, ctx->scissor[1] + ctx->scissor[3]); + } + + /* Convert states into hardware values. */ + blend_mode = convert_blend(blend); + format = convert_path_format(path->format); + quality = convert_path_quality(path->quality); + tiling = (ctx->capabilities.cap.tiled == 2) ? 0x2000000 : 0; + fill = (fill_rule == VG_LITE_FILL_EVEN_ODD) ? 0x10 : 0; + tessellation_size = ( ctx->tsbuffer.tessellation_buffer_size[2] + ? ctx->tsbuffer.tessellation_buffer_size[2] + : ctx->tsbuffer.tessellation_buffer_size[1] + ); + + /* Setup the command buffer. */ + /* Program color register. */ + if(!ctx->premultiply_enabled) { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, 0x12000000 | ctx->capabilities.cap.tiled | 0x00000002 | imageMode | blend_mode | transparency_mode)); + } else { + /* enable pre-multiplied from VG to VGPE */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A00, 0x02000000 | ctx->capabilities.cap.tiled | 0x00000002 | imageMode | blend_mode | transparency_mode)); + } + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A34, 0x01000400 | format | quality | tiling | fill)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3B, 0x3F800000)); /* Path tessellation SCALE. */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3C, 0x00000000)); /* Path tessellation BIAS. */ + /* Program matrix. */ + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A40, (void *) &matrix->m[0][0])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A41, (void *) &matrix->m[0][1])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A42, (void *) &matrix->m[0][2])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A43, (void *) &matrix->m[1][0])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A44, (void *) &matrix->m[1][1])); + VG_LITE_RETURN_ERROR(push_state_ptr(ctx, 0x0A45, (void *) &matrix->m[1][2])); + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) + { + if (path->path_changed != 0) { + if (path->uploaded.handle != NULL) { + free_memory.memory_handle = path->uploaded.handle; + vg_lite_kernel(VG_LITE_FREE, &free_memory); + path->uploaded.address = 0; + path->uploaded.memory = NULL; + path->uploaded.handle = NULL; + } + /* Allocate memory for the path data. */ + memory.bytes = 16 + VG_LITE_ALIGN(path->path_length, 8); + return_offset = (8 + VG_LITE_ALIGN(path->path_length, 8)) / 4; + memory.contiguous = 1; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &memory)); + ((uint64_t *) memory.memory)[(path->path_length + 7) / 8] = 0; + ((uint32_t *) memory.memory)[0] = VG_LITE_DATA((path->path_length + 7) / 8); + ((uint32_t *) memory.memory)[1] = 0; + memcpy((uint8_t *) memory.memory + 8, path->path, path->path_length); + ((uint32_t *) memory.memory)[return_offset] = VG_LITE_RETURN(); + ((uint32_t *) memory.memory)[return_offset + 1] = 0; + + path->uploaded.handle = memory.memory_handle; + path->uploaded.memory = memory.memory; + path->uploaded.address = memory.memory_gpu; + path->uploaded.bytes = memory.bytes; + path->path_changed = 0; + } + } + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { + + vglitemDUMP_BUFFER("path", path->uploaded.address, (uint8_t *)(path->uploaded.memory), 0, path->uploaded.bytes); + } + + vglitemDUMP("@[memory 0x%08X 0x%08X]", ctx->tsbuffer.tessellation_buffer_gpu[0], ctx->tsbuffer.tessellation_buffer_size[0]); + + /* Setup tessellation loop. */ + if((path->path_type & 0x1) == VG_LITE_DRAW_FILL_PATH) { + for (y = point_min.y; y < point_max.y; y += height) { + for (x = point_min.x; x < point_max.x; x += width) { + /* Tessellate path. */ + VG_LITE_RETURN_ERROR(push_stall(ctx, 15)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A1B, 0x00011000)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A01, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A39, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3D, tessellation_size / 64)); + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { + VG_LITE_RETURN_ERROR(push_call(ctx, path->uploaded.address, path->uploaded.bytes)); +#if (DUMP_COMMAND) + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[0], 0); + + unsigned char* pt = (unsigned char*) memory.memory; + + for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) + { + if (i % 8 == 0) + fprintf(fp, "Command buffer: "); + + if (i % 4 == 0) + fprintf(fp, "0x"); + + for (int j = 3; j >= 0; --j) + fprintf(fp, "%02x", pt[i + j]); + + if ((i / 4 + 1) % 2 == 0) + fprintf(fp, ",\n"); + else + fprintf(fp, ", "); + } + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[return_offset], 0); + + fclose(fp); + fp = NULL; +#endif + } else { + push_data(ctx, path->path_length, path->path); + } + } + } + } + /* Setup tessellation loop. */ + if(path->path_type == VG_LITE_DRAW_STROKE_PATH || path->path_type == VG_LITE_DRAW_FILL_STROKE_PATH) { + for (y = point_min.y; y < point_max.y; y += height) { + for (x = point_min.x; x < point_max.x; x += width) { + /* Tessellate path. */ + VG_LITE_RETURN_ERROR(push_stall(ctx, 15)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A1B, 0x00011000)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A01, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A39, x | (y << 16))); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A3D, tessellation_size / 64)); + + if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { + VG_LITE_RETURN_ERROR(push_call(ctx, path->uploaded.address, path->uploaded.bytes)); +#if (DUMP_COMMAND) + if (strncmp(filename, "Commandbuffer", 13)) { + sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); + } + + fp = fopen(filename, "a"); + + if (fp == NULL) + printf("error!\n"); + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[0], 0); + + unsigned char* pt = (unsigned char*) memory.memory; + + for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) + { + if (i % 8 == 0) + fprintf(fp, "Command buffer: "); + + if (i % 4 == 0) + fprintf(fp, "0x"); + + for (int j = 3; j >= 0; --j) + fprintf(fp, "%02x", pt[i + j]); + + if ((i / 4 + 1) % 2 == 0) + fprintf(fp, ",\n"); + else + fprintf(fp, ", "); + } + + fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", + ((uint32_t *) memory.memory)[return_offset], 0); + + fclose(fp); + fp = NULL; +#endif + } else { + format = convert_path_format(VG_LITE_FP32); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A34, 0x01000200 | format | quality | tiling | 0x0)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A02, path->stroke_color)); + push_data(ctx, path->stroke_path_size, path->stroke_path_data); + } + } + } + } + + /* Notify rendering area (added by MicroEJ) */ + vg_lite_draw_notify_render_area(point_min.x, point_min.y, point_max.x, point_max.y); + + /* Finialize command buffer. */ + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A34, 0)); + + vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); +#if DUMP_IMAGE + dump_img(source->memory, src_align_width, source->height, source->format); +#endif + +#if !defined(VG_DRIVER_SINGLE_THREAD) + tls->t_context.ts_init = 1; +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + return error; +} + +vg_lite_error_t vg_lite_init_grad(vg_lite_linear_gradient_t *grad) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + + /* Set the member values according to driver defaults. */ + grad->image.width = VLC_GRADBUFFER_WIDTH; + grad->image.height = 1; + grad->image.stride = 0; + grad->image.format = VG_LITE_BGRA8888; + + /* Allocate the image for gradient. */ + error = vg_lite_allocate(&grad->image); + + grad->count = 0; + + return error; +} + +vg_lite_error_t vg_lite_set_linear_grad(vg_lite_linear_gradient_ext_t *grad, + uint32_t count, + vg_lite_color_ramp_t *vg_color_ramp, + vg_lite_linear_gradient_parameter_t linear_gradient, + vg_lite_radial_gradient_spreadmode_t spread_mode, + uint8_t color_ramp_premultiplied) +{ + int i; + static vg_lite_color_ramp_t default_ramp[] = + { + { + 0.0f, + 0.0f, 0.0f, 0.0f, 1.0f + }, + { + 1.0f, + 1.0f, 1.0f, 1.0f, 1.0f + } + }; + + uint32_t trg_count; + vg_lite_float_t prev_stop; + vg_lite_color_ramp_ptr src_ramp; + vg_lite_color_ramp_ptr src_ramp_last; + vg_lite_color_ramp_ptr trg_ramp; + + /* Reset the count. */ + trg_count = 0; + + if ((linear_gradient.X0 == linear_gradient.X1) && (linear_gradient.Y0 == linear_gradient.Y1)) + return VG_LITE_INVALID_ARGUMENT; + + grad->linear_gradient = linear_gradient; + grad->color_ramp_premultiplied = color_ramp_premultiplied; + grad->spread_mode = spread_mode; + + if (!count || count > MAX_COLOR_RAMP_STOPS || vg_color_ramp == NULL) + goto Empty_sequence_handler; + + for(i = 0; i < count;i++) + grad->vg_color_ramp[i] = vg_color_ramp[i]; + grad->vg_color_ramp_length = count; + + /* Determine the last source ramp. */ + src_ramp_last + = grad->vg_color_ramp + + grad->vg_color_ramp_length; + + /* Set the initial previous stop. */ + prev_stop = -1; + + /* Reset the count. */ + trg_count = 0; + + /* Walk through the source ramp. */ + for ( + src_ramp = grad->vg_color_ramp, trg_ramp = grad->int_color_ramp; + (src_ramp < src_ramp_last) && (trg_count < MAX_COLOR_RAMP_STOPS + 2); + src_ramp += 1 + ) + { + /* Must be in increasing order. */ + if (src_ramp->stop < prev_stop) + { + /* Ignore the entire sequence. */ + trg_count = 0; + break; + } + + /* Update the previous stop value. */ + prev_stop = src_ramp->stop; + + /* Must be within [0..1] range. */ + if ((src_ramp->stop < 0.0f) || (src_ramp->stop > 1.0f)) + { + /* Ignore. */ + continue; + } + + /* Clamp color. */ + ClampColor(COLOR_FROM_RAMP(src_ramp),COLOR_FROM_RAMP(trg_ramp),0); + + /* First stop greater then zero? */ + if ((trg_count == 0) && (src_ramp->stop > 0.0f)) + { + /* Force the first stop to 0.0f. */ + trg_ramp->stop = 0.0f; + + /* Replicate the entry. */ + trg_ramp[1] = *trg_ramp; + trg_ramp[1].stop = src_ramp->stop; + + /* Advance. */ + trg_ramp += 2; + trg_count += 2; + } + else + { + /* Set the stop value. */ + trg_ramp->stop = src_ramp->stop; + + /* Advance. */ + trg_ramp += 1; + trg_count += 1; + } + } + + /* Empty sequence? */ + if (trg_count == 0) + { + memcpy(grad->int_color_ramp,default_ramp,sizeof(default_ramp)); + grad->int_color_ramp_length = sizeof(default_ramp) / 5; + } + else + { + /* The last stop must be at 1.0. */ + if (trg_ramp[-1].stop != 1.0f) + { + /* Replicate the last entry. */ + *trg_ramp = trg_ramp[-1]; + + /* Force the last stop to 1.0f. */ + trg_ramp->stop = 1.0f; + + /* Update the final entry count. */ + trg_count += 1; + } + + /* Set new length. */ + grad->int_color_ramp_length = trg_count; + } + return VG_LITE_SUCCESS; + +Empty_sequence_handler: + memcpy(grad->int_color_ramp,default_ramp,sizeof(default_ramp)); + grad->int_color_ramp_length = sizeof(default_ramp) / 5; + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_update_linear_grad(vg_lite_linear_gradient_ext_t *grad) +{ + uint32_t color_ramp_length; + vg_lite_color_ramp_ptr color_ramp; + uint32_t common, stop; + uint32_t i, width; + uint8_t* bits; + vg_lite_float_t x0,y0,x1,y1,length; + vg_lite_error_t error = VG_LITE_SUCCESS; + + /* Get shortcuts to the color ramp. */ + color_ramp_length = grad->int_color_ramp_length; + color_ramp = grad->int_color_ramp; + + x0 = grad->linear_gradient.X0; + y0 = grad->linear_gradient.Y0; + x1 = grad->linear_gradient.X1; + y1 = grad->linear_gradient.Y1; + length = (vg_lite_float_t)sqrt((x1-x0)*(x1-x0) + (y1-y0)*(y1-y0)); + + if(length <= 0) + return VG_LITE_INVALID_ARGUMENT; + /* Find the common denominator of the color ramp stops. */ + if (length < 1) + { + common = 1; + } + else + { + common = (uint32_t)length; + } + + for (i = 0; i < color_ramp_length; ++i) + { + if (color_ramp[i].stop != 0.0f) + { + vg_lite_float_t mul = common * color_ramp[i].stop; + vg_lite_float_t frac = mul - (vg_lite_float_t) floor(mul); + if (frac > 0.00013f) /* Suppose error for zero is 0.00013 */ + { + common = MAX(common, (uint32_t) (1.0f / frac + 0.5f)); + } + } + } + + /* Compute the width of the required color array. */ + width = common + 1; + + /* Allocate the color ramp surface. */ + memset(&grad->image, 0, sizeof(grad->image)); + grad->image.width = width; + grad->image.height = 1; + grad->image.stride = 0; + grad->image.image_mode = VG_LITE_NONE_IMAGE_MODE; + grad->image.format = VG_LITE_ABGR8888; + + /* Allocate the image for gradient. */ + VG_LITE_RETURN_ERROR(vg_lite_allocate(&grad->image)); + + grad->image.width = width; + + /* Set pointer to color array. */ + bits = (uint8_t *)grad->image.memory; + + /* Start filling the color array. */ + stop = 0; + for (i = 0; i < width; ++i) + { + vg_lite_float_t gradient; + vg_lite_float_t color[4]; + vg_lite_float_t color1[4]; + vg_lite_float_t color2[4]; + vg_lite_float_t weight; + + /* Compute gradient for current color array entry. */ + gradient = (vg_lite_float_t) i / (vg_lite_float_t) (width - 1); + + /* Find the entry in the color ramp that matches or exceeds this + ** gradient. */ + while ((stop < color_ramp_length - 1) && (gradient > color_ramp[stop].stop)) + { + ++stop; + } + + if (gradient == color_ramp[stop].stop) + { + /* Perfect match weight 1.0. */ + weight = 1.0f; + + /* Use color ramp color. */ + color1[3] = color_ramp[stop].alpha; + color1[2] = color_ramp[stop].blue; + color1[1] = color_ramp[stop].green; + color1[0] = color_ramp[stop].red; + + color2[3] = + color2[2] = + color2[1] = + color2[0] = 0.0f; + } + else + { + /* Compute weight. */ + weight = (color_ramp[stop].stop - gradient) + / (color_ramp[stop].stop - color_ramp[stop - 1].stop); + + /* Grab color ramp color of previous stop. */ + color1[3] = color_ramp[stop - 1].alpha; + color1[2] = color_ramp[stop - 1].blue; + color1[1] = color_ramp[stop - 1].green; + color1[0] = color_ramp[stop - 1].red; + + /* Grab color ramp color of current stop. */ + color2[3] = color_ramp[stop].alpha; + color2[2] = color_ramp[stop].blue; + color2[1] = color_ramp[stop].green; + color2[0] = color_ramp[stop].red; + } + + if (grad->color_ramp_premultiplied) + { + /* Pre-multiply the first color. */ + color1[2] *= color1[3]; + color1[1] *= color1[3]; + color1[0] *= color1[3]; + + /* Pre-multiply the second color. */ + color2[2] *= color2[3]; + color2[1] *= color2[3]; + color2[0] *= color2[3]; + } + + /* Filter the colors per channel. */ + color[3] = LERP(color1[3], color2[3], weight); + color[2] = LERP(color1[2], color2[2], weight); + color[1] = LERP(color1[1], color2[1], weight); + color[0] = LERP(color1[0], color2[0], weight); + + /* Pack the final color. */ + *bits++ = PackColorComponent(color[3]); + *bits++ = PackColorComponent(color[2]); + *bits++ = PackColorComponent(color[1]); + *bits++ = PackColorComponent(color[0]); + } + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_set_rad_grad(vg_lite_radial_gradient_t *grad, + uint32_t count, + vg_lite_color_ramp_t *vgColorRamp, + vg_lite_radial_gradient_parameter_t radialGradient, + vg_lite_radial_gradient_spreadmode_t SpreadMode, + uint8_t colorRampPremultiplied) +{ + int i; + static vg_lite_color_ramp_t defaultRamp[] = + { + { + 0.0f, + 0.0f, 0.0f, 0.0f, 1.0f + }, + { + 1.0f, + 1.0f, 1.0f, 1.0f, 1.0f + } + }; + + uint32_t trgCount; + vg_lite_float_t prevStop; + vg_lite_color_ramp_ptr srcRamp; + vg_lite_color_ramp_ptr srcRampLast; + vg_lite_color_ramp_ptr trgRamp; + + /* Reset the count. */ + trgCount = 0; + + if(radialGradient.r <= 0) + return VG_LITE_INVALID_ARGUMENT; + + grad->radialGradient = radialGradient; + grad->colorRampPremultiplied = colorRampPremultiplied; + grad->SpreadMode = SpreadMode; + + if (!count || count > MAX_COLOR_RAMP_STOPS || vgColorRamp == NULL) + goto Empty_sequence_handler; + + for(i = 0; i < count;i++) + grad->vgColorRamp[i] = vgColorRamp[i]; + grad->vgColorRampLength = count; + + /* Determine the last source ramp. */ + srcRampLast + = grad->vgColorRamp + + grad->vgColorRampLength; + + /* Set the initial previous stop. */ + prevStop = -1; + + /* Reset the count. */ + trgCount = 0; + + /* Walk through the source ramp. */ + for ( + srcRamp = grad->vgColorRamp, trgRamp = grad->intColorRamp; + (srcRamp < srcRampLast) && (trgCount < MAX_COLOR_RAMP_STOPS + 2); + srcRamp += 1 + ) + { + /* Must be in increasing order. */ + if (srcRamp->stop < prevStop) + { + /* Ignore the entire sequence. */ + trgCount = 0; + break; + } + + /* Update the previous stop value. */ + prevStop = srcRamp->stop; + + /* Must be within [0..1] range. */ + if ((srcRamp->stop < 0.0f) || (srcRamp->stop > 1.0f)) + { + /* Ignore. */ + continue; + } + + /* Clamp color. */ + ClampColor(COLOR_FROM_RAMP(srcRamp),COLOR_FROM_RAMP(trgRamp),0); + + /* First stop greater then zero? */ + if ((trgCount == 0) && (srcRamp->stop > 0.0f)) + { + /* Force the first stop to 0.0f. */ + trgRamp->stop = 0.0f; + + /* Replicate the entry. */ + trgRamp[1] = *trgRamp; + trgRamp[1].stop = srcRamp->stop; + + /* Advance. */ + trgRamp += 2; + trgCount += 2; + } + else + { + /* Set the stop value. */ + trgRamp->stop = srcRamp->stop; + + /* Advance. */ + trgRamp += 1; + trgCount += 1; + } + } + + /* Empty sequence? */ + if (trgCount == 0) + { + memcpy(grad->intColorRamp,defaultRamp,sizeof(defaultRamp)); + grad->intColorRampLength = sizeof(defaultRamp) / 5; + } + else + { + /* The last stop must be at 1.0. */ + if (trgRamp[-1].stop != 1.0f) + { + /* Replicate the last entry. */ + *trgRamp = trgRamp[-1]; + + /* Force the last stop to 1.0f. */ + trgRamp->stop = 1.0f; + + /* Update the final entry count. */ + trgCount += 1; + } + + /* Set new length. */ + grad->intColorRampLength = trgCount; + } + return VG_LITE_SUCCESS; + +Empty_sequence_handler: + memcpy(grad->intColorRamp,defaultRamp,sizeof(defaultRamp)); + grad->intColorRampLength = sizeof(defaultRamp) / 5; + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_update_rad_grad(vg_lite_radial_gradient_t *grad) +{ + uint32_t colorRampLength; + vg_lite_color_ramp_ptr colorRamp; + uint32_t common, stop; + uint32_t i, width; + uint8_t* bits; + vg_lite_float_t r; + vg_lite_error_t error = VG_LITE_SUCCESS; + + /* Get shortcuts to the color ramp. */ + colorRampLength = grad->intColorRampLength; + colorRamp = grad->intColorRamp; + + r = grad->radialGradient.r; + + if(r <= 0) + return VG_LITE_INVALID_ARGUMENT; + /* Find the common denominator of the color ramp stops. */ + if (r < 1) + { + common = 1; + } + else + { + common = (uint32_t)r; + } + + for (i = 0; i < colorRampLength; ++i) + { + if (colorRamp[i].stop != 0.0f) + { + vg_lite_float_t mul = common * colorRamp[i].stop; + vg_lite_float_t frac = mul - (vg_lite_float_t) floor(mul); + if (frac > 0.00013f) /* Suppose error for zero is 0.00013 */ + { + common = MAX(common, (uint32_t) (1.0f / frac + 0.5f)); + } + } + } + + /* Compute the width of the required color array. */ + width = common + 1; + + /* Allocate the color ramp surface. */ + memset(&grad->image, 0, sizeof(grad->image)); + grad->image.width = width; + grad->image.height = 1; + grad->image.stride = 0; + grad->image.image_mode = VG_LITE_NONE_IMAGE_MODE; + grad->image.format = VG_LITE_ABGR8888; + + /* Allocate the image for gradient. */ + VG_LITE_RETURN_ERROR(vg_lite_allocate(&grad->image)); + + grad->image.width = width; + + /* Set pointer to color array. */ + bits = (uint8_t *)grad->image.memory; + + /* Start filling the color array. */ + stop = 0; + for (i = 0; i < width; ++i) + { + vg_lite_float_t gradient; + vg_lite_float_t color[4]; + vg_lite_float_t color1[4]; + vg_lite_float_t color2[4]; + vg_lite_float_t weight; + + /* Compute gradient for current color array entry. */ + gradient = (vg_lite_float_t) i / (vg_lite_float_t) (width - 1); + + /* Find the entry in the color ramp that matches or exceeds this + ** gradient. */ + while ((stop < colorRampLength - 1) && (gradient > colorRamp[stop].stop)) + { + ++stop; + } + + if (gradient == colorRamp[stop].stop) + { + /* Perfect match weight 1.0. */ + weight = 1.0f; + + /* Use color ramp color. */ + color1[3] = colorRamp[stop].alpha; + color1[2] = colorRamp[stop].blue; + color1[1] = colorRamp[stop].green; + color1[0] = colorRamp[stop].red; + + color2[3] = + color2[2] = + color2[1] = + color2[0] = 0.0f; + } + else + { + /* Compute weight. */ + weight = (colorRamp[stop].stop - gradient) + / (colorRamp[stop].stop - colorRamp[stop - 1].stop); + + /* Grab color ramp color of previous stop. */ + color1[3] = colorRamp[stop - 1].alpha; + color1[2] = colorRamp[stop - 1].blue; + color1[1] = colorRamp[stop - 1].green; + color1[0] = colorRamp[stop - 1].red; + + /* Grab color ramp color of current stop. */ + color2[3] = colorRamp[stop].alpha; + color2[2] = colorRamp[stop].blue; + color2[1] = colorRamp[stop].green; + color2[0] = colorRamp[stop].red; + } + + if (grad->colorRampPremultiplied) + { + /* Pre-multiply the first color. */ + color1[2] *= color1[3]; + color1[1] *= color1[3]; + color1[0] *= color1[3]; + + /* Pre-multiply the second color. */ + color2[2] *= color2[3]; + color2[1] *= color2[3]; + color2[0] *= color2[3]; + } + + /* Filter the colors per channel. */ + color[3] = LERP(color1[3], color2[3], weight); + color[2] = LERP(color1[2], color2[2], weight); + color[1] = LERP(color1[1], color2[1], weight); + color[0] = LERP(color1[0], color2[0], weight); + + /* Pack the final color. */ + *bits++ = PackColorComponent(color[3]); + *bits++ = PackColorComponent(color[2]); + *bits++ = PackColorComponent(color[1]); + *bits++ = PackColorComponent(color[0]); + } + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_set_grad(vg_lite_linear_gradient_t *grad, + uint32_t count, + uint32_t * colors, + uint32_t * stops) +{ + uint32_t i; + + grad->count = 0; /* Opaque B&W gradient */ + if (!count || count > VLC_MAX_GRAD || colors == NULL || stops == NULL) + return VG_LITE_SUCCESS; + /* Check stops validity */ + for (i = 0; i < count; i++) + if (stops[i] <= 255) { + if (!grad->count || stops[i] > grad->stops[grad->count - 1]) { + grad->stops[grad->count] = stops[i]; + grad->colors[grad->count] = colors[i]; + grad->count++; + } else if (stops[i] == grad->stops[grad->count - 1]) { + /* Equal stops : use the color corresponding to the last stop + in the sequence */ + grad->colors[grad->count - 1] = colors[i]; + } + } + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_update_grad(vg_lite_linear_gradient_t *grad) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + int32_t r0, g0, b0, a0; + int32_t r1, g1, b1, a1; + int32_t lr, lg, lb, la; + uint32_t i; + int32_t j; + int32_t ds, dr, dg, db, da; + uint32_t *buffer = (uint32_t *)grad->image.memory; + + if (grad->count == 0) { + /* If no valid stops have been specified (e.g., due to an empty input + * array, out-of-range, or out-of-order stops), a stop at 0 with color + * 0xFF000000 (opaque black) and a stop at 255 with color 0xFFFFFFFF + * (opaque white) are implicitly defined. */ + grad->stops[0] = 0; + grad->colors[0] = 0xFF000000; /* Opaque black */ + grad->stops[1] = 255; + grad->colors[1] = 0xFFFFFFFF; /* Opaque white */ + grad->count = 2; + } else if (grad->count && grad->stops[0] != 0) { + /* If at least one valid stop has been specified, but none has been + * defined with an offset of 0, an implicit stop is added with an + * offset of 0 and the same color as the first user-defined stop. */ + for (i = 0; i < grad->stops[0]; i++) + buffer[i] = grad->colors[0]; + } + a0 = A(grad->colors[0]); + r0 = R(grad->colors[0]); + g0 = G(grad->colors[0]); + b0 = B(grad->colors[0]); + + /* Calculate the colors for each pixel of the image. */ + for (i = 0; i < grad->count - 1; i++) { + buffer[grad->stops[i]] = grad->colors[i]; + ds = grad->stops[i + 1] - grad->stops[i]; + a1 = A(grad->colors[i + 1]); + r1 = R(grad->colors[i + 1]); + g1 = G(grad->colors[i + 1]); + b1 = B(grad->colors[i + 1]); + + da = a1 - a0; + dr = r1 - r0; + dg = g1 - g0; + db = b1 - b0; + + for (j = 1; j < ds; j++) { + la = a0 + da * j / ds; + lr = r0 + dr * j / ds; + lg = g0 + dg * j / ds; + lb = b0 + db * j / ds; + + buffer[grad->stops[i] + j] = ARGB(la, lr, lg, lb); + } + + a0 = a1; + r0 = r1; + g0 = g1; + b0 = b1; + } + /* If at least one valid stop has been specified, but none has been defined + * with an offset of 255, an implicit stop is added with an offset of 255 + * and the same color as the last user-defined stop. */ + for (i = grad->stops[grad->count - 1]; i < 255; i++) + buffer[i] = grad->colors[grad->count - 1]; + /* Last pixel */ + buffer[i] = grad->colors[grad->count - 1]; + return error; +} + +vg_lite_error_t vg_lite_clear_grad(vg_lite_linear_gradient_t *grad) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + + grad->count = 0; + /* Release the image resource. */ + if (grad->image.handle != NULL) + { + error = vg_lite_free(&grad->image); + } + + return error; +} + +vg_lite_error_t vg_lite_clear_rad_grad(vg_lite_radial_gradient_t *grad) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + + grad->count = 0; + /* Release the image resource. */ + if (grad->image.handle != NULL) + { + error = vg_lite_free(&grad->image); + } + + return error; +} + +vg_lite_error_t vg_lite_clear_linear_grad(vg_lite_linear_gradient_ext_t *grad) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + + grad->count = 0; + /* Release the image resource. */ + if (grad->image.handle != NULL) + { + error = vg_lite_free(&grad->image); + } + + return error; +} + +vg_lite_matrix_t * vg_lite_get_linear_grad_matrix(vg_lite_linear_gradient_ext_t *grad) +{ + return &grad->matrix; +} + +vg_lite_matrix_t * vg_lite_get_grad_matrix(vg_lite_linear_gradient_t *grad) +{ + return &grad->matrix; +} + +vg_lite_matrix_t * vg_lite_get_rad_grad_matrix(vg_lite_radial_gradient_t *grad) +{ + return &grad->matrix; +} + +vg_lite_error_t vg_lite_draw_gradient(vg_lite_buffer_t * target, + vg_lite_path_t * path, + vg_lite_fill_t fill_rule, + vg_lite_matrix_t * matrix, + vg_lite_linear_gradient_t * grad, + vg_lite_blend_t blend) +{ + return vg_lite_draw_pattern(target, path, fill_rule, matrix, + &grad->image, &grad->matrix, blend, VG_LITE_PATTERN_PAD, 0, VG_LITE_FILTER_LINEAR); +} + +// added by MicroEJ +uint32_t vg_lite_get_scissor(int32_t** scissor) +{ + *scissor = s_context.scissor; + return s_context.scissor_enabled; +} + +vg_lite_error_t vg_lite_set_command_buffer_size(uint32_t size) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + +#if defined(VG_DRIVER_SINGLE_THREAD) + if(!ctx->init){ + if(!size) + return VG_LITE_INVALID_ARGUMENT; + command_buffer_size = size; + } + else{ +#else + if(CMDBUF_IN_QUEUE(&ctx->context, 0) || + CMDBUF_IN_QUEUE(&ctx->context, 1)) + return VG_LITE_INVALID_ARGUMENT; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + VG_LITE_RETURN_ERROR(_free_command_buffer()); + VG_LITE_RETURN_ERROR(_allocate_command_buffer(size)); + VG_LITE_RETURN_ERROR(program_tessellation(ctx)); + +#if defined(VG_DRIVER_SINGLE_THREAD) + } +#endif /* VG_DRIVER_SINGLE_THREAD */ + + return error; +} + +vg_lite_error_t vg_lite_set_scissor(int32_t x, int32_t y, int32_t width, int32_t height) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; + + /* Scissor dirty. */ + ctx->scissor_dirty = 1; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + /* Save scissor Box States. */ + ctx->scissor[0] = x; + ctx->scissor[1] = y; + ctx->scissor[2] = width; + ctx->scissor[3] = height; + + return error; +} + +vg_lite_error_t vg_lite_enable_scissor(void) +{ +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; + + /* Scissor dirty. */ + ctx->scissor_dirty = 1; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + /* Enable scissor Mode. */ + ctx->scissor_enabled = 1; + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_disable_scissor(void) +{ +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; + + /* Scissor dirty. */ + ctx->scissor_dirty = 1; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + /* disable scissor Mode. */ + ctx->scissor_enabled = 0; + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_mem_avail(uint32_t *size) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_kernel_mem_t mem; + VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_QUERY_MEM,&mem)); + *size = mem.bytes; + + return error; +} + +vg_lite_error_t vg_lite_enable_premultiply(void) +{ +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t *tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if (tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + if(!vg_lite_query_feature(gcFEATURE_BIT_VG_PE_PREMULTIPLY)) + return VG_LITE_NOT_SUPPORT; + + /* Enable premultiply Mode. */ + ctx->premultiply_enabled = 1; + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_disable_premultiply(void) +{ +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + if(!vg_lite_query_feature(gcFEATURE_BIT_VG_PE_PREMULTIPLY)) + return VG_LITE_NOT_SUPPORT; + + /* disable premultiply Mode. */ + ctx->premultiply_enabled = 0; + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t vg_lite_set_dither(int enable) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + uint32_t table_low = 0x7B48F3C0; + uint32_t table_high = 0x596AD1E2; + int dither_enable = enable; +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_tls_t* tls; + vg_lite_context_t *ctx; + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + if(!vg_lite_query_feature(gcFEATURE_BIT_VG_DITHER)) { + return VG_LITE_NOT_SUPPORT; + } + + if(dither_enable) { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A5A, table_low)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A5B, table_high)); + } + else { + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A5A, 0xFFFFFFFF)); + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A5B, 0xFFFFFFFF)); + } + + return error; +} + +vg_lite_error_t vg_lite_set_color_key(vg_lite_color_key4_t colorkey) +{ + uint8_t i; + uint32_t value_low = 0; + uint32_t value_high = 0; + uint8_t r, g, b, a, e; + vg_lite_error_t error = VG_LITE_SUCCESS; +#if defined(VG_DRIVER_SINGLE_THREAD) + vg_lite_context_t *ctx = &s_context; +#else + vg_lite_context_t *ctx; + vg_lite_tls_t* tls; + + tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); + if(tls == NULL) + return VG_LITE_NO_CONTEXT; + + ctx = &tls->t_context; +#endif /* VG_DRIVER_SINGLE_THREAD */ + + if(!vg_lite_query_feature(gcFEATURE_BIT_VG_COLOR_KEY)) + return VG_LITE_NOT_SUPPORT; + + /* Set color key states. */ + for (i = 0; i < 4; i++) + { + /* Set gcregVGPEColorKeyLow. Layout "E/R/G/B". */ + r = colorkey[i].low_r; + g = colorkey[i].low_g; + b = colorkey[i].low_b; + e = colorkey[i].enable; + value_low = (e << 24) | (r << 16) | (g << 8) | b; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A90 + i , value_low)); + + /* Set gcregVGPEColorKeyHigh. Layout "A/R/G/B". */ + r = colorkey[i].hign_r; + g = colorkey[i].hign_g; + b = colorkey[i].hign_b; + a = colorkey[i].alpha; + value_high = (a << 24) | (r << 16) | (g << 8) | b; + VG_LITE_RETURN_ERROR(push_state(ctx, 0x0A94 + i , value_high)); + } + + return error; +} diff --git a/bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_flat.c b/bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_flat.c new file mode 100644 index 0000000..7c6861d --- /dev/null +++ b/bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_flat.c @@ -0,0 +1,536 @@ + +/**************************************************************************** +* +* Copyright Raph Levien 2022 +* Copyright Nicolas Silva 2022 +* Copyright NXP 2022 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*****************************************************************************/ + +#include + +#include "vg_lite_flat.h" +#include "nxp_support.h" + +/* + * Stop IAR compiler from warning about implicit conversions from float to + * double + */ +#if (defined(__ICCARM__)) +#pragma diag_suppress = Pa205 +#endif + +#ifndef VG_CURVE_FLATTENING_TOLERANCE +#define VG_CURVE_FLATTENING_TOLERANCE 0.25 +#endif /* defined(VG_CURVE_FLATTENING_TOLERANCE) */ + +#define FABSF(x) ((vg_lite_float_t) fabs(x)) +#define SQRTF(x) ((vg_lite_float_t) sqrt(x)) +#define CEILF(x) ((vg_lite_float_t) ceil(x)) + +#define VG_LITE_ERROR_HANDLER(func) \ +if ((error = func) != VG_LITE_SUCCESS) \ +goto ErrorHandler + +/* Point flatten type for flattened line segments. */ +#define vgcFLATTEN_NO 0 +#define vgcFLATTEN_START 1 +#define vgcFLATTEN_MIDDLE 2 +#define vgcFLATTEN_END 3 + +/* + * Algorithm originally created by Raph Levien: + * https://raphlinus.github.io/graphics/curves/2019/12/23/flatten-quadbez.html + */ + +#define FHYPOTF(x, y) ((vg_lite_float_t) hypotf(x, y)) +#define FPOWF(x, y) ((vg_lite_float_t) powf(x, y)) + +/* + * Contains the fields that are used to represent the quadratic Bezier curve + * as a 'y = x^2' parabola. + */ +typedef struct parabola_approx { + vg_lite_float_t x0; + vg_lite_float_t x2; + vg_lite_float_t scale; + vg_lite_float_t cross; +} parabola_approx_t; + +/* + * Keeps the quadratic Bezier's control points. This makes life easier when + * passing quadratics as parameters, so we don't have to give 6 floats every + * time. + */ +typedef struct quad_bezier { + vg_lite_float_t X0; + vg_lite_float_t Y0; + vg_lite_float_t X1; + vg_lite_float_t Y1; + vg_lite_float_t X2; + vg_lite_float_t Y2; +} quad_bezier_t; + +/* + * Parameters which are used by the flattening algorithm. + */ +typedef struct quad_bezier_flatten_params { + vg_lite_float_t a0; + vg_lite_float_t a2; + int num_points; + vg_lite_float_t u0; + vg_lite_float_t u2; +} quad_bezier_flatten_params_t; + +/* + * Keeps the cubic Bezier's control points. + */ +typedef struct cubic_bezier { + vg_lite_float_t X0; + vg_lite_float_t Y0; + vg_lite_float_t X1; + vg_lite_float_t Y1; + vg_lite_float_t X2; + vg_lite_float_t Y2; + vg_lite_float_t X3; + vg_lite_float_t Y3; +} cubic_bezier_t; + + +vg_lite_error_t _add_point_to_point_list( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_float_t X, + vg_lite_float_t Y, + uint8_t flatten_flag); + +vg_lite_error_t _add_point_to_point_list_wdelta( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_float_t X, + vg_lite_float_t Y, + vg_lite_float_t DX, + vg_lite_float_t DY, + uint8_t flatten_flag); + + +/* + * Evaluates the Bernstein polynomial that represents the curve, at 't'. + * 't' should be a value between 0.0 and 1.0 (though it can be any float, but + * the relevant values are between 0 and 1). + * 'x' and 'y' will contain the coordinates of the evaluated point. + */ +static void quad_bezier_eval( + const quad_bezier_t *q, + vg_lite_float_t t, + vg_lite_float_t *x, + vg_lite_float_t *y + ) +{ + const vg_lite_float_t omt = 1.0 - t; + *x = q->X0 * omt * omt + 2.0 * q->X1 * t * omt + q->X2 * t * t; + *y = q->Y0 * omt * omt + 2.0 * q->Y1 * t * omt + q->Y2 * t * t; +} + +/* + * Approximates the integral which uses the arclength and curvature of the + * parabola. + */ +static vg_lite_float_t approx_integral(vg_lite_float_t x) +{ + const vg_lite_float_t D = 0.67; + return x / (1.0 - D + FPOWF(FPOWF(D, 4) + 0.25 * x * x, 0.25)); +} + +/* + * Approximates the inverse of the previous integral. + */ +static vg_lite_float_t approx_inverse_integral(vg_lite_float_t x) +{ + const vg_lite_float_t B = 0.39; + return x * (1.0 - B + SQRTF(B * B + 0.25 * x * x)); +} + +/* + * Represents a quadratic Bezier curve as a parabola. + */ +static parabola_approx_t map_to_parabola(const quad_bezier_t *q) +{ + const vg_lite_float_t ddx = 2 * q->X1 - q->X0 - q->X2; + const vg_lite_float_t ddy = 2 * q->Y1 - q->Y0 - q->Y2; + const vg_lite_float_t u0 = (q->X1 - q->X0) * ddx + (q->Y1 - q->Y0) * ddy; + const vg_lite_float_t u2 = (q->X2 - q->X1) * ddx + (q->Y2 - q->Y1) * ddy; + const vg_lite_float_t cross = (q->X2 - q->X0) * ddy - (q->Y2 - q->Y0) * ddx; + const vg_lite_float_t x0 = u0 / cross; + const vg_lite_float_t x2 = u2 / cross; + const vg_lite_float_t scale = FABSF(cross) / (FHYPOTF(ddx, ddy) * FABSF(x2 - x0)); + + return (parabola_approx_t) { + .x0 = x0, + .x2 = x2, + .scale = scale, + .cross = cross + }; +} + +/* + * Tolerance influences the number of lines generated. The lower the tolerance, + * the more lines it generates, thus the flattening will have a higher quality, + * but it will also consume more memory. The bigger the tolerance, the less lines + * will be generated, so the quality will be worse, but the memory consumption + * will be better. + * + * A good default value could be 0.25. + */ +static quad_bezier_flatten_params_t quad_bezier_flatten_params_init( + const quad_bezier_t *q, + vg_lite_float_t tolerance + ) +{ + const parabola_approx_t params = map_to_parabola(q); + const vg_lite_float_t a0 = approx_integral(params.x0); + const vg_lite_float_t a2 = approx_integral(params.x2); + const vg_lite_float_t count = 0.5 * FABSF(a2 - a0) * SQRTF(params.scale / tolerance); + const int num_points = (int)CEILF(count); + const vg_lite_float_t u0 = approx_inverse_integral(a0); + const vg_lite_float_t u2 = approx_inverse_integral(a2); + + return (quad_bezier_flatten_params_t) { + .a0 = a0, + .a2 = a2, + .num_points = num_points, + .u0 = u0, + .u2 = u2 + }; +} + +/* + * Puts into (x, y) the coordinate to which a line should be drawn given the step. + * This should be used in a loop to flatten a curve, like this: + * ``` + * params = quad_bezier_flatten_params_init(&q, tolerance); + * for (int i = 1; i < params.num_points; ++i) { + * vg_lite_float_t x, y; + * quad_bezier_flatten_at(&q, ¶ms, i, &x, &y); + * draw_line_to(x, y); + * } + * ``` + */ +static void quad_bezier_flatten_at( + const quad_bezier_t *q, + const quad_bezier_flatten_params_t *params, + int step, + vg_lite_float_t *x, + vg_lite_float_t *y + ) +{ + const vg_lite_float_t a0 = params->a0, a2 = params->a2, u0 = params->u0, u2 = params->u2; + const int num_points = params->num_points; + const vg_lite_float_t u = approx_inverse_integral(a0 + ((a2 - a0) * step) / num_points); + const vg_lite_float_t t = (u - u0) / (u2 - u0); + + quad_bezier_eval(q, t, x, y); +} + +vg_lite_error_t +_flatten_quad_bezier( + vg_lite_stroke_conversion_t *stroke_conversion, + vg_lite_float_t X0, + vg_lite_float_t Y0, + vg_lite_float_t X1, + vg_lite_float_t Y1, + vg_lite_float_t X2, + vg_lite_float_t Y2 + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_path_point_ptr point0, point1; + vg_lite_float_t x, y; + + const vg_lite_float_t tolerance = VG_CURVE_FLATTENING_TOLERANCE; + const quad_bezier_t q = { + .X0 = X0, + .Y0 = Y0, + .X1 = X1, + .Y1 = Y1, + .X2 = X2, + .Y2 = Y2 + }; + const quad_bezier_flatten_params_t params = quad_bezier_flatten_params_init(&q, tolerance); + + if(!stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + /* Add extra P0 for incoming tangent. */ + point0 = stroke_conversion->path_last_point; + /* First add P1 to calculate incoming tangent, which is saved in P0. */ + VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X1, Y1, vgcFLATTEN_START)); + + point1 = stroke_conversion->path_last_point; + /* Change the point1's coordinates back to P0. */ + point1->x = X0; + point1->y = Y0; + point0->length = 0.0f; + + for (int i = 1; i < params.num_points; ++i) { + quad_bezier_flatten_at(&q, ¶ms, i, &x, &y); + _add_point_to_point_list(stroke_conversion, x, y, vgcFLATTEN_MIDDLE); + } + + /* Add point 2 separately to avoid cumulative errors. */ + VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X2, Y2, vgcFLATTEN_END)); + + /* Add extra P2 for outgoing tangent. */ + /* First change P2(point0)'s coordinates to P1. */ + point0 = stroke_conversion->path_last_point; + point0->x = X1; + point0->y = Y1; + + /* Add P2 to calculate outgoing tangent. */ + VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X2, Y2, vgcFLATTEN_NO)); + + point1 = stroke_conversion->path_last_point; + + /* Change point0's coordinates back to P2. */ + point0->x = X2; + point0->y = Y2; + point0->length = 0.0f; + +ErrorHandler: + return error; +} + +/* + * Like eval_quad_bezier, computes the coordinates of the point which resides at + * `t` for the cubic. + */ +static void cubic_bezier_eval( + const cubic_bezier_t *c, + vg_lite_float_t t, + vg_lite_float_t *x, + vg_lite_float_t *y + ) +{ + const vg_lite_float_t omt = 1.0 - t; + const vg_lite_float_t omt2 = omt * omt; + const vg_lite_float_t omt3 = omt * omt2; + const vg_lite_float_t t2 = t * t; + const vg_lite_float_t t3 = t * t2; + + *x = omt3 * c->X0 + 3.0 * t * omt2 * c->X1 + 3.0 * t2 * omt * c->X2 + t3 * c->X3; + *y = omt3 * c->Y0 + 3.0 * t * omt2 * c->Y1 + 3.0 * t2 * omt * c->Y2 + t3 * c->Y3; +} + +static quad_bezier_t cubic_bezier_derivative(const cubic_bezier_t *c) +{ + const vg_lite_float_t x0 = 3.0 * (c->X1 - c->X0); + const vg_lite_float_t y0 = 3.0 * (c->Y1 - c->Y0); + const vg_lite_float_t x1 = 3.0 * (c->X2 - c->X1); + const vg_lite_float_t y1 = 3.0 * (c->Y2 - c->Y1); + const vg_lite_float_t x2 = 3.0 * (c->X3 - c->X2); + const vg_lite_float_t y2 = 3.0 * (c->Y3 - c->Y2); + + return (quad_bezier_t) { + .X0 = x0, + .Y0 = y0, + .X1 = x1, + .Y1 = y1, + .X2 = x2, + .Y2 = y2 + }; +} + +/* + * Returns the cubic bezier that is between t0 and t1 of c. + */ +static cubic_bezier_t cubic_bezier_split_at( + const cubic_bezier_t *c, + vg_lite_float_t t0, + vg_lite_float_t t1 + ) +{ + vg_lite_float_t p0x, p0y, p1x, p1y, p2x, p2y, p3x, p3y, d1x, d1y, d2x, d2y; + vg_lite_float_t scale; + quad_bezier_t derivative; + + cubic_bezier_eval(c, t0, &p0x, &p0y); + cubic_bezier_eval(c, t1, &p3x, &p3y); + derivative = cubic_bezier_derivative(c); + scale = (t1 - t0) * (1.0 / 3.0); + quad_bezier_eval(&derivative, t0, &d1x, &d1y); + quad_bezier_eval(&derivative, t1, &d2x, &d2y); + p1x = p0x + scale * d1x; + p1y = p0y + scale * d1y; + p2x = p3x - scale * d2x; + p2y = p3y - scale * d2y; + + return (cubic_bezier_t) { + .X0 = p0x, + .Y0 = p0y, + .X1 = p1x, + .Y1 = p1y, + .X2 = p2x, + .Y2 = p2y, + .X3 = p3x, + .Y3 = p3y + }; +} + +/* + * This function returns the number of quadratic Bezier curves that are needed to + * represent the given cubic, respecting the tolerance. + * + * As with the flattening of quadratics, the lower the tolerance, the better the + * quality. The higher the tolerance, the worse the quality, but better performance + * or memory consumption. + * + * The algorithm comes from: + * https://web.archive.org/web/20210108052742/http://caffeineowl.com/graphics/2d/vectorial/cubic2quad01.html + * + * Implementation adapted from: + * https://github.com/linebender/kurbo/blob/master/src/cubicbez.rs + * and: + * https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1000&context=facpub#section.10.6 + */ +static int cubic_bezier_get_flatten_count( + const cubic_bezier_t *c, + vg_lite_float_t tolerance + ) +{ + const vg_lite_float_t x = c->X0 - 3.0 * c->X1 + 3.0 * c->X2 - c->X3; + const vg_lite_float_t y = c->Y0 - 3.0 * c->Y1 + 3.0 * c->Y2 - c->Y3; + const vg_lite_float_t err = x * x + y * y; + vg_lite_float_t result; + + result = FPOWF(err / (432.0 * tolerance * tolerance), 1.0 / 6.0); + result = CEILF(result); + + return result > 1.0 ? (int)result : 1; +} + +vg_lite_error_t +_flatten_cubic_bezier( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_float_t X0, + vg_lite_float_t Y0, + vg_lite_float_t X1, + vg_lite_float_t Y1, + vg_lite_float_t X2, + vg_lite_float_t Y2, + vg_lite_float_t X3, + vg_lite_float_t Y3 + ) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + vg_lite_path_point_ptr point0, point1; + const cubic_bezier_t c = { + .X0 = X0, + .Y0 = Y0, + .X1 = X1, + .Y1 = Y1, + .X2 = X2, + .Y2 = Y2, + .X3 = X3, + .Y3 = Y3 + }; + const vg_lite_float_t tolerance = VG_CURVE_FLATTENING_TOLERANCE; + int num_curves = cubic_bezier_get_flatten_count(&c, tolerance); + vg_lite_float_t fnum_curves = (vg_lite_float_t)num_curves; + vg_lite_float_t fi, t0, t1, p1x, p1y, p2x, p2y, x, y; + cubic_bezier_t subsegment; + quad_bezier_t current_curve; + quad_bezier_flatten_params_t params; + + if(!stroke_conversion) + return VG_LITE_INVALID_ARGUMENT; + + /* Add extra P0 for incoming tangent. */ + point0 = stroke_conversion->path_last_point; + /* First add P1/P2/P3 to calculate incoming tangent, which is saved in P0. */ + if (X0 != X1 || Y0 != Y1) + { + VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X1, Y1, vgcFLATTEN_START)); + } + else if (X0 != X2 || Y0 != Y2) + { + VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X2, Y2, vgcFLATTEN_START)); + } + else + { + VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X3, Y3, vgcFLATTEN_START)); + } + point1 = stroke_conversion->path_last_point; + /* Change the point1's coordinates back to P0. */ + point1->x = X0; + point1->y = Y0; + point0->length = 0.0f; + + for (int i = 0; i < num_curves; ++i) { + fi = (vg_lite_float_t)i; + t0 = fi / fnum_curves; + t1 = (fi + 1.0) / fnum_curves; + subsegment = cubic_bezier_split_at(&c, t0, t1); + p1x = 3.0 * subsegment.X1 - subsegment.X0; + p1y = 3.0 * subsegment.Y1 - subsegment.Y0; + p2x = 3.0 * subsegment.X2 - subsegment.X3; + p2y = 3.0 * subsegment.Y2 - subsegment.Y3; + current_curve = (quad_bezier_t) { + .X0 = subsegment.X0, + .Y0 = subsegment.Y0, + .X1 = (p1x + p2x) / 4.0, + .Y1 = (p1y + p2y) / 4.0, + .X2 = subsegment.X3, + .Y2 = subsegment.Y3 + }; + params = quad_bezier_flatten_params_init(¤t_curve, tolerance); + for (int j = 0; j < params.num_points; ++j) { + quad_bezier_flatten_at(¤t_curve, ¶ms, j, &x, &y); + _add_point_to_point_list(stroke_conversion, x, y, vgcFLATTEN_MIDDLE); + } + } + + /* Add point 3 separately to avoid cumulative errors. */ + VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X3, Y3, vgcFLATTEN_END)); + + /* Add extra P3 for outgoing tangent. */ + /* First change P3(point0)'s coordinates to P0/P1/P2. */ + point0 = stroke_conversion->path_last_point; + if (X3 != X2 || Y3 != Y2) + { + point0->x = X2; + point0->y = Y2; + } + else if (X3 != X1 || Y3 != Y1) + { + point0->x = X1; + point0->y = Y1; + } + else + { + point0->x = X0; + point0->y = Y0; + } + + /* Add P3 to calculate outgoing tangent. */ + VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X3, Y3, vgcFLATTEN_NO)); + + point1 = stroke_conversion->path_last_point; + + /* Change point0's coordinates back to P3. */ + point0->x = X3; + point0->y = Y3; + point0->length = 0.0f; + +ErrorHandler: + return error; +} diff --git a/bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_flat.h b/bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_flat.h new file mode 100644 index 0000000..fa7fbfd --- /dev/null +++ b/bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_flat.h @@ -0,0 +1,55 @@ + +/**************************************************************************** +* +* Copyright Raph Levien 2022 +* Copyright Nicolas Silva 2022 +* Copyright NXP 2022 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*****************************************************************************/ + +#ifndef _vg_lite_flat_h_ +#define _vg_lite_flat_h_ + +#include "vg_lite.h" + +#ifdef __cplusplus +extern "C" { +#endif + +vg_lite_error_t _flatten_quad_bezier( + vg_lite_stroke_conversion_t *stroke_conversion, + vg_lite_float_t X0, + vg_lite_float_t Y0, + vg_lite_float_t X1, + vg_lite_float_t Y1, + vg_lite_float_t X2, + vg_lite_float_t Y2); + +vg_lite_error_t _flatten_cubic_bezier( + vg_lite_stroke_conversion_t * stroke_conversion, + vg_lite_float_t X0, + vg_lite_float_t Y0, + vg_lite_float_t X1, + vg_lite_float_t Y1, + vg_lite_float_t X2, + vg_lite_float_t Y2, + vg_lite_float_t X3, + vg_lite_float_t Y3); + +#ifdef __cplusplus +} +#endif + +#endif /* _vg_lite_flat_h_ */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_image.c b/bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_image.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_image.c rename to bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_image.c diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_matrix.c b/bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_matrix.c similarity index 89% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_matrix.c rename to bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_matrix.c index 53f9469..1df88e4 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_matrix.c +++ b/bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_matrix.c @@ -111,14 +111,3 @@ void vg_lite_rotate(vg_lite_float_t degrees, vg_lite_matrix_t * matrix) /* Multiply with current matrix. */ multiply(matrix, &r); } - -void vg_lite_perspective(vg_lite_float_t px, vg_lite_float_t py, vg_lite_matrix_t * matrix) -{ - /* set prespective matrix */ - vg_lite_matrix_t p = { { {1.0f, 0.0f, 0.0f}, - {0.0f, 1.0f, 0.0f}, - {px, py, 1.0f} - } }; - /* Multiply with current matrix. */ - multiply(matrix, &p); -} diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_path.c b/bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_path.c similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_path.c rename to bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite_path.c diff --git a/bsp/sdk_overlay/middleware/vglite/VGLiteKernel/rtos/vg_lite_hal.c b/bsp/sdk_overlay/middleware/vglite/VGLiteKernel/rtos/vg_lite_hal.c new file mode 100644 index 0000000..9e0d2c4 --- /dev/null +++ b/bsp/sdk_overlay/middleware/vglite/VGLiteKernel/rtos/vg_lite_hal.c @@ -0,0 +1,504 @@ +/**************************************************************************** +* +* The MIT License (MIT) +* +* Copyright (c) 2014 - 2020 Vivante Corporation +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +#include "vg_lite_platform.h" +#include "vg_lite_kernel.h" +#include "vg_lite_hal.h" +#include "vg_lite_hw.h" +#include "vg_lite_os.h" + +#if !_BAREMETAL +#include "FreeRTOS.h" +#include "semphr.h" +#include "task.h" +#if !defined(VG_DRIVER_SINGLE_THREAD) +#include "queue.h" +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ +#else +#include "xil_cache.h" +#endif + +#if _BAREMETAL +/* The followings should be configured by FPGA. */ +static uint32_t registerMemBase = 0x43c80000; +#else +static uint32_t registerMemBase = 0x40240000; +#endif + +#define HEAP_NODE_USED 0xABBAF00D + +volatile void* contiguousMem = NULL; +uint32_t gpuMemBase = 0; + +/* Default heap size is 16MB. */ +static int heap_size = MAX_CONTIGUOUS_SIZE; + +void vg_lite_init_mem(uint32_t register_mem_base, + uint32_t gpu_mem_base, + volatile void * contiguous_mem_base, + uint32_t contiguous_mem_size) +{ + registerMemBase = register_mem_base; + gpuMemBase = gpu_mem_base; + contiguousMem = contiguous_mem_base; + heap_size = contiguous_mem_size; +} + +/* Implementation of list. ****************************************/ +typedef struct list_head { + struct list_head *next; + struct list_head *prev; +}list_head_t; + +#define INIT_LIST_HEAD(entry) \ + (entry)->next = (entry);\ + (entry)->prev = (entry); + +/* Add the list item in front of "head". */ +static inline void add_list(list_head_t *to_add, list_head_t *head) +{ + /* Link the new item. */ + to_add->next = head; + to_add->prev = head->prev; + + /* Modify the neighbor. */ + head->prev = to_add; + if (to_add->prev != NULL) { + to_add->prev->next = to_add; + } +} + +/* Remove an entry out of the list. */ +static inline void delete_list(list_head_t *entry) +{ + if (entry->prev != NULL) { + entry->prev->next = entry->next; + } + if (entry->next != NULL) { + entry->next->prev = entry->prev; + } +} + +/* End of list implementation. ***********/ +static inline void _memset(void *mem, unsigned char value, int size) +{ + int i; + for (i = 0; i < size; i++) { + ((unsigned char*)mem)[i] = value; + } +} + +typedef struct heap_node { + list_head_t list; /* TODO: Linux specific, needs to rewrite. */ + uint32_t offset; + unsigned long size; + uint32_t status; +}heap_node_t; + +struct memory_heap { + uint32_t free; + list_head_t list; +}; + +struct mapped_memory { + void * logical; + uint32_t physical; + int page_count; + struct page ** pages; +}; + +struct vg_lite_device { + /* void * gpu; */ + uint32_t gpu; /* Always use physical for register access in RTOS. */ + /* struct page * pages; */ + volatile void * contiguous; + unsigned int order; + unsigned int heap_size; + void * virtual; + uint32_t physical; + uint32_t size; + struct memory_heap heap; + int irq_enabled; + +#if defined(VG_DRIVER_SINGLE_THREAD) + volatile uint32_t int_flags; +#if _BAREMETAL + /* wait_queue_head_t int_queue; */ + xSemaphoreHandle int_queue; +#else + /* wait_queue_head_t int_queue; */ + SemaphoreHandle_t int_queue; +#endif +#endif /* VG_DRIVER_SINGLE_THREAD */ + + void * device; + int registered; + int major; + struct class * class; + int created; +}; + +struct client_data { + struct vg_lite_device * device; + struct vm_area_struct * vm; + void * contiguous_mapped; +}; + +static struct vg_lite_device Device, * device; + +void vg_lite_hal_delay(uint32_t ms) +{ + vg_lite_os_sleep(ms); +} + +void vg_lite_hal_barrier(void) +{ + /*Memory barrier. */ +#if _BAREMETAL + Xil_DCacheFlush(); +#else + __asm("DSB"); +#endif +} + +static int vg_lite_init(void); +vg_lite_error_t vg_lite_hal_initialize(void) +{ + int32_t error = VG_LITE_SUCCESS; + /* TODO: Turn on the power. */ + vg_lite_init(); + /* TODO: Turn on the clock. */ + error = vg_lite_os_initialize(); + + return (vg_lite_error_t)error; +} + +void vg_lite_hal_deinitialize(void) +{ + /* TODO: Remove clock. */ + vg_lite_os_deinitialize(); + /* TODO: Remove power. */ +} + +static int split_node(heap_node_t * node, unsigned long size) +{ + /* TODO: the original is linux specific list based, needs rewrite. + */ + heap_node_t * split; + + /* + * If the newly allocated object fits exactly the size of the free + * node, there is no need to split. + */ + if (node->size - size == 0) + return 0; + + /* Allocate a new node. */ + split = (heap_node_t *)vg_lite_os_malloc(sizeof(heap_node_t)); + + if (split == NULL) + return -1; + + /* Fill in the data of this node of the remaning size. */ + split->offset = node->offset + size; + split->size = node->size - size; + split->status = 0; + + /* Add the new node behind the current node. */ + add_list(&split->list, &node->list); + + /* Adjust the size of the current node. */ + node->size = size; + return 0; +} + +vg_lite_error_t vg_lite_hal_allocate_contiguous(unsigned long size, void ** logical, uint32_t * physical,void ** node) +{ + unsigned long aligned_size; + heap_node_t * pos; + + /* Align the size to 64 bytes. */ + aligned_size = (size + 63) & ~63; + + /* Check if there is enough free memory available. */ + if (aligned_size > device->heap.free) { + return VG_LITE_OUT_OF_MEMORY; + } + + /* Walk the heap backwards. */ + for (pos = (heap_node_t*)device->heap.list.prev; + &pos->list != &device->heap.list; + pos = (heap_node_t*) pos->list.prev) { + /* Check if the current node is free and is big enough. */ + if (pos->status == 0 && pos->size >= aligned_size) { + /* See if we the current node is big enough to split. */ + if (0 != split_node(pos, aligned_size)) + { + return VG_LITE_OUT_OF_RESOURCES; + } + /* Mark the current node as used. */ + pos->status = HEAP_NODE_USED; + + /* Return the logical/physical address. */ + /* *logical = (uint8_t *) private_data->contiguous_mapped + pos->offset; */ + *logical = (uint8_t *)device->virtual + pos->offset; + *physical = gpuMemBase + (uint32_t)(*logical);/* device->physical + pos->offset; */ + device->heap.free -= aligned_size; + + *node = pos; + return VG_LITE_SUCCESS; + } + } + + /* Out of memory. */ + return VG_LITE_OUT_OF_MEMORY; +} + +void vg_lite_hal_free_contiguous(void * memory_handle) +{ + /* TODO: no list available in RTOS. */ + heap_node_t * pos, * node; + + /* Get pointer to node. */ + node = memory_handle; + + if (node->status != HEAP_NODE_USED) { + return; + } + + /* Mark node as free. */ + node->status = 0; + + /* Add node size to free count. */ + device->heap.free += node->size; + + /* Check if next node is free. */ + pos = node; + for (pos = (heap_node_t *)pos->list.next; + &pos->list != &device->heap.list; + pos = (heap_node_t *)pos->list.next) { + if (pos->status == 0) { + /* Merge the nodes. */ + node->size += pos->size; + if(node->offset > pos->offset) + node->offset = pos->offset; + /* Delete the next node from the list. */ + delete_list(&pos->list); + vg_lite_os_free(pos); + } + break; + } + + /* Check if the previous node is free. */ + pos = node; + for (pos = (heap_node_t *)pos->list.prev; + &pos->list != &device->heap.list; + pos = (heap_node_t *)pos->list.prev) { + if (pos->status == 0) { + /* Merge the nodes. */ + pos->size += node->size; + if(pos->offset > node->offset) + pos->offset = node->offset; + /* Delete the current node from the list. */ + delete_list(&node->list); + vg_lite_os_free(node); + } + break; + } + /* when release command buffer node and ts buffer node to exit,release the linked list*/ + if(device->heap.list.next == device->heap.list.prev) { + delete_list(&pos->list); + vg_lite_os_free(pos); + } +} + +void vg_lite_hal_free_os_heap(void) +{ + struct heap_node *pos, *n; + + /* Check for valid device. */ + if (device != NULL) { + /* Process each node. */ + for (pos = (heap_node_t *)device->heap.list.next, + n = (heap_node_t *)pos->list.next; + &pos->list != &device->heap.list; + pos = n, n = (heap_node_t *)n->list.next) { + /* Remove it from the linked list. */ + delete_list(&pos->list); + /* Free up the memory. */ + vg_lite_os_free(pos); + } + } +} + +/* Portable: read register value. */ +uint32_t vg_lite_hal_peek(uint32_t address) +{ + /* Read data from the GPU register. */ + return (uint32_t) (*(volatile uint32_t *) (device->gpu + address)); +} + +/* Portable: write register. */ +void vg_lite_hal_poke(uint32_t address, uint32_t data) +{ + /* Write data to the GPU register. */ + uint32_t *LocalAddr = (uint32_t *)(device->gpu + address); + *LocalAddr = data; +} + +vg_lite_error_t vg_lite_hal_query_mem(vg_lite_kernel_mem_t *mem) +{ + if(device != NULL){ + mem->bytes = device->heap.free; + return VG_LITE_SUCCESS; + } + mem->bytes = 0; + return VG_LITE_NO_CONTEXT; +} + +void vg_lite_IRQHandler(void) +{ + vg_lite_os_IRQHandler(); +} + +int32_t vg_lite_hal_wait_interrupt(uint32_t timeout, uint32_t mask, uint32_t * value) +{ + return vg_lite_os_wait_interrupt(timeout,mask,value); +} + +void * vg_lite_hal_map(unsigned long bytes, void * logical, uint32_t physical, uint32_t * gpu) +{ + + (void) bytes; + (void) logical; + (void) physical; + (void) gpu; + return (void *)0; +} + +void vg_lite_hal_unmap(void * handle) +{ + + (void) handle; +} + +#if !defined(VG_DRIVER_SINGLE_THREAD) +vg_lite_error_t vg_lite_hal_submit(uint32_t context,uint32_t physical, uint32_t offset, uint32_t size, vg_lite_os_async_event_t *event) +{ + return (vg_lite_error_t)vg_lite_os_submit(context,physical,offset,size,event); +} + +vg_lite_error_t vg_lite_hal_wait(uint32_t timeout, vg_lite_os_async_event_t *event) +{ + return (vg_lite_error_t)vg_lite_os_wait(timeout,event); +} +#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ + +static void vg_lite_exit(void) +{ + heap_node_t * pos; + heap_node_t * n; + + /* Check for valid device. */ + if (device != NULL) { + /* TODO: unmap register mem should be unnecessary. */ + device->gpu = 0; + + /* Process each node. */ + for (pos = (heap_node_t *)device->heap.list.next, n = (heap_node_t *)pos->list.next; + &pos->list != &device->heap.list; + pos = n, n = (heap_node_t *)n->list.next) { + /* Remove it from the linked list. */ + delete_list(&pos->list); + + /* Free up the memory. */ + vg_lite_os_free(pos); + } + + /* Free up the device structure. */ + vg_lite_os_free(device); + } +} + +static int vg_lite_init(void) +{ + heap_node_t * node; + + /* Initialize memory and objects ***************************************/ + /* Create device structure. */ + device = &Device; + + /* Zero out the enture structure. */ + _memset(device, 0, sizeof(struct vg_lite_device)); + + /* Setup register memory. **********************************************/ + device->gpu = registerMemBase; + + /* Initialize contiguous memory. ***************************************/ + /* Allocate the contiguous memory. */ + device->heap_size = heap_size; + device->contiguous = (volatile void *)contiguousMem; + _memset((void *)device->contiguous, 0, heap_size); + /* Make 64byte aligned. */ + while ((((uint32_t)device->contiguous) & 63) != 0) + { + device->contiguous = ((unsigned char*) device->contiguous) + 4; + device->heap_size -= 4; + } + + /* Check if we allocated any contiguous memory or not. */ + if (device->contiguous == NULL) { + vg_lite_exit(); + return -1; + } + + device->virtual = (void *)device->contiguous; + device->physical = gpuMemBase + (uint32_t)device->virtual; + device->size = device->heap_size; + + /* Create the heap. */ + INIT_LIST_HEAD(&device->heap.list); + device->heap.free = device->size; + + node = (heap_node_t *)vg_lite_os_malloc(sizeof(heap_node_t)); + + if (node == NULL) { + vg_lite_exit(); + return -1; + } + node->offset = 0; + node->size = device->size; + node->status = 0; + add_list(&node->list, &device->heap.list); +#if defined(VG_DRIVER_SINGLE_THREAD) +#if !_BAREMETAL /*for rt500*/ + device->int_queue = xSemaphoreCreateBinary(); + device->int_flags = 0; +#endif +#endif /* VG_DRIVER_SINGLE_THREAD */ + /* Success. */ + return 0; +} diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLiteKernel/rtos/vg_lite_platform.h b/bsp/sdk_overlay/middleware/vglite/VGLiteKernel/rtos/vg_lite_platform.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLiteKernel/rtos/vg_lite_platform.h rename to bsp/sdk_overlay/middleware/vglite/VGLiteKernel/rtos/vg_lite_platform.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_hw.h b/bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_hw.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_hw.h rename to bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_hw.h diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_kernel.c b/bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_kernel.c similarity index 94% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_kernel.c rename to bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_kernel.c index cb4c654..8468675 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_kernel.c +++ b/bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_kernel.c @@ -41,6 +41,18 @@ static vg_lite_kernel_initialize_t ts_initialize = {0}; static uint8_t ts_init = 0; #endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ +#if defined(VG_DRIVER_SINGLE_THREAD) + +#define VG_LITE_OS_LOCK() VG_LITE_SUCCESS +#define VG_LITE_OS_UNLOCK() + +#else + +#define VG_LITE_OS_LOCK() vg_lite_os_lock() +#define VG_LITE_OS_UNLOCK() vg_lite_os_unlock() + +#endif /* VG_DRIVER_SINGLE_THREAD */ + static vg_lite_error_t do_terminate(vg_lite_kernel_terminate_t * data); static void soft_reset(void); @@ -49,9 +61,9 @@ static void gpu(int enable) { vg_lite_hw_clock_control_t value; uint32_t reset_timer = 2; -#ifndef VGLITE_DISABLE_AUTO_CLOCK_GATING +#ifdef VG_GPU_AUTO_CLOCK_GATING uint32_t temp; -#endif +#endif /* VG_GPU_AUTO_CLOCK_GATING */ const uint32_t reset_timer_limit = 1000; if (enable) { @@ -76,12 +88,12 @@ static void gpu(int enable) vg_lite_hal_delay(reset_timer); reset_timer *= 2; // If reset failed, try again with a longer wait. Need to check why if dead lopp happens here. } while (!VG_LITE_KERNEL_IS_GPU_IDLE()); -#ifndef VGLITE_DISABLE_AUTO_CLOCK_GATING +#ifdef VG_GPU_AUTO_CLOCK_GATING temp = vg_lite_hal_peek(VG_LITE_HW_POWER_CONTROL); temp |= 0x1; vg_lite_hal_poke(VG_LITE_HW_POWER_CONTROL, temp); vg_lite_hal_delay(1); -#endif +#endif /* VG_GPU_AUTO_CLOCK_GATING */ } else { @@ -354,7 +366,7 @@ static vg_lite_error_t init_vglite(vg_lite_kernel_initialize_t * data) } } - if((error = (vg_lite_error_t)vg_lite_os_lock()) == VG_LITE_SUCCESS){ + if((error = (vg_lite_error_t)VG_LITE_OS_LOCK()) == VG_LITE_SUCCESS){ ++task_num; for(semaphore_id = 0; semaphore_id < TASK_LENGTH ; semaphore_id++) { @@ -371,7 +383,7 @@ static vg_lite_error_t init_vglite(vg_lite_kernel_initialize_t * data) break; } } - vg_lite_os_unlock(); + VG_LITE_OS_UNLOCK(); } else return error; @@ -392,12 +404,12 @@ static vg_lite_error_t init_vglite(vg_lite_kernel_initialize_t * data) for (i = 0; i < CMDBUF_COUNT; i ++) { /* Allocate the memory. */ - vg_lite_os_lock(); + VG_LITE_OS_LOCK(); error = vg_lite_hal_allocate_contiguous(data->command_buffer_size, &context->command_buffer_logical[i], &context->command_buffer_physical[i], &context->command_buffer[i]); - vg_lite_os_unlock(); + VG_LITE_OS_UNLOCK(); if (error != VG_LITE_SUCCESS) { /* Free any allocated memory. */ @@ -420,12 +432,12 @@ static vg_lite_error_t init_vglite(vg_lite_kernel_initialize_t * data) for (i = 0; i < CMDBUF_COUNT; i ++) { /* Allocate the memory. */ - vg_lite_os_lock(); + VG_LITE_OS_LOCK(); error = vg_lite_hal_allocate_contiguous(data->context_buffer_size, &context->context_buffer_logical[i], &context->context_buffer_physical[i], &context->context_buffer[i]); - vg_lite_os_unlock(); + VG_LITE_OS_UNLOCK(); if (error != VG_LITE_SUCCESS) { /* Free any allocated memory. */ @@ -473,12 +485,12 @@ static vg_lite_error_t init_vglite(vg_lite_kernel_initialize_t * data) l2_size = data->capabilities.cap.l2_cache ? VG_LITE_ALIGN(VG_LITE_ALIGN(l1_size / 32, 64) / 8, 64) : 0; /* Allocate the memory. */ - vg_lite_os_lock(); + VG_LITE_OS_LOCK(); error = vg_lite_hal_allocate_contiguous(buffer_size + l1_size + l2_size, &context->tessellation_buffer_logical, &context->tessellation_buffer_physical, &context->tessellation_buffer); - vg_lite_os_unlock(); + VG_LITE_OS_UNLOCK(); if (error != VG_LITE_SUCCESS) { /* Free any allocated memory. */ @@ -646,10 +658,10 @@ static vg_lite_error_t terminate_vglite(vg_lite_kernel_terminate_t * data) context->context_buffer[1] = NULL; } - if((error = (vg_lite_error_t)vg_lite_os_lock()) == VG_LITE_SUCCESS){ + if((error = (vg_lite_error_t)VG_LITE_OS_LOCK()) == VG_LITE_SUCCESS){ --task_num; --s_reference; - vg_lite_os_unlock(); + VG_LITE_OS_UNLOCK(); } else return error; @@ -703,15 +715,11 @@ static vg_lite_error_t do_allocate(vg_lite_kernel_allocate_t * data) { vg_lite_error_t error; -#if defined(VG_DRIVER_SINGLE_THREAD) - error = vg_lite_hal_allocate_contiguous(data->bytes, &data->memory, &data->memory_gpu, &data->memory_handle); -#else - if((error = (vg_lite_error_t)vg_lite_os_lock()) == VG_LITE_SUCCESS) + if((error = (vg_lite_error_t)VG_LITE_OS_LOCK()) == VG_LITE_SUCCESS) { error = vg_lite_hal_allocate_contiguous(data->bytes, &data->memory, &data->memory_gpu, &data->memory_handle); - vg_lite_os_unlock(); + VG_LITE_OS_UNLOCK(); } -#endif /* VG_DRIVER_SINGLE_THREAD */ return error; } @@ -928,12 +936,12 @@ static void soft_reset(void) #if !defined(VG_DRIVER_SINGLE_THREAD) static vg_lite_error_t do_mutex_lock() { - return (vg_lite_error_t)vg_lite_os_lock(); + return (vg_lite_error_t)VG_LITE_OS_LOCK(); } static vg_lite_error_t do_mutex_unlock() { - return (vg_lite_error_t)vg_lite_os_unlock(); + return (vg_lite_error_t)VG_LITE_OS_UNLOCK(); } #endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_kernel.h b/bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_kernel.h similarity index 95% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_kernel.h rename to bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_kernel.h index 04dc5f6..c119637 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_kernel.h +++ b/bsp/sdk_overlay/middleware/vglite/VGLiteKernel/vg_lite_kernel.h @@ -40,9 +40,7 @@ #define MAX_CONTIGUOUS_SIZE 0x02000000 #define VG_LITE_INFINITE 0xFFFFFFFF -#if !defined(VG_DRIVER_SINGLE_THREAD) #define VG_LITE_MAX_WAIT_TIME 0x130000 -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ #define CMDBUF_COUNT 2 #define VG_LITE_ALIGN(number, alignment) \ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/inc/Elm.h b/bsp/sdk_overlay/middleware/vglite/elementary/inc/Elm.h similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/inc/Elm.h rename to bsp/sdk_overlay/middleware/vglite/elementary/inc/Elm.h index cb8c91f..28529d3 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/inc/Elm.h +++ b/bsp/sdk_overlay/middleware/vglite/elementary/inc/Elm.h @@ -1,681 +1,681 @@ -/**************************************************************************** -* -* Copyright 2012 - 2020 Vivante Corporation, Santa Clara, California. -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -#ifndef ELM_H_ -#define ELM_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define ELM_VERSION 0x00010000 /* Current Version: 1.0. */ -#define ELM_NULL_HANDLE 0 /*! NULL object handle, represent a void object. */ - - /*! - @typedef ELM_EVO_PROP_BIT - evo property bits to control evo manipulation. - */ - typedef enum { - ELM_PROP_ROTATE_BIT = 1 << 0, /*! rotate bit of evo/ego/ebo transformation property. */ - ELM_PROP_TRANSFER_BIT = 1 << 1, /*! transfer bit of evo/ego/ebo transformation property. */ - ELM_PROP_SCALE_BIT = 1 << 2, /*! scale bit of evo/ego/ebo transformation property. */ - ELM_PROP_BLEND_BIT = 1 << 3, /*! blending bit of evo/ebo rendering property. */ - ELM_PROP_QUALITY_BIT = 1 << 4, /*! quality bit of evo/ebo rendering property. */ - ELM_PROP_FILL_BIT = 1 << 5, /*! fill rule bit of evo rendering property. */ - ELM_PROP_COLOR_BIT = 1 << 6, /*! fill color bit of evo rendering property. */ - ELM_PROP_PAINT_BIT = 1 << 7, /*! paint type bit of evo. */ - ELM_PROP_ALL_BIT = 0xFFFFFFFF, /*! all transformation property bits of evo. */ - } ELM_EVO_PROP_BIT; - - /*! - @typedef ELM_EVO_BLEND - The blending property of the evo object when it's drawn. - D is Destination color, S is Source color; - Da is Destination alpha, S is Source alpha. - */ - typedef enum { - ELM_BLEND_NONE = 0, /*! D = S. */ - ELM_BLEND_SRC_OVER, /*! D = S + (1 - Sa) * D */ - ELM_BLEND_DST_OVER, /*! D = (1 - Da) * S + D */ - ELM_BLEND_SRC_IN, /*! D = Da * S */ - ELM_BLEND_DST_IN, /*! D = Sa * D */ - ELM_BLEND_SCR, /*! D = S + D - S * D */ - ELM_BLEND_MUL, /*! D = S * (1 - Da) + D * (1 - Sa) + S * D */ - ELM_BLEND_ADD, /*! S + D */ - ELM_BLEND_SUB /*! D * (1 - S) */ - } ELM_BLEND; - - /*! - @typedef ELM_EVO_QUALITY - The drawing quality of the evo object. - */ - typedef enum { - ELM_QUALITY_LOW = 0, /*! NOAA for evo, POINT SAMPLE for ebo. */ - ELM_QUALITY_MED = 1, /*! 2XAA for evo, LINEAR SAMPLE for ebo. */ - ELM_QULIATY_HI = 2, /*! 4XAA for evo, BI-LINEAR SAMPLE for ebo. */ - } ELM_QUALITY; - - /*! - @typedef ELM_PAINT_TYPE - Those are types for evo fill paint. - COLOR means solid color fill; - PATTERN means fill with an image (evo); - GRADIENT means fill with linear gradient. - */ - typedef enum { - ELM_PAINT_COLOR = 0, /*! Paint evo with solid color */ - ELM_PAINT_PATTERN = 1, /*! Paint evo with ebo */ - ELM_PAINT_GRADIENT = 2, /*! Paint evo with a linear gradient built-in evo object */ - ELM_PAINT_RADIAL_GRADIENT = 3, /*! Paint evo with a radial gradient built-in evo object */ - ELM_PAINT_TEXT = 4, /*! Paint evo-text */ - } ELM_PAINT_TYPE; - - /*! - @typedef ELM_PATTERN_MODE - Those are enum types for pattern fill mode. - COLOR means fill the area outside the pattern with a solid color; - PAD means extend the border color to the area outside the pattern. - */ - typedef enum { - ELM_PATTERN_MODE_COLOR = 0, - ELM_PATTERN_MODE_PAD = 1, - } ELM_PATTERN_MODE; - - /*! - @typedef ELM_EVO_FILL - The filling rule of for an evo object. - EO = EVEN_ODD; - NZ = NONE_ZERO; - */ - typedef enum { - ELM_EVO_FILL_NZ = 0, /*! none-zero fill rule */ - ELM_EVO_FILL_EO = 1, /*! Even-odd fill rule */ - } ELM_EVO_FILL; - - /*! - @typedef ELM_EVO_TYPE - the type of an evo object. could be pathes, images, or a group which contains other EVOs. - */ - typedef enum { - ELM_OBJECT_TYPE_EVO = 0, /*! elementary vector object, representing a path object. */ - ELM_OBJECT_TYPE_EGO = 1, /*! elementary group object, containing multiple path objects. */ - ELM_OBJECT_TYPE_EBO = 2, /*! elementary bitmap object, representing image data. */ - ELM_OBJECT_TYPE_BUF = 3, /*! rendering buffer object, created by application. */ - ELM_OBJECT_TYPE_FONT = 4, /*! elementary font object, representing character data. */ - ELM_OBJECT_TYPE_TEXT = 5, /*! elementary text object, representing text data. */ - } ELM_OBJECT_TYPE; - - /*! - @typedef ELM_BUFFER_FORMAT - Enumeration for buffer format, all format name definiton is sequenced from LSB to MSB. - */ - typedef enum { - ELM_BUFFER_FORMAT_RGBA8888, /*! 32-bit RGBA format with 8 bits per color channel. Red is in bits 7:0, green in bits 15:8, blue in - bits 23:16, and the alpha channel is in bits 31:24. */ - ELM_BUFFER_FORMAT_BGRA8888, /*! 32-bit RGBA format with 8 bits per color channel. Red is in bits 23:16, green in bits 15:8, blue in - bits 7:0, and the alpha channel is in bits 31:24. */ - ELM_BUFFER_FORMAT_RGBX8888, /*! 32-bit RGBX format with 8 bits per color channel. Red is in bits 7:0, green in bits 15:8, blue in - bits 23:16, and the x channel is in bits 31:24. */ - ELM_BUFFER_FORMAT_BGRX8888, /*! 32-bit RGBX format with 8 bits per color channel. Red is in bits 23:16, green in bits 15:8, blue in - bits 7:0, and the x channel is in bits 31:24. */ - ELM_BUFFER_FORMAT_RGB565, /*! 16-bit RGB format with 5 and 6 bits per color channel. Red is in bits 4:0, green in bits 10:5, and - the blue color channel is in bits 15:11. */ - ELM_BUFFER_FORMAT_BGR565, /*! 16-bit RGB format with 5 and 6 bits per color channel. Red is in bits 15:11, green in bits 10:5, - and the blue color channel is in bits 4:0. */ - ELM_BUFFER_FORMAT_RGBA4444, /*! 16-bit RGBA format with 4 bits per color channel. Red is in bits 3:0, green in bits 7:4, blue in - bits 11:8 and the alpha channel is in bits 15:12. */ - ELM_BUFFER_FORMAT_BGRA4444, /*! 16-bit RGBA format with 4 bits per color channel. Red is in bits 11:8, green in bits 7:4, blue in - bits 3:0 and the alpha channel is in bits 15:12. */ - ELM_BUFFER_FORMAT_BGRA5551, /*! 16-bit RGBA format with 4 bits per color channel. Red is in bits 14:10, green in bits 9:5, blue in - bits 4:0 and the alpha channel is in bit 15:15. */ - ELM_BUFFER_FORMAT_INDEX_1, /*! 1-bit indexed format. */ - ELM_BUFFER_FORMAT_INDEX_2, /*! 2-bits indexed format. */ - ELM_BUFFER_FORMAT_INDEX_4, /*! 4-bits indexed format. */ - ELM_BUFFER_FORMAT_INDEX_8, /*! 8-bits indexed format. */ - } ELM_BUFFER_FORMAT; - - /*! - @typedef ElmHandle - common handle type for object reference. - */ - typedef unsigned int ElmHandle; - - /*! - @typedef ElmVecObj - evo object handle (elemtry vector object). Created from an external binary evo file. - */ - typedef ElmHandle ElmVecObj; - - /*! - @typedef ElmBitmapObj - ebo object handle (elementry image object). Created from an external ebo file. - */ - typedef ElmHandle ElmBitmapObj; - - /*! - @typedef ElmGroupObj - group object handle. Create from an external ego file. - */ - typedef ElmHandle ElmGroupObj; - - /*! - @typedef ElmBuffer - render buffer object handle. - */ - typedef ElmHandle ElmBuffer; - - #define TRUE 1 - #define FALSE 0 - /*! - @typedef BOOL - boolean type define. - */ - typedef unsigned int BOOL; - - /*! - @abstract Initialize Elementary context. - - @discussion - It should be called as the first function of Elemenatary libary, which initializes the library. Currently - Elementary library doesn't support context concept, neigher multi-threading. Elementary library defines - origin of coordinate system is at top-left. - - @param none - - @return none - */ - BOOL ElmInitialize(uint32_t width, uint32_t height); - - /*! - @abstract Terminate Elementary context. - - @discussion - This should be called when an app exits. It frees all the resource. - - @param none - - @return none - */ - void ElmTerminate(void); - - /*! - @abstract Create an elementary object from an existing binary file. - - @discussion - This function creates an elementary object from the file whose file name is specified by param name. - Caller must match type with the binary file, otherwise create mail fail by returning ELM_NULL_HANDLE. - - @param type - Specify what type of object to be created. - - @param name - The name of the binary resource file. - - @return ElmHandle - An object handle depending on the corresponding type. If type mismatches, it - returns ELM_NULL_HANDLE. - */ - ElmHandle ElmCreateObjectFromFile(ELM_OBJECT_TYPE type, const char *name); - - /*! - @abstract Create an elementary object from build-in data within the appplication. - - @discussion - This function creates an elementar object from local data pointer, which is specially useful for environment without filesystem support. - - @param type - Specify what type of object to be created. - - @param data - The pointer to the binary data which has exactly same layout as external resource file. - - @return ElmHandle - An object handle depending on the corresponding type. If type mismatches with the binary data, it - returns ELM_NULL_HANDLE. - */ - ElmHandle ElmCreateObjectFromData(ELM_OBJECT_TYPE type, void *data, int size); - - /*! - @abstract Rotate a graphics object with centain degree - - @discussion - This function sets an evo/ebo/ego object rotated with specified angle. Without reset, these setting will be - accumulated. - - @param obj - The graphics object will be rotated. - - @param angle - A radian value to be applied on the evo object. - - @return bool - Rotate is set successfully. - */ - BOOL ElmRotate(ElmHandle obj, float angle); - - /*! - @abstract Transfer an graphics object at different directions. - - @discussion - This function put an evo/ebo/ego object away at different directions. Without reset, the setting will be - accumulated. - - @param obj - The graphics object will be transfered. - - @param x - The units in pixel of X direction. - - @param y - The units in pixel of Y direction. - - @return bool - Transfer is set successfully. - */ - BOOL ElmTransfer(ElmHandle obj, int x, int y); - - /*! - @abstract Scale an graphics object at different directions. - - @discussion - This function scale up or down an evo/ego/ebo object at different directions. Without reset, the setting will - be accumateled. - - @param obj - The graphics object which is targeted to manipulate. - - @param x - The scale ratio in X direction. - - @param y - The scale ratio in Y direction. - - @return bool - Scale is set succefully. - */ - BOOL ElmScale(ElmHandle obj, float x, float y); - - /*! - @abstract Reset the attribute of a graphics object for specified property bit. - - @discussion - This funcion resets specified property for an elementary object. It can be applied all types of objects. - But some properties are only valid for centain types of objects. If the function is called to reset an invalid - property for this type of object, it will be siliently ignored. - After reset, the specifed property of an evo/ebo/ego object is set to the initial state. The initial states are decided - by the binary resource file. The resource creator should set right value for all properties if they want to directly render - the object without any adjustment in application. There is one issue, at present, application has no way to query current value - of each property, is it required? - - @param obj - The graphics object which is targeted to manipulate. - - @param mask - Specify which property or properties need to reset to initial value. - - @return bool - Reset is done successfully. If some mask is not valid for this type of object, it would return false. - */ - BOOL ElmReset(ElmHandle obj, ELM_EVO_PROP_BIT mask); - - /*! - @abstract Draw a graphics object onto current render target - - @discussion - This is an enssentail function to do the real job, it takes all current setting of the elementary object and - render into theb buffer target. - - @param buffer - The render target that an elmentary object will be rendered into. - - @param obj - The elmentary object will be draw into render target. - - @return bool - The draw operation for this elmentary object is sucessful. - */ - BOOL ElmDraw(ElmBuffer buffer, ElmHandle object); - - /*! - @abstract Set the rendering quality of an graphics object. - - @discussion - This function sets the rendering quality of an evo/ebo object. Avaliable quality setting contains: - ELM_EVO_QUALITY_LOW, ELM_EVO_QUALITY_MED, ELM_EVO_QUALITY_HI. This function is only applied to an evo or an ebo. - Group object can't be set quality. It always use the setting from its binary. - - @param obj - The elementary object. - - @param quality - The quality enum. - - @return bool - The operation for this object is sucessful, for group object and invalid enum, would return false. - */ - BOOL ElmSetQuality(ElmHandle obj, ELM_QUALITY quality); - - /*! - @abstract Set the fill rule of an evo object. - - @discussion - This function sets the fill rule of an elementary object. Avaliable quality setting contains: - ELM_EVO_EO, ELM_EVO_NZ. It only applies to evo object. - - @param evo - The evo object. - - @param fill - The fill rule enum. - - @return bool - The operation for this evo is sucessful. For non-evo object an ENUM is not a valid enum, would return false. - */ - BOOL ElmSetFill(ElmVecObj evo, ELM_EVO_FILL fill); - - /*! - @abstract Set the blending mode of an evo/ebo object. - - @discussion - This function sets the blending mode of an evo/ebo object. It's not applied to group object. - - @param obj - The graphics object. - - @param blend - The blending mode enum. - - @return bool - The operation for this evo/ebo is sucessful. If object is a group object or blend mode is not a legal one, it would return false. - */ - BOOL ElmSetBlend(ElmHandle obj, ELM_BLEND blend); - - /*! - @abstract Set the solid fill color of an evo object. - - @discussion - This function sets the solid fill color of an evo object. - - @param evo - The evo object. - - @param color - The uint32 color value in rgba order. - - @return bool - The operation for this evo is sucessful. If the object is not a evo object, it would return false. - */ - BOOL ElmSetColor(ElmVecObj evo, uint32_t color); - - /*! - @abstract Set the image paint fill of an evo. - - @discussion - This function sets the image pattern for filling an evo. The image pattern - is a loaded ebo. The ebo's transformation is applied when drawing the evo. - - @param evo - The evo object. - - @param pattern - The image pattern to be set for the evo. - - @return bool - The operation is successful or not. - */ - BOOL ElmSetPattern(ElmVecObj evo, ElmBitmapObj pattern); - - /*! - @abstract Set the image paint fill of an evo. - - @discussion - This function sets the image pattern for filling an evo. The image pattern - is a loaded ebo. The ebo's transformation is applied when drawing the evo. - - @param evo - The evo object. - - @param pattern - The image pattern to be set for the evo. - - @return bool - The operation is successful or not. - */ - BOOL ElmSetPatternMode(ElmVecObj evo, ELM_PATTERN_MODE mode, uint32_t color); - - /*! - @abstract Set the paint type of an evo. - - @discussion - This function selects the paint type for evo to use. An evo may have 3 types - of paint: COLOR, PATTERN, and LINEAR GRADIENT. The Linear graident is always - a built-in resource, which can not be altered. If a binary resource doesn't - have built-in gradient paint resource, it can't be selected as the paint source. - Solid color is also a built-in attribute, but it can be changed by ElmSetColor(). - Paint with a pattern always need an external ebo object, which is impossible - to be embedded in resource file,i.e. ebo object. Before select paint type to - be PATTERN, ElmSetPattern() must be called to attach an EBO to an EVO. - - @param evo - The evo object. - - @param type - The paint type to be set for the evo. - - @return bool - The operation is successful or not. - If the corresponding type is not avaiable for the evo, it returns false and - type paint type falls back to COLOR. - */ - BOOL ElmSetPaintType(ElmVecObj evo, ELM_PAINT_TYPE type); - - /*! - @abstract Create internal render buffer. - - @discussion - This functiois is to create an internal render buffer for Elementary rendering, ussually it's not for direct display. - The buffer which is displayed on pannel is wrapped up by another API, whose address is managed by display controller side. - - @param width - The buffer's width. - - @param height - The buffer's height. - - @param format - The buffer's format, check enumeration of ELM_BUFFER_FORMAT. - - @return - The buffer handle. - */ - ElmBuffer ElmCreateBuffer(unsigned int width, unsigned int height, ELM_BUFFER_FORMAT format); - - /*! - @abstract Wrap a customized buffer. - - @discussion - The application may wrap a user created buffer by giving the information of - the buffer including the size, the memory addresses and format. E.g., the - application can wrap a system framebuffer thus ELM can directly render onto - the screen. - - @return - The buffer handle. - */ - ElmBuffer ElmWrapBuffer(int width, int height, int stride, - void *logical, uint32_t physical, - ELM_BUFFER_FORMAT format); - - /*! - @abstract Get buffer address. - - @discussion - The function is to get the address of ElmBuffer. - - @return - The buffer address. - */ - - uint32_t ElmGetBufferAddress(ElmBuffer buffer); - - /*! - @abstract Destroy a render buffer. - - @discussion - This function is to release all internal resource inside Elementary libary belonging to this buffer. - Applicatoin need make sure the buffer is not being used by elmentary library any more when calling this function. - - @param buffer - The render buffer handle - - @return - If destroying is completed successfully. - */ - BOOL ElmDestroyBuffer(ElmBuffer buffer); - - /*! - @abstract Save a buffer to PNG file. - - @discussion - This function can save the buffer into a PNG file. - - @param buffer - The render buffer handle. - - @param name - The name of the PNG file to sve. - - @return - Save OK or NOT. - - */ - BOOL ElmSaveBuffer(ElmBuffer buffer, const char *name); - - /*! - @abstract Clear a render buffer with specified color and dimension. - - @discussion - This function is called to clear full or partial of the buffer. If the rectangle is out of buffer space, the intersect portion will be cleared. - - @param buffer - A render buffer handle. - - @param color - Clear color value. - - @param x - x origin of partical clear rectangle. - - @param y - y origin of partial clear rectangle. - - @param width - width of partical clear rectangle. - - @param height - height of partical clear rectangle. - - @param full - Flag to indicate a full buffer clear. If true, the dimension parameters will be ignored. - - @return bool - Indicate the clear operation is set up correctly. - */ - BOOL ElmClear(ElmBuffer buffer, uint32_t color, uint32_t x, uint32_t y, uint32_t width, uint32_t height, BOOL full); - - /*! - @abstract Destroy an ELM object. - - @discussion - This function is to release all internal resource inside Elementary libary belonging to this object. - Applicatoin need make sure the object is not being used by elmentary library any more when calling this function. - If an EBO is being destroyed and it's attached to one EVO, it need to guarantee that EVO is not being used by elementary library too. - - @param object - The object handle - - @return - If destroying is completed successfully. - */ - BOOL ElmDestroyObject(ElmHandle object); - - /*! - @abstract Finish all rendering on GPU issued before this call. - - @discussion - This function tells the engine that it has finished the frame data and GPU can draw it now. It's blocked until GPU rendering done. - - @return - If the opeartion is successfully done or not. - */ - BOOL ElmFinish(); - - /*! - @abstract Flush all rendering command to GPU issued before this call. - - @discussion - This function tells the engine to start kicking off command to GPU side, it will return immediately after firing off GPU. - - @return - If the opeartion is successfully done or not. - */ - BOOL ElmFlush(); - - /*! - @abstract Query the paint color of an evo object. - */ - BOOL ElmGetColor(ElmVecObj evoHandle,uint32_t *color); - - /*! - @abstract Query the vectory path count of an EGO object. If the given object - is an evo/ebo, the count is 0. - */ - uint32_t ElmGetVectorCount(ElmHandle handle); - - /*! - @abstract Query the type of an object (by handle). - */ - ELM_OBJECT_TYPE ElmGetObjectType(ElmHandle handle); - - /*! - @abstract Set the current vectory object index to operate on. - */ - BOOL ElmSetCurrentVector(int32_t id); - - BOOL ElmScalePaint(ElmHandle handle, float sx, float sy); - BOOL ElmRotatePaint(ElmHandle handle, float degrees); - BOOL ElmTranslatePaint(ElmHandle handle, float tx, float ty); - - /*! - @abstract Get handle of the framebuffer. - */ - ElmBuffer ElmGetBuffer(vg_lite_buffer_t *buffer); - -#ifdef __cplusplus -} -#endif -#endif /* ELM_H_ */ +/**************************************************************************** +* +* Copyright 2012 - 2020 Vivante Corporation, Santa Clara, California. +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +#ifndef ELM_H_ +#define ELM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define ELM_VERSION 0x00010000 /* Current Version: 1.0. */ +#define ELM_NULL_HANDLE 0 /*! NULL object handle, represent a void object. */ + + /*! + @typedef ELM_EVO_PROP_BIT + evo property bits to control evo manipulation. + */ + typedef enum { + ELM_PROP_ROTATE_BIT = 1 << 0, /*! rotate bit of evo/ego/ebo transformation property. */ + ELM_PROP_TRANSFER_BIT = 1 << 1, /*! transfer bit of evo/ego/ebo transformation property. */ + ELM_PROP_SCALE_BIT = 1 << 2, /*! scale bit of evo/ego/ebo transformation property. */ + ELM_PROP_BLEND_BIT = 1 << 3, /*! blending bit of evo/ebo rendering property. */ + ELM_PROP_QUALITY_BIT = 1 << 4, /*! quality bit of evo/ebo rendering property. */ + ELM_PROP_FILL_BIT = 1 << 5, /*! fill rule bit of evo rendering property. */ + ELM_PROP_COLOR_BIT = 1 << 6, /*! fill color bit of evo rendering property. */ + ELM_PROP_PAINT_BIT = 1 << 7, /*! paint type bit of evo. */ + ELM_PROP_ALL_BIT = 0xFFFFFFFF, /*! all transformation property bits of evo. */ + } ELM_EVO_PROP_BIT; + + /*! + @typedef ELM_EVO_BLEND + The blending property of the evo object when it's drawn. + D is Destination color, S is Source color; + Da is Destination alpha, S is Source alpha. + */ + typedef enum { + ELM_BLEND_NONE = 0, /*! D = S. */ + ELM_BLEND_SRC_OVER, /*! D = S + (1 - Sa) * D */ + ELM_BLEND_DST_OVER, /*! D = (1 - Da) * S + D */ + ELM_BLEND_SRC_IN, /*! D = Da * S */ + ELM_BLEND_DST_IN, /*! D = Sa * D */ + ELM_BLEND_SCR, /*! D = S + D - S * D */ + ELM_BLEND_MUL, /*! D = S * (1 - Da) + D * (1 - Sa) + S * D */ + ELM_BLEND_ADD, /*! S + D */ + ELM_BLEND_SUB /*! D * (1 - S) */ + } ELM_BLEND; + + /*! + @typedef ELM_EVO_QUALITY + The drawing quality of the evo object. + */ + typedef enum { + ELM_QUALITY_LOW = 0, /*! NOAA for evo, POINT SAMPLE for ebo. */ + ELM_QUALITY_MED = 1, /*! 2XAA for evo, LINEAR SAMPLE for ebo. */ + ELM_QULIATY_HI = 2, /*! 4XAA for evo, BI-LINEAR SAMPLE for ebo. */ + } ELM_QUALITY; + + /*! + @typedef ELM_PAINT_TYPE + Those are types for evo fill paint. + COLOR means solid color fill; + PATTERN means fill with an image (evo); + GRADIENT means fill with linear gradient. + */ + typedef enum { + ELM_PAINT_COLOR = 0, /*! Paint evo with solid color */ + ELM_PAINT_PATTERN = 1, /*! Paint evo with ebo */ + ELM_PAINT_GRADIENT = 2, /*! Paint evo with a linear gradient built-in evo object */ + ELM_PAINT_RADIAL_GRADIENT = 3, /*! Paint evo with a radial gradient built-in evo object */ + ELM_PAINT_TEXT = 4, /*! Paint evo-text */ + } ELM_PAINT_TYPE; + + /*! + @typedef ELM_PATTERN_MODE + Those are enum types for pattern fill mode. + COLOR means fill the area outside the pattern with a solid color; + PAD means extend the border color to the area outside the pattern. + */ + typedef enum { + ELM_PATTERN_MODE_COLOR = 0, + ELM_PATTERN_MODE_PAD = 1, + } ELM_PATTERN_MODE; + + /*! + @typedef ELM_EVO_FILL + The filling rule of for an evo object. + EO = EVEN_ODD; + NZ = NONE_ZERO; + */ + typedef enum { + ELM_EVO_FILL_NZ = 0, /*! none-zero fill rule */ + ELM_EVO_FILL_EO = 1, /*! Even-odd fill rule */ + } ELM_EVO_FILL; + + /*! + @typedef ELM_EVO_TYPE + the type of an evo object. could be pathes, images, or a group which contains other EVOs. + */ + typedef enum { + ELM_OBJECT_TYPE_EVO = 0, /*! elementary vector object, representing a path object. */ + ELM_OBJECT_TYPE_EGO = 1, /*! elementary group object, containing multiple path objects. */ + ELM_OBJECT_TYPE_EBO = 2, /*! elementary bitmap object, representing image data. */ + ELM_OBJECT_TYPE_BUF = 3, /*! rendering buffer object, created by application. */ + ELM_OBJECT_TYPE_FONT = 4, /*! elementary font object, representing character data. */ + ELM_OBJECT_TYPE_TEXT = 5, /*! elementary text object, representing text data. */ + } ELM_OBJECT_TYPE; + + /*! + @typedef ELM_BUFFER_FORMAT + Enumeration for buffer format, all format name definiton is sequenced from LSB to MSB. + */ + typedef enum { + ELM_BUFFER_FORMAT_RGBA8888, /*! 32-bit RGBA format with 8 bits per color channel. Red is in bits 7:0, green in bits 15:8, blue in + bits 23:16, and the alpha channel is in bits 31:24. */ + ELM_BUFFER_FORMAT_BGRA8888, /*! 32-bit RGBA format with 8 bits per color channel. Red is in bits 23:16, green in bits 15:8, blue in + bits 7:0, and the alpha channel is in bits 31:24. */ + ELM_BUFFER_FORMAT_RGBX8888, /*! 32-bit RGBX format with 8 bits per color channel. Red is in bits 7:0, green in bits 15:8, blue in + bits 23:16, and the x channel is in bits 31:24. */ + ELM_BUFFER_FORMAT_BGRX8888, /*! 32-bit RGBX format with 8 bits per color channel. Red is in bits 23:16, green in bits 15:8, blue in + bits 7:0, and the x channel is in bits 31:24. */ + ELM_BUFFER_FORMAT_RGB565, /*! 16-bit RGB format with 5 and 6 bits per color channel. Red is in bits 4:0, green in bits 10:5, and + the blue color channel is in bits 15:11. */ + ELM_BUFFER_FORMAT_BGR565, /*! 16-bit RGB format with 5 and 6 bits per color channel. Red is in bits 15:11, green in bits 10:5, + and the blue color channel is in bits 4:0. */ + ELM_BUFFER_FORMAT_RGBA4444, /*! 16-bit RGBA format with 4 bits per color channel. Red is in bits 3:0, green in bits 7:4, blue in + bits 11:8 and the alpha channel is in bits 15:12. */ + ELM_BUFFER_FORMAT_BGRA4444, /*! 16-bit RGBA format with 4 bits per color channel. Red is in bits 11:8, green in bits 7:4, blue in + bits 3:0 and the alpha channel is in bits 15:12. */ + ELM_BUFFER_FORMAT_BGRA5551, /*! 16-bit RGBA format with 4 bits per color channel. Red is in bits 14:10, green in bits 9:5, blue in + bits 4:0 and the alpha channel is in bit 15:15. */ + ELM_BUFFER_FORMAT_INDEX_1, /*! 1-bit indexed format. */ + ELM_BUFFER_FORMAT_INDEX_2, /*! 2-bits indexed format. */ + ELM_BUFFER_FORMAT_INDEX_4, /*! 4-bits indexed format. */ + ELM_BUFFER_FORMAT_INDEX_8, /*! 8-bits indexed format. */ + } ELM_BUFFER_FORMAT; + + /*! + @typedef ElmHandle + common handle type for object reference. + */ + typedef unsigned int ElmHandle; + + /*! + @typedef ElmVecObj + evo object handle (elemtry vector object). Created from an external binary evo file. + */ + typedef ElmHandle ElmVecObj; + + /*! + @typedef ElmBitmapObj + ebo object handle (elementry image object). Created from an external ebo file. + */ + typedef ElmHandle ElmBitmapObj; + + /*! + @typedef ElmGroupObj + group object handle. Create from an external ego file. + */ + typedef ElmHandle ElmGroupObj; + + /*! + @typedef ElmBuffer + render buffer object handle. + */ + typedef ElmHandle ElmBuffer; + + #define TRUE 1 + #define FALSE 0 + /*! + @typedef BOOL + boolean type define. + */ + typedef unsigned int BOOL; + + /*! + @abstract Initialize Elementary context. + + @discussion + It should be called as the first function of Elemenatary libary, which initializes the library. Currently + Elementary library doesn't support context concept, neigher multi-threading. Elementary library defines + origin of coordinate system is at top-left. + + @param none + + @return none + */ + BOOL ElmInitialize(uint32_t width, uint32_t height); + + /*! + @abstract Terminate Elementary context. + + @discussion + This should be called when an app exits. It frees all the resource. + + @param none + + @return none + */ + void ElmTerminate(void); + + /*! + @abstract Create an elementary object from an existing binary file. + + @discussion + This function creates an elementary object from the file whose file name is specified by param name. + Caller must match type with the binary file, otherwise create mail fail by returning ELM_NULL_HANDLE. + + @param type + Specify what type of object to be created. + + @param name + The name of the binary resource file. + + @return ElmHandle + An object handle depending on the corresponding type. If type mismatches, it + returns ELM_NULL_HANDLE. + */ + ElmHandle ElmCreateObjectFromFile(ELM_OBJECT_TYPE type, const char *name); + + /*! + @abstract Create an elementary object from build-in data within the appplication. + + @discussion + This function creates an elementar object from local data pointer, which is specially useful for environment without filesystem support. + + @param type + Specify what type of object to be created. + + @param data + The pointer to the binary data which has exactly same layout as external resource file. + + @return ElmHandle + An object handle depending on the corresponding type. If type mismatches with the binary data, it + returns ELM_NULL_HANDLE. + */ + ElmHandle ElmCreateObjectFromData(ELM_OBJECT_TYPE type, void *data, int size); + + /*! + @abstract Rotate a graphics object with centain degree + + @discussion + This function sets an evo/ebo/ego object rotated with specified angle. Without reset, these setting will be + accumulated. + + @param obj + The graphics object will be rotated. + + @param angle + A radian value to be applied on the evo object. + + @return bool + Rotate is set successfully. + */ + BOOL ElmRotate(ElmHandle obj, float angle); + + /*! + @abstract Transfer an graphics object at different directions. + + @discussion + This function put an evo/ebo/ego object away at different directions. Without reset, the setting will be + accumulated. + + @param obj + The graphics object will be transfered. + + @param x + The units in pixel of X direction. + + @param y + The units in pixel of Y direction. + + @return bool + Transfer is set successfully. + */ + BOOL ElmTransfer(ElmHandle obj, int x, int y); + + /*! + @abstract Scale an graphics object at different directions. + + @discussion + This function scale up or down an evo/ego/ebo object at different directions. Without reset, the setting will + be accumateled. + + @param obj + The graphics object which is targeted to manipulate. + + @param x + The scale ratio in X direction. + + @param y + The scale ratio in Y direction. + + @return bool + Scale is set succefully. + */ + BOOL ElmScale(ElmHandle obj, float x, float y); + + /*! + @abstract Reset the attribute of a graphics object for specified property bit. + + @discussion + This funcion resets specified property for an elementary object. It can be applied all types of objects. + But some properties are only valid for centain types of objects. If the function is called to reset an invalid + property for this type of object, it will be siliently ignored. + After reset, the specifed property of an evo/ebo/ego object is set to the initial state. The initial states are decided + by the binary resource file. The resource creator should set right value for all properties if they want to directly render + the object without any adjustment in application. There is one issue, at present, application has no way to query current value + of each property, is it required? + + @param obj + The graphics object which is targeted to manipulate. + + @param mask + Specify which property or properties need to reset to initial value. + + @return bool + Reset is done successfully. If some mask is not valid for this type of object, it would return false. + */ + BOOL ElmReset(ElmHandle obj, ELM_EVO_PROP_BIT mask); + + /*! + @abstract Draw a graphics object onto current render target + + @discussion + This is an enssentail function to do the real job, it takes all current setting of the elementary object and + render into theb buffer target. + + @param buffer + The render target that an elmentary object will be rendered into. + + @param obj + The elmentary object will be draw into render target. + + @return bool + The draw operation for this elmentary object is sucessful. + */ + BOOL ElmDraw(ElmBuffer buffer, ElmHandle object); + + /*! + @abstract Set the rendering quality of an graphics object. + + @discussion + This function sets the rendering quality of an evo/ebo object. Avaliable quality setting contains: + ELM_EVO_QUALITY_LOW, ELM_EVO_QUALITY_MED, ELM_EVO_QUALITY_HI. This function is only applied to an evo or an ebo. + Group object can't be set quality. It always use the setting from its binary. + + @param obj + The elementary object. + + @param quality + The quality enum. + + @return bool + The operation for this object is sucessful, for group object and invalid enum, would return false. + */ + BOOL ElmSetQuality(ElmHandle obj, ELM_QUALITY quality); + + /*! + @abstract Set the fill rule of an evo object. + + @discussion + This function sets the fill rule of an elementary object. Avaliable quality setting contains: + ELM_EVO_EO, ELM_EVO_NZ. It only applies to evo object. + + @param evo + The evo object. + + @param fill + The fill rule enum. + + @return bool + The operation for this evo is sucessful. For non-evo object an ENUM is not a valid enum, would return false. + */ + BOOL ElmSetFill(ElmVecObj evo, ELM_EVO_FILL fill); + + /*! + @abstract Set the blending mode of an evo/ebo object. + + @discussion + This function sets the blending mode of an evo/ebo object. It's not applied to group object. + + @param obj + The graphics object. + + @param blend + The blending mode enum. + + @return bool + The operation for this evo/ebo is sucessful. If object is a group object or blend mode is not a legal one, it would return false. + */ + BOOL ElmSetBlend(ElmHandle obj, ELM_BLEND blend); + + /*! + @abstract Set the solid fill color of an evo object. + + @discussion + This function sets the solid fill color of an evo object. + + @param evo + The evo object. + + @param color + The uint32 color value in rgba order. + + @return bool + The operation for this evo is sucessful. If the object is not a evo object, it would return false. + */ + BOOL ElmSetColor(ElmVecObj evo, uint32_t color); + + /*! + @abstract Set the image paint fill of an evo. + + @discussion + This function sets the image pattern for filling an evo. The image pattern + is a loaded ebo. The ebo's transformation is applied when drawing the evo. + + @param evo + The evo object. + + @param pattern + The image pattern to be set for the evo. + + @return bool + The operation is successful or not. + */ + BOOL ElmSetPattern(ElmVecObj evo, ElmBitmapObj pattern); + + /*! + @abstract Set the image paint fill of an evo. + + @discussion + This function sets the image pattern for filling an evo. The image pattern + is a loaded ebo. The ebo's transformation is applied when drawing the evo. + + @param evo + The evo object. + + @param pattern + The image pattern to be set for the evo. + + @return bool + The operation is successful or not. + */ + BOOL ElmSetPatternMode(ElmVecObj evo, ELM_PATTERN_MODE mode, uint32_t color); + + /*! + @abstract Set the paint type of an evo. + + @discussion + This function selects the paint type for evo to use. An evo may have 3 types + of paint: COLOR, PATTERN, and LINEAR GRADIENT. The Linear graident is always + a built-in resource, which can not be altered. If a binary resource doesn't + have built-in gradient paint resource, it can't be selected as the paint source. + Solid color is also a built-in attribute, but it can be changed by ElmSetColor(). + Paint with a pattern always need an external ebo object, which is impossible + to be embedded in resource file,i.e. ebo object. Before select paint type to + be PATTERN, ElmSetPattern() must be called to attach an EBO to an EVO. + + @param evo + The evo object. + + @param type + The paint type to be set for the evo. + + @return bool + The operation is successful or not. + If the corresponding type is not avaiable for the evo, it returns false and + type paint type falls back to COLOR. + */ + BOOL ElmSetPaintType(ElmVecObj evo, ELM_PAINT_TYPE type); + + /*! + @abstract Create internal render buffer. + + @discussion + This functiois is to create an internal render buffer for Elementary rendering, ussually it's not for direct display. + The buffer which is displayed on pannel is wrapped up by another API, whose address is managed by display controller side. + + @param width + The buffer's width. + + @param height + The buffer's height. + + @param format + The buffer's format, check enumeration of ELM_BUFFER_FORMAT. + + @return + The buffer handle. + */ + ElmBuffer ElmCreateBuffer(unsigned int width, unsigned int height, ELM_BUFFER_FORMAT format); + + /*! + @abstract Wrap a customized buffer. + + @discussion + The application may wrap a user created buffer by giving the information of + the buffer including the size, the memory addresses and format. E.g., the + application can wrap a system framebuffer thus ELM can directly render onto + the screen. + + @return + The buffer handle. + */ + ElmBuffer ElmWrapBuffer(int width, int height, int stride, + void *logical, uint32_t physical, + ELM_BUFFER_FORMAT format); + + /*! + @abstract Get buffer address. + + @discussion + The function is to get the address of ElmBuffer. + + @return + The buffer address. + */ + + uint32_t ElmGetBufferAddress(ElmBuffer buffer); + + /*! + @abstract Destroy a render buffer. + + @discussion + This function is to release all internal resource inside Elementary libary belonging to this buffer. + Applicatoin need make sure the buffer is not being used by elmentary library any more when calling this function. + + @param buffer + The render buffer handle + + @return + If destroying is completed successfully. + */ + BOOL ElmDestroyBuffer(ElmBuffer buffer); + + /*! + @abstract Save a buffer to PNG file. + + @discussion + This function can save the buffer into a PNG file. + + @param buffer + The render buffer handle. + + @param name + The name of the PNG file to sve. + + @return + Save OK or NOT. + + */ + BOOL ElmSaveBuffer(ElmBuffer buffer, const char *name); + + /*! + @abstract Clear a render buffer with specified color and dimension. + + @discussion + This function is called to clear full or partial of the buffer. If the rectangle is out of buffer space, the intersect portion will be cleared. + + @param buffer + A render buffer handle. + + @param color + Clear color value. + + @param x + x origin of partical clear rectangle. + + @param y + y origin of partial clear rectangle. + + @param width + width of partical clear rectangle. + + @param height + height of partical clear rectangle. + + @param full + Flag to indicate a full buffer clear. If true, the dimension parameters will be ignored. + + @return bool + Indicate the clear operation is set up correctly. + */ + BOOL ElmClear(ElmBuffer buffer, uint32_t color, uint32_t x, uint32_t y, uint32_t width, uint32_t height, BOOL full); + + /*! + @abstract Destroy an ELM object. + + @discussion + This function is to release all internal resource inside Elementary libary belonging to this object. + Applicatoin need make sure the object is not being used by elmentary library any more when calling this function. + If an EBO is being destroyed and it's attached to one EVO, it need to guarantee that EVO is not being used by elementary library too. + + @param object + The object handle + + @return + If destroying is completed successfully. + */ + BOOL ElmDestroyObject(ElmHandle object); + + /*! + @abstract Finish all rendering on GPU issued before this call. + + @discussion + This function tells the engine that it has finished the frame data and GPU can draw it now. It's blocked until GPU rendering done. + + @return + If the opeartion is successfully done or not. + */ + BOOL ElmFinish(); + + /*! + @abstract Flush all rendering command to GPU issued before this call. + + @discussion + This function tells the engine to start kicking off command to GPU side, it will return immediately after firing off GPU. + + @return + If the opeartion is successfully done or not. + */ + BOOL ElmFlush(); + + /*! + @abstract Query the paint color of an evo object. + */ + BOOL ElmGetColor(ElmVecObj evoHandle,uint32_t *color); + + /*! + @abstract Query the vectory path count of an EGO object. If the given object + is an evo/ebo, the count is 0. + */ + uint32_t ElmGetVectorCount(ElmHandle handle); + + /*! + @abstract Query the type of an object (by handle). + */ + ELM_OBJECT_TYPE ElmGetObjectType(ElmHandle handle); + + /*! + @abstract Set the current vectory object index to operate on. + */ + BOOL ElmSetCurrentVector(int32_t id); + + BOOL ElmScalePaint(ElmHandle handle, float sx, float sy); + BOOL ElmRotatePaint(ElmHandle handle, float degrees); + BOOL ElmTranslatePaint(ElmHandle handle, float tx, float ty); + + /*! + @abstract Get handle of the framebuffer. + */ + ElmBuffer ElmGetBuffer(vg_lite_buffer_t *buffer); + +#ifdef __cplusplus +} +#endif +#endif /* ELM_H_ */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_buffer.c b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_buffer.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_buffer.c rename to bsp/sdk_overlay/middleware/vglite/elementary/src/elm_buffer.c index 0a45291..36f1414 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_buffer.c +++ b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_buffer.c @@ -1,321 +1,321 @@ -/**************************************************************************** -* -* Copyright 2012 - 2020 Vivante Corporation, Santa Clara, California. -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -#include "elm_precom.h" -#include "vg_lite.h" -#if !DDRLESS -static vg_lite_buffer_format_t _buffer_format_to_vglite(ELM_BUFFER_FORMAT format) -{ - vg_lite_buffer_format_t fmt; - switch (format) { - case ELM_BUFFER_FORMAT_RGBA8888: - fmt = VG_LITE_RGBA8888; - break; - - case ELM_BUFFER_FORMAT_RGBX8888: - fmt = VG_LITE_RGBX8888; - break; - - case ELM_BUFFER_FORMAT_BGRA8888: - fmt = VG_LITE_BGRA8888; - break; - - case ELM_BUFFER_FORMAT_BGRX8888: - fmt = VG_LITE_BGRX8888; - break; - - case ELM_BUFFER_FORMAT_RGB565: - fmt = VG_LITE_RGB565; - break; - - case ELM_BUFFER_FORMAT_BGR565: - fmt = VG_LITE_BGR565; - break; - - case ELM_BUFFER_FORMAT_RGBA4444: - fmt = VG_LITE_RGBA4444; - break; - - case ELM_BUFFER_FORMAT_BGRA4444: - fmt = VG_LITE_BGRA4444; - break; - - default: - fmt = VG_LITE_RGBA8888; - break; - } - - return fmt; -} -#endif -/*! - @abstract Create internal render buffer. - - @discussion - This functiois is to create an internal render buffer for Elementary rendering, ussually it's not for direct display. - The buffer which is displayed on pannel is wrapped up by another API, whose address is managed by display controller side. - - @param width - The buffer's width. - - @param height - The buffer's height. - - @param format - The buffer's format, check enumeration of ELM_BUFFER_FORMAT. - - @return - The buffer handle. - */ -ElmBuffer ElmCreateBuffer(unsigned int width, unsigned int height, ELM_BUFFER_FORMAT format) -{ -#if !DDRLESS - el_Obj_Buffer *buffer_obj; - vg_lite_buffer_t *buffer; - vg_lite_error_t error; - ElmHandle handle = ELM_NULL_HANDLE; - - do { - /* Allocate ebo object. */ - buffer_obj = (el_Obj_Buffer *)calloc(1,sizeof(el_Obj_Buffer)); - if (buffer_obj != NULL) { - buffer_obj->object.type = ELM_OBJECT_TYPE_BUF; - - /* Allocate the buffer. */ - buffer = &buffer_obj->buffer; - memset(buffer, 0, sizeof(vg_lite_buffer_t)); - buffer->width = width; - buffer->height = height; - buffer->format = (vg_lite_buffer_format_t)format; - error = vg_lite_allocate(buffer); - if (error) - goto error_exit; - - JUMP_IF_NON_ZERO_VALUE(add_object((el_Object *)buffer_obj), error_exit); - handle = buffer_obj->object.handle; - } - } while(0); - - return handle; -error_exit: - vg_lite_free(buffer); - free(buffer_obj); - return ELM_NULL_HANDLE; -#else - return ELM_NULL_HANDLE; -#endif -} - -/*! - @abstract Wrap a customized buffer. - - @discussion - The application may wrap a user created buffer by giving the information of - the buffer including the size, the memory addresses and format. E.g., the - application can wrap a system framebuffer thus ELM can directly render onto - the screen. - - @return - The buffer handle. - */ -ElmBuffer ElmWrapBuffer(int width, int height, int stride, - void *logical, uint32_t physical, - ELM_BUFFER_FORMAT format) -{ -#if !DDRLESS - el_Obj_Buffer *buffer_obj; - vg_lite_buffer_t *buffer; - ElmHandle handle = ELM_NULL_HANDLE; - - do { - /* open framebuffer. */ - buffer_obj = (el_Obj_Buffer *)elm_alloc(1, sizeof(el_Obj_Buffer)); - if (buffer_obj != NULL) { - buffer_obj->object.type = ELM_OBJECT_TYPE_BUF; - buffer = &buffer_obj->buffer; - - buffer->width = width; - buffer->height = height; - buffer->stride = stride; - buffer->memory = logical; - buffer->handle = NULL; - buffer->address = physical; - buffer->format = _buffer_format_to_vglite(format); - buffer->tiled = VG_LITE_LINEAR; - JUMP_IF_NON_ZERO_VALUE(add_object((el_Object *)buffer_obj), error_exit); - handle = buffer_obj->object.handle; - } - } while(0); - - return handle; - -error_exit: - free(buffer_obj); - return ELM_NULL_HANDLE; -#else - return ELM_NULL_HANDLE; -#endif - -} - -/*! - @abstract Get buffer address. - -@discussion -The function is to get the address of ElmBuffer. - -@return -The buffer address. -*/ - -uint32_t ElmGetBufferAddress(ElmBuffer buffer) -{ -#if !DDRLESS - el_Obj_Buffer *buff_obj; - buff_obj = (el_Obj_Buffer *)get_object(buffer); - - if (buff_obj == NULL) - { - return 0; - } - else - { - return buff_obj->buffer.address; - } -#else - return 0; -#endif -} - -/*! - @abstract Destroy a render buffer. - - @discussion - This function is to release all internal resource inside Elementary libary belonging to this buffer. - Applicatoin need make sure the buffer is not being used by elmentary library any more when calling this function. - - @param buffer - The render buffer handle - - @return - If destroying is completed successfully. - */ -BOOL ElmDestroyBuffer(ElmBuffer buffer) -{ -#if !DDRLESS - /* Find the object. */ - el_Obj_Buffer *buff = (el_Obj_Buffer *)get_object(buffer); - - /* If found, delete the vg_lite_buffer object. Otherwise, return FALSE. */ - if (buff != NULL) { - if (buff->buffer.handle != NULL) { - /* Free the buffer memory. */ - vg_lite_free(&buff->buffer); - } - - remove_object((el_Object*)buff); - elm_free(buff); - - return TRUE; - } - else { - return FALSE; - } -#else - return TRUE; -#endif -} - -BOOL ElmSaveBuffer(ElmBuffer buffer, const char *name) -{ -#if !DDRLESS - el_Obj_Buffer *buff = (el_Obj_Buffer *)get_object(buffer); - - /* If found, delete the vg_lite_buffer object. Otherwise, return FALSE. */ - if (buff != NULL) { -#if !RTOS - /* - "vg_lite_save_png" function does not exist (anymore). Probably a left - over from an older driver. - */ - if (buff->buffer.memory != NULL) { - vg_lite_save_png(name, &buff->buffer); - } -#endif - return TRUE; - } - else { - return FALSE; - } -#else - return TRUE; -#endif -} - - /*! - @abstract Convert vglite format to elm format. - */ -ELM_BUFFER_FORMAT _buffer_format_to_Elm(vg_lite_buffer_format_t format) -{ - switch (format) - { - case VG_LITE_RGB565: - return ELM_BUFFER_FORMAT_RGB565; - break; - case VG_LITE_BGR565: - return ELM_BUFFER_FORMAT_BGR565; - break; - default: - return ELM_BUFFER_FORMAT_RGBA8888; - break; - } -} - - /*! - @abstract Get handle of the framebuffer. - */ -ElmBuffer ElmGetBuffer(vg_lite_buffer_t *buffer) -{ - elm_tls_t* elm_tls; - - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return ELM_NULL_HANDLE; - - for (int i = 0; i < APP_BUFFER_COUNT; i++) { - if (elm_tls->gContext.elmFB[i].buffer == NULL) { - elm_tls->gContext.elmFB[i].buffer = buffer; - elm_tls->gContext.elmFB[i].handle = ElmWrapBuffer(buffer->width, buffer->height, buffer->stride, buffer->memory, - buffer->address, _buffer_format_to_Elm(buffer->format)); - vg_lite_clear(buffer, NULL, 0x0); - return elm_tls->gContext.elmFB[i].handle; - } - if (elm_tls->gContext.elmFB[i].buffer == buffer) - return elm_tls->gContext.elmFB[i].handle; - } - return 0; +/**************************************************************************** +* +* Copyright 2012 - 2020 Vivante Corporation, Santa Clara, California. +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +#include "elm_precom.h" +#include "vg_lite.h" +#if !DDRLESS +static vg_lite_buffer_format_t _buffer_format_to_vglite(ELM_BUFFER_FORMAT format) +{ + vg_lite_buffer_format_t fmt; + switch (format) { + case ELM_BUFFER_FORMAT_RGBA8888: + fmt = VG_LITE_RGBA8888; + break; + + case ELM_BUFFER_FORMAT_RGBX8888: + fmt = VG_LITE_RGBX8888; + break; + + case ELM_BUFFER_FORMAT_BGRA8888: + fmt = VG_LITE_BGRA8888; + break; + + case ELM_BUFFER_FORMAT_BGRX8888: + fmt = VG_LITE_BGRX8888; + break; + + case ELM_BUFFER_FORMAT_RGB565: + fmt = VG_LITE_RGB565; + break; + + case ELM_BUFFER_FORMAT_BGR565: + fmt = VG_LITE_BGR565; + break; + + case ELM_BUFFER_FORMAT_RGBA4444: + fmt = VG_LITE_RGBA4444; + break; + + case ELM_BUFFER_FORMAT_BGRA4444: + fmt = VG_LITE_BGRA4444; + break; + + default: + fmt = VG_LITE_RGBA8888; + break; + } + + return fmt; +} +#endif +/*! + @abstract Create internal render buffer. + + @discussion + This functiois is to create an internal render buffer for Elementary rendering, ussually it's not for direct display. + The buffer which is displayed on pannel is wrapped up by another API, whose address is managed by display controller side. + + @param width + The buffer's width. + + @param height + The buffer's height. + + @param format + The buffer's format, check enumeration of ELM_BUFFER_FORMAT. + + @return + The buffer handle. + */ +ElmBuffer ElmCreateBuffer(unsigned int width, unsigned int height, ELM_BUFFER_FORMAT format) +{ +#if !DDRLESS + el_Obj_Buffer *buffer_obj; + vg_lite_buffer_t *buffer; + vg_lite_error_t error; + ElmHandle handle = ELM_NULL_HANDLE; + + do { + /* Allocate ebo object. */ + buffer_obj = (el_Obj_Buffer *)calloc(1,sizeof(el_Obj_Buffer)); + if (buffer_obj != NULL) { + buffer_obj->object.type = ELM_OBJECT_TYPE_BUF; + + /* Allocate the buffer. */ + buffer = &buffer_obj->buffer; + memset(buffer, 0, sizeof(vg_lite_buffer_t)); + buffer->width = width; + buffer->height = height; + buffer->format = (vg_lite_buffer_format_t)format; + error = vg_lite_allocate(buffer); + if (error) + goto error_exit; + + JUMP_IF_NON_ZERO_VALUE(add_object((el_Object *)buffer_obj), error_exit); + handle = buffer_obj->object.handle; + } + } while(0); + + return handle; +error_exit: + vg_lite_free(buffer); + free(buffer_obj); + return ELM_NULL_HANDLE; +#else + return ELM_NULL_HANDLE; +#endif +} + +/*! + @abstract Wrap a customized buffer. + + @discussion + The application may wrap a user created buffer by giving the information of + the buffer including the size, the memory addresses and format. E.g., the + application can wrap a system framebuffer thus ELM can directly render onto + the screen. + + @return + The buffer handle. + */ +ElmBuffer ElmWrapBuffer(int width, int height, int stride, + void *logical, uint32_t physical, + ELM_BUFFER_FORMAT format) +{ +#if !DDRLESS + el_Obj_Buffer *buffer_obj; + vg_lite_buffer_t *buffer; + ElmHandle handle = ELM_NULL_HANDLE; + + do { + /* open framebuffer. */ + buffer_obj = (el_Obj_Buffer *)elm_alloc(1, sizeof(el_Obj_Buffer)); + if (buffer_obj != NULL) { + buffer_obj->object.type = ELM_OBJECT_TYPE_BUF; + buffer = &buffer_obj->buffer; + + buffer->width = width; + buffer->height = height; + buffer->stride = stride; + buffer->memory = logical; + buffer->handle = NULL; + buffer->address = physical; + buffer->format = _buffer_format_to_vglite(format); + buffer->tiled = VG_LITE_LINEAR; + JUMP_IF_NON_ZERO_VALUE(add_object((el_Object *)buffer_obj), error_exit); + handle = buffer_obj->object.handle; + } + } while(0); + + return handle; + +error_exit: + free(buffer_obj); + return ELM_NULL_HANDLE; +#else + return ELM_NULL_HANDLE; +#endif + +} + +/*! + @abstract Get buffer address. + +@discussion +The function is to get the address of ElmBuffer. + +@return +The buffer address. +*/ + +uint32_t ElmGetBufferAddress(ElmBuffer buffer) +{ +#if !DDRLESS + el_Obj_Buffer *buff_obj; + buff_obj = (el_Obj_Buffer *)get_object(buffer); + + if (buff_obj == NULL) + { + return 0; + } + else + { + return buff_obj->buffer.address; + } +#else + return 0; +#endif +} + +/*! + @abstract Destroy a render buffer. + + @discussion + This function is to release all internal resource inside Elementary libary belonging to this buffer. + Applicatoin need make sure the buffer is not being used by elmentary library any more when calling this function. + + @param buffer + The render buffer handle + + @return + If destroying is completed successfully. + */ +BOOL ElmDestroyBuffer(ElmBuffer buffer) +{ +#if !DDRLESS + /* Find the object. */ + el_Obj_Buffer *buff = (el_Obj_Buffer *)get_object(buffer); + + /* If found, delete the vg_lite_buffer object. Otherwise, return FALSE. */ + if (buff != NULL) { + if (buff->buffer.handle != NULL) { + /* Free the buffer memory. */ + vg_lite_free(&buff->buffer); + } + + remove_object((el_Object*)buff); + elm_free(buff); + + return TRUE; + } + else { + return FALSE; + } +#else + return TRUE; +#endif +} + +BOOL ElmSaveBuffer(ElmBuffer buffer, const char *name) +{ +#if !DDRLESS + el_Obj_Buffer *buff = (el_Obj_Buffer *)get_object(buffer); + + /* If found, delete the vg_lite_buffer object. Otherwise, return FALSE. */ + if (buff != NULL) { +#if !RTOS + /* + "vg_lite_save_png" function does not exist (anymore). Probably a left + over from an older driver. + */ + if (buff->buffer.memory != NULL) { + vg_lite_save_png(name, &buff->buffer); + } +#endif + return TRUE; + } + else { + return FALSE; + } +#else + return TRUE; +#endif +} + + /*! + @abstract Convert vglite format to elm format. + */ +ELM_BUFFER_FORMAT _buffer_format_to_Elm(vg_lite_buffer_format_t format) +{ + switch (format) + { + case VG_LITE_RGB565: + return ELM_BUFFER_FORMAT_RGB565; + break; + case VG_LITE_BGR565: + return ELM_BUFFER_FORMAT_BGR565; + break; + default: + return ELM_BUFFER_FORMAT_RGBA8888; + break; + } +} + + /*! + @abstract Get handle of the framebuffer. + */ +ElmBuffer ElmGetBuffer(vg_lite_buffer_t *buffer) +{ + elm_tls_t* elm_tls; + + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return ELM_NULL_HANDLE; + + for (int i = 0; i < APP_BUFFER_COUNT; i++) { + if (elm_tls->gContext.elmFB[i].buffer == NULL) { + elm_tls->gContext.elmFB[i].buffer = buffer; + elm_tls->gContext.elmFB[i].handle = ElmWrapBuffer(buffer->width, buffer->height, buffer->stride, buffer->memory, + buffer->address, _buffer_format_to_Elm(buffer->format)); + vg_lite_clear(buffer, NULL, 0x0); + return elm_tls->gContext.elmFB[i].handle; + } + if (elm_tls->gContext.elmFB[i].buffer == buffer) + return elm_tls->gContext.elmFB[i].handle; + } + return 0; } \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_draw.c b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_draw.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_draw.c rename to bsp/sdk_overlay/middleware/vglite/elementary/src/elm_draw.c index 6e90409..8d66881 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_draw.c +++ b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_draw.c @@ -1,483 +1,483 @@ -/**************************************************************************** -* -* Copyright 2012 - 2020 Vivante Corporation, Santa Clara, California. -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -#include "elm_precom.h" - -#if (VG_RENDER_TEXT==1) -#include "elm_text.h" -#endif /* VG_RENDER_TEXT */ - -static void multiply(vg_lite_matrix_t * matrix, vg_lite_matrix_t * mult) -{ - vg_lite_matrix_t temp; - int row, column; - - /* Process all rows. */ - for (row = 0; row < 3; row++) { - /* Process all columns. */ - for (column = 0; column < 3; column++) { - /* Compute matrix entry. */ - temp.m[row][column] = (matrix->m[row][0] * mult->m[0][column]) - + (matrix->m[row][1] * mult->m[1][column]) - + (matrix->m[row][2] * mult->m[2][column]); - } - } - - memcpy(matrix, &temp, sizeof(temp)); - -} - -static vg_lite_filter_t quality_to_filter(ELM_QUALITY quality) -{ - switch (quality) { - case ELM_QULIATY_HI: - return VG_LITE_FILTER_BI_LINEAR; - break; - - case ELM_QUALITY_MED: - return VG_LITE_FILTER_LINEAR; - break; - - case ELM_QUALITY_LOW: - default: - return VG_LITE_FILTER_POINT; - break; - } -} - -static vg_lite_pattern_mode_t pat_to_pad(ELM_PATTERN_MODE mode) -{ - switch (mode) { - case ELM_PATTERN_MODE_PAD: - return VG_LITE_PATTERN_PAD; - break; - - default: - return VG_LITE_PATTERN_COLOR; - break; - } -} -static vg_lite_error_t draw_evo_pattern(el_Obj_Buffer *buff, el_Obj_Group *ego,int * index) -{ - el_Obj_EVO *evo; - vg_lite_error_t error = VG_LITE_INVALID_ARGUMENT; - vg_lite_color_t color; - vg_lite_filter_t filter; - vg_lite_blend_t blend; - vg_lite_fill_t rule; - vg_lite_buffer_t *buffer; - vg_lite_matrix_t mat; - vg_lite_pattern_mode_t pat_mode; - int width = 0; - int height = 0; - - int start = *index; - int i = start; - evo = &ego->group.objects[i]; - width = (int)(evo->data.path.bounding_box[2] - evo->data.path.bounding_box[0]); - height = (int)(evo->data.path.bounding_box[3] - evo->data.path.bounding_box[1]); - buffer = (vg_lite_buffer_t *)malloc(sizeof(vg_lite_buffer_t)); - memset(buffer,0,sizeof(vg_lite_buffer_t)); - buffer->width = width; - buffer->height = height; - buffer->format = VG_LITE_RGBA8888; - error = vg_lite_allocate(buffer); - vg_lite_clear(buffer,NULL,0xffffffff); - i++; - evo = &ego->group.objects[i]; - while(evo->is_pattern) - { - blend = (vg_lite_blend_t)evo->attribute.blend; - rule = (vg_lite_fill_t)evo->attribute.fill_rule; - color = (vg_lite_color_t)evo->attribute.paint.color; - memcpy(&mat, &(evo->attribute.transform.matrix), sizeof(mat)); - error = vg_lite_draw(buffer, &evo->data.path, - rule, - &mat, - blend, - color); - if(error) - return error; - i++; - evo = &ego->group.objects[i]; - } - *index = i - 1; - evo = &ego->group.objects[start]; - blend = (vg_lite_blend_t)evo->attribute.blend; - rule = (vg_lite_fill_t)evo->attribute.fill_rule; - color = (vg_lite_color_t)evo->attribute.paint.color; - memcpy(&mat, &(evo->attribute.transform.matrix), sizeof(mat)); - filter = VG_LITE_FILTER_POINT; - pat_mode = VG_LITE_PATTERN_COLOR; - error = vg_lite_draw_pattern(&buff->buffer, &evo->data.path, - rule, - &mat, - buffer, - &mat, - blend, - pat_mode, - color, - filter); - vg_lite_finish(); - vg_lite_free(buffer); - free(buffer); - return error; -} - -static vg_lite_error_t draw_evo(el_Obj_Buffer *buff, el_Obj_EVO *evo, vg_lite_matrix_t *mat) -{ - el_Obj_EBO *pattern; - vg_lite_error_t error = VG_LITE_INVALID_ARGUMENT; - vg_lite_color_t color; - vg_lite_filter_t filter; - vg_lite_matrix_t mat_pattern; - ELM_PAINT_TYPE paint_type = evo->attribute.paint.type; - vg_lite_blend_t blend = (vg_lite_blend_t)evo->attribute.blend; - vg_lite_fill_t rule = (vg_lite_fill_t)evo->attribute.fill_rule; - vg_lite_pattern_mode_t pat_mode = pat_to_pad(evo->attribute.paint.pattern.mode); - - switch (paint_type) { - case ELM_PAINT_GRADIENT: - memcpy(&evo->attribute.paint.grad->data.grad.matrix, - &evo->attribute.paint.grad->data.transform.matrix, - sizeof(evo->attribute.paint.grad->data.transform.matrix)); -#if !DDRLESS - error = vg_lite_draw_gradient(&buff->buffer, &evo->data.path, - rule, - mat, - &evo->attribute.paint.grad->data.grad, - blend); -#else - error = vg_lite_draw_gradient(NULL, &evo->data.path, - rule, - mat, - &evo->attribute.paint.grad->data.grad, - blend); -#endif - break; - case ELM_PAINT_RADIAL_GRADIENT: - memcpy(&evo->attribute.paint.radgrad->data.rad_grad.matrix, - &evo->attribute.paint.radgrad->data.transform.matrix, - sizeof(evo->attribute.paint.radgrad->data.transform.matrix)); - - error = vg_lite_draw_radial_gradient(&buff->buffer, &evo->data.path, - rule, - mat, - &evo->attribute.paint.radgrad->data.rad_grad, - 0, - blend, - VG_LITE_FILTER_LINEAR); - break; - case ELM_PAINT_COLOR: - color = (vg_lite_color_t)evo->attribute.paint.color; - -#if !DDRLESS - error = vg_lite_draw(&buff->buffer, &evo->data.path, - rule, - mat, - blend, - color); -#else - error = vg_lite_draw(NULL, &evo->data.path, - rule, - mat, - blend, - color); -#endif - break; - case ELM_PAINT_PATTERN: - pattern = (el_Obj_EBO *)(evo->attribute.paint.pattern.pattern); - blend = (vg_lite_blend_t)(pattern->attribute.blend); - filter = quality_to_filter(evo->attribute.quality); - color = (vg_lite_color_t)pattern->attribute.paint.color; - memcpy(&mat_pattern, &pattern->attribute.transform.matrix, - sizeof(pattern->attribute.transform.matrix)); - -#if !DDRLESS - error = vg_lite_draw_pattern(&buff->buffer, &evo->data.path, rule, mat, - &pattern->data.buffer, &mat_pattern, blend, - pat_mode, color, filter); -#else - error = vg_lite_draw_pattern(NULL, &evo->data.path, rule, mat, - &pattern->data.buffer, &mat_pattern, blend, - pat_mode, color, filter); -#endif - break; - case ELM_PAINT_TEXT: -#if (VG_RENDER_TEXT==1) - error = draw_text(buff, evo, mat); -#endif /* VG_RENDER_TEXT */ - break; - } - - return error; -} - -static vg_lite_error_t draw_ebo(el_Obj_Buffer *buff, el_Obj_EBO *ebo, vg_lite_matrix_t *mat) -{ - vg_lite_error_t error; - vg_lite_buffer_t *image_buffer = &ebo->data.buffer; - vg_lite_blend_t blend = (vg_lite_blend_t)ebo->attribute.blend; - vg_lite_color_t color = ebo->attribute.paint.color; - vg_lite_filter_t filter = quality_to_filter(ebo->attribute.quality); - - if (image_buffer->format >= VG_LITE_INDEX_1 && image_buffer->format <= VG_LITE_INDEX_8) - { - vg_lite_set_CLUT(ebo->clut_count, ebo->clut); - } - - image_buffer->image_mode = VG_LITE_NORMAL_IMAGE_MODE; -#if !DDRLESS - error = vg_lite_blit(&buff->buffer, image_buffer, mat, blend, color, filter); -#else - error = vg_lite_blit(NULL, image_buffer, mat, blend, color, filter); -#endif - return error; -} -/*! - @abstract Clear a render buffer with specified color and dimension. - - @discussion - This function is called to clear full or partial of the buffer. If the rectangle is out of buffer space, the intersect portion will be cleared. - - @param buffer - A render buffer handle. - - @param color - Clear color value. - - @param x - x origin of partical clear rectangle. - - @param y - y origin of partial clear rectangle. - - @param width - width of partical clear rectangle. - - @param height - height of partical clear rectangle. - - @param full - Flag to indicate a full buffer clear. If true, the dimension parameters will be ignored. - - @return bool - Indicate the clear operation is set up correctly. - */ -BOOL ElmClear(ElmBuffer buffer, uint32_t color, uint32_t x, uint32_t y, uint32_t width, uint32_t height, BOOL full) -{ -#if !DDRLESS - vg_lite_error_t error = VG_LITE_SUCCESS; - el_Obj_Buffer *buff = (el_Obj_Buffer *)get_object(buffer); - vg_lite_rectangle_t rectangle; - rectangle.x = x; - rectangle.y = y; - rectangle.width = width; - rectangle.height = height; - - if (full == 1) - { - error = vg_lite_clear(&buff->buffer, NULL, color); - } - else - { - error = vg_lite_clear(&buff->buffer, &rectangle, color); - } - return ((error == VG_LITE_SUCCESS) ? TRUE : FALSE); -#else - return TRUE; -#endif -} - -/*! - @abstract Finish all rendering on GPU issued before this call. - - @discussion - This function tells the engine that it has finished the frame data and GPU can draw it now. It's blocked until GPU rendering done. - - @return - If the opeartion is successfully done or not. - */ -BOOL ElmFinish() -{ - vg_lite_finish(); - return TRUE; -} - -/*! - @abstract Flush all rendering command to GPU issued before this call. - - @discussion - This function tells the engine to start kicking off command to GPU side, it will return immediately after firing off GPU. - - @return - If the opeartion is successfully done or not. - */ -BOOL ElmFlush() -{ - vg_lite_flush(); - return TRUE; -} - - - -/*! - @abstract Draw a graphics object onto current render target - - @discussion - This is an enssentail function to do the real job, it takes all current setting of the elementary object and - render into theb buffer target. - - @param buffer - The render target that an elmentary object will be rendered into. - - @param obj - The elmentary object will be draw into render target. - - @return bool - The draw operation for this elmentary object is sucessful. - */ -BOOL ElmDraw(ElmBuffer buffer, ElmHandle object) -{ - BOOL status = TRUE; - el_Object *elm; - el_Obj_Buffer *buff; - vg_lite_error_t error; - vg_lite_matrix_t mat; - elm = get_object(object); - - if (!elm) - { - return FALSE; - } - -#if !DDRLESS - buff = (el_Obj_Buffer *)get_object(buffer); - if (buff == NULL) - { - return FALSE; - } -#else - buff = NULL; -#endif - - if (elm->type == ELM_OBJECT_TYPE_EGO) - { - el_Obj_EVO *evo; - el_Obj_Group *ego = (el_Obj_Group *)elm; - vg_lite_matrix_t mat_group, res_mat; - - if (ego->group.count > 0) - { - int i; - memcpy(&mat_group, &(ego->transform.matrix), sizeof(ego->transform.matrix)); - for (i = 0; i < ego->group.count; i++) - { - evo = &ego->group.objects[i]; - - /* Font objects may generate empty objects */ - if (evo->object.handle == ELM_NULL_HANDLE) - continue; - - if(evo->is_image) - { - ElmHandle ebo_handle; - el_Object *elm_ebo; - el_Obj_EBO *ebo; - ebo_handle = ElmCreateObjectFromFile(ELM_OBJECT_TYPE_EBO, evo->eboname); - elm_ebo = get_object(ebo_handle); - ebo = (el_Obj_EBO *)elm_ebo; - memcpy(&mat, &evo->defaultAttrib.transform.matrix, sizeof(mat)); - - error = draw_ebo(buff, ebo, &mat); - if (error) - { - status = FALSE; - } - continue; - } - memcpy(&mat, &(evo->attribute.transform.matrix), sizeof(mat)); - memcpy(&res_mat, &mat_group, sizeof(mat_group)); - multiply(&res_mat, &mat); - - if(evo->has_pattern) - error = draw_evo_pattern(buff,ego,&i); - else - error = draw_evo(buff, evo, &res_mat); - if (error) - { - status = FALSE; - break; - } - } - } - } - else if (elm->type == ELM_OBJECT_TYPE_EVO) - { - el_Obj_EVO *evo = (el_Obj_EVO *)elm; - memcpy(&mat, &(evo->attribute.transform.matrix), sizeof(mat)); - - error = draw_evo(buff, evo, &mat); - if (error) - { - status = FALSE; - } - } - else if (elm->type == ELM_OBJECT_TYPE_EBO) - { - el_Obj_EBO *ebo = (el_Obj_EBO *)elm; - memcpy(&mat, &(ebo->attribute.transform.matrix), sizeof(mat)); - - error = draw_ebo(buff, ebo, &mat); - if (error) - { - status = FALSE; - } - - } - else if (elm->type == ELM_OBJECT_TYPE_BUF) - { - el_Obj_Buffer *src = (el_Obj_Buffer *)elm; - vg_lite_identity(&mat); - -#if !DDRLESS - if (VG_LITE_SUCCESS != - vg_lite_blit(&buff->buffer, &src->buffer, &mat, VG_LITE_BLEND_NONE, 0, - VG_LITE_FILTER_BI_LINEAR) - ) -#else - if (VG_LITE_SUCCESS != - vg_lite_blit(NULL, &src->buffer, &mat, VG_LITE_BLEND_NONE, 0, - VG_LITE_FILTER_BI_LINEAR) - ) -#endif - { - status = FALSE; - } - } - return status; -} +/**************************************************************************** +* +* Copyright 2012 - 2020 Vivante Corporation, Santa Clara, California. +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +#include "elm_precom.h" + +#if (VG_RENDER_TEXT==1) +#include "elm_text.h" +#endif /* VG_RENDER_TEXT */ + +static void multiply(vg_lite_matrix_t * matrix, vg_lite_matrix_t * mult) +{ + vg_lite_matrix_t temp; + int row, column; + + /* Process all rows. */ + for (row = 0; row < 3; row++) { + /* Process all columns. */ + for (column = 0; column < 3; column++) { + /* Compute matrix entry. */ + temp.m[row][column] = (matrix->m[row][0] * mult->m[0][column]) + + (matrix->m[row][1] * mult->m[1][column]) + + (matrix->m[row][2] * mult->m[2][column]); + } + } + + memcpy(matrix, &temp, sizeof(temp)); + +} + +static vg_lite_filter_t quality_to_filter(ELM_QUALITY quality) +{ + switch (quality) { + case ELM_QULIATY_HI: + return VG_LITE_FILTER_BI_LINEAR; + break; + + case ELM_QUALITY_MED: + return VG_LITE_FILTER_LINEAR; + break; + + case ELM_QUALITY_LOW: + default: + return VG_LITE_FILTER_POINT; + break; + } +} + +static vg_lite_pattern_mode_t pat_to_pad(ELM_PATTERN_MODE mode) +{ + switch (mode) { + case ELM_PATTERN_MODE_PAD: + return VG_LITE_PATTERN_PAD; + break; + + default: + return VG_LITE_PATTERN_COLOR; + break; + } +} +static vg_lite_error_t draw_evo_pattern(el_Obj_Buffer *buff, el_Obj_Group *ego,int * index) +{ + el_Obj_EVO *evo; + vg_lite_error_t error = VG_LITE_INVALID_ARGUMENT; + vg_lite_color_t color; + vg_lite_filter_t filter; + vg_lite_blend_t blend; + vg_lite_fill_t rule; + vg_lite_buffer_t *buffer; + vg_lite_matrix_t mat; + vg_lite_pattern_mode_t pat_mode; + int width = 0; + int height = 0; + + int start = *index; + int i = start; + evo = &ego->group.objects[i]; + width = (int)(evo->data.path.bounding_box[2] - evo->data.path.bounding_box[0]); + height = (int)(evo->data.path.bounding_box[3] - evo->data.path.bounding_box[1]); + buffer = (vg_lite_buffer_t *)malloc(sizeof(vg_lite_buffer_t)); + memset(buffer,0,sizeof(vg_lite_buffer_t)); + buffer->width = width; + buffer->height = height; + buffer->format = VG_LITE_RGBA8888; + error = vg_lite_allocate(buffer); + vg_lite_clear(buffer,NULL,0xffffffff); + i++; + evo = &ego->group.objects[i]; + while(evo->is_pattern) + { + blend = (vg_lite_blend_t)evo->attribute.blend; + rule = (vg_lite_fill_t)evo->attribute.fill_rule; + color = (vg_lite_color_t)evo->attribute.paint.color; + memcpy(&mat, &(evo->attribute.transform.matrix), sizeof(mat)); + error = vg_lite_draw(buffer, &evo->data.path, + rule, + &mat, + blend, + color); + if(error) + return error; + i++; + evo = &ego->group.objects[i]; + } + *index = i - 1; + evo = &ego->group.objects[start]; + blend = (vg_lite_blend_t)evo->attribute.blend; + rule = (vg_lite_fill_t)evo->attribute.fill_rule; + color = (vg_lite_color_t)evo->attribute.paint.color; + memcpy(&mat, &(evo->attribute.transform.matrix), sizeof(mat)); + filter = VG_LITE_FILTER_POINT; + pat_mode = VG_LITE_PATTERN_COLOR; + error = vg_lite_draw_pattern(&buff->buffer, &evo->data.path, + rule, + &mat, + buffer, + &mat, + blend, + pat_mode, + color, + filter); + vg_lite_finish(); + vg_lite_free(buffer); + free(buffer); + return error; +} + +static vg_lite_error_t draw_evo(el_Obj_Buffer *buff, el_Obj_EVO *evo, vg_lite_matrix_t *mat) +{ + el_Obj_EBO *pattern; + vg_lite_error_t error = VG_LITE_INVALID_ARGUMENT; + vg_lite_color_t color; + vg_lite_filter_t filter; + vg_lite_matrix_t mat_pattern; + ELM_PAINT_TYPE paint_type = evo->attribute.paint.type; + vg_lite_blend_t blend = (vg_lite_blend_t)evo->attribute.blend; + vg_lite_fill_t rule = (vg_lite_fill_t)evo->attribute.fill_rule; + vg_lite_pattern_mode_t pat_mode = pat_to_pad(evo->attribute.paint.pattern.mode); + + switch (paint_type) { + case ELM_PAINT_GRADIENT: + memcpy(&evo->attribute.paint.grad->data.grad.matrix, + &evo->attribute.paint.grad->data.transform.matrix, + sizeof(evo->attribute.paint.grad->data.transform.matrix)); +#if !DDRLESS + error = vg_lite_draw_gradient(&buff->buffer, &evo->data.path, + rule, + mat, + &evo->attribute.paint.grad->data.grad, + blend); +#else + error = vg_lite_draw_gradient(NULL, &evo->data.path, + rule, + mat, + &evo->attribute.paint.grad->data.grad, + blend); +#endif + break; + case ELM_PAINT_RADIAL_GRADIENT: + memcpy(&evo->attribute.paint.radgrad->data.rad_grad.matrix, + &evo->attribute.paint.radgrad->data.transform.matrix, + sizeof(evo->attribute.paint.radgrad->data.transform.matrix)); + + error = vg_lite_draw_radial_gradient(&buff->buffer, &evo->data.path, + rule, + mat, + &evo->attribute.paint.radgrad->data.rad_grad, + 0, + blend, + VG_LITE_FILTER_LINEAR); + break; + case ELM_PAINT_COLOR: + color = (vg_lite_color_t)evo->attribute.paint.color; + +#if !DDRLESS + error = vg_lite_draw(&buff->buffer, &evo->data.path, + rule, + mat, + blend, + color); +#else + error = vg_lite_draw(NULL, &evo->data.path, + rule, + mat, + blend, + color); +#endif + break; + case ELM_PAINT_PATTERN: + pattern = (el_Obj_EBO *)(evo->attribute.paint.pattern.pattern); + blend = (vg_lite_blend_t)(pattern->attribute.blend); + filter = quality_to_filter(evo->attribute.quality); + color = (vg_lite_color_t)pattern->attribute.paint.color; + memcpy(&mat_pattern, &pattern->attribute.transform.matrix, + sizeof(pattern->attribute.transform.matrix)); + +#if !DDRLESS + error = vg_lite_draw_pattern(&buff->buffer, &evo->data.path, rule, mat, + &pattern->data.buffer, &mat_pattern, blend, + pat_mode, color, filter); +#else + error = vg_lite_draw_pattern(NULL, &evo->data.path, rule, mat, + &pattern->data.buffer, &mat_pattern, blend, + pat_mode, color, filter); +#endif + break; + case ELM_PAINT_TEXT: +#if (VG_RENDER_TEXT==1) + error = draw_text(buff, evo, mat); +#endif /* VG_RENDER_TEXT */ + break; + } + + return error; +} + +static vg_lite_error_t draw_ebo(el_Obj_Buffer *buff, el_Obj_EBO *ebo, vg_lite_matrix_t *mat) +{ + vg_lite_error_t error; + vg_lite_buffer_t *image_buffer = &ebo->data.buffer; + vg_lite_blend_t blend = (vg_lite_blend_t)ebo->attribute.blend; + vg_lite_color_t color = ebo->attribute.paint.color; + vg_lite_filter_t filter = quality_to_filter(ebo->attribute.quality); + + if (image_buffer->format >= VG_LITE_INDEX_1 && image_buffer->format <= VG_LITE_INDEX_8) + { + vg_lite_set_CLUT(ebo->clut_count, ebo->clut); + } + + image_buffer->image_mode = VG_LITE_NORMAL_IMAGE_MODE; +#if !DDRLESS + error = vg_lite_blit(&buff->buffer, image_buffer, mat, blend, color, filter); +#else + error = vg_lite_blit(NULL, image_buffer, mat, blend, color, filter); +#endif + return error; +} +/*! + @abstract Clear a render buffer with specified color and dimension. + + @discussion + This function is called to clear full or partial of the buffer. If the rectangle is out of buffer space, the intersect portion will be cleared. + + @param buffer + A render buffer handle. + + @param color + Clear color value. + + @param x + x origin of partical clear rectangle. + + @param y + y origin of partial clear rectangle. + + @param width + width of partical clear rectangle. + + @param height + height of partical clear rectangle. + + @param full + Flag to indicate a full buffer clear. If true, the dimension parameters will be ignored. + + @return bool + Indicate the clear operation is set up correctly. + */ +BOOL ElmClear(ElmBuffer buffer, uint32_t color, uint32_t x, uint32_t y, uint32_t width, uint32_t height, BOOL full) +{ +#if !DDRLESS + vg_lite_error_t error = VG_LITE_SUCCESS; + el_Obj_Buffer *buff = (el_Obj_Buffer *)get_object(buffer); + vg_lite_rectangle_t rectangle; + rectangle.x = x; + rectangle.y = y; + rectangle.width = width; + rectangle.height = height; + + if (full == 1) + { + error = vg_lite_clear(&buff->buffer, NULL, color); + } + else + { + error = vg_lite_clear(&buff->buffer, &rectangle, color); + } + return ((error == VG_LITE_SUCCESS) ? TRUE : FALSE); +#else + return TRUE; +#endif +} + +/*! + @abstract Finish all rendering on GPU issued before this call. + + @discussion + This function tells the engine that it has finished the frame data and GPU can draw it now. It's blocked until GPU rendering done. + + @return + If the opeartion is successfully done or not. + */ +BOOL ElmFinish() +{ + vg_lite_finish(); + return TRUE; +} + +/*! + @abstract Flush all rendering command to GPU issued before this call. + + @discussion + This function tells the engine to start kicking off command to GPU side, it will return immediately after firing off GPU. + + @return + If the opeartion is successfully done or not. + */ +BOOL ElmFlush() +{ + vg_lite_flush(); + return TRUE; +} + + + +/*! + @abstract Draw a graphics object onto current render target + + @discussion + This is an enssentail function to do the real job, it takes all current setting of the elementary object and + render into theb buffer target. + + @param buffer + The render target that an elmentary object will be rendered into. + + @param obj + The elmentary object will be draw into render target. + + @return bool + The draw operation for this elmentary object is sucessful. + */ +BOOL ElmDraw(ElmBuffer buffer, ElmHandle object) +{ + BOOL status = TRUE; + el_Object *elm; + el_Obj_Buffer *buff; + vg_lite_error_t error; + vg_lite_matrix_t mat; + elm = get_object(object); + + if (!elm) + { + return FALSE; + } + +#if !DDRLESS + buff = (el_Obj_Buffer *)get_object(buffer); + if (buff == NULL) + { + return FALSE; + } +#else + buff = NULL; +#endif + + if (elm->type == ELM_OBJECT_TYPE_EGO) + { + el_Obj_EVO *evo; + el_Obj_Group *ego = (el_Obj_Group *)elm; + vg_lite_matrix_t mat_group, res_mat; + + if (ego->group.count > 0) + { + int i; + memcpy(&mat_group, &(ego->transform.matrix), sizeof(ego->transform.matrix)); + for (i = 0; i < ego->group.count; i++) + { + evo = &ego->group.objects[i]; + + /* Font objects may generate empty objects */ + if (evo->object.handle == ELM_NULL_HANDLE) + continue; + + if(evo->is_image) + { + ElmHandle ebo_handle; + el_Object *elm_ebo; + el_Obj_EBO *ebo; + ebo_handle = ElmCreateObjectFromFile(ELM_OBJECT_TYPE_EBO, evo->eboname); + elm_ebo = get_object(ebo_handle); + ebo = (el_Obj_EBO *)elm_ebo; + memcpy(&mat, &evo->defaultAttrib.transform.matrix, sizeof(mat)); + + error = draw_ebo(buff, ebo, &mat); + if (error) + { + status = FALSE; + } + continue; + } + memcpy(&mat, &(evo->attribute.transform.matrix), sizeof(mat)); + memcpy(&res_mat, &mat_group, sizeof(mat_group)); + multiply(&res_mat, &mat); + + if(evo->has_pattern) + error = draw_evo_pattern(buff,ego,&i); + else + error = draw_evo(buff, evo, &res_mat); + if (error) + { + status = FALSE; + break; + } + } + } + } + else if (elm->type == ELM_OBJECT_TYPE_EVO) + { + el_Obj_EVO *evo = (el_Obj_EVO *)elm; + memcpy(&mat, &(evo->attribute.transform.matrix), sizeof(mat)); + + error = draw_evo(buff, evo, &mat); + if (error) + { + status = FALSE; + } + } + else if (elm->type == ELM_OBJECT_TYPE_EBO) + { + el_Obj_EBO *ebo = (el_Obj_EBO *)elm; + memcpy(&mat, &(ebo->attribute.transform.matrix), sizeof(mat)); + + error = draw_ebo(buff, ebo, &mat); + if (error) + { + status = FALSE; + } + + } + else if (elm->type == ELM_OBJECT_TYPE_BUF) + { + el_Obj_Buffer *src = (el_Obj_Buffer *)elm; + vg_lite_identity(&mat); + +#if !DDRLESS + if (VG_LITE_SUCCESS != + vg_lite_blit(&buff->buffer, &src->buffer, &mat, VG_LITE_BLEND_NONE, 0, + VG_LITE_FILTER_BI_LINEAR) + ) +#else + if (VG_LITE_SUCCESS != + vg_lite_blit(NULL, &src->buffer, &mat, VG_LITE_BLEND_NONE, 0, + VG_LITE_FILTER_BI_LINEAR) + ) +#endif + { + status = FALSE; + } + } + return status; +} diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_headers.h b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_headers.h similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_headers.h rename to bsp/sdk_overlay/middleware/vglite/elementary/src/elm_headers.h index 70937c8..dff48eb 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_headers.h +++ b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_headers.h @@ -1,158 +1,158 @@ -/**************************************************************************** -* -* Copyright 2021 Vivante Corporation, Santa Clara, California. -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -#ifndef __ELM_HEADERS_H__ -#define __ELM_HEADERS_H__ - - -#define ATTR_PACKED __attribute__((packed, aligned(4))) - - -typedef struct { - vg_lite_matrix_t matrix; - uint32_t reserved; - uint32_t stop_count; - uint32_t stop_offset; - uint32_t color_offset; -} el_EVO_GradData; - -typedef struct { - vg_lite_radial_gradient_parameter_t params; - vg_lite_radial_gradient_spreadmode_t spread_mode; -} el_EVO_RadGradDataExt; - -struct el_PaintType_t { - uint32_t paint:28; - uint32_t flags:1; - uint32_t is_image:1; - uint32_t is_pattern:1; - uint32_t has_pattern:1; -}; - -typedef struct ATTR_PACKED { - uint32_t type; - vg_lite_float_t min_x, min_y, max_x, max_y; - uint32_t format; - uint32_t length:31; - uint32_t arc_flag:1; - uint32_t offset; - vg_lite_matrix_t matrix; - uint32_t reserved; - uint32_t quality; - uint32_t fill_rule; - uint32_t blend; - union { - uint32_t paint_data; - struct el_PaintType_t paint_type; - }; - vg_lite_color_t color; - el_EVO_GradData grad; -} el_EVO_Polygon; - -typedef struct ATTR_PACKED { - uint32_t type; - uint32_t namelength; - char eboname[76]; - union { - uint32_t paint_data; - struct el_PaintType_t paint_type; - }; - vg_lite_matrix_t matrix; - uint32_t width; - uint32_t height; -} el_EVO_Image; - -typedef struct ATTR_PACKED { - union { - el_EVO_Polygon polygon; - el_EVO_Image image; - }; -} el_EVO_Header; - -typedef struct ATTR_PACKED { - uint32_t type; - uint32_t size_font_block; - uint32_t num_ttf_fonts; - uint32_t num_vector_fonts; - uint32_t num_text_fonts; - uint32_t ttf_fonts_block_offset; - uint32_t ttf_fonts_block_length; - uint32_t vector_fonts_block_offset; - uint32_t vector_fonts_block_length; - uint32_t text_fonts_block_offset; - uint32_t text_fonts_block_length; - uint32_t property_block_offset; - uint32_t property_block_length; -} el_Font_Header; - -struct el_TextFlags_t { - uint32_t flags1:1; - uint32_t text_anchor:2; - uint32_t flags2:29; -}; - -typedef struct ATTR_PACKED { - uint32_t type; - uint32_t size_text_block; - uint32_t tspan_has_dx_dy; - float x_pos; - float y_pos; - float font_size; - uint32_t font_id; - uint32_t color; - union { - uint32_t flags_data; - struct el_TextFlags_t text_flags; - }; - vg_lite_matrix_t matrix; - uint32_t reserved; - uint16_t data_length; -} el_Text_Header; - -typedef struct ATTR_PACKED { - uint32_t type; - uint32_t width; - uint32_t height; - uint32_t stride; - uint32_t tiled; - uint32_t format; - uint32_t data_offset; -} el_EBO_Header; - -typedef struct ATTR_PACKED { - uint32_t clut_count; - uint32_t clut_data_offset; -} el_EBO_Palette; - -typedef struct ATTR_PACKED { - uint32_t type; - vg_lite_matrix_t matrix; - uint32_t count; -} el_EGO_Header; - - -#endif /* __ELM_HEADERS_H__ */ +/**************************************************************************** +* +* Copyright 2021 Vivante Corporation, Santa Clara, California. +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +#ifndef __ELM_HEADERS_H__ +#define __ELM_HEADERS_H__ + + +#define ATTR_PACKED __attribute__((packed, aligned(4))) + + +typedef struct { + vg_lite_matrix_t matrix; + uint32_t reserved; + uint32_t stop_count; + uint32_t stop_offset; + uint32_t color_offset; +} el_EVO_GradData; + +typedef struct { + vg_lite_radial_gradient_parameter_t params; + vg_lite_radial_gradient_spreadmode_t spread_mode; +} el_EVO_RadGradDataExt; + +struct el_PaintType_t { + uint32_t paint:28; + uint32_t flags:1; + uint32_t is_image:1; + uint32_t is_pattern:1; + uint32_t has_pattern:1; +}; + +typedef struct ATTR_PACKED { + uint32_t type; + vg_lite_float_t min_x, min_y, max_x, max_y; + uint32_t format; + uint32_t length:31; + uint32_t arc_flag:1; + uint32_t offset; + vg_lite_matrix_t matrix; + uint32_t reserved; + uint32_t quality; + uint32_t fill_rule; + uint32_t blend; + union { + uint32_t paint_data; + struct el_PaintType_t paint_type; + }; + vg_lite_color_t color; + el_EVO_GradData grad; +} el_EVO_Polygon; + +typedef struct ATTR_PACKED { + uint32_t type; + uint32_t namelength; + char eboname[76]; + union { + uint32_t paint_data; + struct el_PaintType_t paint_type; + }; + vg_lite_matrix_t matrix; + uint32_t width; + uint32_t height; +} el_EVO_Image; + +typedef struct ATTR_PACKED { + union { + el_EVO_Polygon polygon; + el_EVO_Image image; + }; +} el_EVO_Header; + +typedef struct ATTR_PACKED { + uint32_t type; + uint32_t size_font_block; + uint32_t num_ttf_fonts; + uint32_t num_vector_fonts; + uint32_t num_text_fonts; + uint32_t ttf_fonts_block_offset; + uint32_t ttf_fonts_block_length; + uint32_t vector_fonts_block_offset; + uint32_t vector_fonts_block_length; + uint32_t text_fonts_block_offset; + uint32_t text_fonts_block_length; + uint32_t property_block_offset; + uint32_t property_block_length; +} el_Font_Header; + +struct el_TextFlags_t { + uint32_t flags1:1; + uint32_t text_anchor:2; + uint32_t flags2:29; +}; + +typedef struct ATTR_PACKED { + uint32_t type; + uint32_t size_text_block; + uint32_t tspan_has_dx_dy; + float x_pos; + float y_pos; + float font_size; + uint32_t font_id; + uint32_t color; + union { + uint32_t flags_data; + struct el_TextFlags_t text_flags; + }; + vg_lite_matrix_t matrix; + uint32_t reserved; + uint16_t data_length; +} el_Text_Header; + +typedef struct ATTR_PACKED { + uint32_t type; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t tiled; + uint32_t format; + uint32_t data_offset; +} el_EBO_Header; + +typedef struct ATTR_PACKED { + uint32_t clut_count; + uint32_t clut_data_offset; +} el_EBO_Palette; + +typedef struct ATTR_PACKED { + uint32_t type; + vg_lite_matrix_t matrix; + uint32_t count; +} el_EGO_Header; + + +#endif /* __ELM_HEADERS_H__ */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_init.c b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_init.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_init.c rename to bsp/sdk_overlay/middleware/vglite/elementary/src/elm_init.c index 3c5f168..2318e9b 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_init.c +++ b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_init.c @@ -1,160 +1,160 @@ -/**************************************************************************** -* -* Copyright 2012 - 2020 Vivante Corporation, Santa Clara, California. -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -#include "elm_precom.h" -#include "elm_os.h" -#include "vg_lite_os.h" -#if (VG_RENDER_TEXT==1) -#include "elm_text.h" -#endif /* VG_RENDER_TEXT */ - -/* Prototypes */ -static int _initialize_elm(uint32_t width, uint32_t height); - -/* Initialize vg_lite related. */ -static int _initialize_vglite(int32_t width, int32_t height) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - - error = vg_lite_init(width, height); - - return (error == VG_LITE_SUCCESS); -} - -/* Initialize elm global objects. */ -static int _initialize_elm(uint32_t width, uint32_t height) -{ - vg_lite_error_t error; - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *)elm_os_get_tls(); - if (elm_tls == NULL) { - elm_tls = (elm_tls_t *)vg_lite_os_malloc(sizeof(elm_tls_t)); - error = elm_os_set_tls((void *) elm_tls); - if(error != VG_LITE_SUCCESS) - return error; - } - - int i; - - elm_tls->gContext.version = VERSION; - elm_tls->gContext.currentHandle = (ELM_NULL_HANDLE + 1); /* Reserve handle 0 for error */ - elm_tls->gContext.objectCount = 0; - elm_tls->gContext.tessellation_width = width; - elm_tls->gContext.tessellation_height = height; - elm_tls->gContext.vector_id = -1; - - for (i = 0; i < SLOT_COUNT; i++) { - elm_tls->gContext.object_slots[i] = NULL; - } - -#if (RTOS && DDRLESS) || BAREMETAL - for (i = 0; i < sizeof(elm_tls->gContext.objmap_ebo) / 4; i++) { - elm_tls->gContext.objmap_ebo[i] = 0; - } - for (i = 0; i < sizeof(elm_tls->gContext.objmap_evo) / 4; i++) { - elm_tls->gContext.objmap_evo[i] = 0; - } - for (i = 0; i < sizeof(elm_tls->gContext.objmap_group) / 4; i++) { - elm_tls->gContext.objmap_group[i] = 0; - } - for (i = 0; i < sizeof(elm_tls->gContext.objmap_grad) / 4; i++) { - elm_tls->gContext.objmap_grad[i] = 0; - } - - elm_tls->gContext.objcounter_grad = 0; - elm_tls->gContext.objcounter_evo = 0; - elm_tls->gContext.objcounter_ebo = 0; - elm_tls->gContext.objcounter_group = 0; -#endif - return 1; -} - -/* Terminate vg_lite related. */ -static void _terminate_vglite(void) -{ - vg_lite_close(); -} - -/* Terminate elm global objects. */ -static void _terminate_elm(void) -{ -#if (VG_RENDER_TEXT==1) - _release_default_text_parameters(); -#endif - elm_os_reset_tls(); -} - -/*! - @abstract Initialize Elementary context. - - @discussion - It should be called as the first function of Elemenatary libary, which initializes the library. Currently - Elementary library doesn't support context concept, neigher multi-threading. Elementary library defines - origin of coordinate system is at top-left. - - @param none - - @return none - */ -BOOL ElmInitialize(uint32_t width, uint32_t height) -{ - BOOL result = TRUE; - - do { - result = _initialize_vglite((int32_t)width, (int32_t)height); - - if (!result) - break; - - result = _initialize_elm(width, height); - - if (!result) - break; - } - while (0); - -#if (VG_RENDER_TEXT==1) - initialize_elm_text(); -#endif /* VG_RENDER_TEXT */ - return result; -} - -/*! - @abstract Terminate Elementary context. - - @discussion - This should be called when an app exits. It frees all the resource. - - @param none - - @return none - */ -void ElmTerminate(void) -{ - _terminate_elm(); - _terminate_vglite(); -} +/**************************************************************************** +* +* Copyright 2012 - 2020 Vivante Corporation, Santa Clara, California. +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +#include "elm_precom.h" +#include "elm_os.h" +#include "vg_lite_os.h" +#if (VG_RENDER_TEXT==1) +#include "elm_text.h" +#endif /* VG_RENDER_TEXT */ + +/* Prototypes */ +static int _initialize_elm(uint32_t width, uint32_t height); + +/* Initialize vg_lite related. */ +static int _initialize_vglite(int32_t width, int32_t height) +{ + vg_lite_error_t error = VG_LITE_SUCCESS; + + error = vg_lite_init(width, height); + + return (error == VG_LITE_SUCCESS); +} + +/* Initialize elm global objects. */ +static int _initialize_elm(uint32_t width, uint32_t height) +{ + vg_lite_error_t error; + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *)elm_os_get_tls(); + if (elm_tls == NULL) { + elm_tls = (elm_tls_t *)vg_lite_os_malloc(sizeof(elm_tls_t)); + error = elm_os_set_tls((void *) elm_tls); + if(error != VG_LITE_SUCCESS) + return error; + } + + int i; + + elm_tls->gContext.version = VERSION; + elm_tls->gContext.currentHandle = (ELM_NULL_HANDLE + 1); /* Reserve handle 0 for error */ + elm_tls->gContext.objectCount = 0; + elm_tls->gContext.tessellation_width = width; + elm_tls->gContext.tessellation_height = height; + elm_tls->gContext.vector_id = -1; + + for (i = 0; i < SLOT_COUNT; i++) { + elm_tls->gContext.object_slots[i] = NULL; + } + +#if (RTOS && DDRLESS) || BAREMETAL + for (i = 0; i < sizeof(elm_tls->gContext.objmap_ebo) / 4; i++) { + elm_tls->gContext.objmap_ebo[i] = 0; + } + for (i = 0; i < sizeof(elm_tls->gContext.objmap_evo) / 4; i++) { + elm_tls->gContext.objmap_evo[i] = 0; + } + for (i = 0; i < sizeof(elm_tls->gContext.objmap_group) / 4; i++) { + elm_tls->gContext.objmap_group[i] = 0; + } + for (i = 0; i < sizeof(elm_tls->gContext.objmap_grad) / 4; i++) { + elm_tls->gContext.objmap_grad[i] = 0; + } + + elm_tls->gContext.objcounter_grad = 0; + elm_tls->gContext.objcounter_evo = 0; + elm_tls->gContext.objcounter_ebo = 0; + elm_tls->gContext.objcounter_group = 0; +#endif + return 1; +} + +/* Terminate vg_lite related. */ +static void _terminate_vglite(void) +{ + vg_lite_close(); +} + +/* Terminate elm global objects. */ +static void _terminate_elm(void) +{ +#if (VG_RENDER_TEXT==1) + _release_default_text_parameters(); +#endif + elm_os_reset_tls(); +} + +/*! + @abstract Initialize Elementary context. + + @discussion + It should be called as the first function of Elemenatary libary, which initializes the library. Currently + Elementary library doesn't support context concept, neigher multi-threading. Elementary library defines + origin of coordinate system is at top-left. + + @param none + + @return none + */ +BOOL ElmInitialize(uint32_t width, uint32_t height) +{ + BOOL result = TRUE; + + do { + result = _initialize_vglite((int32_t)width, (int32_t)height); + + if (!result) + break; + + result = _initialize_elm(width, height); + + if (!result) + break; + } + while (0); + +#if (VG_RENDER_TEXT==1) + initialize_elm_text(); +#endif /* VG_RENDER_TEXT */ + return result; +} + +/*! + @abstract Terminate Elementary context. + + @discussion + This should be called when an app exits. It frees all the resource. + + @param none + + @return none + */ +void ElmTerminate(void) +{ + _terminate_elm(); + _terminate_vglite(); +} diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_object.c b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_object.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_object.c rename to bsp/sdk_overlay/middleware/vglite/elementary/src/elm_object.c index 742bc14..55c1852 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_object.c +++ b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_object.c @@ -1,2238 +1,2238 @@ -/**************************************************************************** -* -* Copyright 2012 - 2021 Vivante Corporation, Santa Clara, California. -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -#include "elm_precom.h" -#include "elm_os.h" -#include "vg_lite_text.h" -#include "vft_debug.h" -#include "elm_headers.h" - -#if (VG_RENDER_TEXT==1) -#include "elm_text.h" -#endif /* VG_RENDER_TEXT */ - -#if RTOS -#define BASE_ADDRESS_ALIGNMENT 32 -#else -#define BASE_ADDRESS_ALIGNMENT 4 -# endif -/* #define ENABLE_ELM_CRATE_OBJECT_FROM_FILE */ - -/* - * ANSI APIs are missing so application can use ElmCreateObjectFromData - * This simplifies things since file can be from FATFS, NOR Flash buffer etc. - */ - -#if (RTOS && DDRLESS) || BAREMETAL -/* Find some free objects, return the first index, - * and mark the bits as 1 (allocated). - * Params: - * free_map: the map bits of the objects where 0 is free and 1 is allocated; - * count : the element count of free_map[]; - * obj_count:how many objects to allocate from the pool. - * - * Return: - * The free index of the object in the pool. - * */ -int get_free_objects(int32_t free_map[], int count, int obj_count) -{ - int i, j; - int result = -1; - int counter = 0; - int bit_count = 0; - int32_t bits; - - /* Find a free bit. */ - for (i = 0; i < count; i++) { - bits = free_map[i]; - - for (j = 0; j < 32; j++) { - //Increase the bit counter. - bit_count++; - - if ((bits & 0x80000000) == 0) { - //Free bit is found. then count available free bits. - counter++; - } - else { - //Free bit is not found, reset the counter. - counter = 0; - } - - //Check to see whether enough bits are found. - if (counter >= obj_count) { - result = bit_count - counter; - - //Get out of the two loops. - i = count; - break; - } - - //Shift to next bit. - bits <<= 1; - } - } - - /* Mark the bits as allocated if OK. */ - if (result > -1) { - int bits_set = 1; - int bit_offset = result % 32; - bit_count = result / 32; - - while (obj_count > 0) { - bits_set = ~(0xffffffff << (32 - bit_offset)); - if (obj_count <= 32 - bit_offset) { - //Done. - bits_set = bits_set & (0xffffffff << (32 - bit_offset - obj_count)); - free_map[bit_count] |= bits_set; - break; - } - free_map[bit_count] |= bits_set; - - //Go to next map element. - obj_count -= (32 - bit_offset); - bit_count++; - bit_offset = 0; - } - } - - return result; -} - -/* When an object is "freed", mark the corresponding bits to 0. */ -void mark_free_object(int32_t free_map[], int object) -{ - int index, offset; - - index = object / 32; - offset = object % 32; - - free_map[index] &= ~(1 << (31 - offset)); -} - -/* Check whether an object (with given index) allocated or not. */ -int object_exists(int32_t free_map[], int index) -{ - int32_t bits; - int offset = index % 32; - index /= 32; - - bits = ~(1 << (31 - offset)); - - if (free_map[index] & bits) { - return 1; - } - else { - return 0; - } -} - -/* Allocate an EVO object from pool. */ -static el_Obj_EVO * alloc_evo(int count) -{ - elm_tls_t* elm_tls; - int index; - el_Obj_EVO *object = NULL; - - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return NULL; - - index = get_free_objects(elm_tls->gContext.objmap_evo, COUNT_OF(elm_tls->gContext.objmap_evo), count); - - if (index > -1) { - object = &elm_tls->gContext.objpool_evo[index]; - elm_tls->gContext.objcounter_evo += count; - for (; count > 0; count--) { - object[count - 1].object.index = index + count - 1; - } - } - - return object; -} - -/* Allocate an EBO object from pool. */ -static el_Obj_EBO * alloc_ebo() -{ - elm_tls_t* elm_tls; - int index; - el_Obj_EBO *object = NULL; - - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return NULL; - - index = get_free_objects(elm_tls->gContext.objmap_ebo, COUNT_OF(elm_tls->gContext.objmap_ebo), 1); - - if (index > -1) { - object = &elm_tls->gContext.objpool_ebo[index]; - object->object.index = index; - elm_tls->gContext.objcounter_ebo++; - } - - return object; -} - -/* Allocate an EGO object from pool. */ -static el_Obj_Group * alloc_ego() -{ - elm_tls_t* elm_tls; - int index; - el_Obj_Group *object = NULL; - - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return NULL; - - index = get_free_objects(elm_tls->gContext.objmap_group, COUNT_OF(elm_tls->gContext.objmap_group), 1); - - if (index > -1) { - object = &elm_tls->gContext.objpool_group[index]; - object->object.index = index; - elm_tls->gContext.objcounter_group++; - } - - return object; -} - -/* Mark an EGO object as free: insert it into the free list. */ -static void free_ego(el_Obj_Group *object) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return NULL; - - mark_free_object(elm_tls->gContext.objmap_group, elm_tls->object->object.index); - elm_tls->gContext.objcounter_group--; -} - -/* Allocate a grad object from pool. */ -static el_Obj_Grad * alloc_grad() -{ - elm_tls_t* elm_tls; - int index; - el_Obj_Grad *object = NULL; - - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return NULL; - - index = get_free_objects(elm_tls->gContext.objmap_grad, COUNT_OF(elm_tls->gContext.objmap_grad), 1); - - if (index > -1) { - object = &elm_tls->gContext.objpool_grad[index]; - object->object.index = index; - elm_tls->gContext.objcounter_grad++; - } - - return object; -} - -#endif -/* Internal Implementations *******************************/ -int deref_object(el_Object *object) -{ - object->reference--; - return object->reference; -} - -int ref_object(el_Object *object) -{ - object->reference++; - return object->reference; -} - -int add_object(el_Object *object) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return 0; -#if (RTOS && DDRLESS) || BAREMETAL - /* Assign handle. */ - object->handle = elm_tls->gContext.currentHandle++; - return 1; -#else - int result = 1; - el_ObjList *list = NULL; - - /* Assign handle. */ - object->handle = elm_tls->gContext.currentHandle++; - - /* Get the list slot. */ - list = OBJECT_SLOT(object->handle); - if (list == NULL) { - list = (el_ObjList *) elm_alloc(1, sizeof(el_ObjList)); - if ( list == NULL ) { - return 0; /* Memory allocation failed */ - } -#ifdef ENABLE_STRICT_DEBUG_MEMSET - memset(list, 0, sizeof(el_ObjList)); -#endif - - OBJECT_SLOT(object->handle) = list; - - list->object = object; - list->next = NULL; - - return 1; - } - - /* Insert the object. */ - while (list->next != NULL) { - list = list->next; - } - list->next = (el_ObjList *) elm_alloc(1, sizeof(el_ObjList)); - if ( list->next == NULL ) { - return 0; /* Memory allocation failed */ - } -#ifdef ENABLE_STRICT_DEBUG_MEMSET - memset(list->next, 0, sizeof(el_ObjList)); -#endif - list = list->next; - list->object = object; - list->next = NULL; - - return result; -#endif -} - -int remove_object(el_Object *object) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return 0; - - int result = 0; -#if (!(RTOS && DDRLESS)) && (!BAREMETAL) - el_ObjList *list = NULL, *node = NULL; - - // Get the list slot. - list = OBJECT_SLOT(object->handle); - - // Invalid. - if (list == NULL) - return 0; - - // Find the object. - if (list->object == object) { - OBJECT_SLOT(object->handle) = list->next; - elm_free(list); - return 1; - } - - while (list->next != NULL) { - if (list->next->object == object) { - node = list->next; - list->next = list->next->next; - elm_free(node); - return 1; - } - list = list->next; - } -#endif - - return result; -} - -el_Object *get_object(ElmHandle handle) -{ - elm_tls_t* elm_tls; - el_Object *object = NULL; - - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return NULL; - -#if (RTOS && DDRLESS) || BAREMETAL - int i; - for (i = 0; i < OBJCOUNT_EVO; i++) { - if (object_exists(elm_tls->gContext.objmap_evo, i)) { - if (elm_tls->gContext.objpool_evo[i].object.handle == handle) { - object = (el_Object *)&elm_tls->gContext.objpool_evo[i]; - return object; - } - } - } - for (i = 0; i < OBJCOUNT_EBO; i++) { - if (object_exists(elm_tls->gContext.objmap_ebo, i)) { - if (elm_tls->gContext.objpool_ebo[i].object.handle == handle) { - object = (el_Object *)&elm_tls->gContext.objpool_ebo[i]; - return object; - } - } - } - for (i = 0; i < OBJCOUNT_GRAD; i++) { - if (object_exists(elm_tls->gContext.objmap_grad, i)) { - if (elm_tls->gContext.objpool_grad[i].object.handle == handle) { - object = (el_Object *)&elm_tls->gContext.objpool_grad[i]; - return object; - } - } - } - for (i = 0; i < OBJCOUNT_GROUP; i++) { - if (object_exists(elm_tls->gContext.objmap_group, i)) { - if (elm_tls->gContext.objpool_group[i].object.handle == handle) { - object = (el_Object *)&elm_tls->gContext.objpool_group[i]; - return object; - } - } - } -#else - el_ObjList *list = NULL; - - // Get the slot. - list = OBJECT_SLOT(handle); - - // Find the object. - while (list != NULL) { - if ((list->object != NULL) && - (list->object->handle == handle)) { - object = list->object; - return object; - } - list = list->next; - } -#endif - - DEBUG_ASSERT(0, "Unknown object"); - return NULL; -} - -#if (RTOS && DDRLESS) || BAREMETAL -static void free_grad(el_Obj_Grad *object) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls != NULL) { - mark_free_object(elm_tls->gContext.objmap_grad, object->object.index); - elm_tls->gContext.objcounter_grad--; - } -} -#endif - -/* Destroy an evo object data. */ -int destroy_evo(el_Obj_EVO *evo) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return 0; - -#if (RTOS && DDRLESS) || BAREMETAL - mark_free_object(elm_tls->gContext.objmap_evo, evo->object.index); - elm_tls->gContext.objcounter_evo--; - free_grad(evo->defaultAttrib.paint.grad); -#else - - if ( evo->defaultAttrib.paint.type == ELM_PAINT_TEXT ) { -#if (VG_RENDER_TEXT==1) - _unload_text(evo); -#else - ; -#endif /* VG_RENDER_TEXT */ - } else { - /* TODO: EVO destroy not done yet. */ - if (evo->defaultAttrib.paint.grad != NULL) { - vg_lite_clear_grad(&evo->defaultAttrib.paint.grad->data.grad); - elm_free(evo->defaultAttrib.paint.grad); - evo->defaultAttrib.paint.grad = NULL; - } - - if (evo->data.path.path != NULL) { - vg_lite_clear_path(&evo->data.path); - elm_free(evo->data.path.path); - evo->data.path.path = NULL; - } - } - - remove_object(&evo->object); -#endif - -#if (VG_RENDER_TEXT==1) - destroy_font_data(); -#endif /* VG_RENDER_TEXT */ - return 1; -} - -/* Destroy an ego object data. */ -int destroy_ego(el_Obj_Group *ego) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if(elm_tls == NULL) - return 0; - -#if (RTOS && DDRLESS) || BAREMETAL - mark_free_object(elm_tls->gContext.objmap_group, ego->object.index); - elm_tls->gContext.objcounter_group--; -#else - int i; - for (i = 0; i < ego->group.count; i++) - { - destroy_evo(&ego->group.objects[i]); - } - elm_free(ego->group.objects); - elm_free(ego); -#endif - -#if (VG_RENDER_TEXT==1) - destroy_font_data(); -#endif /* VG_RENDER_TEXT */ - return 1; -} - -/* Destroy an ebo object data. */ -int destroy_ebo(el_Obj_EBO *ebo) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if(elm_tls == NULL) - return 0; - -#if (RTOS && DDRLESS) || BAREMETAL - mark_free_object(elm_tls->gContext.objmap_ebo, ebo->object.index); - elm_tls->gContext.objcounter_ebo--; -#else - if ( ebo != NULL && ebo->data.buffer.handle != NULL) { - vg_lite_free(&ebo->data.buffer); - } - elm_free(ebo); -#endif - return 1; -} - -/* Destroy an object. - return: - -1: any error; - 0: destroyed when reference count is 0; - 1: decreased reference count but still > 0. - */ -int destroy_object(ElmHandle handle) -{ - el_Object *object = NULL; - int ref_count = 0; - - object = get_object(handle); - - // No such object. - if (object == NULL) { - DEBUG_ASSERT(0, "No such object"); - return -1; - } - - // Dereference object, and destroy if it's no more referred. - ref_count = deref_object(object); - if (ref_count == 0) { - remove_object(object); - - switch (object->type) { - case ELM_OBJECT_TYPE_EVO: - destroy_evo((el_Obj_EVO *)object); - elm_free(object); - break; - - case ELM_OBJECT_TYPE_EGO: - destroy_ego((el_Obj_Group *) object); - break; - - case ELM_OBJECT_TYPE_EBO: - destroy_ebo((el_Obj_EBO *) object); - break; - - default: - DEBUG_ASSERT(0, "Unknow object type"); - break; - } - } - - return 1; -} - -void _init_transform(el_Transform *transform) -{ - int i = 0; - transform->rotate = 0.0f; - for (i = 0;i < 2; i++) - { - transform->scale[i] = 1.0f; - transform->translate[i] = 0.0f; - } - vg_lite_identity(&transform->matrix); -} - -/* Static functions. *************************************************/ - -/* Get the specified vector object in a group. */ -static el_Obj_EVO* _get_evo(el_Obj_Group *group, int32_t id) -{ - if ((id >= group->group.count) || - (id < 0)){ - return (el_Obj_EVO*)NULL; - } - else { - return (el_Obj_EVO*)(group->group.objects + id); - } -} - -#if (VG_RENDER_TEXT==1) -static int _load_font(uint8_t *data, - unsigned size) -{ - ElmHandle ret = ELM_NULL_HANDLE; - el_Font_Header *font_header = (el_Font_Header *)data; - - - if (font_header->size_font_block != size) - return ret; - - return _load_font_data(data); -} - -static ElmHandle _load_text(uint8_t *data, - unsigned size, - el_Obj_EVO *evo) -{ - ElmHandle ret = ELM_NULL_HANDLE; - el_Text_Header *text_header = (el_Text_Header *)data; - - - if (text_header->size_text_block != size) - return ret; - - return _load_text_data(data, evo); -} -#endif /* VG_RENDER_TEXT */ - -#if (defined(__ICCARM__)) -/* - * Disable the unaligned structure attribute warning. Due to the packed data - * structures used to interpret ELM objects data the IAR compiler issues a - * number of warnings that certain attributes of the headers might be unaligned. - * This is not true, however, as all atributes are manually aligned to 4 bytes. - */ -#pragma diag_suppress = Pa039 -#endif - -static ElmHandle _load_evo(const uint8_t *data, unsigned size, el_Obj_EVO *evo) -{ - int i = 0; -#if (RTOS && DDRLESS) || BAREMETAL - uint32_t colors[VLC_MAX_GRAD]; - void *path_data; -#else - uint32_t *colors = NULL; - uint8_t *path_data = NULL; -#endif - el_Obj_EVO *local_evo = NULL; - el_EVO_Header *evo_header = (el_EVO_Header *) data; - - if (evo == NULL) { -#if (RTOS && DDRLESS) || BAREMETAL - local_evo = alloc_evo(1); -#else - local_evo = (el_Obj_EVO *)elm_alloc(1, sizeof(el_Obj_EVO)); -#endif - evo = local_evo; - } - JUMP_IF_NULL(evo, error_exit); - memset(evo, 0, sizeof(el_Obj_EVO)); - - /* - * Check if object size is valid. The size parameter - * needs to be a value greater or equal to the - * size of the current object to be loaded. - * This check needs to be done in order to ensure - * that the is_image field is correctly read and - * we do not read from invalid memory. - */ - JUMP_IF_LOWER(size, - MIN(sizeof(el_EVO_Polygon), sizeof(el_EVO_Image)), - error_exit); - - if(evo_header->polygon.paint_type.is_image) - { - /* - * Check if object size is valid - * (greater or equal to el_EVO_Image size). - */ - JUMP_IF_LOWER(size, - sizeof(el_EVO_Image), - error_exit); - memcpy(evo->eboname, - evo_header->image.eboname, - evo_header->image.namelength); - evo->is_image = evo_header->image.paint_type.is_image; - _init_transform(&evo->defaultAttrib.transform); - memcpy(&evo->defaultAttrib.transform.matrix, - &(evo_header->image.matrix), - sizeof(vg_lite_matrix_t)); - evo->img_width = evo_header->image.width; - evo->img_height = evo_header->image.height; - } - else - { - /* - * Check if object size is valid - * (greater or equal to el_EVO_Polygon size). - */ - JUMP_IF_LOWER(size, - sizeof(el_EVO_Polygon), - error_exit); - el_Transform *transform = NULL; - el_Transform *grad_transform = NULL; - el_EVO_Polygon *object_data = (el_EVO_Polygon *) &(evo_header->polygon); - el_EVO_GradData *grad_data = (el_EVO_GradData *) &(evo_header->polygon.grad); - - /* Get path data from the object. */ -#if (RTOS && DDRLESS) || BAREMETAL - path_data = (void *) (data + object_data->offset); -#else - path_data = (uint8_t *)elm_alloc(1, object_data->length); - JUMP_IF_NULL(path_data, error_exit); - -#ifdef ENABLE_STRICT_DEBUG_MEMSET - memset(path_data, 0, object_data->length); -#endif - JUMP_IF_LOWER(size, - object_data->offset + object_data->length, - error_exit); - /* Get path data. */ - memcpy(path_data, (void *)(data + object_data->offset), - object_data->length); -#endif - - if(object_data->paint_type.has_pattern) - evo->has_pattern = 1; - if(object_data->paint_type.is_pattern) - evo->is_pattern = 1; - - _init_transform(&evo->defaultAttrib.transform); - transform = &evo->defaultAttrib.transform; - - evo->object.type = ELM_OBJECT_TYPE_EVO; - evo->object.reference = 0; - - if ((object_data->paint_type.paint == ELM_PAINT_RADIAL_GRADIENT) || - (object_data->paint_type.paint == ELM_PAINT_GRADIENT)) { -#if (RTOS && DDRLESS) || BAREMETAL - evo->defaultAttrib.paint.grad = alloc_grad(); -#else - evo->defaultAttrib.paint.grad = (el_Obj_Grad*)elm_alloc(1, sizeof(el_Obj_Grad)); -#endif - JUMP_IF_NULL(evo->defaultAttrib.paint.grad, error_exit); -#ifdef ENABLE_STRICT_DEBUG_MEMSET - memset(evo->defaultAttrib.paint.grad, 0, sizeof(el_Obj_Grad)); -#endif - evo->defaultAttrib.paint.grad->data.grad.image.width = 0; - evo->defaultAttrib.paint.grad->data.grad.image.height = 0; - evo->defaultAttrib.paint.grad->data.grad.image.stride = 0; - evo->defaultAttrib.paint.grad->data.grad.image.tiled = VG_LITE_LINEAR; - - _init_transform(&evo->defaultAttrib.paint.grad->data.transform); - grad_transform = &evo->defaultAttrib.paint.grad->data.transform; - memcpy(&grad_transform->matrix, &(grad_data->matrix), - sizeof(vg_lite_matrix_t)); - colors = (uint32_t *)elm_alloc(grad_data->stop_count, sizeof(uint32_t)); - JUMP_IF_NULL(colors, error_exit); - memcpy(colors, - data + grad_data->color_offset, - grad_data->stop_count * sizeof(uint32_t)); - } - - if (object_data->arc_flag) - vg_lite_init_arc_path(&evo->data.path, - (vg_lite_format_t) object_data->format, - (vg_lite_quality_t) object_data->quality, - object_data->length, - path_data, - object_data->min_x, - object_data->min_y, - object_data->max_x, - object_data->max_y); - else - vg_lite_init_path(&evo->data.path, - (vg_lite_format_t) object_data->format, - (vg_lite_quality_t) object_data->quality, - object_data->length, - path_data, - object_data->min_x, - object_data->min_y, - object_data->max_x, - object_data->max_y); - - memcpy(&transform->matrix, &(object_data->matrix), sizeof(vg_lite_matrix_t)); - - evo->defaultAttrib.quality = ELM_QUALITY_LOW; - evo->defaultAttrib.fill_rule = (ELM_EVO_FILL) object_data->fill_rule; - evo->defaultAttrib.blend = (ELM_BLEND) object_data->blend; - evo->defaultAttrib.paint.type = (ELM_PAINT_TYPE) object_data->paint_type.paint; - - switch (object_data->paint_type.paint) { - case ELM_PAINT_GRADIENT: - { -#if (RTOS && DDRLESS) || BAREMETAL - uint32_t stops[VLC_MAX_GRAD]; -#else - uint32_t *stops = NULL; - - stops = (uint32_t *)elm_alloc(sizeof(uint32_t), grad_data->stop_count); - JUMP_IF_NULL(stops, error_exit); -#endif - for (i = 0 ;i < grad_data->stop_count; i++) - { - stops[i] = (uint32_t)((*(float *) (data + - grad_data->stop_offset + i * 4)) * 255); - } - - vg_lite_init_grad(&evo->defaultAttrib.paint.grad->data.grad); - vg_lite_set_grad(&evo->defaultAttrib.paint.grad->data.grad, - grad_data->stop_count, colors, stops); - if (grad_data->stop_count > 0) - { - vg_lite_update_grad(&evo->defaultAttrib.paint.grad->data.grad); - } -#if (RTOS && DDRLESS) || BAREMETAL -#else - elm_free(stops); -#endif - break; - } - case ELM_PAINT_RADIAL_GRADIENT: - { - float *stops; - vg_lite_color_ramp_t *vgColorRamp; - el_EVO_RadGradDataExt *rad_grad = (el_EVO_RadGradDataExt *) (data + sizeof(el_EVO_Header)); - - JUMP_IF_LOWER(size, - sizeof(el_EVO_Polygon) + sizeof(el_EVO_RadGradDataExt), - error_exit); - - stops = (float *)elm_alloc(grad_data->stop_count, sizeof(float)); - JUMP_IF_NULL(stops, error_exit); - memset(stops, 0, grad_data->stop_count * sizeof(float)); - vgColorRamp = (vg_lite_color_ramp_t *) elm_alloc(grad_data->stop_count, - sizeof(vg_lite_color_ramp_t)); - if (vgColorRamp == NULL) { - elm_free(stops); - goto error_exit; - } - memset(vgColorRamp, 0, - sizeof(vg_lite_color_ramp_t) * grad_data->stop_count); - for (i = 0; i < grad_data->stop_count; i++) - { - stops[i] = (*(float *) (data + grad_data->stop_offset + i * 4)); - vgColorRamp[i].alpha = (float)(colors[i] >> 24) / 255.0f; - vgColorRamp[i].red = (float)(colors[i] >> 16 & 0xFF) / 255.0f; - vgColorRamp[i].green = (float)(colors[i] >> 8 & 0xFF) / 255.0f; - vgColorRamp[i].blue = (float)(colors[i] & 0xFF) / 255.0f; - vgColorRamp[i].stop = stops[i]; - } - - memset(&evo->defaultAttrib.paint.radgrad->data.rad_grad, 0, sizeof(evo->defaultAttrib.paint.radgrad->data.rad_grad)); - vg_lite_set_rad_grad(&evo->defaultAttrib.paint.radgrad->data.rad_grad, - grad_data->stop_count, - vgColorRamp, - rad_grad->params, - rad_grad->spread_mode, - 0); - vg_lite_update_rad_grad(&evo->defaultAttrib.paint.radgrad->data.rad_grad); - - elm_free(stops); - elm_free(vgColorRamp); - break; - } - default: - /* Do nothing */ - break; - } - - evo->defaultAttrib.paint.color = object_data->color; - evo->attribute = evo->defaultAttrib; - ref_object(&evo->object); - JUMP_IF_NON_ZERO_VALUE(add_object(&evo->object), error_exit); - -#if (RTOS && DDRLESS) || BAREMETAL -#else - elm_free(colors); -#endif - } - - return evo->object.handle; - -error_exit: -#if (RTOS && DDRLESS) || BAREMETAL -#else - if ( colors != NULL ) - elm_free(colors); - if ( path_data != NULL) - elm_free(path_data); -#endif - - if ( (evo != NULL) && (evo->defaultAttrib.paint.grad != NULL) ) - elm_free(evo->defaultAttrib.paint.grad); - if ( (evo != NULL) && (evo->defaultAttrib.paint.radgrad != NULL) ) - elm_free(evo->defaultAttrib.paint.radgrad); - if ( local_evo != NULL ) - elm_free(local_evo); - - return ELM_NULL_HANDLE; -} - -static ElmHandle _load_ebo(const uint8_t *data, int size, uint32_t version) -{ - vg_lite_error_t error; - vg_lite_buffer_t *buffer; - uint32_t *colors, bytes = 0; - - el_EBO_Header *ebo_header = (el_EBO_Header *) data; - -#if (RTOS && DDRLESS) || BAREMETAL - el_Obj_EBO *ebo = alloc_ebo(); -#else - el_Obj_EBO *ebo = (el_Obj_EBO *)elm_alloc(1, (sizeof(el_Obj_EBO))); -#endif - JUMP_IF_NULL(ebo, error_exit); -#ifdef ENABLE_STRICT_DEBUG_MEMSET - memset(ebo, 0, sizeof(el_Obj_EBO)); -#endif - buffer = &ebo->data.buffer; - - /* - * Check if object size is valid. "size" needs to be a value greater than or - * equal to the size of the current object header. - */ - JUMP_IF_LOWER(size, sizeof(el_EBO_Header), error_exit); - bytes += sizeof(el_EBO_Header); - - if(version == 1) - { - el_EBO_Palette *clut_header = (el_EBO_Palette *) (data + sizeof(el_EBO_Header)); - - /* Make sure object size includes the CLUT header */ - bytes += sizeof(el_EBO_Palette); - JUMP_IF_LOWER(size, bytes, error_exit); - - ebo->object.type = (ELM_OBJECT_TYPE) ebo_header->type; - ebo->object.reference = 0; - - buffer->width = ebo_header->width; - buffer->height = ebo_header->height; - buffer->format = (vg_lite_buffer_format_t) ebo_header->format; - buffer->stride = 0; - - error = vg_lite_allocate(buffer); - if (error != VG_LITE_SUCCESS) - { - destroy_ebo(ebo); - return 0; - } - - buffer->stride = ebo_header->stride; - buffer->tiled = (vg_lite_buffer_layout_t) ebo_header->tiled; - colors = (uint32_t *)(data + clut_header->clut_data_offset); - - /* Make sure the object size includes image data */ - JUMP_IF_LOWER(size, - ebo_header->data_offset + - (buffer->stride * buffer->height), - error_exit); - - memcpy(buffer->memory, - data + ebo_header->data_offset, - buffer->stride * buffer->height); - - /* Save CLUT infomation. */ - ebo->clut_count = clut_header->clut_count; - - /* Make sure object size includes CLUT data */ - JUMP_IF_LOWER(size, - clut_header->clut_data_offset + - (sizeof(uint32_t) * clut_header->clut_count), - error_exit); - - memcpy(ebo->clut, colors, sizeof(uint32_t) * clut_header->clut_count); - } - else if(version == 2) - { - ebo->object.type = (ELM_OBJECT_TYPE) ebo_header->type; - ebo->object.reference = 0; - - buffer->width = ebo_header->width; - buffer->height = ebo_header->height; - buffer->format = (vg_lite_buffer_format_t) ebo_header->format; - buffer->stride = 0; - - error = vg_lite_allocate(buffer); - if (error != VG_LITE_SUCCESS) - { - destroy_ebo(ebo); - return 0; - } - - buffer->stride = ebo_header->stride; - buffer->tiled = (vg_lite_buffer_layout_t) ebo_header->tiled; - - /* Make sure the object size includes image data */ - JUMP_IF_LOWER(size, - ebo_header->data_offset + - (buffer->stride * buffer->height), - error_exit); - - memcpy(buffer->memory, - data + ebo_header->data_offset, - buffer->stride * buffer->height); - } - /* Set transformation to identity. */ - ebo->defaultAttrib.transform.dirty = 1; - ebo->defaultAttrib.transform.identity = 1; - - _init_transform(&ebo->defaultAttrib.transform); - ebo->attribute = ebo->defaultAttrib; - - ref_object(&ebo->object); - JUMP_IF_NON_ZERO_VALUE(add_object(&ebo->object), error_exit); - - return ebo->object.handle; - -error_exit: - if (ebo != NULL ) { - elm_free(ebo); - } - - return ELM_NULL_HANDLE; -} - -static ElmHandle _load_ego(const uint8_t *data, int size) -{ - int i; - unsigned int invalid_count = 0; - uint32_t *obj_size, *obj_offset, *obj_type; - void *obj_data; - el_EGO_Header *ego_header = (el_EGO_Header *) data; - -#if (RTOS && DDRLESS) || BAREMETAL - el_Obj_Group *ego = alloc_ego(); -#else - el_Obj_Group *ego = (el_Obj_Group *)elm_alloc(1, sizeof(el_Obj_Group)); -#endif - JUMP_IF_NULL(ego, error_exit); -#ifdef ENABLE_STRICT_DEBUG_MEMSET - memset(ego, 0, sizeof(el_Obj_Group)); -#endif - - ego->object.type = (ELM_OBJECT_TYPE) ego_header->type; - ego->object.reference = 0; - - _init_transform(&ego->defaultTrans); - memcpy(&(ego->defaultTrans.matrix.m), - &(ego_header->matrix), - sizeof(vg_lite_matrix_t)); - ego->group.count = ego_header->count; -#if (RTOS && DDRLESS) || BAREMETAL - ego->group.objects = alloc_evo(ego->group.count); -#else - ego->group.objects = (el_Obj_EVO *)elm_alloc(1, ego->group.count * sizeof(el_Obj_EVO)); -#endif - JUMP_IF_NULL(ego->group.objects, error_exit); -#ifdef ENABLE_STRICT_DEBUG_MEMSET - memset(ego->group.objects, 0, ego->group.count * sizeof(el_Obj_EVO)); -#endif - - obj_size = (uint32_t *)((unsigned)data + sizeof(el_EGO_Header)); - obj_offset = (uint32_t *)((unsigned)obj_size + \ - (ego_header->count * sizeof(uint32_t))); - - for (i = 0; i < ego->group.count && obj_offset[i] < size; i++) - { - if (obj_size[i] == 0) { - invalid_count++; - continue; - } - - /* Check whether EVO object is truncated */ - JUMP_IF_GREATER(obj_offset[i] + obj_size[i], size, error_exit); - - /* Call appropriate object loader according to object type */ - obj_data = (void*)((unsigned)data + obj_offset[i]); - obj_type = obj_data; - switch (*obj_type) { - case ELM_OBJECT_TYPE_EVO: - ego->group.objects[i].object.handle = _load_evo(obj_data, - obj_size[i], - &ego->group.objects[i]); - break; -#if (VG_RENDER_TEXT==1) - case ELM_OBJECT_TYPE_FONT: - _load_font(obj_data, obj_size[i]); - break; - case ELM_OBJECT_TYPE_TEXT: - ego->group.objects[i].object.handle = _load_text(obj_data, - obj_size[i], - &ego->group.objects[i]); - break; -#endif /* VG_RENDER_TEXT */ - default: - break; - } - } - - ego->group.count -= invalid_count; - ego->transform = ego->defaultTrans; - - ref_object(&ego->object); - JUMP_IF_NON_ZERO_VALUE(add_object(&ego->object), error_exit); - - return ego->object.handle; - -error_exit: - if (ego != NULL ) { - if ( ego->group.objects != NULL ) { - elm_free(ego->group.objects); - } - elm_free(ego); - } - - return ELM_NULL_HANDLE; -} - -#if (defined(__ICCARM__)) -/* Restore the unaligned data structure attribute warning */ -#pragma diag_default = Pa039 -#endif - -static BOOL _scale(ElmHandle obj, float x, float y) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return FALSE; - - el_Object *object = get_object(obj); - el_Obj_EBO *ebo = NULL; - el_Obj_EVO *evo = NULL; - el_Obj_Group *ego = NULL; - el_Transform *transform = NULL; - - switch (object->type) { - case ELM_OBJECT_TYPE_EBO: - ebo = (el_Obj_EBO *)object; - transform = &ebo->attribute.transform; - break; - - case ELM_OBJECT_TYPE_EGO: - ego = (el_Obj_Group *)object; - if (elm_tls->gContext.vector_id < 0) { - transform = &ego->transform; - } - else { - evo = _get_evo(ego, elm_tls->gContext.vector_id); - if (evo != NULL) { - transform = &evo->attribute.transform; - } - else { /* No such vector object to set. */ - return FALSE; - } - } - break; - - case ELM_OBJECT_TYPE_EVO: - evo = (el_Obj_EVO *)object; - transform = &evo->attribute.transform; - break; - - default: - DEBUG_ASSERT(0, "Bad object type"); - break; - } - - // Update the transformation params. - transform->scale[0] *= x; - transform->scale[1] *= y; - - vg_lite_scale(x, y, &transform->matrix); - - // Clean dirty. - transform->dirty = FALSE; - - return TRUE; -} - -static BOOL _reset_attrib(ElmHandle obj, ELM_EVO_PROP_BIT mask) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return FALSE; - - el_Object *object = get_object(obj); - el_Obj_EBO *ebo = NULL; - el_Obj_EVO *evo = NULL; - el_Obj_Group *ego = NULL; - el_Attribute *attrib = NULL; - el_Attribute *defaultAttr = NULL; - el_Transform *transform = NULL; - el_Transform *defaultTrans = NULL; - - switch (object->type) { - case ELM_OBJECT_TYPE_EBO: - ebo = (el_Obj_EBO *)object; - attrib = &ebo->attribute; - defaultAttr = &ebo->defaultAttrib; - transform = &attrib->transform; - defaultTrans = &defaultAttr->transform; - break; - - case ELM_OBJECT_TYPE_EGO: - ego = (el_Obj_Group *)object; - if (elm_tls->gContext.vector_id < 0) { - transform = &ego->transform; - defaultTrans = &ego->defaultTrans; - } - else { - evo = _get_evo((el_Obj_Group*)obj, elm_tls->gContext.vector_id); - if (evo != NULL) { - attrib = &evo->attribute; - defaultAttr = &evo->defaultAttrib; - transform = &attrib->transform; - defaultTrans = &defaultAttr->transform; - } - else { - return FALSE; - } - } - break; - - case ELM_OBJECT_TYPE_EVO: - evo = (el_Obj_EVO *)object; - attrib = &evo->attribute; - defaultAttr = &evo->defaultAttrib; - transform = &attrib->transform; - defaultTrans = &defaultAttr->transform; - break; - - default: - DEBUG_ASSERT(0, "Bad object type"); - return FALSE; - break; - } - - // Update the attribute value. When transform is modified, update the matrix. - if (mask & ELM_PROP_ROTATE_BIT) { - transform->rotate = defaultTrans->rotate; - } - - if (mask & ELM_PROP_TRANSFER_BIT) { - transform->translate[0] = defaultTrans->translate[0]; - transform->translate[1] = defaultTrans->translate[1]; - } - - if (mask & ELM_PROP_SCALE_BIT) { - transform->scale[0] = defaultTrans->scale[0]; - transform->scale[1] = defaultTrans->scale[1]; - } - - /* On any bit reset, reset the whole matrix to the default one. */ - if (mask & (ELM_PROP_ROTATE_BIT | ELM_PROP_TRANSFER_BIT | ELM_PROP_SCALE_BIT)) { - memcpy(&(transform->matrix), &(defaultTrans->matrix), sizeof(defaultTrans->matrix)); - transform->dirty = FALSE; - } - - /* Update other rendering attributes. */ - if (mask & ELM_PROP_BLEND_BIT) { - attrib->blend = defaultAttr->blend; - } - - if (mask & ELM_PROP_QUALITY_BIT) { - attrib->quality = defaultAttr->quality; - } - - if (mask & ELM_PROP_FILL_BIT) { - attrib->fill_rule = defaultAttr->fill_rule; - } - - if (mask & ELM_PROP_COLOR_BIT) { - attrib->paint.color = defaultAttr->paint.color; - } - - if (mask & ELM_PROP_PAINT_BIT) { - attrib->paint.type = defaultAttr->paint.type; - } - - return TRUE; -} - -static BOOL _set_quality(ElmHandle obj, ELM_QUALITY quality) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return FALSE; - - el_Object *object = get_object(obj); - el_Obj_EBO *ebo = NULL; - el_Obj_EVO *evo = NULL; - el_Obj_Group *group = NULL; - el_Attribute *attrib = NULL; - - switch (object->type) { - case ELM_OBJECT_TYPE_EBO: - ebo = (el_Obj_EBO *)object; - attrib = &ebo->attribute; - break; - - case ELM_OBJECT_TYPE_EVO: - evo = (el_Obj_EVO *)object; - attrib = &evo->attribute; - break; - - case ELM_OBJECT_TYPE_EGO: - group = (el_Obj_Group *)object; - evo = _get_evo(group, elm_tls->gContext.vector_id); - if (evo != NULL) { - attrib = &evo->attribute; - } - else { - return FALSE; - } - break; - default: - DEBUG_ASSERT(0, "Bad object type"); - return FALSE; - break; - } - - attrib->quality = quality; - - return TRUE; -} - -static BOOL _set_fill(ElmVecObj evo, ELM_EVO_FILL fill) -{ - el_Obj_EVO *object = (el_Obj_EVO *)get_object(evo); - - if (object == NULL) { - DEBUG_ASSERT(0, "Bad object handle"); - return FALSE; - } - - object->attribute.fill_rule = fill; - - return TRUE; -} - -static BOOL _set_blend(ElmHandle obj, ELM_BLEND blend) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return FALSE; - - el_Object *object = get_object(obj); - el_Obj_EBO *ebo = NULL; - el_Obj_EVO *evo = NULL; - el_Obj_Group *group = NULL; - el_Attribute *attrib = NULL; - - switch (object->type) { - case ELM_OBJECT_TYPE_EBO: - ebo = (el_Obj_EBO *)object; - attrib = &ebo->attribute; - break; - - case ELM_OBJECT_TYPE_EVO: - evo = (el_Obj_EVO *)object; - attrib = &evo->attribute; - break; - - case ELM_OBJECT_TYPE_EGO: - group = (el_Obj_Group *)object; - evo = _get_evo(group, elm_tls->gContext.vector_id); - if (evo != NULL) { - attrib = &evo->attribute; - } - else { - return FALSE; - } - break; - default: - DEBUG_ASSERT(0, "Bad object type"); - return FALSE; - break; - } - - attrib->blend = blend; - - return TRUE; -} - -static BOOL _set_color(ElmVecObj evo, uint32_t color) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return FALSE; - - el_Obj_EVO *object = (el_Obj_EVO *)get_object(evo); - el_Obj_Group *group = NULL; - - if (object == NULL) { - DEBUG_ASSERT(0, "Bad object handle"); - return FALSE; - } - - switch (object->object.type) { - case ELM_OBJECT_TYPE_EVO: - break; - - case ELM_OBJECT_TYPE_EGO: - group = (el_Obj_Group *)object; - object = _get_evo(group, elm_tls->gContext.vector_id); - if (object == NULL) { - return FALSE; - } - break; - case ELM_OBJECT_TYPE_EBO: - default: - DEBUG_ASSERT(0, "Bad object type"); - return FALSE; - break; - } - - object->attribute.paint.color = color; - - return TRUE; -} - -static BOOL _set_pattern(ElmVecObj evo, ElmBitmapObj pattern) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return FALSE; - - el_Obj_EVO *object = (el_Obj_EVO *)get_object(evo); - el_Obj_EBO *ebo_obj = (el_Obj_EBO *) get_object(pattern); - el_Obj_Group *group = NULL; - - if ((object == NULL) || - (ebo_obj == NULL)){ - DEBUG_ASSERT(0, "Bad object handle"); - return FALSE; - } - - switch (object->object.type) { - case ELM_OBJECT_TYPE_EVO: - break; - - case ELM_OBJECT_TYPE_EGO: - group = (el_Obj_Group *)object; - object = _get_evo(group, elm_tls->gContext.vector_id); - if (object == NULL) { - return FALSE; - } - break; - - default: - break; - } - - object->attribute.paint.pattern.pattern = ebo_obj; - ref_object((el_Object *)ebo_obj); - - return TRUE; -} - -static BOOL _set_pattern_mode(ElmVecObj evo, ELM_PATTERN_MODE mode, uint32_t color) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return FALSE; - - el_Obj_EVO *object = (el_Obj_EVO *)get_object(evo); - el_Obj_Group *group = NULL; - - if (object == NULL){ - DEBUG_ASSERT(0, "Bad object handle"); - return FALSE; - } - - switch (object->object.type) { - case ELM_OBJECT_TYPE_EVO: - break; - - case ELM_OBJECT_TYPE_EGO: - group = (el_Obj_Group *)object; - object = _get_evo(group, elm_tls->gContext.vector_id); - if (object == NULL) { - return FALSE; - } - break; - - default: - break; - } - - object->attribute.paint.pattern.mode = mode; - object->attribute.paint.pattern.color = color; - - return TRUE; -} - -static BOOL _set_paintType(ElmVecObj evo, ELM_PAINT_TYPE type) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return FALSE; - - el_Obj_EVO *object = (el_Obj_EVO *)get_object(evo); - el_Obj_Group *group = NULL; - - if (object == NULL) { - DEBUG_ASSERT(0, "Bad object handle"); - return FALSE; - } - switch (object->object.type) { - case ELM_OBJECT_TYPE_EVO: - break; - - case ELM_OBJECT_TYPE_EGO: - group = (el_Obj_Group *)object; - object = _get_evo(group, elm_tls->gContext.vector_id); - if (object == NULL) { - return FALSE; - } - break; - - default: - break; - } - - object->attribute.paint.type = type; - - return TRUE; -} - -static BOOL _rotate(ElmHandle obj, float angle) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return FALSE; - - el_Object *object = get_object(obj); - el_Obj_EBO *ebo = NULL; - el_Obj_EVO *evo = NULL; - el_Obj_Group *ego = NULL; - el_Transform *transform = NULL; - - switch (object->type) { - case ELM_OBJECT_TYPE_EBO: - ebo = (el_Obj_EBO *)object; - transform = &ebo->attribute.transform; - break; - - case ELM_OBJECT_TYPE_EGO: - ego = (el_Obj_Group *)object; - if (elm_tls->gContext.vector_id < 0) { - transform = &ego->transform; - } - else { - evo = _get_evo(ego, elm_tls->gContext.vector_id); - if (evo != NULL) { - transform = &evo->attribute.transform; - } - else { - return FALSE; - } - } - break; - - case ELM_OBJECT_TYPE_EVO: - evo = (el_Obj_EVO *)object; - transform = &evo->attribute.transform; - break; - - default: - DEBUG_ASSERT(0, "Bad object type"); - break; - } - - // Update the transformation params. - transform->rotate += angle; - - // Upate the matrix. - vg_lite_rotate(angle, &transform->matrix); - - // Clean dirty. - transform->dirty = FALSE; - - return TRUE; -} -static BOOL _translate(ElmHandle obj, float x, float y) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return FALSE; - - el_Object *object = get_object(obj); - el_Obj_EBO *ebo = NULL; - el_Obj_EVO *evo = NULL; - el_Obj_Group *ego = NULL; - el_Transform *transform = NULL; - - switch (object->type) { - case ELM_OBJECT_TYPE_EBO: - ebo = (el_Obj_EBO *)object; - transform = &ebo->attribute.transform; - break; - - case ELM_OBJECT_TYPE_EGO: - ego = (el_Obj_Group *)object; - if (elm_tls->gContext.vector_id < 0) { - transform = &ego->transform; - } - else { - evo = _get_evo(ego, elm_tls->gContext.vector_id); - if (evo != NULL) { - transform = &evo->attribute.transform; - } - else { - return FALSE; - } - } - break; - - case ELM_OBJECT_TYPE_EVO: - evo = (el_Obj_EVO *)object; - transform = &evo->attribute.transform; - break; - - default: - DEBUG_ASSERT(0, "Bad object type"); - break; - } - - // Update the transformation params. - transform->translate[0] += x; - transform->translate[1] += y; - - // Update the matrix. - vg_lite_translate(x, y, &transform->matrix); - - // Clean dirty. - transform->dirty = FALSE; - - return TRUE; -} - -static BOOL _verify_header(ELM_OBJECT_TYPE *type, uint32_t *version, void *data) -{ - uint32_t *p32_data = (uint32_t *)data; - - if (type != NULL) { - *type = (ELM_OBJECT_TYPE)(*(p32_data + 1)); - } - - if (version != NULL) { - *version = *p32_data; - - if (*version <= ELM_VERSION) { - return TRUE; /* Verified OK, compatible. */ - } - else { - return FALSE; /* Verified Failed, API version is lower. */ - } - } - - return TRUE; -} - -/* - Load the specified object from the data. - */ -static ElmHandle _create_object_from_data(ELM_OBJECT_TYPE type, void *data, int size) -{ - ELM_OBJECT_TYPE real_type; - uint32_t p_data = (uint32_t)data; - uint32_t version; - - if(p_data % BASE_ADDRESS_ALIGNMENT != 0) { - DEBUG_ASSERT(0, "Error: data address don't align with 32 bytes!"); - return ELM_NULL_HANDLE; - } - - if (FALSE == _verify_header(&real_type, &version, data)) { - DEBUG_ASSERT(0, "Error: Incompatible file."); - return ELM_NULL_HANDLE; - } - - if (real_type != type) { - DEBUG_ASSERT(0, "Warning: Specified type mismatched.\n"); - } - - /* Jump over the version field to get to the start of the first ELM object */ - data = (void *)((unsigned)data + sizeof(uint32_t)); - - switch (real_type) { - case ELM_OBJECT_TYPE_EVO: - return _load_evo(data, size, NULL); - break; - - case ELM_OBJECT_TYPE_EGO: - return _load_ego(data, size); - - case ELM_OBJECT_TYPE_EBO: - return _load_ebo(data, size, version); -#if (VG_RENDER_TEXT==1) - case ELM_OBJECT_TYPE_FONT: - return _load_font(data, size); - - case ELM_OBJECT_TYPE_TEXT: - return _load_text(data, size, NULL); -#endif - default: - DEBUG_ASSERT(0, "Bad object type"); - break; - } - - return ELM_NULL_HANDLE; -} - -static el_Transform *_get_paint_transform(ElmHandle handle) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return FALSE; - - el_Transform *transform = NULL; - el_Obj_Group *group = NULL; - el_Obj_EVO *evo = NULL; - - evo = (el_Obj_EVO *)get_object(handle); - - if (evo == NULL) { - DEBUG_ASSERT(0, "Bad object handle.\n"); - return NULL; - } - - /* Find the corresponding evo object. */ - switch (evo->object.type) { - case ELM_OBJECT_TYPE_EVO: - break; - - case ELM_OBJECT_TYPE_EGO: - group = (el_Obj_Group *)evo; - evo = _get_evo(group, elm_tls->gContext.vector_id); - if (evo == NULL) { - return NULL; - } - break; - - case ELM_OBJECT_TYPE_EBO: - default: - DEBUG_ASSERT(0, "Incorrect object tyoe.\n"); - return NULL; - break; - } - - /* Get the correct transformation based on the paint type. */ - if (evo->attribute.paint.type == ELM_PAINT_PATTERN) { - transform = &((el_Obj_EBO*)evo->attribute.paint.pattern.pattern)->attribute.transform; - } - else if (evo->attribute.paint.type == ELM_PAINT_GRADIENT) { - transform = &evo->attribute.paint.grad->data.transform; - } - - return transform; -} - -/*********************** ELM API *********************/ -#if !RTOS -/*! - @abstract Create an elementary object from an existing binary file. - - @discussion - This function creates an elementary object from the file whose file name is specified by param name. - Caller must match type with the binary file, otherwise create mail fail by returning ELM_NULL_HANDLE. - - @param type - Specify what type of object to be created. - - @param name - The name of the binary resource file. - - @return ElmHandle - An object handle depending on the corresponding type. If type mismatches, it - returns ELM_NULL_HANDLE. - */ -ElmHandle ElmCreateObjectFromFile(ELM_OBJECT_TYPE type, const char *name) -{ -#if RTOS || BAREMETAL - return ELM_NULL_HANDLE; -#else - void *data = NULL; - long size = 0; - FILE *fp = fopen(name, "rb"); - ElmHandle handle = ELM_NULL_HANDLE; - - if (fp != NULL) { - fseek(fp, 0, SEEK_END); - size = ftell(fp); - - data = elm_alloc(1, size); - if (data != NULL) { - fseek(fp, 0, SEEK_SET); - fread(data, size, 1, fp); - - handle = _create_object_from_data(type, data, size); - } - else { - printf("open %s failed!\n", name); - } - elm_free(data); - fclose(fp); - } - - return handle; -#endif -} -#else -ElmHandle ElmCreateObjectFromFile(ELM_OBJECT_TYPE type, const char *name) -{ - return ELM_NULL_HANDLE; -} -#endif /*!ENABLE_ELM_CRATE_OBJECT_FROM_FILE*/ -/*! - @abstract Create an elementary object from build-in data within the appplication. - - @discussion - This function creates an elementar object from local data pointer, which is specially useful for environment without filesystem support. - - @param type - Specify what type of object to be created. - - @param data - The pointer to the binary data which has exactly same layout as external resource file. - - @return ElmHandle - An object handle depending on the corresponding type. If type mismatches with the binary data, it - returns ELM_NULL_HANDLE. - */ -ElmHandle ElmCreateObjectFromData(ELM_OBJECT_TYPE type, void *data, int size) -{ - return _create_object_from_data(type, data, size); -} - -/*! - @abstract Destroy an ELM object. - - @discussion - This function is to release all internal resource inside Elementary libary belonging to this object. - Applicatoin need make sure the object is not being used by elmentary library any more when calling this function. - If an EBO is being destroyed and it's attached to one EVO, it need to guarantee that EVO is not being used by elementary library too. - - @param object - The object handle - - @return - If destroying is completed successfully. - */ -BOOL ElmDestroyObject(ElmHandle object) -{ - int result = destroy_object(object); - return (result >= 0); -} - -/*! - @abstract Rotate a graphics object with centain degree - - @discussion - This function sets an evo/ebo/ego object rotated with specified angle. Without reset, these setting will be - accumulated. - - @param obj - The graphics object will be rotated. - - @param angle - A radian value to be applied on the evo object. - - @return bool - Rotate is set successfully. - */ -BOOL ElmRotate(ElmHandle obj, float angle) -{ - return _rotate(obj, angle); -} - -/*! - @abstract Transfer an graphics object at different directions. - - @discussion - This function put an evo/ebo/ego object away at different directions. Without reset, the setting will be - accumulated. - - @param obj - The graphics object will be transfered. - - @param x - The units in pixel of X direction. - - @param y - The units in pixel of Y direction. - - @return bool - Transfer is set successfully. - */ -BOOL ElmTransfer(ElmHandle obj, int x, int y) -{ - return _translate(obj, x, y); -} - -/*! - @abstract Scale an graphics object at different directions. - - @discussion - This function scale up or down an evo/ego/ebo object at different directions. Without reset, the setting will - be accumateled. - - @param obj - The graphics object which is targeted to manipulate. - - @param x - The scale ratio in X direction. - - @param y - The scale ratio in Y direction. - - @return bool - Scale is set succefully. - */ -BOOL ElmScale(ElmHandle obj, float x, float y) -{ - return _scale(obj, x, y); -} - -/*! - @abstract Reset the attribute of a graphics object for specified property bit. - - @discussion - This funcion resets specified property for an elementary object. It can be applied all types of objects. - But some properties are only valid for centain types of objects. If the function is called to reset an invalid - property for this type of object, it will be siliently ignored. - After reset, the specifed property of an evo/ebo/ego object is set to the initial state. The initial states are decided - by the binary resource file. The resource creator should set right value for all properties if they want to directly render - the object without any adjustment in application. There is one issue, at present, application has no way to query current value - of each property, is it required? - - @param obj - The graphics object which is targeted to manipulate. - - @param mask - Specify which property or properties need to reset to initial value. - - @return bool - Reset is done successfully. If some mask is not valid for this type of object, it would return false. - */ -BOOL ElmReset(ElmHandle obj, ELM_EVO_PROP_BIT mask) -{ - return _reset_attrib(obj, mask); -} - -/*! - @abstract Set the rendering quality of an graphics object. - - @discussion - This function sets the rendering quality of an evo/ebo object. Avaliable quality setting contains: - ELM_EVO_QUALITY_LOW, ELM_EVO_QUALITY_MED, ELM_EVO_QUALITY_HI. This function is only applied to an evo or an ebo. - Group object can't be set quality. It always use the setting from its binary. - - @param obj - The elementary object. - - @param quality - The quality enum. - - @return bool - The operation for this object is sucessful, for group object and invalid enum, would return false. - */ -BOOL ElmSetQuality(ElmHandle obj, ELM_QUALITY quality) -{ - return _set_quality(obj, quality); -} - -/*! - @abstract Set the fill rule of an evo object. - - @discussion - This function sets the fill rule of an elementary object. Avaliable quality setting contains: - ELM_EVO_EO, ELM_EVO_NZ. It only applies to evo object. - - @param evo - The evo object. - - @param fill - The fill rule enum. - - @return bool - The operation for this evo is sucessful. For non-evo object an ENUM is not a valid enum, would return false. - */ -BOOL ElmSetFill(ElmVecObj evo, ELM_EVO_FILL fill) -{ - return _set_fill(evo, fill); -} - -/*! - @abstract Set the blending mode of an evo/ebo object. - - @discussion - This function sets the blending mode of an evo/ebo object. It's not applied to group object. - - @param obj - The graphics object. - - @param blend - The blending mode enum. - - @return bool - The operation for this evo/ebo is sucessful. If object is a group object or blend mode is not a legal one, it would return false. - */ -BOOL ElmSetBlend(ElmHandle obj, ELM_BLEND blend) -{ - return _set_blend(obj, blend); -} - -/*! - @abstract Set the solid fill color of an evo object. - - @discussion - This function sets the solid fill color of an evo object. - - @param evo - The evo object. - - @param color - The uint32 color value in rgba order. - - @return bool - The operation for this evo is sucessful. If the object is not a evo object, it would return false. - */ -BOOL ElmSetColor(ElmVecObj evo, uint32_t color) -{ - return _set_color(evo, color); -} - -/*! - @abstract Set the image paint fill of an evo. - - @discussion - This function sets the image pattern for filling an evo. The image pattern - is a loaded ebo. The ebo's transformation is applied when drawing the evo. - - @param evo - The evo object. - - @param pattern - The image pattern to be set for the evo. - - @return bool - The operation is successful or not. - */ -BOOL ElmSetPattern(ElmVecObj evo, ElmBitmapObj pattern) -{ - return _set_pattern(evo, pattern); -} - -/*! - @abstract Set the image paint fill of an evo. - - @discussion - This function sets the image pattern for filling an evo. The image pattern - is a loaded ebo. The ebo's transformation is applied when drawing the evo. - - @param evo - The evo object. - - @param pattern - The image pattern to be set for the evo. - - @return bool - The operation is successful or not. - */ -BOOL ElmSetPatternMode(ElmVecObj evo, ELM_PATTERN_MODE mode, uint32_t color) -{ - return _set_pattern_mode(evo, mode, color); -} - -/*! - @abstract Set the paint type of an evo. - - @discussion - This function selects the paint type for evo to use. An evo may have 3 types - of paint: COLOR, PATTERN, and LINEAR GRADIENT. The Linear graident is always - a built-in resource, which can not be altered. If a binary resource doesn't - have built-in gradient paint resource, it can't be selected as the paint source. - Solid color is also a built-in attribute, but it can be changed by ElmSetColor(). - Paint with a pattern always need an external ebo object, which is impossible - to be embedded in resource file,i.e. ebo object. Before select paint type to - be PATTERN, ElmSetPattern() must be called to attach an EBO to an EVO. - - @param evo - The evo object. - - @param type - The paint type to be set for the evo. - - @return bool - The operation is successful or not. - If the corresponding type is not avaiable for the evo, it returns false and - type paint type falls back to COLOR. - */ -BOOL ElmSetPaintType(ElmVecObj evo, ELM_PAINT_TYPE type) -{ - return _set_paintType(evo, type); -} - -/*! - @abstract Get the solid fill color of an evo object. - - @discussion - This function Get the solid fill color of an evo object. - - @param evo - The evo object. - - @return uint32_t - The uint32 color value in rgba order. - */ -BOOL ElmGetColor(ElmGroupObj handle,uint32_t *color) -{ - elm_tls_t* elm_tls; - el_Obj_EVO *evo; - - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return FALSE; - - el_Obj_Group *ego = (el_Obj_Group*) get_object(handle); - evo = _get_evo(ego, elm_tls->gContext.vector_id); - *color = evo->attribute.paint.color; - - return TRUE; -} - -/*! - @abstract Query the vectory path count of an EGO object. If the given object - is an evo/ebo, the count is 0. - */ -uint32_t ElmGetVectorCount(ElmHandle handle) -{ - el_Obj_Group *ego = (el_Obj_Group*) get_object(handle); - if (ego->object.type != ELM_OBJECT_TYPE_EGO) { - return 0; - } - else { - return ego->group.count; - } -} - -/*! - @abstract Query the type of an object (by handle). - */ -ELM_OBJECT_TYPE ElmGetObjectType(ElmHandle handle) -{ - el_Object *object = get_object(handle); - return object->type; -} - -/*! - @abstract Set the current vectory object index to operate on. - */ -BOOL ElmSetCurrentVector(int32_t id) -{ - elm_tls_t* elm_tls; - elm_tls = (elm_tls_t *) elm_os_get_tls(); - if (elm_tls == NULL) - return FALSE; - - elm_tls->gContext.vector_id = id; - - return TRUE; -} - -BOOL ElmScalePaint(ElmHandle handle, float sx, float sy) -{ - el_Transform *transform = NULL; - - transform = _get_paint_transform(handle); - - if (transform != NULL) { - vg_lite_scale(sx, sy, &transform->matrix); - transform->dirty = FALSE; - return TRUE; - } - else { - return FALSE; - } -} -BOOL ElmRotatePaint(ElmHandle handle, float degrees) -{ - el_Transform *transform = NULL; - - transform = _get_paint_transform(handle); - - if (transform != NULL) { - vg_lite_rotate(degrees, &transform->matrix); - transform->dirty = FALSE; - return TRUE; - } - else { - return FALSE; - } -} - -BOOL ElmTranslatePaint(ElmHandle handle, float tx, float ty) -{ - el_Transform *transform = NULL; - - transform = _get_paint_transform(handle); - - if (transform != NULL) { - vg_lite_translate(tx, ty, &transform->matrix); - transform->dirty = FALSE; - return TRUE; - } - else { - return FALSE; - } -} +/**************************************************************************** +* +* Copyright 2012 - 2021 Vivante Corporation, Santa Clara, California. +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +#include "elm_precom.h" +#include "elm_os.h" +#include "vg_lite_text.h" +#include "vft_debug.h" +#include "elm_headers.h" + +#if (VG_RENDER_TEXT==1) +#include "elm_text.h" +#endif /* VG_RENDER_TEXT */ + +#if RTOS +#define BASE_ADDRESS_ALIGNMENT 32 +#else +#define BASE_ADDRESS_ALIGNMENT 4 +# endif +/* #define ENABLE_ELM_CRATE_OBJECT_FROM_FILE */ + +/* + * ANSI APIs are missing so application can use ElmCreateObjectFromData + * This simplifies things since file can be from FATFS, NOR Flash buffer etc. + */ + +#if (RTOS && DDRLESS) || BAREMETAL +/* Find some free objects, return the first index, + * and mark the bits as 1 (allocated). + * Params: + * free_map: the map bits of the objects where 0 is free and 1 is allocated; + * count : the element count of free_map[]; + * obj_count:how many objects to allocate from the pool. + * + * Return: + * The free index of the object in the pool. + * */ +int get_free_objects(int32_t free_map[], int count, int obj_count) +{ + int i, j; + int result = -1; + int counter = 0; + int bit_count = 0; + int32_t bits; + + /* Find a free bit. */ + for (i = 0; i < count; i++) { + bits = free_map[i]; + + for (j = 0; j < 32; j++) { + //Increase the bit counter. + bit_count++; + + if ((bits & 0x80000000) == 0) { + //Free bit is found. then count available free bits. + counter++; + } + else { + //Free bit is not found, reset the counter. + counter = 0; + } + + //Check to see whether enough bits are found. + if (counter >= obj_count) { + result = bit_count - counter; + + //Get out of the two loops. + i = count; + break; + } + + //Shift to next bit. + bits <<= 1; + } + } + + /* Mark the bits as allocated if OK. */ + if (result > -1) { + int bits_set = 1; + int bit_offset = result % 32; + bit_count = result / 32; + + while (obj_count > 0) { + bits_set = ~(0xffffffff << (32 - bit_offset)); + if (obj_count <= 32 - bit_offset) { + //Done. + bits_set = bits_set & (0xffffffff << (32 - bit_offset - obj_count)); + free_map[bit_count] |= bits_set; + break; + } + free_map[bit_count] |= bits_set; + + //Go to next map element. + obj_count -= (32 - bit_offset); + bit_count++; + bit_offset = 0; + } + } + + return result; +} + +/* When an object is "freed", mark the corresponding bits to 0. */ +void mark_free_object(int32_t free_map[], int object) +{ + int index, offset; + + index = object / 32; + offset = object % 32; + + free_map[index] &= ~(1 << (31 - offset)); +} + +/* Check whether an object (with given index) allocated or not. */ +int object_exists(int32_t free_map[], int index) +{ + int32_t bits; + int offset = index % 32; + index /= 32; + + bits = ~(1 << (31 - offset)); + + if (free_map[index] & bits) { + return 1; + } + else { + return 0; + } +} + +/* Allocate an EVO object from pool. */ +static el_Obj_EVO * alloc_evo(int count) +{ + elm_tls_t* elm_tls; + int index; + el_Obj_EVO *object = NULL; + + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return NULL; + + index = get_free_objects(elm_tls->gContext.objmap_evo, COUNT_OF(elm_tls->gContext.objmap_evo), count); + + if (index > -1) { + object = &elm_tls->gContext.objpool_evo[index]; + elm_tls->gContext.objcounter_evo += count; + for (; count > 0; count--) { + object[count - 1].object.index = index + count - 1; + } + } + + return object; +} + +/* Allocate an EBO object from pool. */ +static el_Obj_EBO * alloc_ebo() +{ + elm_tls_t* elm_tls; + int index; + el_Obj_EBO *object = NULL; + + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return NULL; + + index = get_free_objects(elm_tls->gContext.objmap_ebo, COUNT_OF(elm_tls->gContext.objmap_ebo), 1); + + if (index > -1) { + object = &elm_tls->gContext.objpool_ebo[index]; + object->object.index = index; + elm_tls->gContext.objcounter_ebo++; + } + + return object; +} + +/* Allocate an EGO object from pool. */ +static el_Obj_Group * alloc_ego() +{ + elm_tls_t* elm_tls; + int index; + el_Obj_Group *object = NULL; + + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return NULL; + + index = get_free_objects(elm_tls->gContext.objmap_group, COUNT_OF(elm_tls->gContext.objmap_group), 1); + + if (index > -1) { + object = &elm_tls->gContext.objpool_group[index]; + object->object.index = index; + elm_tls->gContext.objcounter_group++; + } + + return object; +} + +/* Mark an EGO object as free: insert it into the free list. */ +static void free_ego(el_Obj_Group *object) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return NULL; + + mark_free_object(elm_tls->gContext.objmap_group, elm_tls->object->object.index); + elm_tls->gContext.objcounter_group--; +} + +/* Allocate a grad object from pool. */ +static el_Obj_Grad * alloc_grad() +{ + elm_tls_t* elm_tls; + int index; + el_Obj_Grad *object = NULL; + + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return NULL; + + index = get_free_objects(elm_tls->gContext.objmap_grad, COUNT_OF(elm_tls->gContext.objmap_grad), 1); + + if (index > -1) { + object = &elm_tls->gContext.objpool_grad[index]; + object->object.index = index; + elm_tls->gContext.objcounter_grad++; + } + + return object; +} + +#endif +/* Internal Implementations *******************************/ +int deref_object(el_Object *object) +{ + object->reference--; + return object->reference; +} + +int ref_object(el_Object *object) +{ + object->reference++; + return object->reference; +} + +int add_object(el_Object *object) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return 0; +#if (RTOS && DDRLESS) || BAREMETAL + /* Assign handle. */ + object->handle = elm_tls->gContext.currentHandle++; + return 1; +#else + int result = 1; + el_ObjList *list = NULL; + + /* Assign handle. */ + object->handle = elm_tls->gContext.currentHandle++; + + /* Get the list slot. */ + list = OBJECT_SLOT(object->handle); + if (list == NULL) { + list = (el_ObjList *) elm_alloc(1, sizeof(el_ObjList)); + if ( list == NULL ) { + return 0; /* Memory allocation failed */ + } +#ifdef ENABLE_STRICT_DEBUG_MEMSET + memset(list, 0, sizeof(el_ObjList)); +#endif + + OBJECT_SLOT(object->handle) = list; + + list->object = object; + list->next = NULL; + + return 1; + } + + /* Insert the object. */ + while (list->next != NULL) { + list = list->next; + } + list->next = (el_ObjList *) elm_alloc(1, sizeof(el_ObjList)); + if ( list->next == NULL ) { + return 0; /* Memory allocation failed */ + } +#ifdef ENABLE_STRICT_DEBUG_MEMSET + memset(list->next, 0, sizeof(el_ObjList)); +#endif + list = list->next; + list->object = object; + list->next = NULL; + + return result; +#endif +} + +int remove_object(el_Object *object) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return 0; + + int result = 0; +#if (!(RTOS && DDRLESS)) && (!BAREMETAL) + el_ObjList *list = NULL, *node = NULL; + + // Get the list slot. + list = OBJECT_SLOT(object->handle); + + // Invalid. + if (list == NULL) + return 0; + + // Find the object. + if (list->object == object) { + OBJECT_SLOT(object->handle) = list->next; + elm_free(list); + return 1; + } + + while (list->next != NULL) { + if (list->next->object == object) { + node = list->next; + list->next = list->next->next; + elm_free(node); + return 1; + } + list = list->next; + } +#endif + + return result; +} + +el_Object *get_object(ElmHandle handle) +{ + elm_tls_t* elm_tls; + el_Object *object = NULL; + + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return NULL; + +#if (RTOS && DDRLESS) || BAREMETAL + int i; + for (i = 0; i < OBJCOUNT_EVO; i++) { + if (object_exists(elm_tls->gContext.objmap_evo, i)) { + if (elm_tls->gContext.objpool_evo[i].object.handle == handle) { + object = (el_Object *)&elm_tls->gContext.objpool_evo[i]; + return object; + } + } + } + for (i = 0; i < OBJCOUNT_EBO; i++) { + if (object_exists(elm_tls->gContext.objmap_ebo, i)) { + if (elm_tls->gContext.objpool_ebo[i].object.handle == handle) { + object = (el_Object *)&elm_tls->gContext.objpool_ebo[i]; + return object; + } + } + } + for (i = 0; i < OBJCOUNT_GRAD; i++) { + if (object_exists(elm_tls->gContext.objmap_grad, i)) { + if (elm_tls->gContext.objpool_grad[i].object.handle == handle) { + object = (el_Object *)&elm_tls->gContext.objpool_grad[i]; + return object; + } + } + } + for (i = 0; i < OBJCOUNT_GROUP; i++) { + if (object_exists(elm_tls->gContext.objmap_group, i)) { + if (elm_tls->gContext.objpool_group[i].object.handle == handle) { + object = (el_Object *)&elm_tls->gContext.objpool_group[i]; + return object; + } + } + } +#else + el_ObjList *list = NULL; + + // Get the slot. + list = OBJECT_SLOT(handle); + + // Find the object. + while (list != NULL) { + if ((list->object != NULL) && + (list->object->handle == handle)) { + object = list->object; + return object; + } + list = list->next; + } +#endif + + DEBUG_ASSERT(0, "Unknown object"); + return NULL; +} + +#if (RTOS && DDRLESS) || BAREMETAL +static void free_grad(el_Obj_Grad *object) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls != NULL) { + mark_free_object(elm_tls->gContext.objmap_grad, object->object.index); + elm_tls->gContext.objcounter_grad--; + } +} +#endif + +/* Destroy an evo object data. */ +int destroy_evo(el_Obj_EVO *evo) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return 0; + +#if (RTOS && DDRLESS) || BAREMETAL + mark_free_object(elm_tls->gContext.objmap_evo, evo->object.index); + elm_tls->gContext.objcounter_evo--; + free_grad(evo->defaultAttrib.paint.grad); +#else + + if ( evo->defaultAttrib.paint.type == ELM_PAINT_TEXT ) { +#if (VG_RENDER_TEXT==1) + _unload_text(evo); +#else + ; +#endif /* VG_RENDER_TEXT */ + } else { + /* TODO: EVO destroy not done yet. */ + if (evo->defaultAttrib.paint.grad != NULL) { + vg_lite_clear_grad(&evo->defaultAttrib.paint.grad->data.grad); + elm_free(evo->defaultAttrib.paint.grad); + evo->defaultAttrib.paint.grad = NULL; + } + + if (evo->data.path.path != NULL) { + vg_lite_clear_path(&evo->data.path); + elm_free(evo->data.path.path); + evo->data.path.path = NULL; + } + } + + remove_object(&evo->object); +#endif + +#if (VG_RENDER_TEXT==1) + destroy_font_data(); +#endif /* VG_RENDER_TEXT */ + return 1; +} + +/* Destroy an ego object data. */ +int destroy_ego(el_Obj_Group *ego) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if(elm_tls == NULL) + return 0; + +#if (RTOS && DDRLESS) || BAREMETAL + mark_free_object(elm_tls->gContext.objmap_group, ego->object.index); + elm_tls->gContext.objcounter_group--; +#else + int i; + for (i = 0; i < ego->group.count; i++) + { + destroy_evo(&ego->group.objects[i]); + } + elm_free(ego->group.objects); + elm_free(ego); +#endif + +#if (VG_RENDER_TEXT==1) + destroy_font_data(); +#endif /* VG_RENDER_TEXT */ + return 1; +} + +/* Destroy an ebo object data. */ +int destroy_ebo(el_Obj_EBO *ebo) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if(elm_tls == NULL) + return 0; + +#if (RTOS && DDRLESS) || BAREMETAL + mark_free_object(elm_tls->gContext.objmap_ebo, ebo->object.index); + elm_tls->gContext.objcounter_ebo--; +#else + if ( ebo != NULL && ebo->data.buffer.handle != NULL) { + vg_lite_free(&ebo->data.buffer); + } + elm_free(ebo); +#endif + return 1; +} + +/* Destroy an object. + return: + -1: any error; + 0: destroyed when reference count is 0; + 1: decreased reference count but still > 0. + */ +int destroy_object(ElmHandle handle) +{ + el_Object *object = NULL; + int ref_count = 0; + + object = get_object(handle); + + // No such object. + if (object == NULL) { + DEBUG_ASSERT(0, "No such object"); + return -1; + } + + // Dereference object, and destroy if it's no more referred. + ref_count = deref_object(object); + if (ref_count == 0) { + remove_object(object); + + switch (object->type) { + case ELM_OBJECT_TYPE_EVO: + destroy_evo((el_Obj_EVO *)object); + elm_free(object); + break; + + case ELM_OBJECT_TYPE_EGO: + destroy_ego((el_Obj_Group *) object); + break; + + case ELM_OBJECT_TYPE_EBO: + destroy_ebo((el_Obj_EBO *) object); + break; + + default: + DEBUG_ASSERT(0, "Unknow object type"); + break; + } + } + + return 1; +} + +void _init_transform(el_Transform *transform) +{ + int i = 0; + transform->rotate = 0.0f; + for (i = 0;i < 2; i++) + { + transform->scale[i] = 1.0f; + transform->translate[i] = 0.0f; + } + vg_lite_identity(&transform->matrix); +} + +/* Static functions. *************************************************/ + +/* Get the specified vector object in a group. */ +static el_Obj_EVO* _get_evo(el_Obj_Group *group, int32_t id) +{ + if ((id >= group->group.count) || + (id < 0)){ + return (el_Obj_EVO*)NULL; + } + else { + return (el_Obj_EVO*)(group->group.objects + id); + } +} + +#if (VG_RENDER_TEXT==1) +static int _load_font(uint8_t *data, + unsigned size) +{ + ElmHandle ret = ELM_NULL_HANDLE; + el_Font_Header *font_header = (el_Font_Header *)data; + + + if (font_header->size_font_block != size) + return ret; + + return _load_font_data(data); +} + +static ElmHandle _load_text(uint8_t *data, + unsigned size, + el_Obj_EVO *evo) +{ + ElmHandle ret = ELM_NULL_HANDLE; + el_Text_Header *text_header = (el_Text_Header *)data; + + + if (text_header->size_text_block != size) + return ret; + + return _load_text_data(data, evo); +} +#endif /* VG_RENDER_TEXT */ + +#if (defined(__ICCARM__)) +/* + * Disable the unaligned structure attribute warning. Due to the packed data + * structures used to interpret ELM objects data the IAR compiler issues a + * number of warnings that certain attributes of the headers might be unaligned. + * This is not true, however, as all atributes are manually aligned to 4 bytes. + */ +#pragma diag_suppress = Pa039 +#endif + +static ElmHandle _load_evo(const uint8_t *data, unsigned size, el_Obj_EVO *evo) +{ + int i = 0; +#if (RTOS && DDRLESS) || BAREMETAL + uint32_t colors[VLC_MAX_GRAD]; + void *path_data; +#else + uint32_t *colors = NULL; + uint8_t *path_data = NULL; +#endif + el_Obj_EVO *local_evo = NULL; + el_EVO_Header *evo_header = (el_EVO_Header *) data; + + if (evo == NULL) { +#if (RTOS && DDRLESS) || BAREMETAL + local_evo = alloc_evo(1); +#else + local_evo = (el_Obj_EVO *)elm_alloc(1, sizeof(el_Obj_EVO)); +#endif + evo = local_evo; + } + JUMP_IF_NULL(evo, error_exit); + memset(evo, 0, sizeof(el_Obj_EVO)); + + /* + * Check if object size is valid. The size parameter + * needs to be a value greater or equal to the + * size of the current object to be loaded. + * This check needs to be done in order to ensure + * that the is_image field is correctly read and + * we do not read from invalid memory. + */ + JUMP_IF_LOWER(size, + MIN(sizeof(el_EVO_Polygon), sizeof(el_EVO_Image)), + error_exit); + + if(evo_header->polygon.paint_type.is_image) + { + /* + * Check if object size is valid + * (greater or equal to el_EVO_Image size). + */ + JUMP_IF_LOWER(size, + sizeof(el_EVO_Image), + error_exit); + memcpy(evo->eboname, + evo_header->image.eboname, + evo_header->image.namelength); + evo->is_image = evo_header->image.paint_type.is_image; + _init_transform(&evo->defaultAttrib.transform); + memcpy(&evo->defaultAttrib.transform.matrix, + &(evo_header->image.matrix), + sizeof(vg_lite_matrix_t)); + evo->img_width = evo_header->image.width; + evo->img_height = evo_header->image.height; + } + else + { + /* + * Check if object size is valid + * (greater or equal to el_EVO_Polygon size). + */ + JUMP_IF_LOWER(size, + sizeof(el_EVO_Polygon), + error_exit); + el_Transform *transform = NULL; + el_Transform *grad_transform = NULL; + el_EVO_Polygon *object_data = (el_EVO_Polygon *) &(evo_header->polygon); + el_EVO_GradData *grad_data = (el_EVO_GradData *) &(evo_header->polygon.grad); + + /* Get path data from the object. */ +#if (RTOS && DDRLESS) || BAREMETAL + path_data = (void *) (data + object_data->offset); +#else + path_data = (uint8_t *)elm_alloc(1, object_data->length); + JUMP_IF_NULL(path_data, error_exit); + +#ifdef ENABLE_STRICT_DEBUG_MEMSET + memset(path_data, 0, object_data->length); +#endif + JUMP_IF_LOWER(size, + object_data->offset + object_data->length, + error_exit); + /* Get path data. */ + memcpy(path_data, (void *)(data + object_data->offset), + object_data->length); +#endif + + if(object_data->paint_type.has_pattern) + evo->has_pattern = 1; + if(object_data->paint_type.is_pattern) + evo->is_pattern = 1; + + _init_transform(&evo->defaultAttrib.transform); + transform = &evo->defaultAttrib.transform; + + evo->object.type = ELM_OBJECT_TYPE_EVO; + evo->object.reference = 0; + + if ((object_data->paint_type.paint == ELM_PAINT_RADIAL_GRADIENT) || + (object_data->paint_type.paint == ELM_PAINT_GRADIENT)) { +#if (RTOS && DDRLESS) || BAREMETAL + evo->defaultAttrib.paint.grad = alloc_grad(); +#else + evo->defaultAttrib.paint.grad = (el_Obj_Grad*)elm_alloc(1, sizeof(el_Obj_Grad)); +#endif + JUMP_IF_NULL(evo->defaultAttrib.paint.grad, error_exit); +#ifdef ENABLE_STRICT_DEBUG_MEMSET + memset(evo->defaultAttrib.paint.grad, 0, sizeof(el_Obj_Grad)); +#endif + evo->defaultAttrib.paint.grad->data.grad.image.width = 0; + evo->defaultAttrib.paint.grad->data.grad.image.height = 0; + evo->defaultAttrib.paint.grad->data.grad.image.stride = 0; + evo->defaultAttrib.paint.grad->data.grad.image.tiled = VG_LITE_LINEAR; + + _init_transform(&evo->defaultAttrib.paint.grad->data.transform); + grad_transform = &evo->defaultAttrib.paint.grad->data.transform; + memcpy(&grad_transform->matrix, &(grad_data->matrix), + sizeof(vg_lite_matrix_t)); + colors = (uint32_t *)elm_alloc(grad_data->stop_count, sizeof(uint32_t)); + JUMP_IF_NULL(colors, error_exit); + memcpy(colors, + data + grad_data->color_offset, + grad_data->stop_count * sizeof(uint32_t)); + } + + if (object_data->arc_flag) + vg_lite_init_arc_path(&evo->data.path, + (vg_lite_format_t) object_data->format, + (vg_lite_quality_t) object_data->quality, + object_data->length, + path_data, + object_data->min_x, + object_data->min_y, + object_data->max_x, + object_data->max_y); + else + vg_lite_init_path(&evo->data.path, + (vg_lite_format_t) object_data->format, + (vg_lite_quality_t) object_data->quality, + object_data->length, + path_data, + object_data->min_x, + object_data->min_y, + object_data->max_x, + object_data->max_y); + + memcpy(&transform->matrix, &(object_data->matrix), sizeof(vg_lite_matrix_t)); + + evo->defaultAttrib.quality = ELM_QUALITY_LOW; + evo->defaultAttrib.fill_rule = (ELM_EVO_FILL) object_data->fill_rule; + evo->defaultAttrib.blend = (ELM_BLEND) object_data->blend; + evo->defaultAttrib.paint.type = (ELM_PAINT_TYPE) object_data->paint_type.paint; + + switch (object_data->paint_type.paint) { + case ELM_PAINT_GRADIENT: + { +#if (RTOS && DDRLESS) || BAREMETAL + uint32_t stops[VLC_MAX_GRAD]; +#else + uint32_t *stops = NULL; + + stops = (uint32_t *)elm_alloc(sizeof(uint32_t), grad_data->stop_count); + JUMP_IF_NULL(stops, error_exit); +#endif + for (i = 0 ;i < grad_data->stop_count; i++) + { + stops[i] = (uint32_t)((*(float *) (data + + grad_data->stop_offset + i * 4)) * 255); + } + + vg_lite_init_grad(&evo->defaultAttrib.paint.grad->data.grad); + vg_lite_set_grad(&evo->defaultAttrib.paint.grad->data.grad, + grad_data->stop_count, colors, stops); + if (grad_data->stop_count > 0) + { + vg_lite_update_grad(&evo->defaultAttrib.paint.grad->data.grad); + } +#if (RTOS && DDRLESS) || BAREMETAL +#else + elm_free(stops); +#endif + break; + } + case ELM_PAINT_RADIAL_GRADIENT: + { + float *stops; + vg_lite_color_ramp_t *vgColorRamp; + el_EVO_RadGradDataExt *rad_grad = (el_EVO_RadGradDataExt *) (data + sizeof(el_EVO_Header)); + + JUMP_IF_LOWER(size, + sizeof(el_EVO_Polygon) + sizeof(el_EVO_RadGradDataExt), + error_exit); + + stops = (float *)elm_alloc(grad_data->stop_count, sizeof(float)); + JUMP_IF_NULL(stops, error_exit); + memset(stops, 0, grad_data->stop_count * sizeof(float)); + vgColorRamp = (vg_lite_color_ramp_t *) elm_alloc(grad_data->stop_count, + sizeof(vg_lite_color_ramp_t)); + if (vgColorRamp == NULL) { + elm_free(stops); + goto error_exit; + } + memset(vgColorRamp, 0, + sizeof(vg_lite_color_ramp_t) * grad_data->stop_count); + for (i = 0; i < grad_data->stop_count; i++) + { + stops[i] = (*(float *) (data + grad_data->stop_offset + i * 4)); + vgColorRamp[i].alpha = (float)(colors[i] >> 24) / 255.0f; + vgColorRamp[i].red = (float)(colors[i] >> 16 & 0xFF) / 255.0f; + vgColorRamp[i].green = (float)(colors[i] >> 8 & 0xFF) / 255.0f; + vgColorRamp[i].blue = (float)(colors[i] & 0xFF) / 255.0f; + vgColorRamp[i].stop = stops[i]; + } + + memset(&evo->defaultAttrib.paint.radgrad->data.rad_grad, 0, sizeof(evo->defaultAttrib.paint.radgrad->data.rad_grad)); + vg_lite_set_rad_grad(&evo->defaultAttrib.paint.radgrad->data.rad_grad, + grad_data->stop_count, + vgColorRamp, + rad_grad->params, + rad_grad->spread_mode, + 0); + vg_lite_update_rad_grad(&evo->defaultAttrib.paint.radgrad->data.rad_grad); + + elm_free(stops); + elm_free(vgColorRamp); + break; + } + default: + /* Do nothing */ + break; + } + + evo->defaultAttrib.paint.color = object_data->color; + evo->attribute = evo->defaultAttrib; + ref_object(&evo->object); + JUMP_IF_NON_ZERO_VALUE(add_object(&evo->object), error_exit); + +#if (RTOS && DDRLESS) || BAREMETAL +#else + elm_free(colors); +#endif + } + + return evo->object.handle; + +error_exit: +#if (RTOS && DDRLESS) || BAREMETAL +#else + if ( colors != NULL ) + elm_free(colors); + if ( path_data != NULL) + elm_free(path_data); +#endif + + if ( (evo != NULL) && (evo->defaultAttrib.paint.grad != NULL) ) + elm_free(evo->defaultAttrib.paint.grad); + if ( (evo != NULL) && (evo->defaultAttrib.paint.radgrad != NULL) ) + elm_free(evo->defaultAttrib.paint.radgrad); + if ( local_evo != NULL ) + elm_free(local_evo); + + return ELM_NULL_HANDLE; +} + +static ElmHandle _load_ebo(const uint8_t *data, int size, uint32_t version) +{ + vg_lite_error_t error; + vg_lite_buffer_t *buffer; + uint32_t *colors, bytes = 0; + + el_EBO_Header *ebo_header = (el_EBO_Header *) data; + +#if (RTOS && DDRLESS) || BAREMETAL + el_Obj_EBO *ebo = alloc_ebo(); +#else + el_Obj_EBO *ebo = (el_Obj_EBO *)elm_alloc(1, (sizeof(el_Obj_EBO))); +#endif + JUMP_IF_NULL(ebo, error_exit); +#ifdef ENABLE_STRICT_DEBUG_MEMSET + memset(ebo, 0, sizeof(el_Obj_EBO)); +#endif + buffer = &ebo->data.buffer; + + /* + * Check if object size is valid. "size" needs to be a value greater than or + * equal to the size of the current object header. + */ + JUMP_IF_LOWER(size, sizeof(el_EBO_Header), error_exit); + bytes += sizeof(el_EBO_Header); + + if(version == 1) + { + el_EBO_Palette *clut_header = (el_EBO_Palette *) (data + sizeof(el_EBO_Header)); + + /* Make sure object size includes the CLUT header */ + bytes += sizeof(el_EBO_Palette); + JUMP_IF_LOWER(size, bytes, error_exit); + + ebo->object.type = (ELM_OBJECT_TYPE) ebo_header->type; + ebo->object.reference = 0; + + buffer->width = ebo_header->width; + buffer->height = ebo_header->height; + buffer->format = (vg_lite_buffer_format_t) ebo_header->format; + buffer->stride = 0; + + error = vg_lite_allocate(buffer); + if (error != VG_LITE_SUCCESS) + { + destroy_ebo(ebo); + return 0; + } + + buffer->stride = ebo_header->stride; + buffer->tiled = (vg_lite_buffer_layout_t) ebo_header->tiled; + colors = (uint32_t *)(data + clut_header->clut_data_offset); + + /* Make sure the object size includes image data */ + JUMP_IF_LOWER(size, + ebo_header->data_offset + + (buffer->stride * buffer->height), + error_exit); + + memcpy(buffer->memory, + data + ebo_header->data_offset, + buffer->stride * buffer->height); + + /* Save CLUT infomation. */ + ebo->clut_count = clut_header->clut_count; + + /* Make sure object size includes CLUT data */ + JUMP_IF_LOWER(size, + clut_header->clut_data_offset + + (sizeof(uint32_t) * clut_header->clut_count), + error_exit); + + memcpy(ebo->clut, colors, sizeof(uint32_t) * clut_header->clut_count); + } + else if(version == 2) + { + ebo->object.type = (ELM_OBJECT_TYPE) ebo_header->type; + ebo->object.reference = 0; + + buffer->width = ebo_header->width; + buffer->height = ebo_header->height; + buffer->format = (vg_lite_buffer_format_t) ebo_header->format; + buffer->stride = 0; + + error = vg_lite_allocate(buffer); + if (error != VG_LITE_SUCCESS) + { + destroy_ebo(ebo); + return 0; + } + + buffer->stride = ebo_header->stride; + buffer->tiled = (vg_lite_buffer_layout_t) ebo_header->tiled; + + /* Make sure the object size includes image data */ + JUMP_IF_LOWER(size, + ebo_header->data_offset + + (buffer->stride * buffer->height), + error_exit); + + memcpy(buffer->memory, + data + ebo_header->data_offset, + buffer->stride * buffer->height); + } + /* Set transformation to identity. */ + ebo->defaultAttrib.transform.dirty = 1; + ebo->defaultAttrib.transform.identity = 1; + + _init_transform(&ebo->defaultAttrib.transform); + ebo->attribute = ebo->defaultAttrib; + + ref_object(&ebo->object); + JUMP_IF_NON_ZERO_VALUE(add_object(&ebo->object), error_exit); + + return ebo->object.handle; + +error_exit: + if (ebo != NULL ) { + elm_free(ebo); + } + + return ELM_NULL_HANDLE; +} + +static ElmHandle _load_ego(const uint8_t *data, int size) +{ + int i; + unsigned int invalid_count = 0; + uint32_t *obj_size, *obj_offset, *obj_type; + void *obj_data; + el_EGO_Header *ego_header = (el_EGO_Header *) data; + +#if (RTOS && DDRLESS) || BAREMETAL + el_Obj_Group *ego = alloc_ego(); +#else + el_Obj_Group *ego = (el_Obj_Group *)elm_alloc(1, sizeof(el_Obj_Group)); +#endif + JUMP_IF_NULL(ego, error_exit); +#ifdef ENABLE_STRICT_DEBUG_MEMSET + memset(ego, 0, sizeof(el_Obj_Group)); +#endif + + ego->object.type = (ELM_OBJECT_TYPE) ego_header->type; + ego->object.reference = 0; + + _init_transform(&ego->defaultTrans); + memcpy(&(ego->defaultTrans.matrix.m), + &(ego_header->matrix), + sizeof(vg_lite_matrix_t)); + ego->group.count = ego_header->count; +#if (RTOS && DDRLESS) || BAREMETAL + ego->group.objects = alloc_evo(ego->group.count); +#else + ego->group.objects = (el_Obj_EVO *)elm_alloc(1, ego->group.count * sizeof(el_Obj_EVO)); +#endif + JUMP_IF_NULL(ego->group.objects, error_exit); +#ifdef ENABLE_STRICT_DEBUG_MEMSET + memset(ego->group.objects, 0, ego->group.count * sizeof(el_Obj_EVO)); +#endif + + obj_size = (uint32_t *)((unsigned)data + sizeof(el_EGO_Header)); + obj_offset = (uint32_t *)((unsigned)obj_size + \ + (ego_header->count * sizeof(uint32_t))); + + for (i = 0; i < ego->group.count && obj_offset[i] < size; i++) + { + if (obj_size[i] == 0) { + invalid_count++; + continue; + } + + /* Check whether EVO object is truncated */ + JUMP_IF_GREATER(obj_offset[i] + obj_size[i], size, error_exit); + + /* Call appropriate object loader according to object type */ + obj_data = (void*)((unsigned)data + obj_offset[i]); + obj_type = obj_data; + switch (*obj_type) { + case ELM_OBJECT_TYPE_EVO: + ego->group.objects[i].object.handle = _load_evo(obj_data, + obj_size[i], + &ego->group.objects[i]); + break; +#if (VG_RENDER_TEXT==1) + case ELM_OBJECT_TYPE_FONT: + _load_font(obj_data, obj_size[i]); + break; + case ELM_OBJECT_TYPE_TEXT: + ego->group.objects[i].object.handle = _load_text(obj_data, + obj_size[i], + &ego->group.objects[i]); + break; +#endif /* VG_RENDER_TEXT */ + default: + break; + } + } + + ego->group.count -= invalid_count; + ego->transform = ego->defaultTrans; + + ref_object(&ego->object); + JUMP_IF_NON_ZERO_VALUE(add_object(&ego->object), error_exit); + + return ego->object.handle; + +error_exit: + if (ego != NULL ) { + if ( ego->group.objects != NULL ) { + elm_free(ego->group.objects); + } + elm_free(ego); + } + + return ELM_NULL_HANDLE; +} + +#if (defined(__ICCARM__)) +/* Restore the unaligned data structure attribute warning */ +#pragma diag_default = Pa039 +#endif + +static BOOL _scale(ElmHandle obj, float x, float y) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return FALSE; + + el_Object *object = get_object(obj); + el_Obj_EBO *ebo = NULL; + el_Obj_EVO *evo = NULL; + el_Obj_Group *ego = NULL; + el_Transform *transform = NULL; + + switch (object->type) { + case ELM_OBJECT_TYPE_EBO: + ebo = (el_Obj_EBO *)object; + transform = &ebo->attribute.transform; + break; + + case ELM_OBJECT_TYPE_EGO: + ego = (el_Obj_Group *)object; + if (elm_tls->gContext.vector_id < 0) { + transform = &ego->transform; + } + else { + evo = _get_evo(ego, elm_tls->gContext.vector_id); + if (evo != NULL) { + transform = &evo->attribute.transform; + } + else { /* No such vector object to set. */ + return FALSE; + } + } + break; + + case ELM_OBJECT_TYPE_EVO: + evo = (el_Obj_EVO *)object; + transform = &evo->attribute.transform; + break; + + default: + DEBUG_ASSERT(0, "Bad object type"); + break; + } + + // Update the transformation params. + transform->scale[0] *= x; + transform->scale[1] *= y; + + vg_lite_scale(x, y, &transform->matrix); + + // Clean dirty. + transform->dirty = FALSE; + + return TRUE; +} + +static BOOL _reset_attrib(ElmHandle obj, ELM_EVO_PROP_BIT mask) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return FALSE; + + el_Object *object = get_object(obj); + el_Obj_EBO *ebo = NULL; + el_Obj_EVO *evo = NULL; + el_Obj_Group *ego = NULL; + el_Attribute *attrib = NULL; + el_Attribute *defaultAttr = NULL; + el_Transform *transform = NULL; + el_Transform *defaultTrans = NULL; + + switch (object->type) { + case ELM_OBJECT_TYPE_EBO: + ebo = (el_Obj_EBO *)object; + attrib = &ebo->attribute; + defaultAttr = &ebo->defaultAttrib; + transform = &attrib->transform; + defaultTrans = &defaultAttr->transform; + break; + + case ELM_OBJECT_TYPE_EGO: + ego = (el_Obj_Group *)object; + if (elm_tls->gContext.vector_id < 0) { + transform = &ego->transform; + defaultTrans = &ego->defaultTrans; + } + else { + evo = _get_evo((el_Obj_Group*)obj, elm_tls->gContext.vector_id); + if (evo != NULL) { + attrib = &evo->attribute; + defaultAttr = &evo->defaultAttrib; + transform = &attrib->transform; + defaultTrans = &defaultAttr->transform; + } + else { + return FALSE; + } + } + break; + + case ELM_OBJECT_TYPE_EVO: + evo = (el_Obj_EVO *)object; + attrib = &evo->attribute; + defaultAttr = &evo->defaultAttrib; + transform = &attrib->transform; + defaultTrans = &defaultAttr->transform; + break; + + default: + DEBUG_ASSERT(0, "Bad object type"); + return FALSE; + break; + } + + // Update the attribute value. When transform is modified, update the matrix. + if (mask & ELM_PROP_ROTATE_BIT) { + transform->rotate = defaultTrans->rotate; + } + + if (mask & ELM_PROP_TRANSFER_BIT) { + transform->translate[0] = defaultTrans->translate[0]; + transform->translate[1] = defaultTrans->translate[1]; + } + + if (mask & ELM_PROP_SCALE_BIT) { + transform->scale[0] = defaultTrans->scale[0]; + transform->scale[1] = defaultTrans->scale[1]; + } + + /* On any bit reset, reset the whole matrix to the default one. */ + if (mask & (ELM_PROP_ROTATE_BIT | ELM_PROP_TRANSFER_BIT | ELM_PROP_SCALE_BIT)) { + memcpy(&(transform->matrix), &(defaultTrans->matrix), sizeof(defaultTrans->matrix)); + transform->dirty = FALSE; + } + + /* Update other rendering attributes. */ + if (mask & ELM_PROP_BLEND_BIT) { + attrib->blend = defaultAttr->blend; + } + + if (mask & ELM_PROP_QUALITY_BIT) { + attrib->quality = defaultAttr->quality; + } + + if (mask & ELM_PROP_FILL_BIT) { + attrib->fill_rule = defaultAttr->fill_rule; + } + + if (mask & ELM_PROP_COLOR_BIT) { + attrib->paint.color = defaultAttr->paint.color; + } + + if (mask & ELM_PROP_PAINT_BIT) { + attrib->paint.type = defaultAttr->paint.type; + } + + return TRUE; +} + +static BOOL _set_quality(ElmHandle obj, ELM_QUALITY quality) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return FALSE; + + el_Object *object = get_object(obj); + el_Obj_EBO *ebo = NULL; + el_Obj_EVO *evo = NULL; + el_Obj_Group *group = NULL; + el_Attribute *attrib = NULL; + + switch (object->type) { + case ELM_OBJECT_TYPE_EBO: + ebo = (el_Obj_EBO *)object; + attrib = &ebo->attribute; + break; + + case ELM_OBJECT_TYPE_EVO: + evo = (el_Obj_EVO *)object; + attrib = &evo->attribute; + break; + + case ELM_OBJECT_TYPE_EGO: + group = (el_Obj_Group *)object; + evo = _get_evo(group, elm_tls->gContext.vector_id); + if (evo != NULL) { + attrib = &evo->attribute; + } + else { + return FALSE; + } + break; + default: + DEBUG_ASSERT(0, "Bad object type"); + return FALSE; + break; + } + + attrib->quality = quality; + + return TRUE; +} + +static BOOL _set_fill(ElmVecObj evo, ELM_EVO_FILL fill) +{ + el_Obj_EVO *object = (el_Obj_EVO *)get_object(evo); + + if (object == NULL) { + DEBUG_ASSERT(0, "Bad object handle"); + return FALSE; + } + + object->attribute.fill_rule = fill; + + return TRUE; +} + +static BOOL _set_blend(ElmHandle obj, ELM_BLEND blend) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return FALSE; + + el_Object *object = get_object(obj); + el_Obj_EBO *ebo = NULL; + el_Obj_EVO *evo = NULL; + el_Obj_Group *group = NULL; + el_Attribute *attrib = NULL; + + switch (object->type) { + case ELM_OBJECT_TYPE_EBO: + ebo = (el_Obj_EBO *)object; + attrib = &ebo->attribute; + break; + + case ELM_OBJECT_TYPE_EVO: + evo = (el_Obj_EVO *)object; + attrib = &evo->attribute; + break; + + case ELM_OBJECT_TYPE_EGO: + group = (el_Obj_Group *)object; + evo = _get_evo(group, elm_tls->gContext.vector_id); + if (evo != NULL) { + attrib = &evo->attribute; + } + else { + return FALSE; + } + break; + default: + DEBUG_ASSERT(0, "Bad object type"); + return FALSE; + break; + } + + attrib->blend = blend; + + return TRUE; +} + +static BOOL _set_color(ElmVecObj evo, uint32_t color) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return FALSE; + + el_Obj_EVO *object = (el_Obj_EVO *)get_object(evo); + el_Obj_Group *group = NULL; + + if (object == NULL) { + DEBUG_ASSERT(0, "Bad object handle"); + return FALSE; + } + + switch (object->object.type) { + case ELM_OBJECT_TYPE_EVO: + break; + + case ELM_OBJECT_TYPE_EGO: + group = (el_Obj_Group *)object; + object = _get_evo(group, elm_tls->gContext.vector_id); + if (object == NULL) { + return FALSE; + } + break; + case ELM_OBJECT_TYPE_EBO: + default: + DEBUG_ASSERT(0, "Bad object type"); + return FALSE; + break; + } + + object->attribute.paint.color = color; + + return TRUE; +} + +static BOOL _set_pattern(ElmVecObj evo, ElmBitmapObj pattern) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return FALSE; + + el_Obj_EVO *object = (el_Obj_EVO *)get_object(evo); + el_Obj_EBO *ebo_obj = (el_Obj_EBO *) get_object(pattern); + el_Obj_Group *group = NULL; + + if ((object == NULL) || + (ebo_obj == NULL)){ + DEBUG_ASSERT(0, "Bad object handle"); + return FALSE; + } + + switch (object->object.type) { + case ELM_OBJECT_TYPE_EVO: + break; + + case ELM_OBJECT_TYPE_EGO: + group = (el_Obj_Group *)object; + object = _get_evo(group, elm_tls->gContext.vector_id); + if (object == NULL) { + return FALSE; + } + break; + + default: + break; + } + + object->attribute.paint.pattern.pattern = ebo_obj; + ref_object((el_Object *)ebo_obj); + + return TRUE; +} + +static BOOL _set_pattern_mode(ElmVecObj evo, ELM_PATTERN_MODE mode, uint32_t color) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return FALSE; + + el_Obj_EVO *object = (el_Obj_EVO *)get_object(evo); + el_Obj_Group *group = NULL; + + if (object == NULL){ + DEBUG_ASSERT(0, "Bad object handle"); + return FALSE; + } + + switch (object->object.type) { + case ELM_OBJECT_TYPE_EVO: + break; + + case ELM_OBJECT_TYPE_EGO: + group = (el_Obj_Group *)object; + object = _get_evo(group, elm_tls->gContext.vector_id); + if (object == NULL) { + return FALSE; + } + break; + + default: + break; + } + + object->attribute.paint.pattern.mode = mode; + object->attribute.paint.pattern.color = color; + + return TRUE; +} + +static BOOL _set_paintType(ElmVecObj evo, ELM_PAINT_TYPE type) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return FALSE; + + el_Obj_EVO *object = (el_Obj_EVO *)get_object(evo); + el_Obj_Group *group = NULL; + + if (object == NULL) { + DEBUG_ASSERT(0, "Bad object handle"); + return FALSE; + } + switch (object->object.type) { + case ELM_OBJECT_TYPE_EVO: + break; + + case ELM_OBJECT_TYPE_EGO: + group = (el_Obj_Group *)object; + object = _get_evo(group, elm_tls->gContext.vector_id); + if (object == NULL) { + return FALSE; + } + break; + + default: + break; + } + + object->attribute.paint.type = type; + + return TRUE; +} + +static BOOL _rotate(ElmHandle obj, float angle) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return FALSE; + + el_Object *object = get_object(obj); + el_Obj_EBO *ebo = NULL; + el_Obj_EVO *evo = NULL; + el_Obj_Group *ego = NULL; + el_Transform *transform = NULL; + + switch (object->type) { + case ELM_OBJECT_TYPE_EBO: + ebo = (el_Obj_EBO *)object; + transform = &ebo->attribute.transform; + break; + + case ELM_OBJECT_TYPE_EGO: + ego = (el_Obj_Group *)object; + if (elm_tls->gContext.vector_id < 0) { + transform = &ego->transform; + } + else { + evo = _get_evo(ego, elm_tls->gContext.vector_id); + if (evo != NULL) { + transform = &evo->attribute.transform; + } + else { + return FALSE; + } + } + break; + + case ELM_OBJECT_TYPE_EVO: + evo = (el_Obj_EVO *)object; + transform = &evo->attribute.transform; + break; + + default: + DEBUG_ASSERT(0, "Bad object type"); + break; + } + + // Update the transformation params. + transform->rotate += angle; + + // Upate the matrix. + vg_lite_rotate(angle, &transform->matrix); + + // Clean dirty. + transform->dirty = FALSE; + + return TRUE; +} +static BOOL _translate(ElmHandle obj, float x, float y) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return FALSE; + + el_Object *object = get_object(obj); + el_Obj_EBO *ebo = NULL; + el_Obj_EVO *evo = NULL; + el_Obj_Group *ego = NULL; + el_Transform *transform = NULL; + + switch (object->type) { + case ELM_OBJECT_TYPE_EBO: + ebo = (el_Obj_EBO *)object; + transform = &ebo->attribute.transform; + break; + + case ELM_OBJECT_TYPE_EGO: + ego = (el_Obj_Group *)object; + if (elm_tls->gContext.vector_id < 0) { + transform = &ego->transform; + } + else { + evo = _get_evo(ego, elm_tls->gContext.vector_id); + if (evo != NULL) { + transform = &evo->attribute.transform; + } + else { + return FALSE; + } + } + break; + + case ELM_OBJECT_TYPE_EVO: + evo = (el_Obj_EVO *)object; + transform = &evo->attribute.transform; + break; + + default: + DEBUG_ASSERT(0, "Bad object type"); + break; + } + + // Update the transformation params. + transform->translate[0] += x; + transform->translate[1] += y; + + // Update the matrix. + vg_lite_translate(x, y, &transform->matrix); + + // Clean dirty. + transform->dirty = FALSE; + + return TRUE; +} + +static BOOL _verify_header(ELM_OBJECT_TYPE *type, uint32_t *version, void *data) +{ + uint32_t *p32_data = (uint32_t *)data; + + if (type != NULL) { + *type = (ELM_OBJECT_TYPE)(*(p32_data + 1)); + } + + if (version != NULL) { + *version = *p32_data; + + if (*version <= ELM_VERSION) { + return TRUE; /* Verified OK, compatible. */ + } + else { + return FALSE; /* Verified Failed, API version is lower. */ + } + } + + return TRUE; +} + +/* + Load the specified object from the data. + */ +static ElmHandle _create_object_from_data(ELM_OBJECT_TYPE type, void *data, int size) +{ + ELM_OBJECT_TYPE real_type; + uint32_t p_data = (uint32_t)data; + uint32_t version; + + if(p_data % BASE_ADDRESS_ALIGNMENT != 0) { + DEBUG_ASSERT(0, "Error: data address don't align with 32 bytes!"); + return ELM_NULL_HANDLE; + } + + if (FALSE == _verify_header(&real_type, &version, data)) { + DEBUG_ASSERT(0, "Error: Incompatible file."); + return ELM_NULL_HANDLE; + } + + if (real_type != type) { + DEBUG_ASSERT(0, "Warning: Specified type mismatched.\n"); + } + + /* Jump over the version field to get to the start of the first ELM object */ + data = (void *)((unsigned)data + sizeof(uint32_t)); + + switch (real_type) { + case ELM_OBJECT_TYPE_EVO: + return _load_evo(data, size, NULL); + break; + + case ELM_OBJECT_TYPE_EGO: + return _load_ego(data, size); + + case ELM_OBJECT_TYPE_EBO: + return _load_ebo(data, size, version); +#if (VG_RENDER_TEXT==1) + case ELM_OBJECT_TYPE_FONT: + return _load_font(data, size); + + case ELM_OBJECT_TYPE_TEXT: + return _load_text(data, size, NULL); +#endif + default: + DEBUG_ASSERT(0, "Bad object type"); + break; + } + + return ELM_NULL_HANDLE; +} + +static el_Transform *_get_paint_transform(ElmHandle handle) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return FALSE; + + el_Transform *transform = NULL; + el_Obj_Group *group = NULL; + el_Obj_EVO *evo = NULL; + + evo = (el_Obj_EVO *)get_object(handle); + + if (evo == NULL) { + DEBUG_ASSERT(0, "Bad object handle.\n"); + return NULL; + } + + /* Find the corresponding evo object. */ + switch (evo->object.type) { + case ELM_OBJECT_TYPE_EVO: + break; + + case ELM_OBJECT_TYPE_EGO: + group = (el_Obj_Group *)evo; + evo = _get_evo(group, elm_tls->gContext.vector_id); + if (evo == NULL) { + return NULL; + } + break; + + case ELM_OBJECT_TYPE_EBO: + default: + DEBUG_ASSERT(0, "Incorrect object tyoe.\n"); + return NULL; + break; + } + + /* Get the correct transformation based on the paint type. */ + if (evo->attribute.paint.type == ELM_PAINT_PATTERN) { + transform = &((el_Obj_EBO*)evo->attribute.paint.pattern.pattern)->attribute.transform; + } + else if (evo->attribute.paint.type == ELM_PAINT_GRADIENT) { + transform = &evo->attribute.paint.grad->data.transform; + } + + return transform; +} + +/*********************** ELM API *********************/ +#if !RTOS +/*! + @abstract Create an elementary object from an existing binary file. + + @discussion + This function creates an elementary object from the file whose file name is specified by param name. + Caller must match type with the binary file, otherwise create mail fail by returning ELM_NULL_HANDLE. + + @param type + Specify what type of object to be created. + + @param name + The name of the binary resource file. + + @return ElmHandle + An object handle depending on the corresponding type. If type mismatches, it + returns ELM_NULL_HANDLE. + */ +ElmHandle ElmCreateObjectFromFile(ELM_OBJECT_TYPE type, const char *name) +{ +#if RTOS || BAREMETAL + return ELM_NULL_HANDLE; +#else + void *data = NULL; + long size = 0; + FILE *fp = fopen(name, "rb"); + ElmHandle handle = ELM_NULL_HANDLE; + + if (fp != NULL) { + fseek(fp, 0, SEEK_END); + size = ftell(fp); + + data = elm_alloc(1, size); + if (data != NULL) { + fseek(fp, 0, SEEK_SET); + fread(data, size, 1, fp); + + handle = _create_object_from_data(type, data, size); + } + else { + printf("open %s failed!\n", name); + } + elm_free(data); + fclose(fp); + } + + return handle; +#endif +} +#else +ElmHandle ElmCreateObjectFromFile(ELM_OBJECT_TYPE type, const char *name) +{ + return ELM_NULL_HANDLE; +} +#endif /*!ENABLE_ELM_CRATE_OBJECT_FROM_FILE*/ +/*! + @abstract Create an elementary object from build-in data within the appplication. + + @discussion + This function creates an elementar object from local data pointer, which is specially useful for environment without filesystem support. + + @param type + Specify what type of object to be created. + + @param data + The pointer to the binary data which has exactly same layout as external resource file. + + @return ElmHandle + An object handle depending on the corresponding type. If type mismatches with the binary data, it + returns ELM_NULL_HANDLE. + */ +ElmHandle ElmCreateObjectFromData(ELM_OBJECT_TYPE type, void *data, int size) +{ + return _create_object_from_data(type, data, size); +} + +/*! + @abstract Destroy an ELM object. + + @discussion + This function is to release all internal resource inside Elementary libary belonging to this object. + Applicatoin need make sure the object is not being used by elmentary library any more when calling this function. + If an EBO is being destroyed and it's attached to one EVO, it need to guarantee that EVO is not being used by elementary library too. + + @param object + The object handle + + @return + If destroying is completed successfully. + */ +BOOL ElmDestroyObject(ElmHandle object) +{ + int result = destroy_object(object); + return (result >= 0); +} + +/*! + @abstract Rotate a graphics object with centain degree + + @discussion + This function sets an evo/ebo/ego object rotated with specified angle. Without reset, these setting will be + accumulated. + + @param obj + The graphics object will be rotated. + + @param angle + A radian value to be applied on the evo object. + + @return bool + Rotate is set successfully. + */ +BOOL ElmRotate(ElmHandle obj, float angle) +{ + return _rotate(obj, angle); +} + +/*! + @abstract Transfer an graphics object at different directions. + + @discussion + This function put an evo/ebo/ego object away at different directions. Without reset, the setting will be + accumulated. + + @param obj + The graphics object will be transfered. + + @param x + The units in pixel of X direction. + + @param y + The units in pixel of Y direction. + + @return bool + Transfer is set successfully. + */ +BOOL ElmTransfer(ElmHandle obj, int x, int y) +{ + return _translate(obj, x, y); +} + +/*! + @abstract Scale an graphics object at different directions. + + @discussion + This function scale up or down an evo/ego/ebo object at different directions. Without reset, the setting will + be accumateled. + + @param obj + The graphics object which is targeted to manipulate. + + @param x + The scale ratio in X direction. + + @param y + The scale ratio in Y direction. + + @return bool + Scale is set succefully. + */ +BOOL ElmScale(ElmHandle obj, float x, float y) +{ + return _scale(obj, x, y); +} + +/*! + @abstract Reset the attribute of a graphics object for specified property bit. + + @discussion + This funcion resets specified property for an elementary object. It can be applied all types of objects. + But some properties are only valid for centain types of objects. If the function is called to reset an invalid + property for this type of object, it will be siliently ignored. + After reset, the specifed property of an evo/ebo/ego object is set to the initial state. The initial states are decided + by the binary resource file. The resource creator should set right value for all properties if they want to directly render + the object without any adjustment in application. There is one issue, at present, application has no way to query current value + of each property, is it required? + + @param obj + The graphics object which is targeted to manipulate. + + @param mask + Specify which property or properties need to reset to initial value. + + @return bool + Reset is done successfully. If some mask is not valid for this type of object, it would return false. + */ +BOOL ElmReset(ElmHandle obj, ELM_EVO_PROP_BIT mask) +{ + return _reset_attrib(obj, mask); +} + +/*! + @abstract Set the rendering quality of an graphics object. + + @discussion + This function sets the rendering quality of an evo/ebo object. Avaliable quality setting contains: + ELM_EVO_QUALITY_LOW, ELM_EVO_QUALITY_MED, ELM_EVO_QUALITY_HI. This function is only applied to an evo or an ebo. + Group object can't be set quality. It always use the setting from its binary. + + @param obj + The elementary object. + + @param quality + The quality enum. + + @return bool + The operation for this object is sucessful, for group object and invalid enum, would return false. + */ +BOOL ElmSetQuality(ElmHandle obj, ELM_QUALITY quality) +{ + return _set_quality(obj, quality); +} + +/*! + @abstract Set the fill rule of an evo object. + + @discussion + This function sets the fill rule of an elementary object. Avaliable quality setting contains: + ELM_EVO_EO, ELM_EVO_NZ. It only applies to evo object. + + @param evo + The evo object. + + @param fill + The fill rule enum. + + @return bool + The operation for this evo is sucessful. For non-evo object an ENUM is not a valid enum, would return false. + */ +BOOL ElmSetFill(ElmVecObj evo, ELM_EVO_FILL fill) +{ + return _set_fill(evo, fill); +} + +/*! + @abstract Set the blending mode of an evo/ebo object. + + @discussion + This function sets the blending mode of an evo/ebo object. It's not applied to group object. + + @param obj + The graphics object. + + @param blend + The blending mode enum. + + @return bool + The operation for this evo/ebo is sucessful. If object is a group object or blend mode is not a legal one, it would return false. + */ +BOOL ElmSetBlend(ElmHandle obj, ELM_BLEND blend) +{ + return _set_blend(obj, blend); +} + +/*! + @abstract Set the solid fill color of an evo object. + + @discussion + This function sets the solid fill color of an evo object. + + @param evo + The evo object. + + @param color + The uint32 color value in rgba order. + + @return bool + The operation for this evo is sucessful. If the object is not a evo object, it would return false. + */ +BOOL ElmSetColor(ElmVecObj evo, uint32_t color) +{ + return _set_color(evo, color); +} + +/*! + @abstract Set the image paint fill of an evo. + + @discussion + This function sets the image pattern for filling an evo. The image pattern + is a loaded ebo. The ebo's transformation is applied when drawing the evo. + + @param evo + The evo object. + + @param pattern + The image pattern to be set for the evo. + + @return bool + The operation is successful or not. + */ +BOOL ElmSetPattern(ElmVecObj evo, ElmBitmapObj pattern) +{ + return _set_pattern(evo, pattern); +} + +/*! + @abstract Set the image paint fill of an evo. + + @discussion + This function sets the image pattern for filling an evo. The image pattern + is a loaded ebo. The ebo's transformation is applied when drawing the evo. + + @param evo + The evo object. + + @param pattern + The image pattern to be set for the evo. + + @return bool + The operation is successful or not. + */ +BOOL ElmSetPatternMode(ElmVecObj evo, ELM_PATTERN_MODE mode, uint32_t color) +{ + return _set_pattern_mode(evo, mode, color); +} + +/*! + @abstract Set the paint type of an evo. + + @discussion + This function selects the paint type for evo to use. An evo may have 3 types + of paint: COLOR, PATTERN, and LINEAR GRADIENT. The Linear graident is always + a built-in resource, which can not be altered. If a binary resource doesn't + have built-in gradient paint resource, it can't be selected as the paint source. + Solid color is also a built-in attribute, but it can be changed by ElmSetColor(). + Paint with a pattern always need an external ebo object, which is impossible + to be embedded in resource file,i.e. ebo object. Before select paint type to + be PATTERN, ElmSetPattern() must be called to attach an EBO to an EVO. + + @param evo + The evo object. + + @param type + The paint type to be set for the evo. + + @return bool + The operation is successful or not. + If the corresponding type is not avaiable for the evo, it returns false and + type paint type falls back to COLOR. + */ +BOOL ElmSetPaintType(ElmVecObj evo, ELM_PAINT_TYPE type) +{ + return _set_paintType(evo, type); +} + +/*! + @abstract Get the solid fill color of an evo object. + + @discussion + This function Get the solid fill color of an evo object. + + @param evo + The evo object. + + @return uint32_t + The uint32 color value in rgba order. + */ +BOOL ElmGetColor(ElmGroupObj handle,uint32_t *color) +{ + elm_tls_t* elm_tls; + el_Obj_EVO *evo; + + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return FALSE; + + el_Obj_Group *ego = (el_Obj_Group*) get_object(handle); + evo = _get_evo(ego, elm_tls->gContext.vector_id); + *color = evo->attribute.paint.color; + + return TRUE; +} + +/*! + @abstract Query the vectory path count of an EGO object. If the given object + is an evo/ebo, the count is 0. + */ +uint32_t ElmGetVectorCount(ElmHandle handle) +{ + el_Obj_Group *ego = (el_Obj_Group*) get_object(handle); + if (ego->object.type != ELM_OBJECT_TYPE_EGO) { + return 0; + } + else { + return ego->group.count; + } +} + +/*! + @abstract Query the type of an object (by handle). + */ +ELM_OBJECT_TYPE ElmGetObjectType(ElmHandle handle) +{ + el_Object *object = get_object(handle); + return object->type; +} + +/*! + @abstract Set the current vectory object index to operate on. + */ +BOOL ElmSetCurrentVector(int32_t id) +{ + elm_tls_t* elm_tls; + elm_tls = (elm_tls_t *) elm_os_get_tls(); + if (elm_tls == NULL) + return FALSE; + + elm_tls->gContext.vector_id = id; + + return TRUE; +} + +BOOL ElmScalePaint(ElmHandle handle, float sx, float sy) +{ + el_Transform *transform = NULL; + + transform = _get_paint_transform(handle); + + if (transform != NULL) { + vg_lite_scale(sx, sy, &transform->matrix); + transform->dirty = FALSE; + return TRUE; + } + else { + return FALSE; + } +} +BOOL ElmRotatePaint(ElmHandle handle, float degrees) +{ + el_Transform *transform = NULL; + + transform = _get_paint_transform(handle); + + if (transform != NULL) { + vg_lite_rotate(degrees, &transform->matrix); + transform->dirty = FALSE; + return TRUE; + } + else { + return FALSE; + } +} + +BOOL ElmTranslatePaint(ElmHandle handle, float tx, float ty) +{ + el_Transform *transform = NULL; + + transform = _get_paint_transform(handle); + + if (transform != NULL) { + vg_lite_translate(tx, ty, &transform->matrix); + transform->dirty = FALSE; + return TRUE; + } + else { + return FALSE; + } +} diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_os.c b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_os.c similarity index 95% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_os.c rename to bsp/sdk_overlay/middleware/vglite/elementary/src/elm_os.c index 7a883cf..4baa5b8 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_os.c +++ b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_os.c @@ -1,21 +1,21 @@ -#include "elm_os.h" -#include "FreeRTOS.h" -#include "task.h" - -vg_lite_error_t elm_os_set_tls(void* tls) -{ - if(tls == NULL) - return VG_LITE_INVALID_ARGUMENT; - vTaskSetThreadLocalStoragePointer(NULL, 1, tls); - return VG_LITE_SUCCESS; -} - -void * elm_os_get_tls(void) -{ - return pvTaskGetThreadLocalStoragePointer(NULL, 1); -} - -void elm_os_reset_tls(void) -{ - vTaskSetThreadLocalStoragePointer(NULL, 1, NULL); +#include "elm_os.h" +#include "FreeRTOS.h" +#include "task.h" + +vg_lite_error_t elm_os_set_tls(void* tls) +{ + if(tls == NULL) + return VG_LITE_INVALID_ARGUMENT; + vTaskSetThreadLocalStoragePointer(NULL, 1, tls); + return VG_LITE_SUCCESS; +} + +void * elm_os_get_tls(void) +{ + return pvTaskGetThreadLocalStoragePointer(NULL, 1); +} + +void elm_os_reset_tls(void) +{ + vTaskSetThreadLocalStoragePointer(NULL, 1, NULL); } \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_os.h b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_os.h similarity index 93% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_os.h rename to bsp/sdk_overlay/middleware/vglite/elementary/src/elm_os.h index e5a0736..e91ed3c 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_os.h +++ b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_os.h @@ -1,13 +1,13 @@ -#ifndef ELM_OS_H_ -#define ELM_OS_H_ - -#include -#include"vg_lite.h" - -vg_lite_error_t elm_os_set_tls(void* tls); - -void * elm_os_get_tls(void); - -void elm_os_reset_tls(void); - +#ifndef ELM_OS_H_ +#define ELM_OS_H_ + +#include +#include"vg_lite.h" + +vg_lite_error_t elm_os_set_tls(void* tls); + +void * elm_os_get_tls(void); + +void elm_os_reset_tls(void); + #endif \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_precom.h b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_precom.h similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_precom.h rename to bsp/sdk_overlay/middleware/vglite/elementary/src/elm_precom.h index 0ef71a3..fecd979 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_precom.h +++ b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_precom.h @@ -1,55 +1,55 @@ -/**************************************************************************** -* -* Copyright 2012 - 2021 Vivante Corporation, Santa Clara, California. -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -#ifndef elm_precom_h -#define elm_precom_h - -/* System headers. */ -#include -#include -#include - -/* VGLite hdaders. */ -#include "vg_lite.h" - -/* Project headers. */ -#include "Elm.h" -#include "velm.h" -#include "elm_os.h" - -#define JUMP_IF_NON_ZERO_VALUE(x, label) { int ret = x; if ( (ret) != 1 ) { goto label; } } -#define JUMP_IF_NULL(x, label) { if (x == NULL) { goto label;} } -#define JUMP_IF_LOWER(x, y, label) {if (x < y) {goto label;} } -#define JUMP_IF_GREATER(x, y, label) {if (x > y) {goto label;} } -#define JUMP_IF_EQUAL(x, y, label) {if (x == y) {goto label;} } -#define JUMP_IF_LOWER_OR_EQUAL(x, y, label) {if (x <= y) {goto label;} } -#define JUMP_IF_GREATER_OR_EQUAL(x, y, label) {if (x => y) {goto label;} } - -#define MIN(a, b) ((a) > (b) ? (b) : (a)) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) - -#endif /* elm_precom_h */ +/**************************************************************************** +* +* Copyright 2012 - 2021 Vivante Corporation, Santa Clara, California. +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +#ifndef elm_precom_h +#define elm_precom_h + +/* System headers. */ +#include +#include +#include + +/* VGLite hdaders. */ +#include "vg_lite.h" + +/* Project headers. */ +#include "Elm.h" +#include "velm.h" +#include "elm_os.h" + +#define JUMP_IF_NON_ZERO_VALUE(x, label) { int ret = x; if ( (ret) != 1 ) { goto label; } } +#define JUMP_IF_NULL(x, label) { if (x == NULL) { goto label;} } +#define JUMP_IF_LOWER(x, y, label) {if (x < y) {goto label;} } +#define JUMP_IF_GREATER(x, y, label) {if (x > y) {goto label;} } +#define JUMP_IF_EQUAL(x, y, label) {if (x == y) {goto label;} } +#define JUMP_IF_LOWER_OR_EQUAL(x, y, label) {if (x <= y) {goto label;} } +#define JUMP_IF_GREATER_OR_EQUAL(x, y, label) {if (x => y) {goto label;} } + +#define MIN(a, b) ((a) > (b) ? (b) : (a)) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) + +#endif /* elm_precom_h */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_text.c b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_text.c similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_text.c rename to bsp/sdk_overlay/middleware/vglite/elementary/src/elm_text.c index 0feff8e..d5bb3e4 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/elementary/src/elm_text.c +++ b/bsp/sdk_overlay/middleware/vglite/elementary/src/elm_text.c @@ -1,734 +1,734 @@ -/**************************************************************************** -* -* Copyright 2020 NXP -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -/* - ElmDrawText API - */ -/** Include Files */ -#include // for snprintf -#include -#include - -#include "FreeRTOS.h" - -#include "vg_lite.h" -#include "Elm.h" -#include "velm.h" -#include "vg_lite_text.h" -#include "elm_headers.h" -#include "elm_text.h" -#include "elm_precom.h" -#include "vft_draw.h" - -/** Macros */ -#ifndef VECTOR_DEFAULT_FONT -#define VECTOR_DEFAULT_FONT 1 -#endif - -#if VECTOR_DEFAULT_FONT /* Use vector font as default font */ -#define DEFAULT_FONT_NAME "SVGFreeSansASCII" -#define DEFAULT_FONT_WEIGHT eFontWeightRegular -#define DEFAULT_FONT_STRETCH eFontStretchNormal -#define DEFAULT_FONT_STYLE eFontStyleNormal -#define DEFAULT_FONT_HEIGHT 35 -#define DEFAULT_TEXT_FG_COLOR 0xff000000 -#define DEFAULT_TEXT_ALIGN (eTextAlignLeft) - -#else /* Use raster font as default font */ -#define DEFAULT_FONT_NAME "DejaVuSans_Oblique" -#define DEFAULT_FONT_WEIGHT eFontWeightRegular -#define DEFAULT_FONT_STRETCH eFontStretchNormal -#define DEFAULT_FONT_STYLE eFontStyleItalic -#define DEFAULT_FONT_HEIGHT 35 -#define DEFAULT_TEXT_FG_COLOR 0xff000000 -#define DEFAULT_TEXT_ALIGN (eTextAlignLeft) - -#endif - -/* Maximum font properties from EVO file */ -#define MAX_FONT_ATTRIB_COMBINATIONS (32) - -#define TRANSPARENT_VGLITE_COLOUR(a, r, g, b) \ - ((uint32_t)(a) << 24) | ((uint32_t)(b) << 16) | ((uint32_t)(g) << 8) | \ - (uint32_t)r - -#define OPAQUE_VGLITE_COLOUR(r, g, b) TRANSPARENT_VGLITE_COLOUR(0xff, r, g, b) - -/** Data structures */ - -/** Internal or external API prototypes */ -int vg_lite_is_font_valid(vg_lite_font_t font); -char *vg_lite_get_font_name(vg_lite_font_t font); -vg_lite_error_t vg_lite_free_font_memory(vg_lite_font_t font); -int ref_object (el_Object *object); - -/** Globals */ -int g_total_system_font = 0; -static font_field_info_t g_default_font_properties[eMaxFontProperties]; -static font_field_info_t g_font_properties[MAX_FONT_ATTRIB_COMBINATIONS][eMaxFontProperties]; - -/** Externs if any */ -extern vg_lite_font_attributes_t g_font_attribs; -extern vg_lite_font_t g_last_font; -extern int g_last_font_attrib_idx; - -void initialize_elm_text(void) -{ - font_field_info_t *font_fields = NULL; - /* internal parameters of mcufont library */ - g_font_attribs.alignment = 0; - g_font_attribs.scale = 1; - g_font_attribs.width = 1200; /* Describes drawing area */ - g_font_attribs.margin = 5; /* Left margin in drawing area */ - g_font_attribs.bg_color = OPAQUE_VGLITE_COLOUR(0xff,0xff,0xff); // white - g_font_attribs.last_y = 0; - g_font_attribs.last_x =0; - g_font_attribs.last_dx = 0; - - /* Initialize default properties */ - font_fields = &g_default_font_properties[0]; - - char *font_name = (char *)elm_alloc(1, strlen(DEFAULT_FONT_NAME)+1); - strcpy(font_name, DEFAULT_FONT_NAME); - font_fields[eFontNameProperty].value.data = font_name; - font_fields[eFontWeightProperty].value.i_value = DEFAULT_FONT_WEIGHT; - font_fields[eFontStretchProperty].value.i_value = DEFAULT_FONT_STRETCH; - font_fields[eFontStyleProperty].value.i_value = DEFAULT_FONT_STYLE; - font_fields[eFontHeightProperty].value.i_value = DEFAULT_FONT_HEIGHT; - font_fields[eTextColorProperty].value.i_value = DEFAULT_TEXT_FG_COLOR; - font_fields[eTextAlignProperty].value.i_value = DEFAULT_TEXT_ALIGN; -} - -static int get_property(font_field_info_t *dst_font_fields, font_fields_t *src_font_fields, int num_fields) -{ - int i=0; - int len; - - /* Initialize default values */ - dst_font_fields[eFontWeightProperty].value.i_value = DEFAULT_FONT_WEIGHT; - dst_font_fields[eFontStretchProperty].value.i_value = DEFAULT_FONT_STRETCH; - dst_font_fields[eFontStyleProperty].value.i_value = eFontStyleNormal; - dst_font_fields[eTextAlignProperty].value.i_value = DEFAULT_TEXT_ALIGN; - - dst_font_fields[eFontNameProperty].value.data = NULL; - dst_font_fields[eFontHeightProperty].value.i_value = DEFAULT_FONT_HEIGHT; - dst_font_fields[eTextColorProperty].value.i_value = DEFAULT_TEXT_FG_COLOR; - - for(i=0; iattribute.blend; - vg_lite_font_t curr_font = VG_LITE_INVALID_FONT; - int curr_font_attrib_idx = INVALID_FONT_PROPERTY_IDX; - - vg_lite_font_attributes_t *font_attribs = &g_font_attribs; - font_field_info_t *font_fields = NULL; - - curr_font_attrib_idx = text->font_id; - - /* Single font caching can be done here (No caching for now) - Release last font object if it is different - */ - if ( vg_lite_is_font_valid(g_last_font) == 1 ) { - /* recycle font objects */ - vg_lite_free_font_memory(g_last_font); - g_last_font = VG_LITE_INVALID_FONT; - } - - if(curr_font_attrib_idx != INVALID_FONT_PROPERTY_IDX) - { - font_fields = &g_font_properties[curr_font_attrib_idx][0]; - font_fields[eFontHeightProperty].value.i_value = text->font_size; - - curr_font = vg_lite_find_font( - font_fields[eFontNameProperty].value.data, - (eFontWeight_t)font_fields[eFontWeightProperty].value.i_value, - (eFontStretch_t)font_fields[eFontStretchProperty].value.i_value, - (eFontStyle_t)font_fields[eFontStyleProperty].value.i_value, - font_fields[eFontHeightProperty].value.i_value - ); - } - - if (curr_font == VG_LITE_INVALID_FONT) { - //printf("ERROR: Font not found. Rendering with default configuration\n"); - font_fields = &g_default_font_properties[0]; - curr_font = vg_lite_find_font( - font_fields[eFontNameProperty].value.data, - (eFontWeight_t)font_fields[eFontWeightProperty].value.i_value, - (eFontStretch_t)font_fields[eFontStretchProperty].value.i_value, - (eFontStyle_t)font_fields[eFontStyleProperty].value.i_value, - font_fields[eFontHeightProperty].value.i_value); - } - if (curr_font == VG_LITE_INVALID_FONT) { - printf("Font[%s] not found\n", font_fields[eFontNameProperty].value.data); - return VG_LITE_INVALID_ARGUMENT; - } - font_attribs->is_vector_font = vg_lite_is_vector_font(curr_font); - /* Properties that changes over time */ - font_attribs->text_color = text->attribute.paint.color; - font_attribs->alignment = (eTextAlign_t)text->text_anchor; - font_attribs->font_height = font_fields[eFontHeightProperty].value.i_value; - font_attribs->tspan_has_dx_dy = text->tspan_has_dx_dy; - - error = vg_lite_draw_text(&buff->buffer, - (char *)text->msg, - curr_font, - text->x_pos, text->y_pos, - &text->attribute.transform.matrix, - blend, - font_attribs); - - g_last_font = curr_font; - g_last_font_attrib_idx = curr_font_attrib_idx; - return error; -} - -/* process font-field data */ -static int _process_font_field_data( uint8_t *data_start, uint8_t *data, int num_fields, font_fields_t* fields) -{ - eFontFields_t eName; - - if (g_total_system_font >= MAX_FONT_ATTRIB_COMBINATIONS) { - printf("WARNING: Font property buffer overflowing...\n" - "Increase MAX_FONT_ATTRIB_COMBINATIONS\n"); - return -1; - } - - for(int i=0; ittf_fonts[id].id = *(uint32_t *)(data); - fontblockobj->ttf_fonts[id].type = (eElemType_t)*(uint32_t *)(data + 1 * 4); - num_fields = *(uint32_t *)(data + 2 * 4); - fontblockobj->ttf_fonts[id].num_fields = num_fields; - fontblockobj->ttf_fonts[id].fields = (font_fields_t *)elm_alloc(1, num_fields * sizeof(font_fields_t)); - - _process_font_field_data(data_start, (uint8_t*)(data + 3 * 4), num_fields, fontblockobj->ttf_fonts[id].fields); - return 0; -} - -/* process vector-type font data */ -static int _process_vector_font_data(uint8_t *data_start, uint8_t *data, font_block_t *fontblockobj, int id) -{ - unsigned int num_fields = 0; - - fontblockobj->vector_fonts[id].id = *(uint32_t *)(data); - fontblockobj->vector_fonts[id].type = (eElemType_t)*(uint32_t *)(data + 1 * 4); - num_fields = *(uint32_t *)(data + 2 * 4); - fontblockobj->vector_fonts[id].num_fields = num_fields; - fontblockobj->vector_fonts[id].fields = (font_fields_t *)elm_alloc(1, num_fields * sizeof(font_fields_t)); - - _process_font_field_data(data_start, (uint8_t*)(data + 3 * 4), num_fields, fontblockobj->vector_fonts[id].fields); - - return 0; -} - -static int _process_text_font_data(uint8_t *data_start, uint8_t *void_data, font_block_t *fontblockobj, int id) -{ - unsigned int num_fields; - uint8_t * data = (uint8_t *) void_data; - - fontblockobj->text_fonts[id].id = *(uint32_t *)(data); - fontblockobj->text_fonts[id].type = (eElemType_t)*(uint32_t *)(data + 1 * 4); - num_fields = *(uint32_t *)(data + 2 * 4); - fontblockobj->text_fonts[id].num_fields = num_fields; - fontblockobj->text_fonts[id].fields = (font_fields_t *)elm_alloc(1, num_fields * sizeof(font_fields_t)); - - _process_font_field_data(data_start, (uint8_t*)(data + 3 * 4), num_fields, fontblockobj->text_fonts[id].fields); - return 0; -} - -static uint32_t *alloc_mem(uint32_t size) -{ - uint32_t *data = NULL; - data = (uint32_t *)elm_alloc(1, size); - JUMP_IF_NULL(data, error_exit); -#ifdef ENABLE_STRICT_DEBUG_MEMSET - memset(data, 0, size); -#endif - return data; -error_exit: - return NULL; -} - -font_block_t *fontblockobj = NULL; - -/* load font-data */ -int _load_font_data(uint8_t *data) -{ - el_Font_Header *font_header = (el_Font_Header *)data; - - if ( fontblockobj != NULL ) - { - return -1; - } - - fontblockobj = (font_block_t *)elm_alloc(1, sizeof(font_block_t)); - memset(fontblockobj, 0, sizeof(font_block_t)); - - fontblockobj->size = font_header->size_font_block; - fontblockobj->type = eElemTypeFont; - fontblockobj->num_ttf_fonts = font_header->num_ttf_fonts; - fontblockobj->num_vector_fonts = font_header->num_vector_fonts; - fontblockobj->num_text_fonts = font_header->num_text_fonts; - fontblockobj->ttf_fonts_block_offset = font_header->ttf_fonts_block_offset; - fontblockobj->ttf_fonts_block_length = font_header->ttf_fonts_block_length; - fontblockobj->vector_fonts_block_offset = font_header->vector_fonts_block_offset; - fontblockobj->vector_fonts_block_length = font_header->vector_fonts_block_length; - fontblockobj->text_fonts_block_offset = font_header->text_fonts_block_offset; - fontblockobj->text_fonts_block_length = font_header->text_fonts_block_length; - fontblockobj->property_block_offset = font_header->property_block_offset; - fontblockobj->property_block_length = font_header->property_block_length; -#ifdef ENABLE_DEBUG_TRACE - printf("size: %d(%0x)\n", fontblockobj->size, fontblockobj->size); - printf("type: %d\n", fontblockobj->type); - printf("num_ttf_fonts: %d\n", fontblockobj->num_ttf_fonts); - printf("num_vector_fonts: %d\n", fontblockobj->num_vector_fonts); - printf("num_text_fonts: %d\n", fontblockobj->num_text_fonts); - printf("ttf_fonts_block_offset: %d(%0x)\n", fontblockobj->ttf_fonts_block_offset, - fontblockobj->ttf_fonts_block_offset); - printf("ttf_fonts_block_length: %d(%0x)\n", fontblockobj->ttf_fonts_block_length, - fontblockobj->ttf_fonts_block_length); - printf("vector_fonts_block_offset: %d(%0x)\n", fontblockobj->vector_fonts_block_offset, - fontblockobj->vector_fonts_block_offset); - printf("vector_fonts_block_length: %d(%0x)\n", fontblockobj->vector_fonts_block_length, - fontblockobj->vector_fonts_block_length); - printf("text_fonts_block_offset: %d(%0x)\n", fontblockobj->text_fonts_block_offset, - fontblockobj->text_fonts_block_offset); - printf("text_fonts_block_length: %d(%0x)\n", fontblockobj->text_fonts_block_length, - fontblockobj->text_fonts_block_length); - printf("property_block_offset: %d(%0x)\n", fontblockobj->property_block_offset, - fontblockobj->property_block_offset); - printf("property_block_length: %d(%0x)\n", fontblockobj->property_block_length, - fontblockobj->property_block_length); -#endif - - g_total_system_font = 0; - - if ( fontblockobj->num_ttf_fonts > 0 ) { - fontblockobj->sizes_of_ttf_data = - (unsigned int *)alloc_mem(4 * fontblockobj->num_ttf_fonts); - fontblockobj->offsets_of_ttf_data = - (unsigned int *)alloc_mem(4 * fontblockobj->num_ttf_fonts); - fontblockobj->ttf_fonts = NULL; - fontblockobj->ttf_fonts = (ttf_font_t *)elm_alloc(1, fontblockobj->num_ttf_fonts * sizeof(ttf_font_t)); - JUMP_IF_NULL(fontblockobj->sizes_of_ttf_data, error_exit); - JUMP_IF_NULL(fontblockobj->offsets_of_ttf_data, error_exit); - JUMP_IF_NULL(fontblockobj->ttf_fonts, error_exit); - - memset(fontblockobj->ttf_fonts, 0, fontblockobj->num_ttf_fonts * sizeof(ttf_font_t)); - for(int i=0; inum_ttf_fonts; i++) - { - fontblockobj->sizes_of_ttf_data[i] = *(uint32_t *)(data + (i) * 4 + fontblockobj->ttf_fonts_block_offset); - printf("ttf-DataSize: %d(%0x)\n", fontblockobj->sizes_of_ttf_data[i], - fontblockobj->sizes_of_ttf_data[i]); - fontblockobj->offsets_of_ttf_data[i] = *(uint32_t *)(data + (i + fontblockobj->num_ttf_fonts) * 4 + fontblockobj->ttf_fonts_block_offset); - printf("ttf-offset: %d(%0x)\n", fontblockobj->offsets_of_ttf_data[i], - fontblockobj->offsets_of_ttf_data[i]); - - if (fontblockobj->sizes_of_ttf_data[i] == 0) - { - continue; - } - - _process_ttf_font_data(data, (uint8_t *)(data + fontblockobj->offsets_of_ttf_data[i]), fontblockobj, i); - } - } - - if ( fontblockobj->num_vector_fonts > 0 ) { - fontblockobj->sizes_of_vector_data = - (unsigned int *)alloc_mem(4 * fontblockobj->num_vector_fonts); - fontblockobj->offsets_of_vector_data = - (unsigned int *)alloc_mem(4 * fontblockobj->num_vector_fonts); - fontblockobj->vector_fonts = NULL; - fontblockobj->vector_fonts = (vector_font_t *)elm_alloc(1, fontblockobj->num_vector_fonts * sizeof(vector_font_t)); - JUMP_IF_NULL(fontblockobj->sizes_of_vector_data, error_exit); - JUMP_IF_NULL(fontblockobj->offsets_of_vector_data, error_exit); - JUMP_IF_NULL(fontblockobj->vector_fonts, error_exit); - - memset(fontblockobj->vector_fonts, 0, fontblockobj->num_vector_fonts * sizeof(vector_font_t)); - for(int i=0; inum_vector_fonts; i++) - { - fontblockobj->sizes_of_vector_data[i] = *(uint32_t *)(data + (i) * 4 + fontblockobj->vector_fonts_block_offset); -#ifdef ENABLE_DEBUG_TRACE - printf("vector-DataSize: %d(%0x)\n", fontblockobj->sizes_of_vector_data[i], - fontblockobj->sizes_of_vector_data[i]); -#endif - fontblockobj->offsets_of_vector_data[i] = *(uint32_t *)(data + (i + fontblockobj->num_vector_fonts) * 4 + fontblockobj->vector_fonts_block_offset); -#ifdef ENABLE_DEBUG_TRACE - printf("vector-offset: %d(%0x)\n", fontblockobj->offsets_of_vector_data[i], - fontblockobj->offsets_of_vector_data[i]); -#endif - - if (fontblockobj->sizes_of_vector_data[i] == 0) - { - continue; - } - - _process_vector_font_data(data, (uint8_t *)(data + fontblockobj->offsets_of_vector_data[i]), fontblockobj, i); - } - } - - if ( fontblockobj->num_text_fonts > 0 ) { - fontblockobj->sizes_of_text_font_data = - (unsigned int *)alloc_mem(4 * fontblockobj->num_text_fonts); - fontblockobj->offsets_of_text_font_data = - (unsigned int *)alloc_mem(4 * fontblockobj->num_text_fonts); - fontblockobj->text_fonts = NULL; - fontblockobj->text_fonts = (ttf_font_t *)elm_alloc(1, fontblockobj->num_text_fonts * sizeof(ttf_font_t)); - JUMP_IF_NULL(fontblockobj->sizes_of_text_font_data, error_exit); - JUMP_IF_NULL(fontblockobj->offsets_of_text_font_data, error_exit); - JUMP_IF_NULL(fontblockobj->text_fonts, error_exit); - memset(fontblockobj->text_fonts, 0, fontblockobj->num_text_fonts * sizeof(ttf_font_t)); - for(int i=0; inum_text_fonts; i++) - { - fontblockobj->sizes_of_text_font_data[i] = *(uint32_t *)(data + (i) * 4 + fontblockobj->text_fonts_block_offset); -#ifdef ENABLE_DEBUG_TRACE - printf("textfont-DataSize: %d(%0x)\n", fontblockobj->sizes_of_text_font_data[i], - fontblockobj->sizes_of_text_font_data[i]); -#endif - fontblockobj->offsets_of_text_font_data[i] = *(uint32_t *)(data + (i + fontblockobj->num_text_fonts) * 4 + fontblockobj->text_fonts_block_offset); -#ifdef ENABLE_DEBUG_TRACE - printf("textfont-offset: %d(%0x)\n", fontblockobj->offsets_of_text_font_data[i], - fontblockobj->offsets_of_text_font_data[i]); -#endif - - if (fontblockobj->sizes_of_text_font_data[i] == 0) - { - continue; - } - - _process_text_font_data(data, (uint8_t *)(data + fontblockobj->offsets_of_text_font_data[i]), fontblockobj, i); - } - } - - return 0; - -error_exit: - destroy_font_data(); - - return -1; -} - -#if (defined(__ICCARM__)) -/* - * Disable the unaligned structure attribute warning. Due to the packed data - * structures used to interpret ELM objects data the IAR compiler issues a - * number of warnings that certain attributes of the headers might be unaligned. - * This is not true, however, as all atributes are manually aligned to 4 bytes. - */ -#pragma diag_suppress = Pa039 -#endif - -#define TEXT_CONTENT_OFFSET_WITHOUT_TRANSFORM 9 * 4 -#define TRANSFORM_MATRIX_LENGTH 9 * 4 -ElmHandle _load_text_data(uint8_t *data, el_Obj_EVO *evo) -{ - el_Obj_TEXT *evo_text = NULL; - uint8_t *text_data = NULL; - el_Text_Header *text_header = (el_Text_Header *)data; - - if (evo == NULL) { -#if (RTOS && DDRLESS) || BAREMETAL - evo = alloc_evo(1); -#else - evo = (el_Obj_EVO *)elm_alloc(1, sizeof(el_Obj_TEXT)); -#endif - } - JUMP_IF_NULL(evo, error_exit); -#ifdef ENABLE_STRICT_DEBUG_MEMSET - memset(evo, 0, sizeof(el_Obj_EVO)); -#endif - evo_text = (el_Obj_TEXT *)evo; - - /* - Default transform matrix is, - identity matrix - no-scaling - zero-translate - */ - _init_transform(&evo_text->defaultAttrib.transform); - memcpy(&evo_text->defaultAttrib.transform.matrix, &text_header->matrix, - sizeof(vg_lite_matrix_t)); - - text_data = (uint8_t *)elm_alloc(1, text_header->data_length); - - memcpy(text_data, (void *)(data + sizeof(el_Text_Header)), text_header->data_length); - - evo_text->tspan_has_dx_dy = text_header->tspan_has_dx_dy; - evo_text->x_pos = (int)text_header->x_pos; - evo_text->y_pos = (int)text_header->y_pos; - evo_text->text_anchor = text_header->text_flags.text_anchor; - evo_text->font_id = (int)text_header->font_id; - evo_text->font_size = (int)text_header->font_size; - evo_text->msg = text_data; - - evo_text->defaultAttrib.quality = (ELM_QUALITY)VG_LITE_HIGH; - evo_text->defaultAttrib.fill_rule = ELM_EVO_FILL_NZ; - evo_text->defaultAttrib.blend = ELM_BLEND_SRC_OVER; - evo_text->defaultAttrib.paint.type = ELM_PAINT_TEXT; - evo_text->defaultAttrib.paint.color = text_header->color; - - evo_text->object.type = ELM_OBJECT_TYPE_EVO; - evo_text->object.reference = 0; - evo_text->attribute = evo_text->defaultAttrib; - - ref_object(&evo_text->object); - JUMP_IF_NON_ZERO_VALUE(add_object(&evo_text->object), error_exit); - - return evo_text->object.handle; - -error_exit: - if ( (evo_text) && (evo_text->msg != NULL) ) { - elm_free(evo_text->msg); - evo_text->msg = NULL; - } - if ( evo != NULL ) { - elm_free(evo); - } - - return ELM_NULL_HANDLE; -} - -#if (defined(__ICCARM__)) -/* Restore the unaligned data structure attribute warning */ -#pragma diag_default = Pa039 -#endif - -void _unload_text(el_Obj_EVO *evo) -{ - el_Obj_TEXT *evo_text = (el_Obj_TEXT *)evo; - if(evo_text->msg != NULL) - { - elm_free(evo_text->msg); - evo_text->msg = NULL; - } -} -void destroy_font_data() -{ - int i=0, j = 0; - if(fontblockobj != NULL) { - if(fontblockobj->sizes_of_ttf_data != NULL){ - elm_free(fontblockobj->sizes_of_ttf_data); - fontblockobj->sizes_of_ttf_data = NULL; - } - if(fontblockobj->offsets_of_ttf_data != NULL){ - elm_free(fontblockobj->offsets_of_ttf_data); - fontblockobj->offsets_of_ttf_data = NULL; - } - if(fontblockobj->sizes_of_vector_data != NULL){ - elm_free(fontblockobj->sizes_of_vector_data); - fontblockobj->sizes_of_vector_data = NULL; - } - if(fontblockobj->offsets_of_vector_data != NULL){ - elm_free(fontblockobj->offsets_of_vector_data); - fontblockobj->offsets_of_vector_data = NULL; - } - if(fontblockobj->sizes_of_text_font_data != NULL){ - elm_free(fontblockobj->sizes_of_text_font_data); - fontblockobj->sizes_of_text_font_data = NULL; - } - if(fontblockobj->offsets_of_text_font_data != NULL){ - elm_free(fontblockobj->offsets_of_text_font_data); - fontblockobj->offsets_of_text_font_data = NULL; - } - for(i=0; inum_ttf_fonts; i++) - { - if(fontblockobj->ttf_fonts[i].fields != NULL){ - for(j=0; jttf_fonts[i].num_fields; j++) - { - if(fontblockobj->ttf_fonts[i].fields[j].data != NULL) { - elm_free(fontblockobj->ttf_fonts[i].fields[j].data); - fontblockobj->ttf_fonts[i].fields[j].data = NULL; - } - } - elm_free(fontblockobj->ttf_fonts[i].fields); - fontblockobj->ttf_fonts[i].fields = NULL; - } - } - if(fontblockobj->ttf_fonts != NULL){ - elm_free(fontblockobj->ttf_fonts); - fontblockobj->ttf_fonts = NULL; - } - for(i=0; inum_vector_fonts; i++) - { - if(fontblockobj->vector_fonts[i].fields != NULL){ - for(j=0; jvector_fonts[i].num_fields; j++) - { - if(fontblockobj->vector_fonts[i].fields[j].data != NULL) { - elm_free(fontblockobj->vector_fonts[i].fields[j].data); - fontblockobj->vector_fonts[i].fields[j].data = NULL; - } - } - elm_free(fontblockobj->vector_fonts[i].fields); - fontblockobj->vector_fonts[i].fields = NULL; - } - } - if(fontblockobj->vector_fonts != NULL){ - elm_free(fontblockobj->vector_fonts); - fontblockobj->vector_fonts = NULL; - } - for(i=0; inum_text_fonts; i++) - { - if(fontblockobj->text_fonts[i].fields != NULL){ - for(j=0; jtext_fonts[i].num_fields; j++) - { - if(fontblockobj->text_fonts[i].fields[j].data != NULL) { - elm_free(fontblockobj->text_fonts[i].fields[j].data); - fontblockobj->text_fonts[i].fields[j].data = NULL; - } - } - elm_free(fontblockobj->text_fonts[i].fields); - fontblockobj->text_fonts[i].fields = NULL; - } - } - if(fontblockobj->text_fonts != NULL){ - elm_free(fontblockobj->text_fonts); - fontblockobj->text_fonts = NULL; - } - - elm_free(fontblockobj); - fontblockobj = NULL; - } - - vg_lite_unload_font_data(); - - for(int i=0; i // for snprintf +#include +#include + +#include "FreeRTOS.h" + +#include "vg_lite.h" +#include "Elm.h" +#include "velm.h" +#include "vg_lite_text.h" +#include "elm_headers.h" +#include "elm_text.h" +#include "elm_precom.h" +#include "vft_draw.h" + +/** Macros */ +#ifndef VECTOR_DEFAULT_FONT +#define VECTOR_DEFAULT_FONT 1 +#endif + +#if VECTOR_DEFAULT_FONT /* Use vector font as default font */ +#define DEFAULT_FONT_NAME "SVGFreeSansASCII" +#define DEFAULT_FONT_WEIGHT eFontWeightRegular +#define DEFAULT_FONT_STRETCH eFontStretchNormal +#define DEFAULT_FONT_STYLE eFontStyleNormal +#define DEFAULT_FONT_HEIGHT 35 +#define DEFAULT_TEXT_FG_COLOR 0xff000000 +#define DEFAULT_TEXT_ALIGN (eTextAlignLeft) + +#else /* Use raster font as default font */ +#define DEFAULT_FONT_NAME "DejaVuSans_Oblique" +#define DEFAULT_FONT_WEIGHT eFontWeightRegular +#define DEFAULT_FONT_STRETCH eFontStretchNormal +#define DEFAULT_FONT_STYLE eFontStyleItalic +#define DEFAULT_FONT_HEIGHT 35 +#define DEFAULT_TEXT_FG_COLOR 0xff000000 +#define DEFAULT_TEXT_ALIGN (eTextAlignLeft) + +#endif + +/* Maximum font properties from EVO file */ +#define MAX_FONT_ATTRIB_COMBINATIONS (32) + +#define TRANSPARENT_VGLITE_COLOUR(a, r, g, b) \ + ((uint32_t)(a) << 24) | ((uint32_t)(b) << 16) | ((uint32_t)(g) << 8) | \ + (uint32_t)r + +#define OPAQUE_VGLITE_COLOUR(r, g, b) TRANSPARENT_VGLITE_COLOUR(0xff, r, g, b) + +/** Data structures */ + +/** Internal or external API prototypes */ +int vg_lite_is_font_valid(vg_lite_font_t font); +char *vg_lite_get_font_name(vg_lite_font_t font); +vg_lite_error_t vg_lite_free_font_memory(vg_lite_font_t font); +int ref_object (el_Object *object); + +/** Globals */ +int g_total_system_font = 0; +static font_field_info_t g_default_font_properties[eMaxFontProperties]; +static font_field_info_t g_font_properties[MAX_FONT_ATTRIB_COMBINATIONS][eMaxFontProperties]; + +/** Externs if any */ +extern vg_lite_font_attributes_t g_font_attribs; +extern vg_lite_font_t g_last_font; +extern int g_last_font_attrib_idx; + +void initialize_elm_text(void) +{ + font_field_info_t *font_fields = NULL; + /* internal parameters of mcufont library */ + g_font_attribs.alignment = 0; + g_font_attribs.scale = 1; + g_font_attribs.width = 1200; /* Describes drawing area */ + g_font_attribs.margin = 5; /* Left margin in drawing area */ + g_font_attribs.bg_color = OPAQUE_VGLITE_COLOUR(0xff,0xff,0xff); // white + g_font_attribs.last_y = 0; + g_font_attribs.last_x =0; + g_font_attribs.last_dx = 0; + + /* Initialize default properties */ + font_fields = &g_default_font_properties[0]; + + char *font_name = (char *)elm_alloc(1, strlen(DEFAULT_FONT_NAME)+1); + strcpy(font_name, DEFAULT_FONT_NAME); + font_fields[eFontNameProperty].value.data = font_name; + font_fields[eFontWeightProperty].value.i_value = DEFAULT_FONT_WEIGHT; + font_fields[eFontStretchProperty].value.i_value = DEFAULT_FONT_STRETCH; + font_fields[eFontStyleProperty].value.i_value = DEFAULT_FONT_STYLE; + font_fields[eFontHeightProperty].value.i_value = DEFAULT_FONT_HEIGHT; + font_fields[eTextColorProperty].value.i_value = DEFAULT_TEXT_FG_COLOR; + font_fields[eTextAlignProperty].value.i_value = DEFAULT_TEXT_ALIGN; +} + +static int get_property(font_field_info_t *dst_font_fields, font_fields_t *src_font_fields, int num_fields) +{ + int i=0; + int len; + + /* Initialize default values */ + dst_font_fields[eFontWeightProperty].value.i_value = DEFAULT_FONT_WEIGHT; + dst_font_fields[eFontStretchProperty].value.i_value = DEFAULT_FONT_STRETCH; + dst_font_fields[eFontStyleProperty].value.i_value = eFontStyleNormal; + dst_font_fields[eTextAlignProperty].value.i_value = DEFAULT_TEXT_ALIGN; + + dst_font_fields[eFontNameProperty].value.data = NULL; + dst_font_fields[eFontHeightProperty].value.i_value = DEFAULT_FONT_HEIGHT; + dst_font_fields[eTextColorProperty].value.i_value = DEFAULT_TEXT_FG_COLOR; + + for(i=0; iattribute.blend; + vg_lite_font_t curr_font = VG_LITE_INVALID_FONT; + int curr_font_attrib_idx = INVALID_FONT_PROPERTY_IDX; + + vg_lite_font_attributes_t *font_attribs = &g_font_attribs; + font_field_info_t *font_fields = NULL; + + curr_font_attrib_idx = text->font_id; + + /* Single font caching can be done here (No caching for now) + Release last font object if it is different + */ + if ( vg_lite_is_font_valid(g_last_font) == 1 ) { + /* recycle font objects */ + vg_lite_free_font_memory(g_last_font); + g_last_font = VG_LITE_INVALID_FONT; + } + + if(curr_font_attrib_idx != INVALID_FONT_PROPERTY_IDX) + { + font_fields = &g_font_properties[curr_font_attrib_idx][0]; + font_fields[eFontHeightProperty].value.i_value = text->font_size; + + curr_font = vg_lite_find_font( + font_fields[eFontNameProperty].value.data, + (eFontWeight_t)font_fields[eFontWeightProperty].value.i_value, + (eFontStretch_t)font_fields[eFontStretchProperty].value.i_value, + (eFontStyle_t)font_fields[eFontStyleProperty].value.i_value, + font_fields[eFontHeightProperty].value.i_value + ); + } + + if (curr_font == VG_LITE_INVALID_FONT) { + //printf("ERROR: Font not found. Rendering with default configuration\n"); + font_fields = &g_default_font_properties[0]; + curr_font = vg_lite_find_font( + font_fields[eFontNameProperty].value.data, + (eFontWeight_t)font_fields[eFontWeightProperty].value.i_value, + (eFontStretch_t)font_fields[eFontStretchProperty].value.i_value, + (eFontStyle_t)font_fields[eFontStyleProperty].value.i_value, + font_fields[eFontHeightProperty].value.i_value); + } + if (curr_font == VG_LITE_INVALID_FONT) { + printf("Font[%s] not found\n", font_fields[eFontNameProperty].value.data); + return VG_LITE_INVALID_ARGUMENT; + } + font_attribs->is_vector_font = vg_lite_is_vector_font(curr_font); + /* Properties that changes over time */ + font_attribs->text_color = text->attribute.paint.color; + font_attribs->alignment = (eTextAlign_t)text->text_anchor; + font_attribs->font_height = font_fields[eFontHeightProperty].value.i_value; + font_attribs->tspan_has_dx_dy = text->tspan_has_dx_dy; + + error = vg_lite_draw_text(&buff->buffer, + (char *)text->msg, + curr_font, + text->x_pos, text->y_pos, + &text->attribute.transform.matrix, + blend, + font_attribs); + + g_last_font = curr_font; + g_last_font_attrib_idx = curr_font_attrib_idx; + return error; +} + +/* process font-field data */ +static int _process_font_field_data( uint8_t *data_start, uint8_t *data, int num_fields, font_fields_t* fields) +{ + eFontFields_t eName; + + if (g_total_system_font >= MAX_FONT_ATTRIB_COMBINATIONS) { + printf("WARNING: Font property buffer overflowing...\n" + "Increase MAX_FONT_ATTRIB_COMBINATIONS\n"); + return -1; + } + + for(int i=0; ittf_fonts[id].id = *(uint32_t *)(data); + fontblockobj->ttf_fonts[id].type = (eElemType_t)*(uint32_t *)(data + 1 * 4); + num_fields = *(uint32_t *)(data + 2 * 4); + fontblockobj->ttf_fonts[id].num_fields = num_fields; + fontblockobj->ttf_fonts[id].fields = (font_fields_t *)elm_alloc(1, num_fields * sizeof(font_fields_t)); + + _process_font_field_data(data_start, (uint8_t*)(data + 3 * 4), num_fields, fontblockobj->ttf_fonts[id].fields); + return 0; +} + +/* process vector-type font data */ +static int _process_vector_font_data(uint8_t *data_start, uint8_t *data, font_block_t *fontblockobj, int id) +{ + unsigned int num_fields = 0; + + fontblockobj->vector_fonts[id].id = *(uint32_t *)(data); + fontblockobj->vector_fonts[id].type = (eElemType_t)*(uint32_t *)(data + 1 * 4); + num_fields = *(uint32_t *)(data + 2 * 4); + fontblockobj->vector_fonts[id].num_fields = num_fields; + fontblockobj->vector_fonts[id].fields = (font_fields_t *)elm_alloc(1, num_fields * sizeof(font_fields_t)); + + _process_font_field_data(data_start, (uint8_t*)(data + 3 * 4), num_fields, fontblockobj->vector_fonts[id].fields); + + return 0; +} + +static int _process_text_font_data(uint8_t *data_start, uint8_t *void_data, font_block_t *fontblockobj, int id) +{ + unsigned int num_fields; + uint8_t * data = (uint8_t *) void_data; + + fontblockobj->text_fonts[id].id = *(uint32_t *)(data); + fontblockobj->text_fonts[id].type = (eElemType_t)*(uint32_t *)(data + 1 * 4); + num_fields = *(uint32_t *)(data + 2 * 4); + fontblockobj->text_fonts[id].num_fields = num_fields; + fontblockobj->text_fonts[id].fields = (font_fields_t *)elm_alloc(1, num_fields * sizeof(font_fields_t)); + + _process_font_field_data(data_start, (uint8_t*)(data + 3 * 4), num_fields, fontblockobj->text_fonts[id].fields); + return 0; +} + +static uint32_t *alloc_mem(uint32_t size) +{ + uint32_t *data = NULL; + data = (uint32_t *)elm_alloc(1, size); + JUMP_IF_NULL(data, error_exit); +#ifdef ENABLE_STRICT_DEBUG_MEMSET + memset(data, 0, size); +#endif + return data; +error_exit: + return NULL; +} + +font_block_t *fontblockobj = NULL; + +/* load font-data */ +int _load_font_data(uint8_t *data) +{ + el_Font_Header *font_header = (el_Font_Header *)data; + + if ( fontblockobj != NULL ) + { + return -1; + } + + fontblockobj = (font_block_t *)elm_alloc(1, sizeof(font_block_t)); + memset(fontblockobj, 0, sizeof(font_block_t)); + + fontblockobj->size = font_header->size_font_block; + fontblockobj->type = eElemTypeFont; + fontblockobj->num_ttf_fonts = font_header->num_ttf_fonts; + fontblockobj->num_vector_fonts = font_header->num_vector_fonts; + fontblockobj->num_text_fonts = font_header->num_text_fonts; + fontblockobj->ttf_fonts_block_offset = font_header->ttf_fonts_block_offset; + fontblockobj->ttf_fonts_block_length = font_header->ttf_fonts_block_length; + fontblockobj->vector_fonts_block_offset = font_header->vector_fonts_block_offset; + fontblockobj->vector_fonts_block_length = font_header->vector_fonts_block_length; + fontblockobj->text_fonts_block_offset = font_header->text_fonts_block_offset; + fontblockobj->text_fonts_block_length = font_header->text_fonts_block_length; + fontblockobj->property_block_offset = font_header->property_block_offset; + fontblockobj->property_block_length = font_header->property_block_length; +#ifdef ENABLE_DEBUG_TRACE + printf("size: %d(%0x)\n", fontblockobj->size, fontblockobj->size); + printf("type: %d\n", fontblockobj->type); + printf("num_ttf_fonts: %d\n", fontblockobj->num_ttf_fonts); + printf("num_vector_fonts: %d\n", fontblockobj->num_vector_fonts); + printf("num_text_fonts: %d\n", fontblockobj->num_text_fonts); + printf("ttf_fonts_block_offset: %d(%0x)\n", fontblockobj->ttf_fonts_block_offset, + fontblockobj->ttf_fonts_block_offset); + printf("ttf_fonts_block_length: %d(%0x)\n", fontblockobj->ttf_fonts_block_length, + fontblockobj->ttf_fonts_block_length); + printf("vector_fonts_block_offset: %d(%0x)\n", fontblockobj->vector_fonts_block_offset, + fontblockobj->vector_fonts_block_offset); + printf("vector_fonts_block_length: %d(%0x)\n", fontblockobj->vector_fonts_block_length, + fontblockobj->vector_fonts_block_length); + printf("text_fonts_block_offset: %d(%0x)\n", fontblockobj->text_fonts_block_offset, + fontblockobj->text_fonts_block_offset); + printf("text_fonts_block_length: %d(%0x)\n", fontblockobj->text_fonts_block_length, + fontblockobj->text_fonts_block_length); + printf("property_block_offset: %d(%0x)\n", fontblockobj->property_block_offset, + fontblockobj->property_block_offset); + printf("property_block_length: %d(%0x)\n", fontblockobj->property_block_length, + fontblockobj->property_block_length); +#endif + + g_total_system_font = 0; + + if ( fontblockobj->num_ttf_fonts > 0 ) { + fontblockobj->sizes_of_ttf_data = + (unsigned int *)alloc_mem(4 * fontblockobj->num_ttf_fonts); + fontblockobj->offsets_of_ttf_data = + (unsigned int *)alloc_mem(4 * fontblockobj->num_ttf_fonts); + fontblockobj->ttf_fonts = NULL; + fontblockobj->ttf_fonts = (ttf_font_t *)elm_alloc(1, fontblockobj->num_ttf_fonts * sizeof(ttf_font_t)); + JUMP_IF_NULL(fontblockobj->sizes_of_ttf_data, error_exit); + JUMP_IF_NULL(fontblockobj->offsets_of_ttf_data, error_exit); + JUMP_IF_NULL(fontblockobj->ttf_fonts, error_exit); + + memset(fontblockobj->ttf_fonts, 0, fontblockobj->num_ttf_fonts * sizeof(ttf_font_t)); + for(int i=0; inum_ttf_fonts; i++) + { + fontblockobj->sizes_of_ttf_data[i] = *(uint32_t *)(data + (i) * 4 + fontblockobj->ttf_fonts_block_offset); + printf("ttf-DataSize: %d(%0x)\n", fontblockobj->sizes_of_ttf_data[i], + fontblockobj->sizes_of_ttf_data[i]); + fontblockobj->offsets_of_ttf_data[i] = *(uint32_t *)(data + (i + fontblockobj->num_ttf_fonts) * 4 + fontblockobj->ttf_fonts_block_offset); + printf("ttf-offset: %d(%0x)\n", fontblockobj->offsets_of_ttf_data[i], + fontblockobj->offsets_of_ttf_data[i]); + + if (fontblockobj->sizes_of_ttf_data[i] == 0) + { + continue; + } + + _process_ttf_font_data(data, (uint8_t *)(data + fontblockobj->offsets_of_ttf_data[i]), fontblockobj, i); + } + } + + if ( fontblockobj->num_vector_fonts > 0 ) { + fontblockobj->sizes_of_vector_data = + (unsigned int *)alloc_mem(4 * fontblockobj->num_vector_fonts); + fontblockobj->offsets_of_vector_data = + (unsigned int *)alloc_mem(4 * fontblockobj->num_vector_fonts); + fontblockobj->vector_fonts = NULL; + fontblockobj->vector_fonts = (vector_font_t *)elm_alloc(1, fontblockobj->num_vector_fonts * sizeof(vector_font_t)); + JUMP_IF_NULL(fontblockobj->sizes_of_vector_data, error_exit); + JUMP_IF_NULL(fontblockobj->offsets_of_vector_data, error_exit); + JUMP_IF_NULL(fontblockobj->vector_fonts, error_exit); + + memset(fontblockobj->vector_fonts, 0, fontblockobj->num_vector_fonts * sizeof(vector_font_t)); + for(int i=0; inum_vector_fonts; i++) + { + fontblockobj->sizes_of_vector_data[i] = *(uint32_t *)(data + (i) * 4 + fontblockobj->vector_fonts_block_offset); +#ifdef ENABLE_DEBUG_TRACE + printf("vector-DataSize: %d(%0x)\n", fontblockobj->sizes_of_vector_data[i], + fontblockobj->sizes_of_vector_data[i]); +#endif + fontblockobj->offsets_of_vector_data[i] = *(uint32_t *)(data + (i + fontblockobj->num_vector_fonts) * 4 + fontblockobj->vector_fonts_block_offset); +#ifdef ENABLE_DEBUG_TRACE + printf("vector-offset: %d(%0x)\n", fontblockobj->offsets_of_vector_data[i], + fontblockobj->offsets_of_vector_data[i]); +#endif + + if (fontblockobj->sizes_of_vector_data[i] == 0) + { + continue; + } + + _process_vector_font_data(data, (uint8_t *)(data + fontblockobj->offsets_of_vector_data[i]), fontblockobj, i); + } + } + + if ( fontblockobj->num_text_fonts > 0 ) { + fontblockobj->sizes_of_text_font_data = + (unsigned int *)alloc_mem(4 * fontblockobj->num_text_fonts); + fontblockobj->offsets_of_text_font_data = + (unsigned int *)alloc_mem(4 * fontblockobj->num_text_fonts); + fontblockobj->text_fonts = NULL; + fontblockobj->text_fonts = (ttf_font_t *)elm_alloc(1, fontblockobj->num_text_fonts * sizeof(ttf_font_t)); + JUMP_IF_NULL(fontblockobj->sizes_of_text_font_data, error_exit); + JUMP_IF_NULL(fontblockobj->offsets_of_text_font_data, error_exit); + JUMP_IF_NULL(fontblockobj->text_fonts, error_exit); + memset(fontblockobj->text_fonts, 0, fontblockobj->num_text_fonts * sizeof(ttf_font_t)); + for(int i=0; inum_text_fonts; i++) + { + fontblockobj->sizes_of_text_font_data[i] = *(uint32_t *)(data + (i) * 4 + fontblockobj->text_fonts_block_offset); +#ifdef ENABLE_DEBUG_TRACE + printf("textfont-DataSize: %d(%0x)\n", fontblockobj->sizes_of_text_font_data[i], + fontblockobj->sizes_of_text_font_data[i]); +#endif + fontblockobj->offsets_of_text_font_data[i] = *(uint32_t *)(data + (i + fontblockobj->num_text_fonts) * 4 + fontblockobj->text_fonts_block_offset); +#ifdef ENABLE_DEBUG_TRACE + printf("textfont-offset: %d(%0x)\n", fontblockobj->offsets_of_text_font_data[i], + fontblockobj->offsets_of_text_font_data[i]); +#endif + + if (fontblockobj->sizes_of_text_font_data[i] == 0) + { + continue; + } + + _process_text_font_data(data, (uint8_t *)(data + fontblockobj->offsets_of_text_font_data[i]), fontblockobj, i); + } + } + + return 0; + +error_exit: + destroy_font_data(); + + return -1; +} + +#if (defined(__ICCARM__)) +/* + * Disable the unaligned structure attribute warning. Due to the packed data + * structures used to interpret ELM objects data the IAR compiler issues a + * number of warnings that certain attributes of the headers might be unaligned. + * This is not true, however, as all atributes are manually aligned to 4 bytes. + */ +#pragma diag_suppress = Pa039 +#endif + +#define TEXT_CONTENT_OFFSET_WITHOUT_TRANSFORM 9 * 4 +#define TRANSFORM_MATRIX_LENGTH 9 * 4 +ElmHandle _load_text_data(uint8_t *data, el_Obj_EVO *evo) +{ + el_Obj_TEXT *evo_text = NULL; + uint8_t *text_data = NULL; + el_Text_Header *text_header = (el_Text_Header *)data; + + if (evo == NULL) { +#if (RTOS && DDRLESS) || BAREMETAL + evo = alloc_evo(1); +#else + evo = (el_Obj_EVO *)elm_alloc(1, sizeof(el_Obj_TEXT)); +#endif + } + JUMP_IF_NULL(evo, error_exit); +#ifdef ENABLE_STRICT_DEBUG_MEMSET + memset(evo, 0, sizeof(el_Obj_EVO)); +#endif + evo_text = (el_Obj_TEXT *)evo; + + /* + Default transform matrix is, + identity matrix + no-scaling + zero-translate + */ + _init_transform(&evo_text->defaultAttrib.transform); + memcpy(&evo_text->defaultAttrib.transform.matrix, &text_header->matrix, + sizeof(vg_lite_matrix_t)); + + text_data = (uint8_t *)elm_alloc(1, text_header->data_length); + + memcpy(text_data, (void *)(data + sizeof(el_Text_Header)), text_header->data_length); + + evo_text->tspan_has_dx_dy = text_header->tspan_has_dx_dy; + evo_text->x_pos = (int)text_header->x_pos; + evo_text->y_pos = (int)text_header->y_pos; + evo_text->text_anchor = text_header->text_flags.text_anchor; + evo_text->font_id = (int)text_header->font_id; + evo_text->font_size = (int)text_header->font_size; + evo_text->msg = text_data; + + evo_text->defaultAttrib.quality = (ELM_QUALITY)VG_LITE_HIGH; + evo_text->defaultAttrib.fill_rule = ELM_EVO_FILL_NZ; + evo_text->defaultAttrib.blend = ELM_BLEND_SRC_OVER; + evo_text->defaultAttrib.paint.type = ELM_PAINT_TEXT; + evo_text->defaultAttrib.paint.color = text_header->color; + + evo_text->object.type = ELM_OBJECT_TYPE_EVO; + evo_text->object.reference = 0; + evo_text->attribute = evo_text->defaultAttrib; + + ref_object(&evo_text->object); + JUMP_IF_NON_ZERO_VALUE(add_object(&evo_text->object), error_exit); + + return evo_text->object.handle; + +error_exit: + if ( (evo_text) && (evo_text->msg != NULL) ) { + elm_free(evo_text->msg); + evo_text->msg = NULL; + } + if ( evo != NULL ) { + elm_free(evo); + } + + return ELM_NULL_HANDLE; +} + +#if (defined(__ICCARM__)) +/* Restore the unaligned data structure attribute warning */ +#pragma diag_default = Pa039 +#endif + +void _unload_text(el_Obj_EVO *evo) +{ + el_Obj_TEXT *evo_text = (el_Obj_TEXT *)evo; + if(evo_text->msg != NULL) + { + elm_free(evo_text->msg); + evo_text->msg = NULL; + } +} +void destroy_font_data() +{ + int i=0, j = 0; + if(fontblockobj != NULL) { + if(fontblockobj->sizes_of_ttf_data != NULL){ + elm_free(fontblockobj->sizes_of_ttf_data); + fontblockobj->sizes_of_ttf_data = NULL; + } + if(fontblockobj->offsets_of_ttf_data != NULL){ + elm_free(fontblockobj->offsets_of_ttf_data); + fontblockobj->offsets_of_ttf_data = NULL; + } + if(fontblockobj->sizes_of_vector_data != NULL){ + elm_free(fontblockobj->sizes_of_vector_data); + fontblockobj->sizes_of_vector_data = NULL; + } + if(fontblockobj->offsets_of_vector_data != NULL){ + elm_free(fontblockobj->offsets_of_vector_data); + fontblockobj->offsets_of_vector_data = NULL; + } + if(fontblockobj->sizes_of_text_font_data != NULL){ + elm_free(fontblockobj->sizes_of_text_font_data); + fontblockobj->sizes_of_text_font_data = NULL; + } + if(fontblockobj->offsets_of_text_font_data != NULL){ + elm_free(fontblockobj->offsets_of_text_font_data); + fontblockobj->offsets_of_text_font_data = NULL; + } + for(i=0; inum_ttf_fonts; i++) + { + if(fontblockobj->ttf_fonts[i].fields != NULL){ + for(j=0; jttf_fonts[i].num_fields; j++) + { + if(fontblockobj->ttf_fonts[i].fields[j].data != NULL) { + elm_free(fontblockobj->ttf_fonts[i].fields[j].data); + fontblockobj->ttf_fonts[i].fields[j].data = NULL; + } + } + elm_free(fontblockobj->ttf_fonts[i].fields); + fontblockobj->ttf_fonts[i].fields = NULL; + } + } + if(fontblockobj->ttf_fonts != NULL){ + elm_free(fontblockobj->ttf_fonts); + fontblockobj->ttf_fonts = NULL; + } + for(i=0; inum_vector_fonts; i++) + { + if(fontblockobj->vector_fonts[i].fields != NULL){ + for(j=0; jvector_fonts[i].num_fields; j++) + { + if(fontblockobj->vector_fonts[i].fields[j].data != NULL) { + elm_free(fontblockobj->vector_fonts[i].fields[j].data); + fontblockobj->vector_fonts[i].fields[j].data = NULL; + } + } + elm_free(fontblockobj->vector_fonts[i].fields); + fontblockobj->vector_fonts[i].fields = NULL; + } + } + if(fontblockobj->vector_fonts != NULL){ + elm_free(fontblockobj->vector_fonts); + fontblockobj->vector_fonts = NULL; + } + for(i=0; inum_text_fonts; i++) + { + if(fontblockobj->text_fonts[i].fields != NULL){ + for(j=0; jtext_fonts[i].num_fields; j++) + { + if(fontblockobj->text_fonts[i].fields[j].data != NULL) { + elm_free(fontblockobj->text_fonts[i].fields[j].data); + fontblockobj->text_fonts[i].fields[j].data = NULL; + } + } + elm_free(fontblockobj->text_fonts[i].fields); + fontblockobj->text_fonts[i].fields = NULL; + } + } + if(fontblockobj->text_fonts != NULL){ + elm_free(fontblockobj->text_fonts); + fontblockobj->text_fonts = NULL; + } + + elm_free(fontblockobj); + fontblockobj = NULL; + } + + vg_lite_unload_font_data(); + + for(int i=0; igContext.object_slots[id % SLOT_COUNT] - - /* - VGLite releated configurations. - */ -#define TS_WIDTH 64 -#define TS_HEIGHT 64 -#define RTOS 1 -#define APP_BUFFER_COUNT 2 -#if (RTOS && DDRLESS) || BAREMETAL -#define OBJCOUNT_GRAD 16 -#define OBJCOUNT_EVO 128 -#define OBJCOUNT_EBO 64 -#define OBJCOUNT_GROUP 16 -#endif - -#if RTOS -#include "FreeRTOS.h" - -#define elm_alloc(num_objects,object_size) pvPortMalloc(num_objects * object_size) -#define elm_free vPortFree -#else -#define elm_alloc calloc -#define elm_free free -#endif - -typedef enum { - ELEMENT_LINEARGRADIENT = 0, /*! linear gradient element */ - ELEMENT_PATH = 1, /*! path element */ - ELEMENT_GROUP = 2, /*! group element */ - ELEMENT_TEXT = 3, /*! text element */ - ELEMENT_TSPAN = 4, /*! tspan element */ - ELEMENT_FONT = 5, /*! font element */ - ELEMENT_TTF_FONT = 6, /*! ttf-type font */ - ELEMENT_VECTOR_FONT = 7, /*! vector fonts */ - ELEMENT_TEXT_FONT = 8, /*! text fonts */ -} ELM_ELEMENT_TYPE; - -#define COUNT_OF(array) (sizeof(array) / sizeof(array[0])) - /* - System definitions. - */ -#define DEBUG_ASSERT(a, message) \ - if (!a) \ - printf("%s: ASSERT failed @ %s, %d.\n", message, __FILE__, __LINE__) - - /*! - @typedef el_Object - common object type definition shared by all EVO object to identify its handle, - object type, and ELM version info. - for reference purpose, handle = 0 is reserved. - */ - typedef struct { - ElmHandle handle; - ELM_OBJECT_TYPE type; - unsigned int reference; // Reference count by other objects. -#if (RTOS && DDRLESS) || BAREMETAL - int index; /* The index of the object in pool. */ -#endif - } el_Object; - - /*! - @typedef el_Transform - The transformation attribute for an EVO/EBO/Group object. - */ - typedef struct { - float rotate; - float translate[2]; - float scale[2]; - BOOL dirty; - BOOL identity; - vg_lite_matrix_t matrix; - } el_Transform; - - /*! - @typedef el_GradData - Linear gradient definition. - !grad the native vg_lite gradient data; - !gransform the grad's transformation. matrix is synced to grad's. - */ - typedef struct { - vg_lite_linear_gradient_t grad; - el_Transform transform; - } el_GradData; - - /*! - @typedef el_RadgradData - Radial gradient definition. - !rad_grad the native vg_lite_radial_gradient data; - !gransform the grad's transformation. matrix is synced to grad's. - */ - typedef struct { - vg_lite_radial_gradient_t rad_grad; - el_Transform transform; - } el_RadgradData; - - /*! - @typedef el_Obj_Grad - The linear gradient object definition. - */ - typedef struct { - el_Object object; - el_GradData data; - } el_Obj_Grad; - - /*! - @typedef el_Obj_Radgrad - The radial gradient object definition. - */ - typedef struct { - el_Object object; - el_RadgradData data; - } el_Obj_Radgrad; - - /*! - @typedef el_Obj_Pattern - The pattern paint object definition. - pattern: it should be an pointer to an el_Obj_EVO; - mode: the pattern fill mode. - color: the color value if pattern mode is COLOR - */ - typedef struct { - void *pattern; - ELM_PATTERN_MODE mode; - uint32_t color; - } el_Obj_Pattern; - - /*! - @typedef el_Paint - The paint object definition. - color: for solid fill; - grad: for linear gradient fill; - pattern: for image fill. - */ - typedef struct { - ELM_PAINT_TYPE type; - uint32_t color; - el_Obj_Grad * grad; - el_Obj_Radgrad * radgrad; - el_Obj_Pattern pattern; - } el_Paint; - - /*! - @typedef el_Attribute - The rendering attribute definition. - */ - typedef struct { - ELM_QUALITY quality; - ELM_BLEND blend; - ELM_EVO_FILL fill_rule; - el_Paint paint; - el_Transform transform; - } el_Attribute; - - /*! - @typedef el_EVOData - The data definition for EVO (vector object). - */ - typedef struct { - vg_lite_path_t path; - } el_EVOData; - - /*! - @typedef el_Obj_EVO - EVO (Elementry Vector Object) type definition. - */ - typedef struct { - el_Object object; - el_Attribute attribute; - el_Attribute defaultAttrib; - el_EVOData data; - uint32_t has_pattern; - uint32_t is_pattern; - uint32_t is_image; - char eboname[20]; - uint32_t img_width; - uint32_t img_height; - } el_Obj_EVO; - - /*! - @typedef el_EBOData - The data definition for EBO (bitmap object). - */ - typedef struct { - vg_lite_buffer_t buffer; - } el_EBOData; - - /*! - @typedef el_Obj_EBO - EBO (Elementry Buffer Object) type definition. - */ - typedef struct { - el_Object object; - el_Attribute attribute; - el_Attribute defaultAttrib; - el_EBOData data; - uint32_t clut_count; - uint32_t clut[256]; - } el_Obj_EBO; - - /*! - @typedef el_GroupData - The group object data definition. - */ - typedef struct { - unsigned int count; - el_Obj_EVO * objects; - } el_GroupData; - - /*! - @typedef el_Obj_Group - Group object type definition. - */ - typedef struct { - el_Object object; - el_Transform transform; - el_Transform defaultTrans; - el_GroupData group; - } el_Obj_Group; - - /*! - @typedef el_Obj_Buffer - The render buffer object definition. - */ - typedef struct { - el_Object object; - vg_lite_buffer_t buffer; - } el_Obj_Buffer; - - /*! - @typedef el_ObjList - List to organize objects. - */ - typedef struct _object_list{ - el_Object *object; - struct _object_list *next; - } el_ObjList; - - /*! - @typedef ElmRenderBuffer - The ElmRenderBuffer definition. - */ - typedef struct elm_render_buffer { - ElmBuffer handle; - vg_lite_buffer_t *buffer; - } ElmRenderBuffer; - - /*! - @typedef el_Context - The context object for global data management. - !version UXDK version - !currentHandle The current handle for new object - !objectCount Count of all objects - !object_slots List array to manage objects - */ - typedef struct { - uint32_t version; - int reference; - ElmHandle currentHandle; - unsigned int objectCount; - el_ObjList *object_slots[SLOT_COUNT]; - ElmRenderBuffer elmFB[APP_BUFFER_COUNT]; - /* VGLite related states. */ - uint32_t tessellation_width; - uint32_t tessellation_height; - - /* The current vector index (within a group). */ - int32_t vector_id; - -#if (RTOS && DDRLESS) || BAREMETAL - /* Static object pools. */ - el_Obj_Grad objpool_grad[OBJCOUNT_GRAD]; - el_Obj_EVO objpool_evo[OBJCOUNT_EVO]; - el_Obj_EBO objpool_ebo[OBJCOUNT_EBO]; - el_Obj_Group objpool_group[OBJCOUNT_GROUP]; - - /* The allocation map table. - * Each bit in the element maps to the usage of the object. - * 0 means free, 1 means allocated. - * The mapping order is 01234567...31 (hi -> low) in big endian systems. - * */ - int32_t objmap_grad[(OBJCOUNT_GRAD + 31) / 32]; - int32_t objmap_evo[(OBJCOUNT_EVO + 31) / 32]; - int32_t objmap_ebo[(OBJCOUNT_EBO + 31) / 32]; - int32_t objmap_group[(OBJCOUNT_GROUP + 31) / 32]; - - int objcounter_grad; - int objcounter_evo; - int objcounter_ebo; - int objcounter_group; -#endif - } el_Context; - - /*! - @typedef elm_tls_t - The elm_tls_t definition. - */ - typedef struct vglite_elm_tls { - el_Context gContext; - } elm_tls_t; - - /* - API function prototypes. - */ - int add_object (el_Object *object); - int remove_object (el_Object *object); - el_Object *get_object (ElmHandle handle); - -#ifdef __cplusplus -} -#endif -#endif /* VELM_H_ */ +/**************************************************************************** +* +* Copyright 2012 - 2020 Vivante Corporation, Santa Clara, California. +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +#ifndef VELM_H_ +#define VELM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + /* + */ +#define VERSION 0x00000001 +#define SLOT_COUNT 256/*16*/ +#define OBJECT_SLOT(id) \ + elm_tls->gContext.object_slots[id % SLOT_COUNT] + + /* + VGLite releated configurations. + */ +#define TS_WIDTH 64 +#define TS_HEIGHT 64 +#define RTOS 1 +#define APP_BUFFER_COUNT 2 +#if (RTOS && DDRLESS) || BAREMETAL +#define OBJCOUNT_GRAD 16 +#define OBJCOUNT_EVO 128 +#define OBJCOUNT_EBO 64 +#define OBJCOUNT_GROUP 16 +#endif + +#if RTOS +#include "FreeRTOS.h" + +#define elm_alloc(num_objects,object_size) pvPortMalloc(num_objects * object_size) +#define elm_free vPortFree +#else +#define elm_alloc calloc +#define elm_free free +#endif + +typedef enum { + ELEMENT_LINEARGRADIENT = 0, /*! linear gradient element */ + ELEMENT_PATH = 1, /*! path element */ + ELEMENT_GROUP = 2, /*! group element */ + ELEMENT_TEXT = 3, /*! text element */ + ELEMENT_TSPAN = 4, /*! tspan element */ + ELEMENT_FONT = 5, /*! font element */ + ELEMENT_TTF_FONT = 6, /*! ttf-type font */ + ELEMENT_VECTOR_FONT = 7, /*! vector fonts */ + ELEMENT_TEXT_FONT = 8, /*! text fonts */ +} ELM_ELEMENT_TYPE; + +#define COUNT_OF(array) (sizeof(array) / sizeof(array[0])) + /* + System definitions. + */ +#define DEBUG_ASSERT(a, message) \ + if (!a) \ + printf("%s: ASSERT failed @ %s, %d.\n", message, __FILE__, __LINE__) + + /*! + @typedef el_Object + common object type definition shared by all EVO object to identify its handle, + object type, and ELM version info. + for reference purpose, handle = 0 is reserved. + */ + typedef struct { + ElmHandle handle; + ELM_OBJECT_TYPE type; + unsigned int reference; // Reference count by other objects. +#if (RTOS && DDRLESS) || BAREMETAL + int index; /* The index of the object in pool. */ +#endif + } el_Object; + + /*! + @typedef el_Transform + The transformation attribute for an EVO/EBO/Group object. + */ + typedef struct { + float rotate; + float translate[2]; + float scale[2]; + BOOL dirty; + BOOL identity; + vg_lite_matrix_t matrix; + } el_Transform; + + /*! + @typedef el_GradData + Linear gradient definition. + !grad the native vg_lite gradient data; + !gransform the grad's transformation. matrix is synced to grad's. + */ + typedef struct { + vg_lite_linear_gradient_t grad; + el_Transform transform; + } el_GradData; + + /*! + @typedef el_RadgradData + Radial gradient definition. + !rad_grad the native vg_lite_radial_gradient data; + !gransform the grad's transformation. matrix is synced to grad's. + */ + typedef struct { + vg_lite_radial_gradient_t rad_grad; + el_Transform transform; + } el_RadgradData; + + /*! + @typedef el_Obj_Grad + The linear gradient object definition. + */ + typedef struct { + el_Object object; + el_GradData data; + } el_Obj_Grad; + + /*! + @typedef el_Obj_Radgrad + The radial gradient object definition. + */ + typedef struct { + el_Object object; + el_RadgradData data; + } el_Obj_Radgrad; + + /*! + @typedef el_Obj_Pattern + The pattern paint object definition. + pattern: it should be an pointer to an el_Obj_EVO; + mode: the pattern fill mode. + color: the color value if pattern mode is COLOR + */ + typedef struct { + void *pattern; + ELM_PATTERN_MODE mode; + uint32_t color; + } el_Obj_Pattern; + + /*! + @typedef el_Paint + The paint object definition. + color: for solid fill; + grad: for linear gradient fill; + pattern: for image fill. + */ + typedef struct { + ELM_PAINT_TYPE type; + uint32_t color; + el_Obj_Grad * grad; + el_Obj_Radgrad * radgrad; + el_Obj_Pattern pattern; + } el_Paint; + + /*! + @typedef el_Attribute + The rendering attribute definition. + */ + typedef struct { + ELM_QUALITY quality; + ELM_BLEND blend; + ELM_EVO_FILL fill_rule; + el_Paint paint; + el_Transform transform; + } el_Attribute; + + /*! + @typedef el_EVOData + The data definition for EVO (vector object). + */ + typedef struct { + vg_lite_path_t path; + } el_EVOData; + + /*! + @typedef el_Obj_EVO + EVO (Elementry Vector Object) type definition. + */ + typedef struct { + el_Object object; + el_Attribute attribute; + el_Attribute defaultAttrib; + el_EVOData data; + uint32_t has_pattern; + uint32_t is_pattern; + uint32_t is_image; + char eboname[20]; + uint32_t img_width; + uint32_t img_height; + } el_Obj_EVO; + + /*! + @typedef el_EBOData + The data definition for EBO (bitmap object). + */ + typedef struct { + vg_lite_buffer_t buffer; + } el_EBOData; + + /*! + @typedef el_Obj_EBO + EBO (Elementry Buffer Object) type definition. + */ + typedef struct { + el_Object object; + el_Attribute attribute; + el_Attribute defaultAttrib; + el_EBOData data; + uint32_t clut_count; + uint32_t clut[256]; + } el_Obj_EBO; + + /*! + @typedef el_GroupData + The group object data definition. + */ + typedef struct { + unsigned int count; + el_Obj_EVO * objects; + } el_GroupData; + + /*! + @typedef el_Obj_Group + Group object type definition. + */ + typedef struct { + el_Object object; + el_Transform transform; + el_Transform defaultTrans; + el_GroupData group; + } el_Obj_Group; + + /*! + @typedef el_Obj_Buffer + The render buffer object definition. + */ + typedef struct { + el_Object object; + vg_lite_buffer_t buffer; + } el_Obj_Buffer; + + /*! + @typedef el_ObjList + List to organize objects. + */ + typedef struct _object_list{ + el_Object *object; + struct _object_list *next; + } el_ObjList; + + /*! + @typedef ElmRenderBuffer + The ElmRenderBuffer definition. + */ + typedef struct elm_render_buffer { + ElmBuffer handle; + vg_lite_buffer_t *buffer; + } ElmRenderBuffer; + + /*! + @typedef el_Context + The context object for global data management. + !version UXDK version + !currentHandle The current handle for new object + !objectCount Count of all objects + !object_slots List array to manage objects + */ + typedef struct { + uint32_t version; + int reference; + ElmHandle currentHandle; + unsigned int objectCount; + el_ObjList *object_slots[SLOT_COUNT]; + ElmRenderBuffer elmFB[APP_BUFFER_COUNT]; + /* VGLite related states. */ + uint32_t tessellation_width; + uint32_t tessellation_height; + + /* The current vector index (within a group). */ + int32_t vector_id; + +#if (RTOS && DDRLESS) || BAREMETAL + /* Static object pools. */ + el_Obj_Grad objpool_grad[OBJCOUNT_GRAD]; + el_Obj_EVO objpool_evo[OBJCOUNT_EVO]; + el_Obj_EBO objpool_ebo[OBJCOUNT_EBO]; + el_Obj_Group objpool_group[OBJCOUNT_GROUP]; + + /* The allocation map table. + * Each bit in the element maps to the usage of the object. + * 0 means free, 1 means allocated. + * The mapping order is 01234567...31 (hi -> low) in big endian systems. + * */ + int32_t objmap_grad[(OBJCOUNT_GRAD + 31) / 32]; + int32_t objmap_evo[(OBJCOUNT_EVO + 31) / 32]; + int32_t objmap_ebo[(OBJCOUNT_EBO + 31) / 32]; + int32_t objmap_group[(OBJCOUNT_GROUP + 31) / 32]; + + int objcounter_grad; + int objcounter_evo; + int objcounter_ebo; + int objcounter_group; +#endif + } el_Context; + + /*! + @typedef elm_tls_t + The elm_tls_t definition. + */ + typedef struct vglite_elm_tls { + el_Context gContext; + } elm_tls_t; + + /* + API function prototypes. + */ + int add_object (el_Object *object); + int remove_object (el_Object *object); + el_Object *get_object (ElmHandle handle); + +#ifdef __cplusplus +} +#endif +#endif /* VELM_H_ */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/buf_reader.c b/bsp/sdk_overlay/middleware/vglite/font/buf_reader.c similarity index 95% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/buf_reader.c rename to bsp/sdk_overlay/middleware/vglite/font/buf_reader.c index 110bf22..5eeaaf4 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/buf_reader.c +++ b/bsp/sdk_overlay/middleware/vglite/font/buf_reader.c @@ -1,221 +1,221 @@ -/**************************************************************************** -* -* The MIT License (MIT) -* -* Copyright 2020 NXP -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ -#include "buf_reader.h" -#include "stdio.h" -#include "string.h" - -#define DBG_TRACE(x) printf x - -static int _is_buffered_handle_valid(bufferred_reader_t *fd) -{ - if (fd == NULL) - return E_BUF_INVALID_HANDLE; - if ( fd->data_buf == NULL ) - return E_BUF_INVALID_HANDLE; - if ( fd->size < 0 ) - return E_BUF_INVALID_HANDLE; - if ( fd->index > fd->size ) - return E_BUF_INVALID_HANDLE; - - return 0; -} - -/* Write buffered IO operations */ -int bufferred_fopen(bufferred_reader_t *fd, char *buf, int size) -{ - if (fd == NULL) - return E_BUF_INVALID_HANDLE; - - fd->data_buf = buf; - fd->size = size; - fd->index = 0; - - if ( _is_buffered_handle_valid(fd)) { - return E_BUF_INVALID_HANDLE; - } - - fd->is_valid = 1; - - return 0; -} - -int bufferred_ftell(bufferred_reader_t *fd) -{ - if ( _is_buffered_handle_valid(fd)) { - return E_BUF_INVALID_HANDLE; - } - - return fd->index; -} - -int bufferred_fread( - void *ptr, - int size, - int nmemb, - bufferred_reader_t *fd -) -{ - int to_copy = 0; - char *data_ptr = NULL; - char *buff = (char *)ptr; - int byte_to_read = size * nmemb; - - if ( _is_buffered_handle_valid(fd)) { - return E_BUF_INVALID_HANDLE; - } - - if ( buff == NULL ) { - return E_BUF_IO_INVALID_PARAMETERS; - } - - if ( byte_to_read < 0 ) { - return E_BUF_IO_INVALID_PARAMETERS; - } - - to_copy = (fd->size - fd->index); - data_ptr = fd->data_buf + fd->index; - - if ( to_copy > byte_to_read ) - to_copy = byte_to_read; - - if (to_copy <= 0) - return -1; //EOF - - memcpy(buff, data_ptr, to_copy); - - fd->index += to_copy; - - return 0; -} - -int bufferred_fseek( - bufferred_reader_t *fd, - int offset, - int direction -) -{ - if ( _is_buffered_handle_valid(fd)) { - return E_BUF_INVALID_HANDLE; - } - - switch(direction) - { - case SEEK_SET: - fd->index = offset; - break; - case SEEK_CUR: - fd->index += offset; - break; - case SEEK_END: - fd->index = fd->size - offset; - break; - } - - /* Clamp current offset */ - if ( fd->index > fd->size ) { - DBG_TRACE(("WARNING: seeking beyond buffer size\n")); - fd->index = fd->size; - } - if ( fd->index < 0 ) { - DBG_TRACE(("WARNING: seeking beyond buffer size\n")); - fd->index = 0; - } - - return 0; -} - -int bufferred_fclose(bufferred_reader_t *fd) -{ - if ( _is_buffered_handle_valid(fd)) { - return E_BUF_INVALID_HANDLE; - } - - fd->size = -1; - fd->is_valid = 0; - - return 0; -} - -char *bufferred_fgets(char* buff, int len, bufferred_reader_t *fd) -{ - char *ptr; - int i, j, valid_bytes; - - if ( buff == NULL ) { - return NULL; - } - - if ( len <= 0 ) { - return NULL; - } - - if ( _is_buffered_handle_valid(fd)) { - return NULL; - } - - /* Check how many bytes are available to read */ - valid_bytes = fd->size - fd->index; - if ( len > 0 ) - len -=1; /* fgets read one character less than buffer length */ - if ( len > valid_bytes ) - len = valid_bytes; - - if ( valid_bytes <= 0 ) - return NULL; - - ptr = fd->data_buf + fd->index; - for(i=0; ptr[i] != '\0' && i < len; i++) - { - if ( ptr[i] == '\n' ) - break; - if ( ptr[i] == '\r' ) - break; - buff[i] = ptr[i]; - } - buff[i] = '\0'; - j = i; - /* skip trailing newline from file buffer */ - if ( ptr[i] == '\r' ) - i++; - if ( ptr[i] == '\n' ) - i++; - fd->index += i; - - /* Trim trailing spaces from output buffer */ - for (i = j-1 ; i>0; i--) { - if (buff[i] == ' ') - buff[i] = '\0'; - else - break; - } - - - return ptr; - -} +/**************************************************************************** +* +* The MIT License (MIT) +* +* Copyright 2020 NXP +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ +#include "buf_reader.h" +#include "stdio.h" +#include "string.h" + +#define DBG_TRACE(x) printf x + +static int _is_buffered_handle_valid(bufferred_reader_t *fd) +{ + if (fd == NULL) + return E_BUF_INVALID_HANDLE; + if ( fd->data_buf == NULL ) + return E_BUF_INVALID_HANDLE; + if ( fd->size < 0 ) + return E_BUF_INVALID_HANDLE; + if ( fd->index > fd->size ) + return E_BUF_INVALID_HANDLE; + + return 0; +} + +/* Write buffered IO operations */ +int bufferred_fopen(bufferred_reader_t *fd, char *buf, int size) +{ + if (fd == NULL) + return E_BUF_INVALID_HANDLE; + + fd->data_buf = buf; + fd->size = size; + fd->index = 0; + + if ( _is_buffered_handle_valid(fd)) { + return E_BUF_INVALID_HANDLE; + } + + fd->is_valid = 1; + + return 0; +} + +int bufferred_ftell(bufferred_reader_t *fd) +{ + if ( _is_buffered_handle_valid(fd)) { + return E_BUF_INVALID_HANDLE; + } + + return fd->index; +} + +int bufferred_fread( + void *ptr, + int size, + int nmemb, + bufferred_reader_t *fd +) +{ + int to_copy = 0; + char *data_ptr = NULL; + char *buff = (char *)ptr; + int byte_to_read = size * nmemb; + + if ( _is_buffered_handle_valid(fd)) { + return E_BUF_INVALID_HANDLE; + } + + if ( buff == NULL ) { + return E_BUF_IO_INVALID_PARAMETERS; + } + + if ( byte_to_read < 0 ) { + return E_BUF_IO_INVALID_PARAMETERS; + } + + to_copy = (fd->size - fd->index); + data_ptr = fd->data_buf + fd->index; + + if ( to_copy > byte_to_read ) + to_copy = byte_to_read; + + if (to_copy <= 0) + return -1; //EOF + + memcpy(buff, data_ptr, to_copy); + + fd->index += to_copy; + + return 0; +} + +int bufferred_fseek( + bufferred_reader_t *fd, + int offset, + int direction +) +{ + if ( _is_buffered_handle_valid(fd)) { + return E_BUF_INVALID_HANDLE; + } + + switch(direction) + { + case SEEK_SET: + fd->index = offset; + break; + case SEEK_CUR: + fd->index += offset; + break; + case SEEK_END: + fd->index = fd->size - offset; + break; + } + + /* Clamp current offset */ + if ( fd->index > fd->size ) { + DBG_TRACE(("WARNING: seeking beyond buffer size\n")); + fd->index = fd->size; + } + if ( fd->index < 0 ) { + DBG_TRACE(("WARNING: seeking beyond buffer size\n")); + fd->index = 0; + } + + return 0; +} + +int bufferred_fclose(bufferred_reader_t *fd) +{ + if ( _is_buffered_handle_valid(fd)) { + return E_BUF_INVALID_HANDLE; + } + + fd->size = -1; + fd->is_valid = 0; + + return 0; +} + +char *bufferred_fgets(char* buff, int len, bufferred_reader_t *fd) +{ + char *ptr; + int i, j, valid_bytes; + + if ( buff == NULL ) { + return NULL; + } + + if ( len <= 0 ) { + return NULL; + } + + if ( _is_buffered_handle_valid(fd)) { + return NULL; + } + + /* Check how many bytes are available to read */ + valid_bytes = fd->size - fd->index; + if ( len > 0 ) + len -=1; /* fgets read one character less than buffer length */ + if ( len > valid_bytes ) + len = valid_bytes; + + if ( valid_bytes <= 0 ) + return NULL; + + ptr = fd->data_buf + fd->index; + for(i=0; ptr[i] != '\0' && i < len; i++) + { + if ( ptr[i] == '\n' ) + break; + if ( ptr[i] == '\r' ) + break; + buff[i] = ptr[i]; + } + buff[i] = '\0'; + j = i; + /* skip trailing newline from file buffer */ + if ( ptr[i] == '\r' ) + i++; + if ( ptr[i] == '\n' ) + i++; + fd->index += i; + + /* Trim trailing spaces from output buffer */ + for (i = j-1 ; i>0; i--) { + if (buff[i] == ' ') + buff[i] = '\0'; + else + break; + } + + + return ptr; + +} diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/buf_reader.h b/bsp/sdk_overlay/middleware/vglite/font/buf_reader.h similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/buf_reader.h rename to bsp/sdk_overlay/middleware/vglite/font/buf_reader.h index 2e8756f..9b85035 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/buf_reader.h +++ b/bsp/sdk_overlay/middleware/vglite/font/buf_reader.h @@ -1,63 +1,63 @@ -/**************************************************************************** -* -* The MIT License (MIT) -* -* Copyright 2020 NXP -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -/* Bufferred reader interface */ -#ifndef _BUFFERRED_READER_ -#define _BUFFERRED_READER_ - -typedef struct buffered_reader { - char *data_buf; - int size; - int index; - int is_valid; -} bufferred_reader_t; - -#define E_BUF_IO_OUT_OF_MEMORY -10 -#define E_BUF_IO_READ_ERROR -11 -#define E_BUF_INVALID_HANDLE -12 -#define E_BUF_IO_INVALID_PARAMETERS -13 - -int is_buffered_handle_valid(bufferred_reader_t *fd); -int bufferred_fopen(bufferred_reader_t *fd, char *buf, int size); -int bufferred_ftell(bufferred_reader_t *fd); -int bufferred_fread( - void *ptr, - int size, - int nmemb, - bufferred_reader_t *fd -); -int bufferred_fseek( - bufferred_reader_t *fd, - int offset, - int direction -); -int bufferred_fclose(bufferred_reader_t *fd); -char *bufferred_fgets(char* buff, int len, bufferred_reader_t *fd); - +/**************************************************************************** +* +* The MIT License (MIT) +* +* Copyright 2020 NXP +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +/* Bufferred reader interface */ +#ifndef _BUFFERRED_READER_ +#define _BUFFERRED_READER_ + +typedef struct buffered_reader { + char *data_buf; + int size; + int index; + int is_valid; +} bufferred_reader_t; + +#define E_BUF_IO_OUT_OF_MEMORY -10 +#define E_BUF_IO_READ_ERROR -11 +#define E_BUF_INVALID_HANDLE -12 +#define E_BUF_IO_INVALID_PARAMETERS -13 + +int is_buffered_handle_valid(bufferred_reader_t *fd); +int bufferred_fopen(bufferred_reader_t *fd, char *buf, int size); +int bufferred_ftell(bufferred_reader_t *fd); +int bufferred_fread( + void *ptr, + int size, + int nmemb, + bufferred_reader_t *fd +); +int bufferred_fseek( + bufferred_reader_t *fd, + int offset, + int direction +); +int bufferred_fclose(bufferred_reader_t *fd); +char *bufferred_fgets(char* buff, int len, bufferred_reader_t *fd); + #endif //!_BUFFERRED_READER_ \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/fonts.h b/bsp/sdk_overlay/middleware/vglite/font/fonts.h similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/fonts.h rename to bsp/sdk_overlay/middleware/vglite/font/fonts.h index 40ebe27..d260789 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/fonts.h +++ b/bsp/sdk_overlay/middleware/vglite/font/fonts.h @@ -1,30 +1,30 @@ -/**************************************************************************** -* -* The MIT License (MIT) -* -* Copyright 2020 NXP -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -#define ABS_ARY(x) (void *)x, sizeof(x), 0 +/**************************************************************************** +* +* The MIT License (MIT) +* +* Copyright 2020 NXP +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +#define ABS_ARY(x) (void *)x, sizeof(x), 0 diff --git a/bsp/sdk_overlay/middleware/vglite/font/mcufont/LICENSE b/bsp/sdk_overlay/middleware/vglite/font/mcufont/LICENSE new file mode 100644 index 0000000..b67f3cf --- /dev/null +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/LICENSE @@ -0,0 +1,31 @@ +mcufont is available under the MIT license: + +Copyright (C) 2013 Petteri Aimonen + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice shall be +included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +--- + +In addition, the files under the "decoder" folder and all font files +generated by the encoder are placed in the public domain. You can do +anything with them without any restriction from me. + +Note that the licenses of the fonts you import may pose additional +restrictions. diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mcufont.h b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mcufont.h similarity index 95% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mcufont.h rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mcufont.h index 8a81ff4..e02733b 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mcufont.h +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mcufont.h @@ -1,14 +1,14 @@ -/* Tiny library for rendering compressed bitmap fonts on microcontrollers. */ - -#ifndef _MCUFONT_H_ -#define _MCUFONT_H_ - -#include "mf_config.h" -#include "mf_encoding.h" -#include "mf_justify.h" -#include "mf_kerning.h" -#include "mf_rlefont.h" -#include "mf_scaledfont.h" -#include "mf_wordwrap.h" - -#endif +/* Tiny library for rendering compressed bitmap fonts on microcontrollers. */ + +#ifndef _MCUFONT_H_ +#define _MCUFONT_H_ + +#include "mf_config.h" +#include "mf_encoding.h" +#include "mf_justify.h" +#include "mf_kerning.h" +#include "mf_rlefont.h" +#include "mf_scaledfont.h" +#include "mf_wordwrap.h" + +#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_bwfont.c b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_bwfont.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_bwfont.c rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_bwfont.c index a7b6530..20ab35b 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_bwfont.c +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_bwfont.c @@ -1,134 +1,134 @@ -#include "mf_bwfont.h" -#include - -/* Find the character range and index that contains a given glyph.. */ -static const struct mf_bwfont_char_range_s *find_char_range( - const struct mf_bwfont_s *font, uint16_t character, uint16_t *index_ret) -{ - unsigned i, index; - const struct mf_bwfont_char_range_s *range; - for (i = 0; i < font->char_range_count; i++) - { - range = &font->char_ranges[i]; - index = character - range->first_char; - if (character >= range->first_char && index < range->char_count) - { - *index_ret = index; - return range; - } - } - - return 0; -} - -static uint8_t get_width(const struct mf_bwfont_char_range_s *r, uint16_t index) -{ - if (r->width) - { - return r->width + r->offset_x; - } - else - { - return r->glyph_widths[index]; - } -} - -static uint8_t render_char(const struct mf_bwfont_char_range_s *r, - int16_t x0, int16_t y0, uint16_t index, - mf_pixel_callback_t callback, - void *state) -{ - const uint8_t *data, *p; - uint8_t stride, runlen; - uint8_t x, y, height, num_cols; - uint8_t bit, byte, mask; - bool oldstate, newstate; - - if (r->width) - { - data = r->glyph_data + r->width * index * r->height_bytes; - num_cols = r->width; - } - else - { - data = r->glyph_data + r->glyph_offsets[index] * r->height_bytes; - num_cols = r->glyph_offsets[index + 1] - r->glyph_offsets[index]; - } - - stride = r->height_bytes; - height = r->height_pixels; - y0 += r->offset_y; - x0 += r->offset_x; - bit = 0; - byte = 0; - - for (y = 0; y < height; y++) - { - mask = (1 << bit); - - oldstate = false; - runlen = 0; - p = data + byte; - for (x = 0; x < num_cols; x++, p += stride) - { - newstate = pgm_read_byte(p) & mask; - if (newstate != oldstate) - { - if (oldstate && runlen) - { - callback(x0 + x - runlen, y0 + y, runlen, 255, state); - } - - oldstate = newstate; - runlen = 0; - } - - runlen++; - } - - if (oldstate && runlen) - { - callback(x0 + x - runlen, y0 + y, runlen, 255, state); - } - - bit++; - if (bit > 7) - { - bit = 0; - byte++; - } - } - - return get_width(r, index); -} - -uint8_t mf_bwfont_render_character(const struct mf_font_s *font, - int16_t x0, int16_t y0, - uint16_t character, - mf_pixel_callback_t callback, - void *state) -{ - const struct mf_bwfont_s *bwfont = (const struct mf_bwfont_s*)font; - const struct mf_bwfont_char_range_s *range; - uint16_t index; - - range = find_char_range(bwfont, character, &index); - if (!range) - return 0; - - return render_char(range, x0, y0, index, callback, state); -} - -uint8_t mf_bwfont_character_width(const struct mf_font_s *font, - uint16_t character) -{ - const struct mf_bwfont_s *bwfont = (const struct mf_bwfont_s*)font; - const struct mf_bwfont_char_range_s *range; - uint16_t index; - - range = find_char_range(bwfont, character, &index); - if (!range) - return 0; - - return get_width(range, index); -} +#include "mf_bwfont.h" +#include + +/* Find the character range and index that contains a given glyph.. */ +static const struct mf_bwfont_char_range_s *find_char_range( + const struct mf_bwfont_s *font, uint16_t character, uint16_t *index_ret) +{ + unsigned i, index; + const struct mf_bwfont_char_range_s *range; + for (i = 0; i < font->char_range_count; i++) + { + range = &font->char_ranges[i]; + index = character - range->first_char; + if (character >= range->first_char && index < range->char_count) + { + *index_ret = index; + return range; + } + } + + return 0; +} + +static uint8_t get_width(const struct mf_bwfont_char_range_s *r, uint16_t index) +{ + if (r->width) + { + return r->width + r->offset_x; + } + else + { + return r->glyph_widths[index]; + } +} + +static uint8_t render_char(const struct mf_bwfont_char_range_s *r, + int16_t x0, int16_t y0, uint16_t index, + mf_pixel_callback_t callback, + void *state) +{ + const uint8_t *data, *p; + uint8_t stride, runlen; + uint8_t x, y, height, num_cols; + uint8_t bit, byte, mask; + bool oldstate, newstate; + + if (r->width) + { + data = r->glyph_data + r->width * index * r->height_bytes; + num_cols = r->width; + } + else + { + data = r->glyph_data + r->glyph_offsets[index] * r->height_bytes; + num_cols = r->glyph_offsets[index + 1] - r->glyph_offsets[index]; + } + + stride = r->height_bytes; + height = r->height_pixels; + y0 += r->offset_y; + x0 += r->offset_x; + bit = 0; + byte = 0; + + for (y = 0; y < height; y++) + { + mask = (1 << bit); + + oldstate = false; + runlen = 0; + p = data + byte; + for (x = 0; x < num_cols; x++, p += stride) + { + newstate = pgm_read_byte(p) & mask; + if (newstate != oldstate) + { + if (oldstate && runlen) + { + callback(x0 + x - runlen, y0 + y, runlen, 255, state); + } + + oldstate = newstate; + runlen = 0; + } + + runlen++; + } + + if (oldstate && runlen) + { + callback(x0 + x - runlen, y0 + y, runlen, 255, state); + } + + bit++; + if (bit > 7) + { + bit = 0; + byte++; + } + } + + return get_width(r, index); +} + +uint8_t mf_bwfont_render_character(const struct mf_font_s *font, + int16_t x0, int16_t y0, + uint16_t character, + mf_pixel_callback_t callback, + void *state) +{ + const struct mf_bwfont_s *bwfont = (const struct mf_bwfont_s*)font; + const struct mf_bwfont_char_range_s *range; + uint16_t index; + + range = find_char_range(bwfont, character, &index); + if (!range) + return 0; + + return render_char(range, x0, y0, index, callback, state); +} + +uint8_t mf_bwfont_character_width(const struct mf_font_s *font, + uint16_t character) +{ + const struct mf_bwfont_s *bwfont = (const struct mf_bwfont_s*)font; + const struct mf_bwfont_char_range_s *range; + uint16_t index; + + range = find_char_range(bwfont, character, &index); + if (!range) + return 0; + + return get_width(range, index); +} diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_bwfont.h b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_bwfont.h similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_bwfont.h rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_bwfont.h index aadcbf2..1863a76 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_bwfont.h +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_bwfont.h @@ -1,77 +1,77 @@ -/* Uncompressed font format for storing black & white fonts. Very efficient - * to decode and works well for small font sizes. - */ - -#ifndef _MF_BWFONT_H_ -#define _MF_BWFONT_H_ - -#include "mf_font.h" - -/* Versions of the BW font format that are supported. */ -#define MF_BWFONT_VERSION_4_SUPPORTED 1 - -/* Structure for a range of characters. */ -struct mf_bwfont_char_range_s -{ - /* The number of the first character in this range. */ - uint16_t first_char; - - /* The total count of characters in this range. */ - uint16_t char_count; - - /* The left and top skips of the characters in this range. - * This is the number of empty rows at left and at top. */ - uint8_t offset_x; - uint8_t offset_y; - - /* Column height for glyphs in this range, in bytes and pixels. */ - uint8_t height_bytes; - uint8_t height_pixels; - - /* Positive value if the width of all glyphs in this range is the - * same, or zero if it is not. */ - uint8_t width; - - /* Lookup table for the character widths. NULL if width is specified. */ - uint8_t *glyph_widths; - - /* Lookup table for the character offsets. Multiply by height_bytes - * to get the byte offset. Also allows lookup of the number of columns. - * NULL if width is specified. */ - uint16_t *glyph_offsets; - - /* Table for the glyph data. - * The data for each glyph is column-by-column, with N bytes per each - * column. The LSB of the first byte is the top left pixel. - */ - uint8_t *glyph_data; -}; - -/* Structure for the font */ -struct mf_bwfont_s -{ - struct mf_font_s font; - - /* Version of the font format. */ - uint8_t version; - - /* Number of character ranges. */ - uint8_t char_range_count; - - /* Array of the character ranges */ - struct mf_bwfont_char_range_s *char_ranges; -}; - -#ifdef MF_BWFONT_INTERNALS -/* Internal functions, don't use these directly. */ -MF_EXTERN uint8_t mf_bwfont_render_character(const struct mf_font_s *font, - int16_t x0, int16_t y0, - mf_char character, - mf_pixel_callback_t callback, - void *state); - -MF_EXTERN uint8_t mf_bwfont_character_width(const struct mf_font_s *font, - mf_char character); -#endif - -#endif +/* Uncompressed font format for storing black & white fonts. Very efficient + * to decode and works well for small font sizes. + */ + +#ifndef _MF_BWFONT_H_ +#define _MF_BWFONT_H_ + +#include "mf_font.h" + +/* Versions of the BW font format that are supported. */ +#define MF_BWFONT_VERSION_4_SUPPORTED 1 + +/* Structure for a range of characters. */ +struct mf_bwfont_char_range_s +{ + /* The number of the first character in this range. */ + uint16_t first_char; + + /* The total count of characters in this range. */ + uint16_t char_count; + + /* The left and top skips of the characters in this range. + * This is the number of empty rows at left and at top. */ + uint8_t offset_x; + uint8_t offset_y; + + /* Column height for glyphs in this range, in bytes and pixels. */ + uint8_t height_bytes; + uint8_t height_pixels; + + /* Positive value if the width of all glyphs in this range is the + * same, or zero if it is not. */ + uint8_t width; + + /* Lookup table for the character widths. NULL if width is specified. */ + uint8_t *glyph_widths; + + /* Lookup table for the character offsets. Multiply by height_bytes + * to get the byte offset. Also allows lookup of the number of columns. + * NULL if width is specified. */ + uint16_t *glyph_offsets; + + /* Table for the glyph data. + * The data for each glyph is column-by-column, with N bytes per each + * column. The LSB of the first byte is the top left pixel. + */ + uint8_t *glyph_data; +}; + +/* Structure for the font */ +struct mf_bwfont_s +{ + struct mf_font_s font; + + /* Version of the font format. */ + uint8_t version; + + /* Number of character ranges. */ + uint8_t char_range_count; + + /* Array of the character ranges */ + struct mf_bwfont_char_range_s *char_ranges; +}; + +#ifdef MF_BWFONT_INTERNALS +/* Internal functions, don't use these directly. */ +MF_EXTERN uint8_t mf_bwfont_render_character(const struct mf_font_s *font, + int16_t x0, int16_t y0, + mf_char character, + mf_pixel_callback_t callback, + void *state); + +MF_EXTERN uint8_t mf_bwfont_character_width(const struct mf_font_s *font, + mf_char character); +#endif + +#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_config.h b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_config.h similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_config.h rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_config.h index 492dcd4..f8a2d39 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_config.h +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_config.h @@ -1,144 +1,144 @@ -/* Configuration constants for mcufont. */ - -#ifndef _MF_CONFIG_H_ -#define _MF_CONFIG_H_ - -#ifdef __AVR__ - #include -#elif defined(ARDUINO_ARCH_ESP8266) || defined(ARDUINO_ARCH_ESP32) - #include -#else - #include - #define PROGMEM - #define pgm_read_byte(addr) (*(const unsigned char *)(addr)) - #define pgm_read_word(addr) (*(const uint16_t *)(addr)) -#endif /* __AVR__ */ - - -/******************************************************* - * Configuration settings related to build environment * - *******************************************************/ - -/* Name of the file that contains all the included fonts. */ -#ifndef MF_FONT_FILE_NAME -#define MF_FONT_FILE_NAME "fonts.h" -#endif - - -/***************************************** - * Configuration settings related to API * - *****************************************/ - -/* Encoding for the input data. - * With the unicode encodings, the library supports the range of unicode - * characters 0x0000-0xFFFF (the Basic Multilingual Plane). - * - * ASCII: Plain ascii (somewhat works with ISO8859-1 also) - * UTF8: UTF8 encoding (variable number of bytes) - * UTF16: UTF16 encoding (2 bytes per character, compatible with UCS-2) - * WCHAR: Use compiler's wchar_t (usually same as UTF16) - */ -#define MF_ENCODING_ASCII 0 -#define MF_ENCODING_UTF8 1 -#define MF_ENCODING_UTF16 2 -#define MF_ENCODING_WCHAR 3 -#ifndef MF_ENCODING -#define MF_ENCODING MF_ENCODING_UTF8 -#endif - - -/************************************************************************ - * Configuration settings related to visual appearance of rendered text * - ************************************************************************/ - -/* Minimum space between characters, in percents of the glyph width. - * Increasing this causes the kerning module to leave more space between - * characters. - */ -#ifndef MF_KERNING_SPACE_PERCENT -#define MF_KERNING_SPACE_PERCENT 15 -#endif - -/* Minimum space between characters, in pixels. Added to the percentual - * spacing. This pixel-based value guarantees enough space even with small - * fonts. - */ -#ifndef MF_KERNING_SPACE_PIXELS -#define MF_KERNING_SPACE_PIXELS 3 -#endif - -/* Maximum adjustment done by the kerning algorithm, as percent of the - * glyph width. - */ -#ifndef MF_KERNING_LIMIT -#define MF_KERNING_LIMIT 20 -#endif - -/* Spacing of tabulator stops. The value is multiplied by the width of the - * 'm' character in the current font. - */ -#ifndef MF_TABSIZE -#define MF_TABSIZE 8 -#endif - - -/************************************************************************* - * Configuration settings to strip down library to reduce resource usage * - *************************************************************************/ - -/* Enable or disable the kerning module. - * Disabling it saves some code size and run time, but causes the spacing - * between characters to be less consistent. - */ -#ifndef MF_USE_KERNING -#define MF_USE_KERNING 1 -#endif - -/* Enable or disable the advanced word wrap algorithm. - * If disabled, uses a simpler algorithm. - */ -#ifndef MF_USE_ADVANCED_WORDWRAP -#define MF_USE_ADVANCED_WORDWRAP 1 -#endif - -/* Enable of disable the justification algorithm. - * If disabled, mf_render_justified renders just left-aligned. - */ -#ifndef MF_USE_JUSTIFY -#define MF_USE_JUSTIFY 1 -#endif - -/* Enable or disable the center and right alignment code. - * If disabled, any alignment results in MF_ALIGN_LEFT. - */ -#ifndef MF_USE_ALIGN -#define MF_USE_ALIGN 1 -#endif - -/* Enable or disable the support for tab alignment. - * If disabled, tabs will be rendered as regular space character. - */ -#ifndef MF_USE_TABS -#define MF_USE_TABS 1 -#endif - -/* Number of vertical zones to use when computing kerning. - * Larger values give more accurate kerning, but are slower and use somewhat - * more memory. There is no point to increase this beyond the height of the - * font. - */ -#ifndef MF_KERNING_ZONES -#define MF_KERNING_ZONES 16 -#endif - - - -/* Add extern "C" when used from C++. */ -#ifdef __cplusplus -#define MF_EXTERN extern "C" -#else -#define MF_EXTERN extern -#endif - -#endif - +/* Configuration constants for mcufont. */ + +#ifndef _MF_CONFIG_H_ +#define _MF_CONFIG_H_ + +#ifdef __AVR__ + #include +#elif defined(ARDUINO_ARCH_ESP8266) || defined(ARDUINO_ARCH_ESP32) + #include +#else + #include + #define PROGMEM + #define pgm_read_byte(addr) (*(const unsigned char *)(addr)) + #define pgm_read_word(addr) (*(const uint16_t *)(addr)) +#endif /* __AVR__ */ + + +/******************************************************* + * Configuration settings related to build environment * + *******************************************************/ + +/* Name of the file that contains all the included fonts. */ +#ifndef MF_FONT_FILE_NAME +#define MF_FONT_FILE_NAME "fonts.h" +#endif + + +/***************************************** + * Configuration settings related to API * + *****************************************/ + +/* Encoding for the input data. + * With the unicode encodings, the library supports the range of unicode + * characters 0x0000-0xFFFF (the Basic Multilingual Plane). + * + * ASCII: Plain ascii (somewhat works with ISO8859-1 also) + * UTF8: UTF8 encoding (variable number of bytes) + * UTF16: UTF16 encoding (2 bytes per character, compatible with UCS-2) + * WCHAR: Use compiler's wchar_t (usually same as UTF16) + */ +#define MF_ENCODING_ASCII 0 +#define MF_ENCODING_UTF8 1 +#define MF_ENCODING_UTF16 2 +#define MF_ENCODING_WCHAR 3 +#ifndef MF_ENCODING +#define MF_ENCODING MF_ENCODING_UTF8 +#endif + + +/************************************************************************ + * Configuration settings related to visual appearance of rendered text * + ************************************************************************/ + +/* Minimum space between characters, in percents of the glyph width. + * Increasing this causes the kerning module to leave more space between + * characters. + */ +#ifndef MF_KERNING_SPACE_PERCENT +#define MF_KERNING_SPACE_PERCENT 15 +#endif + +/* Minimum space between characters, in pixels. Added to the percentual + * spacing. This pixel-based value guarantees enough space even with small + * fonts. + */ +#ifndef MF_KERNING_SPACE_PIXELS +#define MF_KERNING_SPACE_PIXELS 3 +#endif + +/* Maximum adjustment done by the kerning algorithm, as percent of the + * glyph width. + */ +#ifndef MF_KERNING_LIMIT +#define MF_KERNING_LIMIT 20 +#endif + +/* Spacing of tabulator stops. The value is multiplied by the width of the + * 'm' character in the current font. + */ +#ifndef MF_TABSIZE +#define MF_TABSIZE 8 +#endif + + +/************************************************************************* + * Configuration settings to strip down library to reduce resource usage * + *************************************************************************/ + +/* Enable or disable the kerning module. + * Disabling it saves some code size and run time, but causes the spacing + * between characters to be less consistent. + */ +#ifndef MF_USE_KERNING +#define MF_USE_KERNING 1 +#endif + +/* Enable or disable the advanced word wrap algorithm. + * If disabled, uses a simpler algorithm. + */ +#ifndef MF_USE_ADVANCED_WORDWRAP +#define MF_USE_ADVANCED_WORDWRAP 1 +#endif + +/* Enable of disable the justification algorithm. + * If disabled, mf_render_justified renders just left-aligned. + */ +#ifndef MF_USE_JUSTIFY +#define MF_USE_JUSTIFY 1 +#endif + +/* Enable or disable the center and right alignment code. + * If disabled, any alignment results in MF_ALIGN_LEFT. + */ +#ifndef MF_USE_ALIGN +#define MF_USE_ALIGN 1 +#endif + +/* Enable or disable the support for tab alignment. + * If disabled, tabs will be rendered as regular space character. + */ +#ifndef MF_USE_TABS +#define MF_USE_TABS 1 +#endif + +/* Number of vertical zones to use when computing kerning. + * Larger values give more accurate kerning, but are slower and use somewhat + * more memory. There is no point to increase this beyond the height of the + * font. + */ +#ifndef MF_KERNING_ZONES +#define MF_KERNING_ZONES 16 +#endif + + + +/* Add extern "C" when used from C++. */ +#ifdef __cplusplus +#define MF_EXTERN extern "C" +#else +#define MF_EXTERN extern +#endif + +#endif + diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_encoding.c b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_encoding.c similarity index 94% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_encoding.c rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_encoding.c index 74e13fe..8d1817b 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_encoding.c +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_encoding.c @@ -1,84 +1,84 @@ -#include "mf_encoding.h" - -#if MF_ENCODING == MF_ENCODING_UTF8 - -mf_char mf_getchar(mf_str *str) -{ - uint8_t c; - uint8_t tmp, seqlen; - uint16_t result; - - c = **str; - if (!c) - return 0; - - (*str)++; - - if ((c & 0x80) == 0) - { - /* Just normal ASCII character. */ - return c; - } - else if ((c & 0xC0) == 0x80) - { - /* Dangling piece of corrupted multibyte sequence. - * Did you cut the string in the wrong place? - */ - return c; - } - else if ((**str & 0xC0) == 0xC0) - { - /* Start of multibyte sequence without any following bytes. - * Silly. Maybe you are using the wrong encoding. - */ - return c; - } - else - { - /* Beginning of a multi-byte sequence. - * Find out how many characters and combine them. - */ - seqlen = 2; - tmp = 0x20; - result = 0; - while ((c & tmp) && (seqlen < 5)) - { - seqlen++; - tmp >>= 1; - - result = (result << 6) | (**str & 0x3F); - (*str)++; - } - - result = (result << 6) | (**str & 0x3F); - (*str)++; - - result |= (c & (tmp - 1)) << ((seqlen - 1) * 6); - return result; - } -} - -void mf_rewind(mf_str *str) -{ - (*str)--; - - while ((**str & 0x80) != 0x00 && (**str & 0xC0) != 0xC0) - (*str)--; -} - -#else - -mf_char mf_getchar(mf_str *str) -{ - if (!(**str)) - return 0; - else - return *(*str)++; -} - -void mf_rewind(mf_str *str) -{ - (*str)--; -} - -#endif +#include "mf_encoding.h" + +#if MF_ENCODING == MF_ENCODING_UTF8 + +mf_char mf_getchar(mf_str *str) +{ + uint8_t c; + uint8_t tmp, seqlen; + uint16_t result; + + c = **str; + if (!c) + return 0; + + (*str)++; + + if ((c & 0x80) == 0) + { + /* Just normal ASCII character. */ + return c; + } + else if ((c & 0xC0) == 0x80) + { + /* Dangling piece of corrupted multibyte sequence. + * Did you cut the string in the wrong place? + */ + return c; + } + else if ((**str & 0xC0) == 0xC0) + { + /* Start of multibyte sequence without any following bytes. + * Silly. Maybe you are using the wrong encoding. + */ + return c; + } + else + { + /* Beginning of a multi-byte sequence. + * Find out how many characters and combine them. + */ + seqlen = 2; + tmp = 0x20; + result = 0; + while ((c & tmp) && (seqlen < 5)) + { + seqlen++; + tmp >>= 1; + + result = (result << 6) | (**str & 0x3F); + (*str)++; + } + + result = (result << 6) | (**str & 0x3F); + (*str)++; + + result |= (c & (tmp - 1)) << ((seqlen - 1) * 6); + return result; + } +} + +void mf_rewind(mf_str *str) +{ + (*str)--; + + while ((**str & 0x80) != 0x00 && (**str & 0xC0) != 0xC0) + (*str)--; +} + +#else + +mf_char mf_getchar(mf_str *str) +{ + if (!(**str)) + return 0; + else + return *(*str)++; +} + +void mf_rewind(mf_str *str) +{ + (*str)--; +} + +#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_encoding.h b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_encoding.h similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_encoding.h rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_encoding.h index 68ddf14..cf04ef7 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_encoding.h +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_encoding.h @@ -1,45 +1,45 @@ -/* Simple UTF-8 decoder. Also implements the much simpler ASCII and UTF16 - * input encodings. - */ - -#ifndef _MF_ENCODING_H_ -#define _MF_ENCODING_H_ - -#include "mf_config.h" -#include - -/* Type used to represent characters internally. */ -#if MF_ENCODING == MF_ENCODING_ASCII -typedef char mf_char; -#else -typedef uint16_t mf_char; -#endif - -/* Type used to represent input strings. */ -#if MF_ENCODING == MF_ENCODING_ASCII -typedef const char * mf_str; -#elif MF_ENCODING == MF_ENCODING_UTF8 -typedef const char * mf_str; -#elif MF_ENCODING == MF_ENCODING_UTF16 -typedef const uint16_t * mf_str; -#elif MF_ENCODING == MF_ENCODING_WCHAR -#include -typedef const wchar_t * mf_str; -#endif - -/* Returns the next character in the string and advances the pointer. - * When the string ends, returns 0 and leaves the pointer at the 0 byte. - * - * str: Pointer to variable holding current location in string. - * Initialize it to the start of the string. - * - * Returns: The next character, as unicode codepoint. - */ -MF_EXTERN mf_char mf_getchar(mf_str *str); - -/* Moves back the pointer to the beginning of the previous character. - * Be careful not to go beyond the start of the string. - */ -MF_EXTERN void mf_rewind(mf_str *str); - -#endif +/* Simple UTF-8 decoder. Also implements the much simpler ASCII and UTF16 + * input encodings. + */ + +#ifndef _MF_ENCODING_H_ +#define _MF_ENCODING_H_ + +#include "mf_config.h" +#include + +/* Type used to represent characters internally. */ +#if MF_ENCODING == MF_ENCODING_ASCII +typedef char mf_char; +#else +typedef uint16_t mf_char; +#endif + +/* Type used to represent input strings. */ +#if MF_ENCODING == MF_ENCODING_ASCII +typedef const char * mf_str; +#elif MF_ENCODING == MF_ENCODING_UTF8 +typedef const char * mf_str; +#elif MF_ENCODING == MF_ENCODING_UTF16 +typedef const uint16_t * mf_str; +#elif MF_ENCODING == MF_ENCODING_WCHAR +#include +typedef const wchar_t * mf_str; +#endif + +/* Returns the next character in the string and advances the pointer. + * When the string ends, returns 0 and leaves the pointer at the 0 byte. + * + * str: Pointer to variable holding current location in string. + * Initialize it to the start of the string. + * + * Returns: The next character, as unicode codepoint. + */ +MF_EXTERN mf_char mf_getchar(mf_str *str); + +/* Moves back the pointer to the beginning of the previous character. + * Be careful not to go beyond the start of the string. + */ +MF_EXTERN void mf_rewind(mf_str *str); + +#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_font.c b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_font.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_font.c rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_font.c index 58f91c5..8d87b31 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_font.c +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_font.c @@ -1,122 +1,122 @@ -#include "mf_font.h" -#include - -/* This will be made into a list of included fonts using macro magic. */ -#define MF_INCLUDED_FONTS 0 - -/* Included fonts begin here */ -#include MF_FONT_FILE_NAME -/* Include fonts end here */ - -uint8_t mf_render_character(const struct mf_font_s *font, - int16_t x0, int16_t y0, - mf_char character, - mf_pixel_callback_t callback, - void *state) -{ - uint8_t width; - width = font->render_character(font, x0, y0, character, callback, state); - - if (!width) - { - width = font->render_character(font, x0, y0, font->fallback_character, - callback, state); - } - - return width; -} - -uint8_t mf_character_width(const struct mf_font_s *font, - mf_char character) -{ - uint8_t width; - width = font->character_width(font, character); - - if (!width) - { - width = font->character_width(font, font->fallback_character); - } - - return width; -} - -struct whitespace_state -{ - uint8_t min_x, min_y; - uint8_t max_x, max_y; -}; - -static void whitespace_callback(int16_t x, int16_t y, uint8_t count, - uint8_t alpha, void *state) -{ - struct whitespace_state *s = state; - if (alpha > 7) - { - if (s->min_x > x) s->min_x = x; - if (s->min_y > y) s->min_y = y; - x += count - 1; - if (s->max_x < x) s->max_x = x; - if (s->max_y < y) s->max_y = y; - } -} - -MF_EXTERN void mf_character_whitespace(const struct mf_font_s *font, - mf_char character, - uint8_t *left, uint8_t *top, - uint8_t *right, uint8_t *bottom) -{ - struct whitespace_state state = {255, 255, 0, 0}; - mf_render_character(font, 0, 0, character, whitespace_callback, &state); - - if (state.min_x == 255 && state.min_y == 255) - { - /* Character is whitespace */ - if (left) *left = font->width; - if (top) *top = font->height; - if (right) *right = 0; - if (bottom) *bottom = 0; - } - else - { - if (left) *left = state.min_x; - if (top) *top = state.min_y; - if (right) *right = font->width - state.max_x - 1; - if (bottom) *bottom = font->height - state.max_y - 1; - } -} - -/* Avoids a dependency on libc */ -static bool strequals(const char *a, const char *b) -{ - while (*a) - { - if (*a++ != *b++) - return false; - } - return (!*b); -} - -const struct mf_font_s *mf_find_font(const char *name) -{ - const struct mf_font_list_s *f; - f = MF_INCLUDED_FONTS; - - while (f) - { - if (strequals(f->font->full_name, name) || - strequals(f->font->short_name, name)) - { - return f->font; - } - - f = f->next; - } - - return 0; -} - -const struct mf_font_list_s *mf_get_font_list() -{ - return MF_INCLUDED_FONTS; -} - +#include "mf_font.h" +#include + +/* This will be made into a list of included fonts using macro magic. */ +#define MF_INCLUDED_FONTS 0 + +/* Included fonts begin here */ +#include MF_FONT_FILE_NAME +/* Include fonts end here */ + +uint8_t mf_render_character(const struct mf_font_s *font, + int16_t x0, int16_t y0, + mf_char character, + mf_pixel_callback_t callback, + void *state) +{ + uint8_t width; + width = font->render_character(font, x0, y0, character, callback, state); + + if (!width) + { + width = font->render_character(font, x0, y0, font->fallback_character, + callback, state); + } + + return width; +} + +uint8_t mf_character_width(const struct mf_font_s *font, + mf_char character) +{ + uint8_t width; + width = font->character_width(font, character); + + if (!width) + { + width = font->character_width(font, font->fallback_character); + } + + return width; +} + +struct whitespace_state +{ + uint8_t min_x, min_y; + uint8_t max_x, max_y; +}; + +static void whitespace_callback(int16_t x, int16_t y, uint8_t count, + uint8_t alpha, void *state) +{ + struct whitespace_state *s = state; + if (alpha > 7) + { + if (s->min_x > x) s->min_x = x; + if (s->min_y > y) s->min_y = y; + x += count - 1; + if (s->max_x < x) s->max_x = x; + if (s->max_y < y) s->max_y = y; + } +} + +MF_EXTERN void mf_character_whitespace(const struct mf_font_s *font, + mf_char character, + uint8_t *left, uint8_t *top, + uint8_t *right, uint8_t *bottom) +{ + struct whitespace_state state = {255, 255, 0, 0}; + mf_render_character(font, 0, 0, character, whitespace_callback, &state); + + if (state.min_x == 255 && state.min_y == 255) + { + /* Character is whitespace */ + if (left) *left = font->width; + if (top) *top = font->height; + if (right) *right = 0; + if (bottom) *bottom = 0; + } + else + { + if (left) *left = state.min_x; + if (top) *top = state.min_y; + if (right) *right = font->width - state.max_x - 1; + if (bottom) *bottom = font->height - state.max_y - 1; + } +} + +/* Avoids a dependency on libc */ +static bool strequals(const char *a, const char *b) +{ + while (*a) + { + if (*a++ != *b++) + return false; + } + return (!*b); +} + +const struct mf_font_s *mf_find_font(const char *name) +{ + const struct mf_font_list_s *f; + f = MF_INCLUDED_FONTS; + + while (f) + { + if (strequals(f->font->full_name, name) || + strequals(f->font->short_name, name)) + { + return f->font; + } + + f = f->next; + } + + return 0; +} + +const struct mf_font_list_s *mf_get_font_list() +{ + return MF_INCLUDED_FONTS; +} + diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_font.h b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_font.h similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_font.h rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_font.h index 6970937..309ed36 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_font.h +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_font.h @@ -1,137 +1,137 @@ -/* Generic font type that supports fonts with multiple kinds of compression. - * Provides an interface for decoding and rendering single characters. - */ - -#ifndef _MF_FONT_H_ -#define _MF_FONT_H_ - -#include "mf_encoding.h" - -/* Callback function that writes pixels to screen / buffer / whatever. - * - * x: X coordinate of the first pixel to write. - * y: Y coordinate of the first pixel to write. - * count: Number of pixels to fill (horizontally). - * alpha: The "opaqueness" of the pixels, 0 for background, 255 for text. - * state: Free variable that was passed to render_character(). - */ -typedef void (*mf_pixel_callback_t) (int16_t x, int16_t y, uint8_t count, - uint8_t alpha, void *state); - -/* General information about a font. */ -struct mf_font_s -{ - /* Full name of the font, comes from the original font file. */ - char *full_name; - - /* Short name of the font, comes from file name. */ - char *short_name; - - /* Width and height of the character bounding box. */ - uint8_t width; - uint8_t height; - - /* Minimum and maximum tracking width of characters. */ - uint8_t min_x_advance; - uint8_t max_x_advance; - - /* Location of the text baseline relative to character. */ - int8_t baseline_x; - uint8_t baseline_y; - - /* Line height of the font (vertical advance). */ - uint8_t line_height; - - /* Flags identifying various aspects of the font. */ - uint8_t flags; - - /* Fallback character to use for missing glyphs. */ - mf_char fallback_character; - - /* Function to get character width. Should return 0 if character is - * not found. */ - uint8_t (*character_width)(const struct mf_font_s *font, mf_char character); - - /* Function to render a character. Returns the character width or 0 if - * character is not found. */ - uint8_t (*render_character)(const struct mf_font_s *font, - int16_t x0, int16_t y0, - mf_char character, - mf_pixel_callback_t callback, - void *state); -}; - -/* The flag definitions for the font.flags field. */ -#define MF_FONT_FLAG_MONOSPACE 0x01 -#define MF_FONT_FLAG_BW 0x02 - -/* Lookup structure for searching fonts by name. */ -struct mf_font_list_s -{ - const struct mf_font_list_s *next; - const struct mf_font_s *font; -}; - - -/* Function to decode and render a single character. - * - * font: Pointer to the font definition. - * x0, y0: Upper left corner of the target area. - * character: The character code (unicode) to render. - * callback: Callback function to write out the pixels. - * state: Free variable for caller to use (can be NULL). - * - * Returns width of the character. - */ -MF_EXTERN uint8_t mf_render_character(const struct mf_font_s *font, - int16_t x0, int16_t y0, - mf_char character, - mf_pixel_callback_t callback, - void *state); - -/* Function to get the width of a single character. - * This is not necessarily the bounding box of the character - * data, but rather the tracking width. - * - * font: Pointer to the font definition. - * character: The character code (unicode) to check width of. - * - * Returns width of the character in pixels. - */ -MF_EXTERN uint8_t mf_character_width(const struct mf_font_s *font, - mf_char character); - -/* Count the amount of white space at the borders of a character. - * - * E.g. if the font->width and font->height are 10x20, but the character - * is only a thin line at the very left edge, this function will return - * (0, 0, 9, 0). If the character is fully whitespace, the function will - * return (10, 20, 0, 0). - * - * font: Pointer to the font definition. - * character: The character code (unicode) to check white space of. - * left: Number of empty rows at left edge. Can be NULL. - * top: Number of empty rows at top edge. Can be NULL. - * right: Number of empty rows at right edge. Can be NULL. - * bottom: Number of empty rows at bottom edge. Can be NULL. - */ -MF_EXTERN void mf_character_whitespace(const struct mf_font_s *font, - mf_char character, - uint8_t *left, uint8_t *top, - uint8_t *right, uint8_t *bottom); - -/* Find a font based on name. The name can be either short name or full name. - * Note: You can pass MF_INCLUDED_FONTS to search among all the included .h - * files. - * - * name: Font name to search for. - * fonts: Pointer to the first font search entry. - * - * Returns a pointer to the font or NULL if not found. - */ -MF_EXTERN const struct mf_font_s *mf_find_font(const char *name); - -/* Get the list of included fonts */ -MF_EXTERN const struct mf_font_list_s *mf_get_font_list(); - -#endif +/* Generic font type that supports fonts with multiple kinds of compression. + * Provides an interface for decoding and rendering single characters. + */ + +#ifndef _MF_FONT_H_ +#define _MF_FONT_H_ + +#include "mf_encoding.h" + +/* Callback function that writes pixels to screen / buffer / whatever. + * + * x: X coordinate of the first pixel to write. + * y: Y coordinate of the first pixel to write. + * count: Number of pixels to fill (horizontally). + * alpha: The "opaqueness" of the pixels, 0 for background, 255 for text. + * state: Free variable that was passed to render_character(). + */ +typedef void (*mf_pixel_callback_t) (int16_t x, int16_t y, uint8_t count, + uint8_t alpha, void *state); + +/* General information about a font. */ +struct mf_font_s +{ + /* Full name of the font, comes from the original font file. */ + char *full_name; + + /* Short name of the font, comes from file name. */ + char *short_name; + + /* Width and height of the character bounding box. */ + uint8_t width; + uint8_t height; + + /* Minimum and maximum tracking width of characters. */ + uint8_t min_x_advance; + uint8_t max_x_advance; + + /* Location of the text baseline relative to character. */ + int8_t baseline_x; + uint8_t baseline_y; + + /* Line height of the font (vertical advance). */ + uint8_t line_height; + + /* Flags identifying various aspects of the font. */ + uint8_t flags; + + /* Fallback character to use for missing glyphs. */ + mf_char fallback_character; + + /* Function to get character width. Should return 0 if character is + * not found. */ + uint8_t (*character_width)(const struct mf_font_s *font, mf_char character); + + /* Function to render a character. Returns the character width or 0 if + * character is not found. */ + uint8_t (*render_character)(const struct mf_font_s *font, + int16_t x0, int16_t y0, + mf_char character, + mf_pixel_callback_t callback, + void *state); +}; + +/* The flag definitions for the font.flags field. */ +#define MF_FONT_FLAG_MONOSPACE 0x01 +#define MF_FONT_FLAG_BW 0x02 + +/* Lookup structure for searching fonts by name. */ +struct mf_font_list_s +{ + const struct mf_font_list_s *next; + const struct mf_font_s *font; +}; + + +/* Function to decode and render a single character. + * + * font: Pointer to the font definition. + * x0, y0: Upper left corner of the target area. + * character: The character code (unicode) to render. + * callback: Callback function to write out the pixels. + * state: Free variable for caller to use (can be NULL). + * + * Returns width of the character. + */ +MF_EXTERN uint8_t mf_render_character(const struct mf_font_s *font, + int16_t x0, int16_t y0, + mf_char character, + mf_pixel_callback_t callback, + void *state); + +/* Function to get the width of a single character. + * This is not necessarily the bounding box of the character + * data, but rather the tracking width. + * + * font: Pointer to the font definition. + * character: The character code (unicode) to check width of. + * + * Returns width of the character in pixels. + */ +MF_EXTERN uint8_t mf_character_width(const struct mf_font_s *font, + mf_char character); + +/* Count the amount of white space at the borders of a character. + * + * E.g. if the font->width and font->height are 10x20, but the character + * is only a thin line at the very left edge, this function will return + * (0, 0, 9, 0). If the character is fully whitespace, the function will + * return (10, 20, 0, 0). + * + * font: Pointer to the font definition. + * character: The character code (unicode) to check white space of. + * left: Number of empty rows at left edge. Can be NULL. + * top: Number of empty rows at top edge. Can be NULL. + * right: Number of empty rows at right edge. Can be NULL. + * bottom: Number of empty rows at bottom edge. Can be NULL. + */ +MF_EXTERN void mf_character_whitespace(const struct mf_font_s *font, + mf_char character, + uint8_t *left, uint8_t *top, + uint8_t *right, uint8_t *bottom); + +/* Find a font based on name. The name can be either short name or full name. + * Note: You can pass MF_INCLUDED_FONTS to search among all the included .h + * files. + * + * name: Font name to search for. + * fonts: Pointer to the first font search entry. + * + * Returns a pointer to the font or NULL if not found. + */ +MF_EXTERN const struct mf_font_s *mf_find_font(const char *name); + +/* Get the list of included fonts */ +MF_EXTERN const struct mf_font_list_s *mf_get_font_list(); + +#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_justify.c b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_justify.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_justify.c rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_justify.c index 623ab30..634c87c 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_justify.c +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_justify.c @@ -1,332 +1,332 @@ -#include "mf_justify.h" -#include "mf_kerning.h" - -#if MF_USE_TABS -/* Round the X coordinate up to the nearest tab stop. */ -static int16_t mf_round_to_tab(const struct mf_font_s *font, - int16_t x0, int16_t x) -{ - int16_t tabw, dx; - - tabw = mf_character_width(font, 'm') * MF_TABSIZE; - - /* Always atleast 1 space */ - x += mf_character_width(font, ' '); - - /* Round to next tab stop */ - dx = x - x0 + font->baseline_x; - x += tabw - (dx % tabw); - - return x; -} - -/* Round the X coordinate down to the nearest tab stop. */ -static int16_t mf_round_to_prev_tab(const struct mf_font_s *font, - int16_t x0, int16_t x) -{ - int16_t tabw, dx; - - tabw = mf_character_width(font, 'm') * MF_TABSIZE; - - /* Always atleast 1 space */ - x -= mf_character_width(font, ' '); - - /* Round to previous tab stop */ - dx = x0 - x + font->baseline_x; - x -= tabw - (dx % tabw); - - return x; -} -#endif - -int16_t mf_get_string_width(const struct mf_font_s *font, mf_str text, - uint16_t count, bool kern) -{ - int16_t result = 0; - uint16_t c1 = 0, c2; - - if (!count) - count = 0xFFFF; - - while (count-- && *text) - { - c2 = mf_getchar(&text); - - if (c2 == '\t') - { -#if MF_USE_TABS - result = mf_round_to_tab(font, 0, result); - c1 = ' '; - continue; -#else - c2 = ' '; -#endif - } - - if (kern && c1 != 0) - result += mf_compute_kerning(font, c1, c2); - - result += mf_character_width(font, c2); - c1 = c2; - } - - return result; -} - -/* Return the length of the string without trailing spaces. */ -static uint16_t strip_spaces(mf_str text, uint16_t count, mf_char *last_char) -{ - uint16_t i = 0, result = 0; - mf_char tmp = 0; - - if (!count) - count = 0xFFFF; - - while (count-- && *text) - { - i++; - tmp = mf_getchar(&text); - if (tmp != ' ' && tmp != 0xA0 && tmp != '\n' && - tmp != '\r' && tmp != '\t') - { - result = i; - } - } - - if (last_char) - { - if (!*text) - *last_char = 0; - else - *last_char = tmp; - } - - return result; -} - -/* Render left-aligned string, left edge at x0. */ -static void render_left(const struct mf_font_s *font, - int16_t x0, int16_t y0, - mf_str text, uint16_t count, - mf_character_callback_t callback, - void *state) -{ - int16_t x; - mf_char c1 = 0, c2; - - x = x0 - font->baseline_x; - while (count--) - { - c2 = mf_getchar(&text); - - if (c2 == '\t') - { -#if MF_USE_TABS - x = mf_round_to_tab(font, x0, x); - c1 = ' '; - continue; -#else - c2 = ' '; -#endif - } - - if (c1 != 0) - x += mf_compute_kerning(font, c1, c2); - - x += callback(x, y0, c2, state); - c1 = c2; - } -} - -#if !MF_USE_ALIGN - -void mf_render_aligned(const struct mf_font_s *font, - int16_t x0, int16_t y0, - enum mf_align_t align, - mf_str text, uint16_t count, - mf_character_callback_t callback, - void *state) -{ - int16_t string_width; - count = strip_spaces(text, count, 0); - render_left(font, x0, y0, text, count, callback, state); -} - -#else - -/* Render right-aligned string, right edge at x0. */ -static void render_right(const struct mf_font_s *font, - int16_t x0, int16_t y0, - mf_str text, uint16_t count, - mf_character_callback_t callback, - void *state) -{ - int16_t x; - uint16_t i; - mf_char c1, c2 = 0; - mf_str tmp; - - /* Go to the end of the line. */ - for (i = 0; i < count; i++) - mf_getchar(&text); - - x = x0 - font->baseline_x; - for (i = 0; i < count; i++) - { - mf_rewind(&text); - tmp = text; - c1 = mf_getchar(&tmp); - - /* Perform tab alignment */ - if (c1 == '\t') - { -#if MF_USE_TABS - x = mf_round_to_prev_tab(font, x0, x); - c2 = ' '; - continue; -#else - c1 = ' '; -#endif - } - - /* Apply the nominal character width */ - x -= mf_character_width(font, c1); - - /* Apply kerning */ - if (c2 != 0) - x -= mf_compute_kerning(font, c1, c2); - - callback(x, y0, c1, state); - c2 = c1; - } -} - -void mf_render_aligned(const struct mf_font_s *font, - int16_t x0, int16_t y0, - enum mf_align_t align, - mf_str text, uint16_t count, - mf_character_callback_t callback, - void *state) -{ - int16_t string_width; - count = strip_spaces(text, count, 0); - - if (align == MF_ALIGN_LEFT) - { - render_left(font, x0, y0, text, count, callback, state); - } - if (align == MF_ALIGN_CENTER) - { - string_width = mf_get_string_width(font, text, count, false); - x0 -= string_width / 2; - render_left(font, x0, y0, text, count, callback, state); - } - else if (align == MF_ALIGN_RIGHT) - { - render_right(font, x0, y0, text, count, callback, state); - } -} - -#endif - - -#if !MF_USE_JUSTIFY - -void mf_render_justified(const struct mf_font_s *font, - int16_t x0, int16_t y0, int16_t width, - mf_str text, uint16_t count, - mf_character_callback_t callback, - void *state) -{ - mf_render_aligned(font, x0, y0, MF_ALIGN_LEFT, text, count, callback, state); -} - -#else - -/* Returns true if the character is a justification point, i.e. expands - * when the text is being justified. */ -static bool is_justify_space(uint16_t c) -{ - return c == ' ' || c == 0xA0; -} - -/* Count the number of space characters in string */ -static uint16_t count_spaces(mf_str text, uint16_t count) -{ - uint16_t spaces = 0; - while (count-- && *text) - { - if (is_justify_space(mf_getchar(&text))) - spaces++; - } - return spaces; -} - -void mf_render_justified(const struct mf_font_s *font, - int16_t x0, int16_t y0, int16_t width, - mf_str text, uint16_t count, - mf_character_callback_t callback, - void *state) -{ - int16_t string_width, adjustment; - uint16_t num_spaces; - mf_char last_char; - - count = strip_spaces(text, count, &last_char); - - if (last_char == '\n' || last_char == 0) - { - /* Line ends in linefeed, do not justify. */ - render_left(font, x0, y0, text, count, callback, state); - return; - } - - string_width = mf_get_string_width(font, text, count, false); - adjustment = width - string_width; - num_spaces = count_spaces(text, count); - - { - int16_t x, tmp; - uint16_t c1 = 0, c2; - - x = x0 - font->baseline_x; - while (count--) - { - c2 = mf_getchar(&text); - - if (c2 == '\t') - { -#if MF_USE_TABS - tmp = x; - x = mf_round_to_tab(font, x0, x); - adjustment -= x - tmp - mf_character_width(font, '\t'); - c1 = c2; - continue; -#else - c2 = ' '; -#endif - } - - if (is_justify_space(c2)) - { - tmp = (adjustment + num_spaces / 2) / num_spaces; - adjustment -= tmp; - num_spaces--; - x += tmp; - } - - if (c1 != 0) - { - tmp = mf_compute_kerning(font, c1, c2); - x += tmp; - adjustment -= tmp; - } - - x += callback(x, y0, c2, state); - c1 = c2; - } - } -} - -#endif - +#include "mf_justify.h" +#include "mf_kerning.h" + +#if MF_USE_TABS +/* Round the X coordinate up to the nearest tab stop. */ +static int16_t mf_round_to_tab(const struct mf_font_s *font, + int16_t x0, int16_t x) +{ + int16_t tabw, dx; + + tabw = mf_character_width(font, 'm') * MF_TABSIZE; + + /* Always atleast 1 space */ + x += mf_character_width(font, ' '); + + /* Round to next tab stop */ + dx = x - x0 + font->baseline_x; + x += tabw - (dx % tabw); + + return x; +} + +/* Round the X coordinate down to the nearest tab stop. */ +static int16_t mf_round_to_prev_tab(const struct mf_font_s *font, + int16_t x0, int16_t x) +{ + int16_t tabw, dx; + + tabw = mf_character_width(font, 'm') * MF_TABSIZE; + + /* Always atleast 1 space */ + x -= mf_character_width(font, ' '); + + /* Round to previous tab stop */ + dx = x0 - x + font->baseline_x; + x -= tabw - (dx % tabw); + + return x; +} +#endif + +int16_t mf_get_string_width(const struct mf_font_s *font, mf_str text, + uint16_t count, bool kern) +{ + int16_t result = 0; + uint16_t c1 = 0, c2; + + if (!count) + count = 0xFFFF; + + while (count-- && *text) + { + c2 = mf_getchar(&text); + + if (c2 == '\t') + { +#if MF_USE_TABS + result = mf_round_to_tab(font, 0, result); + c1 = ' '; + continue; +#else + c2 = ' '; +#endif + } + + if (kern && c1 != 0) + result += mf_compute_kerning(font, c1, c2); + + result += mf_character_width(font, c2); + c1 = c2; + } + + return result; +} + +/* Return the length of the string without trailing spaces. */ +static uint16_t strip_spaces(mf_str text, uint16_t count, mf_char *last_char) +{ + uint16_t i = 0, result = 0; + mf_char tmp = 0; + + if (!count) + count = 0xFFFF; + + while (count-- && *text) + { + i++; + tmp = mf_getchar(&text); + if (tmp != ' ' && tmp != 0xA0 && tmp != '\n' && + tmp != '\r' && tmp != '\t') + { + result = i; + } + } + + if (last_char) + { + if (!*text) + *last_char = 0; + else + *last_char = tmp; + } + + return result; +} + +/* Render left-aligned string, left edge at x0. */ +static void render_left(const struct mf_font_s *font, + int16_t x0, int16_t y0, + mf_str text, uint16_t count, + mf_character_callback_t callback, + void *state) +{ + int16_t x; + mf_char c1 = 0, c2; + + x = x0 - font->baseline_x; + while (count--) + { + c2 = mf_getchar(&text); + + if (c2 == '\t') + { +#if MF_USE_TABS + x = mf_round_to_tab(font, x0, x); + c1 = ' '; + continue; +#else + c2 = ' '; +#endif + } + + if (c1 != 0) + x += mf_compute_kerning(font, c1, c2); + + x += callback(x, y0, c2, state); + c1 = c2; + } +} + +#if !MF_USE_ALIGN + +void mf_render_aligned(const struct mf_font_s *font, + int16_t x0, int16_t y0, + enum mf_align_t align, + mf_str text, uint16_t count, + mf_character_callback_t callback, + void *state) +{ + int16_t string_width; + count = strip_spaces(text, count, 0); + render_left(font, x0, y0, text, count, callback, state); +} + +#else + +/* Render right-aligned string, right edge at x0. */ +static void render_right(const struct mf_font_s *font, + int16_t x0, int16_t y0, + mf_str text, uint16_t count, + mf_character_callback_t callback, + void *state) +{ + int16_t x; + uint16_t i; + mf_char c1, c2 = 0; + mf_str tmp; + + /* Go to the end of the line. */ + for (i = 0; i < count; i++) + mf_getchar(&text); + + x = x0 - font->baseline_x; + for (i = 0; i < count; i++) + { + mf_rewind(&text); + tmp = text; + c1 = mf_getchar(&tmp); + + /* Perform tab alignment */ + if (c1 == '\t') + { +#if MF_USE_TABS + x = mf_round_to_prev_tab(font, x0, x); + c2 = ' '; + continue; +#else + c1 = ' '; +#endif + } + + /* Apply the nominal character width */ + x -= mf_character_width(font, c1); + + /* Apply kerning */ + if (c2 != 0) + x -= mf_compute_kerning(font, c1, c2); + + callback(x, y0, c1, state); + c2 = c1; + } +} + +void mf_render_aligned(const struct mf_font_s *font, + int16_t x0, int16_t y0, + enum mf_align_t align, + mf_str text, uint16_t count, + mf_character_callback_t callback, + void *state) +{ + int16_t string_width; + count = strip_spaces(text, count, 0); + + if (align == MF_ALIGN_LEFT) + { + render_left(font, x0, y0, text, count, callback, state); + } + if (align == MF_ALIGN_CENTER) + { + string_width = mf_get_string_width(font, text, count, false); + x0 -= string_width / 2; + render_left(font, x0, y0, text, count, callback, state); + } + else if (align == MF_ALIGN_RIGHT) + { + render_right(font, x0, y0, text, count, callback, state); + } +} + +#endif + + +#if !MF_USE_JUSTIFY + +void mf_render_justified(const struct mf_font_s *font, + int16_t x0, int16_t y0, int16_t width, + mf_str text, uint16_t count, + mf_character_callback_t callback, + void *state) +{ + mf_render_aligned(font, x0, y0, MF_ALIGN_LEFT, text, count, callback, state); +} + +#else + +/* Returns true if the character is a justification point, i.e. expands + * when the text is being justified. */ +static bool is_justify_space(uint16_t c) +{ + return c == ' ' || c == 0xA0; +} + +/* Count the number of space characters in string */ +static uint16_t count_spaces(mf_str text, uint16_t count) +{ + uint16_t spaces = 0; + while (count-- && *text) + { + if (is_justify_space(mf_getchar(&text))) + spaces++; + } + return spaces; +} + +void mf_render_justified(const struct mf_font_s *font, + int16_t x0, int16_t y0, int16_t width, + mf_str text, uint16_t count, + mf_character_callback_t callback, + void *state) +{ + int16_t string_width, adjustment; + uint16_t num_spaces; + mf_char last_char; + + count = strip_spaces(text, count, &last_char); + + if (last_char == '\n' || last_char == 0) + { + /* Line ends in linefeed, do not justify. */ + render_left(font, x0, y0, text, count, callback, state); + return; + } + + string_width = mf_get_string_width(font, text, count, false); + adjustment = width - string_width; + num_spaces = count_spaces(text, count); + + { + int16_t x, tmp; + uint16_t c1 = 0, c2; + + x = x0 - font->baseline_x; + while (count--) + { + c2 = mf_getchar(&text); + + if (c2 == '\t') + { +#if MF_USE_TABS + tmp = x; + x = mf_round_to_tab(font, x0, x); + adjustment -= x - tmp - mf_character_width(font, '\t'); + c1 = c2; + continue; +#else + c2 = ' '; +#endif + } + + if (is_justify_space(c2)) + { + tmp = (adjustment + num_spaces / 2) / num_spaces; + adjustment -= tmp; + num_spaces--; + x += tmp; + } + + if (c1 != 0) + { + tmp = mf_compute_kerning(font, c1, c2); + x += tmp; + adjustment -= tmp; + } + + x += callback(x, y0, c2, state); + c1 = c2; + } + } +} + +#endif + diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_justify.h b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_justify.h similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_justify.h rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_justify.h index c3e8ba7..437c0e2 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_justify.h +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_justify.h @@ -1,74 +1,74 @@ -/* Text alignment and justification algorithm. Supports left, right, center - * alignment and justify. Supports tab stops and kerning. - */ - -#ifndef _MF_JUSTIFY_H_ -#define _MF_JUSTIFY_H_ - -#include "mf_rlefont.h" -#include - -enum mf_align_t -{ - MF_ALIGN_LEFT = 0, - MF_ALIGN_CENTER, - MF_ALIGN_RIGHT -}; - -/* Callback for rendering a single character. - * x0: Left edge of the target position of character. - * y0: Upper edge of the target position of character. - * character: Character to render. - * state: Free state variable for use by the callback. - * Returns the width of the character. - */ -typedef uint8_t (*mf_character_callback_t) (int16_t x0, int16_t y0, - mf_char character, void *state); - -/* Get width of a string in pixels. - * - * font: Pointer to the font definition. - * text: Pointer to start of the text to measure. - * count: Number of characters on the line or 0 to read until end of string. - * kern: True to consider kerning (slower). - */ -MF_EXTERN int16_t mf_get_string_width(const struct mf_font_s *font, - mf_str text, uint16_t count, bool kern); - -/* Render a single line of aligned text. - * - * font: Pointer to the font definition. - * x0: Depending on aligned, either left, center or right edge of target. - * y0: Upper edge of the target area. - * align: Type of alignment. - * text: Pointer to start of the text to render. - * count: Number of characters on the line or 0 to read until end of string. - * callback: Callback to call for each character. - * state: Free variable for use in the callback. - */ -MF_EXTERN void mf_render_aligned(const struct mf_font_s *font, - int16_t x0, int16_t y0, - enum mf_align_t align, - mf_str text, uint16_t count, - mf_character_callback_t callback, - void *state); - -/* Render a single line of justified text. - * - * font: Pointer to the font definition. - * x0: Left edge of the target area. - * y0: Upper edge of the target area. - * width: Width of the target area. - * text: Pointer to start of the text to render. - * count: Number of characters on the line or 0 to read until end of string. - * callback: Callback to call for each character. - * state: Free variable for use in the callback. - */ -MF_EXTERN void mf_render_justified(const struct mf_font_s *font, - int16_t x0, int16_t y0, int16_t width, - mf_str text, uint16_t count, - mf_character_callback_t callback, - void *state); - - -#endif +/* Text alignment and justification algorithm. Supports left, right, center + * alignment and justify. Supports tab stops and kerning. + */ + +#ifndef _MF_JUSTIFY_H_ +#define _MF_JUSTIFY_H_ + +#include "mf_rlefont.h" +#include + +enum mf_align_t +{ + MF_ALIGN_LEFT = 0, + MF_ALIGN_CENTER, + MF_ALIGN_RIGHT +}; + +/* Callback for rendering a single character. + * x0: Left edge of the target position of character. + * y0: Upper edge of the target position of character. + * character: Character to render. + * state: Free state variable for use by the callback. + * Returns the width of the character. + */ +typedef uint8_t (*mf_character_callback_t) (int16_t x0, int16_t y0, + mf_char character, void *state); + +/* Get width of a string in pixels. + * + * font: Pointer to the font definition. + * text: Pointer to start of the text to measure. + * count: Number of characters on the line or 0 to read until end of string. + * kern: True to consider kerning (slower). + */ +MF_EXTERN int16_t mf_get_string_width(const struct mf_font_s *font, + mf_str text, uint16_t count, bool kern); + +/* Render a single line of aligned text. + * + * font: Pointer to the font definition. + * x0: Depending on aligned, either left, center or right edge of target. + * y0: Upper edge of the target area. + * align: Type of alignment. + * text: Pointer to start of the text to render. + * count: Number of characters on the line or 0 to read until end of string. + * callback: Callback to call for each character. + * state: Free variable for use in the callback. + */ +MF_EXTERN void mf_render_aligned(const struct mf_font_s *font, + int16_t x0, int16_t y0, + enum mf_align_t align, + mf_str text, uint16_t count, + mf_character_callback_t callback, + void *state); + +/* Render a single line of justified text. + * + * font: Pointer to the font definition. + * x0: Left edge of the target area. + * y0: Upper edge of the target area. + * width: Width of the target area. + * text: Pointer to start of the text to render. + * count: Number of characters on the line or 0 to read until end of string. + * callback: Callback to call for each character. + * state: Free variable for use in the callback. + */ +MF_EXTERN void mf_render_justified(const struct mf_font_s *font, + int16_t x0, int16_t y0, int16_t width, + mf_str text, uint16_t count, + mf_character_callback_t callback, + void *state); + + +#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_kerning.c b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_kerning.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_kerning.c rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_kerning.c index 51ce303..f2721ab 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_kerning.c +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_kerning.c @@ -1,118 +1,118 @@ -#include "mf_kerning.h" -#include - -#if MF_USE_KERNING - -/* Structure for keeping track of the edge of the glyph as it is rendered. */ -struct kerning_state_s -{ - uint8_t edgepos[MF_KERNING_ZONES]; - uint8_t zoneheight; -}; - -/* Pixel callback for analyzing the left edge of a glyph. */ -static void fit_leftedge(int16_t x, int16_t y, uint8_t count, uint8_t alpha, - void *state) -{ - struct kerning_state_s *s = state; - - if (alpha > 7) - { - uint8_t zone = y / s->zoneheight; - if (x < s->edgepos[zone]) - s->edgepos[zone] = x; - } -} - -/* Pixel callback for analyzing the right edge of a glyph. */ -static void fit_rightedge(int16_t x, int16_t y, uint8_t count, uint8_t alpha, - void *state) -{ - struct kerning_state_s *s = state; - - if (alpha > 7) - { - uint8_t zone = y / s->zoneheight; - x += count - 1; - if (x > s->edgepos[zone]) - s->edgepos[zone] = x; - } -} - -/* Should kerning be done against this character? */ -static bool do_kerning(mf_char c) -{ - /* Just a speed optimization, spaces would be ignored anyway. */ - if (c == ' ' || c == '\n' || c == '\r' || c == '\t') - return false; - - /* Do not kern against digits, in order to keep values in tables nicely - * aligned. Most fonts have constant width for digits. */ - if (c >= '0' && c <= '9') - return false; - - return true; -} - -/*static int16_t min16(int16_t a, int16_t b) { return (a < b) ? a : b; }*/ -static int16_t max16(int16_t a, int16_t b) { return (a > b) ? a : b; } -static int16_t avg16(int16_t a, int16_t b) { return (a + b) / 2; } - -int8_t mf_compute_kerning(const struct mf_font_s *font, - mf_char c1, mf_char c2) -{ - struct kerning_state_s leftedge, rightedge; - uint8_t w1, w2, i, min_space; - int16_t normal_space, adjust, max_adjust; - - if (font->flags & MF_FONT_FLAG_MONOSPACE) - return 0; /* No kerning for monospace fonts */ - - if (!do_kerning(c1) || !do_kerning(c2)) - return 0; - - /* Compute the height of one kerning zone in pixels */ - i = (font->height + MF_KERNING_ZONES - 1) / MF_KERNING_ZONES; - if (i < 1) i = 1; - - /* Initialize structures */ - leftedge.zoneheight = rightedge.zoneheight = i; - for (i = 0; i < MF_KERNING_ZONES; i++) - { - leftedge.edgepos[i] = 255; - rightedge.edgepos[i] = 0; - } - - /* Analyze the edges of both glyphs. */ - w1 = mf_render_character(font, 0, 0, c1, fit_rightedge, &rightedge); - w2 = mf_render_character(font, 0, 0, c2, fit_leftedge, &leftedge); - - /* Find the minimum horizontal space between the glyphs. */ - min_space = 255; - for (i = 0; i < MF_KERNING_ZONES; i++) - { - uint8_t space; - if (leftedge.edgepos[i] == 255 || rightedge.edgepos[i] == 0) - continue; /* Outside glyph area. */ - - space = w1 - rightedge.edgepos[i] + leftedge.edgepos[i]; - if (space < min_space) - min_space = space; - } - - if (min_space == 255) - return 0; /* One of the characters is space, or both are punctuation. */ - - /* Compute the adjustment of the glyph position. */ - normal_space = avg16(w1, w2) * MF_KERNING_SPACE_PERCENT / 100; - normal_space += MF_KERNING_SPACE_PIXELS; - adjust = normal_space - min_space; - max_adjust = -max16(w1, w2) * MF_KERNING_LIMIT / 100; - - if (adjust > 0) adjust = 0; - if (adjust < max_adjust) adjust = max_adjust; - - return adjust; -} - -#endif +#include "mf_kerning.h" +#include + +#if MF_USE_KERNING + +/* Structure for keeping track of the edge of the glyph as it is rendered. */ +struct kerning_state_s +{ + uint8_t edgepos[MF_KERNING_ZONES]; + uint8_t zoneheight; +}; + +/* Pixel callback for analyzing the left edge of a glyph. */ +static void fit_leftedge(int16_t x, int16_t y, uint8_t count, uint8_t alpha, + void *state) +{ + struct kerning_state_s *s = state; + + if (alpha > 7) + { + uint8_t zone = y / s->zoneheight; + if (x < s->edgepos[zone]) + s->edgepos[zone] = x; + } +} + +/* Pixel callback for analyzing the right edge of a glyph. */ +static void fit_rightedge(int16_t x, int16_t y, uint8_t count, uint8_t alpha, + void *state) +{ + struct kerning_state_s *s = state; + + if (alpha > 7) + { + uint8_t zone = y / s->zoneheight; + x += count - 1; + if (x > s->edgepos[zone]) + s->edgepos[zone] = x; + } +} + +/* Should kerning be done against this character? */ +static bool do_kerning(mf_char c) +{ + /* Just a speed optimization, spaces would be ignored anyway. */ + if (c == ' ' || c == '\n' || c == '\r' || c == '\t') + return false; + + /* Do not kern against digits, in order to keep values in tables nicely + * aligned. Most fonts have constant width for digits. */ + if (c >= '0' && c <= '9') + return false; + + return true; +} + +/*static int16_t min16(int16_t a, int16_t b) { return (a < b) ? a : b; }*/ +static int16_t max16(int16_t a, int16_t b) { return (a > b) ? a : b; } +static int16_t avg16(int16_t a, int16_t b) { return (a + b) / 2; } + +int8_t mf_compute_kerning(const struct mf_font_s *font, + mf_char c1, mf_char c2) +{ + struct kerning_state_s leftedge, rightedge; + uint8_t w1, w2, i, min_space; + int16_t normal_space, adjust, max_adjust; + + if (font->flags & MF_FONT_FLAG_MONOSPACE) + return 0; /* No kerning for monospace fonts */ + + if (!do_kerning(c1) || !do_kerning(c2)) + return 0; + + /* Compute the height of one kerning zone in pixels */ + i = (font->height + MF_KERNING_ZONES - 1) / MF_KERNING_ZONES; + if (i < 1) i = 1; + + /* Initialize structures */ + leftedge.zoneheight = rightedge.zoneheight = i; + for (i = 0; i < MF_KERNING_ZONES; i++) + { + leftedge.edgepos[i] = 255; + rightedge.edgepos[i] = 0; + } + + /* Analyze the edges of both glyphs. */ + w1 = mf_render_character(font, 0, 0, c1, fit_rightedge, &rightedge); + w2 = mf_render_character(font, 0, 0, c2, fit_leftedge, &leftedge); + + /* Find the minimum horizontal space between the glyphs. */ + min_space = 255; + for (i = 0; i < MF_KERNING_ZONES; i++) + { + uint8_t space; + if (leftedge.edgepos[i] == 255 || rightedge.edgepos[i] == 0) + continue; /* Outside glyph area. */ + + space = w1 - rightedge.edgepos[i] + leftedge.edgepos[i]; + if (space < min_space) + min_space = space; + } + + if (min_space == 255) + return 0; /* One of the characters is space, or both are punctuation. */ + + /* Compute the adjustment of the glyph position. */ + normal_space = avg16(w1, w2) * MF_KERNING_SPACE_PERCENT / 100; + normal_space += MF_KERNING_SPACE_PIXELS; + adjust = normal_space - min_space; + max_adjust = -max16(w1, w2) * MF_KERNING_LIMIT / 100; + + if (adjust > 0) adjust = 0; + if (adjust < max_adjust) adjust = max_adjust; + + return adjust; +} + +#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_kerning.h b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_kerning.h similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_kerning.h rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_kerning.h index a7dcecc..0c41aec 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_kerning.h +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_kerning.h @@ -1,27 +1,27 @@ -/* Automatic kerning for font rendering. This solves the issue where some - * fonts (especially serif fonts) have too much space between specific - * character pairs, like WA or L'. - */ - -#ifndef _MF_KERNING_H_ -#define _MF_KERNING_H_ - -#include "mf_config.h" -#include "mf_rlefont.h" - -/* Compute the kerning adjustment when c1 is followed by c2. - * - * font: Pointer to the font definition. - * c1: The previous character. - * c2: The next character to render. - * - * Returns the offset to add to the x position for c2. - */ -#if MF_USE_KERNING -MF_EXTERN int8_t mf_compute_kerning(const struct mf_font_s *font, - mf_char c1, mf_char c2); -#else -#define mf_compute_kerning(f,c1,c2) (0) -#endif - +/* Automatic kerning for font rendering. This solves the issue where some + * fonts (especially serif fonts) have too much space between specific + * character pairs, like WA or L'. + */ + +#ifndef _MF_KERNING_H_ +#define _MF_KERNING_H_ + +#include "mf_config.h" +#include "mf_rlefont.h" + +/* Compute the kerning adjustment when c1 is followed by c2. + * + * font: Pointer to the font definition. + * c1: The previous character. + * c2: The next character to render. + * + * Returns the offset to add to the x position for c2. + */ +#if MF_USE_KERNING +MF_EXTERN int8_t mf_compute_kerning(const struct mf_font_s *font, + mf_char c1, mf_char c2); +#else +#define mf_compute_kerning(f,c1,c2) (0) +#endif + #endif \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_rlefont.c b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_rlefont.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_rlefont.c rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_rlefont.c index 27f2073..1407290 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_rlefont.c +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_rlefont.c @@ -1,286 +1,286 @@ -#include "mf_rlefont.h" - -/* Number of reserved codes before the dictionary entries. */ -#define DICT_START 24 - -/* Special reference to mean "fill with zeros to the end of the glyph" */ -#define REF_FILLZEROS 16 - -/* RLE codes */ -#define RLE_CODEMASK 0xC0 -#define RLE_VALMASK 0x3F -#define RLE_ZEROS 0x00 -#define RLE_64ZEROS 0x40 -#define RLE_ONES 0x80 -#define RLE_SHADE 0xC0 - -/* Dictionary "fill entries" for encoding bits directly. */ -#define DICT_START7BIT 4 -#define DICT_START6BIT 132 -#define DICT_START5BIT 196 -#define DICT_START4BIT 228 -#define DICT_START3BIT 244 -#define DICT_START2BIT 252 - -/* Find a pointer to the glyph matching a given character by searching - * through the character ranges. If the character is not found, return - * pointer to the default glyph. - */ -static const uint8_t *find_glyph(const struct mf_rlefont_s *font, - uint16_t character) -{ - unsigned i, index; - const struct mf_rlefont_char_range_s *range; - for (i = 0; i < font->char_range_count; i++) - { - range = &font->char_ranges[i]; - index = character - range->first_char; - if (character >= range->first_char && index < range->char_count) - { - uint16_t offset = pgm_read_word(range->glyph_offsets + index); - return &range->glyph_data[offset]; - } - } - - return 0; -} - -/* Structure to keep track of coordinates of the next pixel to be written, - * and also the bounds of the character. */ -struct renderstate_r -{ - int16_t x_begin; - int16_t x_end; - int16_t x; - int16_t y; - int16_t y_end; - mf_pixel_callback_t callback; - void *state; -}; - -/* Call the callback to write one pixel to screen, and advance to next - * pixel position. */ -static void write_pixels(struct renderstate_r *rstate, uint16_t count, - uint8_t alpha) -{ - uint8_t rowlen; - - /* Write row-by-row if the run spans multiple rows. */ - while (rstate->x + count >= rstate->x_end) - { - rowlen = rstate->x_end - rstate->x; - rstate->callback(rstate->x, rstate->y, rowlen, alpha, rstate->state); - count -= rowlen; - rstate->x = rstate->x_begin; - rstate->y++; - } - - /* Write the remaining part */ - if (count) - { - rstate->callback(rstate->x, rstate->y, count, alpha, rstate->state); - rstate->x += count; - } -} - -/* Skip the given number of pixels (0 alpha) */ -static void skip_pixels(struct renderstate_r *rstate, uint16_t count) -{ - rstate->x += count; - while (rstate->x >= rstate->x_end) - { - rstate->x -= rstate->x_end - rstate->x_begin; - rstate->y++; - } -} - -/* Decode and write out a RLE-encoded dictionary entry. */ -static void write_rle_dictentry(const struct mf_rlefont_s *font, - struct renderstate_r *rstate, - uint8_t index) -{ - uint16_t offset = pgm_read_word(font->dictionary_offsets + index); - uint16_t length = pgm_read_word(font->dictionary_offsets + index + 1) - offset; - uint16_t i; - - for (i = 0; i < length; i++) - { - uint8_t code = pgm_read_byte(font->dictionary_data + offset + i); - if ((code & RLE_CODEMASK) == RLE_ZEROS) - { - skip_pixels(rstate, code & RLE_VALMASK); - } - else if ((code & RLE_CODEMASK) == RLE_64ZEROS) - { - skip_pixels(rstate, ((code & RLE_VALMASK) + 1) * 64); - } - else if ((code & RLE_CODEMASK) == RLE_ONES) - { - write_pixels(rstate, (code & RLE_VALMASK) + 1, 255); - } - else if ((code & RLE_CODEMASK) == RLE_SHADE) - { - uint8_t count, alpha; - count = ((code & RLE_VALMASK) >> 4) + 1; - alpha = ((code & RLE_VALMASK) & 0xF) * 0x11; - write_pixels(rstate, count, alpha); - } - } -} - -/* Get bit count for the "fill entries" */ -static uint8_t fillentry_bitcount(uint8_t index) -{ - if (index >= DICT_START2BIT) - return 2; - else if (index >= DICT_START3BIT) - return 3; - else if (index >= DICT_START4BIT) - return 4; - else if (index >= DICT_START5BIT) - return 5; - else if (index >= DICT_START6BIT) - return 6; - else - return 7; -} - -/* Decode and write out a direct binary codeword */ -static void write_bin_codeword(const struct mf_rlefont_s *font, - struct renderstate_r *rstate, - uint8_t code) -{ - uint8_t bitcount = fillentry_bitcount(code); - uint8_t byte = code - DICT_START7BIT; - uint8_t runlen = 0; - - while (bitcount--) - { - if (byte & 1) - { - runlen++; - } - else - { - if (runlen) - { - write_pixels(rstate, runlen, 255); - runlen = 0; - } - - skip_pixels(rstate, 1); - } - - byte >>= 1; - } - - if (runlen) - write_pixels(rstate, runlen, 255); -} - -/* Decode and write out a reference codeword */ -static void write_ref_codeword(const struct mf_rlefont_s *font, - struct renderstate_r *rstate, - uint8_t code) -{ - if (code == 0) - { - skip_pixels(rstate, 1); - } - else if (code <= 15) - { - write_pixels(rstate, 1, 0x11 * code); - } - else if (code == REF_FILLZEROS) - { - /* Fill with zeroes to end */ - rstate->y = rstate->y_end; - } - else if (code < DICT_START) - { - /* Reserved */ - } - else if (code < DICT_START + font->rle_entry_count) - { - write_rle_dictentry(font, rstate, code - DICT_START); - } - else - { - write_bin_codeword(font, rstate, code); - } -} - -/* Decode and write out a reference encoded dictionary entry. */ -static void write_ref_dictentry(const struct mf_rlefont_s *font, - struct renderstate_r *rstate, - uint8_t index) -{ - uint16_t offset = pgm_read_word(font->dictionary_offsets + index); - uint16_t length = pgm_read_word(font->dictionary_offsets + index + 1) - offset; - uint16_t i; - - for (i = 0; i < length; i++) - { - uint8_t code = pgm_read_byte(font->dictionary_data + offset + i); - write_ref_codeword(font, rstate, code); - } -} - -/* Decode and write out an arbitrary glyph codeword */ -static void write_glyph_codeword(const struct mf_rlefont_s *font, - struct renderstate_r *rstate, - uint8_t code) -{ - if (code >= DICT_START + font->rle_entry_count && - code < DICT_START + font->dict_entry_count) - { - write_ref_dictentry(font, rstate, code - DICT_START); - } - else - { - write_ref_codeword(font, rstate, code); - } -} - - -uint8_t mf_rlefont_render_character(const struct mf_font_s *font, - int16_t x0, int16_t y0, - uint16_t character, - mf_pixel_callback_t callback, - void *state) -{ - const uint8_t *p; - uint8_t width; - - struct renderstate_r rstate; - rstate.x_begin = x0; - rstate.x_end = x0 + font->width; - rstate.x = x0; - rstate.y = y0; - rstate.y_end = y0 + font->height; - rstate.callback = callback; - rstate.state = state; - - p = find_glyph((struct mf_rlefont_s*)font, character); - if (!p) - return 0; - - width = pgm_read_byte(p++); - while (rstate.y < rstate.y_end) - { - write_glyph_codeword((struct mf_rlefont_s*)font, &rstate, pgm_read_byte(p++)); - } - - return width; -} - -uint8_t mf_rlefont_character_width(const struct mf_font_s *font, - uint16_t character) -{ - const uint8_t *p; - p = find_glyph((struct mf_rlefont_s*)font, character); - if (!p) - return 0; - - return pgm_read_byte(p); -} +#include "mf_rlefont.h" + +/* Number of reserved codes before the dictionary entries. */ +#define DICT_START 24 + +/* Special reference to mean "fill with zeros to the end of the glyph" */ +#define REF_FILLZEROS 16 + +/* RLE codes */ +#define RLE_CODEMASK 0xC0 +#define RLE_VALMASK 0x3F +#define RLE_ZEROS 0x00 +#define RLE_64ZEROS 0x40 +#define RLE_ONES 0x80 +#define RLE_SHADE 0xC0 + +/* Dictionary "fill entries" for encoding bits directly. */ +#define DICT_START7BIT 4 +#define DICT_START6BIT 132 +#define DICT_START5BIT 196 +#define DICT_START4BIT 228 +#define DICT_START3BIT 244 +#define DICT_START2BIT 252 + +/* Find a pointer to the glyph matching a given character by searching + * through the character ranges. If the character is not found, return + * pointer to the default glyph. + */ +static const uint8_t *find_glyph(const struct mf_rlefont_s *font, + uint16_t character) +{ + unsigned i, index; + const struct mf_rlefont_char_range_s *range; + for (i = 0; i < font->char_range_count; i++) + { + range = &font->char_ranges[i]; + index = character - range->first_char; + if (character >= range->first_char && index < range->char_count) + { + uint16_t offset = pgm_read_word(range->glyph_offsets + index); + return &range->glyph_data[offset]; + } + } + + return 0; +} + +/* Structure to keep track of coordinates of the next pixel to be written, + * and also the bounds of the character. */ +struct renderstate_r +{ + int16_t x_begin; + int16_t x_end; + int16_t x; + int16_t y; + int16_t y_end; + mf_pixel_callback_t callback; + void *state; +}; + +/* Call the callback to write one pixel to screen, and advance to next + * pixel position. */ +static void write_pixels(struct renderstate_r *rstate, uint16_t count, + uint8_t alpha) +{ + uint8_t rowlen; + + /* Write row-by-row if the run spans multiple rows. */ + while (rstate->x + count >= rstate->x_end) + { + rowlen = rstate->x_end - rstate->x; + rstate->callback(rstate->x, rstate->y, rowlen, alpha, rstate->state); + count -= rowlen; + rstate->x = rstate->x_begin; + rstate->y++; + } + + /* Write the remaining part */ + if (count) + { + rstate->callback(rstate->x, rstate->y, count, alpha, rstate->state); + rstate->x += count; + } +} + +/* Skip the given number of pixels (0 alpha) */ +static void skip_pixels(struct renderstate_r *rstate, uint16_t count) +{ + rstate->x += count; + while (rstate->x >= rstate->x_end) + { + rstate->x -= rstate->x_end - rstate->x_begin; + rstate->y++; + } +} + +/* Decode and write out a RLE-encoded dictionary entry. */ +static void write_rle_dictentry(const struct mf_rlefont_s *font, + struct renderstate_r *rstate, + uint8_t index) +{ + uint16_t offset = pgm_read_word(font->dictionary_offsets + index); + uint16_t length = pgm_read_word(font->dictionary_offsets + index + 1) - offset; + uint16_t i; + + for (i = 0; i < length; i++) + { + uint8_t code = pgm_read_byte(font->dictionary_data + offset + i); + if ((code & RLE_CODEMASK) == RLE_ZEROS) + { + skip_pixels(rstate, code & RLE_VALMASK); + } + else if ((code & RLE_CODEMASK) == RLE_64ZEROS) + { + skip_pixels(rstate, ((code & RLE_VALMASK) + 1) * 64); + } + else if ((code & RLE_CODEMASK) == RLE_ONES) + { + write_pixels(rstate, (code & RLE_VALMASK) + 1, 255); + } + else if ((code & RLE_CODEMASK) == RLE_SHADE) + { + uint8_t count, alpha; + count = ((code & RLE_VALMASK) >> 4) + 1; + alpha = ((code & RLE_VALMASK) & 0xF) * 0x11; + write_pixels(rstate, count, alpha); + } + } +} + +/* Get bit count for the "fill entries" */ +static uint8_t fillentry_bitcount(uint8_t index) +{ + if (index >= DICT_START2BIT) + return 2; + else if (index >= DICT_START3BIT) + return 3; + else if (index >= DICT_START4BIT) + return 4; + else if (index >= DICT_START5BIT) + return 5; + else if (index >= DICT_START6BIT) + return 6; + else + return 7; +} + +/* Decode and write out a direct binary codeword */ +static void write_bin_codeword(const struct mf_rlefont_s *font, + struct renderstate_r *rstate, + uint8_t code) +{ + uint8_t bitcount = fillentry_bitcount(code); + uint8_t byte = code - DICT_START7BIT; + uint8_t runlen = 0; + + while (bitcount--) + { + if (byte & 1) + { + runlen++; + } + else + { + if (runlen) + { + write_pixels(rstate, runlen, 255); + runlen = 0; + } + + skip_pixels(rstate, 1); + } + + byte >>= 1; + } + + if (runlen) + write_pixels(rstate, runlen, 255); +} + +/* Decode and write out a reference codeword */ +static void write_ref_codeword(const struct mf_rlefont_s *font, + struct renderstate_r *rstate, + uint8_t code) +{ + if (code == 0) + { + skip_pixels(rstate, 1); + } + else if (code <= 15) + { + write_pixels(rstate, 1, 0x11 * code); + } + else if (code == REF_FILLZEROS) + { + /* Fill with zeroes to end */ + rstate->y = rstate->y_end; + } + else if (code < DICT_START) + { + /* Reserved */ + } + else if (code < DICT_START + font->rle_entry_count) + { + write_rle_dictentry(font, rstate, code - DICT_START); + } + else + { + write_bin_codeword(font, rstate, code); + } +} + +/* Decode and write out a reference encoded dictionary entry. */ +static void write_ref_dictentry(const struct mf_rlefont_s *font, + struct renderstate_r *rstate, + uint8_t index) +{ + uint16_t offset = pgm_read_word(font->dictionary_offsets + index); + uint16_t length = pgm_read_word(font->dictionary_offsets + index + 1) - offset; + uint16_t i; + + for (i = 0; i < length; i++) + { + uint8_t code = pgm_read_byte(font->dictionary_data + offset + i); + write_ref_codeword(font, rstate, code); + } +} + +/* Decode and write out an arbitrary glyph codeword */ +static void write_glyph_codeword(const struct mf_rlefont_s *font, + struct renderstate_r *rstate, + uint8_t code) +{ + if (code >= DICT_START + font->rle_entry_count && + code < DICT_START + font->dict_entry_count) + { + write_ref_dictentry(font, rstate, code - DICT_START); + } + else + { + write_ref_codeword(font, rstate, code); + } +} + + +uint8_t mf_rlefont_render_character(const struct mf_font_s *font, + int16_t x0, int16_t y0, + uint16_t character, + mf_pixel_callback_t callback, + void *state) +{ + const uint8_t *p; + uint8_t width; + + struct renderstate_r rstate; + rstate.x_begin = x0; + rstate.x_end = x0 + font->width; + rstate.x = x0; + rstate.y = y0; + rstate.y_end = y0 + font->height; + rstate.callback = callback; + rstate.state = state; + + p = find_glyph((struct mf_rlefont_s*)font, character); + if (!p) + return 0; + + width = pgm_read_byte(p++); + while (rstate.y < rstate.y_end) + { + write_glyph_codeword((struct mf_rlefont_s*)font, &rstate, pgm_read_byte(p++)); + } + + return width; +} + +uint8_t mf_rlefont_character_width(const struct mf_font_s *font, + uint16_t character) +{ + const uint8_t *p; + p = find_glyph((struct mf_rlefont_s*)font, character); + if (!p) + return 0; + + return pgm_read_byte(p); +} diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_rlefont.h b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_rlefont.h similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_rlefont.h rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_rlefont.h index b672ef9..fc84ebd 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_rlefont.h +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_rlefont.h @@ -1,82 +1,82 @@ -/* A compressed font format based on run length encoding and dictionary - * compression. - */ - -#ifndef _MF_RLEFONT_H_ -#define _MF_RLEFONT_H_ - -#include "mf_font.h" - -/* Versions of the RLE font format that are supported. */ -#define MF_RLEFONT_VERSION_4_SUPPORTED 1 - -/* Structure for a range of characters. This implements a sparse storage of - * character indices, so that you can e.g. pick a 100 characters in the middle - * of the UTF16 range and just store them. */ -struct mf_rlefont_char_range_s -{ - /* The number of the first character in this range. */ - uint16_t first_char; - - /* The total count of characters in this range. */ - uint16_t char_count; - - /* Lookup table with the start indices into glyph_data. */ - uint16_t *glyph_offsets; - uint32_t glyph_offsets_size; - uint32_t glyph_offsets_fp_offset; - - /* The encoded glyph data for glyphs in this range. */ - uint8_t *glyph_data; - uint32_t glyph_data_size; - uint32_t glyph_data_fp_offset; -}; - -/* Structure for a single encoded font. */ -struct mf_rlefont_s -{ - struct mf_font_s font; - - /* Version of the font definition used. */ - uint8_t version; - - /* Big array of the data for all the dictionary entries. */ - uint8_t *dictionary_data; - uint32_t dictionary_data_size; - uint32_t dictionary_data_fp_offset; - - /* Lookup table with the start indices into dictionary_data. - * Contains N+1 entries, so that the length of the entry can - * be determined by subtracting from the next offset. */ - uint16_t *dictionary_offsets; - uint32_t dictionary_offsets_size; - uint32_t dictionary_offsets_fp_offset; - - /* Number of dictionary entries using the RLE encoding. - * Entries starting at this index use the dictionary encoding. */ - uint8_t rle_entry_count; - - /* Total number of dictionary entries. - * Entries after this are nonexistent. */ - uint8_t dict_entry_count; - - /* Number of discontinuous character ranges */ - uint8_t char_range_count; - - /* Array of the character ranges */ - struct mf_rlefont_char_range_s *char_ranges; -}; - -#ifdef MF_RLEFONT_INTERNALS -/* Internal functions, don't use these directly. */ -MF_EXTERN uint8_t mf_rlefont_render_character(const struct mf_font_s *font, - int16_t x0, int16_t y0, - mf_char character, - mf_pixel_callback_t callback, - void *state); - -MF_EXTERN uint8_t mf_rlefont_character_width(const struct mf_font_s *font, - mf_char character); -#endif - -#endif +/* A compressed font format based on run length encoding and dictionary + * compression. + */ + +#ifndef _MF_RLEFONT_H_ +#define _MF_RLEFONT_H_ + +#include "mf_font.h" + +/* Versions of the RLE font format that are supported. */ +#define MF_RLEFONT_VERSION_4_SUPPORTED 1 + +/* Structure for a range of characters. This implements a sparse storage of + * character indices, so that you can e.g. pick a 100 characters in the middle + * of the UTF16 range and just store them. */ +struct mf_rlefont_char_range_s +{ + /* The number of the first character in this range. */ + uint16_t first_char; + + /* The total count of characters in this range. */ + uint16_t char_count; + + /* Lookup table with the start indices into glyph_data. */ + uint16_t *glyph_offsets; + uint32_t glyph_offsets_size; + uint32_t glyph_offsets_fp_offset; + + /* The encoded glyph data for glyphs in this range. */ + uint8_t *glyph_data; + uint32_t glyph_data_size; + uint32_t glyph_data_fp_offset; +}; + +/* Structure for a single encoded font. */ +struct mf_rlefont_s +{ + struct mf_font_s font; + + /* Version of the font definition used. */ + uint8_t version; + + /* Big array of the data for all the dictionary entries. */ + uint8_t *dictionary_data; + uint32_t dictionary_data_size; + uint32_t dictionary_data_fp_offset; + + /* Lookup table with the start indices into dictionary_data. + * Contains N+1 entries, so that the length of the entry can + * be determined by subtracting from the next offset. */ + uint16_t *dictionary_offsets; + uint32_t dictionary_offsets_size; + uint32_t dictionary_offsets_fp_offset; + + /* Number of dictionary entries using the RLE encoding. + * Entries starting at this index use the dictionary encoding. */ + uint8_t rle_entry_count; + + /* Total number of dictionary entries. + * Entries after this are nonexistent. */ + uint8_t dict_entry_count; + + /* Number of discontinuous character ranges */ + uint8_t char_range_count; + + /* Array of the character ranges */ + struct mf_rlefont_char_range_s *char_ranges; +}; + +#ifdef MF_RLEFONT_INTERNALS +/* Internal functions, don't use these directly. */ +MF_EXTERN uint8_t mf_rlefont_render_character(const struct mf_font_s *font, + int16_t x0, int16_t y0, + mf_char character, + mf_pixel_callback_t callback, + void *state); + +MF_EXTERN uint8_t mf_rlefont_character_width(const struct mf_font_s *font, + mf_char character); +#endif + +#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_scaledfont.c b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_scaledfont.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_scaledfont.c rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_scaledfont.c index da2b31f..cb9d7e3 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_scaledfont.c +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_scaledfont.c @@ -1,83 +1,83 @@ -#include "mf_scaledfont.h" - -struct scaled_renderstate -{ - mf_pixel_callback_t orig_callback; - void *orig_state; - uint8_t x_scale; - uint8_t y_scale; - int16_t x0; - int16_t y0; -}; - -static void scaled_pixel_callback(int16_t x, int16_t y, uint8_t count, - uint8_t alpha, void *state) -{ - struct scaled_renderstate *rstate = state; - uint8_t dy; - - count *= rstate->x_scale; - x = rstate->x0 + x * rstate->x_scale; - y = rstate->y0 + y * rstate->y_scale; - - for (dy = 0; dy < rstate->y_scale; dy++) - { - rstate->orig_callback(x, y + dy, count, alpha, rstate->orig_state); - } -} - -static uint8_t scaled_character_width(const struct mf_font_s *font, - mf_char character) -{ - struct mf_scaledfont_s *sfont = (struct mf_scaledfont_s*)font; - uint8_t basewidth; - - basewidth = sfont->basefont->character_width(sfont->basefont, character); - - return sfont->x_scale * basewidth; -} - -static uint8_t scaled_render_character(const struct mf_font_s *font, - int16_t x0, int16_t y0, - mf_char character, - mf_pixel_callback_t callback, - void *state) -{ - struct mf_scaledfont_s *sfont = (struct mf_scaledfont_s*)font; - struct scaled_renderstate rstate; - uint8_t basewidth; - - rstate.orig_callback = callback; - rstate.orig_state = state; - rstate.x_scale = sfont->x_scale; - rstate.y_scale = sfont->y_scale; - rstate.x0 = x0; - rstate.y0 = y0; - - basewidth = sfont->basefont->render_character(sfont->basefont, 0, 0, - character, scaled_pixel_callback, &rstate); - - return sfont->x_scale * basewidth; -} - -void mf_scale_font(struct mf_scaledfont_s *newfont, - const struct mf_font_s *basefont, - uint8_t x_scale, uint8_t y_scale) -{ - newfont->font = *basefont; - newfont->basefont = basefont; - - newfont->font.width *= x_scale; - newfont->font.height *= y_scale; - newfont->font.baseline_x *= x_scale; - newfont->font.baseline_y *= y_scale; - newfont->font.min_x_advance *= x_scale; - newfont->font.max_x_advance *= x_scale; - newfont->font.line_height *= y_scale; - newfont->font.character_width = &scaled_character_width; - newfont->font.render_character = &scaled_render_character; - - newfont->x_scale = x_scale; - newfont->y_scale = y_scale; -} - +#include "mf_scaledfont.h" + +struct scaled_renderstate +{ + mf_pixel_callback_t orig_callback; + void *orig_state; + uint8_t x_scale; + uint8_t y_scale; + int16_t x0; + int16_t y0; +}; + +static void scaled_pixel_callback(int16_t x, int16_t y, uint8_t count, + uint8_t alpha, void *state) +{ + struct scaled_renderstate *rstate = state; + uint8_t dy; + + count *= rstate->x_scale; + x = rstate->x0 + x * rstate->x_scale; + y = rstate->y0 + y * rstate->y_scale; + + for (dy = 0; dy < rstate->y_scale; dy++) + { + rstate->orig_callback(x, y + dy, count, alpha, rstate->orig_state); + } +} + +static uint8_t scaled_character_width(const struct mf_font_s *font, + mf_char character) +{ + struct mf_scaledfont_s *sfont = (struct mf_scaledfont_s*)font; + uint8_t basewidth; + + basewidth = sfont->basefont->character_width(sfont->basefont, character); + + return sfont->x_scale * basewidth; +} + +static uint8_t scaled_render_character(const struct mf_font_s *font, + int16_t x0, int16_t y0, + mf_char character, + mf_pixel_callback_t callback, + void *state) +{ + struct mf_scaledfont_s *sfont = (struct mf_scaledfont_s*)font; + struct scaled_renderstate rstate; + uint8_t basewidth; + + rstate.orig_callback = callback; + rstate.orig_state = state; + rstate.x_scale = sfont->x_scale; + rstate.y_scale = sfont->y_scale; + rstate.x0 = x0; + rstate.y0 = y0; + + basewidth = sfont->basefont->render_character(sfont->basefont, 0, 0, + character, scaled_pixel_callback, &rstate); + + return sfont->x_scale * basewidth; +} + +void mf_scale_font(struct mf_scaledfont_s *newfont, + const struct mf_font_s *basefont, + uint8_t x_scale, uint8_t y_scale) +{ + newfont->font = *basefont; + newfont->basefont = basefont; + + newfont->font.width *= x_scale; + newfont->font.height *= y_scale; + newfont->font.baseline_x *= x_scale; + newfont->font.baseline_y *= y_scale; + newfont->font.min_x_advance *= x_scale; + newfont->font.max_x_advance *= x_scale; + newfont->font.line_height *= y_scale; + newfont->font.character_width = &scaled_character_width; + newfont->font.render_character = &scaled_render_character; + + newfont->x_scale = x_scale; + newfont->y_scale = y_scale; +} + diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_scaledfont.h b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_scaledfont.h similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_scaledfont.h rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_scaledfont.h index f660701..8c399d6 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_scaledfont.h +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_scaledfont.h @@ -1,23 +1,23 @@ -/* Generate scaled (nearest-neighbor) fonts. This can be used for displaying - * larger text without spending the memory required for including larger fonts. - */ - -#ifndef _MF_SCALEDFONT_H_ -#define _MF_SCALEDFONT_H_ - -#include "mf_font.h" - -struct mf_scaledfont_s -{ - struct mf_font_s font; - - const struct mf_font_s *basefont; - uint8_t x_scale; - uint8_t y_scale; -}; - -MF_EXTERN void mf_scale_font(struct mf_scaledfont_s *newfont, - const struct mf_font_s *basefont, - uint8_t x_scale, uint8_t y_scale); - -#endif +/* Generate scaled (nearest-neighbor) fonts. This can be used for displaying + * larger text without spending the memory required for including larger fonts. + */ + +#ifndef _MF_SCALEDFONT_H_ +#define _MF_SCALEDFONT_H_ + +#include "mf_font.h" + +struct mf_scaledfont_s +{ + struct mf_font_s font; + + const struct mf_font_s *basefont; + uint8_t x_scale; + uint8_t y_scale; +}; + +MF_EXTERN void mf_scale_font(struct mf_scaledfont_s *newfont, + const struct mf_font_s *basefont, + uint8_t x_scale, uint8_t y_scale); + +#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_wordwrap.c b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_wordwrap.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_wordwrap.c rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_wordwrap.c index 065d51c..c357d3a 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_wordwrap.c +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_wordwrap.c @@ -1,357 +1,357 @@ -#include "mf_wordwrap.h" - -/* Returns true if the line can be broken at this character. */ -static bool is_wrap_space(uint16_t c) -{ - return c == ' ' || c == '\n' || c == '\t' || c == '\r' || c == '-'; -} - -#if MF_USE_ADVANCED_WORDWRAP - -/* Represents a single word and the whitespace after it. */ -struct wordlen_s -{ - int16_t word; /* Length of the word in pixels. */ - int16_t space; /* Length of the whitespace in pixels. */ - uint16_t chars; /* Number of characters in word + space, combined. */ -}; - -/* Take the next word from the string and compute its width. - * Returns true if the word ends in a linebreak. */ -static bool get_wordlen(const struct mf_font_s *font, mf_str *text, - struct wordlen_s *result) -{ - mf_char c; - mf_str prev = *text; - - result->word = 0; - result->space = 0; - result->chars = 0; - - c = mf_getchar(text); - while (c && !is_wrap_space(c)) - { - result->chars++; - result->word += mf_character_width(font, c); - - prev = *text; - c = mf_getchar(text); - } - - while (c && is_wrap_space(c)) - { - result->chars++; - - if (c == ' ' || c == '-') - result->space += mf_character_width(font, c); - else if (c == '\t') - result->space += mf_character_width(font, 'm') * MF_TABSIZE; - else if (c == '\n') { - /* Special case for newlines, skip the character then break. */ - prev = *text; - break; - } - - prev = *text; - c = mf_getchar(text); - } - - /* The last loop reads the first character of next word, put it back. */ - if (c) - *text = prev; - - return (c == '\0' || c == '\n'); -} - -/* Represents the rendered length for a single line. */ -struct linelen_s -{ - mf_str start; /* Start of the text for line. */ - uint16_t chars; /* Total number of characters on the line. */ - int16_t width; /* Total length of all words + whitespace on the line in pixels. */ - bool linebreak; /* True if line ends in a linebreak */ - struct wordlen_s last_word; /* Last word on the line. */ - struct wordlen_s last_word_2; /* Second to last word on the line. */ -}; - -/* Append word onto the line if it fits. If it would overflow, don't add and - * return false. */ -static bool append_word(const struct mf_font_s *font, int16_t width, - struct linelen_s *current, mf_str *text) -{ - mf_str tmp = *text; - struct wordlen_s wordlen; - bool linebreak; - - linebreak = get_wordlen(font, &tmp, &wordlen); - - if (current->width + wordlen.word <= width) - { - *text = tmp; - current->last_word_2 = current->last_word; - current->last_word = wordlen; - current->linebreak = linebreak; - current->chars += wordlen.chars; - current->width += wordlen.word + wordlen.space; - return true; - } - else - { - return false; - } -} - -/* Append a character to the line if it fits. */ -static bool append_char(const struct mf_font_s *font, int16_t width, - struct linelen_s *current, mf_str *text) -{ - mf_str tmp = *text; - mf_char c; - uint16_t w; - - c = mf_getchar(&tmp); - w = mf_character_width(font, c); - - if (current->width + w <= width) - { - *text = tmp; - current->chars++; - current->width += w; - return true; - } - else - { - return false; - } -} - -/*static int16_t abs16(int16_t x) { return (x > 0) ? x : -x; }*/ -static int32_t sq16(int16_t x) { return (int32_t)x * x; } - -/* Try to balance the lines by potentially moving one word from the previous - * line to the the current one. */ -static void tune_lines(struct linelen_s *current, struct linelen_s *previous, - int16_t max_width) -{ - int16_t curw1, prevw1; - int16_t curw2, prevw2; - int32_t delta1, delta2; - - /* If the lines are rendered as is */ - curw1 = current->width - current->last_word.space; - prevw1 = previous->width - previous->last_word.space; - delta1 = sq16(max_width - prevw1) + sq16(max_width - curw1); - - /* If the last word is moved */ - curw2 = current->width + previous->last_word.word; - prevw2 = previous->width - previous->last_word.word - - previous->last_word.space - - previous->last_word_2.space; - delta2 = sq16(max_width - prevw2) + sq16(max_width - curw2); - - if (delta1 > delta2 && curw2 <= max_width) - { - /* Do the change. */ - uint16_t chars; - - chars = previous->last_word.chars; - previous->chars -= chars; - current->chars += chars; - previous->width -= previous->last_word.word + previous->last_word.space; - current->width += previous->last_word.word + previous->last_word.space; - previous->last_word = previous->last_word_2; - - while (chars--) mf_rewind(¤t->start); - } -} - -void mf_wordwrap(const struct mf_font_s *font, int16_t width, - mf_str text, mf_line_callback_t callback, void *state) -{ - struct linelen_s current = { 0 }; - struct linelen_s previous = { 0 }; - bool full; - - current.start = text; - - while (*text) - { - full = !append_word(font, width, ¤t, &text); - - if (full || current.linebreak) - { - if (!current.chars) - { - /* We have a very long word. We must just cut it off at some - * point. */ - while (append_char(font, width, ¤t, &text)); - } - - if (previous.chars) - { - /* Tune the length and dispatch the previous line. */ - if (!previous.linebreak && !current.linebreak) - tune_lines(¤t, &previous, width); - - if (!callback(previous.start, previous.chars, state)) - return; - } - - previous = current; - current.start = text; - current.chars = 0; - current.width = 0; - current.linebreak = false; - current.last_word.word = 0; - current.last_word.space = 0; - current.last_word.chars = 0; - } - } - - /* Dispatch the last lines. */ - if (previous.chars) - { - if (!callback(previous.start, previous.chars, state)) - return; - } - - if (current.chars) - callback(current.start, current.chars, state); -} - -void mf_text_draw_area(const struct mf_font_s *font, int16_t width, - mf_str text, - int *total_height_in_rows, - int *max_pixels_per_row) -{ - struct linelen_s current = { 0 }; - struct linelen_s previous = { 0 }; - bool full; - - current.start = text; - *total_height_in_rows = 0; - *max_pixels_per_row = 0; - - while (*text) - { - full = !append_word(font, width, ¤t, &text); - - if (full || current.linebreak) - { - if (!current.chars) - { - /* We have a very long word. We must just cut it off at some - * point. */ - while (append_char(font, width, ¤t, &text)); - } - - if (previous.chars) - { - /* Tune the length and dispatch the previous line. */ - if (!previous.linebreak && !current.linebreak) - tune_lines(¤t, &previous, width); - *total_height_in_rows += 1; - } - - if ( *max_pixels_per_row < current.width ) - *max_pixels_per_row = current.width; - previous = current; - current.start = text; - current.chars = 0; - current.width = 0; - current.linebreak = false; - current.last_word.word = 0; - current.last_word.space = 0; - current.last_word.chars = 0; - } - } - - /* Dispatch the last lines. */ - if (previous.chars) - { - if ( *max_pixels_per_row < previous.width ) - *max_pixels_per_row = previous.width; - *total_height_in_rows += 1; - } - - if (current.chars) { - if ( *max_pixels_per_row < current.width ) - *max_pixels_per_row = current.width; - *total_height_in_rows += 1; - } - -} - -#else - -void mf_wordwrap(const struct mf_font_s *font, int16_t width, - mf_str text, mf_line_callback_t callback, void *state) -{ - mf_str orig = text; - mf_str linestart; - - /* Current line width and character count */ - int16_t lw_cur = 0, cc_cur = 0; - - /* Previous wrap point */ - int16_t cc_prev; - mf_str ls_prev; - - linestart = text; - - while (*text) - { - cc_prev = 0; - ls_prev = text; - - while (*text) - { - mf_char c; - int16_t new_width; - mf_str tmp; - - tmp = text; - c = mf_getchar(&text); - new_width = lw_cur + mf_character_width(font, c); - - if (c == '\n') - { - cc_prev = cc_cur + 1; - ls_prev = text; - break; - } - - if (new_width > width) - { - text = tmp; - break; - } - - cc_cur++; - lw_cur = new_width; - - if (is_wrap_space(c)) - { - cc_prev = cc_cur; - ls_prev = text; - } - } - - /* Handle unbreakable words */ - if (cc_prev == 0) - { - cc_prev = cc_cur; - ls_prev = text; - } - - if (!callback(linestart, cc_prev, state)) - return; - - linestart = ls_prev; - text = linestart; - lw_cur = 0; - cc_cur = 0; - } -} - -#endif +#include "mf_wordwrap.h" + +/* Returns true if the line can be broken at this character. */ +static bool is_wrap_space(uint16_t c) +{ + return c == ' ' || c == '\n' || c == '\t' || c == '\r' || c == '-'; +} + +#if MF_USE_ADVANCED_WORDWRAP + +/* Represents a single word and the whitespace after it. */ +struct wordlen_s +{ + int16_t word; /* Length of the word in pixels. */ + int16_t space; /* Length of the whitespace in pixels. */ + uint16_t chars; /* Number of characters in word + space, combined. */ +}; + +/* Take the next word from the string and compute its width. + * Returns true if the word ends in a linebreak. */ +static bool get_wordlen(const struct mf_font_s *font, mf_str *text, + struct wordlen_s *result) +{ + mf_char c; + mf_str prev = *text; + + result->word = 0; + result->space = 0; + result->chars = 0; + + c = mf_getchar(text); + while (c && !is_wrap_space(c)) + { + result->chars++; + result->word += mf_character_width(font, c); + + prev = *text; + c = mf_getchar(text); + } + + while (c && is_wrap_space(c)) + { + result->chars++; + + if (c == ' ' || c == '-') + result->space += mf_character_width(font, c); + else if (c == '\t') + result->space += mf_character_width(font, 'm') * MF_TABSIZE; + else if (c == '\n') { + /* Special case for newlines, skip the character then break. */ + prev = *text; + break; + } + + prev = *text; + c = mf_getchar(text); + } + + /* The last loop reads the first character of next word, put it back. */ + if (c) + *text = prev; + + return (c == '\0' || c == '\n'); +} + +/* Represents the rendered length for a single line. */ +struct linelen_s +{ + mf_str start; /* Start of the text for line. */ + uint16_t chars; /* Total number of characters on the line. */ + int16_t width; /* Total length of all words + whitespace on the line in pixels. */ + bool linebreak; /* True if line ends in a linebreak */ + struct wordlen_s last_word; /* Last word on the line. */ + struct wordlen_s last_word_2; /* Second to last word on the line. */ +}; + +/* Append word onto the line if it fits. If it would overflow, don't add and + * return false. */ +static bool append_word(const struct mf_font_s *font, int16_t width, + struct linelen_s *current, mf_str *text) +{ + mf_str tmp = *text; + struct wordlen_s wordlen; + bool linebreak; + + linebreak = get_wordlen(font, &tmp, &wordlen); + + if (current->width + wordlen.word <= width) + { + *text = tmp; + current->last_word_2 = current->last_word; + current->last_word = wordlen; + current->linebreak = linebreak; + current->chars += wordlen.chars; + current->width += wordlen.word + wordlen.space; + return true; + } + else + { + return false; + } +} + +/* Append a character to the line if it fits. */ +static bool append_char(const struct mf_font_s *font, int16_t width, + struct linelen_s *current, mf_str *text) +{ + mf_str tmp = *text; + mf_char c; + uint16_t w; + + c = mf_getchar(&tmp); + w = mf_character_width(font, c); + + if (current->width + w <= width) + { + *text = tmp; + current->chars++; + current->width += w; + return true; + } + else + { + return false; + } +} + +/*static int16_t abs16(int16_t x) { return (x > 0) ? x : -x; }*/ +static int32_t sq16(int16_t x) { return (int32_t)x * x; } + +/* Try to balance the lines by potentially moving one word from the previous + * line to the the current one. */ +static void tune_lines(struct linelen_s *current, struct linelen_s *previous, + int16_t max_width) +{ + int16_t curw1, prevw1; + int16_t curw2, prevw2; + int32_t delta1, delta2; + + /* If the lines are rendered as is */ + curw1 = current->width - current->last_word.space; + prevw1 = previous->width - previous->last_word.space; + delta1 = sq16(max_width - prevw1) + sq16(max_width - curw1); + + /* If the last word is moved */ + curw2 = current->width + previous->last_word.word; + prevw2 = previous->width - previous->last_word.word + - previous->last_word.space + - previous->last_word_2.space; + delta2 = sq16(max_width - prevw2) + sq16(max_width - curw2); + + if (delta1 > delta2 && curw2 <= max_width) + { + /* Do the change. */ + uint16_t chars; + + chars = previous->last_word.chars; + previous->chars -= chars; + current->chars += chars; + previous->width -= previous->last_word.word + previous->last_word.space; + current->width += previous->last_word.word + previous->last_word.space; + previous->last_word = previous->last_word_2; + + while (chars--) mf_rewind(¤t->start); + } +} + +void mf_wordwrap(const struct mf_font_s *font, int16_t width, + mf_str text, mf_line_callback_t callback, void *state) +{ + struct linelen_s current = { 0 }; + struct linelen_s previous = { 0 }; + bool full; + + current.start = text; + + while (*text) + { + full = !append_word(font, width, ¤t, &text); + + if (full || current.linebreak) + { + if (!current.chars) + { + /* We have a very long word. We must just cut it off at some + * point. */ + while (append_char(font, width, ¤t, &text)); + } + + if (previous.chars) + { + /* Tune the length and dispatch the previous line. */ + if (!previous.linebreak && !current.linebreak) + tune_lines(¤t, &previous, width); + + if (!callback(previous.start, previous.chars, state)) + return; + } + + previous = current; + current.start = text; + current.chars = 0; + current.width = 0; + current.linebreak = false; + current.last_word.word = 0; + current.last_word.space = 0; + current.last_word.chars = 0; + } + } + + /* Dispatch the last lines. */ + if (previous.chars) + { + if (!callback(previous.start, previous.chars, state)) + return; + } + + if (current.chars) + callback(current.start, current.chars, state); +} + +void mf_text_draw_area(const struct mf_font_s *font, int16_t width, + mf_str text, + int *total_height_in_rows, + int *max_pixels_per_row) +{ + struct linelen_s current = { 0 }; + struct linelen_s previous = { 0 }; + bool full; + + current.start = text; + *total_height_in_rows = 0; + *max_pixels_per_row = 0; + + while (*text) + { + full = !append_word(font, width, ¤t, &text); + + if (full || current.linebreak) + { + if (!current.chars) + { + /* We have a very long word. We must just cut it off at some + * point. */ + while (append_char(font, width, ¤t, &text)); + } + + if (previous.chars) + { + /* Tune the length and dispatch the previous line. */ + if (!previous.linebreak && !current.linebreak) + tune_lines(¤t, &previous, width); + *total_height_in_rows += 1; + } + + if ( *max_pixels_per_row < current.width ) + *max_pixels_per_row = current.width; + previous = current; + current.start = text; + current.chars = 0; + current.width = 0; + current.linebreak = false; + current.last_word.word = 0; + current.last_word.space = 0; + current.last_word.chars = 0; + } + } + + /* Dispatch the last lines. */ + if (previous.chars) + { + if ( *max_pixels_per_row < previous.width ) + *max_pixels_per_row = previous.width; + *total_height_in_rows += 1; + } + + if (current.chars) { + if ( *max_pixels_per_row < current.width ) + *max_pixels_per_row = current.width; + *total_height_in_rows += 1; + } + +} + +#else + +void mf_wordwrap(const struct mf_font_s *font, int16_t width, + mf_str text, mf_line_callback_t callback, void *state) +{ + mf_str orig = text; + mf_str linestart; + + /* Current line width and character count */ + int16_t lw_cur = 0, cc_cur = 0; + + /* Previous wrap point */ + int16_t cc_prev; + mf_str ls_prev; + + linestart = text; + + while (*text) + { + cc_prev = 0; + ls_prev = text; + + while (*text) + { + mf_char c; + int16_t new_width; + mf_str tmp; + + tmp = text; + c = mf_getchar(&text); + new_width = lw_cur + mf_character_width(font, c); + + if (c == '\n') + { + cc_prev = cc_cur + 1; + ls_prev = text; + break; + } + + if (new_width > width) + { + text = tmp; + break; + } + + cc_cur++; + lw_cur = new_width; + + if (is_wrap_space(c)) + { + cc_prev = cc_cur; + ls_prev = text; + } + } + + /* Handle unbreakable words */ + if (cc_prev == 0) + { + cc_prev = cc_cur; + ls_prev = text; + } + + if (!callback(linestart, cc_prev, state)) + return; + + linestart = ls_prev; + text = linestart; + lw_cur = 0; + cc_cur = 0; + } +} + +#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_wordwrap.h b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_wordwrap.h similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_wordwrap.h rename to bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_wordwrap.h index d14eb66..ada7333 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_wordwrap.h +++ b/bsp/sdk_overlay/middleware/vglite/font/mcufont/decoder/mf_wordwrap.h @@ -1,35 +1,35 @@ -/* Word wrapping algorithm with UTF-8 support. More than just a basic greedy - * word-wrapper: it attempts to balance consecutive lines as pairs. - */ - -#ifndef _MF_WORDWRAP_H_ -#define _MF_WORDWRAP_H_ - -#include "mf_rlefont.h" -#include - -/* Callback function for handling each line. - * - * line: Pointer to the beginning of the string for this line. - * count: Number of characters on the line. - * state: Free variable that was passed to wordwrap(). - * - * Returns: true to continue, false to stop after this line. - */ -typedef bool (*mf_line_callback_t) (mf_str line, uint16_t count, - void *state); - -/* Word wrap a piece of text. Calls the callback function for each line. - * - * font: Font to use for metrics. - * width: Maximum line width in pixels. - * text: Pointer to the start of the text to process. - * state: Free variable for caller to use (can be NULL). - */ -MF_EXTERN void mf_wordwrap(const struct mf_font_s *font, int16_t width, - mf_str text, mf_line_callback_t callback, void *state); - -void mf_text_draw_area(const struct mf_font_s *font, int16_t width, - mf_str text, int *total_height_in_rows, - int *max_pixels_per_row); -#endif +/* Word wrapping algorithm with UTF-8 support. More than just a basic greedy + * word-wrapper: it attempts to balance consecutive lines as pairs. + */ + +#ifndef _MF_WORDWRAP_H_ +#define _MF_WORDWRAP_H_ + +#include "mf_rlefont.h" +#include + +/* Callback function for handling each line. + * + * line: Pointer to the beginning of the string for this line. + * count: Number of characters on the line. + * state: Free variable that was passed to wordwrap(). + * + * Returns: true to continue, false to stop after this line. + */ +typedef bool (*mf_line_callback_t) (mf_str line, uint16_t count, + void *state); + +/* Word wrap a piece of text. Calls the callback function for each line. + * + * font: Font to use for metrics. + * width: Maximum line width in pixels. + * text: Pointer to the start of the text to process. + * state: Free variable for caller to use (can be NULL). + */ +MF_EXTERN void mf_wordwrap(const struct mf_font_s *font, int16_t width, + mf_str text, mf_line_callback_t callback, void *state); + +void mf_text_draw_area(const struct mf_font_s *font, int16_t width, + mf_str text, int *total_height_in_rows, + int *max_pixels_per_row); +#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/rle_font_read.c b/bsp/sdk_overlay/middleware/vglite/font/rle_font_read.c similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/rle_font_read.c rename to bsp/sdk_overlay/middleware/vglite/font/rle_font_read.c index bffb081..6869feb 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/rle_font_read.c +++ b/bsp/sdk_overlay/middleware/vglite/font/rle_font_read.c @@ -1,716 +1,716 @@ -/**************************************************************************** -* -* The MIT License (MIT) -* -* Copyright 2020 NXP -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -/** Include Files */ -#include -#include -#include -#include -#include "FreeRTOS.h" -#include "vg_lite.h" -#include "buf_reader.h" -#include "vg_lite_text.h" -#include "vft_draw.h" -#include "vft_debug.h" - -/** Macros */ -#define __COUNTOF(x) (sizeof(x)/sizeof(x[0])) -#define MAX_SYSTEM_FONTS (8) - -#define RCD_ALLOC(x) _mem_allocate(x) -#define RCD_FREE(x) _mem_free(x) - -#ifdef ENABLE_DEBUG_TRACE -static int g_id; - -#define DBG_ID() (g_id) -#define DBG_INC_ID() (g_id++) -#define DBG_SET_ID(x) g_id = x -#else - -#define DBG_ID() (0) -#define DBG_INC_ID() (0) -#define DBG_SET_ID(x) -#endif - -#if APP_ENABLE_SDCARD -#define sprintf_s snprintf -#endif - -/** Data structures */ -typedef struct font_height_list { - const char font_height; - const char ref_font_height; - const char ref_font_scale; -} font_height_list_t; - -typedef struct font_info_internal { - /* Variable shared between user and driver */ - vg_lite_font_params_t font_params; - /* any additional variables internal to driver */ - int valid; - /* Internal loaded raster font */ - struct mf_font_s *_raster_font; - /* Internal loaded vector font */ - font_face_desc_t *_vector_font; -}font_info_internal_t; - -/** Internal or external API prototypes */ - -/** Globals */ -static font_info_internal_t s_device_fonts[MAX_SYSTEM_FONTS]; - -/** Local function prototypes */ -int read_rle_font_header(bufferred_reader_t *f, struct mf_font_s* font); -int read_rle_font_from_buffer(char *buf, int size, struct mf_font_s* font); -int load_raster_font(char *data, int data_len, struct mf_font_s** font); - -int read_8b(bufferred_reader_t *f, uint8_t* pdata); -int read_16b(bufferred_reader_t *f, uint16_t* pword); -int read_32b(bufferred_reader_t *f, uint32_t* pword); -int read_16b_blob(bufferred_reader_t *f, uint16_t** ary, uint32_t* ary_len); -int read_8b_blob(bufferred_reader_t *f, uint8_t** ary, uint32_t* ary_len); -int free_rle_font_memory(struct mf_font_s** font); -vg_lite_error_t vg_lite_free_font_memory(vg_lite_font_t font); -vg_lite_error_t vg_lite_load_font_data(vg_lite_font_t font, int font_height); - -/** Externs if any */ - -/** Code section */ -vg_lite_font_t vg_lite_find_font( - char *font_name, - eFontWeight_t font_weight, - eFontStretch_t font_stretch, - eFontStyle_t font_style, - int font_height); - -vg_lite_error_t vg_lite_register_font(vg_lite_font_t *font, - vg_lite_font_params_t *params) -{ - int i; - int free_entry = VG_LITE_INVALID_FONT; - - if (font != NULL) - *font = VG_LITE_INVALID_FONT; - - /* Check if font is already registered */ - for (i=0; iname, - strlen(s_device_fonts[i].font_params.name)) == 0) - { - return VG_LITE_ALREADY_EXISTS; - } - } else { - printf("Corrupt font table\n"); - return VG_LITE_INVALID_ARGUMENT; - } - } - - /* Check if list is completely full or not */ - if ( i == MAX_SYSTEM_FONTS && free_entry == VG_LITE_INVALID_FONT) { - /* Font List descriptor exhausted */ - return VG_LITE_OUT_OF_RESOURCES; - } else { - /* Add new font in global table */ - memcpy(&s_device_fonts[free_entry].font_params, params, sizeof(vg_lite_font_params_t)); - s_device_fonts[free_entry].valid = 1; -/* - Loading font here leads to low run-time memory, we may need to characterize memory usage - e.g. pure path test don't require font, eventhrough application registers them -*/ -#if 0 - error = vg_lite_load_font_data(free_entry, params->font_height); - if ( error != 0 ) { - s_device_fonts[free_entry].valid = 0; - return error; - } -#endif - } - - if (font != NULL) - *font = free_entry; - - return VG_LITE_SUCCESS; -} - -int vg_lite_is_font_valid(vg_lite_font_t font) -{ - if (font < MAX_SYSTEM_FONTS) { - if (s_device_fonts[font].valid == 1) - return 0; - } - return VG_LITE_INVALID_ARGUMENT; -} - -int vg_lite_is_vector_font(vg_lite_font_t font) -{ - if (font < MAX_SYSTEM_FONTS) { - if (s_device_fonts[font].valid == 1) - return (s_device_fonts[font].font_params.font_type == - eFontTypeVector); - else - return 0; - } - return VG_LITE_INVALID_ARGUMENT;; -} - -vg_lite_error_t vg_lite_unregister_font(vg_lite_font_t font) -{ - if (vg_lite_is_font_valid(font) != 0 ) { - /* Font not found */ - return VG_LITE_INVALID_ARGUMENT;; - } - - vg_lite_free_font_memory(font); - s_device_fonts[font].valid = 0; - return VG_LITE_SUCCESS; -} - -char *vg_lite_get_font_name(vg_lite_font_t font) -{ - if ( vg_lite_is_font_valid(font) != 0 ) { - return NULL; - } - - return (char *)s_device_fonts[font].font_params.name; -} - -vg_lite_error_t vg_lite_free_font_memory(vg_lite_font_t font) -{ - if ( vg_lite_is_font_valid(font) != 0 ) { - /* Font not found */ - return VG_LITE_INVALID_ARGUMENT; - } - switch (s_device_fonts[font].font_params.font_type) { - case eFontTypeVector: - if ( s_device_fonts[font]._vector_font != NULL ) { - vft_unload(s_device_fonts[font]._vector_font); - s_device_fonts[font]._vector_font = NULL; - } - break; - case eFontTypeRaster: - if ( s_device_fonts[font]._raster_font != NULL ) { - free_rle_font_memory(&s_device_fonts[font]._raster_font); - s_device_fonts[font]._raster_font = NULL; - } - break; - } - - return VG_LITE_SUCCESS; -} - -font_face_desc_t *_vg_lite_get_vector_font(vg_lite_font_t font) -{ - if ( vg_lite_is_font_valid(font) != 0 ) { - return NULL; - } - - return s_device_fonts[font]._vector_font; -} - -struct mf_font_s *_vg_lite_get_raster_font(vg_lite_font_t font) -{ - if ( vg_lite_is_font_valid(font) != 0 ) { - return NULL; - } - - return s_device_fonts[font]._raster_font; -} - -vg_lite_error_t vg_lite_load_font_data(vg_lite_font_t font, int font_height) -{ - if ( vg_lite_is_font_valid(font) != 0 ) { - /* Font not found */ - return VG_LITE_INVALID_ARGUMENT; - } - - switch (s_device_fonts[font].font_params.font_type) { - case eFontTypeVector: - if (s_device_fonts[font]._vector_font == NULL ) { - //printf("Loading vector font : [%s]\n", - // s_device_fonts[font].font_params.name); - s_device_fonts[font]._vector_font = - vft_load_from_buffer( - s_device_fonts[font].font_params.data, - s_device_fonts[font].font_params.data_len); - if ( s_device_fonts[font]._vector_font == NULL ) { - return VG_LITE_INVALID_ARGUMENT; - } - } - return VG_LITE_SUCCESS; - case eFontTypeRaster: - if (s_device_fonts[font]._raster_font == NULL ) { - //printf("Loading raster font : [%s]\n", - // s_device_fonts[font].font_params.name); - /* Raster fonts height should match */ - if ( font_height == s_device_fonts[font].font_params.font_height && - load_raster_font( - s_device_fonts[font].font_params.data, - s_device_fonts[font].font_params.data_len, - &s_device_fonts[font]._raster_font) != 0) - { - return VG_LITE_INVALID_ARGUMENT; - } - } - return VG_LITE_SUCCESS; - } - return VG_LITE_INVALID_ARGUMENT; -} - - -vg_lite_font_t vg_lite_find_font( - char *font_name_list, - eFontWeight_t font_weight, - eFontStretch_t font_stretch, - eFontStyle_t font_style, - int font_height) -{ - int i; - char tmp_data; - int font_found = 0; - int end_pos = 0; /* End position of font name */ - char *font_name; - /* - printf("Font params: [%s],%d, %d, %d, %d\n", - font_name_list, - font_weight, - font_stretch, - font_style, - font_height); - */ - - /* While probing font, if required font is found, then - only keep that name in supplied font list */ - - /* Split and extract font name one-by-one */ - font_name = font_name_list; - while (font_found == 0 && - font_name[end_pos] != '\0') - { - tmp_data = '\0'; - /* Scan for seperator */ - while (font_name[end_pos] != '\0') { - if (font_name[end_pos] == ',' || font_name[end_pos] == ' ' || - font_name[end_pos] == '\t') - { - tmp_data = font_name[end_pos]; - font_name[end_pos] = '\0'; - break; - } - end_pos++; - } - - /* Search for exact font-name match */ - for (i=0; i<__COUNTOF(s_device_fonts); i++) { - if (s_device_fonts[i].valid == 0) - continue; - - /* For vector font only compare name */ - if (s_device_fonts[i].font_params.font_type == eFontTypeVector ) { - if ( strlen(font_name) > 0 && - strcmp(font_name, - s_device_fonts[i].font_params.name) == 0) - { - font_name[end_pos] = tmp_data; /* Restor delimeter */ - return i; - } - } else { - /* For raster font compare all properties */ - if (s_device_fonts[i].font_params.font_weight == font_weight && - s_device_fonts[i].font_params.font_stretch == font_stretch && - s_device_fonts[i].font_params.font_style == font_style ) - { - if ( strlen(font_name) > 0 && - strcmp(font_name, - s_device_fonts[i].font_params.name) == 0) - { - font_name[end_pos] = tmp_data; /* Restor delimeter */ - - if (s_device_fonts[i].font_params.font_height == font_height) - { - return i; - } - /* Update font_name_list to improve future searches */ - strncpy(font_name_list, font_name, strlen(font_name)+1); - } - } - } - } - /* Continue searching for other font entries */ - font_name[end_pos] = tmp_data; - font_name += (end_pos + 1); - end_pos = 0; - } - printf("WARNING: [%s] Font not found\r\n",font_name_list); - - return VG_LITE_INVALID_FONT; -} - -void vg_lite_text_init(void) -{ - static int font_table_ready = 0; - - if (font_table_ready) - return; - - /* Initialize font table */ - memset(s_device_fonts, 0, MAX_SYSTEM_FONTS * sizeof(font_info_internal_t)); - font_table_ready = 1; -} - -/* Read-Write 8-bit unsigned int data */ -int read_8b(bufferred_reader_t * f, uint8_t* pdata) -{ - bufferred_fread(pdata, 1, 1, f); - TRACE_DBG(("%d) 8b: fp=%08x %d %d\r\n", DBG_INC_ID(), - bufferred_ftell(f) - 1, 1, *pdata)); - return 1; -} - -/* Read-Write 16-bit unsigned int data */ -int read_16b(bufferred_reader_t * f, uint16_t* pword) -{ - uint8_t buf[4]; - uint16_t word; - - bufferred_fread(buf, 2, 1, f); - word = 0; word += buf[1]; - word <<= 8; word += buf[0]; - - TRACE_DBG(("%d) 16b: fp=%08x %d %d\r\n", DBG_INC_ID(), - bufferred_ftell(f)-2, 2, word)); - *pword = word; - return 2; -} - -/* Read-write 32-bit unsigned int data */ -int read_32b(bufferred_reader_t * f, uint32_t* pword) -{ - uint8_t buf[4]; - uint32_t word; - - bufferred_fread(buf, 4, 1, f); - word = 0; word += buf[3]; - word <<= 8; word += buf[2]; - word <<= 8; word += buf[1]; - word <<= 8; word += buf[0]; - - *pword = word; - TRACE_DBG(("%d) 32b: fp=%08x %d %d\r\n", DBG_INC_ID(), - bufferred_ftell(f) - 4, 4, - word)); - return 4; -} - -int read_16b_blob(bufferred_reader_t * f, uint16_t** ary, uint32_t* ary_len) -{ - uint16_t blob_len = 0; - - *ary_len = 0; - bufferred_fread(&blob_len, 1, sizeof(uint16_t), f); - *ary = (uint16_t *)RCD_ALLOC(blob_len * sizeof(uint16_t)); /* Malloc must be aligned on 2 byte boundary */ - if (*ary == NULL) { - TRACE_ERR(("ERROR: malloc failed\n"));; - return VG_LITE_OUT_OF_MEMORY; - } - if ((((unsigned long)*ary) & 0x1) != 0) { - TRACE_ERR(("ERROR: malloc pointer not 2 byte aligned\n"));; - return VG_LITE_NOT_ALIGNED; - } - TRACE_DBG(("%d ) 16b_blob: fp=%08x %d\r\n", DBG_INC_ID(), bufferred_ftell(f)-2, - (int)blob_len)); - bufferred_fread(*ary, 2, blob_len, f); - *ary_len = blob_len * 2; - - return blob_len + 2; /* Actual bytes read from file */ -} - -int read_8b_blob(bufferred_reader_t * f, uint8_t** ary, uint32_t *ary_len) -{ - uint16_t blob_len = 0; - uint8_t* p_tmp = (uint8_t *)NULL; - bufferred_fread(&blob_len, 1, sizeof(uint16_t), f); - //TRACE_DBG(("%d) 8b_blob: %d\r\n", DBG_INC_ID(), blob_len)); - p_tmp = (uint8_t *)RCD_ALLOC(blob_len+1); - if (p_tmp == NULL) { - TRACE_ERR(("ERROR: malloc failed\n"));; - return VG_LITE_OUT_OF_MEMORY; - } - TRACE_DBG(("%d ) 8b_blob: fp=%08x %d\r\n", DBG_INC_ID(), bufferred_ftell(f)-2, - (int)blob_len)); - bufferred_fread(p_tmp, 1, blob_len, f); - p_tmp[blob_len] = 0; - *ary = p_tmp; - - return blob_len + 2; /* Actual bytes read from file */ -} - -#define EXIT_IF_NEGATIVE(param) if ((ret = param) < 0) return ret; - -int read_rle_font_header(bufferred_reader_t * f, struct mf_font_s* font) -{ - int raw_header_offset = 0; - struct mf_rlefont_s* mfont = (struct mf_rlefont_s*)font; - uint32_t size = 0; - int ret = 0; - - TRACE_DBG(("** %s\r\n", __FUNCTION__)); - DBG_SET_ID(0); - - EXIT_IF_NEGATIVE(read_8b_blob(f, (uint8_t **)&font->full_name, &size)); - raw_header_offset += ret; /* font.full_name */ - - EXIT_IF_NEGATIVE(read_8b_blob(f, (uint8_t **)&font->short_name, &size)); - raw_header_offset += ret; /* font.short_name */ - - EXIT_IF_NEGATIVE(read_8b(f, &font->width)); - raw_header_offset += 1; /* font.width */ - - EXIT_IF_NEGATIVE(read_8b(f, &font->height)); - raw_header_offset += 1; /* font.height */ - - EXIT_IF_NEGATIVE(read_8b(f, &font->min_x_advance)); - raw_header_offset += 1; /* font.min_x_advance */ - - EXIT_IF_NEGATIVE(read_8b(f, &font->max_x_advance)); - raw_header_offset += 1; /* font.max_x_advance */ - - EXIT_IF_NEGATIVE(read_8b(f, (uint8_t *)&font->baseline_x)); - raw_header_offset += 1; /* font.baseline_x */ - - EXIT_IF_NEGATIVE(read_8b(f, &font->baseline_y)); - raw_header_offset += 1; /* font.baseline_y */ - - EXIT_IF_NEGATIVE(read_8b(f, &font->line_height)); - raw_header_offset += 1; /* font.line_height */ - - EXIT_IF_NEGATIVE(read_8b(f, &font->flags)); - raw_header_offset += 1; /* font.flags */ - - EXIT_IF_NEGATIVE(read_16b(f, &font->fallback_character)); - raw_header_offset += 2; /* font.fallback_character */ - - EXIT_IF_NEGATIVE(read_8b(f, &(mfont->version))); - raw_header_offset += 1; /* mf_rlefont_s.version */ - - /* Other mf_rlefont_s variables */ - uint16_t value = 0; - EXIT_IF_NEGATIVE(read_16b(f, &value)); //&mfont->dictionary_data_size)); - mfont->dictionary_data_size = value; - raw_header_offset += 2; /* mf_rlefont_s.dictionary_data_size */ - - EXIT_IF_NEGATIVE(read_32b(f, &mfont->dictionary_data_fp_offset)); - raw_header_offset += 4; /* mf_rlefont_s.dictionary_data_fp_offset */ - - value = 0; - EXIT_IF_NEGATIVE(read_16b(f, &value)); //mfont->dictionary_offsets_size)); - mfont->dictionary_offsets_size = value; - raw_header_offset += 2; /* mf_rlefont_s.dictionary_data_size */ - - EXIT_IF_NEGATIVE(read_32b(f, &mfont->dictionary_offsets_fp_offset)); - raw_header_offset += 4; /* mf_rlefont_s.dictionary_data_fp_offset */ - - EXIT_IF_NEGATIVE(read_8b(f, &mfont->rle_entry_count)); - raw_header_offset += 1; /* mf_rlefont_s.rle_entry_count */ - - EXIT_IF_NEGATIVE(read_8b(f, &mfont->dict_entry_count)); - raw_header_offset += 1; /* mf_rlefont_s.dict_entry_count */ - - EXIT_IF_NEGATIVE(read_8b(f, &mfont->char_range_count)); - raw_header_offset += 1; /* mf_rlefont_s.char_range_count */ - - mfont->char_ranges = (struct mf_rlefont_char_range_s *)RCD_ALLOC(sizeof(struct mf_rlefont_char_range_s)* mfont->char_range_count); - memset(mfont->char_ranges, 0, sizeof(struct mf_rlefont_char_range_s) * mfont->char_range_count); - - /* Skip size of ranges */ - for (int r = 0; r < mfont->char_range_count; r++) { - EXIT_IF_NEGATIVE(read_16b(f, &mfont->char_ranges[r].first_char)); - raw_header_offset += 2; /* mf_rlefont_s.char_ranges[r].first_char */ - - EXIT_IF_NEGATIVE(read_16b(f, &mfont->char_ranges[r].char_count)); - raw_header_offset += 2; /* mf_rlefont_s.char_ranges[r].char_count */ - - EXIT_IF_NEGATIVE(read_32b(f, &mfont->char_ranges[r].glyph_offsets_fp_offset)); - raw_header_offset += 4; /* mf_rlefont_s.char_ranges[r].glyph_offsets_fp_offset */ - - EXIT_IF_NEGATIVE(read_32b(f, &mfont->char_ranges[r].glyph_offsets_size)); - raw_header_offset += 4; /* mf_rlefont_s.char_ranges[r].glyph_offsets_size */ - - EXIT_IF_NEGATIVE(read_32b(f, &mfont->char_ranges[r].glyph_data_fp_offset)); - raw_header_offset += 4; /* mf_rlefont_s.char_ranges[r].glyph_offsets_fp_offset */ - - EXIT_IF_NEGATIVE(read_32b(f, &mfont->char_ranges[r].glyph_data_size)); - raw_header_offset += 4; /* mf_rlefont_s.char_ranges[r].glyph_offsets_size */ - } - return raw_header_offset; -} - -/* Writes a BMP file. The data is assumed to be 8-bit grayscale. */ -int read_rle_font_from_buffer(char *buff, int size, struct mf_font_s* font) -{ - struct mf_rlefont_s* mfont = (struct mf_rlefont_s*)font; - bufferred_reader_t f_obj; - bufferred_reader_t * f = &f_obj; - int raw_header_offset = 0; - int fp_offset; - int ret; - - DBG_SET_ID(0); - - /* No need to dynamically allocate small descriptor */ - if ( bufferred_fopen(f, buff, size) < 0 ) { - /* Font file open failed */ - return VG_LITE_INVALID_ARGUMENT; - } - - raw_header_offset = read_rle_font_header(f, font); - if (mfont->dictionary_data_fp_offset != raw_header_offset) { - TRACE_ERR(("ERROR: dictonary offset is different")); - } - TRACE_DBG(("** %s\r\n", __FUNCTION__)); - DBG_SET_ID(0); - - /* Skip header portion */ - bufferred_fseek(f, raw_header_offset, SEEK_SET); - /* Write dictionary entries */ - fp_offset = raw_header_offset; - TRACE_DBG(("dictionary_data_fp_offset=%08x %08x\r\n", - mfont->dictionary_data_fp_offset, bufferred_ftell(f))); - //mfont->dictionary_data_fp_offset = fp_offset; - EXIT_IF_NEGATIVE(read_8b_blob(f, &mfont->dictionary_data, - &mfont->dictionary_data_size)); - fp_offset += mfont->dictionary_data_size + 2; - - //mfont->dictionary_offsets_fp_offset = fp_offset; - TRACE_DBG(("dictionary_offsets_fp_offset=%08x %08x\r\n", - mfont->dictionary_offsets_fp_offset, bufferred_ftell(f))); - EXIT_IF_NEGATIVE(read_16b_blob(f, &mfont->dictionary_offsets, - &mfont->dictionary_offsets_size)); - fp_offset += mfont->dictionary_offsets_size + 2; - - /* Write range entries */ - for (int r = 0; r < mfont->char_range_count; r++) { - //mfont->char_ranges[r].glyph_offsets_fp_offset = fp_offset; - TRACE_DBG(("mfont->char_ranges[%d].glyph_offsets=%08x %08x\r\n", r, - mfont->char_ranges[r].glyph_offsets_fp_offset, bufferred_ftell(f))); - EXIT_IF_NEGATIVE(read_16b_blob(f, &mfont->char_ranges[r].glyph_offsets, - &mfont->char_ranges[r].glyph_offsets_size)); - fp_offset += mfont->char_ranges[r].glyph_offsets_size + 2; - - //mfont->char_ranges[r].glyph_data_fp_offset = fp_offset; - TRACE_DBG(("mfont->char_ranges[%d].glyph_data_fp_offset=%08x %08x\r\n", - r, - mfont->char_ranges[r].glyph_data_fp_offset, bufferred_ftell(f))); - EXIT_IF_NEGATIVE(read_8b_blob(f, &mfont->char_ranges[r].glyph_data,\ - &mfont->char_ranges[r].glyph_data_size)); - fp_offset += mfont->char_ranges[r].glyph_data_size + 2; - } - - bufferred_fclose(f); - return 0; -} - -int load_raster_font(char *data, int data_len, struct mf_font_s** font) -{ - int ret; - - /* Allocate font memory */ - *font = (struct mf_font_s*)RCD_ALLOC(sizeof(struct mf_rlefont_s)); - if (*font == NULL) { - return VG_LITE_OUT_OF_MEMORY; - } - memset(*font, 0, sizeof(struct mf_rlefont_s)); - - /* Load font from file */ - ret = read_rle_font_from_buffer(data, - data_len, *font); - if (ret < 0) { - return ret; - } - - /* Update generic char width pointers of mculib */ - uint8_t mf_rlefont_character_width(const struct mf_font_s* font, - uint16_t character); - uint8_t mf_rlefont_render_character(const struct mf_font_s* font, - int16_t x0, int16_t y0, - uint16_t character, - mf_pixel_callback_t callback, - void* state); - - (*font)->character_width = &mf_rlefont_character_width; - (*font)->render_character = &mf_rlefont_render_character; - - - return 0; -} - -int free_rle_font_memory(struct mf_font_s** font) -{ - struct mf_rlefont_s* mfont = (struct mf_rlefont_s*)(*font); - - RCD_FREE(mfont->font.full_name); - RCD_FREE(mfont->font.short_name); - RCD_FREE(mfont->dictionary_data); - RCD_FREE(mfont->dictionary_offsets); - for (int r = 0; r < mfont->char_range_count; r++) { - RCD_FREE(mfont->char_ranges[r].glyph_offsets); - RCD_FREE(mfont->char_ranges[r].glyph_data); - } - #ifdef DEBUG_RESET_DATASTRUCTURE_ON_FREE - memset(mfont->char_ranges); - #endif - RCD_FREE(mfont->char_ranges); - - #ifdef DEBUG_RESET_DATASTRUCTURE_ON_FREE - memset(mfont); - #endif - RCD_FREE(mfont); - - *font = NULL; - return 0; -} - -void vg_lite_unload_font_data(void) -{ - for(int i=0; i +#include +#include +#include +#include "FreeRTOS.h" +#include "vg_lite.h" +#include "buf_reader.h" +#include "vg_lite_text.h" +#include "vft_draw.h" +#include "vft_debug.h" + +/** Macros */ +#define __COUNTOF(x) (sizeof(x)/sizeof(x[0])) +#define MAX_SYSTEM_FONTS (8) + +#define RCD_ALLOC(x) _mem_allocate(x) +#define RCD_FREE(x) _mem_free(x) + +#ifdef ENABLE_DEBUG_TRACE +static int g_id; + +#define DBG_ID() (g_id) +#define DBG_INC_ID() (g_id++) +#define DBG_SET_ID(x) g_id = x +#else + +#define DBG_ID() (0) +#define DBG_INC_ID() (0) +#define DBG_SET_ID(x) +#endif + +#if APP_ENABLE_SDCARD +#define sprintf_s snprintf +#endif + +/** Data structures */ +typedef struct font_height_list { + const char font_height; + const char ref_font_height; + const char ref_font_scale; +} font_height_list_t; + +typedef struct font_info_internal { + /* Variable shared between user and driver */ + vg_lite_font_params_t font_params; + /* any additional variables internal to driver */ + int valid; + /* Internal loaded raster font */ + struct mf_font_s *_raster_font; + /* Internal loaded vector font */ + font_face_desc_t *_vector_font; +}font_info_internal_t; + +/** Internal or external API prototypes */ + +/** Globals */ +static font_info_internal_t s_device_fonts[MAX_SYSTEM_FONTS]; + +/** Local function prototypes */ +int read_rle_font_header(bufferred_reader_t *f, struct mf_font_s* font); +int read_rle_font_from_buffer(char *buf, int size, struct mf_font_s* font); +int load_raster_font(char *data, int data_len, struct mf_font_s** font); + +int read_8b(bufferred_reader_t *f, uint8_t* pdata); +int read_16b(bufferred_reader_t *f, uint16_t* pword); +int read_32b(bufferred_reader_t *f, uint32_t* pword); +int read_16b_blob(bufferred_reader_t *f, uint16_t** ary, uint32_t* ary_len); +int read_8b_blob(bufferred_reader_t *f, uint8_t** ary, uint32_t* ary_len); +int free_rle_font_memory(struct mf_font_s** font); +vg_lite_error_t vg_lite_free_font_memory(vg_lite_font_t font); +vg_lite_error_t vg_lite_load_font_data(vg_lite_font_t font, int font_height); + +/** Externs if any */ + +/** Code section */ +vg_lite_font_t vg_lite_find_font( + char *font_name, + eFontWeight_t font_weight, + eFontStretch_t font_stretch, + eFontStyle_t font_style, + int font_height); + +vg_lite_error_t vg_lite_register_font(vg_lite_font_t *font, + vg_lite_font_params_t *params) +{ + int i; + int free_entry = VG_LITE_INVALID_FONT; + + if (font != NULL) + *font = VG_LITE_INVALID_FONT; + + /* Check if font is already registered */ + for (i=0; iname, + strlen(s_device_fonts[i].font_params.name)) == 0) + { + return VG_LITE_ALREADY_EXISTS; + } + } else { + printf("Corrupt font table\n"); + return VG_LITE_INVALID_ARGUMENT; + } + } + + /* Check if list is completely full or not */ + if ( i == MAX_SYSTEM_FONTS && free_entry == VG_LITE_INVALID_FONT) { + /* Font List descriptor exhausted */ + return VG_LITE_OUT_OF_RESOURCES; + } else { + /* Add new font in global table */ + memcpy(&s_device_fonts[free_entry].font_params, params, sizeof(vg_lite_font_params_t)); + s_device_fonts[free_entry].valid = 1; +/* + Loading font here leads to low run-time memory, we may need to characterize memory usage + e.g. pure path test don't require font, eventhrough application registers them +*/ +#if 0 + error = vg_lite_load_font_data(free_entry, params->font_height); + if ( error != 0 ) { + s_device_fonts[free_entry].valid = 0; + return error; + } +#endif + } + + if (font != NULL) + *font = free_entry; + + return VG_LITE_SUCCESS; +} + +int vg_lite_is_font_valid(vg_lite_font_t font) +{ + if (font < MAX_SYSTEM_FONTS) { + if (s_device_fonts[font].valid == 1) + return 0; + } + return VG_LITE_INVALID_ARGUMENT; +} + +int vg_lite_is_vector_font(vg_lite_font_t font) +{ + if (font < MAX_SYSTEM_FONTS) { + if (s_device_fonts[font].valid == 1) + return (s_device_fonts[font].font_params.font_type == + eFontTypeVector); + else + return 0; + } + return VG_LITE_INVALID_ARGUMENT;; +} + +vg_lite_error_t vg_lite_unregister_font(vg_lite_font_t font) +{ + if (vg_lite_is_font_valid(font) != 0 ) { + /* Font not found */ + return VG_LITE_INVALID_ARGUMENT;; + } + + vg_lite_free_font_memory(font); + s_device_fonts[font].valid = 0; + return VG_LITE_SUCCESS; +} + +char *vg_lite_get_font_name(vg_lite_font_t font) +{ + if ( vg_lite_is_font_valid(font) != 0 ) { + return NULL; + } + + return (char *)s_device_fonts[font].font_params.name; +} + +vg_lite_error_t vg_lite_free_font_memory(vg_lite_font_t font) +{ + if ( vg_lite_is_font_valid(font) != 0 ) { + /* Font not found */ + return VG_LITE_INVALID_ARGUMENT; + } + switch (s_device_fonts[font].font_params.font_type) { + case eFontTypeVector: + if ( s_device_fonts[font]._vector_font != NULL ) { + vft_unload(s_device_fonts[font]._vector_font); + s_device_fonts[font]._vector_font = NULL; + } + break; + case eFontTypeRaster: + if ( s_device_fonts[font]._raster_font != NULL ) { + free_rle_font_memory(&s_device_fonts[font]._raster_font); + s_device_fonts[font]._raster_font = NULL; + } + break; + } + + return VG_LITE_SUCCESS; +} + +font_face_desc_t *_vg_lite_get_vector_font(vg_lite_font_t font) +{ + if ( vg_lite_is_font_valid(font) != 0 ) { + return NULL; + } + + return s_device_fonts[font]._vector_font; +} + +struct mf_font_s *_vg_lite_get_raster_font(vg_lite_font_t font) +{ + if ( vg_lite_is_font_valid(font) != 0 ) { + return NULL; + } + + return s_device_fonts[font]._raster_font; +} + +vg_lite_error_t vg_lite_load_font_data(vg_lite_font_t font, int font_height) +{ + if ( vg_lite_is_font_valid(font) != 0 ) { + /* Font not found */ + return VG_LITE_INVALID_ARGUMENT; + } + + switch (s_device_fonts[font].font_params.font_type) { + case eFontTypeVector: + if (s_device_fonts[font]._vector_font == NULL ) { + //printf("Loading vector font : [%s]\n", + // s_device_fonts[font].font_params.name); + s_device_fonts[font]._vector_font = + vft_load_from_buffer( + s_device_fonts[font].font_params.data, + s_device_fonts[font].font_params.data_len); + if ( s_device_fonts[font]._vector_font == NULL ) { + return VG_LITE_INVALID_ARGUMENT; + } + } + return VG_LITE_SUCCESS; + case eFontTypeRaster: + if (s_device_fonts[font]._raster_font == NULL ) { + //printf("Loading raster font : [%s]\n", + // s_device_fonts[font].font_params.name); + /* Raster fonts height should match */ + if ( font_height == s_device_fonts[font].font_params.font_height && + load_raster_font( + s_device_fonts[font].font_params.data, + s_device_fonts[font].font_params.data_len, + &s_device_fonts[font]._raster_font) != 0) + { + return VG_LITE_INVALID_ARGUMENT; + } + } + return VG_LITE_SUCCESS; + } + return VG_LITE_INVALID_ARGUMENT; +} + + +vg_lite_font_t vg_lite_find_font( + char *font_name_list, + eFontWeight_t font_weight, + eFontStretch_t font_stretch, + eFontStyle_t font_style, + int font_height) +{ + int i; + char tmp_data; + int font_found = 0; + int end_pos = 0; /* End position of font name */ + char *font_name; + /* + printf("Font params: [%s],%d, %d, %d, %d\n", + font_name_list, + font_weight, + font_stretch, + font_style, + font_height); + */ + + /* While probing font, if required font is found, then + only keep that name in supplied font list */ + + /* Split and extract font name one-by-one */ + font_name = font_name_list; + while (font_found == 0 && + font_name[end_pos] != '\0') + { + tmp_data = '\0'; + /* Scan for seperator */ + while (font_name[end_pos] != '\0') { + if (font_name[end_pos] == ',' || font_name[end_pos] == ' ' || + font_name[end_pos] == '\t') + { + tmp_data = font_name[end_pos]; + font_name[end_pos] = '\0'; + break; + } + end_pos++; + } + + /* Search for exact font-name match */ + for (i=0; i<__COUNTOF(s_device_fonts); i++) { + if (s_device_fonts[i].valid == 0) + continue; + + /* For vector font only compare name */ + if (s_device_fonts[i].font_params.font_type == eFontTypeVector ) { + if ( strlen(font_name) > 0 && + strcmp(font_name, + s_device_fonts[i].font_params.name) == 0) + { + font_name[end_pos] = tmp_data; /* Restor delimeter */ + return i; + } + } else { + /* For raster font compare all properties */ + if (s_device_fonts[i].font_params.font_weight == font_weight && + s_device_fonts[i].font_params.font_stretch == font_stretch && + s_device_fonts[i].font_params.font_style == font_style ) + { + if ( strlen(font_name) > 0 && + strcmp(font_name, + s_device_fonts[i].font_params.name) == 0) + { + font_name[end_pos] = tmp_data; /* Restor delimeter */ + + if (s_device_fonts[i].font_params.font_height == font_height) + { + return i; + } + /* Update font_name_list to improve future searches */ + strncpy(font_name_list, font_name, strlen(font_name)+1); + } + } + } + } + /* Continue searching for other font entries */ + font_name[end_pos] = tmp_data; + font_name += (end_pos + 1); + end_pos = 0; + } + printf("WARNING: [%s] Font not found\r\n",font_name_list); + + return VG_LITE_INVALID_FONT; +} + +void vg_lite_text_init(void) +{ + static int font_table_ready = 0; + + if (font_table_ready) + return; + + /* Initialize font table */ + memset(s_device_fonts, 0, MAX_SYSTEM_FONTS * sizeof(font_info_internal_t)); + font_table_ready = 1; +} + +/* Read-Write 8-bit unsigned int data */ +int read_8b(bufferred_reader_t * f, uint8_t* pdata) +{ + bufferred_fread(pdata, 1, 1, f); + TRACE_DBG(("%d) 8b: fp=%08x %d %d\r\n", DBG_INC_ID(), + bufferred_ftell(f) - 1, 1, *pdata)); + return 1; +} + +/* Read-Write 16-bit unsigned int data */ +int read_16b(bufferred_reader_t * f, uint16_t* pword) +{ + uint8_t buf[4]; + uint16_t word; + + bufferred_fread(buf, 2, 1, f); + word = 0; word += buf[1]; + word <<= 8; word += buf[0]; + + TRACE_DBG(("%d) 16b: fp=%08x %d %d\r\n", DBG_INC_ID(), + bufferred_ftell(f)-2, 2, word)); + *pword = word; + return 2; +} + +/* Read-write 32-bit unsigned int data */ +int read_32b(bufferred_reader_t * f, uint32_t* pword) +{ + uint8_t buf[4]; + uint32_t word; + + bufferred_fread(buf, 4, 1, f); + word = 0; word += buf[3]; + word <<= 8; word += buf[2]; + word <<= 8; word += buf[1]; + word <<= 8; word += buf[0]; + + *pword = word; + TRACE_DBG(("%d) 32b: fp=%08x %d %d\r\n", DBG_INC_ID(), + bufferred_ftell(f) - 4, 4, + word)); + return 4; +} + +int read_16b_blob(bufferred_reader_t * f, uint16_t** ary, uint32_t* ary_len) +{ + uint16_t blob_len = 0; + + *ary_len = 0; + bufferred_fread(&blob_len, 1, sizeof(uint16_t), f); + *ary = (uint16_t *)RCD_ALLOC(blob_len * sizeof(uint16_t)); /* Malloc must be aligned on 2 byte boundary */ + if (*ary == NULL) { + TRACE_ERR(("ERROR: malloc failed\n"));; + return VG_LITE_OUT_OF_MEMORY; + } + if ((((unsigned long)*ary) & 0x1) != 0) { + TRACE_ERR(("ERROR: malloc pointer not 2 byte aligned\n"));; + return VG_LITE_NOT_ALIGNED; + } + TRACE_DBG(("%d ) 16b_blob: fp=%08x %d\r\n", DBG_INC_ID(), bufferred_ftell(f)-2, + (int)blob_len)); + bufferred_fread(*ary, 2, blob_len, f); + *ary_len = blob_len * 2; + + return blob_len + 2; /* Actual bytes read from file */ +} + +int read_8b_blob(bufferred_reader_t * f, uint8_t** ary, uint32_t *ary_len) +{ + uint16_t blob_len = 0; + uint8_t* p_tmp = (uint8_t *)NULL; + bufferred_fread(&blob_len, 1, sizeof(uint16_t), f); + //TRACE_DBG(("%d) 8b_blob: %d\r\n", DBG_INC_ID(), blob_len)); + p_tmp = (uint8_t *)RCD_ALLOC(blob_len+1); + if (p_tmp == NULL) { + TRACE_ERR(("ERROR: malloc failed\n"));; + return VG_LITE_OUT_OF_MEMORY; + } + TRACE_DBG(("%d ) 8b_blob: fp=%08x %d\r\n", DBG_INC_ID(), bufferred_ftell(f)-2, + (int)blob_len)); + bufferred_fread(p_tmp, 1, blob_len, f); + p_tmp[blob_len] = 0; + *ary = p_tmp; + + return blob_len + 2; /* Actual bytes read from file */ +} + +#define EXIT_IF_NEGATIVE(param) if ((ret = param) < 0) return ret; + +int read_rle_font_header(bufferred_reader_t * f, struct mf_font_s* font) +{ + int raw_header_offset = 0; + struct mf_rlefont_s* mfont = (struct mf_rlefont_s*)font; + uint32_t size = 0; + int ret = 0; + + TRACE_DBG(("** %s\r\n", __FUNCTION__)); + DBG_SET_ID(0); + + EXIT_IF_NEGATIVE(read_8b_blob(f, (uint8_t **)&font->full_name, &size)); + raw_header_offset += ret; /* font.full_name */ + + EXIT_IF_NEGATIVE(read_8b_blob(f, (uint8_t **)&font->short_name, &size)); + raw_header_offset += ret; /* font.short_name */ + + EXIT_IF_NEGATIVE(read_8b(f, &font->width)); + raw_header_offset += 1; /* font.width */ + + EXIT_IF_NEGATIVE(read_8b(f, &font->height)); + raw_header_offset += 1; /* font.height */ + + EXIT_IF_NEGATIVE(read_8b(f, &font->min_x_advance)); + raw_header_offset += 1; /* font.min_x_advance */ + + EXIT_IF_NEGATIVE(read_8b(f, &font->max_x_advance)); + raw_header_offset += 1; /* font.max_x_advance */ + + EXIT_IF_NEGATIVE(read_8b(f, (uint8_t *)&font->baseline_x)); + raw_header_offset += 1; /* font.baseline_x */ + + EXIT_IF_NEGATIVE(read_8b(f, &font->baseline_y)); + raw_header_offset += 1; /* font.baseline_y */ + + EXIT_IF_NEGATIVE(read_8b(f, &font->line_height)); + raw_header_offset += 1; /* font.line_height */ + + EXIT_IF_NEGATIVE(read_8b(f, &font->flags)); + raw_header_offset += 1; /* font.flags */ + + EXIT_IF_NEGATIVE(read_16b(f, &font->fallback_character)); + raw_header_offset += 2; /* font.fallback_character */ + + EXIT_IF_NEGATIVE(read_8b(f, &(mfont->version))); + raw_header_offset += 1; /* mf_rlefont_s.version */ + + /* Other mf_rlefont_s variables */ + uint16_t value = 0; + EXIT_IF_NEGATIVE(read_16b(f, &value)); //&mfont->dictionary_data_size)); + mfont->dictionary_data_size = value; + raw_header_offset += 2; /* mf_rlefont_s.dictionary_data_size */ + + EXIT_IF_NEGATIVE(read_32b(f, &mfont->dictionary_data_fp_offset)); + raw_header_offset += 4; /* mf_rlefont_s.dictionary_data_fp_offset */ + + value = 0; + EXIT_IF_NEGATIVE(read_16b(f, &value)); //mfont->dictionary_offsets_size)); + mfont->dictionary_offsets_size = value; + raw_header_offset += 2; /* mf_rlefont_s.dictionary_data_size */ + + EXIT_IF_NEGATIVE(read_32b(f, &mfont->dictionary_offsets_fp_offset)); + raw_header_offset += 4; /* mf_rlefont_s.dictionary_data_fp_offset */ + + EXIT_IF_NEGATIVE(read_8b(f, &mfont->rle_entry_count)); + raw_header_offset += 1; /* mf_rlefont_s.rle_entry_count */ + + EXIT_IF_NEGATIVE(read_8b(f, &mfont->dict_entry_count)); + raw_header_offset += 1; /* mf_rlefont_s.dict_entry_count */ + + EXIT_IF_NEGATIVE(read_8b(f, &mfont->char_range_count)); + raw_header_offset += 1; /* mf_rlefont_s.char_range_count */ + + mfont->char_ranges = (struct mf_rlefont_char_range_s *)RCD_ALLOC(sizeof(struct mf_rlefont_char_range_s)* mfont->char_range_count); + memset(mfont->char_ranges, 0, sizeof(struct mf_rlefont_char_range_s) * mfont->char_range_count); + + /* Skip size of ranges */ + for (int r = 0; r < mfont->char_range_count; r++) { + EXIT_IF_NEGATIVE(read_16b(f, &mfont->char_ranges[r].first_char)); + raw_header_offset += 2; /* mf_rlefont_s.char_ranges[r].first_char */ + + EXIT_IF_NEGATIVE(read_16b(f, &mfont->char_ranges[r].char_count)); + raw_header_offset += 2; /* mf_rlefont_s.char_ranges[r].char_count */ + + EXIT_IF_NEGATIVE(read_32b(f, &mfont->char_ranges[r].glyph_offsets_fp_offset)); + raw_header_offset += 4; /* mf_rlefont_s.char_ranges[r].glyph_offsets_fp_offset */ + + EXIT_IF_NEGATIVE(read_32b(f, &mfont->char_ranges[r].glyph_offsets_size)); + raw_header_offset += 4; /* mf_rlefont_s.char_ranges[r].glyph_offsets_size */ + + EXIT_IF_NEGATIVE(read_32b(f, &mfont->char_ranges[r].glyph_data_fp_offset)); + raw_header_offset += 4; /* mf_rlefont_s.char_ranges[r].glyph_offsets_fp_offset */ + + EXIT_IF_NEGATIVE(read_32b(f, &mfont->char_ranges[r].glyph_data_size)); + raw_header_offset += 4; /* mf_rlefont_s.char_ranges[r].glyph_offsets_size */ + } + return raw_header_offset; +} + +/* Writes a BMP file. The data is assumed to be 8-bit grayscale. */ +int read_rle_font_from_buffer(char *buff, int size, struct mf_font_s* font) +{ + struct mf_rlefont_s* mfont = (struct mf_rlefont_s*)font; + bufferred_reader_t f_obj; + bufferred_reader_t * f = &f_obj; + int raw_header_offset = 0; + int fp_offset; + int ret; + + DBG_SET_ID(0); + + /* No need to dynamically allocate small descriptor */ + if ( bufferred_fopen(f, buff, size) < 0 ) { + /* Font file open failed */ + return VG_LITE_INVALID_ARGUMENT; + } + + raw_header_offset = read_rle_font_header(f, font); + if (mfont->dictionary_data_fp_offset != raw_header_offset) { + TRACE_ERR(("ERROR: dictonary offset is different")); + } + TRACE_DBG(("** %s\r\n", __FUNCTION__)); + DBG_SET_ID(0); + + /* Skip header portion */ + bufferred_fseek(f, raw_header_offset, SEEK_SET); + /* Write dictionary entries */ + fp_offset = raw_header_offset; + TRACE_DBG(("dictionary_data_fp_offset=%08x %08x\r\n", + mfont->dictionary_data_fp_offset, bufferred_ftell(f))); + //mfont->dictionary_data_fp_offset = fp_offset; + EXIT_IF_NEGATIVE(read_8b_blob(f, &mfont->dictionary_data, + &mfont->dictionary_data_size)); + fp_offset += mfont->dictionary_data_size + 2; + + //mfont->dictionary_offsets_fp_offset = fp_offset; + TRACE_DBG(("dictionary_offsets_fp_offset=%08x %08x\r\n", + mfont->dictionary_offsets_fp_offset, bufferred_ftell(f))); + EXIT_IF_NEGATIVE(read_16b_blob(f, &mfont->dictionary_offsets, + &mfont->dictionary_offsets_size)); + fp_offset += mfont->dictionary_offsets_size + 2; + + /* Write range entries */ + for (int r = 0; r < mfont->char_range_count; r++) { + //mfont->char_ranges[r].glyph_offsets_fp_offset = fp_offset; + TRACE_DBG(("mfont->char_ranges[%d].glyph_offsets=%08x %08x\r\n", r, + mfont->char_ranges[r].glyph_offsets_fp_offset, bufferred_ftell(f))); + EXIT_IF_NEGATIVE(read_16b_blob(f, &mfont->char_ranges[r].glyph_offsets, + &mfont->char_ranges[r].glyph_offsets_size)); + fp_offset += mfont->char_ranges[r].glyph_offsets_size + 2; + + //mfont->char_ranges[r].glyph_data_fp_offset = fp_offset; + TRACE_DBG(("mfont->char_ranges[%d].glyph_data_fp_offset=%08x %08x\r\n", + r, + mfont->char_ranges[r].glyph_data_fp_offset, bufferred_ftell(f))); + EXIT_IF_NEGATIVE(read_8b_blob(f, &mfont->char_ranges[r].glyph_data,\ + &mfont->char_ranges[r].glyph_data_size)); + fp_offset += mfont->char_ranges[r].glyph_data_size + 2; + } + + bufferred_fclose(f); + return 0; +} + +int load_raster_font(char *data, int data_len, struct mf_font_s** font) +{ + int ret; + + /* Allocate font memory */ + *font = (struct mf_font_s*)RCD_ALLOC(sizeof(struct mf_rlefont_s)); + if (*font == NULL) { + return VG_LITE_OUT_OF_MEMORY; + } + memset(*font, 0, sizeof(struct mf_rlefont_s)); + + /* Load font from file */ + ret = read_rle_font_from_buffer(data, + data_len, *font); + if (ret < 0) { + return ret; + } + + /* Update generic char width pointers of mculib */ + uint8_t mf_rlefont_character_width(const struct mf_font_s* font, + uint16_t character); + uint8_t mf_rlefont_render_character(const struct mf_font_s* font, + int16_t x0, int16_t y0, + uint16_t character, + mf_pixel_callback_t callback, + void* state); + + (*font)->character_width = &mf_rlefont_character_width; + (*font)->render_character = &mf_rlefont_render_character; + + + return 0; +} + +int free_rle_font_memory(struct mf_font_s** font) +{ + struct mf_rlefont_s* mfont = (struct mf_rlefont_s*)(*font); + + RCD_FREE(mfont->font.full_name); + RCD_FREE(mfont->font.short_name); + RCD_FREE(mfont->dictionary_data); + RCD_FREE(mfont->dictionary_offsets); + for (int r = 0; r < mfont->char_range_count; r++) { + RCD_FREE(mfont->char_ranges[r].glyph_offsets); + RCD_FREE(mfont->char_ranges[r].glyph_data); + } + #ifdef DEBUG_RESET_DATASTRUCTURE_ON_FREE + memset(mfont->char_ranges); + #endif + RCD_FREE(mfont->char_ranges); + + #ifdef DEBUG_RESET_DATASTRUCTURE_ON_FREE + memset(mfont); + #endif + RCD_FREE(mfont); + + *font = NULL; + return 0; +} + +void vg_lite_unload_font_data(void) +{ + for(int i=0; i -#include -#include "vg_lite_text.h" -#include "vft_draw.h" -#include "vft_debug.h" - -#ifdef ENABLE_DEBUG_TRACE - -/** Macros */ - -/** Data structures */ -typedef enum path_type { - PATH_DONE, - PATH_CLOSE, - MOVE_TO, - MOVE_TO_REL, - LINE_TO, - LINE_TO_REL, - QUAD_TO, - QUAD_TO_REL, - CUBI_TO, - CUBI_TO_REL, - NUM_PATH_CMD -} path_type_t; - -/** Internal or external API prototypes */ - -/** Globals */ -static const int data_count[] = -{ - 0, - 0, - 2, - 2, - 2, - 2, - 4, - 4, - 6, - 6 -}; - -static char s_cmd_name[][16] = -{ - {"PATH_DONE" }, - {"PATH_CLOSE" }, - {"MOVE_TO" }, - {"MOVE_TO_REL" }, - {"LINE_TO" }, - {"LINE_TO_REL" }, - {"QUAD_TO" }, - {"QUAD_TO_REL" }, - {"CUBI_TO" }, - {"CUBI_TO_REL" }, - {"NUM_PATH_CMD"}, -}; - - -/** Externs if any */ - -/** Code section */ -void vfg_dbg_path_data(path_desc_t* path_data_desc, int offset) -{ - float* draw_cmds; - - draw_cmds = &path_data_desc->draw_cmds[0]; - - for (int i = 0; i < path_data_desc->num_draw_cmds; i++) { - uint32_t cmd, j; - - cmd = *((uint32_t*)(&draw_cmds[i])); - if (cmd < NUM_PATH_CMD) { - TRACE_BIN(("BIN: %08x: %s(%d) [", - offset + i * 4, - s_cmd_name[cmd], cmd)); - for (j = 0; j < data_count[cmd]; j++) { - TRACE_BIN((" %.2f", draw_cmds[i + j + 1])); - } - i += j; - TRACE_BIN(("]\n")); - } - } -} - -void vft_dbg_path(char *prefix, void *draw_cmds_args, int num_draw_cmds) -{ - float* draw_cmds; - - draw_cmds = draw_cmds_args; - int offset = 0; - for (int i = 0; i < num_draw_cmds; i++) { - uint32_t cmd, j; - - cmd = *((uint32_t*)(&draw_cmds[i])); - if (cmd < NUM_PATH_CMD) { - printf("BIN: %08x: %s(%d) [", - offset + i * 4, - s_cmd_name[cmd], cmd); - for (j = 0; j < data_count[cmd]; j++) { - printf(" %.2f", draw_cmds[i + j + 1]); - } - i += j; - printf("]\n"); - } - } -} - -void vft_dbg_path_bounds(char *name, float *ary, int num_elements) -{ - float* array_data; - - array_data = ary; - printf("%s [",name); - for (int i = 0; i < num_elements; i++) { - printf(" %.2f", array_data[i]); - } - printf("]\n"); -} - -void vft_dbg_kern_desc(kern_desc_t* kern_desc, int num_kern_entries, int offset) -{ - for (int i = 0; i < num_kern_entries; i++) { - TRACE_BIN(("BIN: %08x: [%d] (u,k)=(%hu, %hu)\n", - (int)(offset + i * sizeof(kern_desc_t)), - i, - kern_desc[i].unicode, - kern_desc[i].kern)); - } -} -void vft_dbg_glyph_desc(glyph_desc_t* g, int offset) -{ - glyph_desc_t _desc = *g; /* Temporary copy descriptor*/ - - TRACE_BIN_FIELD_UINT16(unicode); - TRACE_BIN_FIELD_UINT16(horiz_adv_x); - TRACE_BIN_FIELD_UINT32(kern_num_entries); - TRACE_BIN_FIELD_UINT32(kern_table_offset); - TRACE_BIN_FIELD_FLOAT(path.bounds[0]); - TRACE_BIN_FIELD_FLOAT(path.bounds[1]); - TRACE_BIN_FIELD_FLOAT(path.bounds[2]); - TRACE_BIN_FIELD_FLOAT(path.bounds[3]); - TRACE_BIN_FIELD_UINT32(path.num_draw_cmds); - TRACE_BIN_FIELD_UINT32(path.draw_cmds_offset); - -} - -/* TRACE values for debugging purpose */ -void vft_dbg_font_face_desc(font_face_desc_t* font_face, int offset) -{ - font_face_desc_t _desc = *font_face; /* Temporary copy descriptor*/ - - TRACE_INFO(("font-face-block\n")); - - TRACE_BIN_FIELD_STR(font_family_name); offset += sizeof(_desc.font_family_name); - TRACE_BIN_FIELD_UINT16(units_per_em); - TRACE_BIN_FIELD_UINT16(ascent); - TRACE_BIN_FIELD_UINT16(descent); - TRACE_BIN_FIELD_UINT16(vg_font); - TRACE_BIN_FIELD_UINT32(num_glyphs); -} - -void vft_dbg_matrix(char *name, vg_lite_matrix_t *mat) -{ - printf("%s\n",name); - printf(" %0.3f %0.3f %0.3f\n", - mat->m[0][0],mat->m[0][1],mat->m[0][2]); - printf(" %0.3f %0.3f %0.3f\n", - mat->m[1][0],mat->m[1][1],mat->m[1][2]); - printf(" %0.3f %0.3f %0.3f\n", - mat->m[2][0],mat->m[1][1],mat->m[2][2]); -} - -void vft_dbg_path_table(font_face_desc_t* font_face, int offset) -{ - TRACE_INFO(("path-block\n")); - for (uint32_t i = 0; i < font_face->num_glyphs; i++) { - glyph_desc_t* g = &font_face->glyphs[i]; - TRACE_BIN(("Glyph - path: '%c' unicode = %d\n", g->unicode, g->unicode)); - offset = g->path.draw_cmds_offset; - vfg_dbg_path_data(&g->path, offset); - } -} - -void vft_dbg_kern_table(font_face_desc_t* font_face, int offset) -{ - TRACE_INFO(("kern-block\n")); - for (uint32_t i = 0; i < font_face->num_glyphs; i++) { - glyph_desc_t* g = &font_face->glyphs[i]; - - TRACE_INFO(("Kern: '%c' unicode=%hu\n", g->unicode, g->unicode)); - - vft_dbg_kern_desc(&g->kern_table[0], - g->kern_num_entries, - offset); - offset += (g->kern_num_entries * sizeof(kern_desc_t)); - } -} - -void vft_dbg_glyph_table(font_face_desc_t* font_face, int offset) -{ - TRACE_INFO(("glyph-block\n")); - for (uint32_t i = 0; i < font_face->num_glyphs; i++) { - glyph_desc_t* g = &font_face->glyphs[i]; - TRACE_INFO(("Glyph: '%c'\n", g->unicode)); - vft_dbg_glyph_desc(g, offset); - offset += sizeof(glyph_desc_t); - } -} - -int g_offset = 0; - -void dbg_float_ary(char *name, float *ary, int count, int *disk_offset) -{ - int i; - int offset = *disk_offset; - for (i=0; i +#include +#include "vg_lite_text.h" +#include "vft_draw.h" +#include "vft_debug.h" + +#ifdef ENABLE_DEBUG_TRACE + +/** Macros */ + +/** Data structures */ +typedef enum path_type { + PATH_DONE, + PATH_CLOSE, + MOVE_TO, + MOVE_TO_REL, + LINE_TO, + LINE_TO_REL, + QUAD_TO, + QUAD_TO_REL, + CUBI_TO, + CUBI_TO_REL, + NUM_PATH_CMD +} path_type_t; + +/** Internal or external API prototypes */ + +/** Globals */ +static const int data_count[] = +{ + 0, + 0, + 2, + 2, + 2, + 2, + 4, + 4, + 6, + 6 +}; + +static char s_cmd_name[][16] = +{ + {"PATH_DONE" }, + {"PATH_CLOSE" }, + {"MOVE_TO" }, + {"MOVE_TO_REL" }, + {"LINE_TO" }, + {"LINE_TO_REL" }, + {"QUAD_TO" }, + {"QUAD_TO_REL" }, + {"CUBI_TO" }, + {"CUBI_TO_REL" }, + {"NUM_PATH_CMD"}, +}; + + +/** Externs if any */ + +/** Code section */ +void vfg_dbg_path_data(path_desc_t* path_data_desc, int offset) +{ + float* draw_cmds; + + draw_cmds = &path_data_desc->draw_cmds[0]; + + for (int i = 0; i < path_data_desc->num_draw_cmds; i++) { + uint32_t cmd, j; + + cmd = *((uint32_t*)(&draw_cmds[i])); + if (cmd < NUM_PATH_CMD) { + TRACE_BIN(("BIN: %08x: %s(%d) [", + offset + i * 4, + s_cmd_name[cmd], cmd)); + for (j = 0; j < data_count[cmd]; j++) { + TRACE_BIN((" %.2f", draw_cmds[i + j + 1])); + } + i += j; + TRACE_BIN(("]\n")); + } + } +} + +void vft_dbg_path(char *prefix, void *draw_cmds_args, int num_draw_cmds) +{ + float* draw_cmds; + + draw_cmds = draw_cmds_args; + int offset = 0; + for (int i = 0; i < num_draw_cmds; i++) { + uint32_t cmd, j; + + cmd = *((uint32_t*)(&draw_cmds[i])); + if (cmd < NUM_PATH_CMD) { + printf("BIN: %08x: %s(%d) [", + offset + i * 4, + s_cmd_name[cmd], cmd); + for (j = 0; j < data_count[cmd]; j++) { + printf(" %.2f", draw_cmds[i + j + 1]); + } + i += j; + printf("]\n"); + } + } +} + +void vft_dbg_path_bounds(char *name, float *ary, int num_elements) +{ + float* array_data; + + array_data = ary; + printf("%s [",name); + for (int i = 0; i < num_elements; i++) { + printf(" %.2f", array_data[i]); + } + printf("]\n"); +} + +void vft_dbg_kern_desc(kern_desc_t* kern_desc, int num_kern_entries, int offset) +{ + for (int i = 0; i < num_kern_entries; i++) { + TRACE_BIN(("BIN: %08x: [%d] (u,k)=(%hu, %hu)\n", + (int)(offset + i * sizeof(kern_desc_t)), + i, + kern_desc[i].unicode, + kern_desc[i].kern)); + } +} +void vft_dbg_glyph_desc(glyph_desc_t* g, int offset) +{ + glyph_desc_t _desc = *g; /* Temporary copy descriptor*/ + + TRACE_BIN_FIELD_UINT16(unicode); + TRACE_BIN_FIELD_UINT16(horiz_adv_x); + TRACE_BIN_FIELD_UINT32(kern_num_entries); + TRACE_BIN_FIELD_UINT32(kern_table_offset); + TRACE_BIN_FIELD_FLOAT(path.bounds[0]); + TRACE_BIN_FIELD_FLOAT(path.bounds[1]); + TRACE_BIN_FIELD_FLOAT(path.bounds[2]); + TRACE_BIN_FIELD_FLOAT(path.bounds[3]); + TRACE_BIN_FIELD_UINT32(path.num_draw_cmds); + TRACE_BIN_FIELD_UINT32(path.draw_cmds_offset); + +} + +/* TRACE values for debugging purpose */ +void vft_dbg_font_face_desc(font_face_desc_t* font_face, int offset) +{ + font_face_desc_t _desc = *font_face; /* Temporary copy descriptor*/ + + TRACE_INFO(("font-face-block\n")); + + TRACE_BIN_FIELD_STR(font_family_name); offset += sizeof(_desc.font_family_name); + TRACE_BIN_FIELD_UINT16(units_per_em); + TRACE_BIN_FIELD_UINT16(ascent); + TRACE_BIN_FIELD_UINT16(descent); + TRACE_BIN_FIELD_UINT16(vg_font); + TRACE_BIN_FIELD_UINT32(num_glyphs); +} + +void vft_dbg_matrix(char *name, vg_lite_matrix_t *mat) +{ + printf("%s\n",name); + printf(" %0.3f %0.3f %0.3f\n", + mat->m[0][0],mat->m[0][1],mat->m[0][2]); + printf(" %0.3f %0.3f %0.3f\n", + mat->m[1][0],mat->m[1][1],mat->m[1][2]); + printf(" %0.3f %0.3f %0.3f\n", + mat->m[2][0],mat->m[1][1],mat->m[2][2]); +} + +void vft_dbg_path_table(font_face_desc_t* font_face, int offset) +{ + TRACE_INFO(("path-block\n")); + for (uint32_t i = 0; i < font_face->num_glyphs; i++) { + glyph_desc_t* g = &font_face->glyphs[i]; + TRACE_BIN(("Glyph - path: '%c' unicode = %d\n", g->unicode, g->unicode)); + offset = g->path.draw_cmds_offset; + vfg_dbg_path_data(&g->path, offset); + } +} + +void vft_dbg_kern_table(font_face_desc_t* font_face, int offset) +{ + TRACE_INFO(("kern-block\n")); + for (uint32_t i = 0; i < font_face->num_glyphs; i++) { + glyph_desc_t* g = &font_face->glyphs[i]; + + TRACE_INFO(("Kern: '%c' unicode=%hu\n", g->unicode, g->unicode)); + + vft_dbg_kern_desc(&g->kern_table[0], + g->kern_num_entries, + offset); + offset += (g->kern_num_entries * sizeof(kern_desc_t)); + } +} + +void vft_dbg_glyph_table(font_face_desc_t* font_face, int offset) +{ + TRACE_INFO(("glyph-block\n")); + for (uint32_t i = 0; i < font_face->num_glyphs; i++) { + glyph_desc_t* g = &font_face->glyphs[i]; + TRACE_INFO(("Glyph: '%c'\n", g->unicode)); + vft_dbg_glyph_desc(g, offset); + offset += sizeof(glyph_desc_t); + } +} + +int g_offset = 0; + +void dbg_float_ary(char *name, float *ary, int count, int *disk_offset) +{ + int i; + int offset = *disk_offset; + for (i=0; iparam[0], count, &g_offset); - -#define DBG_INT_ARY(obj, param, count) \ - dbg_int_ary(#param, obj->param, count, &g_offset); - -#define DBG_FIELD(obj, param) \ - dbg_int_param(#param, obj->param, &g_offset) - -#define DBG_READ_32B(name, value, offset) \ - dbg_int_param_no_offset_update(name, value, offset) -extern int g_offset; - -#define VFT_DBG_FONT_FACE_DESC(a,b) vft_dbg_font_face_desc(a,b) -#define VFT_DBG_GLYPH_TABLE(a,b) vft_dbg_glyph_table(a,b) -#define VFT_DBG_KERN_TABLE(a,b) vft_dbg_kern_table(a,b) -#define VFT_DBG_PATH_TABLE(a,b) vft_dbg_path_table(a,b) - -static int g_offset = 0; /* Dummy just to solve build errors */ -#define DBG_TRACE(x) -#define DBG_INC_OFFSET(x) g_offset += (x); -#define DBG_OFFSET() (g_offset) - -/* Prorotypes */ -void vft_dbg_font_face_desc(font_face_desc_t* font_face, int offset); -void vft_dbg_glyph_desc(glyph_desc_t* g, int offset); -void vft_dbg_kern_desc(kern_desc_t* kern_desc, int num_kern_entries, int offset); -void vfg_dbg_path_data(path_desc_t* path_data_desc, int offset); -void vft_dbg_matrix(char *name, vg_lite_matrix_t *mat); -void vft_dbg_path_table(font_face_desc_t* font_face, int offset); -void vft_dbg_kern_table(font_face_desc_t* font_face, int offset); -void vft_dbg_glyph_table(font_face_desc_t* font_face, int offset); - -void dbg_float_ary_no_offset_update(char *name, float *ary, - int count, int disk_offset); -void dbg_int_ary_no_offset_update(char *name, uint32_t *ary, - int count, int disk_offset); -void dbg_int_param_no_offset_update(char *name, uint32_t value, int disk_offset); - -#else -/** Without -debug configuration */ -/* Macros */ -#define TRACE_DBG(x) -#define TRACE_BIN(x) -#define TRACE_WRN(x) printf x -#define TRACE_INFO(x) -#define TRACE_ERR(x) printf x - -#define DBG_READ_32B(a,b,c) -#define DBG_TRACE(x) -#define vft_dbg_glyph_desc(g,offset) -#define dbg_float_ary_no_offset_update(a, b, c,d) -#define dbg_int_ary_no_offset_update(a, b, c,d) -#define vft_dbg_path_bounds(a,b,c) -#define vft_dbg_path(a,b,c) - -#define VFT_DBG_FONT_FACE_DESC(a,b) -#define VFT_DBG_GLYPH_TABLE(a,b) -#define VFT_DBG_KERN_TABLE(a,b) -#define VFT_DBG_PATH_TABLE(a,b) - -#define DBG_INC_OFFSET(x) -#define DBG_OFFSET() (0) - -#endif - -#define TRACE_BIN_FIELD_STR(x) TRACE_BIN(("BIN: %08x: "#x"=%s\n",offset,_desc.x)); -#define TRACE_BIN_FIELD_UINT16(x) TRACE_BIN(("BIN: %08x: "#x"=%hu\n",offset,_desc.x)); offset += 2; -#define TRACE_BIN_FIELD_UINT32(x) TRACE_BIN(("BIN: %08x: "#x"=%u\n",offset,_desc.x)); offset += 4; -#define TRACE_BIN_FIELD_FLOAT(x) TRACE_BIN(("BIN: %08x: "#x"=%f\n",offset,_desc.x)); offset += 4; - +/**************************************************************************** +* +* The MIT License (MIT) +* +* Copyright 2020 NXP +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +//#define ENABLE_DEBUG_TRACE + +#ifdef ENABLE_DEBUG_TRACE +/* With debug configuration */ + +/* Macros */ +#define TRACE_DBG(x) printf x +#define TRACE_BIN(x) // printf x /* Tracer for binary layout */ +#define TRACE_WRN(x) printf x +#define TRACE_INFO(x) printf x +#define TRACE_ERR(x) printf x +#define DBG_ARY(obj, param, count) \ + dbg_float_ary(#param, &obj->param[0], count, &g_offset); + +#define DBG_INT_ARY(obj, param, count) \ + dbg_int_ary(#param, obj->param, count, &g_offset); + +#define DBG_FIELD(obj, param) \ + dbg_int_param(#param, obj->param, &g_offset) + +#define DBG_READ_32B(name, value, offset) \ + dbg_int_param_no_offset_update(name, value, offset) +extern int g_offset; + +#define VFT_DBG_FONT_FACE_DESC(a,b) vft_dbg_font_face_desc(a,b) +#define VFT_DBG_GLYPH_TABLE(a,b) vft_dbg_glyph_table(a,b) +#define VFT_DBG_KERN_TABLE(a,b) vft_dbg_kern_table(a,b) +#define VFT_DBG_PATH_TABLE(a,b) vft_dbg_path_table(a,b) + +static int g_offset = 0; /* Dummy just to solve build errors */ +#define DBG_TRACE(x) +#define DBG_INC_OFFSET(x) g_offset += (x); +#define DBG_OFFSET() (g_offset) + +/* Prorotypes */ +void vft_dbg_font_face_desc(font_face_desc_t* font_face, int offset); +void vft_dbg_glyph_desc(glyph_desc_t* g, int offset); +void vft_dbg_kern_desc(kern_desc_t* kern_desc, int num_kern_entries, int offset); +void vfg_dbg_path_data(path_desc_t* path_data_desc, int offset); +void vft_dbg_matrix(char *name, vg_lite_matrix_t *mat); +void vft_dbg_path_table(font_face_desc_t* font_face, int offset); +void vft_dbg_kern_table(font_face_desc_t* font_face, int offset); +void vft_dbg_glyph_table(font_face_desc_t* font_face, int offset); + +void dbg_float_ary_no_offset_update(char *name, float *ary, + int count, int disk_offset); +void dbg_int_ary_no_offset_update(char *name, uint32_t *ary, + int count, int disk_offset); +void dbg_int_param_no_offset_update(char *name, uint32_t value, int disk_offset); + +#else +/** Without -debug configuration */ +/* Macros */ +#define TRACE_DBG(x) +#define TRACE_BIN(x) +#define TRACE_WRN(x) printf x +#define TRACE_INFO(x) +#define TRACE_ERR(x) printf x + +#define DBG_READ_32B(a,b,c) +#define DBG_TRACE(x) +#define vft_dbg_glyph_desc(g,offset) +#define dbg_float_ary_no_offset_update(a, b, c,d) +#define dbg_int_ary_no_offset_update(a, b, c,d) +#define vft_dbg_path_bounds(a,b,c) +#define vft_dbg_path(a,b,c) + +#define VFT_DBG_FONT_FACE_DESC(a,b) +#define VFT_DBG_GLYPH_TABLE(a,b) +#define VFT_DBG_KERN_TABLE(a,b) +#define VFT_DBG_PATH_TABLE(a,b) + +#define DBG_INC_OFFSET(x) +#define DBG_OFFSET() (0) + +#endif + +#define TRACE_BIN_FIELD_STR(x) TRACE_BIN(("BIN: %08x: "#x"=%s\n",offset,_desc.x)); +#define TRACE_BIN_FIELD_UINT16(x) TRACE_BIN(("BIN: %08x: "#x"=%hu\n",offset,_desc.x)); offset += 2; +#define TRACE_BIN_FIELD_UINT32(x) TRACE_BIN(("BIN: %08x: "#x"=%u\n",offset,_desc.x)); offset += 4; +#define TRACE_BIN_FIELD_FLOAT(x) TRACE_BIN(("BIN: %08x: "#x"=%f\n",offset,_desc.x)); offset += 4; + diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/vft_draw.c b/bsp/sdk_overlay/middleware/vglite/font/vft_draw.c similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/vft_draw.c rename to bsp/sdk_overlay/middleware/vglite/font/vft_draw.c index 3937e44..433c1a1 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/vft_draw.c +++ b/bsp/sdk_overlay/middleware/vglite/font/vft_draw.c @@ -1,462 +1,462 @@ -/**************************************************************************** -* -* The MIT License (MIT) -* -* Copyright 2020 NXP -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -/** Include Files */ -#include -#include -#include -#include "vg_lite.h" -#include "vg_lite_text.h" -#include "vft_draw.h" -#include "vft_debug.h" -#include "FreeRTOS.h" - -/** Macros */ -#define VFT_ALLOC(x) _mem_allocate(x) -#define VFT_FREE(x) _mem_free(x) -#define READ_BIN_FIELD(x) memcpy(&g->x, (buf + offset), sizeof(g->x)); offset += sizeof(g->x) -#define READ_BIN_FIELD_STR(x) READ_BIN_FIELD(x) -#define READ_BIN_FIELD_UINT16(x) READ_BIN_FIELD(x) -#define READ_BIN_FIELD_UINT32(x) READ_BIN_FIELD(x) -#define READ_BIN_FIELD_FLOAT(x) READ_BIN_FIELD(x) -#define READ_BIN_FIELD_DUMMY_POINTER(x) offset += 4; -#define GLYPH_CACHE_SIZE 16 -#define ENABLE_TEXT_WRAP 0 -#define HALT_ALLOCATOR_ERROR 1 - -/** Data structures */ -typedef struct glyph_cache_desc { - vg_lite_path_t *h_path; - glyph_desc_t *g; - uint32_t use_count; -}glyph_cache_desc_t; - -/** Internal or external API prototypes */ - -/** Globals */ -static int g_glyph_cache_init_done = 0; -static glyph_cache_desc_t g_glyph_cache[GLYPH_CACHE_SIZE]; -int g_total_bytes = 0; - -/** Externs if any */ - -/* Internal API, not published to user */ -font_face_desc_t *_vg_lite_get_vector_font(vg_lite_font_t font_idx); -void matrix_multiply(vg_lite_matrix_t * matrix, vg_lite_matrix_t *mult); - -void *_mem_allocate(int size) -{ - char *buf = NULL; - - if ( size == 0 ) { - printf("ERROR: HALT: Why allocating %d bytes\n", size); -#if HALT_ALLOCATOR_ERROR - while(1); -#else - return NULL; -#endif - } - - buf = pvPortMalloc(size); - if (buf == NULL) { - printf("ERROR: HALT: allocating %d bytes \"system out of memory\"\n", size); -#if HALT_ALLOCATOR_ERROR - while(1); -#else - return NULL; -#endif - } - g_total_bytes += size; - return buf; -} - -void _mem_free(void *buf) -{ - vPortFree(buf); -} - -/** GLYPH CACHING Code */ -void glyph_cache_init(void) -{ - if ( g_glyph_cache_init_done == 0 ) { - memset(g_glyph_cache,0,sizeof(g_glyph_cache)); - g_glyph_cache_init_done = 1; - } -} - -void glyph_cache_free(void) -{ - int i; - for (i=0; iunicode == - g_glyph_cache[i].g->unicode ) - { - g_glyph_cache[i].use_count++; - return g_glyph_cache[i].h_path; - } - } - - /* Find least used descriptor */ - unused_idx = 0; - for (i=1; ipath.num_draw_cmds*4, - g->path.draw_cmds, - g->path.bounds[0], - g->path.bounds[1], - g->path.bounds[2], - g->path.bounds[3]); - g_glyph_cache[unused_idx].g = g; - g_glyph_cache[unused_idx].use_count = 1; - return g_glyph_cache[unused_idx].h_path; -} - -/** Render text using vector fonts */ -int vg_lite_vtf_draw_text(vg_lite_buffer_t *rt, int x, int y, - vg_lite_blend_t blend, - vg_lite_font_t font, - vg_lite_matrix_t *matrix, - vg_lite_font_attributes_t * attributes, - char *text) -{ - font_face_desc_t *font_face; - glyph_desc_t* g1 = NULL; - glyph_desc_t* g2; - int error = 0; - float font_scale = 1.0; - int text_wrap = 0; - - font_face = (font_face_desc_t *)_vg_lite_get_vector_font(font); - - attributes->last_dx = 0; - font_scale = ((1.0*attributes->font_height)/font_face->units_per_em); - - vg_lite_matrix_t mat; - - vg_lite_fill_t fill_rule = VG_LITE_FILL_NON_ZERO; - vg_lite_color_t color = attributes->text_color; - - /* Compute size of tex in pixels - * For center alignment adjust x position - * Present parser has bug in encoding alignment value, - * Once it is fixed following code will align text in center - */ - if ( attributes->alignment == eTextAlignCenter || - attributes->alignment == eTextAlignRight ) { - char *t2 = text; - int dx = 0; - uint16_t ug2; /* Unicode glyph */ - int kx; - - /* Case of center alignement */ - while (*t2 != '\0') { - ug2 = *t2; - kx = 0; - g2 = vft_find_glyph(font_face, ug2); - if (g1 != NULL && g2 != NULL) { - kx = vft_glyph_distance(g1, g2); - } - - dx += ((g2->horiz_adv_x + kx )* font_scale); - t2++; - } - - if ( attributes->alignment == eTextAlignCenter) { - x -= (dx/2); - } else if ( attributes->alignment == eTextAlignRight) { - x -= (dx); - } - } - - /* Compute pixels that will cover this vector path */ - while (*text != '\0') { - uint16_t ug2; /* Unicode glyph */ - int kx; - - if (text_wrap == 0) { - vg_lite_identity(&mat); - matrix_multiply(&mat, matrix); - vg_lite_translate(x,y, &mat); - vg_lite_scale(font_scale,font_scale, &mat); // 0.35 = height/units_per_em - vg_lite_scale(-1.0,1.0, &mat); - vg_lite_scale(-1.0,-1.0, &mat); - text_wrap = 1; - } - - /* Read unicode character */ - kx = 0; - ug2 = *text; - g2 = vft_find_glyph(font_face, ug2); - if (g1 != NULL && g2 != NULL) { - kx = vft_glyph_distance(g1, g2); - } - -#if (ENABLE_TEXT_WRAP==1) - /* Wrap text */ - if ( (x + attributes->last_dx + ((g2->horiz_adv_x + kx )* font_scale)) - >= (720 - 5) ) - { - text_wrap = 0; - attributes->last_dx = 0; - y += (attributes->font_height + 1); - continue; - } -#endif /* ENABLE_TEXT_WRAP */ - - /* Compute glyph size in horizontal dimension */ - g1 = g2; - text++; - - error = vg_lite_draw(rt, vft_cache_lookup(g2), - fill_rule, - &mat, - blend, - color); - if ( error != VG_LITE_SUCCESS ) { - break; - } - - vg_lite_translate(g2->horiz_adv_x + kx, 0, &mat); - attributes->last_dx += ((g2->horiz_adv_x + kx )* font_scale); - } - - attributes->last_dx += 2; /* Space between 2 text strings */ - - return 0; -} - -void load_font_face(font_face_desc_t* font_face, uint8_t* buf, int font_face_offset) -{ - font_face_desc_t* g = font_face; - int offset = font_face_offset; - - READ_BIN_FIELD_STR(font_family_name); - READ_BIN_FIELD_UINT16(units_per_em); - READ_BIN_FIELD_UINT16(ascent); - READ_BIN_FIELD_UINT16(descent); - READ_BIN_FIELD_UINT16(vg_font); - READ_BIN_FIELD_UINT32(num_glyphs); -} - -void load_glyph_table(font_face_desc_t* font_face, uint8_t* buf, int glyph_table_offset) -{ - int offset = glyph_table_offset; - - for (uint32_t i = 0; i < font_face->num_glyphs; i++) { - glyph_desc_t* g = &font_face->glyphs[i]; - - memset(g, 0, sizeof(glyph_desc_t)); - READ_BIN_FIELD_UINT16(unicode); - READ_BIN_FIELD_UINT16(horiz_adv_x); - READ_BIN_FIELD_UINT32(kern_num_entries); - READ_BIN_FIELD_UINT32(kern_table_offset); - READ_BIN_FIELD_DUMMY_POINTER(); - READ_BIN_FIELD_FLOAT(path.bounds[0]); - READ_BIN_FIELD_FLOAT(path.bounds[1]); - READ_BIN_FIELD_FLOAT(path.bounds[2]); - READ_BIN_FIELD_FLOAT(path.bounds[3]); - READ_BIN_FIELD_UINT32(path.num_draw_cmds); - READ_BIN_FIELD_UINT32(path.draw_cmds_offset); - READ_BIN_FIELD_DUMMY_POINTER(); - - font_face->glyphs[i].kern_table = (kern_desc_t *)(buf + font_face->glyphs[i].kern_table_offset); - font_face->glyphs[i].path.draw_cmds = (float *)(buf + font_face->glyphs[i].path.draw_cmds_offset); - - TRACE_INFO(("Glyph: '%c'\n", g->unicode)); - vft_dbg_glyph_desc(g, d_offset); - } -} - -/* Load vector font ROM table from file */ -font_face_desc_t* vft_load_from_buffer(char* buf_base, int file_size) -{ - font_face_desc_t* font_face = NULL; - uint32_t* blk_hdr; - //int error = 0; - - /* Setup internal memory pointers of font_face_desc_t */ - int font_face_offset = 0; - int glyph_table_offset = 0; - //int kern_table_offset = 0; - //int path_data_offset = 0; - int offset = 0; - - /* May be we can avoid this lookup */ - while (offset < file_size) { - blk_hdr = (uint32_t*)(buf_base + offset); - eFontBlock_t eType = (eFontBlock_t)((*blk_hdr) >> 24); - int size = ((*blk_hdr) & ((1<<24)-1)); - TRACE_BIN(("BIN: %08x: block(%hu, %hu)\n", - offset, eType, size)); - offset += BLK_HDR_SIZE; - - /* Check integrity of block and then only proceed */ - switch (eType) { - case eFontFaceDesc: - font_face_offset = offset; - break; - case eGlyphTableDesc: - glyph_table_offset = offset; - break; - case eKernTableDesc: - //kern_table_offset = offset; - break; - case eGlyphData: - //path_data_offset = offset; - break; - default: - case eUnkBlock: - case eMaxBlock: - return NULL;; - } - offset += size; - } - - if (offset < 0 || offset > file_size) { - printf("ERROR: Vector font file integrity error aborting..\n"); - return NULL; - } - - /* Make structure binary compliant to reduce loading time */ - font_face = (font_face_desc_t*)(buf_base + font_face_offset); - font_face->glyphs = (glyph_desc_t*)(buf_base + glyph_table_offset); - - VFT_DBG_FONT_FACE_DESC(font_face, font_face_offset); - for (uint32_t i = 0; i < font_face->num_glyphs; i++) { - /* Update internal pointer from memory mapped file */ - font_face->glyphs[i].kern_table = - (kern_desc_t*)(buf_base + font_face->glyphs[i].kern_table_offset); - font_face->glyphs[i].path.draw_cmds = - (float*)(buf_base + - font_face->glyphs[i].path.draw_cmds_offset); - /* Try to get these paramters from Binary object or attributes */ - //vg_lite_format_t data_format = VG_LITE_FP32; //VG_LITE_S16; - //vg_lite_quality_t quality = VG_LITE_HIGH; - } - VFT_DBG_GLYPH_TABLE(font_face, glyph_table_offset); - - VFT_DBG_KERN_TABLE(font_face, kern_table_offset); - VFT_DBG_PATH_TABLE(font_face, path_data_offset); - - return font_face; -} - -/* Find glyph of given character from glyph table */ -glyph_desc_t* vft_find_glyph(font_face_desc_t* font_face, uint16_t ug2) -{ - const int num_glyphs = font_face->num_glyphs; - glyph_desc_t* glyphs = font_face->glyphs; - - /* - * Present approach is slow linear search, this is ok in 1st prototype - * Since glyph table is already sorted, we can have binary search - */ - for (int i = 0; i < num_glyphs; i++) { - if (glyphs[i].unicode == ug2) { - return (glyph_desc_t*)&glyphs[i]; - } - } - return (glyph_desc_t*)&glyphs[0];; -} - -/* Find distance between 2 glyph symbols */ -int vft_glyph_distance(glyph_desc_t* g1, glyph_desc_t* g2) -{ - signed short kx = 0; - uint16_t ug2 = g2->unicode; - kern_desc_t* kern_table = &g1->kern_table[0]; - - for (int i = 0; i < g1->kern_num_entries; i++) { - if (kern_table[i].unicode == ug2) { - signed short *pkx = (signed short *)&kern_table[i].kern; - kx = *pkx; - break; - } - } - - return kx; -} - -/* -* Get internal vector path of given glyph -* This is internal function -*/ -path_desc_t* vft_get_glyph_path(glyph_desc_t* g2) -{ - return &g2->path; -} - -/* Unload font face descriptor and all glyphs */ -void vft_unload(font_face_desc_t* font_face) -{ - glyph_cache_free(); - //VFT_FREE(font_face); -} +/**************************************************************************** +* +* The MIT License (MIT) +* +* Copyright 2020 NXP +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +/** Include Files */ +#include +#include +#include +#include "vg_lite.h" +#include "vg_lite_text.h" +#include "vft_draw.h" +#include "vft_debug.h" +#include "FreeRTOS.h" + +/** Macros */ +#define VFT_ALLOC(x) _mem_allocate(x) +#define VFT_FREE(x) _mem_free(x) +#define READ_BIN_FIELD(x) memcpy(&g->x, (buf + offset), sizeof(g->x)); offset += sizeof(g->x) +#define READ_BIN_FIELD_STR(x) READ_BIN_FIELD(x) +#define READ_BIN_FIELD_UINT16(x) READ_BIN_FIELD(x) +#define READ_BIN_FIELD_UINT32(x) READ_BIN_FIELD(x) +#define READ_BIN_FIELD_FLOAT(x) READ_BIN_FIELD(x) +#define READ_BIN_FIELD_DUMMY_POINTER(x) offset += 4; +#define GLYPH_CACHE_SIZE 16 +#define ENABLE_TEXT_WRAP 0 +#define HALT_ALLOCATOR_ERROR 1 + +/** Data structures */ +typedef struct glyph_cache_desc { + vg_lite_path_t *h_path; + glyph_desc_t *g; + uint32_t use_count; +}glyph_cache_desc_t; + +/** Internal or external API prototypes */ + +/** Globals */ +static int g_glyph_cache_init_done = 0; +static glyph_cache_desc_t g_glyph_cache[GLYPH_CACHE_SIZE]; +int g_total_bytes = 0; + +/** Externs if any */ + +/* Internal API, not published to user */ +font_face_desc_t *_vg_lite_get_vector_font(vg_lite_font_t font_idx); +void matrix_multiply(vg_lite_matrix_t * matrix, vg_lite_matrix_t *mult); + +void *_mem_allocate(int size) +{ + char *buf = NULL; + + if ( size == 0 ) { + printf("ERROR: HALT: Why allocating %d bytes\n", size); +#if HALT_ALLOCATOR_ERROR + while(1); +#else + return NULL; +#endif + } + + buf = pvPortMalloc(size); + if (buf == NULL) { + printf("ERROR: HALT: allocating %d bytes \"system out of memory\"\n", size); +#if HALT_ALLOCATOR_ERROR + while(1); +#else + return NULL; +#endif + } + g_total_bytes += size; + return buf; +} + +void _mem_free(void *buf) +{ + vPortFree(buf); +} + +/** GLYPH CACHING Code */ +void glyph_cache_init(void) +{ + if ( g_glyph_cache_init_done == 0 ) { + memset(g_glyph_cache,0,sizeof(g_glyph_cache)); + g_glyph_cache_init_done = 1; + } +} + +void glyph_cache_free(void) +{ + int i; + for (i=0; iunicode == + g_glyph_cache[i].g->unicode ) + { + g_glyph_cache[i].use_count++; + return g_glyph_cache[i].h_path; + } + } + + /* Find least used descriptor */ + unused_idx = 0; + for (i=1; ipath.num_draw_cmds*4, + g->path.draw_cmds, + g->path.bounds[0], + g->path.bounds[1], + g->path.bounds[2], + g->path.bounds[3]); + g_glyph_cache[unused_idx].g = g; + g_glyph_cache[unused_idx].use_count = 1; + return g_glyph_cache[unused_idx].h_path; +} + +/** Render text using vector fonts */ +int vg_lite_vtf_draw_text(vg_lite_buffer_t *rt, int x, int y, + vg_lite_blend_t blend, + vg_lite_font_t font, + vg_lite_matrix_t *matrix, + vg_lite_font_attributes_t * attributes, + char *text) +{ + font_face_desc_t *font_face; + glyph_desc_t* g1 = NULL; + glyph_desc_t* g2; + int error = 0; + float font_scale = 1.0; + int text_wrap = 0; + + font_face = (font_face_desc_t *)_vg_lite_get_vector_font(font); + + attributes->last_dx = 0; + font_scale = ((1.0*attributes->font_height)/font_face->units_per_em); + + vg_lite_matrix_t mat; + + vg_lite_fill_t fill_rule = VG_LITE_FILL_NON_ZERO; + vg_lite_color_t color = attributes->text_color; + + /* Compute size of tex in pixels + * For center alignment adjust x position + * Present parser has bug in encoding alignment value, + * Once it is fixed following code will align text in center + */ + if ( attributes->alignment == eTextAlignCenter || + attributes->alignment == eTextAlignRight ) { + char *t2 = text; + int dx = 0; + uint16_t ug2; /* Unicode glyph */ + int kx; + + /* Case of center alignement */ + while (*t2 != '\0') { + ug2 = *t2; + kx = 0; + g2 = vft_find_glyph(font_face, ug2); + if (g1 != NULL && g2 != NULL) { + kx = vft_glyph_distance(g1, g2); + } + + dx += ((g2->horiz_adv_x + kx )* font_scale); + t2++; + } + + if ( attributes->alignment == eTextAlignCenter) { + x -= (dx/2); + } else if ( attributes->alignment == eTextAlignRight) { + x -= (dx); + } + } + + /* Compute pixels that will cover this vector path */ + while (*text != '\0') { + uint16_t ug2; /* Unicode glyph */ + int kx; + + if (text_wrap == 0) { + vg_lite_identity(&mat); + matrix_multiply(&mat, matrix); + vg_lite_translate(x,y, &mat); + vg_lite_scale(font_scale,font_scale, &mat); // 0.35 = height/units_per_em + vg_lite_scale(-1.0,1.0, &mat); + vg_lite_scale(-1.0,-1.0, &mat); + text_wrap = 1; + } + + /* Read unicode character */ + kx = 0; + ug2 = *text; + g2 = vft_find_glyph(font_face, ug2); + if (g1 != NULL && g2 != NULL) { + kx = vft_glyph_distance(g1, g2); + } + +#if (ENABLE_TEXT_WRAP==1) + /* Wrap text */ + if ( (x + attributes->last_dx + ((g2->horiz_adv_x + kx )* font_scale)) + >= (720 - 5) ) + { + text_wrap = 0; + attributes->last_dx = 0; + y += (attributes->font_height + 1); + continue; + } +#endif /* ENABLE_TEXT_WRAP */ + + /* Compute glyph size in horizontal dimension */ + g1 = g2; + text++; + + error = vg_lite_draw(rt, vft_cache_lookup(g2), + fill_rule, + &mat, + blend, + color); + if ( error != VG_LITE_SUCCESS ) { + break; + } + + vg_lite_translate(g2->horiz_adv_x + kx, 0, &mat); + attributes->last_dx += ((g2->horiz_adv_x + kx )* font_scale); + } + + attributes->last_dx += 2; /* Space between 2 text strings */ + + return 0; +} + +void load_font_face(font_face_desc_t* font_face, uint8_t* buf, int font_face_offset) +{ + font_face_desc_t* g = font_face; + int offset = font_face_offset; + + READ_BIN_FIELD_STR(font_family_name); + READ_BIN_FIELD_UINT16(units_per_em); + READ_BIN_FIELD_UINT16(ascent); + READ_BIN_FIELD_UINT16(descent); + READ_BIN_FIELD_UINT16(vg_font); + READ_BIN_FIELD_UINT32(num_glyphs); +} + +void load_glyph_table(font_face_desc_t* font_face, uint8_t* buf, int glyph_table_offset) +{ + int offset = glyph_table_offset; + + for (uint32_t i = 0; i < font_face->num_glyphs; i++) { + glyph_desc_t* g = &font_face->glyphs[i]; + + memset(g, 0, sizeof(glyph_desc_t)); + READ_BIN_FIELD_UINT16(unicode); + READ_BIN_FIELD_UINT16(horiz_adv_x); + READ_BIN_FIELD_UINT32(kern_num_entries); + READ_BIN_FIELD_UINT32(kern_table_offset); + READ_BIN_FIELD_DUMMY_POINTER(); + READ_BIN_FIELD_FLOAT(path.bounds[0]); + READ_BIN_FIELD_FLOAT(path.bounds[1]); + READ_BIN_FIELD_FLOAT(path.bounds[2]); + READ_BIN_FIELD_FLOAT(path.bounds[3]); + READ_BIN_FIELD_UINT32(path.num_draw_cmds); + READ_BIN_FIELD_UINT32(path.draw_cmds_offset); + READ_BIN_FIELD_DUMMY_POINTER(); + + font_face->glyphs[i].kern_table = (kern_desc_t *)(buf + font_face->glyphs[i].kern_table_offset); + font_face->glyphs[i].path.draw_cmds = (float *)(buf + font_face->glyphs[i].path.draw_cmds_offset); + + TRACE_INFO(("Glyph: '%c'\n", g->unicode)); + vft_dbg_glyph_desc(g, d_offset); + } +} + +/* Load vector font ROM table from file */ +font_face_desc_t* vft_load_from_buffer(char* buf_base, int file_size) +{ + font_face_desc_t* font_face = NULL; + uint32_t* blk_hdr; + //int error = 0; + + /* Setup internal memory pointers of font_face_desc_t */ + int font_face_offset = 0; + int glyph_table_offset = 0; + //int kern_table_offset = 0; + //int path_data_offset = 0; + int offset = 0; + + /* May be we can avoid this lookup */ + while (offset < file_size) { + blk_hdr = (uint32_t*)(buf_base + offset); + eFontBlock_t eType = (eFontBlock_t)((*blk_hdr) >> 24); + int size = ((*blk_hdr) & ((1<<24)-1)); + TRACE_BIN(("BIN: %08x: block(%hu, %hu)\n", + offset, eType, size)); + offset += BLK_HDR_SIZE; + + /* Check integrity of block and then only proceed */ + switch (eType) { + case eFontFaceDesc: + font_face_offset = offset; + break; + case eGlyphTableDesc: + glyph_table_offset = offset; + break; + case eKernTableDesc: + //kern_table_offset = offset; + break; + case eGlyphData: + //path_data_offset = offset; + break; + default: + case eUnkBlock: + case eMaxBlock: + return NULL;; + } + offset += size; + } + + if (offset < 0 || offset > file_size) { + printf("ERROR: Vector font file integrity error aborting..\n"); + return NULL; + } + + /* Make structure binary compliant to reduce loading time */ + font_face = (font_face_desc_t*)(buf_base + font_face_offset); + font_face->glyphs = (glyph_desc_t*)(buf_base + glyph_table_offset); + + VFT_DBG_FONT_FACE_DESC(font_face, font_face_offset); + for (uint32_t i = 0; i < font_face->num_glyphs; i++) { + /* Update internal pointer from memory mapped file */ + font_face->glyphs[i].kern_table = + (kern_desc_t*)(buf_base + font_face->glyphs[i].kern_table_offset); + font_face->glyphs[i].path.draw_cmds = + (float*)(buf_base + + font_face->glyphs[i].path.draw_cmds_offset); + /* Try to get these paramters from Binary object or attributes */ + //vg_lite_format_t data_format = VG_LITE_FP32; //VG_LITE_S16; + //vg_lite_quality_t quality = VG_LITE_HIGH; + } + VFT_DBG_GLYPH_TABLE(font_face, glyph_table_offset); + + VFT_DBG_KERN_TABLE(font_face, kern_table_offset); + VFT_DBG_PATH_TABLE(font_face, path_data_offset); + + return font_face; +} + +/* Find glyph of given character from glyph table */ +glyph_desc_t* vft_find_glyph(font_face_desc_t* font_face, uint16_t ug2) +{ + const int num_glyphs = font_face->num_glyphs; + glyph_desc_t* glyphs = font_face->glyphs; + + /* + * Present approach is slow linear search, this is ok in 1st prototype + * Since glyph table is already sorted, we can have binary search + */ + for (int i = 0; i < num_glyphs; i++) { + if (glyphs[i].unicode == ug2) { + return (glyph_desc_t*)&glyphs[i]; + } + } + return (glyph_desc_t*)&glyphs[0];; +} + +/* Find distance between 2 glyph symbols */ +int vft_glyph_distance(glyph_desc_t* g1, glyph_desc_t* g2) +{ + signed short kx = 0; + uint16_t ug2 = g2->unicode; + kern_desc_t* kern_table = &g1->kern_table[0]; + + for (int i = 0; i < g1->kern_num_entries; i++) { + if (kern_table[i].unicode == ug2) { + signed short *pkx = (signed short *)&kern_table[i].kern; + kx = *pkx; + break; + } + } + + return kx; +} + +/* +* Get internal vector path of given glyph +* This is internal function +*/ +path_desc_t* vft_get_glyph_path(glyph_desc_t* g2) +{ + return &g2->path; +} + +/* Unload font face descriptor and all glyphs */ +void vft_unload(font_face_desc_t* font_face) +{ + glyph_cache_free(); + //VFT_FREE(font_face); +} diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/vft_draw.h b/bsp/sdk_overlay/middleware/vglite/font/vft_draw.h similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/vft_draw.h rename to bsp/sdk_overlay/middleware/vglite/font/vft_draw.h index 39eb8f1..c309a80 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/vft_draw.h +++ b/bsp/sdk_overlay/middleware/vglite/font/vft_draw.h @@ -1,119 +1,119 @@ -/**************************************************************************** -* -* The MIT License (MIT) -* -* Copyright 2020 NXP -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -#ifndef _VFT_DRAW_H -#define _VFT_DRAW_H - -#include - -typedef enum eFontBlkType { - eUnkBlock, - eFontFaceDesc, - eGlyphTableDesc, - eKernTableDesc, - eGlyphData, - eMaxBlock -}eFontBlock_t; - -static const int32_t BLK_HDR_SIZE = 4; - -typedef struct path_descriptor { - float bounds[4]; - uint32_t num_draw_cmds; - uint32_t draw_cmds_offset; - float* draw_cmds; /* NOTE: this will be used while loading table, DONT REMOVE */ -}path_desc_t; - -typedef struct kern_desc { - uint16_t unicode; - uint16_t kern; -}kern_desc_t; - -typedef struct glyph_descriptor { - uint16_t unicode; /* unicode name */ - uint16_t horiz_adv_x; /* Short to align to 32-bit boundry */ - uint32_t kern_num_entries; - uint32_t kern_table_offset; - kern_desc_t* kern_table; /* NOTE: this will be used while loading table, DONT REMOVE */ - path_desc_t path; -}glyph_desc_t; - -typedef struct font_face_info { - int8_t font_family_name[64]; - uint16_t units_per_em; - uint16_t ascent; - uint16_t descent; - uint16_t vg_font; - uint32_t num_glyphs; - glyph_desc_t* glyphs; /* NOTE: this will be used while loading table, DONT REMOVE */ -}font_face_desc_t; - -//NOTE: No glyph caching at this time - -/* Load vector font ROM table from file */ -font_face_desc_t* vft_load(char* vcft_file_path); - -/* Find glyph of given character from glyph table */ -glyph_desc_t* vft_find_glyph(font_face_desc_t* font_face, uint16_t ug2); - -/* Find distance between 2 glyph symbols */ -int vft_glyph_distance(glyph_desc_t* g1, glyph_desc_t* g2); - -/* -* Get internal vector path of given glyph -* This is internal function -*/ -path_desc_t* vft_get_glyph_path(glyph_desc_t* g2); - -/* Draw vector font based glyph on given x,y co-ordinate */ -void vft_draw_glyph(int x, int y, glyph_desc_t* g2); - -/* Compute horizotal pixels coverted by this path */ -int vft_compute_dx(glyph_desc_t* g2); - -/* Unload font face descriptor and all glyphs */ -void vft_unload(font_face_desc_t*); - -/* Draw string with vector font s*/ -int vg_lite_vtf_draw_text(vg_lite_buffer_t *rt, int x, int y, - vg_lite_blend_t blend, - vg_lite_font_t font, - vg_lite_matrix_t *matrix, - vg_lite_font_attributes_t * attributes, - char *text); - -/* Internal memory allocator API */ -void *_mem_allocate(int size); -void _mem_free(void *buf); - -vg_lite_error_t vg_lite_load_font_data(vg_lite_font_t font, int font_height); -font_face_desc_t* vft_load_from_buffer(char* buf_base, int file_size); -void vg_lite_unload_font_data(void); - -#endif //!_VFT_DRAW_H +/**************************************************************************** +* +* The MIT License (MIT) +* +* Copyright 2020 NXP +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +#ifndef _VFT_DRAW_H +#define _VFT_DRAW_H + +#include + +typedef enum eFontBlkType { + eUnkBlock, + eFontFaceDesc, + eGlyphTableDesc, + eKernTableDesc, + eGlyphData, + eMaxBlock +}eFontBlock_t; + +static const int32_t BLK_HDR_SIZE = 4; + +typedef struct path_descriptor { + float bounds[4]; + uint32_t num_draw_cmds; + uint32_t draw_cmds_offset; + float* draw_cmds; /* NOTE: this will be used while loading table, DONT REMOVE */ +}path_desc_t; + +typedef struct kern_desc { + uint16_t unicode; + uint16_t kern; +}kern_desc_t; + +typedef struct glyph_descriptor { + uint16_t unicode; /* unicode name */ + uint16_t horiz_adv_x; /* Short to align to 32-bit boundry */ + uint32_t kern_num_entries; + uint32_t kern_table_offset; + kern_desc_t* kern_table; /* NOTE: this will be used while loading table, DONT REMOVE */ + path_desc_t path; +}glyph_desc_t; + +typedef struct font_face_info { + int8_t font_family_name[64]; + uint16_t units_per_em; + uint16_t ascent; + uint16_t descent; + uint16_t vg_font; + uint32_t num_glyphs; + glyph_desc_t* glyphs; /* NOTE: this will be used while loading table, DONT REMOVE */ +}font_face_desc_t; + +//NOTE: No glyph caching at this time + +/* Load vector font ROM table from file */ +font_face_desc_t* vft_load(char* vcft_file_path); + +/* Find glyph of given character from glyph table */ +glyph_desc_t* vft_find_glyph(font_face_desc_t* font_face, uint16_t ug2); + +/* Find distance between 2 glyph symbols */ +int vft_glyph_distance(glyph_desc_t* g1, glyph_desc_t* g2); + +/* +* Get internal vector path of given glyph +* This is internal function +*/ +path_desc_t* vft_get_glyph_path(glyph_desc_t* g2); + +/* Draw vector font based glyph on given x,y co-ordinate */ +void vft_draw_glyph(int x, int y, glyph_desc_t* g2); + +/* Compute horizotal pixels coverted by this path */ +int vft_compute_dx(glyph_desc_t* g2); + +/* Unload font face descriptor and all glyphs */ +void vft_unload(font_face_desc_t*); + +/* Draw string with vector font s*/ +int vg_lite_vtf_draw_text(vg_lite_buffer_t *rt, int x, int y, + vg_lite_blend_t blend, + vg_lite_font_t font, + vg_lite_matrix_t *matrix, + vg_lite_font_attributes_t * attributes, + char *text); + +/* Internal memory allocator API */ +void *_mem_allocate(int size); +void _mem_free(void *buf); + +vg_lite_error_t vg_lite_load_font_data(vg_lite_font_t font, int font_height); +font_face_desc_t* vft_load_from_buffer(char* buf_base, int file_size); +void vg_lite_unload_font_data(void); + +#endif //!_VFT_DRAW_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/vg_lite_text.c b/bsp/sdk_overlay/middleware/vglite/font/vg_lite_text.c similarity index 97% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/vg_lite_text.c rename to bsp/sdk_overlay/middleware/vglite/font/vg_lite_text.c index 5b433f7..3aefcea 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/vg_lite_text.c +++ b/bsp/sdk_overlay/middleware/vglite/font/vg_lite_text.c @@ -1,359 +1,359 @@ -/**************************************************************************** -* -* The MIT License (MIT) -* -* Copyright 2020 NXP -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -*****************************************************************************/ - -/** Include Files */ -#include "vg_lite.h" -#include "vg_lite_text.h" -#include -#include - -#include -#include "vft_draw.h" - -/** Macros */ - -/** Data structures */ -typedef struct { - /* Font related parameters */ - vg_lite_font_attributes_t *attributes; - vg_lite_buffer_t buffer; - uint16_t width; - uint16_t height; - uint16_t y; - const struct mf_font_s *rcd_font; -} text_context_t; - -/** Internal or external API prototypes */ -struct mf_font_s *_vg_lite_get_raster_font(vg_lite_font_t font_idx); -int vg_lite_is_font_valid(vg_lite_font_t font); - -/** Globals */ -vg_lite_font_attributes_t g_font_attribs; -vg_lite_font_t g_last_font = VG_LITE_INVALID_FONT; -int g_last_font_attrib_idx; - -/** Externs if any */ - -/* Capture unique values of alpha */ -static unsigned int g_index_table[257]; - -/* text_color is in ARGB8888 format */ -int init_256pallet_color_table(unsigned int bg_color, unsigned int fg_color) -{ - int i; - g_index_table[0] = 0; /* Background color */ - int fg_r = ((fg_color>>0)&0xff); - int fg_g = ((fg_color>>8)&0xff); - int fg_b = ((fg_color>>16)&0xff); - - int bg_r = ((bg_color>>0)&0xff); - int bg_g = ((bg_color>>8)&0xff); - int bg_b = ((bg_color>>16)&0xff); - - for (i=1; i<256; i++) { - int r, g, b; - int a = 0xff; - register int mult, mult2; - - mult = ((i*1024)/256); - mult2 = (((256-i)*1024)/256); - - /* Blend with white bg */ - r = ( ((bg_r * mult2)>>10) +((fg_r * mult)>>10) ); - g = ( ((bg_g * mult2)>>10) +((fg_g * mult)>>10) ); - b = ( ((bg_b * mult2)>>10) +((fg_b * mult)>>10) ); - g_index_table[i] = ((a) + (r<<8) + (g<<16)+(b<<24)); - } - return 0; -} - -/* Callback to write to a memory buffer. */ -static void pixel_callback(int16_t x, int16_t y, uint8_t count, uint8_t alpha, - void *state) -{ - text_context_t *s = (text_context_t*)state; - uint32_t pos; - uint32_t value; - uint32_t *raw_pixel_buffer = (uint32_t *)s->buffer.memory; - int stride = s->buffer.stride; - - if (y < 0 || y >= s->height) return; - if (x < 0 || x + count >= s->width) return; - - while (count--) - { - pos = (uint32_t)stride * y + x; - value = g_index_table[alpha]; - - raw_pixel_buffer[pos] = value; - - x++; - } -} - -/* Callback to render characters. */ -static uint8_t character_callback(int16_t x, int16_t y, mf_char character, - void *state) -{ - text_context_t *s = (text_context_t*)state; - return mf_render_character(s->rcd_font, x, y, character, pixel_callback, state); -} - -/* Callback to render lines. */ -static bool line_callback(const char *line, uint16_t count, void *state) -{ - text_context_t *s = (text_context_t*)state; - - if (s->attributes->justify) - { - mf_render_justified(s->rcd_font, s->attributes->anchor, s->y, - s->width - s->attributes->margin * 2, - line, count, character_callback, state); - } - else - { - mf_render_aligned(s->rcd_font, s->attributes->anchor, s->y, - (enum mf_align_t)s->attributes->alignment, line, count, - character_callback, state); - } - s->y += s->rcd_font->line_height; - return true; -} - -/* Callback to just count the lines. - * Used to decide the image height */ -bool count_lines(const char *line, uint16_t count, void *state) -{ - int *linecount = (int*)state; - (*linecount)++; - return true; -} - -vg_lite_error_t alloc_font_buffer(vg_lite_buffer_t *buffer, int width , int height) -{ - vg_lite_error_t error; - - /* Align width to 16 pixels, heigh to 16 pixels */ - width = ((width+15)&(~15)); - height = ((height+15)&(~15)); - - /* Allocate memory from VGLITE space */ - buffer->width = width; - buffer->height = height; - buffer->format = VG_LITE_ARGB8888; - buffer->stride = 0; - error = vg_lite_allocate(buffer); - buffer->stride = width; - buffer->tiled = VG_LITE_LINEAR; - - return error; -} - -static vg_lite_error_t free_font_buffer(vg_lite_buffer_t *buffer) -{ - vg_lite_error_t error; - - error = vg_lite_free(buffer); - - return error; -} - -void matrix_multiply(vg_lite_matrix_t * matrix, vg_lite_matrix_t * mult) -{ - vg_lite_matrix_t temp; - int row, column; - - /* Process all rows. */ - for (row = 0; row < 3; row++) { - /* Process all columns. */ - for (column = 0; column < 3; column++) { - /* Compute matrix entry. */ - temp.m[row][column] = (matrix->m[row][0] * mult->m[0][column]) - + (matrix->m[row][1] * mult->m[1][column]) - + (matrix->m[row][2] * mult->m[2][column]); - } - } - - /* Copy temporary matrix into result. */ - memcpy(matrix, &temp, sizeof(temp)); -} - -vg_lite_error_t vg_lite_draw_text(vg_lite_buffer_t *target, - char *text, - vg_lite_font_t font, - int x, - int y, - vg_lite_matrix_t *matrix, - vg_lite_blend_t blend, - vg_lite_font_attributes_t *attributes) -{ - vg_lite_error_t error; - int height; - text_context_t ctx_text; - vg_lite_matrix_t m_text; - int text_img_size = 0; - font_face_desc_t* font_face = NULL; - int text_width_in_pixels = 0; - int tmpX; - - memset(&ctx_text, 0, sizeof(ctx_text)); - ctx_text.attributes = attributes; - - if ( vg_lite_is_font_valid(font) != 0 ) { - return VG_LITE_INVALID_ARGUMENT; - } - - error = vg_lite_load_font_data(font, - attributes->font_height); - if ( error != 0 ) { - return VG_LITE_INVALID_ARGUMENT; - } - - if(attributes->tspan_has_dx_dy != 0) - { - if ( x < 0 ) - x = attributes->last_x + attributes->last_dx; - if ( y < 0 ) - y = attributes->last_y; - } - - // Dynamic decision - if ( attributes->is_vector_font == 0 ) { - init_256pallet_color_table(attributes->bg_color, attributes->text_color); - - /* Application specifies actual font by reading proper rcd file */ - ctx_text.rcd_font = _vg_lite_get_raster_font(font); - - /* Count number of lines to decide font buffer size. */ - height = 0; - mf_text_draw_area(ctx_text.rcd_font, attributes->width - 2 * attributes->margin, - text, &height, &text_width_in_pixels); - height *= attributes->font_height; - height += 4; - - if( attributes->tspan_has_dx_dy == 0) { - y -= attributes->font_height; - } - - tmpX = x; - if(attributes->alignment == eTextAlignCenter) { - tmpX -= text_width_in_pixels/2; - } else if(attributes->alignment == eTextAlignRight) { - tmpX -= text_width_in_pixels; - } - /* Manually calculate X-offset for text-alignemnt; mcufont just - * doesn't render half part(left-part) for center alignment and - * full string skipped for right-alignment, So again set it to - * left-alignment for font-attrib, as offsets are already - * calculated and alignment handled in other way */ - attributes->alignment = 0; - - /* Allocate and initialize vg_lite_buffer that can hold font text - * Note: ctx_text.width and ctx_text.height get used by internal - * state of MF rendering engine. Based on amount of text to render - * This buffer gets allocated, and buffer width gets aligned to - * 16 pixel boundary - */ - ctx_text.width = attributes->width; - /* Memory optimization */ - ctx_text.width = text_width_in_pixels; - /* Align width to 16 pixel boundary */ - if (ctx_text.width & 15) { - ctx_text.width += 15; - ctx_text.width &= (~15); - } - - ctx_text.height = height; - error = alloc_font_buffer(&ctx_text.buffer, ctx_text.width, ctx_text.height); - if ( error != VG_LITE_SUCCESS) { - printf("WARNING: alloc_font_buffer failed(%d).\r\n",error); - } - ctx_text.y = 2; - - /* Initialize vg_lite buffer with transperant color */ - /* Due to alignment requirement of vg_lite, font buffer can be larger */ - if ( ctx_text.buffer.format == VG_LITE_ARGB8888 ) - text_img_size = ctx_text.buffer.width * ctx_text.buffer.height * 4; - else - text_img_size = ctx_text.buffer.width * ctx_text.buffer.height; - memset(ctx_text.buffer.memory, 0, - text_img_size); - - /* Render font text into vg_lite_buffer */ - mf_wordwrap(ctx_text.rcd_font, attributes->width - 2 * attributes->margin, - text, line_callback, &ctx_text); - - /* Draw font bitmap on render target */ - vg_lite_identity(&m_text); - matrix_multiply(&m_text, matrix); - vg_lite_translate(x, y, &m_text); - vg_lite_scale(1.0, 1.0, &m_text); - if ( ctx_text.buffer.format == VG_LITE_ARGB8888 ) - ctx_text.buffer.stride = ctx_text.width*4; - - error = vg_lite_blit(target, &ctx_text.buffer, &m_text, blend, - 0, VG_LITE_FILTER_POINT); - if ( error != VG_LITE_SUCCESS) { - printf("WARNING: vg_lite_blit failed(%d).\r\n",error); - } - - error = vg_lite_finish(); - if ( error != VG_LITE_SUCCESS) { - printf("WARNING: vg_lite_finish failed(%d).\r\n",error); - } - - error = free_font_buffer(&ctx_text.buffer); - if ( error != VG_LITE_SUCCESS) { - printf("WARNING: vg_lite_finish failed(%d).\r\n",error); - } - attributes->last_dx = text_width_in_pixels; - } else { - error = (vg_lite_error_t)vg_lite_vtf_draw_text(target, - x, y, - blend, - font, - matrix, - attributes, - text); - /* Note: vg_lite_vtf_draw_text updates attributes->last_dx internally - This assignment is just to keep code similar to rcd code */ - attributes->last_dx = attributes->last_dx; - - error = vg_lite_finish(); - if ( error != VG_LITE_SUCCESS) { - printf("WARNING: vg_lite_finish failed(%d).\r\n",error); - } - - vft_unload(font_face); - } - attributes->last_x = x; - attributes->last_y = y; - - return error; -} +/**************************************************************************** +* +* The MIT License (MIT) +* +* Copyright 2020 NXP +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* 'Software'), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sub license, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject +* to the following conditions: +* +* The above copyright notice and this permission notice (including the +* next paragraph) shall be included in all copies or substantial +* portions of the Software. +* +* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*****************************************************************************/ + +/** Include Files */ +#include "vg_lite.h" +#include "vg_lite_text.h" +#include +#include + +#include +#include "vft_draw.h" + +/** Macros */ + +/** Data structures */ +typedef struct { + /* Font related parameters */ + vg_lite_font_attributes_t *attributes; + vg_lite_buffer_t buffer; + uint16_t width; + uint16_t height; + uint16_t y; + const struct mf_font_s *rcd_font; +} text_context_t; + +/** Internal or external API prototypes */ +struct mf_font_s *_vg_lite_get_raster_font(vg_lite_font_t font_idx); +int vg_lite_is_font_valid(vg_lite_font_t font); + +/** Globals */ +vg_lite_font_attributes_t g_font_attribs; +vg_lite_font_t g_last_font = VG_LITE_INVALID_FONT; +int g_last_font_attrib_idx; + +/** Externs if any */ + +/* Capture unique values of alpha */ +static unsigned int g_index_table[257]; + +/* text_color is in ARGB8888 format */ +int init_256pallet_color_table(unsigned int bg_color, unsigned int fg_color) +{ + int i; + g_index_table[0] = 0; /* Background color */ + int fg_r = ((fg_color>>0)&0xff); + int fg_g = ((fg_color>>8)&0xff); + int fg_b = ((fg_color>>16)&0xff); + + int bg_r = ((bg_color>>0)&0xff); + int bg_g = ((bg_color>>8)&0xff); + int bg_b = ((bg_color>>16)&0xff); + + for (i=1; i<256; i++) { + int r, g, b; + int a = 0xff; + register int mult, mult2; + + mult = ((i*1024)/256); + mult2 = (((256-i)*1024)/256); + + /* Blend with white bg */ + r = ( ((bg_r * mult2)>>10) +((fg_r * mult)>>10) ); + g = ( ((bg_g * mult2)>>10) +((fg_g * mult)>>10) ); + b = ( ((bg_b * mult2)>>10) +((fg_b * mult)>>10) ); + g_index_table[i] = ((a) + (r<<8) + (g<<16)+(b<<24)); + } + return 0; +} + +/* Callback to write to a memory buffer. */ +static void pixel_callback(int16_t x, int16_t y, uint8_t count, uint8_t alpha, + void *state) +{ + text_context_t *s = (text_context_t*)state; + uint32_t pos; + uint32_t value; + uint32_t *raw_pixel_buffer = (uint32_t *)s->buffer.memory; + int stride = s->buffer.stride; + + if (y < 0 || y >= s->height) return; + if (x < 0 || x + count >= s->width) return; + + while (count--) + { + pos = (uint32_t)stride * y + x; + value = g_index_table[alpha]; + + raw_pixel_buffer[pos] = value; + + x++; + } +} + +/* Callback to render characters. */ +static uint8_t character_callback(int16_t x, int16_t y, mf_char character, + void *state) +{ + text_context_t *s = (text_context_t*)state; + return mf_render_character(s->rcd_font, x, y, character, pixel_callback, state); +} + +/* Callback to render lines. */ +static bool line_callback(const char *line, uint16_t count, void *state) +{ + text_context_t *s = (text_context_t*)state; + + if (s->attributes->justify) + { + mf_render_justified(s->rcd_font, s->attributes->anchor, s->y, + s->width - s->attributes->margin * 2, + line, count, character_callback, state); + } + else + { + mf_render_aligned(s->rcd_font, s->attributes->anchor, s->y, + (enum mf_align_t)s->attributes->alignment, line, count, + character_callback, state); + } + s->y += s->rcd_font->line_height; + return true; +} + +/* Callback to just count the lines. + * Used to decide the image height */ +bool count_lines(const char *line, uint16_t count, void *state) +{ + int *linecount = (int*)state; + (*linecount)++; + return true; +} + +vg_lite_error_t alloc_font_buffer(vg_lite_buffer_t *buffer, int width , int height) +{ + vg_lite_error_t error; + + /* Align width to 16 pixels, heigh to 16 pixels */ + width = ((width+15)&(~15)); + height = ((height+15)&(~15)); + + /* Allocate memory from VGLITE space */ + buffer->width = width; + buffer->height = height; + buffer->format = VG_LITE_ARGB8888; + buffer->stride = 0; + error = vg_lite_allocate(buffer); + buffer->stride = width; + buffer->tiled = VG_LITE_LINEAR; + + return error; +} + +static vg_lite_error_t free_font_buffer(vg_lite_buffer_t *buffer) +{ + vg_lite_error_t error; + + error = vg_lite_free(buffer); + + return error; +} + +void matrix_multiply(vg_lite_matrix_t * matrix, vg_lite_matrix_t * mult) +{ + vg_lite_matrix_t temp; + int row, column; + + /* Process all rows. */ + for (row = 0; row < 3; row++) { + /* Process all columns. */ + for (column = 0; column < 3; column++) { + /* Compute matrix entry. */ + temp.m[row][column] = (matrix->m[row][0] * mult->m[0][column]) + + (matrix->m[row][1] * mult->m[1][column]) + + (matrix->m[row][2] * mult->m[2][column]); + } + } + + /* Copy temporary matrix into result. */ + memcpy(matrix, &temp, sizeof(temp)); +} + +vg_lite_error_t vg_lite_draw_text(vg_lite_buffer_t *target, + char *text, + vg_lite_font_t font, + int x, + int y, + vg_lite_matrix_t *matrix, + vg_lite_blend_t blend, + vg_lite_font_attributes_t *attributes) +{ + vg_lite_error_t error; + int height; + text_context_t ctx_text; + vg_lite_matrix_t m_text; + int text_img_size = 0; + font_face_desc_t* font_face = NULL; + int text_width_in_pixels = 0; + int tmpX; + + memset(&ctx_text, 0, sizeof(ctx_text)); + ctx_text.attributes = attributes; + + if ( vg_lite_is_font_valid(font) != 0 ) { + return VG_LITE_INVALID_ARGUMENT; + } + + error = vg_lite_load_font_data(font, + attributes->font_height); + if ( error != 0 ) { + return VG_LITE_INVALID_ARGUMENT; + } + + if(attributes->tspan_has_dx_dy != 0) + { + if ( x < 0 ) + x = attributes->last_x + attributes->last_dx; + if ( y < 0 ) + y = attributes->last_y; + } + + // Dynamic decision + if ( attributes->is_vector_font == 0 ) { + init_256pallet_color_table(attributes->bg_color, attributes->text_color); + + /* Application specifies actual font by reading proper rcd file */ + ctx_text.rcd_font = _vg_lite_get_raster_font(font); + + /* Count number of lines to decide font buffer size. */ + height = 0; + mf_text_draw_area(ctx_text.rcd_font, attributes->width - 2 * attributes->margin, + text, &height, &text_width_in_pixels); + height *= attributes->font_height; + height += 4; + + if( attributes->tspan_has_dx_dy == 0) { + y -= attributes->font_height; + } + + tmpX = x; + if(attributes->alignment == eTextAlignCenter) { + tmpX -= text_width_in_pixels/2; + } else if(attributes->alignment == eTextAlignRight) { + tmpX -= text_width_in_pixels; + } + /* Manually calculate X-offset for text-alignemnt; mcufont just + * doesn't render half part(left-part) for center alignment and + * full string skipped for right-alignment, So again set it to + * left-alignment for font-attrib, as offsets are already + * calculated and alignment handled in other way */ + attributes->alignment = 0; + + /* Allocate and initialize vg_lite_buffer that can hold font text + * Note: ctx_text.width and ctx_text.height get used by internal + * state of MF rendering engine. Based on amount of text to render + * This buffer gets allocated, and buffer width gets aligned to + * 16 pixel boundary + */ + ctx_text.width = attributes->width; + /* Memory optimization */ + ctx_text.width = text_width_in_pixels; + /* Align width to 16 pixel boundary */ + if (ctx_text.width & 15) { + ctx_text.width += 15; + ctx_text.width &= (~15); + } + + ctx_text.height = height; + error = alloc_font_buffer(&ctx_text.buffer, ctx_text.width, ctx_text.height); + if ( error != VG_LITE_SUCCESS) { + printf("WARNING: alloc_font_buffer failed(%d).\r\n",error); + } + ctx_text.y = 2; + + /* Initialize vg_lite buffer with transperant color */ + /* Due to alignment requirement of vg_lite, font buffer can be larger */ + if ( ctx_text.buffer.format == VG_LITE_ARGB8888 ) + text_img_size = ctx_text.buffer.width * ctx_text.buffer.height * 4; + else + text_img_size = ctx_text.buffer.width * ctx_text.buffer.height; + memset(ctx_text.buffer.memory, 0, + text_img_size); + + /* Render font text into vg_lite_buffer */ + mf_wordwrap(ctx_text.rcd_font, attributes->width - 2 * attributes->margin, + text, line_callback, &ctx_text); + + /* Draw font bitmap on render target */ + vg_lite_identity(&m_text); + matrix_multiply(&m_text, matrix); + vg_lite_translate(x, y, &m_text); + vg_lite_scale(1.0, 1.0, &m_text); + if ( ctx_text.buffer.format == VG_LITE_ARGB8888 ) + ctx_text.buffer.stride = ctx_text.width*4; + + error = vg_lite_blit(target, &ctx_text.buffer, &m_text, blend, + 0, VG_LITE_FILTER_POINT); + if ( error != VG_LITE_SUCCESS) { + printf("WARNING: vg_lite_blit failed(%d).\r\n",error); + } + + error = vg_lite_finish(); + if ( error != VG_LITE_SUCCESS) { + printf("WARNING: vg_lite_finish failed(%d).\r\n",error); + } + + error = free_font_buffer(&ctx_text.buffer); + if ( error != VG_LITE_SUCCESS) { + printf("WARNING: vg_lite_finish failed(%d).\r\n",error); + } + attributes->last_dx = text_width_in_pixels; + } else { + error = (vg_lite_error_t)vg_lite_vtf_draw_text(target, + x, y, + blend, + font, + matrix, + attributes, + text); + /* Note: vg_lite_vtf_draw_text updates attributes->last_dx internally + This assignment is just to keep code similar to rcd code */ + attributes->last_dx = attributes->last_dx; + + error = vg_lite_finish(); + if ( error != VG_LITE_SUCCESS) { + printf("WARNING: vg_lite_finish failed(%d).\r\n",error); + } + + vft_unload(font_face); + } + attributes->last_x = x; + attributes->last_y = y; + + return error; +} diff --git a/bsp/sdk_overlay/middleware/vglite/inc/nxp_support.h b/bsp/sdk_overlay/middleware/vglite/inc/nxp_support.h new file mode 100644 index 0000000..4d94c46 --- /dev/null +++ b/bsp/sdk_overlay/middleware/vglite/inc/nxp_support.h @@ -0,0 +1,34 @@ +/**************************************************************************** +* +* The MIT License (MIT) +* +* Copyright 2023 NXP +* All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to +* deal in the Software without restriction, including without limitation the +* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +* sell copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +* IN THE SOFTWARE. +* +*****************************************************************************/ + +#include +#include + +#if (defined(__REDLIB__)) +float hypotf (float x, float y); +#endif + diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/inc/vg_lite.h b/bsp/sdk_overlay/middleware/vglite/inc/vg_lite.h similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/inc/vg_lite.h rename to bsp/sdk_overlay/middleware/vglite/inc/vg_lite.h index 4ccbbce..e9ec29a 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/inc/vg_lite.h +++ b/bsp/sdk_overlay/middleware/vglite/inc/vg_lite.h @@ -25,7 +25,7 @@ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * -* Copyright 2022 MicroEJ Corp. This file has been modified by MicroEJ Corp. +* Copyright 2022-2023 MicroEJ Corp. This file has been modified by MicroEJ Corp. * 1. Add "vg_lite_get_scissor()" * *****************************************************************************/ @@ -44,7 +44,7 @@ extern "C" { #include #include -#define VGLITE_RELEASE_VERSION 0x201000 +#define VGLITE_RELEASE_VERSION 0x03000f #define VGLITE_HEADER_VERSION 6 @@ -613,7 +613,7 @@ extern "C" { void *path; /*! Pointer to the physical description of the path. */ int8_t path_changed; /* Indicate whether path data is synced with command buffer (uploaded) or not. */ int8_t pdata_internal; /*! Indicate whether path data memory is allocated by driver. */ - vg_lite_stroke_conversion_t stroke_conversion; /*! Refer to the definition by vg_lite_stroke_conversion_t.*/ + vg_lite_stroke_conversion_t *stroke_conversion; /*! Refer to the definition by vg_lite_stroke_conversion_t.*/ vg_lite_draw_path_type_t path_type; /*! Refer to the definition by vg_lite_draw_path_type_t. */ void *stroke_path_data; /*! Pointer to the physical description of the stroke path. */ int32_t stroke_path_size; /*! Number of bytes in the stroke path data. */ @@ -1913,20 +1913,6 @@ extern "C" { */ void vg_lite_rotate(vg_lite_float_t degrees, vg_lite_matrix_t *matrix); - /*! - @abstract projective transformation. - - @discussion - set perspective matrix. - - @param degrees - px: indicate w0 of perspective transformation matrix - py: indicate w1 of perspective transformation matrix - @param matrix - Pointer to a vg_lite_matrix_t structure that will be rotated. - */ - void vg_lite_perspective(vg_lite_float_t px, vg_lite_float_t py, vg_lite_matrix_t *matrix); - /*! @abstract Set the command buffer size. diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/inc/vg_lite_hal.h b/bsp/sdk_overlay/middleware/vglite/inc/vg_lite_hal.h similarity index 90% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/inc/vg_lite_hal.h rename to bsp/sdk_overlay/middleware/vglite/inc/vg_lite_hal.h index eb3b70a..33e4531 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/inc/vg_lite_hal.h +++ b/bsp/sdk_overlay/middleware/vglite/inc/vg_lite_hal.h @@ -25,10 +25,6 @@ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * -* Copyright 2020-2022 MicroEJ Corp. This file has been modified by MicroEJ Corp. -* 1. Add callback mecanism to notify MicroEJ when a VGLite operation -* is complete -* *****************************************************************************/ #ifndef _vg_lite_hal_h_ @@ -39,9 +35,7 @@ #include "vg_lite_kernel.h" #define VGLITE_MEM_ALIGNMENT 128 -#if !defined(VG_DRIVER_SINGLE_THREAD) #define TASK_LENGTH 8 -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ #ifdef __cplusplus extern "C" { @@ -70,25 +64,7 @@ void vg_lite_hal_delay(uint32_t milliseconds); The implementer should make sure that on exit of this function the power and clock to the VGLite graphics hardware is turned on and stable. */ -#if defined(VG_DRIVER_SINGLE_THREAD) -void vg_lite_hal_initialize(void); - -// added by MicroEJ -#if _VG_LITE_IRQ_CALLBACK == 1 -typedef void (* vg_lite_irq_callback) (void); - -/* - * @brief Registers a callback that will be called when the GPU IRQ is triggered - * meaning that a VGLite operation is completed - * - * @param[in] cb: The callback to register - */ -void vg_lite_hal_register_irq_callback(vg_lite_irq_callback cb); -#endif /* _VG_LITE_IRQ_CALLBACK */ - -#else vg_lite_error_t vg_lite_hal_initialize(void); -#endif /* VG_DRIVER_SINGLE_THREAD */ /*! @brief Uninitialize the hardware. diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/inc/vg_lite_text.h b/bsp/sdk_overlay/middleware/vglite/inc/vg_lite_text.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/inc/vg_lite_text.h rename to bsp/sdk_overlay/middleware/vglite/inc/vg_lite_text.h diff --git a/bsp/sdk_overlay/middleware/vglite/middleware_vglite.cmake b/bsp/sdk_overlay/middleware/vglite/middleware_vglite.cmake new file mode 100644 index 0000000..91f156e --- /dev/null +++ b/bsp/sdk_overlay/middleware/vglite/middleware_vglite.cmake @@ -0,0 +1,49 @@ +# Add set(CONFIG_USE_middleware_vglite true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/VGLite/vg_lite.c + ${CMAKE_CURRENT_LIST_DIR}/VGLite/vg_lite_image.c + ${CMAKE_CURRENT_LIST_DIR}/VGLite/vg_lite_matrix.c + ${CMAKE_CURRENT_LIST_DIR}/VGLite/vg_lite_path.c + ${CMAKE_CURRENT_LIST_DIR}/VGLite/nxp_support.c + ${CMAKE_CURRENT_LIST_DIR}/VGLite/vg_lite_flat.c + ${CMAKE_CURRENT_LIST_DIR}/VGLite/rtos/vg_lite_os.c + ${CMAKE_CURRENT_LIST_DIR}/font/buf_reader.c + ${CMAKE_CURRENT_LIST_DIR}/font/rle_font_read.c + ${CMAKE_CURRENT_LIST_DIR}/font/vft_debug.c + ${CMAKE_CURRENT_LIST_DIR}/font/vft_draw.c + ${CMAKE_CURRENT_LIST_DIR}/font/vg_lite_text.c + ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_bwfont.c + ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_encoding.c + ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_font.c + ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_justify.c + ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_kerning.c + ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_rlefont.c + ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_scaledfont.c + ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_wordwrap.c + ${CMAKE_CURRENT_LIST_DIR}/VGLiteKernel/vg_lite_kernel.c + ${CMAKE_CURRENT_LIST_DIR}/VGLiteKernel/rtos/vg_lite_hal.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc + ${CMAKE_CURRENT_LIST_DIR}/font + ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder + ${CMAKE_CURRENT_LIST_DIR}/VGLite/rtos + ${CMAKE_CURRENT_LIST_DIR}/VGLiteKernel + ${CMAKE_CURRENT_LIST_DIR}/VGLiteKernel/rtos +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DVG_COMMAND_CALL=1 + -DVG_TARGET_FAST_CLEAR=0 + ) + +endif() + diff --git a/bsp/sdk_overlay/middleware/vglite/middleware_vglite_elementary.cmake b/bsp/sdk_overlay/middleware/vglite/middleware_vglite_elementary.cmake new file mode 100644 index 0000000..d4fb308 --- /dev/null +++ b/bsp/sdk_overlay/middleware/vglite/middleware_vglite_elementary.cmake @@ -0,0 +1,29 @@ +# Add set(CONFIG_USE_middleware_vglite_elementary true) in config.cmake to use this component + +include_guard(GLOBAL) +message("${CMAKE_CURRENT_LIST_FILE} component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/elementary/src/elm_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/elementary/src/elm_draw.c + ${CMAKE_CURRENT_LIST_DIR}/elementary/src/elm_init.c + ${CMAKE_CURRENT_LIST_DIR}/elementary/src/elm_object.c + ${CMAKE_CURRENT_LIST_DIR}/elementary/src/elm_os.c + ${CMAKE_CURRENT_LIST_DIR}/elementary/src/elm_text.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/elementary/inc + ${CMAKE_CURRENT_LIST_DIR}/elementary/src +) + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DVG_RENDER_TEXT=1 + -DRTOS + ) + +endif() + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/CODEOWNERS b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/CODEOWNERS new file mode 100644 index 0000000..540b2ae --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/CODEOWNERS @@ -0,0 +1,39 @@ +# Each line is a file pattern followed by one or more owners. + +# These owners will be the default owners for everything in +# the repo. Unless a later match takes precedence, +# @global-owner1 and @global-owner2 will be requested for +# review when someone opens a pull request. +* @FreeRTOS/pr-bar-raiser + +# Order is important; the last matching pattern takes the most +# precedence. When someone opens a pull request that only +# modifies JS files, only @js-owner and not the global +# owner(s) will be requested for a review. +# *.c FreeRTOS/pr-bar-raiser + +# You can also use email addresses if you prefer. They'll be +# used to look up users just like we do for commit author +# emails. +# *.go docs@example.com + +# In this example, @doctocat owns any files in the build/logs +# directory at the root of the repository and any of its +# subdirectories. +# /build/logs/ @doctocat + +# The `docs/*` pattern will match files like +# `docs/getting-started.md` but not further nested files like +# `docs/build-app/troubleshooting.md`. +# docs/* docs@example.com + +# In this example, @octocat owns any file in an apps directory +# anywhere in your repository. +# apps/ @octocat + +# In this example, @doctocat owns any file in the `/docs` +# directory in the root of your repository and any of its +# subdirectories. +# /docs/ @doctocat + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/CONTRIBUTING.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/CONTRIBUTING.md new file mode 100644 index 0000000..ec5d6e5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/CONTRIBUTING.md @@ -0,0 +1,70 @@ +# Contribution guidelines + +Thank you for your interest in contributing to our project. Whether it's a bug report, new feature, code, or +documentation, we welcome our community to be involved in this project. + +Please read through this document before submitting any issues or pull requests to ensure we are able to help you and all members of the community as effectively as possible. + +## Code of conduct +This project has adopted the [Amazon Open Source Code of Conduct](https://aws.github.io/code-of-conduct). +For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or contact +opensource-codeofconduct@amazon.com with any additional questions or comments. + + +## Security issue notifications +If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security via our [vulnerability reporting page](https://aws.amazon.com/security/vulnerability-reporting/). Please do **not** create a public github issue. + + +## Submitting a bugs/feature request +Have a bug to report or feature to request? Follow these steps: +1. Search on the [FreeRTOS Community Support Forums](https://forums.freertos.org/) and [GitHub issue tracker](https://github.com/FreeRTOS/FreeRTOS/issues?utf8=%E2%9C%93&q=is%3Aissue) to be sure this hasn't been already reported or discussed. +2. If your search turns up empty, create a new topic in the [forums](https://forums.freertos.org/) and work with the community to help clarify issues or refine the idea. Include as many of the details listed below. +3. Once the community has had time to discuss and digest, we welcome you to create an [issue](https://github.com/FreeRTOS/FreeRTOS/issues) to report bugs or suggest features. + +When creating a new topic on the forums or filing an issue, please include as many relevant details as possible. Examples include: + +* A clear description of the situation - what you observe, what you expect, and your view on how the two differ. +* A reproducible test case or sequence of steps. +* The version of our code being used. +* Any modifications you've made relevant to the bug. +* Details of your environment or deployment. Highlight anything unusual. + + +## Contributing via pull request +Contributions via pull requests are much appreciated. Before sending us a pull request, please ensure that: + +1. You are working against the latest source on the *main* branch. +2. You check existing open, and recently merged, pull requests to make sure someone else hasn't addressed the problem already. +3. You open an issue to discuss any significant work - we would hate for your time to be wasted. + +To send us a pull request, please: + +1. Fork the repository. +2. Modify the source; focus on the specific change you are contributing. If you also reformat all the code, it will be hard for us to focus on your change. +3. Follow the [coding style guide](https://www.FreeRTOS.org/FreeRTOS-Coding-Standard-and-Style-Guide.html). +4. Commit to your fork using clear commit messages. +5. Send us a pull request, answering any default questions in the pull request interface. + NOTE: Please make sure the default option (Allow edits from maintainers) is left checked. +6. Pay attention to any automated CI failures reported in the pull request, and stay involved in the conversation. + +GitHub provides additional document on [forking a repository](https://help.github.com/articles/fork-a-repo/) and +[creating a pull request](https://help.github.com/articles/creating-a-pull-request/). + +## Coding style +* Please ensure that your code complies to the [FreeRTOS coding style guidelines](https://www.FreeRTOS.org/FreeRTOS-Coding-Standard-and-Style-Guide.html). + + +## Getting your pull request merged +All pull requests must be approved by our review team before it can be merged in. We appreciate your patience while pull requests are reviewed. The time it takes to review will depend on complexity and consideration of wider implications. + + +## Finding contributions to work on +Looking at the existing issues is a great way to find something to contribute on. As our projects, by default, use the default GitHub issue labels (enhancement/bug/duplicate/help wanted/invalid/question/wontfix), tackling open 'help wanted' issues is a great place to start. + + +## Licensing +The FreeRTOS kernel is released under the MIT open source license, the text of which can be found [here](https://github.com/FreeRTOS/FreeRTOS/blob/main/FreeRTOS/License/license.txt) + +Additional license files can be found in the folders containing any supplementary libraries licensed by their respective copyright owners where applicable. + +We may ask you to sign a [Contributor License Agreement (CLA)](https://en.wikipedia.org/wiki/Contributor_License_Agreement) for larger changes. diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/ISSUE_TEMPLATE/bug-report.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/ISSUE_TEMPLATE/bug-report.md new file mode 100644 index 0000000..96f3595 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/ISSUE_TEMPLATE/bug-report.md @@ -0,0 +1,40 @@ +--- +name: Bug report +about: Create a report to help us improve FreeRTOS. This should only be used for confirmed + bugs. If you suspect something it is best to first discuss it on the FreeRTOS community + support forums linked below. +title: "[BUG]" +labels: bug +assignees: '' + +--- + +**Describe the bug** +A concise description of what the bug is. + +**Target** +- Development board: [e.g. HiFive11 RevB] +- Instruction Set Architecture: [e.g. RV32IMAC] +- IDE and version: [e.g. Freedom Studio 4.12.0.2019-08-2] +- Toolchain and version: [e.g. riscv64-unknown-elf-gcc-8.3.0-2019.08.0] + +**Host** +- Host OS: [e.g. MacOS] +- Version: [e.g. Mojave 10.14.6] + +**To Reproduce** +- Use project ... and configure with ... +- Run on ... and could observe ... + +**Expected behavior** +A concise description of what you expected to happen. + +**Screenshots** +If applicable, add screenshots to help explain your problem. + +**Additional context** +Add any other context about the problem here. +e.g. code snippet to reproduce the issue. +e.g. stack trace, memory dump, debugger log, and many etc. + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/ISSUE_TEMPLATE/config.yml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/ISSUE_TEMPLATE/config.yml new file mode 100644 index 0000000..55777b0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/ISSUE_TEMPLATE/config.yml @@ -0,0 +1,6 @@ +blank_issues_enabled: false +contact_links: + - name: FreeRTOS Community Support Forum + url: https://forums.freertos.org/ + about: Please ask and answer questions about FreeRTOS here. + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/ISSUE_TEMPLATE/documentation-issue.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/ISSUE_TEMPLATE/documentation-issue.md new file mode 100644 index 0000000..e5c1a19 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/ISSUE_TEMPLATE/documentation-issue.md @@ -0,0 +1,23 @@ +--- +name: Documentation issue +about: Create a report to help us improve our documentation. +title: "[DOC]" +labels: documentation +assignees: '' + +--- + +**Describe the issue** +Please describe the issue and expected clarification in concise language. + +**Reference** +Please attach the URL at which you are experiencing the issue. + +**Screenshot** +If applicable, please attach screenshot. + +**Browser** +- Browser: [e.g. Chrome] +- Version: [e.g. 80.0.3987.132] + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/ISSUE_TEMPLATE/feature_request.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/ISSUE_TEMPLATE/feature_request.md new file mode 100644 index 0000000..645f684 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/ISSUE_TEMPLATE/feature_request.md @@ -0,0 +1,30 @@ +--- +name: Feature request +about: Suggest a new feature for this project +title: "[Feature Request] " +labels: enhancement +assignees: '' + +--- + +**Is your feature request related to a problem? Please describe.** +A clear and concise description of what the problem is. Ex. I'm always frustrated when [...] + +**Describe the solution you'd like** +A clear and concise description of what you want to happen. + +**Describe alternatives you've considered** +A clear and concise description of any alternative solutions or features you've considered. + +**How many devices will this feature impact?** +Expected volume for your product. + +**What are your project timelines?** +Timeline for milestones such as design completion, testing and validation, and production. + +**Additional context** +Add any other context or screenshots about the feature request here. + + +If you have the same (or similar) feature request, please upvote this issue with thumbs up 👍 +and use the comments section to provide answers to the questions above. diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/SECURITY.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/SECURITY.md new file mode 100644 index 0000000..b4049f2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/SECURITY.md @@ -0,0 +1,5 @@ +## Reporting a Vulnerability + +If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security +via our [vulnerability reporting page](https://aws.amazon.com/security/vulnerability-reporting/) or directly via email to aws-security@amazon.com. +Please do **not** create a public github issue. diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/actions/url_verifier.sh b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/actions/url_verifier.sh new file mode 100755 index 0000000..f92d2df --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/actions/url_verifier.sh @@ -0,0 +1,63 @@ +#!/bin/bash - + +PROJECT=$1 +echo "Verifying url links of: ${PROJECT}" +if [ ! -d "$PROJECT" ] +then + echo "Directory passed does not exist" + exit 2 +fi + +USER_AGENT="Mozilla/5.0 (Macintosh; Intel Mac OS X 10_14_6) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/88.0.4324.146 Safari/537.36" +SCRIPT_RET=0 + +set -o nounset # Treat unset variables as an error + +declare -A dict + +function test { + while IFS= read -r LINE; do + FILE=$(echo $LINE | cut -f 1 -d ':') + URL=$(echo $LINE | grep -IoE '\b(https?|ftp|file)://[-A-Za-z0-9+&@#/%?=~_|!:,.;]*[-A-Za-z0-9+&@#/%=~_|]') + + # remove trailing / if it exists curl diferenciate between links with + # and without / at the end + # URL=`echo "$URL" | sed 's,/$,,'` + dict+=(["$URL"]="$FILE ") + done < <(grep -e 'https\?://' ${PROJECT} -RIa --exclude='*.exe' --exclude-dir=.git | tr '*' ' ') + + for UNIQ_URL in ${!dict[@]} # loop urls + do + CURL_RES=$(curl -si --user-agent "$(USER_AGENT)" ${UNIQ_URL} 2>/dev/null| head -n 1 | cut -f 2 -d ' ') + RES=$? + + if [ "${CURL_RES}" == '' -o "${CURL_RES}" != '200' ] + then + echo "URL is: ${UNIQ_URL}" + echo "File names: ${dict[$UNIQ_URL]}" + if [ "${CURL_RES}" == '' ] # curl returned an error + then + CURL_RES=$RES + SCRIPT_RET=1 + echo ERROR: Result is: "${CURL_RES}" + elif [ "${CURL_RES}" == '403' ] + then + SCRIPT_RET=1 + echo ERROR: Result is: "${CURL_RES}" + else + echo WARNING: Result is: "${CURL_RES}" + fi + echo "=================================" + fi + done + + if [ "${SCRIPT_RET}" -eq 0 ] + then + exit 0 + else + exit 1 + fi +} + +test + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/lexicon.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/lexicon.txt new file mode 100644 index 0000000..6e04c24 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/lexicon.txt @@ -0,0 +1,3104 @@ +aa +aaaa +aarch +aasr +ab +abetrg +abi +abis +abm +absr +abtsz +abttyp +ac +acc +accah +accal +accau +accbh +accbl +accbu +aclk +acpa +acpc +acr +adb +adc +addi +addr +adtrg +aeevt +aerr +aes +afunction +aic +aircr +aka +al +almien +almv +alt +altera +amd +amessage +aninterrupthandler +ansi +api +apic +apis +app +appnote +apr +apsr +arblst +aren +arg +armcc +armv +arp +asa +ascii +asm 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+configmemmodel +configminimal +configmtime +configmtimecmp +confignum +configoverride +configpre +configprecondition +configprintf +configqueue +configrecord +configrun +configsetup +configstack +configsupport +configtask +configtick +configtimer +configtotal +configunique +configurator +configureit +configuse +configxt +configyield +const +coproc +coprocessor +coprocessors +coreid +coroutinehandle +covfs +cp +cpacr +cpas +cpbs +cpcdis +cpcs +cpcstop +cpctrg +cpd +cpenable +cpiv +cpol +cpp +cprd +cprdr +cpre +cprivilegedonlyaccessarray +cpsid +cpsie +cpsr +cpstored +cpu +cr +crc +crcb +crcoroutine +crdelay +creadonlyarray +creadwritearray +createevent +crend +crgint +croutine +crqueue +crstart +crt +crtv +crxedchar +crxlock +csa +csaat +csas +cse +csl +csr +csrr +csrs +css +cstackbuffer +cstart +cstatus +ctaskwokenbypost +ctaskwokenbyreceive +ctcr +ctor +ctr +ctrl +cts +ctsic +ctx +ctxlock +ctype +cupd +cupdr +cv +cvaluetopost +cvs +cwgr +cx +cy +cygnal +dadr +daemontaskmessage +daif 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new file mode 100644 index 0000000..c3c8607 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/pull_request_template.md @@ -0,0 +1,16 @@ + + +Description +----------- + + +Test Steps +----------- + + +Related Issue +----------- + + + +By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice. diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/scripts/find_replace.sh b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/scripts/find_replace.sh new file mode 100755 index 0000000..c7ee796 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/scripts/find_replace.sh @@ -0,0 +1,7 @@ +#!/bin/bash +old_text=$1 +new_text=$2 +echo "Old text: ${old_text}" +echo "New text: ${new_text}" +grep -rl "${old_text}" . | xargs gsed -i -e '1h;2,$H;$!d;g' -e "s/${old_text}/${new_text}/g" + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/scripts/kernel_checker.py b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/scripts/kernel_checker.py new file mode 100755 index 0000000..e2b2c87 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/scripts/kernel_checker.py @@ -0,0 +1,152 @@ +#!/usr/bin/env python3 +#/* +# * FreeRTOS Kernel V10.5.0 +# * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# * +# * SPDX-License-Identifier: MIT +# * +# * Permission is hereby granted, free of charge, to any person obtaining a copy of +# * this software and associated documentation files (the "Software"), to deal in +# * the Software without restriction, including without limitation the rights to +# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +# * the Software, and to permit persons to whom the Software is furnished to do so, +# * subject to the following conditions: +# * +# * The above copyright notice and this permission notice shall be included in all +# * copies or substantial portions of the Software. +# * +# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# * +# * https://www.FreeRTOS.org +# * https://github.com/FreeRTOS +# * +# */ + +import os +from common.header_checker import HeaderChecker + +#-------------------------------------------------------------------------------------------------- +# CONFIG +#-------------------------------------------------------------------------------------------------- +KERNEL_IGNORED_FILES = [ + 'FreeRTOS-openocd.c', + 'Makefile', + '.DS_Store' +] + +KERNEL_IGNORED_EXTENSIONS = [ + '.yml', + '.css', + '.idx', + '.md', + '.url', + '.sty', + '.0-rc2', + '.s82', + '.js', + '.out', + '.pack', + '.2', + '.1-kernel-only', + '.0-kernel-only', + '.0-rc1', + '.readme', + '.tex', + '.png', + '.bat', + '.sh', + '.txt', + '.cmake' +] + +KERNEL_ASM_EXTENSIONS = [ + '.s', + '.S', + '.src', + '.inc', + '.s26', + '.s43', + '.s79', + '.s85', + '.s87', + '.s90', + '.asm', + '.h' +] + +KERNEL_PY_EXTENSIONS = [ + '.py' +] + +KERNEL_IGNORED_PATTERNS = [ + r'.*\.git.*', + r'.*portable/IAR/AtmelSAM7S64/.*AT91SAM7.*', + r'.*portable/GCC/ARM7_AT91SAM7S/.*', + r'.*portable/MPLAB/PIC18F/stdio.h' +] + +KERNEL_THIRD_PARTY_PATTERNS = [ + r'.*portable/ThirdParty/GCC/Posix/port*', + r'.*portable/ThirdParty/*', + r'.*portable/IAR/AVR32_UC3/.*', + r'.*portable/GCC/AVR32_UC3/.*', +] + +KERNEL_HEADER = [ + '/*\n', + ' * FreeRTOS Kernel V10.5.0\n', + ' * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n', + ' *\n', + ' * SPDX-License-Identifier: MIT\n', + ' *\n', + ' * Permission is hereby granted, free of charge, to any person obtaining a copy of\n', + ' * this software and associated documentation files (the "Software"), to deal in\n', + ' * the Software without restriction, including without limitation the rights to\n', + ' * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n', + ' * the Software, and to permit persons to whom the Software is furnished to do so,\n', + ' * subject to the following conditions:\n', + ' *\n', + ' * The above copyright notice and this permission notice shall be included in all\n', + ' * copies or substantial portions of the Software.\n', + ' *\n', + ' * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n', + ' * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n', + ' * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n', + ' * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n', + ' * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n', + ' * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n', + ' *\n', + ' * https://www.FreeRTOS.org\n', + ' * https://github.com/FreeRTOS\n', + ' *\n', + ' */\n', +] + +def main(): + parser = HeaderChecker.configArgParser() + args = parser.parse_args() + + # Configure the checks then run + checker = HeaderChecker(KERNEL_HEADER, + ignored_files=KERNEL_IGNORED_FILES, + ignored_ext=KERNEL_IGNORED_EXTENSIONS, + ignored_patterns=KERNEL_IGNORED_PATTERNS, + third_party_patterns=KERNEL_THIRD_PARTY_PATTERNS, + py_ext=KERNEL_PY_EXTENSIONS, + asm_ext=KERNEL_ASM_EXTENSIONS) + checker.ignoreFile(os.path.split(__file__)[-1]) + + rc = checker.processArgs(args) + if rc: + checker.showHelp(__file__) + + return rc + +if __name__ == '__main__': + exit(main()) + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/uncrustify.cfg b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/uncrustify.cfg new file mode 100644 index 0000000..3f4c40c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/uncrustify.cfg @@ -0,0 +1,673 @@ +# Uncrustify-0.69.0 + +newlines = auto # lf/crlf/cr/auto +input_tab_size = 4 # unsigned number +output_tab_size = 4 # unsigned number +string_escape_char = 92 # unsigned number +string_escape_char2 = 0 # unsigned number +string_replace_tab_chars = false # true/false +tok_split_gte = false # true/false +disable_processing_cmt = " *INDENT-OFF*" # string +enable_processing_cmt = " *INDENT-ON*" # string +enable_digraphs = false # true/false +utf8_bom = ignore # ignore/add/remove/force +utf8_byte = false # true/false +utf8_force = false # true/false +sp_arith = force # ignore/add/remove/force +sp_arith_additive = ignore # ignore/add/remove/force +sp_assign = force # ignore/add/remove/force +sp_cpp_lambda_assign = ignore # ignore/add/remove/force +sp_cpp_lambda_paren = ignore # ignore/add/remove/force +sp_assign_default = force # ignore/add/remove/force +sp_before_assign = force # ignore/add/remove/force +sp_after_assign = force # ignore/add/remove/force +sp_enum_paren = ignore # ignore/add/remove/force +sp_enum_assign = force # ignore/add/remove/force +sp_enum_before_assign = force # ignore/add/remove/force +sp_enum_after_assign = force # ignore/add/remove/force +sp_enum_colon = ignore # ignore/add/remove/force +sp_pp_concat = add # ignore/add/remove/force +sp_pp_stringify = add # ignore/add/remove/force +sp_before_pp_stringify = ignore # ignore/add/remove/force +sp_bool = force # ignore/add/remove/force +sp_compare = force # ignore/add/remove/force +sp_inside_paren = force # ignore/add/remove/force +sp_paren_paren = force # ignore/add/remove/force +sp_cparen_oparen = ignore # ignore/add/remove/force +sp_balance_nested_parens = false # true/false +sp_paren_brace = force # ignore/add/remove/force +sp_brace_brace = ignore # ignore/add/remove/force +sp_before_ptr_star = force # ignore/add/remove/force +sp_before_unnamed_ptr_star = force # ignore/add/remove/force +sp_between_ptr_star = remove # ignore/add/remove/force +sp_after_ptr_star = force # ignore/add/remove/force +sp_after_ptr_block_caret = ignore # ignore/add/remove/force +sp_after_ptr_star_qualifier = ignore # ignore/add/remove/force +sp_after_ptr_star_func = ignore # ignore/add/remove/force +sp_ptr_star_paren = ignore # ignore/add/remove/force +sp_before_ptr_star_func = ignore # ignore/add/remove/force +sp_before_byref = force # ignore/add/remove/force +sp_before_unnamed_byref = ignore # ignore/add/remove/force +sp_after_byref = remove # ignore/add/remove/force +sp_after_byref_func = remove # ignore/add/remove/force +sp_before_byref_func = ignore # ignore/add/remove/force +sp_after_type = force # ignore/add/remove/force +sp_after_decltype = ignore # ignore/add/remove/force +sp_before_template_paren = ignore # ignore/add/remove/force +sp_template_angle = ignore # ignore/add/remove/force +sp_before_angle = remove # ignore/add/remove/force +sp_inside_angle = remove # ignore/add/remove/force +sp_inside_angle_empty = ignore # ignore/add/remove/force +sp_angle_colon = ignore # ignore/add/remove/force +sp_after_angle = force # ignore/add/remove/force +sp_angle_paren = ignore # ignore/add/remove/force +sp_angle_paren_empty = ignore # ignore/add/remove/force +sp_angle_word = ignore # ignore/add/remove/force +sp_angle_shift = add # ignore/add/remove/force +sp_permit_cpp11_shift = false # true/false +sp_before_sparen = remove # ignore/add/remove/force +sp_inside_sparen = force # ignore/add/remove/force +sp_inside_sparen_open = ignore # ignore/add/remove/force +sp_inside_sparen_close = ignore # ignore/add/remove/force +sp_after_sparen = force # ignore/add/remove/force +sp_sparen_brace = force # ignore/add/remove/force +sp_invariant_paren = ignore # ignore/add/remove/force +sp_after_invariant_paren = ignore # ignore/add/remove/force +sp_special_semi = ignore # ignore/add/remove/force +sp_before_semi = remove # ignore/add/remove/force +sp_before_semi_for = remove # ignore/add/remove/force +sp_before_semi_for_empty = add # ignore/add/remove/force +sp_after_semi = add # ignore/add/remove/force +sp_after_semi_for = force # ignore/add/remove/force +sp_after_semi_for_empty = force # ignore/add/remove/force +sp_before_square = remove # ignore/add/remove/force +sp_before_squares = remove # ignore/add/remove/force +sp_cpp_before_struct_binding = ignore # ignore/add/remove/force +sp_inside_square = force # ignore/add/remove/force +sp_inside_square_oc_array = ignore # ignore/add/remove/force +sp_after_comma = force # ignore/add/remove/force +sp_before_comma = remove # ignore/add/remove/force +sp_after_mdatype_commas = ignore # ignore/add/remove/force +sp_before_mdatype_commas = ignore # ignore/add/remove/force +sp_between_mdatype_commas = ignore # ignore/add/remove/force +sp_paren_comma = force # ignore/add/remove/force +sp_before_ellipsis = ignore # ignore/add/remove/force +sp_type_ellipsis = ignore # ignore/add/remove/force +sp_type_question = ignore # ignore/add/remove/force +sp_paren_ellipsis = ignore # ignore/add/remove/force +sp_paren_qualifier = ignore # ignore/add/remove/force +sp_paren_noexcept = ignore # ignore/add/remove/force +sp_after_class_colon = ignore # ignore/add/remove/force +sp_before_class_colon = ignore # ignore/add/remove/force +sp_after_constr_colon = ignore # ignore/add/remove/force +sp_before_constr_colon = ignore # ignore/add/remove/force +sp_before_case_colon = remove # ignore/add/remove/force +sp_after_operator = ignore # ignore/add/remove/force +sp_after_operator_sym = ignore # ignore/add/remove/force +sp_after_operator_sym_empty = ignore # ignore/add/remove/force +sp_after_cast = force # ignore/add/remove/force +sp_inside_paren_cast = force # ignore/add/remove/force +sp_cpp_cast_paren = ignore # ignore/add/remove/force +sp_sizeof_paren = remove # ignore/add/remove/force +sp_sizeof_ellipsis = ignore # ignore/add/remove/force +sp_sizeof_ellipsis_paren = ignore # ignore/add/remove/force +sp_decltype_paren = ignore # ignore/add/remove/force +sp_after_tag = ignore # ignore/add/remove/force +sp_inside_braces_enum = force # ignore/add/remove/force +sp_inside_braces_struct = force # ignore/add/remove/force +sp_inside_braces_oc_dict = ignore # ignore/add/remove/force +sp_after_type_brace_init_lst_open = ignore # ignore/add/remove/force +sp_before_type_brace_init_lst_close = ignore # ignore/add/remove/force +sp_inside_type_brace_init_lst = ignore # ignore/add/remove/force +sp_inside_braces = force # ignore/add/remove/force +sp_inside_braces_empty = remove # ignore/add/remove/force +sp_type_func = force # ignore/add/remove/force +sp_type_brace_init_lst = ignore # ignore/add/remove/force +sp_func_proto_paren = remove # ignore/add/remove/force +sp_func_proto_paren_empty = ignore # ignore/add/remove/force +sp_func_def_paren = remove # ignore/add/remove/force +sp_func_def_paren_empty = ignore # ignore/add/remove/force +sp_inside_fparens = remove # ignore/add/remove/force +sp_inside_fparen = force # ignore/add/remove/force +sp_inside_tparen = ignore # ignore/add/remove/force +sp_after_tparen_close = ignore # ignore/add/remove/force +sp_square_fparen = ignore # ignore/add/remove/force +sp_fparen_brace = add # ignore/add/remove/force +sp_fparen_brace_initializer = ignore # ignore/add/remove/force +sp_fparen_dbrace = ignore # ignore/add/remove/force +sp_func_call_paren = remove # ignore/add/remove/force +sp_func_call_paren_empty = ignore # ignore/add/remove/force +sp_func_call_user_paren = ignore # ignore/add/remove/force +sp_func_call_user_inside_fparen = ignore # ignore/add/remove/force +sp_func_call_user_paren_paren = ignore # ignore/add/remove/force +sp_func_class_paren = remove # ignore/add/remove/force +sp_func_class_paren_empty = ignore # ignore/add/remove/force +sp_return_paren = remove # ignore/add/remove/force +sp_return_brace = ignore # ignore/add/remove/force +sp_attribute_paren = remove # ignore/add/remove/force +sp_defined_paren = remove # ignore/add/remove/force +sp_throw_paren = ignore # ignore/add/remove/force +sp_after_throw = ignore # ignore/add/remove/force +sp_catch_paren = ignore # ignore/add/remove/force +sp_oc_catch_paren = ignore # ignore/add/remove/force +sp_oc_classname_paren = ignore # ignore/add/remove/force +sp_version_paren = ignore # ignore/add/remove/force +sp_scope_paren = ignore # ignore/add/remove/force +sp_super_paren = remove # ignore/add/remove/force +sp_this_paren = remove # ignore/add/remove/force +sp_macro = force # ignore/add/remove/force +sp_macro_func = force # ignore/add/remove/force +sp_else_brace = ignore # ignore/add/remove/force +sp_brace_else = ignore # ignore/add/remove/force +sp_brace_typedef = force # ignore/add/remove/force +sp_catch_brace = ignore # ignore/add/remove/force +sp_oc_catch_brace = ignore # ignore/add/remove/force +sp_brace_catch = ignore # ignore/add/remove/force +sp_oc_brace_catch = ignore # ignore/add/remove/force +sp_finally_brace = ignore # ignore/add/remove/force +sp_brace_finally = ignore # ignore/add/remove/force +sp_try_brace = ignore # ignore/add/remove/force +sp_getset_brace = ignore # ignore/add/remove/force +sp_word_brace = add # ignore/add/remove/force +sp_word_brace_ns = add # ignore/add/remove/force +sp_before_dc = remove # ignore/add/remove/force +sp_after_dc = remove # ignore/add/remove/force +sp_d_array_colon = ignore # ignore/add/remove/force +sp_not = remove # ignore/add/remove/force +sp_inv = remove # ignore/add/remove/force +sp_addr = remove # ignore/add/remove/force +sp_member = remove # ignore/add/remove/force +sp_deref = remove # ignore/add/remove/force +sp_sign = remove # ignore/add/remove/force +sp_incdec = remove # ignore/add/remove/force +sp_before_nl_cont = add # ignore/add/remove/force +sp_after_oc_scope = ignore # ignore/add/remove/force +sp_after_oc_colon = ignore # ignore/add/remove/force +sp_before_oc_colon = ignore # ignore/add/remove/force +sp_after_oc_dict_colon = ignore # ignore/add/remove/force +sp_before_oc_dict_colon = ignore # ignore/add/remove/force +sp_after_send_oc_colon = ignore # ignore/add/remove/force +sp_before_send_oc_colon = ignore # ignore/add/remove/force +sp_after_oc_type = ignore # ignore/add/remove/force +sp_after_oc_return_type = ignore # ignore/add/remove/force +sp_after_oc_at_sel = ignore # ignore/add/remove/force +sp_after_oc_at_sel_parens = ignore # ignore/add/remove/force +sp_inside_oc_at_sel_parens = ignore # ignore/add/remove/force +sp_before_oc_block_caret = ignore # ignore/add/remove/force +sp_after_oc_block_caret = ignore # ignore/add/remove/force +sp_after_oc_msg_receiver = ignore # ignore/add/remove/force +sp_after_oc_property = ignore # ignore/add/remove/force +sp_after_oc_synchronized = ignore # ignore/add/remove/force +sp_cond_colon = force # ignore/add/remove/force +sp_cond_colon_before = ignore # ignore/add/remove/force +sp_cond_colon_after = ignore # ignore/add/remove/force +sp_cond_question = force # ignore/add/remove/force +sp_cond_question_before = ignore # ignore/add/remove/force +sp_cond_question_after = ignore # ignore/add/remove/force +sp_cond_ternary_short = ignore # ignore/add/remove/force +sp_case_label = force # ignore/add/remove/force +sp_range = ignore # ignore/add/remove/force +sp_after_for_colon = ignore # ignore/add/remove/force +sp_before_for_colon = ignore # ignore/add/remove/force +sp_extern_paren = ignore # ignore/add/remove/force +sp_cmt_cpp_start = ignore # ignore/add/remove/force +sp_cmt_cpp_doxygen = false # true/false +sp_cmt_cpp_qttr = false # true/false +sp_endif_cmt = force # ignore/add/remove/force +sp_after_new = ignore # ignore/add/remove/force +sp_between_new_paren = ignore # ignore/add/remove/force +sp_after_newop_paren = ignore # ignore/add/remove/force +sp_inside_newop_paren = ignore # ignore/add/remove/force +sp_inside_newop_paren_open = ignore # ignore/add/remove/force +sp_inside_newop_paren_close = ignore # ignore/add/remove/force +sp_before_tr_emb_cmt = force # ignore/add/remove/force +sp_num_before_tr_emb_cmt = 1 # unsigned number +sp_annotation_paren = ignore # ignore/add/remove/force +sp_skip_vbrace_tokens = false # true/false +sp_after_noexcept = ignore # ignore/add/remove/force +sp_vala_after_translation = ignore # ignore/add/remove/force +force_tab_after_define = false # true/false +indent_columns = 4 # unsigned number +indent_continue = 0 # number +indent_continue_class_head = 0 # unsigned number +indent_single_newlines = false # true/false +indent_param = 0 # unsigned number +indent_with_tabs = 0 # unsigned number +indent_cmt_with_tabs = false # true/false +indent_align_string = true # true/false +indent_xml_string = 0 # unsigned number +indent_brace = 0 # unsigned number +indent_braces = false # true/false +indent_braces_no_func = false # true/false +indent_braces_no_class = false # true/false +indent_braces_no_struct = false # true/false +indent_brace_parent = false # true/false +indent_paren_open_brace = false # true/false +indent_cs_delegate_brace = false # true/false +indent_cs_delegate_body = false # true/false +indent_namespace = false # true/false +indent_namespace_single_indent = false # true/false +indent_namespace_level = 0 # unsigned number +indent_namespace_limit = 0 # unsigned number +indent_extern = false # true/false +indent_class = true # true/false +indent_class_colon = true # true/false +indent_class_on_colon = false # true/false +indent_constr_colon = false # true/false +indent_ctor_init_leading = 2 # unsigned number +indent_ctor_init = 0 # number +indent_else_if = false # true/false +indent_var_def_blk = 0 # number +indent_var_def_cont = false # true/false +indent_shift = false # true/false +indent_func_def_force_col1 = false # true/false +indent_func_call_param = false # true/false +indent_func_def_param = false # true/false +indent_func_proto_param = false # true/false +indent_func_class_param = false # true/false +indent_func_ctor_var_param = false # true/false +indent_template_param = false # true/false +indent_func_param_double = false # true/false +indent_func_const = 0 # unsigned number +indent_func_throw = 0 # unsigned number +indent_member = 3 # unsigned number +indent_member_single = false # true/false +indent_sing_line_comments = 0 # unsigned number +indent_relative_single_line_comments = false # true/false +indent_switch_case = 4 # unsigned number +indent_switch_pp = true # true/false +indent_case_shift = 0 # unsigned number +indent_case_brace = 3 # number +indent_col1_comment = false # true/false +indent_col1_multi_string_literal = false # true/false +indent_label = 1 # number +indent_access_spec = 1 # number +indent_access_spec_body = false # true/false +indent_paren_nl = false # true/false +indent_paren_close = 0 # unsigned number +indent_paren_after_func_def = false # true/false +indent_paren_after_func_decl = false # true/false +indent_paren_after_func_call = false # true/false +indent_comma_paren = false # true/false +indent_bool_paren = false # true/false +indent_semicolon_for_paren = false # true/false +indent_first_bool_expr = false # true/false +indent_first_for_expr = false # true/false +indent_square_nl = false # true/false +indent_preserve_sql = false # true/false +indent_align_assign = true # true/false +indent_align_paren = true # true/false +indent_oc_block = false # true/false +indent_oc_block_msg = 0 # unsigned number +indent_oc_msg_colon = 0 # unsigned number +indent_oc_msg_prioritize_first_colon = true # true/false +indent_oc_block_msg_xcode_style = false # true/false +indent_oc_block_msg_from_keyword = false # true/false +indent_oc_block_msg_from_colon = false # true/false +indent_oc_block_msg_from_caret = false # true/false +indent_oc_block_msg_from_brace = false # true/false +indent_min_vbrace_open = 0 # unsigned number +indent_vbrace_open_on_tabstop = false # true/false +indent_token_after_brace = true # true/false +indent_cpp_lambda_body = false # true/false +indent_using_block = true # true/false +indent_ternary_operator = 0 # unsigned number +indent_off_after_return_new = false # true/false +indent_single_after_return = false # true/false +indent_ignore_asm_block = false # true/false +nl_collapse_empty_body = false # true/false +nl_assign_leave_one_liners = true # true/false +nl_class_leave_one_liners = true # true/false +nl_enum_leave_one_liners = false # true/false +nl_getset_leave_one_liners = false # true/false +nl_cs_property_leave_one_liners = false # true/false +nl_func_leave_one_liners = false # true/false +nl_cpp_lambda_leave_one_liners = false # true/false +nl_if_leave_one_liners = false # true/false +nl_while_leave_one_liners = false # true/false +nl_for_leave_one_liners = false # true/false +nl_oc_msg_leave_one_liner = false # true/false +nl_oc_mdef_brace = ignore # ignore/add/remove/force +nl_oc_block_brace = ignore # ignore/add/remove/force +nl_oc_interface_brace = ignore # ignore/add/remove/force +nl_oc_implementation_brace = ignore # ignore/add/remove/force +nl_start_of_file = remove # ignore/add/remove/force +nl_start_of_file_min = 0 # unsigned number +nl_end_of_file = force # ignore/add/remove/force +nl_end_of_file_min = 1 # unsigned number +nl_assign_brace = add # ignore/add/remove/force +nl_assign_square = ignore # ignore/add/remove/force +nl_tsquare_brace = ignore # ignore/add/remove/force +nl_after_square_assign = ignore # ignore/add/remove/force +nl_fcall_brace = add # ignore/add/remove/force +nl_enum_brace = force # ignore/add/remove/force +nl_enum_class = ignore # ignore/add/remove/force +nl_enum_class_identifier = ignore # ignore/add/remove/force +nl_enum_identifier_colon = ignore # ignore/add/remove/force +nl_enum_colon_type = ignore # ignore/add/remove/force +nl_struct_brace = force # ignore/add/remove/force +nl_union_brace = force # ignore/add/remove/force +nl_if_brace = add # ignore/add/remove/force +nl_brace_else = add # ignore/add/remove/force +nl_elseif_brace = ignore # ignore/add/remove/force +nl_else_brace = add # ignore/add/remove/force +nl_else_if = ignore # ignore/add/remove/force +nl_before_if_closing_paren = ignore # ignore/add/remove/force +nl_brace_finally = ignore # ignore/add/remove/force +nl_finally_brace = ignore # ignore/add/remove/force +nl_try_brace = ignore # ignore/add/remove/force +nl_getset_brace = force # ignore/add/remove/force +nl_for_brace = add # ignore/add/remove/force +nl_catch_brace = ignore # ignore/add/remove/force +nl_oc_catch_brace = ignore # ignore/add/remove/force +nl_brace_catch = ignore # ignore/add/remove/force +nl_oc_brace_catch = ignore # ignore/add/remove/force +nl_brace_square = ignore # ignore/add/remove/force +nl_brace_fparen = ignore # ignore/add/remove/force +nl_while_brace = add # ignore/add/remove/force +nl_scope_brace = ignore # ignore/add/remove/force +nl_unittest_brace = ignore # ignore/add/remove/force +nl_version_brace = ignore # ignore/add/remove/force +nl_using_brace = ignore # ignore/add/remove/force +nl_brace_brace = ignore # ignore/add/remove/force +nl_do_brace = add # ignore/add/remove/force +nl_brace_while = ignore # ignore/add/remove/force +nl_switch_brace = add # ignore/add/remove/force +nl_synchronized_brace = ignore # ignore/add/remove/force +nl_multi_line_cond = false # true/false +nl_multi_line_define = true # true/false +nl_before_case = true # true/false +nl_after_case = true # true/false +nl_case_colon_brace = ignore # ignore/add/remove/force +nl_before_throw = ignore # ignore/add/remove/force +nl_namespace_brace = ignore # ignore/add/remove/force +nl_template_class = ignore # ignore/add/remove/force +nl_class_brace = ignore # ignore/add/remove/force +nl_class_init_args = ignore # ignore/add/remove/force +nl_constr_init_args = ignore # ignore/add/remove/force +nl_enum_own_lines = ignore # ignore/add/remove/force +nl_func_type_name = remove # ignore/add/remove/force +nl_func_type_name_class = ignore # ignore/add/remove/force +nl_func_class_scope = ignore # ignore/add/remove/force +nl_func_scope_name = ignore # ignore/add/remove/force +nl_func_proto_type_name = remove # ignore/add/remove/force +nl_func_paren = remove # ignore/add/remove/force +nl_func_paren_empty = ignore # ignore/add/remove/force +nl_func_def_paren = remove # ignore/add/remove/force +nl_func_def_paren_empty = ignore # ignore/add/remove/force +nl_func_call_paren = ignore # ignore/add/remove/force +nl_func_call_paren_empty = ignore # ignore/add/remove/force +nl_func_decl_start = remove # ignore/add/remove/force +nl_func_def_start = remove # ignore/add/remove/force +nl_func_decl_start_single = ignore # ignore/add/remove/force +nl_func_def_start_single = ignore # ignore/add/remove/force +nl_func_decl_start_multi_line = false # true/false +nl_func_def_start_multi_line = false # true/false +nl_func_decl_args = add # ignore/add/remove/force +nl_func_def_args = add # ignore/add/remove/force +nl_func_decl_args_multi_line = false # true/false +nl_func_def_args_multi_line = false # true/false +nl_func_decl_end = remove # ignore/add/remove/force +nl_func_def_end = remove # ignore/add/remove/force +nl_func_decl_end_single = ignore # ignore/add/remove/force +nl_func_def_end_single = ignore # ignore/add/remove/force +nl_func_decl_end_multi_line = false # true/false +nl_func_def_end_multi_line = false # true/false +nl_func_decl_empty = ignore # ignore/add/remove/force +nl_func_def_empty = ignore # ignore/add/remove/force +nl_func_call_empty = ignore # ignore/add/remove/force +nl_func_call_start = ignore # ignore/add/remove/force +nl_func_call_start_multi_line = false # true/false +nl_func_call_args_multi_line = false # true/false +nl_func_call_end_multi_line = false # true/false +nl_oc_msg_args = false # true/false +nl_fdef_brace = add # ignore/add/remove/force +nl_fdef_brace_cond = ignore # ignore/add/remove/force +nl_cpp_ldef_brace = ignore # ignore/add/remove/force +nl_return_expr = ignore # ignore/add/remove/force +nl_after_semicolon = true # true/false +nl_paren_dbrace_open = ignore # ignore/add/remove/force +nl_type_brace_init_lst = ignore # ignore/add/remove/force +nl_type_brace_init_lst_open = ignore # ignore/add/remove/force +nl_type_brace_init_lst_close = ignore # ignore/add/remove/force +nl_after_brace_open = true # true/false +nl_after_brace_open_cmt = false # true/false +nl_after_vbrace_open = false # true/false +nl_after_vbrace_open_empty = false # true/false +nl_after_brace_close = true # true/false +nl_after_vbrace_close = false # true/false +nl_brace_struct_var = ignore # ignore/add/remove/force +nl_define_macro = false # true/false +nl_squeeze_paren_close = false # true/false +nl_squeeze_ifdef = true # true/false +nl_squeeze_ifdef_top_level = false # true/false +nl_before_if = force # ignore/add/remove/force +nl_after_if = force # ignore/add/remove/force +nl_before_for = force # ignore/add/remove/force +nl_after_for = force # ignore/add/remove/force +nl_before_while = force # ignore/add/remove/force +nl_after_while = force # ignore/add/remove/force +nl_before_switch = force # ignore/add/remove/force +nl_after_switch = force # ignore/add/remove/force +nl_before_synchronized = ignore # ignore/add/remove/force +nl_after_synchronized = ignore # ignore/add/remove/force +nl_before_do = force # ignore/add/remove/force +nl_after_do = force # ignore/add/remove/force +nl_before_return = false # true/false +nl_after_return = true # true/false +nl_ds_struct_enum_cmt = false # true/false +nl_ds_struct_enum_close_brace = false # true/false +nl_class_colon = ignore # ignore/add/remove/force +nl_constr_colon = ignore # ignore/add/remove/force +nl_namespace_two_to_one_liner = false # true/false +nl_create_if_one_liner = false # true/false +nl_create_for_one_liner = false # true/false +nl_create_while_one_liner = false # true/false +nl_create_func_def_one_liner = false # true/false +nl_split_if_one_liner = false # true/false +nl_split_for_one_liner = false # true/false +nl_split_while_one_liner = false # true/false +nl_max = 4 # unsigned number +nl_max_blank_in_func = 0 # unsigned number +nl_before_func_body_proto = 0 # unsigned number +nl_before_func_body_def = 0 # unsigned number +nl_before_func_class_proto = 0 # unsigned number +nl_before_func_class_def = 0 # unsigned number +nl_after_func_proto = 0 # unsigned number +nl_after_func_proto_group = 1 # unsigned number +nl_after_func_class_proto = 0 # unsigned number +nl_after_func_class_proto_group = 0 # unsigned number +nl_class_leave_one_liner_groups = false # true/false +nl_after_func_body = 0 # unsigned number +nl_after_func_body_class = 2 # unsigned number +nl_after_func_body_one_liner = 0 # unsigned number +nl_func_var_def_blk = 1 # unsigned number +nl_typedef_blk_start = 0 # unsigned number +nl_typedef_blk_end = 0 # unsigned number +nl_typedef_blk_in = 0 # unsigned number +nl_var_def_blk_start = 0 # unsigned number +nl_var_def_blk_end = 0 # unsigned number +nl_var_def_blk_in = 0 # unsigned number +nl_before_block_comment = 2 # unsigned number +nl_before_c_comment = 0 # unsigned number +nl_before_cpp_comment = 0 # unsigned number +nl_after_multiline_comment = false # true/false +nl_after_label_colon = false # true/false +nl_after_struct = 0 # unsigned number +nl_before_class = 0 # unsigned number +nl_after_class = 0 # unsigned number +nl_before_access_spec = 0 # unsigned number +nl_after_access_spec = 0 # unsigned number +nl_comment_func_def = 0 # unsigned number +nl_after_try_catch_finally = 0 # unsigned number +nl_around_cs_property = 0 # unsigned number +nl_between_get_set = 0 # unsigned number +nl_property_brace = ignore # ignore/add/remove/force +nl_inside_namespace = 0 # unsigned number +eat_blanks_after_open_brace = true # true/false +eat_blanks_before_close_brace = true # true/false +nl_remove_extra_newlines = 0 # unsigned number +nl_after_annotation = ignore # ignore/add/remove/force +nl_between_annotation = ignore # ignore/add/remove/force +pos_arith = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_assign = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_bool = trail # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_compare = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_conditional = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_enum_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_class_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_constr_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_class_colon = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_constr_colon = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +code_width = 0 # unsigned number +ls_for_split_full = false # true/false +ls_func_split_full = false # true/false +ls_code_width = false # true/false +align_keep_tabs = false # true/false +align_with_tabs = false # true/false +align_on_tabstop = false # true/false +align_number_right = false # true/false +align_keep_extra_space = false # true/false +align_func_params = false # true/false +align_func_params_span = 0 # unsigned number +align_func_params_thresh = 0 # number +align_func_params_gap = 0 # unsigned number +align_constr_value_span = 0 # unsigned number +align_constr_value_thresh = 0 # number +align_constr_value_gap = 0 # unsigned number +align_same_func_call_params = false # true/false +align_same_func_call_params_span = 0 # unsigned number +align_same_func_call_params_thresh = 0 # number +align_var_def_span = 0 # unsigned number +align_var_def_star_style = 0 # unsigned number +align_var_def_amp_style = 1 # unsigned number +align_var_def_thresh = 16 # number +align_var_def_gap = 0 # unsigned number +align_var_def_colon = false # true/false +align_var_def_colon_gap = 0 # unsigned number +align_var_def_attribute = false # true/false +align_var_def_inline = false # true/false +align_assign_span = 0 # unsigned number +align_assign_func_proto_span = 0 # unsigned number +align_assign_thresh = 12 # number +align_assign_decl_func = 0 # unsigned number +align_enum_equ_span = 0 # unsigned number +align_enum_equ_thresh = 0 # number +align_var_class_span = 0 # unsigned number +align_var_class_thresh = 0 # number +align_var_class_gap = 0 # unsigned number +align_var_struct_span = 0 # unsigned number +align_var_struct_thresh = 0 # number +align_var_struct_gap = 0 # unsigned number +align_struct_init_span = 3 # unsigned number +align_typedef_span = 5 # unsigned number +align_typedef_gap = 3 # unsigned number +align_typedef_func = 0 # unsigned number +align_typedef_star_style = 1 # unsigned number +align_typedef_amp_style = 1 # unsigned number +align_right_cmt_span = 3 # unsigned number +align_right_cmt_gap = 0 # unsigned number +align_right_cmt_mix = false # true/false +align_right_cmt_same_level = false # true/false +align_right_cmt_at_col = 0 # unsigned number +align_func_proto_span = 0 # unsigned number +align_func_proto_thresh = 0 # number +align_func_proto_gap = 0 # unsigned number +align_on_operator = false # true/false +align_mix_var_proto = false # true/false +align_single_line_func = false # true/false +align_single_line_brace = false # true/false +align_single_line_brace_gap = 0 # unsigned number +align_oc_msg_spec_span = 0 # unsigned number +align_nl_cont = true # true/false +align_pp_define_together = false # true/false +align_pp_define_span = 3 # unsigned number +align_pp_define_gap = 4 # unsigned number +align_left_shift = true # true/false +align_asm_colon = false # true/false +align_oc_msg_colon_span = 0 # unsigned number +align_oc_msg_colon_first = false # true/false +align_oc_decl_colon = false # true/false +cmt_width = 0 # unsigned number +cmt_reflow_mode = 0 # unsigned number +cmt_convert_tab_to_spaces = false # true/false +cmt_indent_multi = true # true/false +cmt_c_group = false # true/false +cmt_c_nl_start = false # true/false +cmt_c_nl_end = false # true/false +cmt_cpp_to_c = true # true/false +cmt_cpp_group = false # true/false +cmt_cpp_nl_start = false # true/false +cmt_cpp_nl_end = false # true/false +cmt_star_cont = true # true/false +cmt_sp_before_star_cont = 0 # unsigned number +cmt_sp_after_star_cont = 0 # unsigned number +cmt_multi_check_last = true # true/false +cmt_multi_first_len_minimum = 4 # unsigned number +cmt_insert_file_header = "" # string +cmt_insert_file_footer = "" # string +cmt_insert_func_header = "" # string +cmt_insert_class_header = "" # string +cmt_insert_oc_msg_header = "" # string +cmt_insert_before_preproc = false # true/false +cmt_insert_before_inlines = true # true/false +cmt_insert_before_ctor_dtor = false # true/false +mod_full_brace_do = add # ignore/add/remove/force +mod_full_brace_for = add # ignore/add/remove/force +mod_full_brace_function = ignore # ignore/add/remove/force +mod_full_brace_if = add # ignore/add/remove/force +mod_full_brace_if_chain = false # true/false +mod_full_brace_if_chain_only = false # true/false +mod_full_brace_while = add # ignore/add/remove/force +mod_full_brace_using = ignore # ignore/add/remove/force +mod_full_brace_nl = 0 # unsigned number +mod_full_brace_nl_block_rem_mlcond = false # true/false +mod_paren_on_return = ignore # ignore/add/remove/force +mod_pawn_semicolon = false # true/false +mod_full_paren_if_bool = true # true/false +mod_remove_extra_semicolon = true # true/false +mod_add_long_function_closebrace_comment = 0 # unsigned number +mod_add_long_namespace_closebrace_comment = 0 # unsigned number +mod_add_long_class_closebrace_comment = 0 # unsigned number +mod_add_long_switch_closebrace_comment = 0 # unsigned number +mod_add_long_ifdef_endif_comment = 10 # unsigned number +mod_add_long_ifdef_else_comment = 10 # unsigned number +mod_sort_import = false # true/false +mod_sort_using = false # true/false +mod_sort_include = false # true/false +mod_move_case_break = false # true/false +mod_case_brace = remove # ignore/add/remove/force +mod_remove_empty_return = true # true/false +mod_enum_last_comma = ignore # ignore/add/remove/force +mod_sort_oc_properties = false # true/false +mod_sort_oc_property_class_weight = 0 # number +mod_sort_oc_property_thread_safe_weight = 0 # number +mod_sort_oc_property_readwrite_weight = 0 # number +mod_sort_oc_property_reference_weight = 0 # number +mod_sort_oc_property_getter_weight = 0 # number +mod_sort_oc_property_setter_weight = 0 # number +mod_sort_oc_property_nullability_weight = 0 # number +pp_indent = force # ignore/add/remove/force +pp_indent_at_level = true # true/false +pp_indent_count = 4 # unsigned number +pp_space = remove # ignore/add/remove/force +pp_space_count = 0 # unsigned number +pp_indent_region = 0 # number +pp_region_indent_code = false # true/false +pp_indent_if = 0 # number +pp_if_indent_code = true # true/false +pp_define_at_level = false # true/false +pp_ignore_define_body = false # true/false +pp_indent_case = true # true/false +pp_indent_func_def = true # true/false +pp_indent_extern = true # true/false +pp_indent_brace = false # true/false +include_category_0 = "" # string +include_category_1 = "" # string +include_category_2 = "" # string +use_indent_func_call_param = true # true/false +use_indent_continue_only_once = false # true/false +indent_cpp_lambda_only_once = false # true/false +use_options_overriding_for_qt_macros = true # true/false +warn_level_tabs_found_in_verbatim_string_literals = 2 # unsigned number diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/auto-release.yml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/auto-release.yml new file mode 100644 index 0000000..3bf820a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/auto-release.yml @@ -0,0 +1,77 @@ +name: Kernel-Auto-Release + +on: + workflow_dispatch: + inputs: + commit_id: + description: 'Commit ID' + required: true + default: 'HEAD' + version_number: + description: 'Version Number (Ex. 10.4.4)' + required: true + default: '10.4.4' + main_br_version: + description: "Version String for task.h on main branch (leave empty to leave as-is)." + required: false + default: '' + +jobs: + release-packager: + name: Release Packager + runs-on: ubuntu-latest + steps: + # Install python 3 + - name: Tool Setup + uses: actions/setup-python@v2 + with: + python-version: 3.7.10 + architecture: x64 + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + + # Currently FreeRTOS/.github/scripts houses the release script. Download it for upcoming usage + - name: Checkout FreeRTOS Release Tools + uses: actions/checkout@v2 + with: + repository: FreeRTOS/FreeRTOS + path: tools + + # Simpler git auth if we use checkout action and forward the repo to release script + - name: Checkout FreeRTOS Kernel + uses: actions/checkout@v2 + with: + path: local_kernel + fetch-depth: 0 + + - name: Configure git identity + run: | + git config --global user.name ${{ github.actor }} + git config --global user.email ${{ github.actor }}@users.noreply.github.com + + - name: create a new branch that references commit id + working-directory: ./local_kernel + run: git checkout -b ${{ github.event.inputs.version_number }} ${{ github.event.inputs.commit_id }} + + - name: Generate SBOM + uses: FreeRTOS/CI-CD-Github-Actions/sbom-generator@main + with: + repo_path: ./local_kernel + source_path: ./ + + - name: commit SBOM file + working-directory: ./local_kernel + run: | + git add . + git commit -m 'Update SBOM' + git push -u origin ${{ github.event.inputs.version_number }} + echo "COMMIT_SHA=$(git rev-parse HEAD)" >> $GITHUB_ENV + + - name: Release + run: | + # Install deps and run + pip install -r ./tools/.github/scripts/release-requirements.txt + ./tools/.github/scripts/release.py FreeRTOS --kernel-repo-path=local_kernel --kernel-commit=${{ env.COMMIT_SHA }} --new-kernel-version=${{ github.event.inputs.version_number }} --new-kernel-main-br-version=${{ github.event.inputs.main_br_version }} + exit $? + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/ci.yml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/ci.yml new file mode 100644 index 0000000..e3a622d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/ci.yml @@ -0,0 +1,68 @@ +name: CI Checks +on: + push: + branches: ["**"] + pull_request: + branches: [main] + workflow_dispatch: +jobs: + spell-check: + runs-on: ubuntu-latest + steps: + - name: Checkout Parent Repo + uses: actions/checkout@v2 + with: + ref: main + repository: aws/aws-iot-device-sdk-embedded-C + path: main + - name: Clone This Repo + uses: actions/checkout@v2 + with: + path: ./kernel + - name: Install spell + run: | + sudo apt-get install spell + sudo apt-get install util-linux + - name: Check spelling + run: | + PATH=$PATH:main/tools/spell + # Make sure that the portable directory is not included in the spellcheck. + sed -i 's/find $DIRNAME/find $DIRNAME -not -path '*portable*'/g' main/tools/spell/find-unknown-comment-words + find-unknown-comment-words --directory kernel/ --lexicon ./kernel/.github/lexicon.txt + if [ "$?" = "0" ]; then + exit 0 + else + exit 1 + fi + formatting: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - name: Install Uncrustify + run: sudo apt-get install uncrustify=0.69.0+dfsg1-1build1 + - name: Run Uncrustify + run: | + uncrustify --version + find . portable/MemMang/* portable/Common/* \( -name portable \) -prune -false -o -iname "*.[hc]" -exec uncrustify --check -c .github/uncrustify.cfg {} + + - name: Check For Trailing Whitespace + run: | + set +e + grep --exclude="README.md" --exclude-dir="portable" -rnI -e "[[:blank:]]$" . + if [ "$?" = "0" ]; then + echo "Files have trailing whitespace." + exit 1 + else + exit 0 + fi + + url-check: + runs-on: ubuntu-latest + steps: + - name: Clone This Repo + uses: actions/checkout@v2 + with: + path: ./kernel + - name: URL Checker + run: | + bash kernel/.github/actions/url_verifier.sh kernel + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/git-secrets.yml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/git-secrets.yml new file mode 100644 index 0000000..b78a79c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/git-secrets.yml @@ -0,0 +1,24 @@ +name: git-secrets Check +on: + push: + pull_request: + workflow_dispatch: +jobs: + git-secrets: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + with: + submodules: recursive + - name: Checkout awslabs/git-secrets + uses: actions/checkout@v2 + with: + repository: awslabs/git-secrets + ref: master + path: git-secrets + - name: Install git-secrets + run: cd git-secrets && sudo make install && cd .. + - name: Run git-secrets + run: | + git-secrets --register-aws + git-secrets --scan diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/kernel-checks.yml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/kernel-checks.yml new file mode 100644 index 0000000..7087bb8 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/kernel-checks.yml @@ -0,0 +1,72 @@ +name: Kernel-Checker + +on: [push, pull_request] + +jobs: + kernel-checker: + name: FreeRTOS Kernel Header Checks + runs-on: ubuntu-latest + steps: + # Install python 3 + - name: Tool Setup + uses: actions/setup-python@v2 + with: + python-version: 3.7.10 + architecture: x64 + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + + # There is shared code, hosted by FreeRTOS/FreeRTOS, with deps needed by header checker + - name: Checkout FreeRTOS Tools + uses: actions/checkout@v2 + with: + repository: FreeRTOS/FreeRTOS + ref: main + path: tools + + # Checkout user pull request changes + - name: Checkout Pull Request + uses: actions/checkout@v2 + with: + ref: ${{ github.event.pull_request.head.sha }} + path: inspect + + # Collect all affected files + - name: Collecting changed files + uses: lots0logs/gh-action-get-changed-files@2.1.4 + with: + token: ${{ secrets.GITHUB_TOKEN }} + + # Run checks + - name: Check File Headers + run: | + mv tools/.github/scripts/common inspect/.github/scripts + pip install -r inspect/.github/scripts/common/requirements.txt + cd inspect + .github/scripts/kernel_checker.py --json ${HOME}/files_modified.json ${HOME}/files_added.json ${HOME}/files_renamed.json + exit $? + build-checker: + name: FreeRTOS Posix Build Check + runs-on: ubuntu-latest + steps: + - name: Checkout the parent repository + uses: actions/checkout@v2 + with: + ref: main + repository: FreeRTOS/FreeRTOS + submodules: 'recursive' + fetch-depth: 1 + path: ./workspace + - name: Checkout the current repository + uses: actions/checkout@v2 + with: + path: ./workspace/FreeRTOS/Source + - name: Posix Build Checker + run: | + bash workspace/.github/scripts/posix_build_checker.sh workspace + - name: Install lib pcap dev + run: | + sudo apt-get install libpcap-dev + - name: Posix Network Build Checker + run: | + bash workspace/.github/scripts/posix_network_build_checker.sh workspace diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/unit-tests.yml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/unit-tests.yml new file mode 100644 index 0000000..0039e5b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/.github/workflows/unit-tests.yml @@ -0,0 +1,54 @@ +name: CMock Unit Tests +on: [push, pull_request] + +jobs: + run: + runs-on: ubuntu-latest + steps: + - name: Checkout Parent Repository + uses: actions/checkout@v2 + with: + ref: main + repository: FreeRTOS/FreeRTOS + submodules: 'recursive' + fetch-depth: 1 + - name: Clone This Repo + uses: actions/checkout@v2 + with: + path: ./FreeRTOS/Source + + - name: Setup Python + uses: actions/setup-python@master + with: + python-version: 3.8 + + - name: Install packages + run: | + sudo apt-get install lcov cflow ruby doxygen build-essential unifdef + - name: Run Unit Tests with ENABLE_SANITIZER=1 + run: | + make -C FreeRTOS/Test/CMock clean + make -C FreeRTOS/Test/CMock ENABLE_SANITIZER=1 run_col_formatted + - name: Run Unit Tests for coverage + run: | + make -C FreeRTOS/Test/CMock clean + make -C FreeRTOS/Test/CMock lcovhtml + lcov --config-file FreeRTOS/Test/CMock/lcovrc --summary FreeRTOS/Test/CMock/build/cmock_test.info > FreeRTOS/Test/CMock/build/cmock_test_summary.txt + - name: Upload coverage to Codecov + uses: codecov/codecov-action@v3.1.0 + with: + files: ${{ github.workspace }}/FreeRTOS/Test/CMock/build/cmock_test.info + root_dir: ${{ github.workspace }}/FreeRTOS/Source + flags: unittests + fail_ci_if_error: false + verbose: false + - name: Archive code coverage data + uses: actions/upload-artifact@v2 + with: + name: coverage-data + path: FreeRTOS/Test/CMock/build/cmock_test* + - name: Archive code coverage html report + uses: actions/upload-artifact@v2 + with: + name: coverage-report + path: FreeRTOS/Test/CMock/build/coverage diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/CMakeLists.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/CMakeLists.txt new file mode 100644 index 0000000..5b048d2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/CMakeLists.txt @@ -0,0 +1,208 @@ +cmake_minimum_required(VERSION 3.15) + +# User is responsible to set two mandatory options: +# FREERTOS_CONFIG_FILE_DIRECTORY +# FREERTOS_PORT +# +# User can choose which heap implementation to use (either the implementations +# included with FreeRTOS [1..5] or a custom implementation ) by providing the +# option FREERTOS_HEAP. If the option is not set, the cmake will default to +# using heap_4.c. + +# Absolute path to FreeRTOS config file directory +set(FREERTOS_CONFIG_FILE_DIRECTORY "" CACHE STRING "Absolute path to the directory with FreeRTOSConfig.h") + +if(NOT FREERTOS_CONFIG_FILE_DIRECTORY) + message(FATAL_ERROR " FreeRTOSConfig.h file directory not specified. Please specify absolute path to it from top-level CMake file:\n" + " set(FREERTOS_CONFIG_FILE_DIRECTORY CACHE STRING \"\")\n" + " or from CMake command line option:\n" + " -DFREERTOS_CONFIG_FILE_DIRECTORY='/absolute_path/to/FreeRTOSConfig.h/directory'") +elseif(NOT EXISTS ${FREERTOS_CONFIG_FILE_DIRECTORY}/FreeRTOSConfig.h) + message(FATAL_ERROR " FreeRTOSConfig.h file not found in the directory specified (${FREERTOS_CONFIG_FILE_DIRECTORY})\n" + " Please specify absolute path to it from top-level CMake file:\n" + " set(FREERTOS_CONFIG_FILE_DIRECTORY CACHE STRING \"\")\n" + " or from CMake command line option:\n" + " -DFREERTOS_CONFIG_FILE_DIRECTORY='/absolute_path/to/FreeRTOSConfig.h/directory'") +endif() + +# Heap number or absolute path to custom heap implementation provided by user +set(FREERTOS_HEAP "4" CACHE STRING "FreeRTOS heap model number. 1 .. 5. Or absolute path to custom heap source file") + +# FreeRTOS port option +set(FREERTOS_PORT "" CACHE STRING "FreeRTOS port name") + +if(NOT FREERTOS_PORT) + message(FATAL_ERROR " FREERTOS_PORT is not set. Please specify it from top-level CMake file (example):\n" + " set(FREERTOS_PORT GCC_ARM_CM4F CACHE STRING \"\")\n" + " or from CMake command line option:\n" + " -DFREERTOS_PORT=GCC_ARM_CM4F\n" + " \n" + " Available port options:\n" + " BCC_16BIT_DOS_FLSH186 - Compiller: BCC Target: 16 bit DOS Flsh186\n" + " BCC_16BIT_DOS_PC - Compiller: BCC Target: 16 bit DOS PC\n" + " CCS_ARM_CM3 - Compiller: CCS Target: ARM Cortex-M3\n" + " CCS_ARM_CM4F - Compiller: CCS Target: ARM Cortex-M4 with FPU\n" + " CCS_ARM_CR4 - Compiller: CCS Target: ARM Cortex-R4\n" + " CCS_MSP430X - Compiller: CCS Target: MSP430X\n" + " CODEWARRIOR_COLDFIRE_V1 - Compiller: CoreWarrior Target: ColdFire V1\n" + " CODEWARRIOR_COLDFIRE_V2 - Compiller: CoreWarrior Target: ColdFire V2\n" + " CODEWARRIOR_HCS12 - Compiller: CoreWarrior Target: HCS12\n" + " GCC_ARM_CA9 - Compiller: GCC Target: ARM Cortex-A9\n" + " GCC_ARM_CA53_64_BIT - Compiller: GCC Target: ARM Cortex-A53 64 bit\n" + " GCC_ARM_CA53_64_BIT_SRE - Compiller: GCC Target: ARM Cortex-A53 64 bit SRE\n" + " GCC_ARM_CM0 - Compiller: GCC Target: ARM Cortex-M0\n" + " GCC_ARM_CM3 - Compiller: GCC Target: ARM Cortex-M3\n" + " GCC_ARM_CM3_MPU - Compiller: GCC Target: ARM Cortex-M3 with MPU\n" + " GCC_ARM_CM4_MPU - Compiller: GCC Target: ARM Cortex-M4 with MPU\n" + " GCC_ARM_CM4F - Compiller: GCC Target: ARM Cortex-M4 with FPU\n" + " GCC_ARM_CM7 - Compiller: GCC Target: ARM Cortex-M7\n" + " GCC_ARM_CM23_NONSECURE - Compiller: GCC Target: ARM Cortex-M23 non-secure\n" + " GCC_ARM_CM23_SECURE - Compiller: GCC Target: ARM Cortex-M23 secure\n" + " GCC_ARM_CM23_NTZ_NONSECURE - Compiller: GCC Target: ARM Cortex-M23 non-trustzone non-secure\n" + " GCC_ARM_CM33_NONSECURE - Compiller: GCC Target: ARM Cortex-M33 non-secure\n" + " GCC_ARM_CM33_SECURE - Compiller: GCC Target: ARM Cortex-M33 secure\n" + " GCC_ARM_CM33_NTZ_NONSECURE - Compiller: GCC Target: ARM Cortex-M33 non-trustzone non-secure\n" + " GCC_ARM_CM33_TFM - Compiller: GCC Target: ARM Cortex-M33 non-secure for TF-M\n" + " GCC_ARM_CM55_NONSECURE - Compiller: GCC Target: ARM Cortex-M55 non-secure\n" + " GCC_ARM_CM55_SECURE - Compiller: GCC Target: ARM Cortex-M55 secure\n" + " GCC_ARM_CM55_NTZ_NONSECURE - Compiller: GCC Target: ARM Cortex-M55 non-trustzone non-secure\n" + " GCC_ARM_CM55_TFM - Compiller: GCC Target: ARM Cortex-M55 non-secure for TF-M\n" + " GCC_ARM_CM85_NONSECURE - Compiller: GCC Target: ARM Cortex-M85 non-secure\n" + " GCC_ARM_CM85_SECURE - Compiller: GCC Target: ARM Cortex-M85 secure\n" + " GCC_ARM_CM85_NTZ_NONSECURE - Compiller: GCC Target: ARM Cortex-M85 non-trustzone non-secure\n" + " GCC_ARM_CM85_TFM - Compiller: GCC Target: ARM Cortex-M85 non-secure for TF-M\n" + " GCC_ARM_CR5 - Compiller: GCC Target: ARM Cortex-R5\n" + " GCC_ARM_CRX_NOGIC - Compiller: GCC Target: ARM Cortex-Rx no GIC\n" + " GCC_ARM7_AT91FR40008 - Compiller: GCC Target: ARM7 Atmel AT91R40008\n" + " GCC_ARM7_AT91SAM7S - Compiller: GCC Target: ARM7 Atmel AT91SAM7S\n" + " GCC_ARM7_LPC2000 - Compiller: GCC Target: ARM7 LPC2000\n" + " GCC_ARM7_LPC23XX - Compiller: GCC Target: ARM7 LPC23xx\n" + " GCC_ATMEGA323 - Compiller: GCC Target: ATMega323\n" + " GCC_AVR32_UC3 - Compiller: GCC Target: AVR32 UC3\n" + " GCC_COLDFIRE_V2 - Compiller: GCC Target: ColdFire V2\n" + " GCC_CORTUS_APS3 - Compiller: GCC Target: CORTUS APS3\n" + " GCC_H8S2329 - Compiller: GCC Target: H8S2329\n" + " GCC_HCS12 - Compiller: GCC Target: HCS12\n" + " GCC_IA32_FLAT - Compiller: GCC Target: IA32 flat\n" + " GCC_MICROBLAZE - Compiller: GCC Target: MicroBlaze\n" + " GCC_MICROBLAZE_V8 - Compiller: GCC Target: MicroBlaze V8\n" + " GCC_MICROBLAZE_V9 - Compiller: GCC Target: MicroBlaze V9\n" + " GCC_MSP430F449 - Compiller: GCC Target: MSP430F449\n" + " GCC_NIOSII - Compiller: GCC Target: NiosII\n" + " GCC_PPC405_XILINX - Compiller: GCC Target: Xilinx PPC405\n" + " GCC_PPC440_XILINX - Compiller: GCC Target: Xilinx PPC440\n" + " GCC_RISC_V - Compiller: GCC Target: RISC-V\n" + " GCC_RISC_V_PULPINO_VEGA_RV32M1RM - Compiller: GCC Target: RISC-V Pulpino Vega RV32M1RM\n" + " GCC_RL78 - Compiller: GCC Target: Renesas RL78\n" + " GCC_RX100 - Compiller: GCC Target: Renesas RX100\n" + " GCC_RX200 - Compiller: GCC Target: Renesas RX200\n" + " GCC_RX600 - Compiller: GCC Target: Renesas RX600\n" + " GCC_RX600_V2 - Compiller: GCC Target: Renesas RX600 v2\n" + " GCC_RX700_V3_DPFPU - Compiller: GCC Target: Renesas RX700 v3 with DPFPU\n" + " GCC_STR75X - Compiller: GCC Target: STR75x\n" + " GCC_TRICORE_1782 - Compiller: GCC Target: TriCore 1782\n" + " GCC_ARC_EM_HS - Compiller: GCC Target: DesignWare ARC EM HS\n" + " GCC_ARC_V1 - Compiller: GCC Target: DesignWare ARC v1\n" + " GCC_ATMEGA - Compiller: GCC Target: ATmega\n" + " GCC_POSIX - Compiller: GCC Target: Posix\n" + " GCC_RP2040 - Compiller: GCC Target: RP2040 ARM Cortex-M0+\n" + " GCC_XTENSA_ESP32 - Compiller: GCC Target: Xtensa ESP32\n" + " GCC_AVRDX - Compiller: GCC Target: AVRDx\n" + " GCC_AVR_MEGA0 - Compiller: GCC Target: AVR Mega0\n" + " IAR_78K0K - Compiller: IAR Target: Renesas 78K0K\n" + " IAR_ARM_CA5_NOGIC - Compiller: IAR Target: ARM Cortex-A5 no GIC\n" + " IAR_ARM_CA9 - Compiller: IAR Target: ARM Cortex-A9\n" + " IAR_ARM_CM0 - Compiller: IAR Target: ARM Cortex-M0\n" + " IAR_ARM_CM3 - Compiller: IAR Target: ARM Cortex-M3\n" + " IAR_ARM_CM4F - Compiller: IAR Target: ARM Cortex-M4 with FPU\n" + " IAR_ARM_CM4F_MPU - Compiller: IAR Target: ARM Cortex-M4 with FPU and MPU\n" + " IAR_ARM_CM7 - Compiller: IAR Target: ARM Cortex-M7\n" + " IAR_ARM_CM23_NONSECURE - Compiller: IAR Target: ARM Cortex-M23 non-secure\n" + " IAR_ARM_CM23_SECURE - Compiller: IAR Target: ARM Cortex-M23 secure\n" + " IAR_ARM_CM23_NTZ_NONSECURE - Compiller: IAR Target: ARM Cortex-M23 non-trustzone non-secure\n" + " IAR_ARM_CM33_NONSECURE - Compiller: IAR Target: ARM Cortex-M33 non-secure\n" + " IAR_ARM_CM33_SECURE - Compiller: IAR Target: ARM Cortex-M33 secure\n" + " IAR_ARM_CM33_NTZ_NONSECURE - Compiller: IAR Target: ARM Cortex-M33 non-trustzone non-secure\n" + " IAR_ARM_CM55_NONSECURE - Compiller: IAR Target: ARM Cortex-M55 non-secure\n" + " IAR_ARM_CM55_SECURE - Compiller: IAR Target: ARM Cortex-M55 secure\n" + " IAR_ARM_CM55_NTZ_NONSECURE - Compiller: IAR Target: ARM Cortex-M55 non-trustzone non-secure\n" + " IAR_ARM_CM85_NONSECURE - Compiller: IAR Target: ARM Cortex-M85 non-secure\n" + " IAR_ARM_CM85_SECURE - Compiller: IAR Target: ARM Cortex-M85 secure\n" + " IAR_ARM_CM85_NTZ_NONSECURE - Compiller: IAR Target: ARM Cortex-M85 non-trustzone non-secure\n" + " IAR_ARM_CRX_NOGIC - Compiller: IAR Target: ARM Cortex-Rx no GIC\n" + " IAR_ATMEGA323 - Compiller: IAR Target: ATMega323\n" + " IAR_ATMEL_SAM7S64 - Compiller: IAR Target: Atmel SAM7S64\n" + " IAR_ATMEL_SAM9XE - Compiller: IAR Target: Atmel SAM9XE\n" + " IAR_AVR_AVRDX - Compiller: IAR Target: AVRDx\n" + " IAR_AVR_MEGA0 - Compiller: IAR Target: AVR Mega0\n" + " IAR_AVR32_UC3 - Compiller: IAR Target: AVR32 UC3\n" + " IAR_LPC2000 - Compiller: IAR Target: LPC2000\n" + " IAR_MSP430 - Compiller: IAR Target: MSP430\n" + " IAR_MSP430X - Compiller: IAR Target: MSP430X\n" + " IAR_RISC_V - Compiller: IAR Target: RISC-V\n" + " IAR_RL78 - Compiller: IAR Target: Renesas RL78\n" + " IAR_RX100 - Compiller: IAR Target: Renesas RX100\n" + " IAR_RX600 - Compiller: IAR Target: Renesas RX600\n" + " IAR_RX700_V3_DPFPU - Compiller: IAR Target: Renesas RX700 v3 with DPFPU\n" + " IAR_RX_V2 - Compiller: IAR Target: Renesas RX v2\n" + " IAR_STR71X - Compiller: IAR Target: STR71x\n" + " IAR_STR75X - Compiller: IAR Target: STR75x\n" + " IAR_STR91X - Compiller: IAR Target: STR91x\n" + " IAR_V850ES_FX3 - Compiller: IAR Target: Renesas V850ES/Fx3\n" + " IAR_V850ES_HX3 - Compiller: IAR Target: Renesas V850ES/Hx3\n" + " MIKROC_ARM_CM4F - Compiller: MikroC Target: ARM Cortex-M4 with FPU\n" + " MPLAB_PIC18F - Compiller: MPLAB Target: PIC18F\n" + " MPLAB_PIC24 - Compiller: MPLAB Target: PIC24\n" + " MPLAB_PIC32MEC14XX - Compiller: MPLAB Target: PIC32MEC14xx\n" + " MPLAB_PIC32MX - Compiller: MPLAB Target: PIC32MX\n" + " MPLAB_PIC32MZ - Compiller: MPLAB Target: PIC32MZ\n" + " MSVC_MINGW - Compiller: MSVC or MinGW Target: x86\n" + " OWATCOM_16BIT_DOS_FLSH186 - Compiller: Open Watcom Target: 16 bit DOS Flsh186\n" + " OWATCOM_16BIT_DOS_PC - Compiller: Open Watcom Target: 16 bit DOS PC\n" + " PARADIGM_TERN_EE_LARGE - Compiller: Paradigm Target: Tern EE large\n" + " PARADIGM_TERN_EE_SMALL - Compiller: Paradigm Target: Tern EE small\n" + " RENESAS_RX100 - Compiller: Renesas Target: RX100\n" + " RENESAS_RX200 - Compiller: Renesas Target: RX200\n" + " RENESAS_RX600 - Compiller: Renesas Target: RX600\n" + " RENESAS_RX600_V2 - Compiller: Renesas Target: RX600 v2\n" + " RENESAS_RX700_V3_DPFPU - Compiller: Renesas Target: RX700 v3 with DPFPU\n" + " RENESAS_SH2A_FPU - Compiller: Renesas Target: SH2A with FPU\n" + " ROWLEY_MSP430F449 - Compiller: Rowley Target: MSP430F449\n" + " RVDS_ARM_CA9 - Compiller: RVDS Target: ARM Cortex-A9\n" + " RVDS_ARM_CM0 - Compiller: RVDS Target: ARM Cortex-M0\n" + " RVDS_ARM_CM3 - Compiller: RVDS Target: ARM Cortex-M3\n" + " RVDS_ARM_CM4_MPU - Compiller: RVDS Target: ARM Cortex-M4 with MPU\n" + " RVDS_ARM_CM4F - Compiller: RVDS Target: ARM Cortex-M4 with FPU\n" + " RVDS_ARM_CM7 - Compiller: RVDS Target: ARM Cortex-M7\n" + " RVDS_ARM7_LPC21XX - Compiller: RVDS Target: ARM7 LPC21xx\n" + " SDCC_CYGNAL - Compiller: SDCC Target: Cygnal\n" + " SOFTUNE_MB91460 - Compiller: Softune Target: MB91460\n" + " SOFTUNE_MB96340 - Compiller: Softune Target: MB96340\n" + " TASKING_ARM_CM4F - Compiller: Tasking Target: ARM Cortex-M4 with FPU\n" + " CDK_THEAD_CK802 - Compiller: CDK Target: T-head CK802\n" + " XCC_XTENSA - Compiller: XCC Target: Xtensa\n" + " WIZC_PIC18 - Compiller: WizC Target: PIC18") +endif() + +add_subdirectory(portable) + +add_library(freertos_kernel STATIC + croutine.c + event_groups.c + list.c + queue.c + stream_buffer.c + tasks.c + timers.c + + # If FREERTOS_HEAP is digit between 1 .. 5 - it is heap number, otherwise - it is path to custom heap source file + $>,${FREERTOS_HEAP},portable/MemMang/heap_${FREERTOS_HEAP}.c> +) + +target_include_directories(freertos_kernel + PUBLIC + include + ${FREERTOS_CONFIG_FILE_DIRECTORY} +) + +target_link_libraries(freertos_kernel freertos_kernel_port) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/ChangeLogKSDK.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/ChangeLogKSDK.txt new file mode 100644 index 0000000..91a0697 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/ChangeLogKSDK.txt @@ -0,0 +1,52 @@ +/** +@page rtos_log RTOS Change Log + +@section FreeRTOS kernel for MCUXpresso SDK. +The current version is FreeRTOS kernel 10.4.3-LTS-Patch-2 Original package is available at github.com/FreeRTOS/FreeRTOS-Kernel. + + - 10.5.1_rev0 + - update amazon freertos version + + - 10.4.3_rev1 + - Apply CM33 security fix from 10.4.3-LTS-Patch-2. See rtos\freertos\freertos_kernel\History.txt + - Apply CM33 security fix from 10.4.3-LTS-Patch-1. See rtos\freertos\freertos_kernel\History.txt + + - 10.4.3_rev0 + - update amazon freertos version. + + - 10.4.3_rev0 + - update amazon freertos version. + + - 9.0.0_rev3 + - New features: + - Tickless idle mode support for Cortex-A7. Add fsl_tickless_epit.c and fsl_tickless_generic.h in portable/IAR/ARM_CA9 folder. + - Enabled float context saving in IAR for Cortex-A7. Added configUSE_TASK_FPU_SUPPORT macros. Modified port.c and portmacro.h in portable/IAR/ARM_CA9 folder. + - Other changes: + - Transformed ARM_CM core specific tickless low power support into generic form under freertos/Source/portable/low_power_tickless/. + + - 9.0.0_rev2 + - New features: + - Enabled MCUXpresso thread aware debugging. Add freertos_tasks_c_additions.h and configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H and configFRTOS_MEMORY_SCHEME macros. + + - 9.0.0_rev1 + - New features: + - Enabled -flto optimization in GCC by adding __attribute__((used)) for vTaskSwitchContext. + - Enabled KDS Task Aware Debugger. Apply FreeRTOS patch to enable configRECORD_STACK_HIGH_ADDRESS macro. Modified files are task.c and FreeRTOS.h. + + - 9.0.0_rev0 + - New features: + - Example freertos_sem_static. + - Static allocation support RTOS driver wrappers. + - Other changes: + - Tickless idle rework. Support for different timers is in separated files (fsl_tickless_systick.c, fsl_tickless_lptmr.c). + - Removed configuration option configSYSTICK_USE_LOW_POWER_TIMER. Low power timer is now selected by linking of apropriate file fsl_tickless_lptmr.c. + - Removed configOVERRIDE_DEFAULT_TICK_CONFIGURATION in RVDS port. Use of __attribute__((weak)) is the preferred solution. Not same as _weak! + + - 8.2.3 + - New features: + - Tickless idle mode support. + - Added template application for Kinetis Expert (KEx) tool (template_application). + - Other changes: + - Folder structure reduction. Keep only Kinetis related parts. + +*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/GitHub-FreeRTOS-Kernel-Home.url b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/GitHub-FreeRTOS-Kernel-Home.url similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/GitHub-FreeRTOS-Kernel-Home.url rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/GitHub-FreeRTOS-Kernel-Home.url diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/History.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/History.txt similarity index 89% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/History.txt rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/History.txt index f91df9f..544b0bf 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/History.txt +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/History.txt @@ -1,2855 +1,3057 @@ -Documentation and download available at https://www.FreeRTOS.org/ - -Changes between FreeRTOS V10.4.3 LTS Patch 1 and FreeRTOS V10.4.3 LTS Patch 2 - - + ARMv7-M and ARMv8-M MPU ports – prevent non-kernel code from calling the - internal functions xPortRaisePrivilege and vPortResetPrivilege by changing - them to macros. - -Changes between FreeRTOS V10.4.3 and FreeRTOS V10.4.3 LTS Patch 1 released September 10 2021 - - See https://www.FreeRTOS.org/FreeRTOS-V10.4.5.html - - + ARMv8-M secure-side port: Tasks that call secure functions from the - non-secure side of an ARMv8-M MCU (ARM Cortex-M23 and Cortex-M33) have two - contexts – one on the non-secure side and one on the secure-side. Previous - versions of the FreeRTOS ARMv8-M secure-side ports allocated the structures - that reference secure-side contexts at run time. Now the structures are - allocated statically at compile time. The change necessitates the - introduction of the secureconfigMAX_SECURE_CONTEXTS configuration constant, - which sets the number of statically allocated secure contexts. - secureconfigMAX_SECURE_CONTEXTS defaults to 8 if left undefined. - Applications that only use FreeRTOS code on the non-secure side, such as - those running third-party code on the secure side, are not affected by - this change. - - -Changes between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020 - - V10.4.3 is included in the 202012.00 LTS release. Learn more at https:/freertos.org/lts-libraries.html - - See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html - - + Changes to improve robustness and consistency for buffer allocation in - the heap, queue and stream buffer. - + The following functions can no longer be called from unprivileged code. - - xTaskCreateRestricted - - xTaskCreateRestrictedStatic - - vTaskAllocateMPURegions - - -Changes between FreeRTOS V10.4.1 and FreeRTOS V10.4.2 released November 10 2020 - - See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html - - + Fix an issue in the ARMv8-M ports that caused BASEPRI to be masked - between the first task starting to execute and that task making - a FreeRTOS API call. - + Introduced xTaskDelayUntil(), which is functionally equivalent to - vTaskDelayUntil(), with the addition of returning a value to - indicating whether or not the function placed the calling task into - the Blocked state or not. - + Update WolfSSL to 4.5.0 and add the FIPS ready demo. - + Add support for ESP IDF 4.2 to ThirdParty Xtensa port. - + Re-introduce uxTopUsedPriority to support OpenOCD debugging. - + Convert most dependent libraries in FreeRTOS/FreeRTOS to submodules. - + Various general maintenance and improvements to MISRA compliance. - - -Changes between FreeRTOS V10.4.0 and FreeRTOS V10.4.1 released September 17 2020 - - See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html - - + Fixed an incorrectly named parameter that prevented the - ulTaskNotifyTakeIndexed macro compiling, and the name space clash in the - test code that prevented this error causing test failures. - - -Changes between FreeRTOS V10.3.1 and FreeRTOS V10.4.0 released September 10 2020 - - See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html - - Major enhancements: - - + Task notifications: Prior to FreeRTOS V10.4.0 each created task had a - single direct to task notification. From FreeRTOS V10.4.0 each task has - an array of notifications. The direct to task notification API has been - extended with API functions postfixed with "Indexed" to enable the API to - operate on a task notification at any array index. See - https://www.freertos.org/RTOS-task-notifications.html for more information. - + Kernel ports that support memory protection units (MPUs): The ARMv7-M and - ARMv8-M MPU ports now support a privilege access only heap. The ARMv7-M - MPU ports now support devices that have 16 MPU regions, have the ability - to override default memory attributes for privileged code and data - regions, and have the ability to place the FreeRTOS kernel code outside of - the Flash memory. The ARMv8-M MPU ports now support tickless idle mode. - See https://www.freertos.org/FreeRTOS-MPU-memory-protection-unit.html - for more information. - - Additional noteworthy updates: - - + Code formatting is now automated to facilitate the increase in - collaborative development in Git. The auto-formated code is not identical - to the original formatting conventions. Most notably spaces are now used - in place of tabs. - + The prototypes for callback functions (those that start with "Application", - such as vApplicationStackOverflowHook()) are now in the FreeRTOS header - files, removing the need for application writers to add prototypes into - the C files in which they define the functions. - + New Renesas RXv3 port layer. - + Updates to the Synopsys ARC code, including support for EM and HS cores, - and updated BSP. - + Added new POSIX port layer that allows FreeRTOS to run on Linux hosts in - the same way the Windows port layer enables FreeRTOS to run on Windows - hosts. - + Many other minor optimisations and enhancements. For full details - see https://github.com/FreeRTOS/FreeRTOS-Kernel/commits/master - - -Changes between FreeRTOS V10.3.0 and FreeRTOS V10.3.1 released February 18 2020 - - See https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html - - + ./FreeRTOS-Labs directory was removed from this file. The libraries it - contained are now available as a separate download. - -Changes between FreeRTOS V10.2.1 and FreeRTOS V10.3.0 released February 7 2020 - - See https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html - - New and updated kernel ports: - - + Added RISC-V port for the IAR compiler. - + Update the Windows simulator port to use a synchronous object to prevent - a user reported error whereby a task continues to run for a short time - after being moved to the Blocked state. Note we were not able to - replicate the reported issue and it likely depends on your CPU model. - + Correct alignment of stack top in RISC-V port when - configISR_STACK_SIZE_WORDS is defined to a non zero value, which causes - the interrupt stack to be statically allocated. - + The RISC-V machine timer compare register can now be for any HART, whereas - previously it was always assumed FreeRTOS was running on HART 0. - + Update the sequence used to update the 64-bit machine timer - compare register on 32-bit cores to match that suggested in RISC-V - documentation. - + Added tickless low power modes into the ARM, IAR and GCC Cortex-M0 compiler - ports. - + Updated the behaviour of the ARMv7-M MPU (Memory Protection Unit) ports to - match that of the ARMv8-M ports whereby privilege escalations can only - originate from within the kernel's own memory segment. Added - configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY configuration constant. - + Update existing MPU ports to correctly disable the MPU before it is - updated. - + Added contributed port and demo application for a T-Head (formally C-SKY) - microcontroller. - - New API functions: - - + Added the vPortGetHeapStats() API function which returns information on - the heap_4 and heap_5 state. - + Added xTaskCatchUpTicks(), which corrects the tick count value after the - application code has held interrupts disabled for an extended period. - + Added xTaskNotifyValueClear() API function. - + Added uxTimerGetReloadMode() API function. - - Other miscellaneous changes: - + Change type of uxPendedTicks from UBaseType_t to TickType_t to ensure it - has the same type as variables with which it is compared to, and therefore - also renamed the variable xPendingTicks. - + Update Keil projects that use the MPU so memory regions come from linker - script (scatter file) variables instead of being hard coded. - + Added LPC51U68 Cortex-M0+ demos for GCC (MCUXpresso), Keil and IAR - compilers. - + Added CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube demo. - + Added LPC54018 MPU demo. - + Rename xTaskGetIdleRunTimeCounter() to ulTaskGetIdleRunTimeCounter(). - - -Changes between FreeRTOS V10.2.1 and FreeRTOS V10.2.0 released May 13 2019: - - + Added ARM Cortex-M23 port layer to complement the pre-existing ARM - Cortex-M33 port layer. - + The RISC-V port now automatically switches between 32-bit and 64-bit - cores. - + Introduced the portMEMORY_BARRIER macro to prevent instruction re-ordering - when GCC link time optimisation is used. - + Introduced the portDONT_DISCARD macro to the ARMv8-M ports to try and - prevent the secure side builds from removing symbols required by the - non secure side build. - + Introduced the portARCH_NAME to provide additional data to select semi- - automated build environments. - + Cortex-M33 and Cortex-M23 ports now correctly disable the MPU before - updating the MPU registers. - - + Added Nuvoton NuMaker-PFM-M2351 ARM Cortex-M23 demo. - + Added LPC55S69 ARM Cortex-M33 demo. - + Added an STM32 dual core AMP stress test demo. - - -Changes between FreeRTOS V10.1.1 and FreeRTOS V10.2.0 released February 25 2019: - - + Added GCC RISC-V MCU port with three separate demo applications. - + Included pre-existing ARM Cortex-M33 (ARMv8-M) GCC/ARMclang and IAR ports - with Keil simulator demo. - + Update the method used to detect if a timer is active. Previously the - timer was deemed to be inactive if it was not referenced from a list. - However, when a timer is updated it is temporarily removed from, then - re-added to a list, so now the timer's active status is stored separately. - + Add vTimerSetReloadMode(), xTaskGetIdleRunTimeCounter(), and - xTaskGetApplicationTaskTagFromISR() API functions. - + Updated third party Xtensa port so it is MIT licensed. - + Added configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H to the Renesas - compiler RX600v2 port to enable switching between platform.h and - iodefine.h includes within that port's port.c file. - + Removed the 'FromISR' functions from the MPU ports as ISRs run privileged - anyway. - + Added uxTaskGetStackHighWaterMark2() function to enable the return type to - be changed without breaking backward compatibility. - uxTaskGetStackHighWaterMark() returns a UBaseType_t as always, - uxTaskGetStackHighWaterMark2() returns configSTACK_DEPTH_TYPE to allow the - user to determine the return type. - + Fixed issues in memory protected ports related to different combinations - of static memory only and dynamic memory only builds. As a result the - definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE became more - complex and was moved to FreeRTOS.h with a table explaining its definition. - + Added a 'get task tag from ISR' function. - + Change the method used to determine if a timer is active or not from just - seeing if it is referenced from the active timer list to storing its - active state explicitly. The change prevents the timer reporting that it - is inactive while it is being moved from one list to another. - + The pcName parameter passed into the task create functions can be NULL, - previously a name had to be provided. - + When using tickless idle, prvResetNextTaskUnblockTime() is now only called - in xTaskRemoveFromEventList() if the scheduler is not suspended. - + Introduced portHAS_STACK_OVERFLOW_CHECKING, which should be set to 1 for - FreeRTOS ports that run on architectures that have stack limit registers. - - -Changes between FreeRTOS V10.1.0 and FreeRTOS V10.1.1 released 7 September 2018 - - + Reverted a few structure name changes that broke several kernel aware - debugger plug-ins. - + Updated to the latest trace recorder code. - + Fixed some formatting in the FreeRTOS+TCP TCP/IP stack code. - + Reverted moving some variables from file to function scope as doing so - broke debug scenarios that require the static qualifier to be removed. - -Changes between FreeRTOS V10.0.1 and FreeRTOS V10.1.0 released 22 August 2018 - - FreeRTOS Kernel Changes: - - + Update lint checked MISRA compliance to use the latest MISRA standard, was - previously using the original MISRA standard. - + Updated all object handles (TaskHandle_t, QueueHandle_t, etc.) to be - unique types instead of void pointers, improving type safety. (this was - attempted some years back but had to be backed out due to bugs in some - debuggers). Note this required the pvContainer member of a ListItem_t - struct to be renamed - set configENABLE_BACKWARD_COMPATIBILITY to 1 if - this causes an issue. - + Added configUSE_POSIX_ERRNO to enable per task POSIX style errno - functionality in a more user friendly way - previously the generic thread - local storage feature was used for this purpose. - + Added Xtensa port and demo application for the XCC compiler. - + Changed the implementation of vPortEndScheduler() for the Win32 port to - simply call exit( 0 ). - + Bug fix in vPortEnableInterrupt() for the GCC Microblaze port to protect - the read modify write access to an internal Microblaze register. - + Fix minor niggles when the MPU is used with regards to prototype - differences, static struct size differences, etc. - + The usStackHighWaterMark member of the TaskStatus_t structure now has type - configSTACK_DEPTH_TYPE in place of uint16_t - that change should have been - made when the configSTACK_DEPTH_TYPE type (which gets around the previous - 16-bit limit on stack size specifications) was introduced. - + Added the xMessageBufferNextLengthBytes() API function and likewise stream - buffer equivalent. - + Introduce configMESSAGE_BUFFER_LENGTH_TYPE to allow the number of bytes - used to hold the length of a message in the message buffer to be reduced. - configMESSAGE_BUFFER_LENGTH_TYPE default to size_t, but if, for example, - messages can never be more than 255 bytes it could be set to uint8_t, - saving 3 bytes each time a message is written into the message buffer - (assuming sizeof( size_t ) is 4). - + Updated the StaticTimer_t structure to ensure it matches the size of the - Timer_t structure when the size of TaskFunction_t does not equal the size - of void *. - + Update various Xilinx demos to use 2018.1 version of the SDK tools. - + Various updates to demo tasks to maintain test coverage. - + FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by - FreeRTOS+TCP, which was brought into the main download in FreeRTOS - V10.0.0. FreeRTOS+TCP can be configured as a UDP only stack, and - FreeRTOS+UDP does not contain the patches applied to FreeRTOS+TCP. - - FreeRTOS+TCP Changes: - - + Multiple security improvements and fixes in packet parsing routines, DNS - caching, and TCP sequence number and ID generation. - + Disable NBNS and LLMNR by default. - + Add TCP hang protection by default. - - We thank Ori Karliner of Zimperium zLabs Team for reporting these issues. - - -Changes between FreeRTOS V10.0.0 and FreeRTOS V10.0.1, released December 20 2017 - - + Fix position of "#if defined( __cplusplus )" in stream_buffer.h. - + Correct declarations of MPU_xQueuePeek() and MPU_xQueueSemaphoreTake() in - mpu_prototypes.h. - + Correct formatting in vTaskList() helper function when it prints the state - of the currently executing task. - + Introduce #error if stream_buffer.c is built without - configUSE_TASK_NOTIFICATIONS set to 1. - + Update FreeRTOS+TCP to V2.0.0 - - Improve the formatting of text that displays the available netword - interfaces when FreeRTOS+TCP is used on Windows with WinPCap. - - Introduce ipconfigSOCKET_HAS_USER_WAKE_CALLBACK option to enable a user - definable callback to execute when data arrives on a socket. - -Changes between FreeRTOS V9.0.1 and FreeRTOS V10.0.0: - - The FreeRTOS kernel is now MIT licensed: https://www.FreeRTOS.org/license - - New Features and components: - - + Stream Buffers - see https://www.FreeRTOS.org/RTOS-stream-buffer-example.html - + Message Buffers - see https://www.FreeRTOS.org//RTOS-message-buffer-example.html - + Move FreeRTOS+TCP into the main repository, along with the basic Win32 - TCP demo FreeRTOS_Plus_TCP_Minimal_Windows_Simulator. - - New ports or demos: - - + Added demo for TI SimpleLink CC3220 MCU. - + Added MPU and non MPU projects for Microchip CEC and MEC 17xx and 51xx - MCUs. - + Added CORTEX_MPU_Static_Simulator_Keil_GCC demo to test static allocation - in the MPU port. - - Fixes or enhancements: - - + Cortex-M ports push additional register prior to calling - vTaskSwitchContext to ensure 8-byte alignment is maintained. Only - important if a user defined tick hook function performs an operation that - requires 8-byte alignment. - + Optimisations to the implementation of the standard tickless idle mode on - Cortex-M devices. - + Improvements to the Win32 port including using higher priority threads. - + Ensure interrupt stack alignment on PIC32 ports. - + Updated GCC TriCore port to build with later compiler versions. - + Update mpu_wrappers.c to support static allocation. - + The uxNumberOfItems member of List_t is now volatile - solving an issue - when the IAR compiler was used with maximum optimization. - + Introduced configRECORD_STACK_HIGH_ADDRESS. When set to 1 the stack start - address is saved into each task's TCB (assuming stack grows down). - + Introduced configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H to allow user defined - functionality, and user defined initialisation, to be added to FreeRTOS's - tasks.c source file. When configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H is - set to 1 a user provided header file called freertos_task_c_additions.h - will be included at the bottom of tasks.c. Functions defined in that - header file can call freertos_tasks_c_additions_init(), which in turn - calls a macro called FREERTOS_TASKS_C_ADDITIONS_INIT(), if it is defined. - FREERTOS_TASKS_C_ADDITIONS_INIT() can be defined in FreeRTOSConfig.h. - + Introduced configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) which can be - defined by a user in FreeRTOSConfig.h. The macro is called before - assessing whether to enter tickless idle mode or not. If the macro sets - x to zero then tickless idle mode will not be entered. This allows users - to abort tickless idle mode entry before the tickless idle function is - even called - previously it was only possible to abort from within the - tickless idle function itself. - + Added configPRINTF(), which can be defined by users to allow all libraries - to use the same print formatter. - + Introduced configMAX() and configMIN() macros which default to standard - max( x, y ) and min( x, y ) macro behaviour, but can be overridden if the - application writer defines the same macros in FreeRTOSConfig.h. - + Corrected the definition of StaticTask_t in the case where - INCLUDE_xTaskAbortDelay is set to 1. - + Introduced configTIMER_SERVICE_TASK_NAME and configIDLE_TASK_NAME, both of - which can be defined to strings in FreeRTOSConfig.h to change the default - names of the timer service and idle tasks respectively. - + Only fill the stack of a newly created task with a known value if stack - checking, or high water mark checking/viewing, is in use - removing the - dependency on memset() in other cases. - + Introduced xTaskCreateRestrictedStatic() so static allocation can be used - with the MPU. - + Ensure suspended tasks cannot be unsuspended by a received task - notification. - + Fix race condition in vTaskSetTimeOutState(). - + Updated trace recorder files to the latest version. - -Changes since FreeRTOS V9.0.0: - - + Priority dis-inheritance behaviour has been enhanced in the case where a - task that attempted to take a mutex that was held by a lower priority task - timed out before it was able to obtain the mutex (causing the task that - holds the mutex to have its priority raised, then lowered again, in - accordance with the priority inheritance protocol). - + Split the overloaded xQueueGenericReceive() function into three separate - dedicated functions. - + Allow the default human readable text names given to the Idle and Timer - tasks to be overridden by defining the configIDLE_TASK_NAME and - configTIMER_SERVICE_TASK_NAME definitions respectively in FreeRTOSConfig.h. - + Introduced configINITIAL_TICK_COUNT to allow the tick count to take a - value of than than 0 when the system boots. This can be useful for - testing purposes - although setting configUSE_16_BIT_TICKS to 1 can also - be used to test frequent tick overflows. - + Ensure the Cortex-M SysTick count is cleared to zero before starting the - first task. - + Add configASSERT() into ARM Cortex-M ports to check the number of priority - bit settings. - + Clear the 'control' register before starting ARM Cortex-M4F ports in case - the FPU is used before the scheduler is started. This just saves a few - bytes on the main stack as it prevents space being left for a later save - of FPU registers. - + Added xSemaphoreGetMutexHolderFromISR(). - + Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports. - + Introduced configSTACK_DEPTH_TYPE to allow users to change the type used - to specify the stack size when using xTaskCreate(). For historic reasons, - when FreeRTOS was only used on small MCUs, the type was set to uint16_t, - but that can be too restrictive when FreeRTOS is used on larger - processors. configSTACK_DEPTH_TYPE defaults to uint16_t. - xTaskCreateStatic(), being a newer function, used a uint32_t. - + Increase the priority of the Windows threads used by the Win32 port. As - all the threads run on the same core, and the threads run with very high - priority, there is a risk that the host will become unresponsive, so also - prevent the Windows port executing on single core hosts. - -Changes between FreeRTOS V9.0.0 and FreeRTOS V9.0.0rc2 released May 25 2016: - - See https://www.FreeRTOS.org/FreeRTOS-V9.html - - RTOS kernel updates: - - + The prototype of the new xTaskCreateStatic() API function was modified to - remove a parameter and improve compatibility with other new - "CreateStatic()" API functions. The stack size parameter in - xTaskCreateStatic() is now uint32_t, which changes the prototype of the - callback functions. See the following URL: - https://www.FreeRTOS.org/xTaskCreateStatic.html - + GCC ARM Cortex-A port: Introduced the configUSE_TASK_FPU_SUPPORT - constant. When configUSE_TASK_FPU_SUPPORT is set to 2 every task is - automatically given a floating point (FPU) context. - + GCC ARM Cortex-A port: It is now possible to automatically save and - restore all floating point (FPU) registers on entry to each potentially - nested interrupt by defining vApplicationFPUSafeIRQHandler() instead of - vApplicationIRQHandler(). - + All ARM Cortex-M3/4F/7 ports: Clear the least significant bit of the task - entry address placed onto the stack of a task when the task is created for - strict compliance with the ARM Cortex-M3/4/7 architecture documentation - (no noticeable effect unless using the QMEU emulator). - + Added GCC and Keil ARM Cortex-M4F MPU ports - previously the MPU was only - supported on ARM Cortex-M3. - + ARM Cortex-M3/4F MPU ports: Update to fully support the FreeRTOS V9.0.0 - API (other than static object creation) and added the - FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC demo application to - demonstrate how to use the updated MPU port. - + All ARM Cortex-M3/4F/7 ports: Add additional barrier instructions to the - default low power tickless implementation. - + All ARM Cortex-M0 ports: Prevent an item being left on the stack of the - first task that executes. - + Win32 ports: Reduce the amount of stack used and change the way Windows - threads are deleted to increase the maximum execution time. - + Add an ARM Cortex-M4F port for the MikroC compiler. Ensure to read the - documentation page for this port before use. - + MPS430X IAR port: Update to be compatible with the latest EW430 tools - release. - + IAR32 GCC port: Correct vPortExitCritical() when - configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY. - + For consistency vTaskGetTaskInfo() now has the alias vTaskGetInfo(), - xTaskGetTaskHandle() now has the alias xTaskGetHandle() and - pcQueueGetQueueName() now has an alias pcQueueGetName(). - + Fix various errors in comments and compiler warnings. - - Demo application updates: - - + Update Atmel Studio projects to use Atmel Studio 7. - + Update Xilinx SDK projects to use the 2016.1 version of the SDK. - + Remove dependency on legacy IO libraries from the PIC32 demos. - + Move the Xilinx UltraScale Cortex-R5 demo into the main distribution. - + Update the MSP432 libraries to the latest version. - + Add Microchip CEC1302 (ARM Cortex-M4F) demos for GCC, Keil and MikroC - compilers. - + Move the Atmel SAMA5D2 demo into the main distribution. - -Changes between FreeRTOS V9.0.0rc1 and FreeRTOS V9.0.0rc2 (release candidate 2) -released March 30 2016: - - NOTE - See https://www.FreeRTOS.org/FreeRTOS-V9.html for details - - + The functions that create RTOS objects using static memory allocation have - been simplified and will not revert to using dynamic allocation if a - buffer is passed into a function as NULL. - + Introduced the configSUPPORT_DYNAMIC_ALLOCATION configuration constant to - allow a FreeRTOS application to be built without a heap even being being - defined. The Win32 example located in the - /FreeRTOS/demo/WIN32-MSVC-Static-Allocation-Only directory is provided as - a reference for projects that do not include a FreeRTOS heap. - + Minor run-time optimisations. - + Two new low power tickless implementations that target Silicon Labs EFM32 - microcontrollers. - + Addition of the xTimerGetPeriod() and xTimerGetExpireTime() API functions. - -Changes between FreeRTOS V8.2.3 and FreeRTOS V9.0.0rc1 (release candidate 1) -released February 19 2016: - - RTOS Kernel Updates: - - + Major new feature - tasks, semaphores, queues, timers and event groups can - now be created using statically allocated memory, so without any calls to - pvPortMalloc(). - + Major new features - Added the xTaskAbortDelay() API function which allows - one task to force another task to immediately leave the Blocked state, - even if the event the blocked task is waiting for has not occurred, or the - blocked task's timeout has not expired. - + Updates necessary to allow FreeRTOS to run on 64-bit architectures. - + Added vApplicationDaemonTaskStartupHook() which executes when the RTOS - daemon task (which used to be called the timer service task) starts - running. This is useful if the application includes initialisation code - that would benefit from executing after the scheduler has been started. - + Added the xTaskGetTaskHandle() API function, which obtains a task handle - from the task's name. xTaskGetTaskHandle() uses multiple string compare - operations, so it is recommended that it is called only once per task. - The handle returned by xTaskGetTaskHandle() can then be stored locally for - later re-use. - + Added the pcQueueGetQueueName() API function, which obtains the name of - a queue from the queue's handle. - + Tickless idling (for low power applications) can now also be used when - configUSE_PREEMPTION is 0. - + If one task deletes another task, then the stack and TCB of the deleted - task is now freed immediately. If a task deletes itself, then the stack - and TCB of the deleted task are freed by the Idle task as before. - + If a task notification is used to unblock a task from an ISR, but the - xHigherPriorityTaskWoken parameter is not used, then pend a context switch - that will then occur during the next tick interrupt. - + Heap_1.c and Heap_2.c now use the configAPPLICATION_ALLOCATED_HEAP - settings, which previously was only used by heap_4.c. - configAPPLICATION_ALLOCATED_HEAP allows the application writer to declare - the array that will be used as the FreeRTOS heap, and in-so-doing, place - the heap at a specific memory location. - + TaskStatus_t structures are used to obtain details of a task. - TaskStatus_t now includes the bae address of the task's stack. - + Added the vTaskGetTaskInfo() API function, which returns a TaskStatus_t - structure that contains information about a single task. Previously this - information could only be obtained for all the tasks at once, as an array - of TaskStatus_t structures. - + Added the uxSemaphoreGetCount() API function. - + Replicate previous Cortex-M4F and Cortex-M7 optimisations in some - Cortex-M3 port layers. - - Demo Application Updates: - - Further demo applications will be added prior to the final FreeRTOS V9 - release. - - + Updated SAM4L Atmel Studio project to use Atmel Studio 7. - + Added ARM Cortex-A53 64-bit port. - + Added a port and demo for the ARM Cortex-A53 64-bit cores on the Xilinx - Ultrascale MPSoC. - + Added Cortex-M7 SAME70 GCC demo. - + Added EFM32 Giant and Wonder Gecko demos. - - -Changes between V8.2.2 and V8.2.3 released October 16, 2015 - - RTOS kernel updates: - - + Fix bug identified in a modification made in V8.2.2 to the software timer - code that allows tickless low power applications to sleep indefinitely - when software timers are used. - + Simplify and improve efficiency of stack overflow checking. - + Add xTaskNotifyStateClear() API function. - + New IAR and GCC Cortex-R ports for microprocessors that do not use an ARM - generic interrupt controller (GIC). - + New PIC32MEC14xx port. - + Add support for PIC32MZ EF parts (with floating point) into the PIC32MZ - port. - + Zynq7000 port layer now declares the functions that setup and clear the - tick interrupt as weak symbols so they can be overridden by the - application, and uses a global XScuGic object so the same object can be - used by the application code. - + Introduced configUSE_TASK_FPU_SUPPORT, although the PIC32MZ EF port is - currently the only port that uses it. - + Updates to RL78 and 78K0 IAR port layers to improve support for - combinations of memory models. - + Minor updates to heap_5.c to remove compiler warnings generated by some - compilers. - + License simplifications. See /FreeRTOS/License/license.txt in the - official distribution. - - FreeRTOS+ updates: - - + Update directory names to use WolfSSL instead of CyaSSL, inline with - WolfSSL's re-branding. - + Update to latest WolfSSL code. - + Update to latest FreeRTOS+Trace recorder code. - + Add in the FreeRTOS+Trace recorder library required for streaming trace. - - Demo application changes: - - + Add demo applications for Renesas RZ/T (Cortex-R), PIC32MZ EF (PIC32 with - floating point hardware), PIC32MEC14xx, RX71M, RX113 and RX231. - + General tidy up of spelling and compiler warnings. - - -Changes between V8.2.1 and V8.2.2 released August 12, 2015 - - RTOS kernel updates: - - + Added Intel IA32/x86 32-bit port. - + General maintenance. - + PRIVILEGED_FUNCTION and PRIVILEGED_DATA macros, which are used in memory - protected systems, have been added to the newer event group and software - timer functions. - + Add the errno definitions used by FreeRTOS+ components into projdefs.h. - + Remove the restriction that prevented tick-less idle implementations - waiting indefinitely when software timers were used in the same - application. - + Introduce xTaskNotifyAndQueryFromISR() as the interrupt safe version of - xTaskNotifyAndQuery(). - + Add additional NOPs to the MSP430X port layers to ensure strict compliance - with the hardware documentation. - + Microblaze port: Added option for port optimised task selection. - + Microblaze port: Previously tasks inherited the exception enable state - at the time the task was created. Now all tasks are created with - exceptions enabled if the Microblaze design supports exceptions. - + Windows port: Add additional safe guards to ensure the correct start up - sequence and thread switching timing. - + Windows port: Improve the implementation of the port optimised task - selection assembly code. - + Update heap_4 and heap_5 to allow use on 64-bit processors. - + Simplify the code that creates a queue. - + General improved tick-less idle behaviour. - + Ensure none of the variables in the common kernel files are initialised to - anything other than zero. - + Correct calculation of xHeapStructSize in heap_4 and heap_5. - - Demo application updates: - - + Added demo project for the new IA32/x86 port that targets the Galileo - hardware. - + Added MSP430FR5969 demos (previously provided as a separate download). - + Added FreeRTOS BSP repository for automatic creation of FreeRTOS - applications in the Xilinx SDK. - + Added Atmel Studio / GCC project for the SAMV71 (ARM Cortex-M7) - + Update Xilinx SDK projects to use version 2015.2 of the SDK. - + Remove Microblaze demos that were using obsolete tools. - + Add MSP43FR5969 IAR and CCS demos. - - FreeRTOS+ Updates: - - + Updated FreeRTOS+Trace recorder library, which requires an update to the - FreeRTOS+Trace application. - + Added Reliance Edge source code and demo application. Reliance edge is - a fail safe transactional file system ideal for applications that require - file storage, and especially when high reliability is essential. - + Introduce configAPPLICATION_PROVIDES_cOutputBuffer to allow FreeRTOS+CLI - users to place the output buffer at a fixed memory address. - + Improve the NetworkInterface.c file provided for the Windows port of - FreeRTOS+UDP. - -Changes between V8.2.0 and V8.2.1 released 24th March 2015. - - RTOS kernel updates: - - + Added user definable and flexible thread local storage facility. - + Added vTimerSetTimerID() API function to complement the pvTimerGetTimerID() - function to allow the timer's ID to be used as timer local storage. - + Fixed a potential issue related to the use of queue sets from an ISR. - + Some updates to the Xilinx Microblaze GCC port. - + Added ARM Cortex-M4F port for Texas Instruments Code Composer Studio. - + Added ARM Cortex-M7 r0p1 port layer for IAR, GCC and Keil which contains a - minor errata work around. All other ARM Cortex-M7 core revisions should - use the ARM Cortex-M4F port. - + Exclude the whole of croutine.c if configUSE_CO_ROUTINES is set to 0. - + Change some data types from uint32_t to size_t in preparation for 64-bit - Windows port. - + Update the PIC32 port to remove deprecation warnings output by the latest - XC32 compilers. - + Fix bug when xQueueOverwrite() and xQueueOverwrite() from ISR are used to - overwrite items in two queues that are part of the same set. - - Demo application updates: - - + Added demo application for TI's ARM Cortex-M4F based MSP432 - microcontroller using IAR, Keil and CCS compilers. - + Added demo application for STM32F ARM Cortex-M7 based microcontroller - using IAR and Keil. - + Added demo application for Atmel SAMV71 ARM Cortex-M7 based - microcontroller using IAR and Keil. - + Added Microblaze demo that uses the 2014.4 version of the Xilinx SDK and - runs on the KC705 evaluation board (Kintex FPGA). - -Changes between V8.1.2 and V8.2.0 released 16th January 2015 - - Changes between release candidate 1 and the official release are restricted - to maintenance only. - - Significant RTOS kernel updates: - - + MAJOR NEW FEATURE! Task notifications. Please see the following URL for - details: https://www.FreeRTOS.org/RTOS-task-notifications.html - + NEW HEADER FILE REQUIRED! Obsolete definitions have been separated into - a new header file called FreeRTOS/Source/include/deprecated_definitions.h. - This header file must be present to build. Note some of the obsolete - definitions are still used by very old demo application projects. - - Other RTOS kernel updates: - - + Made xSemaphoreGiveFromISR() a function rather than a macro that calls - xQueueGenericSendFromISR(). This allows for major performance - enhancements at the expense of some additional code size if both functions - are used in the same application. NOTE: In most uses cases such use of - a semaphore can now be replaced with a task notification which is smaller - and faster still. - + The TCB is now always allocated such that the task's stack grows away from - the TCB (improves debugging of stack overflows as the overflow will not - overwrite the task's name). - + GCC, IAR and Keil Cortex-M4F ports now use more inlining (performance - enhancements at the cost of a little additional code space). - + Queues are now allocated with a single call to pvPortMalloc() which - allocates both the queue structure and the queue storage area. - + Introduced a new critical section macro for reading the tick count that - defines away to nothing in cases where the width of the tick allows the - tick count to be read atomically (performance benefits - especially when - optimisation is on). - + Introduced configAPPLICATION_ALLOCATED_HEAP in heap_4.c to allow the - application writer to provide their own heap array - and in so doing - control the location of the heap. - + Introduced configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES which, when set, will - include known values in both list and list item structures. The values - are intended to assist debugging. If the values get overwritten then it - is likely application code has written over RAM used by the kernel. - + configASSERT()s in all Cortex-M ports used to test the lowest 5 bits of - the interrupt control register to detect taskENTER_CRITICAL() being called - from an interrupt. This has been changed to test all 8 bits. - + Introduced uxTaskPriorityGetFromISR(). - + Microblze V8 port now tests XPAR_MICROBLAZE_0_USE_FPU for inequality to 0 - rather than equality to 1, and 2 and 3 are also valid values. - + Cortex-A5 GIC-less port no longer passes the address of the interrupting - peripheral into the interrupt handler. - + Fix an issue in FreeRTOS-MPU where an attempt was made to free the stack - belonging to a task when the task was deleted, even when the stack was - allocated statically. - + Utility (helper) functions that format task statistic information into - human readable tables now pad task names with spaces to ensure columns - line up correctly even where task name lengths vary greatly. - + Update FreeRTOS+Trace recorder library to version 2.7.0. - - Demo application updates: - - + Added two new standard demo task sets: IntSemTest and TaskNotify. - + Added port and demo application for Atmel SAMA5D4 Cortex-A5 MPU. - + Added demo application for Altera Cyclone V Cortex-A9 MPU. - + Updated Zynq demo to use version 2014.4 of Xilinx's SDK and added in - demo tasks for new RTOS features. - + Updated Atmel SAM4E and SAM4S demos to include a lot of additional test - and demo tasks. - + Fixed a corner case issue in Atmel SAM4L low power tickless - implementation, and added button interrupt handling. - + Make the interrupt queue tests more tolerant to heave CPU loads. - + Updated MSVC FreeRTOS simulator demo to include the latest standard test - and demo tasks. - + Updated MingW/Eclipse FreeRTOS simulator demo to match the FreeRTOS MSVC - simulator demo. - + Updated all demos that use FreeRTOS+Trace to work with the latest trace - recorder code. - - -Changes between V8.1.1 and V8.1.2 released September 2nd 2014 - - Move the defaulting of configUSE_PORT_OPTIMISED_TASK_SELECTION into the - individual port layers where necessary so it does not affect ports that do - not support the definition. - -Changes between V8.1.0 and V8.1.1 released August 29th 2014 - - By popular requests - a minor patch to V8.1.0 to re-instate the ability to - give a mutex type semaphore (with priority inheritance) from an interrupt - handler. - -Changes between V8.0.1 and V8.1.0 released August 26th 2014 - - FreeRTOS scheduler, kernel, demo and test updates: - - + Improved the priority inheritance algorithms to assist integration with - off the shelf middleware that may hold multiple mutexes simultaneously. - + Introduce heap_5.c, which is similar to heap_4.c but allows the heap to - span multiple non-contiguous memory regions. - + Updated all Cortex-A9 ports to help trap a couple of common usage errors - - the first being when a task incorrectly attempts to exit its implementing - function and the second being when a non interrupt safe API function is - called from an interrupt. - + Update all Cortex-A9 ports to remove obsolete mode switches prior to - restoring a task context. - + configUSE_PORT_OPTIMISED_TASK_SELECTION now defaults to 1 instead of 0. - + Update all Cortex-M3/4F ports to trap a non interrupt safe API function - being called from an interrupt handler. - + Simplify the alignment checks in heap_4.c. - + Update the MSVC Windows simulator demo to use heap_5.c in place of - heap_4.c to ensure end users have an example to refer to. - + Updated standard demo test code to test the new priority inheritance - algorithms. - + Updated the standard demo tasks to make use of stdint and the FreeRTOS - specific typedefs that were introduced in FreeRTOS V8.0.0. - + Introduce the pdMS_TO_TICKS() macro as a more user friendly and intuitive - alternative to pdTICKS_PER_MS - both of which can be used to convert a - time specified in milliseconds to a time specified in RTOS ticks. - + Fix a bug in the Tasking compiler's Cortex-M port that resulted in an - incorrect value being written to the basepri register. This only effects - users of the Tasking compiler. - + Update the Zynq demo to use version 2014.2 of the SDK and add in an lwIP - example that demonstrates lwIP being used with both its raw and sockets - interfaces. - + Updated the CCS Cortex-R4 port to enable it to be built with the latest - CCS compiler. - - New ports and demo applications: - - + Two Renesas RX64M ports (RXv2 core) and demos introduced, one for the GCC - compiler and one for the Renesas compiler. Both demos use e2 studio. - + Generic IAR Cortex-A5 port (without any reliance on a GIC) introduced. - The new port is demonstrated on an Atmel SAMA5D3 XPlained board. - - FreeRTOS+ component updates: - - + Update CyaSSL to the latest version. - + Updated the FreeRTOS+ components supplied directly by Real Time Engineers - Ltd. to make use of stdint and the FreeRTOS specific typedefs that were - introduced in FreeRTOS V8.0.0. - + Rework and simplify the FreeRTOS+FAT SL RAM disk driver. - - Miscellaneous updates and maintenance: - - + Update the IAR and DS-5/ARM RZ demos to target the official RZ RSK - hardware in place of the previously targeted Renesas internal (not - publicly available) hardware. - + Various other maintenance tasks. - - -Changes between V8.0.0 and V8.0.1 released 2nd May 2014 - - + Minor fixes to the event group functionality that was released in V8.0.0. - The 'clear bits from ISR' functionality is now implemented using a - deferred interrupt callback instead of a function, and the 'wait bits' and - 'task sync' functions now correctly clear internal control bits before - returning a value in every possible path through the respective functions. - + Ensure the updating of internal control data is protected by a critical - section after a task is deleted or suspended. - + Minor fixes to FreeRTOS+FAT SL - namely seeking beyond the end of a file - when the offset was not a multiple of the sector size. - + Ensure Cortex-A9 system registers are only ever accessed as 32-bit values, - even when only the lest significant byte of the register is implemented. - - Other updates: - - + Updated the XMC4200 IAR project so it links with version 7.x of the IAR - tools. - + Add RL78L1C demo. - + Add pcTimerGetName() API function. - + Call _reclaim_reent() when a task is deleted if configUSE_NEWLIB_REENTRANT - is defined. - -Changes between V7.6.0 and V8.0.0 released 19th Feb 2014 - - https://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html - - FreeRTOS V8.x.x is a drop-in compatible replacement for FreeRTOS V7.x.x, - although a change to the type used to reference character strings may result - in application code generating a few (easily clearable) compiler warnings - after the upgrade, and an updated typedef naming convention means use of the - old typedef names is now discouraged. - See https://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html for full - information. - - New features and functionality: - - + Event groups - see https://www.FreeRTOS.org/FreeRTOS-Event-Groups.html - + Centralised deferred interrupt processing - see - https://www.FreeRTOS.org/xTimerPendFunctionCallFromISR.html - - Other updates: - - + Previously, when a task left the Blocked state, a context switch was - performed if the priority of the unblocked task was greater than or equal - to the priority of the Running task. Now a context switch is only - performed if the priority of the unblocked task is greater than the - priority of the Running task. - + New low power tickless demonstration project that targets the ST STM32L - microcontroller - see - https://www.FreeRTOS.org/STM32L-discovery-low-power-tickless-RTOS-demo.html - + Add xPortGetMinimumEverFreeHeapSize() to heap_4.c. - + Small change to the tickless low power implementation on the SAM4L to - ensure the alarm value (compare match value) cannot be set to zero when a - tickless period is exited due to an interrupt originating from a source - other than the RTOS tick. - + Update the GCC/Eclipse Win32 simulator demo to make better use of Eclipse - resource filters and match the functionality of the MSVC equivalent. - + xTaskIsTaskSuspended() is no longer a public function. Use - eTaskGetState() in its place. - + Improved trace macros, including tracing of heap usage. - + Remove one level of indirection when accepting interrupts on the PIC32MZ. - + Add Cortex-A9 GCC port layer. - + Add Xilinx Zynq demo application. - - -Changes between V7.5.3 and V7.6.0 released 18th November 2013 - - V7.6.0 changes some behaviour when the co-operative scheduler is used (when - configUSE_PREEMPTION is set to 0). It is important to note that the - behaviour of the pre-emptive scheduler is unchanged - the following - description only applies when configUSE_PREEMPTION is set to 0: - - WHEN configUSE_PREEMPTION IS SET TO 0 (which is in a small minority of - cases) a context switch will now only occur when a task places itself into - the Blocked state, or explicitly calls taskYIELD(). This differs from - previous versions, where a context switch would also occur when implicitly - moving a higher priority task out of the Blocked state. For example, - previously, WHEN PREEMPTION WAS TURNED OFF, if task A unblocks task B by - writing to a queue, then the scheduler would switch to the higher priority - task. Now, WHEN PREEMPTION IS TURNED OFF, if task A unblocks task B by - writing to a queue, task B will not start running until task A enters the - Blocked state or task A calls taskYIELD(). [If configUSE_PREEMPTION is not - set to 0, so the normal pre-emptive scheduler is being used, then task B - will start running immediately that it is moved out of the Blocked state]. - - Other changes: - - + Added a port layer and a demo project for the new PIC32MZ architecture. - + Update the PIC32MX port layer to re-introduce some ehb instructions that - were previously removed, add the ability to catch interrupt stack - overflows (previously only task stack overflows were trapped), and also - add the ability to catch an application task incorrectly attempting to - return from its implementing function. - + Make dramatic improvements to the performance of the Win32 simulator port - layer. - + Ensure tasks that are blocked indefinitely report their state as Blocked - instead of Suspended. - + Slight improvement to the Cortex-M4F port layers where previously one - register was inadvertently being saved twice. - + Introduce the xSemaphoreCreateBinary() API function to ensure consistency - in the semantics of how each semaphore type is created. It is no longer - recommended to use vSemaphoreCreateBinary() (the version prefixed with a - 'v'), although it will remain in the code for backward compatibility. - + Update the Cortex-M0 port layers to allow the scheduler to be started - without using the SVC handler. - + Added a build configuration to the PIC32MX MPLAB X demo project that - targets the PIC32 USB II starter kit. Previously all the build - configurations required the Explorer 16 hardware. - + Some of the standard demo tasks have been updated to ensure they execute - correctly with the updated co-operative scheduling behaviour. - + Added comprehensive demo for the Atmel SAM4E, including use of - FreeRTOS+UDP, FreeRTOS+FAT SL and FreeRTOS+CLI. - - FreeRTOS+ Changes: - - + Minor maintenance on FreeRTOS+UDP. - -Changes between V7.5.2 and V7.5.3 released October 14 2013 - - Kernel changes: - - + Prior to V7.5.x yields requested from the tick hook would occur in the - same tick interrupt - revert to that original behaviour. - + New API function uxQueueSpacesAvailable(). - + Introduced the prvTaskExitError() function to Cortex-M0, Cortex-M3/4 - and Cortex-M4F ports. prvTaskExitError() is used to trap tasks that - attempt to return from their implementing functions (tasks should call - vTaskDelete( NULL ); if they want to exit). - + The Cortex-M0 version of portSET_INTERRUPT_MASK_FROM_ISR and - portCLEAR_INTERRUPT_MASK_FROM_ISR are now fully nestable. - + Improved behaviour and robustness of the default Cortex-M tickless idle - behaviour. - + Add workaround for silicon errata PMU_CM001 in Infineon XMC4000 devices to - all Cortex-M4F ports. - + Add Cortex-M0 port for Keil. - + Updated Cortus port. - + Ensure _impure_ptr is initialised before the scheduler is started. - Previously it was not set until the first context switch. - - FreeRTOS+ changes: - - + Update FreeRTOS+UDP to V1.0.1 - including direct integration of the - FreeRTOS+Nabto task, improvements to the DHCP behaviour, and a correction - to the test that prevents the network event hook being called on the first - network down event. The FreeRTOS+UDP change history is maintained - separately. - + Correct the __NVIC_PRIO_BITS setting in the LPC18xx.h header files - provided in the NXP CMSIS library, then update the interrupts used by the - LPC18xx demos accordingly. - + Replace double quotes (") with single quotes (') in FreeRTOS+CLI help - strings to ensure the strings can be used with the JSON descriptions used - in the FreeRTOS+Nabto demos. - - Demo and miscellaneous changes: - - + Added demo for the Atmel SAMD20 Cortex-M0+. The demo includes - FreeRTOS+CLI - + Added a demo for the Infineon Cortex-M0 that can be built with the IAR - Keil and GCC tools. - + Updated the Infineon XMC4000 demos for IAR, Keil, GCC and Tasking tools, - with additional build configurations to directly support the XMC4200 and - XMC4400 devices, in addition to the previously supported XMC4500. - + Updated the demo application. - + Added additional trace macros traceMALLOC and traceFREE to track heap - usage. - -Changes between V7.5.0 and V7.5.2 released July 24 2013 - - V7.5.2 makes the new Cortex-M vPortCheckInterruptPriority() function - compatible with the STM32 standard peripheral driver library, and adds - an extra critical section to the default low power tickless mode - implementation. Only users of the STM32 peripheral library or the default - tickless implementation need update from version 7.5.0. - -Changes between V7.4.2 and V7.5.0 released July 19 2013 - - V7.5.0 is a major upgrade that includes multiple scheduling and efficiency - improvements, and some new API functions. - - Compatibility information for FreeRTOS users: - FreeRTOS V7.5.0 is backward compatible with FreeRTOS V7.4.0 with one - exception; the vTaskList() and vTaskGetRunTimeStats() functions are now - considered legacy, having been replaced by the single uxTaskGetSystemState() - function. configUSE_STATS_FORMATTING_FUNCTIONS must be set to 1 in - FreeRTOSConfig.h for vTaskList() and vTaskGetRunTimeStats() to be - available. - - Compatibility information for FreeRTOS port writers: - vTaskIncrementTick() is now called xTaskIncrementTick() (because it now - returns a value). - - Headline changes: - - + Multiple scheduling and efficiency improvements. - + Core kernel files now pass PC-Lint V8 static checking without outputting - any warnings (information on the test conditions will follow). - - New API functions: - - + uxTaskGetSystemState() https://www.FreeRTOS.org/uxTaskGetSystemState.html - + xQueueOverwrite() https://www.FreeRTOS.org/xQueueOverwrite.html - + xQueueOverwriteFromISR() - + xQueuePeekFromISR() - - The following ports and demos, which were previously available separately, - are now incorporated into the main FreeRTOS zip file download: - - + ARM Cortex-A9 IAR - + ARM Cortex-A9 ARM compiler - + Renesas RZ - + Microsemi SmartFusion2 - - New FreeRTOSConfig.h settings - https://freertos.org/a00110.html - - + configUSE_TIME_SLICING - + configUSE_NEWLIB_REENTRANT - + configUSE_STATS_FORMATTING_FUNCTIONS - + configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS - - Other changes: - - + (MPU port only) The configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS - options provides a mechanism that allows application writers to execute - certain functions in privileged mode even when a task is running in user - mode. - + Ports that support interrupt nesting now include a configASSERT() that - will trigger if an interrupt safe FreeRTOS function is called from an - interrupt that has a priority designated as above the maximum system/API - call interrupt priority. - + The included FreeRTOS+Trace recorder code has been updated to the latest - version, and the demo applications that use the trace recorder code have - been updated accordingly. - + The FreeRTOS Windows Simulator (MSVC version only) has been updated to - include a new basic 'blinky' build option in addition to the original - comprehensive build option. - + Improve RAM usage efficiency of heap_4.c and heap_2.c. - + Prevent heap_4.c from attempting to free memory blocks that were not - allocated by heap_4.c, or have already been freed. - + As FreeRTOS now comes with FreeRTOS+FAT SL (donated by HCC) the Chan FATfs - files have been removed from FreeRTOS/Demo/Common. - + Fix build error when R4 port is build in co-operative mode. - + Multiple port and demo application maintenance activities. - -Changes between V7.4.1 and V7.4.2 released May 1 2013 - - NOTE: There are no changes in the FreeRTOS kernel between V7.4.1 and V7.4.2 - - + Added FreeRTOS+FAT SL source code and demo project. The demo project - runs in the FreeRTOS Windows simulator for easy and hardware independent - experimentation and evaluation. See https://www.FreeRTOS.org/fat_sl - -Changes between V7.4.0 and V7.4.1 released April 18 2013 - - + To ensure strict conformance with the spec and ensure compatibility with - future chips data and instruction barrier instructions have been added to - the yield macros of Cortex-M and Cortex-R port layers. For efficiency - the Cortex-M port layer "yield" and "yield" from ISR are now implemented - separately as the barrier instructions are not required in the ISR case. - + Added FreeRTOS+UDP into main download. - + Reorganised the FreeRTOS+ directory so it now matches the FreeRTOS - directory with Source and Demo subdirectories. - + Implemented the Berkeley sockets select() function in FreeRTOS+UDP. - + Changed (unsigned) casting in calls to standard library functions with - (size_t) casting. - + Added the Atmel SAM4L and Renesas RX100 demos that demonstrates the - tickless (tick suppression) low power FreeRTOS features. - + Add a new RL78 IAR demo that targets numerous new RL78 chips and - evaluation boards. - + Adjusted stack alignment on RX200 ports to ensure an assert was not - falsely triggered when configASSERT() is defined. - + Updated the Cortex_M4F_Infineon_XMC4500_IAR demo to build with the latest - version of EWARM. - + Corrected header comments in the het.c and het.h files (RM48/TMS570 demo). - - -Changes between V7.3.0 and V7.4.0 released February 20 2013 - - + New feature: Queue sets. See: - https://www.FreeRTOS.org/Pend-on-multiple-rtos-objects.html - + Overhauled the default tickless idle mode implementation provided with the - ARM Cortex-M3 port layers. - + Enhanced tickless support in the core kernel code with the introduction of - the configEXPECTED_IDLE_TIME_BEFORE_SLEEP macro and the - eTaskConfirmSleepModeStatus() function. - + Added the QueueSet.c common demo/test file. Several demo applications - have been updated to use the new demo/test tasks. - + Removed reliance on the PLIB libraries from the MPLAB PIC32 port layer and - demo applications. - + Added the FreeRTOS+Trace recorder code to the MSVC Win32 demo. - + Renamed eTaskStateGet() to eTaskGetState() for consistency, and added a - pre-processor macro for backward compatibility with the previous name. - + Updated functions implemented in the core queue.c source file to allow - queue.h to be included from the .c file directly (this prevents compiler - warnings that were generated by some compilers). - + Updated the CCS Cortex-R4 port layer to replace the CLZ assembler function - with the CLZ compiler intrinsic that is provided by the latest versions of - the CCS ARM compiler. - + Updated all heap_x.c implementations to replace the structure that was - used to ensure the start of the heap was aligned with a more portable - direct C code implementation. - + Added support for PIC24 devices that include EDS. - + Minor optimisations to the PIC32 port layer. - + Minor changes to tasks.c that allow the state viewer plug-ins to display - additional information. - + Bug fix: Update prvProcessReceivedCommands() in timers.c to remove an - issue that could occur if the priority of the timer daemon task was set - below the priority of tasks that used timer services. - + Update the FreeRTOS+Trace recorder code to the latest version. - -Changes between V7.2.0 and V7.3.0 released October 31 2012 - - + Added ability to override the default scheduler task selection mechanism - with implementations that make use of architecture specific instructions. - + Added ability to suppress tick interrupts during idle time, and in so - doing, provide the ability to make use of architecture specific low power - functionality. - + Added the portSUPPRESS_TICKS_AND_SLEEP() macro and vTaskStepTick() helper - function. - + Added the configSYSTICK_CLOCK_HZ configuration constant. - + Reworked the Cortex-M3 and Cortex-M4F port layers for GCC, Keil and IAR to - directly support basic power saving functionality. - + Added hooks to allow basic power saving to be augmented in the application - by making use of chip specific functionality. - + Minor change to allow mutex type semaphores to be used from interrupts - (which would not be a normal usage model for a mutex). - + Change the behaviour of the interrupt safe interrupt mask save and restore - macros in the Cortex-M ports. The save macro now returns the previous - mask value. The restore macro now uses the previous mask value. These - changes are not necessary for the kernel's own implementation, and are - made purely because the macros were being used by application writers. - + Added eTaskStateGet() API function. - + Added port specific optimisations to the PIC32 port layer, and updated the - PIC32 demo applications to make use of this new feature. - + Added port specific optimisations to the Win32 simulator port. - + Added new ports and demo applications for the TI Hercules RM48 and TMS570 - safety microcontrollers. - + Added SAM3 demos targeting the ATSAM3S-EK2 and ATSAM3X-EK evaluation - boards. - + Updated the PIC32 MPLAB X project to manually set the compiler include - paths instead of using the IDE entry box following reports that the - include paths were somehow being deleted. - + Improved character handling in FreeRTOS+CLI. - -Changes between V7.1.1 and V7.2.0 released 14 August 2012 - - FreeRTOS V7.2.0 is backward compatible with FreeRTOS V7.1.2. - - + Added a FreeRTOS+ sub-directory. The directory contains some FreeRTOS+ - source code, and example projects that use the FreeRTOS Win32 simulator. - + Added a new example heap allocation implementation (heap_4.c) that - includes memory block coalescence. - + Added a demo that targets the Atmel SAM4S Cortex-M4 based microcontroller. - The demo is preconfigured to build using the free Atmel Studio 6 IDE and - GCC compiler. - + Added xSemaphoreTakeFromISR() implementation. - + The last parameter in ISR safe FreeRTOS queue and semaphore functions - (xHigherPriorityTaskWoken) is now optional and can be set to NULL if it - is not required. - + Update the IAR and MSP430X ports to clear all lower power mode bits before - exiting the tick interrupt [bug fix]. - + Allow xQueueReset() to be used, even when the queues event lists are not - empty. - + Added a vQueueDelete() handler for the FreeRTOS MPU port (this was - previously missing). - + Updated the vPortSVCHandler() functions in the FreeRTOS MPU port layer to - ensure it compiles with the latest ARM GCC compilers from Linaro. - + Updated the prvReadGP() function in the NIOS II port to ensure the compiler - can choose any register for the functions parameter (required at high - compiler optimisation levels). - + Add #error macros into the Keil and IAR Cortex-M ports to ensure they - cannot be built if the user has set configMAX_SYSCALL_INTERRUPT_PRIORITY - to 0. - + Added comments in the FreeRTOSConfig.h files associated with Cortex-M3 and - Cortex-M4 demos stating that the configMAX_SYSCALL_INTERRUPT_PRIORITY - parameter must not be set to 0. - + Introduce new INCLUDE_xQueueGetMutexHolder configuration constant - (defaulted to 0). - + Added two new list handling macros - for internal use only in upcoming new - products. - + Removed all mention of the legacy vTaskStartTrace and ulTaskEndTrace - macros. FreeRTOS+Trace supersedes the legacy trace. - + Added a configASSERT() into the vPortFree() function in heap_1.c as it is - invalid for the function to be called. - + Made the xRxLock and xTxLock members of the queue structure volatile. - This is probably not necessary, and is included as a precautionary - measure. - + Modify the assert() that checks to see if the priority passed into an - xTaskCreate() function is within valid bounds to permit the assert to be - used in the FreeRTOS MPU port. - + The software timer service (daemon) task is now created in a way that - to ensure compatibility with FreeRTOS MPU. - -Changes between V7.1.0 and V7.1.1 released May 1 2012 - - New ports: - - The following ports are brand new: - + Cortex-M3 Tasking - - The following ports have been available as separate downloads for a number - of months, but are now included in the main FreeRTOS download. - + Cortex-M0 IAR - + Cortex-M0 GCC - + Cortex-M4F GCC (with full floating point support) - - - New demos: - - The following demos are brand new: - + Renesas RX63N RDK (Renesas compiler) - - The following demos have been available as separate downloads for a number - of months, but are now included in the main FreeRTOS download. - + NXP LPC1114 GCC/LPCXpresso - + ST STM32F0518 IAR - + Infineon XMC4500 GCC/Atollic - + Infineon XMC4500 IAR - + Infineon XMC4500 Keil - + Infineon XMC4500 Tasking - - - Kernel miscellaneous / maintenance: - - + Introduced the portSETUP_TCB() macro to remove the requirement for the - Windows simulator to use the traceTASK_CREATE() macro, leaving the trace - macro available for use by FreeRTOS+Trace (https://www.FreeRTOS.org/trace). - + Added a new trace macro, traceMOVE_TASK_TO_READY_STATE(), to allow future - FreeRTOS+Trace versions to provide even more information to users. - + Updated the FreeRTOS MPU port to be correct for changes that were - introduced in FreeRTOS V7.1.0. - + Introduced the xQueueReset() API function. - + Introduced the xSemaphoreGetMutexHolder() API function. - + Tidy up various port implementations to add the static key word where - appropriate, and remove obsolete code. - + Slight change to the initial stack frame given to the RX600 ports to allow - them to be used in the Eclipse based E2Studio IDE without confusing GDB. - + Correct the alignment given to the initial stack of Cortex-M4F tasks. - + Added a NOP following each DINT instruction on MSP430 devices for strict - conformance with the instructions on using DINT. - + Changed the implementation of thread deletes in the Win32 port to prevent - the port making use of the traceTASK_DELETE() trace macros - leaving this - macro free for use by FreeRTOS+Trace. - + Made some benign changes to the RX600 Renesas compiler port layer to - ensure the code can be built to a library without essential code being - removed by the linker. - + Reverted the change in the name of the uxTaskNumber variable made in - V7.1.0 as it broke the IAR plug-in. - - - Demo miscellaneous / maintenance: - - + The command interpreter has now been formally released as FreeRTOS+CLI, - and been moved out of the main FreeRTOS download, to instead be available - from the FreeRTOS+ Ecosystem site https://www.FreeRTOS.org/plus. - + flash_timer.c/h has been added to the list of standard demo tasks. This - performs the same functionality as the flash.c tasks, but using software - timers in place of tasks. - + Upgraded the PIC32 demo as follows: Changes to how the library functions - are called necessitated by the new compiler version, addition of MPLAB X - project with PIC32MX360, PIC32MX460 and PIC32MX795 configurations, - addition of simply blinky demo, updated FreeRTOSConfig.h to include more - parameters, addition of hook function stubs. - + The MSP430X IAR and CCS demos have been updated to ensure the power - settings are correct for the configured CPU frequency. - + Rowley CrossWorks projects have been updated to correct the "multiple - definition of ..." warnings introduced when the toolchain was updated. - + Updated various FreeRTOSConfig.h header files associated with projects - that build with Eclipse to include a #error statement informing the user - that the CreateProjectDirectoryStructure.bat batch file needs to be - executed before the projects can be opened. - + Renamed directories that included "CCS4" in their name to remove the '4' - and instead just be "CCS". This is because the demo was updated and - tested to also work with later Code Composer Studio versions. - + Updated the TCP/IP periodic timer frequency in numerous uIP demos to be - 50ms instead of 500ms. - -Changes between V7.0.2 and V7.1.0 released December 13 2011 - - New ports: - - + Cortex-M4F IAR port. - + Cortex-M4F Keil/RVDS port. - + TriCore GCC port. - - New demos: - - + NXP LPC4350 using the Keil MDK, and demonstrated on a Hitex development - board. - + ST STM32F407 using the IAR Embedded Workbench for ARM, and demonstrated on - the IAR STM32F407ZG-SK starter kit. - + Infineon TriCore TC1782, using the GCC compiler, demonstrated on the - TriBoard TC1782 evaluation board. - + Renesas RX630, using the Renesas compiler and HEW, demonstrated on an - RX630 RSK (Renesas Starter Kit). - - Miscellaneous / maintenance: - - + Removed all calls to printf() from the K60/IAR Kinetis demo so the project - can execute stand alone - without being connected to the debugger. - + Completed the command interpreter framework. Command handlers now receive - the entire command string, giving them direct access to parameters. - Utility functions are provided to check the number of parameters, and - return parameter sub-strings. - + The previously documented fix for the bug in xTaskResumeFromISR() that - effected (only) ports supporting interrupt nesting has now been - incorporated into the main release. - + The portALIGNMENT_ASSERT_pxCurrentTCB() definition has been added to allow - specific ports to skip the second stack alignment check when a task is - created. This is because the second check is not appropriate for some - ports - including the new TriCore port where the checked pointer does not - actually point to a stack. - + The portCLEAN_UP_TCB() macro has been added to allow port specific clean - up when a task is deleted - again this is required by the TriCore port. - + Various other minor changes to ensure warning free builds on a growing - number of microcontroller and toolchain platforms. This includes a - (benign) correction to the prototype of the - vApplicationStackOverflowHook() definition found in lots of recent demos. - - Trace system: - - + The legacy trace mechanism has been completely removed - it has been - obsolete for the years since the trace macros were introduced. The - configuration constant configUSE_TRACE_FACILITY is now used to optionally - include additional queue and task information. The additional information - is intended to make the trace mechanism more generic, and allow the trace - output to provide more information. When configUSE_TRACE_FACILITY is set - to 1: - - the queue structure includes an additional member to hold the queue - type, which can be base, mutex, counting semaphore, binary semaphore - or recursive mutex. - - the queue structure includes an additional member to hold a queue - number. A trace tool can set and query the queue number for its own - purposes. The kernel does not use the queue number itself. - - the TCB structure includes an additional member to hold a task number - number. A trace tool can set and query the task number for its own - purposes. The kernel does not use the task number itself. - + Queues and all types of semaphores are now automatically allocated their - type as they are created. - + Added two new trace macros - traceTASK_PRIORITY_INHERIT() and - traskTASK_PRIORITY_DISINHERIT(). - + Updated the traceQUEUE_CREATE_FAILED() macro to take a parameter that - indicates the type of queue, mutex, or semaphore that failed to be - created. - + The position from which traceCREATE_MUTEX() is called has been moved from - after the call to xQueueGenericSend() [within the same function] to before - the call. This ensures the trace events occur in the correct order. - + The value passed into tracePRIORITY_SET() has been corrected for the case - where vTaskPrioritySet() is called with a null parameter. - -Changes between V7.0.1 and V7.0.2 released September 20 2011 - - New ports: - - + The official FreeRTOS Renesas RX200 port and demo application have been - incorporated into the main FreeRTOS zip file download. - + The official FreeRTOS Renesas RL78 port and demo application have been - incorporated into the main FreeRTOS zip file download. - + The official FreeRTOS Freescale Kinetis K60 tower demo application has - been incorporated into the main FreeRTOS zip file download. This includes - an embedded web server example. - + A new Microblaze V8 port layer has been created to replace the older, now - deprecated, port layer. The V8 port supports V8.x of the Microblaze IP, - including exceptions, caches, and the floating point unit. A new - Microblaze demo has also been added to demonstrate the new Microblaze V8 - port layer. The demo application was created using V13.1 of the Xilinx - EDK, and includes a basic embedded web server that uses lwIP V1.4.0. - + The official FreeRTOS Fujitsu FM3 MB9A310 demo application has been - incorporated into the main FreeRTOS zip file download. Projects are - provided for both the IAR and Keil toolchains. - - - API additions: - - + xTaskGetIdleTaskHandle() has been added. - + xTaskGetTimerDaemonTaskHandle() has been added. - + pcTaskGetTaskName() has been added. - + vSemaphoreDelete() macro has been added to make it obvious how to delete - a semaphore. In previous versions vQueueDelete() had to be used. - + vTaskCleanUpResources() has been removed. It has been obsolete for a - while. - + portPOINTER_SIZE_TYPE has been introduced to prevent compiler warnings - being generated when the size of a pointer does not match the size of - the stack type. This will (has already) be used in new ports, but will - not be retrofitted to existing ports until the existing port itself is - updated. - - Other updates and news: - - + The core files have all been modified to tighten the coding standard even - further. These are style, not functional changes. - + All ARM7 port layers have been slightly modified to prevent erroneous - assert() failures when tasks are created and configASSERT() is defined. - + All ARM IAR projects have been updated to build with the latest V6.2.x - versions of the IAR Embedded Workbench for ARM tools (EWARM). This was - necessary due to a change in the way EWARM uses the CMSIS libraries. - + The PIC32 port layer has been updated in preparation for V2 of the C32 - compiler. - + The old Virtex-4 Microblaze demo has been marked as deprecated. Please - use the brand new Spartan-6 port and demo in its place. - + The bones of a new generic command interpreter is located in - FreeRTOS/Demo/Common/Utils/CommandInterpreter.c. This is still a work in - progress, and not documented. It is however already in use. It will be - documented in full when the projects that are already using it are - completed. - + A couple of new standard demos have been included. First, a version of - flop.c called sp_flop.c. This is similar to flop.c, but uses single - precision floats in place of double precision doubles. This allows the - for testing ports to processors that have only single precision floating - point units, and revert to using emulated calculations whenever a double - is used. Second, comtest_strings.c has been included to allow the test - of UART drivers when an entire string is transmitted at once. The - previous comtest.c only used single character transmission and reception. - + lwIP V1.4.0 is now included in the FreeRTOS/Demo/Common directory, and - used by a couple of new demos. - -Changes between V7.0.0 and V7.0.1 released May 13 2011 - - + Added a Fujitsu FM3 demo application for both the IAR and Keil tool - chains. - + Added a SmartFusion demo application for all of the IAR, Keil and - SoftConsole (GCC/Eclipse) tool chains. - + Updated the RX600 port and demo applications to take into account the - different semantics required when using the latest (V1.0.2.0) version of - the Renesas compiler. - + Modified the RX600 Ethernet driver slightly to make it more robust under - heavy load, and updated the uIP handling task to make use of the FreeRTOS - software timers. - + Slightly changed the PIC32 port layer to move an ehb instruction in line - with the recommendations of the MIPS core manual, and ensure 8 byte stack - alignment is truly always obtained. - + Changed the behaviour when tasks are suspended before the scheduler has - been started. Before, there needed to be at least one task that was not - in the suspended state. This is no longer the case. - -Changes between V6.1.1 and V7.0.0 released April 8 2011 - - FreeRTOS V7.0.0 is backward compatible with FreeRTOS V6.x.x - - Main changes: - - + Introduced a new software timer implementation. - + Introduced a new common demo application file to exercise the new timer - implementation. - + Updated the Win32/MSVC simulator project to include the new software timer - demo tasks and software timer tick hook test. Much simpler software timer - demonstrations are included in the demo projects for both of the new ports - (MSP430X with CCS4 and STM32 with TrueStudio). - + Various enhancements to the kernel implementation in tasks.c. These are - transparent to users and do not effect the pre-existing API. - + Added calls to configASSERT() within the kernel code. configASSERT() is - functionally equivalent to the standard C assert() macro, but does not - rely on the compiler providing assert.h. - - Other changes: - - + Updated the MSP430X IAR port and demo project to include support for the - medium memory model. - + Added a demo project for the MSP430X that targets the MSP430X Discovery - board and uses the Code Composer Studio 4 tools. This demo includes use - of the new software timer implementation. - + Added an STM32F100RB demo project that targets the STM32 Discovery Board - and uses the TrueStudio Eclipse based IDE from Atollic. - + Removed some compiler warnings from the PSoC demo application. - + Updated the PIC32 port layer to ensure the - configMAX_SYSCALL_INTERRUPT_PRIORITY constant works as expected no matter - what its value is (within the valid range set by the microcontroller - kernel). - + Updated the PIC24, dsPIC and PIC32 projects so they work with the latest - MPLAB compiler versions from Microchip. - + Various cosmetic changes to prepare for a standards compliance statement - that will be published after the software release. - - -Changes between V6.1.0 and V6.1.1 released January 14 2011 - - + Added two new Windows simulator ports. One uses the free Microsoft Visual - Studio 2010 express edition, and the other the free MingW/Eclipse - environment. Demo projects are provided for both. - + Added three demo projects for the PSoC 5 (CYAC5588). These are for the - GCC, Keil, and RVDS build tools, and all use the PSoC Creator IDE. - + Added a demo for the low power STM32L152 microcontroller using the IAR - Embedded Workbench. - + Added a new port for the MSP430X core using the IAR Embedded Workbench. - + Updated all the RX62N demo projects that target the Renesas Demonstration - Kit (RDK) to take into account the revered LED wiring on later hardware - revisions, and the new J-Link debug interface DLL. - + Updated all the RX62N demo projects so the IO page served by the example - embedded web server works with all web browsers. - + Updated the Red Suite projects to work with the up coming Red Suite - release, and to use a more recent version of the CMSIS libraries. - + Added the traceTAKE_MUTEX_RECURSIVE_FAILED() trace macro. - + Removed the (pointless) parameter from the traceTASK_CREATE_FAILED() - trace macro. - + Introduced the portALT_GET_RUN_TIME_COUNTER_VALUE() macro to compliment - the already existing portGET_RUN_TIME_COUNTER_VALUE(). This allows for - more flexibility in how the time base for the run time statistics feature - can be implemented. - + Added a "cpsie i" instruction before the "svc 0" instruction used to start - the scheduler in each of the Cortex M3 ports. This is to ensure that - interrupts are globally enabled prior to the "svc 0" instruction being - executed in cases where interrupts are left disabled by the C start up - code. - + Slight optimisation in the run time stats calculation. - -Changes between V6.0.5 and V6.1.0 released October 6 2010 - - + Added xTaskGetTickCountFromISR() function. - + Modified vTaskSuspend() to allow tasks that have just been created to be - immediately suspended even when the kernel has not been started. This - allows them to effectively start in the Suspended state - a feature that - has been asked for on numerous occasions to assist with initialisation - procedures. - + Added ports for the Renesas RX62N using IAR, GCC and Renesas tool suites. - + Added a STM32F103 demo application that uses the Rowley tools. - + Under specific conditions xFreeBytesRemaining within heap_2.c could end up - with an incorrect value. This has been fixed. - + xTaskCreateGeneric() has a parameter that can be used to pass the handle - of the task just created out to the calling task. The assignment to this - parameter has been moved to ensure it is assigned prior to the newly - created having any possibility of executing. This takes into account the - case where the assignment is made to a global variable that is accessed by - the newly created task. - + Fixed some build time compiler warnings in various FreeTCPIP (based on - uIP) files. - + Fixed some build time compiler warnings in Demo/Common/Minimal/IntQueue.c. - -Changes between V6.0.4 and V6.0.5 released May 17 2010 - - + Added port and demo application for the Cortus APS3 processor. - -Changes between V6.0.3 and V6.0.4 released March 14 2010 - - + All the contributed files that were located in the Demo/Unsupported_Demos - directory have been removed. These files are instead now available in the - new Community Contributions section of the FreeRTOS website. See - https://www.FreeRTOS.org/RTOS-contributed-ports.html - + The project file located in the Demo/CORTEX_STM32F107_GCC_Rowley directory - has been upgraded to use V2.x of the Rowley Crossworks STM32 support - package. - + An initial Energy Micro EFM32 demo has been included. This will be - updated over the coming months to make better use of the low power modes - the EFM32 provides. - -Changes between V6.0.2 and V6.0.3 released February 26 2010 - - + SuperH SH7216 (SH2A-FPU) port and demo application added. - + Slight modification made to the default implementation of - pvPortMallocAligned() and vPortFreeAligned() macros so by default they - just call pvPortMalloc() and vPortFree(). The macros are only needed to - be defined when a memory protection unit (MPU) is being used - and then - only depending on other configuration settings. - -Changes between V6.0.1 and V6.0.2 released January 9th 2010 - - + Changed all GCC ARM 7 ports to use 0 as the SWI instruction parameter. - Previously the parameter was blank and therefore only an implicit 0 but - newer GCC releases do not permit this. - + Updated IAR SAM7S and SAM7X ports to work with IAR V5.40. - + Changed the stack alignment requirement for PIC32 from 4 bytes to 8 bytes. - + Updated prvListTaskWithinSingleList() is it works on processors where the - stack grows up from low memory. - + Corrected some comments. - + Updated the startup file for the RVDS LPC21xx demo. - -Changes between V6.0.0 and V6.0.1 released November 15th 2009 - - + Altered pxPortInitialiseStack() for all Cortex-M3 ports to ensure the - stack pointer is where the compiler expects it to be when a task first - starts executing. - - The following minor changes only effect the Cortex-M3 MPU port: - - + portRESET_PRIVILEGE() assembly macro updated to include a clobber list. - + Added prototypes for all the privileged function wrappers to ensure no - compile time warnings are generated no matter what the warning level - setting. - + Corrected the name of portSVC_prvRaisePrivilege to - portSVC_RAISE_PRIVILEGE. - + Added conditional compilation into xTaskGenericCreate() to prevent some - compilers issuing warnings when portPRIVILEGE_BIT is defined as zero. - - -Changes between V5.4.2 and V6.0.0 released October 16th 2009 - - FreeRTOS V6 is backward compatible with FreeRTOS V5.x. - - Main changes: - - + FreeRTOS V6 is the first version to include memory protection unit (MPU) - support. Two ports now exist for the Cortex M3, the standard FreeRTOS - which does not include MPU support, and FreeRTOS-MPU which does. - + xTaskCreateRestricted() and vTaskAllocateMPURegions() API functions added - in support of FreeRTOS-MPU. - + Wording for the GPL exception has been (hopefully) clarified. Also the - license.txt file included in the download has been fixed (the previous - version contained some corruption). - - Other changes: - - + New API function xPortGetFreeHeapSize() added to heap_1.c and heap_2.c. - + ARM7 GCC demo interrupt service routines wrappers have been modified to - call the C portion using an __asm statement. This prevents the function - call being inlined at higher optimisation levels. - + ARM7 ports now automatically set the THUMB bit if necessary when - setting up the initial stack of a task - removing the need for - THUMB_INTERWORK to be defined. This also allows THUMB mode and ARM mode - tasks to be mixed more easily. - + All ARM7/9 ports now have portBYTE_ALIGNMENT set to 8 by default. - + Various demo application project files have been updated to be up to date - with the latest IDE versions. - + The linker scripts used with command line GCC demos have been updated to - include an eh_frame section to allow their use with the latest Yagarto - release. Likewise the demo makefiles have been updated to include - command line options to reduce or eliminate the eh_frame section all - together. - + The definition of portBYTE_ALIGNMENT_MASK has been moved out of the - various memory allocation files and into the common portable.h header - file. - + Removed unnecessary use of portLONG, portSHORT and portCHAR. - + Added LM3Sxxxx demo for Rowley CrossWorks. - + Posix simulator has been upgraded - see the corresponding WEB page on the - FreeRTOS.org site. - - -Changes between V5.4.1 and V5.4.2 released August 9th 2009 - - + Added a new port and demo app for the Altera Nios2 soft core. - + Added LPC1768 demo for IAR. - + Added a USB CDC demo to all LPC1768 demos (Code Red, CrossWorks and IAR). - + Changed clock frequency of LPC1768 demos to 99MHz. - -Changes between V5.4.0 and V5.4.1 released July 25th 2009 - - + New hook function added. vApplicationMallocFailedHook() is (optionally) - called if pvPortMalloc() returns NULL. - + Additional casting added to xTaskCheckForTimeOut(). This prevents - problems that can arise should configUSE_16_BIT_TICKS be set to 1 on a - 32 bit architecture (which would probably be a mistake, anyway). - + Corrected the parameter passed to NVIC_SetPriority() to set the MAC - interrupt priority in both LPC1768 demos. - + Decreased the default setting of configMINIMAL_STACK_SIZE in the PIC32 - demo application to ensure the heap space was not completely consumed - before the scheduler was started. - -Changes between V5.3.1 and V5.4.0 released July 13th 2009 - - + Added Virtex5 / PPC440 port and demos. - + Replaced the LPC1766 Red Suite demo with an LPC1768 Red Suite demo. The - original demo was configured to use engineering samples of the CPU. The - new demo has an improved Ethernet driver. - + Added LPC1768 Rowley demo with zero copy Ethernet driver. - + Reworked byte alignment code to ensure 8 byte alignment works correctly. - + Set configUSE_16_BIT_TICKS to 0 in the PPC405 demo projects. - + Changed the initial stack setup for the PPC405 to ensure the small data - area pointers are setup correctly. - -Changes between V5.3.0 and V5.3.1 released June 21st 2009 - - + Added ColdFire V1 MCF51CN128 port and WEB server demo. - + Added STM32 Connectivity Line STM32107 Cortex M3 WEB server demo. - + Changed the Cortex M3 port.c asm statements to __asm so it can be - compiled using Rowley CrossWorks V2 in its default configuration. - + Updated the Posix/Linux simulator contributed port. - -Changes between V5.2.0 and V5.3.0 released June 1st 2009 - - Main changes: - - + Added new (optional) feature that gathers statistics on the amount of CPU - time used by each task. - + Added a new demo application for the Atmel AT91SAM3U Cortex-M3 based - microcontroller. - + Added a new demo application for the NXP LPC1766 Cortex-M3 based - microcontroller. - + Added a contributed port/demo that allows FreeRTOS to be 'simulated' in a - Linux environment. - - Minor changes: - + Updated the Stellaris uIP WEB server demos to include the new run time - statistics gathering feature - and include a served WEB page that - presents the information in a tabular format. - + Added in the lwIP port layer for the Coldfire MCF52259. - + Updated the CrossWorks LPC2368 WEB server to include an image in the - served content. - + Changed some of the timing in the initialisation of the LPC2368 MAC to - permit its use on all part revisions. - + Minor modifications to the core uIP code to remove some compiler warnings. - + Added xTaskGetApplicationTaskTag() function and updated the OpenWatcom - demo to make use of the new function. - + Added contributed demos for AVR32 AP7000, STM32 Primer 2 and STM32 using - Rowley Crossworks. - + Heap_1.c and Heap_2.c used to define structures for the purpose of data - alignment. These have been converted to unions to save a few bytes of - RAM that would otherwise be wasted. - + Remove the call to strncpy() used to copy the task name into the TCB when - the maximum task name is configured to be 1 byte long. - -Changes between V5.1.2 and V5.2.0 released March 14th 2009 - - + Optimised the queue send and receive functions (also used by semaphores). - + Replaced the standard critical sections used to protect BIOS calls in the - PC port to instead use scheduler locks. This is because the BIOS calls - always return with interrupts enabled. - + Corrected unclosed comments in boot.s. - -Changes between V5.1.1 and V5.1.2 released February 9th 2009 - - + Added NEC V850ES port and demo. - + Added NEC 78K0R port and demo. - + Added MCF52259 port and demo. - + Added the AT91SAM9XE port and demo. - + Updated the MCF52233 FEC driver to work around a silicon bug that - prevents the part auto negotiating some network parameters. - + Minor modifications to the MCF52233 makefile to permit it to be used - on Linux hosts. - + Updated the STM32 primer files to allow them to be built with the latest - version of the RIDE tools. - + Updated the threads.js Java script used for kernel aware debugging in - the Rowley CrossWorks IDE. - - -Changes between V5.1.0 and V5.1.1 released November 20, 2008 - - + Added Coldfire MCF52233 WEB server demo using GCC and Eclipse. - + Added IAR MSP430 port and demo. - + Corrected several compiler time issues that had crept in as tool versions - change. - + Included FreeRTOS-uIP - a faster uIP. This is not yet complete. - -Changes between V5.0.4 and V5.1.0 released October 24, 2008 - - + Added a new port and demo application for the ColdFire V2 core using the - CodeWarrior development tools. - + Replaced the ARM7 demo that used the old (and now no longer supported) - Keil compiler with a new port that uses the new Keil/RVDS combo. - + Stack overflow checking now works for stacks that grow up from low - memory (PIC24 and dsPIC). - + BUG FIX - set the PIC32 definition of portSTACK_GROWTH to the correct - value of -1. - + MSP430 port layers have been updated to permit tasks to place the - microcontroller into power down modes 1 to 3. The demo applications have - likewise been updated to demonstrate the new feature. - + Replaced the two separate MSP430/Rowley port layers with a single and more - flexible version. - + Added more contributed ports, including ports for NEC and SAM9 - microcontrollers. - + Changed the linker script used in the LPC2368 Eclipse demo. - -Changes between V5.0.3 and V5.0.4 released September 22, 2008 - - + Completely re-written port for ColdFire GCC. - + Bug fix: All Cortex M3 ports have a minor change to the code that sets - the pending interrupt. - + Some header files require that FreeRTOS.h be included prior to their - inclusion. #error message have been added to all such header file - informing users to the cause of the compilation error should the headers - not be included in the correct order. - -Changes between V5.0.2 and V5.0.3 released July 31, 2008 - - Changes relating to the Cortex M3: - - + Added configMAX_SYSCALL_INTERRUPT_PRIORITY usage to all the Cortex M3 - ports and demos. See the port documentation pages on the FreeRTOS.org - WEB site for full usage information. - + Improved efficiency of Cortex M3 port even further. - + Ensure the Cortex M3 port works no matter where the vector table is - located. - + Added the IntQTimer demo/test tasks to a demo project for each CM3 port - (Keil, GCC and IAR) to test the new configMAX_SYSCALL_INTERRUPT_PRIORITY - functionality. - + Added the mainINCLUDE_WEB_SERVER definition to the LM3SXXXX IAR and Keil - projects to allow the WEB server to be conditionally excluded from the - build and therefore allow use of the KickStart (code size limited) - compiler version. - - Other changes: - - + Moved the PIC24 and dsPIC versions of vPortYield() from the C file to - an assembly file to allow use with all MPLAB compiler versions. This also - allows the omit-frame-pointer optimisation to be turned off. - -Changes between V5.0.0 and V5.0.2 released May 30, 2008 - - + Updated the PIC32 port to allow queue API calls to be used from - interrupts above the kernel interrupt priority, and to allow full - interrupt nesting. Task stack usages has also been reduced. - + Added a new PowerPC port that demonstrates how the trace macros can be - used to allow the use of a floating point co-processor. The - traceTASK_SWITCHED_OUT() and traceTASK_SWITCHED_INT() macros are used to - save and restore the floating point context respectively for those tasks - that actually use floating point operations. - + BUG FIX: The first PPC405 port contained a bug in that it did not leave - adequate space above the stack for the backchain to be saved when a task - started to execute for the first time. - + Updated queue.c to add in the means to allow interrupt nesting and for - queue API functions to be called from interrupts that have a priority - above the kernel priority. This is only supported on PIC32 ports thus - far. - + Fixed the compiler warnings that were generated when the latest version - of WinAVR was used. - + Remove all inline usage of 'inline' from the core kernel code. - + Added the queue registry feature. The queue registry is provided as a - means for kernel aware debuggers to locate queue definitions. It has no - purpose unless you are using a kernel aware debugger. The queue registry - will only be used when configQUEUE_REGISTRY_SIZE is greater than zero. - + Added the ST Cortex-M3 drivers into the Demo/Common/Drivers directory to - prevent them from having to be included in multiple demos. - + Added a Keil STM32 demo application. - + Changed the blocktim.c test files as it is no longer legitimate for all - ports to call queue API functions from within a critical section. - + Added the IntQueue.c test file to test the calling of queue API functions - from different interrupt priority levels, and test interrupt nesting. - -Changes between V5.0.0 and V5.0.1 - - + V5.0.1 was a customer specific release. - -Changes between V4.8.0 and V5.0.0 released April 15, 2008 - - *** VERY IMPORTANT INFORMATION ON UPGRADING TO FREERTOS.ORG V5.0.0 *** - - The parameters to the functions xQueueSendFromISR(), xQueueSendToFrontFromISR(), - xQueueSendToBackFromISR() and xSemaphoreGiveFromISR() have changed. You must - update all calls to these functions to use the new calling convention! Your - compiler might not issue any type mismatch warnings! - - - Other changes: - - + Support added for the new Luminary Micro LM3S3768 and LM3S3748 Cortex-M3 - microcontrollers. - + New task hook feature added. - + PowerPC demo updated to use version 10.1 of the Xilinx EDK. - + Efficiency gains within the PIC32 port layer. - -Changes between V4.7.2 and V4.8.0 released March 26 2008 - - + Added a Virtex4 PowerPC 405 port and demo application. - + Added optional stack overflow checking and new - uxTaskGetStackHighWaterMark() function. - + Added new xQueueIsQueueEmptyFromISR(), xQueueIsQueueFullFromISR() and - uxQueueMessagesWaitingFromISR() API functions. - + Efficiency improvements to the Cortex-M3 port layer. NOTE: This - requires that an SVC handler be installed in the application. - + Efficiency improvements to the queue send and receive functions. - + Added new trace macros. These are application definable to provide - a flexible trace facility. - + Implemented the configKERNEL_INTERRUPT_PRIORITY within the Keil Cortex - M3 port layer (bringing it up to the same standard as the IAR and GCC - versions). - + Ports that used the arm-stellaris-eabi-gcc tools have been converted to - use the arm-non-eabi-gcc tools. - -Changes between V4.7.1 and V4.7.2 released February 21, 2008 - - + Added Fujitsu MB91460 port and demo. - + Added Fujitsu MB96340 port and demo. - + Tidied up the capitalisation of include files to facilitate builds on - Linux hosts. - + Removed some redundant casting that was generating warnings - but was - included to remove warnings on other compilers. - -Changes between V4.7.0 and V4.7.1 released February 3, 2008 - - + Updated all IAR ARM projects to use V5.11 of the IAR Embedded Workbench - for ARM. - + Introduced recursive semaphore feature. - + Updated LPC2368 demos to take into account silicon bugs in old chip - revisions. - + Updated STR9 uIP port to manually set the net mask and gateway addresses. - + Updating demos to allow more to run with the co-operative scheduler. - + Fixed co-operative scheduler behaviour upon the occurrence of a tick - interrupt while the scheduler was suspended. - + Updated documentation contained within semphr.h. - + ARM7 GCC ports no longer use the IRQ attribute. - -Changes between V4.6.1 and V4.7.0 released December 6, 2007 - - + Introduced the counting semaphore macros and demo source files. The - Open Watcom PC project has been updated to include the new demo. See - the online documentation for more information. - + Introduced the 'alternative' queue handling API and demo source files. - The Open Watcom PC project has been updated to include the new demo - source files. See the online documentation for more information. - + Added AT91SAM7X Eclipse demo project. - + Added the STM32 primer demo project for the GCC compiler and Ride IDE. - + Removed the .lock files that were mistakenly included in the V4.6.1 - eclipse workspaces. - -Changes between V4.6.0 and V4.6.1 released November 5 2007 - - + Added support for the MIPS M4K based PIC32. - + Added 'extern "C"' to all the header files to facilitate use with C++. - -Changes between V4.5.0 and V4.6.0 released October 28 2007 - - + Changed the method used to force a context switch within an ISR for the - ARM7/9 GCC ports only. The portENTER_SWITCHING_ISR() and - portEXIT_SWITCHING_ISR() macros are no longer supported. This is to - ensure correct behaviour no matter which GCC version is used, with or - without the -fomit-frame-pointer option, and at all optimisation levels. - + Corrected the prototype for xQueueGenericSend() within queue.h. - -Changes between V4.4.0 and V4.5.0 released September 17 2007 - - + Added the xQueueSendToFront(), xQueueSendToBack() and xQueuePeek() - functionality. These should now be used in preference to the old - xQueueSend() function - which is maintained for backward compatibility. - + Added Mutex functionality. The behaviour of mutexes is subtly different - to the already existing binary semaphores as mutexes automatically - include a priority inheritance mechanism. - + Added the GenQTest.c and QPeek.c to test and demonstrate the behaviour - of the new functionality. - + Updated the LM3Sxxxx and PC ports to include the new GenQTest.c and - QPeek.c files. - + Updated the GCC port for the Cortex M3 to include the - configKERNEL_INTERRUPT_PRIORITY functionality. This was previously only - included in the IAR port. - + Optimised the GCC and IAR port layer code - specifically the context - switch code. - + Consolidated the LM3Sxxxx EK demos for all development tools into a - single project that automatically detects which version of the EK the - application is executing on. - + Added Eclipse support for LM3Sxxxx evaluation kits. - + Added Eclipse support for the Keil LPC2368 evaluation kit. - + Added the Demo/Drivers directory to hold code that is common to multiple - demo application projects. - + Included some minor bug fixes in the uIP 1.0 code. - + Added an lwIP demo for the STR9 - thanks ST for assistance. - + Updated the AVR32 port to ensure correct behaviour with full compiler - optimisation. - + Included binaries for OpenOCD FTDI and parallel port interfaces. - -Changes between V4.4.0 and V4.3.1 released July 31, 2007 - - + Added AVR32 UC3B demo application. - + Updated AVR32 UC3A port and demo applications. - + Added IAR lwIP demo for AVR32 UC3A. - + Updated listGET_OWNER_OF_NEXT_ENTRY() to assist compiler optimisation - (thanks Niu Yong for making the suggestion). - + Added xTaskGetSchedulerState() API function. - + BUG FIX: Corrected behaviour when tasks that are blocked indefinitely - have their block time adjusted (within xQueueSend() and xQueueReceive()), - and are the subject of a call the vTaskResume() when they are not - actually in the Suspended state (thanks Dan Searles for reporting the - issues). - - -Changes between V4.3.0 and V4.3.1 released June 11, 2007 - - + Added STMicroelectronics STM32 Cortex-M3 demo application. - + Updated ustdlib.c for the GCC LM3S6965 demo. - -Changes between V4.2.1 and V4.3.0 released June 5, 2007 - - + Introduced configKERNEL_INTERRUPT_PRIORITY to the IAR Cortex-M3, PIC24 - and dsPIC ports. See the LM3S6965 and PIC24 demo application - documentation pages for more information. - + Updated the PIC24 and dsPIC demos to build with V3.0 of the PIC30 GCC - tools, and changed the demo applications. - + Added demos for the new Ethernet and CAN enabled Luminary Micro Stellaris - microcontrollers. - + Corrected bug in uIP the demos that prevented frames of approximately 1480 - bytes and over from being transmitted. - + Included the LPC2368/uIP/Rowley demo into the main FreeRTOS.org - download. - + Update to WizC PIC18 port to permit its use with version 14 of the - compiler. Thanks Marcel! - -Changes between V4.2.1 and V4.2.0 released April 2, 2007 - - + Added AVR32 AT32UC3A ports for GCC and IAR. - + Added -fomit-frame-pointer option to lwIP SAM7X demo makefile. - + Moved location of call to LCD_Init() in STR9 demo to ensure it is only - called after the scheduler has been started. - -Changes between V4.1.3 and V4.2.0 released February 8, 2007 - - + Changes to both task.c and queue.c as a result of testing performed on - the SafeRTOS code base. - + Added Cortex-M3 LM3S811 demos for GCC and IAR tools. - -Changes between V4.1.2 and V4.1.3 released November 19, 2006 - - + Added STR750 ARM7 port using the Raisonance RIDE/GCC tools. - + Added -fomit-frame-pointer option to Rowley ARM7 demos as work around - to GCC bug at some optimisation levels. - + Altered the way the heap is defined in the LM3S811 Keil demo to prevent - the RAM usage from counting toward the code size limit calculation. - + CO-ROUTINE BUG FIX: Removed the call to prvIsQueueEmpty from within - xQueueCRReceive as it exited with interrupts enabled. Thanks Paul Katz. - + Tasks that block on events with a timeout of portMAX_DELAY are now - blocked indefinitely if configINCLUDE_vTaskSuspend is defined. - Previously portMAX_DELAY was just the longest block time possible. This - is still the case if configINCLUDE_vTaskSuspend is not defined. - + Minor changes to some demo application files. - -Changes between V4.1.1 and V4.1.2 released October 21, 2006 - - + Added 16bit PIC ports and demos. - + Added STR750 port and demo. - - -Changes between V4.1.0 and V4.1.1 released September 24, 2006 - - + Added the Luminary Micro Stellaris LM3S811 demo application. - -Changes between V4.0.5 and V4.1.0 released August 28, 2006 - - + Prior to V4.1.0, under certain documented circumstances, it was possible - for xQueueSend() and xQueueReceive() to return without having completed - and without their block time expiring. The block time effectively - stated a maximum block time, and the return value of the function needed - to be checked to determine the reason for returning. This is no longer - the case as the functions will only return once the block time has - expired or they are able to complete their operation. It is therefore no - longer necessary to wrap calls within loops. - + Changed the critical section handling in the IAR AVR port to correct the - behaviour when used with later compiler versions. - + Added the LPC2138 CrossWorks demo into the zip file. Previously this was - only available as a separate download. - + Modified the AVR demo applications to demonstrate the use of co-routines. - -Changes between V4.0.4 and V4.0.5 released August 13, 2006 - - + Introduced API function xTaskResumeFromISR(). Same functionality as - xTaskResume(), but can be called from within an interrupt service routine. - + Optimised vListInsert() in the case when the wake time is the maximum - tick count value. - + Bug fix: The 'value' of the event list item is updated when the priority - of a task is changed. Previously only the priority of the TCB itself was - changed. - + vTaskPrioritySet() and vTaskResume() no longer use the event list item. - This has not been necessary since V4.0.1 when the xMissedYield handling - was added. - + Lowered the PCLK setting on the ARM9 STR9 demo from 96MHz to 48MHz. - + When ending the scheduler - do not try to attempt a context switch when - deleting the current task. - + SAM7X EMAC drivers: Corrected the Rx frame length mask when obtaining - the length from the rx descriptor. - - -Changes between V4.0.3 and V4.0.4 released June 22, 2006 - - + Added a port and demo application for the STR9 ARM9 based processors from - ST. - + Slight optimisation to the vTaskPrioritySet() function. - + Included the latest uIP version (1.0) in the demo/common/ethernet - directory. - -Changes between V4.0.2 and V4.0.3 released June 7, 2006 - - + Added a port and demo application for the Cortex-M3 target using the IAR - development tools. - + The ARM Cortex-m3 Rowley projects have been updated to use V1.6 of the - CrossStudio tools. - + The heap size defined for the lwIP Rowley demo has been reduced so that - the project will link correctly when using the command line GCC tools - also. The makefile has also been modified to allow debugging. - + The lwIP Rowley demo not includes a 'kernel aware' debug window. - + The uIP Rowley project has been updated to build with V1.6 of CrossWorks. - + The second set of tasks in the blockQ demo were created the wrong way - around (inconsistent to the description in the file). This has been - corrected. - -Changes between V4.0.1 and V4.0.2 released May 28, 2006 - - + Port and demo application added for the Tern Ethernet Engine controller. - + Port and demo application added for MC9S12 using GCC, thanks to - Jefferson "imajeff" Smith. - + The function vTaskList() now suspends the scheduler rather than disabling - interrupts during the creation of the task list. - + Allow a task to delete itself by passing in its own handle. Previously - this could only be done by passing in NULL. - + Corrected the value passed to the WDG_PeriodValueConfig() library - function in the STR71x demo. - + The tick hook function is now called only within a tick isr. Previously - it was also called when the tick function was called during the scheduler - unlocking process. - + The EMAC driver in the SAM7X lwIP demo has been made more robust as per - the thread: https://sourceforge.net/forum/message.php?msg_id=3714405 - + In the PC ports: Add function prvSetTickFrequencyDefault() to set the - DOS tick back to its proper value when the scheduler exits. Thanks - Raynald! - + In the Borland x86 ports there was a mistake in the portFIRST_CONTEXT - macro where the BP register was not popped from the stack correctly. The - BP value would never get used so this did not cause a problem, but it has - been corrected all the same. - - -Changes between V4.0.0 and V4.0.1 released April 7 2006 - - + Improved the ARM CORTEX M3 ports so they now only have to service - pendSV interrupts. - + Added a Luminary Micro port and demo for use with Rowley CrossWorks. - + Added the xMissedYield handling to tasks.c. - -Changes between V3.2.4 and V4.0.0 - - Major changes: - - + Added new RTOS port for Luminary Micros ARM CORTEX M3 microcontrollers. - + Added new co-routine functionality. - - Other kernel changes: - - + An optional tick hook call is now included in the tick function. - + Introduced the xMiniListItem structure and removed the list pxHead - member in order to reduce RAM usage. - + Added the following definitions to the FreeRTOSConfig.h file included - with every port: - configUSE_TICK_HOOK - configUSE_CO_ROUTINES - configMAX_CO_ROUTINE_PRIORITIES - + The volatile qualification has been changed on the list members to allow - the task.c code to be tidied up a bit. - + The scheduler can now be started even if no tasks have been created! - This is to allow co-routines to run when there are no tasks. - + A task being woken by an event will now preempt the currently running task - even if its priority is only equal to the currently running task. - - Port and demo application changes: - - + Updated the WinAVR demo to compile with the latest version of WinAVR - with no warnings generated. - + Changed the WinAVR makefile to make chars signed - needed for the - co-routine code if BaseType_t is set to char. - + Added new demo application file crflash.c. This demonstrates co-routine - functionality including passing data between co-routines. - + Added new demo application file crhook.c. This demonstrates co-routine - and tick hook functionality including passing data between and ISR and - a co-routine. - + Some NOP's were missing following stmdb{}^ instructions in various ARM7 - ports. These have been added. - + Updated the Open Watcom PC demo project to include the crflash and crhook - demo co-routines as an example of their use. - + Updated the H8S demo to compile with the latest version of GCC. - + Updated the SAM7X EMAC drivers to take into account the hardware errata - regarding lost packets. - + Changed the default MAC address used by some WEB server demos as the - original addresses used was not liked by some routers. - + Modified the SAM7X/IAR startup code slightly to prevent it hanging on - some systems when the code is executed using a j-link debugger. The - j-link macro file configures the PLL before the code executes so - attempting to configure it again in the startup code was causing a - problem for some user. Now a check is performed first to see if the - PLL is already set up. - + GCC port now contain all assembler code in a single asm block rather than - individual blocks as before. - + GCC LPC2000 code now explicitly uses R0 rather than letting the assembler - choose the register to use as a temporary register during the context - switch. - + Added portNOP() macro. - + The compare match load value on LPC2000 ports now has 1 added to correct - the value used. - + The minimal stack depth has been increased slightly on the WIZC PIC18 - port. - -Changes between V3.2.3 and V3.2.4 - - + Modified the GCC ARM7 port layer to allow use with GCC V4.0.0 and above. - Many thanks to Glen Biagioni for the provided update. - + Added a new Microblaze port and demo application. - + Modified the SAM7X EMAC demo to default to use the MII interface rather - than the RMII interface. - + Modified the startup sequence of the SAM7X demo slightly to allow the - EMAC longer to auto negotiate. - -Changes between V3.2.2 and V3.2.3 - - + Added MII interface support to the SAM7X EMAC peripheral driver. - Previously versions worked with the RMII interface only. - + Added command line GCC support to the SAM7X lwIP demo. Previously the - project could only be built using the CrossWorks IDE. Modifications to - this end include the addition of a standard makefile and linker script to - the download, and some adjustments to the stacks allocated to each task. - + Changed the page returned by the lwIP WEB server demo to display the - task status table rather than the TCP/IP statistics. - + Corrected the capitalisation of some header file includes and makefile - dependencies to facilitate use on Linux host computers. - + The various LPC2000 ports had a mistake in the timer setup where the - prescale value was written to T0_PC instead of T0_PR. This would have - no effect unless a prescale value was actually required. This has been - corrected. - -Changes between V3.2.1 and V3.2.2 - Released 23 September, 2005 - - + Added an IAR port for the Philips LPC2129 - + The Atmel ARM7 IAR demo project files are now saved in the IAR Embedded - Workbench V4.30a format. - + Updated the J-Link macro file included with the SAM7X uIP demo project - to allow the demo board to be reset over the J-Link. - -Changes between V3.2.0 and V3.2.1 - Released 1 September, 2005 - - + Added lwIP demo for AT91SAM7X using Rowley tools. - + Added uIP demo for AT91SAM7X using IAR tools. - + Added function xTaskGetCurrentTaskHandle(). - + Renamed events.h to mevents.h to prevent it conflicting with the events.h - generated automatically by the HCS12 processor expert utility. events.h - is only used by the PC demo application. - + Both PIC18 ports now initialise the TBLPTRU to 0 as this is the value - expected by the compiler, and the compilers do not write to this - register. - + The HCS12 banked model demo now creates the 'suicide' tasks immediately - prior to starting the scheduler. These tasks should be the last tasks to - get started in order for the test to function correctly. - -Changes between V3.1.1 and V3.2.0 - Released 29 June, 2005 - - V3.2.0 introduces two new MSP430 ports and corrects a minor kernel - issues. Thanks to Ares.qi for his input. - - + Added two MSP430 ports that use the Rowley CrossWorks development tools. - One port just mirrors the existing GCC port. The other port was provided - by Milos Prokic. Thanks! - + V3.2.0 corrects the behavior when vTaskPrioritySet() or vTaskResume() - are called while the scheduler is locked (by a call to - vTaskSuspendAll()). When this is done the subject task now starts to - execute immediately when the scheduler is unlocked if it has the highest - priority that is ready to run. Previously there was a possibility that - the task would not run until the next RTOS tick or call to portYIELD(). - + Another similar small correction ensures that in the case where more than - one task is blocked on a semaphore or queue, the task with the highest - priority is guaranteed to be unblocked first. - + Added a couple of more test tasks to the PC demo which cover the points - above. - -Changes between V3.1.0 and V3.1.1 - Released 21st June, 2005 - - This release updates the HCS12 port. The common kernel code - remains unchanged. - - + Updated the HCS12 port to support banking and introduced a demo - application for the MC9S12DP256. The new demo application is - located in the Demo/HCS12_CodeWarrior_banked directory. - + The name of the directory containing the MC9S12F32 demo application - has been changed to Demo/HCS12_CodeWarrior_small (as in 'small' - memory model). - + MC9S12F32 demo updated slightly to use the PLL. The CPU speed for the - demo application is now 24MHz. Previously it was 8MHz. - + The demo application file Demo/Common/Minimal/death.c has a slight - alteration to prevent it using floating point variables. - - -Changes between V3.0.0 and V3.1.0 - Released 11th June, 2005 - - + Added new ports for ST Microsystems STR71x, and Freescale HCS12 - microcontrollers. Currently the HCS12 port is limited to the small - memory model. Large memory models will be supported in the next - release. - + PIC18 wizC port updated. Thanks to Marcel van Lieshout for his - continuing contribution. - + The accuracy of the AVR port timer setup has been improved. Thanks to - Thomas Krutmann for this contribution. - + Added a new conditional compilation macro configIDLE_SHOULD_YIELD. - See the WEB documentation for details. - + Updated the CrossWorks uIP demo to build with V1.4 of CrossWorks. - + Slight modification to the SAM7 release build configuration to correct - an include path definition. - + Updated the MPLAB PIC18 documentation to provide extra details on linker - file configuration. - -Changes between V3.0.0 and V2.6.1 - Released 23rd April, 2005 - - V3.0.0 includes many enhancements, so this history list is broken into - subsections as follows: - - API changes - New ports - Directory name changes - Kernel and miscellaneous changes changes - - - API changes - - + Each port now defines BaseType_t as the data type that is most - efficient for that architecture. The type BaseType_t is used - extensively in API calls necessitating the following changes to the - FreeRTOS API function prototypes. - - See the "New for V3.0.0" section of the FreeRTOS online - documentation for full details of API changes. - - - New ports - - + The AT91FR40008 ARM7 port contributed by John Feller is now included - in the download (thanks John!). - + The PIC18 port for the wizC/fedC compiler contributed by Marcel van - Lieshout is now included in the download (thanks Marcel!). - + The IAR port for the AVR microcontroller has been upgraded to V3.0.0 - and is now a supported port. - - - Directory name changes - - For consistency, and to allow integration of the new ports, the - following directory names have been changed. - - + The source/portable/GCC/ARM7 directory has been renamed - source/portable/GCC/ARM7_LPC2000 so it is compatible with the naming - of other GCC ARM7 ports. - + The Demo/PIC directory has been renamed Demo/PIC18_MPLAB to - accommodate the wizC/fedC PIC port. - + The demo applications for the two AVR ports no longer share the same - directory. The WinAVR demo is in the Demo/AVR_ATMega323_WinAVR - directory and the IAR port in the Demo/AVR_ATMega323_IAR directory. - - - - Kernel and miscellaneous changes changes - - See the "New for V3.0.0" section of the FreeRTOS online - documentation for more information. - - + Previously 'portmacro.h' contained some user editable definitions - relating to the user application, and some fixed definitions relating - specifically to the port being used. The application specific - definitions have been removed from 'portmacro.h' and placed inside a - new header file called 'FreeRTOSConfig.h'. 'portmacro.h' should now - never be modified by the user. A 'FreeRTOSConfig.h' is now included - in each of FreeRTOS/Demo subdirectories - as it's settings relate to - the demo application rather than being specific to the port. - + Introduced configUSE_IDLE_HOOK in idle task. - + The idle task will yield when another idle priority task is ready to - run. Previously the idle task would run to the end of its time slice - regardless. - + The idle task is now created when the scheduler is started. This - requires less stack than the previous scheme where it was created upon - creation of the first application task. - + The function usPortCheckFreeStackSpace() has been renamed - usTaskCheckFreeStackSpace() and moved from the portable layer to - tasks.c. - + Corrected spelling of portMINMAL_STACK_SIZE to portMINIMAL_STACK_SIZE. - + The portheap.c file included with the AVR port has been deleted. The - AVR demo now uses the standard heap1 sample memory allocator. - + The GCC AVR port is now build using the standard make utility. The - batch files used previously have been deleted. This means a recent - version of WinAVR is required in order to create a binary suitable for - source level debugging. - + vTaskStartScheduler() no longer takes the configUSE_PREEMPTION - constant as a parameter. Instead the constant is used directly within - tasks.c and no parameter is required. - + The header file 'FreeRTOS.h' has been created and is used to include - 'projdefs.h', 'FreeRTOSConfig.h' and 'portable.h' in the necessary - order. FreeRTOS.h can now be included in place of these other - headers. - + The header file 'errors.h' has been deleted. The definitions it - contained are now located within 'projdefs.h'. - + pvPortMalloc() now takes a size_t parameter as per the ANSI malloc(). - Previously an unsigned short was used. - + When resuming the scheduler a yield is performed if either a tick has - been missed, or a task is moved from the pending ready list into a - ready list. Previously a yield was not performed on this second - condition. - + In heap1.c an overflow check has been added to ensure the next free - byte variable does not wrap around. - + Introduced the portTASK_FUNCTION() and portTASK_FUNCTION_PROTO() - macros. - + The MPLAB PIC port now saved the TABLAT register in interrupt service - routines. - -Changes between V2.6.0 and V2.6.1 - Released Feb 22, 2005 - - This version adds support for the H8 processor. - - Other changes: - - + tskMAX_TASK_NAME_LEN removed from the task.h header and added to each - individual portmacro.h file as portMAX_TASK_NAME_LEN. This allows RAM - limited ports to allocate fewer characters to the task name. - + AVR port - Replaced the inb() and outb() functions with direct memory - access. This allows the port to be built with the 20050414 build of - WinAVR. - + GCC LPC2106 port - removed the 'static' from the definition of - vNonPreemptiveTick() to allow the demo to link when using the cooperative - scheduler. - + GCC LPC2106 port - Corrected the optimisation options in the batch files - ROM_THUMB.bat, RAM_THUMB.bat, ROM_ARM.bat and RAM_ARM.bat. The lower case - -o is replaced by an uppercase -O. - + Tasks.c - The strcpy call has been removed when copying across the task - name into the TCB. - + Updated the trace visualisation to always be 4 byte aligned so it can be - used on ARM architectures. - + There are now two tracecon executables (that convert the trace file binary - into an ASCII file). One for big endian targets and one for little endian - targets. - + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called - too often in the idle task. - + SAM7 USB driver - Replaced the duplicated RX_DATA_BK0 in the interrupt - mask with the RX_DATA_BK1. - - -Changes between V2.5.5 and V2.6.0 - Released January 16, 2005 - - + Added the API function vTaskDelayUntil(). The demo app file - Demo/Common/Minimal/flash.c has been updated to demonstrate its use. - + Added INCLUDE_vTaskDelay conditional compilation. - + Changed the name of the Demo/ARM7_AtmelSAM7S64_IAR directory to - Demo/ARM7_AT91SAM7S64_IAR for consistency. - + Modified the AT91SAM7S USB driver to allow descriptors that have - a length that is an exact multiple of the FIFO to be transmitted. - -Changes between V2.5.4 and V2.5.5 - Released January 3, 2005 - - This version adds support for the Atmel SAM7 ARM7 microcontrollers - along with the IAR development tools. - - Other changes: - - + Renamed the Demo/ARM7 directory to Demo/ARM7_LPC2106_GCC. - + Renamed the Demo/ARM7_Keil directory to Demo/ARM7_LPC2129_Keil. - + Modified the Philips ARM7 serial interrupt service routines to only - process one interrupt per call. This seems to enable the ISR to - operate more quickly. - + Removed the 'far' keyword from the Open Watcom portable layer source - files. This allows their use with V1.3 of Open Watcom. - + Minor modifications to the SDCC build files to allow their use under - Linux. Thanks to Frieder Ferlemann for this contribution. - + Small change to sTaskCreate() to allow a context switch even when - pxCreatedTask is NULL. Thanks to Kamil for this contribution. - + inline keyword removed from vTaskSwitchContext() and VTaskIncrementTick() - definitions. - -Changes between V2.5.3 and V2.5.4 - Released Dec 1, 2004 - - This is an important maintenance release. - - The function cTaskResumeAll() has been modified so it can be used safely - prior to the kernel being initialised. This was an issue as - cTaskResumeAll() is called from pvPortMalloc(). Thanks to Daniel Braun - for highlighting this issue. - -Changes between V2.5.2 and V2.5.3 - Released Nov 2, 2004 - - The critical section handling functions have been changed for the GCC ARM7 - port. Some optimisation levels use the stack differently to others. This - means the interrupt flags cannot always be stored on the stack and are - instead now stored in a variable, which is then saved as part of the - tasks context. This allows the GCC ARM7 port to be used at all - optimisation levels - including -Os. - - Other minor changes: - - + MSP430 definition of usCriticalNesting now uses the volatile qualifier. - This is probably not required but added just in case. - -Changes between V2.5.1 and V2.5.2 - Released Oct 26, 2004 - - + Added the Keil ARM7 port. - + Slight modification to comtest.c to make the delay periods more random. - This creates a better test condition. - -Changes between V2.5.0 and V2.5.1 - Released Oct 9, 2004 - - + Added the MSP430 port. - + Extra comments added to the GCC ARM7 port.c and portISR.c files. - + The memory pool allocated within heap_1.c has been placed within a - structure to ensure correct memory alignment on 32bit systems. - + Within the GCC ARM7 serial drivers an extra check is made to ensure - the post to the queue was successful if then attempting immediately - retrieve the posted character. - + Changed the name of the constant portTICKS_PER_MS to portTICK_PERIOD_MS - as the old name was misleading. - - -Changes between V2.4.2 and V2.5.0 - Released Aug 12, 2004 - - The RTOS source code download now includes three separate memory allocation - schemes - so you can choose the most appropriate for your application. - These are found in the Source/Portable/MemMang directory. The demo - application projects have also been updated to demonstrate the new schemes. - See the "Memory Management" page of the API documentation for more details. - - + Added heap_1.c, heap_2.c and heap_3.c in the Source/Portable/MemMang - directory. - + Replaced the portheap.c files for each demo application with one of the - new memory allocation files. - + Updated the portmacro.h file for each demo application to include the - constants required for the new memory allocators: portTOTAL_HEAP_SIZE and - portBYTE_ALIGNMENT. - + Added a new test to the ARM7 demo application that tests the operation - of the heap_2 memory allocator. - - -Changes between V2.4.1 and V2.4.2 - Released July 14, 2004 - - + The ARM7 port now supports THUMB mode. - + Modification to the ARM7 demo application serial port driver. - -Changes between V2.4.0 and V2.4.1 - Released July 2, 2004 - - + Rationalised the ARM7 port version of portEXIT_CRITICAL() - - improvements provided by Bill Knight. - + Made demo serial driver more complete and robust. - - -Changes between V2.4.0 and V2.3.1 - Released June 30, 2004 - - + Added the first ARM7 port - thanks to Bill Knight for the assistance - provided. - + Added extra files to the Demo/Common/Minimal directory. These are - equivalent to their Demo/Common/Full counterparts but with the - calls to the functions defined in print.c removed. - + Added TABLAT to the list of registers saved as part of a PIC18 context. - -Changes between V2.3.0 and V2.3.1 - Released June 25, 2004 - - + Changed the way the vector table is defined to be more portable. - + Corrected the definitions of SPH and SPL in portmacro.s90. - The previous definitions prevented V2.3.0 operating if the iom323.h - header file was included in portmacro.s90. - -Changes between V2.2.0 and V2.3.0 - Released June 19, 2004 - - + Added an AVR port that uses the IAR compiler. - + Explicit use of 'signed' qualifier on plain char types. - + Modified the Open Watcom project files to use 'signed' as the - default char type. - + Changed odd calculation of initial pxTopOfStack value when - portSTACK_GROWTH < 0. - + Added inline qualifier to context switch functions within task.c. - Ports that do not support the (non ANSI) inline keyword have the - inline #define'd away in their respective portmacro.h files. - -Changes between V2.1.1 and V2.2.0 - Released May 18, 2004 - - + Added Cygnal 8051 port. - + PCLATU and PCLATH are now saved as part of the PIC18 context. This - allows function pointers to be used within tasks. Thanks to Javier - Espeche for the enhancement. - + Minor changes to demo application files to reduce stack usage. - + Minor changes to prevent compiler warnings when compiling the new port. - -Changes between V2.1.0 and V2.1.1 - Released March 12, 2004 - - + Bug fix - pxCurrentTCB is now initialised before the call to - prvInitialiseTaskLists(). Previously pxCurrentTCB could be accessed - while null during the initialisation sequence. Thanks to Giuseppe - Franco for the correction. - -Changes between V2.0.0 and V2.1.0 - Released Feb 29, 2004 - - V2.1.0 has significant reworks that greatly reduce the amount of time - the kernel has interrupts disabled. The first section of modifications - listed here must be taken into account by users. The second section - are related to the kernel implementation and as such are transparent. - - Section1 : - - + The typedef TickType_t has been introduced. All delay times should - now use a variable of type TickType_t in place of the unsigned long's - used previously. API function prototypes have been updated - appropriately. - + The configuration macro USE_16_BIT_TICKS has been introduced. If set - to 1 TickType_t is defined as an unsigned short. If set to 0 - TickType_t is defined as an unsigned long. See the configuration - section of the API documentation for more details. - + The configuration macro INCLUDE_vTaskSuspendAll is now obsolete. - + vTaskResumeAll() has been renamed cTaskResumeAll() as it now returns a - value (see the API documentation). - + ulTaskGetTickCount() has been renamed xTaskGetTickCount() as the type - it returns now depends on the USE_16_BIT_TICKS definition. - + cQueueReceive() must now >never< be used from within an ISR. Use the new - cQueueReceiveFromISR() function instead. - - Section 2: - - + A mechanism has been introduced that allows a queue to be accessed by - a task and ISR simultaneously. - + A "pending ready" queue has been introduced that enables interrupts to - be processed when the scheduler is suspended. - + The list implementation has been improved to provide faster item - removal. - + The scheduler now makes use of the scheduler suspend mechanism in places - where previously interrupts were disabled. - -Changes between V1.2.6 and V2.0.0 - Released Jan 31, 2004 - - + Introduced new API functions: - vTaskPriorityGet () - vTaskPrioritySet () - vTaskSuspend () - vTaskResume () - vTaskSuspendAll () - vTaskResumeAll () - + Added conditional compilation options that allow the components of the - kernel that are unused by an application to be excluded from the build. - See the Configuration section on the WEB site for more information (on - the API pages). The macros have been added to each portmacro.h file ( - sometimes called prtmacro.h). - + Rearranged tasks.c. - + Added demo application file dynamic.c. - + Updated the PC demo application to make use of dynamic.c. - + Updated the documentation contained in the kernel header files. - + Creating a task now causes a context switch if the task being created - has a higher priority than the calling task - assuming the kernel is - running. - + vTaskDelete() now only causes a context switch if the calling task is - the task being deleted. - -Changes between V1.2.5 and V1.2.6 - Released December 31, 2003 - - Barring the change to the interrupt vector (PIC port) these are minor - enhancements. - - + The interrupt vector used for the PIC master ISR has been changed from - 0x18 to 0x08 - where it should have always been. The incorrect address - still works but probably executes a number of NOP's before getting to the - ISR. - + Changed the baud rate used by the AVR demo application to 38400. This - has an error percentage of less than one percent with an 8MHz clock. - + Raised the priority of the Rx task in demo\full\comtest.c. This only - affects the Flashlite and PC ports. This was done to prevent the Rx - buffer becoming full. - + Reverted the Flashlite COM port driver back so it does not use the DMA. - The DMA appears to miss characters under stress. The Borland Flashlite - port was also calculating a register value incorrectly resulting in the - wrong DMA source address being used. The same code worked fine when - compiling with Open Watcom. Other minor enhancements were made to the - interrupt handling. - + Modified the PIC serial Rx ISR to check for and clear overrun errors. - Overrun errors seem to prevent any further characters being received. - + The PIC demo projects now have some optimisation switched on. - - -Changes between V1.2.4 and V1.2.5 - - Small fix made to the PIC specific port.c file described below. - - + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global - interrupt flag setting. Using the two bits defined within - portINITAL_INTERRUPT_STATE was causing the w register to get clobbered - before the test was performed. - -Changes between V1.2.3 and V1.2.4 - - V1.2.4 contains a release version of the PIC18 port. - An optional exception has been included with the GPL. See the licensing - section of www.FreeRTOS.org for details. - - + The function xPortInitMinimal() has been renamed to - xSerialPortInitMinimal() and the function xPortInit() has been renamed - to xSerialPortInit(). - + The function sSerialPutChar() has been renamed cSerialPutChar() and - the function return type chaned to portCHAR. - + The integer and flop tasks now include calls to tskYIELD(), allowing - them to be used with the cooperative scheduler. - + All the demo applications now use the integer and comtest tasks when the - cooperative scheduler is being used. Previously they were only used with - the preemptive scheduler. - + Minor changes made to operation of minimal versions of comtest.c and - integer.c. - + The ATMega port definition of portCPU_CLOSK_HZ definition changed to - 8MHz base 10, previously it base 16. - - - -Changes between V1.2.2a and V1.2.3 - - The only change of any significance is to the license, which has changed - from the Open Software License to the GNU GPL. - - The zip file also contains a pre-release version of the PIC18 port. This - has not yet completed testing and as such does not constitute part of the - V1.2.3 release. It is still however covered by the GNU GPL. - - There are minor source code changes to accommodate the PIC C compiler. - These mainly involve more explicit casting. - - + sTaskCreate() has been modified slightly to make use of the - portSTACK_GROWTH macro. This is required for the PIC port where the - stack grows in the opposite direction to the other existing ports. - + prvCheckTasksWaitingTermination() has been modified slightly to bring - the decrementing of usCurrentNumberOfTasks within the critical section, - where it should have been since the creation of an eight bit port. - -Changes between V1.2.2 and V1.2.2a - - The makefile and buildcoff.bat files included with the AVR demo application - have been modified for use with the September 2003 build of WinAVR. No - source files have changed. - -Changes between V1.2.1 and V1.2.2 - - There are only minor changes here to allow the PC and Flashlite 186 ports - to use the Borland V4.52 compiler, as supplied with the Flashlite 186 - development kit. - - + Introduced a BCC directory under source\portable. This contains all the - files specific to the Borland compiler port. - + Corrected the macro naming of portMS_PER_TICK to portTICKS_PER_MS. - + Modified comtest.c to increase the rate at which the string is - transmitted and received on the serial port. The Flashlite 186 demo - app baud rate has also been increased. - + The values of the constants used in both integer.c files have been - increased to force the Borland compiler to use 32 bit values. The - Borland optimiser placed the previous values in 16 bit registers, and in - So doing invalidated the test. - -Changes between V1.2.0 and V1.2.1 - - This version includes some minor changes to the list implementation aimed - at improving the context switch time - with is now approximately 10% faster. - Changes include the removal of some null pointer assignment checks. These - were redundant where the scheduler uses the list functions, but means any - user application choosing to use the same list functions must now check - that no NULL pointers are passed as a parameter. - - The Flashlite 186 serial port driver has also been modified to use a DMA - channel for transmissions. The serial driver is fully functional but still - under development. Flashlite users may prefer to use V1.2.0 for now. - - Details: - - + Changed the baud rate for the ATMega323 serial test from 19200 to 57600. - + Use vSerialPutString() instead of single character puts in - Demo\Full\Comtest.c. This allows the use of the flashlite DMA serial - driver. Also the check variable only stops incrementing after two - consecutive failures. - + semtest.c creates four tasks, two of which operate at the idle priority. - The tasks that operate at the idle priority now use a lower expected - count than those running at a higher priority. This prevents the low - priority tasks from signalling an error because they have not been - scheduled enough time for each of them to count the shared variable to - the higher original value. - + The flashlite 186 serial driver now uses a DMA channel for transmissions. - + Removed the volatile modifier from the list function parameters. This was - only ever included to prevent compiler warnings. Now warnings are - removed by casting parameters where the calls are made. - + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been - removed from list.c and added as macros in list.h. - + usNumberOfItems has been added to the list structure. This removes the - need for a pointer comparison when checking if a list is empty, and so - is slightly faster. - + Removed the NULL check in vListRemove(). This makes the call faster but - necessitates any application code utilising the list implementation to - ensure NULL pointers are not passed. - + Renamed portTICKS_PER_MS definition to portMS_PER_TICK (milli seconds - per tick). This is what it always should have been. - -Changes between V1.01 and V1.2.0 - - The majority of these changes were made to accommodate the 8bit AVR port. - The scheduler workings have not changed, but some of the data types used - have been made more friendly to an eight bit environment. - - Details: - - + Changed the version numbering format. - + Added AVR port. - + Split the directory demo\common into demo\common\minimal and - demo\common\full. The files in the full directory are for systems with - a display (currently PC and Flashlite 186 demo's). The files in the - minimal directory are for systems with limited RAM and no display - (currently MegaAVR). - + Minor changes to demo application function prototypes to make more use - of 8bit data types. - + Within the scheduler itself the following functions have slightly - modified declarations to make use of 8bit data types where possible: - xQueueCreate(), - sQueueReceive(), - sQUeueReceive(), - usQueueMessageWaiting(), - sQueueSendFromISR(), - sSemaphoreTake(), - sSemaphoreGive(), - sSemaphoreGiveFromISR(), - sTaskCreate(), - sTaskMoveFromEventList(). - - Where the return type has changed the function name has also changed in - accordance with the naming convention. For example - usQueueMessageWaiting() has become ucQueueMessageWaiting(). - + The definition tskMAX_PRIORITIES has been moved from task.h to - portmacro.h and renamed portMAX_PRIORITIES. This allows different - ports to allocate a different maximum number of priorities. - + By default the trace facility is off, previously USE_TRACE_FACILITY - was defined. - + comtest.c now uses a psuedo random delay between sends. This allows for - better testing as the interrupts do not arrive at regular intervals. - + Minor change to the Flashlite serial port driver. The driver is written - to demonstrate the scheduler and is not written to be efficient. - - - -Changes between V1.00 and V1.01 - - These changes improve the ports. The scheduler itself has not changed. - - Improved context switch mechanism used when performing a context - switch from an ISR (both the tick ISR and the serial comms ISR's within - the demo application). The new mechanism is faster and uses less stack. - - The assembler file portasm.asm has been replaced by a header file - portasm.h. This includes a few assembler macro definitions. - - All saving and restoring of registers onto/off of the stack is now handled - by the compiler. This means the initial stack setup for a task has to - mimic the stack used by the compiler, which is different for debug and - release builds. - - Slightly changed the operation of the demo application, details below. - - Details: - - + portSWITCH_CONTEXT() replaced by vPortFirstContext(). - + pxPortInitialiseStack() modified to replicate the stack used by the - compiler. - + portasm.asm file removed. - + portasm.h introduced. This contains macro definitions for - portSWITCH_CONTEXT() and portFIRST_CONTEXT(). - + Context switch from ISR now uses the compiler generated interrupt - mechanism. This is done simply by calling portSWITCH_CONTEXT and leaving - the save/restore to compiler generated code. - + Calls to taskYIELD() during ISR's have been replaced by calling the - simpler and faster portSWITCH_CONTEXT(). - + The Flashlite 186 port now uses 186 instruction set (used to use 80x86 - instructions only). - + The blocking queue tasks within the demo application did not operate - quite as described. This has been corrected. - + The priority of the comtest Rx task within the demo application has been - lowered. Received characters are now processed (read from the queue) at - the idle priority, allowing low priority tasks to run evenly at times of - a high communications overhead. - + Prevent the call to kbhit() in main.c for debug builds as the debugger - seems to have problems stepping over the call. This if for the PC port - only. - - - +Documentation and download available at https://www.FreeRTOS.org/ + +Changes between FreeRTOS V10.5.0 and FreeRTOS V10.5.1 released November 16 2022 + + + Updating the version in the manifest.yml file to be accurate. + +Changes between FreeRTOS V10.4.6 and FreeRTOS V10.5.0 released September 16 2022 + + + ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that + already independently gained the ability to execute injected code to + read from or write to arbitrary addresses by passing a negative argument + as the xIndex parameter to pvTaskGetThreadLocalStoragePointer() or + vTaskSetThreadLocalStoragePointer respectively. A check has been added to + ensure that passing a negative argument as the xIndex parameter does not + cause arbitrary read or write. + We thank Certibit Consulting, LLC for reporting this issue. + + ARMv7-M and ARMv8-M MPU ports: It was possible for an unprivileged task + to invoke any function with privilege by passing it as a parameter to + MPU_xTaskCreate, MPU_xTaskCreateStatic, MPU_xTimerCreate, + MPU_xTimerCreateStatic, or MPU_xTimerPendFunctionCall. MPU_xTaskCreate + and MPU_xTaskCreateStatic have been updated to only allow creation of + unprivileged tasks. MPU_xTimerCreate, MPU_xTimerCreateStatic and + MPU_xTimerPendFunctionCall APIs have been removed. + We thank Huazhong University of Science and Technology for reporting + this issue. + + ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that + already independently gained the ability to execute injected code to + achieve further privilege escalation by branching directly inside a + FreeRTOS MPU API wrapper function with a manually crafted stack frame. + The local stack variable `xRunningPrivileged` has been removed so that + a manually crafted stack frame cannot be used for privilege escalation + by branching directly inside a FreeRTOS MPU API wrapper. + We thank Certibit Consulting, LLC, Huazhong University of Science and + Technology and the SecLab team at Northeastern University for reporting + this issue. + + ARMv7-M MPU ports: It was possible to configure overlapping memory + protection unit (MPU) regions such that an unprivileged task could access + privileged data. The kernel now uses highest numbered MPU regions for + kernel protections to prevent such MPU configurations. + We thank the SecLab team at Northeastern University for reporting this + issue. + + Add support for ARM Cortex-M55. + + Add support for ARM Cortex-M85. Contributed by @gbrtth. + + Add vectored mode interrupt support to the RISC-V port. + + Add support for RV32E extension (Embedded Profile) in RISC-V GCC port. + Contributed by @Limoto. + + Heap improvements: + - Add a check to heap_2 to track if a memory block is allocated to + the application or not. The MSB of the size field is used for this + purpose. The same check already exists in heap_4 and heap_5. This + check prevents double free errors. + - Add a new flag configHEAP_CLEAR_MEMORY_ON_FREE to heap_2, heap_4 + and heap_5. If the flag is set in FreeRTOSConfig.h then memory freed using + vPortFree() is automatically cleared to zero. + - Add a new API pvPortCalloc to heap_2, heap_4 and heap_5 which has the same + signature as the standard library calloc function. + - Update the pointer types to portPOINTER_SIZE_TYPE. Contributed by + @Octaviarius. + + Add the ability to override send and receive completed callbacks for each + instance of a stream buffer or message buffer. Earlier there could be + one send and one receive callback for all instances of stream and message + buffers. Having separate callbacks per instance allows different message + and stream buffers to be used differently - for example, some for inter core + communication and others for same core communication. + The feature can be controlled by setting the configuration option + configUSE_SB_COMPLETED_CALLBACK in FreeRTOSConfig.h. When the option is set to 1, + APIs xStreamBufferCreateWithCallback() or xStreamBufferCreateStaticWithCallback() + (and likewise APIs for message buffer) can be used to create a stream buffer + or message buffer instance with application provided callback overrides. When + the option is set to 0, then the default callbacks as defined by + sbSEND_COMPLETED() and sbRECEIVE_COMPLETED() macros are invoked. To maintain + backwards compatibility, configUSE_SB_COMPLETED_CALLBACK defaults to 0. The + functionality is currently not supported for MPU enabled ports. + + Generalize the FreeRTOS's Thread Local Storage (TLS) support so that it + is not tied to newlib and can be used with other c-runtime libraries also. + The default behavior for newlib support is kept same for backward + compatibility. + + Add support to build and link FreeRTOS using CMake build system. Contributed + by @yhsb2k. + + Add support to generate Software Bill of Materials (SBOM) for every release. + + Add support for 16 MPU regions to the GCC Cortex-M33 ports. + + Add ARM Cortex-M7 r0p0/r0p1 Errata 837070 workaround to ARM CM4 MPU ports. + The application writer needs to define configENABLE_ERRATA_837070_WORKAROUND + when using CM4 MPU ports on a Cortex-M7 r0p0/r0p1 core. + + Add configSYSTICK_CLOCK_HZ to Cortex-M0 ports. This is needed to support + the case when the SysTick timer is not clocked from the same source as the CPU. + + Add hardware stack protection support to MicroBlazeV9 port. This ensures that + the CPU immediately raises Stack Protection Violation exception as soon as any + task violates its stack limits. Contributed by @uecasm. + + Introduce the configUSE_MINI_LIST_ITEM configuration option. When this + option is set to 1, ListItem_t and MiniLitItem_t remain separate types. + However, when configUSE_MINI_LIST_ITEM == 0, MiniLitItem_t and ListItem_t + are both typedefs of the same struct xLIST_ITEM. This addresses some issues + observed when strict-aliasing and link time optimization are enabled. + To maintain backwards compatibility, configUSE_MINI_LIST_ITEM defaults to 1. + + Simplify prvInitialiseNewTask to memset newly allocated TCB structures + to zero, and remove code that set individual structure members to zero. + + Add prototype for prvPortYieldFromISR to the POSIX port so that it builds + without any warning with -Wmissing-prototypes compiler option. + + Add top of stack and end of stack to the task info report obtained using + vTaskGetInfo(). Contributed by @shreyasbharath. + + Add a cap to the cRxLock and cTxLock members of the queue data structure. + These locks count the number items received and sent to the queue while + the queue was locked. These are later used to unblock tasks waiting on + the queue when the queue is unlocked. This PR caps the values of the + cRxLock and cTxLock to the number of tasks in the system because we cannot + unblock more tasks than there are in the system. Note that the same assert + could still be triggered is the application creates more than 127 tasks. + + Changed uxAutoReload parameter in timer functions to xAutoReload. The + type is now BaseType_t. This matches the type of pdTRUE and pdFALSE. + The new function xTimerGetAutoReload() provides the auto-reload state as + a BaseType_t. The legacy function uxTimerGetAutoReload is retained with the + original UBaseType_t return value. + + Fix support for user implementations of tickless idle that call + vTaskStepTick() with xExpectedIdleTime ticks to step. The new code + ensures xTickCount reaches xNextTaskUnblockTime inside xTaskIncrementTick() + instead of inside vTaskStepTick(). This fixes the typical case where a task + wakes up one tick late and a rare case assertion failure when xTickCount\ + rolls over. Contributed by @jefftenney. + + Fix deadlock in event groups when pvPortMalloc and vPortFree functions + are protected with a mutex. Contributed by @clemenskresser. + + Fix a warning in tasks.c when compiled with -Wduplicated-branches + GCC option. Contributed by @pierrenoel-bouteville-act. + + Fix compilation error in tasks.c when configSUPPORT_DYNAMIC_ALLOCATION + is set to zero. Contributed by @rdpoor. + + Fix prvWriteMessageToBuffer() function in stream_buffer.c so that it correctly + copies length on big endian platforms too. + + Remove the need for INCLUDE_vTaskSuspend to be set to 1 + when configUSE_TICKLESS_IDLE is enabled. Contributed by @pramithkv. + + Update the RL78 IAR port to the latest version of IAR which uses the + industry standard ELF format as opposed to earlier UBROF object format. + Contributed by @felipe-iar. + + Add tick type is atomic flag when tick count is 16-bit to PIC24 port. This + allows the PIC24 family of 16 bit processors to read the tick count without + a critical section when the tick count is also 16 bits. + + Fix offset-out-of-range errors for GCC CM3/CM4 mpu ports when + Link Time Optimization is enabled. Contributed by @niniemann. + + Remove #error when RISC-V port is compiled on a 64-bit RISC-V platform. + Contributed by @cmdrf. + + Fix ullPortInterruptNesting alignment in Cortex-A53 port so that it is + 8-byte aligned. This fixes the unaligned access exception. Contributed + by @Atomar25. + + Fix Interrupt Handler Register Function and Exception Process in NiosII + Port. Contributed by @ghost. + + Change FreeRTOS IRQ Handler for Cortex-A53 SRE port to store and restore + interrupt acknowledge register. This ensures that the SRE port behavior + matches the Memory Mapped IO port. Contributed by @sviaunxp. + + Update the uncrustify config file to match the version of the uncrustify + used in the CI Action. Also, pin the version of uncrustify in CI. Contributed + by @swaldhoer. + +Changes between FreeRTOS V10.4.5 and FreeRTOS V10.4.6 released November 12 2021 + + + ARMv7-M and ARMv8-M MPU ports – prevent non-kernel code from calling the + internal functions xPortRaisePrivilege and vPortResetPrivilege by changing + them to macros. + + Introduce a new config configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS which + enables developers to prevent critical sections from unprivileged tasks. + It defaults to 1 for backward compatibility. Application should set it to + 0 to disable critical sections from unprivileged tasks. + +Changes between FreeRTOS V10.4.4 and FreeRTOS V10.4.5 released September 10 2021 + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.5.html + + + Introduce configRUN_TIME_COUNTER_TYPE which enables developers to define + the type used to hold run time statistic counters. Defaults to uint32_t + for backward compatibility. #define configRUN_TIME_COUNTER_TYPE to a type + (for example, uint64_t) in FreeRTOSConfig.h to override the default. + + Introduce ulTaskGetIdleRunTimePercent() to complement the pre-existing + ulTaskGetIdleRunTimeCounter(). Whereas the pre-existing function returns + the raw run time counter value, the new function returns the percentage of + the entire run time consumed by the idle task. Note the amount of idle + time is only a good measure of the slack time in a system if there are no + other tasks executing at the idle priority, tickless idle is not used, and + configIDLE_SHOULD_YIELD is set to 0. + + ARMv8-M secure-side port: Tasks that call secure functions from the + non-secure side of an ARMv8-M MCU (ARM Cortex-M23 and Cortex-M33) have two + contexts - one on the non-secure side and one on the secure-side. Previous + versions of the FreeRTOS ARMv8-M secure-side ports allocated the structures + that reference secure-side contexts at run time. Now the structures are + allocated statically at compile time. The change necessitates the + introduction of the secureconfigMAX_SECURE_CONTEXTS configuration constant, + which sets the number of statically allocated secure contexts. + secureconfigMAX_SECURE_CONTEXTS defaults to 8 if left undefined. + Applications that only use FreeRTOS code on the non-secure side, such as + those running third-party code on the secure side, are not affected by + this change. + +Changes between FreeRTOS V10.4.3 and FreeRTOS V10.4.4 released May 28 2021 + + Minor performance improvements to xTaskIncrementTick() achieved by providing + macro versions of uxListRemove() and vListInsertEnd(). + + Minor refactor of timers.c that obsoletes the need for the + tmrCOMMAND_START_DONT_TRACE macro and removes the need for timers.c to + post to its own event queue. A consequence of this change is that auto- + reload timers that miss their intended next execution time will execute + again immediately rather than executing again the next time the command + queue is processed. (thanks Jeff Tenney). + + Fix a race condition in the message buffer implementation. The + underlying cause was that length and data bytes are written and read as + two distinct operations, which both modify the size of the buffer. If a + context switch occurs after adding or removing the length bytes, but + before adding or removing the data bytes, then another task may observe + the message buffer in an invalid state. + + The xTaskCreate() and xTaskCreateStatic() functions accept a task priority + as an input parameter. The priority has always been silently capped to + (configMAX_PRIORITIES - 1) should it be set to a value above that priority. + Now values above that priority will also trigger a configASSERT() failure. + + Replace configASSERT( pcQueueName ) in vQueueAddToRegistry with a NULL + pointer check. + + Introduce the configSTACK_ALLOCATION_FROM_SEPARATE_HEAP configuration + constant that enables the stack allocated to tasks to come from a heap other + than the heap used by other memory allocations. This enables stacks to be + placed within special regions, such as fast tightly coupled memory. + + If there is an attempt to add the same queue or semaphore handle to the + queue registry more than once then prior versions would create two separate + entries. Now if this is done the first entry is overwritten rather than + duplicated. + + Update the ESP32 port and TF-M (Trusted Firmware M)code to the latest from + their respective repositories. + + Correct a build error in the POSIX port. + + Additional minor formatting updates, including replacing tabs with spaces + in more files. + + Other minor updates include adding additional configASSERT() checks and + correcting and improving code comments. + + Go look at the smp branch to see the progress towards the Symetric + Multiprocessing Kernel. https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/smp + +Changes between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020 + + V10.4.3 is included in the 202012.00 LTS release. Learn more at https:/freertos.org/lts-libraries.html + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html + + + Changes to improve robustness and consistency for buffer allocation in + the heap, queue and stream buffer. + + The following functions can no longer be called from unprivileged code. + - xTaskCreateRestricted + - xTaskCreateRestrictedStatic + - vTaskAllocateMPURegions + + +Changes between FreeRTOS V10.4.1 and FreeRTOS V10.4.2 released November 10 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html + + + Fix an issue in the ARMv8-M ports that caused BASEPRI to be masked + between the first task starting to execute and that task making + a FreeRTOS API call. + + Introduced xTaskDelayUntil(), which is functionally equivalent to + vTaskDelayUntil(), with the addition of returning a value to + indicating whether or not the function placed the calling task into + the Blocked state or not. + + Update WolfSSL to 4.5.0 and add the FIPS ready demo. + + Add support for ESP IDF 4.2 to ThirdParty Xtensa port. + + Re-introduce uxTopUsedPriority to support OpenOCD debugging. + + Convert most dependent libraries in FreeRTOS/FreeRTOS to submodules. + + Various general maintenance and improvements to MISRA compliance. + + +Changes between FreeRTOS V10.4.0 and FreeRTOS V10.4.1 released September 17 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html + + + Fixed an incorrectly named parameter that prevented the + ulTaskNotifyTakeIndexed macro compiling, and the name space clash in the + test code that prevented this error causing test failures. + + +Changes between FreeRTOS V10.3.1 and FreeRTOS V10.4.0 released September 10 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html + + Major enhancements: + + + Task notifications: Prior to FreeRTOS V10.4.0 each created task had a + single direct to task notification. From FreeRTOS V10.4.0 each task has + an array of notifications. The direct to task notification API has been + extended with API functions postfixed with "Indexed" to enable the API to + operate on a task notification at any array index. See + https://www.freertos.org/RTOS-task-notifications.html for more information. + + Kernel ports that support memory protection units (MPUs): The ARMv7-M and + ARMv8-M MPU ports now support a privilege access only heap. The ARMv7-M + MPU ports now support devices that have 16 MPU regions, have the ability + to override default memory attributes for privileged code and data + regions, and have the ability to place the FreeRTOS kernel code outside of + the Flash memory. The ARMv8-M MPU ports now support tickless idle mode. + See https://www.freertos.org/FreeRTOS-MPU-memory-protection-unit.html + for more information. + + Additional noteworthy updates: + + + Code formatting is now automated to facilitate the increase in + collaborative development in Git. The auto-formated code is not identical + to the original formatting conventions. Most notably spaces are now used + in place of tabs. + + The prototypes for callback functions (those that start with "Application", + such as vApplicationStackOverflowHook()) are now in the FreeRTOS header + files, removing the need for application writers to add prototypes into + the C files in which they define the functions. + + New Renesas RXv3 port layer. + + Updates to the Synopsys ARC code, including support for EM and HS cores, + and updated BSP. + + Added new POSIX port layer that allows FreeRTOS to run on Linux hosts in + the same way the Windows port layer enables FreeRTOS to run on Windows + hosts. + + Many other minor optimisations and enhancements. For full details + see https://github.com/FreeRTOS/FreeRTOS-Kernel/commits/main + + +Changes between FreeRTOS V10.3.0 and FreeRTOS V10.3.1 released February 18 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html + + + ./FreeRTOS-Labs directory was removed from this file. The libraries it + contained are now available as a separate download. + +Changes between FreeRTOS V10.2.1 and FreeRTOS V10.3.0 released February 7 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html + + New and updated kernel ports: + + + Added RISC-V port for the IAR compiler. + + Update the Windows simulator port to use a synchronous object to prevent + a user reported error whereby a task continues to run for a short time + after being moved to the Blocked state. Note we were not able to + replicate the reported issue and it likely depends on your CPU model. + + Correct alignment of stack top in RISC-V port when + configISR_STACK_SIZE_WORDS is defined to a non zero value, which causes + the interrupt stack to be statically allocated. + + The RISC-V machine timer compare register can now be for any HART, whereas + previously it was always assumed FreeRTOS was running on HART 0. + + Update the sequence used to update the 64-bit machine timer + compare register on 32-bit cores to match that suggested in RISC-V + documentation. + + Added tickless low power modes into the ARM, IAR and GCC Cortex-M0 compiler + ports. + + Updated the behaviour of the ARMv7-M MPU (Memory Protection Unit) ports to + match that of the ARMv8-M ports whereby privilege escalations can only + originate from within the kernel's own memory segment. Added + configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY configuration constant. + + Update existing MPU ports to correctly disable the MPU before it is + updated. + + Added contributed port and demo application for a T-Head (formally C-SKY) + microcontroller. + + New API functions: + + + Added the vPortGetHeapStats() API function which returns information on + the heap_4 and heap_5 state. + + Added xTaskCatchUpTicks(), which corrects the tick count value after the + application code has held interrupts disabled for an extended period. + + Added xTaskNotifyValueClear() API function. + + Added uxTimerGetReloadMode() API function. + + Other miscellaneous changes: + + Change type of uxPendedTicks from UBaseType_t to TickType_t to ensure it + has the same type as variables with which it is compared to, and therefore + also renamed the variable xPendingTicks. + + Update Keil projects that use the MPU so memory regions come from linker + script (scatter file) variables instead of being hard coded. + + Added LPC51U68 Cortex-M0+ demos for GCC (MCUXpresso), Keil and IAR + compilers. + + Added CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube demo. + + Added LPC54018 MPU demo. + + Rename xTaskGetIdleRunTimeCounter() to ulTaskGetIdleRunTimeCounter(). + + +Changes between FreeRTOS V10.2.1 and FreeRTOS V10.2.0 released May 13 2019: + + + Added ARM Cortex-M23 port layer to complement the pre-existing ARM + Cortex-M33 port layer. + + The RISC-V port now automatically switches between 32-bit and 64-bit + cores. + + Introduced the portMEMORY_BARRIER macro to prevent instruction re-ordering + when GCC link time optimisation is used. + + Introduced the portDONT_DISCARD macro to the ARMv8-M ports to try and + prevent the secure side builds from removing symbols required by the + non secure side build. + + Introduced the portARCH_NAME to provide additional data to select semi- + automated build environments. + + Cortex-M33 and Cortex-M23 ports now correctly disable the MPU before + updating the MPU registers. + + + Added Nuvoton NuMaker-PFM-M2351 ARM Cortex-M23 demo. + + Added LPC55S69 ARM Cortex-M33 demo. + + Added an STM32 dual core AMP stress test demo. + + +Changes between FreeRTOS V10.1.1 and FreeRTOS V10.2.0 released February 25 2019: + + + Added GCC RISC-V MCU port with three separate demo applications. + + Included pre-existing ARM Cortex-M33 (ARMv8-M) GCC/ARMclang and IAR ports + with Keil simulator demo. + + Update the method used to detect if a timer is active. Previously the + timer was deemed to be inactive if it was not referenced from a list. + However, when a timer is updated it is temporarily removed from, then + re-added to a list, so now the timer's active status is stored separately. + + Add vTimerSetReloadMode(), xTaskGetIdleRunTimeCounter(), and + xTaskGetApplicationTaskTagFromISR() API functions. + + Updated third party Xtensa port so it is MIT licensed. + + Added configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H to the Renesas + compiler RX600v2 port to enable switching between platform.h and + iodefine.h includes within that port's port.c file. + + Removed the 'FromISR' functions from the MPU ports as ISRs run privileged + anyway. + + Added uxTaskGetStackHighWaterMark2() function to enable the return type to + be changed without breaking backward compatibility. + uxTaskGetStackHighWaterMark() returns a UBaseType_t as always, + uxTaskGetStackHighWaterMark2() returns configSTACK_DEPTH_TYPE to allow the + user to determine the return type. + + Fixed issues in memory protected ports related to different combinations + of static memory only and dynamic memory only builds. As a result the + definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE became more + complex and was moved to FreeRTOS.h with a table explaining its definition. + + Added a 'get task tag from ISR' function. + + Change the method used to determine if a timer is active or not from just + seeing if it is referenced from the active timer list to storing its + active state explicitly. The change prevents the timer reporting that it + is inactive while it is being moved from one list to another. + + The pcName parameter passed into the task create functions can be NULL, + previously a name had to be provided. + + When using tickless idle, prvResetNextTaskUnblockTime() is now only called + in xTaskRemoveFromEventList() if the scheduler is not suspended. + + Introduced portHAS_STACK_OVERFLOW_CHECKING, which should be set to 1 for + FreeRTOS ports that run on architectures that have stack limit registers. + + +Changes between FreeRTOS V10.1.0 and FreeRTOS V10.1.1 released 7 September 2018 + + + Reverted a few structure name changes that broke several kernel aware + debugger plug-ins. + + Updated to the latest trace recorder code. + + Fixed some formatting in the FreeRTOS+TCP TCP/IP stack code. + + Reverted moving some variables from file to function scope as doing so + broke debug scenarios that require the static qualifier to be removed. + +Changes between FreeRTOS V10.0.1 and FreeRTOS V10.1.0 released 22 August 2018 + + FreeRTOS Kernel Changes: + + + Update lint checked MISRA compliance to use the latest MISRA standard, was + previously using the original MISRA standard. + + Updated all object handles (TaskHandle_t, QueueHandle_t, etc.) to be + unique types instead of void pointers, improving type safety. (this was + attempted some years back but had to be backed out due to bugs in some + debuggers). Note this required the pvContainer member of a ListItem_t + struct to be renamed - set configENABLE_BACKWARD_COMPATIBILITY to 1 if + this causes an issue. + + Added configUSE_POSIX_ERRNO to enable per task POSIX style errno + functionality in a more user friendly way - previously the generic thread + local storage feature was used for this purpose. + + Added Xtensa port and demo application for the XCC compiler. + + Changed the implementation of vPortEndScheduler() for the Win32 port to + simply call exit( 0 ). + + Bug fix in vPortEnableInterrupt() for the GCC Microblaze port to protect + the read modify write access to an internal Microblaze register. + + Fix minor niggles when the MPU is used with regards to prototype + differences, static struct size differences, etc. + + The usStackHighWaterMark member of the TaskStatus_t structure now has type + configSTACK_DEPTH_TYPE in place of uint16_t - that change should have been + made when the configSTACK_DEPTH_TYPE type (which gets around the previous + 16-bit limit on stack size specifications) was introduced. + + Added the xMessageBufferNextLengthBytes() API function and likewise stream + buffer equivalent. + + Introduce configMESSAGE_BUFFER_LENGTH_TYPE to allow the number of bytes + used to hold the length of a message in the message buffer to be reduced. + configMESSAGE_BUFFER_LENGTH_TYPE default to size_t, but if, for example, + messages can never be more than 255 bytes it could be set to uint8_t, + saving 3 bytes each time a message is written into the message buffer + (assuming sizeof( size_t ) is 4). + + Updated the StaticTimer_t structure to ensure it matches the size of the + Timer_t structure when the size of TaskFunction_t does not equal the size + of void *. + + Update various Xilinx demos to use 2018.1 version of the SDK tools. + + Various updates to demo tasks to maintain test coverage. + + FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by + FreeRTOS+TCP, which was brought into the main download in FreeRTOS + V10.0.0. FreeRTOS+TCP can be configured as a UDP only stack, and + FreeRTOS+UDP does not contain the patches applied to FreeRTOS+TCP. + + FreeRTOS+TCP Changes: + + + Multiple security improvements and fixes in packet parsing routines, DNS + caching, and TCP sequence number and ID generation. + + Disable NBNS and LLMNR by default. + + Add TCP hang protection by default. + + We thank Ori Karliner of Zimperium zLabs Team for reporting these issues. + + +Changes between FreeRTOS V10.0.0 and FreeRTOS V10.0.1, released December 20 2017 + + + Fix position of "#if defined( __cplusplus )" in stream_buffer.h. + + Correct declarations of MPU_xQueuePeek() and MPU_xQueueSemaphoreTake() in + mpu_prototypes.h. + + Correct formatting in vTaskList() helper function when it prints the state + of the currently executing task. + + Introduce #error if stream_buffer.c is built without + configUSE_TASK_NOTIFICATIONS set to 1. + + Update FreeRTOS+TCP to V2.0.0 + - Improve the formatting of text that displays the available netword + interfaces when FreeRTOS+TCP is used on Windows with WinPCap. + - Introduce ipconfigSOCKET_HAS_USER_WAKE_CALLBACK option to enable a user + definable callback to execute when data arrives on a socket. + +Changes between FreeRTOS V9.0.1 and FreeRTOS V10.0.0: + + The FreeRTOS kernel is now MIT licensed: https://www.FreeRTOS.org/license + + New Features and components: + + + Stream Buffers - see https://www.FreeRTOS.org/RTOS-stream-buffer-example.html + + Message Buffers - see https://www.FreeRTOS.org//RTOS-message-buffer-example.html + + Move FreeRTOS+TCP into the main repository, along with the basic Win32 + TCP demo FreeRTOS_Plus_TCP_Minimal_Windows_Simulator. + + New ports or demos: + + + Added demo for TI SimpleLink CC3220 MCU. + + Added MPU and non MPU projects for Microchip CEC and MEC 17xx and 51xx + MCUs. + + Added CORTEX_MPU_Static_Simulator_Keil_GCC demo to test static allocation + in the MPU port. + + Fixes or enhancements: + + + Cortex-M ports push additional register prior to calling + vTaskSwitchContext to ensure 8-byte alignment is maintained. Only + important if a user defined tick hook function performs an operation that + requires 8-byte alignment. + + Optimisations to the implementation of the standard tickless idle mode on + Cortex-M devices. + + Improvements to the Win32 port including using higher priority threads. + + Ensure interrupt stack alignment on PIC32 ports. + + Updated GCC TriCore port to build with later compiler versions. + + Update mpu_wrappers.c to support static allocation. + + The uxNumberOfItems member of List_t is now volatile - solving an issue + when the IAR compiler was used with maximum optimization. + + Introduced configRECORD_STACK_HIGH_ADDRESS. When set to 1 the stack start + address is saved into each task's TCB (assuming stack grows down). + + Introduced configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H to allow user defined + functionality, and user defined initialisation, to be added to FreeRTOS's + tasks.c source file. When configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H is + set to 1 a user provided header file called freertos_task_c_additions.h + will be included at the bottom of tasks.c. Functions defined in that + header file can call freertos_tasks_c_additions_init(), which in turn + calls a macro called FREERTOS_TASKS_C_ADDITIONS_INIT(), if it is defined. + FREERTOS_TASKS_C_ADDITIONS_INIT() can be defined in FreeRTOSConfig.h. + + Introduced configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) which can be + defined by a user in FreeRTOSConfig.h. The macro is called before + assessing whether to enter tickless idle mode or not. If the macro sets + x to zero then tickless idle mode will not be entered. This allows users + to abort tickless idle mode entry before the tickless idle function is + even called - previously it was only possible to abort from within the + tickless idle function itself. + + Added configPRINTF(), which can be defined by users to allow all libraries + to use the same print formatter. + + Introduced configMAX() and configMIN() macros which default to standard + max( x, y ) and min( x, y ) macro behaviour, but can be overridden if the + application writer defines the same macros in FreeRTOSConfig.h. + + Corrected the definition of StaticTask_t in the case where + INCLUDE_xTaskAbortDelay is set to 1. + + Introduced configTIMER_SERVICE_TASK_NAME and configIDLE_TASK_NAME, both of + which can be defined to strings in FreeRTOSConfig.h to change the default + names of the timer service and idle tasks respectively. + + Only fill the stack of a newly created task with a known value if stack + checking, or high water mark checking/viewing, is in use - removing the + dependency on memset() in other cases. + + Introduced xTaskCreateRestrictedStatic() so static allocation can be used + with the MPU. + + Ensure suspended tasks cannot be unsuspended by a received task + notification. + + Fix race condition in vTaskSetTimeOutState(). + + Updated trace recorder files to the latest version. + +Changes since FreeRTOS V9.0.0: + + + Priority dis-inheritance behaviour has been enhanced in the case where a + task that attempted to take a mutex that was held by a lower priority task + timed out before it was able to obtain the mutex (causing the task that + holds the mutex to have its priority raised, then lowered again, in + accordance with the priority inheritance protocol). + + Split the overloaded xQueueGenericReceive() function into three separate + dedicated functions. + + Allow the default human readable text names given to the Idle and Timer + tasks to be overridden by defining the configIDLE_TASK_NAME and + configTIMER_SERVICE_TASK_NAME definitions respectively in FreeRTOSConfig.h. + + Introduced configINITIAL_TICK_COUNT to allow the tick count to take a + value of than than 0 when the system boots. This can be useful for + testing purposes - although setting configUSE_16_BIT_TICKS to 1 can also + be used to test frequent tick overflows. + + Ensure the Cortex-M SysTick count is cleared to zero before starting the + first task. + + Add configASSERT() into ARM Cortex-M ports to check the number of priority + bit settings. + + Clear the 'control' register before starting ARM Cortex-M4F ports in case + the FPU is used before the scheduler is started. This just saves a few + bytes on the main stack as it prevents space being left for a later save + of FPU registers. + + Added xSemaphoreGetMutexHolderFromISR(). + + Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports. + + Introduced configSTACK_DEPTH_TYPE to allow users to change the type used + to specify the stack size when using xTaskCreate(). For historic reasons, + when FreeRTOS was only used on small MCUs, the type was set to uint16_t, + but that can be too restrictive when FreeRTOS is used on larger + processors. configSTACK_DEPTH_TYPE defaults to uint16_t. + xTaskCreateStatic(), being a newer function, used a uint32_t. + + Increase the priority of the Windows threads used by the Win32 port. As + all the threads run on the same core, and the threads run with very high + priority, there is a risk that the host will become unresponsive, so also + prevent the Windows port executing on single core hosts. + +Changes between FreeRTOS V9.0.0 and FreeRTOS V9.0.0rc2 released May 25 2016: + + See https://www.FreeRTOS.org/FreeRTOS-V9.html + + RTOS kernel updates: + + + The prototype of the new xTaskCreateStatic() API function was modified to + remove a parameter and improve compatibility with other new + "CreateStatic()" API functions. The stack size parameter in + xTaskCreateStatic() is now uint32_t, which changes the prototype of the + callback functions. See the following URL: + https://www.FreeRTOS.org/xTaskCreateStatic.html + + GCC ARM Cortex-A port: Introduced the configUSE_TASK_FPU_SUPPORT + constant. When configUSE_TASK_FPU_SUPPORT is set to 2 every task is + automatically given a floating point (FPU) context. + + GCC ARM Cortex-A port: It is now possible to automatically save and + restore all floating point (FPU) registers on entry to each potentially + nested interrupt by defining vApplicationFPUSafeIRQHandler() instead of + vApplicationIRQHandler(). + + All ARM Cortex-M3/4F/7 ports: Clear the least significant bit of the task + entry address placed onto the stack of a task when the task is created for + strict compliance with the ARM Cortex-M3/4/7 architecture documentation + (no noticeable effect unless using the QMEU emulator). + + Added GCC and Keil ARM Cortex-M4F MPU ports - previously the MPU was only + supported on ARM Cortex-M3. + + ARM Cortex-M3/4F MPU ports: Update to fully support the FreeRTOS V9.0.0 + API (other than static object creation) and added the + FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC demo application to + demonstrate how to use the updated MPU port. + + All ARM Cortex-M3/4F/7 ports: Add additional barrier instructions to the + default low power tickless implementation. + + All ARM Cortex-M0 ports: Prevent an item being left on the stack of the + first task that executes. + + Win32 ports: Reduce the amount of stack used and change the way Windows + threads are deleted to increase the maximum execution time. + + Add an ARM Cortex-M4F port for the MikroC compiler. Ensure to read the + documentation page for this port before use. + + MPS430X IAR port: Update to be compatible with the latest EW430 tools + release. + + IAR32 GCC port: Correct vPortExitCritical() when + configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY. + + For consistency vTaskGetTaskInfo() now has the alias vTaskGetInfo(), + xTaskGetTaskHandle() now has the alias xTaskGetHandle() and + pcQueueGetQueueName() now has an alias pcQueueGetName(). + + Fix various errors in comments and compiler warnings. + + Demo application updates: + + + Update Atmel Studio projects to use Atmel Studio 7. + + Update Xilinx SDK projects to use the 2016.1 version of the SDK. + + Remove dependency on legacy IO libraries from the PIC32 demos. + + Move the Xilinx UltraScale Cortex-R5 demo into the main distribution. + + Update the MSP432 libraries to the latest version. + + Add Microchip CEC1302 (ARM Cortex-M4F) demos for GCC, Keil and MikroC + compilers. + + Move the Atmel SAMA5D2 demo into the main distribution. + +Changes between FreeRTOS V9.0.0rc1 and FreeRTOS V9.0.0rc2 (release candidate 2) +released March 30 2016: + + NOTE - See https://www.FreeRTOS.org/FreeRTOS-V9.html for details + + + The functions that create RTOS objects using static memory allocation have + been simplified and will not revert to using dynamic allocation if a + buffer is passed into a function as NULL. + + Introduced the configSUPPORT_DYNAMIC_ALLOCATION configuration constant to + allow a FreeRTOS application to be built without a heap even being being + defined. The Win32 example located in the + /FreeRTOS/demo/WIN32-MSVC-Static-Allocation-Only directory is provided as + a reference for projects that do not include a FreeRTOS heap. + + Minor run-time optimisations. + + Two new low power tickless implementations that target Silicon Labs EFM32 + microcontrollers. + + Addition of the xTimerGetPeriod() and xTimerGetExpireTime() API functions. + +Changes between FreeRTOS V8.2.3 and FreeRTOS V9.0.0rc1 (release candidate 1) +released February 19 2016: + + RTOS Kernel Updates: + + + Major new feature - tasks, semaphores, queues, timers and event groups can + now be created using statically allocated memory, so without any calls to + pvPortMalloc(). + + Major new features - Added the xTaskAbortDelay() API function which allows + one task to force another task to immediately leave the Blocked state, + even if the event the blocked task is waiting for has not occurred, or the + blocked task's timeout has not expired. + + Updates necessary to allow FreeRTOS to run on 64-bit architectures. + + Added vApplicationDaemonTaskStartupHook() which executes when the RTOS + daemon task (which used to be called the timer service task) starts + running. This is useful if the application includes initialisation code + that would benefit from executing after the scheduler has been started. + + Added the xTaskGetTaskHandle() API function, which obtains a task handle + from the task's name. xTaskGetTaskHandle() uses multiple string compare + operations, so it is recommended that it is called only once per task. + The handle returned by xTaskGetTaskHandle() can then be stored locally for + later re-use. + + Added the pcQueueGetQueueName() API function, which obtains the name of + a queue from the queue's handle. + + Tickless idling (for low power applications) can now also be used when + configUSE_PREEMPTION is 0. + + If one task deletes another task, then the stack and TCB of the deleted + task is now freed immediately. If a task deletes itself, then the stack + and TCB of the deleted task are freed by the Idle task as before. + + If a task notification is used to unblock a task from an ISR, but the + xHigherPriorityTaskWoken parameter is not used, then pend a context switch + that will then occur during the next tick interrupt. + + Heap_1.c and Heap_2.c now use the configAPPLICATION_ALLOCATED_HEAP + settings, which previously was only used by heap_4.c. + configAPPLICATION_ALLOCATED_HEAP allows the application writer to declare + the array that will be used as the FreeRTOS heap, and in-so-doing, place + the heap at a specific memory location. + + TaskStatus_t structures are used to obtain details of a task. + TaskStatus_t now includes the bae address of the task's stack. + + Added the vTaskGetTaskInfo() API function, which returns a TaskStatus_t + structure that contains information about a single task. Previously this + information could only be obtained for all the tasks at once, as an array + of TaskStatus_t structures. + + Added the uxSemaphoreGetCount() API function. + + Replicate previous Cortex-M4F and Cortex-M7 optimisations in some + Cortex-M3 port layers. + + Demo Application Updates: + + Further demo applications will be added prior to the final FreeRTOS V9 + release. + + + Updated SAM4L Atmel Studio project to use Atmel Studio 7. + + Added ARM Cortex-A53 64-bit port. + + Added a port and demo for the ARM Cortex-A53 64-bit cores on the Xilinx + Ultrascale MPSoC. + + Added Cortex-M7 SAME70 GCC demo. + + Added EFM32 Giant and Wonder Gecko demos. + + +Changes between V8.2.2 and V8.2.3 released October 16, 2015 + + RTOS kernel updates: + + + Fix bug identified in a modification made in V8.2.2 to the software timer + code that allows tickless low power applications to sleep indefinitely + when software timers are used. + + Simplify and improve efficiency of stack overflow checking. + + Add xTaskNotifyStateClear() API function. + + New IAR and GCC Cortex-R ports for microprocessors that do not use an ARM + generic interrupt controller (GIC). + + New PIC32MEC14xx port. + + Add support for PIC32MZ EF parts (with floating point) into the PIC32MZ + port. + + Zynq7000 port layer now declares the functions that setup and clear the + tick interrupt as weak symbols so they can be overridden by the + application, and uses a global XScuGic object so the same object can be + used by the application code. + + Introduced configUSE_TASK_FPU_SUPPORT, although the PIC32MZ EF port is + currently the only port that uses it. + + Updates to RL78 and 78K0 IAR port layers to improve support for + combinations of memory models. + + Minor updates to heap_5.c to remove compiler warnings generated by some + compilers. + + License simplifications. See /FreeRTOS/License/license.txt in the + official distribution. + + FreeRTOS+ updates: + + + Update directory names to use WolfSSL instead of CyaSSL, inline with + WolfSSL's re-branding. + + Update to latest WolfSSL code. + + Update to latest FreeRTOS+Trace recorder code. + + Add in the FreeRTOS+Trace recorder library required for streaming trace. + + Demo application changes: + + + Add demo applications for Renesas RZ/T (Cortex-R), PIC32MZ EF (PIC32 with + floating point hardware), PIC32MEC14xx, RX71M, RX113 and RX231. + + General tidy up of spelling and compiler warnings. + + +Changes between V8.2.1 and V8.2.2 released August 12, 2015 + + RTOS kernel updates: + + + Added Intel IA32/x86 32-bit port. + + General maintenance. + + PRIVILEGED_FUNCTION and PRIVILEGED_DATA macros, which are used in memory + protected systems, have been added to the newer event group and software + timer functions. + + Add the errno definitions used by FreeRTOS+ components into projdefs.h. + + Remove the restriction that prevented tick-less idle implementations + waiting indefinitely when software timers were used in the same + application. + + Introduce xTaskNotifyAndQueryFromISR() as the interrupt safe version of + xTaskNotifyAndQuery(). + + Add additional NOPs to the MSP430X port layers to ensure strict compliance + with the hardware documentation. + + Microblaze port: Added option for port optimised task selection. + + Microblaze port: Previously tasks inherited the exception enable state + at the time the task was created. Now all tasks are created with + exceptions enabled if the Microblaze design supports exceptions. + + Windows port: Add additional safe guards to ensure the correct start up + sequence and thread switching timing. + + Windows port: Improve the implementation of the port optimised task + selection assembly code. + + Update heap_4 and heap_5 to allow use on 64-bit processors. + + Simplify the code that creates a queue. + + General improved tick-less idle behaviour. + + Ensure none of the variables in the common kernel files are initialised to + anything other than zero. + + Correct calculation of xHeapStructSize in heap_4 and heap_5. + + Demo application updates: + + + Added demo project for the new IA32/x86 port that targets the Galileo + hardware. + + Added MSP430FR5969 demos (previously provided as a separate download). + + Added FreeRTOS BSP repository for automatic creation of FreeRTOS + applications in the Xilinx SDK. + + Added Atmel Studio / GCC project for the SAMV71 (ARM Cortex-M7) + + Update Xilinx SDK projects to use version 2015.2 of the SDK. + + Remove Microblaze demos that were using obsolete tools. + + Add MSP43FR5969 IAR and CCS demos. + + FreeRTOS+ Updates: + + + Updated FreeRTOS+Trace recorder library, which requires an update to the + FreeRTOS+Trace application. + + Added Reliance Edge source code and demo application. Reliance edge is + a fail safe transactional file system ideal for applications that require + file storage, and especially when high reliability is essential. + + Introduce configAPPLICATION_PROVIDES_cOutputBuffer to allow FreeRTOS+CLI + users to place the output buffer at a fixed memory address. + + Improve the NetworkInterface.c file provided for the Windows port of + FreeRTOS+UDP. + +Changes between V8.2.0 and V8.2.1 released 24th March 2015. + + RTOS kernel updates: + + + Added user definable and flexible thread local storage facility. + + Added vTimerSetTimerID() API function to complement the pvTimerGetTimerID() + function to allow the timer's ID to be used as timer local storage. + + Fixed a potential issue related to the use of queue sets from an ISR. + + Some updates to the Xilinx Microblaze GCC port. + + Added ARM Cortex-M4F port for Texas Instruments Code Composer Studio. + + Added ARM Cortex-M7 r0p1 port layer for IAR, GCC and Keil which contains a + minor errata work around. All other ARM Cortex-M7 core revisions should + use the ARM Cortex-M4F port. + + Exclude the whole of croutine.c if configUSE_CO_ROUTINES is set to 0. + + Change some data types from uint32_t to size_t in preparation for 64-bit + Windows port. + + Update the PIC32 port to remove deprecation warnings output by the latest + XC32 compilers. + + Fix bug when xQueueOverwrite() and xQueueOverwrite() from ISR are used to + overwrite items in two queues that are part of the same set. + + Demo application updates: + + + Added demo application for TI's ARM Cortex-M4F based MSP432 + microcontroller using IAR, Keil and CCS compilers. + + Added demo application for STM32F ARM Cortex-M7 based microcontroller + using IAR and Keil. + + Added demo application for Atmel SAMV71 ARM Cortex-M7 based + microcontroller using IAR and Keil. + + Added Microblaze demo that uses the 2014.4 version of the Xilinx SDK and + runs on the KC705 evaluation board (Kintex FPGA). + +Changes between V8.1.2 and V8.2.0 released 16th January 2015 + + Changes between release candidate 1 and the official release are restricted + to maintenance only. + + Significant RTOS kernel updates: + + + MAJOR NEW FEATURE! Task notifications. Please see the following URL for + details: https://www.FreeRTOS.org/RTOS-task-notifications.html + + NEW HEADER FILE REQUIRED! Obsolete definitions have been separated into + a new header file called FreeRTOS/Source/include/deprecated_definitions.h. + This header file must be present to build. Note some of the obsolete + definitions are still used by very old demo application projects. + + Other RTOS kernel updates: + + + Made xSemaphoreGiveFromISR() a function rather than a macro that calls + xQueueGenericSendFromISR(). This allows for major performance + enhancements at the expense of some additional code size if both functions + are used in the same application. NOTE: In most uses cases such use of + a semaphore can now be replaced with a task notification which is smaller + and faster still. + + The TCB is now always allocated such that the task's stack grows away from + the TCB (improves debugging of stack overflows as the overflow will not + overwrite the task's name). + + GCC, IAR and Keil Cortex-M4F ports now use more inlining (performance + enhancements at the cost of a little additional code space). + + Queues are now allocated with a single call to pvPortMalloc() which + allocates both the queue structure and the queue storage area. + + Introduced a new critical section macro for reading the tick count that + defines away to nothing in cases where the width of the tick allows the + tick count to be read atomically (performance benefits - especially when + optimisation is on). + + Introduced configAPPLICATION_ALLOCATED_HEAP in heap_4.c to allow the + application writer to provide their own heap array - and in so doing + control the location of the heap. + + Introduced configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES which, when set, will + include known values in both list and list item structures. The values + are intended to assist debugging. If the values get overwritten then it + is likely application code has written over RAM used by the kernel. + + configASSERT()s in all Cortex-M ports used to test the lowest 5 bits of + the interrupt control register to detect taskENTER_CRITICAL() being called + from an interrupt. This has been changed to test all 8 bits. + + Introduced uxTaskPriorityGetFromISR(). + + Microblze V8 port now tests XPAR_MICROBLAZE_0_USE_FPU for inequality to 0 + rather than equality to 1, and 2 and 3 are also valid values. + + Cortex-A5 GIC-less port no longer passes the address of the interrupting + peripheral into the interrupt handler. + + Fix an issue in FreeRTOS-MPU where an attempt was made to free the stack + belonging to a task when the task was deleted, even when the stack was + allocated statically. + + Utility (helper) functions that format task statistic information into + human readable tables now pad task names with spaces to ensure columns + line up correctly even where task name lengths vary greatly. + + Update FreeRTOS+Trace recorder library to version 2.7.0. + + Demo application updates: + + + Added two new standard demo task sets: IntSemTest and TaskNotify. + + Added port and demo application for Atmel SAMA5D4 Cortex-A5 MPU. + + Added demo application for Altera Cyclone V Cortex-A9 MPU. + + Updated Zynq demo to use version 2014.4 of Xilinx's SDK and added in + demo tasks for new RTOS features. + + Updated Atmel SAM4E and SAM4S demos to include a lot of additional test + and demo tasks. + + Fixed a corner case issue in Atmel SAM4L low power tickless + implementation, and added button interrupt handling. + + Make the interrupt queue tests more tolerant to heave CPU loads. + + Updated MSVC FreeRTOS simulator demo to include the latest standard test + and demo tasks. + + Updated MingW/Eclipse FreeRTOS simulator demo to match the FreeRTOS MSVC + simulator demo. + + Updated all demos that use FreeRTOS+Trace to work with the latest trace + recorder code. + + +Changes between V8.1.1 and V8.1.2 released September 2nd 2014 + + Move the defaulting of configUSE_PORT_OPTIMISED_TASK_SELECTION into the + individual port layers where necessary so it does not affect ports that do + not support the definition. + +Changes between V8.1.0 and V8.1.1 released August 29th 2014 + + By popular requests - a minor patch to V8.1.0 to re-instate the ability to + give a mutex type semaphore (with priority inheritance) from an interrupt + handler. + +Changes between V8.0.1 and V8.1.0 released August 26th 2014 + + FreeRTOS scheduler, kernel, demo and test updates: + + + Improved the priority inheritance algorithms to assist integration with + off the shelf middleware that may hold multiple mutexes simultaneously. + + Introduce heap_5.c, which is similar to heap_4.c but allows the heap to + span multiple non-contiguous memory regions. + + Updated all Cortex-A9 ports to help trap a couple of common usage errors - + the first being when a task incorrectly attempts to exit its implementing + function and the second being when a non interrupt safe API function is + called from an interrupt. + + Update all Cortex-A9 ports to remove obsolete mode switches prior to + restoring a task context. + + configUSE_PORT_OPTIMISED_TASK_SELECTION now defaults to 1 instead of 0. + + Update all Cortex-M3/4F ports to trap a non interrupt safe API function + being called from an interrupt handler. + + Simplify the alignment checks in heap_4.c. + + Update the MSVC Windows simulator demo to use heap_5.c in place of + heap_4.c to ensure end users have an example to refer to. + + Updated standard demo test code to test the new priority inheritance + algorithms. + + Updated the standard demo tasks to make use of stdint and the FreeRTOS + specific typedefs that were introduced in FreeRTOS V8.0.0. + + Introduce the pdMS_TO_TICKS() macro as a more user friendly and intuitive + alternative to pdTICKS_PER_MS - both of which can be used to convert a + time specified in milliseconds to a time specified in RTOS ticks. + + Fix a bug in the Tasking compiler's Cortex-M port that resulted in an + incorrect value being written to the basepri register. This only effects + users of the Tasking compiler. + + Update the Zynq demo to use version 2014.2 of the SDK and add in an lwIP + example that demonstrates lwIP being used with both its raw and sockets + interfaces. + + Updated the CCS Cortex-R4 port to enable it to be built with the latest + CCS compiler. + + New ports and demo applications: + + + Two Renesas RX64M ports (RXv2 core) and demos introduced, one for the GCC + compiler and one for the Renesas compiler. Both demos use e2 studio. + + Generic IAR Cortex-A5 port (without any reliance on a GIC) introduced. + The new port is demonstrated on an Atmel SAMA5D3 XPlained board. + + FreeRTOS+ component updates: + + + Update CyaSSL to the latest version. + + Updated the FreeRTOS+ components supplied directly by Real Time Engineers + Ltd. to make use of stdint and the FreeRTOS specific typedefs that were + introduced in FreeRTOS V8.0.0. + + Rework and simplify the FreeRTOS+FAT SL RAM disk driver. + + Miscellaneous updates and maintenance: + + + Update the IAR and DS-5/ARM RZ demos to target the official RZ RSK + hardware in place of the previously targeted Renesas internal (not + publicly available) hardware. + + Various other maintenance tasks. + + +Changes between V8.0.0 and V8.0.1 released 2nd May 2014 + + + Minor fixes to the event group functionality that was released in V8.0.0. + The 'clear bits from ISR' functionality is now implemented using a + deferred interrupt callback instead of a function, and the 'wait bits' and + 'task sync' functions now correctly clear internal control bits before + returning a value in every possible path through the respective functions. + + Ensure the updating of internal control data is protected by a critical + section after a task is deleted or suspended. + + Minor fixes to FreeRTOS+FAT SL - namely seeking beyond the end of a file + when the offset was not a multiple of the sector size. + + Ensure Cortex-A9 system registers are only ever accessed as 32-bit values, + even when only the lest significant byte of the register is implemented. + + Other updates: + + + Updated the XMC4200 IAR project so it links with version 7.x of the IAR + tools. + + Add RL78L1C demo. + + Add pcTimerGetName() API function. + + Call _reclaim_reent() when a task is deleted if configUSE_NEWLIB_REENTRANT + is defined. + +Changes between V7.6.0 and V8.0.0 released 19th Feb 2014 + + https://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html + + FreeRTOS V8.x.x is a drop-in compatible replacement for FreeRTOS V7.x.x, + although a change to the type used to reference character strings may result + in application code generating a few (easily clearable) compiler warnings + after the upgrade, and an updated typedef naming convention means use of the + old typedef names is now discouraged. + See https://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html for full + information. + + New features and functionality: + + + Event groups - see https://www.FreeRTOS.org/FreeRTOS-Event-Groups.html + + Centralised deferred interrupt processing - see + https://www.FreeRTOS.org/xTimerPendFunctionCallFromISR.html + + Other updates: + + + Previously, when a task left the Blocked state, a context switch was + performed if the priority of the unblocked task was greater than or equal + to the priority of the Running task. Now a context switch is only + performed if the priority of the unblocked task is greater than the + priority of the Running task. + + New low power tickless demonstration project that targets the ST STM32L + microcontroller - see + https://www.FreeRTOS.org/STM32L-discovery-low-power-tickless-RTOS-demo.html + + Add xPortGetMinimumEverFreeHeapSize() to heap_4.c. + + Small change to the tickless low power implementation on the SAM4L to + ensure the alarm value (compare match value) cannot be set to zero when a + tickless period is exited due to an interrupt originating from a source + other than the RTOS tick. + + Update the GCC/Eclipse Win32 simulator demo to make better use of Eclipse + resource filters and match the functionality of the MSVC equivalent. + + xTaskIsTaskSuspended() is no longer a public function. Use + eTaskGetState() in its place. + + Improved trace macros, including tracing of heap usage. + + Remove one level of indirection when accepting interrupts on the PIC32MZ. + + Add Cortex-A9 GCC port layer. + + Add Xilinx Zynq demo application. + + +Changes between V7.5.3 and V7.6.0 released 18th November 2013 + + V7.6.0 changes some behaviour when the co-operative scheduler is used (when + configUSE_PREEMPTION is set to 0). It is important to note that the + behaviour of the pre-emptive scheduler is unchanged - the following + description only applies when configUSE_PREEMPTION is set to 0: + + WHEN configUSE_PREEMPTION IS SET TO 0 (which is in a small minority of + cases) a context switch will now only occur when a task places itself into + the Blocked state, or explicitly calls taskYIELD(). This differs from + previous versions, where a context switch would also occur when implicitly + moving a higher priority task out of the Blocked state. For example, + previously, WHEN PREEMPTION WAS TURNED OFF, if task A unblocks task B by + writing to a queue, then the scheduler would switch to the higher priority + task. Now, WHEN PREEMPTION IS TURNED OFF, if task A unblocks task B by + writing to a queue, task B will not start running until task A enters the + Blocked state or task A calls taskYIELD(). [If configUSE_PREEMPTION is not + set to 0, so the normal pre-emptive scheduler is being used, then task B + will start running immediately that it is moved out of the Blocked state]. + + Other changes: + + + Added a port layer and a demo project for the new PIC32MZ architecture. + + Update the PIC32MX port layer to re-introduce some ehb instructions that + were previously removed, add the ability to catch interrupt stack + overflows (previously only task stack overflows were trapped), and also + add the ability to catch an application task incorrectly attempting to + return from its implementing function. + + Make dramatic improvements to the performance of the Win32 simulator port + layer. + + Ensure tasks that are blocked indefinitely report their state as Blocked + instead of Suspended. + + Slight improvement to the Cortex-M4F port layers where previously one + register was inadvertently being saved twice. + + Introduce the xSemaphoreCreateBinary() API function to ensure consistency + in the semantics of how each semaphore type is created. It is no longer + recommended to use vSemaphoreCreateBinary() (the version prefixed with a + 'v'), although it will remain in the code for backward compatibility. + + Update the Cortex-M0 port layers to allow the scheduler to be started + without using the SVC handler. + + Added a build configuration to the PIC32MX MPLAB X demo project that + targets the PIC32 USB II starter kit. Previously all the build + configurations required the Explorer 16 hardware. + + Some of the standard demo tasks have been updated to ensure they execute + correctly with the updated co-operative scheduling behaviour. + + Added comprehensive demo for the Atmel SAM4E, including use of + FreeRTOS+UDP, FreeRTOS+FAT SL and FreeRTOS+CLI. + + FreeRTOS+ Changes: + + + Minor maintenance on FreeRTOS+UDP. + +Changes between V7.5.2 and V7.5.3 released October 14 2013 + + Kernel changes: + + + Prior to V7.5.x yields requested from the tick hook would occur in the + same tick interrupt - revert to that original behaviour. + + New API function uxQueueSpacesAvailable(). + + Introduced the prvTaskExitError() function to Cortex-M0, Cortex-M3/4 + and Cortex-M4F ports. prvTaskExitError() is used to trap tasks that + attempt to return from their implementing functions (tasks should call + vTaskDelete( NULL ); if they want to exit). + + The Cortex-M0 version of portSET_INTERRUPT_MASK_FROM_ISR and + portCLEAR_INTERRUPT_MASK_FROM_ISR are now fully nestable. + + Improved behaviour and robustness of the default Cortex-M tickless idle + behaviour. + + Add workaround for silicon errata PMU_CM001 in Infineon XMC4000 devices to + all Cortex-M4F ports. + + Add Cortex-M0 port for Keil. + + Updated Cortus port. + + Ensure _impure_ptr is initialised before the scheduler is started. + Previously it was not set until the first context switch. + + FreeRTOS+ changes: + + + Update FreeRTOS+UDP to V1.0.1 - including direct integration of the + FreeRTOS+Nabto task, improvements to the DHCP behaviour, and a correction + to the test that prevents the network event hook being called on the first + network down event. The FreeRTOS+UDP change history is maintained + separately. + + Correct the __NVIC_PRIO_BITS setting in the LPC18xx.h header files + provided in the NXP CMSIS library, then update the interrupts used by the + LPC18xx demos accordingly. + + Replace double quotes (") with single quotes (') in FreeRTOS+CLI help + strings to ensure the strings can be used with the JSON descriptions used + in the FreeRTOS+Nabto demos. + + Demo and miscellaneous changes: + + + Added demo for the Atmel SAMD20 Cortex-M0+. The demo includes + FreeRTOS+CLI + + Added a demo for the Infineon Cortex-M0 that can be built with the IAR + Keil and GCC tools. + + Updated the Infineon XMC4000 demos for IAR, Keil, GCC and Tasking tools, + with additional build configurations to directly support the XMC4200 and + XMC4400 devices, in addition to the previously supported XMC4500. + + Updated the demo application. + + Added additional trace macros traceMALLOC and traceFREE to track heap + usage. + +Changes between V7.5.0 and V7.5.2 released July 24 2013 + + V7.5.2 makes the new Cortex-M vPortCheckInterruptPriority() function + compatible with the STM32 standard peripheral driver library, and adds + an extra critical section to the default low power tickless mode + implementation. Only users of the STM32 peripheral library or the default + tickless implementation need update from version 7.5.0. + +Changes between V7.4.2 and V7.5.0 released July 19 2013 + + V7.5.0 is a major upgrade that includes multiple scheduling and efficiency + improvements, and some new API functions. + + Compatibility information for FreeRTOS users: + FreeRTOS V7.5.0 is backward compatible with FreeRTOS V7.4.0 with one + exception; the vTaskList() and vTaskGetRunTimeStats() functions are now + considered legacy, having been replaced by the single uxTaskGetSystemState() + function. configUSE_STATS_FORMATTING_FUNCTIONS must be set to 1 in + FreeRTOSConfig.h for vTaskList() and vTaskGetRunTimeStats() to be + available. + + Compatibility information for FreeRTOS port writers: + vTaskIncrementTick() is now called xTaskIncrementTick() (because it now + returns a value). + + Headline changes: + + + Multiple scheduling and efficiency improvements. + + Core kernel files now pass PC-Lint V8 static checking without outputting + any warnings (information on the test conditions will follow). + + New API functions: + + + uxTaskGetSystemState() https://www.FreeRTOS.org/uxTaskGetSystemState.html + + xQueueOverwrite() https://www.FreeRTOS.org/xQueueOverwrite.html + + xQueueOverwriteFromISR() + + xQueuePeekFromISR() + + The following ports and demos, which were previously available separately, + are now incorporated into the main FreeRTOS zip file download: + + + ARM Cortex-A9 IAR + + ARM Cortex-A9 ARM compiler + + Renesas RZ + + Microsemi SmartFusion2 + + New FreeRTOSConfig.h settings + https://freertos.org/a00110.html + + + configUSE_TIME_SLICING + + configUSE_NEWLIB_REENTRANT + + configUSE_STATS_FORMATTING_FUNCTIONS + + configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + + Other changes: + + + (MPU port only) The configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + options provides a mechanism that allows application writers to execute + certain functions in privileged mode even when a task is running in user + mode. + + Ports that support interrupt nesting now include a configASSERT() that + will trigger if an interrupt safe FreeRTOS function is called from an + interrupt that has a priority designated as above the maximum system/API + call interrupt priority. + + The included FreeRTOS+Trace recorder code has been updated to the latest + version, and the demo applications that use the trace recorder code have + been updated accordingly. + + The FreeRTOS Windows Simulator (MSVC version only) has been updated to + include a new basic 'blinky' build option in addition to the original + comprehensive build option. + + Improve RAM usage efficiency of heap_4.c and heap_2.c. + + Prevent heap_4.c from attempting to free memory blocks that were not + allocated by heap_4.c, or have already been freed. + + As FreeRTOS now comes with FreeRTOS+FAT SL (donated by HCC) the Chan FATfs + files have been removed from FreeRTOS/Demo/Common. + + Fix build error when R4 port is build in co-operative mode. + + Multiple port and demo application maintenance activities. + +Changes between V7.4.1 and V7.4.2 released May 1 2013 + + NOTE: There are no changes in the FreeRTOS kernel between V7.4.1 and V7.4.2 + + + Added FreeRTOS+FAT SL source code and demo project. The demo project + runs in the FreeRTOS Windows simulator for easy and hardware independent + experimentation and evaluation. See https://www.FreeRTOS.org/fat_sl + +Changes between V7.4.0 and V7.4.1 released April 18 2013 + + + To ensure strict conformance with the spec and ensure compatibility with + future chips data and instruction barrier instructions have been added to + the yield macros of Cortex-M and Cortex-R port layers. For efficiency + the Cortex-M port layer "yield" and "yield" from ISR are now implemented + separately as the barrier instructions are not required in the ISR case. + + Added FreeRTOS+UDP into main download. + + Reorganised the FreeRTOS+ directory so it now matches the FreeRTOS + directory with Source and Demo subdirectories. + + Implemented the Berkeley sockets select() function in FreeRTOS+UDP. + + Changed (unsigned) casting in calls to standard library functions with + (size_t) casting. + + Added the Atmel SAM4L and Renesas RX100 demos that demonstrates the + tickless (tick suppression) low power FreeRTOS features. + + Add a new RL78 IAR demo that targets numerous new RL78 chips and + evaluation boards. + + Adjusted stack alignment on RX200 ports to ensure an assert was not + falsely triggered when configASSERT() is defined. + + Updated the Cortex_M4F_Infineon_XMC4500_IAR demo to build with the latest + version of EWARM. + + Corrected header comments in the het.c and het.h files (RM48/TMS570 demo). + + +Changes between V7.3.0 and V7.4.0 released February 20 2013 + + + New feature: Queue sets. See: + https://www.FreeRTOS.org/Pend-on-multiple-rtos-objects.html + + Overhauled the default tickless idle mode implementation provided with the + ARM Cortex-M3 port layers. + + Enhanced tickless support in the core kernel code with the introduction of + the configEXPECTED_IDLE_TIME_BEFORE_SLEEP macro and the + eTaskConfirmSleepModeStatus() function. + + Added the QueueSet.c common demo/test file. Several demo applications + have been updated to use the new demo/test tasks. + + Removed reliance on the PLIB libraries from the MPLAB PIC32 port layer and + demo applications. + + Added the FreeRTOS+Trace recorder code to the MSVC Win32 demo. + + Renamed eTaskStateGet() to eTaskGetState() for consistency, and added a + pre-processor macro for backward compatibility with the previous name. + + Updated functions implemented in the core queue.c source file to allow + queue.h to be included from the .c file directly (this prevents compiler + warnings that were generated by some compilers). + + Updated the CCS Cortex-R4 port layer to replace the CLZ assembler function + with the CLZ compiler intrinsic that is provided by the latest versions of + the CCS ARM compiler. + + Updated all heap_x.c implementations to replace the structure that was + used to ensure the start of the heap was aligned with a more portable + direct C code implementation. + + Added support for PIC24 devices that include EDS. + + Minor optimisations to the PIC32 port layer. + + Minor changes to tasks.c that allow the state viewer plug-ins to display + additional information. + + Bug fix: Update prvProcessReceivedCommands() in timers.c to remove an + issue that could occur if the priority of the timer daemon task was set + below the priority of tasks that used timer services. + + Update the FreeRTOS+Trace recorder code to the latest version. + +Changes between V7.2.0 and V7.3.0 released October 31 2012 + + + Added ability to override the default scheduler task selection mechanism + with implementations that make use of architecture specific instructions. + + Added ability to suppress tick interrupts during idle time, and in so + doing, provide the ability to make use of architecture specific low power + functionality. + + Added the portSUPPRESS_TICKS_AND_SLEEP() macro and vTaskStepTick() helper + function. + + Added the configSYSTICK_CLOCK_HZ configuration constant. + + Reworked the Cortex-M3 and Cortex-M4F port layers for GCC, Keil and IAR to + directly support basic power saving functionality. + + Added hooks to allow basic power saving to be augmented in the application + by making use of chip specific functionality. + + Minor change to allow mutex type semaphores to be used from interrupts + (which would not be a normal usage model for a mutex). + + Change the behaviour of the interrupt safe interrupt mask save and restore + macros in the Cortex-M ports. The save macro now returns the previous + mask value. The restore macro now uses the previous mask value. These + changes are not necessary for the kernel's own implementation, and are + made purely because the macros were being used by application writers. + + Added eTaskStateGet() API function. + + Added port specific optimisations to the PIC32 port layer, and updated the + PIC32 demo applications to make use of this new feature. + + Added port specific optimisations to the Win32 simulator port. + + Added new ports and demo applications for the TI Hercules RM48 and TMS570 + safety microcontrollers. + + Added SAM3 demos targeting the ATSAM3S-EK2 and ATSAM3X-EK evaluation + boards. + + Updated the PIC32 MPLAB X project to manually set the compiler include + paths instead of using the IDE entry box following reports that the + include paths were somehow being deleted. + + Improved character handling in FreeRTOS+CLI. + +Changes between V7.1.1 and V7.2.0 released 14 August 2012 + + FreeRTOS V7.2.0 is backward compatible with FreeRTOS V7.1.2. + + + Added a FreeRTOS+ sub-directory. The directory contains some FreeRTOS+ + source code, and example projects that use the FreeRTOS Win32 simulator. + + Added a new example heap allocation implementation (heap_4.c) that + includes memory block coalescence. + + Added a demo that targets the Atmel SAM4S Cortex-M4 based microcontroller. + The demo is preconfigured to build using the free Atmel Studio 6 IDE and + GCC compiler. + + Added xSemaphoreTakeFromISR() implementation. + + The last parameter in ISR safe FreeRTOS queue and semaphore functions + (xHigherPriorityTaskWoken) is now optional and can be set to NULL if it + is not required. + + Update the IAR and MSP430X ports to clear all lower power mode bits before + exiting the tick interrupt [bug fix]. + + Allow xQueueReset() to be used, even when the queues event lists are not + empty. + + Added a vQueueDelete() handler for the FreeRTOS MPU port (this was + previously missing). + + Updated the vPortSVCHandler() functions in the FreeRTOS MPU port layer to + ensure it compiles with the latest ARM GCC compilers from Linaro. + + Updated the prvReadGP() function in the NIOS II port to ensure the compiler + can choose any register for the functions parameter (required at high + compiler optimisation levels). + + Add #error macros into the Keil and IAR Cortex-M ports to ensure they + cannot be built if the user has set configMAX_SYSCALL_INTERRUPT_PRIORITY + to 0. + + Added comments in the FreeRTOSConfig.h files associated with Cortex-M3 and + Cortex-M4 demos stating that the configMAX_SYSCALL_INTERRUPT_PRIORITY + parameter must not be set to 0. + + Introduce new INCLUDE_xQueueGetMutexHolder configuration constant + (defaulted to 0). + + Added two new list handling macros - for internal use only in upcoming new + products. + + Removed all mention of the legacy vTaskStartTrace and ulTaskEndTrace + macros. FreeRTOS+Trace supersedes the legacy trace. + + Added a configASSERT() into the vPortFree() function in heap_1.c as it is + invalid for the function to be called. + + Made the xRxLock and xTxLock members of the queue structure volatile. + This is probably not necessary, and is included as a precautionary + measure. + + Modify the assert() that checks to see if the priority passed into an + xTaskCreate() function is within valid bounds to permit the assert to be + used in the FreeRTOS MPU port. + + The software timer service (daemon) task is now created in a way that + to ensure compatibility with FreeRTOS MPU. + +Changes between V7.1.0 and V7.1.1 released May 1 2012 + + New ports: + + The following ports are brand new: + + Cortex-M3 Tasking + + The following ports have been available as separate downloads for a number + of months, but are now included in the main FreeRTOS download. + + Cortex-M0 IAR + + Cortex-M0 GCC + + Cortex-M4F GCC (with full floating point support) + + + New demos: + + The following demos are brand new: + + Renesas RX63N RDK (Renesas compiler) + + The following demos have been available as separate downloads for a number + of months, but are now included in the main FreeRTOS download. + + NXP LPC1114 GCC/LPCXpresso + + ST STM32F0518 IAR + + Infineon XMC4500 GCC/Atollic + + Infineon XMC4500 IAR + + Infineon XMC4500 Keil + + Infineon XMC4500 Tasking + + + Kernel miscellaneous / maintenance: + + + Introduced the portSETUP_TCB() macro to remove the requirement for the + Windows simulator to use the traceTASK_CREATE() macro, leaving the trace + macro available for use by FreeRTOS+Trace (https://www.FreeRTOS.org/trace). + + Added a new trace macro, traceMOVE_TASK_TO_READY_STATE(), to allow future + FreeRTOS+Trace versions to provide even more information to users. + + Updated the FreeRTOS MPU port to be correct for changes that were + introduced in FreeRTOS V7.1.0. + + Introduced the xQueueReset() API function. + + Introduced the xSemaphoreGetMutexHolder() API function. + + Tidy up various port implementations to add the static key word where + appropriate, and remove obsolete code. + + Slight change to the initial stack frame given to the RX600 ports to allow + them to be used in the Eclipse based E2Studio IDE without confusing GDB. + + Correct the alignment given to the initial stack of Cortex-M4F tasks. + + Added a NOP following each DINT instruction on MSP430 devices for strict + conformance with the instructions on using DINT. + + Changed the implementation of thread deletes in the Win32 port to prevent + the port making use of the traceTASK_DELETE() trace macros - leaving this + macro free for use by FreeRTOS+Trace. + + Made some benign changes to the RX600 Renesas compiler port layer to + ensure the code can be built to a library without essential code being + removed by the linker. + + Reverted the change in the name of the uxTaskNumber variable made in + V7.1.0 as it broke the IAR plug-in. + + + Demo miscellaneous / maintenance: + + + The command interpreter has now been formally released as FreeRTOS+CLI, + and been moved out of the main FreeRTOS download, to instead be available + from the FreeRTOS+ Ecosystem site https://www.FreeRTOS.org/plus. + + flash_timer.c/h has been added to the list of standard demo tasks. This + performs the same functionality as the flash.c tasks, but using software + timers in place of tasks. + + Upgraded the PIC32 demo as follows: Changes to how the library functions + are called necessitated by the new compiler version, addition of MPLAB X + project with PIC32MX360, PIC32MX460 and PIC32MX795 configurations, + addition of simply blinky demo, updated FreeRTOSConfig.h to include more + parameters, addition of hook function stubs. + + The MSP430X IAR and CCS demos have been updated to ensure the power + settings are correct for the configured CPU frequency. + + Rowley CrossWorks projects have been updated to correct the "multiple + definition of ..." warnings introduced when the toolchain was updated. + + Updated various FreeRTOSConfig.h header files associated with projects + that build with Eclipse to include a #error statement informing the user + that the CreateProjectDirectoryStructure.bat batch file needs to be + executed before the projects can be opened. + + Renamed directories that included "CCS4" in their name to remove the '4' + and instead just be "CCS". This is because the demo was updated and + tested to also work with later Code Composer Studio versions. + + Updated the TCP/IP periodic timer frequency in numerous uIP demos to be + 50ms instead of 500ms. + +Changes between V7.0.2 and V7.1.0 released December 13 2011 + + New ports: + + + Cortex-M4F IAR port. + + Cortex-M4F Keil/RVDS port. + + TriCore GCC port. + + New demos: + + + NXP LPC4350 using the Keil MDK, and demonstrated on a Hitex development + board. + + ST STM32F407 using the IAR Embedded Workbench for ARM, and demonstrated on + the IAR STM32F407ZG-SK starter kit. + + Infineon TriCore TC1782, using the GCC compiler, demonstrated on the + TriBoard TC1782 evaluation board. + + Renesas RX630, using the Renesas compiler and HEW, demonstrated on an + RX630 RSK (Renesas Starter Kit). + + Miscellaneous / maintenance: + + + Removed all calls to printf() from the K60/IAR Kinetis demo so the project + can execute stand alone - without being connected to the debugger. + + Completed the command interpreter framework. Command handlers now receive + the entire command string, giving them direct access to parameters. + Utility functions are provided to check the number of parameters, and + return parameter sub-strings. + + The previously documented fix for the bug in xTaskResumeFromISR() that + effected (only) ports supporting interrupt nesting has now been + incorporated into the main release. + + The portALIGNMENT_ASSERT_pxCurrentTCB() definition has been added to allow + specific ports to skip the second stack alignment check when a task is + created. This is because the second check is not appropriate for some + ports - including the new TriCore port where the checked pointer does not + actually point to a stack. + + The portCLEAN_UP_TCB() macro has been added to allow port specific clean + up when a task is deleted - again this is required by the TriCore port. + + Various other minor changes to ensure warning free builds on a growing + number of microcontroller and toolchain platforms. This includes a + (benign) correction to the prototype of the + vApplicationStackOverflowHook() definition found in lots of recent demos. + + Trace system: + + + The legacy trace mechanism has been completely removed - it has been + obsolete for the years since the trace macros were introduced. The + configuration constant configUSE_TRACE_FACILITY is now used to optionally + include additional queue and task information. The additional information + is intended to make the trace mechanism more generic, and allow the trace + output to provide more information. When configUSE_TRACE_FACILITY is set + to 1: + - the queue structure includes an additional member to hold the queue + type, which can be base, mutex, counting semaphore, binary semaphore + or recursive mutex. + - the queue structure includes an additional member to hold a queue + number. A trace tool can set and query the queue number for its own + purposes. The kernel does not use the queue number itself. + - the TCB structure includes an additional member to hold a task number + number. A trace tool can set and query the task number for its own + purposes. The kernel does not use the task number itself. + + Queues and all types of semaphores are now automatically allocated their + type as they are created. + + Added two new trace macros - traceTASK_PRIORITY_INHERIT() and + traskTASK_PRIORITY_DISINHERIT(). + + Updated the traceQUEUE_CREATE_FAILED() macro to take a parameter that + indicates the type of queue, mutex, or semaphore that failed to be + created. + + The position from which traceCREATE_MUTEX() is called has been moved from + after the call to xQueueGenericSend() [within the same function] to before + the call. This ensures the trace events occur in the correct order. + + The value passed into tracePRIORITY_SET() has been corrected for the case + where vTaskPrioritySet() is called with a null parameter. + +Changes between V7.0.1 and V7.0.2 released September 20 2011 + + New ports: + + + The official FreeRTOS Renesas RX200 port and demo application have been + incorporated into the main FreeRTOS zip file download. + + The official FreeRTOS Renesas RL78 port and demo application have been + incorporated into the main FreeRTOS zip file download. + + The official FreeRTOS Freescale Kinetis K60 tower demo application has + been incorporated into the main FreeRTOS zip file download. This includes + an embedded web server example. + + A new Microblaze V8 port layer has been created to replace the older, now + deprecated, port layer. The V8 port supports V8.x of the Microblaze IP, + including exceptions, caches, and the floating point unit. A new + Microblaze demo has also been added to demonstrate the new Microblaze V8 + port layer. The demo application was created using V13.1 of the Xilinx + EDK, and includes a basic embedded web server that uses lwIP V1.4.0. + + The official FreeRTOS Fujitsu FM3 MB9A310 demo application has been + incorporated into the main FreeRTOS zip file download. Projects are + provided for both the IAR and Keil toolchains. + + + API additions: + + + xTaskGetIdleTaskHandle() has been added. + + xTaskGetTimerDaemonTaskHandle() has been added. + + pcTaskGetTaskName() has been added. + + vSemaphoreDelete() macro has been added to make it obvious how to delete + a semaphore. In previous versions vQueueDelete() had to be used. + + vTaskCleanUpResources() has been removed. It has been obsolete for a + while. + + portPOINTER_SIZE_TYPE has been introduced to prevent compiler warnings + being generated when the size of a pointer does not match the size of + the stack type. This will (has already) be used in new ports, but will + not be retrofitted to existing ports until the existing port itself is + updated. + + Other updates and news: + + + The core files have all been modified to tighten the coding standard even + further. These are style, not functional changes. + + All ARM7 port layers have been slightly modified to prevent erroneous + assert() failures when tasks are created and configASSERT() is defined. + + All ARM IAR projects have been updated to build with the latest V6.2.x + versions of the IAR Embedded Workbench for ARM tools (EWARM). This was + necessary due to a change in the way EWARM uses the CMSIS libraries. + + The PIC32 port layer has been updated in preparation for V2 of the C32 + compiler. + + The old Virtex-4 Microblaze demo has been marked as deprecated. Please + use the brand new Spartan-6 port and demo in its place. + + The bones of a new generic command interpreter is located in + FreeRTOS/Demo/Common/Utils/CommandInterpreter.c. This is still a work in + progress, and not documented. It is however already in use. It will be + documented in full when the projects that are already using it are + completed. + + A couple of new standard demos have been included. First, a version of + flop.c called sp_flop.c. This is similar to flop.c, but uses single + precision floats in place of double precision doubles. This allows the + for testing ports to processors that have only single precision floating + point units, and revert to using emulated calculations whenever a double + is used. Second, comtest_strings.c has been included to allow the test + of UART drivers when an entire string is transmitted at once. The + previous comtest.c only used single character transmission and reception. + + lwIP V1.4.0 is now included in the FreeRTOS/Demo/Common directory, and + used by a couple of new demos. + +Changes between V7.0.0 and V7.0.1 released May 13 2011 + + + Added a Fujitsu FM3 demo application for both the IAR and Keil tool + chains. + + Added a SmartFusion demo application for all of the IAR, Keil and + SoftConsole (GCC/Eclipse) tool chains. + + Updated the RX600 port and demo applications to take into account the + different semantics required when using the latest (V1.0.2.0) version of + the Renesas compiler. + + Modified the RX600 Ethernet driver slightly to make it more robust under + heavy load, and updated the uIP handling task to make use of the FreeRTOS + software timers. + + Slightly changed the PIC32 port layer to move an ehb instruction in line + with the recommendations of the MIPS core manual, and ensure 8 byte stack + alignment is truly always obtained. + + Changed the behaviour when tasks are suspended before the scheduler has + been started. Before, there needed to be at least one task that was not + in the suspended state. This is no longer the case. + +Changes between V6.1.1 and V7.0.0 released April 8 2011 + + FreeRTOS V7.0.0 is backward compatible with FreeRTOS V6.x.x + + Main changes: + + + Introduced a new software timer implementation. + + Introduced a new common demo application file to exercise the new timer + implementation. + + Updated the Win32/MSVC simulator project to include the new software timer + demo tasks and software timer tick hook test. Much simpler software timer + demonstrations are included in the demo projects for both of the new ports + (MSP430X with CCS4 and STM32 with TrueStudio). + + Various enhancements to the kernel implementation in tasks.c. These are + transparent to users and do not effect the pre-existing API. + + Added calls to configASSERT() within the kernel code. configASSERT() is + functionally equivalent to the standard C assert() macro, but does not + rely on the compiler providing assert.h. + + Other changes: + + + Updated the MSP430X IAR port and demo project to include support for the + medium memory model. + + Added a demo project for the MSP430X that targets the MSP430X Discovery + board and uses the Code Composer Studio 4 tools. This demo includes use + of the new software timer implementation. + + Added an STM32F100RB demo project that targets the STM32 Discovery Board + and uses the TrueStudio Eclipse based IDE from Atollic. + + Removed some compiler warnings from the PSoC demo application. + + Updated the PIC32 port layer to ensure the + configMAX_SYSCALL_INTERRUPT_PRIORITY constant works as expected no matter + what its value is (within the valid range set by the microcontroller + kernel). + + Updated the PIC24, dsPIC and PIC32 projects so they work with the latest + MPLAB compiler versions from Microchip. + + Various cosmetic changes to prepare for a standards compliance statement + that will be published after the software release. + + +Changes between V6.1.0 and V6.1.1 released January 14 2011 + + + Added two new Windows simulator ports. One uses the free Microsoft Visual + Studio 2010 express edition, and the other the free MingW/Eclipse + environment. Demo projects are provided for both. + + Added three demo projects for the PSoC 5 (CYAC5588). These are for the + GCC, Keil, and RVDS build tools, and all use the PSoC Creator IDE. + + Added a demo for the low power STM32L152 microcontroller using the IAR + Embedded Workbench. + + Added a new port for the MSP430X core using the IAR Embedded Workbench. + + Updated all the RX62N demo projects that target the Renesas Demonstration + Kit (RDK) to take into account the revered LED wiring on later hardware + revisions, and the new J-Link debug interface DLL. + + Updated all the RX62N demo projects so the IO page served by the example + embedded web server works with all web browsers. + + Updated the Red Suite projects to work with the up coming Red Suite + release, and to use a more recent version of the CMSIS libraries. + + Added the traceTAKE_MUTEX_RECURSIVE_FAILED() trace macro. + + Removed the (pointless) parameter from the traceTASK_CREATE_FAILED() + trace macro. + + Introduced the portALT_GET_RUN_TIME_COUNTER_VALUE() macro to compliment + the already existing portGET_RUN_TIME_COUNTER_VALUE(). This allows for + more flexibility in how the time base for the run time statistics feature + can be implemented. + + Added a "cpsie i" instruction before the "svc 0" instruction used to start + the scheduler in each of the Cortex M3 ports. This is to ensure that + interrupts are globally enabled prior to the "svc 0" instruction being + executed in cases where interrupts are left disabled by the C start up + code. + + Slight optimisation in the run time stats calculation. + +Changes between V6.0.5 and V6.1.0 released October 6 2010 + + + Added xTaskGetTickCountFromISR() function. + + Modified vTaskSuspend() to allow tasks that have just been created to be + immediately suspended even when the kernel has not been started. This + allows them to effectively start in the Suspended state - a feature that + has been asked for on numerous occasions to assist with initialisation + procedures. + + Added ports for the Renesas RX62N using IAR, GCC and Renesas tool suites. + + Added a STM32F103 demo application that uses the Rowley tools. + + Under specific conditions xFreeBytesRemaining within heap_2.c could end up + with an incorrect value. This has been fixed. + + xTaskCreateGeneric() has a parameter that can be used to pass the handle + of the task just created out to the calling task. The assignment to this + parameter has been moved to ensure it is assigned prior to the newly + created having any possibility of executing. This takes into account the + case where the assignment is made to a global variable that is accessed by + the newly created task. + + Fixed some build time compiler warnings in various FreeTCPIP (based on + uIP) files. + + Fixed some build time compiler warnings in Demo/Common/Minimal/IntQueue.c. + +Changes between V6.0.4 and V6.0.5 released May 17 2010 + + + Added port and demo application for the Cortus APS3 processor. + +Changes between V6.0.3 and V6.0.4 released March 14 2010 + + + All the contributed files that were located in the Demo/Unsupported_Demos + directory have been removed. These files are instead now available in the + new Community Contributions section of the FreeRTOS website. See + https://www.FreeRTOS.org/RTOS-contributed-ports.html + + The project file located in the Demo/CORTEX_STM32F107_GCC_Rowley directory + has been upgraded to use V2.x of the Rowley Crossworks STM32 support + package. + + An initial Energy Micro EFM32 demo has been included. This will be + updated over the coming months to make better use of the low power modes + the EFM32 provides. + +Changes between V6.0.2 and V6.0.3 released February 26 2010 + + + SuperH SH7216 (SH2A-FPU) port and demo application added. + + Slight modification made to the default implementation of + pvPortMallocAligned() and vPortFreeAligned() macros so by default they + just call pvPortMalloc() and vPortFree(). The macros are only needed to + be defined when a memory protection unit (MPU) is being used - and then + only depending on other configuration settings. + +Changes between V6.0.1 and V6.0.2 released January 9th 2010 + + + Changed all GCC ARM 7 ports to use 0 as the SWI instruction parameter. + Previously the parameter was blank and therefore only an implicit 0 but + newer GCC releases do not permit this. + + Updated IAR SAM7S and SAM7X ports to work with IAR V5.40. + + Changed the stack alignment requirement for PIC32 from 4 bytes to 8 bytes. + + Updated prvListTaskWithinSingleList() is it works on processors where the + stack grows up from low memory. + + Corrected some comments. + + Updated the startup file for the RVDS LPC21xx demo. + +Changes between V6.0.0 and V6.0.1 released November 15th 2009 + + + Altered pxPortInitialiseStack() for all Cortex-M3 ports to ensure the + stack pointer is where the compiler expects it to be when a task first + starts executing. + + The following minor changes only effect the Cortex-M3 MPU port: + + + portRESET_PRIVILEGE() assembly macro updated to include a clobber list. + + Added prototypes for all the privileged function wrappers to ensure no + compile time warnings are generated no matter what the warning level + setting. + + Corrected the name of portSVC_prvRaisePrivilege to + portSVC_RAISE_PRIVILEGE. + + Added conditional compilation into xTaskGenericCreate() to prevent some + compilers issuing warnings when portPRIVILEGE_BIT is defined as zero. + + +Changes between V5.4.2 and V6.0.0 released October 16th 2009 + + FreeRTOS V6 is backward compatible with FreeRTOS V5.x. + + Main changes: + + + FreeRTOS V6 is the first version to include memory protection unit (MPU) + support. Two ports now exist for the Cortex M3, the standard FreeRTOS + which does not include MPU support, and FreeRTOS-MPU which does. + + xTaskCreateRestricted() and vTaskAllocateMPURegions() API functions added + in support of FreeRTOS-MPU. + + Wording for the GPL exception has been (hopefully) clarified. Also the + license.txt file included in the download has been fixed (the previous + version contained some corruption). + + Other changes: + + + New API function xPortGetFreeHeapSize() added to heap_1.c and heap_2.c. + + ARM7 GCC demo interrupt service routines wrappers have been modified to + call the C portion using an __asm statement. This prevents the function + call being inlined at higher optimisation levels. + + ARM7 ports now automatically set the THUMB bit if necessary when + setting up the initial stack of a task - removing the need for + THUMB_INTERWORK to be defined. This also allows THUMB mode and ARM mode + tasks to be mixed more easily. + + All ARM7/9 ports now have portBYTE_ALIGNMENT set to 8 by default. + + Various demo application project files have been updated to be up to date + with the latest IDE versions. + + The linker scripts used with command line GCC demos have been updated to + include an eh_frame section to allow their use with the latest Yagarto + release. Likewise the demo makefiles have been updated to include + command line options to reduce or eliminate the eh_frame section all + together. + + The definition of portBYTE_ALIGNMENT_MASK has been moved out of the + various memory allocation files and into the common portable.h header + file. + + Removed unnecessary use of portLONG, portSHORT and portCHAR. + + Added LM3Sxxxx demo for Rowley CrossWorks. + + Posix simulator has been upgraded - see the corresponding WEB page on the + FreeRTOS.org site. + + +Changes between V5.4.1 and V5.4.2 released August 9th 2009 + + + Added a new port and demo app for the Altera Nios2 soft core. + + Added LPC1768 demo for IAR. + + Added a USB CDC demo to all LPC1768 demos (Code Red, CrossWorks and IAR). + + Changed clock frequency of LPC1768 demos to 99MHz. + +Changes between V5.4.0 and V5.4.1 released July 25th 2009 + + + New hook function added. vApplicationMallocFailedHook() is (optionally) + called if pvPortMalloc() returns NULL. + + Additional casting added to xTaskCheckForTimeOut(). This prevents + problems that can arise should configUSE_16_BIT_TICKS be set to 1 on a + 32 bit architecture (which would probably be a mistake, anyway). + + Corrected the parameter passed to NVIC_SetPriority() to set the MAC + interrupt priority in both LPC1768 demos. + + Decreased the default setting of configMINIMAL_STACK_SIZE in the PIC32 + demo application to ensure the heap space was not completely consumed + before the scheduler was started. + +Changes between V5.3.1 and V5.4.0 released July 13th 2009 + + + Added Virtex5 / PPC440 port and demos. + + Replaced the LPC1766 Red Suite demo with an LPC1768 Red Suite demo. The + original demo was configured to use engineering samples of the CPU. The + new demo has an improved Ethernet driver. + + Added LPC1768 Rowley demo with zero copy Ethernet driver. + + Reworked byte alignment code to ensure 8 byte alignment works correctly. + + Set configUSE_16_BIT_TICKS to 0 in the PPC405 demo projects. + + Changed the initial stack setup for the PPC405 to ensure the small data + area pointers are setup correctly. + +Changes between V5.3.0 and V5.3.1 released June 21st 2009 + + + Added ColdFire V1 MCF51CN128 port and WEB server demo. + + Added STM32 Connectivity Line STM32107 Cortex M3 WEB server demo. + + Changed the Cortex M3 port.c asm statements to __asm so it can be + compiled using Rowley CrossWorks V2 in its default configuration. + + Updated the Posix/Linux simulator contributed port. + +Changes between V5.2.0 and V5.3.0 released June 1st 2009 + + Main changes: + + + Added new (optional) feature that gathers statistics on the amount of CPU + time used by each task. + + Added a new demo application for the Atmel AT91SAM3U Cortex-M3 based + microcontroller. + + Added a new demo application for the NXP LPC1766 Cortex-M3 based + microcontroller. + + Added a contributed port/demo that allows FreeRTOS to be 'simulated' in a + Linux environment. + + Minor changes: + + Updated the Stellaris uIP WEB server demos to include the new run time + statistics gathering feature - and include a served WEB page that + presents the information in a tabular format. + + Added in the lwIP port layer for the Coldfire MCF52259. + + Updated the CrossWorks LPC2368 WEB server to include an image in the + served content. + + Changed some of the timing in the initialisation of the LPC2368 MAC to + permit its use on all part revisions. + + Minor modifications to the core uIP code to remove some compiler warnings. + + Added xTaskGetApplicationTaskTag() function and updated the OpenWatcom + demo to make use of the new function. + + Added contributed demos for AVR32 AP7000, STM32 Primer 2 and STM32 using + Rowley Crossworks. + + Heap_1.c and Heap_2.c used to define structures for the purpose of data + alignment. These have been converted to unions to save a few bytes of + RAM that would otherwise be wasted. + + Remove the call to strncpy() used to copy the task name into the TCB when + the maximum task name is configured to be 1 byte long. + +Changes between V5.1.2 and V5.2.0 released March 14th 2009 + + + Optimised the queue send and receive functions (also used by semaphores). + + Replaced the standard critical sections used to protect BIOS calls in the + PC port to instead use scheduler locks. This is because the BIOS calls + always return with interrupts enabled. + + Corrected unclosed comments in boot.s. + +Changes between V5.1.1 and V5.1.2 released February 9th 2009 + + + Added NEC V850ES port and demo. + + Added NEC 78K0R port and demo. + + Added MCF52259 port and demo. + + Added the AT91SAM9XE port and demo. + + Updated the MCF52233 FEC driver to work around a silicon bug that + prevents the part auto negotiating some network parameters. + + Minor modifications to the MCF52233 makefile to permit it to be used + on Linux hosts. + + Updated the STM32 primer files to allow them to be built with the latest + version of the RIDE tools. + + Updated the threads.js Java script used for kernel aware debugging in + the Rowley CrossWorks IDE. + + +Changes between V5.1.0 and V5.1.1 released November 20, 2008 + + + Added Coldfire MCF52233 WEB server demo using GCC and Eclipse. + + Added IAR MSP430 port and demo. + + Corrected several compiler time issues that had crept in as tool versions + change. + + Included FreeRTOS-uIP - a faster uIP. This is not yet complete. + +Changes between V5.0.4 and V5.1.0 released October 24, 2008 + + + Added a new port and demo application for the ColdFire V2 core using the + CodeWarrior development tools. + + Replaced the ARM7 demo that used the old (and now no longer supported) + Keil compiler with a new port that uses the new Keil/RVDS combo. + + Stack overflow checking now works for stacks that grow up from low + memory (PIC24 and dsPIC). + + BUG FIX - set the PIC32 definition of portSTACK_GROWTH to the correct + value of -1. + + MSP430 port layers have been updated to permit tasks to place the + microcontroller into power down modes 1 to 3. The demo applications have + likewise been updated to demonstrate the new feature. + + Replaced the two separate MSP430/Rowley port layers with a single and more + flexible version. + + Added more contributed ports, including ports for NEC and SAM9 + microcontrollers. + + Changed the linker script used in the LPC2368 Eclipse demo. + +Changes between V5.0.3 and V5.0.4 released September 22, 2008 + + + Completely re-written port for ColdFire GCC. + + Bug fix: All Cortex M3 ports have a minor change to the code that sets + the pending interrupt. + + Some header files require that FreeRTOS.h be included prior to their + inclusion. #error message have been added to all such header file + informing users to the cause of the compilation error should the headers + not be included in the correct order. + +Changes between V5.0.2 and V5.0.3 released July 31, 2008 + + Changes relating to the Cortex M3: + + + Added configMAX_SYSCALL_INTERRUPT_PRIORITY usage to all the Cortex M3 + ports and demos. See the port documentation pages on the FreeRTOS.org + WEB site for full usage information. + + Improved efficiency of Cortex M3 port even further. + + Ensure the Cortex M3 port works no matter where the vector table is + located. + + Added the IntQTimer demo/test tasks to a demo project for each CM3 port + (Keil, GCC and IAR) to test the new configMAX_SYSCALL_INTERRUPT_PRIORITY + functionality. + + Added the mainINCLUDE_WEB_SERVER definition to the LM3SXXXX IAR and Keil + projects to allow the WEB server to be conditionally excluded from the + build and therefore allow use of the KickStart (code size limited) + compiler version. + + Other changes: + + + Moved the PIC24 and dsPIC versions of vPortYield() from the C file to + an assembly file to allow use with all MPLAB compiler versions. This also + allows the omit-frame-pointer optimisation to be turned off. + +Changes between V5.0.0 and V5.0.2 released May 30, 2008 + + + Updated the PIC32 port to allow queue API calls to be used from + interrupts above the kernel interrupt priority, and to allow full + interrupt nesting. Task stack usages has also been reduced. + + Added a new PowerPC port that demonstrates how the trace macros can be + used to allow the use of a floating point co-processor. The + traceTASK_SWITCHED_OUT() and traceTASK_SWITCHED_INT() macros are used to + save and restore the floating point context respectively for those tasks + that actually use floating point operations. + + BUG FIX: The first PPC405 port contained a bug in that it did not leave + adequate space above the stack for the backchain to be saved when a task + started to execute for the first time. + + Updated queue.c to add in the means to allow interrupt nesting and for + queue API functions to be called from interrupts that have a priority + above the kernel priority. This is only supported on PIC32 ports thus + far. + + Fixed the compiler warnings that were generated when the latest version + of WinAVR was used. + + Remove all inline usage of 'inline' from the core kernel code. + + Added the queue registry feature. The queue registry is provided as a + means for kernel aware debuggers to locate queue definitions. It has no + purpose unless you are using a kernel aware debugger. The queue registry + will only be used when configQUEUE_REGISTRY_SIZE is greater than zero. + + Added the ST Cortex-M3 drivers into the Demo/Common/Drivers directory to + prevent them from having to be included in multiple demos. + + Added a Keil STM32 demo application. + + Changed the blocktim.c test files as it is no longer legitimate for all + ports to call queue API functions from within a critical section. + + Added the IntQueue.c test file to test the calling of queue API functions + from different interrupt priority levels, and test interrupt nesting. + +Changes between V5.0.0 and V5.0.1 + + + V5.0.1 was a customer specific release. + +Changes between V4.8.0 and V5.0.0 released April 15, 2008 + + *** VERY IMPORTANT INFORMATION ON UPGRADING TO FREERTOS.ORG V5.0.0 *** + + The parameters to the functions xQueueSendFromISR(), xQueueSendToFrontFromISR(), + xQueueSendToBackFromISR() and xSemaphoreGiveFromISR() have changed. You must + update all calls to these functions to use the new calling convention! Your + compiler might not issue any type mismatch warnings! + + + Other changes: + + + Support added for the new Luminary Micro LM3S3768 and LM3S3748 Cortex-M3 + microcontrollers. + + New task hook feature added. + + PowerPC demo updated to use version 10.1 of the Xilinx EDK. + + Efficiency gains within the PIC32 port layer. + +Changes between V4.7.2 and V4.8.0 released March 26 2008 + + + Added a Virtex4 PowerPC 405 port and demo application. + + Added optional stack overflow checking and new + uxTaskGetStackHighWaterMark() function. + + Added new xQueueIsQueueEmptyFromISR(), xQueueIsQueueFullFromISR() and + uxQueueMessagesWaitingFromISR() API functions. + + Efficiency improvements to the Cortex-M3 port layer. NOTE: This + requires that an SVC handler be installed in the application. + + Efficiency improvements to the queue send and receive functions. + + Added new trace macros. These are application definable to provide + a flexible trace facility. + + Implemented the configKERNEL_INTERRUPT_PRIORITY within the Keil Cortex + M3 port layer (bringing it up to the same standard as the IAR and GCC + versions). + + Ports that used the arm-stellaris-eabi-gcc tools have been converted to + use the arm-non-eabi-gcc tools. + +Changes between V4.7.1 and V4.7.2 released February 21, 2008 + + + Added Fujitsu MB91460 port and demo. + + Added Fujitsu MB96340 port and demo. + + Tidied up the capitalisation of include files to facilitate builds on + Linux hosts. + + Removed some redundant casting that was generating warnings - but was + included to remove warnings on other compilers. + +Changes between V4.7.0 and V4.7.1 released February 3, 2008 + + + Updated all IAR ARM projects to use V5.11 of the IAR Embedded Workbench + for ARM. + + Introduced recursive semaphore feature. + + Updated LPC2368 demos to take into account silicon bugs in old chip + revisions. + + Updated STR9 uIP port to manually set the net mask and gateway addresses. + + Updating demos to allow more to run with the co-operative scheduler. + + Fixed co-operative scheduler behaviour upon the occurrence of a tick + interrupt while the scheduler was suspended. + + Updated documentation contained within semphr.h. + + ARM7 GCC ports no longer use the IRQ attribute. + +Changes between V4.6.1 and V4.7.0 released December 6, 2007 + + + Introduced the counting semaphore macros and demo source files. The + Open Watcom PC project has been updated to include the new demo. See + the online documentation for more information. + + Introduced the 'alternative' queue handling API and demo source files. + The Open Watcom PC project has been updated to include the new demo + source files. See the online documentation for more information. + + Added AT91SAM7X Eclipse demo project. + + Added the STM32 primer demo project for the GCC compiler and Ride IDE. + + Removed the .lock files that were mistakenly included in the V4.6.1 + eclipse workspaces. + +Changes between V4.6.0 and V4.6.1 released November 5 2007 + + + Added support for the MIPS M4K based PIC32. + + Added 'extern "C"' to all the header files to facilitate use with C++. + +Changes between V4.5.0 and V4.6.0 released October 28 2007 + + + Changed the method used to force a context switch within an ISR for the + ARM7/9 GCC ports only. The portENTER_SWITCHING_ISR() and + portEXIT_SWITCHING_ISR() macros are no longer supported. This is to + ensure correct behaviour no matter which GCC version is used, with or + without the -fomit-frame-pointer option, and at all optimisation levels. + + Corrected the prototype for xQueueGenericSend() within queue.h. + +Changes between V4.4.0 and V4.5.0 released September 17 2007 + + + Added the xQueueSendToFront(), xQueueSendToBack() and xQueuePeek() + functionality. These should now be used in preference to the old + xQueueSend() function - which is maintained for backward compatibility. + + Added Mutex functionality. The behaviour of mutexes is subtly different + to the already existing binary semaphores as mutexes automatically + include a priority inheritance mechanism. + + Added the GenQTest.c and QPeek.c to test and demonstrate the behaviour + of the new functionality. + + Updated the LM3Sxxxx and PC ports to include the new GenQTest.c and + QPeek.c files. + + Updated the GCC port for the Cortex M3 to include the + configKERNEL_INTERRUPT_PRIORITY functionality. This was previously only + included in the IAR port. + + Optimised the GCC and IAR port layer code - specifically the context + switch code. + + Consolidated the LM3Sxxxx EK demos for all development tools into a + single project that automatically detects which version of the EK the + application is executing on. + + Added Eclipse support for LM3Sxxxx evaluation kits. + + Added Eclipse support for the Keil LPC2368 evaluation kit. + + Added the Demo/Drivers directory to hold code that is common to multiple + demo application projects. + + Included some minor bug fixes in the uIP 1.0 code. + + Added an lwIP demo for the STR9 - thanks ST for assistance. + + Updated the AVR32 port to ensure correct behaviour with full compiler + optimisation. + + Included binaries for OpenOCD FTDI and parallel port interfaces. + +Changes between V4.4.0 and V4.3.1 released July 31, 2007 + + + Added AVR32 UC3B demo application. + + Updated AVR32 UC3A port and demo applications. + + Added IAR lwIP demo for AVR32 UC3A. + + Updated listGET_OWNER_OF_NEXT_ENTRY() to assist compiler optimisation + (thanks Niu Yong for making the suggestion). + + Added xTaskGetSchedulerState() API function. + + BUG FIX: Corrected behaviour when tasks that are blocked indefinitely + have their block time adjusted (within xQueueSend() and xQueueReceive()), + and are the subject of a call the vTaskResume() when they are not + actually in the Suspended state (thanks Dan Searles for reporting the + issues). + + +Changes between V4.3.0 and V4.3.1 released June 11, 2007 + + + Added STMicroelectronics STM32 Cortex-M3 demo application. + + Updated ustdlib.c for the GCC LM3S6965 demo. + +Changes between V4.2.1 and V4.3.0 released June 5, 2007 + + + Introduced configKERNEL_INTERRUPT_PRIORITY to the IAR Cortex-M3, PIC24 + and dsPIC ports. See the LM3S6965 and PIC24 demo application + documentation pages for more information. + + Updated the PIC24 and dsPIC demos to build with V3.0 of the PIC30 GCC + tools, and changed the demo applications. + + Added demos for the new Ethernet and CAN enabled Luminary Micro Stellaris + microcontrollers. + + Corrected bug in uIP the demos that prevented frames of approximately 1480 + bytes and over from being transmitted. + + Included the LPC2368/uIP/Rowley demo into the main FreeRTOS.org + download. + + Update to WizC PIC18 port to permit its use with version 14 of the + compiler. Thanks Marcel! + +Changes between V4.2.1 and V4.2.0 released April 2, 2007 + + + Added AVR32 AT32UC3A ports for GCC and IAR. + + Added -fomit-frame-pointer option to lwIP SAM7X demo makefile. + + Moved location of call to LCD_Init() in STR9 demo to ensure it is only + called after the scheduler has been started. + +Changes between V4.1.3 and V4.2.0 released February 8, 2007 + + + Changes to both task.c and queue.c as a result of testing performed on + the SafeRTOS code base. + + Added Cortex-M3 LM3S811 demos for GCC and IAR tools. + +Changes between V4.1.2 and V4.1.3 released November 19, 2006 + + + Added STR750 ARM7 port using the Raisonance RIDE/GCC tools. + + Added -fomit-frame-pointer option to Rowley ARM7 demos as work around + to GCC bug at some optimisation levels. + + Altered the way the heap is defined in the LM3S811 Keil demo to prevent + the RAM usage from counting toward the code size limit calculation. + + CO-ROUTINE BUG FIX: Removed the call to prvIsQueueEmpty from within + xQueueCRReceive as it exited with interrupts enabled. Thanks Paul Katz. + + Tasks that block on events with a timeout of portMAX_DELAY are now + blocked indefinitely if configINCLUDE_vTaskSuspend is defined. + Previously portMAX_DELAY was just the longest block time possible. This + is still the case if configINCLUDE_vTaskSuspend is not defined. + + Minor changes to some demo application files. + +Changes between V4.1.1 and V4.1.2 released October 21, 2006 + + + Added 16bit PIC ports and demos. + + Added STR750 port and demo. + + +Changes between V4.1.0 and V4.1.1 released September 24, 2006 + + + Added the Luminary Micro Stellaris LM3S811 demo application. + +Changes between V4.0.5 and V4.1.0 released August 28, 2006 + + + Prior to V4.1.0, under certain documented circumstances, it was possible + for xQueueSend() and xQueueReceive() to return without having completed + and without their block time expiring. The block time effectively + stated a maximum block time, and the return value of the function needed + to be checked to determine the reason for returning. This is no longer + the case as the functions will only return once the block time has + expired or they are able to complete their operation. It is therefore no + longer necessary to wrap calls within loops. + + Changed the critical section handling in the IAR AVR port to correct the + behaviour when used with later compiler versions. + + Added the LPC2138 CrossWorks demo into the zip file. Previously this was + only available as a separate download. + + Modified the AVR demo applications to demonstrate the use of co-routines. + +Changes between V4.0.4 and V4.0.5 released August 13, 2006 + + + Introduced API function xTaskResumeFromISR(). Same functionality as + xTaskResume(), but can be called from within an interrupt service routine. + + Optimised vListInsert() in the case when the wake time is the maximum + tick count value. + + Bug fix: The 'value' of the event list item is updated when the priority + of a task is changed. Previously only the priority of the TCB itself was + changed. + + vTaskPrioritySet() and vTaskResume() no longer use the event list item. + This has not been necessary since V4.0.1 when the xMissedYield handling + was added. + + Lowered the PCLK setting on the ARM9 STR9 demo from 96MHz to 48MHz. + + When ending the scheduler - do not try to attempt a context switch when + deleting the current task. + + SAM7X EMAC drivers: Corrected the Rx frame length mask when obtaining + the length from the rx descriptor. + + +Changes between V4.0.3 and V4.0.4 released June 22, 2006 + + + Added a port and demo application for the STR9 ARM9 based processors from + ST. + + Slight optimisation to the vTaskPrioritySet() function. + + Included the latest uIP version (1.0) in the demo/common/ethernet + directory. + +Changes between V4.0.2 and V4.0.3 released June 7, 2006 + + + Added a port and demo application for the Cortex-M3 target using the IAR + development tools. + + The ARM Cortex-m3 Rowley projects have been updated to use V1.6 of the + CrossStudio tools. + + The heap size defined for the lwIP Rowley demo has been reduced so that + the project will link correctly when using the command line GCC tools + also. The makefile has also been modified to allow debugging. + + The lwIP Rowley demo not includes a 'kernel aware' debug window. + + The uIP Rowley project has been updated to build with V1.6 of CrossWorks. + + The second set of tasks in the blockQ demo were created the wrong way + around (inconsistent to the description in the file). This has been + corrected. + +Changes between V4.0.1 and V4.0.2 released May 28, 2006 + + + Port and demo application added for the Tern Ethernet Engine controller. + + Port and demo application added for MC9S12 using GCC, thanks to + Jefferson "imajeff" Smith. + + The function vTaskList() now suspends the scheduler rather than disabling + interrupts during the creation of the task list. + + Allow a task to delete itself by passing in its own handle. Previously + this could only be done by passing in NULL. + + Corrected the value passed to the WDG_PeriodValueConfig() library + function in the STR71x demo. + + The tick hook function is now called only within a tick isr. Previously + it was also called when the tick function was called during the scheduler + unlocking process. + + The EMAC driver in the SAM7X lwIP demo has been made more robust as per + the thread: https://sourceforge.net/forum/message.php?msg_id=3714405 + + In the PC ports: Add function prvSetTickFrequencyDefault() to set the + DOS tick back to its proper value when the scheduler exits. Thanks + Raynald! + + In the Borland x86 ports there was a mistake in the portFIRST_CONTEXT + macro where the BP register was not popped from the stack correctly. The + BP value would never get used so this did not cause a problem, but it has + been corrected all the same. + + +Changes between V4.0.0 and V4.0.1 released April 7 2006 + + + Improved the ARM CORTEX M3 ports so they now only have to service + pendSV interrupts. + + Added a Luminary Micro port and demo for use with Rowley CrossWorks. + + Added the xMissedYield handling to tasks.c. + +Changes between V3.2.4 and V4.0.0 + + Major changes: + + + Added new RTOS port for Luminary Micros ARM CORTEX M3 microcontrollers. + + Added new co-routine functionality. + + Other kernel changes: + + + An optional tick hook call is now included in the tick function. + + Introduced the xMiniListItem structure and removed the list pxHead + member in order to reduce RAM usage. + + Added the following definitions to the FreeRTOSConfig.h file included + with every port: + configUSE_TICK_HOOK + configUSE_CO_ROUTINES + configMAX_CO_ROUTINE_PRIORITIES + + The volatile qualification has been changed on the list members to allow + the task.c code to be tidied up a bit. + + The scheduler can now be started even if no tasks have been created! + This is to allow co-routines to run when there are no tasks. + + A task being woken by an event will now preempt the currently running task + even if its priority is only equal to the currently running task. + + Port and demo application changes: + + + Updated the WinAVR demo to compile with the latest version of WinAVR + with no warnings generated. + + Changed the WinAVR makefile to make chars signed - needed for the + co-routine code if BaseType_t is set to char. + + Added new demo application file crflash.c. This demonstrates co-routine + functionality including passing data between co-routines. + + Added new demo application file crhook.c. This demonstrates co-routine + and tick hook functionality including passing data between and ISR and + a co-routine. + + Some NOP's were missing following stmdb{}^ instructions in various ARM7 + ports. These have been added. + + Updated the Open Watcom PC demo project to include the crflash and crhook + demo co-routines as an example of their use. + + Updated the H8S demo to compile with the latest version of GCC. + + Updated the SAM7X EMAC drivers to take into account the hardware errata + regarding lost packets. + + Changed the default MAC address used by some WEB server demos as the + original addresses used was not liked by some routers. + + Modified the SAM7X/IAR startup code slightly to prevent it hanging on + some systems when the code is executed using a j-link debugger. The + j-link macro file configures the PLL before the code executes so + attempting to configure it again in the startup code was causing a + problem for some user. Now a check is performed first to see if the + PLL is already set up. + + GCC port now contain all assembler code in a single asm block rather than + individual blocks as before. + + GCC LPC2000 code now explicitly uses R0 rather than letting the assembler + choose the register to use as a temporary register during the context + switch. + + Added portNOP() macro. + + The compare match load value on LPC2000 ports now has 1 added to correct + the value used. + + The minimal stack depth has been increased slightly on the WIZC PIC18 + port. + +Changes between V3.2.3 and V3.2.4 + + + Modified the GCC ARM7 port layer to allow use with GCC V4.0.0 and above. + Many thanks to Glen Biagioni for the provided update. + + Added a new Microblaze port and demo application. + + Modified the SAM7X EMAC demo to default to use the MII interface rather + than the RMII interface. + + Modified the startup sequence of the SAM7X demo slightly to allow the + EMAC longer to auto negotiate. + +Changes between V3.2.2 and V3.2.3 + + + Added MII interface support to the SAM7X EMAC peripheral driver. + Previously versions worked with the RMII interface only. + + Added command line GCC support to the SAM7X lwIP demo. Previously the + project could only be built using the CrossWorks IDE. Modifications to + this end include the addition of a standard makefile and linker script to + the download, and some adjustments to the stacks allocated to each task. + + Changed the page returned by the lwIP WEB server demo to display the + task status table rather than the TCP/IP statistics. + + Corrected the capitalisation of some header file includes and makefile + dependencies to facilitate use on Linux host computers. + + The various LPC2000 ports had a mistake in the timer setup where the + prescale value was written to T0_PC instead of T0_PR. This would have + no effect unless a prescale value was actually required. This has been + corrected. + +Changes between V3.2.1 and V3.2.2 - Released 23 September, 2005 + + + Added an IAR port for the Philips LPC2129 + + The Atmel ARM7 IAR demo project files are now saved in the IAR Embedded + Workbench V4.30a format. + + Updated the J-Link macro file included with the SAM7X uIP demo project + to allow the demo board to be reset over the J-Link. + +Changes between V3.2.0 and V3.2.1 - Released 1 September, 2005 + + + Added lwIP demo for AT91SAM7X using Rowley tools. + + Added uIP demo for AT91SAM7X using IAR tools. + + Added function xTaskGetCurrentTaskHandle(). + + Renamed events.h to mevents.h to prevent it conflicting with the events.h + generated automatically by the HCS12 processor expert utility. events.h + is only used by the PC demo application. + + Both PIC18 ports now initialise the TBLPTRU to 0 as this is the value + expected by the compiler, and the compilers do not write to this + register. + + The HCS12 banked model demo now creates the 'suicide' tasks immediately + prior to starting the scheduler. These tasks should be the last tasks to + get started in order for the test to function correctly. + +Changes between V3.1.1 and V3.2.0 - Released 29 June, 2005 + + V3.2.0 introduces two new MSP430 ports and corrects a minor kernel + issues. Thanks to Ares.qi for his input. + + + Added two MSP430 ports that use the Rowley CrossWorks development tools. + One port just mirrors the existing GCC port. The other port was provided + by Milos Prokic. Thanks! + + V3.2.0 corrects the behavior when vTaskPrioritySet() or vTaskResume() + are called while the scheduler is locked (by a call to + vTaskSuspendAll()). When this is done the subject task now starts to + execute immediately when the scheduler is unlocked if it has the highest + priority that is ready to run. Previously there was a possibility that + the task would not run until the next RTOS tick or call to portYIELD(). + + Another similar small correction ensures that in the case where more than + one task is blocked on a semaphore or queue, the task with the highest + priority is guaranteed to be unblocked first. + + Added a couple of more test tasks to the PC demo which cover the points + above. + +Changes between V3.1.0 and V3.1.1 - Released 21st June, 2005 + + This release updates the HCS12 port. The common kernel code + remains unchanged. + + + Updated the HCS12 port to support banking and introduced a demo + application for the MC9S12DP256. The new demo application is + located in the Demo/HCS12_CodeWarrior_banked directory. + + The name of the directory containing the MC9S12F32 demo application + has been changed to Demo/HCS12_CodeWarrior_small (as in 'small' + memory model). + + MC9S12F32 demo updated slightly to use the PLL. The CPU speed for the + demo application is now 24MHz. Previously it was 8MHz. + + The demo application file Demo/Common/Minimal/death.c has a slight + alteration to prevent it using floating point variables. + + +Changes between V3.0.0 and V3.1.0 - Released 11th June, 2005 + + + Added new ports for ST Microsystems STR71x, and Freescale HCS12 + microcontrollers. Currently the HCS12 port is limited to the small + memory model. Large memory models will be supported in the next + release. + + PIC18 wizC port updated. Thanks to Marcel van Lieshout for his + continuing contribution. + + The accuracy of the AVR port timer setup has been improved. Thanks to + Thomas Krutmann for this contribution. + + Added a new conditional compilation macro configIDLE_SHOULD_YIELD. + See the WEB documentation for details. + + Updated the CrossWorks uIP demo to build with V1.4 of CrossWorks. + + Slight modification to the SAM7 release build configuration to correct + an include path definition. + + Updated the MPLAB PIC18 documentation to provide extra details on linker + file configuration. + +Changes between V3.0.0 and V2.6.1 - Released 23rd April, 2005 + + V3.0.0 includes many enhancements, so this history list is broken into + subsections as follows: + + API changes + New ports + Directory name changes + Kernel and miscellaneous changes changes + + - API changes + + + Each port now defines BaseType_t as the data type that is most + efficient for that architecture. The type BaseType_t is used + extensively in API calls necessitating the following changes to the + FreeRTOS API function prototypes. + + See the "New for V3.0.0" section of the FreeRTOS online + documentation for full details of API changes. + + - New ports + + + The AT91FR40008 ARM7 port contributed by John Feller is now included + in the download (thanks John!). + + The PIC18 port for the wizC/fedC compiler contributed by Marcel van + Lieshout is now included in the download (thanks Marcel!). + + The IAR port for the AVR microcontroller has been upgraded to V3.0.0 + and is now a supported port. + + - Directory name changes + + For consistency, and to allow integration of the new ports, the + following directory names have been changed. + + + The source/portable/GCC/ARM7 directory has been renamed + source/portable/GCC/ARM7_LPC2000 so it is compatible with the naming + of other GCC ARM7 ports. + + The Demo/PIC directory has been renamed Demo/PIC18_MPLAB to + accommodate the wizC/fedC PIC port. + + The demo applications for the two AVR ports no longer share the same + directory. The WinAVR demo is in the Demo/AVR_ATMega323_WinAVR + directory and the IAR port in the Demo/AVR_ATMega323_IAR directory. + + + - Kernel and miscellaneous changes changes + + See the "New for V3.0.0" section of the FreeRTOS online + documentation for more information. + + + Previously 'portmacro.h' contained some user editable definitions + relating to the user application, and some fixed definitions relating + specifically to the port being used. The application specific + definitions have been removed from 'portmacro.h' and placed inside a + new header file called 'FreeRTOSConfig.h'. 'portmacro.h' should now + never be modified by the user. A 'FreeRTOSConfig.h' is now included + in each of FreeRTOS/Demo subdirectories - as it's settings relate to + the demo application rather than being specific to the port. + + Introduced configUSE_IDLE_HOOK in idle task. + + The idle task will yield when another idle priority task is ready to + run. Previously the idle task would run to the end of its time slice + regardless. + + The idle task is now created when the scheduler is started. This + requires less stack than the previous scheme where it was created upon + creation of the first application task. + + The function usPortCheckFreeStackSpace() has been renamed + usTaskCheckFreeStackSpace() and moved from the portable layer to + tasks.c. + + Corrected spelling of portMINMAL_STACK_SIZE to portMINIMAL_STACK_SIZE. + + The portheap.c file included with the AVR port has been deleted. The + AVR demo now uses the standard heap1 sample memory allocator. + + The GCC AVR port is now build using the standard make utility. The + batch files used previously have been deleted. This means a recent + version of WinAVR is required in order to create a binary suitable for + source level debugging. + + vTaskStartScheduler() no longer takes the configUSE_PREEMPTION + constant as a parameter. Instead the constant is used directly within + tasks.c and no parameter is required. + + The header file 'FreeRTOS.h' has been created and is used to include + 'projdefs.h', 'FreeRTOSConfig.h' and 'portable.h' in the necessary + order. FreeRTOS.h can now be included in place of these other + headers. + + The header file 'errors.h' has been deleted. The definitions it + contained are now located within 'projdefs.h'. + + pvPortMalloc() now takes a size_t parameter as per the ANSI malloc(). + Previously an unsigned short was used. + + When resuming the scheduler a yield is performed if either a tick has + been missed, or a task is moved from the pending ready list into a + ready list. Previously a yield was not performed on this second + condition. + + In heap1.c an overflow check has been added to ensure the next free + byte variable does not wrap around. + + Introduced the portTASK_FUNCTION() and portTASK_FUNCTION_PROTO() + macros. + + The MPLAB PIC port now saved the TABLAT register in interrupt service + routines. + +Changes between V2.6.0 and V2.6.1 - Released Feb 22, 2005 + + This version adds support for the H8 processor. + + Other changes: + + + tskMAX_TASK_NAME_LEN removed from the task.h header and added to each + individual portmacro.h file as portMAX_TASK_NAME_LEN. This allows RAM + limited ports to allocate fewer characters to the task name. + + AVR port - Replaced the inb() and outb() functions with direct memory + access. This allows the port to be built with the 20050414 build of + WinAVR. + + GCC LPC2106 port - removed the 'static' from the definition of + vNonPreemptiveTick() to allow the demo to link when using the cooperative + scheduler. + + GCC LPC2106 port - Corrected the optimisation options in the batch files + ROM_THUMB.bat, RAM_THUMB.bat, ROM_ARM.bat and RAM_ARM.bat. The lower case + -o is replaced by an uppercase -O. + + Tasks.c - The strcpy call has been removed when copying across the task + name into the TCB. + + Updated the trace visualisation to always be 4 byte aligned so it can be + used on ARM architectures. + + There are now two tracecon executables (that convert the trace file binary + into an ASCII file). One for big endian targets and one for little endian + targets. + + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called + too often in the idle task. + + SAM7 USB driver - Replaced the duplicated RX_DATA_BK0 in the interrupt + mask with the RX_DATA_BK1. + + +Changes between V2.5.5 and V2.6.0 - Released January 16, 2005 + + + Added the API function vTaskDelayUntil(). The demo app file + Demo/Common/Minimal/flash.c has been updated to demonstrate its use. + + Added INCLUDE_vTaskDelay conditional compilation. + + Changed the name of the Demo/ARM7_AtmelSAM7S64_IAR directory to + Demo/ARM7_AT91SAM7S64_IAR for consistency. + + Modified the AT91SAM7S USB driver to allow descriptors that have + a length that is an exact multiple of the FIFO to be transmitted. + +Changes between V2.5.4 and V2.5.5 - Released January 3, 2005 + + This version adds support for the Atmel SAM7 ARM7 microcontrollers + along with the IAR development tools. + + Other changes: + + + Renamed the Demo/ARM7 directory to Demo/ARM7_LPC2106_GCC. + + Renamed the Demo/ARM7_Keil directory to Demo/ARM7_LPC2129_Keil. + + Modified the Philips ARM7 serial interrupt service routines to only + process one interrupt per call. This seems to enable the ISR to + operate more quickly. + + Removed the 'far' keyword from the Open Watcom portable layer source + files. This allows their use with V1.3 of Open Watcom. + + Minor modifications to the SDCC build files to allow their use under + Linux. Thanks to Frieder Ferlemann for this contribution. + + Small change to sTaskCreate() to allow a context switch even when + pxCreatedTask is NULL. Thanks to Kamil for this contribution. + + inline keyword removed from vTaskSwitchContext() and VTaskIncrementTick() + definitions. + +Changes between V2.5.3 and V2.5.4 - Released Dec 1, 2004 + + This is an important maintenance release. + + The function cTaskResumeAll() has been modified so it can be used safely + prior to the kernel being initialised. This was an issue as + cTaskResumeAll() is called from pvPortMalloc(). Thanks to Daniel Braun + for highlighting this issue. + +Changes between V2.5.2 and V2.5.3 - Released Nov 2, 2004 + + The critical section handling functions have been changed for the GCC ARM7 + port. Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and are + instead now stored in a variable, which is then saved as part of the + tasks context. This allows the GCC ARM7 port to be used at all + optimisation levels - including -Os. + + Other minor changes: + + + MSP430 definition of usCriticalNesting now uses the volatile qualifier. + This is probably not required but added just in case. + +Changes between V2.5.1 and V2.5.2 - Released Oct 26, 2004 + + + Added the Keil ARM7 port. + + Slight modification to comtest.c to make the delay periods more random. + This creates a better test condition. + +Changes between V2.5.0 and V2.5.1 - Released Oct 9, 2004 + + + Added the MSP430 port. + + Extra comments added to the GCC ARM7 port.c and portISR.c files. + + The memory pool allocated within heap_1.c has been placed within a + structure to ensure correct memory alignment on 32bit systems. + + Within the GCC ARM7 serial drivers an extra check is made to ensure + the post to the queue was successful if then attempting immediately + retrieve the posted character. + + Changed the name of the constant portTICKS_PER_MS to portTICK_PERIOD_MS + as the old name was misleading. + + +Changes between V2.4.2 and V2.5.0 - Released Aug 12, 2004 + + The RTOS source code download now includes three separate memory allocation + schemes - so you can choose the most appropriate for your application. + These are found in the Source/Portable/MemMang directory. The demo + application projects have also been updated to demonstrate the new schemes. + See the "Memory Management" page of the API documentation for more details. + + + Added heap_1.c, heap_2.c and heap_3.c in the Source/Portable/MemMang + directory. + + Replaced the portheap.c files for each demo application with one of the + new memory allocation files. + + Updated the portmacro.h file for each demo application to include the + constants required for the new memory allocators: portTOTAL_HEAP_SIZE and + portBYTE_ALIGNMENT. + + Added a new test to the ARM7 demo application that tests the operation + of the heap_2 memory allocator. + + +Changes between V2.4.1 and V2.4.2 - Released July 14, 2004 + + + The ARM7 port now supports THUMB mode. + + Modification to the ARM7 demo application serial port driver. + +Changes between V2.4.0 and V2.4.1 - Released July 2, 2004 + + + Rationalised the ARM7 port version of portEXIT_CRITICAL() - + improvements provided by Bill Knight. + + Made demo serial driver more complete and robust. + + +Changes between V2.4.0 and V2.3.1 - Released June 30, 2004 + + + Added the first ARM7 port - thanks to Bill Knight for the assistance + provided. + + Added extra files to the Demo/Common/Minimal directory. These are + equivalent to their Demo/Common/Full counterparts but with the + calls to the functions defined in print.c removed. + + Added TABLAT to the list of registers saved as part of a PIC18 context. + +Changes between V2.3.0 and V2.3.1 - Released June 25, 2004 + + + Changed the way the vector table is defined to be more portable. + + Corrected the definitions of SPH and SPL in portmacro.s90. + The previous definitions prevented V2.3.0 operating if the iom323.h + header file was included in portmacro.s90. + +Changes between V2.2.0 and V2.3.0 - Released June 19, 2004 + + + Added an AVR port that uses the IAR compiler. + + Explicit use of 'signed' qualifier on plain char types. + + Modified the Open Watcom project files to use 'signed' as the + default char type. + + Changed odd calculation of initial pxTopOfStack value when + portSTACK_GROWTH < 0. + + Added inline qualifier to context switch functions within task.c. + Ports that do not support the (non ANSI) inline keyword have the + inline #define'd away in their respective portmacro.h files. + +Changes between V2.1.1 and V2.2.0 - Released May 18, 2004 + + + Added Cygnal 8051 port. + + PCLATU and PCLATH are now saved as part of the PIC18 context. This + allows function pointers to be used within tasks. Thanks to Javier + Espeche for the enhancement. + + Minor changes to demo application files to reduce stack usage. + + Minor changes to prevent compiler warnings when compiling the new port. + +Changes between V2.1.0 and V2.1.1 - Released March 12, 2004 + + + Bug fix - pxCurrentTCB is now initialised before the call to + prvInitialiseTaskLists(). Previously pxCurrentTCB could be accessed + while null during the initialisation sequence. Thanks to Giuseppe + Franco for the correction. + +Changes between V2.0.0 and V2.1.0 - Released Feb 29, 2004 + + V2.1.0 has significant reworks that greatly reduce the amount of time + the kernel has interrupts disabled. The first section of modifications + listed here must be taken into account by users. The second section + are related to the kernel implementation and as such are transparent. + + Section1 : + + + The typedef TickType_t has been introduced. All delay times should + now use a variable of type TickType_t in place of the unsigned long's + used previously. API function prototypes have been updated + appropriately. + + The configuration macro USE_16_BIT_TICKS has been introduced. If set + to 1 TickType_t is defined as an unsigned short. If set to 0 + TickType_t is defined as an unsigned long. See the configuration + section of the API documentation for more details. + + The configuration macro INCLUDE_vTaskSuspendAll is now obsolete. + + vTaskResumeAll() has been renamed cTaskResumeAll() as it now returns a + value (see the API documentation). + + ulTaskGetTickCount() has been renamed xTaskGetTickCount() as the type + it returns now depends on the USE_16_BIT_TICKS definition. + + cQueueReceive() must now >never< be used from within an ISR. Use the new + cQueueReceiveFromISR() function instead. + + Section 2: + + + A mechanism has been introduced that allows a queue to be accessed by + a task and ISR simultaneously. + + A "pending ready" queue has been introduced that enables interrupts to + be processed when the scheduler is suspended. + + The list implementation has been improved to provide faster item + removal. + + The scheduler now makes use of the scheduler suspend mechanism in places + where previously interrupts were disabled. + +Changes between V1.2.6 and V2.0.0 - Released Jan 31, 2004 + + + Introduced new API functions: + vTaskPriorityGet () + vTaskPrioritySet () + vTaskSuspend () + vTaskResume () + vTaskSuspendAll () + vTaskResumeAll () + + Added conditional compilation options that allow the components of the + kernel that are unused by an application to be excluded from the build. + See the Configuration section on the WEB site for more information (on + the API pages). The macros have been added to each portmacro.h file ( + sometimes called prtmacro.h). + + Rearranged tasks.c. + + Added demo application file dynamic.c. + + Updated the PC demo application to make use of dynamic.c. + + Updated the documentation contained in the kernel header files. + + Creating a task now causes a context switch if the task being created + has a higher priority than the calling task - assuming the kernel is + running. + + vTaskDelete() now only causes a context switch if the calling task is + the task being deleted. + +Changes between V1.2.5 and V1.2.6 - Released December 31, 2003 + + Barring the change to the interrupt vector (PIC port) these are minor + enhancements. + + + The interrupt vector used for the PIC master ISR has been changed from + 0x18 to 0x08 - where it should have always been. The incorrect address + still works but probably executes a number of NOP's before getting to the + ISR. + + Changed the baud rate used by the AVR demo application to 38400. This + has an error percentage of less than one percent with an 8MHz clock. + + Raised the priority of the Rx task in demo\full\comtest.c. This only + affects the Flashlite and PC ports. This was done to prevent the Rx + buffer becoming full. + + Reverted the Flashlite COM port driver back so it does not use the DMA. + The DMA appears to miss characters under stress. The Borland Flashlite + port was also calculating a register value incorrectly resulting in the + wrong DMA source address being used. The same code worked fine when + compiling with Open Watcom. Other minor enhancements were made to the + interrupt handling. + + Modified the PIC serial Rx ISR to check for and clear overrun errors. + Overrun errors seem to prevent any further characters being received. + + The PIC demo projects now have some optimisation switched on. + + +Changes between V1.2.4 and V1.2.5 + + Small fix made to the PIC specific port.c file described below. + + + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global + interrupt flag setting. Using the two bits defined within + portINITAL_INTERRUPT_STATE was causing the w register to get clobbered + before the test was performed. + +Changes between V1.2.3 and V1.2.4 + + V1.2.4 contains a release version of the PIC18 port. + An optional exception has been included with the GPL. See the licensing + section of www.FreeRTOS.org for details. + + + The function xPortInitMinimal() has been renamed to + xSerialPortInitMinimal() and the function xPortInit() has been renamed + to xSerialPortInit(). + + The function sSerialPutChar() has been renamed cSerialPutChar() and + the function return type chaned to portCHAR. + + The integer and flop tasks now include calls to tskYIELD(), allowing + them to be used with the cooperative scheduler. + + All the demo applications now use the integer and comtest tasks when the + cooperative scheduler is being used. Previously they were only used with + the preemptive scheduler. + + Minor changes made to operation of minimal versions of comtest.c and + integer.c. + + The ATMega port definition of portCPU_CLOSK_HZ definition changed to + 8MHz base 10, previously it base 16. + + + +Changes between V1.2.2a and V1.2.3 + + The only change of any significance is to the license, which has changed + from the Open Software License to the GNU GPL. + + The zip file also contains a pre-release version of the PIC18 port. This + has not yet completed testing and as such does not constitute part of the + V1.2.3 release. It is still however covered by the GNU GPL. + + There are minor source code changes to accommodate the PIC C compiler. + These mainly involve more explicit casting. + + + sTaskCreate() has been modified slightly to make use of the + portSTACK_GROWTH macro. This is required for the PIC port where the + stack grows in the opposite direction to the other existing ports. + + prvCheckTasksWaitingTermination() has been modified slightly to bring + the decrementing of usCurrentNumberOfTasks within the critical section, + where it should have been since the creation of an eight bit port. + +Changes between V1.2.2 and V1.2.2a + + The makefile and buildcoff.bat files included with the AVR demo application + have been modified for use with the September 2003 build of WinAVR. No + source files have changed. + +Changes between V1.2.1 and V1.2.2 + + There are only minor changes here to allow the PC and Flashlite 186 ports + to use the Borland V4.52 compiler, as supplied with the Flashlite 186 + development kit. + + + Introduced a BCC directory under source\portable. This contains all the + files specific to the Borland compiler port. + + Corrected the macro naming of portMS_PER_TICK to portTICKS_PER_MS. + + Modified comtest.c to increase the rate at which the string is + transmitted and received on the serial port. The Flashlite 186 demo + app baud rate has also been increased. + + The values of the constants used in both integer.c files have been + increased to force the Borland compiler to use 32 bit values. The + Borland optimiser placed the previous values in 16 bit registers, and in + So doing invalidated the test. + +Changes between V1.2.0 and V1.2.1 + + This version includes some minor changes to the list implementation aimed + at improving the context switch time - with is now approximately 10% faster. + Changes include the removal of some null pointer assignment checks. These + were redundant where the scheduler uses the list functions, but means any + user application choosing to use the same list functions must now check + that no NULL pointers are passed as a parameter. + + The Flashlite 186 serial port driver has also been modified to use a DMA + channel for transmissions. The serial driver is fully functional but still + under development. Flashlite users may prefer to use V1.2.0 for now. + + Details: + + + Changed the baud rate for the ATMega323 serial test from 19200 to 57600. + + Use vSerialPutString() instead of single character puts in + Demo\Full\Comtest.c. This allows the use of the flashlite DMA serial + driver. Also the check variable only stops incrementing after two + consecutive failures. + + semtest.c creates four tasks, two of which operate at the idle priority. + The tasks that operate at the idle priority now use a lower expected + count than those running at a higher priority. This prevents the low + priority tasks from signalling an error because they have not been + scheduled enough time for each of them to count the shared variable to + the higher original value. + + The flashlite 186 serial driver now uses a DMA channel for transmissions. + + Removed the volatile modifier from the list function parameters. This was + only ever included to prevent compiler warnings. Now warnings are + removed by casting parameters where the calls are made. + + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been + removed from list.c and added as macros in list.h. + + usNumberOfItems has been added to the list structure. This removes the + need for a pointer comparison when checking if a list is empty, and so + is slightly faster. + + Removed the NULL check in vListRemove(). This makes the call faster but + necessitates any application code utilising the list implementation to + ensure NULL pointers are not passed. + + Renamed portTICKS_PER_MS definition to portMS_PER_TICK (milli seconds + per tick). This is what it always should have been. + +Changes between V1.01 and V1.2.0 + + The majority of these changes were made to accommodate the 8bit AVR port. + The scheduler workings have not changed, but some of the data types used + have been made more friendly to an eight bit environment. + + Details: + + + Changed the version numbering format. + + Added AVR port. + + Split the directory demo\common into demo\common\minimal and + demo\common\full. The files in the full directory are for systems with + a display (currently PC and Flashlite 186 demo's). The files in the + minimal directory are for systems with limited RAM and no display + (currently MegaAVR). + + Minor changes to demo application function prototypes to make more use + of 8bit data types. + + Within the scheduler itself the following functions have slightly + modified declarations to make use of 8bit data types where possible: + xQueueCreate(), + sQueueReceive(), + sQUeueReceive(), + usQueueMessageWaiting(), + sQueueSendFromISR(), + sSemaphoreTake(), + sSemaphoreGive(), + sSemaphoreGiveFromISR(), + sTaskCreate(), + sTaskMoveFromEventList(). + + Where the return type has changed the function name has also changed in + accordance with the naming convention. For example + usQueueMessageWaiting() has become ucQueueMessageWaiting(). + + The definition tskMAX_PRIORITIES has been moved from task.h to + portmacro.h and renamed portMAX_PRIORITIES. This allows different + ports to allocate a different maximum number of priorities. + + By default the trace facility is off, previously USE_TRACE_FACILITY + was defined. + + comtest.c now uses a psuedo random delay between sends. This allows for + better testing as the interrupts do not arrive at regular intervals. + + Minor change to the Flashlite serial port driver. The driver is written + to demonstrate the scheduler and is not written to be efficient. + + + +Changes between V1.00 and V1.01 + + These changes improve the ports. The scheduler itself has not changed. + + Improved context switch mechanism used when performing a context + switch from an ISR (both the tick ISR and the serial comms ISR's within + the demo application). The new mechanism is faster and uses less stack. + + The assembler file portasm.asm has been replaced by a header file + portasm.h. This includes a few assembler macro definitions. + + All saving and restoring of registers onto/off of the stack is now handled + by the compiler. This means the initial stack setup for a task has to + mimic the stack used by the compiler, which is different for debug and + release builds. + + Slightly changed the operation of the demo application, details below. + + Details: + + + portSWITCH_CONTEXT() replaced by vPortFirstContext(). + + pxPortInitialiseStack() modified to replicate the stack used by the + compiler. + + portasm.asm file removed. + + portasm.h introduced. This contains macro definitions for + portSWITCH_CONTEXT() and portFIRST_CONTEXT(). + + Context switch from ISR now uses the compiler generated interrupt + mechanism. This is done simply by calling portSWITCH_CONTEXT and leaving + the save/restore to compiler generated code. + + Calls to taskYIELD() during ISR's have been replaced by calling the + simpler and faster portSWITCH_CONTEXT(). + + The Flashlite 186 port now uses 186 instruction set (used to use 80x86 + instructions only). + + The blocking queue tasks within the demo application did not operate + quite as described. This has been corrected. + + The priority of the comtest Rx task within the demo application has been + lowered. Received characters are now processed (read from the queue) at + the idle priority, allowing low priority tasks to run evenly at times of + a high communications overhead. + + Prevent the call to kbhit() in main.c for debug builds as the debugger + seems to have problems stepping over the call. This if for the PC port + only. + + + diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/LICENSE.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/LICENSE.md similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/LICENSE.md rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/LICENSE.md diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/Quick_Start_Guide.url b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/Quick_Start_Guide.url similarity index 96% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/Quick_Start_Guide.url rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/Quick_Start_Guide.url index ebefebd..0aa68ed 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/Quick_Start_Guide.url +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/Quick_Start_Guide.url @@ -1,5 +1,5 @@ -[InternetShortcut] -URL=https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html -IDList= -[{000214A0-0000-0000-C000-000000000046}] -Prop3=19,2 +[InternetShortcut] +URL=https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html +IDList= +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/README.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/README.md new file mode 100644 index 0000000..52d78dd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/README.md @@ -0,0 +1,39 @@ +## Getting started +This repository contains FreeRTOS kernel source/header files and kernel ports only. This repository is referenced as a submodule in [FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS) repository, which contains pre-configured demo application projects under ```FreeRTOS/Demo``` directory. + +The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects. That way you will have the correct FreeRTOS source files included, and the correct include paths configured. Once a demo application is building and executing you can remove the demo application files, and start to add in your own application source files. See the [FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html) for detailed instructions and other useful links. + +Additionally, for FreeRTOS kernel feature information refer to the [Developer Documentation](https://www.FreeRTOS.org/features.html), and [API Reference](https://www.FreeRTOS.org/a00106.html). + +### Getting help +If you have any questions or need assistance troubleshooting your FreeRTOS project, we have an active community that can help on the [FreeRTOS Community Support Forum](https://forums.freertos.org). + +## Cloning this repository + +To clone using HTTPS: +``` +git clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git +``` +Using SSH: +``` +git clone git@github.com:FreeRTOS/FreeRTOS-Kernel.git +``` + +## Repository structure +- The root of this repository contains the three files that are common to +every port - list.c, queue.c and tasks.c. The kernel is contained within these +three files. croutine.c implements the optional co-routine functionality - which +is normally only used on very memory limited systems. + +- The ```./portable``` directory contains the files that are specific to a particular microcontroller and/or compiler. +See the readme file in the ```./portable``` directory for more information. + +- The ```./include``` directory contains the real time kernel header files. + +### Code Formatting +FreeRTOS files are formatted using the "uncrustify" tool. The configuration file used by uncrustify can be found in the [FreeRTOS/FreeRTOS repository](https://github.com/FreeRTOS/FreeRTOS/blob/main/tools/uncrustify.cfg). + +### Spelling +*lexicon.txt* contains words that are not traditionally found in an English dictionary. It is used by the spellchecker to verify the various jargon, variable names, and other odd words used in the FreeRTOS code base. If your pull request fails to pass the spelling and you believe this is a mistake, then add the word to *lexicon.txt*. +Note that only the FreeRTOS Kernel source files are checked for proper spelling, the portable section is ignored. + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/SW-Content-Register.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/SW-Content-Register.txt new file mode 100644 index 0000000..0b0cce5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/SW-Content-Register.txt @@ -0,0 +1,8 @@ +Release Name: FreeRTOS kernel +Release Version: 10.5.0 +Outgoing License: MIT +License File: LICENSE.md +Format: source code +Description: Open source RTOS kernel for small devices +Origin: Amazon (MIT) +Url: https://aws.amazon.com/freertos/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/croutine.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/croutine.c new file mode 100644 index 0000000..9e58334 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/croutine.c @@ -0,0 +1,363 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Remove the whole file is co-routines are not being used. */ +#if ( configUSE_CO_ROUTINES != 0 ) + +/* + * Some kernel aware debuggers require data to be viewed to be global, rather + * than file scope. + */ + #ifdef portREMOVE_STATIC_QUALIFIER + #define static + #endif + + +/* Lists for ready and blocked co-routines. --------------------*/ + static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ + static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */ + static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ + static List_t * pxDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used. */ + static List_t * pxOverflowDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ + static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ + +/* Other file private variables. --------------------------------*/ + CRCB_t * pxCurrentCoRoutine = NULL; + static UBaseType_t uxTopCoRoutineReadyPriority = 0; + static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0; + +/* The initial state of the co-routine when it is created. */ + #define corINITIAL_STATE ( 0 ) + +/* + * Place the co-routine represented by pxCRCB into the appropriate ready queue + * for the priority. It is inserted at the end of the list. + * + * This macro accesses the co-routine ready lists and therefore must not be + * used from within an ISR. + */ + #define prvAddCoRoutineToReadyQueue( pxCRCB ) \ + { \ + if( ( pxCRCB )->uxPriority > uxTopCoRoutineReadyPriority ) \ + { \ + uxTopCoRoutineReadyPriority = ( pxCRCB )->uxPriority; \ + } \ + vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ ( pxCRCB )->uxPriority ] ), &( ( pxCRCB )->xGenericListItem ) ); \ + } + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first co-routine. + */ + static void prvInitialiseCoRoutineLists( void ); + +/* + * Co-routines that are readied by an interrupt cannot be placed directly into + * the ready lists (there is no mutual exclusion). Instead they are placed in + * in the pending ready list in order that they can later be moved to the ready + * list by the co-routine scheduler. + */ + static void prvCheckPendingReadyList( void ); + +/* + * Macro that looks at the list of co-routines that are currently delayed to + * see if any require waking. + * + * Co-routines are stored in the queue in the order of their wake time - + * meaning once one co-routine has been found whose timer has not expired + * we need not look any further down the list. + */ + static void prvCheckDelayedList( void ); + +/*-----------------------------------------------------------*/ + + BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, + UBaseType_t uxPriority, + UBaseType_t uxIndex ) + { + BaseType_t xReturn; + CRCB_t * pxCoRoutine; + + /* Allocate the memory that will store the co-routine control block. */ + pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) ); + + if( pxCoRoutine ) + { + /* If pxCurrentCoRoutine is NULL then this is the first co-routine to + * be created and the co-routine data structures need initialising. */ + if( pxCurrentCoRoutine == NULL ) + { + pxCurrentCoRoutine = pxCoRoutine; + prvInitialiseCoRoutineLists(); + } + + /* Check the priority is within limits. */ + if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) + { + uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; + } + + /* Fill out the co-routine control block from the function parameters. */ + pxCoRoutine->uxState = corINITIAL_STATE; + pxCoRoutine->uxPriority = uxPriority; + pxCoRoutine->uxIndex = uxIndex; + pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; + + /* Initialise all the other co-routine control block parameters. */ + vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); + vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); + + /* Set the co-routine control block as a link back from the ListItem_t. + * This is so we can get back to the containing CRCB from a generic item + * in a list. */ + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) ); + + /* Now the co-routine has been initialised it can be added to the ready + * list at the correct priority. */ + prvAddCoRoutineToReadyQueue( pxCoRoutine ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, + List_t * pxEventList ) + { + TickType_t xTimeToWake; + + /* Calculate the time to wake - this may overflow but this is + * not a problem. */ + xTimeToWake = xCoRoutineTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + * ourselves to the blocked list as the same list item is used for + * both lists. */ + ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xCoRoutineTickCount ) + { + /* Wake time has overflowed. Place this item in the + * overflow list. */ + vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + * current block list. */ + vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + + if( pxEventList ) + { + /* Also add the co-routine to an event list. If this is done then the + * function must be called with interrupts disabled. */ + vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); + } + } +/*-----------------------------------------------------------*/ + + static void prvCheckPendingReadyList( void ) + { + /* Are there any co-routines waiting to get moved to the ready list? These + * are co-routines that have been readied by an ISR. The ISR cannot access + * the ready lists itself. */ + while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE ) + { + CRCB_t * pxUnblockedCRCB; + + /* The pending ready list can be accessed by an ISR. */ + portDISABLE_INTERRUPTS(); + { + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyCoRoutineList ) ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + } + portENABLE_INTERRUPTS(); + + ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); + prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); + } + } +/*-----------------------------------------------------------*/ + + static void prvCheckDelayedList( void ) + { + CRCB_t * pxCRCB; + + xPassedTicks = xTaskGetTickCount() - xLastTickCount; + + while( xPassedTicks ) + { + xCoRoutineTickCount++; + xPassedTicks--; + + /* If the tick count has overflowed we need to swap the ready lists. */ + if( xCoRoutineTickCount == 0 ) + { + List_t * pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. If there are + * any items in pxDelayedCoRoutineList here then there is an error! */ + pxTemp = pxDelayedCoRoutineList; + pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; + pxOverflowDelayedCoRoutineList = pxTemp; + } + + /* See if this tick has made a timeout expire. */ + while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE ) + { + pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ); + + if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) + { + /* Timeout not yet expired. */ + break; + } + + portDISABLE_INTERRUPTS(); + { + /* The event could have occurred just before this critical + * section. If this is the case then the generic list item will + * have been moved to the pending ready list and the following + * line is still valid. Also the pvContainer parameter will have + * been set to NULL so the following lines are also valid. */ + ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); + + /* Is the co-routine waiting on an event also? */ + if( pxCRCB->xEventListItem.pxContainer ) + { + ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); + } + } + portENABLE_INTERRUPTS(); + + prvAddCoRoutineToReadyQueue( pxCRCB ); + } + } + + xLastTickCount = xCoRoutineTickCount; + } +/*-----------------------------------------------------------*/ + + void vCoRoutineSchedule( void ) + { + /* Only run a co-routine after prvInitialiseCoRoutineLists() has been + * called. prvInitialiseCoRoutineLists() is called automatically when a + * co-routine is created. */ + if( pxDelayedCoRoutineList != NULL ) + { + /* See if any co-routines readied by events need moving to the ready lists. */ + prvCheckPendingReadyList(); + + /* See if any delayed co-routines have timed out. */ + prvCheckDelayedList(); + + /* Find the highest priority queue that contains ready co-routines. */ + while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) + { + if( uxTopCoRoutineReadyPriority == 0 ) + { + /* No more co-routines to check. */ + return; + } + + --uxTopCoRoutineReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines + * of the same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); + + /* Call the co-routine. */ + ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); + } + } +/*-----------------------------------------------------------*/ + + static void prvInitialiseCoRoutineLists( void ) + { + UBaseType_t uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); + } + + vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 ); + vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 ); + vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList ); + + /* Start with pxDelayedCoRoutineList using list1 and the + * pxOverflowDelayedCoRoutineList using list2. */ + pxDelayedCoRoutineList = &xDelayedCoRoutineList1; + pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; + } +/*-----------------------------------------------------------*/ + + BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList ) + { + CRCB_t * pxUnblockedCRCB; + BaseType_t xReturn; + + /* This function is called from within an interrupt. It can only access + * event lists and the pending ready list. This function assumes that a + * check has already been made to ensure pxEventList is not empty. */ + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); + + if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES == 0 */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/event_groups.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/event_groups.c new file mode 100644 index 0000000..9313455 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/event_groups.c @@ -0,0 +1,778 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "event_groups.h" + +/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ + +/* The following bit fields convey control information in a task's event list + * item value. It is important they don't clash with the + * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ +#if configUSE_16_BIT_TICKS == 1 + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U + #define eventWAIT_FOR_ALL_BITS 0x0400U + #define eventEVENT_BITS_CONTROL_BYTES 0xff00U +#else + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL + #define eventWAIT_FOR_ALL_BITS 0x04000000UL + #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL +#endif + +typedef struct EventGroupDef_t +{ + EventBits_t uxEventBits; + List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupNumber; + #endif + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ + #endif +} EventGroup_t; + +/*-----------------------------------------------------------*/ + +/* + * Test the bits set in uxCurrentEventBits to see if the wait condition is met. + * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is + * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor + * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the + * wait condition is met if any of the bits set in uxBitsToWait for are also set + * in uxCurrentEventBits. + */ +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) + { + EventGroup_t * pxEventBits; + + /* A StaticEventGroup_t object must be provided. */ + configASSERT( pxEventGroupBuffer ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticEventGroup_t equals the size of the real + * event group structure. */ + volatile size_t xSize = sizeof( StaticEventGroup_t ); + configASSERT( xSize == sizeof( EventGroup_t ) ); + } /*lint !e529 xSize is referenced if configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + + /* The user has provided a statically allocated event group - use it. */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note that + * this event group was created statically in case the event group + * is later deleted. */ + pxEventBits->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + /* xEventGroupCreateStatic should only ever be called with + * pxEventGroupBuffer pointing to a pre-allocated (compile time + * allocated) StaticEventGroup_t variable. */ + traceEVENT_GROUP_CREATE_FAILED(); + } + + return pxEventBits; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreate( void ) + { + EventGroup_t * pxEventBits; + + /* Allocate the event group. Justification for MISRA deviation as + * follows: pvPortMalloc() always ensures returned memory blocks are + * aligned per the requirements of the MCU stack. In this case + * pvPortMalloc() must return a pointer that is guaranteed to meet the + * alignment requirements of the EventGroup_t structure - which (if you + * follow it through) is the alignment requirements of the TickType_t type + * (EventBits_t being of TickType_t itself). Therefore, whenever the + * stack alignment requirements are greater than or equal to the + * TickType_t alignment requirements the cast is safe. In other cases, + * where the natural word size of the architecture is less than + * sizeof( TickType_t ), the TickType_t variables will be accessed in two + * or more reads operations, and the alignment requirements is only that + * of each individual read. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note this + * event group was allocated statically in case the event group is + * later deleted. */ + pxEventBits->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ + } + + return pxEventBits; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) +{ + EventBits_t uxOriginalBitValue, uxReturn; + EventGroup_t * pxEventBits = xEventGroup; + BaseType_t xAlreadyYielded; + BaseType_t xTimeoutOccurred = pdFALSE; + + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + uxOriginalBitValue = pxEventBits->uxEventBits; + + ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); + + if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + /* All the rendezvous bits are now set - no need to block. */ + uxReturn = ( uxOriginalBitValue | uxBitsToSet ); + + /* Rendezvous always clear the bits. They will have been cleared + * already unless this is the only task in the rendezvous. */ + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + + xTicksToWait = 0; + } + else + { + if( xTicksToWait != ( TickType_t ) 0 ) + { + traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); + + /* Store the bits that the calling task is waiting for in the + * task's event list item so the kernel knows when a match is + * found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); + + /* This assignment is obsolete as uxReturn will get set after + * the task unblocks, but some compilers mistakenly generate a + * warning about uxReturn being returned without being set if the + * assignment is omitted. */ + uxReturn = 0; + } + else + { + /* The rendezvous bits were not set, but no block time was + * specified - just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + xTimeoutOccurred = pdTRUE; + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + * point either the required bits were set or the block time expired. If + * the required bits were set they will have been stored in the task's + * event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + /* The task timed out, just return the current event bit value. */ + taskENTER_CRITICAL(); + { + uxReturn = pxEventBits->uxEventBits; + + /* Although the task got here because it timed out before the + * bits it was waiting for were set, it is possible that since it + * unblocked another task has set the bits. If this is the case + * then it needs to clear the bits before exiting. */ + if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* Control bits might be set as the task had blocked should not be + * returned. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) +{ + EventGroup_t * pxEventBits = xEventGroup; + EventBits_t uxReturn, uxControlBits = 0; + BaseType_t xWaitConditionMet, xAlreadyYielded; + BaseType_t xTimeoutOccurred = pdFALSE; + + /* Check the user is not attempting to wait on the bits used by the kernel + * itself, and that at least one bit is being requested. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; + + /* Check to see if the wait condition is already met or not. */ + xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); + + if( xWaitConditionMet != pdFALSE ) + { + /* The wait condition has already been met so there is no need to + * block. */ + uxReturn = uxCurrentEventBits; + xTicksToWait = ( TickType_t ) 0; + + /* Clear the wait bits if requested to do so. */ + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The wait condition has not been met, but no block time was + * specified, so just return the current value. */ + uxReturn = uxCurrentEventBits; + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task is going to block to wait for its required bits to be + * set. uxControlBits are used to remember the specified behaviour of + * this call to xEventGroupWaitBits() - for use when the event bits + * unblock the task. */ + if( xClearOnExit != pdFALSE ) + { + uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWaitForAllBits != pdFALSE ) + { + uxControlBits |= eventWAIT_FOR_ALL_BITS; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the bits that the calling task is waiting for in the + * task's event list item so the kernel knows when a match is + * found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); + + /* This is obsolete as it will get set after the task unblocks, but + * some compilers mistakenly generate a warning about the variable + * being returned without being set if it is not done. */ + uxReturn = 0; + + traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + * point either the required bits were set or the block time expired. If + * the required bits were set they will have been stored in the task's + * event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + taskENTER_CRITICAL(); + { + /* The task timed out, just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + + /* It is possible that the event bits were updated between this + * task leaving the Blocked state and running again. */ + if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) + { + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xTimeoutOccurred = pdTRUE; + } + taskEXIT_CRITICAL(); + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* The task blocked so control bits may have been set. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) +{ + EventGroup_t * pxEventBits = xEventGroup; + EventBits_t uxReturn; + + /* Check the user is not attempting to clear the bits used by the kernel + * itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + taskENTER_CRITICAL(); + { + traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); + + /* The value returned is the event group value prior to the bits being + * cleared. */ + uxReturn = pxEventBits->uxEventBits; + + /* Clear the bits. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) +{ + UBaseType_t uxSavedInterruptStatus; + EventGroup_t const * const pxEventBits = xEventGroup; + EventBits_t uxReturn; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + uxReturn = pxEventBits->uxEventBits; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return uxReturn; +} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) +{ + ListItem_t * pxListItem; + ListItem_t * pxNext; + ListItem_t const * pxListEnd; + List_t const * pxList; + EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; + EventGroup_t * pxEventBits = xEventGroup; + BaseType_t xMatchFound = pdFALSE; + + /* Check the user is not attempting to set the bits used by the kernel + * itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + pxList = &( pxEventBits->xTasksWaitingForBits ); + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + vTaskSuspendAll(); + { + traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); + + pxListItem = listGET_HEAD_ENTRY( pxList ); + + /* Set the bits. */ + pxEventBits->uxEventBits |= uxBitsToSet; + + /* See if the new bit value should unblock any tasks. */ + while( pxListItem != pxListEnd ) + { + pxNext = listGET_NEXT( pxListItem ); + uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); + xMatchFound = pdFALSE; + + /* Split the bits waited for from the control bits. */ + uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; + uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; + + if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) + { + /* Just looking for single bit being set. */ + if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) + { + xMatchFound = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) + { + /* All bits are set. */ + xMatchFound = pdTRUE; + } + else + { + /* Need all bits to be set, but not all the bits were set. */ + } + + if( xMatchFound != pdFALSE ) + { + /* The bits match. Should the bits be cleared on exit? */ + if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) + { + uxBitsToClear |= uxBitsWaitedFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the actual event flag value in the task's event list + * item before removing the task from the event list. The + * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows + * that is was unblocked due to its required bits matching, rather + * than because it timed out. */ + vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + /* Move onto the next list item. Note pxListItem->pxNext is not + * used here as the list item may have been removed from the event list + * and inserted into the ready/pending reading list. */ + pxListItem = pxNext; + } + + /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT + * bit was set in the control word. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + ( void ) xTaskResumeAll(); + + return pxEventBits->uxEventBits; +} +/*-----------------------------------------------------------*/ + +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) +{ + EventGroup_t * pxEventBits = xEventGroup; + const List_t * pxTasksWaitingForBits; + + configASSERT( pxEventBits ); + + pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); + + vTaskSuspendAll(); + { + traceEVENT_GROUP_DELETE( xEventGroup ); + + while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) + { + /* Unblock the task, returning 0 as the event list is being deleted + * and cannot therefore have any bits set. */ + configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); + vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); + } + } + ( void ) xTaskResumeAll(); + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The event group can only have been allocated dynamically - free + * it again. */ + vPortFree( pxEventBits ); + } + #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The event group could have been allocated statically or + * dynamically, so check before attempting to free the memory. */ + if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxEventBits ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'set bits' command that was pended from + * an interrupt. */ +void vEventGroupSetBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToSet ) +{ + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'clear bits' command that was pended from + * an interrupt. */ +void vEventGroupClearBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToClear ) +{ + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xWaitForAllBits ) +{ + BaseType_t xWaitConditionMet = pdFALSE; + + if( xWaitForAllBits == pdFALSE ) + { + /* Task only has to wait for one bit within uxBitsToWaitFor to be + * set. Is one already set? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Task has to wait for all the bits in uxBitsToWaitFor to be set. + * Are they set already? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return xWaitConditionMet; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + BaseType_t * pxHigherPriorityTaskWoken ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) + { + UBaseType_t xReturn; + EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + + if( xEventGroup == NULL ) + { + xReturn = 0; + } + else + { + xReturn = pxEventBits->uxEventGroupNumber; + } + + return xReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) + { + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/FreeRTOS.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/FreeRTOS.h new file mode 100644 index 0000000..7ca6e36 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/FreeRTOS.h @@ -0,0 +1,1476 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + * + * Copyright 2019 MicroEJ Corp. This file has been modified by MicroEJ Corp. + * 1. Patch for SystemView support + */ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +/* Required if struct _reent is used. */ +#if ( configUSE_NEWLIB_REENTRANT == 1 ) + +/* Note Newlib support has been included by popular demand, but is not + * used by the FreeRTOS maintainers themselves. FreeRTOS is not + * responsible for resulting newlib operation. User must be familiar with + * newlib and must provide system-wide implementations of the necessary + * stubs. Be warned that (at the time of writing) the current newlib design + * implements a system-wide malloc() that must be provided with locks. + * + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + #include + + #define configUSE_C_RUNTIME_TLS_SUPPORT 1 + + #ifndef configTLS_BLOCK_TYPE + #define configTLS_BLOCK_TYPE struct _reent + #endif + + #ifndef configINIT_TLS_BLOCK + #define configINIT_TLS_BLOCK( xTLSBlock ) _REENT_INIT_PTR( &( xTLSBlock ) ) + #endif + + #ifndef configSET_TLS_BLOCK + #define configSET_TLS_BLOCK( xTLSBlock ) _impure_ptr = &( xTLSBlock ) + #endif + + #ifndef configDEINIT_TLS_BLOCK + #define configDEINIT_TLS_BLOCK( xTLSBlock ) _reclaim_reent( &( xTLSBlock ) ) + #endif +#endif /* if ( configUSE_NEWLIB_REENTRANT == 1 ) */ + +#ifndef configUSE_C_RUNTIME_TLS_SUPPORT + #define configUSE_C_RUNTIME_TLS_SUPPORT 0 +#endif + +#if ( ( configUSE_NEWLIB_REENTRANT == 0 ) && ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) ) + + #ifndef configTLS_BLOCK_TYPE + #error Missing definition: configTLS_BLOCK_TYPE must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1. + #endif + + #ifndef configINIT_TLS_BLOCK + #error Missing definition: configINIT_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1. + #endif + + #ifndef configSET_TLS_BLOCK + #error Missing definition: configSET_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1. + #endif + + #ifndef configDEINIT_TLS_BLOCK + #error Missing definition: configDEINIT_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1. + #endif +#endif /* if ( ( configUSE_NEWLIB_REENTRANT == 0 ) && ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) ) */ + +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #define configUSE_CO_ROUTINES 0 +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #define INCLUDE_vTaskPrioritySet 0 +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #define INCLUDE_uxTaskPriorityGet 0 +#endif + +#ifndef INCLUDE_vTaskDelete + #define INCLUDE_vTaskDelete 0 +#endif + +#ifndef INCLUDE_vTaskSuspend + #define INCLUDE_vTaskSuspend 0 +#endif + +#ifdef INCLUDE_xTaskDelayUntil + #ifdef INCLUDE_vTaskDelayUntil + +/* INCLUDE_vTaskDelayUntil was replaced by INCLUDE_xTaskDelayUntil. Backward + * compatibility is maintained if only one or the other is defined, but + * there is a conflict if both are defined. */ + #error INCLUDE_vTaskDelayUntil and INCLUDE_xTaskDelayUntil are both defined. INCLUDE_vTaskDelayUntil is no longer required and should be removed + #endif +#endif + +#ifndef INCLUDE_xTaskDelayUntil + #ifdef INCLUDE_vTaskDelayUntil + +/* If INCLUDE_vTaskDelayUntil is set but INCLUDE_xTaskDelayUntil is not then + * the project's FreeRTOSConfig.h probably pre-dates the introduction of + * xTaskDelayUntil and setting INCLUDE_xTaskDelayUntil to whatever + * INCLUDE_vTaskDelayUntil is set to will ensure backward compatibility. + */ + #define INCLUDE_xTaskDelayUntil INCLUDE_vTaskDelayUntil + #endif +#endif + +#ifndef INCLUDE_xTaskDelayUntil + #define INCLUDE_xTaskDelayUntil 0 +#endif + +#ifndef INCLUDE_vTaskDelay + #define INCLUDE_vTaskDelay 0 +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 0 +#endif + +#ifndef INCLUDE_xTaskAbortDelay + #define INCLUDE_xTaskAbortDelay 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_xTaskGetHandle + #define INCLUDE_xTaskGetHandle 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 + #define INCLUDE_uxTaskGetStackHighWaterMark2 0 +#endif + +#ifndef INCLUDE_pxTaskGetStackStart + #define INCLUDE_pxTaskGetStackStart 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 1 +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +/* configPRECONDITION should be defined as configASSERT. + * The CBMC proofs need a way to track assumptions and assertions. + * A configPRECONDITION statement should express an implicit invariant or + * assumption made. A configASSERT statement should express an invariant that must + * hold explicit before calling the code. */ +#ifndef configPRECONDITION + #define configPRECONDITION( X ) configASSERT( X ) + #define configPRECONDITION_DEFINED 0 +#else + #define configPRECONDITION_DEFINED 1 +#endif + +#ifndef portMEMORY_BARRIER + #define portMEMORY_BARRIER() +#endif + +#ifndef portSOFTWARE_BARRIER + #define portSOFTWARE_BARRIER() +#endif + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + +#endif /* configUSE_TIMERS */ + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) ( uxSavedStatusValue ) +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) ( pxTCB ) +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) ( pxTCB ) +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) + #define pcQueueGetName( xQueue ) +#endif + +#ifndef configUSE_MINI_LIST_ITEM + #define configUSE_MINI_LIST_ITEM 1 +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + +/* Used to perform any necessary initialisation - for example, open a file + * into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + +/* Use to close a trace, for example close a file into which trace has been + * written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + +/* Called after a task has been selected to run. pxCurrentTCB holds a pointer + * to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceINCREASE_TICK_COUNT + +/* Called before stepping the tick count after waking from tickless idle + * sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + +/* Called before a task has been selected to run. pxCurrentTCB holds a pointer + * to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + +/* Called when a task attempts to take a mutex that is already held by a + * lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + * that holds the mutex. uxInheritedPriority is the priority the mutex holder + * will inherit (the priority of the task that is attempting to obtain the + * muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + +/* Called when a task releases a mutex, the holding of which had resulted in + * the task inheriting the priority of a higher priority task. + * pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + * mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + +/* Task is about to block because it cannot read from a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the read was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_PEEK + +/* Task is about to block because it cannot read from a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the read was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + +/* Task is about to block because it cannot write to a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the write was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 0 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef tracePOST_MOVED_TASK_TO_READY_STATE + #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceREADDED_TASK_TO_READY_STATE + #define traceREADDED_TASK_TO_READY_STATE( pxTCB ) traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceMOVED_TASK_TO_DELAYED_LIST + #define traceMOVED_TASK_TO_DELAYED_LIST() +#endif + +#ifndef traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST + #define traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST() +#endif + +#ifndef traceMOVED_TASK_TO_SUSPENDED_LIST + #define traceMOVED_TASK_TO_SUSPENDED_LIST( pxTCB ) +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SET_SEND + #define traceQUEUE_SET_SEND traceQUEUE_SEND +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL( x ) +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) ( xTimeoutOccurred ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) ( xTimeoutOccurred ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, ret ) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, ret ) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ) +#endif + +#ifndef traceTASK_NOTIFY_TAKE_BLOCK + #define traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_TAKE + #define traceTASK_NOTIFY_TAKE( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_WAIT_BLOCK + #define traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_WAIT + #define traceTASK_NOTIFY_WAIT( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY + #define traceTASK_NOTIFY( uxIndexToNotify ) +#endif + +#ifndef traceTASK_NOTIFY_FROM_ISR + #define traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify ) +#endif + +#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR + #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ) +#endif + +#ifndef traceISR_EXIT_TO_SCHEDULER + #define traceISR_EXIT_TO_SCHEDULER() +#endif + +#ifndef traceISR_EXIT + #define traceISR_EXIT() +#endif + +#ifndef traceISR_ENTER + #define traceISR_ENTER() +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef configTASK_NOTIFICATION_ARRAY_ENTRIES + #define configTASK_NOTIFICATION_ARRAY_ENTRIES 1 +#endif + +#if configTASK_NOTIFICATION_ARRAY_ENTRIES < 1 + #error configTASK_NOTIFICATION_ARRAY_ENTRIES must be at least 1 +#endif + +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + +#ifndef configUSE_SB_COMPLETED_CALLBACK + +/* By default per-instance callbacks are not enabled for stream buffer or message buffer. */ + #define configUSE_SB_COMPLETED_CALLBACK 0 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#if ( ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION != 1 ) ) + #error configUSE_STATS_FORMATTING_FUNCTIONS cannot be used without dynamic allocation, but configSUPPORT_DYNAMIC_ALLOCATION is not set to 1. +#endif + +#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) + #if ( ( configUSE_TRACE_FACILITY != 1 ) && ( configGENERATE_RUN_TIME_STATS != 1 ) ) + #error configUSE_STATS_FORMATTING_FUNCTIONS is 1 but the functions it enables are not used because neither configUSE_TRACE_FACILITY or configGENERATE_RUN_TIME_STATS are 1. Set configUSE_STATS_FORMATTING_FUNCTIONS to 0 in FreeRTOSConfig.h. + #endif +#endif + +#ifndef configSTACK_DEPTH_TYPE + +/* Defaults to uint16_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +#ifndef configRUN_TIME_COUNTER_TYPE + +/* Defaults to uint32_t for backward compatibility, but can be overridden in + * FreeRTOSConfig.h if uint32_t is too restrictive. */ + + #define configRUN_TIME_COUNTER_TYPE uint32_t +#endif + +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + +/* Defaults to size_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if lengths will always be less than the number of bytes + * in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + +/* Sanity check the configuration. */ +#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if ( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if ( portTICK_TYPE_IS_ATOMIC == 0 ) + +/* Either variables of tick type cannot be read atomically, or + * portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + * the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + +/* The tick type can be read atomically, so critical sections used when the + * tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) ( x ) +#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */ + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to + * V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + +/* configPRINTF() was not defined, so define it away to nothing. To use + * configPRINTF() then define it as follows (where MyPrintFunction() is + * provided by the application writer): + * + * void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + * + * Then call like a standard printf() function, but placing brackets around + * all parameters so they are passed as a single parameter. For example: + * configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + +/* The application writer has not provided their own MAX macro, so define + * the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + +/* The application writer has not provided their own MIN macro, so define + * the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName + #define vTaskGetTaskInfo vTaskGetInfo + #define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + +/* Backward compatibility within the scheduler code only - these definitions + * are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t + +/* For libraries that break the list data hiding, and access list structure + * members directly (which is not supposed to be done). */ + #define pxContainer pvContainer +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#if ( configUSE_ALTERNATIVE_API != 0 ) + #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 +#endif + +/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even + * if floating point hardware is otherwise supported by the FreeRTOS port in use. + * This constant is not supported by all FreeRTOS ports that include floating + * point support. */ +#ifndef configUSE_TASK_FPU_SUPPORT + #define configUSE_TASK_FPU_SUPPORT 1 +#endif + +/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif + +/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif + +/* Set configENABLE_MVE to 1 to enable MVE support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#endif + +/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. + * This is currently used in ARMv8M ports. */ +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 1 +#endif + +/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on + * the Secure Side only. */ +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + +#ifndef configRUN_ADDITIONAL_TESTS + #define configRUN_ADDITIONAL_TESTS 0 +#endif + + +/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using + * dynamically allocated RAM, in which case when any task is deleted it is known + * that both the task's stack and TCB need to be freed. Sometimes the + * FreeRTOSConfig.h settings only allow a task to be created using statically + * allocated RAM, in which case when any task is deleted it is known that neither + * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h + * settings allow a task to be created using either statically or dynamically + * allocated RAM, in which case a member of the TCB is used to record whether the + * stack and/or TCB were allocated statically or dynamically, so when a task is + * deleted the RAM that was allocated dynamically is freed again and no attempt is + * made to free the RAM that was allocated statically. + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a + * task to be created using either statically or dynamically allocated RAM. Note + * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with + * a statically allocated stack and a dynamically allocated TCB. + * + * The following table lists various combinations of portUSING_MPU_WRAPPERS, + * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and + * when it is possible to have both static and dynamic allocation: + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | + * | | | | | | Static Possible | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | + * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + */ +#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE \ + ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ + ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be known. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +struct xSTATIC_LIST_ITEM +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void * pvDummy3[ 4 ]; + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy4; + #endif +}; +typedef struct xSTATIC_LIST_ITEM StaticListItem_t; + +#if ( configUSE_MINI_LIST_ITEM == 1 ) + /* See the comments above the struct xSTATIC_LIST_ITEM definition. */ + struct xSTATIC_MINI_LIST_ITEM + { + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void * pvDummy3[ 2 ]; + }; + typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; +#else /* if ( configUSE_MINI_LIST_ITEM == 1 ) */ + typedef struct xSTATIC_LIST_ITEM StaticMiniListItem_t; +#endif /* if ( configUSE_MINI_LIST_ITEM == 1 ) */ + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +typedef struct xSTATIC_LIST +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + UBaseType_t uxDummy2; + void * pvDummy3; + StaticMiniListItem_t xDummy4; + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy5; + #endif +} StaticList_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be known. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +typedef struct xSTATIC_TCB +{ + void * pxDummy1; + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xDummy2; + #endif + StaticListItem_t xDummy3[ 2 ]; + UBaseType_t uxDummy5; + void * pxDummy6; + uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + void * pxDummy8; + #endif + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxDummy9; + #endif + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy10[ 2 ]; + #endif + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxDummy12[ 2 ]; + #endif + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void * pxDummy14; + #endif + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + configRUN_TIME_COUNTER_TYPE ulDummy16; + #endif + #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) ) + configTLS_BLOCK_TYPE xDummy17; + #endif + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t ulDummy18[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + uint8_t ucDummy19[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + #endif + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + uint8_t uxDummy20; + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif +} StaticTask_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be known. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +typedef struct xSTATIC_QUEUE +{ + void * pvDummy1[ 3 ]; + + union + { + void * pvDummy2; + UBaseType_t uxDummy2; + } u; + + StaticList_t xDummy3[ 2 ]; + UBaseType_t uxDummy4[ 3 ]; + uint8_t ucDummy5[ 2 ]; + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy6; + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + void * pvDummy7; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy8; + uint8_t ucDummy9; + #endif +} StaticQueue_t; +typedef StaticQueue_t StaticSemaphore_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_EVENT_GROUP +{ + TickType_t xDummy1; + StaticList_t xDummy2; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy3; + #endif + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy4; + #endif +} StaticEventGroup_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be known. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +typedef struct xSTATIC_TIMER +{ + void * pvDummy1; + StaticListItem_t xDummy2; + TickType_t xDummy3; + void * pvDummy5; + TaskFunction_t pvDummy6; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy7; + #endif + uint8_t ucDummy8; +} StaticTimer_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the stream buffer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a stream buffer then the size of the stream buffer object needs to be + * known. The StaticStreamBuffer_t structure below is provided for this + * purpose. Its size and alignment requirements are guaranteed to match those + * of the genuine structure, no matter which architecture is being used, and + * no matter how the values in FreeRTOSConfig.h are set. Its contents are + * somewhat obfuscated in the hope users will recognise that it would be unwise + * to make direct use of the structure members. + */ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif + #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + void * pvDummy5[ 2 ]; + #endif +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* INC_FREERTOS_H */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/StackMacros.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/StackMacros.h similarity index 86% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/StackMacros.h rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/StackMacros.h index 0f37c4d..6ec5063 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/StackMacros.h +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/StackMacros.h @@ -1,32 +1,34 @@ -/* - * FreeRTOS Kernel V10.4.3 LTS Patch 2 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - - -#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */ - #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released. -#endif - -#include "stack_macros.h" +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */ + #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in a future release. +#endif + +#include "stack_macros.h" diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/atomic.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/atomic.h new file mode 100644 index 0000000..a7866ed --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/atomic.h @@ -0,0 +1,419 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * @file atomic.h + * @brief FreeRTOS atomic operation support. + * + * This file implements atomic functions by disabling interrupts globally. + * Implementations with architecture specific atomic instructions can be + * provided under each compiler directory. + */ + +#ifndef ATOMIC_H +#define ATOMIC_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include atomic.h" +#endif + +/* Standard includes. */ +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* + * Port specific definitions -- entering/exiting critical section. + * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h + * + * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with + * ATOMIC_ENTER_CRITICAL(). + * + */ +#if defined( portSET_INTERRUPT_MASK_FROM_ISR ) + +/* Nested interrupt scheme is supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() \ + UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR() + + #define ATOMIC_EXIT_CRITICAL() \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType ) + +#else + +/* Nested interrupt scheme is NOT supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL() + #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL() + +#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */ + +/* + * Port specific definition -- "always inline". + * Inline is compiler specific, and may not always get inlined depending on your + * optimization level. Also, inline is considered as performance optimization + * for atomic. Thus, if portFORCE_INLINE is not provided by portmacro.h, + * instead of resulting error, simply define it away. + */ +#ifndef portFORCE_INLINE + #define portFORCE_INLINE +#endif + +#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */ +#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */ + +/*----------------------------- Swap && CAS ------------------------------*/ + +/** + * Atomic compare-and-swap + * + * @brief Performs an atomic compare-and-swap operation on the specified values. + * + * @param[in, out] pulDestination Pointer to memory location from where value is + * to be loaded and checked. + * @param[in] ulExchange If condition meets, write this value to memory. + * @param[in] ulComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *pulDestination with ulExchange, if previous + * *pulDestination value equals ulComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination, + uint32_t ulExchange, + uint32_t ulComparand ) +{ + uint32_t ulReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + if( *pulDestination == ulComparand ) + { + *pulDestination = ulExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + else + { + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic swap (pointers) + * + * @brief Atomically sets the address pointed to by *ppvDestination to the value + * of *pvExchange. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and written back to. + * @param[in] pvExchange Pointer value to be written to *ppvDestination. + * + * @return The initial value of *ppvDestination. + */ +static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange ) +{ + void * pReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + pReturnValue = *ppvDestination; + *ppvDestination = pvExchange; + } + ATOMIC_EXIT_CRITICAL(); + + return pReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic compare-and-swap (pointers) + * + * @brief Performs an atomic compare-and-swap operation on the specified pointer + * values. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and checked. + * @param[in] pvExchange If condition meets, write this value to memory. + * @param[in] pvComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *ppvDestination with pvExchange, if previous + * *ppvDestination value equals pvComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange, + void * pvComparand ) +{ + uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + + ATOMIC_ENTER_CRITICAL(); + { + if( *ppvDestination == pvComparand ) + { + *ppvDestination = pvExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} + + +/*----------------------------- Arithmetic ------------------------------*/ + +/** + * Atomic add + * + * @brief Atomically adds count to the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be added to *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic subtract + * + * @brief Atomically subtracts count from the value of the specified pointer + * pointers to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be subtract from *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic increment + * + * @brief Atomically increments the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before increment. + */ +static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic decrement + * + * @brief Atomically decrements the value of the specified pointer points to + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before decrement. + */ +static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/*----------------------------- Bitwise Logical ------------------------------*/ + +/** + * Atomic OR + * + * @brief Performs an atomic OR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination |= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic AND + * + * @brief Performs an atomic AND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination &= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic NAND + * + * @brief Performs an atomic NAND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be NANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination = ~( ulCurrent & ulValue ); + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic XOR + * + * @brief Performs an atomic XOR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be XORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination ^= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* ATOMIC_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/croutine.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/croutine.h new file mode 100644 index 0000000..4edf47b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/croutine.h @@ -0,0 +1,753 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef CO_ROUTINE_H +#define CO_ROUTINE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include croutine.h" +#endif + +#include "list.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Used to hide the implementation of the co-routine control block. The + * control block structure however has to be included in the header due to + * the macro implementation of the co-routine functionality. */ +typedef void * CoRoutineHandle_t; + +/* Defines the prototype to which co-routine functions must conform. */ +typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t, + UBaseType_t ); + +typedef struct corCoRoutineControlBlock +{ + crCOROUTINE_CODE pxCoRoutineFunction; + ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ + ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */ + UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ + UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ + uint16_t uxState; /*< Used internally by the co-routine implementation. */ +} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */ + +/** + * croutine. h + * @code{c} + * BaseType_t xCoRoutineCreate( + * crCOROUTINE_CODE pxCoRoutineCode, + * UBaseType_t uxPriority, + * UBaseType_t uxIndex + * ); + * @endcode + * + * Create a new co-routine and add it to the list of co-routines that are + * ready to run. + * + * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine + * functions require special syntax - see the co-routine section of the WEB + * documentation for more information. + * + * @param uxPriority The priority with respect to other co-routines at which + * the co-routine will run. + * + * @param uxIndex Used to distinguish between different co-routines that + * execute the same function. See the example below and the co-routine section + * of the WEB documentation for further information. + * + * @return pdPASS if the co-routine was successfully created and added to a ready + * list, otherwise an error code defined with ProjDefs.h. + * + * Example usage: + * @code{c} + * // Co-routine to be created. + * void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * // This may not be necessary for const variables. + * static const char cLedToFlash[ 2 ] = { 5, 6 }; + * static const TickType_t uxFlashRates[ 2 ] = { 200, 400 }; + * + * // Must start every co-routine with a call to crSTART(); + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // This co-routine just delays for a fixed period, then toggles + * // an LED. Two co-routines are created using this function, so + * // the uxIndex parameter is used to tell the co-routine which + * // LED to flash and how int32_t to delay. This assumes xQueue has + * // already been created. + * vParTestToggleLED( cLedToFlash[ uxIndex ] ); + * crDELAY( xHandle, uxFlashRates[ uxIndex ] ); + * } + * + * // Must end every co-routine with a call to crEND(); + * crEND(); + * } + * + * // Function that creates two co-routines. + * void vOtherFunction( void ) + * { + * uint8_t ucParameterToPass; + * TaskHandle_t xHandle; + * + * // Create two co-routines at priority 0. The first is given index 0 + * // so (from the code above) toggles LED 5 every 200 ticks. The second + * // is given index 1 so toggles LED 6 every 400 ticks. + * for( uxIndex = 0; uxIndex < 2; uxIndex++ ) + * { + * xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex ); + * } + * } + * @endcode + * \defgroup xCoRoutineCreate xCoRoutineCreate + * \ingroup Tasks + */ +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, + UBaseType_t uxPriority, + UBaseType_t uxIndex ); + + +/** + * croutine. h + * @code{c} + * void vCoRoutineSchedule( void ); + * @endcode + * + * Run a co-routine. + * + * vCoRoutineSchedule() executes the highest priority co-routine that is able + * to run. The co-routine will execute until it either blocks, yields or is + * preempted by a task. Co-routines execute cooperatively so one + * co-routine cannot be preempted by another, but can be preempted by a task. + * + * If an application comprises of both tasks and co-routines then + * vCoRoutineSchedule should be called from the idle task (in an idle task + * hook). + * + * Example usage: + * @code{c} + * // This idle task hook will schedule a co-routine each time it is called. + * // The rest of the idle task will execute between co-routine calls. + * void vApplicationIdleHook( void ) + * { + * vCoRoutineSchedule(); + * } + * + * // Alternatively, if you do not require any other part of the idle task to + * // execute, the idle task hook can call vCoRoutineSchedule() within an + * // infinite loop. + * void vApplicationIdleHook( void ) + * { + * for( ;; ) + * { + * vCoRoutineSchedule(); + * } + * } + * @endcode + * \defgroup vCoRoutineSchedule vCoRoutineSchedule + * \ingroup Tasks + */ +void vCoRoutineSchedule( void ); + +/** + * croutine. h + * @code{c} + * crSTART( CoRoutineHandle_t xHandle ); + * @endcode + * + * This macro MUST always be called at the start of a co-routine function. + * + * Example usage: + * @code{c} + * // Co-routine to be created. + * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * static int32_t ulAVariable; + * + * // Must start every co-routine with a call to crSTART(); + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Co-routine functionality goes here. + * } + * + * // Must end every co-routine with a call to crEND(); + * crEND(); + * } + * @endcode + * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crSTART( pxCRCB ) \ + switch( ( ( CRCB_t * ) ( pxCRCB ) )->uxState ) { \ + case 0: + +/** + * croutine. h + * @code{c} + * crEND(); + * @endcode + * + * This macro MUST always be called at the end of a co-routine function. + * + * Example usage: + * @code{c} + * // Co-routine to be created. + * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * static int32_t ulAVariable; + * + * // Must start every co-routine with a call to crSTART(); + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Co-routine functionality goes here. + * } + * + * // Must end every co-routine with a call to crEND(); + * crEND(); + * } + * @endcode + * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crEND() } + +/* + * These macros are intended for internal use by the co-routine implementation + * only. The macros should not be used directly by application writers. + */ +#define crSET_STATE0( xHandle ) \ + ( ( CRCB_t * ) ( xHandle ) )->uxState = ( __LINE__ * 2 ); return; \ + case ( __LINE__ * 2 ): +#define crSET_STATE1( xHandle ) \ + ( ( CRCB_t * ) ( xHandle ) )->uxState = ( ( __LINE__ * 2 ) + 1 ); return; \ + case ( ( __LINE__ * 2 ) + 1 ): + +/** + * croutine. h + * @code{c} + * crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay ); + * @endcode + * + * Delay a co-routine for a fixed period of time. + * + * crDELAY can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * @param xHandle The handle of the co-routine to delay. This is the xHandle + * parameter of the co-routine function. + * + * @param xTickToDelay The number of ticks that the co-routine should delay + * for. The actual amount of time this equates to is defined by + * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS + * can be used to convert ticks to milliseconds. + * + * Example usage: + * @code{c} + * // Co-routine to be created. + * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * // This may not be necessary for const variables. + * // We are to delay for 200ms. + * static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS; + * + * // Must start every co-routine with a call to crSTART(); + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Delay for 200ms. + * crDELAY( xHandle, xDelayTime ); + * + * // Do something here. + * } + * + * // Must end every co-routine with a call to crEND(); + * crEND(); + * } + * @endcode + * \defgroup crDELAY crDELAY + * \ingroup Tasks + */ +#define crDELAY( xHandle, xTicksToDelay ) \ + if( ( xTicksToDelay ) > 0 ) \ + { \ + vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ + } \ + crSET_STATE0( ( xHandle ) ); + +/** + * @code{c} + * crQUEUE_SEND( + * CoRoutineHandle_t xHandle, + * QueueHandle_t pxQueue, + * void *pvItemToQueue, + * TickType_t xTicksToWait, + * BaseType_t *pxResult + * ) + * @endcode + * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_SEND can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue on which the data will be posted. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvItemToQueue A pointer to the data being posted onto the queue. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied from pvItemToQueue into the queue + * itself. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for space to become available on the queue, should space not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example + * below). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully posted onto the queue, otherwise it will be set to an + * error defined within ProjDefs.h. + * + * Example usage: + * @code{c} + * // Co-routine function that blocks for a fixed period then posts a number onto + * // a queue. + * static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * static BaseType_t xNumberToPost = 0; + * static BaseType_t xResult; + * + * // Co-routines must begin with a call to crSTART(). + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // This assumes the queue has already been created. + * crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult ); + * + * if( xResult != pdPASS ) + * { + * // The message was not posted! + * } + * + * // Increment the number to be posted onto the queue. + * xNumberToPost++; + * + * // Delay for 100 ticks. + * crDELAY( xHandle, 100 ); + * } + * + * // Co-routines must end with a call to crEND(). + * crEND(); + * } + * @endcode + * \defgroup crQUEUE_SEND crQUEUE_SEND + * \ingroup Tasks + */ +#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ + { \ + *( pxResult ) = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *pxResult = pdPASS; \ + } \ + } + +/** + * croutine. h + * @code{c} + * crQUEUE_RECEIVE( + * CoRoutineHandle_t xHandle, + * QueueHandle_t pxQueue, + * void *pvBuffer, + * TickType_t xTicksToWait, + * BaseType_t *pxResult + * ) + * @endcode + * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_RECEIVE can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue from which the data will be received. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvBuffer The buffer into which the received item is to be copied. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied into pvBuffer. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for data to become available from the queue, should data not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the + * crQUEUE_SEND example). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully retrieved from the queue, otherwise it will be set to + * an error code as defined within ProjDefs.h. + * + * Example usage: + * @code{c} + * // A co-routine receives the number of an LED to flash from a queue. It + * // blocks on the queue until the number is received. + * static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * static BaseType_t xResult; + * static UBaseType_t uxLEDToFlash; + * + * // All co-routines must start with a call to crSTART(). + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Wait for data to become available on the queue. + * crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); + * + * if( xResult == pdPASS ) + * { + * // We received the LED to flash - flash it! + * vParTestToggleLED( uxLEDToFlash ); + * } + * } + * + * crEND(); + * } + * @endcode + * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ + { \ + *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), 0 ); \ + } \ + if( *( pxResult ) == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *( pxResult ) = pdPASS; \ + } \ + } + +/** + * croutine. h + * @code{c} + * crQUEUE_SEND_FROM_ISR( + * QueueHandle_t pxQueue, + * void *pvItemToQueue, + * BaseType_t xCoRoutinePreviouslyWoken + * ) + * @endcode + * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue + * that is being used from within a co-routine. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. + * + * @return pdTRUE if a co-routine was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + * @code{c} + * // A co-routine that blocks on a queue waiting for characters to be received. + * static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * char cRxedChar; + * BaseType_t xResult; + * + * // All co-routines must start with a call to crSTART(). + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Wait for data to become available on the queue. This assumes the + * // queue xCommsRxQueue has already been created! + * crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); + * + * // Was a character received? + * if( xResult == pdPASS ) + * { + * // Process the character here. + * } + * } + * + * // All co-routines must end with a call to crEND(). + * crEND(); + * } + * + * // An ISR that uses a queue to send characters received on a serial port to + * // a co-routine. + * void vUART_ISR( void ) + * { + * char cRxedChar; + * BaseType_t xCRWokenByPost = pdFALSE; + * + * // We loop around reading characters until there are none left in the UART. + * while( UART_RX_REG_NOT_EMPTY() ) + * { + * // Obtain the character from the UART. + * cRxedChar = UART_RX_REG; + * + * // Post the character onto a queue. xCRWokenByPost will be pdFALSE + * // the first time around the loop. If the post causes a co-routine + * // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE. + * // In this manner we can ensure that if more than one co-routine is + * // blocked on the queue only one is woken by this ISR no matter how + * // many characters are posted to the queue. + * xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost ); + * } + * } + * @endcode + * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) \ + xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) + + +/** + * croutine. h + * @code{c} + * crQUEUE_SEND_FROM_ISR( + * QueueHandle_t pxQueue, + * void *pvBuffer, + * BaseType_t * pxCoRoutineWoken + * ) + * @endcode + * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data + * from a queue that is being used from within a co-routine (a co-routine + * posted to the queue). + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvBuffer A pointer to a buffer into which the received item will be + * placed. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from the queue into + * pvBuffer. + * + * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become + * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a + * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise + * *pxCoRoutineWoken will remain unchanged. + * + * @return pdTRUE an item was successfully received from the queue, otherwise + * pdFALSE. + * + * Example usage: + * @code{c} + * // A co-routine that posts a character to a queue then blocks for a fixed + * // period. The character is incremented each time. + * static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // cChar holds its value while this co-routine is blocked and must therefore + * // be declared static. + * static char cCharToTx = 'a'; + * BaseType_t xResult; + * + * // All co-routines must start with a call to crSTART(). + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Send the next character to the queue. + * crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult ); + * + * if( xResult == pdPASS ) + * { + * // The character was successfully posted to the queue. + * } + * else + * { + * // Could not post the character to the queue. + * } + * + * // Enable the UART Tx interrupt to cause an interrupt in this + * // hypothetical UART. The interrupt will obtain the character + * // from the queue and send it. + * ENABLE_RX_INTERRUPT(); + * + * // Increment to the next character then block for a fixed period. + * // cCharToTx will maintain its value across the delay as it is + * // declared static. + * cCharToTx++; + * if( cCharToTx > 'x' ) + * { + * cCharToTx = 'a'; + * } + * crDELAY( 100 ); + * } + * + * // All co-routines must end with a call to crEND(). + * crEND(); + * } + * + * // An ISR that uses a queue to receive characters to send on a UART. + * void vUART_ISR( void ) + * { + * char cCharToTx; + * BaseType_t xCRWokenByPost = pdFALSE; + * + * while( UART_TX_REG_EMPTY() ) + * { + * // Are there any characters in the queue waiting to be sent? + * // xCRWokenByPost will automatically be set to pdTRUE if a co-routine + * // is woken by the post - ensuring that only a single co-routine is + * // woken no matter how many times we go around this loop. + * if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) ) + * { + * SEND_CHARACTER( cCharToTx ); + * } + * } + * } + * @endcode + * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) \ + xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) + +/* + * This function is intended for internal use by the co-routine macros only. + * The macro nature of the co-routine implementation requires that the + * prototype appears here. The function should not be used by application + * writers. + * + * Removes the current co-routine from its ready list and places it in the + * appropriate delayed list. + */ +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, + List_t * pxEventList ); + +/* + * This function is intended for internal use by the queue implementation only. + * The function should not be used by application writers. + * + * Removes the highest priority co-routine from the event list and places it in + * the pending ready list. + */ +BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList ); + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* CO_ROUTINE_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/deprecated_definitions.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/deprecated_definitions.h new file mode 100644 index 0000000..6ca125b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/deprecated_definitions.h @@ -0,0 +1,281 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef DEPRECATED_DEFINITIONS_H +#define DEPRECATED_DEFINITIONS_H + + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a + * pre-processor definition was used to ensure the pre-processor found the correct + * portmacro.h file for the port being used. That scheme was deprecated in favour + * of setting the compiler's include path such that it found the correct + * portmacro.h file - removing the need for the constant and allowing the + * portmacro.h file to be located anywhere in relation to the port being used. The + * definitions below remain in the code for backward compatibility only. New + * projects should not use them. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef IAR_MSP430 + #include "..\..\Source\portable\IAR\MSP430\portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef ARM7_LPC21xx_KEIL_RVDS + #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef SAM9XE_IAR + #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_GCC + #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_CODEWARRIOR + #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" +#endif + +#ifdef GCC_PPC405 + #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" +#endif + +#ifdef GCC_PPC440 + #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" +#endif + +#ifdef _16FX_SOFTUNE + #include "..\..\Source\portable\Softune\MB96340\portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + +/* A short file name has to be used in place of the normal + * FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + +/* A short file name has to be used in place of the normal + * FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + + +#ifdef __IAR_V850ES_Fx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3_L__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Hx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3L__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#endif /* DEPRECATED_DEFINITIONS_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/event_groups.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/event_groups.h new file mode 100644 index 0000000..275f316 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/event_groups.h @@ -0,0 +1,783 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef EVENT_GROUPS_H +#define EVENT_GROUPS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" +#endif + +/* FreeRTOS includes. */ +#include "timers.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * An event group is a collection of bits to which an application can assign a + * meaning. For example, an application may create an event group to convey + * the status of various CAN bus related events in which bit 0 might mean "A CAN + * message has been received and is ready for processing", bit 1 might mean "The + * application has queued a message that is ready for sending onto the CAN + * network", and bit 2 might mean "It is time to send a SYNC message onto the + * CAN network" etc. A task can then test the bit values to see which events + * are active, and optionally enter the Blocked state to wait for a specified + * bit or a group of specified bits to be active. To continue the CAN bus + * example, a CAN controlling task can enter the Blocked state (and therefore + * not consume any processing time) until either bit 0, bit 1 or bit 2 are + * active, at which time the bit that was actually active would inform the task + * which action it had to take (process a received message, send a message, or + * send a SYNC). + * + * The event groups implementation contains intelligence to avoid race + * conditions that would otherwise occur were an application to use a simple + * variable for the same purpose. This is particularly important with respect + * to when a bit within an event group is to be cleared, and when bits have to + * be set and then tested atomically - as is the case where event groups are + * used to create a synchronisation point between multiple tasks (a + * 'rendezvous'). + */ + + + +/** + * event_groups.h + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \defgroup EventGroupHandle_t EventGroupHandle_t + * \ingroup EventGroup + */ +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; + +/* + * The type that holds event bits always matches TickType_t - therefore the + * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, + * 32 bits if set to 0. + * + * \defgroup EventBits_t EventBits_t + * \ingroup EventGroup + */ +typedef TickType_t EventBits_t; + +/** + * event_groups.h + * @code{c} + * EventGroupHandle_t xEventGroupCreate( void ); + * @endcode + * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGroupCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see https://www.FreeRTOS.org/a00111.html). If an event group is created + * using xEventGroupCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See https://www.FreeRTOS.org/a00111.html + * + * Example usage: + * @code{c} + * // Declare a variable to hold the created event group. + * EventGroupHandle_t xCreatedEventGroup; + * + * // Attempt to create the event group. + * xCreatedEventGroup = xEventGroupCreate(); + * + * // Was the event group created successfully? + * if( xCreatedEventGroup == NULL ) + * { + * // The event group was not created because there was insufficient + * // FreeRTOS heap available. + * } + * else + * { + * // The event group was created. + * } + * @endcode + * \defgroup xEventGroupCreate xEventGroupCreate + * \ingroup EventGroup + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + * @code{c} + * EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer ); + * @endcode + * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGroupCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see https://www.FreeRTOS.org/a00111.html). If an event group is created + * using xEventGroupCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type + * StaticEventGroup_t, which will be then be used to hold the event group's data + * structures, removing the need for the memory to be allocated dynamically. + * + * @return If the event group was created then a handle to the event group is + * returned. If pxEventGroupBuffer was NULL then NULL is returned. + * + * Example usage: + * @code{c} + * // StaticEventGroup_t is a publicly accessible structure that has the same + * // size and alignment requirements as the real event group structure. It is + * // provided as a mechanism for applications to know the size of the event + * // group (which is dependent on the architecture and configuration file + * // settings) without breaking the strict data hiding policy by exposing the + * // real event group internals. This StaticEventGroup_t variable is passed + * // into the xSemaphoreCreateEventGroupStatic() function and is used to store + * // the event group's data structures + * StaticEventGroup_t xEventGroupBuffer; + * + * // Create the event group without dynamically allocating any memory. + * xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer ); + * @endcode + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + * const EventBits_t uxBitsToWaitFor, + * const BaseType_t xClearOnExit, + * const BaseType_t xWaitForAllBits, + * const TickType_t xTicksToWait ); + * @endcode + * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. A value of portMAX_DELAY can be used to block + * indefinitely (provided INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h). + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * void aFunction( EventGroupHandle_t xEventGroup ) + * { + * EventBits_t uxBits; + * const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS; + * + * // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within + * // the event group. Clear the bits before exiting. + * uxBits = xEventGroupWaitBits( + * xEventGroup, // The event group being tested. + * BIT_0 | BIT_4, // The bits within the event group to wait for. + * pdTRUE, // BIT_0 and BIT_4 should be cleared before returning. + * pdFALSE, // Don't wait for both bits, either bit will do. + * xTicksToWait ); // Wait a maximum of 100ms for either bit to be set. + * + * if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) ) + * { + * // xEventGroupWaitBits() returned because both bits were set. + * } + * else if( ( uxBits & BIT_0 ) != 0 ) + * { + * // xEventGroupWaitBits() returned because just BIT_0 was set. + * } + * else if( ( uxBits & BIT_4 ) != 0 ) + * { + * // xEventGroupWaitBits() returned because just BIT_4 was set. + * } + * else + * { + * // xEventGroupWaitBits() returned because xTicksToWait ticks passed + * // without either BIT_0 or BIT_4 becoming set. + * } + * } + * @endcode + * \defgroup xEventGroupWaitBits xEventGroupWaitBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ); + * @endcode + * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * void aFunction( EventGroupHandle_t xEventGroup ) + * { + * EventBits_t uxBits; + * + * // Clear bit 0 and bit 4 in xEventGroup. + * uxBits = xEventGroupClearBits( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 );// The bits being cleared. + * + * if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) ) + * { + * // Both bit 0 and bit 4 were set before xEventGroupClearBits() was + * // called. Both will now be clear (not set). + * } + * else if( ( uxBits & BIT_0 ) != 0 ) + * { + * // Bit 0 was set before xEventGroupClearBits() was called. It will + * // now be clear. + * } + * else if( ( uxBits & BIT_4 ) != 0 ) + * { + * // Bit 4 was set before xEventGroupClearBits() was called. It will + * // now be clear. + * } + * else + * { + * // Neither bit 0 nor bit 4 were set in the first place. + * } + * } + * @endcode + * \defgroup xEventGroupClearBits xEventGroupClearBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * @code{c} + * BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ); + * @endcode + * + * A version of xEventGroupClearBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed + * while interrupts are disabled, so protects event groups that are accessed + * from tasks by suspending the scheduler rather than disabling interrupts. As + * a result event groups cannot be accessed directly from an interrupt service + * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the + * timer task to have the clear operation performed in the context of the timer + * task. + * + * @note If this function returns pdPASS then the timer task is ready to run + * and a portYIELD_FROM_ISR(pdTRUE) should be executed to perform the needed + * clear on the event group. This behavior is different from + * xEventGroupSetBitsFromISR because the parameter xHigherPriorityTaskWoken is + * not present. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. + * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 + * and bit 0 set uxBitsToClear to 0x09. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * // An event group which it is assumed has already been created by a call to + * // xEventGroupCreate(). + * EventGroupHandle_t xEventGroup; + * + * void anInterruptHandler( void ) + * { + * // Clear bit 0 and bit 4 in xEventGroup. + * xResult = xEventGroupClearBitsFromISR( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 ); // The bits being set. + * + * if( xResult == pdPASS ) + * { + * // The message was posted successfully. + * portYIELD_FROM_ISR(pdTRUE); + * } + * } + * @endcode + * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR + * \ingroup EventGroup + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) \ + xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToClear ), NULL ) +#endif + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ); + * @endcode + * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. There are two reasons why the returned value + * might have the bits specified by the uxBitsToSet parameter cleared. First, + * if setting a bit results in a task that was waiting for the bit leaving the + * blocked state then it is possible the bit will be cleared automatically + * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any + * unblocked (or otherwise Ready state) task that has a priority above that of + * the task that called xEventGroupSetBits() will execute and may change the + * event group value before the call to xEventGroupSetBits() returns. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * void aFunction( EventGroupHandle_t xEventGroup ) + * { + * EventBits_t uxBits; + * + * // Set bit 0 and bit 4 in xEventGroup. + * uxBits = xEventGroupSetBits( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 );// The bits being set. + * + * if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) ) + * { + * // Both bit 0 and bit 4 remained set when the function returned. + * } + * else if( ( uxBits & BIT_0 ) != 0 ) + * { + * // Bit 0 remained set when the function returned, but bit 4 was + * // cleared. It might be that bit 4 was cleared automatically as a + * // task that was waiting for bit 4 was removed from the Blocked + * // state. + * } + * else if( ( uxBits & BIT_4 ) != 0 ) + * { + * // Bit 4 remained set when the function returned, but bit 0 was + * // cleared. It might be that bit 0 was cleared automatically as a + * // task that was waiting for bit 0 was removed from the Blocked + * // state. + * } + * else + * { + * // Neither bit 0 nor bit 4 remained set. It might be that a task + * // was waiting for both of the bits to be set, and the bits were + * // cleared as the task left the Blocked state. + * } + * } + * @endcode + * \defgroup xEventGroupSetBits xEventGroupSetBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * @code{c} + * BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * A version of xEventGroupSetBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed in + * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() + * sends a message to the timer task to have the set operation performed in the + * context of the timer task - where a scheduler lock is used in place of a + * critical section. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task is higher than the priority of the + * currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE by + * xEventGroupSetBitsFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * // An event group which it is assumed has already been created by a call to + * // xEventGroupCreate(). + * EventGroupHandle_t xEventGroup; + * + * void anInterruptHandler( void ) + * { + * BaseType_t xHigherPriorityTaskWoken, xResult; + * + * // xHigherPriorityTaskWoken must be initialised to pdFALSE. + * xHigherPriorityTaskWoken = pdFALSE; + * + * // Set bit 0 and bit 4 in xEventGroup. + * xResult = xEventGroupSetBitsFromISR( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 // The bits being set. + * &xHigherPriorityTaskWoken ); + * + * // Was the message posted successfully? + * if( xResult == pdPASS ) + * { + * // If xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and + * // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - + * // refer to the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * } + * @endcode + * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) \ + xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToSet ), ( pxHigherPriorityTaskWoken ) ) +#endif + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, + * const EventBits_t uxBitsToSet, + * const EventBits_t uxBitsToWaitFor, + * TickType_t xTicksToWait ); + * @endcode + * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + * @code{c} + * // Bits used by the three tasks. + * #define TASK_0_BIT ( 1 << 0 ) + * #define TASK_1_BIT ( 1 << 1 ) + * #define TASK_2_BIT ( 1 << 2 ) + * + * #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT ) + * + * // Use an event group to synchronise three tasks. It is assumed this event + * // group has already been created elsewhere. + * EventGroupHandle_t xEventBits; + * + * void vTask0( void *pvParameters ) + * { + * EventBits_t uxReturn; + * TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS; + * + * for( ;; ) + * { + * // Perform task functionality here. + * + * // Set bit 0 in the event flag to note this task has reached the + * // sync point. The other two tasks will set the other two bits defined + * // by ALL_SYNC_BITS. All three tasks have reached the synchronisation + * // point when all the ALL_SYNC_BITS are set. Wait a maximum of 100ms + * // for this to happen. + * uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait ); + * + * if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS ) + * { + * // All three tasks reached the synchronisation point before the call + * // to xEventGroupSync() timed out. + * } + * } + * } + * + * void vTask1( void *pvParameters ) + * { + * for( ;; ) + * { + * // Perform task functionality here. + * + * // Set bit 1 in the event flag to note this task has reached the + * // synchronisation point. The other two tasks will set the other two + * // bits defined by ALL_SYNC_BITS. All three tasks have reached the + * // synchronisation point when all the ALL_SYNC_BITS are set. Wait + * // indefinitely for this to happen. + * xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY ); + * + * // xEventGroupSync() was called with an indefinite block time, so + * // this task will only reach here if the synchronisation was made by all + * // three tasks, so there is no need to test the return value. + * } + * } + * + * void vTask2( void *pvParameters ) + * { + * for( ;; ) + * { + * // Perform task functionality here. + * + * // Set bit 2 in the event flag to note this task has reached the + * // synchronisation point. The other two tasks will set the other two + * // bits defined by ALL_SYNC_BITS. All three tasks have reached the + * // synchronisation point when all the ALL_SYNC_BITS are set. Wait + * // indefinitely for this to happen. + * xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY ); + * + * // xEventGroupSync() was called with an indefinite block time, so + * // this task will only reach here if the synchronisation was made by all + * // three tasks, so there is no need to test the return value. + * } + * } + * + * @endcode + * \defgroup xEventGroupSync xEventGroupSync + * \ingroup EventGroup + */ +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup ); + * @endcode + * + * Returns the current value of the bits in an event group. This function + * cannot be used from an interrupt. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBits() was called. + * + * \defgroup xEventGroupGetBits xEventGroupGetBits + * \ingroup EventGroup + */ +#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( ( xEventGroup ), 0 ) + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ); + * @endcode + * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR + * \ingroup EventGroup + */ +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * @code{c} + * void xEventGroupDelete( EventGroupHandle_t xEventGroup ); + * @endcode + * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * @param xEventGroup The event group being deleted. + */ +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/* For internal use only. */ +void vEventGroupSetBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; +void vEventGroupClearBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + + +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) PRIVILEGED_FUNCTION; + void vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* EVENT_GROUPS_H */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/freertos_tasks_c_additions.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/freertos_tasks_c_additions.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/freertos_tasks_c_additions.h rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/freertos_tasks_c_additions.h diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/list.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/list.h new file mode 100644 index 0000000..e366319 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/list.h @@ -0,0 +1,503 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * ascending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + + +#ifndef LIST_H +#define LIST_H + +#ifndef INC_FREERTOS_H + #error "FreeRTOS.h must be included before list.h" +#endif + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Macros that can be used to place known values within the list structures, + * then check that the known values do not get corrupted during the execution of + * the application. These may catch the list data structures being overwritten in + * memory. They will not catch data errors caused by incorrect configuration or + * use of FreeRTOS.*/ +#if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else /* if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) */ + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + +/* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + +/* Define macros that will assert if one of the structure members does not + * contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST; +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in ascending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ + +#if ( configUSE_MINI_LIST_ITEM == 1 ) + struct xMINI_LIST_ITEM + { + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; + }; + typedef struct xMINI_LIST_ITEM MiniListItem_t; +#else + typedef struct xLIST_ITEM MiniListItem_t; +#endif + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + volatile UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in ascending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the next list item. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ + { \ + List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ + } + +/* + * Version of uxListRemove() that does not return a value. Provided as a slight + * optimisation for xTaskIncrementTick() by being inline. + * + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page listREMOVE_ITEM listREMOVE_ITEM + * \ingroup LinkedList + */ +#define listREMOVE_ITEM( pxItemToRemove ) \ + { \ + /* The list item knows which list it is in. Obtain the list from the list \ + * item. */ \ + List_t * const pxList = ( pxItemToRemove )->pxContainer; \ + \ + ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious; \ + ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext; \ + /* Make sure the index is left pointing to a valid item. */ \ + if( pxList->pxIndex == ( pxItemToRemove ) ) \ + { \ + pxList->pxIndex = ( pxItemToRemove )->pxPrevious; \ + } \ + \ + ( pxItemToRemove )->pxContainer = NULL; \ + ( pxList->uxNumberOfItems )--; \ + } + +/* + * Inline version of vListInsertEnd() to provide slight optimisation for + * xTaskIncrementTick(). + * + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page listINSERT_END listINSERT_END + * \ingroup LinkedList + */ +#define listINSERT_END( pxList, pxNewListItem ) \ + { \ + ListItem_t * const pxIndex = ( pxList )->pxIndex; \ + \ + /* Only effective when configASSERT() is also defined, these tests may catch \ + * the list data structures being overwritten in memory. They will not catch \ + * data errors caused by incorrect configuration or use of FreeRTOS. */ \ + listTEST_LIST_INTEGRITY( ( pxList ) ); \ + listTEST_LIST_ITEM_INTEGRITY( ( pxNewListItem ) ); \ + \ + /* Insert a new list item into ( pxList ), but rather than sort the list, \ + * makes the new list item the last item to be removed by a call to \ + * listGET_OWNER_OF_NEXT_ENTRY(). */ \ + ( pxNewListItem )->pxNext = pxIndex; \ + ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious; \ + \ + pxIndex->pxPrevious->pxNext = ( pxNewListItem ); \ + pxIndex->pxPrevious = ( pxNewListItem ); \ + \ + /* Remember which list the item is in. */ \ + ( pxNewListItem )->pxContainer = ( pxList ); \ + \ + ( ( pxList )->uxNumberOfItems )++; \ + } + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (ascending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, + ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, + ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* ifndef LIST_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/message_buffer.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/message_buffer.h new file mode 100644 index 0000000..24d59e2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/message_buffer.h @@ -0,0 +1,856 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Message buffers build functionality on top of FreeRTOS stream buffers. + * Whereas stream buffers are used to send a continuous stream of data from one + * task or interrupt to another, message buffers are used to send variable + * length discrete messages from one task or interrupt to another. Their + * implementation is light weight, making them particularly suited for interrupt + * to task and core to core communication scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * timeout to 0. + * + * Message buffers hold variable length messages. To enable that, when a + * message is written to the message buffer an additional sizeof( size_t ) bytes + * are also written to store the message's length (that happens internally, with + * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so writing a 10 byte message to a message buffer on a 32-bit + * architecture will actually reduce the available space in the message buffer + * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length + * of the message). + */ + +#ifndef FREERTOS_MESSAGE_BUFFER_H +#define FREERTOS_MESSAGE_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include message_buffer.h" +#endif + +/* Message buffers are built onto of stream buffers. */ +#include "stream_buffer.h" + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * Type by which message buffers are referenced. For example, a call to + * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can + * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), + * etc. Message buffer is essentially built as a stream buffer hence its handle + * is also set to same type as a stream buffer handle. + */ +typedef StreamBufferHandle_t MessageBufferHandle_t; + +/*-----------------------------------------------------------*/ + +/** + * message_buffer.h + * + * @code{c} + * MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes ); + * @endcode + * + * Creates a new message buffer using dynamically allocated memory. See + * xMessageBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xMessageBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes (not messages) the message + * buffer will be able to hold at any one time. When a message is written to + * the message buffer an additional sizeof( size_t ) bytes are also written to + * store the message's length. sizeof( size_t ) is typically 4 bytes on a + * 32-bit architecture, so on most 32-bit architectures a 10 byte message will + * take up 14 bytes of message buffer space. + * + * @param pxSendCompletedCallback Callback invoked when a send operation to the + * message buffer is complete. If the parameter is NULL or xMessageBufferCreate() + * is called without the parameter, then it will use the default implementation + * provided by sbSEND_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @param pxReceiveCompletedCallback Callback invoked when a receive operation from + * the message buffer is complete. If the parameter is NULL or xMessageBufferCreate() + * is called without the parameter, it will use the default implementation provided + * by sbRECEIVE_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @return If NULL is returned, then the message buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the message buffer data structures and storage area. A non-NULL value being + * returned indicates that the message buffer has been created successfully - + * the returned value should be stored as the handle to the created message + * buffer. + * + * Example use: + * @code{c} + * + * void vAFunction( void ) + * { + * MessageBufferHandle_t xMessageBuffer; + * const size_t xMessageBufferSizeBytes = 100; + * + * // Create a message buffer that can hold 100 bytes. The memory used to hold + * // both the message buffer structure and the messages themselves is allocated + * // dynamically. Each message added to the buffer consumes an additional 4 + * // bytes which are used to hold the length of the message. + * xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes ); + * + * if( xMessageBuffer == NULL ) + * { + * // There was not enough heap memory space available to create the + * // message buffer. + * } + * else + * { + * // The message buffer was created successfully and can now be used. + * } + * + * @endcode + * \defgroup xMessageBufferCreate xMessageBufferCreate + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreate( xBufferSizeBytes ) \ + xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, NULL, NULL ) + +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define xMessageBufferCreateWithCallback( xBufferSizeBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \ + xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) ) +#endif + +/** + * message_buffer.h + * + * @code{c} + * MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes, + * uint8_t *pucMessageBufferStorageArea, + * StaticMessageBuffer_t *pxStaticMessageBuffer ); + * @endcode + * Creates a new message buffer using statically allocated memory. See + * xMessageBufferCreate() for a version that uses dynamically allocated memory. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucMessageBufferStorageArea parameter. When a message is written to the + * message buffer an additional sizeof( size_t ) bytes are also written to store + * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so on most 32-bit architecture a 10 byte message will take up + * 14 bytes of message buffer space. The maximum number of bytes that can be + * stored in the message buffer is actually (xBufferSizeBytes - 1). + * + * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes big. This is the array to which messages are + * copied when they are written to the message buffer. + * + * @param pxStaticMessageBuffer Must point to a variable of type + * StaticMessageBuffer_t, which will be used to hold the message buffer's data + * structure. + * + * @param pxSendCompletedCallback Callback invoked when a new message is sent to the message buffer. + * If the parameter is NULL or xMessageBufferCreate() is called without the parameter, then it will use the default + * implementation provided by sbSEND_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @param pxReceiveCompletedCallback Callback invoked when a message is read from a + * message buffer. If the parameter is NULL or xMessageBufferCreate() is called without the parameter, it will + * use the default implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @return If the message buffer is created successfully then a handle to the + * created message buffer is returned. If either pucMessageBufferStorageArea or + * pxStaticmessageBuffer are NULL then NULL is returned. + * + * Example use: + * @code{c} + * + * // Used to dimension the array used to hold the messages. The available space + * // will actually be one less than this, so 999. + #define STORAGE_SIZE_BYTES 1000 + * + * // Defines the memory that will actually hold the messages within the message + * // buffer. + * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ]; + * + * // The variable used to hold the message buffer structure. + * StaticMessageBuffer_t xMessageBufferStruct; + * + * void MyFunction( void ) + * { + * MessageBufferHandle_t xMessageBuffer; + * + * xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucStorageBuffer ), + * ucStorageBuffer, + * &xMessageBufferStruct ); + * + * // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer + * // parameters were NULL, xMessageBuffer will not be NULL, and can be used to + * // reference the created message buffer in other message buffer API calls. + * + * // Other code that uses the message buffer can go here. + * } + * + * @endcode + * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \ + xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), NULL, NULL ) + +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define xMessageBufferCreateStaticWithCallback( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \ + xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) ) +#endif + +/** + * message_buffer.h + * + * @code{c} + * size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer, + * const void *pvTxData, + * size_t xDataLengthBytes, + * TickType_t xTicksToWait ); + * @endcode + * + * Sends a discrete message to the message buffer. The message can be any + * length that fits within the buffer's free space, and is copied into the + * buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferSend() to write to a message buffer from a task. Use + * xMessageBufferSendFromISR() to write to a message buffer from an interrupt + * service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer to which a message is + * being sent. + * + * @param pvTxData A pointer to the message that is to be copied into the + * message buffer. + * + * @param xDataLengthBytes The length of the message. That is, the number of + * bytes to copy from pvTxData into the message buffer. When a message is + * written to the message buffer an additional sizeof( size_t ) bytes are also + * written to store the message's length. sizeof( size_t ) is typically 4 bytes + * on a 32-bit architecture, so on most 32-bit architecture setting + * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24 + * bytes (20 bytes of message data and 4 bytes to hold the message length). + * + * @param xTicksToWait The maximum amount of time the calling task should remain + * in the Blocked state to wait for enough space to become available in the + * message buffer, should the message buffer have insufficient space when + * xMessageBufferSend() is called. The calling task will never block if + * xTicksToWait is zero. The block time is specified in tick periods, so the + * absolute time it represents is dependent on the tick frequency. The macro + * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into + * a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will cause + * the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any + * CPU time when they are in the Blocked state. + * + * @return The number of bytes written to the message buffer. If the call to + * xMessageBufferSend() times out before there was enough space to write the + * message into the message buffer then zero is returned. If the call did not + * time out then xDataLengthBytes is returned. + * + * Example use: + * @code{c} + * void vAFunction( MessageBufferHandle_t xMessageBuffer ) + * { + * size_t xBytesSent; + * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 }; + * char *pcStringToSend = "String to send"; + * const TickType_t x100ms = pdMS_TO_TICKS( 100 ); + * + * // Send an array to the message buffer, blocking for a maximum of 100ms to + * // wait for enough space to be available in the message buffer. + * xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms ); + * + * if( xBytesSent != sizeof( ucArrayToSend ) ) + * { + * // The call to xMessageBufferSend() times out before there was enough + * // space in the buffer for the data to be written. + * } + * + * // Send the string to the message buffer. Return immediately if there is + * // not enough space in the buffer. + * xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // The string could not be added to the message buffer because there was + * // not enough free space in the buffer. + * } + * } + * @endcode + * \defgroup xMessageBufferSend xMessageBufferSend + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) \ + xStreamBufferSend( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( xTicksToWait ) ) + +/** + * message_buffer.h + * + * @code{c} + * size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer, + * const void *pvTxData, + * size_t xDataLengthBytes, + * BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * Interrupt safe version of the API function that sends a discrete message to + * the message buffer. The message can be any length that fits within the + * buffer's free space, and is copied into the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferSend() to write to a message buffer from a task. Use + * xMessageBufferSendFromISR() to write to a message buffer from an interrupt + * service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer to which a message is + * being sent. + * + * @param pvTxData A pointer to the message that is to be copied into the + * message buffer. + * + * @param xDataLengthBytes The length of the message. That is, the number of + * bytes to copy from pvTxData into the message buffer. When a message is + * written to the message buffer an additional sizeof( size_t ) bytes are also + * written to store the message's length. sizeof( size_t ) is typically 4 bytes + * on a 32-bit architecture, so on most 32-bit architecture setting + * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24 + * bytes (20 bytes of message data and 4 bytes to hold the message length). + * + * @param pxHigherPriorityTaskWoken It is possible that a message buffer will + * have a task blocked on it waiting for data. Calling + * xMessageBufferSendFromISR() can make data available, and so cause a task that + * was waiting for data to leave the Blocked state. If calling + * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the + * unblocked task has a priority higher than the currently executing task (the + * task that was interrupted), then, internally, xMessageBufferSendFromISR() + * will set *pxHigherPriorityTaskWoken to pdTRUE. If + * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. This will + * ensure that the interrupt returns directly to the highest priority Ready + * state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it + * is passed into the function. See the code example below for an example. + * + * @return The number of bytes actually written to the message buffer. If the + * message buffer didn't have enough free space for the message to be stored + * then 0 is returned, otherwise xDataLengthBytes is returned. + * + * Example use: + * @code{c} + * // A message buffer that has already been created. + * MessageBufferHandle_t xMessageBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * size_t xBytesSent; + * char *pcStringToSend = "String to send"; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Attempt to send the string to the message buffer. + * xBytesSent = xMessageBufferSendFromISR( xMessageBuffer, + * ( void * ) pcStringToSend, + * strlen( pcStringToSend ), + * &xHigherPriorityTaskWoken ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // The string could not be added to the message buffer because there was + * // not enough free space in the buffer. + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xMessageBufferSendFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) \ + xStreamBufferSendFromISR( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( pxHigherPriorityTaskWoken ) ) + +/** + * message_buffer.h + * + * @code{c} + * size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer, + * void *pvRxData, + * size_t xBufferLengthBytes, + * TickType_t xTicksToWait ); + * @endcode + * + * Receives a discrete message from a message buffer. Messages can be of + * variable length and are copied out of the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferReceive() to read from a message buffer from a task. Use + * xMessageBufferReceiveFromISR() to read from a message buffer from an + * interrupt service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer from which a message + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received message is + * to be copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData + * parameter. This sets the maximum length of the message that can be received. + * If xBufferLengthBytes is too small to hold the next message then the message + * will be left in the message buffer and 0 will be returned. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for a message, should the message buffer be empty. + * xMessageBufferReceive() will return immediately if xTicksToWait is zero and + * the message buffer is empty. The block time is specified in tick periods, so + * the absolute time it represents is dependent on the tick frequency. The + * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds + * into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will + * cause the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any + * CPU time when they are in the Blocked state. + * + * @return The length, in bytes, of the message read from the message buffer, if + * any. If xMessageBufferReceive() times out before a message became available + * then zero is returned. If the length of the message is greater than + * xBufferLengthBytes then the message will be left in the message buffer and + * zero is returned. + * + * Example use: + * @code{c} + * void vAFunction( MessageBuffer_t xMessageBuffer ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 ); + * + * // Receive the next message from the message buffer. Wait in the Blocked + * // state (so not using any CPU processing time) for a maximum of 100ms for + * // a message to become available. + * xReceivedBytes = xMessageBufferReceive( xMessageBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * xBlockTime ); + * + * if( xReceivedBytes > 0 ) + * { + * // A ucRxData contains a message that is xReceivedBytes long. Process + * // the message here.... + * } + * } + * @endcode + * \defgroup xMessageBufferReceive xMessageBufferReceive + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) \ + xStreamBufferReceive( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( xTicksToWait ) ) + + +/** + * message_buffer.h + * + * @code{c} + * size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer, + * void *pvRxData, + * size_t xBufferLengthBytes, + * BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * An interrupt safe version of the API function that receives a discrete + * message from a message buffer. Messages can be of variable length and are + * copied out of the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferReceive() to read from a message buffer from a task. Use + * xMessageBufferReceiveFromISR() to read from a message buffer from an + * interrupt service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer from which a message + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received message is + * to be copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData + * parameter. This sets the maximum length of the message that can be received. + * If xBufferLengthBytes is too small to hold the next message then the message + * will be left in the message buffer and 0 will be returned. + * + * @param pxHigherPriorityTaskWoken It is possible that a message buffer will + * have a task blocked on it waiting for space to become available. Calling + * xMessageBufferReceiveFromISR() can make space available, and so cause a task + * that is waiting for space to leave the Blocked state. If calling + * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and + * the unblocked task has a priority higher than the currently executing task + * (the task that was interrupted), then, internally, + * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE. + * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. That will + * ensure the interrupt returns directly to the highest priority Ready state + * task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is + * passed into the function. See the code example below for an example. + * + * @return The length, in bytes, of the message read from the message buffer, if + * any. + * + * Example use: + * @code{c} + * // A message buffer that has already been created. + * MessageBuffer_t xMessageBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Receive the next message from the message buffer. + * xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * &xHigherPriorityTaskWoken ); + * + * if( xReceivedBytes > 0 ) + * { + * // A ucRxData contains a message that is xReceivedBytes long. Process + * // the message here.... + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xMessageBufferReceiveFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) \ + xStreamBufferReceiveFromISR( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( pxHigherPriorityTaskWoken ) ) + +/** + * message_buffer.h + * + * @code{c} + * void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * + * Deletes a message buffer that was previously created using a call to + * xMessageBufferCreate() or xMessageBufferCreateStatic(). If the message + * buffer was created using dynamic memory (that is, by xMessageBufferCreate()), + * then the allocated memory is freed. + * + * A message buffer handle must not be used after the message buffer has been + * deleted. + * + * @param xMessageBuffer The handle of the message buffer to be deleted. + * + */ +#define vMessageBufferDelete( xMessageBuffer ) \ + vStreamBufferDelete( xMessageBuffer ) + +/** + * message_buffer.h + * @code{c} + * BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * + * Tests to see if a message buffer is full. A message buffer is full if it + * cannot accept any more messages, of any size, until space is made available + * by a message being removed from the message buffer. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return If the message buffer referenced by xMessageBuffer is full then + * pdTRUE is returned. Otherwise pdFALSE is returned. + */ +#define xMessageBufferIsFull( xMessageBuffer ) \ + xStreamBufferIsFull( xMessageBuffer ) + +/** + * message_buffer.h + * @code{c} + * BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * + * Tests to see if a message buffer is empty (does not contain any messages). + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return If the message buffer referenced by xMessageBuffer is empty then + * pdTRUE is returned. Otherwise pdFALSE is returned. + * + */ +#define xMessageBufferIsEmpty( xMessageBuffer ) \ + xStreamBufferIsEmpty( xMessageBuffer ) + +/** + * message_buffer.h + * @code{c} + * BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * + * Resets a message buffer to its initial empty state, discarding any message it + * contained. + * + * A message buffer can only be reset if there are no tasks blocked on it. + * + * @param xMessageBuffer The handle of the message buffer being reset. + * + * @return If the message buffer was reset then pdPASS is returned. If the + * message buffer could not be reset because either there was a task blocked on + * the message queue to wait for space to become available, or to wait for a + * a message to be available, then pdFAIL is returned. + * + * \defgroup xMessageBufferReset xMessageBufferReset + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReset( xMessageBuffer ) \ + xStreamBufferReset( xMessageBuffer ) + + +/** + * message_buffer.h + * @code{c} + * size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * Returns the number of bytes of free space in the message buffer. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return The number of bytes that can be written to the message buffer before + * the message buffer would be full. When a message is written to the message + * buffer an additional sizeof( size_t ) bytes are also written to store the + * message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size + * of the largest message that can be written to the message buffer is 6 bytes. + * + * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSpaceAvailable( xMessageBuffer ) \ + xStreamBufferSpacesAvailable( xMessageBuffer ) +#define xMessageBufferSpacesAvailable( xMessageBuffer ) \ + xStreamBufferSpacesAvailable( xMessageBuffer ) /* Corrects typo in original macro name. */ + +/** + * message_buffer.h + * @code{c} + * size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * Returns the length (in bytes) of the next message in a message buffer. + * Useful if xMessageBufferReceive() returned 0 because the size of the buffer + * passed into xMessageBufferReceive() was too small to hold the next message. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return The length (in bytes) of the next message in the message buffer, or 0 + * if the message buffer is empty. + * + * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes + * \ingroup MessageBufferManagement + */ +#define xMessageBufferNextLengthBytes( xMessageBuffer ) \ + xStreamBufferNextMessageLengthBytes( xMessageBuffer ) PRIVILEGED_FUNCTION; + +/** + * message_buffer.h + * + * @code{c} + * BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * For advanced users only. + * + * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is sent to a message buffer or stream buffer. If there was a task that + * was blocked on the message or stream buffer waiting for data to arrive then + * the sbSEND_COMPLETED() macro sends a notification to the task to remove it + * from the Blocked state. xMessageBufferSendCompletedFromISR() does the same + * thing. It is provided to enable application writers to implement their own + * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xMessageBuffer The handle of the stream buffer to which data was + * written. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xMessageBufferSendCompletedFromISR(). If calling + * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR + * \ingroup StreamBufferManagement + */ +#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \ + xStreamBufferSendCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) ) + +/** + * message_buffer.h + * + * @code{c} + * BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * For advanced users only. + * + * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is read out of a message buffer or stream buffer. If there was a task + * that was blocked on the message or stream buffer waiting for data to arrive + * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to + * remove it from the Blocked state. xMessageBufferReceiveCompletedFromISR() + * does the same thing. It is provided to enable application writers to + * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT + * ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xMessageBuffer The handle of the stream buffer from which data was + * read. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xMessageBufferReceiveCompletedFromISR(). If calling + * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR + * \ingroup StreamBufferManagement + */ +#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \ + xStreamBufferReceiveCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) ) + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + } /* extern "C" */ +#endif +/* *INDENT-ON* */ + +#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/mpu_prototypes.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/mpu_prototypes.h new file mode 100644 index 0000000..8e19ea0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/mpu_prototypes.h @@ -0,0 +1,264 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * When the MPU is used the standard (non MPU) API functions are mapped to + * equivalents that start "MPU_", the prototypes for which are defined in this + * header files. This will cause the application code to call the MPU_ version + * which wraps the non-MPU version with privilege promoting then demoting code, + * so the kernel code always runs will full privileges. + */ + + +#ifndef MPU_PROTOTYPES_H +#define MPU_PROTOTYPES_H + +/* MPU versions of task.h API functions. */ +BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint16_t usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL; +char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL; +TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL; +configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL; +configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of queue.h API functions. */ +BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of timers.h API functions. */ +TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL; +TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of event_group.h API functions. */ +EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL; +EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of message/stream_buffer.h API functions. */ +size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL; + + + +#endif /* MPU_PROTOTYPES_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/mpu_wrappers.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/mpu_wrappers.h new file mode 100644 index 0000000..0a26d88 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/mpu_wrappers.h @@ -0,0 +1,184 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef MPU_WRAPPERS_H +#define MPU_WRAPPERS_H + +/* This file redefines API functions to be called through a wrapper macro, but + * only for ports that are using the MPU. */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is + * included from queue.c or task.c to prevent it from having an effect within + * those files. */ + #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* + * Map standard (non MPU) API functions to equivalents that start + * "MPU_". This will cause the application code to call the MPU_ + * version, which wraps the non-MPU version with privilege promoting + * then demoting code, so the kernel code always runs will full + * privileges. + */ + +/* Map standard task.h API functions to the MPU equivalents. */ + #define xTaskCreate MPU_xTaskCreate + #define xTaskCreateStatic MPU_xTaskCreateStatic + #define vTaskDelete MPU_vTaskDelete + #define vTaskDelay MPU_vTaskDelay + #define xTaskDelayUntil MPU_xTaskDelayUntil + #define xTaskAbortDelay MPU_xTaskAbortDelay + #define uxTaskPriorityGet MPU_uxTaskPriorityGet + #define eTaskGetState MPU_eTaskGetState + #define vTaskGetInfo MPU_vTaskGetInfo + #define vTaskPrioritySet MPU_vTaskPrioritySet + #define vTaskSuspend MPU_vTaskSuspend + #define vTaskResume MPU_vTaskResume + #define vTaskSuspendAll MPU_vTaskSuspendAll + #define xTaskResumeAll MPU_xTaskResumeAll + #define xTaskGetTickCount MPU_xTaskGetTickCount + #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks + #define pcTaskGetName MPU_pcTaskGetName + #define xTaskGetHandle MPU_xTaskGetHandle + #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark + #define uxTaskGetStackHighWaterMark2 MPU_uxTaskGetStackHighWaterMark2 + #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag + #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag + #define vTaskSetThreadLocalStoragePointer MPU_vTaskSetThreadLocalStoragePointer + #define pvTaskGetThreadLocalStoragePointer MPU_pvTaskGetThreadLocalStoragePointer + #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook + #define xTaskGetIdleTaskHandle MPU_xTaskGetIdleTaskHandle + #define uxTaskGetSystemState MPU_uxTaskGetSystemState + #define vTaskList MPU_vTaskList + #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats + #define ulTaskGetIdleRunTimeCounter MPU_ulTaskGetIdleRunTimeCounter + #define ulTaskGetIdleRunTimePercent MPU_ulTaskGetIdleRunTimePercent + #define xTaskGenericNotify MPU_xTaskGenericNotify + #define xTaskGenericNotifyWait MPU_xTaskGenericNotifyWait + #define ulTaskGenericNotifyTake MPU_ulTaskGenericNotifyTake + #define xTaskGenericNotifyStateClear MPU_xTaskGenericNotifyStateClear + #define ulTaskGenericNotifyValueClear MPU_ulTaskGenericNotifyValueClear + #define xTaskCatchUpTicks MPU_xTaskCatchUpTicks + + #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle + #define vTaskSetTimeOutState MPU_vTaskSetTimeOutState + #define xTaskCheckForTimeOut MPU_xTaskCheckForTimeOut + #define xTaskGetSchedulerState MPU_xTaskGetSchedulerState + +/* Map standard queue.h API functions to the MPU equivalents. */ + #define xQueueGenericSend MPU_xQueueGenericSend + #define xQueueReceive MPU_xQueueReceive + #define xQueuePeek MPU_xQueuePeek + #define xQueueSemaphoreTake MPU_xQueueSemaphoreTake + #define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting + #define uxQueueSpacesAvailable MPU_uxQueueSpacesAvailable + #define vQueueDelete MPU_vQueueDelete + #define xQueueCreateMutex MPU_xQueueCreateMutex + #define xQueueCreateMutexStatic MPU_xQueueCreateMutexStatic + #define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore + #define xQueueCreateCountingSemaphoreStatic MPU_xQueueCreateCountingSemaphoreStatic + #define xQueueGetMutexHolder MPU_xQueueGetMutexHolder + #define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive + #define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive + #define xQueueGenericCreate MPU_xQueueGenericCreate + #define xQueueGenericCreateStatic MPU_xQueueGenericCreateStatic + #define xQueueCreateSet MPU_xQueueCreateSet + #define xQueueAddToSet MPU_xQueueAddToSet + #define xQueueRemoveFromSet MPU_xQueueRemoveFromSet + #define xQueueSelectFromSet MPU_xQueueSelectFromSet + #define xQueueGenericReset MPU_xQueueGenericReset + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + #define vQueueAddToRegistry MPU_vQueueAddToRegistry + #define vQueueUnregisterQueue MPU_vQueueUnregisterQueue + #define pcQueueGetName MPU_pcQueueGetName + #endif + +/* Map standard timer.h API functions to the MPU equivalents. */ + #define pvTimerGetTimerID MPU_pvTimerGetTimerID + #define vTimerSetTimerID MPU_vTimerSetTimerID + #define xTimerIsTimerActive MPU_xTimerIsTimerActive + #define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle + #define pcTimerGetName MPU_pcTimerGetName + #define vTimerSetReloadMode MPU_vTimerSetReloadMode + #define uxTimerGetReloadMode MPU_uxTimerGetReloadMode + #define xTimerGetPeriod MPU_xTimerGetPeriod + #define xTimerGetExpiryTime MPU_xTimerGetExpiryTime + #define xTimerGenericCommand MPU_xTimerGenericCommand + +/* Map standard event_group.h API functions to the MPU equivalents. */ + #define xEventGroupCreate MPU_xEventGroupCreate + #define xEventGroupCreateStatic MPU_xEventGroupCreateStatic + #define xEventGroupWaitBits MPU_xEventGroupWaitBits + #define xEventGroupClearBits MPU_xEventGroupClearBits + #define xEventGroupSetBits MPU_xEventGroupSetBits + #define xEventGroupSync MPU_xEventGroupSync + #define vEventGroupDelete MPU_vEventGroupDelete + +/* Map standard message/stream_buffer.h API functions to the MPU + * equivalents. */ + #define xStreamBufferSend MPU_xStreamBufferSend + #define xStreamBufferReceive MPU_xStreamBufferReceive + #define xStreamBufferNextMessageLengthBytes MPU_xStreamBufferNextMessageLengthBytes + #define vStreamBufferDelete MPU_vStreamBufferDelete + #define xStreamBufferIsFull MPU_xStreamBufferIsFull + #define xStreamBufferIsEmpty MPU_xStreamBufferIsEmpty + #define xStreamBufferReset MPU_xStreamBufferReset + #define xStreamBufferSpacesAvailable MPU_xStreamBufferSpacesAvailable + #define xStreamBufferBytesAvailable MPU_xStreamBufferBytesAvailable + #define xStreamBufferSetTriggerLevel MPU_xStreamBufferSetTriggerLevel + #define xStreamBufferGenericCreate MPU_xStreamBufferGenericCreate + #define xStreamBufferGenericCreateStatic MPU_xStreamBufferGenericCreateStatic + + +/* Remove the privileged function macro, but keep the PRIVILEGED_DATA + * macro so applications can place data in privileged access sections + * (useful when using statically allocated objects). */ + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) ) + #define FREERTOS_SYSTEM_CALL + + #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + +/* Ensure API functions go in the privileged execution section. */ + #define PRIVILEGED_FUNCTION __attribute__( ( section( "privileged_functions" ) ) ) + #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) ) + #define FREERTOS_SYSTEM_CALL __attribute__( ( section( "freertos_system_calls" ) ) ) + + #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + +#else /* portUSING_MPU_WRAPPERS */ + + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA + #define FREERTOS_SYSTEM_CALL + +#endif /* portUSING_MPU_WRAPPERS */ + + +#endif /* MPU_WRAPPERS_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/portable.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/portable.h new file mode 100644 index 0000000..a69e637 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/portable.h @@ -0,0 +1,238 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Portable layer API. Each function must be defined for each port. +*----------------------------------------------------------*/ + +#ifndef PORTABLE_H +#define PORTABLE_H + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a + * pre-processor definition was used to ensure the pre-processor found the correct + * portmacro.h file for the port being used. That scheme was deprecated in favour + * of setting the compiler's include path such that it found the correct + * portmacro.h file - removing the need for the constant and allowing the + * portmacro.h file to be located anywhere in relation to the port being used. + * Purely for reasons of backward compatibility the old method is still valid, but + * to make it clear that new projects should not use it, support for the port + * specific constants has been moved into the deprecated_definitions.h header + * file. */ +#include "deprecated_definitions.h" + +/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h + * did not result in a portmacro.h header file being included - and it should be + * included here. In this case the path to the correct portmacro.h header file + * must be set in the compiler's include path. */ +#ifndef portENTER_CRITICAL + #include "portmacro.h" +#endif + +#if portBYTE_ALIGNMENT == 32 + #define portBYTE_ALIGNMENT_MASK ( 0x001f ) +#elif portBYTE_ALIGNMENT == 16 + #define portBYTE_ALIGNMENT_MASK ( 0x000f ) +#elif portBYTE_ALIGNMENT == 8 + #define portBYTE_ALIGNMENT_MASK ( 0x0007 ) +#elif portBYTE_ALIGNMENT == 4 + #define portBYTE_ALIGNMENT_MASK ( 0x0003 ) +#elif portBYTE_ALIGNMENT == 2 + #define portBYTE_ALIGNMENT_MASK ( 0x0001 ) +#elif portBYTE_ALIGNMENT == 1 + #define portBYTE_ALIGNMENT_MASK ( 0x0000 ) +#else /* if portBYTE_ALIGNMENT == 32 */ + #error "Invalid portBYTE_ALIGNMENT definition" +#endif /* if portBYTE_ALIGNMENT == 32 */ + +#ifndef portUSING_MPU_WRAPPERS + #define portUSING_MPU_WRAPPERS 0 +#endif + +#ifndef portNUM_CONFIGURABLE_REGIONS + #define portNUM_CONFIGURABLE_REGIONS 1 +#endif + +#ifndef portHAS_STACK_OVERFLOW_CHECKING + #define portHAS_STACK_OVERFLOW_CHECKING 0 +#endif + +#ifndef portARCH_NAME + #define portARCH_NAME NULL +#endif + +#ifndef configSTACK_ALLOCATION_FROM_SEPARATE_HEAP + /* Defaults to 0 for backward compatibility. */ + #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include "mpu_wrappers.h" + +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in + * the order that the port expects to find them. + * + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #endif +#else /* if ( portUSING_MPU_WRAPPERS == 1 ) */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) PRIVILEGED_FUNCTION; + #else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) PRIVILEGED_FUNCTION; + #endif +#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */ + +/* Used by heap_5.c to define the start address and size of each memory region + * that together comprise the total FreeRTOS heap space. */ +typedef struct HeapRegion +{ + uint8_t * pucStartAddress; + size_t xSizeInBytes; +} HeapRegion_t; + +/* Used to pass information about the heap out of vPortGetHeapStats(). */ +typedef struct xHeapStats +{ + size_t xAvailableHeapSpaceInBytes; /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */ + size_t xSizeOfLargestFreeBlockInBytes; /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xNumberOfFreeBlocks; /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xMinimumEverFreeBytesRemaining; /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */ + size_t xNumberOfSuccessfulAllocations; /* The number of calls to pvPortMalloc() that have returned a valid memory block. */ + size_t xNumberOfSuccessfulFrees; /* The number of calls to vPortFree() that has successfully freed a block of memory. */ +} HeapStats_t; + +/* + * Used to define multiple heap regions for use by heap_5.c. This function + * must be called before any calls to pvPortMalloc() - not creating a task, + * queue, semaphore, mutex, software timer, event group, etc. will result in + * pvPortMalloc being called. + * + * pxHeapRegions passes in an array of HeapRegion_t structures - each of which + * defines a region of memory that can be used as the heap. The array is + * terminated by a HeapRegions_t structure that has a size of 0. The region + * with the lowest start address must appear first in the array. + */ +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION; + +/* + * Returns a HeapStats_t structure filled with information about the current + * heap state. + */ +void vPortGetHeapStats( HeapStats_t * pxHeapStats ); + +/* + * Map to the memory management routines required for the port. + */ +void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION; +void * pvPortCalloc( size_t xNum, + size_t xSize ) PRIVILEGED_FUNCTION; +void vPortFree( void * pv ) PRIVILEGED_FUNCTION; +void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION; +size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION; +size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION; + +#if ( configSTACK_ALLOCATION_FROM_SEPARATE_HEAP == 1 ) + void * pvPortMallocStack( size_t xSize ) PRIVILEGED_FUNCTION; + void vPortFreeStack( void * pv ) PRIVILEGED_FUNCTION; +#else + #define pvPortMallocStack pvPortMalloc + #define vPortFreeStack vPortFree +#endif + +#if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + +/** + * task.h + * @code{c} + * void vApplicationMallocFailedHook( void ) + * @endcode + * + * This hook function is called when allocation failed. + */ + void vApplicationMallocFailedHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */ +#endif + +/* + * Setup the hardware ready for the scheduler to take control. This generally + * sets up a tick interrupt and sets timers for the correct tick frequency. + */ +BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so + * the hardware is left in its original condition after the scheduler stops + * executing. + */ +void vPortEndScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * The structures and methods of manipulating the MPU are contained within the + * port layer. + * + * Fills the xMPUSettings structure with the memory region information + * contained in xRegions. + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + struct xMEMORY_REGION; + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTABLE_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/projdefs.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/projdefs.h new file mode 100644 index 0000000..595cbed --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/projdefs.h @@ -0,0 +1,122 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PROJDEFS_H +#define PROJDEFS_H + +/* + * Defines the prototype to which task functions must conform. Defined in this + * file to ensure the type is known before portable.h is included. + */ +typedef void (* TaskFunction_t)( void * ); + +/* Converts a time in milliseconds to a time in ticks. This macro can be + * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the + * definition here is not suitable for your application. */ +#ifndef pdMS_TO_TICKS + #define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) ) +#endif + +#define pdFALSE ( ( BaseType_t ) 0 ) +#define pdTRUE ( ( BaseType_t ) 1 ) + +#define pdPASS ( pdTRUE ) +#define pdFAIL ( pdFALSE ) +#define errQUEUE_EMPTY ( ( BaseType_t ) 0 ) +#define errQUEUE_FULL ( ( BaseType_t ) 0 ) + +/* FreeRTOS error definitions. */ +#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) +#define errQUEUE_BLOCKED ( -4 ) +#define errQUEUE_YIELD ( -5 ) + +/* Macros used for basic data corruption checks. */ +#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES + #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0 +#endif + +#if ( configUSE_16_BIT_TICKS == 1 ) + #define pdINTEGRITY_CHECK_VALUE 0x5a5a +#else + #define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL +#endif + +/* The following errno values are used by FreeRTOS+ components, not FreeRTOS + * itself. */ +#define pdFREERTOS_ERRNO_NONE 0 /* No errors */ +#define pdFREERTOS_ERRNO_ENOENT 2 /* No such file or directory */ +#define pdFREERTOS_ERRNO_EINTR 4 /* Interrupted system call */ +#define pdFREERTOS_ERRNO_EIO 5 /* I/O error */ +#define pdFREERTOS_ERRNO_ENXIO 6 /* No such device or address */ +#define pdFREERTOS_ERRNO_EBADF 9 /* Bad file number */ +#define pdFREERTOS_ERRNO_EAGAIN 11 /* No more processes */ +#define pdFREERTOS_ERRNO_EWOULDBLOCK 11 /* Operation would block */ +#define pdFREERTOS_ERRNO_ENOMEM 12 /* Not enough memory */ +#define pdFREERTOS_ERRNO_EACCES 13 /* Permission denied */ +#define pdFREERTOS_ERRNO_EFAULT 14 /* Bad address */ +#define pdFREERTOS_ERRNO_EBUSY 16 /* Mount device busy */ +#define pdFREERTOS_ERRNO_EEXIST 17 /* File exists */ +#define pdFREERTOS_ERRNO_EXDEV 18 /* Cross-device link */ +#define pdFREERTOS_ERRNO_ENODEV 19 /* No such device */ +#define pdFREERTOS_ERRNO_ENOTDIR 20 /* Not a directory */ +#define pdFREERTOS_ERRNO_EISDIR 21 /* Is a directory */ +#define pdFREERTOS_ERRNO_EINVAL 22 /* Invalid argument */ +#define pdFREERTOS_ERRNO_ENOSPC 28 /* No space left on device */ +#define pdFREERTOS_ERRNO_ESPIPE 29 /* Illegal seek */ +#define pdFREERTOS_ERRNO_EROFS 30 /* Read only file system */ +#define pdFREERTOS_ERRNO_EUNATCH 42 /* Protocol driver not attached */ +#define pdFREERTOS_ERRNO_EBADE 50 /* Invalid exchange */ +#define pdFREERTOS_ERRNO_EFTYPE 79 /* Inappropriate file type or format */ +#define pdFREERTOS_ERRNO_ENMFILE 89 /* No more files */ +#define pdFREERTOS_ERRNO_ENOTEMPTY 90 /* Directory not empty */ +#define pdFREERTOS_ERRNO_ENAMETOOLONG 91 /* File or path name too long */ +#define pdFREERTOS_ERRNO_EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define pdFREERTOS_ERRNO_ENOBUFS 105 /* No buffer space available */ +#define pdFREERTOS_ERRNO_ENOPROTOOPT 109 /* Protocol not available */ +#define pdFREERTOS_ERRNO_EADDRINUSE 112 /* Address already in use */ +#define pdFREERTOS_ERRNO_ETIMEDOUT 116 /* Connection timed out */ +#define pdFREERTOS_ERRNO_EINPROGRESS 119 /* Connection already in progress */ +#define pdFREERTOS_ERRNO_EALREADY 120 /* Socket already connected */ +#define pdFREERTOS_ERRNO_EADDRNOTAVAIL 125 /* Address not available */ +#define pdFREERTOS_ERRNO_EISCONN 127 /* Socket is already connected */ +#define pdFREERTOS_ERRNO_ENOTCONN 128 /* Socket is not connected */ +#define pdFREERTOS_ERRNO_ENOMEDIUM 135 /* No medium inserted */ +#define pdFREERTOS_ERRNO_EILSEQ 138 /* An invalid UTF-16 sequence was encountered. */ +#define pdFREERTOS_ERRNO_ECANCELED 140 /* Operation canceled. */ + +/* The following endian values are used by FreeRTOS+ components, not FreeRTOS + * itself. */ +#define pdFREERTOS_LITTLE_ENDIAN 0 +#define pdFREERTOS_BIG_ENDIAN 1 + +/* Re-defining endian values for generic naming. */ +#define pdLITTLE_ENDIAN pdFREERTOS_LITTLE_ENDIAN +#define pdBIG_ENDIAN pdFREERTOS_BIG_ENDIAN + + +#endif /* PROJDEFS_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/queue.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/queue.h new file mode 100644 index 0000000..df572e1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/queue.h @@ -0,0 +1,1722 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef QUEUE_H +#define QUEUE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include queue.h" +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include "task.h" + +/** + * Type by which queues are referenced. For example, a call to xQueueCreate() + * returns an QueueHandle_t variable that can then be used as a parameter to + * xQueueSend(), xQueueReceive(), etc. + */ +struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */ +typedef struct QueueDefinition * QueueHandle_t; + +/** + * Type by which queue sets are referenced. For example, a call to + * xQueueCreateSet() returns an xQueueSet variable that can then be used as a + * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc. + */ +typedef struct QueueDefinition * QueueSetHandle_t; + +/** + * Queue sets can contain both queues and semaphores, so the + * QueueSetMemberHandle_t is defined as a type to be used where a parameter or + * return value can be either an QueueHandle_t or an SemaphoreHandle_t. + */ +typedef struct QueueDefinition * QueueSetMemberHandle_t; + +/* For internal use only. */ +#define queueSEND_TO_BACK ( ( BaseType_t ) 0 ) +#define queueSEND_TO_FRONT ( ( BaseType_t ) 1 ) +#define queueOVERWRITE ( ( BaseType_t ) 2 ) + +/* For internal use only. These definitions *must* match those in queue.c. */ +#define queueQUEUE_TYPE_BASE ( ( uint8_t ) 0U ) +#define queueQUEUE_TYPE_SET ( ( uint8_t ) 0U ) +#define queueQUEUE_TYPE_MUTEX ( ( uint8_t ) 1U ) +#define queueQUEUE_TYPE_COUNTING_SEMAPHORE ( ( uint8_t ) 2U ) +#define queueQUEUE_TYPE_BINARY_SEMAPHORE ( ( uint8_t ) 3U ) +#define queueQUEUE_TYPE_RECURSIVE_MUTEX ( ( uint8_t ) 4U ) + +/** + * queue. h + * @code{c} + * QueueHandle_t xQueueCreate( + * UBaseType_t uxQueueLength, + * UBaseType_t uxItemSize + * ); + * @endcode + * + * Creates a new queue instance, and returns a handle by which the new queue + * can be referenced. + * + * Internally, within the FreeRTOS implementation, queues use two blocks of + * memory. The first block is used to hold the queue's data structures. The + * second block is used to hold items placed into the queue. If a queue is + * created using xQueueCreate() then both blocks of memory are automatically + * dynamically allocated inside the xQueueCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a queue is created using + * xQueueCreateStatic() then the application writer must provide the memory that + * will get used by the queue. xQueueCreateStatic() therefore allows a queue to + * be created without using any dynamic memory allocation. + * + * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @return If the queue is successfully create then a handle to the newly + * created queue is returned. If the queue cannot be created then 0 is + * returned. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * }; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * if( xQueue1 == 0 ) + * { + * // Queue was not created and must not be used. + * } + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * if( xQueue2 == 0 ) + * { + * // Queue was not created and must not be used. + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueCreate xQueueCreate + * \ingroup QueueManagement + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) ) +#endif + +/** + * queue. h + * @code{c} + * QueueHandle_t xQueueCreateStatic( + * UBaseType_t uxQueueLength, + * UBaseType_t uxItemSize, + * uint8_t *pucQueueStorage, + * StaticQueue_t *pxQueueBuffer + * ); + * @endcode + * + * Creates a new queue instance, and returns a handle by which the new queue + * can be referenced. + * + * Internally, within the FreeRTOS implementation, queues use two blocks of + * memory. The first block is used to hold the queue's data structures. The + * second block is used to hold items placed into the queue. If a queue is + * created using xQueueCreate() then both blocks of memory are automatically + * dynamically allocated inside the xQueueCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a queue is created using + * xQueueCreateStatic() then the application writer must provide the memory that + * will get used by the queue. xQueueCreateStatic() therefore allows a queue to + * be created without using any dynamic memory allocation. + * + * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @param pucQueueStorage If uxItemSize is not zero then + * pucQueueStorage must point to a uint8_t array that is at least large + * enough to hold the maximum number of items that can be in the queue at any + * one time - which is ( uxQueueLength * uxItemsSize ) bytes. If uxItemSize is + * zero then pucQueueStorage can be NULL. + * + * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which + * will be used to hold the queue's data structure. + * + * @return If the queue is created then a handle to the created queue is + * returned. If pxQueueBuffer is NULL then NULL is returned. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * }; + * + #define QUEUE_LENGTH 10 + #define ITEM_SIZE sizeof( uint32_t ) + * + * // xQueueBuffer will hold the queue structure. + * StaticQueue_t xQueueBuffer; + * + * // ucQueueStorage will hold the items posted to the queue. Must be at least + * // [(queue length) * ( queue item size)] bytes long. + * uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ]; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold. + * ITEM_SIZE // The size of each item in the queue + * &( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue. + * &xQueueBuffer ); // The buffer that will hold the queue structure. + * + * // The queue is guaranteed to be created successfully as no dynamic memory + * // allocation is used. Therefore xQueue1 is now a handle to a valid queue. + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueCreateStatic xQueueCreateStatic + * \ingroup QueueManagement + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendToToFront( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * TickType_t xTicksToWait + * ); + * @endcode + * + * Post an item to the front of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * uint32_t ulVar = 10UL; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * + * // ... + * + * if( xQueue1 != 0 ) + * { + * // Send an uint32_t. Wait for 10 ticks for space to become + * // available if necessary. + * if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS ) + * { + * // Failed to post the message, even after 10 ticks. + * } + * } + * + * if( xQueue2 != 0 ) + * { + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendToBack( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * TickType_t xTicksToWait + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSend(). + * + * Post an item to the back of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the queue + * is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * uint32_t ulVar = 10UL; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * + * // ... + * + * if( xQueue1 != 0 ) + * { + * // Send an uint32_t. Wait for 10 ticks for space to become + * // available if necessary. + * if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS ) + * { + * // Failed to post the message, even after 10 ticks. + * } + * } + * + * if( xQueue2 != 0 ) + * { + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSend( + * QueueHandle_t xQueue, + * const void * pvItemToQueue, + * TickType_t xTicksToWait + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSend(). It is included for + * backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToFront() and xQueueSendToBack() macros. It is + * equivalent to xQueueSendToBack(). + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * uint32_t ulVar = 10UL; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * + * // ... + * + * if( xQueue1 != 0 ) + * { + * // Send an uint32_t. Wait for 10 ticks for space to become + * // available if necessary. + * if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS ) + * { + * // Failed to post the message, even after 10 ticks. + * } + * } + * + * if( xQueue2 != 0 ) + * { + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueOverwrite( + * QueueHandle_t xQueue, + * const void * pvItemToQueue + * ); + * @endcode + * + * Only for use with queues that have a length of one - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * This function must not be called from an interrupt service routine. + * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle of the queue to which the data is being sent. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and + * therefore has the same return values as xQueueSendToFront(). However, pdPASS + * is the only value that can be returned because xQueueOverwrite() will write + * to the queue even when the queue is already full. + * + * Example usage: + * @code{c} + * + * void vFunction( void *pvParameters ) + * { + * QueueHandle_t xQueue; + * uint32_t ulVarToSend, ulValReceived; + * + * // Create a queue to hold one uint32_t value. It is strongly + * // recommended *not* to use xQueueOverwrite() on queues that can + * // contain more than one value, and doing so will trigger an assertion + * // if configASSERT() is defined. + * xQueue = xQueueCreate( 1, sizeof( uint32_t ) ); + * + * // Write the value 10 to the queue using xQueueOverwrite(). + * ulVarToSend = 10; + * xQueueOverwrite( xQueue, &ulVarToSend ); + * + * // Peeking the queue should now return 10, but leave the value 10 in + * // the queue. A block time of zero is used as it is known that the + * // queue holds a value. + * ulValReceived = 0; + * xQueuePeek( xQueue, &ulValReceived, 0 ); + * + * if( ulValReceived != 10 ) + * { + * // Error unless the item was removed by a different task. + * } + * + * // The queue is still full. Use xQueueOverwrite() to overwrite the + * // value held in the queue with 100. + * ulVarToSend = 100; + * xQueueOverwrite( xQueue, &ulVarToSend ); + * + * // This time read from the queue, leaving the queue empty once more. + * // A block time of 0 is used again. + * xQueueReceive( xQueue, &ulValReceived, 0 ); + * + * // The value read should be the last value written, even though the + * // queue was already full when the value was written. + * if( ulValReceived != 100 ) + * { + * // Error! + * } + * + * // ... + * } + * @endcode + * \defgroup xQueueOverwrite xQueueOverwrite + * \ingroup QueueManagement + */ +#define xQueueOverwrite( xQueue, pvItemToQueue ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE ) + + +/** + * queue. h + * @code{c} + * BaseType_t xQueueGenericSend( + * QueueHandle_t xQueue, + * const void * pvItemToQueue, + * TickType_t xTicksToWait + * BaseType_t xCopyPosition + * ); + * @endcode + * + * It is preferred that the macros xQueueSend(), xQueueSendToFront() and + * xQueueSendToBack() are used in place of calling this function directly. + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * uint32_t ulVar = 10UL; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * + * // ... + * + * if( xQueue1 != 0 ) + * { + * // Send an uint32_t. Wait for 10 ticks for space to become + * // available if necessary. + * if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS ) + * { + * // Failed to post the message, even after 10 ticks. + * } + * } + * + * if( xQueue2 != 0 ) + * { + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK ); + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueuePeek( + * QueueHandle_t xQueue, + * void * const pvBuffer, + * TickType_t xTicksToWait + * ); + * @endcode + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * This macro must not be used in an interrupt service routine. See + * xQueuePeekFromISR() for an alternative that can be called from an interrupt + * service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue + * is empty. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * QueueHandle_t xQueue; + * + * // Task to create a queue and post a value. + * void vATask( void *pvParameters ) + * { + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * if( xQueue == 0 ) + * { + * // Failed to create the queue. + * } + * + * // ... + * + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * + * // ... Rest of task code. + * } + * + * // Task to peek the data from the queue. + * void vADifferentTask( void *pvParameters ) + * { + * struct AMessage *pxRxedMessage; + * + * if( xQueue != 0 ) + * { + * // Peek a message on the created queue. Block for 10 ticks if a + * // message is not immediately available. + * if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) ) + * { + * // pcRxedMessage now points to the struct AMessage variable posted + * // by vATask, but the item still remains on the queue. + * } + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueuePeek xQueuePeek + * \ingroup QueueManagement + */ +BaseType_t xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueuePeekFromISR( + * QueueHandle_t xQueue, + * void *pvBuffer, + * ); + * @endcode + * + * A version of xQueuePeek() that can be called from an interrupt service + * routine (ISR). + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * \defgroup xQueuePeekFromISR xQueuePeekFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, + void * const pvBuffer ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueueReceive( + * QueueHandle_t xQueue, + * void *pvBuffer, + * TickType_t xTicksToWait + * ); + * @endcode + * + * Receive an item from a queue. The item is received by copy so a buffer of + * adequate size must be provided. The number of bytes copied into the buffer + * was defined when the queue was created. + * + * Successfully received items are removed from the queue. + * + * This function must not be used in an interrupt service routine. See + * xQueueReceiveFromISR for an alternative that can. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. xQueueReceive() will return immediately if xTicksToWait + * is zero and the queue is empty. The time is defined in tick periods so the + * constant portTICK_PERIOD_MS should be used to convert to real time if this is + * required. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * QueueHandle_t xQueue; + * + * // Task to create a queue and post a value. + * void vATask( void *pvParameters ) + * { + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * if( xQueue == 0 ) + * { + * // Failed to create the queue. + * } + * + * // ... + * + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * + * // ... Rest of task code. + * } + * + * // Task to receive from the queue. + * void vADifferentTask( void *pvParameters ) + * { + * struct AMessage *pxRxedMessage; + * + * if( xQueue != 0 ) + * { + * // Receive a message on the created queue. Block for 10 ticks if a + * // message is not immediately available. + * if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) ) + * { + * // pcRxedMessage now points to the struct AMessage variable posted + * // by vATask. + * } + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueReceive xQueueReceive + * \ingroup QueueManagement + */ +BaseType_t xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ); + * @endcode + * + * Return the number of messages stored in a queue. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of messages available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ); + * @endcode + * + * Return the number of free spaces available in a queue. This is equal to the + * number of items that can be sent to the queue before the queue becomes full + * if no items are removed. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of spaces available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * void vQueueDelete( QueueHandle_t xQueue ); + * @endcode + * + * Delete a queue - freeing all the memory allocated for storing of items + * placed on the queue. + * + * @param xQueue A handle to the queue to be deleted. + * + * \defgroup vQueueDelete vQueueDelete + * \ingroup QueueManagement + */ +void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendToFrontFromISR( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the front of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * @code{c} + * void vBufferISR( void ) + * { + * char cIn; + * BaseType_t xHigherPriorityTaskWoken; + * + * // We have not woken a task at the start of the ISR. + * xHigherPriorityTaskWoken = pdFALSE; + * + * // Loop until the buffer is empty. + * do + * { + * // Obtain a byte from the buffer. + * cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); + * + * // Post the byte. + * xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken ); + * + * } while( portINPUT_BYTE( BUFFER_COUNT ) ); + * + * // Now the buffer is empty we can switch context if necessary. + * if( xHigherPriorityTaskWoken ) + * { + * taskYIELD (); + * } + * } + * @endcode + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT ) + + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendToBackFromISR( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the back of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * @code{c} + * void vBufferISR( void ) + * { + * char cIn; + * BaseType_t xHigherPriorityTaskWoken; + * + * // We have not woken a task at the start of the ISR. + * xHigherPriorityTaskWoken = pdFALSE; + * + * // Loop until the buffer is empty. + * do + * { + * // Obtain a byte from the buffer. + * cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); + * + * // Post the byte. + * xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken ); + * + * } while( portINPUT_BYTE( BUFFER_COUNT ) ); + * + * // Now the buffer is empty we can switch context if necessary. + * if( xHigherPriorityTaskWoken ) + * { + * taskYIELD (); + * } + * } + * @endcode + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueOverwriteFromISR( + * QueueHandle_t xQueue, + * const void * pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * A version of xQueueOverwrite() that can be used in an interrupt service + * routine (ISR). + * + * Only for use with queues that can hold a single item - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueOverwriteFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return xQueueOverwriteFromISR() is a macro that calls + * xQueueGenericSendFromISR(), and therefore has the same return values as + * xQueueSendToFrontFromISR(). However, pdPASS is the only value that can be + * returned because xQueueOverwriteFromISR() will write to the queue even when + * the queue is already full. + * + * Example usage: + * @code{c} + * + * QueueHandle_t xQueue; + * + * void vFunction( void *pvParameters ) + * { + * // Create a queue to hold one uint32_t value. It is strongly + * // recommended *not* to use xQueueOverwriteFromISR() on queues that can + * // contain more than one value, and doing so will trigger an assertion + * // if configASSERT() is defined. + * xQueue = xQueueCreate( 1, sizeof( uint32_t ) ); + * } + * + * void vAnInterruptHandler( void ) + * { + * // xHigherPriorityTaskWoken must be set to pdFALSE before it is used. + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * uint32_t ulVarToSend, ulValReceived; + * + * // Write the value 10 to the queue using xQueueOverwriteFromISR(). + * ulVarToSend = 10; + * xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken ); + * + * // The queue is full, but calling xQueueOverwriteFromISR() again will still + * // pass because the value held in the queue will be overwritten with the + * // new value. + * ulVarToSend = 100; + * xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken ); + * + * // Reading from the queue will now return 100. + * + * // ... + * + * if( xHigherPrioritytaskWoken == pdTRUE ) + * { + * // Writing to the queue caused a task to unblock and the unblocked task + * // has a priority higher than or equal to the priority of the currently + * // executing task (the task this interrupt interrupted). Perform a context + * // switch so this interrupt returns directly to the unblocked task. + * portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port. + * } + * } + * @endcode + * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR + * \ingroup QueueManagement + */ +#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendFromISR( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSendFromISR(). It is included + * for backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR() + * macros. + * + * Post an item to the back of a queue. It is safe to use this function from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * @code{c} + * void vBufferISR( void ) + * { + * char cIn; + * BaseType_t xHigherPriorityTaskWoken; + * + * // We have not woken a task at the start of the ISR. + * xHigherPriorityTaskWoken = pdFALSE; + * + * // Loop until the buffer is empty. + * do + * { + * // Obtain a byte from the buffer. + * cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); + * + * // Post the byte. + * xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken ); + * + * } while( portINPUT_BYTE( BUFFER_COUNT ) ); + * + * // Now the buffer is empty we can switch context if necessary. + * if( xHigherPriorityTaskWoken ) + * { + * // Actual macro used here is port specific. + * portYIELD_FROM_ISR (); + * } + * } + * @endcode + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueGenericSendFromISR( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken, + * BaseType_t xCopyPosition + * ); + * @endcode + * + * It is preferred that the macros xQueueSendFromISR(), + * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place + * of calling this function directly. xQueueGiveFromISR() is an + * equivalent for use by semaphores that don't actually copy any data. + * + * Post an item on a queue. It is safe to use this function from within an + * interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * @code{c} + * void vBufferISR( void ) + * { + * char cIn; + * BaseType_t xHigherPriorityTaskWokenByPost; + * + * // We have not woken a task at the start of the ISR. + * xHigherPriorityTaskWokenByPost = pdFALSE; + * + * // Loop until the buffer is empty. + * do + * { + * // Obtain a byte from the buffer. + * cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); + * + * // Post each byte. + * xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK ); + * + * } while( portINPUT_BYTE( BUFFER_COUNT ) ); + * + * // Now the buffer is empty we can switch context if necessary. Note that the + * // name of the yield function required is port specific. + * if( xHigherPriorityTaskWokenByPost ) + * { + * portYIELD_FROM_ISR(); + * } + * } + * @endcode + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, + const void * const pvItemToQueue, + BaseType_t * const pxHigherPriorityTaskWoken, + const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueueReceiveFromISR( + * QueueHandle_t xQueue, + * void *pvBuffer, + * BaseType_t *pxTaskWoken + * ); + * @endcode + * + * Receive an item from a queue. It is safe to use this function from within an + * interrupt service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param pxTaskWoken A task may be blocked waiting for space to become + * available on the queue. If xQueueReceiveFromISR causes such a task to + * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will + * remain unchanged. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * @code{c} + * + * QueueHandle_t xQueue; + * + * // Function to create a queue and post some values. + * void vAFunction( void *pvParameters ) + * { + * char cValueToPost; + * const TickType_t xTicksToWait = ( TickType_t )0xff; + * + * // Create a queue capable of containing 10 characters. + * xQueue = xQueueCreate( 10, sizeof( char ) ); + * if( xQueue == 0 ) + * { + * // Failed to create the queue. + * } + * + * // ... + * + * // Post some characters that will be used within an ISR. If the queue + * // is full then this task will block for xTicksToWait ticks. + * cValueToPost = 'a'; + * xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait ); + * cValueToPost = 'b'; + * xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait ); + * + * // ... keep posting characters ... this task may block when the queue + * // becomes full. + * + * cValueToPost = 'c'; + * xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait ); + * } + * + * // ISR that outputs all the characters received on the queue. + * void vISR_Routine( void ) + * { + * BaseType_t xTaskWokenByReceive = pdFALSE; + * char cRxedChar; + * + * while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) ) + * { + * // A character was received. Output the character now. + * vOutputCharacter( cRxedChar ); + * + * // If removing the character from the queue woke the task that was + * // posting onto the queue xTaskWokenByReceive will have been set to + * // pdTRUE. No matter how many times this loop iterates only one + * // task will be woken. + * } + * + * if( xTaskWokenByReceive != ( char ) pdFALSE; + * { + * taskYIELD (); + * } + * } + * @endcode + * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, + void * const pvBuffer, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/* + * Utilities to query queues that are safe to use from an ISR. These utilities + * should be used only from within an ISR, or within a critical section. + */ +BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/* + * The functions defined above are for passing data to and from tasks. The + * functions below are the equivalents for passing data to and from + * co-routines. + * + * These functions are called from the co-routine macro implementation and + * should not be called directly from application code. Instead use the macro + * wrappers defined within croutine.h. + */ +BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, + const void * pvItemToQueue, + BaseType_t xCoRoutinePreviouslyWoken ); +BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, + void * pvBuffer, + BaseType_t * pxTaskWoken ); +BaseType_t xQueueCRSend( QueueHandle_t xQueue, + const void * pvItemToQueue, + TickType_t xTicksToWait ); +BaseType_t xQueueCRReceive( QueueHandle_t xQueue, + void * pvBuffer, + TickType_t xTicksToWait ); + +/* + * For internal use only. Use xSemaphoreCreateMutex(), + * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling + * these functions directly. + */ +QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; +BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Use xSemaphoreTakeMutexRecursive() or + * xSemaphoreGiveMutexRecursive() instead of calling these functions directly. + */ +BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION; + +/* + * Reset a queue back to its original empty state. The return value is now + * obsolete and is always set to pdPASS. + */ +#define xQueueReset( xQueue ) xQueueGenericReset( ( xQueue ), pdFALSE ) + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger. If you are not using a kernel + * aware debugger then this function can be ignored. + * + * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the + * registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0 + * within FreeRTOSConfig.h for the registry to be available. Its value + * does not affect the number of queues, semaphores and mutexes that can be + * created - just the number that the registry can hold. + * + * If vQueueAddToRegistry is called more than once with the same xQueue + * parameter, the registry will store the pcQueueName parameter from the + * most recent call to vQueueAddToRegistry. + * + * @param xQueue The handle of the queue being added to the registry. This + * is the handle returned by a call to xQueueCreate(). Semaphore and mutex + * handles can also be passed in here. + * + * @param pcQueueName The name to be associated with the handle. This is the + * name that the kernel aware debugger will display. The queue registry only + * stores a pointer to the string - so the string must be persistent (global or + * preferably in ROM/Flash), not on the stack. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + void vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#endif + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to + * remove the queue, semaphore or mutex from the register. If you are not using + * a kernel aware debugger then this function can be ignored. + * + * @param xQueue The handle of the queue being removed from the registry. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * The queue registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call pcQueueGetName() to look + * up and return the name of a queue in the queue registry from the queue's + * handle. + * + * @param xQueue The handle of the queue the name of which will be returned. + * @return If the queue is in the registry then a pointer to the name of the + * queue is returned. If the queue is not in the registry then NULL is + * returned. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#endif + +/* + * Generic version of the function used to create a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +#endif + +/* + * Generic version of the function used to create a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +#endif + +/* + * Queue sets provide a mechanism to allow a task to block (pend) on a read + * operation from multiple queues or semaphores simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * A queue set must be explicitly created using a call to xQueueCreateSet() + * before it can be used. Once created, standard FreeRTOS queues and semaphores + * can be added to the set using calls to xQueueAddToSet(). + * xQueueSelectFromSet() is then used to determine which, if any, of the queues + * or semaphores contained in the set is in a state where a queue read or + * semaphore take operation would be successful. + * + * Note 1: See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: An additional 4 bytes of RAM is required for each space in a every + * queue added to a queue set. Therefore counting semaphores that have a high + * maximum count value should not be added to a queue set. + * + * Note 4: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param uxEventQueueLength Queue sets store events that occur on + * the queues and semaphores contained in the set. uxEventQueueLength specifies + * the maximum number of events that can be queued at once. To be absolutely + * certain that events are not lost uxEventQueueLength should be set to the + * total sum of the length of the queues added to the set, where binary + * semaphores and mutexes have a length of 1, and counting semaphores have a + * length set by their maximum count value. Examples: + * + If a queue set is to hold a queue of length 5, another queue of length 12, + * and a binary semaphore, then uxEventQueueLength should be set to + * (5 + 12 + 1), or 18. + * + If a queue set is to hold three binary semaphores then uxEventQueueLength + * should be set to (1 + 1 + 1 ), or 3. + * + If a queue set is to hold a counting semaphore that has a maximum count of + * 5, and a counting semaphore that has a maximum count of 3, then + * uxEventQueueLength should be set to (5 + 3), or 8. + * + * @return If the queue set is created successfully then a handle to the created + * queue set is returned. Otherwise NULL is returned. + */ +QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION; + +/* + * Adds a queue or semaphore to a queue set that was previously created by a + * call to xQueueCreateSet(). + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being added to + * the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set to which the queue or semaphore + * is being added. + * + * @return If the queue or semaphore was successfully added to the queue set + * then pdPASS is returned. If the queue could not be successfully added to the + * queue set because it is already a member of a different queue set then pdFAIL + * is returned. + */ +BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* + * Removes a queue or semaphore from a queue set. A queue or semaphore can only + * be removed from a set if the queue or semaphore is empty. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being removed + * from the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set in which the queue or semaphore + * is included. + * + * @return If the queue or semaphore was successfully removed from the queue set + * then pdPASS is returned. If the queue was not in the queue set, or the + * queue (or semaphore) was not empty, then pdFAIL is returned. + */ +BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* + * xQueueSelectFromSet() selects from the members of a queue set a queue or + * semaphore that either contains data (in the case of a queue) or is available + * to take (in the case of a semaphore). xQueueSelectFromSet() effectively + * allows a task to block (pend) on a read operation on all the queues and + * semaphores in a queue set simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueSet The queue set on which the task will (potentially) block. + * + * @param xTicksToWait The maximum time, in ticks, that the calling task will + * remain in the Blocked state (with other tasks executing) to wait for a member + * of the queue set to be ready for a successful queue read or semaphore take + * operation. + * + * @return xQueueSelectFromSet() will return the handle of a queue (cast to + * a QueueSetMemberHandle_t type) contained in the queue set that contains data, + * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained + * in the queue set that is available, or NULL if no such queue or semaphore + * exists before before the specified block time expires. + */ +QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/* + * A version of xQueueSelectFromSet() that can be used from an ISR. + */ +QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* Not public API functions. */ +void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) PRIVILEGED_FUNCTION; +void vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* QUEUE_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/semphr.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/semphr.h new file mode 100644 index 0000000..e0193bd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/semphr.h @@ -0,0 +1,1193 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SEMAPHORE_H +#define SEMAPHORE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include semphr.h" +#endif + +#include "queue.h" + +typedef QueueHandle_t SemaphoreHandle_t; + +#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( uint8_t ) 1U ) +#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( uint8_t ) 0U ) +#define semGIVE_BLOCK_TIME ( ( TickType_t ) 0U ) + + +/** + * semphr. h + * @code{c} + * vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * Macro that implements a semaphore by using the existing queue mechanism. + * The queue length is 1 as this is a binary semaphore. The data size is 0 + * as we don't want to actually store any data - we just want to know if the + * queue is empty or full. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param xSemaphore Handle to the created semaphore. Should be of type SemaphoreHandle_t. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to vSemaphoreCreateBinary (). + * // This is a macro so pass the variable in directly. + * vSemaphoreCreateBinary( xSemaphore ); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define vSemaphoreCreateBinary( xSemaphore ) \ + { \ + ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \ + if( ( xSemaphore ) != NULL ) \ + { \ + ( void ) xSemaphoreGive( ( xSemaphore ) ); \ + } \ + } +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateBinary( void ); + * @endcode + * + * Creates a new binary semaphore instance, and returns a handle by which the + * new semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, binary semaphores use a block + * of memory, in which the semaphore structure is stored. If a binary semaphore + * is created using xSemaphoreCreateBinary() then the required memory is + * automatically dynamically allocated inside the xSemaphoreCreateBinary() + * function. (see https://www.FreeRTOS.org/a00111.html). If a binary semaphore + * is created using xSemaphoreCreateBinaryStatic() then the application writer + * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a + * binary semaphore to be created without using any dynamic memory allocation. + * + * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @return Handle to the created semaphore, or NULL if the memory required to + * hold the semaphore's data structures could not be allocated. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to xSemaphoreCreateBinary(). + * // This is a macro so pass the variable in directly. + * xSemaphore = xSemaphoreCreateBinary(); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ) +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer ); + * @endcode + * + * Creates a new binary semaphore instance, and returns a handle by which the + * new semaphore can be referenced. + * + * NOTE: In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, binary semaphores use a block + * of memory, in which the semaphore structure is stored. If a binary semaphore + * is created using xSemaphoreCreateBinary() then the required memory is + * automatically dynamically allocated inside the xSemaphoreCreateBinary() + * function. (see https://www.FreeRTOS.org/a00111.html). If a binary semaphore + * is created using xSemaphoreCreateBinaryStatic() then the application writer + * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a + * binary semaphore to be created without using any dynamic memory allocation. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the semaphore's data structure, removing the + * need for the memory to be allocated dynamically. + * + * @return If the semaphore is created then a handle to the created semaphore is + * returned. If pxSemaphoreBuffer is NULL then NULL is returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * StaticSemaphore_t xSemaphoreBuffer; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to xSemaphoreCreateBinary(). + * // The semaphore's data structures will be placed in the xSemaphoreBuffer + * // variable, the address of which is passed into the function. The + * // function's parameter is not NULL, so the function will not attempt any + * // dynamic memory allocation, and therefore the function will not return + * // return NULL. + * xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer ); + * + * // Rest of task code goes here. + * } + * @endcode + * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic + * \ingroup Semaphores + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, ( pxStaticSemaphore ), queueQUEUE_TYPE_BINARY_SEMAPHORE ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * @code{c} + * xSemaphoreTake( + * SemaphoreHandle_t xSemaphore, + * TickType_t xBlockTime + * ); + * @endcode + * + * Macro to obtain a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). + * + * @param xSemaphore A handle to the semaphore being taken - obtained when + * the semaphore was created. + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. A block + * time of portMAX_DELAY can be used to block indefinitely (provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h). + * + * @return pdTRUE if the semaphore was obtained. pdFALSE + * if xBlockTime expired without the semaphore becoming available. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * + * // A task that creates a semaphore. + * void vATask( void * pvParameters ) + * { + * // Create the semaphore to guard a shared resource. + * xSemaphore = xSemaphoreCreateBinary(); + * } + * + * // A task that uses the semaphore. + * void vAnotherTask( void * pvParameters ) + * { + * // ... Do other things. + * + * if( xSemaphore != NULL ) + * { + * // See if we can obtain the semaphore. If the semaphore is not available + * // wait 10 ticks to see if it becomes free. + * if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE ) + * { + * // We were able to obtain the semaphore and can now access the + * // shared resource. + * + * // ... + * + * // We have finished accessing the shared resource. Release the + * // semaphore. + * xSemaphoreGive( xSemaphore ); + * } + * else + * { + * // We could not obtain the semaphore and can therefore not access + * // the shared resource safely. + * } + * } + * } + * @endcode + * \defgroup xSemaphoreTake xSemaphoreTake + * \ingroup Semaphores + */ +#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) ) + +/** + * semphr. h + * @code{c} + * xSemaphoreTakeRecursive( + * SemaphoreHandle_t xMutex, + * TickType_t xBlockTime + * ); + * @endcode + * + * Macro to recursively obtain, or 'take', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being obtained. This is the + * handle returned by xSemaphoreCreateRecursiveMutex(); + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. If + * the task already owns the semaphore then xSemaphoreTakeRecursive() will + * return immediately no matter what the value of xBlockTime. + * + * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime + * expired without the semaphore becoming available. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xMutex = NULL; + * + * // A task that creates a mutex. + * void vATask( void * pvParameters ) + * { + * // Create the mutex to guard a shared resource. + * xMutex = xSemaphoreCreateRecursiveMutex(); + * } + * + * // A task that uses the mutex. + * void vAnotherTask( void * pvParameters ) + * { + * // ... Do other things. + * + * if( xMutex != NULL ) + * { + * // See if we can obtain the mutex. If the mutex is not available + * // wait 10 ticks to see if it becomes free. + * if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE ) + * { + * // We were able to obtain the mutex and can now access the + * // shared resource. + * + * // ... + * // For some reason due to the nature of the code further calls to + * // xSemaphoreTakeRecursive() are made on the same mutex. In real + * // code these would not be just sequential calls as this would make + * // no sense. Instead the calls are likely to be buried inside + * // a more complex call structure. + * xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ); + * xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ); + * + * // The mutex has now been 'taken' three times, so will not be + * // available to another task until it has also been given back + * // three times. Again it is unlikely that real code would have + * // these calls sequentially, but instead buried in a more complex + * // call structure. This is just for illustrative purposes. + * xSemaphoreGiveRecursive( xMutex ); + * xSemaphoreGiveRecursive( xMutex ); + * xSemaphoreGiveRecursive( xMutex ); + * + * // Now the mutex can be taken by other tasks. + * } + * else + * { + * // We could not obtain the mutex and can therefore not access + * // the shared resource safely. + * } + * } + * } + * @endcode + * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive + * \ingroup Semaphores + */ +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + #define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) ) +#endif + +/** + * semphr. h + * @code{c} + * xSemaphoreGive( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake(). + * + * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for + * an alternative which can be used from an ISR. + * + * This macro must also not be used on semaphores created using + * xSemaphoreCreateRecursiveMutex(). + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. + * Semaphores are implemented using queues. An error can occur if there is + * no space on the queue to post a message - indicating that the + * semaphore was not first obtained correctly. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * + * void vATask( void * pvParameters ) + * { + * // Create the semaphore to guard a shared resource. + * xSemaphore = vSemaphoreCreateBinary(); + * + * if( xSemaphore != NULL ) + * { + * if( xSemaphoreGive( xSemaphore ) != pdTRUE ) + * { + * // We would expect this call to fail because we cannot give + * // a semaphore without first "taking" it! + * } + * + * // Obtain the semaphore - don't block if the semaphore is not + * // immediately available. + * if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) ) + * { + * // We now have the semaphore and can access the shared resource. + * + * // ... + * + * // We have finished accessing the shared resource so can free the + * // semaphore. + * if( xSemaphoreGive( xSemaphore ) != pdTRUE ) + * { + * // We would not expect this call to fail because we must have + * // obtained the semaphore to get here. + * } + * } + * } + * } + * @endcode + * \defgroup xSemaphoreGive xSemaphoreGive + * \ingroup Semaphores + */ +#define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) + +/** + * semphr. h + * @code{c} + * xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex ); + * @endcode + * + * Macro to recursively release, or 'give', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being released, or 'given'. This is the + * handle returned by xSemaphoreCreateMutex(); + * + * @return pdTRUE if the semaphore was given. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xMutex = NULL; + * + * // A task that creates a mutex. + * void vATask( void * pvParameters ) + * { + * // Create the mutex to guard a shared resource. + * xMutex = xSemaphoreCreateRecursiveMutex(); + * } + * + * // A task that uses the mutex. + * void vAnotherTask( void * pvParameters ) + * { + * // ... Do other things. + * + * if( xMutex != NULL ) + * { + * // See if we can obtain the mutex. If the mutex is not available + * // wait 10 ticks to see if it becomes free. + * if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE ) + * { + * // We were able to obtain the mutex and can now access the + * // shared resource. + * + * // ... + * // For some reason due to the nature of the code further calls to + * // xSemaphoreTakeRecursive() are made on the same mutex. In real + * // code these would not be just sequential calls as this would make + * // no sense. Instead the calls are likely to be buried inside + * // a more complex call structure. + * xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ); + * xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ); + * + * // The mutex has now been 'taken' three times, so will not be + * // available to another task until it has also been given back + * // three times. Again it is unlikely that real code would have + * // these calls sequentially, it would be more likely that the calls + * // to xSemaphoreGiveRecursive() would be called as a call stack + * // unwound. This is just for demonstrative purposes. + * xSemaphoreGiveRecursive( xMutex ); + * xSemaphoreGiveRecursive( xMutex ); + * xSemaphoreGiveRecursive( xMutex ); + * + * // Now the mutex can be taken by other tasks. + * } + * else + * { + * // We could not obtain the mutex and can therefore not access + * // the shared resource safely. + * } + * } + * } + * @endcode + * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive + * \ingroup Semaphores + */ +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + #define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( ( xMutex ) ) +#endif + +/** + * semphr. h + * @code{c} + * xSemaphoreGiveFromISR( + * SemaphoreHandle_t xSemaphore, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR. + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreGiveFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + \#define LONG_TIME 0xffff + \#define TICKS_TO_WAIT 10 + * SemaphoreHandle_t xSemaphore = NULL; + * + * // Repetitive task. + * void vATask( void * pvParameters ) + * { + * for( ;; ) + * { + * // We want this task to run every 10 ticks of a timer. The semaphore + * // was created before this task was started. + * + * // Block waiting for the semaphore to become available. + * if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE ) + * { + * // It is time to execute. + * + * // ... + * + * // We have finished our task. Return to the top of the loop where + * // we will block on the semaphore until it is time to execute + * // again. Note when using the semaphore for synchronisation with an + * // ISR in this manner there is no need to 'give' the semaphore back. + * } + * } + * } + * + * // Timer ISR + * void vTimerISR( void * pvParameters ) + * { + * static uint8_t ucLocalTickCount = 0; + * static BaseType_t xHigherPriorityTaskWoken; + * + * // A timer tick has occurred. + * + * // ... Do other time functions. + * + * // Is it time for vATask () to run? + * xHigherPriorityTaskWoken = pdFALSE; + * ucLocalTickCount++; + * if( ucLocalTickCount >= TICKS_TO_WAIT ) + * { + * // Unblock the task by releasing the semaphore. + * xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken ); + * + * // Reset the count so we release the semaphore again in 10 ticks time. + * ucLocalTickCount = 0; + * } + * + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // We can force a context switch here. Context switching from an + * // ISR uses port specific syntax. Check the demo task for your port + * // to find the syntax required. + * } + * } + * @endcode + * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR + * \ingroup Semaphores + */ +#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * @code{c} + * xSemaphoreTakeFromISR( + * SemaphoreHandle_t xSemaphore, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * Macro to take a semaphore from an ISR. The semaphore must have + * previously been created with a call to xSemaphoreCreateBinary() or + * xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR, however taking a semaphore from an ISR + * is not a common operation. It is likely to only be useful when taking a + * counting semaphore when an interrupt is obtaining an object from a resource + * pool (when the semaphore count indicates the number of resources available). + * + * @param xSemaphore A handle to the semaphore being taken. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreTakeFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully taken, otherwise + * pdFALSE + */ +#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateMutex( void ); + * @endcode + * + * Creates a new mutex type semaphore instance, and returns a handle by which + * the new mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, mutex semaphores use a block + * of memory, in which the mutex structure is stored. If a mutex is created + * using xSemaphoreCreateMutex() then the required memory is automatically + * dynamically allocated inside the xSemaphoreCreateMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a mutex is created using + * xSemaphoreCreateMutexStatic() then the application writer must provided the + * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created + * without using any dynamic memory allocation. + * + * Mutexes created using this function can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros must not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return If the mutex was successfully created then a handle to the created + * semaphore is returned. If there was not enough heap to allocate the mutex + * data structures then NULL is returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to xSemaphoreCreateMutex(). + * // This is a macro so pass the variable in directly. + * xSemaphore = xSemaphoreCreateMutex(); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_MUTEXES == 1 ) ) + #define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX ) +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer ); + * @endcode + * + * Creates a new mutex type semaphore instance, and returns a handle by which + * the new mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, mutex semaphores use a block + * of memory, in which the mutex structure is stored. If a mutex is created + * using xSemaphoreCreateMutex() then the required memory is automatically + * dynamically allocated inside the xSemaphoreCreateMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a mutex is created using + * xSemaphoreCreateMutexStatic() then the application writer must provided the + * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created + * without using any dynamic memory allocation. + * + * Mutexes created using this function can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros must not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t, + * which will be used to hold the mutex's data structure, removing the need for + * the memory to be allocated dynamically. + * + * @return If the mutex was successfully created then a handle to the created + * mutex is returned. If pxMutexBuffer was NULL then NULL is returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * StaticSemaphore_t xMutexBuffer; + * + * void vATask( void * pvParameters ) + * { + * // A mutex cannot be used before it has been created. xMutexBuffer is + * // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is + * // attempted. + * xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer ); + * + * // As no dynamic memory allocation was performed, xSemaphore cannot be NULL, + * // so there is no need to check it. + * } + * @endcode + * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_MUTEXES == 1 ) ) + #define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) ) +#endif + + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void ); + * @endcode + * + * Creates a new recursive mutex type semaphore instance, and returns a handle + * by which the new recursive mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, recursive mutexes use a block + * of memory, in which the mutex structure is stored. If a recursive mutex is + * created using xSemaphoreCreateRecursiveMutex() then the required memory is + * automatically dynamically allocated inside the + * xSemaphoreCreateRecursiveMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a recursive mutex is created using + * xSemaphoreCreateRecursiveMutexStatic() then the application writer must + * provide the memory that will get used by the mutex. + * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to + * be created without using any dynamic memory allocation. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros must not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return xSemaphore Handle to the created mutex semaphore. Should be of type + * SemaphoreHandle_t. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to xSemaphoreCreateMutex(). + * // This is a macro so pass the variable in directly. + * xSemaphore = xSemaphoreCreateRecursiveMutex(); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + #define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX ) +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer ); + * @endcode + * + * Creates a new recursive mutex type semaphore instance, and returns a handle + * by which the new recursive mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, recursive mutexes use a block + * of memory, in which the mutex structure is stored. If a recursive mutex is + * created using xSemaphoreCreateRecursiveMutex() then the required memory is + * automatically dynamically allocated inside the + * xSemaphoreCreateRecursiveMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a recursive mutex is created using + * xSemaphoreCreateRecursiveMutexStatic() then the application writer must + * provide the memory that will get used by the mutex. + * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to + * be created without using any dynamic memory allocation. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros must not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the recursive mutex's data structure, + * removing the need for the memory to be allocated dynamically. + * + * @return If the recursive mutex was successfully created then a handle to the + * created recursive mutex is returned. If pxMutexBuffer was NULL then NULL is + * returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * StaticSemaphore_t xMutexBuffer; + * + * void vATask( void * pvParameters ) + * { + * // A recursive semaphore cannot be used before it is created. Here a + * // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic(). + * // The address of xMutexBuffer is passed into the function, and will hold + * // the mutexes data structures - so no dynamic memory allocation will be + * // attempted. + * xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer ); + * + * // As no dynamic memory allocation was performed, xSemaphore cannot be NULL, + * // so there is no need to check it. + * } + * @endcode + * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, ( pxStaticSemaphore ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount ); + * @endcode + * + * Creates a new counting semaphore instance, and returns a handle by which the + * new counting semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a counting semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, counting semaphores use a + * block of memory, in which the counting semaphore structure is stored. If a + * counting semaphore is created using xSemaphoreCreateCounting() then the + * required memory is automatically dynamically allocated inside the + * xSemaphoreCreateCounting() function. (see + * https://www.FreeRTOS.org/a00111.html). If a counting semaphore is created + * using xSemaphoreCreateCountingStatic() then the application writer can + * instead optionally provide the memory that will get used by the counting + * semaphore. xSemaphoreCreateCountingStatic() therefore allows a counting + * semaphore to be created without using any dynamic memory allocation. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @return Handle to the created semaphore. Null if the semaphore could not be + * created. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * + * void vATask( void * pvParameters ) + * { + * SemaphoreHandle_t xSemaphore = NULL; + * + * // Semaphore cannot be used before a call to xSemaphoreCreateCounting(). + * // The max value to which the semaphore can count should be 10, and the + * // initial value assigned to the count should be 0. + * xSemaphore = xSemaphoreCreateCounting( 10, 0 ); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) ) +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer ); + * @endcode + * + * Creates a new counting semaphore instance, and returns a handle by which the + * new counting semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a counting semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, counting semaphores use a + * block of memory, in which the counting semaphore structure is stored. If a + * counting semaphore is created using xSemaphoreCreateCounting() then the + * required memory is automatically dynamically allocated inside the + * xSemaphoreCreateCounting() function. (see + * https://www.FreeRTOS.org/a00111.html). If a counting semaphore is created + * using xSemaphoreCreateCountingStatic() then the application writer must + * provide the memory. xSemaphoreCreateCountingStatic() therefore allows a + * counting semaphore to be created without using any dynamic memory allocation. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the semaphore's data structure, removing the + * need for the memory to be allocated dynamically. + * + * @return If the counting semaphore was successfully created then a handle to + * the created counting semaphore is returned. If pxSemaphoreBuffer was NULL + * then NULL is returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * StaticSemaphore_t xSemaphoreBuffer; + * + * void vATask( void * pvParameters ) + * { + * SemaphoreHandle_t xSemaphore = NULL; + * + * // Counting semaphore cannot be used before they have been created. Create + * // a counting semaphore using xSemaphoreCreateCountingStatic(). The max + * // value to which the semaphore can count is 10, and the initial value + * // assigned to the count will be 0. The address of xSemaphoreBuffer is + * // passed in and will be used to hold the semaphore structure, so no dynamic + * // memory allocation will be used. + * xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer ); + * + * // No memory allocation was attempted so xSemaphore cannot be NULL, so there + * // is no need to check its value. + * } + * @endcode + * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic + * \ingroup Semaphores + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * @code{c} + * void vSemaphoreDelete( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * Delete a semaphore. This function must be used with care. For example, + * do not delete a mutex type semaphore if the mutex is held by a task. + * + * @param xSemaphore A handle to the semaphore to be deleted. + * + * \defgroup vSemaphoreDelete vSemaphoreDelete + * \ingroup Semaphores + */ +#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) ) + +/** + * semphr.h + * @code{c} + * TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex ); + * @endcode + * + * If xMutex is indeed a mutex type semaphore, return the current mutex holder. + * If xMutex is not a mutex type semaphore, or the mutex is available (not held + * by a task), return NULL. + * + * Note: This is a good way of determining if the calling task is the mutex + * holder, but not a good way of determining the identity of the mutex holder as + * the holder may change between the function exiting and the returned value + * being tested. + */ +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + #define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) ) +#endif + +/** + * semphr.h + * @code{c} + * TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex ); + * @endcode + * + * If xMutex is indeed a mutex type semaphore, return the current mutex holder. + * If xMutex is not a mutex type semaphore, or the mutex is available (not held + * by a task), return NULL. + * + */ +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + #define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) ) +#endif + +/** + * semphr.h + * @code{c} + * UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns + * its current count value. If the semaphore is a binary semaphore then + * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the + * semaphore is not available. + * + */ +#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) ) + +/** + * semphr.h + * @code{c} + * UBaseType_t uxSemaphoreGetCountFromISR( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * If the semaphore is a counting semaphore then uxSemaphoreGetCountFromISR() returns + * its current count value. If the semaphore is a binary semaphore then + * uxSemaphoreGetCountFromISR() returns 1 if the semaphore is available, and 0 if the + * semaphore is not available. + * + */ +#define uxSemaphoreGetCountFromISR( xSemaphore ) uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) ) + +#endif /* SEMAPHORE_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/stack_macros.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/stack_macros.h new file mode 100644 index 0000000..a289bd0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/stack_macros.h @@ -0,0 +1,137 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef STACK_MACROS_H +#define STACK_MACROS_H + +/* + * Call the stack overflow hook function if the stack of the task being swapped + * out is currently overflowed, or looks like it might have overflowed in the + * past. + * + * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check + * the current stack state only - comparing the current top of stack value to + * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 + * will also cause the last few stack bytes to be checked to ensure the value + * to which the bytes were set when the task was created have not been + * overwritten. Note this second test does not guarantee that an overflowed + * stack will always be recognised. + */ + +/*-----------------------------------------------------------*/ + +/* + * portSTACK_LIMIT_PADDING is a number of extra words to consider to be in + * use on the stack. + */ +#ifndef portSTACK_LIMIT_PADDING + #define portSTACK_LIMIT_PADDING 0 +#endif + +#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) ) + +/* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, (signed char *)pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) ) + +/* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ + const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \ + \ + if( ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \ + static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ + \ + \ + pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ + \ + /* Has the extremity of the task stack ever been written over? */ \ + if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +/* Remove stack overflow macro if not being used. */ +#ifndef taskCHECK_FOR_STACK_OVERFLOW + #define taskCHECK_FOR_STACK_OVERFLOW() +#endif + + + +#endif /* STACK_MACROS_H */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/stdint.readme b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/stdint.readme similarity index 88% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/stdint.readme rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/stdint.readme index 629ae4b..03208f8 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/stdint.readme +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/stdint.readme @@ -1,52 +1,58 @@ -/* - * FreeRTOS Kernel V10.4.3 LTS Patch 2 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -#ifndef FREERTOS_STDINT -#define FREERTOS_STDINT - -/******************************************************************************* - * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions - * necessary to build the FreeRTOS code. It is provided to allow FreeRTOS to be - * built using compilers that do not provide their own stdint.h definition. - * - * To use this file: - * - * 1) Copy this file into the directory that contains your FreeRTOSConfig.h - * header file, as that directory will already be in the compiler's include - * path. - * - * 2) Rename the copied file stdint.h. - * - */ - -typedef signed char int8_t; -typedef unsigned char uint8_t; -typedef short int16_t; -typedef unsigned short uint16_t; -typedef long int32_t; -typedef unsigned long uint32_t; - -#endif /* FREERTOS_STDINT */ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_STDINT +#define FREERTOS_STDINT + +/******************************************************************************* + * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions + * necessary to build the FreeRTOS code. It is provided to allow FreeRTOS to be + * built using compilers that do not provide their own stdint.h definition. + * + * To use this file: + * + * 1) Copy this file into the directory that contains your FreeRTOSConfig.h + * header file, as that directory will already be in the compiler's include + * path. + * + * 2) Rename the copied file stdint.h. + * + */ + +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef short int16_t; +typedef unsigned short uint16_t; +typedef long int32_t; +typedef unsigned long uint32_t; + +#ifndef SIZE_MAX + #define SIZE_MAX ( ( size_t ) -1 ) +#endif + +#endif /* FREERTOS_STDINT */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/stream_buffer.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/stream_buffer.h new file mode 100644 index 0000000..955c094 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/stream_buffer.h @@ -0,0 +1,913 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Stream buffers are used to send a continuous stream of data from one task or + * interrupt to another. Their implementation is light weight, making them + * particularly suited for interrupt to task and core to core communication + * scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section section and set the + * receive block time to 0. + * + */ + +#ifndef STREAM_BUFFER_H +#define STREAM_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include stream_buffer.h" +#endif + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * Type by which stream buffers are referenced. For example, a call to + * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can + * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(), + * etc. + */ +struct StreamBufferDef_t; +typedef struct StreamBufferDef_t * StreamBufferHandle_t; + +/** + * Type used as a stream buffer's optional callback. + */ +typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuffer, + BaseType_t xIsInsideISR, + BaseType_t * const pxHigherPriorityTaskWoken ); + +/** + * stream_buffer.h + * + * @code{c} + * StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes ); + * @endcode + * + * Creates a new stream buffer using dynamically allocated memory. See + * xStreamBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xStreamBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes the stream buffer will be + * able to hold at any one time. + * + * @param xTriggerLevelBytes The number of bytes that must be in the stream + * buffer before a task that is blocked on the stream buffer to wait for data is + * moved out of the blocked state. For example, if a task is blocked on a read + * of an empty stream buffer that has a trigger level of 1 then the task will be + * unblocked when a single byte is written to the buffer or the task's block + * time expires. As another example, if a task is blocked on a read of an empty + * stream buffer that has a trigger level of 10 then the task will not be + * unblocked until the stream buffer contains at least 10 bytes or the task's + * block time expires. If a reading task's block time expires before the + * trigger level is reached then the task will still receive however many bytes + * are actually available. Setting a trigger level of 0 will result in a + * trigger level of 1 being used. It is not valid to specify a trigger level + * that is greater than the buffer size. + * + * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to + * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default + * implementation provided by sbSEND_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a + * stream buffer. If the parameter is NULL, it will use the default + * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @return If NULL is returned, then the stream buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the stream buffer data structures and storage area. A non-NULL value being + * returned indicates that the stream buffer has been created successfully - + * the returned value should be stored as the handle to the created stream + * buffer. + * + * Example use: + * @code{c} + * + * void vAFunction( void ) + * { + * StreamBufferHandle_t xStreamBuffer; + * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10; + * + * // Create a stream buffer that can hold 100 bytes. The memory used to hold + * // both the stream buffer structure and the data in the stream buffer is + * // allocated dynamically. + * xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel ); + * + * if( xStreamBuffer == NULL ) + * { + * // There was not enough heap memory space available to create the + * // stream buffer. + * } + * else + * { + * // The stream buffer was created successfully and can now be used. + * } + * } + * @endcode + * \defgroup xStreamBufferCreate xStreamBufferCreate + * \ingroup StreamBufferManagement + */ + +#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \ + xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, NULL, NULL ) + +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define xStreamBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \ + xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) ) +#endif + +/** + * stream_buffer.h + * + * @code{c} + * StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes, + * size_t xTriggerLevelBytes, + * uint8_t *pucStreamBufferStorageArea, + * StaticStreamBuffer_t *pxStaticStreamBuffer ); + * @endcode + * Creates a new stream buffer using statically allocated memory. See + * xStreamBufferCreate() for a version that uses dynamically allocated memory. + * + * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for + * xStreamBufferCreateStatic() to be available. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucStreamBufferStorageArea parameter. + * + * @param xTriggerLevelBytes The number of bytes that must be in the stream + * buffer before a task that is blocked on the stream buffer to wait for data is + * moved out of the blocked state. For example, if a task is blocked on a read + * of an empty stream buffer that has a trigger level of 1 then the task will be + * unblocked when a single byte is written to the buffer or the task's block + * time expires. As another example, if a task is blocked on a read of an empty + * stream buffer that has a trigger level of 10 then the task will not be + * unblocked until the stream buffer contains at least 10 bytes or the task's + * block time expires. If a reading task's block time expires before the + * trigger level is reached then the task will still receive however many bytes + * are actually available. Setting a trigger level of 0 will result in a + * trigger level of 1 being used. It is not valid to specify a trigger level + * that is greater than the buffer size. + * + * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes big. This is the array to which streams are + * copied when they are written to the stream buffer. + * + * @param pxStaticStreamBuffer Must point to a variable of type + * StaticStreamBuffer_t, which will be used to hold the stream buffer's data + * structure. + * + * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to + * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default + * implementation provided by sbSEND_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a + * stream buffer. If the parameter is NULL, it will use the default + * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @return If the stream buffer is created successfully then a handle to the + * created stream buffer is returned. If either pucStreamBufferStorageArea or + * pxStaticstreamBuffer are NULL then NULL is returned. + * + * Example use: + * @code{c} + * + * // Used to dimension the array used to hold the streams. The available space + * // will actually be one less than this, so 999. + #define STORAGE_SIZE_BYTES 1000 + * + * // Defines the memory that will actually hold the streams within the stream + * // buffer. + * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ]; + * + * // The variable used to hold the stream buffer structure. + * StaticStreamBuffer_t xStreamBufferStruct; + * + * void MyFunction( void ) + * { + * StreamBufferHandle_t xStreamBuffer; + * const size_t xTriggerLevel = 1; + * + * xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ), + * xTriggerLevel, + * ucStorageBuffer, + * &xStreamBufferStruct ); + * + * // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer + * // parameters were NULL, xStreamBuffer will not be NULL, and can be used to + * // reference the created stream buffer in other stream buffer API calls. + * + * // Other code that uses the stream buffer can go here. + * } + * + * @endcode + * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic + * \ingroup StreamBufferManagement + */ + +#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \ + xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL ) + +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define xStreamBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \ + xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) ) +#endif + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + * const void *pvTxData, + * size_t xDataLengthBytes, + * TickType_t xTicksToWait ); + * @endcode + * + * Sends bytes to a stream buffer. The bytes are copied into the stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferSend() to write to a stream buffer from a task. Use + * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt + * service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer to which a stream is + * being sent. + * + * @param pvTxData A pointer to the buffer that holds the bytes to be copied + * into the stream buffer. + * + * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData + * into the stream buffer. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for enough space to become available in the stream + * buffer, should the stream buffer contain too little space to hold the + * another xDataLengthBytes bytes. The block time is specified in tick periods, + * so the absolute time it represents is dependent on the tick frequency. The + * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds + * into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will + * cause the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. If a task times out + * before it can write all xDataLengthBytes into the buffer it will still write + * as many bytes as possible. A task does not use any CPU time when it is in + * the blocked state. + * + * @return The number of bytes written to the stream buffer. If a task times + * out before it can write all xDataLengthBytes into the buffer it will still + * write as many bytes as possible. + * + * Example use: + * @code{c} + * void vAFunction( StreamBufferHandle_t xStreamBuffer ) + * { + * size_t xBytesSent; + * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 }; + * char *pcStringToSend = "String to send"; + * const TickType_t x100ms = pdMS_TO_TICKS( 100 ); + * + * // Send an array to the stream buffer, blocking for a maximum of 100ms to + * // wait for enough space to be available in the stream buffer. + * xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms ); + * + * if( xBytesSent != sizeof( ucArrayToSend ) ) + * { + * // The call to xStreamBufferSend() times out before there was enough + * // space in the buffer for the data to be written, but it did + * // successfully write xBytesSent bytes. + * } + * + * // Send the string to the stream buffer. Return immediately if there is not + * // enough space in the buffer. + * xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // The entire string could not be added to the stream buffer because + * // there was not enough free space in the buffer, but xBytesSent bytes + * // were sent. Could try again to send the remaining bytes. + * } + * } + * @endcode + * \defgroup xStreamBufferSend xStreamBufferSend + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + * const void *pvTxData, + * size_t xDataLengthBytes, + * BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * Interrupt safe version of the API function that sends a stream of bytes to + * the stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferSend() to write to a stream buffer from a task. Use + * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt + * service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer to which a stream is + * being sent. + * + * @param pvTxData A pointer to the data that is to be copied into the stream + * buffer. + * + * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData + * into the stream buffer. + * + * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will + * have a task blocked on it waiting for data. Calling + * xStreamBufferSendFromISR() can make data available, and so cause a task that + * was waiting for data to leave the Blocked state. If calling + * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the + * unblocked task has a priority higher than the currently executing task (the + * task that was interrupted), then, internally, xStreamBufferSendFromISR() + * will set *pxHigherPriorityTaskWoken to pdTRUE. If + * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. This will + * ensure that the interrupt returns directly to the highest priority Ready + * state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it + * is passed into the function. See the example code below for an example. + * + * @return The number of bytes actually written to the stream buffer, which will + * be less than xDataLengthBytes if the stream buffer didn't have enough free + * space for all the bytes to be written. + * + * Example use: + * @code{c} + * // A stream buffer that has already been created. + * StreamBufferHandle_t xStreamBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * size_t xBytesSent; + * char *pcStringToSend = "String to send"; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Attempt to send the string to the stream buffer. + * xBytesSent = xStreamBufferSendFromISR( xStreamBuffer, + * ( void * ) pcStringToSend, + * strlen( pcStringToSend ), + * &xHigherPriorityTaskWoken ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // There was not enough free space in the stream buffer for the entire + * // string to be written, ut xBytesSent bytes were written. + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xStreamBufferSendFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + * void *pvRxData, + * size_t xBufferLengthBytes, + * TickType_t xTicksToWait ); + * @endcode + * + * Receives bytes from a stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferReceive() to read from a stream buffer from a task. Use + * xStreamBufferReceiveFromISR() to read from a stream buffer from an + * interrupt service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer from which bytes are to + * be received. + * + * @param pvRxData A pointer to the buffer into which the received bytes will be + * copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the + * pvRxData parameter. This sets the maximum number of bytes to receive in one + * call. xStreamBufferReceive will return as many bytes as possible up to a + * maximum set by xBufferLengthBytes. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for data to become available if the stream buffer is + * empty. xStreamBufferReceive() will return immediately if xTicksToWait is + * zero. The block time is specified in tick periods, so the absolute time it + * represents is dependent on the tick frequency. The macro pdMS_TO_TICKS() can + * be used to convert a time specified in milliseconds into a time specified in + * ticks. Setting xTicksToWait to portMAX_DELAY will cause the task to wait + * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1 + * in FreeRTOSConfig.h. A task does not use any CPU time when it is in the + * Blocked state. + * + * @return The number of bytes actually read from the stream buffer, which will + * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed + * out before xBufferLengthBytes were available. + * + * Example use: + * @code{c} + * void vAFunction( StreamBuffer_t xStreamBuffer ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 ); + * + * // Receive up to another sizeof( ucRxData ) bytes from the stream buffer. + * // Wait in the Blocked state (so not using any CPU processing time) for a + * // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be + * // available. + * xReceivedBytes = xStreamBufferReceive( xStreamBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * xBlockTime ); + * + * if( xReceivedBytes > 0 ) + * { + * // A ucRxData contains another xReceivedBytes bytes of data, which can + * // be processed here.... + * } + * } + * @endcode + * \defgroup xStreamBufferReceive xStreamBufferReceive + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + * void *pvRxData, + * size_t xBufferLengthBytes, + * BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * An interrupt safe version of the API function that receives bytes from a + * stream buffer. + * + * Use xStreamBufferReceive() to read bytes from a stream buffer from a task. + * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an + * interrupt service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer from which a stream + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received bytes are + * copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the + * pvRxData parameter. This sets the maximum number of bytes to receive in one + * call. xStreamBufferReceive will return as many bytes as possible up to a + * maximum set by xBufferLengthBytes. + * + * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will + * have a task blocked on it waiting for space to become available. Calling + * xStreamBufferReceiveFromISR() can make space available, and so cause a task + * that is waiting for space to leave the Blocked state. If calling + * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and + * the unblocked task has a priority higher than the currently executing task + * (the task that was interrupted), then, internally, + * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE. + * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. That will + * ensure the interrupt returns directly to the highest priority Ready state + * task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is + * passed into the function. See the code example below for an example. + * + * @return The number of bytes read from the stream buffer, if any. + * + * Example use: + * @code{c} + * // A stream buffer that has already been created. + * StreamBuffer_t xStreamBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Receive the next stream from the stream buffer. + * xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * &xHigherPriorityTaskWoken ); + * + * if( xReceivedBytes > 0 ) + * { + * // ucRxData contains xReceivedBytes read from the stream buffer. + * // Process the stream here.... + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xStreamBufferReceiveFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Deletes a stream buffer that was previously created using a call to + * xStreamBufferCreate() or xStreamBufferCreateStatic(). If the stream + * buffer was created using dynamic memory (that is, by xStreamBufferCreate()), + * then the allocated memory is freed. + * + * A stream buffer handle must not be used after the stream buffer has been + * deleted. + * + * @param xStreamBuffer The handle of the stream buffer to be deleted. + * + * \defgroup vStreamBufferDelete vStreamBufferDelete + * \ingroup StreamBufferManagement + */ +void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Queries a stream buffer to see if it is full. A stream buffer is full if it + * does not have any free space, and therefore cannot accept any more data. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return If the stream buffer is full then pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferIsFull xStreamBufferIsFull + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Queries a stream buffer to see if it is empty. A stream buffer is empty if + * it does not contain any data. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return If the stream buffer is empty then pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Resets a stream buffer to its initial, empty, state. Any data that was in + * the stream buffer is discarded. A stream buffer can only be reset if there + * are no tasks blocked waiting to either send to or receive from the stream + * buffer. + * + * @param xStreamBuffer The handle of the stream buffer being reset. + * + * @return If the stream buffer is reset then pdPASS is returned. If there was + * a task blocked waiting to send to or read from the stream buffer then the + * stream buffer is not reset and pdFAIL is returned. + * + * \defgroup xStreamBufferReset xStreamBufferReset + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Queries a stream buffer to see how much free space it contains, which is + * equal to the amount of data that can be sent to the stream buffer before it + * is full. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return The number of bytes that can be written to the stream buffer before + * the stream buffer would be full. + * + * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Queries a stream buffer to see how much data it contains, which is equal to + * the number of bytes that can be read from the stream buffer before the stream + * buffer would be empty. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return The number of bytes that can be read from the stream buffer before + * the stream buffer would be empty. + * + * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ); + * @endcode + * + * A stream buffer's trigger level is the number of bytes that must be in the + * stream buffer before a task that is blocked on the stream buffer to + * wait for data is moved out of the blocked state. For example, if a task is + * blocked on a read of an empty stream buffer that has a trigger level of 1 + * then the task will be unblocked when a single byte is written to the buffer + * or the task's block time expires. As another example, if a task is blocked + * on a read of an empty stream buffer that has a trigger level of 10 then the + * task will not be unblocked until the stream buffer contains at least 10 bytes + * or the task's block time expires. If a reading task's block time expires + * before the trigger level is reached then the task will still receive however + * many bytes are actually available. Setting a trigger level of 0 will result + * in a trigger level of 1 being used. It is not valid to specify a trigger + * level that is greater than the buffer size. + * + * A trigger level is set when the stream buffer is created, and can be modified + * using xStreamBufferSetTriggerLevel(). + * + * @param xStreamBuffer The handle of the stream buffer being updated. + * + * @param xTriggerLevel The new trigger level for the stream buffer. + * + * @return If xTriggerLevel was less than or equal to the stream buffer's length + * then the trigger level will be updated and pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * For advanced users only. + * + * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is sent to a message buffer or stream buffer. If there was a task that + * was blocked on the message or stream buffer waiting for data to arrive then + * the sbSEND_COMPLETED() macro sends a notification to the task to remove it + * from the Blocked state. xStreamBufferSendCompletedFromISR() does the same + * thing. It is provided to enable application writers to implement their own + * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer to which data was + * written. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xStreamBufferSendCompletedFromISR(). If calling + * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * For advanced users only. + * + * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is read out of a message buffer or stream buffer. If there was a task + * that was blocked on the message or stream buffer waiting for data to arrive + * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to + * remove it from the Blocked state. xStreamBufferReceiveCompletedFromISR() + * does the same thing. It is provided to enable application writers to + * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT + * ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer from which data was + * read. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xStreamBufferReceiveCompletedFromISR(). If calling + * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/* Functions below here are not part of the public API. */ +StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION; + + +StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION; + +size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +#if ( configUSE_TRACE_FACILITY == 1 ) + void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, + UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION; + UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + } +#endif +/* *INDENT-ON* */ + +#endif /* !defined( STREAM_BUFFER_H ) */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/task.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/task.h new file mode 100644 index 0000000..bae94c6 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/task.h @@ -0,0 +1,3141 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + * + * Copyright 2019 MicroEJ Corp. This file has been modified by MicroEJ Corp. + * 1. Patch for SystemView support + */ + + +#ifndef INC_TASK_H +#define INC_TASK_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include task.h" +#endif + +#include "list.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- +* MACROS AND DEFINITIONS +*----------------------------------------------------------*/ + +/* + * If tskKERNEL_VERSION_NUMBER ends with + it represents the version in development + * after the numbered release. + * + * The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD + * values will reflect the last released version number. + */ +#define tskKERNEL_VERSION_NUMBER "V10.5.1" +#define tskKERNEL_VERSION_MAJOR 10 +#define tskKERNEL_VERSION_MINOR 5 +#define tskKERNEL_VERSION_BUILD 1 + +/* MPU region parameters passed in ulParameters + * of MemoryRegion_t struct. */ +#define tskMPU_REGION_READ_ONLY ( 1UL << 0UL ) +#define tskMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define tskMPU_REGION_EXECUTE_NEVER ( 1UL << 2UL ) +#define tskMPU_REGION_NORMAL_MEMORY ( 1UL << 3UL ) +#define tskMPU_REGION_DEVICE_MEMORY ( 1UL << 4UL ) + +/* The direct to task notification feature used to have only a single notification + * per task. Now there is an array of notifications per task that is dimensioned by + * configTASK_NOTIFICATION_ARRAY_ENTRIES. For backward compatibility, any use of the + * original direct to task notification defaults to using the first index in the + * array. */ +#define tskDEFAULT_INDEX_TO_NOTIFY ( 0 ) + +/** + * task. h + * + * Type by which tasks are referenced. For example, a call to xTaskCreate + * returns (via a pointer parameter) an TaskHandle_t variable that can then + * be used as a parameter to vTaskDelete to delete the task. + * + * \defgroup TaskHandle_t TaskHandle_t + * \ingroup Tasks + */ +struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +typedef struct tskTaskControlBlock * TaskHandle_t; + +/* + * Defines the prototype to which the application task hook function must + * conform. + */ +typedef BaseType_t (* TaskHookFunction_t)( void * ); + +/* Task states returned by eTaskGetState. */ +typedef enum +{ + eRunning = 0, /* A task is querying the state of itself, so must be running. */ + eReady, /* The task being queried is in a ready or pending ready list. */ + eBlocked, /* The task being queried is in the Blocked state. */ + eSuspended, /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */ + eDeleted, /* The task being queried has been deleted, but its TCB has not yet been freed. */ + eInvalid /* Used as an 'invalid state' value. */ +} eTaskState; + +/* Actions that can be performed when vTaskNotify() is called. */ +typedef enum +{ + eNoAction = 0, /* Notify the task without updating its notify value. */ + eSetBits, /* Set bits in the task's notification value. */ + eIncrement, /* Increment the task's notification value. */ + eSetValueWithOverwrite, /* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */ + eSetValueWithoutOverwrite /* Set the task's notification value if the previous value has been read by the task. */ +} eNotifyAction; + +/* + * Used internally only. + */ +typedef struct xTIME_OUT +{ + BaseType_t xOverflowCount; + TickType_t xTimeOnEntering; +} TimeOut_t; + +/* + * Defines the memory ranges allocated to the task when an MPU is used. + */ +typedef struct xMEMORY_REGION +{ + void * pvBaseAddress; + uint32_t ulLengthInBytes; + uint32_t ulParameters; +} MemoryRegion_t; + +/* + * Parameters required to create an MPU protected task. + */ +typedef struct xTASK_PARAMETERS +{ + TaskFunction_t pvTaskCode; + const char * pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + configSTACK_DEPTH_TYPE usStackDepth; + void * pvParameters; + UBaseType_t uxPriority; + StackType_t * puxStackBuffer; + MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ]; + #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + StaticTask_t * const pxTaskBuffer; + #endif +} TaskParameters_t; + +/* Used with the uxTaskGetSystemState() function to return the state of each task + * in the system. */ +typedef struct xTASK_STATUS +{ + TaskHandle_t xHandle; /* The handle of the task to which the rest of the information in the structure relates. */ + const char * pcTaskName; /* A pointer to the task's name. This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + UBaseType_t xTaskNumber; /* A number unique to the task. */ + eTaskState eCurrentState; /* The state in which the task existed when the structure was populated. */ + UBaseType_t uxCurrentPriority; /* The priority at which the task was running (may be inherited) when the structure was populated. */ + UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */ + configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See https://www.FreeRTOS.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */ + StackType_t * pxStackBase; /* Points to the lowest address of the task's stack area. */ + #if ( ( portSTACK_GROWTH > 0 ) && ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + StackType_t * pxTopOfStack; /* Points to the top address of the task's stack area. */ + StackType_t * pxEndOfStack; /* Points to the end address of the task's stack area. */ + #endif + configSTACK_DEPTH_TYPE usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */ +} TaskStatus_t; + +/* Possible return values for eTaskConfirmSleepModeStatus(). */ +typedef enum +{ + eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPRESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */ + eStandardSleep, /* Enter a sleep mode that will not last any longer than the expected idle time. */ + #if ( INCLUDE_vTaskSuspend == 1 ) + eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */ + #endif /* INCLUDE_vTaskSuspend */ +} eSleepModeStatus; + +/** + * Defines the priority used by the idle task. This must not be modified. + * + * \ingroup TaskUtils + */ +#define tskIDLE_PRIORITY ( ( UBaseType_t ) 0U ) + +/** + * task. h + * + * Macro for forcing a context switch. + * + * \defgroup taskYIELD taskYIELD + * \ingroup SchedulerControl + */ +#define taskYIELD() portYIELD() + +/** + * task. h + * + * Macro to mark the start of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL + * \ingroup SchedulerControl + */ +#define taskENTER_CRITICAL() portENTER_CRITICAL() +#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + +/** + * task. h + * + * Macro to mark the end of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL + * \ingroup SchedulerControl + */ +#define taskEXIT_CRITICAL() portEXIT_CRITICAL() +#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) + +/** + * task. h + * + * Macro to disable all maskable interrupts. + * + * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() + +/** + * task. h + * + * Macro to enable microcontroller interrupts. + * + * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() + +/* Definitions returned by xTaskGetSchedulerState(). taskSCHEDULER_SUSPENDED is + * 0 to generate more optimal code when configASSERT() is defined as the constant + * is used in assert() statements. */ +#define taskSCHEDULER_SUSPENDED ( ( BaseType_t ) 0 ) +#define taskSCHEDULER_NOT_STARTED ( ( BaseType_t ) 1 ) +#define taskSCHEDULER_RUNNING ( ( BaseType_t ) 2 ) + + +/*----------------------------------------------------------- +* TASK CREATION API +*----------------------------------------------------------*/ + +/** + * task. h + * @code{c} + * BaseType_t xTaskCreate( + * TaskFunction_t pxTaskCode, + * const char *pcName, + * configSTACK_DEPTH_TYPE usStackDepth, + * void *pvParameters, + * UBaseType_t uxPriority, + * TaskHandle_t *pxCreatedTask + * ); + * @endcode + * + * Create a new task and add it to the list of tasks that are ready to run. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreate() then both blocks of memory are automatically dynamically + * allocated inside the xTaskCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a task is created using + * xTaskCreateStatic() then the application writer must provide the required + * memory. xTaskCreateStatic() therefore allows a task to be created without + * using any dynamic memory allocation. + * + * See xTaskCreateStatic() for a version that does not use any dynamic memory + * allocation. + * + * xTaskCreate() can only be used to create a task that has unrestricted + * access to the entire microcontroller memory map. Systems that include MPU + * support can alternatively create an MPU constrained task using + * xTaskCreateRestricted(). + * + * @param pxTaskCode Pointer to the task entry function. Tasks + * must be implemented to never return (i.e. continuous loop). + * + * @param pcName A descriptive name for the task. This is mainly used to + * facilitate debugging. Max length defined by configMAX_TASK_NAME_LEN - default + * is 16. + * + * @param usStackDepth The size of the task stack specified as the number of + * variables the stack can hold - not the number of bytes. For example, if + * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes + * will be allocated for stack storage. + * + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * + * @param uxPriority The priority at which the task should run. Systems that + * include MPU support can optionally create tasks in a privileged (system) + * mode by setting bit portPRIVILEGE_BIT of the priority parameter. For + * example, to create a privileged task at priority 2 the uxPriority parameter + * should be set to ( 2 | portPRIVILEGE_BIT ). + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * @code{c} + * // Task to be created. + * void vTaskCode( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * } + * } + * + * // Function that creates a task. + * void vOtherFunction( void ) + * { + * static uint8_t ucParameterToPass; + * TaskHandle_t xHandle = NULL; + * + * // Create the task, storing the handle. Note that the passed parameter ucParameterToPass + * // must exist for the lifetime of the task, so in this case is declared static. If it was just an + * // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time + * // the new task attempts to access it. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle ); + * configASSERT( xHandle ); + * + * // Use the handle to delete the task. + * if( xHandle != NULL ) + * { + * vTaskDelete( xHandle ); + * } + * } + * @endcode + * \defgroup xTaskCreate xTaskCreate + * \ingroup Tasks + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + * const char *pcName, + * uint32_t ulStackDepth, + * void *pvParameters, + * UBaseType_t uxPriority, + * StackType_t *puxStackBuffer, + * StaticTask_t *pxTaskBuffer ); + * @endcode + * + * Create a new task and add it to the list of tasks that are ready to run. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreate() then both blocks of memory are automatically dynamically + * allocated inside the xTaskCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a task is created using + * xTaskCreateStatic() then the application writer must provide the required + * memory. xTaskCreateStatic() therefore allows a task to be created without + * using any dynamic memory allocation. + * + * @param pxTaskCode Pointer to the task entry function. Tasks + * must be implemented to never return (i.e. continuous loop). + * + * @param pcName A descriptive name for the task. This is mainly used to + * facilitate debugging. The maximum length of the string is defined by + * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h. + * + * @param ulStackDepth The size of the task stack specified as the number of + * variables the stack can hold - not the number of bytes. For example, if + * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes + * will be allocated for stack storage. + * + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * + * @param uxPriority The priority at which the task will run. + * + * @param puxStackBuffer Must point to a StackType_t array that has at least + * ulStackDepth indexes - the array will then be used as the task's stack, + * removing the need for the stack to be allocated dynamically. + * + * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will + * then be used to hold the task's data structures, removing the need for the + * memory to be allocated dynamically. + * + * @return If neither puxStackBuffer nor pxTaskBuffer are NULL, then the task + * will be created and a handle to the created task is returned. If either + * puxStackBuffer or pxTaskBuffer are NULL then the task will not be created and + * NULL is returned. + * + * Example usage: + * @code{c} + * + * // Dimensions of the buffer that the task being created will use as its stack. + * // NOTE: This is the number of words the stack will hold, not the number of + * // bytes. For example, if each stack item is 32-bits, and this is set to 100, + * // then 400 bytes (100 * 32-bits) will be allocated. + #define STACK_SIZE 200 + * + * // Structure that will hold the TCB of the task being created. + * StaticTask_t xTaskBuffer; + * + * // Buffer that the task being created will use as its stack. Note this is + * // an array of StackType_t variables. The size of StackType_t is dependent on + * // the RTOS port. + * StackType_t xStack[ STACK_SIZE ]; + * + * // Function that implements the task being created. + * void vTaskCode( void * pvParameters ) + * { + * // The parameter value is expected to be 1 as 1 is passed in the + * // pvParameters value in the call to xTaskCreateStatic(). + * configASSERT( ( uint32_t ) pvParameters == 1UL ); + * + * for( ;; ) + * { + * // Task code goes here. + * } + * } + * + * // Function that creates a task. + * void vOtherFunction( void ) + * { + * TaskHandle_t xHandle = NULL; + * + * // Create the task without using any dynamic memory allocation. + * xHandle = xTaskCreateStatic( + * vTaskCode, // Function that implements the task. + * "NAME", // Text name for the task. + * STACK_SIZE, // Stack size in words, not bytes. + * ( void * ) 1, // Parameter passed into the task. + * tskIDLE_PRIORITY,// Priority at which the task is created. + * xStack, // Array to use as the task's stack. + * &xTaskBuffer ); // Variable to hold the task's data structure. + * + * // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have + * // been created, and xHandle will be the task's handle. Use the handle + * // to suspend the task. + * vTaskSuspend( xHandle ); + * } + * @endcode + * \defgroup xTaskCreateStatic xTaskCreateStatic + * \ingroup Tasks + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * task. h + * @code{c} + * BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask ); + * @endcode + * + * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1. + * + * xTaskCreateRestricted() should only be used in systems that include an MPU + * implementation. + * + * Create a new task and add it to the list of tasks that are ready to run. + * The function parameters define the memory regions and associated access + * permissions allocated to the task. + * + * See xTaskCreateRestrictedStatic() for a version that does not use any + * dynamic memory allocation. + * + * @param pxTaskDefinition Pointer to a structure that contains a member + * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API + * documentation) plus an optional stack buffer and the memory region + * definitions. + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * @code{c} + * // Create an TaskParameters_t structure that defines the task to be created. + * static const TaskParameters_t xCheckTaskParameters = + * { + * vATask, // pvTaskCode - the function that implements the task. + * "ATask", // pcName - just a text name for the task to assist debugging. + * 100, // usStackDepth - the stack size DEFINED IN WORDS. + * NULL, // pvParameters - passed into the task function as the function parameters. + * ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state. + * cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack. + * + * // xRegions - Allocate up to three separate memory regions for access by + * // the task, with appropriate access permissions. Different processors have + * // different memory alignment requirements - refer to the FreeRTOS documentation + * // for full information. + * { + * // Base address Length Parameters + * { cReadWriteArray, 32, portMPU_REGION_READ_WRITE }, + * { cReadOnlyArray, 32, portMPU_REGION_READ_ONLY }, + * { cPrivilegedOnlyAccessArray, 128, portMPU_REGION_PRIVILEGED_READ_WRITE } + * } + * }; + * + * int main( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task from the const structure defined above. The task handle + * // is requested (the second parameter is not NULL) but in this case just for + * // demonstration purposes as its not actually used. + * xTaskCreateRestricted( &xRegTest1Parameters, &xHandle ); + * + * // Start the scheduler. + * vTaskStartScheduler(); + * + * // Will only get here if there was insufficient memory to create the idle + * // and/or timer task. + * for( ;; ); + * } + * @endcode + * \defgroup xTaskCreateRestricted xTaskCreateRestricted + * \ingroup Tasks + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask ); + * @endcode + * + * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1. + * + * xTaskCreateRestrictedStatic() should only be used in systems that include an + * MPU implementation. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreateRestricted() then the stack is provided by the application writer, + * and the memory used to hold the task's data structure is automatically + * dynamically allocated inside the xTaskCreateRestricted() function. If a task + * is created using xTaskCreateRestrictedStatic() then the application writer + * must provide the memory used to hold the task's data structures too. + * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be + * created without using any dynamic memory allocation. + * + * @param pxTaskDefinition Pointer to a structure that contains a member + * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API + * documentation) plus an optional stack buffer and the memory region + * definitions. If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure + * contains an additional member, which is used to point to a variable of type + * StaticTask_t - which is then used to hold the task's data structure. + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * @code{c} + * // Create an TaskParameters_t structure that defines the task to be created. + * // The StaticTask_t variable is only included in the structure when + * // configSUPPORT_STATIC_ALLOCATION is set to 1. The PRIVILEGED_DATA macro can + * // be used to force the variable into the RTOS kernel's privileged data area. + * static PRIVILEGED_DATA StaticTask_t xTaskBuffer; + * static const TaskParameters_t xCheckTaskParameters = + * { + * vATask, // pvTaskCode - the function that implements the task. + * "ATask", // pcName - just a text name for the task to assist debugging. + * 100, // usStackDepth - the stack size DEFINED IN WORDS. + * NULL, // pvParameters - passed into the task function as the function parameters. + * ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state. + * cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack. + * + * // xRegions - Allocate up to three separate memory regions for access by + * // the task, with appropriate access permissions. Different processors have + * // different memory alignment requirements - refer to the FreeRTOS documentation + * // for full information. + * { + * // Base address Length Parameters + * { cReadWriteArray, 32, portMPU_REGION_READ_WRITE }, + * { cReadOnlyArray, 32, portMPU_REGION_READ_ONLY }, + * { cPrivilegedOnlyAccessArray, 128, portMPU_REGION_PRIVILEGED_READ_WRITE } + * } + * + * &xTaskBuffer; // Holds the task's data structure. + * }; + * + * int main( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task from the const structure defined above. The task handle + * // is requested (the second parameter is not NULL) but in this case just for + * // demonstration purposes as its not actually used. + * xTaskCreateRestrictedStatic( &xRegTest1Parameters, &xHandle ); + * + * // Start the scheduler. + * vTaskStartScheduler(); + * + * // Will only get here if there was insufficient memory to create the idle + * // and/or timer task. + * for( ;; ); + * } + * @endcode + * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic + * \ingroup Tasks + */ +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ); + * @endcode + * + * Memory regions are assigned to a restricted task when the task is created by + * a call to xTaskCreateRestricted(). These regions can be redefined using + * vTaskAllocateMPURegions(). + * + * @param xTask The handle of the task being updated. + * + * @param xRegions A pointer to a MemoryRegion_t structure that contains the + * new memory region definitions. + * + * Example usage: + * @code{c} + * // Define an array of MemoryRegion_t structures that configures an MPU region + * // allowing read/write access for 1024 bytes starting at the beginning of the + * // ucOneKByte array. The other two of the maximum 3 definable regions are + * // unused so set to zero. + * static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] = + * { + * // Base address Length Parameters + * { ucOneKByte, 1024, portMPU_REGION_READ_WRITE }, + * { 0, 0, 0 }, + * { 0, 0, 0 } + * }; + * + * void vATask( void *pvParameters ) + * { + * // This task was created such that it has access to certain regions of + * // memory as defined by the MPU configuration. At some point it is + * // desired that these MPU regions are replaced with that defined in the + * // xAltRegions const struct above. Use a call to vTaskAllocateMPURegions() + * // for this purpose. NULL is used as the task handle to indicate that this + * // function should modify the MPU regions of the calling task. + * vTaskAllocateMPURegions( NULL, xAltRegions ); + * + * // Now the task can continue its function, but from this point on can only + * // access its stack and the ucOneKByte array (unless any other statically + * // defined or shared regions have been declared elsewhere). + * } + * @endcode + * \defgroup vTaskAllocateMPURegions vTaskAllocateMPURegions + * \ingroup Tasks + */ +void vTaskAllocateMPURegions( TaskHandle_t xTask, + const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskDelete( TaskHandle_t xTaskToDelete ); + * @endcode + * + * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Remove a task from the RTOS real time kernel's management. The task being + * deleted will be removed from all ready, blocked, suspended and event lists. + * + * NOTE: The idle task is responsible for freeing the kernel allocated + * memory from tasks that have been deleted. It is therefore important that + * the idle task is not starved of microcontroller processing time if your + * application makes any calls to vTaskDelete (). Memory allocated by the + * task code is not automatically freed, and should be freed before the task + * is deleted. + * + * See the demo application file death.c for sample code that utilises + * vTaskDelete (). + * + * @param xTaskToDelete The handle of the task to be deleted. Passing NULL will + * cause the calling task to be deleted. + * + * Example usage: + * @code{c} + * void vOtherFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create the task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // Use the handle to delete the task. + * vTaskDelete( xHandle ); + * } + * @endcode + * \defgroup vTaskDelete vTaskDelete + * \ingroup Tasks + */ +void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* TASK CONTROL API +*----------------------------------------------------------*/ + +/** + * task. h + * @code{c} + * void vTaskDelay( const TickType_t xTicksToDelay ); + * @endcode + * + * Delay a task for a given number of ticks. The actual time that the + * task remains blocked depends on the tick rate. The constant + * portTICK_PERIOD_MS can be used to calculate real time from the tick + * rate - with the resolution of one tick period. + * + * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * + * vTaskDelay() specifies a time at which the task wishes to unblock relative to + * the time at which vTaskDelay() is called. For example, specifying a block + * period of 100 ticks will cause the task to unblock 100 ticks after + * vTaskDelay() is called. vTaskDelay() does not therefore provide a good method + * of controlling the frequency of a periodic task as the path taken through the + * code, as well as other task and interrupt activity, will affect the frequency + * at which vTaskDelay() gets called and therefore the time at which the task + * next executes. See xTaskDelayUntil() for an alternative API function designed + * to facilitate fixed frequency execution. It does this by specifying an + * absolute time (rather than a relative time) at which the calling task should + * unblock. + * + * @param xTicksToDelay The amount of time, in tick periods, that + * the calling task should block. + * + * Example usage: + * + * void vTaskFunction( void * pvParameters ) + * { + * // Block for 500ms. + * const TickType_t xDelay = 500 / portTICK_PERIOD_MS; + * + * for( ;; ) + * { + * // Simply toggle the LED every 500ms, blocking between each toggle. + * vToggleLED(); + * vTaskDelay( xDelay ); + * } + * } + * + * \defgroup vTaskDelay vTaskDelay + * \ingroup TaskCtrl + */ +void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * BaseType_t xTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement ); + * @endcode + * + * INCLUDE_xTaskDelayUntil must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Delay a task until a specified time. This function can be used by periodic + * tasks to ensure a constant execution frequency. + * + * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will + * cause a task to block for the specified number of ticks from the time vTaskDelay () is + * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed + * execution frequency as the time between a task starting to execute and that task + * calling vTaskDelay () may not be fixed [the task may take a different path though the + * code between calls, or may get interrupted or preempted a different number of times + * each time it executes]. + * + * Whereas vTaskDelay () specifies a wake time relative to the time at which the function + * is called, xTaskDelayUntil () specifies the absolute (exact) time at which it wishes to + * unblock. + * + * The macro pdMS_TO_TICKS() can be used to calculate the number of ticks from a + * time specified in milliseconds with a resolution of one tick period. + * + * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the + * task was last unblocked. The variable must be initialised with the current time + * prior to its first use (see the example below). Following this the variable is + * automatically updated within xTaskDelayUntil (). + * + * @param xTimeIncrement The cycle time period. The task will be unblocked at + * time *pxPreviousWakeTime + xTimeIncrement. Calling xTaskDelayUntil with the + * same xTimeIncrement parameter value will cause the task to execute with + * a fixed interface period. + * + * @return Value which can be used to check whether the task was actually delayed. + * Will be pdTRUE if the task way delayed and pdFALSE otherwise. A task will not + * be delayed if the next expected wake time is in the past. + * + * Example usage: + * @code{c} + * // Perform an action every 10 ticks. + * void vTaskFunction( void * pvParameters ) + * { + * TickType_t xLastWakeTime; + * const TickType_t xFrequency = 10; + * BaseType_t xWasDelayed; + * + * // Initialise the xLastWakeTime variable with the current time. + * xLastWakeTime = xTaskGetTickCount (); + * for( ;; ) + * { + * // Wait for the next cycle. + * xWasDelayed = xTaskDelayUntil( &xLastWakeTime, xFrequency ); + * + * // Perform action here. xWasDelayed value can be used to determine + * // whether a deadline was missed if the code here took too long. + * } + * } + * @endcode + * \defgroup xTaskDelayUntil xTaskDelayUntil + * \ingroup TaskCtrl + */ +BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION; + +/* + * vTaskDelayUntil() is the older version of xTaskDelayUntil() and does not + * return a value. + */ +#define vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ) \ + do { \ + ( void ) xTaskDelayUntil( ( pxPreviousWakeTime ), ( xTimeIncrement ) ); \ + } while( 0 ) + + +/** + * task. h + * @code{c} + * BaseType_t xTaskAbortDelay( TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this + * function to be available. + * + * A task will enter the Blocked state when it is waiting for an event. The + * event it is waiting for can be a temporal event (waiting for a time), such + * as when vTaskDelay() is called, or an event on an object, such as when + * xQueueReceive() or ulTaskNotifyTake() is called. If the handle of a task + * that is in the Blocked state is used in a call to xTaskAbortDelay() then the + * task will leave the Blocked state, and return from whichever function call + * placed the task into the Blocked state. + * + * There is no 'FromISR' version of this function as an interrupt would need to + * know which object a task was blocked on in order to know which actions to + * take. For example, if the task was blocked on a queue the interrupt handler + * would then need to know if the queue was locked. + * + * @param xTask The handle of the task to remove from the Blocked state. + * + * @return If the task referenced by xTask was not in the Blocked state then + * pdFAIL is returned. Otherwise pdPASS is returned. + * + * \defgroup xTaskAbortDelay xTaskAbortDelay + * \ingroup TaskCtrl + */ +BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the priority of any task. + * + * @param xTask Handle of the task to be queried. Passing a NULL + * handle results in the priority of the calling task being returned. + * + * @return The priority of xTask. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to obtain the priority of the created task. + * // It was created with tskIDLE_PRIORITY, but may have changed + * // it itself. + * if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY ) + * { + * // The task has changed it's priority. + * } + * + * // ... + * + * // Is our priority higher than the created task? + * if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) ) + * { + * // Our priority (obtained using NULL handle) is higher. + * } + * } + * @endcode + * \defgroup uxTaskPriorityGet uxTaskPriorityGet + * \ingroup TaskCtrl + */ +UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ); + * @endcode + * + * A version of uxTaskPriorityGet() that can be used from an ISR. + */ +UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * eTaskState eTaskGetState( TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_eTaskGetState must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the state of any task. States are encoded by the eTaskState + * enumerated type. + * + * @param xTask Handle of the task to be queried. + * + * @return The state of xTask at the time the function was called. Note the + * state of the task might change between the function being called, and the + * functions return value being tested by the calling task. + */ +eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ); + * @endcode + * + * configUSE_TRACE_FACILITY must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * Populates a TaskStatus_t structure with information about a task. + * + * @param xTask Handle of the task being queried. If xTask is NULL then + * information will be returned about the calling task. + * + * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be + * filled with information about the task referenced by the handle passed using + * the xTask parameter. + * + * @param xGetFreeStackSpace The TaskStatus_t structure contains a member to report + * the stack high water mark of the task being queried. Calculating the stack + * high water mark takes a relatively long time, and can make the system + * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to + * allow the high water mark checking to be skipped. The high watermark value + * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is + * not set to pdFALSE; + * + * @param eState The TaskStatus_t structure contains a member to report the + * state of the task being queried. Obtaining the task state is not as fast as + * a simple assignment - so the eState parameter is provided to allow the state + * information to be omitted from the TaskStatus_t structure. To obtain state + * information then set eState to eInvalid - otherwise the value passed in + * eState will be reported as the task state in the TaskStatus_t structure. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * TaskStatus_t xTaskDetails; + * + * // Obtain the handle of a task from its name. + * xHandle = xTaskGetHandle( "Task_Name" ); + * + * // Check the handle is not NULL. + * configASSERT( xHandle ); + * + * // Use the handle to obtain further information about the task. + * vTaskGetInfo( xHandle, + * &xTaskDetails, + * pdTRUE, // Include the high water mark in xTaskDetails. + * eInvalid ); // Include the task state in xTaskDetails. + * } + * @endcode + * \defgroup vTaskGetInfo vTaskGetInfo + * \ingroup TaskCtrl + */ +void vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ); + * @endcode + * + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Set the priority of any task. + * + * A context switch will occur before the function returns if the priority + * being set is higher than the currently executing task. + * + * @param xTask Handle to the task for which the priority is being set. + * Passing a NULL handle results in the priority of the calling task being set. + * + * @param uxNewPriority The priority to which the task will be set. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to raise the priority of the created task. + * vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 ); + * + * // ... + * + * // Use a NULL handle to raise our priority to the same value. + * vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 ); + * } + * @endcode + * \defgroup vTaskPrioritySet vTaskPrioritySet + * \ingroup TaskCtrl + */ +void vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskSuspend( TaskHandle_t xTaskToSuspend ); + * @endcode + * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Suspend any task. When suspended a task will never get any microcontroller + * processing time, no matter what its priority. + * + * Calls to vTaskSuspend are not accumulative - + * i.e. calling vTaskSuspend () twice on the same task still only requires one + * call to vTaskResume () to ready the suspended task. + * + * @param xTaskToSuspend Handle to the task being suspended. Passing a NULL + * handle will cause the calling task to be suspended. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to suspend the created task. + * vTaskSuspend( xHandle ); + * + * // ... + * + * // The created task will not run during this period, unless + * // another task calls vTaskResume( xHandle ). + * + * //... + * + * + * // Suspend ourselves. + * vTaskSuspend( NULL ); + * + * // We cannot get here unless another task calls vTaskResume + * // with our handle as the parameter. + * } + * @endcode + * \defgroup vTaskSuspend vTaskSuspend + * \ingroup TaskCtrl + */ +void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskResume( TaskHandle_t xTaskToResume ); + * @endcode + * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Resumes a suspended task. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * vTaskResume (). + * + * @param xTaskToResume Handle to the task being readied. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to suspend the created task. + * vTaskSuspend( xHandle ); + * + * // ... + * + * // The created task will not run during this period, unless + * // another task calls vTaskResume( xHandle ). + * + * //... + * + * + * // Resume the suspended task ourselves. + * vTaskResume( xHandle ); + * + * // The created task will once again get microcontroller processing + * // time in accordance with its priority within the system. + * } + * @endcode + * \defgroup vTaskResume vTaskResume + * \ingroup TaskCtrl + */ +void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void xTaskResumeFromISR( TaskHandle_t xTaskToResume ); + * @endcode + * + * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * An implementation of vTaskResume() that can be called from within an ISR. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * xTaskResumeFromISR (). + * + * xTaskResumeFromISR() should not be used to synchronise a task with an + * interrupt if there is a chance that the interrupt could arrive prior to the + * task being suspended - as this can lead to interrupts being missed. Use of a + * semaphore as a synchronisation mechanism would avoid this eventuality. + * + * @param xTaskToResume Handle to the task being readied. + * + * @return pdTRUE if resuming the task should result in a context switch, + * otherwise pdFALSE. This is used by the ISR to determine if a context switch + * may be required following the ISR. + * + * \defgroup vTaskResumeFromISR vTaskResumeFromISR + * \ingroup TaskCtrl + */ +BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* SCHEDULER CONTROL +*----------------------------------------------------------*/ + +/** + * task. h + * @code{c} + * void vTaskStartScheduler( void ); + * @endcode + * + * Starts the real time kernel tick processing. After calling the kernel + * has control over which tasks are executed and when. + * + * See the demo application file main.c for an example of creating + * tasks and starting the kernel. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * // Create at least one task before starting the kernel. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + * + * // Start the real time kernel with preemption. + * vTaskStartScheduler (); + * + * // Will not get here unless a task calls vTaskEndScheduler () + * } + * @endcode + * + * \defgroup vTaskStartScheduler vTaskStartScheduler + * \ingroup SchedulerControl + */ +void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskEndScheduler( void ); + * @endcode + * + * NOTE: At the time of writing only the x86 real mode port, which runs on a PC + * in place of DOS, implements this function. + * + * Stops the real time kernel tick. All created tasks will be automatically + * deleted and multitasking (either preemptive or cooperative) will + * stop. Execution then resumes from the point where vTaskStartScheduler () + * was called, as if vTaskStartScheduler () had just returned. + * + * See the demo application file main. c in the demo/PC directory for an + * example that uses vTaskEndScheduler (). + * + * vTaskEndScheduler () requires an exit function to be defined within the + * portable layer (see vPortEndScheduler () in port. c for the PC port). This + * performs hardware specific operations such as stopping the kernel tick. + * + * vTaskEndScheduler () will cause all of the resources allocated by the + * kernel to be freed - but will not free resources allocated by application + * tasks. + * + * Example usage: + * @code{c} + * void vTaskCode( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * + * // At some point we want to end the real time kernel processing + * // so call ... + * vTaskEndScheduler (); + * } + * } + * + * void vAFunction( void ) + * { + * // Create at least one task before starting the kernel. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + * + * // Start the real time kernel with preemption. + * vTaskStartScheduler (); + * + * // Will only get here when the vTaskCode () task has called + * // vTaskEndScheduler (). When we get here we are back to single task + * // execution. + * } + * @endcode + * + * \defgroup vTaskEndScheduler vTaskEndScheduler + * \ingroup SchedulerControl + */ +void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskSuspendAll( void ); + * @endcode + * + * Suspends the scheduler without disabling interrupts. Context switches will + * not occur while the scheduler is suspended. + * + * After calling vTaskSuspendAll () the calling task will continue to execute + * without risk of being swapped out until a call to xTaskResumeAll () has been + * made. + * + * API functions that have the potential to cause a context switch (for example, + * xTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler + * is suspended. + * + * Example usage: + * @code{c} + * void vTask1( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * + * // ... + * + * // At some point the task wants to perform a long operation during + * // which it does not want to get swapped out. It cannot use + * // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the + * // operation may cause interrupts to be missed - including the + * // ticks. + * + * // Prevent the real time kernel swapping out the task. + * vTaskSuspendAll (); + * + * // Perform the operation here. There is no need to use critical + * // sections as we have all the microcontroller processing time. + * // During this time interrupts will still operate and the kernel + * // tick count will be maintained. + * + * // ... + * + * // The operation is complete. Restart the kernel. + * xTaskResumeAll (); + * } + * } + * @endcode + * \defgroup vTaskSuspendAll vTaskSuspendAll + * \ingroup SchedulerControl + */ +void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * BaseType_t xTaskResumeAll( void ); + * @endcode + * + * Resumes scheduler activity after it was suspended by a call to + * vTaskSuspendAll(). + * + * xTaskResumeAll() only resumes the scheduler. It does not unsuspend tasks + * that were previously suspended by a call to vTaskSuspend(). + * + * @return If resuming the scheduler caused a context switch then pdTRUE is + * returned, otherwise pdFALSE is returned. + * + * Example usage: + * @code{c} + * void vTask1( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * + * // ... + * + * // At some point the task wants to perform a long operation during + * // which it does not want to get swapped out. It cannot use + * // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the + * // operation may cause interrupts to be missed - including the + * // ticks. + * + * // Prevent the real time kernel swapping out the task. + * vTaskSuspendAll (); + * + * // Perform the operation here. There is no need to use critical + * // sections as we have all the microcontroller processing time. + * // During this time interrupts will still operate and the real + * // time kernel tick count will be maintained. + * + * // ... + * + * // The operation is complete. Restart the kernel. We want to force + * // a context switch - but there is no point if resuming the scheduler + * // caused a context switch already. + * if( !xTaskResumeAll () ) + * { + * taskYIELD (); + * } + * } + * } + * @endcode + * \defgroup xTaskResumeAll xTaskResumeAll + * \ingroup SchedulerControl + */ +BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* TASK UTILITIES +*----------------------------------------------------------*/ + +/** + * task. h + * @code{c} + * TickType_t xTaskGetTickCount( void ); + * @endcode + * + * @return The count of ticks since vTaskStartScheduler was called. + * + * \defgroup xTaskGetTickCount xTaskGetTickCount + * \ingroup TaskUtils + */ +TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * TickType_t xTaskGetTickCountFromISR( void ); + * @endcode + * + * @return The count of ticks since vTaskStartScheduler was called. + * + * This is a version of xTaskGetTickCount() that is safe to be called from an + * ISR - provided that TickType_t is the natural word size of the + * microcontroller being used or interrupt nesting is either not supported or + * not being used. + * + * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR + * \ingroup TaskUtils + */ +TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * uint16_t uxTaskGetNumberOfTasks( void ); + * @endcode + * + * @return The number of tasks that the real time kernel is currently managing. + * This includes all ready, blocked and suspended tasks. A task that + * has been deleted but not yet freed by the idle task will also be + * included in the count. + * + * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks + * \ingroup TaskUtils + */ +UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * char *pcTaskGetName( TaskHandle_t xTaskToQuery ); + * @endcode + * + * @return The text (human readable) name of the task referenced by the handle + * xTaskToQuery. A task can query its own name by either passing in its own + * handle, or by setting xTaskToQuery to NULL. + * + * \defgroup pcTaskGetName pcTaskGetName + * \ingroup TaskUtils + */ +char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * @code{c} + * TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ); + * @endcode + * + * NOTE: This function takes a relatively long time to complete and should be + * used sparingly. + * + * @return The handle of the task that has the human readable name pcNameToQuery. + * NULL is returned if no matching name is found. INCLUDE_xTaskGetHandle + * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available. + * + * \defgroup pcTaskGetHandle pcTaskGetHandle + * \ingroup TaskUtils + */ +TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task.h + * @code{c} + * UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task.h + * 

uint8_t* pxTaskGetStackStart( TaskHandle_t xTask);
+ * + * INCLUDE_pxTaskGetStackStart must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the start of the stack associated with xTask. That is, + * the highest stack memory address on architectures where the stack grows down + * from high memory, and the lowest memory address on architectures where the + * stack grows up from low memory. + * + * @param xTask Handle of the task associated with the stack returned. + * Set xTask to NULL to return the stack of the calling task. + * + * @return A pointer to the start of the stack. + */ +uint8_t* pxTaskGetStackStart( TaskHandle_t xTask) PRIVILEGED_FUNCTION; + +/* When using trace macros it is sometimes necessary to include task.h before + * FreeRTOS.h. When this is done TaskHookFunction_t will not yet have been defined, + * so the following two prototypes will cause a compilation error. This can be + * fixed by simply guarding against the inclusion of these two prototypes unless + * they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration + * constant. */ +#ifdef configUSE_APPLICATION_TASK_TAG + #if configUSE_APPLICATION_TASK_TAG == 1 + +/** + * task.h + * @code{c} + * void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ); + * @endcode + * + * Sets pxHookFunction to be the task hook function used by the task xTask. + * Passing xTask as NULL has the effect of setting the calling tasks hook + * function. + */ + void vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * void xTaskGetApplicationTaskTag( TaskHandle_t xTask ); + * @endcode + * + * Returns the pxHookFunction value assigned to the task xTask. Do not + * call from an interrupt service routine - call + * xTaskGetApplicationTaskTagFromISR() instead. + */ + TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ); + * @endcode + * + * Returns the pxHookFunction value assigned to the task xTask. Can + * be called from an interrupt service routine. + */ + TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + #endif /* configUSE_APPLICATION_TASK_TAG ==1 */ +#endif /* ifdef configUSE_APPLICATION_TASK_TAG */ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + +/* Each task contains an array of pointers that is dimensioned by the + * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. The + * kernel does not use the pointers itself, so the application writer can use + * the pointers for any purpose they wish. The following two functions are + * used to set and query a pointer respectively. */ + void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) PRIVILEGED_FUNCTION; + void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) PRIVILEGED_FUNCTION; + +#endif + +#if ( configCHECK_FOR_STACK_OVERFLOW > 0 ) + +/** + * task.h + * @code{c} + * void vApplicationStackOverflowHook( TaskHandle_t xTask char *pcTaskName); + * @endcode + * + * The application stack overflow hook is called when a stack overflow is detected for a task. + * + * Details on stack overflow detection can be found here: https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html + * + * @param xTask the task that just exceeded its stack boundaries. + * @param pcTaskName A character string containing the name of the offending task. + */ + void vApplicationStackOverflowHook( TaskHandle_t xTask, + signed char * pcTaskName ); + +#endif + +#if ( configUSE_TICK_HOOK > 0 ) + +/** + * task.h + * @code{c} + * void vApplicationTickHook( void ); + * @endcode + * + * This hook function is called in the system tick handler after any OS work is completed. + */ + void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */ + +#endif + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + +/** + * task.h + * @code{c} + * void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * @endcode + * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Task TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task + * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + */ + void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */ +#endif + +/** + * task.h + * @code{c} + * BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ); + * @endcode + * + * Calls the hook function associated with xTask. Passing xTask as NULL has + * the effect of calling the Running tasks (the calling task) hook function. + * + * pvParameter is passed to the hook function for the task to interpret as it + * wants. The return value is the value returned by the task hook function + * registered by the user. + */ +BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) PRIVILEGED_FUNCTION; + +/** + * xTaskGetIdleTaskHandle() is only available if + * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h. + * + * Simply returns the handle of the idle task. It is not valid to call + * xTaskGetIdleTaskHandle() before the scheduler has been started. + */ +TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION; + +/** + * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for + * uxTaskGetSystemState() to be available. + * + * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in + * the system. TaskStatus_t structures contain, among other things, members + * for the task handle, task name, task priority, task state, and total amount + * of run time consumed by the task. See the TaskStatus_t structure + * definition in this file for the full member list. + * + * NOTE: This function is intended for debugging use only as its use results in + * the scheduler remaining suspended for an extended period. + * + * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures. + * The array must contain at least one TaskStatus_t structure for each task + * that is under the control of the RTOS. The number of tasks under the control + * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function. + * + * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray + * parameter. The size is specified as the number of indexes in the array, or + * the number of TaskStatus_t structures contained in the array, not by the + * number of bytes in the array. + * + * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in + * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the + * total run time (as defined by the run time stats clock, see + * https://www.FreeRTOS.org/rtos-run-time-stats.html) since the target booted. + * pulTotalRunTime can be set to NULL to omit the total run time information. + * + * @return The number of TaskStatus_t structures that were populated by + * uxTaskGetSystemState(). This should equal the number returned by the + * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed + * in the uxArraySize parameter was too small. + * + * Example usage: + * @code{c} + * // This example demonstrates how a human readable table of run time stats + * // information is generated from raw data provided by uxTaskGetSystemState(). + * // The human readable table is written to pcWriteBuffer + * void vTaskGetRunTimeStats( char *pcWriteBuffer ) + * { + * TaskStatus_t *pxTaskStatusArray; + * volatile UBaseType_t uxArraySize, x; + * configRUN_TIME_COUNTER_TYPE ulTotalRunTime, ulStatsAsPercentage; + * + * // Make sure the write buffer does not contain a string. + * pcWriteBuffer = 0x00; + * + * // Take a snapshot of the number of tasks in case it changes while this + * // function is executing. + * uxArraySize = uxTaskGetNumberOfTasks(); + * + * // Allocate a TaskStatus_t structure for each task. An array could be + * // allocated statically at compile time. + * pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) ); + * + * if( pxTaskStatusArray != NULL ) + * { + * // Generate raw status information about each task. + * uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime ); + * + * // For percentage calculations. + * ulTotalRunTime /= 100UL; + * + * // Avoid divide by zero errors. + * if( ulTotalRunTime > 0 ) + * { + * // For each populated position in the pxTaskStatusArray array, + * // format the raw data as human readable ASCII data + * for( x = 0; x < uxArraySize; x++ ) + * { + * // What percentage of the total run time has the task used? + * // This will always be rounded down to the nearest integer. + * // ulTotalRunTimeDiv100 has already been divided by 100. + * ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime; + * + * if( ulStatsAsPercentage > 0UL ) + * { + * sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage ); + * } + * else + * { + * // If the percentage is zero here then the task has + * // consumed less than 1% of the total run time. + * sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter ); + * } + * + * pcWriteBuffer += strlen( ( char * ) pcWriteBuffer ); + * } + * } + * + * // The array is no longer needed, free the memory it consumes. + * vPortFree( pxTaskStatusArray ); + * } + * } + * @endcode + */ +UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskList( char *pcWriteBuffer ); + * @endcode + * + * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must + * both be defined as 1 for this function to be available. See the + * configuration section of the FreeRTOS.org website for more information. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Lists all the current tasks, along with their current state and stack + * usage high water mark. + * + * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or + * suspended ('S'). + * + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskList() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays task: + * names, states, priority, stack usage and task number. + * Stack usage specified as the number of unused StackType_t words stack can hold + * on top of stack - not the number of bytes. + * + * vTaskList() has a dependency on the sprintf() C library function that might + * bloat the code size, use a lot of stack, and provide different results on + * different platforms. An alternative, tiny, third party, and limited + * functionality implementation of sprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly through a + * call to vTaskList(). + * + * @param pcWriteBuffer A buffer into which the above mentioned details + * will be written, in ASCII form. This buffer is assumed to be large + * enough to contain the generated report. Approximately 40 bytes per + * task should be sufficient. + * + * \defgroup vTaskList vTaskList + * \ingroup TaskUtils + */ +void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * @code{c} + * void vTaskGetRunTimeStats( char *pcWriteBuffer ); + * @endcode + * + * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS + * must both be defined as 1 for this function to be available. The application + * must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * Calling vTaskGetRunTimeStats() writes the total execution time of each + * task into a buffer, both as an absolute count value and as a percentage + * of the total system execution time. + * + * NOTE 2: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays the + * amount of time each task has spent in the Running state in both absolute and + * percentage terms. + * + * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function + * that might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, and + * limited functionality implementation of sprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() directly + * to get access to raw stats data, rather than indirectly through a call to + * vTaskGetRunTimeStats(). + * + * @param pcWriteBuffer A buffer into which the execution times will be + * written, in ASCII form. This buffer is assumed to be large enough to + * contain the generated report. Approximately 40 bytes per task should + * be sufficient. + * + * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats + * \ingroup TaskUtils + */ +void vTaskGetRunTimeStats( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * @code{c} + * configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ); + * configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ); + * @endcode + * + * configGENERATE_RUN_TIME_STATS, configUSE_STATS_FORMATTING_FUNCTIONS and + * INCLUDE_xTaskGetIdleTaskHandle must all be defined as 1 for these functions + * to be available. The application must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total + * execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter() + * returns the total execution time of just the idle task and + * ulTaskGetIdleRunTimePercent() returns the percentage of the CPU time used by + * just the idle task. + * + * Note the amount of idle time is only a good measure of the slack time in a + * system if there are no other tasks executing at the idle priority, tickless + * idle is not used, and configIDLE_SHOULD_YIELD is set to 0. + * + * @return The total run time of the idle task or the percentage of the total + * run time consumed by the idle task. This is the amount of time the + * idle task has actually been executing. The unit of time is dependent on the + * frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and + * portGET_RUN_TIME_COUNTER_VALUE() macros. + * + * \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + * \ingroup TaskUtils + */ +configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION; +configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction ); + * BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Sends a direct to task notification to a task, with an optional value and + * action. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A task can use xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() to + * [optionally] block to wait for a notification to be pending. The task does + * not consume any CPU time while it is in the Blocked state. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotify() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotify() is equivalent to calling xTaskNotifyIndexed() + * with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotify() does + * not have this parameter and always sends notifications to index 0. + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The target notification value is bitwise ORed with ulValue. + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eIncrement - + * The target notification value is incremented. ulValue is not used and + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The target notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification at the + * same array index (the task already had a notification pending at that index). + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending at the + * same array index then the target notification value is set to ulValue and + * xTaskNotifyIndexed() will return pdPASS. If the task being notified already + * had a notification pending at the same array index then no action is + * performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification at the specified array index without the + * notification value at that index being updated. ulValue is not used and + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * pulPreviousNotificationValue - + * Can be used to pass out the subject task's notification value before any + * bits are modified by the notify function. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \defgroup xTaskNotifyIndexed xTaskNotifyIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) PRIVILEGED_FUNCTION; +#define xTaskNotify( xTaskToNotify, ulValue, eAction ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL ) +#define xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyAndQueryIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue ); + * BaseType_t xTaskNotifyAndQuery( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * xTaskNotifyAndQueryIndexed() performs the same operation as + * xTaskNotifyIndexed() with the addition that it also returns the subject + * task's prior notification value (the notification value at the time the + * function is called rather than when the function returns) in the additional + * pulPreviousNotifyValue parameter. + * + * xTaskNotifyAndQuery() performs the same operation as xTaskNotify() with the + * addition that it also returns the subject task's prior notification value + * (the notification value as it was at the time the function is called, rather + * than when the function returns) in the additional pulPreviousNotifyValue + * parameter. + * + * \defgroup xTaskNotifyAndQueryIndexed xTaskNotifyAndQueryIndexed + * \ingroup TaskNotifications + */ +#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) ) +#define xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotifyValue ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken ); + * BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * A version of xTaskNotifyIndexed() that can be used from an interrupt service + * routine (ISR). + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyFromISR() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyFromISR() is equivalent to calling + * xTaskNotifyIndexedFromISR() with the uxIndexToNotify parameter set to 0. + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyFromISR() + * does not have this parameter and always sends notifications to index 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The task's notification value is bitwise ORed with ulValue. xTaskNotify() + * always returns pdPASS in this case. + * + * eIncrement - + * The task's notification value is incremented. ulValue is not used and + * xTaskNotify() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The task's notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification (the + * task already had a notification pending). xTaskNotify() always returns + * pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending then + * the task's notification value is set to ulValue and xTaskNotify() will + * return pdPASS. If the task being notified already had a notification + * pending then no action is performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification without its notification value being + * updated. ulValue is not used and xTaskNotify() always returns pdPASS in + * this case. + * + * @param pxHigherPriorityTaskWoken xTaskNotifyFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the + * task to which the notification was sent to leave the Blocked state, and the + * unblocked task has a priority higher than the currently running task. If + * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should + * be requested before the interrupt is exited. How a context switch is + * requested from an ISR is dependent on the port - see the documentation page + * for the port in use. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \defgroup xTaskNotifyIndexedFromISR xTaskNotifyIndexedFromISR + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) ) +#define xTaskNotifyIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyAndQueryIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ); + * BaseType_t xTaskNotifyAndQueryFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * xTaskNotifyAndQueryIndexedFromISR() performs the same operation as + * xTaskNotifyIndexedFromISR() with the addition that it also returns the + * subject task's prior notification value (the notification value at the time + * the function is called rather than at the time the function returns) in the + * additional pulPreviousNotifyValue parameter. + * + * xTaskNotifyAndQueryFromISR() performs the same operation as + * xTaskNotifyFromISR() with the addition that it also returns the subject + * task's prior notification value (the notification value at the time the + * function is called rather than at the time the function returns) in the + * additional pulPreviousNotifyValue parameter. + * + * \defgroup xTaskNotifyAndQueryIndexedFromISR xTaskNotifyAndQueryIndexedFromISR + * \ingroup TaskNotifications + */ +#define xTaskNotifyAndQueryIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) ) +#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyWaitIndexed( UBaseType_t uxIndexToWaitOn, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ); + * + * BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ); + * @endcode + * + * Waits for a direct to task notification to be pending at a given index within + * an array of direct to task notifications. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyWait() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotifyWait() is equivalent to calling + * xTaskNotifyWaitIndexed() with the uxIndexToWaitOn parameter set to 0. + * + * @param uxIndexToWaitOn The index within the calling task's array of + * notification values on which the calling task will wait for a notification to + * be received. uxIndexToWaitOn must be less than + * configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyWait() does + * not have this parameter and always waits for notifications on index 0. + * + * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value + * will be cleared in the calling task's notification value before the task + * checks to see if any notifications are pending, and optionally blocks if no + * notifications are pending. Setting ulBitsToClearOnEntry to ULONG_MAX (if + * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have + * the effect of resetting the task's notification value to 0. Setting + * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged. + * + * @param ulBitsToClearOnExit If a notification is pending or received before + * the calling task exits the xTaskNotifyWait() function then the task's + * notification value (see the xTaskNotify() API function) is passed out using + * the pulNotificationValue parameter. Then any bits that are set in + * ulBitsToClearOnExit will be cleared in the task's notification value (note + * *pulNotificationValue is set before any bits are cleared). Setting + * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL + * (if limits.h is not included) will have the effect of resetting the task's + * notification value to 0 before the function exits. Setting + * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged + * when the function exits (in which case the value passed out in + * pulNotificationValue will match the task's notification value). + * + * @param pulNotificationValue Used to pass the task's notification value out + * of the function. Note the value passed out will not be effected by the + * clearing of any bits caused by ulBitsToClearOnExit being non-zero. + * + * @param xTicksToWait The maximum amount of time that the task should wait in + * the Blocked state for a notification to be received, should a notification + * not already be pending when xTaskNotifyWait() was called. The task + * will not consume any processing time while it is in the Blocked state. This + * is specified in kernel ticks, the macro pdMS_TO_TICKS( value_in_ms ) can be + * used to convert a time specified in milliseconds to a time specified in + * ticks. + * + * @return If a notification was received (including notifications that were + * already pending when xTaskNotifyWait was called) then pdPASS is + * returned. Otherwise pdFAIL is returned. + * + * \defgroup xTaskNotifyWaitIndexed xTaskNotifyWaitIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#define xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \ + xTaskGenericNotifyWait( tskDEFAULT_INDEX_TO_NOTIFY, ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) ) +#define xTaskNotifyWaitIndexed( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \ + xTaskGenericNotifyWait( ( uxIndexToWaitOn ), ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyGiveIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify ); + * BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify ); + * @endcode + * + * Sends a direct to task notification to a particular index in the target + * task's notification array in a manner similar to giving a counting semaphore. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * macros to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * xTaskNotifyGiveIndexed() is a helper macro intended for use when task + * notifications are used as light weight and faster binary or counting + * semaphore equivalents. Actual FreeRTOS semaphores are given using the + * xSemaphoreGive() API function, the equivalent action that instead uses a task + * notification is xTaskNotifyGiveIndexed(). + * + * When task notifications are being used as a binary or counting semaphore + * equivalent then the task being notified should wait for the notification + * using the ulTaskNotifyTakeIndexed() API function rather than the + * xTaskNotifyWaitIndexed() API function. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyGive() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotifyGive() is equivalent to calling + * xTaskNotifyGiveIndexed() with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyGive() + * does not have this parameter and always sends notifications to index 0. + * + * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the + * eAction parameter set to eIncrement - so pdPASS is always returned. + * + * \defgroup xTaskNotifyGiveIndexed xTaskNotifyGiveIndexed + * \ingroup TaskNotifications + */ +#define xTaskNotifyGive( xTaskToNotify ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( 0 ), eIncrement, NULL ) +#define xTaskNotifyGiveIndexed( xTaskToNotify, uxIndexToNotify ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( 0 ), eIncrement, NULL ) + +/** + * task. h + * @code{c} + * void vTaskNotifyGiveIndexedFromISR( TaskHandle_t xTaskHandle, UBaseType_t uxIndexToNotify, BaseType_t *pxHigherPriorityTaskWoken ); + * void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * A version of xTaskNotifyGiveIndexed() that can be called from an interrupt + * service routine (ISR). + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro + * to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * vTaskNotifyGiveIndexedFromISR() is intended for use when task notifications + * are used as light weight and faster binary or counting semaphore equivalents. + * Actual FreeRTOS semaphores are given from an ISR using the + * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses + * a task notification is vTaskNotifyGiveIndexedFromISR(). + * + * When task notifications are being used as a binary or counting semaphore + * equivalent then the task being notified should wait for the notification + * using the ulTaskNotifyTakeIndexed() API function rather than the + * xTaskNotifyWaitIndexed() API function. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyFromISR() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyGiveFromISR() is equivalent to calling + * xTaskNotifyGiveIndexedFromISR() with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * xTaskNotifyGiveFromISR() does not have this parameter and always sends + * notifications to index 0. + * + * @param pxHigherPriorityTaskWoken vTaskNotifyGiveFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the + * task to which the notification was sent to leave the Blocked state, and the + * unblocked task has a priority higher than the currently running task. If + * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch + * should be requested before the interrupt is exited. How a context switch is + * requested from an ISR is dependent on the port - see the documentation page + * for the port in use. + * + * \defgroup vTaskNotifyGiveIndexedFromISR vTaskNotifyGiveIndexedFromISR + * \ingroup TaskNotifications + */ +void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#define vTaskNotifyGiveFromISR( xTaskToNotify, pxHigherPriorityTaskWoken ) \ + vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) ) +#define vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ) \ + vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) ) + +/** + * task. h + * @code{c} + * uint32_t ulTaskNotifyTakeIndexed( UBaseType_t uxIndexToWaitOn, BaseType_t xClearCountOnExit, TickType_t xTicksToWait ); + * + * uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ); + * @endcode + * + * Waits for a direct to task notification on a particular index in the calling + * task's notification array in a manner similar to taking a counting semaphore. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * ulTaskNotifyTakeIndexed() is intended for use when a task notification is + * used as a faster and lighter weight binary or counting semaphore alternative. + * Actual FreeRTOS semaphores are taken using the xSemaphoreTake() API function, + * the equivalent action that instead uses a task notification is + * ulTaskNotifyTakeIndexed(). + * + * When a task is using its notification value as a binary or counting semaphore + * other tasks should send notifications to it using the xTaskNotifyGiveIndexed() + * macro, or xTaskNotifyIndex() function with the eAction parameter set to + * eIncrement. + * + * ulTaskNotifyTakeIndexed() can either clear the task's notification value at + * the array index specified by the uxIndexToWaitOn parameter to zero on exit, + * in which case the notification value acts like a binary semaphore, or + * decrement the notification value on exit, in which case the notification + * value acts like a counting semaphore. + * + * A task can use ulTaskNotifyTakeIndexed() to [optionally] block to wait for + * a notification. The task does not consume any CPU time while it is in the + * Blocked state. + * + * Where as xTaskNotifyWaitIndexed() will return when a notification is pending, + * ulTaskNotifyTakeIndexed() will return when the task's notification value is + * not zero. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. ulTaskNotifyTake() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling ulTaskNotifyTake() is equivalent to calling + * ulTaskNotifyTakeIndexed() with the uxIndexToWaitOn parameter set to 0. + * + * @param uxIndexToWaitOn The index within the calling task's array of + * notification values on which the calling task will wait for a notification to + * be non-zero. uxIndexToWaitOn must be less than + * configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyTake() does + * not have this parameter and always waits for notifications on index 0. + * + * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's + * notification value is decremented when the function exits. In this way the + * notification value acts like a counting semaphore. If xClearCountOnExit is + * not pdFALSE then the task's notification value is cleared to zero when the + * function exits. In this way the notification value acts like a binary + * semaphore. + * + * @param xTicksToWait The maximum amount of time that the task should wait in + * the Blocked state for the task's notification value to be greater than zero, + * should the count not already be greater than zero when + * ulTaskNotifyTake() was called. The task will not consume any processing + * time while it is in the Blocked state. This is specified in kernel ticks, + * the macro pdMS_TO_TICKS( value_in_ms ) can be used to convert a time + * specified in milliseconds to a time specified in ticks. + * + * @return The task's notification count before it is either cleared to zero or + * decremented (see the xClearCountOnExit parameter). + * + * \defgroup ulTaskNotifyTakeIndexed ulTaskNotifyTakeIndexed + * \ingroup TaskNotifications + */ +uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#define ulTaskNotifyTake( xClearCountOnExit, xTicksToWait ) \ + ulTaskGenericNotifyTake( ( tskDEFAULT_INDEX_TO_NOTIFY ), ( xClearCountOnExit ), ( xTicksToWait ) ) +#define ulTaskNotifyTakeIndexed( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ) \ + ulTaskGenericNotifyTake( ( uxIndexToWaitOn ), ( xClearCountOnExit ), ( xTicksToWait ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyStateClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToCLear ); + * + * BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * If a notification is sent to an index within the array of notifications then + * the notification at that index is said to be 'pending' until it is read or + * explicitly cleared by the receiving task. xTaskNotifyStateClearIndexed() + * is the function that clears a pending notification without reading the + * notification value. The notification value at the same array index is not + * altered. Set xTask to NULL to clear the notification state of the calling + * task. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyStateClear() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyStateClear() is equivalent to calling + * xTaskNotifyStateClearIndexed() with the uxIndexToNotify parameter set to 0. + * + * @param xTask The handle of the RTOS task that will have a notification state + * cleared. Set xTask to NULL to clear a notification state in the calling + * task. To obtain a task's handle create the task using xTaskCreate() and + * make use of the pxCreatedTask parameter, or create the task using + * xTaskCreateStatic() and store the returned value, or use the task's name in + * a call to xTaskGetHandle(). + * + * @param uxIndexToClear The index within the target task's array of + * notification values to act upon. For example, setting uxIndexToClear to 1 + * will clear the state of the notification at index 1 within the array. + * uxIndexToClear must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * ulTaskNotifyStateClear() does not have this parameter and always acts on the + * notification at index 0. + * + * @return pdTRUE if the task's notification state was set to + * eNotWaitingNotification, otherwise pdFALSE. + * + * \defgroup xTaskNotifyStateClearIndexed xTaskNotifyStateClearIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) PRIVILEGED_FUNCTION; +#define xTaskNotifyStateClear( xTask ) \ + xTaskGenericNotifyStateClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ) ) +#define xTaskNotifyStateClearIndexed( xTask, uxIndexToClear ) \ + xTaskGenericNotifyStateClear( ( xTask ), ( uxIndexToClear ) ) + +/** + * task. h + * @code{c} + * uint32_t ulTaskNotifyValueClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToClear, uint32_t ulBitsToClear ); + * + * uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * ulTaskNotifyValueClearIndexed() clears the bits specified by the + * ulBitsToClear bit mask in the notification value at array index uxIndexToClear + * of the task referenced by xTask. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. ulTaskNotifyValueClear() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling ulTaskNotifyValueClear() is equivalent to calling + * ulTaskNotifyValueClearIndexed() with the uxIndexToClear parameter set to 0. + * + * @param xTask The handle of the RTOS task that will have bits in one of its + * notification values cleared. Set xTask to NULL to clear bits in a + * notification value of the calling task. To obtain a task's handle create the + * task using xTaskCreate() and make use of the pxCreatedTask parameter, or + * create the task using xTaskCreateStatic() and store the returned value, or + * use the task's name in a call to xTaskGetHandle(). + * + * @param uxIndexToClear The index within the target task's array of + * notification values in which to clear the bits. uxIndexToClear + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * ulTaskNotifyValueClear() does not have this parameter and always clears bits + * in the notification value at index 0. + * + * @param ulBitsToClear Bit mask of the bits to clear in the notification value of + * xTask. Set a bit to 1 to clear the corresponding bits in the task's notification + * value. Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear + * the notification value to 0. Set ulBitsToClear to 0 to query the task's + * notification value without clearing any bits. + * + * + * @return The value of the target task's notification value before the bits + * specified by ulBitsToClear were cleared. + * \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear + * \ingroup TaskNotifications + */ +uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; +#define ulTaskNotifyValueClear( xTask, ulBitsToClear ) \ + ulTaskGenericNotifyValueClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulBitsToClear ) ) +#define ulTaskNotifyValueClearIndexed( xTask, uxIndexToClear, ulBitsToClear ) \ + ulTaskGenericNotifyValueClear( ( xTask ), ( uxIndexToClear ), ( ulBitsToClear ) ) + +/** + * task.h + * @code{c} + * void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ); + * @endcode + * + * Capture the current time for future use with xTaskCheckForTimeOut(). + * + * @param pxTimeOut Pointer to a timeout object into which the current time + * is to be captured. The captured time includes the tick count and the number + * of times the tick count has overflowed since the system first booted. + * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState + * \ingroup TaskCtrl + */ +void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ); + * @endcode + * + * Determines if pxTicksToWait ticks has passed since a time was captured + * using a call to vTaskSetTimeOutState(). The captured time includes the tick + * count and the number of times the tick count has overflowed. + * + * @param pxTimeOut The time status as captured previously using + * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated + * to reflect the current time status. + * @param pxTicksToWait The number of ticks to check for timeout i.e. if + * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by + * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred. + * If the timeout has not occurred, pxTicksToWait is updated to reflect the + * number of remaining ticks. + * + * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is + * returned and pxTicksToWait is updated to reflect the number of remaining + * ticks. + * + * @see https://www.FreeRTOS.org/xTaskCheckForTimeOut.html + * + * Example Usage: + * @code{c} + * // Driver library function used to receive uxWantedBytes from an Rx buffer + * // that is filled by a UART interrupt. If there are not enough bytes in the + * // Rx buffer then the task enters the Blocked state until it is notified that + * // more data has been placed into the buffer. If there is still not enough + * // data then the task re-enters the Blocked state, and xTaskCheckForTimeOut() + * // is used to re-calculate the Block time to ensure the total amount of time + * // spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This + * // continues until either the buffer contains at least uxWantedBytes bytes, + * // or the total amount of time spent in the Blocked state reaches + * // MAX_TIME_TO_WAIT - at which point the task reads however many bytes are + * // available up to a maximum of uxWantedBytes. + * + * size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes ) + * { + * size_t uxReceived = 0; + * TickType_t xTicksToWait = MAX_TIME_TO_WAIT; + * TimeOut_t xTimeOut; + * + * // Initialize xTimeOut. This records the time at which this function + * // was entered. + * vTaskSetTimeOutState( &xTimeOut ); + * + * // Loop until the buffer contains the wanted number of bytes, or a + * // timeout occurs. + * while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes ) + * { + * // The buffer didn't contain enough data so this task is going to + * // enter the Blocked state. Adjusting xTicksToWait to account for + * // any time that has been spent in the Blocked state within this + * // function so far to ensure the total amount of time spent in the + * // Blocked state does not exceed MAX_TIME_TO_WAIT. + * if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE ) + * { + * //Timed out before the wanted number of bytes were available, + * // exit the loop. + * break; + * } + * + * // Wait for a maximum of xTicksToWait ticks to be notified that the + * // receive interrupt has placed more data into the buffer. + * ulTaskNotifyTake( pdTRUE, xTicksToWait ); + * } + * + * // Attempt to read uxWantedBytes from the receive buffer into pucBuffer. + * // The actual number of bytes read (which might be less than + * // uxWantedBytes) is returned. + * uxReceived = UART_read_from_receive_buffer( pxUARTInstance, + * pucBuffer, + * uxWantedBytes ); + * + * return uxReceived; + * } + * @endcode + * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut + * \ingroup TaskCtrl + */ +BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ); + * @endcode + * + * This function corrects the tick count value after the application code has held + * interrupts disabled for an extended period resulting in tick interrupts having + * been missed. + * + * This function is similar to vTaskStepTick(), however, unlike + * vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a + * time at which a task should be removed from the blocked state. That means + * tasks may have to be removed from the blocked state as the tick count is + * moved. + * + * @param xTicksToCatchUp The number of tick interrupts that have been missed due to + * interrupts being disabled. Its value is not computed automatically, so must be + * computed by the application writer. + * + * @return pdTRUE if moving the tick count forward resulted in a task leaving the + * blocked state and a context switch being performed. Otherwise pdFALSE. + * + * \defgroup xTaskCatchUpTicks xTaskCatchUpTicks + * \ingroup TaskCtrl + */ +BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION; + + +/*----------------------------------------------------------- +* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES +*----------------------------------------------------------*/ + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Called from the real time kernel tick (either preemptive or cooperative), + * this increments the tick count and checks if any tasks that are blocked + * for a finite period required removing from a blocked list and placing on + * a ready list. If a non-zero value is returned then a context switch is + * required because either: + * + A task was removed from a blocked list because its timeout had expired, + * or + * + Time slicing is in use and there is a task of equal priority to the + * currently running task. + */ +BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes the calling task from the ready list and places it both + * on the list of tasks waiting for a particular event, and the + * list of delayed tasks. The task will be removed from both lists + * and replaced on the ready list should either the event occur (and + * there be no higher priority tasks waiting on the same event) or + * the delay period expires. + * + * The 'unordered' version replaces the event list item value with the + * xItemValue value, and inserts the list item at the end of the list. + * + * The 'ordered' version uses the existing event list item value (which is the + * owning task's priority) to insert the list item into the event list in task + * priority order. + * + * @param pxEventList The list containing tasks that are blocked waiting + * for the event to occur. + * + * @param xItemValue The item value to use for the event list item when the + * event list is not ordered by task priority. + * + * @param xTicksToWait The maximum amount of time that the task should wait + * for the event to occur. This is specified in kernel ticks, the constant + * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time + * period. + */ +void vTaskPlaceOnEventList( List_t * const pxEventList, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, + const TickType_t xItemValue, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * This function performs nearly the same function as vTaskPlaceOnEventList(). + * The difference being that this function does not permit tasks to block + * indefinitely, whereas vTaskPlaceOnEventList() does. + * + */ +void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes a task from both the specified event list and the list of blocked + * tasks, and places it on a ready queue. + * + * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called + * if either an event occurs to unblock a task, or the block timeout period + * expires. + * + * xTaskRemoveFromEventList() is used when the event list is in task priority + * order. It removes the list item from the head of the event list as that will + * have the highest priority owning task of all the tasks on the event list. + * vTaskRemoveFromUnorderedEventList() is used when the event list is not + * ordered and the event list items hold something other than the owning tasks + * priority. In this case the event list item value is updated to the value + * passed in the xItemValue parameter. + * + * @return pdTRUE if the task being removed has a higher priority than the task + * making the call, otherwise pdFALSE. + */ +BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION; +void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, + const TickType_t xItemValue ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Sets the pointer to the current TCB to the TCB of the highest priority task + * that is ready to run. + */ +portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION; + +/* + * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY + * THE EVENT BITS MODULE. + */ +TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION; + +/* + * Return the handle of the calling task. + */ +TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION; + +/* + * Shortcut used by the queue implementation to prevent unnecessary call to + * taskYIELD(); + */ +void vTaskMissedYield( void ) PRIVILEGED_FUNCTION; + +/* + * Returns the scheduler state as taskSCHEDULER_RUNNING, + * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED. + */ +BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION; + +/* + * Raises the priority of the mutex holder to that of the calling task should + * the mutex holder have a priority less than the calling task. + */ +BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION; + +/* + * Set the priority of a task back to its proper priority in the case that it + * inherited a higher priority while it was holding a semaphore. + */ +BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION; + +/* + * If a higher priority task attempting to obtain a mutex caused a lower + * priority task to inherit the higher priority task's priority - but the higher + * priority task then timed out without obtaining the mutex, then the lower + * priority task will disinherit the priority again - but only down as far as + * the highest priority task that is still waiting for the mutex (if there were + * more than one task waiting for the mutex). + */ +void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, + UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION; + +/* + * Get the uxTaskNumber assigned to the task referenced by the xTask parameter. + */ +UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/* + * Set the uxTaskNumber of the task referenced by the xTask parameter to + * uxHandle. + */ +void vTaskSetTaskNumber( TaskHandle_t xTask, + const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION; + +/* + * Only available when configUSE_TICKLESS_IDLE is set to 1. + * If tickless mode is being used, or a low power mode is implemented, then + * the tick interrupt will not execute during idle periods. When this is the + * case, the tick count value maintained by the scheduler needs to be kept up + * to date with the actual execution time by being skipped forward by a time + * equal to the idle period. + */ +void vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION; + +/* + * Only available when configUSE_TICKLESS_IDLE is set to 1. + * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port + * specific sleep function to determine if it is ok to proceed with the sleep, + * and if it is ok to proceed, if it is ok to sleep indefinitely. + * + * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only + * called with the scheduler suspended, not from within a critical section. It + * is therefore possible for an interrupt to request a context switch between + * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being + * entered. eTaskConfirmSleepModeStatus() should be called from a short + * critical section between the timer being stopped and the sleep mode being + * entered to ensure it is ok to proceed into the sleep mode. + */ +eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Increment the mutex held count when a mutex is + * taken and return the handle of the task that has taken the mutex. + */ +TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Same as vTaskSetTimeOutState(), but without a critical + * section. + */ +void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ +#endif /* INC_TASK_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/timers.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/timers.h new file mode 100644 index 0000000..4b73908 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/include/timers.h @@ -0,0 +1,1369 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef TIMERS_H +#define TIMERS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include timers.h" +#endif + +/*lint -save -e537 This headers are only multiply included if the application code + * happens to also be including task.h. */ +#include "task.h" +/*lint -restore */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- +* MACROS AND DEFINITIONS +*----------------------------------------------------------*/ + +/* IDs for commands that can be sent/received on the timer queue. These are to + * be used solely through the macros that make up the public software timer API, + * as defined below. The commands that are sent from interrupts must use the + * highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task + * or interrupt version of the queue send function should be used. */ +#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR ( ( BaseType_t ) -2 ) +#define tmrCOMMAND_EXECUTE_CALLBACK ( ( BaseType_t ) -1 ) +#define tmrCOMMAND_START_DONT_TRACE ( ( BaseType_t ) 0 ) +#define tmrCOMMAND_START ( ( BaseType_t ) 1 ) +#define tmrCOMMAND_RESET ( ( BaseType_t ) 2 ) +#define tmrCOMMAND_STOP ( ( BaseType_t ) 3 ) +#define tmrCOMMAND_CHANGE_PERIOD ( ( BaseType_t ) 4 ) +#define tmrCOMMAND_DELETE ( ( BaseType_t ) 5 ) + +#define tmrFIRST_FROM_ISR_COMMAND ( ( BaseType_t ) 6 ) +#define tmrCOMMAND_START_FROM_ISR ( ( BaseType_t ) 6 ) +#define tmrCOMMAND_RESET_FROM_ISR ( ( BaseType_t ) 7 ) +#define tmrCOMMAND_STOP_FROM_ISR ( ( BaseType_t ) 8 ) +#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR ( ( BaseType_t ) 9 ) + + +/** + * Type by which software timers are referenced. For example, a call to + * xTimerCreate() returns an TimerHandle_t variable that can then be used to + * reference the subject timer in calls to other software timer API functions + * (for example, xTimerStart(), xTimerReset(), etc.). + */ +struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +typedef struct tmrTimerControl * TimerHandle_t; + +/* + * Defines the prototype to which timer callback functions must conform. + */ +typedef void (* TimerCallbackFunction_t)( TimerHandle_t xTimer ); + +/* + * Defines the prototype to which functions used with the + * xTimerPendFunctionCallFromISR() function must conform. + */ +typedef void (* PendedFunction_t)( void *, + uint32_t ); + +/** + * TimerHandle_t xTimerCreate( const char * const pcTimerName, + * TickType_t xTimerPeriodInTicks, + * BaseType_t xAutoReload, + * void * pvTimerID, + * TimerCallbackFunction_t pxCallbackFunction ); + * + * Creates a new software timer instance, and returns a handle by which the + * created software timer can be referenced. + * + * Internally, within the FreeRTOS implementation, software timers use a block + * of memory, in which the timer data structure is stored. If a software timer + * is created using xTimerCreate() then the required memory is automatically + * dynamically allocated inside the xTimerCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a software timer is created using + * xTimerCreateStatic() then the application writer must provide the memory that + * will get used by the software timer. xTimerCreateStatic() therefore allows a + * software timer to be created without using any dynamic memory allocation. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a + * timer into the active state. + * + * @param pcTimerName A text name that is assigned to the timer. This is done + * purely to assist debugging. The kernel itself only ever references a timer + * by its handle, and never by its name. + * + * @param xTimerPeriodInTicks The timer period. The time is defined in tick + * periods so the constant portTICK_PERIOD_MS can be used to convert a time that + * has been specified in milliseconds. For example, if the timer must expire + * after 100 ticks, then xTimerPeriodInTicks should be set to 100. + * Alternatively, if the timer must expire after 500ms, then xPeriod can be set + * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or + * equal to 1000. Time timer period must be greater than 0. + * + * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. + * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + * + * @param pvTimerID An identifier that is assigned to the timer being created. + * Typically this would be used in the timer callback function to identify which + * timer expired when the same callback function is assigned to more than one + * timer. + * + * @param pxCallbackFunction The function to call when the timer expires. + * Callback functions must have the prototype defined by TimerCallbackFunction_t, + * which is "void vCallbackFunction( TimerHandle_t xTimer );". + * + * @return If the timer is successfully created then a handle to the newly + * created timer is returned. If the timer cannot be created because there is + * insufficient FreeRTOS heap remaining to allocate the timer + * structures then NULL is returned. + * + * Example usage: + * @verbatim + * #define NUM_TIMERS 5 + * + * // An array to hold handles to the created timers. + * TimerHandle_t xTimers[ NUM_TIMERS ]; + * + * // An array to hold a count of the number of times each timer expires. + * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 }; + * + * // Define a callback function that will be used by multiple timer instances. + * // The callback function does nothing but count the number of times the + * // associated timer expires, and stop the timer once the timer has expired + * // 10 times. + * void vTimerCallback( TimerHandle_t pxTimer ) + * { + * int32_t lArrayIndex; + * const int32_t xMaxExpiryCountBeforeStopping = 10; + * + * // Optionally do something if the pxTimer parameter is NULL. + * configASSERT( pxTimer ); + * + * // Which timer expired? + * lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer ); + * + * // Increment the number of times that pxTimer has expired. + * lExpireCounters[ lArrayIndex ] += 1; + * + * // If the timer has expired 10 times then stop it from running. + * if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping ) + * { + * // Do not use a block time if calling a timer API function from a + * // timer callback function, as doing so could cause a deadlock! + * xTimerStop( pxTimer, 0 ); + * } + * } + * + * void main( void ) + * { + * int32_t x; + * + * // Create then start some timers. Starting the timers before the scheduler + * // has been started means the timers will start running immediately that + * // the scheduler starts. + * for( x = 0; x < NUM_TIMERS; x++ ) + * { + * xTimers[ x ] = xTimerCreate( "Timer", // Just a text name, not used by the kernel. + * ( 100 * ( x + 1 ) ), // The timer period in ticks. + * pdTRUE, // The timers will auto-reload themselves when they expire. + * ( void * ) x, // Assign each timer a unique id equal to its array index. + * vTimerCallback // Each timer calls the same callback when it expires. + * ); + * + * if( xTimers[ x ] == NULL ) + * { + * // The timer was not created. + * } + * else + * { + * // Start the timer. No block time is specified, and even if one was + * // it would be ignored because the scheduler has not yet been + * // started. + * if( xTimerStart( xTimers[ x ], 0 ) != pdPASS ) + * { + * // The timer could not be set into the Active state. + * } + * } + * } + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timers running as they have already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; +#endif + +/** + * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName, + * TickType_t xTimerPeriodInTicks, + * BaseType_t xAutoReload, + * void * pvTimerID, + * TimerCallbackFunction_t pxCallbackFunction, + * StaticTimer_t *pxTimerBuffer ); + * + * Creates a new software timer instance, and returns a handle by which the + * created software timer can be referenced. + * + * Internally, within the FreeRTOS implementation, software timers use a block + * of memory, in which the timer data structure is stored. If a software timer + * is created using xTimerCreate() then the required memory is automatically + * dynamically allocated inside the xTimerCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a software timer is created using + * xTimerCreateStatic() then the application writer must provide the memory that + * will get used by the software timer. xTimerCreateStatic() therefore allows a + * software timer to be created without using any dynamic memory allocation. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a + * timer into the active state. + * + * @param pcTimerName A text name that is assigned to the timer. This is done + * purely to assist debugging. The kernel itself only ever references a timer + * by its handle, and never by its name. + * + * @param xTimerPeriodInTicks The timer period. The time is defined in tick + * periods so the constant portTICK_PERIOD_MS can be used to convert a time that + * has been specified in milliseconds. For example, if the timer must expire + * after 100 ticks, then xTimerPeriodInTicks should be set to 100. + * Alternatively, if the timer must expire after 500ms, then xPeriod can be set + * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or + * equal to 1000. The timer period must be greater than 0. + * + * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. + * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + * + * @param pvTimerID An identifier that is assigned to the timer being created. + * Typically this would be used in the timer callback function to identify which + * timer expired when the same callback function is assigned to more than one + * timer. + * + * @param pxCallbackFunction The function to call when the timer expires. + * Callback functions must have the prototype defined by TimerCallbackFunction_t, + * which is "void vCallbackFunction( TimerHandle_t xTimer );". + * + * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which + * will be then be used to hold the software timer's data structures, removing + * the need for the memory to be allocated dynamically. + * + * @return If the timer is created then a handle to the created timer is + * returned. If pxTimerBuffer was NULL then NULL is returned. + * + * Example usage: + * @verbatim + * + * // The buffer used to hold the software timer's data structure. + * static StaticTimer_t xTimerBuffer; + * + * // A variable that will be incremented by the software timer's callback + * // function. + * UBaseType_t uxVariableToIncrement = 0; + * + * // A software timer callback function that increments a variable passed to + * // it when the software timer was created. After the 5th increment the + * // callback function stops the software timer. + * static void prvTimerCallback( TimerHandle_t xExpiredTimer ) + * { + * UBaseType_t *puxVariableToIncrement; + * BaseType_t xReturned; + * + * // Obtain the address of the variable to increment from the timer ID. + * puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer ); + * + * // Increment the variable to show the timer callback has executed. + * ( *puxVariableToIncrement )++; + * + * // If this callback has executed the required number of times, stop the + * // timer. + * if( *puxVariableToIncrement == 5 ) + * { + * // This is called from a timer callback so must not block. + * xTimerStop( xExpiredTimer, staticDONT_BLOCK ); + * } + * } + * + * + * void main( void ) + * { + * // Create the software time. xTimerCreateStatic() has an extra parameter + * // than the normal xTimerCreate() API function. The parameter is a pointer + * // to the StaticTimer_t structure that will hold the software timer + * // structure. If the parameter is passed as NULL then the structure will be + * // allocated dynamically, just as if xTimerCreate() had been called. + * xTimer = xTimerCreateStatic( "T1", // Text name for the task. Helps debugging only. Not used by FreeRTOS. + * xTimerPeriod, // The period of the timer in ticks. + * pdTRUE, // This is an auto-reload timer. + * ( void * ) &uxVariableToIncrement, // A variable incremented by the software timer's callback function + * prvTimerCallback, // The function to execute when the timer expires. + * &xTimerBuffer ); // The buffer that will hold the software timer structure. + * + * // The scheduler has not started yet so a block time is not used. + * xReturned = xTimerStart( xTimer, 0 ); + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timers running as they have already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * void *pvTimerGetTimerID( TimerHandle_t xTimer ); + * + * Returns the ID assigned to the timer. + * + * IDs are assigned to timers using the pvTimerID parameter of the call to + * xTimerCreated() that was used to create the timer, and by calling the + * vTimerSetTimerID() API function. + * + * If the same callback function is assigned to multiple timers then the timer + * ID can be used as time specific (timer local) storage. + * + * @param xTimer The timer being queried. + * + * @return The ID assigned to the timer being queried. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + */ +void * pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ); + * + * Sets the ID assigned to the timer. + * + * IDs are assigned to timers using the pvTimerID parameter of the call to + * xTimerCreated() that was used to create the timer. + * + * If the same callback function is assigned to multiple timers then the timer + * ID can be used as time specific (timer local) storage. + * + * @param xTimer The timer being updated. + * + * @param pvNewID The ID to assign to the timer. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + */ +void vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ); + * + * Queries a timer to see if it is active or dormant. + * + * A timer will be dormant if: + * 1) It has been created but not started, or + * 2) It is an expired one-shot timer that has not been restarted. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the + * active state. + * + * @param xTimer The timer being queried. + * + * @return pdFALSE will be returned if the timer is dormant. A value other than + * pdFALSE will be returned if the timer is active. + * + * Example usage: + * @verbatim + * // This function assumes xTimer has already been created. + * void vAFunction( TimerHandle_t xTimer ) + * { + * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )" + * { + * // xTimer is active, do something. + * } + * else + * { + * // xTimer is not active, do something else. + * } + * } + * @endverbatim + */ +BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ); + * + * Simply returns the handle of the timer service/daemon task. It it not valid + * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started. + */ +TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerStart() starts a timer that was previously created using the + * xTimerCreate() API function. If the timer had already been started and was + * already in the active state, then xTimerStart() has equivalent functionality + * to the xTimerReset() API function. + * + * Starting a timer ensures the timer is in the active state. If the timer + * is not stopped, deleted, or reset in the mean time, the callback function + * associated with the timer will get called 'n' ticks after xTimerStart() was + * called, where 'n' is the timers defined period. + * + * It is valid to call xTimerStart() before the scheduler has been started, but + * when this is done the timer will not actually start until the scheduler is + * started, and the timers expiry time will be relative to when the scheduler is + * started, not relative to when xTimerStart() was called. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart() + * to be available. + * + * @param xTimer The handle of the timer being started/restarted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the start command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerStart() was called. xTicksToWait is ignored if xTimerStart() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the start command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system, although the + * timers expiry time is relative to when xTimerStart() is actually called. The + * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + * + */ +#define xTimerStart( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerStop() stops a timer that was previously started using either of the + * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(), + * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions. + * + * Stopping a timer ensures the timer is not in the active state. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop() + * to be available. + * + * @param xTimer The handle of the timer being stopped. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the stop command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerStop() was called. xTicksToWait is ignored if xTimerStop() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the stop command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + * + */ +#define xTimerStop( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerChangePeriod( TimerHandle_t xTimer, + * TickType_t xNewPeriod, + * TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerChangePeriod() changes the period of a timer that was previously + * created using the xTimerCreate() API function. + * + * xTimerChangePeriod() can be called to change the period of an active or + * dormant state timer. + * + * The configUSE_TIMERS configuration constant must be set to 1 for + * xTimerChangePeriod() to be available. + * + * @param xTimer The handle of the timer that is having its period changed. + * + * @param xNewPeriod The new period for xTimer. Timer periods are specified in + * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time + * that has been specified in milliseconds. For example, if the timer must + * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively, + * if the timer must expire after 500ms, then xNewPeriod can be set to + * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than + * or equal to 1000. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the change period command to be + * successfully sent to the timer command queue, should the queue already be + * full when xTimerChangePeriod() was called. xTicksToWait is ignored if + * xTimerChangePeriod() is called before the scheduler is started. + * + * @return pdFAIL will be returned if the change period command could not be + * sent to the timer command queue even after xTicksToWait ticks had passed. + * pdPASS will be returned if the command was successfully sent to the timer + * command queue. When the command is actually processed will depend on the + * priority of the timer service/daemon task relative to other tasks in the + * system. The timer service/daemon task priority is set by the + * configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This function assumes xTimer has already been created. If the timer + * // referenced by xTimer is already active when it is called, then the timer + * // is deleted. If the timer referenced by xTimer is not active when it is + * // called, then the period of the timer is set to 500ms and the timer is + * // started. + * void vAFunction( TimerHandle_t xTimer ) + * { + * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )" + * { + * // xTimer is already active - delete it. + * xTimerDelete( xTimer ); + * } + * else + * { + * // xTimer is not active, change its period to 500ms. This will also + * // cause the timer to start. Block for a maximum of 100 ticks if the + * // change period command cannot immediately be sent to the timer + * // command queue. + * if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS ) + * { + * // The command was successfully sent. + * } + * else + * { + * // The command could not be sent, even after waiting for 100 ticks + * // to pass. Take appropriate action here. + * } + * } + * } + * @endverbatim + */ +#define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerDelete() deletes a timer that was previously created using the + * xTimerCreate() API function. + * + * The configUSE_TIMERS configuration constant must be set to 1 for + * xTimerDelete() to be available. + * + * @param xTimer The handle of the timer being deleted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the delete command to be + * successfully sent to the timer command queue, should the queue already be + * full when xTimerDelete() was called. xTicksToWait is ignored if xTimerDelete() + * is called before the scheduler is started. + * + * @return pdFAIL will be returned if the delete command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerChangePeriod() API function example usage scenario. + */ +#define xTimerDelete( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerReset() re-starts a timer that was previously created using the + * xTimerCreate() API function. If the timer had already been started and was + * already in the active state, then xTimerReset() will cause the timer to + * re-evaluate its expiry time so that it is relative to when xTimerReset() was + * called. If the timer was in the dormant state then xTimerReset() has + * equivalent functionality to the xTimerStart() API function. + * + * Resetting a timer ensures the timer is in the active state. If the timer + * is not stopped, deleted, or reset in the mean time, the callback function + * associated with the timer will get called 'n' ticks after xTimerReset() was + * called, where 'n' is the timers defined period. + * + * It is valid to call xTimerReset() before the scheduler has been started, but + * when this is done the timer will not actually start until the scheduler is + * started, and the timers expiry time will be relative to when the scheduler is + * started, not relative to when xTimerReset() was called. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset() + * to be available. + * + * @param xTimer The handle of the timer being reset/started/restarted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the reset command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerReset() was called. xTicksToWait is ignored if xTimerReset() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the reset command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system, although the + * timers expiry time is relative to when xTimerStart() is actually called. The + * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * @verbatim + * // When a key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer. + * + * TimerHandle_t xBacklightTimer = NULL; + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press event handler. + * void vKeyPressEventHandler( char cKey ) + * { + * // Ensure the LCD back-light is on, then reset the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. Wait 10 ticks for the command to be successfully sent + * // if it cannot be sent immediately. + * vSetBacklightState( BACKLIGHT_ON ); + * if( xTimerReset( xBacklightTimer, 100 ) != pdPASS ) + * { + * // The reset command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * } + * + * void main( void ) + * { + * int32_t x; + * + * // Create then start the one-shot timer that is responsible for turning + * // the back-light off if no keys are pressed within a 5 second period. + * xBacklightTimer = xTimerCreate( "BacklightTimer", // Just a text name, not used by the kernel. + * ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks. + * pdFALSE, // The timer is a one-shot timer. + * 0, // The id is not used by the callback so can take any value. + * vBacklightTimerCallback // The callback function that switches the LCD back-light off. + * ); + * + * if( xBacklightTimer == NULL ) + * { + * // The timer was not created. + * } + * else + * { + * // Start the timer. No block time is specified, and even if one was + * // it would be ignored because the scheduler has not yet been + * // started. + * if( xTimerStart( xBacklightTimer, 0 ) != pdPASS ) + * { + * // The timer could not be set into the Active state. + * } + * } + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timer running as it has already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#define xTimerReset( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerStartFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerStart() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer being started/restarted. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerStartFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerStartFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerStartFromISR() function. If + * xTimerStartFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the start command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system, although the timers expiry time is + * relative to when xTimerStartFromISR() is actually called. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xBacklightTimer has already been created. When a + * // key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer, and unlike the example given for + * // the xTimerReset() function, the key press event handler is an interrupt + * // service routine. + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press interrupt service routine. + * void vKeyPressEventInterruptHandler( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // Ensure the LCD back-light is on, then restart the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. This is an interrupt service routine so can only + * // call FreeRTOS API functions that end in "FromISR". + * vSetBacklightState( BACKLIGHT_ON ); + * + * // xTimerStartFromISR() or xTimerResetFromISR() could be called here + * // as both cause the timer to re-calculate its expiry time. + * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was + * // declared (in this function). + * if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The start command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerStopFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerStop() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer being stopped. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerStopFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerStopFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerStopFromISR() function. If + * xTimerStopFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the stop command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system. The timer service/daemon task + * priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xTimer has already been created and started. When + * // an interrupt occurs, the timer should be simply stopped. + * + * // The interrupt service routine that stops the timer. + * void vAnExampleInterruptServiceRoutine( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // The interrupt has occurred - simply stop the timer. + * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined + * // (within this function). As this is an interrupt service routine, only + * // FreeRTOS API functions that end in "FromISR" can be used. + * if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The stop command was not executed successfully. Take appropriate + * // action here. + * } + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer, + * TickType_t xNewPeriod, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerChangePeriod() that can be called from an interrupt + * service routine. + * + * @param xTimer The handle of the timer that is having its period changed. + * + * @param xNewPeriod The new period for xTimer. Timer periods are specified in + * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time + * that has been specified in milliseconds. For example, if the timer must + * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively, + * if the timer must expire after 500ms, then xNewPeriod can be set to + * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than + * or equal to 1000. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerChangePeriodFromISR() writes a message to the + * timer command queue, so has the potential to transition the timer service/ + * daemon task out of the Blocked state. If calling xTimerChangePeriodFromISR() + * causes the timer service/daemon task to leave the Blocked state, and the + * timer service/daemon task has a priority equal to or greater than the + * currently executing task (the task that was interrupted), then + * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the + * xTimerChangePeriodFromISR() function. If xTimerChangePeriodFromISR() sets + * this value to pdTRUE then a context switch should be performed before the + * interrupt exits. + * + * @return pdFAIL will be returned if the command to change the timers period + * could not be sent to the timer command queue. pdPASS will be returned if the + * command was successfully sent to the timer command queue. When the command + * is actually processed will depend on the priority of the timer service/daemon + * task relative to other tasks in the system. The timer service/daemon task + * priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xTimer has already been created and started. When + * // an interrupt occurs, the period of xTimer should be changed to 500ms. + * + * // The interrupt service routine that changes the period of xTimer. + * void vAnExampleInterruptServiceRoutine( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // The interrupt has occurred - change the period of xTimer to 500ms. + * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined + * // (within this function). As this is an interrupt service routine, only + * // FreeRTOS API functions that end in "FromISR" can be used. + * if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The command to change the timers period was not executed + * // successfully. Take appropriate action here. + * } + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerResetFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerReset() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer that is to be started, reset, or + * restarted. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerResetFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerResetFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerResetFromISR() function. If + * xTimerResetFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the reset command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system, although the timers expiry time is + * relative to when xTimerResetFromISR() is actually called. The timer service/daemon + * task priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xBacklightTimer has already been created. When a + * // key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer, and unlike the example given for + * // the xTimerReset() function, the key press event handler is an interrupt + * // service routine. + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press interrupt service routine. + * void vKeyPressEventInterruptHandler( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // Ensure the LCD back-light is on, then reset the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. This is an interrupt service routine so can only + * // call FreeRTOS API functions that end in "FromISR". + * vSetBacklightState( BACKLIGHT_ON ); + * + * // xTimerStartFromISR() or xTimerResetFromISR() could be called here + * // as both cause the timer to re-calculate its expiry time. + * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was + * // declared (in this function). + * if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The reset command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U ) + + +/** + * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + * void *pvParameter1, + * uint32_t ulParameter2, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * + * Used from application interrupt service routines to defer the execution of a + * function to the RTOS daemon task (the timer service task, hence this function + * is implemented in timers.c and is prefixed with 'Timer'). + * + * Ideally an interrupt service routine (ISR) is kept as short as possible, but + * sometimes an ISR either has a lot of processing to do, or needs to perform + * processing that is not deterministic. In these cases + * xTimerPendFunctionCallFromISR() can be used to defer processing of a function + * to the RTOS daemon task. + * + * A mechanism is provided that allows the interrupt to return directly to the + * task that will subsequently execute the pended callback function. This + * allows the callback function to execute contiguously in time with the + * interrupt - just as if the callback had executed in the interrupt itself. + * + * @param xFunctionToPend The function to execute from the timer service/ + * daemon task. The function must conform to the PendedFunction_t + * prototype. + * + * @param pvParameter1 The value of the callback function's first parameter. + * The parameter has a void * type to allow it to be used to pass any type. + * For example, unsigned longs can be cast to a void *, or the void * can be + * used to point to a structure. + * + * @param ulParameter2 The value of the callback function's second parameter. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task (which is set using + * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of + * the currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE within + * xTimerPendFunctionCallFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return pdPASS is returned if the message was successfully sent to the + * timer daemon task, otherwise pdFALSE is returned. + * + * Example usage: + * @verbatim + * + * // The callback function that will execute in the context of the daemon task. + * // Note callback functions must all use this same prototype. + * void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 ) + * { + * BaseType_t xInterfaceToService; + * + * // The interface that requires servicing is passed in the second + * // parameter. The first parameter is not used in this case. + * xInterfaceToService = ( BaseType_t ) ulParameter2; + * + * // ...Perform the processing here... + * } + * + * // An ISR that receives data packets from multiple interfaces + * void vAnISR( void ) + * { + * BaseType_t xInterfaceToService, xHigherPriorityTaskWoken; + * + * // Query the hardware to determine which interface needs processing. + * xInterfaceToService = prvCheckInterfaces(); + * + * // The actual processing is to be deferred to a task. Request the + * // vProcessInterface() callback function is executed, passing in the + * // number of the interface that needs processing. The interface to + * // service is passed in the second parameter. The first parameter is + * // not used in this case. + * xHigherPriorityTaskWoken = pdFALSE; + * xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken ); + * + * // If xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and will + * // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to + * // the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * + * } + * @endverbatim + */ +BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + * void *pvParameter1, + * uint32_t ulParameter2, + * TickType_t xTicksToWait ); + * + * + * Used to defer the execution of a function to the RTOS daemon task (the timer + * service task, hence this function is implemented in timers.c and is prefixed + * with 'Timer'). + * + * @param xFunctionToPend The function to execute from the timer service/ + * daemon task. The function must conform to the PendedFunction_t + * prototype. + * + * @param pvParameter1 The value of the callback function's first parameter. + * The parameter has a void * type to allow it to be used to pass any type. + * For example, unsigned longs can be cast to a void *, or the void * can be + * used to point to a structure. + * + * @param ulParameter2 The value of the callback function's second parameter. + * + * @param xTicksToWait Calling this function will result in a message being + * sent to the timer daemon task on a queue. xTicksToWait is the amount of + * time the calling task should remain in the Blocked state (so not using any + * processing time) for space to become available on the timer queue if the + * queue is found to be full. + * + * @return pdPASS is returned if the message was successfully sent to the + * timer daemon task, otherwise pdFALSE is returned. + * + */ +BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * const char * const pcTimerGetName( TimerHandle_t xTimer ); + * + * Returns the name that was assigned to a timer when the timer was created. + * + * @param xTimer The handle of the timer being queried. + * + * @return The name assigned to the timer specified by the xTimer parameter. + */ +const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * void vTimerSetReloadMode( TimerHandle_t xTimer, const BaseType_t xAutoReload ); + * + * Updates a timer to be either an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being updated. + * + * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the timer's period (see the + * xTimerPeriodInTicks parameter of the xTimerCreate() API function). If + * xAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + */ +void vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer ); + * + * Queries a timer to determine if it is an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise + * pdFALSE is returned. + */ +BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ); + * + * Queries a timer to determine if it is an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise + * pdFALSE is returned. + */ +UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TickType_t xTimerGetPeriod( TimerHandle_t xTimer ); + * + * Returns the period of a timer. + * + * @param xTimer The handle of the timer being queried. + * + * @return The period of the timer in ticks. + */ +TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ); + * + * Returns the time in ticks at which the timer will expire. If this is less + * than the current tick count then the expiry time has overflowed from the + * current time. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is running then the time in ticks at which the timer + * will next expire is returned. If the timer is not running then the return + * value is undefined. + */ +TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/* + * Functions beyond this part are not part of the public API and are intended + * for use by the kernel only. + */ +BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION; +BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +#if ( configUSE_TRACE_FACILITY == 1 ) + void vTimerSetTimerNumber( TimerHandle_t xTimer, + UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION; + UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; +#endif + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + +/** + * task.h + * @code{c} + * void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * @endcode + * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * @param ppxTimerTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task + * @param pulTimerTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + */ + void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ); + +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ +#endif /* TIMERS_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/list.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/list.c new file mode 100644 index 0000000..afcae87 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/list.c @@ -0,0 +1,226 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "list.h" + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be + * defined for the header files above, but not in this file, in order to + * generate the correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + +/*----------------------------------------------------------- +* PUBLIC LIST API documented in list.h +*----------------------------------------------------------*/ + +void vListInitialise( List_t * const pxList ) +{ + /* The list structure contains a list item which is used to mark the + * end of the list. To initialise the list the list end is inserted + * as the only list entry. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + + listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) ); + + /* The list end value is the highest possible value in the list to + * ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + + /* The list end next and previous pointers point to itself so we know + * when the list is empty. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + + /* Initialize the remaining fields of xListEnd when it is a proper ListItem_t */ + #if ( configUSE_MINI_LIST_ITEM == 0 ) + { + pxList->xListEnd.pvOwner = NULL; + pxList->xListEnd.pxContainer = NULL; + listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) ); + } + #endif + + pxList->uxNumberOfItems = ( UBaseType_t ) 0U; + + /* Write known values into the list if + * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); + listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); +} +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( ListItem_t * const pxItem ) +{ + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pxContainer = NULL; + + /* Write known values into the list item if + * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); + listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); +} +/*-----------------------------------------------------------*/ + +void vListInsertEnd( List_t * const pxList, + ListItem_t * const pxNewListItem ) +{ + ListItem_t * const pxIndex = pxList->pxIndex; + + /* Only effective when configASSERT() is also defined, these tests may catch + * the list data structures being overwritten in memory. They will not catch + * data errors caused by incorrect configuration or use of FreeRTOS. */ + listTEST_LIST_INTEGRITY( pxList ); + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert a new list item into pxList, but rather than sort the list, + * makes the new list item the last item to be removed by a call to + * listGET_OWNER_OF_NEXT_ENTRY(). */ + pxNewListItem->pxNext = pxIndex; + pxNewListItem->pxPrevious = pxIndex->pxPrevious; + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + pxIndex->pxPrevious->pxNext = pxNewListItem; + pxIndex->pxPrevious = pxNewListItem; + + /* Remember which list the item is in. */ + pxNewListItem->pxContainer = pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +void vListInsert( List_t * const pxList, + ListItem_t * const pxNewListItem ) +{ + ListItem_t * pxIterator; + const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; + + /* Only effective when configASSERT() is also defined, these tests may catch + * the list data structures being overwritten in memory. They will not catch + * data errors caused by incorrect configuration or use of FreeRTOS. */ + listTEST_LIST_INTEGRITY( pxList ); + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert the new list item into the list, sorted in xItemValue order. + * + * If the list already contains a list item with the same item value then the + * new list item should be placed after it. This ensures that TCBs which are + * stored in ready lists (all of which have the same xItemValue value) get a + * share of the CPU. However, if the xItemValue is the same as the back marker + * the iteration loop below will not end. Therefore the value is checked + * first, and the algorithm slightly modified if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + { + pxIterator = pxList->xListEnd.pxPrevious; + } + else + { + /* *** NOTE *********************************************************** + * If you find your application is crashing here then likely causes are + * listed below. In addition see https://www.FreeRTOS.org/FAQHelp.html for + * more tips, and ensure configASSERT() is defined! + * https://www.FreeRTOS.org/a00110.html#configASSERT + * + * 1) Stack overflow - + * see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html + * 2) Incorrect interrupt priority assignment, especially on Cortex-M + * parts where numerically high priority values denote low actual + * interrupt priorities, which can seem counter intuitive. See + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition + * of configMAX_SYSCALL_INTERRUPT_PRIORITY on + * https://www.FreeRTOS.org/a00110.html + * 3) Calling an API function from within a critical section or when + * the scheduler is suspended, or calling an API function that does + * not end in "FromISR" from an interrupt. + * 4) Using a queue or semaphore before it has been initialised or + * before the scheduler has been started (are interrupts firing + * before vTaskStartScheduler() has been called?). + * 5) If the FreeRTOS port supports interrupt nesting then ensure that + * the priority of the tick interrupt is at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + **********************************************************************/ + + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ + { + /* There is nothing to do here, just iterating to the wanted + * insertion position. */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + pxNewListItem->pxNext->pxPrevious = pxNewListItem; + pxNewListItem->pxPrevious = pxIterator; + pxIterator->pxNext = pxNewListItem; + + /* Remember which list the item is in. This allows fast removal of the + * item later. */ + pxNewListItem->pxContainer = pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) +{ +/* The list item knows which list it is in. Obtain the list from the list + * item. */ + List_t * const pxList = pxItemToRemove->pxContainer; + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxItemToRemove->pxContainer = NULL; + ( pxList->uxNumberOfItems )--; + + return pxList->uxNumberOfItems; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifest.yml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifest.yml new file mode 100644 index 0000000..211e3c2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifest.yml @@ -0,0 +1,4 @@ +name : "FreeRTOS-Kernel" +version: "v10.5.1" +description: "FreeRTOS Kernel." +license: "MIT" diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_K32L2A41A_manifest_v3_10.xml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_K32L2A41A_manifest_v3_10.xml new file mode 100644 index 0000000..ea0cd8d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_K32L2A41A_manifest_v3_10.xml @@ -0,0 +1,260 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_K32L2A41A_manifest_v3_13.xml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_K32L2A41A_manifest_v3_13.xml new file mode 100644 index 0000000..d5fa39c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_K32L2A41A_manifest_v3_13.xml @@ -0,0 +1,234 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_K32L2A41A_manifest_v3_14.xml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_K32L2A41A_manifest_v3_14.xml new file mode 100644 index 0000000..08ea480 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_K32L2A41A_manifest_v3_14.xml @@ -0,0 +1,249 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_K32L2B31A_manifest_v3_10.xml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_K32L2B31A_manifest_v3_10.xml new file mode 100644 index 0000000..f9cb434 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_K32L2B31A_manifest_v3_10.xml @@ -0,0 +1,260 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM34ZA5_manifest_v3_10.xml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM34ZA5_manifest_v3_10.xml new file mode 100644 index 0000000..6f386a4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM34ZA5_manifest_v3_10.xml @@ -0,0 +1,260 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM34ZA5_manifest_v3_13.xml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM34ZA5_manifest_v3_13.xml new file mode 100644 index 0000000..dac58b5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM34ZA5_manifest_v3_13.xml @@ -0,0 +1,234 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM35Z7_manifest_v3_10.xml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM35Z7_manifest_v3_10.xml new file mode 100644 index 0000000..3b0dfea --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM35Z7_manifest_v3_10.xml @@ -0,0 +1,262 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM35Z7_manifest_v3_13.xml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM35Z7_manifest_v3_13.xml new file mode 100644 index 0000000..911344d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM35Z7_manifest_v3_13.xml @@ -0,0 +1,236 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM35Z7_manifest_v3_14.xml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM35Z7_manifest_v3_14.xml new file mode 100644 index 0000000..a0b5d78 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKM35Z7_manifest_v3_14.xml @@ -0,0 +1,278 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKV11Z7_manifest_v3_10.xml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKV11Z7_manifest_v3_10.xml new file mode 100644 index 0000000..ed8fe8d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKV11Z7_manifest_v3_10.xml @@ -0,0 +1,262 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKV31F51212_manifest_v3_10.xml b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKV31F51212_manifest_v3_10.xml new file mode 100644 index 0000000..5088d40 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/manifests/middleware_amazon_freertos_kernel_MKV31F51212_manifest_v3_10.xml @@ -0,0 +1,260 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_K32L2A41A.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_K32L2A41A.cmake new file mode 100644 index 0000000..e09376a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_K32L2A41A.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0 +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_K32L2B31A.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_K32L2B31A.cmake new file mode 100644 index 0000000..e09376a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_K32L2B31A.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0 +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_K32L3A60_cm0plus.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_K32L3A60_cm0plus.cmake new file mode 100644 index 0000000..e09376a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_K32L3A60_cm0plus.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0 +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_K32L3A60_cm4.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_K32L3A60_cm4.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_K32L3A60_cm4.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC51U68.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC51U68.cmake new file mode 100644 index 0000000..e09376a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC51U68.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0 +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54114_cm0plus.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54114_cm0plus.cmake new file mode 100644 index 0000000..f1e0912 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54114_cm0plus.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0 +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54114_cm4.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54114_cm4.cmake new file mode 100644 index 0000000..f425363 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54114_cm4.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54628.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54628.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54628.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54S018.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54S018.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54S018.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54S018M.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54S018M.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC54S018M.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/middleware_freertos-kernel_MIMXRT595S_cm33.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC5506CPXXXX.cmake similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/middleware_freertos-kernel_MIMXRT595S_cm33.cmake rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC5506CPXXXX.cmake diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S06.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S06.cmake new file mode 100644 index 0000000..862b36f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S06.cmake @@ -0,0 +1,20 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S16.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S16.cmake new file mode 100644 index 0000000..862b36f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S16.cmake @@ -0,0 +1,20 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S28.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S28.cmake new file mode 100644 index 0000000..862b36f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S28.cmake @@ -0,0 +1,20 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S36.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S36.cmake new file mode 100644 index 0000000..862b36f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S36.cmake @@ -0,0 +1,20 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S69_cm33_core0.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S69_cm33_core0.cmake new file mode 100644 index 0000000..862b36f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S69_cm33_core0.cmake @@ -0,0 +1,20 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S69_cm33_core1.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S69_cm33_core1.cmake new file mode 100644 index 0000000..862b36f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_LPC55S69_cm33_core1.cmake @@ -0,0 +1,20 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MCIMX7U5.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MCIMX7U5.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MCIMX7U5.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8ML8.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8ML8.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8ML8.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8MM6.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8MM6.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8MM6.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8MN6.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8MN6.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8MN6.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8MQ6.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8MQ6.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8MQ6.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8QM6_cm4_core0.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8QM6_cm4_core0.cmake new file mode 100644 index 0000000..f425363 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8QM6_cm4_core0.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8QM6_cm4_core1.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8QM6_cm4_core1.cmake new file mode 100644 index 0000000..f425363 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8QM6_cm4_core1.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8QX6.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8QX6.cmake new file mode 100644 index 0000000..f425363 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMX8QX6.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1011.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1011.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1011.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1015.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1015.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1015.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1021.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1021.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1021.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1024.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1024.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1024.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1042.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1042.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1042.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1052.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1052.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1052.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1062.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1062.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1062.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1064.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1064.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1064.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1166_cm4.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1166_cm4.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1166_cm4.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1166_cm7.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1166_cm7.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1166_cm7.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_MIMXRT1176_cm4.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1176_cm4.cmake similarity index 75% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_MIMXRT1176_cm4.cmake rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1176_cm4.cmake index 2c75bed..0815f49 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_MIMXRT1176_cm4.cmake +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1176_cm4.cmake @@ -1,4 +1,5 @@ -include_guard() +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) message("middleware_freertos-kernel component is included.") target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE @@ -12,12 +13,10 @@ target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE ${CMAKE_CURRENT_LIST_DIR}/timers.c ) - -target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC ${CMAKE_CURRENT_LIST_DIR}/include ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F ) -include(middleware_freertos-kernel_extension_MIMXRT1176_cm4) - +include(middleware_freertos-kernel_extension) diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_MIMXRT1176_cm7.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1176_cm7.cmake similarity index 75% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_MIMXRT1176_cm7.cmake rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1176_cm7.cmake index 6f4e42f..0815f49 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_MIMXRT1176_cm7.cmake +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT1176_cm7.cmake @@ -1,4 +1,5 @@ -include_guard() +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) message("middleware_freertos-kernel component is included.") target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE @@ -12,12 +13,10 @@ target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE ${CMAKE_CURRENT_LIST_DIR}/timers.c ) - -target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC ${CMAKE_CURRENT_LIST_DIR}/include ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F ) -include(middleware_freertos-kernel_extension_MIMXRT1176_cm7) - +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT595S_cm33.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT595S_cm33.cmake new file mode 100644 index 0000000..862b36f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT595S_cm33.cmake @@ -0,0 +1,20 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT685S_cm33.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT685S_cm33.cmake new file mode 100644 index 0000000..862b36f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MIMXRT685S_cm33.cmake @@ -0,0 +1,20 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MK22F51212.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MK22F51212.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MK22F51212.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MK28FA15.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MK28FA15.cmake new file mode 100644 index 0000000..f425363 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MK28FA15.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MK64F12.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MK64F12.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MK64F12.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MK66F18.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MK66F18.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MK66F18.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKE15Z7.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKE15Z7.cmake new file mode 100644 index 0000000..e09376a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKE15Z7.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0 +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKE16Z4.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKE16Z4.cmake new file mode 100644 index 0000000..e09376a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKE16Z4.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0 +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKE17Z7.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKE17Z7.cmake new file mode 100644 index 0000000..e09376a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKE17Z7.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0 +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKL27Z644.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKL27Z644.cmake new file mode 100644 index 0000000..f1e0912 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKL27Z644.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0 +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKM34Z7.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKM34Z7.cmake new file mode 100644 index 0000000..e09376a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKM34Z7.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0 +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKM34ZA5.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKM34ZA5.cmake new file mode 100644 index 0000000..e09376a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKM34ZA5.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0 +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKM35Z7.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKM35Z7.cmake new file mode 100644 index 0000000..e09376a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKM35Z7.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0 +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKV11Z7.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKV11Z7.cmake new file mode 100644 index 0000000..e09376a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKV11Z7.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM0 +) + + +include(middleware_freertos-kernel_extension) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKV31F51212.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKV31F51212.cmake new file mode 100644 index 0000000..0815f49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_MKV31F51212.cmake @@ -0,0 +1,22 @@ +#Description: FreeRTOS kernel; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/croutine.c + ${CMAKE_CURRENT_LIST_DIR}/event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/list.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F/port.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ${CMAKE_CURRENT_LIST_DIR}/stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/tasks.c + ${CMAKE_CURRENT_LIST_DIR}/timers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/include + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM4F +) + + +include(middleware_freertos-kernel_extension) diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/middleware_freertos-kernel_cm33_nonsecure_port.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_cm33_nonsecure_port.cmake similarity index 93% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/middleware_freertos-kernel_cm33_nonsecure_port.cmake rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_cm33_nonsecure_port.cmake index 0ab475f..3d2f659 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/middleware_freertos-kernel_cm33_nonsecure_port.cmake +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_cm33_nonsecure_port.cmake @@ -12,9 +12,6 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC ) #OR Logic component -if(${MCUX_DEVICE} STREQUAL "LPC55S36") - include(middleware_freertos-kernel_LPC55S36) -endif() if(${MCUX_DEVICE} STREQUAL "LPC5506CPXXXX") include(middleware_freertos-kernel_LPC5506CPXXXX) endif() diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_cm33_secure_port.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_cm33_secure_port.cmake new file mode 100644 index 0000000..89bd736 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_cm33_secure_port.cmake @@ -0,0 +1,16 @@ +#Description: FreeRTOS cm33 secure port; user_visible: False +include_guard(GLOBAL) +message("middleware_freertos-kernel_cm33_secure_port component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM33/non_secure/port.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM33/non_secure/portasm.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM33/non_secure + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM33/secure +) + + +include(middleware_freertos-kernel_mpu_wrappers) diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/middleware_freertos-kernel_extension.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_extension.cmake similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/middleware_freertos-kernel_extension.cmake rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_extension.cmake diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_1.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_1.cmake new file mode 100644 index 0000000..9d00d65 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_1.cmake @@ -0,0 +1,28 @@ +#Description: FreeRTOS heap 1; user_visible: False +include_guard(GLOBAL) +message("middleware_freertos-kernel_heap_1 component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/portable/MemMang/heap_1.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC +) + +#OR Logic component +if(${MCUX_DEVICE} STREQUAL "MK22F12810") + include(middleware_freertos-kernel_MK22F51212) +endif() +if(${MCUX_DEVICE} STREQUAL "MK22F51212") + include(middleware_freertos-kernel_MK22F51212) +endif() +if(${MCUX_DEVICE} STREQUAL "MK02F12810") + include(middleware_freertos-kernel_MK22F51212) +endif() +if(${MCUX_DEVICE} STREQUAL "MK22F25612") + include(middleware_freertos-kernel_MK22F51212) +endif() +if(${MCUX_DEVICE} STREQUAL "MK64F12") + include(middleware_freertos-kernel_MK64F12) +endif() + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_3.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_3.cmake new file mode 100644 index 0000000..184c547 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_3.cmake @@ -0,0 +1,166 @@ +#Description: FreeRTOS heap_3; user_visible: False +include_guard(GLOBAL) +message("middleware_freertos-kernel_heap_3 component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/portable/MemMang/heap_3.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC +) + +#OR Logic component +if(${MCUX_DEVICE} STREQUAL "MIMXRT1166_cm4") + include(middleware_freertos-kernel_MIMXRT1166_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1166_cm7") + include(middleware_freertos-kernel_MIMXRT1166_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1052") + include(middleware_freertos-kernel_MIMXRT1052) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT633S_cm33") + include(middleware_freertos-kernel_MIMXRT685S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1064") + include(middleware_freertos-kernel_MIMXRT1064) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54607") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54S016") + include(middleware_freertos-kernel_LPC54S018) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54606") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54616") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "MKE16Z4") + include(middleware_freertos-kernel_MKE16Z4) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54016") + include(middleware_freertos-kernel_LPC54S018) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54018") + include(middleware_freertos-kernel_LPC54S018) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54628") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1173_cm4") + include(middleware_freertos-kernel_MIMXRT1176_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1173_cm7") + include(middleware_freertos-kernel_MIMXRT1176_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54605") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1051") + include(middleware_freertos-kernel_MIMXRT1052) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54618") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1021") + include(middleware_freertos-kernel_MIMXRT1021) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT555S_cm33") + include(middleware_freertos-kernel_MIMXRT595S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54018M") + include(middleware_freertos-kernel_LPC54S018M) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1062") + include(middleware_freertos-kernel_MIMXRT1062) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54S018") + include(middleware_freertos-kernel_LPC54S018) +endif() +if(${MCUX_DEVICE} STREQUAL "MKE15Z4") + include(middleware_freertos-kernel_MKE16Z4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1042") + include(middleware_freertos-kernel_MIMXRT1042) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1176_cm4") + include(middleware_freertos-kernel_MIMXRT1176_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1176_cm7") + include(middleware_freertos-kernel_MIMXRT1176_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1175_cm4") + include(middleware_freertos-kernel_MIMXRT1176_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1175_cm7") + include(middleware_freertos-kernel_MIMXRT1176_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54S018M") + include(middleware_freertos-kernel_LPC54S018M) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1061") + include(middleware_freertos-kernel_MIMXRT1062) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1165_cm4") + include(middleware_freertos-kernel_MIMXRT1166_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1165_cm7") + include(middleware_freertos-kernel_MIMXRT1166_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54S005") + include(middleware_freertos-kernel_LPC54S018) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1171_cm7") + include(middleware_freertos-kernel_MIMXRT1176_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1024") + include(middleware_freertos-kernel_MIMXRT1024) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54005") + include(middleware_freertos-kernel_LPC54S018) +endif() +if(${MCUX_DEVICE} STREQUAL "MKE14Z4") + include(middleware_freertos-kernel_MKE16Z4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT533S_cm33") + include(middleware_freertos-kernel_MIMXRT595S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54608") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33") + include(middleware_freertos-kernel_MIMXRT685S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT595S_cm33") + include(middleware_freertos-kernel_MIMXRT595S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1172_cm7") + include(middleware_freertos-kernel_MIMXRT1176_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "MK64F12") + include(middleware_freertos-kernel_MK64F12) +endif() +if(${MCUX_DEVICE} STREQUAL "MK66F18") + include(middleware_freertos-kernel_MK66F18) +endif() +if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus") + include(middleware_freertos-kernel_K32L3A60_cm0plus) +endif() +if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4") + include(middleware_freertos-kernel_K32L3A60_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54114_cm0plus") + include(middleware_freertos-kernel_LPC54114_cm0plus) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54114_cm4") + include(middleware_freertos-kernel_LPC54114_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0") + include(middleware_freertos-kernel_LPC55S69_cm33_core0) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core1") + include(middleware_freertos-kernel_LPC55S69_cm33_core1) +endif() + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_4.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_4.cmake new file mode 100644 index 0000000..c82cdd4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_4.cmake @@ -0,0 +1,391 @@ +#Description: FreeRTOS heap 4; user_visible: False +include_guard(GLOBAL) +message("middleware_freertos-kernel_heap_4 component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/portable/MemMang/heap_4.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC +) + +#OR Logic component +if(${MCUX_DEVICE} STREQUAL "MIMXRT1166_cm4") + include(middleware_freertos-kernel_MIMXRT1166_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1166_cm7") + include(middleware_freertos-kernel_MIMXRT1166_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC5506CPXXXX") + include(middleware_freertos-kernel_LPC5506CPXXXX) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1052") + include(middleware_freertos-kernel_MIMXRT1052) +endif() +if(${MCUX_DEVICE} STREQUAL "MK22F12810") + include(middleware_freertos-kernel_MK22F51212) +endif() +if(${MCUX_DEVICE} STREQUAL "MKV10Z1287") + include(middleware_freertos-kernel_MKV11Z7) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT633S_cm33") + include(middleware_freertos-kernel_MIMXRT685S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1064") + include(middleware_freertos-kernel_MIMXRT1064) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC5526") + include(middleware_freertos-kernel_LPC55S28) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC5504CPXXXX") + include(middleware_freertos-kernel_LPC5506CPXXXX) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54607") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54S016") + include(middleware_freertos-kernel_LPC54S018) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54606") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54616") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MN5") + include(middleware_freertos-kernel_MIMX8MN6) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MN4") + include(middleware_freertos-kernel_MIMX8MN6) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6") + include(middleware_freertos-kernel_MIMX8MQ6) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MM6") + include(middleware_freertos-kernel_MIMX8MM6) +endif() +if(${MCUX_DEVICE} STREQUAL "MKE15Z7") + include(middleware_freertos-kernel_MKE15Z7) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S04") + include(middleware_freertos-kernel_LPC55S06) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MM1") + include(middleware_freertos-kernel_MIMX8MM6) +endif() +if(${MCUX_DEVICE} STREQUAL "K32L2B31A") + include(middleware_freertos-kernel_K32L2B31A) +endif() +if(${MCUX_DEVICE} STREQUAL "MKE16Z4") + include(middleware_freertos-kernel_MKE16Z4) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S06") + include(middleware_freertos-kernel_LPC55S06) +endif() +if(${MCUX_DEVICE} STREQUAL "MKM14ZA5") + include(middleware_freertos-kernel_MKM34ZA5) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54016") + include(middleware_freertos-kernel_LPC54S018) +endif() +if(${MCUX_DEVICE} STREQUAL "MKV11Z7") + include(middleware_freertos-kernel_MKV11Z7) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54018") + include(middleware_freertos-kernel_LPC54S018) +endif() +if(${MCUX_DEVICE} STREQUAL "MKV31F51212") + include(middleware_freertos-kernel_MKV31F51212) +endif() +if(${MCUX_DEVICE} STREQUAL "MKE12Z7") + include(middleware_freertos-kernel_MKE17Z7) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54628") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC5502CPXXXX") + include(middleware_freertos-kernel_LPC5506CPXXXX) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MM5") + include(middleware_freertos-kernel_MIMX8MM6) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC5512") + include(middleware_freertos-kernel_LPC55S16) +endif() +if(${MCUX_DEVICE} STREQUAL "MK22F51212") + include(middleware_freertos-kernel_MK22F51212) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MM2") + include(middleware_freertos-kernel_MIMX8MM6) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8ML3") + include(middleware_freertos-kernel_MIMX8ML8) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1173_cm4") + include(middleware_freertos-kernel_MIMXRT1176_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1173_cm7") + include(middleware_freertos-kernel_MIMXRT1176_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC5516") + include(middleware_freertos-kernel_LPC55S16) +endif() +if(${MCUX_DEVICE} STREQUAL "MKM34ZA5") + include(middleware_freertos-kernel_MKM34ZA5) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54605") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1051") + include(middleware_freertos-kernel_MIMXRT1052) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54618") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "MKE13Z7") + include(middleware_freertos-kernel_MKE17Z7) +endif() +if(${MCUX_DEVICE} STREQUAL "MKE14Z7") + include(middleware_freertos-kernel_MKE15Z7) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1021") + include(middleware_freertos-kernel_MIMXRT1021) +endif() +if(${MCUX_DEVICE} STREQUAL "MKV10Z7") + include(middleware_freertos-kernel_MKV11Z7) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MM3") + include(middleware_freertos-kernel_MIMX8MM6) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT555S_cm33") + include(middleware_freertos-kernel_MIMXRT595S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54018M") + include(middleware_freertos-kernel_LPC54S018M) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC5506") + include(middleware_freertos-kernel_LPC55S06) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC5514") + include(middleware_freertos-kernel_LPC55S16) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S16") + include(middleware_freertos-kernel_LPC55S16) +endif() +if(${MCUX_DEVICE} STREQUAL "K32L2B11A") + include(middleware_freertos-kernel_K32L2B31A) +endif() +if(${MCUX_DEVICE} STREQUAL "MK02F12810") + include(middleware_freertos-kernel_MK22F51212) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MQ7") + include(middleware_freertos-kernel_MIMX8MQ6) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1062") + include(middleware_freertos-kernel_MIMXRT1062) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MN6") + include(middleware_freertos-kernel_MIMX8MN6) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8ML6") + include(middleware_freertos-kernel_MIMX8ML8) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54S018") + include(middleware_freertos-kernel_LPC54S018) +endif() +if(${MCUX_DEVICE} STREQUAL "MKE15Z4") + include(middleware_freertos-kernel_MKE16Z4) +endif() +if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus") + include(middleware_freertos-kernel_K32L3A60_cm0plus) +endif() +if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4") + include(middleware_freertos-kernel_K32L3A60_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1042") + include(middleware_freertos-kernel_MIMXRT1042) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1176_cm4") + include(middleware_freertos-kernel_MIMXRT1176_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1176_cm7") + include(middleware_freertos-kernel_MIMXRT1176_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1175_cm4") + include(middleware_freertos-kernel_MIMXRT1176_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1175_cm7") + include(middleware_freertos-kernel_MIMXRT1176_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54S018M") + include(middleware_freertos-kernel_LPC54S018M) +endif() +if(${MCUX_DEVICE} STREQUAL "MK22F25612") + include(middleware_freertos-kernel_MK22F51212) +endif() +if(${MCUX_DEVICE} STREQUAL "MKM35Z7") + include(middleware_freertos-kernel_MKM35Z7) +endif() +if(${MCUX_DEVICE} STREQUAL "K32L2B21A") + include(middleware_freertos-kernel_K32L2B31A) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC51U68") + include(middleware_freertos-kernel_LPC51U68) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1061") + include(middleware_freertos-kernel_MIMXRT1062) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MN2") + include(middleware_freertos-kernel_MIMX8MN6) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC5528") + include(middleware_freertos-kernel_LPC55S28) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1165_cm4") + include(middleware_freertos-kernel_MIMXRT1166_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1165_cm7") + include(middleware_freertos-kernel_MIMXRT1166_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S66_cm33_core0") + include(middleware_freertos-kernel_LPC55S69_cm33_core0) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S66_cm33_core1") + include(middleware_freertos-kernel_LPC55S69_cm33_core1) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8ML4") + include(middleware_freertos-kernel_MIMX8ML8) +endif() +if(${MCUX_DEVICE} STREQUAL "MKM34Z7") + include(middleware_freertos-kernel_MKM34Z7) +endif() +if(${MCUX_DEVICE} STREQUAL "MKV31F12810") + include(middleware_freertos-kernel_MKV31F51212) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MD6") + include(middleware_freertos-kernel_MIMX8MQ6) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54S005") + include(middleware_freertos-kernel_LPC54S018) +endif() +if(${MCUX_DEVICE} STREQUAL "MKE17Z7") + include(middleware_freertos-kernel_MKE17Z7) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1171_cm7") + include(middleware_freertos-kernel_MIMXRT1176_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0") + include(middleware_freertos-kernel_LPC55S69_cm33_core0) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core1") + include(middleware_freertos-kernel_LPC55S69_cm33_core1) +endif() +if(${MCUX_DEVICE} STREQUAL "K32L2A31A") + include(middleware_freertos-kernel_K32L2A41A) +endif() +if(${MCUX_DEVICE} STREQUAL "MCIMX7U5") + include(middleware_freertos-kernel_MCIMX7U5) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1024") + include(middleware_freertos-kernel_MIMXRT1024) +endif() +if(${MCUX_DEVICE} STREQUAL "MKM33ZA5") + include(middleware_freertos-kernel_MKM34ZA5) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1011") + include(middleware_freertos-kernel_MIMXRT1011) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54005") + include(middleware_freertos-kernel_LPC54S018) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MM4") + include(middleware_freertos-kernel_MIMX8MM6) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S28") + include(middleware_freertos-kernel_LPC55S28) +endif() +if(${MCUX_DEVICE} STREQUAL "MKE14Z4") + include(middleware_freertos-kernel_MKE16Z4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MN1") + include(middleware_freertos-kernel_MIMX8MN6) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT533S_cm33") + include(middleware_freertos-kernel_MIMXRT595S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8ML8") + include(middleware_freertos-kernel_MIMX8ML8) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S14") + include(middleware_freertos-kernel_LPC55S16) +endif() +if(${MCUX_DEVICE} STREQUAL "MKV31F25612") + include(middleware_freertos-kernel_MKV31F51212) +endif() +if(${MCUX_DEVICE} STREQUAL "MKV30F12810") + include(middleware_freertos-kernel_MKV31F51212) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S26") + include(middleware_freertos-kernel_LPC55S28) +endif() +if(${MCUX_DEVICE} STREQUAL "K32L2A41A") + include(middleware_freertos-kernel_K32L2A41A) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC5504") + include(middleware_freertos-kernel_LPC55S06) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MN3") + include(middleware_freertos-kernel_MIMX8MN6) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54608") + include(middleware_freertos-kernel_LPC54628) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MD7") + include(middleware_freertos-kernel_MIMX8MQ6) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33") + include(middleware_freertos-kernel_MIMXRT685S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT595S_cm33") + include(middleware_freertos-kernel_MIMXRT595S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8MQ5") + include(middleware_freertos-kernel_MIMX8MQ6) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC5502") + include(middleware_freertos-kernel_LPC55S06) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1172_cm7") + include(middleware_freertos-kernel_MIMXRT1176_cm7) +endif() +if(${MCUX_DEVICE} STREQUAL "MCIMX7U3") + include(middleware_freertos-kernel_MCIMX7U5) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT1015") + include(middleware_freertos-kernel_MIMXRT1015) +endif() +if(${MCUX_DEVICE} STREQUAL "MK64F12") + include(middleware_freertos-kernel_MK64F12) +endif() +if(${MCUX_DEVICE} STREQUAL "MK66F18") + include(middleware_freertos-kernel_MK66F18) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC54114_cm4") + include(middleware_freertos-kernel_LPC54114_cm4) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0") + include(middleware_freertos-kernel_MIMX8QM6_cm4_core0) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core1") + include(middleware_freertos-kernel_MIMX8QM6_cm4_core1) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMX8QX6") + include(middleware_freertos-kernel_MIMX8QX6) +endif() +if(${MCUX_DEVICE} STREQUAL "MK28FA15") + include(middleware_freertos-kernel_MK28FA15) +endif() +if(${MCUX_DEVICE} STREQUAL "MKL27Z644") + include(middleware_freertos-kernel_MKL27Z644) +endif() + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_mpu_wrappers.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_mpu_wrappers.cmake new file mode 100644 index 0000000..fb061c2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_mpu_wrappers.cmake @@ -0,0 +1,34 @@ +#Description: FreeRTOS MPU wrappers; user_visible: False +include_guard(GLOBAL) +message("middleware_freertos-kernel_mpu_wrappers component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/portable/Common/mpu_wrappers.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC +) + +#OR Logic component +if(${MCUX_DEVICE} STREQUAL "MIMXRT633S_cm33") + include(middleware_freertos-kernel_MIMXRT685S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT555S_cm33") + include(middleware_freertos-kernel_MIMXRT595S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S66_cm33_core0") + include(middleware_freertos-kernel_LPC55S69_cm33_core0) +endif() +if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0") + include(middleware_freertos-kernel_LPC55S69_cm33_core0) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT533S_cm33") + include(middleware_freertos-kernel_MIMXRT595S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33") + include(middleware_freertos-kernel_MIMXRT685S_cm33) +endif() +if(${MCUX_DEVICE} STREQUAL "MIMXRT595S_cm33") + include(middleware_freertos-kernel_MIMXRT595S_cm33) +endif() + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_secure_context.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_secure_context.cmake new file mode 100644 index 0000000..dd77e6c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/middleware_freertos-kernel_secure_context.cmake @@ -0,0 +1,17 @@ +#Description: FreeRTOS Secure Context; user_visible: True +include_guard(GLOBAL) +message("middleware_freertos-kernel_secure_context component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM33/secure/secure_context.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM33/secure/secure_context_port.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM33/secure/secure_heap.c + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM33/secure/secure_init.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM33/non_secure + ${CMAKE_CURRENT_LIST_DIR}/portable/GCC/ARM_CM33/secure +) + + diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMClang/Use-the-GCC-ports.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMClang/Use-the-GCC-ports.txt similarity index 99% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMClang/Use-the-GCC-ports.txt rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMClang/Use-the-GCC-ports.txt index d2c3a86..4a23ecd 100644 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMClang/Use-the-GCC-ports.txt +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMClang/Use-the-GCC-ports.txt @@ -1,2 +1,2 @@ -The FreeRTOS GCC port layer also builds and works with the ARMClang compiler. +The FreeRTOS GCC port layer also builds and works with the ARMClang compiler. To use the ARMClang compiler build the port files from FreeRTOS/Source/portable/GCC. \ No newline at end of file diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/ReadMe.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/ReadMe.txt new file mode 100644 index 0000000..c0db145 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/ReadMe.txt @@ -0,0 +1,11 @@ +This directory tree contains the master copy of the FreeeRTOS Armv8-M and +Armv8.1-M ports. +Do not use the files located here! These file are copied into separate +FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to each +FreeRTOS release. + +If your Armv8-M and Armv8.1-M application uses TrustZone then use the files from the +FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories. + +If your Armv8-M and Armv8.1-M application does not use TrustZone then use the files from +the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories. diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/copy_files.py b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/copy_files.py new file mode 100644 index 0000000..5cf9e62 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/copy_files.py @@ -0,0 +1,152 @@ +#/* +# * FreeRTOS Kernel V10.5.1 +# * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# * +# * SPDX-License-Identifier: MIT +# * +# * Permission is hereby granted, free of charge, to any person obtaining a copy of +# * this software and associated documentation files (the "Software"), to deal in +# * the Software without restriction, including without limitation the rights to +# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +# * the Software, and to permit persons to whom the Software is furnished to do so, +# * subject to the following conditions: +# * +# * The above copyright notice and this permission notice shall be included in all +# * copies or substantial portions of the Software. +# * +# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# * +# * https://www.FreeRTOS.org +# * https://github.com/FreeRTOS +# * +# */ + +import os +import shutil + +_THIS_FILE_DIRECTORY_ = os.path.dirname(os.path.realpath(__file__)) +_FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_) + +_COMPILERS_ = ['GCC', 'IAR'] +_ARCH_NS_ = ['ARM_CM85', 'ARM_CM85_NTZ', 'ARM_CM55', 'ARM_CM55_NTZ', 'ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ'] +_ARCH_S_ = ['ARM_CM85', 'ARM_CM55', 'ARM_CM33', 'ARM_CM23'] + +# Files to be compiled in the Secure Project +_SECURE_COMMON_FILE_PATHS_ = [ + os.path.join('secure', 'context'), + os.path.join('secure', 'heap'), + os.path.join('secure', 'init'), + os.path.join('secure', 'macros') +] + +_SECURE_PORTABLE_FILE_PATHS_ = { + 'GCC':{ + 'ARM_CM23':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM23')], + 'ARM_CM33':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')], + 'ARM_CM55':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')], + 'ARM_CM85':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')] + }, + 'IAR':{ + 'ARM_CM23':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM23')], + 'ARM_CM33':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')], + 'ARM_CM55':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')], + 'ARM_CM85':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')] + } +} + +# Files to be compiled in the Non-Secure Project +_NONSECURE_COMMON_FILE_PATHS_ = [ + 'non_secure' +] + +_NONSECURE_PORTABLE_FILE_PATHS_ = { + 'GCC':{ + 'ARM_CM23' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM23')], + 'ARM_CM23_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM23_NTZ')], + 'ARM_CM33' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33')], + 'ARM_CM33_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ')], + 'ARM_CM55' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM55', 'portmacro.h')], + 'ARM_CM55_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM55', 'portmacro.h')], + 'ARM_CM85' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM85', 'portmacro.h')], + 'ARM_CM85_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM85', 'portmacro.h')] + }, + 'IAR':{ + 'ARM_CM23' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM23')], + 'ARM_CM23_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM23_NTZ')], + 'ARM_CM33' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33')], + 'ARM_CM33_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ')], + 'ARM_CM55' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM55', 'portmacro.h')], + 'ARM_CM55_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM55', 'portmacro.h')], + 'ARM_CM85' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM85', 'portmacro.h')], + 'ARM_CM85_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM85', 'portmacro.h')] + }, +} + + +def copy_files_in_dir(src_abs_path, dst_abs_path): + if os.path.isfile(src_abs_path): + print('Src: {}'.format(src_abs_path)) + print('Dst: {}\n'.format(dst_abs_path)) + shutil.copy2(src_abs_path, dst_abs_path) + else: + for src_file in os.listdir(src_abs_path): + src_file_abs_path = os.path.join(src_abs_path, src_file) + if os.path.isfile(src_file_abs_path) and src_file != 'ReadMe.txt': + if not os.path.exists(dst_abs_path): + os.makedirs(dst_abs_path) + print('Src: {}'.format(src_file_abs_path)) + print('Dst: {}\n'.format(dst_abs_path)) + shutil.copy2(src_file_abs_path, dst_abs_path) + + +def copy_common_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path): + for src_path in src_paths: + + src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path) + dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, compiler, arch, dst_path) + + copy_files_in_dir(src_abs_path, dst_abs_path) + + +def copy_portable_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path): + for src_path in src_paths[compiler][arch]: + + src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path) + dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, compiler, arch, dst_path) + + copy_files_in_dir(src_abs_path, dst_abs_path) + + +def copy_files(): + # Copy Secure Files + for compiler in _COMPILERS_: + for arch in _ARCH_S_: + copy_common_files_for_compiler_and_arch(compiler, arch, _SECURE_COMMON_FILE_PATHS_, 'secure') + copy_portable_files_for_compiler_and_arch(compiler, arch, _SECURE_PORTABLE_FILE_PATHS_, 'secure') + + # Copy Non-Secure Files + for compiler in _COMPILERS_: + for arch in _ARCH_NS_: + copy_common_files_for_compiler_and_arch(compiler, arch, _NONSECURE_COMMON_FILE_PATHS_, 'non_secure') + copy_portable_files_for_compiler_and_arch(compiler, arch, _NONSECURE_PORTABLE_FILE_PATHS_, 'non_secure') + + +def main(): + copy_files() + + +if __name__ == '__main__': + main() diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/ReadMe.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/ReadMe.txt new file mode 100644 index 0000000..68ff904 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/ReadMe.txt @@ -0,0 +1,11 @@ +This directory tree contains the master copy of the FreeRTOS Armv8-M and +Armv8.1-M ports. +Do not use the files located here! These file are copied into separate +FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to +each FreeRTOS release. + +If your Armv8-M/Armv8.1-M application uses TrustZone then use the files from the +FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories. + +If your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from +the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories. diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/port.c new file mode 100644 index 0000000..349aeff --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/port.c @@ -0,0 +1,1261 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c new file mode 100644 index 0000000..74e7b9e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c @@ -0,0 +1,478 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif + +void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " movs r5, #1 \n"/* r5 = 1. */ + " bics r4, r5 \n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */ + " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + " movs r5, #4 \n"/* r5 = 4. */ + " str r5, [r2] \n"/* Program RNR = 4. */ + " ldmia r3!, {r6,r7} \n"/* Read first set of RBAR/RLAR from TCB. */ + " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */ + " stmia r4!, {r6,r7} \n"/* Write first set of RBAR/RLAR registers. */ + " movs r5, #5 \n"/* r5 = 5. */ + " str r5, [r2] \n"/* Program RNR = 5. */ + " ldmia r3!, {r6,r7} \n"/* Read second set of RBAR/RLAR from TCB. */ + " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */ + " stmia r4!, {r6,r7} \n"/* Write second set of RBAR/RLAR registers. */ + " movs r5, #6 \n"/* r5 = 6. */ + " str r5, [r2] \n"/* Program RNR = 6. */ + " ldmia r3!, {r6,r7} \n"/* Read third set of RBAR/RLAR from TCB. */ + " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */ + " stmia r4!, {r6,r7} \n"/* Write third set of RBAR/RLAR registers. */ + " movs r5, #7 \n"/* r5 = 7. */ + " str r5, [r2] \n"/* Program RNR = 7. */ + " ldmia r3!, {r6,r7} \n"/* Read fourth set of RBAR/RLAR from TCB. */ + " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */ + " stmia r4!, {r6,r7} \n"/* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " movs r5, #1 \n"/* r5 = 1. */ + " orrs r4, r5 \n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + " ldr r5, xSecureContextConst2 \n" + " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n"/* Set this task's PSPLIM value. */ + " msr control, r3 \n"/* Set this task's CONTROL value. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " bx r4 \n"/* Finally, branch to EXC_RETURN. */ + #else /* configENABLE_MPU */ + " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, xSecureContextConst2 \n" + " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n"/* Set this task's PSPLIM value. */ + " movs r1, #2 \n"/* r1 = 2. */ + " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " bx r3 \n"/* Finally, branch to EXC_RETURN. */ + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + "xSecureContextConst2: .word xSecureContext \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst2: .word 0xe000ed94 \n" + "xMAIR0Const2: .word 0xe000edc0 \n" + "xRNRConst2: .word 0xe000ed98 \n" + "xRBARConst2: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " movs r1, #1 \n"/* r1 = 1. */ + " tst r0, r1 \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + " beq running_privileged \n"/* If the result of previous AND operation was 0, branch. */ + " movs r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " bx lr \n"/* Return. */ + " running_privileged: \n" + " movs r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* Read the CONTROL register. */ + " movs r1, #1 \n"/* r1 = 1. */ + " bics r0, r1 \n"/* Clear the bit 0. */ + " msr control, r0 \n"/* Write back the new CONTROL value. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " movs r1, #1 \n"/* r1 = 1. */ + " orrs r0, r1 \n"/* r0 = r0 | r1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + "xVTORConst: .word 0xe000ed08 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, PRIMASK \n" + " cpsid i \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr PRIMASK, r0 \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/ + " mrs r2, psp \n"/* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n"/* No secure context to save. */ + " push {r0-r2, r14} \n" + " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r3} \n"/* LR is now in r3. */ + " mov lr, r3 \n"/* LR = r3. */ + " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + #if ( configENABLE_MPU == 1 ) + " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r3, control \n"/* r3 = CONTROL. */ + " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + " b select_next_task \n" + " \n" + " save_ns_context: \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + #if ( configENABLE_MPU == 1 ) + " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " adds r2, r2, #16 \n"/* r2 = r2 + 16. */ + " stmia r2!, {r4-r7} \n"/* Store the low registers that are not saved automatically. */ + " mov r4, r8 \n"/* r4 = r8. */ + " mov r5, r9 \n"/* r5 = r9. */ + " mov r6, r10 \n"/* r6 = r10. */ + " mov r7, r11 \n"/* r7 = r11. */ + " stmia r2!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r3, control \n"/* r3 = CONTROL. */ + " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */ + " subs r2, r2, #48 \n"/* r2 = r2 - 48. */ + " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3-r7} \n"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ + " mov r4, r8 \n"/* r4 = r8. */ + " mov r5, r9 \n"/* r5 = r9. */ + " mov r6, r10 \n"/* r6 = r10. */ + " mov r7, r11 \n"/* r7 = r11. */ + " stmia r2!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */ + #endif /* configENABLE_MPU */ + " \n" + " select_next_task: \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */ + " movs r5, #1 \n"/* r5 = 1. */ + " bics r4, r5 \n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */ + " str r4, [r3] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */ + " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r3] \n"/* Program MAIR0. */ + " ldr r4, xRNRConst \n"/* r4 = 0xe000ed98 [Location of RNR]. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " movs r5, #4 \n"/* r5 = 4. */ + " str r5, [r4] \n"/* Program RNR = 4. */ + " ldmia r1!, {r6,r7} \n"/* Read first set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r6,r7} \n"/* Write first set of RBAR/RLAR registers. */ + " movs r5, #5 \n"/* r5 = 5. */ + " str r5, [r4] \n"/* Program RNR = 5. */ + " ldmia r1!, {r6,r7} \n"/* Read second set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r6,r7} \n"/* Write second set of RBAR/RLAR registers. */ + " movs r5, #6 \n"/* r5 = 6. */ + " str r5, [r4] \n"/* Program RNR = 6. */ + " ldmia r1!, {r6,r7} \n"/* Read third set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r6,r7} \n"/* Write third set of RBAR/RLAR registers. */ + " movs r5, #7 \n"/* r5 = 7. */ + " str r5, [r4] \n"/* Program RNR = 7. */ + " ldmia r1!, {r6,r7} \n"/* Read fourth set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r6,r7} \n"/* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */ + " movs r5, #1 \n"/* r5 = 1. */ + " orrs r4, r5 \n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */ + " str r4, [r3] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " msr control, r3 \n"/* Restore the CONTROL register value for the task. */ + " mov lr, r4 \n"/* LR = r4. */ + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n"/* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n"/* LR = r4. */ + " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + #else /* configENABLE_MPU */ + " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " mov lr, r4 \n"/* LR = r4. */ + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n"/* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n"/* LR = r4. */ + " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + #endif /* configENABLE_MPU */ + " \n" + " restore_ns_context: \n" + " adds r2, r2, #16 \n"/* Move to the high registers. */ + " ldmia r2!, {r4-r7} \n"/* Restore the high registers that are not automatically restored. */ + " mov r8, r4 \n"/* r8 = r4. */ + " mov r9, r5 \n"/* r9 = r5. */ + " mov r10, r6 \n"/* r10 = r6. */ + " mov r11, r7 \n"/* r11 = r7. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " subs r2, r2, #32 \n"/* Go back to the low registers. */ + " ldmia r2!, {r4-r7} \n"/* Restore the low registers that are not automatically restored. */ + " bx lr \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + "xSecureContextConst: .word xSecureContext \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst: .word 0xe000ed94 \n" + "xMAIR0Const: .word 0xe000edc0 \n" + "xRNRConst: .word 0xe000ed98 \n" + "xRBARConst: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " movs r0, #4 \n" + " mov r1, lr \n" + " tst r0, r1 \n" + " beq stacking_used_msp \n" + " mrs r0, psp \n" + " ldr r2, svchandler_address_const \n" + " bx r2 \n" + " stacking_used_msp: \n" + " mrs r0, msp \n" + " ldr r2, svchandler_address_const \n" + " bx r2 \n" + " \n" + " .align 4 \n" + "svchandler_address_const: .word vPortSVCHandler_C \n" + ); +} +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n"/* Secure context is allocated in the supervisor call. */ + " bx lr \n"/* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */ + " bne free_secure_context \n"/* Branch if r1 != 0. */ + " bx lr \n"/* There is no secure context (xSecureContext is NULL). */ + " free_secure_context: \n" + " svc %0 \n"/* Secure context is freed in the supervisor call. */ + " bx lr \n"/* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h new file mode 100644 index 0000000..7cca20a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h @@ -0,0 +1,71 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c new file mode 100644 index 0000000..2a81873 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c @@ -0,0 +1,381 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif + +void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " movs r4, #1 \n"/* r4 = 1. */ + " bics r3, r4 \n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */ + " str r3, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */ + " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " movs r4, #4 \n"/* r4 = 4. */ + " str r4, [r2] \n"/* Program RNR = 4. */ + " ldmia r1!, {r5,r6} \n"/* Read first set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write first set of RBAR/RLAR registers. */ + " movs r4, #5 \n"/* r4 = 5. */ + " str r4, [r2] \n"/* Program RNR = 5. */ + " ldmia r1!, {r5,r6} \n"/* Read second set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write second set of RBAR/RLAR registers. */ + " movs r4, #6 \n"/* r4 = 6. */ + " str r4, [r2] \n"/* Program RNR = 6. */ + " ldmia r1!, {r5,r6} \n"/* Read third set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write third set of RBAR/RLAR registers. */ + " movs r4, #7 \n"/* r4 = 7. */ + " str r4, [r2] \n"/* Program RNR = 7. */ + " ldmia r1!, {r5,r6} \n"/* Read fourth set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " movs r4, #1 \n"/* r4 = 1. */ + " orrs r3, r4 \n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */ + " str r3, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " msr control, r2 \n"/* Set this task's CONTROL value. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " bx r3 \n"/* Finally, branch to EXC_RETURN. */ + #else /* configENABLE_MPU */ + " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " movs r1, #2 \n"/* r1 = 2. */ + " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " bx r2 \n"/* Finally, branch to EXC_RETURN. */ + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst2: .word 0xe000ed94 \n" + "xMAIR0Const2: .word 0xe000edc0 \n" + "xRNRConst2: .word 0xe000ed98 \n" + "xRBARConst2: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " movs r1, #1 \n"/* r1 = 1. */ + " tst r0, r1 \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + " beq running_privileged \n"/* If the result of previous AND operation was 0, branch. */ + " movs r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " bx lr \n"/* Return. */ + " running_privileged: \n" + " movs r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* Read the CONTROL register. */ + " movs r1, #1 \n"/* r1 = 1. */ + " bics r0, r1 \n"/* Clear the bit 0. */ + " msr control, r0 \n"/* Write back the new CONTROL value. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " movs r1, #1 \n"/* r1 = 1. */ + " orrs r0, r1 \n"/* r0 = r0 | r1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + "xVTORConst: .word 0xe000ed08 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, PRIMASK \n" + " cpsid i \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr PRIMASK, r0 \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n"/* Read PSP in r0. */ + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + #if ( configENABLE_MPU == 1 ) + " subs r0, r0, #44 \n"/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + " str r0, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r2, control \n"/* r2 = CONTROL. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmia r0!, {r1-r7} \n"/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */ + " mov r4, r8 \n"/* r4 = r8. */ + " mov r5, r9 \n"/* r5 = r9. */ + " mov r6, r10 \n"/* r6 = r10. */ + " mov r7, r11 \n"/* r7 = r11. */ + " stmia r0!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */ + #else /* configENABLE_MPU */ + " subs r0, r0, #40 \n"/* Make space for PSPLIM, LR and the remaining registers on the stack. */ + " str r0, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r2, psplim \n"/* r2 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmia r0!, {r2-r7} \n"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ + " mov r4, r8 \n"/* r4 = r8. */ + " mov r5, r9 \n"/* r5 = r9. */ + " mov r6, r10 \n"/* r6 = r10. */ + " mov r7, r11 \n"/* r7 = r11. */ + " stmia r0!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */ + #endif /* configENABLE_MPU */ + " \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " movs r4, #1 \n"/* r4 = 1. */ + " bics r3, r4 \n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */ + " str r3, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */ + " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " movs r4, #4 \n"/* r4 = 4. */ + " str r4, [r2] \n"/* Program RNR = 4. */ + " ldmia r1!, {r5,r6} \n"/* Read first set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write first set of RBAR/RLAR registers. */ + " movs r4, #5 \n"/* r4 = 5. */ + " str r4, [r2] \n"/* Program RNR = 5. */ + " ldmia r1!, {r5,r6} \n"/* Read second set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write second set of RBAR/RLAR registers. */ + " movs r4, #6 \n"/* r4 = 6. */ + " str r4, [r2] \n"/* Program RNR = 6. */ + " ldmia r1!, {r5,r6} \n"/* Read third set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write third set of RBAR/RLAR registers. */ + " movs r4, #7 \n"/* r4 = 7. */ + " str r4, [r2] \n"/* Program RNR = 7. */ + " ldmia r1!, {r5,r6} \n"/* Read fourth set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " movs r4, #1 \n"/* r4 = 1. */ + " orrs r3, r4 \n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */ + " str r3, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " adds r0, r0, #28 \n"/* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n"/* Restore the high registers that are not automatically restored. */ + " mov r8, r4 \n"/* r8 = r4. */ + " mov r9, r5 \n"/* r9 = r5. */ + " mov r10, r6 \n"/* r10 = r6. */ + " mov r11, r7 \n"/* r11 = r7. */ + " msr psp, r0 \n"/* Remember the new top of stack for the task. */ + " subs r0, r0, #44 \n"/* Move to the starting of the saved context. */ + " ldmia r0!, {r1-r7} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " msr control, r2 \n"/* Restore the CONTROL register value for the task. */ + " bx r3 \n" + #else /* configENABLE_MPU */ + " adds r0, r0, #24 \n"/* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n"/* Restore the high registers that are not automatically restored. */ + " mov r8, r4 \n"/* r8 = r4. */ + " mov r9, r5 \n"/* r9 = r5. */ + " mov r10, r6 \n"/* r10 = r6. */ + " mov r11, r7 \n"/* r11 = r7. */ + " msr psp, r0 \n"/* Remember the new top of stack for the task. */ + " subs r0, r0, #40 \n"/* Move to the starting of the saved context. */ + " ldmia r0!, {r2-r7} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ + " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */ + " bx r3 \n" + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst: .word 0xe000ed94 \n" + "xMAIR0Const: .word 0xe000edc0 \n" + "xRNRConst: .word 0xe000ed98 \n" + "xRBARConst: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " movs r0, #4 \n" + " mov r1, lr \n" + " tst r0, r1 \n" + " beq stacking_used_msp \n" + " mrs r0, psp \n" + " ldr r2, svchandler_address_const \n" + " bx r2 \n" + " stacking_used_msp: \n" + " mrs r0, msp \n" + " ldr r2, svchandler_address_const \n" + " bx r2 \n" + " \n" + " .align 4 \n" + "svchandler_address_const: .word vPortSVCHandler_C \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h new file mode 100644 index 0000000..7cca20a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h @@ -0,0 +1,71 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c new file mode 100644 index 0000000..df117af --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c @@ -0,0 +1,470 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */ + " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #4 \n"/* r4 = 4. */ + " str r4, [r2] \n"/* Program RNR = 4. */ + " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #8 \n"/* r4 = 8. */ + " str r4, [r2] \n"/* Program RNR = 8. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #12 \n"/* r4 = 12. */ + " str r4, [r2] \n"/* Program RNR = 12. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + " ldr r5, xSecureContextConst2 \n" + " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n"/* Set this task's PSPLIM value. */ + " msr control, r3 \n"/* Set this task's CONTROL value. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r4 \n"/* Finally, branch to EXC_RETURN. */ + #else /* configENABLE_MPU */ + " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, xSecureContextConst2 \n" + " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n"/* Set this task's PSPLIM value. */ + " movs r1, #2 \n"/* r1 = 2. */ + " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n"/* Finally, branch to EXC_RETURN. */ + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + "xSecureContextConst2: .word xSecureContext \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst2: .word 0xe000ed94 \n" + "xMAIR0Const2: .word 0xe000edc0 \n" + "xRNRConst2: .word 0xe000ed98 \n" + "xRBARConst2: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* Read the CONTROL register. */ + " bic r0, #1 \n"/* Clear the bit 0. */ + " msr control, r0 \n"/* Write back the new CONTROL value. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " orr r0, #1 \n"/* r0 = r0 | 1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + "xVTORConst: .word 0xe000ed08 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n"/* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " mrs r2, psp \n"/* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n"/* No secure context to save. */ + " push {r0-r2, r14} \n" + " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r3} \n"/* LR is now in r3. */ + " mov lr, r3 \n"/* LR = r3. */ + " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB.*/ + #if ( configENABLE_MPU == 1 ) + " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r3, control \n"/* r3 = CONTROL. */ + " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + " b select_next_task \n" + " \n" + " save_ns_context: \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( configENABLE_MPU == 1 ) + " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " adds r2, r2, #16 \n"/* r2 = r2 + 16. */ + " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r3, control \n"/* r3 = CONTROL. */ + " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */ + " subs r2, r2, #16 \n"/* r2 = r2 - 16. */ + " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " adds r2, r2, #12 \n"/* r2 = r2 + 12. */ + " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " subs r2, r2, #12 \n"/* r2 = r2 - 12. */ + " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n"/* r0 = 0. */ + " msr basepri, r0 \n"/* Enable interrupts. */ + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r3] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */ + " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r3] \n"/* Program MAIR0. */ + " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #4 \n"/* r4 = 4. */ + " str r4, [r3] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #8 \n"/* r4 = 8. */ + " str r4, [r3] \n"/* Program RNR = 8. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #12 \n"/* r4 = 12. */ + " str r4, [r3] \n"/* Program RNR = 12. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r3] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " msr control, r3 \n"/* Restore the CONTROL register value for the task. */ + " mov lr, r4 \n"/* LR = r4. */ + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n"/* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n"/* LR = r4. */ + " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + #else /* configENABLE_MPU */ + " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " mov lr, r4 \n"/* LR = r4. */ + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n"/* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n"/* LR = r4. */ + " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + #endif /* configENABLE_MPU */ + " \n" + " restore_ns_context: \n" + " ldmia r2!, {r4-r11} \n"/* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + "xSecureContextConst: .word xSecureContext \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst: .word 0xe000ed94 \n" + "xMAIR0Const: .word 0xe000edc0 \n" + "xRNRConst: .word 0xe000ed98 \n" + "xRBARConst: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, svchandler_address_const \n" + " bx r1 \n" + " \n" + " .align 4 \n" + "svchandler_address_const: .word vPortSVCHandler_C \n" + ); +} +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n"/* Secure context is allocated in the supervisor call. */ + " bx lr \n"/* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */ + " it ne \n" + " svcne %0 \n"/* Secure context is freed in the supervisor call. */ + " bx lr \n"/* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h new file mode 100644 index 0000000..1f3d964 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c new file mode 100644 index 0000000..660e942 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c @@ -0,0 +1,365 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */ + " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r3, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #4 \n"/* r3 = 4. */ + " str r3, [r2] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #8 \n"/* r3 = 8. */ + " str r3, [r2] \n"/* Program RNR = 8. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #12 \n"/* r3 = 12. */ + " str r3, [r2] \n"/* Program RNR = 12. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " msr control, r2 \n"/* Set this task's CONTROL value. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n"/* Finally, branch to EXC_RETURN. */ + #else /* configENABLE_MPU */ + " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " movs r1, #2 \n"/* r1 = 2. */ + " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r2 \n"/* Finally, branch to EXC_RETURN. */ + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst2: .word 0xe000ed94 \n" + "xMAIR0Const2: .word 0xe000edc0 \n" + "xRNRConst2: .word 0xe000ed98 \n" + "xRBARConst2: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* Read the CONTROL register. */ + " bic r0, #1 \n"/* Clear the bit 0. */ + " msr control, r0 \n"/* Write back the new CONTROL value. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " orr r0, #1 \n"/* r0 = r0 | 1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + "xVTORConst: .word 0xe000ed08 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n"/* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n"/* Read PSP in r0. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( configENABLE_MPU == 1 ) + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r2, control \n"/* r2 = CONTROL. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r1-r11} \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */ + #else /* configENABLE_MPU */ + " mrs r2, psplim \n"/* r2 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r2-r11} \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */ + #endif /* configENABLE_MPU */ + " \n" + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " str r0, [r1] \n"/* Save the new top of stack in TCB. */ + " \n" + " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n"/* r0 = 0. */ + " msr basepri, r0 \n"/* Enable interrupts. */ + " \n" + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */ + " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r3, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #4 \n"/* r3 = 4. */ + " str r3, [r2] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #8 \n"/* r3 = 8. */ + " str r3, [r2] \n"/* Program RNR = 8. */ + " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #12 \n"/* r3 = 12. */ + " str r3, [r2] \n"/* Program RNR = 12. */ + " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r0!, {r1-r11} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */ + #else /* configENABLE_MPU */ + " ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " msr control, r2 \n"/* Restore the CONTROL register value for the task. */ + #else /* configENABLE_MPU */ + " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */ + #endif /* configENABLE_MPU */ + " msr psp, r0 \n"/* Remember the new top of stack for the task. */ + " bx r3 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst: .word 0xe000ed94 \n" + "xMAIR0Const: .word 0xe000edc0 \n" + "xRNRConst: .word 0xe000ed98 \n" + "xRBARConst: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, svchandler_address_const \n" + " bx r1 \n" + " \n" + " .align 4 \n" + "svchandler_address_const: .word vPortSVCHandler_C \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h new file mode 100644 index 0000000..1f3d964 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h new file mode 100644 index 0000000..26577dd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h @@ -0,0 +1,71 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M55" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h new file mode 100644 index 0000000..3795d32 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h @@ -0,0 +1,71 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M85" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s new file mode 100644 index 0000000..35d4795 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s @@ -0,0 +1,391 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + beq running_privileged /* If the result of previous AND operation was 0, branch. */ + movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + bx lr /* Return. */ + running_privileged: + movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + orrs r0, r1 /* r0 = r0 | r1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + movs r5, #1 /* r5 = 1. */ + bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + movs r5, #4 /* r5 = 4. */ + str r5, [r2] /* Program RNR = 4. */ + ldmia r3!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write first set of RBAR/RLAR registers. */ + movs r5, #5 /* r5 = 5. */ + str r5, [r2] /* Program RNR = 5. */ + ldmia r3!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write second set of RBAR/RLAR registers. */ + movs r5, #6 /* r5 = 6. */ + str r5, [r2] /* Program RNR = 6. */ + ldmia r3!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write third set of RBAR/RLAR registers. */ + movs r5, #7 /* r5 = 7. */ + str r5, [r2] /* Program RNR = 7. */ + ldmia r3!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + movs r5, #1 /* r5 = 1. */ + orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + ldr r5, =xSecureContext + str r1, [r5] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + msr control, r3 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r4 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r3 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + movs r1, #1 /* r1 = 1. */ + bics r0, r1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, PRIMASK + cpsid i + bx lr +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr PRIMASK, r0 + bx lr +/*-----------------------------------------------------------*/ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + push {r0-r2, r14} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r3} /* LR is now in r3. */ + mov lr, r3 /* LR = r3. */ + lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ +#if ( configENABLE_MPU == 1 ) + subs r2, r2, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ +#else /* configENABLE_MPU */ + subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ +#endif /* configENABLE_MPU */ + b select_next_task + + save_ns_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + #if ( configENABLE_MPU == 1 ) + subs r2, r2, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + adds r2, r2, #16 /* r2 = r2 + 16. */ + stmia r2!, {r4-r7} /* Store the low registers that are not saved automatically. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r2!, {r4-r7} /* Store the high registers that are not saved automatically. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + subs r2, r2, #48 /* r2 = r2 - 48. */ + stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r2!, {r4-r7} /* Store the high registers that are not saved automatically. */ + #endif /* configENABLE_MPU */ + + select_next_task: + cpsid i + bl vTaskSwitchContext + cpsie i + + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + #if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r3] /* Read the value of MPU_CTRL. */ + movs r5, #1 /* r5 = 1. */ + bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */ + str r4, [r3] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */ + ldr r3, =0xe000edc0 /* r3 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r3] /* Program MAIR0. */ + ldr r4, =0xe000ed98 /* r4 = 0xe000ed98 [Location of RNR]. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + movs r5, #4 /* r5 = 4. */ + str r5, [r4] /* Program RNR = 4. */ + ldmia r1!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r6,r7} /* Write first set of RBAR/RLAR registers. */ + movs r5, #5 /* r5 = 5. */ + str r5, [r4] /* Program RNR = 5. */ + ldmia r1!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r6,r7} /* Write second set of RBAR/RLAR registers. */ + movs r5, #6 /* r5 = 6. */ + str r5, [r4] /* Program RNR = 6. */ + ldmia r1!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r6,r7} /* Write third set of RBAR/RLAR registers. */ + movs r5, #7 /* r5 = 7. */ + str r5, [r4] /* Program RNR = 7. */ + ldmia r1!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r3] /* Read the value of MPU_CTRL. */ + movs r5, #1 /* r5 = 1. */ + orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */ + str r4, [r3] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + + #if ( configENABLE_MPU == 1 ) + ldmia r2!, {r0, r1, r3, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r3 /* Restore the CONTROL register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + #else /* configENABLE_MPU */ + ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + #endif /* configENABLE_MPU */ + + restore_ns_context: + adds r2, r2, #16 /* Move to the high registers. */ + ldmia r2!, {r4-r7} /* Restore the high registers that are not automatically restored. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + subs r2, r2, #32 /* Go back to the low registers. */ + ldmia r2!, {r4-r7} /* Restore the low registers that are not automatically restored. */ + bx lr +/*-----------------------------------------------------------*/ + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stacking_used_msp + mrs r0, psp + b vPortSVCHandler_C + stacking_used_msp: + mrs r0, msp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + bne free_secure_context /* Branch if r1 != 0. */ + bx lr /* There is no secure context (xSecureContext is NULL). */ + free_secure_context: + svc 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h new file mode 100644 index 0000000..a8e2c6a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h @@ -0,0 +1,78 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s new file mode 100644 index 0000000..e6e1251 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s @@ -0,0 +1,310 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + beq running_privileged /* If the result of previous AND operation was 0, branch. */ + movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + bx lr /* Return. */ + running_privileged: + movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ + +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + orrs r0, r1 /* r0 = r0 | r1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + movs r4, #1 /* r4 = 1. */ + bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */ + str r3, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r2] /* Program RNR = 4. */ + ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */ + movs r4, #5 /* r4 = 5. */ + str r4, [r2] /* Program RNR = 5. */ + ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */ + movs r4, #6 /* r4 = 6. */ + str r4, [r2] /* Program RNR = 6. */ + ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */ + movs r4, #7 /* r4 = 7. */ + str r4, [r2] /* Program RNR = 7. */ + ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + movs r4, #1 /* r4 = 1. */ + orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */ + str r3, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + msr control, r2 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r3 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r2 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + movs r1, #1 /* r1 = 1. */ + bics r0, r1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ + nop +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, PRIMASK + cpsid i + bx lr +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr PRIMASK, r0 + bx lr +/*-----------------------------------------------------------*/ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ +#if ( configENABLE_MPU == 1 ) + subs r0, r0, #44 /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r2, control /* r2 = CONTROL. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r0!, {r1-r7} /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */ +#else /* configENABLE_MPU */ + subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */ +#endif /* configENABLE_MPU */ + + cpsid i + bl vTaskSwitchContext + cpsie i + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + movs r4, #1 /* r4 = 1. */ + bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */ + str r3, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r2] /* Program RNR = 4. */ + ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */ + movs r4, #5 /* r4 = 5. */ + str r4, [r2] /* Program RNR = 5. */ + ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */ + movs r4, #6 /* r4 = 6. */ + str r4, [r2] /* Program RNR = 6. */ + ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */ + movs r4, #7 /* r4 = 7. */ + str r4, [r2] /* Program RNR = 7. */ + ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + movs r4, #1 /* r4 = 1. */ + orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */ + str r3, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + adds r0, r0, #28 /* Move to the high registers. */ + ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + subs r0, r0, #44 /* Move to the starting of the saved context. */ + ldmia r0!, {r1-r7} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r2 /* Restore the CONTROL register value for the task. */ + bx r3 +#else /* configENABLE_MPU */ + adds r0, r0, #24 /* Move to the high registers. */ + ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + subs r0, r0, #40 /* Move to the starting of the saved context. */ + ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + bx r3 +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stacking_used_msp + mrs r0, psp + b vPortSVCHandler_C + stacking_used_msp: + mrs r0, msp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h new file mode 100644 index 0000000..a8e2c6a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h @@ -0,0 +1,78 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s new file mode 100644 index 0000000..2267aa7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s @@ -0,0 +1,353 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r2] /* Program RNR = 4. */ + adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + ldr r5, =xSecureContext + str r1, [r5] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + msr control, r3 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r4 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + push {r0-r2, r14} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r3} /* LR is now in r3. */ + mov lr, r3 /* LR = r3. */ + lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ +#if ( configENABLE_MPU == 1 ) + subs r2, r2, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ +#else /* configENABLE_MPU */ + subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ +#endif /* configENABLE_MPU */ + b select_next_task + + save_ns_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( configENABLE_MPU == 1 ) + subs r2, r2, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + adds r2, r2, #16 /* r2 = r2 + 16. */ + stm r2, {r4-r11} /* Store the registers that are not saved automatically. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + subs r2, r2, #16 /* r2 = r2 - 16. */ + stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + adds r2, r2, #12 /* r2 = r2 + 12. */ + stm r2, {r4-r11} /* Store the registers that are not saved automatically. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + subs r2, r2, #12 /* r2 = r2 - 12. */ + stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + #if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r3] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r3] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */ + ldr r3, =0xe000edc0 /* r3 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r3] /* Program MAIR0. */ + ldr r3, =0xe000ed98 /* r3 = 0xe000ed98 [Location of RNR]. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r3] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r3!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r3] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r3] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + + #if ( configENABLE_MPU == 1 ) + ldmia r2!, {r0, r1, r3, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r3 /* Restore the CONTROL register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + #else /* configENABLE_MPU */ + ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + #endif /* configENABLE_MPU */ + + restore_ns_context: + ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr +/*-----------------------------------------------------------*/ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + /* r0 = uint32_t *pulTCB. */ + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + it ne + svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h new file mode 100644 index 0000000..aaefff6 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h @@ -0,0 +1,78 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s new file mode 100644 index 0000000..c4efd3c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s @@ -0,0 +1,262 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r3, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r3, #4 /* r3 = 4. */ + str r3, [r2] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + msr control, r2 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r2 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ +#if ( configENABLE_MPU == 1 ) + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r2, control /* r2 = CONTROL. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */ +#else /* configENABLE_MPU */ + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ +#endif /* configENABLE_MPU */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r3, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r3, #4 /* r3 = 4. */ + str r3, [r2] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */ +#else /* configENABLE_MPU */ + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ +#endif /* configENABLE_MPU */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + #if ( configENABLE_MPU == 1 ) + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r2 /* Restore the CONTROL register value for the task. */ +#else /* configENABLE_MPU */ + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ +#endif /* configENABLE_MPU */ + msr psp, r0 /* Remember the new top of stack for the task. */ + bx r3 +/*-----------------------------------------------------------*/ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h new file mode 100644 index 0000000..aaefff6 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h @@ -0,0 +1,78 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h new file mode 100644 index 0000000..a2ec280 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h @@ -0,0 +1,83 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M55" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h new file mode 100644 index 0000000..59fc09b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h @@ -0,0 +1,83 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M85" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portasm.h new file mode 100644 index 0000000..c3b2f2c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portmacrocommon.h new file mode 100644 index 0000000..e68692a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/ReadMe.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/ReadMe.txt new file mode 100644 index 0000000..68ff904 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/ReadMe.txt @@ -0,0 +1,11 @@ +This directory tree contains the master copy of the FreeRTOS Armv8-M and +Armv8.1-M ports. +Do not use the files located here! These file are copied into separate +FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to +each FreeRTOS release. + +If your Armv8-M/Armv8.1-M application uses TrustZone then use the files from the +FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories. + +If your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from +the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories. diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c new file mode 100644 index 0000000..2d8b2af --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c @@ -0,0 +1,99 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " subs r1, r1, #4 \n" /* Make space for the CONTROL value on the stack. */ + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " stmia r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #else /* configENABLE_MPU */ + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + #endif /* configENABLE_MPU */ + " \n" + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c new file mode 100644 index 0000000..f35fae0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c @@ -0,0 +1,97 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */ + " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s new file mode 100644 index 0000000..b89a865 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s @@ -0,0 +1,88 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */ + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + stmia r1!, {r2} /* Store CONTROL value on the stack. */ +#else /* configENABLE_MPU */ + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ +#endif /* configENABLE_MPU */ + + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s new file mode 100644 index 0000000..a02ab36 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */ + vldmia r1!, {s0} /* Nullify the effect of the previous statement. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + stmdb r1!, {r2} /* Store CONTROL value on the stack. */ +#endif /* configENABLE_MPU */ + + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/secure_context.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/secure_context.c new file mode 100644 index 0000000..ffb4f87 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/secure_context.c @@ -0,0 +1,351 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Ontain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/secure_context.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/secure_context.h new file mode 100644 index 0000000..68efd7c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/secure_context.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/heap/secure_heap.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/heap/secure_heap.c new file mode 100644 index 0000000..fa42ee3 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/heap/secure_heap.c @@ -0,0 +1,454 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/** + * @brief Gets set to the top bit of an size_t type. + * + * When this bit in the xBlockSize member of an BlockLink_t structure is set + * then the block belongs to the application. When the bit is free the block is + * still part of the free heap space. + */ +static size_t xBlockAllocatedBit = 0; +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size is increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number of + * bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); + secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/heap/secure_heap.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/heap/secure_heap.h new file mode 100644 index 0000000..2689c49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/heap/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/init/secure_init.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/init/secure_init.c new file mode 100644 index 0000000..585adfe --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/init/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/init/secure_init.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/init/secure_init.h new file mode 100644 index 0000000..fc000cf --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/init/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/macros/secure_port_macros.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/macros/secure_port_macros.h new file mode 100644 index 0000000..1ca265d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ARMv8M/secure/macros/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/Flsh186/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/Flsh186/port.c new file mode 100644 index 0000000..0210716 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/Flsh186/port.c @@ -0,0 +1,245 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V1.00: + + + Call to taskYIELD() from within tick ISR has been replaced by the more + efficient portSWITCH_CONTEXT(). + + ISR function definitions renamed to include the prv prefix. + +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Flashlite 186 + * port. + *----------------------------------------------------------*/ + +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_EOI_TYPE ( 8 ) +#define portRESET_PIC() portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE ) +#define portTIMER_INT_NUMBER 0x12 + +#define portTIMER_1_CONTROL_REGISTER ( ( uint16_t ) 0xff5e ) +#define portTIMER_0_CONTROL_REGISTER ( ( uint16_t ) 0xff56 ) +#define portTIMER_INTERRUPT_ENABLE ( ( uint16_t ) 0x2000 ) + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetTickFrequency( uint32_t ulTickRateHz ); + +/* Set the hardware back to the state as per before the scheduler started. */ +static void prvExitFunction( void ); + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static BaseType_t xSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual +context switches. This is then used to restore the original routine during +prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +BaseType_t xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + #if( configUSE_PREEMPTION == 1 ) + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + xSchedulerRunning = pdFALSE; + } + else + { + xSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return xSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + } + + /* Reset the PIC ready for the next time. */ + portRESET_PIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + xTaskIncrementTick(); + portRESET_PIC(); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +const uint16_t usTimerDisable = 0x0000; +uint16_t usTimer0Control; + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( xSchedulerRunning == pdTRUE ) + { + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + } + + /* Disable the timer used for the tick to ensure the scheduler is + not called before restoring interrupts. There was previously nothing + on this timer so there is no old ISR to restore. */ + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable ); + + /* Restart the DOS tick. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control |= portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); + + + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( uint32_t ulTickRateHz ) +{ +const uint16_t usMaxCountRegister = 0xff5a; +const uint16_t usTimerPriorityRegister = 0xff32; +const uint16_t usTimerEnable = 0xC000; +const uint16_t usRetrigger = 0x0001; +const uint16_t usTimerHighPriority = 0x0000; +uint16_t usTimer0Control; + +/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */ + +const uint32_t ulClockFrequency = ( uint32_t ) 0x7f31a0UL; + +uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz; + + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger ); + portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount ); + portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority ); + + /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); +} + + +/*lint +e950 */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/Flsh186/prtmacro.h new file mode 100644 index 0000000..80d9637 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/Flsh186/prtmacro.h @@ -0,0 +1,98 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE portSHORT + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/PC/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/PC/port.c new file mode 100644 index 0000000..c3b0564 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/PC/port.c @@ -0,0 +1,289 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. + +Changes from V4.0.1 + + + Add function prvSetTickFrequencyDefault() to set the DOS tick back to + its proper value when the scheduler exits. +*/ + +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the industrial + * PC port. + *----------------------------------------------------------*/ + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_INT_NUMBER 0x08 + +/* Setup hardware for required tick interrupt rate. */ +static void prvSetTickFrequency( uint32_t ulTickRateHz ); + +/* Restore hardware to as it was prior to starting the scheduler. */ +static void prvExitFunction( void ); + +/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC +directly. We chain to the DOS tick as close as possible to the standard DOS +tick rate. */ +static void prvPortResetPIC( void ); + +/* The ISR used depends on whether the preemptive or cooperative +scheduler is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/* Set the tick frequency back so the floppy drive works correctly when the +scheduler exits. */ +static void prvSetTickFrequencyDefault( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */ +static int16_t sDOSTickCounter; + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static BaseType_t xSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISRPlus1 )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +BaseType_t xPortStartScheduler( void ) +{ +pxISR pxOriginalTickISR; + + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER ); + pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Put the old tick on a different interrupt number so we can + call it when we want. */ + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR ); + + /* The ISR used depends on whether the preemptive or cooperative + scheduler is being used. */ + #if( configUSE_PREEMPTION == 1 ) + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + /* Setup a counter that is used to call the DOS interrupt as close + to it's original frequency as can be achieved given our chosen tick + frequency. */ + sDOSTickCounter = portTICKS_PER_DOS_TICK; + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + xSchedulerRunning = pdFALSE; + } + else + { + xSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return xSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative +scheduler is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + } + + /* Reset the PIC ready for the next time. */ + prvPortResetPIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + xTaskIncrementTick(); + prvPortResetPIC(); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +static void prvPortResetPIC( void ) +{ + /* We are going to call the DOS tick interrupt at as close a + frequency to the normal DOS tick as possible. */ + + /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */ + --sDOSTickCounter; + if( sDOSTickCounter <= 0 ) + { + sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK; + __asm{ int portSWITCH_INT_NUMBER + 1 }; + } + else + { + /* Reset the PIC as the DOS tick is not being called to + do it. */ + __asm + { + mov al, 20H + out 20H, al + }; + } +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +void ( __interrupt __far *pxOriginalTickISR )(); + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( xSchedulerRunning == pdTRUE ) + { + /* Set the DOS tick back onto the timer ticker. */ + pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR ); + prvSetTickFrequencyDefault(); + + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 ); + } + /* The tick timer is back how DOS wants it. We can re-enable + interrupts without the scheduler being called. */ + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( uint32_t ulTickRateHz ) +{ +const uint16_t usPIT_MODE = ( uint16_t ) 0x43; +const uint16_t usPIT0 = ( uint16_t ) 0x40; +const uint32_t ulPIT_CONST = ( uint32_t ) 1193180UL; +const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36; +uint32_t ulOutput; + + /* Setup the 8245 to tick at the wanted frequency. */ + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + ulOutput = ulPIT_CONST / ulTickRateHz; + portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) ); + ulOutput >>= 8; + portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) ); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequencyDefault( void ) +{ +const uint16_t usPIT_MODE = ( uint16_t ) 0x43; +const uint16_t usPIT0 = ( uint16_t ) 0x40; +const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36; + + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + portOUTPUT_BYTE( usPIT0,0 ); + portOUTPUT_BYTE( usPIT0,0 ); +} + + +/*lint +e950 */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/PC/prtmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/PC/prtmacro.h new file mode 100644 index 0000000..f4a1716 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/PC/prtmacro.h @@ -0,0 +1,98 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT long +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE portSHORT + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portDOS_TICK_RATE ( 18.20648 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portTICKS_PER_DOS_TICK ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) ) +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +#define portBYTE_ALIGNMENT ( 2 ) +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/common/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/common/portasm.h new file mode 100644 index 0000000..1767b9c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/common/portasm.h @@ -0,0 +1,88 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORT_ASM_H +#define PORT_ASM_H + +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portSWITCH_CONTEXT( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +/* There are slightly different versions depending on whether you are building +to include debugger information. If debugger information is used then there +are a couple of extra bytes left of the ISR stack (presumably for use by the +debugger). The true stack pointer is then stored in the bp register. We add +2 to the stack pointer to remove the extra bytes before we restore our context. */ + +#define portSWITCH_CONTEXT() \ + asm { mov ax, seg pxCurrentTCB } \ + asm { mov ds, ax } \ + asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \ + asm { mov es:0x2[ bx ], ss } \ + asm { mov es:[ bx ], sp } \ + asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \ + asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \ + asm { mov ds, ax } \ + asm { les bx, dword ptr pxCurrentTCB } \ + asm { mov ss, es:[ bx + 2 ] } \ + asm { mov sp, es:[ bx ] } + +#define portFIRST_CONTEXT() \ + __asm { mov ax, seg pxCurrentTCB } \ + __asm { mov ds, ax } \ + __asm { les bx, dword ptr pxCurrentTCB } \ + __asm { mov ss, es:[ bx + 2 ] } \ + __asm { mov sp, es:[ bx ] } \ + __asm { pop bp } \ + __asm { pop di } \ + __asm { pop si } \ + __asm { pop ds } \ + __asm { pop es } \ + __asm { pop dx } \ + __asm { pop cx } \ + __asm { pop bx } \ + __asm { pop ax } \ + __asm { iret } + + +#endif + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/common/portcomn.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/common/portcomn.c new file mode 100644 index 0000000..c01a24c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/BCC/16BitDOS/common/portcomn.c @@ -0,0 +1,121 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V1.00: + + + pxPortInitialiseStack() now initialises the stack of new tasks to the + same format used by the compiler. This allows the compiler generated + interrupt mechanism to be used for context switches. + +Changes from V2.6.1 + + + Move usPortCheckFreeStackSpace() to tasks.c. +*/ + + +#include +#include +#include "FreeRTOS.h" + +/*-----------------------------------------------------------*/ + +/* See header file for description. */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t DS_Reg = 0; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + *pxTopOfStack = 0x4444; + pxTopOfStack--; + *pxTopOfStack = 0x5555; + pxTopOfStack--; + + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + function call with parameters preamble. */ + + *pxTopOfStack = FP_SEG( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* Next the status register and interrupt return address. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */ + pxTopOfStack--; + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + *pxTopOfStack = DS_Reg; /* DS */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */ + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM3/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM3/port.c new file mode 100644 index 0000000..b5df2a4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM3/port.c @@ -0,0 +1,609 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM3 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY + * setting. */ +const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY; + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + ( void ) portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + #pragma WEAK( vPortSuppressTicksAndSleep ) + void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm( " cpsid i"); + __asm( " dsb"); + __asm( " isb"); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_interrupt() + * call above. */ + __asm( " cpsie i"); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm( " dsb"); + __asm( " wfi"); + __asm( " isb"); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __asm( " cpsie i"); + __asm( " dsb"); + __asm( " isb"); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm( " cpsid i"); + __asm( " dsb"); + __asm( " isb"); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm( " cpsie i"); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +#pragma WEAK( vPortSetupTimerInterrupt ) +void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + extern uint32_t ulPortGetIPSR( void ); + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + ulCurrentInterrupt = ulPortGetIPSR(); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM3/portasm.asm b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM3/portasm.asm new file mode 100644 index 0000000..8b4b4fe --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM3/portasm.asm @@ -0,0 +1,145 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + .thumb + + .ref pxCurrentTCB + .ref vTaskSwitchContext + .ref ulMaxSyscallInterruptPriority + + .def xPortPendSVHandler + .def ulPortGetIPSR + .def vPortSVCHandler + .def vPortStartFirstTask + +NVICOffsetConst: .word 0xE000ED08 +CPACRConst: .word 0xE000ED88 +pxCurrentTCBConst: .word pxCurrentTCB +ulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority + +; ----------------------------------------------------------- + + .align 4 +ulPortGetIPSR: .asmfunc + mrs r0, ipsr + bx r14 + .endasmfunc + ; ----------------------------------------------------------- + + .align 4 +vPortSetInterruptMask: .asmfunc + push {r0} + ldr r0, ulMaxSyscallInterruptPriorityConst + msr basepri, r0 + pop {r0} + bx r14 + .endasmfunc +; ----------------------------------------------------------- + + .align 4 +xPortPendSVHandler: .asmfunc + mrs r0, psp + isb + + ;/* Get the location of the current TCB. */ + ldr r3, pxCurrentTCBConst + ldr r2, [r3] + + ;/* Save the core registers. */ + stmdb r0!, {r4-r11} + + ;/* Save the new top of stack into the first member of the TCB. */ + str r0, [r2] + + stmdb sp!, {r3, r14} + ldr r0, ulMaxSyscallInterruptPriorityConst + ldr r1, [r0] + msr basepri, r1 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r3, r14} + + ;/* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [r3] + ldr r0, [r1] + + ;/* Pop the core registers. */ + ldmia r0!, {r4-r11} + + msr psp, r0 + isb + bx r14 + .endasmfunc + +; ----------------------------------------------------------- + + .align 4 +vPortSVCHandler: .asmfunc + ;/* Get the location of the current TCB. */ + ldr r3, pxCurrentTCBConst + ldr r1, [r3] + ldr r0, [r1] + ;/* Pop the core registers. */ + ldmia r0!, {r4-r11} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + orr r14, #0xd + bx r14 + .endasmfunc + +; ----------------------------------------------------------- + + .align 4 +vPortStartFirstTask: .asmfunc + ;/* Use the NVIC offset register to locate the stack. */ + ldr r0, NVICOffsetConst + ldr r0, [r0] + ldr r0, [r0] + ;/* Set the msp back to the start of the stack. */ + msr msp, r0 + ;/* Clear the bit that indicates the FPU is in use in case the FPU was used + ;before the scheduler was started - which would otherwise result in the + ;unnecessary leaving of space in the SVC stack for lazy saving of FPU + ;registers. */ + mov r0, #0 + msr control, r0 + ;/* Call SVC to start the first task. */ + cpsie i + cpsie f + dsb + isb + svc #0 + .endasmfunc + +; ----------------------------------------------------------- + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM3/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM3/portmacro.h new file mode 100644 index 0000000..a7bd8ce --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM3/portmacro.h @@ -0,0 +1,171 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Compiler directives. */ + #define portWEAK_SYMBOL __attribute__( ( weak ) ) + +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __asm( " dsb"); \ + __asm( " isb"); \ + } + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + + #define portDISABLE_INTERRUPTS() \ + { \ + _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __asm( " dsb"); \ + __asm( " isb"); \ + } + + #define portENABLE_INTERRUPTS() _set_interrupt_priority( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #define portSET_INTERRUPT_MASK_FROM_ISR() _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( " dsb" ); __asm( " isb") + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) _set_interrupt_priority( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM4F/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM4F/port.c new file mode 100644 index 0000000..1b705c2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM4F/port.c @@ -0,0 +1,634 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __TI_VFP_SUPPORT__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Turn the VFP on. + */ +extern void vPortEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY + * setting. */ +const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY; + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + ( void ) portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + #pragma WEAK( vPortSuppressTicksAndSleep ) + void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm( " cpsid i"); + __asm( " dsb"); + __asm( " isb"); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_interrupt() + * call above. */ + __asm( " cpsie i"); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm( " dsb"); + __asm( " wfi"); + __asm( " isb"); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __asm( " cpsie i"); + __asm( " dsb"); + __asm( " isb"); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm( " cpsid i"); + __asm( " dsb"); + __asm( " isb"); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm( " cpsie i"); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +#pragma WEAK( vPortSetupTimerInterrupt ) +void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + extern uint32_t ulPortGetIPSR( void ); + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + ulCurrentInterrupt = ulPortGetIPSR(); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM4F/portasm.asm b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM4F/portasm.asm new file mode 100644 index 0000000..8309db0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM4F/portasm.asm @@ -0,0 +1,172 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + .thumb + + .ref pxCurrentTCB + .ref vTaskSwitchContext + .ref ulMaxSyscallInterruptPriority + + .def xPortPendSVHandler + .def ulPortGetIPSR + .def vPortSVCHandler + .def vPortStartFirstTask + .def vPortEnableVFP + +NVICOffsetConst: .word 0xE000ED08 +CPACRConst: .word 0xE000ED88 +pxCurrentTCBConst: .word pxCurrentTCB +ulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority + +; ----------------------------------------------------------- + + .align 4 +ulPortGetIPSR: .asmfunc + mrs r0, ipsr + bx r14 + .endasmfunc + ; ----------------------------------------------------------- + + .align 4 +vPortSetInterruptMask: .asmfunc + push {r0} + ldr r0, ulMaxSyscallInterruptPriorityConst + msr basepri, r0 + pop {r0} + bx r14 + .endasmfunc +; ----------------------------------------------------------- + + .align 4 +xPortPendSVHandler: .asmfunc + mrs r0, psp + isb + + ;/* Get the location of the current TCB. */ + ldr r3, pxCurrentTCBConst + ldr r2, [r3] + + ;/* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + ;/* Save the core registers. */ + stmdb r0!, {r4-r11, r14} + + ;/* Save the new top of stack into the first member of the TCB. */ + str r0, [r2] + + stmdb sp!, {r0, r3} + ldr r0, ulMaxSyscallInterruptPriorityConst + ldr r1, [r0] + msr basepri, r1 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + ;/* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [r3] + ldr r0, [r1] + + ;/* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + + ;/* Is the task using the FPU context? If so, pop the high vfp registers + ;too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + bx r14 + .endasmfunc + +; ----------------------------------------------------------- + + .align 4 +vPortSVCHandler: .asmfunc + ;/* Get the location of the current TCB. */ + ldr r3, pxCurrentTCBConst + ldr r1, [r3] + ldr r0, [r1] + ;/* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 + .endasmfunc + +; ----------------------------------------------------------- + + .align 4 +vPortStartFirstTask: .asmfunc + ;/* Use the NVIC offset register to locate the stack. */ + ldr r0, NVICOffsetConst + ldr r0, [r0] + ldr r0, [r0] + ;/* Set the msp back to the start of the stack. */ + msr msp, r0 + ;/* Clear the bit that indicates the FPU is in use in case the FPU was used + ;before the scheduler was started - which would otherwise result in the + ;unnecessary leaving of space in the SVC stack for lazy saving of FPU + ;registers. */ + mov r0, #0 + msr control, r0 + ;/* Call SVC to start the first task. */ + cpsie i + cpsie f + dsb + isb + svc #0 + .endasmfunc + +; ----------------------------------------------------------- + + .align 4 +vPortEnableVFP: .asmfunc + ;/* The FPU enable bits are in the CPACR. */ + ldr.w r0, CPACRConst + ldr r1, [r0] + + ;/* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [r0] + bx r14 + .endasmfunc + + .end + +; ----------------------------------------------------------- + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM4F/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM4F/portmacro.h new file mode 100644 index 0000000..6663419 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_CM4F/portmacro.h @@ -0,0 +1,165 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __asm( " dsb"); \ + __asm( " isb"); \ + } + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + + #define portDISABLE_INTERRUPTS() \ + { \ + _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __asm( " dsb"); \ + __asm( " isb"); \ + } + + #define portENABLE_INTERRUPTS() _set_interrupt_priority( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #define portSET_INTERRUPT_MASK_FROM_ISR() _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( " dsb" ); __asm( " isb") + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) _set_interrupt_priority( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_Cortex-R4/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_Cortex-R4/port.c new file mode 100644 index 0000000..e5f6ca9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_Cortex-R4/port.c @@ -0,0 +1,313 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*-----------------------------------------------------------*/ + +/* Count of the critical section nesting depth. */ +uint32_t ulCriticalNesting = 9999; + +/*-----------------------------------------------------------*/ + +/* Registers required to configure the RTI. */ +#define portRTI_GCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC00 ) ) +#define portRTI_TBCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC04 ) ) +#define portRTI_COMPCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC0C ) ) +#define portRTI_CNT0_FRC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC10 ) ) +#define portRTI_CNT0_UC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC14 ) ) +#define portRTI_CNT0_CPUC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC18 ) ) +#define portRTI_CNT0_COMP0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC50 ) ) +#define portRTI_CNT0_UDCP0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC54 ) ) +#define portRTI_SETINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC80 ) ) +#define portRTI_CLEARINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC84 ) ) +#define portRTI_INTFLAG_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC88 ) ) + + +/* Constants required to set up the initial stack of each task. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1F ) +#define portINITIAL_FPSCR ( ( StackType_t ) 0x00 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 0x04 ) +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) + +/* The number of words on the stack frame between the saved Top Of Stack and +R0 (in which the parameters are passed. */ +#define portSPACE_BETWEEN_TOS_AND_PARAMETERS ( 12 ) + +/*-----------------------------------------------------------*/ + +/* vPortStartFirstSTask() is defined in portASM.asm */ +extern void vPortStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* Saved as part of the task context. Set to pdFALSE if the task does not +require an FPU context. */ +uint32_t ulTaskHasFPUContext = 0; + +/*-----------------------------------------------------------*/ + + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + #if __TI_VFP_SUPPORT__ + { + /* Ensure the stack is correctly aligned on exit. */ + pxTopOfStack--; + } + #endif + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which is the start of the as + the task has not executed yet. The offset is added to make the return + address appear as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + + #ifdef portPRELOAD_TASK_REGISTERS + { + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + } + #else + { + pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS; + } + #endif + + /* Function parameters are passed in R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* Set the status register for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) ( ( _get_CPSR() & ~0xFF ) | portINITIAL_SPSR ); + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 ) + { + /* The task will start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + #ifdef __TI_VFP_SUPPORT__ + { + pxTopOfStack--; + + /* The last thing on the stack is the tasks ulUsingFPU value, which by + default is set to indicate that the stack frame does not include FPU + registers. */ + *pxTopOfStack = pdFALSE; + } + #endif + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt(void) +{ + /* Disable timer 0. */ + portRTI_GCTRL_REG &= 0xFFFFFFFEUL; + + /* Use the internal counter. */ + portRTI_TBCTRL_REG = 0x00000000U; + + /* COMPSEL0 will use the RTIFRC0 counter. */ + portRTI_COMPCTRL_REG = 0x00000000U; + + /* Initialise the counter and the prescale counter registers. */ + portRTI_CNT0_UC0_REG = 0x00000000U; + portRTI_CNT0_FRC0_REG = 0x00000000U; + + /* Set Prescalar for RTI clock. */ + portRTI_CNT0_CPUC0_REG = 0x00000001U; + portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ; + portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ; + + /* Clear interrupts. */ + portRTI_INTFLAG_REG = 0x0007000FU; + portRTI_CLEARINTENA_REG = 0x00070F0FU; + + /* Enable the compare 0 interrupt. */ + portRTI_SETINTENA_REG = 0x00000001U; + portRTI_GCTRL_REG |= 0x00000001U; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler(void) +{ + /* Start the timer that generates the tick ISR. */ + prvSetupTimerInterrupt(); + + /* Reset the critical section nesting count read to execute the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. This is done from portASM.asm as ARM mode must be + used. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +void vPortEndScheduler(void) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ + __interrupt void vPortNonPreemptiveTick( void ) + { + /* clear clock interrupt flag */ + portRTI_INTFLAG_REG = 0x00000001; + + /* Increment the tick count - this may make a delaying task ready + to run - but a context switch is not performed. */ + xTaskIncrementTick(); + } + + #else + + /* + ************************************************************************** + * The preemptive scheduler ISR is written in assembler and can be found + * in the portASM.asm file. This will only get used if portUSE_PREEMPTION + * is set to 1 in portmacro.h + ************************************************************************** + */ + void vPortPreemptiveTick( void ); + +#endif +/*-----------------------------------------------------------*/ + + +/* + * Disable interrupts, and keep a count of the nesting depth. + */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +/* + * Decrement the critical nesting count, and if it has reached zero, re-enable + * interrupts. + */ +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > 0 ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == 0 ) + { + /* Enable interrupts as per portENABLE_INTERRUPTS(). */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +#if __TI_VFP_SUPPORT__ + + void vPortTaskUsesFPU( void ) + { + extern void vPortInitialiseFPSCR( void ); + + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (saved as part of the task context. */ + ulTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + vPortInitialiseFPSCR(); + } + +#endif /* __TI_VFP_SUPPORT__ */ + +/*-----------------------------------------------------------*/ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_Cortex-R4/portASM.asm b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_Cortex-R4/portASM.asm new file mode 100644 index 0000000..c993540 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_Cortex-R4/portASM.asm @@ -0,0 +1,230 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + .text + .arm + .ref vTaskSwitchContext + .ref xTaskIncrementTick + .ref ulTaskHasFPUContext + .ref pxCurrentTCB + +;/*-----------------------------------------------------------*/ +; +; Save Task Context +; +portSAVE_CONTEXT .macro + DSB + + ; Push R0 as we are going to use it + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP,{SP}^ + SUB SP, SP, #4 + LDMIA SP!,{R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now LR has been saved, it can be used instead of R0. + MOV LR, R0 + + ; Pop R0 so it can be saved onto the task stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR,{R0-LR}^ + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + .if (__TI_VFP_SUPPORT__) + ;Determine if the task maintains an FPU context. + LDR R0, ulFPUContextConst + LDR R0, [R0] + + ; Test the flag + CMP R0, #0 + + ; If the task is not using a floating point context then skip the + ; saving of the FPU registers. + BEQ $+16 + FSTMDBD LR!, {D0-D15} + FMRX R1, FPSCR + STMFD LR!, {R1} + + ; Save the flag + STMDB LR!, {R0} + .endif + + ; Store the new top of stack for the task. + LDR R0, pxCurrentTCBConst + LDR R0, [R0] + STR LR, [R0] + + .endm + +;/*-----------------------------------------------------------*/ +; +; Restore Task Context +; +portRESTORE_CONTEXT .macro + LDR R0, pxCurrentTCBConst + LDR R0, [R0] + LDR LR, [R0] + + .if (__TI_VFP_SUPPORT__) + ; The floating point context flag is the first thing on the stack. + LDR R0, ulFPUContextConst + LDMFD LR!, {R1} + STR R1, [R0] + + ; Test the flag + CMP R1, #0 + + ; If the task is not using a floating point context then skip the + ; VFP register loads. + BEQ $+16 + + ; Restore the floating point context. + LDMFD LR!, {R0} + FLDMIAD LR!, {D0-D15} + FMXR FPSCR, R0 + .endif + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_CSXF, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + .endm + +;/*-----------------------------------------------------------*/ +; Start the first task by restoring its context. + + .def vPortStartFirstTask + +vPortStartFirstTask: + portRESTORE_CONTEXT + +;/*-----------------------------------------------------------*/ +; Yield to another task. + + .def vPortYieldProcessor + +vPortYieldProcessor: + ; Within an IRQ ISR the link register has an offset from the true return + ; address. SWI doesn't do this. Add the offset manually so the ISR + ; return code can be used. + ADD LR, LR, #4 + + ; First save the context of the current task. + portSAVE_CONTEXT + + ; Select the next task to execute. */ + BL vTaskSwitchContext + + ; Restore the context of the task selected to execute. + portRESTORE_CONTEXT + +;/*-----------------------------------------------------------*/ +; Yield to another task from within the FreeRTOS API + + .def vPortYeildWithinAPI + +vPortYeildWithinAPI: + ; Save the context of the current task. + + portSAVE_CONTEXT + ; Clear SSI flag. + MOVW R0, #0xFFF4 + MOVT R0, #0xFFFF + LDR R0, [R0] + + ; Select the next task to execute. */ + BL vTaskSwitchContext + + ; Restore the context of the task selected to execute. + portRESTORE_CONTEXT + +;/*-----------------------------------------------------------*/ +; Preemptive Tick + + .def vPortPreemptiveTick + +vPortPreemptiveTick: + + ; Save the context of the current task. + portSAVE_CONTEXT + + ; Clear interrupt flag + MOVW R0, #0xFC88 + MOVT R0, #0xFFFF + MOV R1, #1 + STR R1, [R0] + + ; Increment the tick count, making any adjustments to the blocked lists + ; that may be necessary. + BL xTaskIncrementTick + + ; Select the next task to execute. + CMP R0, #0 + BLNE vTaskSwitchContext + + ; Restore the context of the task selected to execute. + portRESTORE_CONTEXT + +;------------------------------------------------------------------------------- + + .if (__TI_VFP_SUPPORT__) + + .def vPortInitialiseFPSCR + +vPortInitialiseFPSCR: + + MOV R0, #0 + FMXR FPSCR, R0 + BX LR + + .endif ;__TI_VFP_SUPPORT__ + + +pxCurrentTCBConst .word pxCurrentTCB +ulFPUContextConst .word ulTaskHasFPUContext +;------------------------------------------------------------------------------- + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_Cortex-R4/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_Cortex-R4/portmacro.h new file mode 100644 index 0000000..d1240ae --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/ARM_Cortex-R4/portmacro.h @@ -0,0 +1,118 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORTMACRO_H__ +#define __PORTMACRO_H__ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if (configUSE_16_BIT_TICKS == 1) + typedef uint16_t TickType_t; + #define portMAX_DELAY (TickType_t) 0xFFFF +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY (TickType_t) 0xFFFFFFFFF + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif + + +/* Architecture specifics. */ +#define portSTACK_GROWTH (-1) +#define portTICK_PERIOD_MS ((TickType_t) 1000 / configTICK_RATE_HZ) +#define portBYTE_ALIGNMENT 8 + +/* Critical section handling. */ +extern void vPortEnterCritical(void); +extern void vPortExitCritical(void); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portDISABLE_INTERRUPTS() asm( " CPSID I" ) +#define portENABLE_INTERRUPTS() asm( " CPSIE I" ) + +/* Scheduler utilities. */ +#pragma SWI_ALIAS( vPortYield, 0 ) +extern void vPortYield( void ); +#define portYIELD() vPortYield() +#define portSYS_SSIR1_REG ( * ( ( volatile uint32_t * ) 0xFFFFFFB0 ) ) +#define portSYS_SSIR1_SSKEY ( 0x7500UL ) +#define portYIELD_WITHIN_API() { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY; asm( " DSB " ); asm( " ISB " ); } +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY; ( void ) portSYS_SSIR1_REG; } } while( 0 ) + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +/* Architecture specific optimisations. */ +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters) +#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters) + +#endif /* __PORTMACRO_H__ */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/MSP430X/data_model.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/MSP430X/data_model.h new file mode 100644 index 0000000..aa514e5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/MSP430X/data_model.h @@ -0,0 +1,54 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + .if $DEFINED( __LARGE_DATA_MODEL__ ) + .define "pushm.a", pushm_x + .define "popm.a", popm_x + .define "push.a", push_x + .define "pop.a", pop_x + .define "mov.a", mov_x + .else + .define "pushm.w", pushm_x + .define "popm.w", popm_x + .define "push.w", push_x + .define "pop.w", pop_x + .define "mov.w", mov_x + .endif + + .if $DEFINED( __LARGE_CODE_MODEL__ ) + .define "calla", call_x + .define "reta", ret_x + .else + .define "call", call_x + .define "ret", ret_x + .endif + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/MSP430X/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/MSP430X/port.c new file mode 100644 index 0000000..4bf1a00 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/MSP430X/port.c @@ -0,0 +1,188 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430X port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void vPortSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint16_t *pusTopOfStack; +uint32_t *pulTopOfStack, ulTemp; + + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x3333; + pxTopOfStack--; + */ + + /* Data types are need either 16 bits or 32 bits depending on the data + and code model used. */ + if( sizeof( pxCode ) == sizeof( uint16_t ) ) + { + pusTopOfStack = ( uint16_t * ) pxTopOfStack; + ulTemp = ( uint32_t ) pxCode; + *pusTopOfStack = ( uint16_t ) ulTemp; + } + else + { + /* Make room for a 20 bit value stored as a 32 bit value. */ + pusTopOfStack = ( uint16_t * ) pxTopOfStack; + pusTopOfStack--; + pulTopOfStack = ( uint32_t * ) pusTopOfStack; + *pulTopOfStack = ( uint32_t ) pxCode; + } + + pusTopOfStack--; + *pusTopOfStack = portFLAGS_INT_ENABLED; + pusTopOfStack -= ( sizeof( StackType_t ) / 2 ); + + /* From here on the size of stacked items depends on the memory model. */ + pxTopOfStack = ( StackType_t * ) pusTopOfStack; + + /* Next the general purpose registers. */ + #ifdef PRELOAD_REGISTER_VALUES + *pxTopOfStack = ( StackType_t ) 0xffff; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xeeee; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x4444; + pxTopOfStack--; + #else + pxTopOfStack -= 3; + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack -= 9; + #endif + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. + */ +void vPortSetupTimerInterrupt( void ) +{ + vApplicationSetupTimerInterrupt(); +} +/*-----------------------------------------------------------*/ + +#pragma vector=configTICK_VECTOR +interrupt void vTickISREntry( void ) +{ +extern void vPortTickISR( void ); + + __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF ); + #if configUSE_PREEMPTION == 1 + extern void vPortPreemptiveTickISR( void ); + vPortPreemptiveTickISR(); + #else + extern void vPortCooperativeTickISR( void ); + vPortCooperativeTickISR(); + #endif +} + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/MSP430X/portext.asm b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/MSP430X/portext.asm new file mode 100644 index 0000000..5e3b635 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/MSP430X/portext.asm @@ -0,0 +1,160 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +; * The definition of the "register test" tasks, as described at the top of +; * main.c + + .include data_model.h + + .global xTaskIncrementTick + .global vTaskSwitchContext + .global vPortSetupTimerInterrupt + .global pxCurrentTCB + .global usCriticalNesting + + .def vPortPreemptiveTickISR + .def vPortCooperativeTickISR + .def vPortYield + .def xPortStartScheduler + +;----------------------------------------------------------- + +portSAVE_CONTEXT .macro + + ;Save the remaining registers. + pushm_x #12, r15 + mov.w &usCriticalNesting, r14 + push_x r14 + mov_x &pxCurrentTCB, r12 + mov_x sp, 0( r12 ) + .endm +;----------------------------------------------------------- + +portRESTORE_CONTEXT .macro + + mov_x &pxCurrentTCB, r12 + mov_x @r12, sp + pop_x r15 + mov.w r15, &usCriticalNesting + popm_x #12, r15 + nop + pop.w sr + nop + ret_x + .endm +;----------------------------------------------------------- + +;* +;* The RTOS tick ISR. +;* +;* If the cooperative scheduler is in use this simply increments the tick +;* count. +;* +;* If the preemptive scheduler is in use a context switch can also occur. +;*/ + + .text + .align 2 + +vPortPreemptiveTickISR: .asmfunc + + ; The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs + ;to save it manually before it gets modified (interrupts get disabled). + push.w sr + portSAVE_CONTEXT + + call_x #xTaskIncrementTick + call_x #vTaskSwitchContext + + portRESTORE_CONTEXT + .endasmfunc +;----------------------------------------------------------- + + .align 2 + +vPortCooperativeTickISR: .asmfunc + + ; The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs + ;to save it manually before it gets modified (interrupts get disabled). + push.w sr + portSAVE_CONTEXT + + call_x #xTaskIncrementTick + + portRESTORE_CONTEXT + + .endasmfunc +;----------------------------------------------------------- + +; +; Manual context switch called by the portYIELD() macro. +; + + .align 2 + +vPortYield: .asmfunc + + ; The sr needs saving before it is modified. + push.w sr + + ; Now the SR is stacked we can disable interrupts. + dint + nop + + ; Save the context of the current task. + portSAVE_CONTEXT + + ; Select the next task to run. + call_x #vTaskSwitchContext + + ; Restore the context of the new task. + portRESTORE_CONTEXT + .endasmfunc +;----------------------------------------------------------- + + +; +; Start off the scheduler by initialising the RTOS tick timer, then restoring +; the context of the first task. +; + + .align 2 + +xPortStartScheduler: .asmfunc + + ; Setup the hardware to generate the tick. Interrupts are disabled + ; when this function is called. + call_x #vPortSetupTimerInterrupt + + ; Restore the context of the first task that is going to run. + portRESTORE_CONTEXT + .endasmfunc +;----------------------------------------------------------- + + .end + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/MSP430X/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/MSP430X/portmacro.h new file mode 100644 index 0000000..75b0eb4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CCS/MSP430X/portmacro.h @@ -0,0 +1,144 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Hardware includes. */ +#include "msp430.h" + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portBASE_TYPE portSHORT + +/* The stack type changes depending on the data model. */ +#ifdef __LARGE_DATA_MODEL__ + #define portSTACK_TYPE uint32_t +#else + #define portSTACK_TYPE uint16_t + #define portPOINTER_SIZE_TYPE uint16_t +#endif + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _disable_interrupt(); _nop() +#define portENABLE_INTERRUPTS() _enable_interrupt(); _nop() +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +extern void vTaskSwitchContext( void ); +#define portYIELD_FROM_ISR( x ) do { if( x ) vPortYield(); } while( 0 ) + +void vApplicationSetupTimerInterrupt( void ); + +/* sizeof( int ) != sizeof( long ) so a full printf() library is required if +run time stats information is to be displayed. */ +#define portLU_PRINTF_SPECIFIER_REQUIRED + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CMakeLists.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CMakeLists.txt new file mode 100644 index 0000000..ea54ec4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CMakeLists.txt @@ -0,0 +1,994 @@ +# FreeRTOS internal cmake file. Do not use it in user top-level project + +add_library(freertos_kernel_port STATIC + # 16-Bit DOS ports for BCC + $<$: + BCC/16BitDOS/common/portcomn.c + BCC/16BitDOS/Flsh186/port.c> + + $<$: + BCC/16BitDOS/common/portcomn.c + BCC/16BitDOS/PC/port.c> + + # ARMv7-M port for Texas Instruments Code Composer Studio + $<$: + CCS/ARM_CM3/port.c + CCS/ARM_CM3/portasm.asm> + + # ARMv7E-M port for Texas Instruments Code Composer Studio + $<$: + CCS/ARM_CM4F/port.c + CCS/ARM_CM4F/portasm.asm> + + # ARMv7-R port for Texas Instruments Code Composer Studio + $<$: + CCS/ARM_Cortex-R4/port.c + CCS/ARM_Cortex-R4/portASM.asm> + + # Texas Instruments MSP430 port for Texas Instruments Code Composer Studio + $<$: + CCS/MSP430X/port.c + CCS/MSP430X/portext.asm> + + # NXP (formerly Motorola, Freescale) Cold Fire and 68HCS12 ports for Code Warrior + $<$: + CodeWarrior/ColdFire_V1/port.c + CodeWarrior/ColdFire_V1/portasm.S> + + $<$: + CodeWarrior/ColdFire_V2/port.c + CodeWarrior/ColdFire_V2/portasm.S> + + $<$: + CodeWarrior/HCS12/port.c> + + # ARMv7-A port for GCC + $<$: + GCC/ARM_CA9/port.c + GCC/ARM_CA9/portASM.S> + + # ARMv8-A ports for GCC + $<$: + GCC/ARM_CA53_64_BIT/port.c + GCC/ARM_CA53_64_BIT/portASM.S> + + $<$: + GCC/ARM_CA53_64_BIT_SRE/port.c + GCC/ARM_CA53_64_BIT_SRE/portASM.S> + + # ARMv6-M port for GCC + $<$: + GCC/ARM_CM0/port.c> + + # ARMv6-M / Cortex-M0 Raspberry PI RP2040 port for GCC + $<$: + ThirdParty/GCC/RP2040/idle_task_static_memory.c + ThirdParty/GCC/RP2040/port.c> + + # ARMv7-M ports for GCC + $<$: + GCC/ARM_CM3/port.c> + + $<$: + GCC/ARM_CM3_MPU/port.c> + + # ARMv7E-M ports for GCC + $<$: + GCC/ARM_CM4_MPU/port.c> + + $<$: + GCC/ARM_CM4F/port.c> + + $<$: + GCC/ARM_CM7/r0p1/port.c> + + # ARMv8-M ports for GCC + $<$: + GCC/ARM_CM23/non_secure/port.c + GCC/ARM_CM23/non_secure/portasm.c> + + $<$: + GCC/ARM_CM23/secure/secure_context_port.c + GCC/ARM_CM23/secure/secure_context.c + GCC/ARM_CM23/secure/secure_heap.c + GCC/ARM_CM23/secure/secure_init.c> + + $<$: + GCC/ARM_CM23_NTZ/non_secure/port.c + GCC/ARM_CM23_NTZ/non_secure/portasm.c> + + $<$: + GCC/ARM_CM33/non_secure/port.c + GCC/ARM_CM33/non_secure/portasm.c> + + $<$: + GCC/ARM_CM33/secure/secure_context_port.c + GCC/ARM_CM33/secure/secure_context.c + GCC/ARM_CM33/secure/secure_heap.c + GCC/ARM_CM33/secure/secure_init.c> + + $<$: + GCC/ARM_CM33_NTZ/non_secure/port.c + GCC/ARM_CM33_NTZ/non_secure/portasm.c> + + $<$: + GCC/ARM_CM33_NTZ/non_secure/port.c + GCC/ARM_CM33_NTZ/non_secure/portasm.c + ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c> + + # ARMv8.1-M ports for GCC + $<$: + GCC/ARM_CM55/non_secure/port.c + GCC/ARM_CM55/non_secure/portasm.c> + + $<$: + GCC/ARM_CM55/secure/secure_context_port.c + GCC/ARM_CM55/secure/secure_context.c + GCC/ARM_CM55/secure/secure_heap.c + GCC/ARM_CM55/secure/secure_init.c> + + $<$: + GCC/ARM_CM55_NTZ/non_secure/port.c + GCC/ARM_CM55_NTZ/non_secure/portasm.c> + + $<$: + GCC/ARM_CM55_NTZ/non_secure/port.c + GCC/ARM_CM55_NTZ/non_secure/portasm.c + ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c> + + $<$: + GCC/ARM_CM85/non_secure/port.c + GCC/ARM_CM85/non_secure/portasm.c> + + $<$: + GCC/ARM_CM85/secure/secure_context_port.c + GCC/ARM_CM85/secure/secure_context.c + GCC/ARM_CM85/secure/secure_heap.c + GCC/ARM_CM85/secure/secure_init.c> + + $<$: + GCC/ARM_CM85_NTZ/non_secure/port.c + GCC/ARM_CM85_NTZ/non_secure/portasm.c> + + $<$: + GCC/ARM_CM85_NTZ/non_secure/port.c + GCC/ARM_CM85_NTZ/non_secure/portasm.c + ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c> + + # ARMv7-R ports for GCC + $<$: + GCC/ARM_CR5/port.c + GCC/ARM_CR5/portASM.S> + + $<$: + GCC/ARM_CRx_No_GIC/port.c + GCC/ARM_CRx_No_GIC/portASM.S> + + # ARMv4T ARM7TDMI ports for GCC + $<$: + GCC/ARM7_AT91FR40008/port.c + GCC/ARM7_AT91FR40008/portISR.c> + + $<$: + GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c + GCC/ARM7_AT91SAM7S/port.c + GCC/ARM7_AT91SAM7S/portISR.c> + + $<$: + GCC/ARM7_LPC2000/port.c + GCC/ARM7_LPC2000/portISR.c> + + $<$: + GCC/ARM7_LPC23xx/port.c + GCC/ARM7_LPC23xx/portISR.c> + + $<$: + GCC/STR75x/port.c + GCC/STR75x/portISR.c> + + # Microchip (formerly Ateml) AVR8 ports for GCC + $<$: + GCC/ATMega323/port.c> + + $<$: + ThirdParty/GCC/ATmega/port.c> + + $<$: + ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx/port.c> + + $<$: + ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0/port.c> + + # Microchip (formerly Ateml) AVR32 port for GCC + $<$: + GCC/AVR32_UC3/exception.S + GCC/AVR32_UC3/port.c> + + # NXP (formerly Motorola, Freescale) Cold Fire and 68HCS12 ports for GCC + $<$: + GCC/ColdFire_V2/port.c + GCC/ColdFire_V2/portasm.S> + + $<$: + GCC/HCS12/port.c> + + # Cortus APS3 soft core port for GCC + $<$: + GCC/CORTUS_APS3/port.c> + + # Renesas (formerly Hitach) H8S port for GCC + $<$: + GCC/H8S2329/port.c> + + # x86 / IA32 flat memory model port for GCC + $<$: + GCC/IA32_flat/port.c + GCC/IA32_flat/portASM.S> + + # Xilinx MicroBlaze soft core ports for GCC + $<$: + GCC/MicroBlaze/port.c + GCC/MicroBlaze/portasm.s> + + $<$: + GCC/MicroBlazeV8/port.c + GCC/MicroBlazeV8/port_exceptions.c + GCC/MicroBlazeV8/portasm.S> + + $<$: + GCC/MicroBlazeV9/port.c + GCC/MicroBlazeV9/port_exceptions.c + GCC/MicroBlazeV9/portasm.S> + + # Xilinx PCC4XX soft core ports for GCC + $<$: + GCC/PPC405_Xilinx/port.c + GCC/PPC405_Xilinx/portasm.S> + + $<$: + GCC/PPC440_Xilinx/port.c + GCC/PPC440_Xilinx/portasm.S> + + # Texas Instruments MSP430 port for GCC + $<$: + GCC/MSP430F449/port.c> + + # Intel (formerly Altera) NIOS II soft core port for GCC + $<$: + GCC/NiosII/port.c + GCC/NiosII/port_asm.S> + + # RISC-V architecture ports for GCC + $<$: + GCC/RISC-V/port.c + GCC/RISC-V/portASM.S> + + $<$: + GCC/RISC-V/port.c + GCC/RISC-V/portASM.S> + + # Renesas RL78 port for GCC + $<$: + GCC/RL78/port.c + GCC/RL78/portasm.S> + + # Renesas RX architecture ports for GCC + $<$: + GCC/RX100/port.c> + + $<$: + GCC/RX200/port.c> + + $<$: + GCC/RX600/port.c> + + $<$: + GCC/RX600v2/port.c> + + $<$: + GCC/RX700v3_DPFPU/port.c> + + # Infineon TriCore 1782 port for GCC + $<$: + GCC/TriCore_1782/port.c + GCC/TriCore_1782/porttrap.c> + + # Synopsys ARC architecture ports for GCC + $<$: + ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c + ThirdParty/GCC/ARC_EM_HS/arc_support.s + ThirdParty/GCC/ARC_EM_HS/freertos_tls.c + ThirdParty/GCC/ARC_EM_HS/port.c> + + $<$: + ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c + ThirdParty/GCC/ARC_v1/arc_support.s + ThirdParty/GCC/ARC_v1/port.c> + + # Posix Simulator port for GCC + $<$: + ThirdParty/GCC/Posix/port.c + ThirdParty/GCC/Posix/utils/wait_for_event.c> + + # Xtensa LX / Espressif ESP32 port for GCC + $<$: + ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c + ThirdParty/GCC/Xtensa_ESP32/port.c + ThirdParty/GCC/Xtensa_ESP32/portasm.S + ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S + ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c + ThirdParty/GCC/Xtensa_ESP32/xtensa_intr_asm.S + ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c + ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S + ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c + ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S + ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S> + + # Renesas (formerly NEC) 78K port for IAR EW78K + $<$: + IAR/78K0R/port.c + IAR/78K0R/portasm.s26> + + # ARMv7-A ports for IAR EWARM + $<$: + IAR/ARM_CA5_No_GIC/port.c + IAR/ARM_CA5_No_GIC/portASM.s> + + $<$: + IAR/ARM_CA9/port.c + IAR/ARM_CA9/portASM.s> + + # ARMv6-M port for IAR EWARM + $<$: + IAR/ARM_CM0/port.c + IAR/ARM_CM0/portasm.s> + + # ARMv7-M port for IAR EWARM + $<$: + IAR/ARM_CM3/port.c + IAR/ARM_CM3/portasm.s> + + # ARMv7E-M ports for IAR EWARM + $<$: + IAR/ARM_CM4F/port.c + IAR/ARM_CM4F/portasm.s> + + $<$: + IAR/ARM_CM4F_MPU/port.c + IAR/ARM_CM4F_MPU/portasm.s> + + $<$: + IAR/ARM_CM7/r0p1/port.c + IAR/ARM_CM7/r0p1/portasm.s> + + # ARMv8-M Ports for IAR EWARM + $<$: + IAR/ARM_CM23/non_secure/port.c + IAR/ARM_CM23/non_secure/portasm.s> + + $<$: + IAR/ARM_CM23/secure/secure_context_port_asm.s + IAR/ARM_CM23/secure/secure_context.c + IAR/ARM_CM23/secure/secure_heap.c + IAR/ARM_CM23/secure/secure_init.c> + + $<$: + IAR/ARM_CM23_NTZ/non_secure/port.c + IAR/ARM_CM23_NTZ/non_secure/portasm.s> + + $<$: + IAR/ARM_CM33/non_secure/port.c + IAR/ARM_CM33/non_secure/portasm.s> + + $<$: + IAR/ARM_CM33/secure/secure_context_port_asm.s + IAR/ARM_CM33/secure/secure_context.c + IAR/ARM_CM33/secure/secure_heap.c + IAR/ARM_CM33/secure/secure_init.c> + + $<$: + IAR/ARM_CM33_NTZ/non_secure/port.c + IAR/ARM_CM33_NTZ/non_secure/portasm.s> + + # ARMv8.1-M ports for IAR EWARM + $<$: + IAR/ARM_CM55/non_secure/port.c + IAR/ARM_CM55/non_secure/portasm.s> + + $<$: + IAR/ARM_CM55/secure/secure_context_port_asm.s + IAR/ARM_CM55/secure/secure_context.c + IAR/ARM_CM55/secure/secure_heap.c + IAR/ARM_CM55/secure/secure_init.c> + + $<$: + IAR/ARM_CM55_NTZ/non_secure/port.c + IAR/ARM_CM55_NTZ/non_secure/portasm.s> + + $<$: + IAR/ARM_CM85/non_secure/port.c + IAR/ARM_CM85/non_secure/portasm.s> + + $<$: + IAR/ARM_CM85/secure/secure_context_port_asm.s + IAR/ARM_CM85/secure/secure_context.c + IAR/ARM_CM85/secure/secure_heap.c + IAR/ARM_CM85/secure/secure_init.c> + + $<$: + IAR/ARM_CM85_NTZ/non_secure/port.c + IAR/ARM_CM85_NTZ/non_secure/portasm.s> + + # ARMv7-R Ports for IAR EWARM + $<$: + IAR/ARM_CRx_No_GIC/port.c + IAR/ARM_CRx_No_GIC/portASM.s> + + # Microchip (formerly Atmel) AVR8 ports for IAR EWAVR + $<$: + IAR/ATMega323/port.c + IAR/ATMega323/portmacro.s90> + + $<$: + IAR/AVR_AVRDx/port.c + IAR/AVR_AVRDx/portmacro.s90> + + $<$: + IAR/AVR_Mega0/port.c + IAR/AVR_Mega0/portmacro.s90> + + # Microchip (formerly Atmel) AVR32 port for IAR Embedded Workbench for AVR32 + $<$: + IAR/AVR32_UC3/exception.s82 + IAR/AVR32_UC3/port.c + IAR/AVR32_UC3/read.c + IAR/AVR32_UC3/write.c> + + # Texas Instruments MSP430 ports for IAR Embedded Workbench for MSP430 + $<$: + IAR/MSP430/port.c + IAR/MSP430/portext.s43> + + $<$: + IAR/MSP430X/port.c + IAR/MSP430X/portext.s43> + + # RISC-V architecture port for IAR Embedded Workbench for RISC-V + $<$: + IAR/RISC-V/port.c + IAR/RISC-V/portASM.s> + + # Renesas RL78 port for IAR EWRL78 + $<$: + IAR/RL78/port.c + IAR/RL78/portasm.s87> + + # Renesas RX architecture ports for IAR EWRX + $<$: + IAR/RX100/port.c + IAR/RX100/port_asm.s> + + $<$: + IAR/RX600/port.c + IAR/RX600/port_asm.s> + + $<$: + IAR/RX700v3_DPFPU/port.c> + + $<$: + IAR/RXv2/port.c + IAR/RXv2/port_asm.s> + + # Renesas (formerly NEC) V850ES port for IAR EWV850 + $<$: + IAR/V850ES/port.c + IAR/V850ES/portasm_Fx3.s85> + + $<$: + IAR/V850ES/port.c + IAR/V850ES/portasm_Hx2.s85> + + # ARMv4T ARM7TDMI ports for IAR Embedded Workbench for ARM + $<$: + IAR/STR71x/port.c + IAR/STR71x/portasm.s79> + + $<$: + IAR/STR75x/port.c + IAR/STR75x/portasm.s79> + + $<$: + IAR/LPC2000/port.c + IAR/LPC2000/portasm.s79> + + $<$: + IAR/AtmelSAM7S64/port.c + IAR/AtmelSAM7S64/portasm.s79> + + # ARMv5TE ARM926 ports for IAR Embedded Workbench for ARM + $<$: + IAR/STR91x/port.c + IAR/STR91x/portasm.s79> + + $<$: + IAR/AtmelSAM9XE/port.c + IAR/AtmelSAM9XE/portasm.s79> + + # ARM Cortex-M4F port for the MikroElektronika MikroC compiler + $<$: + MikroC/ARM_CM4F/port.c> + + # Microchip PIC18 8-bit MCU port for MPLAB XC8 + $<$: + MPLAB/PIC18F/port.c> + + # Microchip PIC24 16-bit MCU port for MPLAB XC16 + $<$: + MPLAB/PIC24_dsPIC/port.c + MPLAB/PIC24_dsPIC/portasm_PIC24.S> # TODO: What to do with portasm_dsPIC.S ? + + # Microchip MIPS 32-Bit MCU ports for MPLAB XC32 + $<$: + MPLAB/PIC32MEC14xx/port.c + MPLAB/PIC32MEC14xx/port_asm.S> + + $<$: + MPLAB/PIC32MX/port.c + MPLAB/PIC32MX/port_asm.S> + + $<$: + MPLAB/PIC32MZ/port.c + MPLAB/PIC32MZ/port_asm.S> + + # Windows Simulator for Microsoft Visual C Compiler and MinGW GCC + $<$: + MSVC-MingW/port.c> + + # 16 bit DOS ports for Open Watcom + $<$: + oWatcom/16BitDOS/common/portcomn.c + oWatcom/16BitDOS/Flsh186/port.c> + + $<$: + oWatcom/16BitDOS/common/portcomn.c + oWatcom/16BitDOS/PC/port.c> + + $<$: + Paradigm/Tern_EE/large_untested/port.c> + + $<$: + Paradigm/Tern_EE/small/port.c> + + # Renesas RX mcu ports for Renesas CC-RX + $<$: + Renesas/RX100/port.c + Renesas/RX100/port_asm.src> + + $<$: + Renesas/RX200/port.c + Renesas/RX200/port_asm.src> + + $<$: + Renesas/RX600/port.c + Renesas/RX600/port_asm.src> + + $<$: + Renesas/RX600v2/port.c + Renesas/RX600v2/port_asm.src> + + $<$: + Renesas/RX700v3_DPFPU/port.c + Renesas/RX700v3_DPFPU/port_asm.src> + + # Renesas (formerly Hitach) SHA2 SuperH port for the Renesas SH C Compiler + $<$: + Renesas/SH2A_FPU/port.c + Renesas/SH2A_FPU/portasm.src> + + # Texas Instruments MSP430 port for Rowley CrossWorks + $<$: + Rowley/MSP430F449/port.c + Rowley/MSP430F449/portext.asm> + + # ARMv7-A Cortex-A9 port for ARM RVDS / armcc + $<$: + RVDS/ARM_CA9/port.c + RVDS/ARM_CA9/portASM.s> + + # ARMv6-M port for ARM RVDS / armcc + $<$: + RVDS/ARM_CM0/port.c> + + # ARMv7-M port for ARM RVDS / armcc + $<$: + RVDS/ARM_CM3/port.c> + + # ARMv7E-M ports for ARM RVDS / armcc + $<$: + RVDS/ARM_CM4_MPU/port.c> + + $<$: + RVDS/ARM_CM4F/port.c> + + $<$: + RVDS/ARM_CM7/r0p1/port.c> + + # ARMv4T / ARM7TDMI LPC21XX port for ARM RVDS / armcc + $<$: + RVDS/ARM7_LPC21xx/port.c + RVDS/ARM7_LPC21xx/portASM.s> + + # Cygnal c8051 port for SDCC (Small Device C Compiler) + $<$: + SDCC/Cygnal/port.c> + + # Infineon (formerly Fujitsu, Spansion, Cypress) MB9x ports for Softune C Compiler + $<$: + Softune/MB91460/__STD_LIB_sbrk.c + Softune/MB91460/port.c> + + $<$: + Softune/MB96340/__STD_LIB_sbrk.c + Softune/MB96340/port.c> + + # ARMv7E-M (Cortex-M4F) port for TASKING VX-toolset for ARM + $<$: + Tasking/ARM_CM4F/port.c + Tasking/ARM_CM4F/port_asm.asm> + + # Port for C-SKY T-HEAD CK802 + $<$: + ThirdParty/CDK/T-HEAD_CK802/port.c + ThirdParty/CDK/T-HEAD_CK802/portasm.S> + + # Tensilica Xtensa port for XCC + $<$: + ThirdParty/XCC/Xtensa/port.c + ThirdParty/XCC/Xtensa/portasm.S + ThirdParty/XCC/Xtensa/portclib.c + ThirdParty/XCC/Xtensa/xtensa_context.S + ThirdParty/XCC/Xtensa/xtensa_init.c + ThirdParty/XCC/Xtensa/xtensa_intr_asm.S + ThirdParty/XCC/Xtensa/xtensa_intr.c + ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c + ThirdParty/XCC/Xtensa/xtensa_vectors.S> + + # Microchip PIC18 port for WIZ-C + $<$: + WizC/PIC18/port.c + WizC/PIC18/Drivers/Tick/isrTick.c + WizC/PIC18/Drivers/Tick/Tick.c> +) + +if( FREERTOS_PORT MATCHES "GCC_ARM_CM(3|4)_MPU" OR + FREERTOS_PORT STREQUAL "IAR_ARM_CM4F_MPU" OR + FREERTOS_PORT STREQUAL "RVDS_ARM_CM4_MPU" OR + FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|55|85)_NTZ_NONSECURE" OR + FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|55|85)_NONSECURE" OR + FREERTOS_PORT MATCHES "GCC_ARM_CM(33|55|85)_TFM" OR + FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|55|85)_NTZ_NONSECURE" OR + FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|55|85)_NONSECURE" +) + target_sources(freertos_kernel_port PRIVATE Common/mpu_wrappers.c) +endif() + +target_include_directories(freertos_kernel_port PUBLIC + # 16-Bit DOS ports for BCC + $<$: + ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/common + ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/Flsh186> + + $<$: + ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/common + ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/PC> + + # ARMv7-M port for Texas Instruments Code Composer Studio + $<$:${CMAKE_CURRENT_LIST_DIR}/CCS/ARM_CM3> + + # ARMv7E-M port for Texas Instruments Code Composer Studio + $<$:${CMAKE_CURRENT_LIST_DIR}/CCS/ARM_CM4F> + + # ARMv7-R port for Texas Instruments Code Composer Studio + $<$:${CMAKE_CURRENT_LIST_DIR}/CCS/ARM_Cortex-R4> + + # Texas Instruments MSP430 port for Texas Instruments Code Composer Studio + $<$:${CMAKE_CURRENT_LIST_DIR}/CCS/MSP430X> + + # NXP (formerly Motorola, Freescale) Cold Fire and 68HCS12 ports for Code Warrior + $<$:${CMAKE_CURRENT_LIST_DIR}/CodeWarrior/ColdFire_V1> + $<$:${CMAKE_CURRENT_LIST_DIR}/CodeWarrior/ColdFire_V2> + $<$:${CMAKE_CURRENT_LIST_DIR}/CodeWarrior/HCS12> + + # ARMv7-A port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA9> + + # ARMv8-A ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA53_64_BIT> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA53_64_BIT_SRE> + + # ARMv6-M port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM0> + + # ARMv6-M / Cortex-M0 Raspberry PI RP2040 port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/RP2040/include> + + # ARMv7-M ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM3> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM3_MPU> + + # ARMv7E-M ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM4_MPU> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM4F> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM7/r0p1> + + # ARMv8-M ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM23/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM23/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM23_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM33/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM33/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM33_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM33_NTZ/non_secure> + + # ARMv8.1-M ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85_NTZ/non_secure> + + # ARMv7-R ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CR5> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CRx_No_GIC> + + # ARMv4T ARM7TDMI ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_AT91FR40008> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_AT91SAM7S> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_LPC2000> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_LPC23xx> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/STR75x> + + # Microchip (formerly Ateml) AVR8 ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ATMega323> + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/ATmega> + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx> + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0> + + # Microchip (formerly Ateml) AVR32 port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/AVR32_UC3> + + # NXP (formerly Motorola, Freescale) Cold Fire and 68HCS12 ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ColdFire_V2> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/HCS12> + + # Cortus APS3 soft core port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/CORTUS_APS3> + + # Renesas (formerly Hitach) H8S port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/H8S2329> + + # x86 / IA32 flat memory model port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/IA32_flat> + + # Intel (formerly Altera) NIOS II soft core port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/NiosII> + + # Texas Instruments MSP430 port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/MSP430F449> + + # Xilinx MicroBlaze soft core ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/MicroBlaze> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/MicroBlazeV8> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/MicroBlazeV9> + + # Xilinx PCC4XX soft core ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/PPC405_Xilinx> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/PPC440_Xilinx> + + # RISC-V architecture ports for GCC + $<$: + ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V + ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions> + + $<$: + ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V + ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM> + + # Renesas RL78 port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/RL78> + + # Renesas RX architecture ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/RX100> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/RX200> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/RX600> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/RX600v2> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/RX700v3_DPFPU> + + # Infineon TriCore 1782 port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/TriCore_1782> + + # Synopsys ARC architecture ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/ARC_EM_HS> + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/ARC_v1> + + # Posix Simulator port for GCC + $<$: + ${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/Posix + ${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/Posix/utils> + + # Xtensa LX / Espressif ESP32 port for GCC + $<$: + ${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/Xtensa_ESP32 + ${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/Xtensa_ESP32/include> + + # Renesas (formerly NEC) 78K port for IAR EW78K + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/78K0R> + + # ARMv7-A ports for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CA5_No_GIC> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CA9> + + # ARMv6-M port for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM0> + + # ARMv7-M port for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM3> + + # ARMv7E-M ports for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM4F> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM4F_MPU> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM7/r0p1> + + # ARMv8-M Ports for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM23/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM23/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM23_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33_NTZ/non_secure> + + # ARMv8.1-M ports for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85_NTZ/non_secure> + + # ARMv7-R Ports for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CRx_No_GIC> + + # ARMv4T ARM7TDMI ports for IAR Embedded Workbench for ARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/STR71x> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/STR75x> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/LPC2000> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/AtmelSAM7S64> + + # ARMv5TE ARM926 ports for IAR Embedded Workbench for ARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/STR91x> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/AtmelSAM9XE> + + # Microchip (formerly Atmel) AVR8 ports for IAR EWAVR + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ATMega323> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/AVR_AVRDx> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/AVR_Mega0> + + # Microchip (formerly Atmel) AVR32 port for IAR Embedded Workbench for AVR32 + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/AVR32_UC3> + + # Texas Instruments MSP430 ports for IAR Embedded Workbench for MSP430 + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/MSP430> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/MSP430X> + + # RISC-V architecture port for IAR Embedded Workbench for RISC-V + $<$: + ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V + ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions> + + # Renesas RL78 port for IAR EWRL78 + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/RL78> + + # Renesas RX architecture ports for IAR EWRX + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/RX100> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/RX600> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/RX700v3_DPFPU> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/RXv2> + + # Renesas (formerly NEC) V850ES port for IAR EWV850 + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/V850ES> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/V850ES> + + # ARM Cortex-M4F port for the MikroElektronika MikroC compiler + $<$:${CMAKE_CURRENT_LIST_DIR}/MikroC/ARM_CM4F> + + # Microchip PIC18 8-bit MCU port for MPLAB XC8 + $<$:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC18F> + + # Microchip PIC24 16-bit MCU port for MPLAB XC16 + $<$:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC24_dsPIC> + + # Microchip MIPS 32-Bit MCU ports for MPLAB XC32 + $<$:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC32MEC14xx> + $<$:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC32MX> + $<$:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC32MZ> + + # Windows Simulator for Microsoft Visual C Compiler and MinGW GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/MSVC-MingW> + + # 16 bit DOS ports for Open Watcom + $<$: + ${CMAKE_CURRENT_LIST_DIR}/oWatcom/16BitDOS/common + ${CMAKE_CURRENT_LIST_DIR}/oWatcom/16BitDOS/Flsh186> + $<$: + ${CMAKE_CURRENT_LIST_DIR}/oWatcom/16BitDOS/common + ${CMAKE_CURRENT_LIST_DIR}/oWatcom/16BitDOS/PC> + + $<$:${CMAKE_CURRENT_LIST_DIR}/Paradigm/Tern_EE/large_untested> + $<$:${CMAKE_CURRENT_LIST_DIR}/Paradigm/Tern_EE/small> + + # Renesas RX mcu ports for Renesas CC-RX + $<$:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX100> + $<$:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX200> + $<$:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX600> + $<$:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX600v2> + $<$:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX700v3_DPFPU> + + # Renesas (formerly Hitach) SHA2 SuperH port for the Renesas SH C Compiler + $<$:${CMAKE_CURRENT_LIST_DIR}/Renesas/SH2A_FPU> + + # Texas Instruments MSP430 port for Rowley CrossWorks + $<$:${CMAKE_CURRENT_LIST_DIR}/Rowley/MSP430F449> + + # ARMv7-A Cortex-A9 port for ARM RVDS / armcc + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CA9> + + # ARMv6-M port for ARM RVDS / armcc + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM0> + + # ARMv7-M port for ARM RVDS / armcc + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM3> + + # ARMv7E-M ports for ARM RVDS / armcc + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM4_MPU> + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM4F> + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM7/r0p1> + + # ARMv4T / ARM7TDMI LPC21XX port for ARM RVDS / armcc + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM7_LPC21xx> + + # Cygnal c8051 port for SDCC (Small Device C Compiler) + $<$:${CMAKE_CURRENT_LIST_DIR}/SDCC/Cygnal> + + # Infineon (formerly Fujitsu, Spansion, Cypress) MB9x ports for Softune C Compiler + $<$:${CMAKE_CURRENT_LIST_DIR}/Softune/MB91460> + $<$:${CMAKE_CURRENT_LIST_DIR}/Softune/MB96340> + + # ARMv7E-M (Cortex-M4F) port for TASKING VX-toolset for ARM + $<$:${CMAKE_CURRENT_LIST_DIR}/Tasking/ARM_CM4F> + + # Port for C-SKY T-HEAD CK802 + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/CDK/T-HEAD_CK802> + + # Tensilica Xtensa port for XCC + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/XCC/Xtensa> + + # Microchip PIC18 port for WIZ-C + $<$:${CMAKE_CURRENT_LIST_DIR}/WizC/PIC18> +) + +target_link_libraries(freertos_kernel_port + PUBLIC + $<$:pico_base_headers> + $<$:idf::esp32> + PRIVATE + freertos_kernel + "$<$:hardware_clocks;hardware_exception>" + $<$:winmm> # Windows library which implements timers +) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V1/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V1/port.c new file mode 100644 index 0000000..bed369d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V1/port.c @@ -0,0 +1,184 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + + +#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 ) + +/* Supervisor mode set. */ +#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000) + +/* The clock prescale into the timer peripheral. */ +#define portPRESCALE_VALUE ( ( uint8_t ) 10 ) + +/* The clock frequency into the RTC. */ +#define portRTC_CLOCK_HZ ( ( uint32_t ) 1000 ) + +asm void interrupt VectorNumber_VL1swi vPortYieldISR( void ); +static void prvSetupTimerInterrupt( void ); + +/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This +will be set to 0 prior to the first task being started. */ +static uint32_t ulCriticalNesting = 0x9999UL; + +/*-----------------------------------------------------------*/ + +StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + +uint32_t ulOriginalA5; + + __asm{ MOVE.L A5, ulOriginalA5 }; + + + *pxTopOfStack = (StackType_t) 0xDEADBEEF; + pxTopOfStack--; + + /* Exception stack frame starts with the return address. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/ + pxTopOfStack -= 14; /* A5 to D0. */ + + /* Parameter in A0. */ + *( pxTopOfStack + 8 ) = ( StackType_t ) pvParameters; + + /* A5 must be maintained as it is resurved by the compiler. */ + *( pxTopOfStack + 13 ) = ulOriginalA5; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + ulCriticalNesting = 0UL; + + /* Configure a timer to generate the tick interrupt. */ + prvSetupTimerInterrupt(); + + /* Start the first task executing. */ + vPortStartFirstTask(); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Prescale by 1 - ie no prescale. */ + RTCSC |= 8; + + /* Compare match value. */ + RTCMOD = portRTC_CLOCK_HZ / configTICK_RATE_HZ; + + /* Enable the RTC to generate interrupts - interrupts are already disabled + when this code executes. */ + RTCSC_RTIE = 1; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented as there is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + if( ulCriticalNesting == 0UL ) + { + /* Guard against context switches being pended simultaneously with a + critical section being entered. */ + do + { + portDISABLE_INTERRUPTS(); + if( INTC_FRC == 0UL ) + { + break; + } + + portENABLE_INTERRUPTS(); + + } while( 1 ); + } + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + ulCriticalNesting--; + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void vPortYieldHandler( void ) +{ +uint32_t ulSavedInterruptMask; + + ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Note this will clear all forced interrupts - this is done for speed. */ + INTC_CFRC = 0x3E; + vTaskSwitchContext(); + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); +} +/*-----------------------------------------------------------*/ + +void interrupt VectorNumber_Vrtc vPortTickISR( void ) +{ +uint32_t ulSavedInterruptMask; + + /* Clear the interrupt. */ + RTCSC |= RTCSC_RTIF_MASK; + + /* Increment the RTOS tick. */ + ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); +} + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V1/portasm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V1/portasm.S new file mode 100644 index 0000000..10c2f99 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V1/portasm.S @@ -0,0 +1,131 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Purpose: Lowest level routines for all ColdFire processors. + * + * Notes: + * + * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale + * supplied source files. + */ + + .global ulPortSetIPL + .global _ulPortSetIPL + .global mcf5xxx_wr_cacrx + .global _mcf5xxx_wr_cacrx + .global vPortYieldISR + .global _vPortYieldISR + .global vPortStartFirstTask + .global _vPortStartFirstTask + .extern _pxCurrentTCB + .extern _vPortYieldHandler + + .text + +.macro portSAVE_CONTEXT + + lea.l (-60, sp), sp + movem.l d0-a6, (sp) + move.l _pxCurrentTCB, a0 + move.l sp, (a0) + + .endm + +.macro portRESTORE_CONTEXT + + move.l _pxCurrentTCB, a0 + move.l (a0), sp + movem.l (sp), d0-a6 + lea.l (60, sp), sp + rte + + .endm + +/********************************************************************/ +/* + * This routines changes the IPL to the value passed into the routine. + * It also returns the old IPL value back. + * Calling convention from C: + * old_ipl = asm_set_ipl(new_ipl); + * For the Diab Data C compiler, it passes return value thru D0. + * Note that only the least significant three bits of the passed + * value are used. + */ + +ulPortSetIPL: +_ulPortSetIPL: + link A6,#-8 + movem.l D6-D7,(SP) + + move.w SR,D7 /* current sr */ + + move.l D7,D6 /* prepare return value */ + andi.l #0x0700,D6 /* mask out IPL */ + lsr.l #8,D6 /* IPL */ + + andi.l #0x07,D0 /* least significant three bits */ + lsl.l #8,D0 /* move over to make mask */ + + andi.l #0x0000F8FF,D7 /* zero out current IPL */ + or.l D0,D7 /* place new IPL in sr */ + move.w D7,SR + + move.l D6, D0 /* Return value in D0. */ + movem.l (SP),D6-D7 + lea 8(SP),SP + unlk A6 + rts +/********************************************************************/ + +mcf5xxx_wr_cacrx: +_mcf5xxx_wr_cacrx: + move.l 4(sp),d0 + .long 0x4e7b0002 /* movec d0,cacr */ + nop + rts + +/********************************************************************/ + +/* Yield interrupt. */ +_vPortYieldISR: +vPortYieldISR: + portSAVE_CONTEXT + jsr _vPortYieldHandler + portRESTORE_CONTEXT + +/********************************************************************/ + + +vPortStartFirstTask: +_vPortStartFirstTask: + portRESTORE_CONTEXT + + .end + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V1/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V1/portmacro.h new file mode 100644 index 0000000..19b92be --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V1/portmacro.h @@ -0,0 +1,113 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +uint32_t ulPortSetIPL( uint32_t ); +#define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 ) + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +extern UBaseType_t uxPortSetInterruptMaskFromISR( void ); +extern void vPortClearInterruptMaskFromISR( UBaseType_t ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister ) + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portNOP() asm volatile ( "nop" ) + +/* Context switches are requested using the force register. */ +#define portYIELD() INTC_SFRC = 0x3E; portNOP(); portNOP(); portNOP(); portNOP(); portNOP() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 ) + + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V2/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V2/port.c new file mode 100644 index 0000000..981f2cc --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V2/port.c @@ -0,0 +1,148 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + + +#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 ) + +/* Supervisor mode set. */ +#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000) + +/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This +will be set to 0 prior to the first task being started. */ +static uint32_t ulCriticalNesting = 0x9999UL; + + +#define portSAVE_CONTEXT() \ + lea.l (-60, %sp), %sp; \ + movem.l %d0-%fp, (%sp); \ + move.l pxCurrentTCB, %a0; \ + move.l %sp, (%a0); + +#define portRESTORE_CONTEXT() \ + move.l pxCurrentTCB, %a0; \ + move.l (%a0), %sp; \ + movem.l (%sp), %d0-%fp; \ + lea.l %sp@(60), %sp; \ + rte + + + +/*-----------------------------------------------------------*/ + +StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0xDEADBEEF; + pxTopOfStack--; + + /* Exception stack frame starts with the return address. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/ + pxTopOfStack -= 14; /* A5 to D0. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + ulCriticalNesting = 0UL; + + /* Configure the interrupts used by this port. */ + vApplicationSetupInterrupts(); + + /* Start the first task executing. */ + vPortStartFirstTask(); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented as there is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + if( ulCriticalNesting == 0UL ) + { + /* Guard against context switches being pended simultaneously with a + critical section being entered. */ + do + { + portDISABLE_INTERRUPTS(); + if( MCF_INTC0_INTFRCH == 0UL ) + { + break; + } + + portENABLE_INTERRUPTS(); + + } while( 1 ); + } + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + ulCriticalNesting--; + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void vPortYieldHandler( void ) +{ +uint32_t ulSavedInterruptMask; + + ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + /* Note this will clear all forced interrupts - this is done for speed. */ + MCF_INTC0_INTFRCL = 0; + vTaskSwitchContext(); + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); +} +/*-----------------------------------------------------------*/ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V2/portasm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V2/portasm.S new file mode 100644 index 0000000..bc45ea6 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V2/portasm.S @@ -0,0 +1,131 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Purpose: Lowest level routines for all ColdFire processors. + * + * Notes: + * + * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale + * supplied source files. + */ + + .global ulPortSetIPL + .global _ulPortSetIPL + .global mcf5xxx_wr_cacrx + .global _mcf5xxx_wr_cacrx + .global vPortYieldISR + .global _vPortYieldISR + .global vPortStartFirstTask + .global _vPortStartFirstTask + .extern _pxCurrentTCB + .extern _vPortYieldHandler + + .text + +.macro portSAVE_CONTEXT + + lea.l (-60, sp), sp + movem.l d0-a6, (sp) + move.l _pxCurrentTCB, a0 + move.l sp, (a0) + + .endm + +.macro portRESTORE_CONTEXT + + move.l _pxCurrentTCB, a0 + move.l (a0), sp + movem.l (sp), d0-a6 + lea.l (60, sp), sp + rte + + .endm + +/********************************************************************/ +/* + * This routines changes the IPL to the value passed into the routine. + * It also returns the old IPL value back. + * Calling convention from C: + * old_ipl = asm_set_ipl(new_ipl); + * For the Diab Data C compiler, it passes return value thru D0. + * Note that only the least significant three bits of the passed + * value are used. + */ + +ulPortSetIPL: +_ulPortSetIPL: + link A6,#-8 + movem.l D6-D7,(SP) + + move.w SR,D7 /* current sr */ + + move.l D7,D0 /* prepare return value */ + andi.l #0x0700,D0 /* mask out IPL */ + lsr.l #8,D0 /* IPL */ + + move.l 8(A6),D6 /* get argument */ + andi.l #0x07,D6 /* least significant three bits */ + lsl.l #8,D6 /* move over to make mask */ + + andi.l #0x0000F8FF,D7 /* zero out current IPL */ + or.l D6,D7 /* place new IPL in sr */ + move.w D7,SR + + movem.l (SP),D6-D7 + lea 8(SP),SP + unlk A6 + rts +/********************************************************************/ + +mcf5xxx_wr_cacrx: +_mcf5xxx_wr_cacrx: + move.l 4(sp),d0 + .long 0x4e7b0002 /* movec d0,cacr */ + nop + rts + +/********************************************************************/ + +/* Yield interrupt. */ +_vPortYieldISR: +vPortYieldISR: + portSAVE_CONTEXT + jsr _vPortYieldHandler + portRESTORE_CONTEXT + +/********************************************************************/ + + +vPortStartFirstTask: +_vPortStartFirstTask: + portRESTORE_CONTEXT + + .end + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V2/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V2/portmacro.h new file mode 100644 index 0000000..b7501e2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/ColdFire_V2/portmacro.h @@ -0,0 +1,112 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ +uint32_t ulPortSetIPL( uint32_t ); +#define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 ) + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +extern UBaseType_t uxPortSetInterruptMaskFromISR( void ); +extern void vPortClearInterruptMaskFromISR( UBaseType_t ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister ) + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +#define portNOP() asm volatile ( "nop" ) + +/* Note this will overwrite all other bits in the force register, it is done this way for speed. */ +#define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() /* -32 as we are using the high word of the 64bit mask. */ + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 ) + + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/HCS12/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/HCS12/port.c new file mode 100644 index 0000000..53ea0f3 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/HCS12/port.c @@ -0,0 +1,238 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the HCS12 port. + *----------------------------------------------------------*/ + + +/* + * Configure a timer to generate the RTOS tick at the frequency specified + * within FreeRTOSConfig.h. + */ +static void prvSetupTimerInterrupt( void ); + +/* Interrupt service routines have to be in non-banked memory - as does the +scheduler startup function. */ +#pragma CODE_SEG __NEAR_SEG NON_BANKED + + /* Manual context switch function. This is the SWI ISR. */ + void interrupt vPortYield( void ); + + /* Tick context switch function. This is the timer ISR. */ + void interrupt vPortTickInterrupt( void ); + + /* Simply called by xPortStartScheduler(). xPortStartScheduler() does not + start the scheduler directly because the header file containing the + xPortStartScheduler() prototype is part of the common kernel code, and + therefore cannot use the CODE_SEG pragma. */ + static BaseType_t xBankedStartScheduler( void ); + +#pragma CODE_SEG DEFAULT + +/* Calls to portENTER_CRITICAL() can be nested. When they are nested the +critical section should not be left (i.e. interrupts should not be re-enabled) +until the nesting depth reaches 0. This variable simply tracks the nesting +depth. Each task maintains it's own critical nesting depth variable so +uxCriticalNesting is saved and restored from the task stack during a context +switch. */ +volatile UBaseType_t uxCriticalNesting = 0xff; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This can be uncommented to provide useful stack markers when debugging. + + *pxTopOfStack = ( StackType_t ) 0x11; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x33; + pxTopOfStack--; + */ + + + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. In this case the stack as + expected by the HCS12 RTI instruction. */ + + + /* The address of the task function is placed in the stack byte at a time. */ + *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 ); + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 ); + pxTopOfStack--; + + /* Next are all the registers that form part of the task context. */ + + /* Y register */ + *pxTopOfStack = ( StackType_t ) 0xff; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xee; + pxTopOfStack--; + + /* X register */ + *pxTopOfStack = ( StackType_t ) 0xdd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xcc; + pxTopOfStack--; + + /* A register contains parameter high byte. */ + *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 ); + pxTopOfStack--; + + /* B register contains parameter low byte. */ + *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 ); + pxTopOfStack--; + + /* CCR: Note that when the task starts interrupts will be enabled since + "I" bit of CCR is cleared */ + *pxTopOfStack = ( StackType_t ) 0x00; + pxTopOfStack--; + + #ifdef BANKED_MODEL + /* The page of the task. */ + *pxTopOfStack = ( StackType_t ) ( ( int ) pxCode ); + pxTopOfStack--; + #endif + + /* Finally the critical nesting depth is initialised with 0 (not within + a critical section). */ + *pxTopOfStack = ( StackType_t ) 0x00; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the HCS12 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + TickTimer_SetFreqHz( configTICK_RATE_HZ ); + TickTimer_Enable(); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* xPortStartScheduler() does not start the scheduler directly because + the header file containing the xPortStartScheduler() prototype is part + of the common kernel code, and therefore cannot use the CODE_SEG pragma. + Instead it simply calls the locally defined xBankedStartScheduler() - + which does use the CODE_SEG pragma. */ + + return xBankedStartScheduler(); +} +/*-----------------------------------------------------------*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED + +static BaseType_t xBankedStartScheduler( void ) +{ + /* Configure the timer that will generate the RTOS tick. Interrupts are + disabled when this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task. */ + portRESTORE_CONTEXT(); + + /* Simulate the end of an interrupt to start the scheduler off. */ + __asm( "rti" ); + + /* Should not get here! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +/* + * Context switch functions. These are both interrupt service routines. + */ + +/* + * Manual context switch forced by calling portYIELD(). This is the SWI + * handler. + */ +void interrupt vPortYield( void ) +{ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * RTOS tick interrupt service routine. If the cooperative scheduler is + * being used then this simply increments the tick count. If the + * preemptive scheduler is being used a context switch can occur. + */ +void interrupt vPortTickInterrupt( void ) +{ + #if configUSE_PREEMPTION == 1 + { + /* A context switch might happen so save the context. */ + portSAVE_CONTEXT(); + + /* Increment the tick ... */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + TFLG1 = 1; + + /* Restore the context of a task - which may be a different task + to that interrupted. */ + portRESTORE_CONTEXT(); + } + #else + { + xTaskIncrementTick(); + TFLG1 = 1; + } + #endif +} + +#pragma CODE_SEG DEFAULT + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/HCS12/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/HCS12/portmacro.h new file mode 100644 index 0000000..858e2da --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/CodeWarrior/HCS12/portmacro.h @@ -0,0 +1,203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portYIELD() __asm( "swi" ); +#define portNOP() __asm( "nop" ); +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENABLE_INTERRUPTS() __asm( "cli" ) +#define portDISABLE_INTERRUPTS() __asm( "sei" ) + +/* + * Disable interrupts before incrementing the count of critical section nesting. + * The nesting count is maintained so we know when interrupts should be + * re-enabled. Once interrupts are disabled the nesting count can be accessed + * directly. Each task maintains its own nesting count. + */ +#define portENTER_CRITICAL() \ +{ \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + uxCriticalNesting++; \ +} + +/* + * Interrupts are disabled so we can access the nesting count directly. If the + * nesting is found to be 0 (no nesting) then we are leaving the critical + * section and interrupts can be re-enabled. + */ +#define portEXIT_CRITICAL() \ +{ \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * These macros are very simple as the processor automatically saves and + * restores its registers as interrupts are entered and exited. In + * addition to the (automatically stacked) registers we also stack the + * critical nesting count. Each task maintains its own critical nesting + * count as it is legitimate for a task to yield from within a critical + * section. If the banked memory model is being used then the PPAGE + * register is also stored as part of the tasks context. + */ + +#ifdef BANKED_MODEL + /* + * Load the stack pointer for the task, then pull the critical nesting + * count and PPAGE register from the stack. The remains of the + * context are restored by the RTI instruction. + */ + #define portRESTORE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "lds 0, x" ); \ + __asm( "pula" ); \ + __asm( "staa uxCriticalNesting" ); \ + __asm( "pula" ); \ + __asm( "staa 0x30" ); /* 0x30 = PPAGE */ \ + } + + /* + * By the time this macro is called the processor has already stacked the + * registers. Simply stack the nesting count and PPAGE value, then save + * the task stack pointer. + */ + #define portSAVE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + __asm( "ldaa 0x30" ); /* 0x30 = PPAGE */ \ + __asm( "psha" ); \ + __asm( "ldaa uxCriticalNesting" ); \ + __asm( "psha" ); \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "sts 0, x" ); \ + } +#else + + /* + * These macros are as per the BANKED versions above, but without saving + * and restoring the PPAGE register. + */ + + #define portRESTORE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "lds 0, x" ); \ + __asm( "pula" ); \ + __asm( "staa uxCriticalNesting" ); \ + } + + #define portSAVE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + __asm( "ldaa uxCriticalNesting" ); \ + __asm( "psha" ); \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "sts 0, x" ); \ + } +#endif + +/* + * Utility macro to call macros above in correct order in order to perform a + * task switch from within a standard ISR. This macro can only be used if + * the ISR does not use any local (stack) variables. If the ISR uses stack + * variables portYIELD() should be used in it's place. + */ +#define portTASK_SWITCH_FROM_ISR() \ + portSAVE_CONTEXT(); \ + vTaskSwitchContext(); \ + portRESTORE_CONTEXT(); + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Common/mpu_wrappers.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Common/mpu_wrappers.c new file mode 100644 index 0000000..23f8ff9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Common/mpu_wrappers.c @@ -0,0 +1,2541 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Implementation of the wrapper functions used to raise the processor privilege + * before calling a standard FreeRTOS API function. + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( portUSING_MPU_WRAPPERS == 1 ) + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, + const char * const pcName, + uint16_t usStackDepth, + void * pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxPriority = uxPriority & ~( portPRIVILEGE_BIT ); + portMEMORY_BARRIER(); + + xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ); + } + + return xReturn; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + TaskHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxPriority = uxPriority & ~( portPRIVILEGE_BIT ); + portMEMORY_BARRIER(); + + xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer ); + } + + return xReturn; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelete == 1 ) + void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskDelete( pxTaskToDelete ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskDelete( pxTaskToDelete ); + } + } + #endif /* if ( INCLUDE_vTaskDelete == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); + } + + return xReturn; + } + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskAbortDelay( xTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskAbortDelay( xTask ); + } + + return xReturn; + } + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + void MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskDelay( xTicksToDelay ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskDelay( xTicksToDelay ); + } + } + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */ + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxTaskPriorityGet( pxTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxTaskPriorityGet( pxTask ); + } + + return uxReturn; + } + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskPrioritySet == 1 ) + void MPU_vTaskPrioritySet( TaskHandle_t pxTask, + UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskPrioritySet( pxTask, uxNewPriority ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskPrioritySet( pxTask, uxNewPriority ); + } + } + #endif /* if ( INCLUDE_vTaskPrioritySet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + eTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */ + { + eTaskState eReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + eReturn = eTaskGetState( pxTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + eReturn = eTaskGetState( pxTask ); + } + + return eReturn; + } + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState ); + } + } + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */ + { + TaskHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + xReturn = xTaskGetIdleTaskHandle(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGetIdleTaskHandle(); + } + + return xReturn; + } + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskSuspend( pxTaskToSuspend ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskSuspend( pxTaskToSuspend ); + } + } + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + void MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskResume( pxTaskToResume ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskResume( pxTaskToResume ); + } + } + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskSuspendAll(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskSuspendAll(); + } + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskResumeAll(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskResumeAll(); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */ + { + TickType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGetTickCount(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGetTickCount(); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */ + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxTaskGetNumberOfTasks(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxTaskGetNumberOfTasks(); + } + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */ + { + char * pcReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + pcReturn = pcTaskGetName( xTaskToQuery ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + pcReturn = pcTaskGetName( xTaskToQuery ); + } + + return pcReturn; + } +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetHandle == 1 ) + TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */ + { + TaskHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGetHandle( pcNameToQuery ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGetHandle( pcNameToQuery ); + } + + return xReturn; + } + #endif /* if ( INCLUDE_xTaskGetHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + void MPU_vTaskList( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskList( pcWriteBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskList( pcWriteBuffer ); + } + } + #endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskGetRunTimeStats( pcWriteBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskGetRunTimeStats( pcWriteBuffer ); + } + } + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* FREERTOS_SYSTEM_CALL */ + { + configRUN_TIME_COUNTER_TYPE xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = ulTaskGetIdleRunTimePercent(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = ulTaskGetIdleRunTimePercent(); + } + + return xReturn; + } + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */ + { + configRUN_TIME_COUNTER_TYPE xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = ulTaskGetIdleRunTimeCounter(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = ulTaskGetIdleRunTimeCounter(); + } + + return xReturn; + } + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskSetApplicationTaskTag( xTask, pxTagValue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskSetApplicationTaskTag( xTask, pxTagValue ); + } + } + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ + { + TaskHookFunction_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGetApplicationTaskTag( xTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGetApplicationTaskTag( xTask ); + } + + return xReturn; + } + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue ); + } + } + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */ + { + void * pvReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex ); + } + + return pvReturn; + } + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter ); + } + + return xReturn; + } + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * pxTaskStatusArray, + UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */ + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime ); + } + + return uxReturn; + } + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskCatchUpTicks( xTicksToCatchUp ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskCatchUpTicks( xTicksToCatchUp ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxTaskGetStackHighWaterMark( xTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxTaskGetStackHighWaterMark( xTask ); + } + + return uxReturn; + } + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ + { + configSTACK_DEPTH_TYPE uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxTaskGetStackHighWaterMark2( xTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxTaskGetStackHighWaterMark2( xTask ); + } + + return uxReturn; + } + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */ + { + TaskHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + xReturn = xTaskGetCurrentTaskHandle(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGetCurrentTaskHandle(); + } + + return xReturn; + } + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGetSchedulerState(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGetSchedulerState(); + } + + return xReturn; + } + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskSetTimeOutState( pxTimeOut ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskSetTimeOutState( pxTimeOut ); + } + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue ); + } + + return xReturn; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ); + } + + return xReturn; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + uint32_t ulReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ); + } + + return ulReturn; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear ); + } + + return xReturn; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */ + { + uint32_t ulReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear ); + } + + return ulReturn; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, + UBaseType_t uxItemSize, + uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */ + { + QueueHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType ); + } + + return xReturn; + } + #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */ + { + QueueHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType ); + } + + return xReturn; + } + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, + BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueGenericReset( pxQueue, xNewQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueGenericReset( pxQueue, xNewQueue ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */ + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxQueueMessagesWaiting( pxQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxQueueMessagesWaiting( pxQueue ); + } + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxQueueSpacesAvailable( xQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxQueueSpacesAvailable( xQueue ); + } + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */ + { + void * xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueGetMutexHolder( xSemaphore ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueGetMutexHolder( xSemaphore ); + } + + return xReturn; + } + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */ + { + QueueHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueCreateMutex( ucQueueType ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueCreateMutex( ucQueueType ); + } + + return xReturn; + } + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */ + { + QueueHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue ); + } + + return xReturn; + } + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, + UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */ + { + QueueHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount ); + } + + return xReturn; + } + #endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */ + { + QueueHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue ); + } + + return xReturn; + } + #endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime ); + } + + return xReturn; + } + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueGiveMutexRecursive( xMutex ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueGiveMutexRecursive( xMutex ); + } + + return xReturn; + } + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */ + { + QueueSetHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueCreateSet( uxEventQueueLength ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueCreateSet( uxEventQueueLength ); + } + + return xReturn; + } + #endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */ + { + QueueSetMemberHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks ); + } + + return xReturn; + } + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet ); + } + + return xReturn; + } + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet ); + } + + return xReturn; + } + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if configQUEUE_REGISTRY_SIZE > 0 + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vQueueAddToRegistry( xQueue, pcName ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vQueueAddToRegistry( xQueue, pcName ); + } + } + #endif /* if configQUEUE_REGISTRY_SIZE > 0 */ +/*-----------------------------------------------------------*/ + + #if configQUEUE_REGISTRY_SIZE > 0 + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vQueueUnregisterQueue( xQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vQueueUnregisterQueue( xQueue ); + } + } + #endif /* if configQUEUE_REGISTRY_SIZE > 0 */ +/*-----------------------------------------------------------*/ + + #if configQUEUE_REGISTRY_SIZE > 0 + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ + { + const char * pcReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + pcReturn = pcQueueGetName( xQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + pcReturn = pcQueueGetName( xQueue ); + } + + return pcReturn; + } + #endif /* if configQUEUE_REGISTRY_SIZE > 0 */ +/*-----------------------------------------------------------*/ + + void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vQueueDelete( xQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vQueueDelete( xQueue ); + } + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ + { + void * pvReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + pvReturn = pvTimerGetTimerID( xTimer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + pvReturn = pvTimerGetTimerID( xTimer ); + } + + return pvReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTimerSetTimerID( xTimer, pvNewID ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTimerSetTimerID( xTimer, pvNewID ); + } + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTimerIsTimerActive( xTimer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTimerIsTimerActive( xTimer ); + } + + return xReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */ + { + TaskHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTimerGetTimerDaemonTaskHandle(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTimerGetTimerDaemonTaskHandle(); + } + + return xReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTimerSetReloadMode( xTimer, uxAutoReload ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTimerSetReloadMode( xTimer, uxAutoReload ); + } + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxTimerGetReloadMode( xTimer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxTimerGetReloadMode( xTimer ); + } + + return uxReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ + { + const char * pcReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + pcReturn = pcTimerGetName( xTimer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + pcReturn = pcTimerGetName( xTimer ); + } + + return pcReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ + { + TickType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTimerGetPeriod( xTimer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTimerGetPeriod( xTimer ); + } + + return xReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ + { + TickType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTimerGetExpiryTime( xTimer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTimerGetExpiryTime( xTimer ); + } + + return xReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); + } + + return xReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */ + { + EventGroupHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xEventGroupCreate(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xEventGroupCreate(); + } + + return xReturn; + } + #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + EventGroupHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xEventGroupCreateStatic( pxEventGroupBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xEventGroupCreateStatic( pxEventGroupBuffer ); + } + + return xReturn; + } + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + + EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + EventBits_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */ + { + EventBits_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */ + { + EventBits_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + EventBits_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vEventGroupDelete( xEventGroup ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vEventGroupDelete( xEventGroup ); + } + } +/*-----------------------------------------------------------*/ + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + size_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + size_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + size_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vStreamBufferDelete( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vStreamBufferDelete( xStreamBuffer ); + } + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferIsFull( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferIsFull( xStreamBuffer ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferIsEmpty( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferIsEmpty( xStreamBuffer ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferReset( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferReset( xStreamBuffer ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + size_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + xReturn = xStreamBufferSpacesAvailable( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferSpacesAvailable( xStreamBuffer ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + size_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferBytesAvailable( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferBytesAvailable( xStreamBuffer ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* FREERTOS_SYSTEM_CALL */ + { + StreamBufferHandle_t xReturn; + + /** + * Streambuffer application level callback functionality is disabled for MPU + * enabled ports. + */ + configASSERT( ( pxSendCompletedCallback == NULL ) && + ( pxReceiveCompletedCallback == NULL ) ); + + if( ( pxSendCompletedCallback == NULL ) && + ( pxReceiveCompletedCallback == NULL ) ) + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferGenericCreate( xBufferSizeBytes, + xTriggerLevelBytes, + xIsMessageBuffer, + NULL, + NULL ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferGenericCreate( xBufferSizeBytes, + xTriggerLevelBytes, + xIsMessageBuffer, + NULL, + NULL ); + } + } + else + { + traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ); + xReturn = NULL; + } + + return xReturn; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* FREERTOS_SYSTEM_CALL */ + { + StreamBufferHandle_t xReturn; + + /** + * Streambuffer application level callback functionality is disabled for MPU + * enabled ports. + */ + configASSERT( ( pxSendCompletedCallback == NULL ) && + ( pxReceiveCompletedCallback == NULL ) ); + + if( ( pxSendCompletedCallback == NULL ) && + ( pxReceiveCompletedCallback == NULL ) ) + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes, + xTriggerLevelBytes, + xIsMessageBuffer, + pucStreamBufferStorageArea, + pxStaticStreamBuffer, + NULL, + NULL ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes, + xTriggerLevelBytes, + xIsMessageBuffer, + pucStreamBufferStorageArea, + pxStaticStreamBuffer, + NULL, + NULL ); + } + } + else + { + traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ); + xReturn = NULL; + } + + return xReturn; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + +/* Functions that the application writer wants to execute in privileged mode + * can be defined in application_defined_privileged_functions.h. The functions + * must take the same format as those above whereby the privilege state on exit + * equals the privilege state on entry. For example: + * + * void MPU_FunctionName( [parameters ] ) FREERTOS_SYSTEM_CALL; + * void MPU_FunctionName( [parameters ] ) + * { + * if( portIS_PRIVILEGED() == pdFALSE ) + * { + * portRAISE_PRIVILEGE(); + * portMEMORY_BARRIER(); + * + * FunctionName( [parameters ] ); + * portMEMORY_BARRIER(); + * + * portRESET_PRIVILEGE(); + * portMEMORY_BARRIER(); + * } + * else + * { + * FunctionName( [parameters ] ); + * } + * } + */ + + #if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1 + #include "application_defined_privileged_functions.h" + #endif +/*-----------------------------------------------------------*/ + +#endif /* portUSING_MPU_WRAPPERS == 1 */ +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91FR40008/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91FR40008/port.c new file mode 100644 index 0000000..0c069a4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91FR40008/port.c @@ -0,0 +1,239 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Atmel AT91R40008 + * port. + * + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file. The ISR routines, which can only be compiled + * to ARM mode are contained in portISR.c. + *----------------------------------------------------------*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware specific definitions. */ +#include "AT91R40008.h" +#include "pio.h" +#include "aic.h" +#include "tc.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) +#define portTICK_PRIORITY_6 ( 6 ) +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the tick timer to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ +volatile uint32_t ulDummy; + + /* Enable clock to the tick timer... */ + AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT; + + /* Stop the tick timer... */ + portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS; + + /* Start with tick timer interrupts disabled... */ + portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF; + + /* Clear any pending tick timer interrupts... */ + ulDummy = portTIMER_REG_BASE_PTR->TC_SR; + + /* Store interrupt handler function address in tick timer vector register... + The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + extern void ( vPreemptiveTick )( void ); + AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vPreemptiveTick; + } + #else // else use cooperative scheduler + { + extern void ( vNonPreemptiveTick )( void ); + AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vNonPreemptiveTick; + } + #endif + + /* Tick timer interrupt level-sensitive, priority 6... */ + AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6; + + /* Enable the tick timer interrupt... + + First at timer level */ + portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS; + + /* Then at the AIC level. */ + AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL); + + /* Calculate timer compare value to achieve the desired tick rate... */ + if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF ) + { + /* The tick rate is fast enough for us to use the faster timer input + clock (main clock / 2). */ + portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG; + portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2); + } + else + { + /* We must use a slower timer input clock (main clock / 8) because the + tick rate is too slow for the faster input clock. */ + portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG; + portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8); + } + + /* Start tick timer... */ + portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN; +} +/*-----------------------------------------------------------*/ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91FR40008/portISR.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91FR40008/portISR.c new file mode 100644 index 0000000..9d4bf6e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91FR40008/portISR.c @@ -0,0 +1,234 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* + Changes from V3.2.4 + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. +*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle interrupts. */ +#define portCLEAR_AIC_INTERRUPT ( ( uint32_t ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); + void vNonPreemptiveTick( void ) + { + static volatile uint32_t ulDummy; + + /* Clear tick timer interrupt indication. */ + ulDummy = portTIMER_REG_BASE_PTR->TC_SR; + + xTaskIncrementTick(); + + /* Acknowledge the interrupt at AIC level... */ + AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; + } + +#else /* else preemption is turned on */ + + /* The preemptive scheduler is defined as "naked" as the full context is + saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__((naked)); + void vPreemptiveTick( void ) + { + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* WARNING - Do not use local (stack) variables here. Use globals + if you must! */ + static volatile uint32_t ulDummy; + + /* Clear tick timer interrupt indication. */ + ulDummy = portTIMER_REG_BASE_PTR->TC_SR; + + /* Increment the RTOS tick count, then look for the highest priority + task that is ready to run. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Acknowledge the interrupt at AIC level... */ + AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + } + +#endif +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + void vPortDisableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91FR40008/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91FR40008/portmacro.h new file mode 100644 index 0000000..5f0f74d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91FR40008/portmacro.h @@ -0,0 +1,256 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + Changes from V3.2.3 + + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + Changes from V3.2.4 + + + Removed the use of the %0 parameter within the assembler macros and + replaced them with hard coded registers. This will ensure the + assembler does not select the link register as the temp register as + was occasionally happening previously. + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. + + Changes from V4.5.0 + + + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros + and replaced them with portYIELD_FROM_ISR() macro. Application code + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() + macros as per the V4.5.1 demo code. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm volatile ( "SWI 0" ) +#define portNOP() asm volatile ( "NOP" ) + +/* + * These define the timer to use for generating the tick interrupt. + * They are put in this file so they can be shared between "port.c" + * and "portisr.c". + */ +#define portTIMER_REG_BASE_PTR AT91C_BASE_TC0 +#define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0 +#define portTIMER_AIC_CHANNEL ( ( uint32_t ) 4 ) +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile uint32_t ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile uint32_t ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} + +#define portYIELD_FROM_ISR() vTaskSwitchContext() + +/* Critical section handling. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h new file mode 100644 index 0000000..a14279e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h @@ -0,0 +1,2731 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// +// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) + +#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \ +{ \ + unsigned int mask ; \ + \ + mask = 0x1 << irq_id; \ + /* Disable the interrupt on the interrupt controller */ \ + AT91C_BASE_AIC->AIC_IDCR = mask ; \ + /* Save the interrupt handler routine pointer and the interrupt priority */ \ + AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ; \ + /* Store the Source Mode Register */ \ + AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority ; \ + /* Clear the interrupt on the interrupt controller */ \ + AT91C_BASE_AIC->AIC_ICCR = mask ; \ +} + + +#endif diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h new file mode 100644 index 0000000..8ea721e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h @@ -0,0 +1,4698 @@ +// - ---------------------------------------------------------------------------- +// - ATMEL Microcontroller Software Support - ROUSSET - +// - ---------------------------------------------------------------------------- +// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// - ---------------------------------------------------------------------------- +// - File Name : AT91SAM7X256.h +// - Object : AT91SAM7X256 definitions +// - Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// - +// - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// - ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) + + + +// - Hardware register definition + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR System Peripherals +// - ***************************************************************************** + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// - ***************************************************************************** +// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#if 0 /*_RB_*/ +AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level +AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level +AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level +AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type +AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive +AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive +AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered +AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered +AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive +AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered +// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status +AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status +// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode +AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask +#endif +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// - ***************************************************************************** +// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable +AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable +AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable +AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable +// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Debug Unit +// - ***************************************************************************** +// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver +AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter +AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable +AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable +AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable +AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable +AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits +// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type +AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity +AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity +AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space) +AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark) +AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity +AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode +AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode +AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt +AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt +AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt +AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt +AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt +AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt +AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt +AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt +AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt +AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt +AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt +AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt +// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// - ***************************************************************************** + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Clock Generator Controler +// - ***************************************************************************** +// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable +AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass +AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time +// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency +AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready +// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected +AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0 +AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed +AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter +AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range +AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier +AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks +AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output +AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2 +AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4 + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Power Management Controler +// - ***************************************************************************** +// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock +AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock +AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output +// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection +AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected +AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected +AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected +AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler +AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock +AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2 +AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4 +AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8 +AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16 +AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32 +AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64 +// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask +AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask +AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask +// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Reset Controller Interface +// - ***************************************************************************** +// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset +AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset +AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset +AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password +// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status +AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status +AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type +AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising. +AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising. +AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured. +AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software. +AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low. +AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured. +AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level +AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress. +// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable +AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable +AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable +AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// - ***************************************************************************** +// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value +AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable +AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable +AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart +// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value +// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value +// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status +AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// - ***************************************************************************** +// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value +AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled +AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable +// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status +// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value +AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter +// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// - ***************************************************************************** +// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart +AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password +// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart +AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable +AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable +AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart +AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable +AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value +AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt +AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt +// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow +AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// - ***************************************************************************** +// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Memory Controller Interface +// - ***************************************************************************** +// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit +// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status +AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status +AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status +AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte +AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word +AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word +AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status +AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read +AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write +AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch +AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source +AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source +AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source +AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source +// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready +AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error +AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error +AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming +AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State +AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations +AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations +AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations +AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations +AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number +// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command +AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN. +AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed. +AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits. +AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits. +AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit. +AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number +AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key +// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status +AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status +AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status +AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status +AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status +AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status +AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status +AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status +AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status +AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status +AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status +AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status +AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status +AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status +AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status +AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status +AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status +AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status +AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status +AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status +AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status +AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status +AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status +AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status +AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Serial Parallel Interface +// - ***************************************************************************** +// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable +AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable +AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset +AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer +// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode +AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select +AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select +AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select +AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode +AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection +AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection +AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection +AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select +AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects +// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data +AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status +// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data +AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status +// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full +AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty +AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error +AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status +AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer +AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer +AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt +AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt +AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt +AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt +AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status +// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity +AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase +AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer +AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer +AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer +AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer +AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer +AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer +AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer +AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer +AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer +AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer +AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer +AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate +AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK +AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Usart +// - ***************************************************************************** +// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break +AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break +AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out +AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address +AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations +AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge +AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out +AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable +AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable +AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable +AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable +// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode +AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal +AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 +AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking +AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem +AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 +AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 +AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA +AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking +AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock +AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock +AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1 +AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM) +AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK) +AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock +AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits +AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits +AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits +AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits +AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select +AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits +AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit +AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits +AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order +AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length +AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select +AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode +AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge +AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK +AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions +AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter +// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break +AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out +AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached +AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge +AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag +AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag +AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag +AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag +// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input +AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input +AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input +AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// - ***************************************************************************** +// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable +AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable +AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable +AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable +AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset +// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection +AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock +AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal +AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin +AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection +AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output +AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion +AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection +AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start +AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input +AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input +AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input +AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input +AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input +AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input +AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0 +AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay +AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection +// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length +AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode +AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First +AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame +AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length +AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection +AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection +// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value +AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable +// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready +AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty +AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission +AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty +AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready +AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun +AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception +AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full +AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync +AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync +AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable +AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable +// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Two-wire Interface +// - ***************************************************************************** +// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition +AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition +AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled +AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled +AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset +// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size +AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address +AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address +AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address +AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address +AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction +AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address +// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider +AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider +AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider +// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed +AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY +AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY +AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error +AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error +AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged +// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR PWMC Channel Interface +// - ***************************************************************************** +// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) +AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) +AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) +AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment +AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity +AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period +// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle +// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period +// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter +// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// - ***************************************************************************** +// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor. +AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A +AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) +AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor. +AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B +AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) +// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0 +AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1 +AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2 +AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3 +// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR USB Device Interface +// - ***************************************************************************** +// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats +AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error +AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK +// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable +AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured +AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume +AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host +AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable +// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value +AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable +// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt +AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt +AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt +AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt +AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt +AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt +AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt +AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt +AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt +AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt +AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt +// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt +// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0 +AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1 +AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2 +AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3 +AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4 +AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5 +// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR +AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0 +AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints) +AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints) +AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready +AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction +AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type +AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control +AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT +AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT +AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT +AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN +AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN +AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN +AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle +AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable +AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO +// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) +AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// - ***************************************************************************** +// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command +AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command +AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command +// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection +AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK +AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK +AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK +AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK +AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK +AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0 +AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1 +AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2 +AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert +AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection +AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal +AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock +AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock +AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock +AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare +AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading +AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare +AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading +AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection +AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None +AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge +AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge +AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge +AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection +AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None +AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge +AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge +AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge +AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection +AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input +AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output +AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output +AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output +AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection +AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable +AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection +AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare +AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare +AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare +AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare +AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable +AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) +AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA +AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none +AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set +AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear +AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle +AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection +AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None +AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA +AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA +AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA +AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA +AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none +AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set +AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear +AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle +AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection +AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None +AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA +AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA +AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA +AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA +AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none +AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set +AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear +AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle +AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA +AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none +AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set +AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear +AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle +AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB +AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none +AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set +AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear +AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle +AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB +AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none +AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set +AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear +AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle +AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB +AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none +AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set +AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear +AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle +AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB +AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none +AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set +AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear +AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle +// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow +AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun +AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare +AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare +AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare +AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading +AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading +AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger +AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling +AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror +AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror +// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Timer Counter Interface +// - ***************************************************************************** +// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command +// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection +AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 +AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 +AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 +AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 +AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection +AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1 +AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1 +AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1 +AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1 +AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection +AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2 +AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2 +AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2 +AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2 + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// - ***************************************************************************** +// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark +AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority +AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type +AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB) +// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode +AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode +AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version +// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value +AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code +AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request +AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort +AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready +AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored +// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox +AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Control Area Network Interface +// - ***************************************************************************** +// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable +AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode +AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode +AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame +AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame +AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode +AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze +AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat +// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag +AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag +AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag +AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag +AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag +AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag +AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag +AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag +AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag +AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag +AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag +AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag +AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag +AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag +AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag +AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag +AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag +AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag +AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag +AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag +AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag +AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag +AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag +AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag +AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error +AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error +AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error +AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error +AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error +// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy +AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy +AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy +// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment +AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment +AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment +AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment +AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler +AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode +// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field +// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter +AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter +// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field +// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// - ***************************************************************************** +// - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level. +AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local. +AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable. +AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable. +AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable. +AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers. +AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers. +AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers. +AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure. +AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission. +AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt. +AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame +AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame +// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed. +AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex. +AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames. +AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames. +AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast. +AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable +AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable. +AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes. +AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable. +AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC) +AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8 +AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16 +AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32 +AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64 +AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC) +AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC) +AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC) +AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer +AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer +AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer +AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer +AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable +AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS +AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC) +AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS +// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC) +AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC) +AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC) +// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC) +AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC) +AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC) +AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go +AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame +AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC) +AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC) +// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC) +AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC) +AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC) +// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC) +AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC) +AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC) +AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC) +AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC) +AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC) +AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC) +AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC) +AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC) +AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC) +AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC) +AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC) +AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC) +// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC) +AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC) +AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC) +AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC) +AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC) +AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC) +// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII +// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address +AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable +AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable +AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable +// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC) +AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC) + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// - ***************************************************************************** +// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset +AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion +// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable +AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled. +AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection +AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0 +AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1 +AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2 +AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3 +AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4 +AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5 +AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger +AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution. +AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution +AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution +AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode +AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode +AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode +AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection +AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time +AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time +// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0 +AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1 +AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2 +AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3 +AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4 +AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5 +AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6 +AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7 +// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion +AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion +AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion +AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion +AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion +AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion +AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion +AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion +AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error +AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error +AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error +AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error +AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error +AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error +AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error +AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error +AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready +AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun +AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer +AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt +// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted +// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data +// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// - ***************************************************************************** +// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- +AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing +AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset +AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading +// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode +AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay +AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode +AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet). +AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode +AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode. +AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode. +AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode. +AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode. +AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode. +AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode +AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size +AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit. +AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit. +AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit. +AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit. +AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit. +AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key +AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type +AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled. +AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled. +AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled. +AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled. +AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled. +// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY +AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End +AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End +AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full +AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty +AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection +// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status +AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode. +AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing. +AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing. +AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation. +AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation. +AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access. + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// - ***************************************************************************** +// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing +AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset +// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode +AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode +AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode +AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode +AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet). +AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode +AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode. +AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode. +AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode. +AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode. +AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode +AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size +AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit. +AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit. +AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit. +AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit. +// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY +AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End +AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End +AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full +AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty +AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection +// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status +AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode. +AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing. +AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing. +AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access. + +// - ***************************************************************************** +// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// - ***************************************************************************** +// - ========== Register definition for SYS peripheral ========== +// - ========== Register definition for AIC peripheral ========== +AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register +AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register +AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register +AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) +AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register +AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register +AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register +AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register +AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register +AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register +AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register +AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register +AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register +AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register +AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register +AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register +AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register +AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register +// - ========== Register definition for PDC_DBGU peripheral ========== +AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register +AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register +AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register +AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register +AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register +AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register +AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register +AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register +AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register +AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register +// - ========== Register definition for DBGU peripheral ========== +AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register +AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register +AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register +AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register +AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register +AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register +AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register +AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register +AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register +AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register +AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register +AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register +// - ========== Register definition for PIOA peripheral ========== +AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr +AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register +AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register +AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register +AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register +AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register +AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register +AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register +AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register +AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register +AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register +AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register +AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register +AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register +AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register +AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register +AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register +AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register +AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register +AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register +AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register +AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register +AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register +AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register +AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register +AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register +AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register +AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register +AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register +// - ========== Register definition for PIOB peripheral ========== +AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register +AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register +AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register +AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register +AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register +AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register +AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register +AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register +AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register +AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register +AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register +AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register +AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register +AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register +AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register +AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register +AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr +AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register +AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register +AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register +AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register +AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register +AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register +AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register +AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register +AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register +AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register +AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register +AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register +// - ========== Register definition for CKGR peripheral ========== +AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register +AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register +AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register +// - ========== Register definition for PMC peripheral ========== +AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register +AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register +AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register +AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register +AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register +AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register +AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register +AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register +AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register +AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register +AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register +AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register +AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register +AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register +AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register +// - ========== Register definition for RSTC peripheral ========== +AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register +AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register +AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register +// - ========== Register definition for RTTC peripheral ========== +AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register +AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register +AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register +AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register +// - ========== Register definition for PITC peripheral ========== +AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register +AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register +AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register +AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register +// - ========== Register definition for WDTC peripheral ========== +AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register +AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register +AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register +// - ========== Register definition for VREG peripheral ========== +AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register +// - ========== Register definition for MC peripheral ========== +AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register +AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register +AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register +AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register +AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register +AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register +// - ========== Register definition for PDC_SPI1 peripheral ========== +AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register +AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register +AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register +AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register +AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register +AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register +AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register +AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register +AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register +AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register +// - ========== Register definition for SPI1 peripheral ========== +AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register +AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register +AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register +AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register +AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register +AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register +AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register +AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register +AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register +// - ========== Register definition for PDC_SPI0 peripheral ========== +AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register +AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register +AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register +AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register +AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register +AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register +AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register +AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register +AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register +AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register +// - ========== Register definition for SPI0 peripheral ========== +AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register +AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register +AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register +AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register +AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register +AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register +AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register +AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register +AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register +// - ========== Register definition for PDC_US1 peripheral ========== +AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register +AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register +AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register +AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register +AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register +AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register +AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register +AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register +AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register +AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register +// - ========== Register definition for US1 peripheral ========== +AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register +AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register +AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register +AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register +AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register +AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register +AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register +AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register +AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register +AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register +AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register +AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register +AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register +AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register +// - ========== Register definition for PDC_US0 peripheral ========== +AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register +AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register +AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register +AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register +AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register +AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register +AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register +AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register +AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register +AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register +// - ========== Register definition for US0 peripheral ========== +AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register +AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register +AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register +AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register +AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register +AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register +AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register +AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register +AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register +AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register +AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register +AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register +AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register +AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register +// - ========== Register definition for PDC_SSC peripheral ========== +AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register +AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register +AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register +AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register +AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register +AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register +AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register +AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register +AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register +AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register +// - ========== Register definition for SSC peripheral ========== +AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register +AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register +AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register +AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register +AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register +AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister +AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register +AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register +AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register +AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register +AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register +AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register +AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register +AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register +// - ========== Register definition for TWI peripheral ========== +AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register +AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register +AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register +AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register +AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register +AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register +AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register +AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register +AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register +AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register +// - ========== Register definition for PWMC_CH3 peripheral ========== +AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register +AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved +AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register +AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register +AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register +AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register +// - ========== Register definition for PWMC_CH2 peripheral ========== +AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved +AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register +AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register +AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register +AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register +AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register +// - ========== Register definition for PWMC_CH1 peripheral ========== +AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved +AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register +AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register +AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register +AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register +AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register +// - ========== Register definition for PWMC_CH0 peripheral ========== +AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved +AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register +AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register +AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register +AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register +AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register +// - ========== Register definition for PWMC peripheral ========== +AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register +AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register +AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register +AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register +AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register +AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register +AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register +AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register +AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register +// - ========== Register definition for UDP peripheral ========== +AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register +AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register +AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register +AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register +AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register +AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register +AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register +AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register +AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register +AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register +AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register +AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register +// - ========== Register definition for TC0 peripheral ========== +AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register +AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C +AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B +AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register +AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register +AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A +AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register +AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value +AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register +// - ========== Register definition for TC1 peripheral ========== +AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B +AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register +AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register +AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register +AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register +AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A +AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C +AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register +AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value +// - ========== Register definition for TC2 peripheral ========== +AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register +AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value +AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A +AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B +AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register +AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register +AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C +AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register +AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register +// - ========== Register definition for TCB peripheral ========== +AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register +AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register +// - ========== Register definition for CAN_MB0 peripheral ========== +AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register +AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register +AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register +AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register +AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register +AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register +AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register +AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register +// - ========== Register definition for CAN_MB1 peripheral ========== +AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register +AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register +AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register +AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register +AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register +AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register +AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register +AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register +// - ========== Register definition for CAN_MB2 peripheral ========== +AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register +AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register +AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register +AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register +AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register +AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register +AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register +AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register +// - ========== Register definition for CAN_MB3 peripheral ========== +AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register +AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register +AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register +AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register +AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register +AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register +AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register +AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register +// - ========== Register definition for CAN_MB4 peripheral ========== +AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register +AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register +AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register +AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register +AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register +AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register +AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register +AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register +// - ========== Register definition for CAN_MB5 peripheral ========== +AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register +AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register +AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register +AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register +AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register +AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register +AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register +AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register +// - ========== Register definition for CAN_MB6 peripheral ========== +AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register +AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register +AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register +AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register +AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register +AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register +AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register +AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register +// - ========== Register definition for CAN_MB7 peripheral ========== +AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register +AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register +AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register +AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register +AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register +AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register +AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register +AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register +// - ========== Register definition for CAN peripheral ========== +AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register +AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register +AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register +AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register +AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register +AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register +AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register +AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register +AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register +AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register +AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register +AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register +// - ========== Register definition for EMAC peripheral ========== +AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register +AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes +AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes +AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register +AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register +AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register +AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register +AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register +AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register +AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register +AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes +AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register +AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes +AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register +AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register +AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register +AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register +AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register +AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0] +AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer +AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register +AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register +AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes +AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register +AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register +AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register +AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer +AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register +AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register +AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32] +AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register +AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register +AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register +AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register +AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register +AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register +AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register +AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register +AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register +AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register +AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register +AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes +AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register +AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register +AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes +AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register +AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes +AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register +AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register +// - ========== Register definition for PDC_ADC peripheral ========== +AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register +AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register +AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register +AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register +AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register +AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register +AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register +AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register +AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register +AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register +// - ========== Register definition for ADC peripheral ========== +AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2 +AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3 +AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0 +AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5 +AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register +AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register +AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4 +AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1 +AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register +AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register +AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register +AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7 +AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6 +AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register +AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register +AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register +AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register +AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register +// - ========== Register definition for PDC_AES peripheral ========== +AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register +AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register +AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register +AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register +AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register +AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register +AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register +AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register +AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register +AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register +// - ========== Register definition for AES peripheral ========== +AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register +AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register +AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register +AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register +AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register +AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register +AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register +AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register +AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register +AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register +AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register +// - ========== Register definition for PDC_TDES peripheral ========== +AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register +AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register +AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register +AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register +AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register +AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register +AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register +AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register +AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register +AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register +// - ========== Register definition for TDES peripheral ========== +AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register +AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register +AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register +AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register +AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register +AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register +AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register +AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register +AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register +AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register +AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register +AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register +AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register + +// - ***************************************************************************** +// - PIO DEFINITIONS FOR AT91SAM7X256 +// - ***************************************************************************** +AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0 +AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data +AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1 +AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data +AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10 +AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data +AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11 +AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock +AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12 +AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0 +AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13 +AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1 +AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1 +AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14 +AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2 +AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1 +AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15 +AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3 +AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input +AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16 +AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave +AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17 +AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave +AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18 +AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock +AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19 +AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive +AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2 +AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock +AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1 +AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20 +AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit +AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21 +AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync +AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0 +AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22 +AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock +AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock +AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23 +AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data +AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave +AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24 +AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data +AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave +AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25 +AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock +AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1 +AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26 +AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync +AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2 +AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27 +AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data +AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3 +AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28 +AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data +AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29 +AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input +AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3 +AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3 +AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send +AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2 +AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30 +AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0 +AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2 +AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4 +AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send +AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3 +AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5 +AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data +AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6 +AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data +AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7 +AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock +AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1 +AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8 +AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send +AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2 +AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9 +AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send +AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3 +AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0 +AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock +AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0 +AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1 +AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable +AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10 +AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2 +AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1 +AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11 +AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3 +AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2 +AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12 +AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error +AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input +AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13 +AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2 +AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1 +AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14 +AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3 +AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2 +AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15 +AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid +AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16 +AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected +AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3 +AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17 +AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock +AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3 +AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18 +AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec +AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger +AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19 +AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0 +AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input +AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2 +AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0 +AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20 +AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1 +AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0 +AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21 +AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2 +AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1 +AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22 +AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3 +AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2 +AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23 +AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A +AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect +AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24 +AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B +AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready +AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25 +AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A +AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready +AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26 +AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B +AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator +AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27 +AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A +AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0 +AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28 +AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B +AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1 +AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29 +AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1 +AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2 +AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3 +AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1 +AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30 +AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2 +AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3 +AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4 +AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5 +AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0 +AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6 +AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1 +AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7 +AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error +AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8 +AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock +AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9 +AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output + +// - ***************************************************************************** +// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// - ***************************************************************************** +AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) +AT91C_ID_SYS EQU ( 1) ;- System Peripheral +AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A +AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B +AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0 +AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1 +AT91C_ID_US0 EQU ( 6) ;- USART 0 +AT91C_ID_US1 EQU ( 7) ;- USART 1 +AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller +AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface +AT91C_ID_PWMC EQU (10) ;- PWM Controller +AT91C_ID_UDP EQU (11) ;- USB Device Port +AT91C_ID_TC0 EQU (12) ;- Timer Counter 0 +AT91C_ID_TC1 EQU (13) ;- Timer Counter 1 +AT91C_ID_TC2 EQU (14) ;- Timer Counter 2 +AT91C_ID_CAN EQU (15) ;- Control Area Network Controller +AT91C_ID_EMAC EQU (16) ;- Ethernet MAC +AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter +AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit +AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard +AT91C_ID_20_Reserved EQU (20) ;- Reserved +AT91C_ID_21_Reserved EQU (21) ;- Reserved +AT91C_ID_22_Reserved EQU (22) ;- Reserved +AT91C_ID_23_Reserved EQU (23) ;- Reserved +AT91C_ID_24_Reserved EQU (24) ;- Reserved +AT91C_ID_25_Reserved EQU (25) ;- Reserved +AT91C_ID_26_Reserved EQU (26) ;- Reserved +AT91C_ID_27_Reserved EQU (27) ;- Reserved +AT91C_ID_28_Reserved EQU (28) ;- Reserved +AT91C_ID_29_Reserved EQU (29) ;- Reserved +AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0) +AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1) + +// - ***************************************************************************** +// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// - ***************************************************************************** +AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address +AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address +AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address +AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address +AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address +AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address +AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address +AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address +AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address +AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address +AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address +AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address +AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address +AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address +AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address +AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address +AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address +AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address +AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address +AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address +AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address +AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address +AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address +AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address +AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address +AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address +AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address +AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address +AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address +AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address +AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address +AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address +AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address +AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address +AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address +AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address +AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address +AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address +AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address +AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address +AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address +AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address +AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address +AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address +AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address +AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address +AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address +AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address +AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address +AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address +AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address + +// - ***************************************************************************** +// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// - ***************************************************************************** +AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address +AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte) +AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address +AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte) + + + +#endif /* AT91SAM7X256_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c new file mode 100644 index 0000000..9cbd823 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c @@ -0,0 +1,51 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X256.h +//* Object : AT91SAM7X256 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + + +#include "AT91SAM7X256.h" + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h new file mode 100644 index 0000000..e66b4e1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h @@ -0,0 +1,4558 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X256.h +//* Object : AT91SAM7X256 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7X256_H +#define lib_AT91SAM7X256_H + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR RSTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSoftReset +//* \brief Start Software Reset +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSoftReset( + AT91PS_RSTC pRSTC, + unsigned int reset) +{ + pRSTC->RSTC_RCR = (0xA5000000 | reset); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSetMode +//* \brief Set Reset Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSetMode( + AT91PS_RSTC pRSTC, + unsigned int mode) +{ + pRSTC->RSTC_RMR = (0xA5000000 | mode); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetMode +//* \brief Get Reset Mode +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetMode( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetStatus +//* \brief Get Reset Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetStatus( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RSR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTIsSoftRstActive +//* \brief Return !=0 if software reset is still not completed +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTIsSoftRstActive( + AT91PS_RSTC pRSTC) +{ + return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); +} +/* ***************************************************************************** + SOFTWARE API FOR RTTC + ***************************************************************************** */ +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_SetRTT_TimeBase() +//* \brief Set the RTT prescaler according to the TimeBase in ms +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetTimeBase( + AT91PS_RTTC pRTTC, + unsigned int ms) +{ + if (ms > 2000) + return 1; // AT91C_TIME_OUT_OF_RANGE + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); + return 0; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTSetPrescaler() +//* \brief Set the new prescaler value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetPrescaler( + AT91PS_RTTC pRTTC, + unsigned int rtpres) +{ + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); + return (pRTTC->RTTC_RTMR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTRestart() +//* \brief Restart the RTT prescaler +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTRestart( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; +} + + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmINT() +//* \brief Enable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearAlarmINT() +//* \brief Disable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetRttIncINT() +//* \brief Enable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearRttIncINT() +//* \brief Disable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmValue() +//* \brief Set RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmValue( + AT91PS_RTTC pRTTC, unsigned int alarm) +{ + pRTTC->RTTC_RTAR = alarm; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_GetAlarmValue() +//* \brief Get RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetAlarmValue( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTAR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTGetStatus() +//* \brief Read the RTT status +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetStatus( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTSR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ReadValue() +//* \brief Read the RTT value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTReadValue( + AT91PS_RTTC pRTTC) +{ + register volatile unsigned int val1,val2; + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while(val1 != val2); + return(val1); +} +/* ***************************************************************************** + SOFTWARE API FOR PITC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITInit +//* \brief System timer init : period in �second, system clock freq in MHz +//*---------------------------------------------------------------------------- +__inline void AT91F_PITInit( + AT91PS_PITC pPITC, + unsigned int period, + unsigned int pit_frequency) +{ + pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 + pPITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITSetPIV +//* \brief Set the PIT Periodic Interval Value +//*---------------------------------------------------------------------------- +__inline void AT91F_PITSetPIV( + AT91PS_PITC pPITC, + unsigned int piv) +{ + pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITEnableInt +//* \brief Enable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITEnableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITDisableInt +//* \brief Disable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITDisableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetMode +//* \brief Read PIT mode register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetMode( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetStatus +//* \brief Read PIT status register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetStatus( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PISR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIIR +//* \brief Read PIT CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIIR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIIR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIVR +//* \brief Read System timer CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIVR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIVR); +} +/* ***************************************************************************** + SOFTWARE API FOR WDTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSetMode +//* \brief Set Watchdog Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTSetMode( + AT91PS_WDTC pWDTC, + unsigned int Mode) +{ + pWDTC->WDTC_WDMR = Mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTRestart +//* \brief Restart Watchdog +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTRestart( + AT91PS_WDTC pWDTC) +{ + pWDTC->WDTC_WDCR = 0xA5000001; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSGettatus +//* \brief Get Watchdog Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTSGettatus( + AT91PS_WDTC pWDTC) +{ + return(pWDTC->WDTC_WDSR & 0x3); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTGetPeriod +//* \brief Translate ms into Watchdog Compatible value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) +{ + if ((ms < 4) || (ms > 16000)) + return 0; + return((ms << 8) / 1000); +} +/* ***************************************************************************** + SOFTWARE API FOR VREG + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Enable_LowPowerMode +//* \brief Enable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Enable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR |= AT91C_VREG_PSTDBY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Disable_LowPowerMode +//* \brief Disable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Disable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; +}/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; + pUDP->UDP_RSTEP = 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR CAN + ***************************************************************************** */ +#define STANDARD_FORMAT 0 +#define EXTENDED_FORMAT 1 + +//*---------------------------------------------------------------------------- +//* \fn AT91F_InitMailboxRegisters() +//* \brief Configure the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, + int mode_reg, + int acceptance_mask_reg, + int id_reg, + int data_low_reg, + int data_high_reg, + int control_reg) +{ + CAN_Mailbox->CAN_MB_MCR = 0x0; + CAN_Mailbox->CAN_MB_MMR = mode_reg; + CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; + CAN_Mailbox->CAN_MB_MID = id_reg; + CAN_Mailbox->CAN_MB_MDL = data_low_reg; + CAN_Mailbox->CAN_MB_MDH = data_high_reg; + CAN_Mailbox->CAN_MB_MCR = control_reg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EnableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_EnableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR |= AT91C_CAN_CANEN; + + // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver + while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DisableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_DisableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR &= ~AT91C_CAN_CANEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_EnableIt +//* \brief Enable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_EnableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pCAN->CAN_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_DisableIt +//* \brief Disable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_DisableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pCAN->CAN_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetStatus +//* \brief Return CAN Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInterruptMaskStatus +//* \brief Return CAN Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsInterruptMasked +//* \brief Test if CAN Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsInterruptMasked( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsStatusSet +//* \brief Test if CAN Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsStatusSet( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgModeReg +//* \brief Configure the Mode Register of the CAN controller +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgModeReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pCAN->CAN_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetModeReg +//* \brief Return the Mode Register of the CAN controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetModeReg ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgBaudrateReg +//* \brief Configure the Baudrate of the CAN controller for the network +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgBaudrateReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int baudrate_cfg) +{ + //* Write to the BR register + pCAN->CAN_BR = baudrate_cfg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetBaudrate +//* \brief Return the Baudrate of the CAN controller for the network value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetBaudrate ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_BR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInternalCounter +//* \brief Return CAN Timer Regsiter Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInternalCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetTimestamp +//* \brief Return CAN Timestamp Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetTimestamp ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIMESTP; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetErrorCounter +//* \brief Return CAN Error Counter Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetErrorCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_ECR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitTransferRequest +//* \brief Request for a transfer on the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitTransferRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int transfer_cmd) +{ + pCAN->CAN_TCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitAbortRequest +//* \brief Abort the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitAbortRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int abort_cmd) +{ + pCAN->CAN_ACR = abort_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageModeReg +//* \brief Program the Message Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mode) +{ + CAN_Mailbox->CAN_MB_MMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageModeReg +//* \brief Return the Message Mode Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageIDReg +//* \brief Program the Message ID Register +//* \brief Version == 0 for Standard messsage, Version == 1 for Extended +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int id, + unsigned char version) +{ + if(version==0) // IDvA Standard Format + CAN_Mailbox->CAN_MB_MID = id<<18; + else // IDvB Extended Format + CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageIDReg +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg +//* \brief Program the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mask) +{ + CAN_Mailbox->CAN_MB_MAM = mask; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg +//* \brief Return the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MAM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetFamilyID +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetFamilyID ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MFID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageCtrl +//* \brief Request and config for a transfer on the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageCtrlReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int message_ctrl_cmd) +{ + CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageStatus +//* \brief Return CAN Mailbox Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageStatus ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataLow +//* \brief Program data low value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDL = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataLow +//* \brief Return data low value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataHigh +//* \brief Program data high value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDH = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataHigh +//* \brief Return data high value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDH; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_Open +//* \brief Open a CAN Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} +/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR AES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_EnableIt +//* \brief Enable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_EnableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pAES->AES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_DisableIt +//* \brief Disable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_DisableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pAES->AES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetStatus +//* \brief Return AES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetInterruptMaskStatus +//* \brief Return AES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsInterruptMasked +//* \brief Test if AES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsInterruptMasked( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsStatusSet +//* \brief Test if AES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsStatusSet( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgModeReg +//* \brief Configure the Mode Register of the AES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgModeReg ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pAES->AES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetModeReg +//* \brief Return the Mode Register of the AES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetModeReg ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + return pAES->AES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_StartProcessing ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SoftReset +//* \brief Reset AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SoftReset ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_LoadNewSeed +//* \brief Load New Seed in the random number generator +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_LoadNewSeed ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_LOADSEED; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetCryptoKey +//* \brief Set Cryptographic Key x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetCryptoKey ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int keyword + ) +{ + pAES->AES_KEYWxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_InputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int indata + ) +{ + pAES->AES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetOutputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index + ) +{ + return pAES->AES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetInitializationVector +//* \brief Set Initialization Vector (or Counter) x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetInitializationVector ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int initvector + ) +{ + pAES->AES_IVxR[index] = initvector; +} + +/* ***************************************************************************** + SOFTWARE API FOR TDES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_EnableIt +//* \brief Enable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_EnableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pTDES->TDES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_DisableIt +//* \brief Disable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_DisableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pTDES->TDES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetStatus +//* \brief Return TDES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetInterruptMaskStatus +//* \brief Return TDES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsInterruptMasked +//* \brief Test if TDES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsInterruptMasked( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsStatusSet +//* \brief Test if TDES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsStatusSet( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgModeReg +//* \brief Configure the Mode Register of the TDES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgModeReg ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pTDES->TDES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetModeReg +//* \brief Return the Mode Register of the TDES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetModeReg ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + return pTDES->TDES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_StartProcessing ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SoftReset +//* \brief Reset TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SoftReset ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey1 +//* \brief Set Cryptographic Key 1 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey1 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY1WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey2 +//* \brief Set Cryptographic Key 2 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey2 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY2WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey3 +//* \brief Set Cryptographic Key 3 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey3 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY3WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_InputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int indata + ) +{ + pTDES->TDES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetOutputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index + ) +{ + return pTDES->TDES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetInitializationVector +//* \brief Set Initialization Vector x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetInitializationVector ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int initvector + ) +{ + pTDES->TDES_IVxR[index] = initvector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA27_DRXD ) | + ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB30_PCK2 ) | + ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A + ((unsigned int) AT91C_PB20_PCK0 ) | + ((unsigned int) AT91C_PB0_PCK0 ) | + ((unsigned int) AT91C_PB22_PCK2 ) | + ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA30_PCK2 ) | + ((unsigned int) AT91C_PA13_PCK1 ) | + ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_CfgPMC +//* \brief Enable Peripheral clock in PMC for VREG +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RSTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA25_RK ) | + ((unsigned int) AT91C_PA22_TK ) | + ((unsigned int) AT91C_PA21_TF ) | + ((unsigned int) AT91C_PA24_RD ) | + ((unsigned int) AT91C_PA26_RF ) | + ((unsigned int) AT91C_PA23_TD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for WDTC +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB26_RI1 ) | + ((unsigned int) AT91C_PB24_DSR1 ) | + ((unsigned int) AT91C_PB23_DCD1 ) | + ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA7_SCK1 ) | + ((unsigned int) AT91C_PA8_RTS1 ) | + ((unsigned int) AT91C_PA6_TXD1 ) | + ((unsigned int) AT91C_PA5_RXD1 ) | + ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_RXD0 ) | + ((unsigned int) AT91C_PA4_CTS0 ) | + ((unsigned int) AT91C_PA3_RTS0 ) | + ((unsigned int) AT91C_PA2_SCK0 ) | + ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI1 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPIO +//* \brief Configure PIO controllers to drive SPI1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB16_NPCS13 ) | + ((unsigned int) AT91C_PB10_NPCS11 ) | + ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA4_NPCS13 ) | + ((unsigned int) AT91C_PA29_NPCS13 ) | + ((unsigned int) AT91C_PA21_NPCS10 ) | + ((unsigned int) AT91C_PA22_SPCK1 ) | + ((unsigned int) AT91C_PA25_NPCS11 ) | + ((unsigned int) AT91C_PA2_NPCS11 ) | + ((unsigned int) AT91C_PA24_MISO1 ) | + ((unsigned int) AT91C_PA3_NPCS12 ) | + ((unsigned int) AT91C_PA26_NPCS12 ) | + ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI0 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPIO +//* \brief Configure PIO controllers to drive SPI0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB13_NPCS01 ) | + ((unsigned int) AT91C_PB17_NPCS03 ) | + ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA16_MISO0 ) | + ((unsigned int) AT91C_PA13_NPCS01 ) | + ((unsigned int) AT91C_PA15_NPCS03 ) | + ((unsigned int) AT91C_PA17_MOSI0 ) | + ((unsigned int) AT91C_PA18_SPCK0 ) | + ((unsigned int) AT91C_PA14_NPCS02 ) | + ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A + ((unsigned int) AT91C_PA7_NPCS01 ) | + ((unsigned int) AT91C_PA9_NPCS03 ) | + ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PITC +//*---------------------------------------------------------------------------- +__inline void AT91F_PITC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ0 ) | + ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A + ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgPMC +//* \brief Enable Peripheral clock in PMC for AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_AES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_TWCK ) | + ((unsigned int) AT91C_PA10_TWD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A + ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RTTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RTTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgPMC +//* \brief Enable Peripheral clock in PMC for TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TDES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPMC +//* \brief Enable Peripheral clock in PMC for EMAC +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_EMAC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPIO +//* \brief Configure PIO controllers to drive EMAC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB2_ETX0 ) | + ((unsigned int) AT91C_PB12_ETXER ) | + ((unsigned int) AT91C_PB16_ECOL ) | + ((unsigned int) AT91C_PB11_ETX3 ) | + ((unsigned int) AT91C_PB6_ERX1 ) | + ((unsigned int) AT91C_PB15_ERXDV ) | + ((unsigned int) AT91C_PB13_ERX2 ) | + ((unsigned int) AT91C_PB3_ETX1 ) | + ((unsigned int) AT91C_PB8_EMDC ) | + ((unsigned int) AT91C_PB5_ERX0 ) | + //((unsigned int) AT91C_PB18_EF100 ) | + ((unsigned int) AT91C_PB14_ERX3 ) | + ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | + ((unsigned int) AT91C_PB1_ETXEN ) | + ((unsigned int) AT91C_PB10_ETX2 ) | + ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | + ((unsigned int) AT91C_PB9_EMDIO ) | + ((unsigned int) AT91C_PB7_ERXER ) | + ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB23_TIOA0 ) | + ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A + ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB25_TIOA1 ) | + ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A + ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB28_TIOB2 ) | + ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A + 0); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOB_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOB +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOB_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOB)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPMC +//* \brief Enable Peripheral clock in PMC for CAN +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_CAN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPIO +//* \brief Configure PIO controllers to drive CAN signals +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA20_CANTX ) | + ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +#endif // lib_AT91SAM7X256_H diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/port.c new file mode 100644 index 0000000..73553ed --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/port.c @@ -0,0 +1,214 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM7 port. + * + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file. The ISR routines, which can only be compiled + * to ARM mode are contained in portISR.c. + *----------------------------------------------------------*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Processor constants. */ +#include "AT91SAM7X256.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the timer 0 to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ +AT91PS_PITC pxPIT = AT91C_BASE_PITC; + + /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends + on whether the preemptive or cooperative scheduler is being used. */ + #if configUSE_PREEMPTION == 0 + + extern void ( vNonPreemptiveTick ) ( void ); + AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick ); + + #else + + extern void ( vPreemptiveTick )( void ); + AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick ); + + #endif + + /* Configure the PIT period. */ + pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; + + /* Enable the interrupt. Global interrupts are disables at this point so + this is safe. */ + AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS; +} +/*-----------------------------------------------------------*/ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/portISR.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/portISR.c new file mode 100644 index 0000000..c7d60f0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/portISR.c @@ -0,0 +1,228 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* + Changes from V3.2.4 + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#include "AT91SAM7X256.h" + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + __asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); + void vNonPreemptiveTick( void ) + { + uint32_t ulDummy; + + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + xTaskIncrementTick(); + + /* Clear the PIT interrupt. */ + ulDummy = AT91C_BASE_PITC->PITC_PIVR; + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = ulDummy; + } + +#else + + /* The preemptive scheduler is defined as "naked" as the full context is + saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__((naked)); + void vPreemptiveTick( void ) + { + /* Save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Increment the tick count - this may wake a task. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + } + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR; + + portRESTORE_CONTEXT(); + } + +#endif +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); +void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + +void vPortDisableInterruptsFromThumb( void ) +{ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ +} + +void vPortEnableInterruptsFromThumb( void ) +{ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ +} + + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/portmacro.h new file mode 100644 index 0000000..8690c80 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_AT91SAM7S/portmacro.h @@ -0,0 +1,250 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + Changes from V3.2.3 + + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + Changes from V3.2.4 + + + Removed the use of the %0 parameter within the assembler macros and + replaced them with hard coded registers. This will ensure the + assembler does not select the link register as the temp register as + was occasionally happening previously. + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. + + Changes from V4.5.0 + + + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros + and replaced them with portYIELD_FROM_ISR() macro. Application code + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() + macros as per the V4.5.1 demo code. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE portLONG + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() __asm volatile ( "NOP" ); +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile uint32_t ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + __asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile uint32_t ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} + + +#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() __asm volatile ( "SWI 0" ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC2000/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC2000/port.c new file mode 100644 index 0000000..af61706 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC2000/port.c @@ -0,0 +1,222 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM7 port. + * + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file. The ISR routines, which can only be compiled + * to ARM mode are contained in portISR.c. + *----------------------------------------------------------*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the timer 0 to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ +uint32_t ulCompareMatch; +extern void ( vTickISR )( void ); + + /* A 1ms tick does not require the use of the timer prescale. This is + defaulted to zero but can be used if necessary. */ + T0_PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + T0_MR0 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; + + /* Setup the VIC for the timer. */ + VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); + VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; + + /* The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + + VICVectAddr0 = ( int32_t ) vTickISR; + VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; + + /* Start the timer - interrupts are disabled when this function is called + so it is okay to do this here. */ + T0_TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC2000/portISR.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC2000/portISR.c new file mode 100644 index 0000000..c277452 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC2000/portISR.c @@ -0,0 +1,216 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* + Changes from V2.5.2 + + + The critical section management functions have been changed. These no + longer modify the stack and are safe to use at all optimisation levels. + The functions are now also the same for both ARM and THUMB modes. + + Changes from V2.6.0 + + + Removed the 'static' from the definition of vNonPreemptiveTick() to + allow the demo to link when using the cooperative scheduler. + + Changes from V3.2.4 + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. +*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + __asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + __asm volatile ( "bl vTaskSwitchContext" ); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick. + */ +void vTickISR( void ) __attribute__((naked)); +void vTickISR( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Increment the RTOS tick count, then look for the highest priority + task that is ready to run. */ + __asm volatile + ( + " bl xTaskIncrementTick \t\n" \ + " cmp r0, #0 \t\n" \ + " beq SkipContextSwitch \t\n" \ + " bl vTaskSwitchContext \t\n" \ + "SkipContextSwitch: \t\n" + ); + + /* Ready for the next interrupt. */ + T0_IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + void vPortDisableInterruptsFromThumb( void ) + { + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC2000/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC2000/portmacro.h new file mode 100644 index 0000000..c8a2090 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC2000/portmacro.h @@ -0,0 +1,227 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE portLONG + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() __asm volatile ( "NOP" ); +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile uint32_t ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + __asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile uint32_t ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} + +extern void vTaskSwitchContext( void ); +#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() __asm volatile ( "SWI 0" ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC23xx/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC23xx/port.c new file mode 100644 index 0000000..0b8b795 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC23xx/port.c @@ -0,0 +1,234 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM7 port. + * + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file. The ISR routines, which can only be compiled + * to ARM mode are contained in portISR.c. + *----------------------------------------------------------*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the timer 0 to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ +uint32_t ulCompareMatch; + + PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2); + T0TCR = 2; /* Stop and reset the timer */ + T0CTCR = 0; /* Timer mode */ + + /* A 1ms tick does not require the use of the timer prescale. This is + defaulted to zero but can be used if necessary. */ + T0PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + T0MR1 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0MCR = (3 << 3); /* Reset timer on match and generate interrupt */ + + /* Setup the VIC for the timer. */ + VICIntEnable = 0x00000010; + + /* The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + extern void ( vPreemptiveTick )( void ); + VICVectAddr4 = ( int32_t ) vPreemptiveTick; + } + #else + { + extern void ( vNonPreemptiveTick )( void ); + VICVectAddr4 = ( int32_t ) vNonPreemptiveTick; + } + #endif + + VICVectCntl4 = 1; + + /* Start the timer - interrupts are disabled when this function is called + so it is okay to do this here. */ + T0TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC23xx/portISR.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC23xx/portISR.c new file mode 100644 index 0000000..dffe9ca --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC23xx/portISR.c @@ -0,0 +1,219 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + __asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + __asm volatile( "bl vTaskSwitchContext" ); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); + void vNonPreemptiveTick( void ) + { + xTaskIncrementTick(); + T0IR = 2; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#else + + /* The preemptive scheduler is defined as "naked" as the full context is + saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__((naked)); + void vPreemptiveTick( void ) + { + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Increment the RTOS tick count, then look for the highest priority + task that is ready to run. */ + __asm volatile + ( + " bl xTaskIncrementTick \t\n" \ + " cmp r0, #0 \t\n" \ + " beq SkipContextSwitch \t\n" \ + " bl vTaskSwitchContext \t\n" \ + "SkipContextSwitch: \t\n" + ); + + /* Ready for the next interrupt. */ + T0IR = 2; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + } + +#endif +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + void vPortDisableInterruptsFromThumb( void ) + { + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC23xx/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC23xx/portmacro.h new file mode 100644 index 0000000..7e4243b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM7_LPC23xx/portmacro.h @@ -0,0 +1,250 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + Changes from V3.2.3 + + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + Changes from V3.2.4 + + + Removed the use of the %0 parameter within the assembler macros and + replaced them with hard coded registers. This will ensure the + assembler does not select the link register as the temp register as + was occasionally happening previously. + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. + + Changes from V4.5.0 + + + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros + and replaced them with portYIELD_FROM_ISR() macro. Application code + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() + macros as per the V4.5.1 demo code. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE portLONG + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() __asm volatile ( "NOP" ); +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile uint32_t ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + __asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile uint32_t ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} + + +#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() __asm volatile ( "SWI 0" ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT/port.c new file mode 100644 index 0000000..99df392 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT/port.c @@ -0,0 +1,519 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS + #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET + #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) +#endif + +/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in +portmacro.h. */ +#ifndef configCLEAR_TICK_INTERRUPT + #define configCLEAR_TICK_INTERRUPT() +#endif + +/* A critical section is exited when the critical section nesting count reaches +this value. */ +#define portNO_CRITICAL_NESTING ( ( size_t ) 0 ) + +/* In all GICs 255 can be written to the priority mask register to unmask all +(but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) + +/* Tasks are not created with a floating point context, but can be given a +floating point context after they have been created. A variable is stored as +part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task +does not have an FPU context, or any other value if the task does have an FPU +context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portSP_ELx ( ( StackType_t ) 0x01 ) +#define portSP_EL0 ( ( StackType_t ) 0x00 ) + +#if defined( GUEST ) + #define portEL1 ( ( StackType_t ) 0x04 ) + #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 ) +#else + #define portEL3 ( ( StackType_t ) 0x0c ) + /* At the time of writing, the BSP only supports EL3. */ + #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 ) +#endif + + +/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary +point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x0C ) + +/* The I bit in the DAIF bits. */ +#define portDAIF_I ( 0x80 ) + +/* Macro to unmask all interrupt priorities. */ +#define portCLEAR_INTERRUPT_MASK() \ +{ \ + portDISABLE_INTERRUPTS(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm volatile ( "DSB SY \n" \ + "ISB SY \n" ); \ + portENABLE_INTERRUPTS(); \ +} + +/* Hardware specifics used when sanity checking the configuration. */ +#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portBIT_0_SET ( ( uint8_t ) 0x01 ) + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This +variable has to be stored as part of the task context and must be initialised to +a non zero value to ensure interrupts don't inadvertently become unmasked before +the scheduler starts. As it is stored as part of the task context it will +automatically be set to 0 when the first task is started. */ +volatile uint64_t ullCriticalNesting = 9999ULL; + +/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero +then floating point context must be saved and restored for the task. */ +uint64_t ullPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +uint64_t ullPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if +if the nesting depth is 0. */ +uint64_t ullPortInterruptNesting = 0; + +/* Used in the ASM code. */ +__attribute__(( used )) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS; +__attribute__(( used )) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS; +__attribute__(( used )) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS; +__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = 0x0101010101010101ULL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = 0x0303030303030303ULL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = 0x0202020202020202ULL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = 0x0505050505050505ULL; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = 0x0404040404040404ULL; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = 0x0707070707070707ULL; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = 0x0606060606060606ULL; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = 0x0909090909090909ULL; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = 0x0808080808080808ULL; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = 0x1111111111111111ULL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = 0x1010101010101010ULL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = 0x1313131313131313ULL; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = 0x1212121212121212ULL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = 0x1515151515151515ULL; /* R15 */ + pxTopOfStack--; + *pxTopOfStack = 0x1414141414141414ULL; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = 0x1717171717171717ULL; /* R17 */ + pxTopOfStack--; + *pxTopOfStack = 0x1616161616161616ULL; /* R16 */ + pxTopOfStack--; + *pxTopOfStack = 0x1919191919191919ULL; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = 0x1818181818181818ULL; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = 0x2121212121212121ULL; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = 0x2020202020202020ULL; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = 0x2323232323232323ULL; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = 0x2222222222222222ULL; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = 0x2525252525252525ULL; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = 0x2424242424242424ULL; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = 0x2727272727272727ULL; /* R27 */ + pxTopOfStack--; + *pxTopOfStack = 0x2626262626262626ULL; /* R26 */ + pxTopOfStack--; + *pxTopOfStack = 0x2929292929292929ULL; /* R29 */ + pxTopOfStack--; + *pxTopOfStack = 0x2828282828282828ULL; /* R28 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_PSTATE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + the floating point hardware must call vPortTaskUsesFPU() before executing + any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +uint32_t ulAPSR; + + #if( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine how many priority bits are implemented in the GIC. + + Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to + all possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Shift to the least significant bits. */ + while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET ) + { + ucMaxPriorityValue >>= ( uint8_t ) 0x01; + } + + /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read + value. */ + + configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY ); + + + /* Restore the clobbered interrupt priority register to its original + value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + + /* At the time of writing, the BSP only supports EL3. */ + __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + +#if defined( GUEST ) + #warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH. + configASSERT( ulAPSR == portEL1 ); + if( ulAPSR == portEL1 ) +#else + configASSERT( ulAPSR == portEL3 ); + if( ulAPSR == portEL3 ) +#endif + { + /* Only continue if the binary point value is set to its lowest possible + setting. See the comments in vPortValidateInterruptPriority() below for + more information. */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + + if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) + { + /* Interrupts are turned off in the CPU itself to ensure a tick does + not execute while the scheduler is being started. Interrupts are + automatically turned back on in the CPU when the first task starts + executing. */ + portDISABLE_INTERRUPTS(); + + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + } + + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ullCriticalNesting == 1000ULL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Mask interrupts up to the max syscall interrupt priority. */ + uxPortSetInterruptMask(); + + /* Now interrupts are disabled ullCriticalNesting can be accessed + directly. Increment ullCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ullCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( ullCriticalNesting == 1ULL ) + { + configASSERT( ullPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ullCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + exited. */ + ullCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + priorities must be re-enabled. */ + if( ullCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + should be unmasked. */ + portCLEAR_INTERRUPT_MASK(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* Must be the lowest possible priority. */ + #if !defined( QEMU ) + { + configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + } + #endif + + /* Interrupts should not be enabled before this point. */ + #if( configASSERT_DEFINED == 1 ) + { + uint32_t ulMaskBits; + + __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" ); + configASSERT( ( ulMaskBits & portDAIF_I ) != 0 ); + } + #endif /* configASSERT_DEFINED */ + + /* Set interrupt mask before altering scheduler structures. The tick + handler runs at the lowest priority, so interrupts cannot already be masked, + so there is no need to save and restore the current mask value. It is + necessary to turn off interrupts in the CPU itself while the ICCPMR is being + updated. */ + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm volatile ( "dsb sy \n" + "isb sy \n" ::: "memory" ); + + /* Ok to enable interrupts after the interrupt source has been cleared. */ + configCLEAR_TICK_INTERRUPT(); + portENABLE_INTERRUPTS(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ullPortYieldRequired = pdTRUE; + } + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (which is saved as part of the task context). */ + ullPortTaskHasFPUContext = pdTRUE; + + /* Consider initialising the FPSR here - but probably not necessary in + AArch64. */ +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ) +{ + if( uxNewMaskValue == pdFALSE ) + { + portCLEAR_INTERRUPT_MASK(); + } +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxPortSetInterruptMask( void ) +{ +uint32_t ulReturn; + + /* Interrupt in the CPU must be turned off while the ICCPMR is being + updated. */ + portDISABLE_INTERRUPTS(); + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + /* Interrupts were already masked. */ + ulReturn = pdTRUE; + } + else + { + ulReturn = pdFALSE; + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm volatile ( "dsb sy \n" + "isb sy \n" ::: "memory" ); + } + portENABLE_INTERRUPTS(); + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +#if( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* The following assertion will fail if a service routine (ISR) for + an interrupt that has been assigned a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + function. ISR safe FreeRTOS API functions must *only* be called + from interrupts that have been assigned a priority at or below + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Numerically low interrupt priority numbers represent logically high + interrupt priorities, therefore the priority of the interrupt must + be set to a value equal to or numerically *higher* than + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + FreeRTOS maintains separate thread and ISR API functions to ensure + interrupt entry is as fast and simple as possible. */ + configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + + /* Priority grouping: The interrupt controller (GIC) allows the bits + that define each interrupt's priority to be split between bits that + define the interrupt's pre-emption priority bits and bits that define + the interrupt's sub-priority. For simplicity all bits must be defined + to be pre-emption priority bits. The following assertion will fail if + this is not the case (if some bits represent a sub-priority). + + The priority grouping is configured by the GIC's binary point register + (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest + possible value (which may be above 0). */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT/portASM.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT/portASM.S new file mode 100644 index 0000000..6202df3 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT/portASM.S @@ -0,0 +1,432 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + .text + + /* Variables and functions. */ + .extern ullMaxAPIPriorityMask + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vApplicationIRQHandler + .extern ullPortInterruptNesting + .extern ullPortTaskHasFPUContext + .extern ullCriticalNesting + .extern ullPortYieldRequired + .extern ullICCEOIR + .extern ullICCIAR + .extern _freertos_vector_table + + .global FreeRTOS_IRQ_Handler + .global FreeRTOS_SWI_Handler + .global vPortRestoreTaskContext + + +.macro portSAVE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Save the entire context. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X20, X21, [SP, #-0x10]! + STP X22, X23, [SP, #-0x10]! + STP X24, X25, [SP, #-0x10]! + STP X26, X27, [SP, #-0x10]! + STP X28, X29, [SP, #-0x10]! + STP X30, XZR, [SP, #-0x10]! + + /* Save the SPSR. */ +#if defined( GUEST ) + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 +#else + MRS X3, SPSR_EL3 + /* Save the ELR. */ + MRS X2, ELR_EL3 +#endif + + STP X2, X3, [SP, #-0x10]! + + /* Save the critical section nesting depth. */ + LDR X0, ullCriticalNestingConst + LDR X3, [X0] + + /* Save the FPU context indicator. */ + LDR X0, ullPortTaskHasFPUContextConst + LDR X2, [X0] + + /* Save the FPU context, if any (32 128-bit registers). */ + CMP X2, #0 + B.EQ 1f + STP Q0, Q1, [SP,#-0x20]! + STP Q2, Q3, [SP,#-0x20]! + STP Q4, Q5, [SP,#-0x20]! + STP Q6, Q7, [SP,#-0x20]! + STP Q8, Q9, [SP,#-0x20]! + STP Q10, Q11, [SP,#-0x20]! + STP Q12, Q13, [SP,#-0x20]! + STP Q14, Q15, [SP,#-0x20]! + STP Q16, Q17, [SP,#-0x20]! + STP Q18, Q19, [SP,#-0x20]! + STP Q20, Q21, [SP,#-0x20]! + STP Q22, Q23, [SP,#-0x20]! + STP Q24, Q25, [SP,#-0x20]! + STP Q26, Q27, [SP,#-0x20]! + STP Q28, Q29, [SP,#-0x20]! + STP Q30, Q31, [SP,#-0x20]! + +1: + /* Store the critical nesting count and FPU context indicator. */ + STP X2, X3, [SP, #-0x10]! + + LDR X0, pxCurrentTCBConst + LDR X1, [X0] + MOV X0, SP /* Move SP into X0 for saving. */ + STR X0, [X1] + + /* Switch to use the ELx stack pointer. */ + MSR SPSEL, #1 + + .endm + +; /**********************************************************************/ + +.macro portRESTORE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Set the SP to point to the stack of the task being restored. */ + LDR X0, pxCurrentTCBConst + LDR X1, [X0] + LDR X0, [X1] + MOV SP, X0 + + LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */ + + /* Set the PMR register to be correct for the current critical nesting + depth. */ + LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */ + MOV X1, #255 /* X1 holds the unmask value. */ + LDR X4, ullICCPMRConst /* X4 holds the address of the ICCPMR constant. */ + CMP X3, #0 + LDR X5, [X4] /* X5 holds the address of the ICCPMR register. */ + B.EQ 1f + LDR X6, ullMaxAPIPriorityMaskConst + LDR X1, [X6] /* X1 holds the mask value. */ +1: + STR W1, [X5] /* Write the mask value to ICCPMR. */ + DSB SY /* _RB_Barriers probably not required here. */ + ISB SY + STR X3, [X0] /* Restore the task's critical nesting count. */ + + /* Restore the FPU context indicator. */ + LDR X0, ullPortTaskHasFPUContextConst + STR X2, [X0] + + /* Restore the FPU context, if any. */ + CMP X2, #0 + B.EQ 1f + LDP Q30, Q31, [SP], #0x20 + LDP Q28, Q29, [SP], #0x20 + LDP Q26, Q27, [SP], #0x20 + LDP Q24, Q25, [SP], #0x20 + LDP Q22, Q23, [SP], #0x20 + LDP Q20, Q21, [SP], #0x20 + LDP Q18, Q19, [SP], #0x20 + LDP Q16, Q17, [SP], #0x20 + LDP Q14, Q15, [SP], #0x20 + LDP Q12, Q13, [SP], #0x20 + LDP Q10, Q11, [SP], #0x20 + LDP Q8, Q9, [SP], #0x20 + LDP Q6, Q7, [SP], #0x20 + LDP Q4, Q5, [SP], #0x20 + LDP Q2, Q3, [SP], #0x20 + LDP Q0, Q1, [SP], #0x20 +1: + LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ + +#if defined( GUEST ) + /* Restore the SPSR. */ + MSR SPSR_EL1, X3 + /* Restore the ELR. */ + MSR ELR_EL1, X2 +#else + /* Restore the SPSR. */ + MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */ + /* Restore the ELR. */ + MSR ELR_EL3, X2 +#endif + + LDP X30, XZR, [SP], #0x10 + LDP X28, X29, [SP], #0x10 + LDP X26, X27, [SP], #0x10 + LDP X24, X25, [SP], #0x10 + LDP X22, X23, [SP], #0x10 + LDP X20, X21, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + /* Switch to use the ELx stack pointer. _RB_ Might not be required. */ + MSR SPSEL, #1 + + ERET + + .endm + + +/****************************************************************************** + * FreeRTOS_SWI_Handler handler is used to perform a context switch. + *****************************************************************************/ +.align 8 +.type FreeRTOS_SWI_Handler, %function +FreeRTOS_SWI_Handler: + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT +#if defined( GUEST ) + MRS X0, ESR_EL1 +#else + MRS X0, ESR_EL3 +#endif + + LSR X1, X0, #26 + +#if defined( GUEST ) + CMP X1, #0x15 /* 0x15 = SVC instruction. */ +#else + CMP X1, #0x17 /* 0x17 = SMC instruction. */ +#endif + B.NE FreeRTOS_Abort + BL vTaskSwitchContext + + portRESTORE_CONTEXT + +FreeRTOS_Abort: + /* Full ESR is in X0, exception class code is in X1. */ + B . + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ +.align 8 +.type vPortRestoreTaskContext, %function +vPortRestoreTaskContext: +.set freertos_vector_base, _freertos_vector_table + + /* Install the FreeRTOS interrupt handlers. */ + LDR X1, =freertos_vector_base +#if defined( GUEST ) + MSR VBAR_EL1, X1 +#else + MSR VBAR_EL3, X1 +#endif + DSB SY + ISB SY + + /* Start the first task. */ + portRESTORE_CONTEXT + + +/****************************************************************************** + * FreeRTOS_IRQ_Handler handles IRQ entry and exit. + *****************************************************************************/ +.align 8 +.type FreeRTOS_IRQ_Handler, %function +FreeRTOS_IRQ_Handler: + /* Save volatile registers. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X29, X30, [SP, #-0x10]! + + /* Save the SPSR and ELR. */ +#if defined( GUEST ) + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 +#else + MRS X3, SPSR_EL3 + MRS X2, ELR_EL3 +#endif + STP X2, X3, [SP, #-0x10]! + + /* Increment the interrupt nesting counter. */ + LDR X5, ullPortInterruptNestingConst + LDR X1, [X5] /* Old nesting count in X1. */ + ADD X6, X1, #1 + STR X6, [X5] /* Address of nesting count variable in X5. */ + + /* Maintain the interrupt nesting information across the function call. */ + STP X1, X5, [SP, #-0x10]! + + /* Read value from the interrupt acknowledge register, which is stored in W0 + for future parameter and interrupt clearing use. */ + LDR X2, ullICCIARConst + LDR X3, [X2] + LDR W0, [X3] /* ICCIAR in W0 as parameter. */ + + /* Maintain the ICCIAR value across the function call. */ + STP X0, X1, [SP, #-0x10]! + + /* Call the C handler. */ + BL vApplicationIRQHandler + + /* Disable interrupts. */ + MSR DAIFSET, #2 + DSB SY + ISB SY + + /* Restore the ICCIAR value. */ + LDP X0, X1, [SP], #0x10 + + /* End IRQ processing by writing ICCIAR to the EOI register. */ + LDR X4, ullICCEOIRConst + LDR X4, [X4] + STR W0, [X4] + + /* Restore the critical nesting count. */ + LDP X1, X5, [SP], #0x10 + STR X1, [X5] + + /* Has interrupt nesting unwound? */ + CMP X1, #0 + B.NE Exit_IRQ_No_Context_Switch + + /* Is a context switch required? */ + LDR X0, ullPortYieldRequiredConst + LDR X1, [X0] + CMP X1, #0 + B.EQ Exit_IRQ_No_Context_Switch + + /* Reset ullPortYieldRequired to 0. */ + MOV X2, #0 + STR X2, [X0] + + /* Restore volatile registers. */ + LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */ +#if defined( GUEST ) + MSR SPSR_EL1, X5 + MSR ELR_EL1, X4 +#else + MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */ + MSR ELR_EL3, X4 +#endif + DSB SY + ISB SY + + LDP X29, X30, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + BL vTaskSwitchContext + portRESTORE_CONTEXT + +Exit_IRQ_No_Context_Switch: + /* Restore volatile registers. */ + LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */ +#if defined( GUEST ) + MSR SPSR_EL1, X5 + MSR ELR_EL1, X4 +#else + MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */ + MSR ELR_EL3, X4 +#endif + DSB SY + ISB SY + + LDP X29, X30, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + ERET + + + + +.align 8 +pxCurrentTCBConst: .dword pxCurrentTCB +ullCriticalNestingConst: .dword ullCriticalNesting +ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext + +ullICCPMRConst: .dword ullICCPMR +ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask +ullPortInterruptNestingConst: .dword ullPortInterruptNesting +ullPortYieldRequiredConst: .dword ullPortYieldRequired +ullICCIARConst: .dword ullICCIAR +ullICCEOIRConst: .dword ullICCEOIR +vApplicationIRQHandlerConst: .word vApplicationIRQHandler + + + +.end + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT/portmacro.h new file mode 100644 index 0000000..5fbd68d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT/portmacro.h @@ -0,0 +1,212 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE size_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef uint64_t UBaseType_t; + +typedef uint64_t TickType_t; +#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff ) + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do +not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 16 +#define portPOINTER_SIZE_TYPE uint64_t + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired )\ +{ \ +extern uint64_t ullPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ullPortYieldRequired = pdTRUE; \ + } \ +} + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#if defined( GUEST ) + #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" ) +#else + #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" ) +#endif +/*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern UBaseType_t uxPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ); +extern void vPortInstallFreeRTOSVectorTable( void ); + +#define portDISABLE_INTERRUPTS() \ + __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \ + __asm volatile ( "DSB SY" ); \ + __asm volatile ( "ISB SY" ); + +#define portENABLE_INTERRUPTS() \ + __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \ + __asm volatile ( "DSB SY" ); \ + __asm volatile ( "ISB SY" ); + + +/* These macros do not globally disable/enable interrupts. They do mask off +interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not required for this port but included in case common demo code that uses these +macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the +handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() +before any floating point instructions are executed. */ +void vPortTaskUsesFPU( void ); +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* configASSERT */ + +#define portNOP() __asm volatile( "NOP" ) +#define portINLINE __inline + +#ifdef __cplusplus + } /* extern C */ +#endif + + +/* The number of bits to shift for an interrupt priority is dependent on the +number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif + +/* Interrupt controller access addresses. */ +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) + +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) + +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT_SRE/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT_SRE/port.c new file mode 100644 index 0000000..5157bf8 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT_SRE/port.c @@ -0,0 +1,459 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) +#endif + +/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in +portmacro.h. */ +#ifndef configCLEAR_TICK_INTERRUPT + #define configCLEAR_TICK_INTERRUPT() +#endif + +/* A critical section is exited when the critical section nesting count reaches +this value. */ +#define portNO_CRITICAL_NESTING ( ( size_t ) 0 ) + +/* In all GICs 255 can be written to the priority mask register to unmask all +(but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) + +/* Tasks are not created with a floating point context, but can be given a +floating point context after they have been created. A variable is stored as +part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task +does not have an FPU context, or any other value if the task does have an FPU +context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portSP_ELx ( ( StackType_t ) 0x01 ) +#define portSP_EL0 ( ( StackType_t ) 0x00 ) + +#if defined( GUEST ) + #define portEL1 ( ( StackType_t ) 0x04 ) + #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 ) +#else + #define portEL3 ( ( StackType_t ) 0x0c ) + /* At the time of writing, the BSP only supports EL3. */ + #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 ) +#endif + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x0C ) + +/* The I bit in the DAIF bits. */ +#define portDAIF_I ( 0x80 ) + +/* Macro to unmask all interrupt priorities. */ +/* s3_0_c4_c6_0 is ICC_PMR_EL1. */ +#define portCLEAR_INTERRUPT_MASK() \ +{ \ + __asm volatile ( "MSR DAIFSET, #2 \n" \ + "DSB SY \n" \ + "ISB SY \n" \ + "MSR s3_0_c4_c6_0, %0 \n" \ + "DSB SY \n" \ + "ISB SY \n" \ + "MSR DAIFCLR, #2 \n" \ + "DSB SY \n" \ + "ISB SY \n" \ + ::"r"( portUNMASK_VALUE ) ); \ +} + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This +variable has to be stored as part of the task context and must be initialised to +a non zero value to ensure interrupts don't inadvertently become unmasked before +the scheduler starts. As it is stored as part of the task context it will +automatically be set to 0 when the first task is started. */ +volatile uint64_t ullCriticalNesting = 9999ULL; + +/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero +then floating point context must be saved and restored for the task. */ +uint64_t ullPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +uint64_t ullPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if +if the nesting depth is 0. */ +uint64_t ullPortInterruptNesting = 0; + +/* Used in the ASM code. */ +__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = 0x0101010101010101ULL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = 0x0303030303030303ULL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = 0x0202020202020202ULL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = 0x0505050505050505ULL; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = 0x0404040404040404ULL; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = 0x0707070707070707ULL; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = 0x0606060606060606ULL; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = 0x0909090909090909ULL; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = 0x0808080808080808ULL; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = 0x1111111111111111ULL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = 0x1010101010101010ULL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = 0x1313131313131313ULL; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = 0x1212121212121212ULL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = 0x1515151515151515ULL; /* R15 */ + pxTopOfStack--; + *pxTopOfStack = 0x1414141414141414ULL; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = 0x1717171717171717ULL; /* R17 */ + pxTopOfStack--; + *pxTopOfStack = 0x1616161616161616ULL; /* R16 */ + pxTopOfStack--; + *pxTopOfStack = 0x1919191919191919ULL; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = 0x1818181818181818ULL; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = 0x2121212121212121ULL; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = 0x2020202020202020ULL; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = 0x2323232323232323ULL; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = 0x2222222222222222ULL; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = 0x2525252525252525ULL; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = 0x2424242424242424ULL; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = 0x2727272727272727ULL; /* R27 */ + pxTopOfStack--; + *pxTopOfStack = 0x2626262626262626ULL; /* R26 */ + pxTopOfStack--; + *pxTopOfStack = 0x2929292929292929ULL; /* R29 */ + pxTopOfStack--; + *pxTopOfStack = 0x2828282828282828ULL; /* R28 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_PSTATE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + the floating point hardware must call vPortTaskUsesFPU() before executing + any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +uint32_t ulAPSR; + + __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + +#if defined( GUEST ) + configASSERT( ulAPSR == portEL1 ); + if( ulAPSR == portEL1 ) +#else + configASSERT( ulAPSR == portEL3 ); + if( ulAPSR == portEL3 ) +#endif + { + /* Interrupts are turned off in the CPU itself to ensure a tick does + not execute while the scheduler is being started. Interrupts are + automatically turned back on in the CPU when the first task starts + executing. */ + portDISABLE_INTERRUPTS(); + + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ullCriticalNesting == 1000ULL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Mask interrupts up to the max syscall interrupt priority. */ + uxPortSetInterruptMask(); + + /* Now interrupts are disabled ullCriticalNesting can be accessed + directly. Increment ullCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ullCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( ullCriticalNesting == 1ULL ) + { + configASSERT( ullPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ullCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + exited. */ + ullCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + priorities must be re-enabled. */ + if( ullCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + should be unmasked. */ + portCLEAR_INTERRUPT_MASK(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* Must be the lowest possible priority. */ + #if !defined( QEMU ) + { + uint64_t ullRunningInterruptPriority; + /* s3_0_c12_c11_3 is ICC_RPR_EL1. */ + __asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) ); + configASSERT( ullRunningInterruptPriority == ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + } + #endif + + /* Interrupts should not be enabled before this point. */ + #if( configASSERT_DEFINED == 1 ) + { + uint32_t ulMaskBits; + + __asm volatile( "MRS %0, DAIF" : "=r"( ulMaskBits ) :: "memory" ); + configASSERT( ( ulMaskBits & portDAIF_I ) != 0 ); + } + #endif /* configASSERT_DEFINED */ + + /* Set interrupt mask before altering scheduler structures. The tick + handler runs at the lowest priority, so interrupts cannot already be masked, + so there is no need to save and restore the current mask value. It is + necessary to turn off interrupts in the CPU itself while the ICCPMR is being + updated. */ + /* s3_0_c4_c6_0 is ICC_PMR_EL1. */ + __asm volatile ( "MSR s3_0_c4_c6_0, %0 \n" + "DSB SY \n" + "ISB SY \n" + :: "r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" ); + + /* Ok to enable interrupts after the interrupt source has been cleared. */ + configCLEAR_TICK_INTERRUPT(); + portENABLE_INTERRUPTS(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ullPortYieldRequired = pdTRUE; + } + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (which is saved as part of the task context). */ + ullPortTaskHasFPUContext = pdTRUE; + + /* Consider initialising the FPSR here - but probably not necessary in + AArch64. */ +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ) +{ + if( uxNewMaskValue == pdFALSE ) + { + portCLEAR_INTERRUPT_MASK(); + } +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxPortSetInterruptMask( void ) +{ +uint32_t ulReturn; +uint64_t ullPMRValue; + + /* Interrupt in the CPU must be turned off while the ICCPMR is being + updated. */ + portDISABLE_INTERRUPTS(); + /* s3_0_c4_c6_0 is ICC_PMR_EL1. */ + __asm volatile ( "MRS %0, s3_0_c4_c6_0" : "=r" ( ullPMRValue ) ); + if( ullPMRValue == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + /* Interrupts were already masked. */ + ulReturn = pdTRUE; + } + else + { + ulReturn = pdFALSE; + /* s3_0_c4_c6_0 is ICC_PMR_EL1. */ + __asm volatile ( "MSR s3_0_c4_c6_0, %0 \n" + "DSB SY \n" + "ISB SY \n" + :: "r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" ); + } + + portENABLE_INTERRUPTS(); + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +#if( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* The following assertion will fail if a service routine (ISR) for + an interrupt that has been assigned a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + function. ISR safe FreeRTOS API functions must *only* be called + from interrupts that have been assigned a priority at or below + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Numerically low interrupt priority numbers represent logically high + interrupt priorities, therefore the priority of the interrupt must + be set to a value equal to or numerically *higher* than + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + FreeRTOS maintains separate thread and ISR API functions to ensure + interrupt entry is as fast and simple as possible. */ + uint64_t ullRunningInterruptPriority; + /* s3_0_c12_c11_3 is ICC_RPR_EL1. */ + __asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) ); + configASSERT( ullRunningInterruptPriority >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S new file mode 100644 index 0000000..de61e9a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S @@ -0,0 +1,421 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + .text + + /* Variables and functions. */ + .extern ullMaxAPIPriorityMask + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vApplicationIRQHandler + .extern ullPortInterruptNesting + .extern ullPortTaskHasFPUContext + .extern ullCriticalNesting + .extern ullPortYieldRequired + .extern _freertos_vector_table + + .global FreeRTOS_IRQ_Handler + .global FreeRTOS_SWI_Handler + .global vPortRestoreTaskContext + + +.macro portSAVE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Save the entire context. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X20, X21, [SP, #-0x10]! + STP X22, X23, [SP, #-0x10]! + STP X24, X25, [SP, #-0x10]! + STP X26, X27, [SP, #-0x10]! + STP X28, X29, [SP, #-0x10]! + STP X30, XZR, [SP, #-0x10]! + + /* Save the SPSR. */ +#if defined( GUEST ) + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 +#else + MRS X3, SPSR_EL3 + /* Save the ELR. */ + MRS X2, ELR_EL3 +#endif + + STP X2, X3, [SP, #-0x10]! + + /* Save the critical section nesting depth. */ + LDR X0, ullCriticalNestingConst + LDR X3, [X0] + + /* Save the FPU context indicator. */ + LDR X0, ullPortTaskHasFPUContextConst + LDR X2, [X0] + + /* Save the FPU context, if any (32 128-bit registers). */ + CMP X2, #0 + B.EQ 1f + STP Q0, Q1, [SP,#-0x20]! + STP Q2, Q3, [SP,#-0x20]! + STP Q4, Q5, [SP,#-0x20]! + STP Q6, Q7, [SP,#-0x20]! + STP Q8, Q9, [SP,#-0x20]! + STP Q10, Q11, [SP,#-0x20]! + STP Q12, Q13, [SP,#-0x20]! + STP Q14, Q15, [SP,#-0x20]! + STP Q16, Q17, [SP,#-0x20]! + STP Q18, Q19, [SP,#-0x20]! + STP Q20, Q21, [SP,#-0x20]! + STP Q22, Q23, [SP,#-0x20]! + STP Q24, Q25, [SP,#-0x20]! + STP Q26, Q27, [SP,#-0x20]! + STP Q28, Q29, [SP,#-0x20]! + STP Q30, Q31, [SP,#-0x20]! + +1: + /* Store the critical nesting count and FPU context indicator. */ + STP X2, X3, [SP, #-0x10]! + + LDR X0, pxCurrentTCBConst + LDR X1, [X0] + MOV X0, SP /* Move SP into X0 for saving. */ + STR X0, [X1] + + /* Switch to use the ELx stack pointer. */ + MSR SPSEL, #1 + + .endm + +; /**********************************************************************/ + +.macro portRESTORE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Set the SP to point to the stack of the task being restored. */ + LDR X0, pxCurrentTCBConst + LDR X1, [X0] + LDR X0, [X1] + MOV SP, X0 + + LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */ + + /* Set the PMR register to be correct for the current critical nesting + depth. */ + LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */ + MOV X1, #255 /* X1 holds the unmask value. */ + CMP X3, #0 + B.EQ 1f + LDR X6, ullMaxAPIPriorityMaskConst + LDR X1, [X6] /* X1 holds the mask value. */ +1: + MSR s3_0_c4_c6_0, X1 /* Write the mask value to ICCPMR. s3_0_c4_c6_0 is ICC_PMR_EL1. */ + DSB SY /* _RB_Barriers probably not required here. */ + ISB SY + STR X3, [X0] /* Restore the task's critical nesting count. */ + + /* Restore the FPU context indicator. */ + LDR X0, ullPortTaskHasFPUContextConst + STR X2, [X0] + + /* Restore the FPU context, if any. */ + CMP X2, #0 + B.EQ 1f + LDP Q30, Q31, [SP], #0x20 + LDP Q28, Q29, [SP], #0x20 + LDP Q26, Q27, [SP], #0x20 + LDP Q24, Q25, [SP], #0x20 + LDP Q22, Q23, [SP], #0x20 + LDP Q20, Q21, [SP], #0x20 + LDP Q18, Q19, [SP], #0x20 + LDP Q16, Q17, [SP], #0x20 + LDP Q14, Q15, [SP], #0x20 + LDP Q12, Q13, [SP], #0x20 + LDP Q10, Q11, [SP], #0x20 + LDP Q8, Q9, [SP], #0x20 + LDP Q6, Q7, [SP], #0x20 + LDP Q4, Q5, [SP], #0x20 + LDP Q2, Q3, [SP], #0x20 + LDP Q0, Q1, [SP], #0x20 +1: + LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ + +#if defined( GUEST ) + /* Restore the SPSR. */ + MSR SPSR_EL1, X3 + /* Restore the ELR. */ + MSR ELR_EL1, X2 +#else + /* Restore the SPSR. */ + MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */ + /* Restore the ELR. */ + MSR ELR_EL3, X2 +#endif + + LDP X30, XZR, [SP], #0x10 + LDP X28, X29, [SP], #0x10 + LDP X26, X27, [SP], #0x10 + LDP X24, X25, [SP], #0x10 + LDP X22, X23, [SP], #0x10 + LDP X20, X21, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + /* Switch to use the ELx stack pointer. _RB_ Might not be required. */ + MSR SPSEL, #1 + + ERET + + .endm + + +/****************************************************************************** + * FreeRTOS_SWI_Handler handler is used to perform a context switch. + *****************************************************************************/ +.align 8 +.type FreeRTOS_SWI_Handler, %function +FreeRTOS_SWI_Handler: + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT +#if defined( GUEST ) + MRS X0, ESR_EL1 +#else + MRS X0, ESR_EL3 +#endif + + LSR X1, X0, #26 + +#if defined( GUEST ) + CMP X1, #0x15 /* 0x15 = SVC instruction. */ +#else + CMP X1, #0x17 /* 0x17 = SMC instruction. */ +#endif + B.NE FreeRTOS_Abort + BL vTaskSwitchContext + + portRESTORE_CONTEXT + +FreeRTOS_Abort: + /* Full ESR is in X0, exception class code is in X1. */ + B . + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ +.align 8 +.type vPortRestoreTaskContext, %function +vPortRestoreTaskContext: +.set freertos_vector_base, _freertos_vector_table + + /* Install the FreeRTOS interrupt handlers. */ + LDR X1, =freertos_vector_base +#if defined( GUEST ) + MSR VBAR_EL1, X1 +#else + MSR VBAR_EL3, X1 +#endif + DSB SY + ISB SY + + /* Start the first task. */ + portRESTORE_CONTEXT + + +/****************************************************************************** + * FreeRTOS_IRQ_Handler handles IRQ entry and exit. + + * This handler is supposed to be used only for IRQs and never for FIQs. Per ARM + * GIC documentation [1], Group 0 interrupts are always signaled as FIQs. Since + * this handler is only for IRQs, We can safely assume Group 1 while accessing + * Interrupt Acknowledge and End Of Interrupt registers and therefore, use + * ICC_IAR1_EL1 and ICC_EOIR1_EL1. + * + * [1] https://developer.arm.com/documentation/198123/0300/Arm-CoreLink-GIC-fundamentals + *****************************************************************************/ +.align 8 +.type FreeRTOS_IRQ_Handler, %function +FreeRTOS_IRQ_Handler: + /* Save volatile registers. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X29, X30, [SP, #-0x10]! + + /* Save the SPSR and ELR. */ +#if defined( GUEST ) + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 +#else + MRS X3, SPSR_EL3 + MRS X2, ELR_EL3 +#endif + STP X2, X3, [SP, #-0x10]! + + /* Increment the interrupt nesting counter. */ + LDR X5, ullPortInterruptNestingConst + LDR X1, [X5] /* Old nesting count in X1. */ + ADD X6, X1, #1 + STR X6, [X5] /* Address of nesting count variable in X5. */ + + /* Maintain the interrupt nesting information across the function call. */ + STP X1, X5, [SP, #-0x10]! + + /* Read interrupt ID from the interrupt acknowledge register and store it + in X0 for future parameter and interrupt clearing use. */ + MRS X0, S3_0_C12_C12_0 /* S3_0_C12_C12_0 is ICC_IAR1_EL1. */ + + /* Maintain the interrupt ID value across the function call. */ + STP X0, X1, [SP, #-0x10]! + + /* Call the C handler. */ + BL vApplicationIRQHandler + + /* Disable interrupts. */ + MSR DAIFSET, #2 + DSB SY + ISB SY + + /* Restore the interrupt ID value. */ + LDP X0, X1, [SP], #0x10 + + /* End IRQ processing by writing interrupt ID value to the EOI register. */ + MSR S3_0_C12_C12_1, X0 /* S3_0_C12_C12_1 is ICC_EOIR1_EL1. */ + + /* Restore the critical nesting count. */ + LDP X1, X5, [SP], #0x10 + STR X1, [X5] + + /* Has interrupt nesting unwound? */ + CMP X1, #0 + B.NE Exit_IRQ_No_Context_Switch + + /* Is a context switch required? */ + LDR X0, ullPortYieldRequiredConst + LDR X1, [X0] + CMP X1, #0 + B.EQ Exit_IRQ_No_Context_Switch + + /* Reset ullPortYieldRequired to 0. */ + MOV X2, #0 + STR X2, [X0] + + /* Restore volatile registers. */ + LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */ +#if defined( GUEST ) + MSR SPSR_EL1, X5 + MSR ELR_EL1, X4 +#else + MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */ + MSR ELR_EL3, X4 +#endif + DSB SY + ISB SY + + LDP X29, X30, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + BL vTaskSwitchContext + portRESTORE_CONTEXT + +Exit_IRQ_No_Context_Switch: + /* Restore volatile registers. */ + LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */ +#if defined( GUEST ) + MSR SPSR_EL1, X5 + MSR ELR_EL1, X4 +#else + MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */ + MSR ELR_EL3, X4 +#endif + DSB SY + ISB SY + + LDP X29, X30, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + ERET + + + + +.align 8 +pxCurrentTCBConst: .dword pxCurrentTCB +ullCriticalNestingConst: .dword ullCriticalNesting +ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext + +ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask +ullPortInterruptNestingConst: .dword ullPortInterruptNesting +ullPortYieldRequiredConst: .dword ullPortYieldRequired + +.end diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h new file mode 100644 index 0000000..763196d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h @@ -0,0 +1,197 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE size_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef uint64_t UBaseType_t; + +typedef uint64_t TickType_t; +#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff ) + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do +not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 16 +#define portPOINTER_SIZE_TYPE uint64_t + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired )\ +{ \ +extern uint64_t ullPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ullPortYieldRequired = pdTRUE; \ + } \ +} + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#if defined( GUEST ) + #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" ) +#else + #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" ) +#endif +/*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern UBaseType_t uxPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ); +extern void vPortInstallFreeRTOSVectorTable( void ); + +#define portDISABLE_INTERRUPTS() \ + __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \ + __asm volatile ( "DSB SY" ); \ + __asm volatile ( "ISB SY" ); + +#define portENABLE_INTERRUPTS() \ + __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \ + __asm volatile ( "DSB SY" ); \ + __asm volatile ( "ISB SY" ); + + +/* These macros do not globally disable/enable interrupts. They do mask off +interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not required for this port but included in case common demo code that uses these +macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the +handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() +before any floating point instructions are executed. */ +void vPortTaskUsesFPU( void ); +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* configASSERT */ + +#define portNOP() __asm volatile( "NOP" ) +#define portINLINE __inline + +#ifdef __cplusplus + } /* extern C */ +#endif + + +/* The number of bits to shift for an interrupt priority is dependent on the +number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif + +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA9/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA9/port.c new file mode 100644 index 0000000..0977b09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA9/port.c @@ -0,0 +1,570 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS + #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET + #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) +#endif + +/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in +portmacro.h. */ +#ifndef configCLEAR_TICK_INTERRUPT + #define configCLEAR_TICK_INTERRUPT() +#endif + +/* A critical section is exited when the critical section nesting count reaches +this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* In all GICs 255 can be written to the priority mask register to unmask all +(but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) + +/* Tasks are not created with a floating point context, but can be given a +floating point context after they have been created. A variable is stored as +part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task +does not have an FPU context, or any other value if the task does have an FPU +context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINTERRUPT_ENABLE_BIT ( 0x80UL ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary +point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user +mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* The critical section macros only mask interrupts up to an application +determined priority level. Sometimes it is necessary to turn interrupt off in +the CPU itself before modifying certain hardware registers. */ +#define portCPU_IRQ_DISABLE() \ + __asm volatile ( "CPSID i" ::: "memory" ); \ + __asm volatile ( "DSB" ); \ + __asm volatile ( "ISB" ); + +#define portCPU_IRQ_ENABLE() \ + __asm volatile ( "CPSIE i" ::: "memory" ); \ + __asm volatile ( "DSB" ); \ + __asm volatile ( "ISB" ); + + +/* Macro to unmask all interrupt priorities. */ +#define portCLEAR_INTERRUPT_MASK() \ +{ \ + portCPU_IRQ_DISABLE(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm volatile ( "DSB \n" \ + "ISB \n" ); \ + portCPU_IRQ_ENABLE(); \ +} + +#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portBIT_0_SET ( ( uint8_t ) 0x01 ) + +/* Let the user override the pre-loading of the initial LR with the address of +prvTaskExitError() in case it messes up unwinding of the stack in the +debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* The space on the stack required to hold the FPU registers. This is 32 64-bit +registers, plus a 32-bit status register. */ +#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/* + * If the application provides an implementation of vApplicationIRQHandler(), + * then it will get called directly without saving the FPU registers on + * interrupt entry, and this weak implementation of + * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors - + * it should never actually get called so its implementation contains a + * call to configASSERT() that will always fail. + * + * If the application provides its own implementation of + * vApplicationFPUSafeIRQHandler() then the implementation of + * vApplicationIRQHandler() provided in portASM.S will save the FPU registers + * before calling it. + * + * Therefore, if the application writer wants FPU registers to be saved on + * interrupt entry their IRQ handler must be called + * vApplicationFPUSafeIRQHandler(), and if the application writer does not want + * FPU registers to be saved on interrupt entry their IRQ handler must be + * called vApplicationIRQHandler(). + */ +void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This +variable has to be stored as part of the task context and must be initialised to +a non zero value to ensure interrupts don't inadvertently become unmasked before +the scheduler starts. As it is stored as part of the task context it will +automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then +a floating point context must be saved and restored for the task. */ +volatile uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +volatile uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if +if the nesting depth is 0. */ +volatile uint32_t ulPortInterruptNesting = 0UL; + +/* Used in the asm file. */ +__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS; +__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS; +__attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS; +__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. + + The fist real value on the stack is the status register, which is set for + system mode, with interrupts enabled. A few NULLs are added first to ensure + GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + #if( configUSE_TASK_FPU_SUPPORT == 1 ) + { + /* The task will start without a floating point context. A task that + uses the floating point hardware must call vPortTaskUsesFPU() before + executing any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + } + #elif( configUSE_TASK_FPU_SUPPORT == 2 ) + { + /* The task will start with a floating point context. Leave enough + space for the registers - and ensure they are initialised to 0. */ + pxTopOfStack -= portFPU_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) ); + + pxTopOfStack--; + *pxTopOfStack = pdTRUE; + ulPortTaskHasFPUContext = pdTRUE; + } + #else + { + #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined. + } + #endif + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +uint32_t ulAPSR; + + #if( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine how many priority bits are implemented in the GIC. + + Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to + all possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Shift to the least significant bits. */ + while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET ) + { + ucMaxPriorityValue >>= ( uint8_t ) 0x01; + } + + /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read + value. */ + configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY ); + + /* Restore the clobbered interrupt priority register to its original + value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + + /* Only continue if the CPU is not in User mode. The CPU must be in a + Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Only continue if the binary point value is set to its lowest possible + setting. See the comments in vPortValidateInterruptPriority() below for + more information. */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + + if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) + { + /* Interrupts are turned off in the CPU itself to ensure tick does + not execute while the scheduler is being started. Interrupts are + automatically turned back on in the CPU when the first task starts + executing. */ + portCPU_IRQ_DISABLE(); + + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + a non-privileged mode or the binary point register was not set to its lowest + possible value. prvTaskExitError() is referenced to prevent a compiler + warning about it being defined but not referenced in the case that the user + defines their own exit address. */ + ( void ) prvTaskExitError; + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Mask interrupts up to the max syscall interrupt priority. */ + ulPortSetInterruptMask(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + should be unmasked. */ + portCLEAR_INTERRUPT_MASK(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* Set interrupt mask before altering scheduler structures. The tick + handler runs at the lowest priority, so interrupts cannot already be masked, + so there is no need to save and restore the current mask value. It is + necessary to turn off interrupts in the CPU itself while the ICCPMR is being + updated. */ + portCPU_IRQ_DISABLE(); + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm volatile ( "dsb \n" + "isb \n" ::: "memory" ); + portCPU_IRQ_ENABLE(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK(); + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +#if( configUSE_TASK_FPU_SUPPORT != 2 ) + + void vPortTaskUsesFPU( void ) + { + uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" ); + } + +#endif /* configUSE_TASK_FPU_SUPPORT */ +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( uint32_t ulNewMaskValue ) +{ + if( ulNewMaskValue == pdFALSE ) + { + portCLEAR_INTERRUPT_MASK(); + } +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortSetInterruptMask( void ) +{ +uint32_t ulReturn; + + /* Interrupt in the CPU must be turned off while the ICCPMR is being + updated. */ + portCPU_IRQ_DISABLE(); + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + /* Interrupts were already masked. */ + ulReturn = pdTRUE; + } + else + { + ulReturn = pdFALSE; + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm volatile ( "dsb \n" + "isb \n" ::: "memory" ); + } + portCPU_IRQ_ENABLE(); + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +#if( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* The following assertion will fail if a service routine (ISR) for + an interrupt that has been assigned a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + function. ISR safe FreeRTOS API functions must *only* be called + from interrupts that have been assigned a priority at or below + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Numerically low interrupt priority numbers represent logically high + interrupt priorities, therefore the priority of the interrupt must + be set to a value equal to or numerically *higher* than + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + FreeRTOS maintains separate thread and ISR API functions to ensure + interrupt entry is as fast and simple as possible. */ + configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + + /* Priority grouping: The interrupt controller (GIC) allows the bits + that define each interrupt's priority to be split between bits that + define the interrupt's pre-emption priority bits and bits that define + the interrupt's sub-priority. For simplicity all bits must be defined + to be pre-emption priority bits. The following assertion will fail if + this is not the case (if some bits represent a sub-priority). + + The priority grouping is configured by the GIC's binary point register + (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest + possible value (which may be above 0). */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ + +void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) +{ + ( void ) ulICCIAR; + configASSERT( ( volatile void * ) NULL ); +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA9/portASM.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA9/portASM.S new file mode 100644 index 0000000..e38d4df --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA9/portASM.S @@ -0,0 +1,324 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + .eabi_attribute Tag_ABI_align_preserved, 1 + .text + .arm + + .set SYS_MODE, 0x1f + .set SVC_MODE, 0x13 + .set IRQ_MODE, 0x12 + + /* Hardware registers. */ + .extern ulICCIAR + .extern ulICCEOIR + .extern ulICCPMR + + /* Variables and functions. */ + .extern ulMaxAPIPriorityMask + .extern _freertos_vector_table + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vApplicationIRQHandler + .extern ulPortInterruptNesting + .extern ulPortTaskHasFPUContext + + .global FreeRTOS_IRQ_Handler + .global FreeRTOS_SWI_Handler + .global vPortRestoreTaskContext + + + + +.macro portSAVE_CONTEXT + + /* Save the LR and SPSR onto the system mode stack before switching to + system mode to save the remaining system mode registers. */ + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + /* Push the critical nesting count. */ + LDR R2, ulCriticalNestingConst + LDR R1, [R2] + PUSH {R1} + + /* Does the task have a floating point context that needs saving? If + ulPortTaskHasFPUContext is 0 then no. */ + LDR R2, ulPortTaskHasFPUContextConst + LDR R3, [R2] + CMP R3, #0 + + /* Save the floating point context, if any. */ + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} + VPUSHNE {D16-D31} + PUSHNE {R1} + + /* Save ulPortTaskHasFPUContext itself. */ + PUSH {R3} + + /* Save the stack pointer in the TCB. */ + LDR R0, pxCurrentTCBConst + LDR R1, [R0] + STR SP, [R1] + + .endm + +; /**********************************************************************/ + +.macro portRESTORE_CONTEXT + + /* Set the SP to point to the stack of the task being restored. */ + LDR R0, pxCurrentTCBConst + LDR R1, [R0] + LDR SP, [R1] + + /* Is there a floating point context to restore? If the restored + ulPortTaskHasFPUContext is zero then no. */ + LDR R0, ulPortTaskHasFPUContextConst + POP {R1} + STR R1, [R0] + CMP R1, #0 + + /* Restore the floating point context, if any. */ + POPNE {R0} + VPOPNE {D16-D31} + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + /* Restore the critical section nesting depth. */ + LDR R0, ulCriticalNestingConst + POP {R1} + STR R1, [R0] + + /* Ensure the priority mask is correct for the critical nesting depth. */ + LDR R2, ulICCPMRConst + LDR R2, [R2] + CMP R1, #0 + MOVEQ R4, #255 + LDRNE R4, ulMaxAPIPriorityMaskConst + LDRNE R4, [R4] + STR R4, [R2] + + /* Restore all system mode registers other than the SP (which is already + being used). */ + POP {R0-R12, R14} + + /* Return to the task code, loading CPSR on the way. */ + RFEIA sp! + + .endm + + + + +/****************************************************************************** + * SVC handler is used to start the scheduler. + *****************************************************************************/ +.align 4 +.type FreeRTOS_SWI_Handler, %function +FreeRTOS_SWI_Handler: + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + LDR R0, vTaskSwitchContextConst + BLX R0 + portRESTORE_CONTEXT + + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ +.type vPortRestoreTaskContext, %function +vPortRestoreTaskContext: + /* Switch to system mode. */ + CPS #SYS_MODE + portRESTORE_CONTEXT + +.align 4 +.type FreeRTOS_IRQ_Handler, %function +FreeRTOS_IRQ_Handler: + /* Return to the interrupted instruction. */ + SUB lr, lr, #4 + + /* Push the return address and SPSR. */ + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + /* Change to supervisor mode to allow reentry. */ + CPS #SVC_MODE + + /* Push used registers. */ + PUSH {r0-r4, r12} + + /* Increment nesting count. r3 holds the address of ulPortInterruptNesting + for future use. r1 holds the original ulPortInterruptNesting value for + future use. */ + LDR r3, ulPortInterruptNestingConst + LDR r1, [r3] + ADD r4, r1, #1 + STR r4, [r3] + + /* Read value from the interrupt acknowledge register, which is stored in r0 + for future parameter and interrupt clearing use. */ + LDR r2, ulICCIARConst + LDR r2, [r2] + LDR r0, [r2] + + /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + future use. _RB_ Does this ever actually need to be done provided the start + of the stack is 8-byte aligned? */ + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + /* Call the interrupt handler. r4 pushed to maintain alignment. */ + PUSH {r0-r4, lr} + LDR r1, vApplicationIRQHandlerConst + BLX r1 + POP {r0-r4, lr} + ADD sp, sp, r2 + + CPSID i + DSB + ISB + + /* Write the value read from ICCIAR to ICCEOIR. */ + LDR r4, ulICCEOIRConst + LDR r4, [r4] + STR r0, [r4] + + /* Restore the old nesting count. */ + STR r1, [r3] + + /* A context switch is never performed if the nesting count is not 0. */ + CMP r1, #0 + BNE exit_without_switch + + /* Did the interrupt request a context switch? r1 holds the address of + ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + use. */ + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch: + /* No context switch. Restore used registers, LR_irq and SPSR before + returning. */ + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit: + /* A context swtich is to be performed. Clear the context switch pending + flag. */ + MOV r0, #0 + STR r0, [r1] + + /* Restore used registers, LR-irq and SPSR before saving the context + to the task stack. */ + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + /* Call the function that selects the new task to execute. + vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + instructions, or 8 byte aligned stack allocated data. LR does not need + saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */ + LDR R0, vTaskSwitchContextConst + BLX R0 + + /* Restore the context of, and branch to, the task selected to execute + next. */ + portRESTORE_CONTEXT + + +/****************************************************************************** + * If the application provides an implementation of vApplicationIRQHandler(), + * then it will get called directly without saving the FPU registers on + * interrupt entry, and this weak implementation of + * vApplicationIRQHandler() will not get called. + * + * If the application provides its own implementation of + * vApplicationFPUSafeIRQHandler() then this implementation of + * vApplicationIRQHandler() will be called, save the FPU registers, and then + * call vApplicationFPUSafeIRQHandler(). + * + * Therefore, if the application writer wants FPU registers to be saved on + * interrupt entry their IRQ handler must be called + * vApplicationFPUSafeIRQHandler(), and if the application writer does not want + * FPU registers to be saved on interrupt entry their IRQ handler must be + * called vApplicationIRQHandler(). + *****************************************************************************/ + +.align 4 +.weak vApplicationIRQHandler +.type vApplicationIRQHandler, %function +vApplicationIRQHandler: + PUSH {LR} + FMRX R1, FPSCR + VPUSH {D0-D15} + VPUSH {D16-D31} + PUSH {R1} + + LDR r1, vApplicationFPUSafeIRQHandlerConst + BLX r1 + + POP {R0} + VPOP {D16-D31} + VPOP {D0-D15} + VMSR FPSCR, R0 + + POP {PC} + + +ulICCIARConst: .word ulICCIAR +ulICCEOIRConst: .word ulICCEOIR +ulICCPMRConst: .word ulICCPMR +pxCurrentTCBConst: .word pxCurrentTCB +ulCriticalNestingConst: .word ulCriticalNesting +ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext +ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask +vTaskSwitchContextConst: .word vTaskSwitchContext +vApplicationIRQHandlerConst: .word vApplicationIRQHandler +ulPortInterruptNestingConst: .word ulPortInterruptNesting +vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler + +.end + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA9/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA9/portmacro.h new file mode 100644 index 0000000..4a6eb54 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CA9/portmacro.h @@ -0,0 +1,216 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +typedef uint32_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do +not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired )\ +{ \ +extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ +} + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" ); + + +/*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); +extern void vPortInstallFreeRTOSVectorTable( void ); + +/* These macros do not globally disable/enable interrupts. They do mask off +interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() +#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not required for this port but included in case common demo code that uses these +macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the +handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are +created without an FPU context and must call vPortTaskUsesFPU() to give +themselves an FPU context before using any FPU instructions. If +configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context +by default. */ +#if( configUSE_TASK_FPU_SUPPORT != 2 ) + void vPortTaskUsesFPU( void ); +#else + /* Each task has an FPU context already, so define this function away to + nothing to prevent it being called accidentally. */ + #define vPortTaskUsesFPU() +#endif +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* configASSERT */ + +#define portNOP() __asm volatile( "NOP" ) +#define portINLINE __inline + +#ifdef __cplusplus + } /* extern C */ +#endif + + +/* The number of bits to shift for an interrupt priority is dependent on the +number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif + +/* Interrupt controller access addresses. */ +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) + +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) + +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM0/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM0/port.c new file mode 100644 index 0000000..8524d0d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM0/port.c @@ -0,0 +1,633 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM0 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#ifndef portMISSED_COUNTS_FACTOR + #define portMISSED_COUNTS_FACTOR ( 94UL ) +#endif + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void vPortStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/*-----------------------------------------------------------*/ + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11..R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being defined + * but never called. ulDummy is used purely to quieten other warnings + * about code appearing after this function is called - making ulDummy + * volatile makes the compiler think the function could return and + * therefore not output an 'unreachable code' warning for code that appears + * after it. */ + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + /* This function is no longer used, but retained for backward + * compatibility. */ +} +/*-----------------------------------------------------------*/ + +void vPortStartFirstTask( void ) +{ + /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector + * table offset register that can be used to locate the initial stack value. + * Not all M0 parts have the application vector table at address 0. */ + __asm volatile ( + " .syntax unified \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Obtain location of pxCurrentTCB. */ + " ldr r3, [r2] \n" + " ldr r0, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " movs r0, #2 \n"/* Switch to the psp stack. */ + " msr CONTROL, r0 \n" + " isb \n" + " pop {r0-r5} \n"/* Pop the registers that are saved automatically. */ + " mov lr, r5 \n"/* lr is now in r5. */ + " pop {r3} \n"/* Return address is now in r3. */ + " pop {r2} \n"/* Pop and discard XPSR. */ + " cpsie i \n"/* The first task has its context and interrupts can be enabled. */ + " bx r3 \n"/* Finally, jump to the user defined task code. */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB " + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimisation does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is completely + * within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMaskFromISR( void ) +{ + __asm volatile ( + " mrs r0, PRIMASK \n" + " cpsid i \n" + " bx lr " + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) +{ + __asm volatile ( + " msr PRIMASK, r0 \n" + " bx lr " + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " .syntax unified \n" + " mrs r0, psp \n" + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " subs r0, r0, #32 \n"/* Make space for the remaining low registers. */ + " str r0, [r2] \n"/* Save the new top of stack. */ + " stmia r0!, {r4-r7} \n"/* Store the low registers that are not saved automatically. */ + " mov r4, r8 \n"/* Store the high registers. */ + " mov r5, r9 \n" + " mov r6, r10 \n" + " mov r7, r11 \n" + " stmia r0!, {r4-r7} \n" + " \n" + " push {r3, r14} \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " pop {r2, r3} \n"/* lr goes in r3. r2 now holds tcb pointer. */ + " \n" + " ldr r1, [r2] \n" + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, r0, #16 \n"/* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n"/* Pop the high registers. */ + " mov r8, r4 \n" + " mov r9, r5 \n" + " mov r10, r6 \n" + " mov r11, r7 \n" + " \n" + " msr psp, r0 \n"/* Remember the new top of stack for the task. */ + " \n" + " subs r0, r0, #32 \n"/* Go back for the low registers that are not automatically restored. */ + " ldmia r0!, {r4-r7} \n"/* Pop low registers. */ + " \n" + " bx r3 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB " + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM0/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM0/portmacro.h new file mode 100644 index 0000000..860196b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM0/portmacro.h @@ -0,0 +1,125 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + extern void vPortYield( void ); + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portYIELD() vPortYield() + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) ); + extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__( ( naked ) ); + + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x ) + #define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) + #define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + + #define portNOP() + + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/portasm.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/portasm.c new file mode 100644 index 0000000..74e7b9e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/portasm.c @@ -0,0 +1,478 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif + +void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " movs r5, #1 \n"/* r5 = 1. */ + " bics r4, r5 \n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */ + " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + " movs r5, #4 \n"/* r5 = 4. */ + " str r5, [r2] \n"/* Program RNR = 4. */ + " ldmia r3!, {r6,r7} \n"/* Read first set of RBAR/RLAR from TCB. */ + " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */ + " stmia r4!, {r6,r7} \n"/* Write first set of RBAR/RLAR registers. */ + " movs r5, #5 \n"/* r5 = 5. */ + " str r5, [r2] \n"/* Program RNR = 5. */ + " ldmia r3!, {r6,r7} \n"/* Read second set of RBAR/RLAR from TCB. */ + " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */ + " stmia r4!, {r6,r7} \n"/* Write second set of RBAR/RLAR registers. */ + " movs r5, #6 \n"/* r5 = 6. */ + " str r5, [r2] \n"/* Program RNR = 6. */ + " ldmia r3!, {r6,r7} \n"/* Read third set of RBAR/RLAR from TCB. */ + " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */ + " stmia r4!, {r6,r7} \n"/* Write third set of RBAR/RLAR registers. */ + " movs r5, #7 \n"/* r5 = 7. */ + " str r5, [r2] \n"/* Program RNR = 7. */ + " ldmia r3!, {r6,r7} \n"/* Read fourth set of RBAR/RLAR from TCB. */ + " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */ + " stmia r4!, {r6,r7} \n"/* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " movs r5, #1 \n"/* r5 = 1. */ + " orrs r4, r5 \n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + " ldr r5, xSecureContextConst2 \n" + " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n"/* Set this task's PSPLIM value. */ + " msr control, r3 \n"/* Set this task's CONTROL value. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " bx r4 \n"/* Finally, branch to EXC_RETURN. */ + #else /* configENABLE_MPU */ + " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, xSecureContextConst2 \n" + " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n"/* Set this task's PSPLIM value. */ + " movs r1, #2 \n"/* r1 = 2. */ + " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " bx r3 \n"/* Finally, branch to EXC_RETURN. */ + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + "xSecureContextConst2: .word xSecureContext \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst2: .word 0xe000ed94 \n" + "xMAIR0Const2: .word 0xe000edc0 \n" + "xRNRConst2: .word 0xe000ed98 \n" + "xRBARConst2: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " movs r1, #1 \n"/* r1 = 1. */ + " tst r0, r1 \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + " beq running_privileged \n"/* If the result of previous AND operation was 0, branch. */ + " movs r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " bx lr \n"/* Return. */ + " running_privileged: \n" + " movs r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* Read the CONTROL register. */ + " movs r1, #1 \n"/* r1 = 1. */ + " bics r0, r1 \n"/* Clear the bit 0. */ + " msr control, r0 \n"/* Write back the new CONTROL value. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " movs r1, #1 \n"/* r1 = 1. */ + " orrs r0, r1 \n"/* r0 = r0 | r1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + "xVTORConst: .word 0xe000ed08 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, PRIMASK \n" + " cpsid i \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr PRIMASK, r0 \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/ + " mrs r2, psp \n"/* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n"/* No secure context to save. */ + " push {r0-r2, r14} \n" + " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r3} \n"/* LR is now in r3. */ + " mov lr, r3 \n"/* LR = r3. */ + " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + #if ( configENABLE_MPU == 1 ) + " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r3, control \n"/* r3 = CONTROL. */ + " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + " b select_next_task \n" + " \n" + " save_ns_context: \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + #if ( configENABLE_MPU == 1 ) + " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " adds r2, r2, #16 \n"/* r2 = r2 + 16. */ + " stmia r2!, {r4-r7} \n"/* Store the low registers that are not saved automatically. */ + " mov r4, r8 \n"/* r4 = r8. */ + " mov r5, r9 \n"/* r5 = r9. */ + " mov r6, r10 \n"/* r6 = r10. */ + " mov r7, r11 \n"/* r7 = r11. */ + " stmia r2!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r3, control \n"/* r3 = CONTROL. */ + " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */ + " subs r2, r2, #48 \n"/* r2 = r2 - 48. */ + " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3-r7} \n"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ + " mov r4, r8 \n"/* r4 = r8. */ + " mov r5, r9 \n"/* r5 = r9. */ + " mov r6, r10 \n"/* r6 = r10. */ + " mov r7, r11 \n"/* r7 = r11. */ + " stmia r2!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */ + #endif /* configENABLE_MPU */ + " \n" + " select_next_task: \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */ + " movs r5, #1 \n"/* r5 = 1. */ + " bics r4, r5 \n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */ + " str r4, [r3] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */ + " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r3] \n"/* Program MAIR0. */ + " ldr r4, xRNRConst \n"/* r4 = 0xe000ed98 [Location of RNR]. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " movs r5, #4 \n"/* r5 = 4. */ + " str r5, [r4] \n"/* Program RNR = 4. */ + " ldmia r1!, {r6,r7} \n"/* Read first set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r6,r7} \n"/* Write first set of RBAR/RLAR registers. */ + " movs r5, #5 \n"/* r5 = 5. */ + " str r5, [r4] \n"/* Program RNR = 5. */ + " ldmia r1!, {r6,r7} \n"/* Read second set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r6,r7} \n"/* Write second set of RBAR/RLAR registers. */ + " movs r5, #6 \n"/* r5 = 6. */ + " str r5, [r4] \n"/* Program RNR = 6. */ + " ldmia r1!, {r6,r7} \n"/* Read third set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r6,r7} \n"/* Write third set of RBAR/RLAR registers. */ + " movs r5, #7 \n"/* r5 = 7. */ + " str r5, [r4] \n"/* Program RNR = 7. */ + " ldmia r1!, {r6,r7} \n"/* Read fourth set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r6,r7} \n"/* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */ + " movs r5, #1 \n"/* r5 = 1. */ + " orrs r4, r5 \n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */ + " str r4, [r3] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " msr control, r3 \n"/* Restore the CONTROL register value for the task. */ + " mov lr, r4 \n"/* LR = r4. */ + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n"/* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n"/* LR = r4. */ + " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + #else /* configENABLE_MPU */ + " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " mov lr, r4 \n"/* LR = r4. */ + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n"/* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n"/* LR = r4. */ + " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + #endif /* configENABLE_MPU */ + " \n" + " restore_ns_context: \n" + " adds r2, r2, #16 \n"/* Move to the high registers. */ + " ldmia r2!, {r4-r7} \n"/* Restore the high registers that are not automatically restored. */ + " mov r8, r4 \n"/* r8 = r4. */ + " mov r9, r5 \n"/* r9 = r5. */ + " mov r10, r6 \n"/* r10 = r6. */ + " mov r11, r7 \n"/* r11 = r7. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " subs r2, r2, #32 \n"/* Go back to the low registers. */ + " ldmia r2!, {r4-r7} \n"/* Restore the low registers that are not automatically restored. */ + " bx lr \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + "xSecureContextConst: .word xSecureContext \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst: .word 0xe000ed94 \n" + "xMAIR0Const: .word 0xe000edc0 \n" + "xRNRConst: .word 0xe000ed98 \n" + "xRBARConst: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " movs r0, #4 \n" + " mov r1, lr \n" + " tst r0, r1 \n" + " beq stacking_used_msp \n" + " mrs r0, psp \n" + " ldr r2, svchandler_address_const \n" + " bx r2 \n" + " stacking_used_msp: \n" + " mrs r0, msp \n" + " ldr r2, svchandler_address_const \n" + " bx r2 \n" + " \n" + " .align 4 \n" + "svchandler_address_const: .word vPortSVCHandler_C \n" + ); +} +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n"/* Secure context is allocated in the supervisor call. */ + " bx lr \n"/* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */ + " bne free_secure_context \n"/* Branch if r1 != 0. */ + " bx lr \n"/* There is no secure context (xSecureContext is NULL). */ + " free_secure_context: \n" + " svc %0 \n"/* Secure context is freed in the supervisor call. */ + " bx lr \n"/* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/portasm.h new file mode 100644 index 0000000..d2152e1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/portmacro.h new file mode 100644 index 0000000..7cca20a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/portmacro.h @@ -0,0 +1,71 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h new file mode 100644 index 0000000..26aa668 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_context.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_context.c new file mode 100644 index 0000000..a63d59e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_context.c @@ -0,0 +1,351 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Ontain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_context.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_context.h new file mode 100644 index 0000000..ba883ed --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_context.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_context_port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_context_port.c new file mode 100644 index 0000000..2d8b2af --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_context_port.c @@ -0,0 +1,99 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " subs r1, r1, #4 \n" /* Make space for the CONTROL value on the stack. */ + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " stmia r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #else /* configENABLE_MPU */ + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + #endif /* configENABLE_MPU */ + " \n" + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_heap.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_heap.c new file mode 100644 index 0000000..19a7fae --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_heap.c @@ -0,0 +1,451 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart, * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/** + * @brief Gets set to the top bit of an size_t type. + * + * When this bit in the xBlockSize member of an BlockLink_t structure is set + * then the block belongs to the application. When the bit is free the block is + * still part of the free heap space. + */ +static size_t xBlockAllocatedBit = 0; +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink; + void * pvReturn = NULL; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size is increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number of + * bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); + secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_heap.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_heap.h new file mode 100644 index 0000000..0009003 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_init.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_init.c new file mode 100644 index 0000000..a21ea1c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_init.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_init.h new file mode 100644 index 0000000..2a0352c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_port_macros.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_port_macros.h new file mode 100644 index 0000000..d8ab67a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c new file mode 100644 index 0000000..2a81873 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c @@ -0,0 +1,381 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif + +void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " movs r4, #1 \n"/* r4 = 1. */ + " bics r3, r4 \n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */ + " str r3, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */ + " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " movs r4, #4 \n"/* r4 = 4. */ + " str r4, [r2] \n"/* Program RNR = 4. */ + " ldmia r1!, {r5,r6} \n"/* Read first set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write first set of RBAR/RLAR registers. */ + " movs r4, #5 \n"/* r4 = 5. */ + " str r4, [r2] \n"/* Program RNR = 5. */ + " ldmia r1!, {r5,r6} \n"/* Read second set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write second set of RBAR/RLAR registers. */ + " movs r4, #6 \n"/* r4 = 6. */ + " str r4, [r2] \n"/* Program RNR = 6. */ + " ldmia r1!, {r5,r6} \n"/* Read third set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write third set of RBAR/RLAR registers. */ + " movs r4, #7 \n"/* r4 = 7. */ + " str r4, [r2] \n"/* Program RNR = 7. */ + " ldmia r1!, {r5,r6} \n"/* Read fourth set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " movs r4, #1 \n"/* r4 = 1. */ + " orrs r3, r4 \n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */ + " str r3, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " msr control, r2 \n"/* Set this task's CONTROL value. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " bx r3 \n"/* Finally, branch to EXC_RETURN. */ + #else /* configENABLE_MPU */ + " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " movs r1, #2 \n"/* r1 = 2. */ + " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " bx r2 \n"/* Finally, branch to EXC_RETURN. */ + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst2: .word 0xe000ed94 \n" + "xMAIR0Const2: .word 0xe000edc0 \n" + "xRNRConst2: .word 0xe000ed98 \n" + "xRBARConst2: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " movs r1, #1 \n"/* r1 = 1. */ + " tst r0, r1 \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + " beq running_privileged \n"/* If the result of previous AND operation was 0, branch. */ + " movs r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " bx lr \n"/* Return. */ + " running_privileged: \n" + " movs r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* Read the CONTROL register. */ + " movs r1, #1 \n"/* r1 = 1. */ + " bics r0, r1 \n"/* Clear the bit 0. */ + " msr control, r0 \n"/* Write back the new CONTROL value. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " movs r1, #1 \n"/* r1 = 1. */ + " orrs r0, r1 \n"/* r0 = r0 | r1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + "xVTORConst: .word 0xe000ed08 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, PRIMASK \n" + " cpsid i \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr PRIMASK, r0 \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n"/* Read PSP in r0. */ + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + #if ( configENABLE_MPU == 1 ) + " subs r0, r0, #44 \n"/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + " str r0, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r2, control \n"/* r2 = CONTROL. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmia r0!, {r1-r7} \n"/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */ + " mov r4, r8 \n"/* r4 = r8. */ + " mov r5, r9 \n"/* r5 = r9. */ + " mov r6, r10 \n"/* r6 = r10. */ + " mov r7, r11 \n"/* r7 = r11. */ + " stmia r0!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */ + #else /* configENABLE_MPU */ + " subs r0, r0, #40 \n"/* Make space for PSPLIM, LR and the remaining registers on the stack. */ + " str r0, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r2, psplim \n"/* r2 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmia r0!, {r2-r7} \n"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ + " mov r4, r8 \n"/* r4 = r8. */ + " mov r5, r9 \n"/* r5 = r9. */ + " mov r6, r10 \n"/* r6 = r10. */ + " mov r7, r11 \n"/* r7 = r11. */ + " stmia r0!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */ + #endif /* configENABLE_MPU */ + " \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " movs r4, #1 \n"/* r4 = 1. */ + " bics r3, r4 \n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */ + " str r3, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */ + " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " movs r4, #4 \n"/* r4 = 4. */ + " str r4, [r2] \n"/* Program RNR = 4. */ + " ldmia r1!, {r5,r6} \n"/* Read first set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write first set of RBAR/RLAR registers. */ + " movs r4, #5 \n"/* r4 = 5. */ + " str r4, [r2] \n"/* Program RNR = 5. */ + " ldmia r1!, {r5,r6} \n"/* Read second set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write second set of RBAR/RLAR registers. */ + " movs r4, #6 \n"/* r4 = 6. */ + " str r4, [r2] \n"/* Program RNR = 6. */ + " ldmia r1!, {r5,r6} \n"/* Read third set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write third set of RBAR/RLAR registers. */ + " movs r4, #7 \n"/* r4 = 7. */ + " str r4, [r2] \n"/* Program RNR = 7. */ + " ldmia r1!, {r5,r6} \n"/* Read fourth set of RBAR/RLAR from TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " stmia r3!, {r5,r6} \n"/* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " movs r4, #1 \n"/* r4 = 1. */ + " orrs r3, r4 \n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */ + " str r3, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " adds r0, r0, #28 \n"/* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n"/* Restore the high registers that are not automatically restored. */ + " mov r8, r4 \n"/* r8 = r4. */ + " mov r9, r5 \n"/* r9 = r5. */ + " mov r10, r6 \n"/* r10 = r6. */ + " mov r11, r7 \n"/* r11 = r7. */ + " msr psp, r0 \n"/* Remember the new top of stack for the task. */ + " subs r0, r0, #44 \n"/* Move to the starting of the saved context. */ + " ldmia r0!, {r1-r7} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " msr control, r2 \n"/* Restore the CONTROL register value for the task. */ + " bx r3 \n" + #else /* configENABLE_MPU */ + " adds r0, r0, #24 \n"/* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n"/* Restore the high registers that are not automatically restored. */ + " mov r8, r4 \n"/* r8 = r4. */ + " mov r9, r5 \n"/* r9 = r5. */ + " mov r10, r6 \n"/* r10 = r6. */ + " mov r11, r7 \n"/* r11 = r7. */ + " msr psp, r0 \n"/* Remember the new top of stack for the task. */ + " subs r0, r0, #40 \n"/* Move to the starting of the saved context. */ + " ldmia r0!, {r2-r7} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ + " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */ + " bx r3 \n" + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst: .word 0xe000ed94 \n" + "xMAIR0Const: .word 0xe000edc0 \n" + "xRNRConst: .word 0xe000ed98 \n" + "xRBARConst: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " movs r0, #4 \n" + " mov r1, lr \n" + " tst r0, r1 \n" + " beq stacking_used_msp \n" + " mrs r0, psp \n" + " ldr r2, svchandler_address_const \n" + " bx r2 \n" + " stacking_used_msp: \n" + " mrs r0, msp \n" + " ldr r2, svchandler_address_const \n" + " bx r2 \n" + " \n" + " .align 4 \n" + "svchandler_address_const: .word vPortSVCHandler_C \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h new file mode 100644 index 0000000..d2152e1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h new file mode 100644 index 0000000..7cca20a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h @@ -0,0 +1,71 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 0000000..26aa668 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM3/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM3/port.c new file mode 100644 index 0000000..f3fb138 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM3/port.c @@ -0,0 +1,707 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM3 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is + * defined. The value should also ensure backward compatibility. + * FreeRTOS.org versions prior to V4.4.0 did not include this definition. */ +#ifndef configKERNEL_INTERRUPT_PRIORITY + #define configKERNEL_INTERRUPT_PRIORITY 255 +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000UL ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ) __attribute__( ( naked ) ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being defined + * but never called. ulDummy is used purely to quieten other warnings + * about code appearing after this function is called - making ulDummy + * volatile makes the compiler think the function could return and + * therefore not output an 'unreachable code' warning for code that appears + * after it. */ + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + __asm volatile ( + " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ + " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n"/* Restore the task stack pointer. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " orr r14, #0xd \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask( void ) +{ + __asm volatile ( + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc 0 \n"/* System call to start first task. */ + " nop \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimisation does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " mrs r0, psp \n" + " isb \n" + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " stmdb r0!, {r4-r11} \n"/* Save the remaining registers. */ + " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */ + " \n" + " stmdb sp!, {r3, r14} \n" + " mov r0, %0 \n" + " msr basepri, r0 \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " ldmia sp!, {r3, r14} \n" + " \n"/* Restore the context, including the critical nesting count. */ + " ldr r1, [r3] \n" + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11} \n"/* Pop the registers. */ + " msr psp, r0 \n" + " isb \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM3/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM3/portmacro.h new file mode 100644 index 0000000..cbde6db --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM3/portmacro.h @@ -0,0 +1,247 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ + } + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() + #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + #define portINLINE __inline + + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) + { + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static void vPortRaiseBASEPRI( void ) + { + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n"\ + " msr basepri, %0 \n"\ + " isb \n"\ + " dsb \n"\ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + } + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) + { + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n"\ + " mov %1, %2 \n"\ + " msr basepri, %1 \n"\ + " isb \n"\ + " dsb \n"\ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; + } +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) + { + __asm volatile + ( + " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/port.c new file mode 100644 index 0000000..349aeff --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/port.c @@ -0,0 +1,1261 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portasm.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portasm.c new file mode 100644 index 0000000..df117af --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portasm.c @@ -0,0 +1,470 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */ + " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #4 \n"/* r4 = 4. */ + " str r4, [r2] \n"/* Program RNR = 4. */ + " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #8 \n"/* r4 = 8. */ + " str r4, [r2] \n"/* Program RNR = 8. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #12 \n"/* r4 = 12. */ + " str r4, [r2] \n"/* Program RNR = 12. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + " ldr r5, xSecureContextConst2 \n" + " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n"/* Set this task's PSPLIM value. */ + " msr control, r3 \n"/* Set this task's CONTROL value. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r4 \n"/* Finally, branch to EXC_RETURN. */ + #else /* configENABLE_MPU */ + " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, xSecureContextConst2 \n" + " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n"/* Set this task's PSPLIM value. */ + " movs r1, #2 \n"/* r1 = 2. */ + " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n"/* Finally, branch to EXC_RETURN. */ + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + "xSecureContextConst2: .word xSecureContext \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst2: .word 0xe000ed94 \n" + "xMAIR0Const2: .word 0xe000edc0 \n" + "xRNRConst2: .word 0xe000ed98 \n" + "xRBARConst2: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* Read the CONTROL register. */ + " bic r0, #1 \n"/* Clear the bit 0. */ + " msr control, r0 \n"/* Write back the new CONTROL value. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " orr r0, #1 \n"/* r0 = r0 | 1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + "xVTORConst: .word 0xe000ed08 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n"/* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " mrs r2, psp \n"/* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n"/* No secure context to save. */ + " push {r0-r2, r14} \n" + " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r3} \n"/* LR is now in r3. */ + " mov lr, r3 \n"/* LR = r3. */ + " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB.*/ + #if ( configENABLE_MPU == 1 ) + " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r3, control \n"/* r3 = CONTROL. */ + " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + " b select_next_task \n" + " \n" + " save_ns_context: \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( configENABLE_MPU == 1 ) + " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " adds r2, r2, #16 \n"/* r2 = r2 + 16. */ + " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r3, control \n"/* r3 = CONTROL. */ + " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */ + " subs r2, r2, #16 \n"/* r2 = r2 - 16. */ + " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " adds r2, r2, #12 \n"/* r2 = r2 + 12. */ + " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " subs r2, r2, #12 \n"/* r2 = r2 - 12. */ + " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n"/* r0 = 0. */ + " msr basepri, r0 \n"/* Enable interrupts. */ + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r3] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */ + " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r3] \n"/* Program MAIR0. */ + " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #4 \n"/* r4 = 4. */ + " str r4, [r3] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #8 \n"/* r4 = 8. */ + " str r4, [r3] \n"/* Program RNR = 8. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #12 \n"/* r4 = 12. */ + " str r4, [r3] \n"/* Program RNR = 12. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r3] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " msr control, r3 \n"/* Restore the CONTROL register value for the task. */ + " mov lr, r4 \n"/* LR = r4. */ + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n"/* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n"/* LR = r4. */ + " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + #else /* configENABLE_MPU */ + " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " mov lr, r4 \n"/* LR = r4. */ + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n"/* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n"/* LR = r4. */ + " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + #endif /* configENABLE_MPU */ + " \n" + " restore_ns_context: \n" + " ldmia r2!, {r4-r11} \n"/* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + "xSecureContextConst: .word xSecureContext \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst: .word 0xe000ed94 \n" + "xMAIR0Const: .word 0xe000edc0 \n" + "xRNRConst: .word 0xe000ed98 \n" + "xRBARConst: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, svchandler_address_const \n" + " bx r1 \n" + " \n" + " .align 4 \n" + "svchandler_address_const: .word vPortSVCHandler_C \n" + ); +} +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n"/* Secure context is allocated in the supervisor call. */ + " bx lr \n"/* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */ + " it ne \n" + " svcne %0 \n"/* Secure context is freed in the supervisor call. */ + " bx lr \n"/* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portasm.h new file mode 100644 index 0000000..c3b2f2c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portmacro.h new file mode 100644 index 0000000..1f3d964 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portmacro.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h new file mode 100644 index 0000000..e68692a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_context.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_context.c new file mode 100644 index 0000000..ffb4f87 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_context.c @@ -0,0 +1,351 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Ontain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_context.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_context.h new file mode 100644 index 0000000..68efd7c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_context.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_context_port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_context_port.c new file mode 100644 index 0000000..f35fae0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_context_port.c @@ -0,0 +1,97 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */ + " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_heap.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_heap.c new file mode 100644 index 0000000..fa42ee3 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_heap.c @@ -0,0 +1,454 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/** + * @brief Gets set to the top bit of an size_t type. + * + * When this bit in the xBlockSize member of an BlockLink_t structure is set + * then the block belongs to the application. When the bit is free the block is + * still part of the free heap space. + */ +static size_t xBlockAllocatedBit = 0; +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size is increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number of + * bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); + secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_heap.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_heap.h new file mode 100644 index 0000000..2689c49 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_init.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_init.c new file mode 100644 index 0000000..585adfe --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_init.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_init.h new file mode 100644 index 0000000..fc000cf --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_port_macros.h new file mode 100644 index 0000000..1ca265d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c new file mode 100644 index 0000000..349aeff --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c @@ -0,0 +1,1261 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c new file mode 100644 index 0000000..660e942 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c @@ -0,0 +1,365 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */ + " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r3, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #4 \n"/* r3 = 4. */ + " str r3, [r2] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #8 \n"/* r3 = 8. */ + " str r3, [r2] \n"/* Program RNR = 8. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #12 \n"/* r3 = 12. */ + " str r3, [r2] \n"/* Program RNR = 12. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " msr control, r2 \n"/* Set this task's CONTROL value. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n"/* Finally, branch to EXC_RETURN. */ + #else /* configENABLE_MPU */ + " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " movs r1, #2 \n"/* r1 = 2. */ + " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r2 \n"/* Finally, branch to EXC_RETURN. */ + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst2: .word 0xe000ed94 \n" + "xMAIR0Const2: .word 0xe000edc0 \n" + "xRNRConst2: .word 0xe000ed98 \n" + "xRBARConst2: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* Read the CONTROL register. */ + " bic r0, #1 \n"/* Clear the bit 0. */ + " msr control, r0 \n"/* Write back the new CONTROL value. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " orr r0, #1 \n"/* r0 = r0 | 1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + "xVTORConst: .word 0xe000ed08 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n"/* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n"/* Read PSP in r0. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( configENABLE_MPU == 1 ) + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r2, control \n"/* r2 = CONTROL. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r1-r11} \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */ + #else /* configENABLE_MPU */ + " mrs r2, psplim \n"/* r2 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r2-r11} \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */ + #endif /* configENABLE_MPU */ + " \n" + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " str r0, [r1] \n"/* Save the new top of stack in TCB. */ + " \n" + " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n"/* r0 = 0. */ + " msr basepri, r0 \n"/* Enable interrupts. */ + " \n" + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */ + " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r3, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #4 \n"/* r3 = 4. */ + " str r3, [r2] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #8 \n"/* r3 = 8. */ + " str r3, [r2] \n"/* Program RNR = 8. */ + " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #12 \n"/* r3 = 12. */ + " str r3, [r2] \n"/* Program RNR = 12. */ + " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r0!, {r1-r11} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */ + #else /* configENABLE_MPU */ + " ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " msr control, r2 \n"/* Restore the CONTROL register value for the task. */ + #else /* configENABLE_MPU */ + " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */ + #endif /* configENABLE_MPU */ + " msr psp, r0 \n"/* Remember the new top of stack for the task. */ + " bx r3 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst: .word 0xe000ed94 \n" + "xMAIR0Const: .word 0xe000edc0 \n" + "xRNRConst: .word 0xe000ed98 \n" + "xRBARConst: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, svchandler_address_const \n" + " bx r1 \n" + " \n" + " .align 4 \n" + "svchandler_address_const: .word vPortSVCHandler_C \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h new file mode 100644 index 0000000..c3b2f2c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h new file mode 100644 index 0000000..1f3d964 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 0000000..e68692a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM3_MPU/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM3_MPU/port.c new file mode 100644 index 0000000..f6077ff --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM3_MPU/port.c @@ -0,0 +1,921 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM3 MPU port. +*----------------------------------------------------------*/ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK ( 0 ) +#endif + +#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS + #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security." + #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1 +#endif + +/* Constants required to access and manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL ) + +/* Constants required to access and manipulate the MPU. */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) ) +#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */ +#define portMPU_ENABLE ( 0x01UL ) +#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) +#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) +#define portMPU_REGION_VALID ( 0x10UL ) +#define portMPU_REGION_ENABLE ( 0x01UL ) +#define portPERIPHERALS_START_ADDRESS 0x40000000UL +#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL + +/* Constants required to access and manipulate the SysTick. */ +#define portNVIC_SYSTICK_INT ( 0x00000002UL ) +#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) +#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) +#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Offsets in the stack to the parameters when inside the SVC handler. */ +#define portOFFSET_TO_PC ( 6 ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) +/*-----------------------------------------------------------*/ + +/* + * Configure a number of standard MPU regions that are used by all tasks. + */ +static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; + +/* + * Return the smallest MPU region size that a given number of bytes will fit + * into. The region size is returned as the value that should be programmed + * into the region attribute register for that region. + */ +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION; + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Standard FreeRTOS exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; +void xPortSysTickHandler( void ) __attribute__( ( optimize( "3" ) ) ) PRIVILEGED_FUNCTION; +void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/* + * Starts the scheduler by restoring the context of the first task to run. + */ +static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/* + * C portion of the SVC handler. The SVC handler is split between an asm entry + * and a C wrapper for simplicity of coding and maintenance. + */ +static void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Enter critical section. + */ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * @brief Exit from critical section. + */ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortExitCritical( void ) PRIVILEGED_FUNCTION; +#endif +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. Note this is not saved as part of the task context as context + * switches can only occur when uxCriticalNesting is zero. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = 0; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED; + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED; + } + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + /* Assumes psp was in use. */ + __asm volatile + ( + #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + #else + " mrs r0, psp \n" + #endif + " b %0 \n" + ::"i" ( prvSVCHandler ) : "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +static void prvSVCHandler( uint32_t * pulParam ) +{ + uint8_t ucSVCNumber; + uint32_t ulPC; + + #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + + /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first + * argument (r0) is pulParam[ 0 ]. */ + ulPC = pulParam[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + case portSVC_START_SCHEDULER: + portNVIC_SHPR2_REG |= portNVIC_SVC_PRI; + prvRestoreContextOfFirstTask(); + break; + + case portSVC_YIELD: + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required + * but do ensure the code is completely + * within the specified behaviour for the + * architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); + + break; + + + #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) + case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the + * svc was raised from any of the + * system calls. */ + + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + __asm volatile + ( + " mrs r1, control \n"/* Obtain current control value. */ + " bic r1, #1 \n"/* Set privilege bit. */ + " msr control, r1 \n"/* Write back new control value. */ + ::: "r1", "memory" + ); + } + + break; + #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + case portSVC_RAISE_PRIVILEGE: + __asm volatile + ( + " mrs r1, control \n"/* Obtain current control value. */ + " bic r1, #1 \n"/* Set privilege bit. */ + " msr control, r1 \n"/* Write back new control value. */ + ::: "r1", "memory" + ); + break; + #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + + default: /* Unknown SVC call. */ + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvRestoreContextOfFirstTask( void ) +{ + __asm volatile + ( + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ + " ldr r1, [r3] \n" + " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */ + " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */ + " \n" + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + " str r3, [r2] \n"/* Disable MPU. */ + " \n" + " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers. */ + " stmia r2!, {r4-r11} \n"/* Write 4 sets of MPU registers. */ + " \n" + " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + " str r3, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + " \n" + " ldmia r0!, {r3, r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry. */ + " msr control, r3 \n" + " msr psp, r0 \n"/* Restore the task stack pointer. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" + " ldr r14, =0xfffffffd \n"/* Load exec return code. */ + " bx r14 \n" + " \n" + " .ltorg \n"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */ + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ); + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions + * to ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the same priority as the kernel, and the SVC + * handler higher priority so it can be used to exit a critical section (where + * lower priorities are masked). */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Configure the regions in the MPU that are common to all tasks. */ + prvSetupMPU(); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + __asm volatile ( + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start first task. */ + " nop \n" + " .ltorg \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" ); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + } +#else + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +#endif +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#else + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +#endif +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " mrs r0, psp \n" + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " mrs r1, control \n" + " stmdb r0!, {r1, r4-r11} \n"/* Save the remaining registers. */ + " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */ + " \n" + " stmdb sp!, {r3, r14} \n" + " mov r0, %0 \n" + " msr basepri, r0 \n" + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " ldmia sp!, {r3, r14} \n" + " \n"/* Restore the context. */ + " ldr r1, [r3] \n" + " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */ + " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */ + " \n" + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + " str r3, [r2] \n"/* Disable MPU. */ + " \n" + " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers. */ + " stmia r2!, {r4-r11} \n"/* Write 4 sets of MPU registers. */ + " \n" + " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + " str r3, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + " \n" + " ldmia r0!, {r3, r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry. */ + " msr control, r3 \n" + " \n" + " msr psp, r0 \n" + " bx r14 \n" + " \n" + " .ltorg \n"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */ + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + uint32_t ulDummy; + + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupMPU( void ) +{ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __FLASH_segment_start__[]; + extern uint32_t __FLASH_segment_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + + /* Check the expected MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* First setup the unprivileged flash for unprivileged read only access. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portUNPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged flash for privileged only access. This is where + * the kernel code is * placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged data RAM region. This is where the kernel data + * is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_RAM_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) | + ( portMPU_REGION_ENABLE ); + + /* By default allow everything to access the general peripherals. The + * system peripherals and registers are protected. */ + portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) | + ( portMPU_REGION_VALID ) | + ( portGENERAL_PERIPHERALS_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) | + ( portMPU_REGION_ENABLE ); + + /* Enable the memory fault exception. */ + portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE; + + /* Enable the MPU with the background region configured. */ + portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE ); + } +} +/*-----------------------------------------------------------*/ + +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) +{ + uint32_t ulRegionSize, ulReturnValue = 4; + + /* 32 is the smallest region size, 31 is the largest valid value for + * ulReturnValue. */ + for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) ) + { + if( ulActualSizeInBytes <= ulRegionSize ) + { + break; + } + else + { + ulReturnValue++; + } + } + + /* Shift the code by one before returning so it can be written directly + * into the the correct bit position of the attribute register. */ + return( ulReturnValue << 1UL ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " mrs r0, control \n"/* r0 = CONTROL. */ + " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " mrs r0, control \n"/* r0 = CONTROL. */ + " orr r0, #1 \n"/* r0 = r0 | 1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) +{ + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + int32_t lIndex; + uint32_t ul; + + if( xRegions == NULL ) + { + /* No MPU regions are specified so allow access to all RAM. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Invalidate user configurable regions. */ + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + } + } + else + { + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that the + * stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) pxBottomOfStack ) | + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( portMPU_REGION_ENABLE ); + } + + lIndex = 0; + + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) + { + /* Translate the generic region definition contained in + * xRegions into the CM3 specific MPU settings that are then + * stored in xMPUSettings. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = + ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | + ( portMPU_REGION_VALID ) | + ( ul - 1UL ); /* Region number. */ + + xMPUSettings->xRegion[ ul ].ulRegionAttribute = + ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | + ( xRegions[ lIndex ].ulParameters ) | + ( portMPU_REGION_ENABLE ); + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + } + + lIndex++; + } + } +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredicable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM3_MPU/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM3_MPU/portmacro.h new file mode 100644 index 0000000..9609754 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM3_MPU/portmacro.h @@ -0,0 +1,309 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* MPU specific constants. */ + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + + #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) + #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) + #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) + #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) + #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) + + #define portGENERAL_PERIPHERALS_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 5UL ) + #define portPRIVILEGED_FLASH_REGION ( 6UL ) + #define portPRIVILEGED_RAM_REGION ( 7UL ) + #define portFIRST_CONFIGURABLE_REGION ( 0UL ) + #define portLAST_CONFIGURABLE_REGION ( 2UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + + #define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" ) + + typedef struct MPU_REGION_REGISTERS + { + uint32_t ulRegionBaseAddress; + uint32_t ulRegionAttribute; + } xMPU_REGION_REGISTERS; + +/* Plus 1 to create space for the stack region. */ + typedef struct MPU_SETTINGS + { + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ]; + } xMPU_SETTINGS; + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* SVC numbers for various services. */ + #define portSVC_START_SCHEDULER 0 + #define portSVC_YIELD 1 + #define portSVC_RAISE_PRIVILEGE 2 + +/* Scheduler utilities. */ + + #define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ + } + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() + #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + #define portINLINE __inline + + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif +/*-----------------------------------------------------------*/ + + extern BaseType_t xIsPrivileged( void ); + extern void vResetPrivilege( void ); + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) + { + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static void vPortRaiseBASEPRI( void ) + { + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n"\ + " msr basepri, %0 \n"\ + " isb \n"\ + " dsb \n"\ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + } + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) + { + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n"\ + " mov %1, %2 \n"\ + " msr basepri, %1 \n"\ + " isb \n"\ + " dsb \n"\ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; + } +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) + { + __asm volatile + ( + " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + + #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html" + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 + #endif +/*-----------------------------------------------------------*/ + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4F/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4F/port.c new file mode 100644 index 0000000..e29d698 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4F/port.c @@ -0,0 +1,839 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __VFP_FP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 + * r0p1 port. */ +#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ) __attribute__( ( naked ) ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP( void ) __attribute__( ( naked ) ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being defined + * but never called. ulDummy is used purely to quieten other warnings + * about code appearing after this function is called - making ulDummy + * volatile makes the compiler think the function could return and + * therefore not output an 'unreachable code' warning for code that appears + * after it. */ + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + __asm volatile ( + " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ + " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n"/* Restore the task stack pointer. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask( void ) +{ + /* Start the first task. This also clears the bit that indicates the FPU is + * in use in case the FPU was used before the scheduler was started - which + * would otherwise result in the unnecessary leaving of space in the SVC stack + * for lazy saving of FPU registers. */ + __asm volatile ( + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */ + " msr control, r0 \n" + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc 0 \n"/* System call to start first task. */ + " nop \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* This port can be used on all revisions of the Cortex-M7 core other than + * the r0p1 parts. r0p1 parts should use the port from the + * /source/portable/GCC/ARM_CM7/r0p1 directory. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimisation does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " mrs r0, psp \n" + " isb \n" + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" + " \n" + " stmdb r0!, {r4-r11, r14} \n"/* Save the core registers. */ + " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */ + " \n" + " stmdb sp!, {r0, r3} \n" + " mov r0, %0 \n" + " msr basepri, r0 \n" + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " ldmia sp!, {r0, r3} \n" + " \n" + " ldr r1, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldr r0, [r1] \n" + " \n" + " ldmia r0!, {r4-r11, r14} \n"/* Pop the core registers. */ + " \n" + " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" + " \n" + " msr psp, r0 \n" + " isb \n" + " \n" + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */ + #if WORKAROUND_PMU_CM001 == 1 + " push { r14 } \n" + " pop { pc } \n" + #endif + #endif + " \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm volatile + ( + " ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */ + " ldr r1, [r0] \n" + " \n" + " orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */ + " str r1, [r0] \n" + " bx r14 \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4F/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4F/portmacro.h new file mode 100644 index 0000000..d92103a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4F/portmacro.h @@ -0,0 +1,245 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ + } + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() + #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + #define portINLINE __inline + + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + + portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) + { + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static void vPortRaiseBASEPRI( void ) + { + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n"\ + " msr basepri, %0 \n"\ + " isb \n"\ + " dsb \n"\ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + } + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) + { + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n"\ + " mov %1, %2 \n"\ + " msr basepri, %1 \n"\ + " isb \n"\ + " dsb \n"\ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; + } +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) + { + __asm volatile + ( + " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4_MPU/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4_MPU/port.c new file mode 100644 index 0000000..989c510 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4_MPU/port.c @@ -0,0 +1,1044 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4 MPU port. +*----------------------------------------------------------*/ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __VFP_FP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK ( 0 ) +#endif + +#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS + #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security." + #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1 +#endif + +/* Constants required to access and manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL ) + +/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure + * that a work around is active for errata 837070. */ +#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +/* Constants required to access and manipulate the MPU. */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) ) +#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portMPU_ENABLE ( 0x01UL ) +#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) +#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) +#define portMPU_REGION_VALID ( 0x10UL ) +#define portMPU_REGION_ENABLE ( 0x01UL ) +#define portPERIPHERALS_START_ADDRESS 0x40000000UL +#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL + +/* Constants required to access and manipulate the SysTick. */ +#define portNVIC_SYSTICK_INT ( 0x00000002UL ) +#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) +#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000UL ) +#define portINITIAL_EXC_RETURN ( 0xfffffffdUL ) +#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) +#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Offsets in the stack to the parameters when inside the SVC handler. */ +#define portOFFSET_TO_PC ( 6 ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* + * Configure a number of standard MPU regions that are used by all tasks. + */ +static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; + +/* + * Return the smallest MPU region size that a given number of bytes will fit + * into. The region size is returned as the value that should be programmed + * into the region attribute register for that region. + */ +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION; + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Standard FreeRTOS exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; +void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION; +void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/* + * Starts the scheduler by restoring the context of the first task to run. + */ +static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/* + * C portion of the SVC handler. The SVC handler is split between an asm entry + * and a C wrapper for simplicity of coding and maintenance. + */ +static void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION; + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP( void ) __attribute__( ( naked ) ); + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Enter critical section. + */ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * @brief Exit from critical section. + */ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortExitCritical( void ) PRIVILEGED_FUNCTION; +#endif +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. Note this is not saved as part of the task context as context + * switches can only occur when uxCriticalNesting is zero. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = 0; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED; + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED; + } + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + /* Assumes psp was in use. */ + __asm volatile + ( + #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + #else + " mrs r0, psp \n" + #endif + " b %0 \n" + ::"i" ( prvSVCHandler ) : "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +static void prvSVCHandler( uint32_t * pulParam ) +{ + uint8_t ucSVCNumber; + uint32_t ulPC; + + #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + + /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first + * argument (r0) is pulParam[ 0 ]. */ + ulPC = pulParam[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + case portSVC_START_SCHEDULER: + portNVIC_SHPR2_REG |= portNVIC_SVC_PRI; + prvRestoreContextOfFirstTask(); + break; + + case portSVC_YIELD: + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required + * but do ensure the code is completely + * within the specified behaviour for the + * architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); + + break; + + #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) + case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the + * svc was raised from any of the + * system calls. */ + + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + __asm volatile + ( + " mrs r1, control \n"/* Obtain current control value. */ + " bic r1, #1 \n"/* Set privilege bit. */ + " msr control, r1 \n"/* Write back new control value. */ + ::: "r1", "memory" + ); + } + + break; + #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + case portSVC_RAISE_PRIVILEGE: + __asm volatile + ( + " mrs r1, control \n"/* Obtain current control value. */ + " bic r1, #1 \n"/* Set privilege bit. */ + " msr control, r1 \n"/* Write back new control value. */ + ::: "r1", "memory" + ); + break; + #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + + default: /* Unknown SVC call. */ + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvRestoreContextOfFirstTask( void ) +{ + __asm volatile + ( + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ + " ldr r1, [r3] \n" + " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */ + " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */ + " \n" + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + " str r3, [r2] \n"/* Disable MPU. */ + " \n" + " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ + " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ + #endif /* configTOTAL_MPU_REGIONS == 16. */ + " \n" + " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + " str r3, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + " \n" + " ldmia r0!, {r3-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry. */ + " msr control, r3 \n" + " msr psp, r0 \n"/* Restore the task stack pointer. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" + " bx r14 \n" + " \n" + " .ltorg \n"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */ + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ); + + /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) ); + #else + /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define + * configENABLE_ERRATA_837070_WORKAROUND to 1 in your + * FreeRTOSConfig.h. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + #endif + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the same priority as the kernel, and the SVC + * handler higher priority so it can be used to exit a critical section (where + * lower priorities are masked). */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Configure the regions in the MPU that are common to all tasks. */ + prvSetupMPU(); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. This also clears the bit that indicates the FPU is + * in use in case the FPU was used before the scheduler was started - which + * would otherwise result in the unnecessary leaving of space in the SVC stack + * for lazy saving of FPU registers. */ + __asm volatile ( + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */ + " msr control, r0 \n" + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start first task. */ + " nop \n" + " .ltorg \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" ); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + } +#else + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +#endif +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#else + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +#endif +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " mrs r0, psp \n" + " isb \n" + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" + " \n" + " mrs r1, control \n" + " stmdb r0!, {r1, r4-r11, r14} \n"/* Save the remaining registers. */ + " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */ + " \n" + " stmdb sp!, {r0, r3} \n" + " mov r0, %0 \n" + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + " msr basepri, r0 \n" + " dsb \n" + " isb \n" + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " ldmia sp!, {r0, r3} \n" + " \n"/* Restore the context. */ + " ldr r1, [r3] \n" + " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */ + " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */ + " \n" + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + " str r3, [r2] \n"/* Disable MPU. */ + " \n" + " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ + " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ + #endif /* configTOTAL_MPU_REGIONS == 16. */ + " \n" + " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */ + " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + " str r3, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + " \n" + " ldmia r0!, {r3-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry. */ + " msr control, r3 \n" + " \n" + " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" + " \n" + " msr psp, r0 \n" + " bx r14 \n" + " \n" + " .ltorg \n"/* Assemble the current literal pool to avoid offset-out-of-bound errors with lto. */ + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + uint32_t ulDummy; + + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE ); +} +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm volatile + ( + " ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */ + " ldr r1, [r0] \n" + " \n" + " orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */ + " str r1, [r0] \n" + " bx r14 \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupMPU( void ) +{ + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __FLASH_segment_start__; + extern uint32_t * __FLASH_segment_end__; + extern uint32_t * __privileged_data_start__; + extern uint32_t * __privileged_data_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __FLASH_segment_start__[]; + extern uint32_t __FLASH_segment_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + #endif /* if defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check the expected MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* First setup the unprivileged flash for unprivileged read only access. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portUNPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) | + ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged flash for privileged only access. This is where + * the kernel code is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) | + ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged data RAM region. This is where the kernel data + * is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_RAM_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) | + ( portMPU_REGION_ENABLE ); + + /* By default allow everything to access the general peripherals. The + * system peripherals and registers are protected. */ + portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) | + ( portMPU_REGION_VALID ) | + ( portGENERAL_PERIPHERALS_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) | + ( portMPU_REGION_ENABLE ); + + /* Enable the memory fault exception. */ + portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE; + + /* Enable the MPU with the background region configured. */ + portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE ); + } +} +/*-----------------------------------------------------------*/ + +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) +{ + uint32_t ulRegionSize, ulReturnValue = 4; + + /* 32 is the smallest region size, 31 is the largest valid value for + * ulReturnValue. */ + for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) ) + { + if( ulActualSizeInBytes <= ulRegionSize ) + { + break; + } + else + { + ulReturnValue++; + } + } + + /* Shift the code by one before returning so it can be written directly + * into the the correct bit position of the attribute register. */ + return( ulReturnValue << 1UL ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " mrs r0, control \n"/* r0 = CONTROL. */ + " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " mrs r0, control \n"/* r0 = CONTROL. */ + " orr r0, #1 \n"/* r0 = r0 | 1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) +{ + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __SRAM_segment_start__; + extern uint32_t * __SRAM_segment_end__; + extern uint32_t * __privileged_data_start__; + extern uint32_t * __privileged_data_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + #endif /* if defined( __ARMCC_VERSION ) */ + + int32_t lIndex; + uint32_t ul; + + if( xRegions == NULL ) + { + /* No MPU regions are specified so allow access to all RAM. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Invalidate user configurable regions. */ + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + } + } + else + { + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that the + * stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) pxBottomOfStack ) | + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( portMPU_REGION_ENABLE ); + } + + lIndex = 0; + + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) + { + /* Translate the generic region definition contained in + * xRegions into the CM4 specific MPU settings that are then + * stored in xMPUSettings. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = + ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | + ( portMPU_REGION_VALID ) | + ( ul - 1UL ); /* Region number. */ + + xMPUSettings->xRegion[ ul ].ulRegionAttribute = + ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | + ( xRegions[ lIndex ].ulParameters ) | + ( portMPU_REGION_ENABLE ); + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + } + + lIndex++; + } + } +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredicable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4_MPU/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4_MPU/portmacro.h new file mode 100644 index 0000000..a9625ab --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4_MPU/portmacro.h @@ -0,0 +1,414 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif + +/*-----------------------------------------------------------*/ + +/* MPU specific constants. */ +#define portUSING_MPU_WRAPPERS 1 +#define portPRIVILEGE_BIT ( 0x80000000UL ) + +#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) +#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) +#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) +#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) + +/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size + * Register (RASR). */ +#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) +#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* + * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the + * memory type, and where necessary the cacheable and shareable properties + * of the memory region. + * + * The TEX, C, and B bits together indicate the memory type of the region, + * and: + * - For Normal memory, the cacheable properties of the region. + * - For Device memory, whether the region is shareable. + * + * For Normal memory regions, the S bit indicates whether the region is + * shareable. For Strongly-ordered and Device memory, the S bit is ignored. + * + * See the following two tables for setting TEX, S, C and B bits for + * unprivileged flash, privileged flash and privileged RAM regions. + * + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 1 | Device | Shared device | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 0 | Device | Non-shared device | Not shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 1 | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 011 | X | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved | + | | | | | outer cacheability rules that must be exported on the | | + | | | | | bus. See the table below for the cacheability policy | | + | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | + +-----------------------------------------+----------------------------------------+ + | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy | + +-----------------------------------------+----------------------------------------+ + | 00 | Non-cacheable | + +-----------------------------------------+----------------------------------------+ + | 01 | Write-back, write and read allocate | + +-----------------------------------------+----------------------------------------+ + | 10 | Write-through, no write allocate | + +-----------------------------------------+----------------------------------------+ + | 11 | Write-back, no write allocate | + +-----------------------------------------+----------------------------------------+ + */ + +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash + * region. */ +#ifndef configTEX_S_C_B_FLASH + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_FLASH ( 0x07UL ) +#endif + +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM + * region. */ +#ifndef configTEX_S_C_B_SRAM + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_SRAM ( 0x07UL ) +#endif + +#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL ) +#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL ) +#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL ) +#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL ) +#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portFIRST_CONFIGURABLE_REGION ( 0UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL ) +#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL ) +#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */ + +#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" ) + +typedef struct MPU_REGION_REGISTERS +{ + uint32_t ulRegionBaseAddress; + uint32_t ulRegionAttribute; +} xMPU_REGION_REGISTERS; + +typedef struct MPU_SETTINGS +{ + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ]; +} xMPU_SETTINGS; + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* SVC numbers for various services. */ +#define portSVC_START_SCHEDULER 0 +#define portSVC_YIELD 1 +#define portSVC_RAISE_PRIVILEGE 2 + +/* Scheduler utilities. */ + +#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" ) +#define portYIELD_WITHIN_API() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +/*-----------------------------------------------------------*/ + +extern BaseType_t xIsPrivileged( void ); +extern void vResetPrivilege( void ); + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +#define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + */ +#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ +#define portRESET_PRIVILEGE() vResetPrivilege() +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n" + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + " msr basepri, %0 \n" + " isb \n" + " dsb \n" + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n" + " mov %1, %2 \n" + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + " msr basepri, %1 \n" + " isb \n" + " dsb \n" + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; +} +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + ( + " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html" + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 +#endif +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ + #ifdef __cplusplus + } + #endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/portasm.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/portasm.c new file mode 100644 index 0000000..a8fe8a2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/portasm.c @@ -0,0 +1,470 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */ + " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #4 \n"/* r4 = 4. */ + " str r4, [r2] \n"/* Program RNR = 4. */ + " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #8 \n"/* r4 = 8. */ + " str r4, [r2] \n"/* Program RNR = 8. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #12 \n"/* r4 = 12. */ + " str r4, [r2] \n"/* Program RNR = 12. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + " ldr r5, xSecureContextConst2 \n" + " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n"/* Set this task's PSPLIM value. */ + " msr control, r3 \n"/* Set this task's CONTROL value. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r4 \n"/* Finally, branch to EXC_RETURN. */ + #else /* configENABLE_MPU */ + " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, xSecureContextConst2 \n" + " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n"/* Set this task's PSPLIM value. */ + " movs r1, #2 \n"/* r1 = 2. */ + " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n"/* Finally, branch to EXC_RETURN. */ + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + "xSecureContextConst2: .word xSecureContext \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst2: .word 0xe000ed94 \n" + "xMAIR0Const2: .word 0xe000edc0 \n" + "xRNRConst2: .word 0xe000ed98 \n" + "xRBARConst2: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* Read the CONTROL register. */ + " bic r0, #1 \n"/* Clear the bit 0. */ + " msr control, r0 \n"/* Write back the new CONTROL value. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " orr r0, #1 \n"/* r0 = r0 | 1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + "xVTORConst: .word 0xe000ed08 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n"/* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " mrs r2, psp \n"/* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n"/* No secure context to save. */ + " push {r0-r2, r14} \n" + " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r3} \n"/* LR is now in r3. */ + " mov lr, r3 \n"/* LR = r3. */ + " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB.*/ + #if ( configENABLE_MPU == 1 ) + " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r3, control \n"/* r3 = CONTROL. */ + " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + " b select_next_task \n" + " \n" + " save_ns_context: \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( configENABLE_MPU == 1 ) + " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " adds r2, r2, #16 \n"/* r2 = r2 + 16. */ + " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r3, control \n"/* r3 = CONTROL. */ + " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */ + " subs r2, r2, #16 \n"/* r2 = r2 - 16. */ + " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " adds r2, r2, #12 \n"/* r2 = r2 + 12. */ + " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " subs r2, r2, #12 \n"/* r2 = r2 - 12. */ + " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n"/* r0 = 0. */ + " msr basepri, r0 \n"/* Enable interrupts. */ + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r3] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */ + " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r3] \n"/* Program MAIR0. */ + " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #4 \n"/* r4 = 4. */ + " str r4, [r3] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #8 \n"/* r4 = 8. */ + " str r4, [r3] \n"/* Program RNR = 8. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #12 \n"/* r4 = 12. */ + " str r4, [r3] \n"/* Program RNR = 12. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r3] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " msr control, r3 \n"/* Restore the CONTROL register value for the task. */ + " mov lr, r4 \n"/* LR = r4. */ + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n"/* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n"/* LR = r4. */ + " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + #else /* configENABLE_MPU */ + " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " mov lr, r4 \n"/* LR = r4. */ + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n"/* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n"/* LR = r4. */ + " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + #endif /* configENABLE_MPU */ + " \n" + " restore_ns_context: \n" + " ldmia r2!, {r4-r11} \n"/* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + "xSecureContextConst: .word xSecureContext \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst: .word 0xe000ed94 \n" + "xMAIR0Const: .word 0xe000edc0 \n" + "xRNRConst: .word 0xe000ed98 \n" + "xRBARConst: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, svchandler_address_const \n" + " bx r1 \n" + " \n" + " .align 4 \n" + "svchandler_address_const: .word vPortSVCHandler_C \n" + ); +} +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n"/* Secure context is allocated in the supervisor call. */ + " bx lr \n"/* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */ + " it ne \n" + " svcne %0 \n"/* Secure context is freed in the supervisor call. */ + " bx lr \n"/* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/portasm.h new file mode 100644 index 0000000..58eb5cd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/portmacro.h new file mode 100644 index 0000000..26577dd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/portmacro.h @@ -0,0 +1,71 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M55" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h new file mode 100644 index 0000000..26aa668 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_context.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_context.c new file mode 100644 index 0000000..dbe45b7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_context.c @@ -0,0 +1,351 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Ontain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_context.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_context.h new file mode 100644 index 0000000..9ba64b5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_context.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_context_port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_context_port.c new file mode 100644 index 0000000..16f6f9d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_context_port.c @@ -0,0 +1,97 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */ + " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_heap.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_heap.c new file mode 100644 index 0000000..41cee90 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_heap.c @@ -0,0 +1,451 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart, * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/** + * @brief Gets set to the top bit of an size_t type. + * + * When this bit in the xBlockSize member of an BlockLink_t structure is set + * then the block belongs to the application. When the bit is free the block is + * still part of the free heap space. + */ +static size_t xBlockAllocatedBit = 0; +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink; + void * pvReturn = NULL; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size is increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number of + * bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); + secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_heap.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_heap.h new file mode 100644 index 0000000..217db7a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_init.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_init.c new file mode 100644 index 0000000..e28974a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_init.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_init.h new file mode 100644 index 0000000..5871002 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_port_macros.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_port_macros.h new file mode 100644 index 0000000..31e4140 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c new file mode 100644 index 0000000..1dde466 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c @@ -0,0 +1,365 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */ + " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r3, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #4 \n"/* r3 = 4. */ + " str r3, [r2] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #8 \n"/* r3 = 8. */ + " str r3, [r2] \n"/* Program RNR = 8. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #12 \n"/* r3 = 12. */ + " str r3, [r2] \n"/* Program RNR = 12. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " msr control, r2 \n"/* Set this task's CONTROL value. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n"/* Finally, branch to EXC_RETURN. */ + #else /* configENABLE_MPU */ + " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " movs r1, #2 \n"/* r1 = 2. */ + " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r2 \n"/* Finally, branch to EXC_RETURN. */ + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst2: .word 0xe000ed94 \n" + "xMAIR0Const2: .word 0xe000edc0 \n" + "xRNRConst2: .word 0xe000ed98 \n" + "xRBARConst2: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* Read the CONTROL register. */ + " bic r0, #1 \n"/* Clear the bit 0. */ + " msr control, r0 \n"/* Write back the new CONTROL value. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " orr r0, #1 \n"/* r0 = r0 | 1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + "xVTORConst: .word 0xe000ed08 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n"/* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n"/* Read PSP in r0. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( configENABLE_MPU == 1 ) + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r2, control \n"/* r2 = CONTROL. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r1-r11} \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */ + #else /* configENABLE_MPU */ + " mrs r2, psplim \n"/* r2 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r2-r11} \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */ + #endif /* configENABLE_MPU */ + " \n" + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " str r0, [r1] \n"/* Save the new top of stack in TCB. */ + " \n" + " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n"/* r0 = 0. */ + " msr basepri, r0 \n"/* Enable interrupts. */ + " \n" + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */ + " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r3, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #4 \n"/* r3 = 4. */ + " str r3, [r2] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #8 \n"/* r3 = 8. */ + " str r3, [r2] \n"/* Program RNR = 8. */ + " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #12 \n"/* r3 = 12. */ + " str r3, [r2] \n"/* Program RNR = 12. */ + " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r0!, {r1-r11} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */ + #else /* configENABLE_MPU */ + " ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " msr control, r2 \n"/* Restore the CONTROL register value for the task. */ + #else /* configENABLE_MPU */ + " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */ + #endif /* configENABLE_MPU */ + " msr psp, r0 \n"/* Remember the new top of stack for the task. */ + " bx r3 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst: .word 0xe000ed94 \n" + "xMAIR0Const: .word 0xe000edc0 \n" + "xRNRConst: .word 0xe000ed98 \n" + "xRBARConst: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, svchandler_address_const \n" + " bx r1 \n" + " \n" + " .align 4 \n" + "svchandler_address_const: .word vPortSVCHandler_C \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h new file mode 100644 index 0000000..58eb5cd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h new file mode 100644 index 0000000..26577dd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h @@ -0,0 +1,71 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M55" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 0000000..26aa668 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM7/ReadMe.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM7/ReadMe.txt new file mode 100644 index 0000000..d661449 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM7/ReadMe.txt @@ -0,0 +1,18 @@ +There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers. +The best option depends on the revision of the ARM Cortex-M7 core in use. The +revision is specified by an 'r' number, and a 'p' number, so will look something +like 'r0p1'. Check the documentation for the microcontroller in use to find the +revision of the Cortex-M7 core used in that microcontroller. If in doubt, use +the FreeRTOS port provided specifically for r0p1 revisions, as that can be used +with all core revisions. + +The first option is to use the ARM Cortex-M4F port, and the second option is to +use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround. + +If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be +used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in +the /FreeRTOS/Source/portable/GCC/ARM_CM4F directory. + +If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM +Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 +directory. \ No newline at end of file diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM7/r0p1/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM7/r0p1/port.c new file mode 100644 index 0000000..16a85be --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM7/r0p1/port.c @@ -0,0 +1,829 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM7 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __VFP_FP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ) __attribute__( ( naked ) ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP( void ) __attribute__( ( naked ) ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being defined + * but never called. ulDummy is used purely to quieten other warnings + * about code appearing after this function is called - making ulDummy + * volatile makes the compiler think the function could return and + * therefore not output an 'unreachable code' warning for code that appears + * after it. */ + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + __asm volatile ( + " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ + " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n"/* Restore the task stack pointer. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask( void ) +{ + /* Start the first task. This also clears the bit that indicates the FPU is + * in use in case the FPU was used before the scheduler was started - which + * would otherwise result in the unnecessary leaving of space in the SVC stack + * for lazy saving of FPU registers. */ + __asm volatile ( + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */ + " msr control, r0 \n" + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc 0 \n"/* System call to start first task. */ + " nop \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimisation does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " mrs r0, psp \n" + " isb \n" + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" + " \n" + " stmdb r0!, {r4-r11, r14} \n"/* Save the core registers. */ + " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */ + " \n" + " stmdb sp!, {r0, r3} \n" + " mov r0, %0 \n" + " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + " msr basepri, r0 \n" + " dsb \n" + " isb \n" + " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " ldmia sp!, {r0, r3} \n" + " \n" + " ldr r1, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldr r0, [r1] \n" + " \n" + " ldmia r0!, {r4-r11, r14} \n"/* Pop the core registers. */ + " \n" + " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" + " \n" + " msr psp, r0 \n" + " isb \n" + " \n" + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */ + #if WORKAROUND_PMU_CM001 == 1 + " push { r14 } \n" + " pop { pc } \n" + #endif + #endif + " \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm volatile + ( + " ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */ + " ldr r1, [r0] \n" + " \n" + " orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */ + " str r1, [r0] \n" + " bx r14 \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM7/r0p1/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM7/r0p1/portmacro.h new file mode 100644 index 0000000..1a9c7c8 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM7/r0p1/portmacro.h @@ -0,0 +1,249 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ + } + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() + #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + #define portINLINE __inline + + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + + portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) + { + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static void vPortRaiseBASEPRI( void ) + { + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n"\ + " cpsid i \n"\ + " msr basepri, %0 \n"\ + " isb \n"\ + " dsb \n"\ + " cpsie i \n"\ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + } + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) + { + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n"\ + " mov %1, %2 \n"\ + " cpsid i \n"\ + " msr basepri, %1 \n"\ + " isb \n"\ + " dsb \n"\ + " cpsie i \n"\ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; + } +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) + { + __asm volatile + ( + " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/portasm.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/portasm.c new file mode 100644 index 0000000..91a185a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/portasm.c @@ -0,0 +1,470 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */ + " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #4 \n"/* r4 = 4. */ + " str r4, [r2] \n"/* Program RNR = 4. */ + " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #8 \n"/* r4 = 8. */ + " str r4, [r2] \n"/* Program RNR = 8. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #12 \n"/* r4 = 12. */ + " str r4, [r2] \n"/* Program RNR = 12. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + " ldr r5, xSecureContextConst2 \n" + " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n"/* Set this task's PSPLIM value. */ + " msr control, r3 \n"/* Set this task's CONTROL value. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r4 \n"/* Finally, branch to EXC_RETURN. */ + #else /* configENABLE_MPU */ + " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, xSecureContextConst2 \n" + " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n"/* Set this task's PSPLIM value. */ + " movs r1, #2 \n"/* r1 = 2. */ + " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n"/* Finally, branch to EXC_RETURN. */ + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + "xSecureContextConst2: .word xSecureContext \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst2: .word 0xe000ed94 \n" + "xMAIR0Const2: .word 0xe000edc0 \n" + "xRNRConst2: .word 0xe000ed98 \n" + "xRBARConst2: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* Read the CONTROL register. */ + " bic r0, #1 \n"/* Clear the bit 0. */ + " msr control, r0 \n"/* Write back the new CONTROL value. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " orr r0, #1 \n"/* r0 = r0 | 1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + "xVTORConst: .word 0xe000ed08 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n"/* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " mrs r2, psp \n"/* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n"/* No secure context to save. */ + " push {r0-r2, r14} \n" + " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r3} \n"/* LR is now in r3. */ + " mov lr, r3 \n"/* LR = r3. */ + " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB.*/ + #if ( configENABLE_MPU == 1 ) + " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r3, control \n"/* r3 = CONTROL. */ + " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + " b select_next_task \n" + " \n" + " save_ns_context: \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( configENABLE_MPU == 1 ) + " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " adds r2, r2, #16 \n"/* r2 = r2 + 16. */ + " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r3, control \n"/* r3 = CONTROL. */ + " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */ + " subs r2, r2, #16 \n"/* r2 = r2 - 16. */ + " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + " str r2, [r1] \n"/* Save the new top of stack in TCB. */ + " adds r2, r2, #12 \n"/* r2 = r2 + 12. */ + " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */ + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " subs r2, r2, #12 \n"/* r2 = r2 - 12. */ + " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n"/* r0 = 0. */ + " msr basepri, r0 \n"/* Enable interrupts. */ + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r3] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */ + " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */ + " str r4, [r3] \n"/* Program MAIR0. */ + " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #4 \n"/* r4 = 4. */ + " str r4, [r3] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #8 \n"/* r4 = 8. */ + " str r4, [r3] \n"/* Program RNR = 8. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */ + " movs r4, #12 \n"/* r4 = 12. */ + " str r4, [r3] \n"/* Program RNR = 12. */ + " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r3] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " msr control, r3 \n"/* Restore the CONTROL register value for the task. */ + " mov lr, r4 \n"/* LR = r4. */ + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n"/* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n"/* LR = r4. */ + " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + #else /* configENABLE_MPU */ + " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " mov lr, r4 \n"/* LR = r4. */ + " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n"/* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n"/* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n"/* LR = r4. */ + " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + #endif /* configENABLE_MPU */ + " \n" + " restore_ns_context: \n" + " ldmia r2!, {r4-r11} \n"/* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " msr psp, r2 \n"/* Remember the new top of stack for the task. */ + " bx lr \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + "xSecureContextConst: .word xSecureContext \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst: .word 0xe000ed94 \n" + "xMAIR0Const: .word 0xe000edc0 \n" + "xRNRConst: .word 0xe000ed98 \n" + "xRBARConst: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, svchandler_address_const \n" + " bx r1 \n" + " \n" + " .align 4 \n" + "svchandler_address_const: .word vPortSVCHandler_C \n" + ); +} +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n"/* Secure context is allocated in the supervisor call. */ + " bx lr \n"/* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */ + " it ne \n" + " svcne %0 \n"/* Secure context is freed in the supervisor call. */ + " bx lr \n"/* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/portasm.h new file mode 100644 index 0000000..d2152e1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/portmacro.h new file mode 100644 index 0000000..3795d32 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/portmacro.h @@ -0,0 +1,71 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M85" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h new file mode 100644 index 0000000..26aa668 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_context.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_context.c new file mode 100644 index 0000000..a63d59e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_context.c @@ -0,0 +1,351 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Ontain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_context.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_context.h new file mode 100644 index 0000000..ba883ed --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_context.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_context_port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_context_port.c new file mode 100644 index 0000000..45de616 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_context_port.c @@ -0,0 +1,97 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */ + " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_heap.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_heap.c new file mode 100644 index 0000000..19a7fae --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_heap.c @@ -0,0 +1,451 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart, * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/** + * @brief Gets set to the top bit of an size_t type. + * + * When this bit in the xBlockSize member of an BlockLink_t structure is set + * then the block belongs to the application. When the bit is free the block is + * still part of the free heap space. + */ +static size_t xBlockAllocatedBit = 0; +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink; + void * pvReturn = NULL; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size is increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number of + * bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); + secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_heap.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_heap.h new file mode 100644 index 0000000..0009003 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_init.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_init.c new file mode 100644 index 0000000..a21ea1c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_init.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_init.h new file mode 100644 index 0000000..2a0352c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_port_macros.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_port_macros.h new file mode 100644 index 0000000..d8ab67a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c new file mode 100644 index 0000000..72bf9a1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c @@ -0,0 +1,365 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */ + " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r3, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #4 \n"/* r3 = 4. */ + " str r3, [r2] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #8 \n"/* r3 = 8. */ + " str r3, [r2] \n"/* Program RNR = 8. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #12 \n"/* r3 = 12. */ + " str r3, [r2] \n"/* Program RNR = 12. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " msr control, r2 \n"/* Set this task's CONTROL value. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n"/* Finally, branch to EXC_RETURN. */ + #else /* configENABLE_MPU */ + " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " movs r1, #2 \n"/* r1 = 2. */ + " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r2 \n"/* Finally, branch to EXC_RETURN. */ + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst2: .word 0xe000ed94 \n" + "xMAIR0Const2: .word 0xe000edc0 \n" + "xRNRConst2: .word 0xe000ed98 \n" + "xRBARConst2: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* Read the CONTROL register. */ + " bic r0, #1 \n"/* Clear the bit 0. */ + " msr control, r0 \n"/* Write back the new CONTROL value. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n"/* r0 = CONTROL. */ + " orr r0, #1 \n"/* r0 = r0 | 1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + "xVTORConst: .word 0xe000ed08 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n"/* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n"/* Read PSP in r0. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( configENABLE_MPU == 1 ) + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r2, control \n"/* r2 = CONTROL. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r1-r11} \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */ + #else /* configENABLE_MPU */ + " mrs r2, psplim \n"/* r2 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r2-r11} \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */ + #endif /* configENABLE_MPU */ + " \n" + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " str r0, [r1] \n"/* Save the new top of stack in TCB. */ + " \n" + " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n"/* r0 = 0. */ + " msr basepri, r0 \n"/* Enable interrupts. */ + " \n" + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */ + " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r3, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #4 \n"/* r3 = 4. */ + " str r3, [r2] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #8 \n"/* r3 = 8. */ + " str r3, [r2] \n"/* Program RNR = 8. */ + " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #12 \n"/* r3 = 12. */ + " str r3, [r2] \n"/* Program RNR = 12. */ + " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r0!, {r1-r11} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */ + #else /* configENABLE_MPU */ + " ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " msr control, r2 \n"/* Restore the CONTROL register value for the task. */ + #else /* configENABLE_MPU */ + " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */ + #endif /* configENABLE_MPU */ + " msr psp, r0 \n"/* Remember the new top of stack for the task. */ + " bx r3 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst: .word 0xe000ed94 \n" + "xMAIR0Const: .word 0xe000edc0 \n" + "xRNRConst: .word 0xe000ed98 \n" + "xRBARConst: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, svchandler_address_const \n" + " bx r1 \n" + " \n" + " .align 4 \n" + "svchandler_address_const: .word vPortSVCHandler_C \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h new file mode 100644 index 0000000..d2152e1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h new file mode 100644 index 0000000..3795d32 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h @@ -0,0 +1,71 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M85" +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 0000000..26aa668 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CR5/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CR5/port.c new file mode 100644 index 0000000..490b608 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CR5/port.c @@ -0,0 +1,531 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS + #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */ +#endif + +#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET + #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */ +#endif + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */ +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */ +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */ +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) +#endif + +/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in + * portmacro.h. */ +#ifndef configCLEAR_TICK_INTERRUPT + #define configCLEAR_TICK_INTERRUPT() +#endif + +/* A critical section is exited when the critical section nesting count reaches + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* In all GICs 255 can be written to the priority mask register to unmask all + * (but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) + +/* Tasks are not created with a floating point context, but can be given a + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINTERRUPT_ENABLE_BIT ( 0x80UL ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary + * point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* The critical section macros only mask interrupts up to an application + * determined priority level. Sometimes it is necessary to turn interrupt off in + * the CPU itself before modifying certain hardware registers. */ +#define portCPU_IRQ_DISABLE() \ + __asm volatile ( "CPSID i" ::: "memory" ); \ + __asm volatile ( "DSB" ); \ + __asm volatile ( "ISB" ); + +#define portCPU_IRQ_ENABLE() \ + __asm volatile ( "CPSIE i" ::: "memory" ); \ + __asm volatile ( "DSB" ); \ + __asm volatile ( "ISB" ); + + +/* Macro to unmask all interrupt priorities. */ +#define portCLEAR_INTERRUPT_MASK() \ + { \ + portCPU_IRQ_DISABLE(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm volatile ( "DSB \n" \ + "ISB \n"); \ + portCPU_IRQ_ENABLE(); \ + } + +#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portBIT_0_SET ( ( uint8_t ) 0x01 ) + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case is messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then + * a floating point context must be saved and restored for the task. */ +uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if + * if the nesting depth is 0. */ +uint32_t ulPortInterruptNesting = 0UL; + +/* Used in asm code. */ +__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + * enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */ + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine how many priority bits are implemented in the GIC. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to + * all possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Shift to the least significant bits. */ + while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET ) + { + ucMaxPriorityValue >>= ( uint8_t ) 0x01; + + /* If ulCycles reaches 0 then ucMaxPriorityValue must have been + * read as 0, indicating a misconfiguration. */ + ulCycles--; + + if( ulCycles == 0 ) + { + break; + } + } + + /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read + * value. */ + configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY ); + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Only continue if the CPU is not in User mode. The CPU must be in a + * Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Only continue if the binary point value is set to its lowest possible + * setting. See the comments in vPortValidateInterruptPriority() below for + * more information. */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + + if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) + { + /* Interrupts are turned off in the CPU itself to ensure tick does + * not execute while the scheduler is being started. Interrupts are + * automatically turned back on in the CPU when the first task starts + * executing. */ + portCPU_IRQ_DISABLE(); + + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. prvTaskExitError() is referenced to prevent a compiler + * warning about it being defined but not referenced in the case that the user + * defines their own exit address. */ + ( void ) prvTaskExitError; + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Mask interrupts up to the max syscall interrupt priority. */ + ulPortSetInterruptMask(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + * exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + * priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + * should be unmasked. */ + portCLEAR_INTERRUPT_MASK(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* Set interrupt mask before altering scheduler structures. The tick + * handler runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. It is + * necessary to turn off interrupts in the CPU itself while the ICCPMR is being + * updated. */ + portCPU_IRQ_DISABLE(); + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm volatile ( "dsb \n" + "isb \n"::: "memory" ); + portCPU_IRQ_ENABLE(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK(); + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ + uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + * FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" ); +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( uint32_t ulNewMaskValue ) +{ + if( ulNewMaskValue == pdFALSE ) + { + portCLEAR_INTERRUPT_MASK(); + } +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortSetInterruptMask( void ) +{ + uint32_t ulReturn; + + /* Interrupt in the CPU must be turned off while the ICCPMR is being + * updated. */ + portCPU_IRQ_DISABLE(); + + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + /* Interrupts were already masked. */ + ulReturn = pdTRUE; + } + else + { + ulReturn = pdFALSE; + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm volatile ( "dsb \n" + "isb \n"::: "memory" ); + } + + portCPU_IRQ_ENABLE(); + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. */ + + configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + + /* Priority grouping: The interrupt controller (GIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * The priority grouping is configured by the GIC's binary point register + * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest + * possible value (which may be above 0). */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CR5/portASM.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CR5/portASM.S new file mode 100644 index 0000000..447a76a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CR5/portASM.S @@ -0,0 +1,281 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + .text + .arm + + .set SYS_MODE, 0x1f + .set SVC_MODE, 0x13 + .set IRQ_MODE, 0x12 + + /* Hardware registers. */ + .extern ulICCIAR + .extern ulICCEOIR + .extern ulICCPMR + + /* Variables and functions. */ + .extern ulMaxAPIPriorityMask + .extern _freertos_vector_table + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vApplicationIRQHandler + .extern ulPortInterruptNesting + .extern ulPortTaskHasFPUContext + + .global FreeRTOS_IRQ_Handler + .global FreeRTOS_SWI_Handler + .global vPortRestoreTaskContext + +.macro portSAVE_CONTEXT + + /* Save the LR and SPSR onto the system mode stack before switching to + system mode to save the remaining system mode registers. */ + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + /* Push the critical nesting count. */ + LDR R2, ulCriticalNestingConst + LDR R1, [R2] + PUSH {R1} + + /* Does the task have a floating point context that needs saving? If + ulPortTaskHasFPUContext is 0 then no. */ + LDR R2, ulPortTaskHasFPUContextConst + LDR R3, [R2] + CMP R3, #0 + + /* Save the floating point context, if any. */ + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} + /*VPUSHNE {D16-D31}*/ + PUSHNE {R1} + + /* Save ulPortTaskHasFPUContext itself. */ + PUSH {R3} + + /* Save the stack pointer in the TCB. */ + LDR R0, pxCurrentTCBConst + LDR R1, [R0] + STR SP, [R1] + + .endm + +; /**********************************************************************/ + +.macro portRESTORE_CONTEXT + + /* Set the SP to point to the stack of the task being restored. */ + LDR R0, pxCurrentTCBConst + LDR R1, [R0] + LDR SP, [R1] + + /* Is there a floating point context to restore? If the restored + ulPortTaskHasFPUContext is zero then no. */ + LDR R0, ulPortTaskHasFPUContextConst + POP {R1} + STR R1, [R0] + CMP R1, #0 + + /* Restore the floating point context, if any. */ + POPNE {R0} + /*VPOPNE {D16-D31}*/ + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + /* Restore the critical section nesting depth. */ + LDR R0, ulCriticalNestingConst + POP {R1} + STR R1, [R0] + + /* Ensure the priority mask is correct for the critical nesting depth. */ + LDR R2, ulICCPMRConst + LDR R2, [R2] + CMP R1, #0 + MOVEQ R4, #255 + LDRNE R4, ulMaxAPIPriorityMaskConst + LDRNE R4, [R4] + STR R4, [R2] + + /* Restore all system mode registers other than the SP (which is already + being used). */ + POP {R0-R12, R14} + + /* Return to the task code, loading CPSR on the way. */ + RFEIA sp! + + .endm + + + + +/****************************************************************************** + * SVC handler is used to start the scheduler. + *****************************************************************************/ +.align 4 +.type FreeRTOS_SWI_Handler, %function +FreeRTOS_SWI_Handler: + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + LDR R0, vTaskSwitchContextConst + BLX R0 + portRESTORE_CONTEXT + + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ +.type vPortRestoreTaskContext, %function +vPortRestoreTaskContext: + /* Switch to system mode. */ + CPS #SYS_MODE + portRESTORE_CONTEXT + +.align 4 +.type FreeRTOS_IRQ_Handler, %function +FreeRTOS_IRQ_Handler: + + /* Return to the interrupted instruction. */ + SUB lr, lr, #4 + + /* Push the return address and SPSR. */ + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + /* Change to supervisor mode to allow reentry. */ + CPS #SVC_MODE + + /* Push used registers. */ + PUSH {r0-r4, r12} + + /* Increment nesting count. r3 holds the address of ulPortInterruptNesting + for future use. r1 holds the original ulPortInterruptNesting value for + future use. */ + LDR r3, ulPortInterruptNestingConst + LDR r1, [r3] + ADD r4, r1, #1 + STR r4, [r3] + + /* Read value from the interrupt acknowledge register, which is stored in r0 + for future parameter and interrupt clearing use. */ + LDR r2, ulICCIARConst + LDR r2, [r2] + LDR r0, [r2] + + /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + future use. _RB_ Is this ever needed provided the start of the stack is + alligned on an 8-byte boundary? */ + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + /* Call the interrupt handler. */ + PUSH {r0-r4, lr} + LDR r1, vApplicationIRQHandlerConst + BLX r1 + POP {r0-r4, lr} + ADD sp, sp, r2 + + CPSID i + DSB + ISB + + /* Write the value read from ICCIAR to ICCEOIR. */ + LDR r4, ulICCEOIRConst + LDR r4, [r4] + STR r0, [r4] + + /* Restore the old nesting count. */ + STR r1, [r3] + + /* A context switch is never performed if the nesting count is not 0. */ + CMP r1, #0 + BNE exit_without_switch + + /* Did the interrupt request a context switch? r1 holds the address of + ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + use. */ + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch: + /* No context switch. Restore used registers, LR_irq and SPSR before + returning. */ + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit: + /* A context swtich is to be performed. Clear the context switch pending + flag. */ + MOV r0, #0 + STR r0, [r1] + + /* Restore used registers, LR-irq and SPSR before saving the context + to the task stack. */ + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + /* Call the function that selects the new task to execute. + vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + instructions, or 8 byte aligned stack allocated data. LR does not need + saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */ + LDR R0, vTaskSwitchContextConst + BLX R0 + + /* Restore the context of, and branch to, the task selected to execute + next. */ + portRESTORE_CONTEXT + +ulICCIARConst: .word ulICCIAR +ulICCEOIRConst: .word ulICCEOIR +ulICCPMRConst: .word ulICCPMR +pxCurrentTCBConst: .word pxCurrentTCB +ulCriticalNestingConst: .word ulCriticalNesting +ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext +ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask +vTaskSwitchContextConst: .word vTaskSwitchContext +vApplicationIRQHandlerConst: .word vApplicationIRQHandler +ulPortInterruptNestingConst: .word ulPortInterruptNesting + +.end + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CR5/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CR5/portmacro.h new file mode 100644 index 0000000..b097acd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CR5/portmacro.h @@ -0,0 +1,195 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ + #define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } + + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + #define portYIELD() __asm volatile ( "SWI 0" ::: "memory" ); + + +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ + + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + extern uint32_t ulPortSetInterruptMask( void ); + extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); + extern void vPortInstallFreeRTOSVectorTable( void ); + +/* These macros do not globally disable/enable interrupts. They do mask off + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ + #define portENTER_CRITICAL() vPortEnterCritical(); + #define portEXIT_CRITICAL() vPortExitCritical(); + #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() + #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ + void FreeRTOS_Tick_Handler( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + * before any floating point instructions are executed. */ + void vPortTaskUsesFPU( void ); + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + + #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) + #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif /* configASSERT */ + + #define portNOP() __asm volatile ( "NOP" ) + + + #ifdef __cplusplus + } /* extern C */ + #endif + + +/* The number of bits to shift for an interrupt priority is dependent on the + * number of bits implemented by the interrupt controller. */ + #if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 + #elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 + #elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 + #elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 + #elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 + #else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware + #endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + +/* Interrupt controller access addresses. */ + #define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) + #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) + #define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) + #define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) + #define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) + + #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) + #define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) + #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) + #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) + #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) + #define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) + #define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) + + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CRx_No_GIC/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CRx_No_GIC/port.c new file mode 100644 index 0000000..8577e53 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CRx_No_GIC/port.c @@ -0,0 +1,320 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt. +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt. +#endif + +/* A critical section is exited when the critical section nesting count reaches +this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Tasks are not created with a floating point context, but can be given a +floating point context after they have been created. A variable is stored as +part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task +does not have an FPU context, or any other value if the task does have an FPU +context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user +mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* Let the user override the pre-loading of the initial LR with the address of +prvTaskExitError() in case it messes up unwinding of the stack in the +debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This +variable has to be stored as part of the task context and must be initialised to +a non zero value to ensure interrupts don't inadvertently become unmasked before +the scheduler starts. As it is stored as part of the task context it will +automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then +a floating point context must be saved and restored for the task. */ +volatile uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +volatile uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if +if the nesting depth is 0. */ +volatile uint32_t ulPortInterruptNesting = 0UL; + +/* Used in the asm file to clear an interrupt. */ +__attribute__(( used )) const uint32_t ulICCEOIR = configEOI_ADDRESS; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. + + The fist real value on the stack is the status register, which is set for + system mode, with interrupts enabled. A few NULLs are added first to ensure + GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + the floating point hardware must call vPortTaskUsesFPU() before executing + any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +uint32_t ulAPSR; + + /* Only continue if the CPU is not in User mode. The CPU must be in a + Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Start the timer that generates the tick ISR. */ + portDISABLE_INTERRUPTS(); + configSETUP_TICK_INTERRUPT(); + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + a non-privileged mode or the binary point register was not set to its lowest + possible value. prvTaskExitError() is referenced to prevent a compiler + warning about it being defined but not referenced in the case that the user + defines their own exit address. */ + ( void ) prvTaskExitError; + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + should be unmasked. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ +uint32_t ulInterruptStatus; + + ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus ); + + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ +uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" ); +} +/*-----------------------------------------------------------*/ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CRx_No_GIC/portASM.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CRx_No_GIC/portASM.S new file mode 100644 index 0000000..f3c9947 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CRx_No_GIC/portASM.S @@ -0,0 +1,265 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + .text + .arm + + .set SYS_MODE, 0x1f + .set SVC_MODE, 0x13 + .set IRQ_MODE, 0x12 + + /* Variables and functions. */ + .extern ulMaxAPIPriorityMask + .extern _freertos_vector_table + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vApplicationIRQHandler + .extern ulPortInterruptNesting + .extern ulPortTaskHasFPUContext + .extern ulICCEOIR + .extern ulPortYieldRequired + + .global FreeRTOS_IRQ_Handler + .global FreeRTOS_SVC_Handler + .global vPortRestoreTaskContext + + +.macro portSAVE_CONTEXT + + /* Save the LR and SPSR onto the system mode stack before switching to + system mode to save the remaining system mode registers. */ + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + /* Push the critical nesting count. */ + LDR R2, ulCriticalNestingConst + LDR R1, [R2] + PUSH {R1} + + /* Does the task have a floating point context that needs saving? If + ulPortTaskHasFPUContext is 0 then no. */ + LDR R2, ulPortTaskHasFPUContextConst + LDR R3, [R2] + CMP R3, #0 + + /* Save the floating point context, if any. */ + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} +#if configFPU_D32 == 1 + VPUSHNE {D16-D31} +#endif /* configFPU_D32 */ + PUSHNE {R1} + + /* Save ulPortTaskHasFPUContext itself. */ + PUSH {R3} + + /* Save the stack pointer in the TCB. */ + LDR R0, pxCurrentTCBConst + LDR R1, [R0] + STR SP, [R1] + + .endm + +; /**********************************************************************/ + +.macro portRESTORE_CONTEXT + + /* Set the SP to point to the stack of the task being restored. */ + LDR R0, pxCurrentTCBConst + LDR R1, [R0] + LDR SP, [R1] + + /* Is there a floating point context to restore? If the restored + ulPortTaskHasFPUContext is zero then no. */ + LDR R0, ulPortTaskHasFPUContextConst + POP {R1} + STR R1, [R0] + CMP R1, #0 + + /* Restore the floating point context, if any. */ + POPNE {R0} +#if configFPU_D32 == 1 + VPOPNE {D16-D31} +#endif /* configFPU_D32 */ + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + /* Restore the critical section nesting depth. */ + LDR R0, ulCriticalNestingConst + POP {R1} + STR R1, [R0] + + /* Restore all system mode registers other than the SP (which is already + being used). */ + POP {R0-R12, R14} + + /* Return to the task code, loading CPSR on the way. */ + RFEIA sp! + + .endm + + + + +/****************************************************************************** + * SVC handler is used to yield. + *****************************************************************************/ +.align 4 +.type FreeRTOS_SVC_Handler, %function +FreeRTOS_SVC_Handler: + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + LDR R0, vTaskSwitchContextConst + BLX R0 + portRESTORE_CONTEXT + + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ +.align 4 +.type vPortRestoreTaskContext, %function +vPortRestoreTaskContext: + /* Switch to system mode. */ + CPS #SYS_MODE + portRESTORE_CONTEXT + +.align 4 +.type FreeRTOS_IRQ_Handler, %function +FreeRTOS_IRQ_Handler: + /* Return to the interrupted instruction. */ + SUB lr, lr, #4 + + /* Push the return address and SPSR. */ + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + /* Change to supervisor mode to allow reentry. */ + CPS #0x13 + + /* Push used registers. */ + PUSH {r0-r3, r12} + + /* Increment nesting count. r3 holds the address of ulPortInterruptNesting + for future use. r1 holds the original ulPortInterruptNesting value for + future use. */ + LDR r3, ulPortInterruptNestingConst + LDR r1, [r3] + ADD r0, r1, #1 + STR r0, [r3] + + /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + future use. */ + MOV r0, sp + AND r2, r0, #4 + SUB sp, sp, r2 + + /* Call the interrupt handler. */ + PUSH {r0-r3, lr} + LDR r1, vApplicationIRQHandlerConst + BLX r1 + POP {r0-r3, lr} + ADD sp, sp, r2 + + CPSID i + DSB + ISB + + /* Write to the EOI register. */ + LDR r0, ulICCEOIRConst + LDR r2, [r0] + STR r0, [r2] + + /* Restore the old nesting count. */ + STR r1, [r3] + + /* A context switch is never performed if the nesting count is not 0. */ + CMP r1, #0 + BNE exit_without_switch + + /* Did the interrupt request a context switch? r1 holds the address of + ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + use. */ + LDR r1, ulPortYieldRequiredConst + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch: + /* No context switch. Restore used registers, LR_irq and SPSR before + returning. */ + POP {r0-r3, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit: + /* A context swtich is to be performed. Clear the context switch pending + flag. */ + MOV r0, #0 + STR r0, [r1] + + /* Restore used registers, LR-irq and SPSR before saving the context + to the task stack. */ + POP {r0-r3, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + /* Call the function that selects the new task to execute. + vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + instructions, or 8 byte aligned stack allocated data. LR does not need + saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */ + LDR R0, vTaskSwitchContextConst + BLX R0 + + /* Restore the context of, and branch to, the task selected to execute + next. */ + portRESTORE_CONTEXT + +ulICCEOIRConst: .word ulICCEOIR +pxCurrentTCBConst: .word pxCurrentTCB +ulCriticalNestingConst: .word ulCriticalNesting +ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext +vTaskSwitchContextConst: .word vTaskSwitchContext +vApplicationIRQHandlerConst: .word vApplicationIRQHandler +ulPortInterruptNestingConst: .word ulPortInterruptNesting +ulPortYieldRequiredConst: .word ulPortYieldRequired + +.end + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CRx_No_GIC/portmacro.h new file mode 100644 index 0000000..8b26e65 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ARM_CRx_No_GIC/portmacro.h @@ -0,0 +1,182 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +typedef uint32_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do +not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired )\ +{ \ +extern volatile uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ +} + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm volatile ( "SWI 0 \n" \ + "ISB " ::: "memory" ); + + +/*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); +extern void vPortInstallFreeRTOSVectorTable( void ); + +/* The I bit within the CPSR. */ +#define portINTERRUPT_ENABLE_BIT ( 1 << 7 ) + +/* In the absence of a priority mask register, these functions and macros +globally enable and disable interrupts. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ::: "memory" ); +#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \ + "DSB \n" \ + "ISB " ::: "memory" ); + +__attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void ) +{ +volatile uint32_t ulCPSR; + + __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) :: "memory" ); + ulCPSR &= portINTERRUPT_ENABLE_BIT; + portDISABLE_INTERRUPTS(); + return ulCPSR; +} + +#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) do { if( x == 0 ) portENABLE_INTERRUPTS(); } while( 0 ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not required for this port but included in case common demo code that uses these +macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif + +/* Prototype of the FreeRTOS tick handler. This must be installed as the +handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() +before any floating point instructions are executed. */ +void vPortTaskUsesFPU( void ); +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#define portNOP() __asm volatile( "NOP" ) +#define portINLINE __inline + +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) + +#ifdef __cplusplus + } /* extern C */ +#endif + + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ATMega323/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ATMega323/port.c new file mode 100644 index 0000000..06eccbc --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ATMega323/port.c @@ -0,0 +1,427 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + +Changes from V2.6.0 + + + AVR port - Replaced the inb() and outb() functions with direct memory + access. This allows the port to be built with the 20050414 build of + WinAVR. +*/ + +#include +#include + +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the AVR port. + *----------------------------------------------------------*/ + +/* Start tasks with interrupts enables. */ +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) + +/* Hardware constants for timer 1. */ +#define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) 0x08 ) +#define portPRESCALE_64 ( ( uint8_t ) 0x03 ) +#define portCLOCK_PRESCALER ( ( uint32_t ) 64 ) +#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) 0x10 ) + +/*-----------------------------------------------------------*/ + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * Macro to save all the general purpose registers, the save the stack pointer + * into the TCB. + * + * The first thing we do is save the flags then disable interrupts. This is to + * guard our stack against having a context switch interrupt after we have already + * pushed the registers onto the stack - causing the 32 registers to be on the + * stack twice. + * + * r1 is set to zero as the compiler expects it to be thus, however some + * of the math routines make use of R1. + * + * The interrupts will have been disabled during the call to portSAVE_CONTEXT() + * so we need not worry about reading/writing to the stack pointer. + */ + +#define portSAVE_CONTEXT() \ + asm volatile ( "push r0 \n\t" \ + "in r0, __SREG__ \n\t" \ + "cli \n\t" \ + "push r0 \n\t" \ + "push r1 \n\t" \ + "clr r1 \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in r0, 0x3d \n\t" \ + "st x+, r0 \n\t" \ + "in r0, 0x3e \n\t" \ + "st x+, r0 \n\t" \ + ); + +/* + * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during + * the context save so we can write to the stack pointer. + */ + +#define portRESTORE_CONTEXT() \ + asm volatile ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop r1 \n\t" \ + "pop r0 \n\t" \ + "out __SREG__, r0 \n\t" \ + "pop r0 \n\t" \ + ); + +/*-----------------------------------------------------------*/ + +/* + * Perform hardware setup to enable ticks from timer 1, compare match A. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint16_t usAddress; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + + /* Simulate how the stack would look after a call to vPortYield() generated by + the compiler. */ + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* The start of the task code will be popped off the stack last, so place + it on first. */ + usAddress = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + portSAVE_CONTEXT places the flags on the stack immediately after r0 + to ensure the interrupts get disabled as soon as possible, and so ensuring + the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + + /* Now the remaining registers. The compiler expects R1 to be 0. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x16; /* R16 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x17; /* R17 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ + pxTopOfStack--; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x28; /* R28 Y */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x29; /* R29 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ + pxTopOfStack--; + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT(); + + /* Simulate a function call end as generated by the compiler. We will now + jump to the start of the task the context of which we have just restored. */ + asm volatile ( "ret" ); + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. The first thing we do is save the registers so we + * can use a naked attribute. + */ +void vPortYield( void ) __attribute__ ( ( naked ) ); +void vPortYield( void ) +{ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); + + asm volatile ( "ret" ); +} +/*-----------------------------------------------------------*/ + +/* + * Context switch function used by the tick. This must be identical to + * vPortYield() from the call to vTaskSwitchContext() onwards. The only + * difference from vPortYield() is the tick count is incremented as the + * call comes from the tick ISR. + */ +void vPortYieldFromTick( void ) __attribute__ ( ( naked ) ); +void vPortYieldFromTick( void ) +{ + portSAVE_CONTEXT(); + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + portRESTORE_CONTEXT(); + + asm volatile ( "ret" ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup timer 1 compare match A to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ +uint32_t ulCompareMatch; +uint8_t ucHighByte, ucLowByte; + + /* Using 16bit timer 1 to generate the tick. Correct fuses must be + selected for the configCPU_CLOCK_HZ clock. */ + + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* We only have 16 bits so have to scale to get our required tick rate. */ + ulCompareMatch /= portCLOCK_PRESCALER; + + /* Adjust for correct value. */ + ulCompareMatch -= ( uint32_t ) 1; + + /* Setup compare match value for compare match A. Interrupts are disabled + before this is called so we need not worry here. */ + ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); + ulCompareMatch >>= 8; + ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); + OCR1AH = ucHighByte; + OCR1AL = ucLowByte; + + /* Setup clock source and compare match behaviour. */ + ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64; + TCCR1B = ucLowByte; + + /* Enable the interrupt - this is okay as interrupt are currently globally + disabled. */ + ucLowByte = TIMSK; + ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; + TIMSK = ucLowByte; +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + void TIMER1_COMPA_vect( void ) __attribute__ ( ( signal, naked ) ); + void TIMER1_COMPA_vect( void ) + { + vPortYieldFromTick(); + asm volatile ( "reti" ); + } +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + void TIMER1_COMPA_vect( void ) __attribute__ ( ( signal ) ); + void TIMER1_COMPA_vect( void ) + { + xTaskIncrementTick(); + } +#endif + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ATMega323/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ATMega323/portmacro.h new file mode 100644 index 0000000..4b4d1f1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ATMega323/portmacro.h @@ -0,0 +1,110 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V1.2.3 + + + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it + base 16. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +#define portPOINTER_SIZE_TYPE uint16_t + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portENTER_CRITICAL() asm volatile ( "in __tmp_reg__, __SREG__" :: ); \ + asm volatile ( "cli" :: ); \ + asm volatile ( "push __tmp_reg__" :: ) + +#define portEXIT_CRITICAL() asm volatile ( "pop __tmp_reg__" :: ); \ + asm volatile ( "out __SREG__, __tmp_reg__" :: ) + +#define portDISABLE_INTERRUPTS() asm volatile ( "cli" :: ); +#define portENABLE_INTERRUPTS() asm volatile ( "sei" :: ); +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm volatile ( "nop" ); +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +extern void vPortYield( void ) __attribute__ ( ( naked ) ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR32_UC3/exception.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR32_UC3/exception.S new file mode 100644 index 0000000..7924774 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR32_UC3/exception.S @@ -0,0 +1,327 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Exception and interrupt vectors. + * + * This file maps all events supported by an AVR32UC. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32UC devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + * https://www.microchip.com \n + * Support and FAQ: https://www.microchip.com/support/ + * + ******************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "intc.h" + + +//! @{ +//! \verbatim + + + .section .exception, "ax", @progbits + + +// Start of Exception Vector Table. + + // EVBA must be aligned with a power of two strictly greater than the EVBA- + // relative offset of the last vector. + .balign 0x200 + + // Export symbol. + .global _evba + .type _evba, @function +_evba: + + .org 0x000 + // Unrecoverable Exception. +_handle_Unrecoverable_Exception: + rjmp $ + + .org 0x004 + // TLB Multiple Hit: UNUSED IN AVR32UC. +_handle_TLB_Multiple_Hit: + rjmp $ + + .org 0x008 + // Bus Error Data Fetch. +_handle_Bus_Error_Data_Fetch: + rjmp $ + + .org 0x00C + // Bus Error Instruction Fetch. +_handle_Bus_Error_Instruction_Fetch: + rjmp $ + + .org 0x010 + // NMI. +_handle_NMI: + rjmp $ + + .org 0x014 + // Instruction Address. +_handle_Instruction_Address: + rjmp $ + + .org 0x018 + // ITLB Protection. +_handle_ITLB_Protection: + rjmp $ + + .org 0x01C + // Breakpoint. +_handle_Breakpoint: + rjmp $ + + .org 0x020 + // Illegal Opcode. +_handle_Illegal_Opcode: + rjmp $ + + .org 0x024 + // Unimplemented Instruction. +_handle_Unimplemented_Instruction: + rjmp $ + + .org 0x028 + // Privilege Violation. +_handle_Privilege_Violation: + rjmp $ + + .org 0x02C + // Floating-Point: UNUSED IN AVR32UC. +_handle_Floating_Point: + rjmp $ + + .org 0x030 + // Coprocessor Absent: UNUSED IN AVR32UC. +_handle_Coprocessor_Absent: + rjmp $ + + .org 0x034 + // Data Address (Read). +_handle_Data_Address_Read: + rjmp $ + + .org 0x038 + // Data Address (Write). +_handle_Data_Address_Write: + rjmp $ + + .org 0x03C + // DTLB Protection (Read). +_handle_DTLB_Protection_Read: + rjmp $ + + .org 0x040 + // DTLB Protection (Write). +_handle_DTLB_Protection_Write: + rjmp $ + + .org 0x044 + // DTLB Modified: UNUSED IN AVR32UC. +_handle_DTLB_Modified: + rjmp $ + + .org 0x050 + // ITLB Miss: UNUSED IN AVR32UC. +_handle_ITLB_Miss: + rjmp $ + + .org 0x060 + // DTLB Miss (Read): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Read: + rjmp $ + + .org 0x070 + // DTLB Miss (Write): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Write: + rjmp $ + + .org 0x100 + // Supervisor Call. +_handle_Supervisor_Call: + lda.w pc, SCALLYield + + +// Interrupt support. +// The interrupt controller must provide the offset address relative to EVBA. +// Important note: +// All interrupts call a C function named _get_interrupt_handler. +// This function will read group and interrupt line number to then return in +// R12 a pointer to a user-provided interrupt handler. + + .balign 4 + +_int0: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 0b110 + brlo _int0_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int0_normal: +#endif + mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int1: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 0b110 + brlo _int1_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int1_normal: +#endif + mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int2: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 0b110 + brlo _int2_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int2_normal: +#endif + mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int3: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 0b110 + brlo _int3_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int3_normal: +#endif + mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + + +// Constant data area. + + .balign 4 + + // Values to store in the interrupt priority registers for the various interrupt priority levels. + // The interrupt priority registers contain the interrupt priority level and + // the EVBA-relative interrupt vector offset. + .global ipr_val + .type ipr_val, @object +ipr_val: + .word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\ + (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\ + (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\ + (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba) + + +//! \endverbatim +//! @} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR32_UC3/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR32_UC3/port.c new file mode 100644 index 0000000..d1acd2d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR32_UC3/port.c @@ -0,0 +1,464 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS port source for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + * https://www.microchip.com \n + * Support and FAQ: https://www.microchip.com/support/ + * + *****************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Standard includes. */ +#include +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* AVR32 UC3 includes. */ +#include +#include "gpio.h" +#if( configTICK_USE_TC==1 ) + #include "tc.h" +#endif + + +/* Constants required to setup the task context. */ +#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */ +#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 ) + +/* Each task maintains its own critical nesting variable. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +#if( configTICK_USE_TC==0 ) + static void prvScheduleNextTick( void ); +#else + static void prvClearTcInt( void ); +#endif + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ + +/* + * Low-level initialization routine called during startup, before the main + * function. + * This version comes in replacement to the default one provided by Newlib. + * Newlib's _init_startup only calls init_exceptions, but Newlib's exception + * vectors are not compatible with the SCALL management in the current FreeRTOS + * port. More low-level initializations are besides added here. + */ +void _init_startup(void) +{ + /* Import the Exception Vector Base Address. */ + extern void _evba; + + #if configHEAP_INIT + extern void __heap_start__; + extern void __heap_end__; + BaseType_t *pxMem; + #endif + + /* Load the Exception Vector Base Address in the corresponding system register. */ + Set_system_register( AVR32_EVBA, ( int ) &_evba ); + + /* Enable exceptions. */ + ENABLE_ALL_EXCEPTIONS(); + + /* Initialize interrupt handling. */ + INTC_init_interrupts(); + + #if configHEAP_INIT + + /* Initialize the heap used by malloc. */ + for( pxMem = &__heap_start__; pxMem < ( BaseType_t * )&__heap_end__; ) + { + *pxMem++ = 0xA5A5A5A5; + } + + #endif + + /* Give the used CPU clock frequency to Newlib, so it can work properly. */ + set_cpu_hz( configCPU_CLOCK_HZ ); + + /* Code section present if and only if the debug trace is activated. */ + #if configDBG + { + static const gpio_map_t DBG_USART_GPIO_MAP = + { + { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION }, + { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION } + }; + + /* Initialize the USART used for the debug trace with the configured parameters. */ + set_usart_base( ( void * ) configDBG_USART ); + gpio_enable_module( DBG_USART_GPIO_MAP, + sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) ); + usart_init( configDBG_USART_BAUDRATE ); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* + * malloc, realloc and free are meant to be called through respectively + * pvPortMalloc, pvPortRealloc and vPortFree. + * The latter functions call the former ones from within sections where tasks + * are suspended, so the latter functions are task-safe. __malloc_lock and + * __malloc_unlock use the same mechanism to also keep the former functions + * task-safe as they may be called directly from Newlib's functions. + * However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE + * CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do + * not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable + * interrupts during memory allocation management as this may be a very time- + * consuming process. + */ + +/* + * Lock routine called by Newlib on malloc / realloc / free entry to guarantee a + * safe section as memory allocation management uses global data. + * See the aforementioned details. + */ +void __malloc_lock(struct _reent *ptr) +{ + vTaskSuspendAll(); +} + +/* + * Unlock routine called by Newlib on malloc / realloc / free exit to guarantee + * a safe section as memory allocation management uses global data. + * See the aforementioned details. + */ +void __malloc_unlock(struct _reent *ptr) +{ + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +/* Added as there is no such function in FreeRTOS. */ +void *pvPortRealloc( void *pv, size_t xWantedSize ) +{ +void *pvReturn; + + vTaskSuspendAll(); + { + pvReturn = realloc( pv, xWantedSize ); + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +/* The cooperative scheduler requires a normal IRQ service routine to +simply increment the system tick. */ +/* The preemptive scheduler is defined as "naked" as the full context is saved +on entry as part of the context switch. */ +__attribute__((__naked__)) static void vTick( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_OS_INT(); + + #if( configTICK_USE_TC==1 ) + /* Clear the interrupt flag. */ + prvClearTcInt(); + #else + /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) + clock cycles from now. */ + prvScheduleNextTick(); + #endif + + /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS + calls in a critical section . */ + portENTER_CRITICAL(); + xTaskIncrementTick(); + portEXIT_CRITICAL(); + + /* Restore the context of the "elected task". */ + portRESTORE_CONTEXT_OS_INT(); +} +/*-----------------------------------------------------------*/ + +__attribute__((__naked__)) void SCALLYield( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_SCALL(); + vTaskSwitchContext(); + portRESTORE_CONTEXT_SCALL(); +} +/*-----------------------------------------------------------*/ + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +__attribute__((__noinline__)) void vPortEnterCritical( void ) +{ + /* Disable interrupts */ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__attribute__((__noinline__)) void vPortExitCritical( void ) +{ + if(ulCriticalNesting > portNO_CRITICAL_NESTING) + { + ulCriticalNesting--; + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable all interrupt/exception. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* When the task starts, it will expect to find the function parameter in R12. */ + pxTopOfStack--; + *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */ + *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */ + *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */ + *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */ + *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */ + *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */ + *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */ + *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + portRESTORE_CONTEXT(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR32 port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) +clock cycles from now. */ +#if( configTICK_USE_TC==0 ) + static void prvScheduleFirstTick(void) + { + uint32_t lCycles; + + lCycles = Get_system_register(AVR32_COUNT); + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception + // generation feature does not get disabled. + if(0 == lCycles) + { + lCycles++; + } + Set_system_register(AVR32_COMPARE, lCycles); + } + + __attribute__((__noinline__)) static void prvScheduleNextTick(void) + { + uint32_t lCycles, lCount; + + lCycles = Get_system_register(AVR32_COMPARE); + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception + // generation feature does not get disabled. + if(0 == lCycles) + { + lCycles++; + } + lCount = Get_system_register(AVR32_COUNT); + if( lCycles < lCount ) + { // We missed a tick, recover for the next. + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + } + Set_system_register(AVR32_COMPARE, lCycles); + } +#else + __attribute__((__noinline__)) static void prvClearTcInt(void) + { + AVR32_TC.channel[configTICK_TC_CHANNEL].sr; + } +#endif +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt(void) +{ +#if( configTICK_USE_TC==1 ) + + volatile avr32_tc_t *tc = &AVR32_TC; + + // Options for waveform genration. + tc_waveform_opt_t waveform_opt = + { + .channel = configTICK_TC_CHANNEL, /* Channel selection. */ + + .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */ + .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */ + .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */ + .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */ + + .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */ + .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */ + .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */ + .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */ + + .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */ + .enetrg = FALSE, /* External event trigger enable. */ + .eevt = 0, /* External event selection. */ + .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */ + .cpcdis = FALSE, /* Counter disable when RC compare. */ + .cpcstop = FALSE, /* Counter clock stopped with RC compare. */ + + .burst = FALSE, /* Burst signal selection. */ + .clki = FALSE, /* Clock inversion. */ + .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */ + }; + + tc_interrupt_t tc_interrupt = + { + .etrgs=0, + .ldrbs=0, + .ldras=0, + .cpcs =1, + .cpbs =0, + .cpas =0, + .lovrs=0, + .covfs=0, + }; + +#endif + + /* Disable all interrupt/exception. */ + portDISABLE_INTERRUPTS(); + + /* Register the compare interrupt handler to the interrupt controller and + enable the compare interrupt. */ + + #if( configTICK_USE_TC==1 ) + { + INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0); + + /* Initialize the timer/counter. */ + tc_init_waveform(tc, &waveform_opt); + + /* Set the compare triggers. + Remember TC counter is 16-bits, so counting second is not possible! + That's why we configure it to count ms. */ + tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ ); + + tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt ); + + /* Start the timer/counter. */ + tc_start(tc, configTICK_TC_CHANNEL); + } + #else + { + INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0); + prvScheduleFirstTick(); + } + #endif +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR32_UC3/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR32_UC3/portmacro.h new file mode 100644 index 0000000..1d2992b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR32_UC3/portmacro.h @@ -0,0 +1,696 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS port source for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + * https://www.microchip.com \n + * Support and FAQ: https://www.microchip.com/support/ + * + *****************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ +#include +#include "intc.h" +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS ) +#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS ) +#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS ) + +#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL) + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() {__asm__ __volatile__ ("nop");} +/*-----------------------------------------------------------*/ + + +/*-----------------------------------------------------------*/ + +/* INTC-specific. */ +#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception() +#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception() + +#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt() +#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt() + +#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev) +#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev) + + +/* + * Debug trace. + * Activated if and only if configDBG is nonzero. + * Prints a formatted string to stdout. + * The current source file name and line number are output with a colon before + * the formatted string. + * A carriage return and a linefeed are appended to the output. + * stdout is redirected to the USART configured by configDBG_USART. + * The parameters are the same as for the standard printf function. + * There is no return value. + * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc, + * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock. + */ +#if configDBG +#define portDBG_TRACE(...) \ +{\ + fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\ + printf(__VA_ARGS__);\ + fputs("\r\n", stdout);\ +} +#else +#define portDBG_TRACE(...) +#endif + + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS() +#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS() + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); + + +/* Added as there is no such function in FreeRTOS. */ +extern void *pvPortRealloc( void *pv, size_t xSize ); +/*-----------------------------------------------------------*/ + + +/*=============================================================================================*/ + +/* + * Restore Context for cases other than INTi. + */ +#define portRESTORE_CONTEXT() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + /* R0-R7 should not be used below this line */ \ + /* Skip PC and SR (will do it at the end) */ \ + "sub sp, -2*4 \n\t"\ + /* Restore R8..R12 and LR */ \ + "ldm sp++, r8-r12, lr \n\t"\ + /* Restore SR */ \ + "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \ + "mtsr %[SR], r0 \n\t"\ + /* Restore r0 */ \ + "ld.w r0, sp[-9*4] \n\t"\ + /* Restore PC */ \ + "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting), \ + [pxCurrentTCB] "i" (&pxCurrentTCB), \ + [SR] "i" (AVR32_SR) \ + ); \ +} + + +/* + * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions. + * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception. + * + * Had to make different versions because registers saved on the system stack + * are not the same between INT0..3 exceptions and the scall exception. + */ + +// Task context stack layout: + // R8 (*) + // R9 (*) + // R10 (*) + // R11 (*) + // R12 (*) + // R14/LR (*) + // R15/PC (*) + // SR (*) + // R0 + // R1 + // R2 + // R3 + // R4 + // R5 + // R6 + // R7 + // ulCriticalNesting +// (*) automatically done for INT0..INT3, but not for SCALL + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ +#define portSAVE_CONTEXT_OS_INT() \ +{ \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ("stm --sp, r0-r7"); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ +} + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ +#define portRESTORE_CONTEXT_OS_INT() \ +{ \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7\n\t" \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ +} + +#else + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ +#define portSAVE_CONTEXT_OS_INT() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting])\n\t" \ + "orh r8, HI(%[ulCriticalNesting])\n\t" \ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0 \n\t"\ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + /* NOTE: we don't enter a critical section here because all interrupt handlers */ \ + /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \ + /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \ + /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \ + "mov r8, LO(%[pxCurrentTCB])\n\t" \ + "orh r8, HI(%[pxCurrentTCB])\n\t" \ + "ld.w r0, r8[0]\n\t" \ + "st.w r0[0], sp\n" \ + \ + "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting), \ + [pxCurrentTCB] "i" (&pxCurrentTCB), \ + [LINE] "i" (__LINE__) \ + ); \ +} + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ +#define portRESTORE_CONTEXT_OS_INT() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + __asm__ __volatile__ ( \ + "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \ + : \ + : [LINE] "i" (__LINE__) \ + ); \ + \ + /* Else */ \ + /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + /* Restore all registers */ \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n"\ + \ + "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting), \ + [pxCurrentTCB] "i" (&pxCurrentTCB), \ + [LINE] "i" (__LINE__) \ + ); \ +} + +#endif + + +/* + * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception. + * + * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode. + * + */ +#define portSAVE_CONTEXT_SCALL() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ + /* If SR[M2:M0] == 001 */ \ + /* PC and SR are on the stack. */ \ + /* Else (other modes) */ \ + /* Nothing on the stack. */ \ + \ + /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ + /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ + /* in an interrupt|exception handler. */ \ + \ + __asm__ __volatile__ ( \ + /* in order to save R0-R7 */ \ + "sub sp, 6*4 \n\t"\ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* in order to save R8-R12 and LR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp,-16*4 \n\t"\ + /* Copy PC and SR in other places in the stack. */ \ + "ld.w r0, r7[-2*4] \n\t" /* Read SR */\ + "st.w r7[-8*4], r0 \n\t" /* Copy SR */\ + "ld.w r0, r7[-1*4] \n\t" /* Read PC */\ + "st.w r7[-7*4], r0 \n\t" /* Copy PC */\ + \ + /* Save R8..R12 and LR on the stack. */ \ + "stm --r7, r8-r12, lr \n\t"\ + \ + /* Arriving here we have the following stack organizations: */ \ + /* R8..R12, LR, PC, SR, R0..R7. */ \ + \ + /* Now we can finalize the save. */ \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0" \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting) \ + ); \ + \ + /* Disable the its which may cause a context switch (i.e. cause a change of */ \ + /* pxCurrentTCB). */ \ + /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ + /* critical section because it is a global structure. */ \ + portENTER_CRITICAL(); \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + __asm__ __volatile__ ( \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp" \ + : \ + : [pxCurrentTCB] "i" (&pxCurrentTCB) \ + ); \ +} + +/* + * portRESTORE_CONTEXT() for SupervisorCALL exception. + */ +#define portRESTORE_CONTEXT_SCALL() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + __asm__ __volatile__ ( \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0]" \ + : \ + : [pxCurrentTCB] "i" (&pxCurrentTCB) \ + ); \ + \ + /* Leave pxCurrentTCB variable access critical section */ \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* skip PC and SR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp, -10*4 \n\t"\ + /* Restore r8-r12 and LR */ \ + "ldm r7++, r8-r12, lr \n\t"\ + \ + /* RETS will take care of the extra PC and SR restore. */ \ + /* So, we have to prepare the stack for this. */ \ + "ld.w r0, r7[-8*4] \n\t" /* Read SR */\ + "st.w r7[-2*4], r0 \n\t" /* Copy SR */\ + "ld.w r0, r7[-7*4] \n\t" /* Read PC */\ + "st.w r7[-1*4], r0 \n\t" /* Copy PC */\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + "sub sp, -6*4 \n\t"\ + \ + "rets" \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting) \ + ); \ +} + + +/* + * The ISR used depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ +#define portENTER_SWITCHING_ISR() \ +{ \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ("stm --sp, r0-r7"); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ +} + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ +#define portEXIT_SWITCHING_ISR() \ +{ \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ +} + +#else + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ +#define portENTER_SWITCHING_ISR() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0 \n\t"\ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp \n"\ + \ + "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting), \ + [pxCurrentTCB] "i" (&pxCurrentTCB), \ + [LINE] "i" (__LINE__) \ + ); \ +} + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ +#define portEXIT_SWITCHING_ISR() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \ + /* did not previously save SP in its TCB. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\ + \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\ + "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \ + : \ + : [LINE] "i" (__LINE__) \ + ); \ + \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n"\ + \ + "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting), \ + [pxCurrentTCB] "i" (&pxCurrentTCB), \ + [LINE] "i" (__LINE__) \ + ); \ +} + +#endif + + +#define portYIELD() {__asm__ __volatile__ ("scall");} + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR_AVRDx/README.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR_AVRDx/README.md new file mode 100644 index 0000000..af5856a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR_AVRDx/README.md @@ -0,0 +1 @@ +This port has been moved to `portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx` directory. diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR_Mega0/README.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR_Mega0/README.md new file mode 100644 index 0000000..c83311f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/AVR_Mega0/README.md @@ -0,0 +1 @@ +This port has been moved to `portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0` directory. diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/CORTUS_APS3/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/CORTUS_APS3/port.c new file mode 100644 index 0000000..0ea4836 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/CORTUS_APS3/port.c @@ -0,0 +1,146 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Machine includes */ +#include +#include +/*-----------------------------------------------------------*/ + +/* The initial PSR has the Previous Interrupt Enabled (PIEN) flag set. */ +#define portINITIAL_PSR ( 0x00020000 ) + +/*-----------------------------------------------------------*/ + +/* + * Perform any hardware configuration necessary to generate the tick interrupt. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Make space on the stack for the context - this leaves a couple of spaces + empty. */ + pxTopOfStack -= 20; + + /* Fill the registers with known values to assist debugging. */ + pxTopOfStack[ 16 ] = 0; + pxTopOfStack[ 15 ] = portINITIAL_PSR; + pxTopOfStack[ 14 ] = ( uint32_t ) pxCode; + pxTopOfStack[ 13 ] = 0x00000000UL; /* R15. */ + pxTopOfStack[ 12 ] = 0x00000000UL; /* R14. */ + pxTopOfStack[ 11 ] = 0x0d0d0d0dUL; + pxTopOfStack[ 10 ] = 0x0c0c0c0cUL; + pxTopOfStack[ 9 ] = 0x0b0b0b0bUL; + pxTopOfStack[ 8 ] = 0x0a0a0a0aUL; + pxTopOfStack[ 7 ] = 0x09090909UL; + pxTopOfStack[ 6 ] = 0x08080808UL; + pxTopOfStack[ 5 ] = 0x07070707UL; + pxTopOfStack[ 4 ] = 0x06060606UL; + pxTopOfStack[ 3 ] = 0x05050505UL; + pxTopOfStack[ 2 ] = 0x04040404UL; + pxTopOfStack[ 1 ] = 0x03030303UL; + pxTopOfStack[ 0 ] = ( uint32_t ) pvParameters; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Set-up the timer interrupt. */ + prvSetupTimerInterrupt(); + + /* Integrated Interrupt Controller: Enable all interrupts. */ + ic->ien = 1; + + /* Restore callee saved registers. */ + portRESTORE_CONTEXT(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Enable timer interrupts */ + counter1->reload = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1; + counter1->value = counter1->reload; + counter1->mask = 1; + + /* Set the IRQ Handler priority and enable it. */ + irq[ IRQ_COUNTER1 ].ien = 1; +} +/*-----------------------------------------------------------*/ + +/* Trap 31 handler. */ +void interrupt31_handler( void ) __attribute__((naked)); +void interrupt31_handler( void ) +{ + portSAVE_CONTEXT(); + __asm volatile ( "call vTaskSwitchContext" ); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +static void prvProcessTick( void ) __attribute__((noinline)); +static void prvProcessTick( void ) +{ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Clear the Tick Interrupt. */ + counter1->expired = 0; +} +/*-----------------------------------------------------------*/ + +/* Timer 1 interrupt handler, used for tick interrupt. */ +void interrupt7_handler( void ) __attribute__((naked)); +void interrupt7_handler( void ) +{ + portSAVE_CONTEXT(); + prvProcessTick(); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Nothing to do. Unlikely to want to end. */ +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/CORTUS_APS3/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/CORTUS_APS3/portmacro.h new file mode 100644 index 0000000..162b251 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/CORTUS_APS3/portmacro.h @@ -0,0 +1,153 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() __asm__ volatile ( "mov r0, r0" ) +#define portCRITICAL_NESTING_IN_TCB 1 +#define portIRQ_TRAP_YIELD 31 +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +extern void vPortYield( void ); + +/*---------------------------------------------------------------------------*/ + +#define portYIELD() asm __volatile__( " trap #%0 "::"i"(portIRQ_TRAP_YIELD):"memory") +/*---------------------------------------------------------------------------*/ + +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() +/*---------------------------------------------------------------------------*/ + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() cpu_int_disable() +#define portENABLE_INTERRUPTS() cpu_int_enable() + +/*---------------------------------------------------------------------------*/ + +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext(); } while( 0 ) + +/*---------------------------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ + asm __volatile__ \ + ( \ + "sub r1, #68 \n" /* Make space on the stack for the context. */ \ + "std r2, [r1] + 0 \n" \ + "stq r4, [r1] + 8 \n" \ + "stq r8, [r1] + 24 \n" \ + "stq r12, [r1] + 40 \n" \ + "mov r6, rtt \n" \ + "mov r7, psr \n" \ + "std r6, [r1] + 56 \n" \ + "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \ + "ldub r3, [r2] + 2 \n" /* Load the current interrupt mask. */ \ + "st r3, [r1]+ 64 \n" /* Store the interrupt mask on the stack. */ \ + "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the pointer to the TCB. */ \ + "st r1, [r2] \n" /* Save the stack pointer into the TCB. */ \ + "mov r14, r1 \n" /* Compiler expects r14 to be set to the function stack. */ \ + ); +/*---------------------------------------------------------------------------*/ + +#define portRESTORE_CONTEXT() \ + asm __volatile__( \ + "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the TCB to find the stack pointer and context. */ \ + "ld r1, [r2] \n" \ + "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \ + "ld r3, [r1] + 64 \n" /* Load the previous interrupt mask. */ \ + "stb r3, [r2] + 2 \n" /* Set the current interrupt mask to be the previous. */ \ + "ldd r6, [r1] + 56 \n" /* Restore context. */ \ + "mov rtt, r6 \n" \ + "mov psr, r7 \n" \ + "ldd r2, [r1] + 0 \n" \ + "ldq r4, [r1] + 8 \n" \ + "ldq r8, [r1] + 24 \n" \ + "ldq r12, [r1] + 40 \n" \ + "add r1, #68 \n" \ + "rti \n" \ + ); + +/*---------------------------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*---------------------------------------------------------------------------*/ + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ColdFire_V2/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ColdFire_V2/port.c new file mode 100644 index 0000000..0fc40e6 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ColdFire_V2/port.c @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 ) + +/* Supervisor mode set. */ +#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000) + +/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This +will be set to 0 prior to the first task being started. */ +static uint32_t ulCriticalNesting = 0x9999UL; + +/*-----------------------------------------------------------*/ + +StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0xDEADBEEF; + pxTopOfStack--; + + /* Exception stack frame starts with the return address. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/ + pxTopOfStack -= 14; /* A5 to D0. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + ulCriticalNesting = 0UL; + + /* Configure the interrupts used by this port. */ + vApplicationSetupInterrupts(); + + /* Start the first task executing. */ + vPortStartFirstTask(); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented as there is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + if( ulCriticalNesting == 0UL ) + { + /* Guard against context switches being pended simultaneously with a + critical section being entered. */ + do + { + portDISABLE_INTERRUPTS(); + if( MCF_INTC0_INTFRCL == 0UL ) + { + break; + } + + portENABLE_INTERRUPTS(); + + } while( 1 ); + } + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + ulCriticalNesting--; + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void vPortYieldHandler( void ) +{ +uint32_t ulSavedInterruptMask; + + ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + /* Note this will clear all forced interrupts - this is done for speed. */ + MCF_INTC0_INTFRCL = 0; + vTaskSwitchContext(); + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); +} + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ColdFire_V2/portasm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ColdFire_V2/portasm.S new file mode 100644 index 0000000..846e2af --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ColdFire_V2/portasm.S @@ -0,0 +1,121 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Purpose: Lowest level routines for all ColdFire processors. + * + * Notes: + * + * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale + * supplied source files. + */ + + .global ulPortSetIPL + .global mcf5xxx_wr_cacr + .global __cs3_isr_interrupt_80 + .global vPortStartFirstTask + + .text + +.macro portSAVE_CONTEXT + + lea.l (-60, %sp), %sp + movem.l %d0-%fp, (%sp) + move.l pxCurrentTCB, %a0 + move.l %sp, (%a0) + + .endm + +.macro portRESTORE_CONTEXT + + move.l pxCurrentTCB, %a0 + move.l (%a0), %sp + movem.l (%sp), %d0-%fp + lea.l %sp@(60), %sp + rte + + .endm + +/********************************************************************/ +/* + * This routines changes the IPL to the value passed into the routine. + * It also returns the old IPL value back. + * Calling convention from C: + * old_ipl = asm_set_ipl(new_ipl); + * For the Diab Data C compiler, it passes return value thru D0. + * Note that only the least significant three bits of the passed + * value are used. + */ + +ulPortSetIPL: + link A6,#-8 + movem.l D6-D7,(SP) + + move.w SR,D7 /* current sr */ + + move.l D7,D0 /* prepare return value */ + andi.l #0x0700,D0 /* mask out IPL */ + lsr.l #8,D0 /* IPL */ + + move.l 8(A6),D6 /* get argument */ + andi.l #0x07,D6 /* least significant three bits */ + lsl.l #8,D6 /* move over to make mask */ + + andi.l #0x0000F8FF,D7 /* zero out current IPL */ + or.l D6,D7 /* place new IPL in sr */ + move.w D7,SR + + movem.l (SP),D6-D7 + lea 8(SP),SP + unlk A6 + rts +/********************************************************************/ + +mcf5xxx_wr_cacr: + move.l 4(sp),d0 + .long 0x4e7b0002 /* movec d0,cacr */ + nop + rts + +/********************************************************************/ + +/* Yield interrupt. */ +__cs3_isr_interrupt_80: + portSAVE_CONTEXT + jsr vPortYieldHandler + portRESTORE_CONTEXT + +/********************************************************************/ + + +vPortStartFirstTask: + portRESTORE_CONTEXT + + .end + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ColdFire_V2/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ColdFire_V2/portmacro.h new file mode 100644 index 0000000..af7ff2b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/ColdFire_V2/portmacro.h @@ -0,0 +1,112 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ +uint32_t ulPortSetIPL( uint32_t ); +#define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 ) + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +extern UBaseType_t uxPortSetInterruptMaskFromISR( void ); +extern void vPortClearInterruptMaskFromISR( UBaseType_t ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister ) + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +#define portNOP() asm volatile ( "nop" ) + +/* Note this will overwrite all other bits in the force register, it is done this way for speed. */ +#define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 ) + + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/H8S2329/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/H8S2329/port.c new file mode 100644 index 0000000..459183c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/H8S2329/port.c @@ -0,0 +1,304 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the H8S port. + *----------------------------------------------------------*/ + + +/*-----------------------------------------------------------*/ + +/* When the task starts interrupts should be enabled. */ +#define portINITIAL_CCR ( ( StackType_t ) 0x00 ) + +/* Hardware specific constants used to generate the RTOS tick from the TPU. */ +#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( uint8_t ) 0x20 ) +#define portCLOCK_DIV_64 ( ( uint8_t ) 0x03 ) +#define portCLOCK_DIV ( ( uint32_t ) 64 ) +#define portTGRA_INTERRUPT_ENABLE ( ( uint8_t ) 0x01 ) +#define portTIMER_CHANNEL ( ( uint8_t ) 0x02 ) +#define portMSTP13 ( ( uint16_t ) 0x2000 ) + +/* + * Setup TPU channel one for the RTOS tick at the requested frequency. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The ISR used by portYIELD(). This is installed as a trap handler. + */ +void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint32_t ulValue; + + /* This requires an even address. */ + ulValue = ( uint32_t ) pxTopOfStack; + if( ulValue & 1UL ) + { + pxTopOfStack = pxTopOfStack - 1; + } + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + pxTopOfStack--; + *pxTopOfStack = 0xaa; + pxTopOfStack--; + *pxTopOfStack = 0xbb; + pxTopOfStack--; + *pxTopOfStack = 0xcc; + pxTopOfStack--; + *pxTopOfStack = 0xdd; + + /* The initial stack mimics an interrupt stack. First there is the program + counter (24 bits). */ + ulValue = ( uint32_t ) pxCode; + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + + /* Followed by the CCR. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_CCR; + + /* Next all the general purpose registers - with the parameters being passed + in ER0. The parameter order must match that used by the compiler when the + "saveall" function attribute is used. */ + + /* ER6 */ + pxTopOfStack--; + *pxTopOfStack = 0x66; + pxTopOfStack--; + *pxTopOfStack = 0x66; + pxTopOfStack--; + *pxTopOfStack = 0x66; + pxTopOfStack--; + *pxTopOfStack = 0x66; + + /* ER0 */ + ulValue = ( uint32_t ) pvParameters; + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + + /* ER1 */ + pxTopOfStack--; + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x11; + + /* ER2 */ + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x22; + + /* ER3 */ + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + *pxTopOfStack = 0x33; + + /* ER4 */ + pxTopOfStack--; + *pxTopOfStack = 0x44; + pxTopOfStack--; + *pxTopOfStack = 0x44; + pxTopOfStack--; + *pxTopOfStack = 0x44; + pxTopOfStack--; + *pxTopOfStack = 0x44; + + /* ER5 */ + pxTopOfStack--; + *pxTopOfStack = 0x55; + pxTopOfStack--; + *pxTopOfStack = 0x55; + pxTopOfStack--; + *pxTopOfStack = 0x55; + pxTopOfStack--; + *pxTopOfStack = 0x55; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void * pxCurrentTCB; + + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. This + mirrors the function epilogue code generated by the compiler when the + "saveall" function attribute is used. */ + asm volatile ( + "MOV.L @_pxCurrentTCB, ER6 \n\t" + "MOV.L @ER6, ER7 \n\t" + "LDM.L @SP+, (ER4-ER5) \n\t" + "LDM.L @SP+, (ER0-ER3) \n\t" + "MOV.L @ER7+, ER6 \n\t" + "RTE \n\t" + ); + + ( void ) pxCurrentTCB; + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the h8 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. This is a trap handler. The "saveall" function + * attribute is used so the context is saved by the compiler prologue. All + * we have to do is save the stack pointer. + */ +void vPortYield( void ) +{ + portSAVE_STACK_POINTER(); + vTaskSwitchContext(); + portRESTORE_STACK_POINTER(); +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt handler installed for the RTOS tick depends on whether the + * preemptive or cooperative scheduler is being used. + */ +#if( configUSE_PREEMPTION == 1 ) + + /* + * The preemptive scheduler is used so the ISR calls vTaskSwitchContext(). + * The function prologue saves the context so all we have to do is save + * the stack pointer. + */ + void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) ); + void vTickISR( void ) + { + portSAVE_STACK_POINTER(); + + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Clear the interrupt. */ + TSR1 &= ~0x01; + + portRESTORE_STACK_POINTER(); + } + +#else + + /* + * The cooperative scheduler is being used so all we have to do is + * periodically increment the tick. This can just be a normal ISR and + * the "saveall" attribute is not required. + */ + void vTickISR( void ) __attribute__ ( ( interrupt_handler ) ); + void vTickISR( void ) + { + xTaskIncrementTick(); + + /* Clear the interrupt. */ + TSR1 &= ~0x01; + } + +#endif +/*-----------------------------------------------------------*/ + +/* + * Setup timer 1 compare match to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ +const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV; + + /* Turn the module on. */ + MSTPCR &= ~portMSTP13; + + /* Configure timer 1. */ + TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64; + + /* Configure the compare match value for a tick of configTICK_RATE_HZ. */ + TGR1A = ulCompareMatch; + + /* Start the timer and enable the interrupt - we can do this here as + interrupts are globally disabled when this function is called. */ + TIER1 |= portTGRA_INTERRUPT_ENABLE; + TSTR |= portTIMER_CHANNEL; +} +/*-----------------------------------------------------------*/ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/H8S2329/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/H8S2329/portmacro.h new file mode 100644 index 0000000..7cd885a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/H8S2329/portmacro.h @@ -0,0 +1,139 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portYIELD() asm volatile( "TRAPA #0" ) +#define portNOP() asm volatile( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENABLE_INTERRUPTS() asm volatile( "ANDC #0x7F, CCR" ); +#define portDISABLE_INTERRUPTS() asm volatile( "ORC #0x80, CCR" ); + +/* Push the CCR then disable interrupts. */ +#define portENTER_CRITICAL() asm volatile( "STC CCR, @-ER7" ); \ + portDISABLE_INTERRUPTS(); + +/* Pop the CCR to set the interrupt masking back to its previous state. */ +#define portEXIT_CRITICAL() asm volatile( "LDC @ER7+, CCR" ); +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Context switch macros. These macros are very simple as the context +is saved simply by selecting the saveall attribute of the context switch +interrupt service routines. These macros save and restore the stack +pointer to the TCB. */ + +#define portSAVE_STACK_POINTER() \ +extern void* pxCurrentTCB; \ + \ + asm volatile( \ + "MOV.L @_pxCurrentTCB, ER5 \n\t" \ + "MOV.L ER7, @ER5 \n\t" \ + ); \ + ( void ) pxCurrentTCB; + + +#define portRESTORE_STACK_POINTER() \ +extern void* pxCurrentTCB; \ + \ + asm volatile( \ + "MOV.L @_pxCurrentTCB, ER5 \n\t" \ + "MOV.L @ER5, ER7 \n\t" \ + ); \ + ( void ) pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* Macros to allow a context switch from within an application ISR. */ + +#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); { + +#define portEXIT_SWITCHING_ISR( x ) \ + if( x ) \ + { \ + extern void vTaskSwitchContext( void ); \ + vTaskSwitchContext(); \ + } \ + } portRESTORE_STACK_POINTER(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/HCS12/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/HCS12/port.c new file mode 100644 index 0000000..efdf463 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/HCS12/port.c @@ -0,0 +1,238 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* GCC/HCS12 port by Jefferson L Smith, 2005 */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Port includes */ +#include + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the HCS12 port. + *----------------------------------------------------------*/ + + +/* + * Configure a timer to generate the RTOS tick at the frequency specified + * within FreeRTOSConfig.h. + */ +static void prvSetupTimerInterrupt( void ); + +/* NOTE: Interrupt service routines must be in non-banked memory - as does the +scheduler startup function. */ +#define ATTR_NEAR __attribute__((near)) + +/* Manual context switch function. This is the SWI ISR. */ +// __attribute__((interrupt)) +void ATTR_NEAR vPortYield( void ); + +/* Tick context switch function. This is the timer ISR. */ +// __attribute__((interrupt)) +void ATTR_NEAR vPortTickInterrupt( void ); + +/* Function in non-banked memory which actually switches to first task. */ +BaseType_t ATTR_NEAR xStartSchedulerNear( void ); + +/* Calls to portENTER_CRITICAL() can be nested. When they are nested the +critical section should not be left (i.e. interrupts should not be re-enabled) +until the nesting depth reaches 0. This variable simply tracks the nesting +depth. Each task maintains it's own critical nesting depth variable so +uxCriticalNesting is saved and restored from the task stack during a context +switch. */ +volatile UBaseType_t uxCriticalNesting = 0x80; // un-initialized + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. In this case the stack as + expected by the HCS12 RTI instruction. */ + + + /* The address of the task function is placed in the stack byte at a time. */ + *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 ); + *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 ); + + /* Next are all the registers that form part of the task context. */ + + /* Y register */ + *--pxTopOfStack = ( StackType_t ) 0xff; + *--pxTopOfStack = ( StackType_t ) 0xee; + + /* X register */ + *--pxTopOfStack = ( StackType_t ) 0xdd; + *--pxTopOfStack = ( StackType_t ) 0xcc; + + /* A register contains parameter high byte. */ + *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 ); + + /* B register contains parameter low byte. */ + *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 ); + + /* CCR: Note that when the task starts interrupts will be enabled since + "I" bit of CCR is cleared */ + *--pxTopOfStack = ( StackType_t ) 0x80; // keeps Stop disabled (MCU default) + + /* tmp softregs used by GCC. Values right now don't matter. */ + __asm("\n\ + movw _.frame, 2,-%0 \n\ + movw _.tmp, 2,-%0 \n\ + movw _.z, 2,-%0 \n\ + movw _.xy, 2,-%0 \n\ + ;movw _.d2, 2,-%0 \n\ + ;movw _.d1, 2,-%0 \n\ + ": "=A"(pxTopOfStack) : "0"(pxTopOfStack) ); + + #ifdef BANKED_MODEL + /* The page of the task. */ + *--pxTopOfStack = 0x30; // can only directly start in PPAGE 0x30 + #endif + + /* The critical nesting depth is initialised with 0 (meaning not in + a critical section). */ + *--pxTopOfStack = ( StackType_t ) 0x00; + + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the HCS12 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Enable hardware RTI timer */ + /* Ignores configTICK_RATE_HZ */ + RTICTL = 0x50; // 16 MHz xtal: 976.56 Hz, 1024mS + CRGINT |= 0x80; // RTIE +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* xPortStartScheduler() does not start the scheduler directly because + the header file containing the xPortStartScheduler() prototype is part + of the common kernel code, and therefore cannot use the CODE_SEG pragma. + Instead it simply calls the locally defined xNearStartScheduler() - + which does use the CODE_SEG pragma. */ + + int16_t register d; + __asm ("jmp xStartSchedulerNear ; will never return": "=d"(d)); + return d; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStartSchedulerNear( void ) +{ + /* Configure the timer that will generate the RTOS tick. Interrupts are + disabled when this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task. */ + portRESTORE_CONTEXT(); + + portISR_TAIL(); + + /* Should not get here! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +/* + * Context switch functions. These are interrupt service routines. + */ + +/* + * Manual context switch forced by calling portYIELD(). This is the SWI + * handler. + */ +void vPortYield( void ) +{ + portISR_HEAD(); + /* NOTE: This is the trap routine (swi) although not defined as a trap. + It will fill the stack the same way as an ISR in order to mix preemtion + and cooperative yield. */ + + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); + + portISR_TAIL(); +} +/*-----------------------------------------------------------*/ + +/* + * RTOS tick interrupt service routine. If the cooperative scheduler is + * being used then this simply increments the tick count. If the + * preemptive scheduler is being used a context switch can occur. + */ +void vPortTickInterrupt( void ) +{ + portISR_HEAD(); + + /* Clear tick timer flag */ + CRGFLG = 0x80; + + #if configUSE_PREEMPTION == 1 + { + /* A context switch might happen so save the context. */ + portSAVE_CONTEXT(); + + /* Increment the tick ... */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is necessary. */ + vTaskSwitchContext(); + } + + /* Restore the context of a task - which may be a different task + to that interrupted. */ + portRESTORE_CONTEXT(); + } + #else + { + xTaskIncrementTick(); + } + #endif + + portISR_TAIL(); +} + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/HCS12/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/HCS12/portmacro.h new file mode 100644 index 0000000..6b2d24e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/HCS12/portmacro.h @@ -0,0 +1,247 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portYIELD() __asm( "swi" ); +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENABLE_INTERRUPTS() __asm( "cli" ) +#define portDISABLE_INTERRUPTS() __asm( "sei" ) + +/* + * Disable interrupts before incrementing the count of critical section nesting. + * The nesting count is maintained so we know when interrupts should be + * re-enabled. Once interrupts are disabled the nesting count can be accessed + * directly. Each task maintains its own nesting count. + */ +#define portENTER_CRITICAL() \ +{ \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + uxCriticalNesting++; \ +} + +/* + * Interrupts are disabled so we can access the nesting count directly. If the + * nesting is found to be 0 (no nesting) then we are leaving the critical + * section and interrupts can be re-enabled. + */ +#define portEXIT_CRITICAL() \ +{ \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * These macros are very simple as the processor automatically saves and + * restores its registers as interrupts are entered and exited. In + * addition to the (automatically stacked) registers we also stack the + * critical nesting count. Each task maintains its own critical nesting + * count as it is legitimate for a task to yield from within a critical + * section. If the banked memory model is being used then the PPAGE + * register is also stored as part of the tasks context. + */ + +#ifdef BANKED_MODEL + /* + * Load the stack pointer for the task, then pull the critical nesting + * count and PPAGE register from the stack. The remains of the + * context are restored by the RTI instruction. + */ + #define portRESTORE_CONTEXT() \ + { \ + __asm( " \n\ + .globl pxCurrentTCB ; void * \n\ + .globl uxCriticalNesting ; char \n\ + \n\ + ldx pxCurrentTCB \n\ + lds 0,x ; Stack \n\ + \n\ + movb 1,sp+,uxCriticalNesting \n\ + movb 1,sp+,0x30 ; PPAGE \n\ + " ); \ + } + + /* + * By the time this macro is called the processor has already stacked the + * registers. Simply stack the nesting count and PPAGE value, then save + * the task stack pointer. + */ + #define portSAVE_CONTEXT() \ + { \ + __asm( " \n\ + .globl pxCurrentTCB ; void * \n\ + .globl uxCriticalNesting ; char \n\ + \n\ + movb 0x30, 1,-sp ; PPAGE \n\ + movb uxCriticalNesting, 1,-sp \n\ + \n\ + ldx pxCurrentTCB \n\ + sts 0,x ; Stack \n\ + " ); \ + } +#else + + /* + * These macros are as per the BANKED versions above, but without saving + * and restoring the PPAGE register. + */ + + #define portRESTORE_CONTEXT() \ + { \ + __asm( " \n\ + .globl pxCurrentTCB ; void * \n\ + .globl uxCriticalNesting ; char \n\ + \n\ + ldx pxCurrentTCB \n\ + lds 0,x ; Stack \n\ + \n\ + movb 1,sp+,uxCriticalNesting \n\ + " ); \ + } + + #define portSAVE_CONTEXT() \ + { \ + __asm( " \n\ + .globl pxCurrentTCB ; void * \n\ + .globl uxCriticalNesting ; char \n\ + \n\ + movb uxCriticalNesting, 1,-sp \n\ + \n\ + ldx pxCurrentTCB \n\ + sts 0,x ; Stack \n\ + " ); \ + } +#endif + +/* + * Utility macros to save/restore correct software registers for GCC. This is + * useful when GCC does not generate appropriate ISR head/tail code. + */ +#define portISR_HEAD() \ +{ \ + __asm(" \n\ + movw _.frame, 2,-sp \n\ + movw _.tmp, 2,-sp \n\ + movw _.z, 2,-sp \n\ + movw _.xy, 2,-sp \n\ + ;movw _.d2, 2,-sp \n\ + ;movw _.d1, 2,-sp \n\ + "); \ +} + +#define portISR_TAIL() \ +{ \ + __asm(" \n\ + movw 2,sp+, _.xy \n\ + movw 2,sp+, _.z \n\ + movw 2,sp+, _.tmp \n\ + movw 2,sp+, _.frame \n\ + ;movw 2,sp+, _.d1 \n\ + ;movw 2,sp+, _.d2 \n\ + rti \n\ + "); \ +} + +/* + * Utility macro to call macros above in correct order in order to perform a + * task switch from within a standard ISR. This macro can only be used if + * the ISR does not use any local (stack) variables. If the ISR uses stack + * variables portYIELD() should be used in it's place. + */ + +#define portTASK_SWITCH_FROM_ISR() \ + portSAVE_CONTEXT(); \ + vTaskSwitchContext(); \ + portRESTORE_CONTEXT(); + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/IA32_flat/ISR_Support.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/IA32_flat/ISR_Support.h new file mode 100644 index 0000000..66479c2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/IA32_flat/ISR_Support.h @@ -0,0 +1,128 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + .extern ulTopOfSystemStack + .extern ulInterruptNesting + +/*-----------------------------------------------------------*/ + +.macro portFREERTOS_INTERRUPT_ENTRY + + /* Save general purpose registers. */ + pusha + + /* If ulInterruptNesting is zero the rest of the task context will need + saving and a stack switch might be required. */ + movl ulInterruptNesting, %eax + test %eax, %eax + jne 2f + + /* Interrupts are not nested, so save the rest of the task context. */ + .if configSUPPORT_FPU == 1 + + /* If the task has a buffer allocated to save the FPU context then + save the FPU context now. */ + movl pucPortTaskFPUContextBuffer, %eax + test %eax, %eax + je 1f + fnsave ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */ + fwait + + 1: + /* Save the address of the FPU context, if any. */ + push pucPortTaskFPUContextBuffer + + .endif /* configSUPPORT_FPU */ + + /* Find the TCB. */ + movl pxCurrentTCB, %eax + + /* Stack location is first item in the TCB. */ + movl %esp, (%eax) + + /* Switch stacks. */ + movl ulTopOfSystemStack, %esp + movl %esp, %ebp + + 2: + /* Increment nesting count. */ + add $1, ulInterruptNesting + +.endm +/*-----------------------------------------------------------*/ + +.macro portINTERRUPT_EPILOGUE + + cli + sub $1, ulInterruptNesting + + /* If the nesting has unwound to zero. */ + movl ulInterruptNesting, %eax + test %eax, %eax + jne 2f + + /* If a yield was requested then select a new TCB now. */ + movl ulPortYieldPending, %eax + test %eax, %eax + je 1f + movl $0, ulPortYieldPending + call vTaskSwitchContext + + 1: + /* Stack location is first item in the TCB. */ + movl pxCurrentTCB, %eax + movl (%eax), %esp + + .if configSUPPORT_FPU == 1 + + /* Restore address of task's FPU context buffer. */ + pop pucPortTaskFPUContextBuffer + + /* If the task has a buffer allocated in which its FPU context is saved, + then restore it now. */ + movl pucPortTaskFPUContextBuffer, %eax + test %eax, %eax + je 1f + frstor ( %eax ) + 1: + .endif + + 2: + popa + +.endm +/*-----------------------------------------------------------*/ + +.macro portFREERTOS_INTERRUPT_EXIT + + portINTERRUPT_EPILOGUE + /* EOI. */ + movl $0x00, (0xFEE000B0) + iret + +.endm diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/IA32_flat/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/IA32_flat/port.c new file mode 100644 index 0000000..75b9075 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/IA32_flat/port.c @@ -0,0 +1,687 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#if( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) ) + #warning configISR_STACK_SIZE is probably too small! +#endif /* ( configISR_STACK_SIZE < configMINIMAL_STACK_SIZE * 2 ) */ + +#if( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) ) + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be between 2 and 15 +#endif + +#if( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port with an FPU +#endif + +/* A critical section is exited when the critical section nesting count reaches +this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Tasks are not created with a floating point context, but can be given a +floating point context after they have been created. A variable is stored as +part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task +does not have an FPU context, or any other value if the task does have an FPU +context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Only the IF bit is set so tasks start with interrupts enabled. */ +#define portINITIAL_EFLAGS ( 0x200UL ) + +/* Error interrupts are at the highest priority vectors. */ +#define portAPIC_LVT_ERROR_VECTOR ( 0xfe ) +#define portAPIC_SPURIOUS_INT_VECTOR ( 0xff ) + +/* EFLAGS bits. */ +#define portEFLAGS_IF ( 0x200UL ) + +/* FPU context size if FSAVE is used. */ +#define portFPU_CONTEXT_SIZE_BYTES 108 + +/* The expected size of each entry in the IDT. Used to check structure packing + is set correctly. */ +#define portEXPECTED_IDT_ENTRY_SIZE 8 + +/* Default flags setting for entries in the IDT. */ +#define portIDT_FLAGS ( 0x8E ) + +/* This is the lowest possible ISR vector available to application code. */ +#define portAPIC_MIN_ALLOWABLE_VECTOR ( 0x20 ) + +/* If configASSERT() is defined then the system stack is filled with this value +to allow for a crude stack overflow check. */ +#define portSTACK_WORD ( 0xecececec ) +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. + */ +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/* + * Complete one descriptor in the IDT. + */ +static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags ); + +/* + * The default handler installed in each IDT position. + */ +extern void vPortCentralInterruptWrapper( void ); + +/* + * Handler for portYIELD(). + */ +extern void vPortYieldCall( void ); + +/* + * Configure the APIC to generate the RTOS tick. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * Tick interrupt handler. + */ +extern void vPortTimerHandler( void ); + +/* + * Check an interrupt vector is not too high, too low, in use by FreeRTOS, or + * already in use by the application. + */ +static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This +variable must be initialised to a non zero value to ensure interrupts don't +inadvertently become unmasked before the scheduler starts. It is set to zero +before the first task starts executing. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* A structure used to map the various fields of an IDT entry into separate +structure members. */ +struct IDTEntry +{ + uint16_t usISRLow; /* Low 16 bits of handler address. */ + uint16_t usSegmentSelector; /* Flat model means this is not changed. */ + uint8_t ucZero; /* Must be set to zero. */ + uint8_t ucFlags; /* Flags for this entry. */ + uint16_t usISRHigh; /* High 16 bits of handler address. */ +} __attribute__( ( packed ) ); +typedef struct IDTEntry IDTEntry_t; + + +/* Use to pass the location of the IDT to the CPU. */ +struct IDTPointer +{ + uint16_t usTableLimit; + uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */ +} __attribute__( ( __packed__ ) ); +typedef struct IDTPointer IDTPointer_t; + +/* The IDT itself. */ +static __attribute__ ( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ]; + +#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) + + /* A table in which application defined interrupt handlers are stored. These + are called by the central interrupt handler if a common interrupt entry + point it used. */ + static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL }; + +#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */ + +#if ( configSUPPORT_FPU == 1 ) + + /* Saved as part of the task context. If pucPortTaskFPUContextBuffer is NULL + then the task does not have an FPU context. If pucPortTaskFPUContextBuffer is + not NULL then it points to a buffer into which the FPU context can be saved. */ + uint8_t *pucPortTaskFPUContextBuffer __attribute__((used)) = pdFALSE; + +#endif /* configSUPPORT_FPU */ + +/* The stack used by interrupt handlers. */ +static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__((used)) = { 0 }; + +/* Don't use the very top of the system stack so the return address +appears as 0 if the debugger tries to unwind the stack. */ +volatile uint32_t ulTopOfSystemStack __attribute__((used)) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] ); + +/* If a yield is requested from an interrupt or from a critical section then +the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE +instead to indicate the yield should be performed at the end of the interrupt +when the critical section is exited. */ +volatile uint32_t ulPortYieldPending __attribute__((used)) = pdFALSE; + +/* Counts the interrupt nesting depth. Used to know when to switch to the +interrupt/system stack and when to save/restore a complete context. */ +volatile uint32_t ulInterruptNesting __attribute__((used)) = 0; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint32_t ulCodeSegment; + + /* Setup the initial stack as expected by the portFREERTOS_INTERRUPT_EXIT macro. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = 0x00; + pxTopOfStack--; + + /* Parameters first. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + /* There is nothing to return to so assert if attempting to use the return + address. */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; + pxTopOfStack--; + + /* iret used to start the task pops up to here. */ + *pxTopOfStack = portINITIAL_EFLAGS; + pxTopOfStack--; + + /* CS */ + __asm volatile( "movl %%cs, %0" : "=r" ( ulCodeSegment ) ); + *pxTopOfStack = ulCodeSegment; + pxTopOfStack--; + + /* First instruction in the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* General purpose registers as expected by a POPA instruction. */ + *pxTopOfStack = 0xEA; + pxTopOfStack--; + + *pxTopOfStack = 0xEC; + pxTopOfStack--; + + *pxTopOfStack = 0xED1; /* EDX */ + pxTopOfStack--; + + *pxTopOfStack = 0xEB1; /* EBX */ + pxTopOfStack--; + + /* Hole for ESP. */ + pxTopOfStack--; + + *pxTopOfStack = 0x00; /* EBP */ + pxTopOfStack--; + + *pxTopOfStack = 0xE5; /* ESI */ + pxTopOfStack--; + + *pxTopOfStack = 0xeeeeeeee; /* EDI */ + + #if ( configSUPPORT_FPU == 1 ) + { + pxTopOfStack--; + + /* Buffer for FPU context, which is initialised to NULL as tasks are not + created with an FPU context. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + } + #endif /* configSUPPORT_FPU */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags ) +{ +uint16_t usCodeSegment; +uint32_t ulBase = ( uint32_t ) pxHandlerFunction; + + xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX ); + xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX ); + + /* When the flat model is used the CS will never change. */ + __asm volatile( "mov %%cs, %0" : "=r" ( usCodeSegment ) ); + xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment; + xInterruptDescriptorTable[ ucNumber ].ucZero = 0; + xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags; +} +/*-----------------------------------------------------------*/ + +void vPortSetupIDT( void ) +{ +uint32_t ulNum; +IDTPointer_t xIDT; + + #if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) + { + for( ulNum = 0; ulNum < portNUM_VECTORS; ulNum++ ) + { + /* If a handler has not already been installed on this vector. */ + if( ( xInterruptDescriptorTable[ ulNum ].usISRLow == 0x00 ) && ( xInterruptDescriptorTable[ ulNum ].usISRHigh == 0x00 ) ) + { + prvSetInterruptGate( ( uint8_t ) ulNum, vPortCentralInterruptWrapper, portIDT_FLAGS ); + } + } + } + #endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */ + + /* Set IDT address. */ + xIDT.ulTableBase = ( uint32_t ) xInterruptDescriptorTable; + xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1; + + /* Set IDT in CPU. */ + __asm volatile( "lidt %0" :: "m" (xIDT) ); +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +extern void vPortAPICErrorHandlerWrapper( void ); +extern void vPortAPICSpuriousHandler( void ); + + /* Initialise LAPIC to a well known state. */ + portAPIC_LDR = 0xFFFFFFFF; + portAPIC_LDR = ( ( portAPIC_LDR & 0x00FFFFFF ) | 0x00000001 ); + portAPIC_LVT_TIMER = portAPIC_DISABLE; + portAPIC_LVT_PERF = portAPIC_NMI; + portAPIC_LVT_LINT0 = portAPIC_DISABLE; + portAPIC_LVT_LINT1 = portAPIC_DISABLE; + portAPIC_TASK_PRIORITY = 0; + + /* Install APIC timer ISR vector. */ + prvSetInterruptGate( ( uint8_t ) portAPIC_TIMER_INT_VECTOR, vPortTimerHandler, portIDT_FLAGS ); + + /* Install API error handler. */ + prvSetInterruptGate( ( uint8_t ) portAPIC_LVT_ERROR_VECTOR, vPortAPICErrorHandlerWrapper, portIDT_FLAGS ); + + /* Install Yield handler. */ + prvSetInterruptGate( ( uint8_t ) portAPIC_YIELD_INT_VECTOR, vPortYieldCall, portIDT_FLAGS ); + + /* Install spurious interrupt vector. */ + prvSetInterruptGate( ( uint8_t ) portAPIC_SPURIOUS_INT_VECTOR, vPortAPICSpuriousHandler, portIDT_FLAGS ); + + /* Enable the APIC, mapping the spurious interrupt at the same time. */ + portAPIC_SPURIOUS_INT = portAPIC_SPURIOUS_INT_VECTOR | portAPIC_ENABLE_BIT; + + /* Set timer error vector. */ + portAPIC_LVT_ERROR = portAPIC_LVT_ERROR_VECTOR; + + /* Set the interrupt frequency. */ + portAPIC_TMRDIV = portAPIC_DIV_16; + portAPIC_TIMER_INITIAL_COUNT = ( ( configCPU_CLOCK_HZ >> 4UL ) / configTICK_RATE_HZ ) - 1UL; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +BaseType_t xWord; + + /* Some versions of GCC require the -mno-ms-bitfields command line option + for packing to work. */ + configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE ); + + /* Fill part of the system stack with a known value to help detect stack + overflow. A few zeros are left so GDB doesn't get confused unwinding + the stack. */ + for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ ) + { + ulSystemStack[ xWord ] = portSTACK_WORD; + } + + /* Initialise Interrupt Descriptor Table (IDT). */ + vPortSetupIDT(); + + /* Initialise LAPIC and install system handlers. */ + prvSetupTimerInterrupt(); + + /* Make sure the stack used by interrupts is aligned. */ + ulTopOfSystemStack &= ~portBYTE_ALIGNMENT_MASK; + + ulCriticalNesting = 0; + + /* Enable LAPIC Counter.*/ + portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR; + + /* Sometimes needed. */ + portAPIC_TMRDIV = portAPIC_DIV_16; + + /* Should not return from the following function as the scheduler will then + be executing the tasks. */ + vPortStartFirstTask(); + + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + if( ulCriticalNesting == 0 ) + { + #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) + { + __asm volatile( "cli" ); + } + #else + { + portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY; + configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY ); + } + #endif + } + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + should be unmasked. */ + #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) + { + __asm volatile( "sti" ); + } + #else + { + portAPIC_TASK_PRIORITY = 0; + } + #endif + + /* If a yield was pended from within the critical section then + perform the yield now. */ + if( ulPortYieldPending != pdFALSE ) + { + ulPortYieldPending = pdFALSE; + __asm volatile( portYIELD_INTERRUPT ); + } + } + } +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortSetInterruptMask( void ) +{ +volatile uint32_t ulOriginalMask; + + /* Set mask to max syscall priority. */ + #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) + { + /* Return whether interrupts were already enabled or not. Pop adjusts + the stack first. */ + __asm volatile( "pushf \t\n" + "pop %0 \t\n" + "cli " + : "=rm" (ulOriginalMask) :: "memory" ); + + ulOriginalMask &= portEFLAGS_IF; + } + #else + { + /* Return original mask. */ + ulOriginalMask = portAPIC_TASK_PRIORITY; + portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY; + configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY ); + } + #endif + + return ulOriginalMask; +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( uint32_t ulNewMaskValue ) +{ + #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) + { + if( ulNewMaskValue != pdFALSE ) + { + __asm volatile( "sti" ); + } + } + #else + { + portAPIC_TASK_PRIORITY = ulNewMaskValue; + configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue ); + } + #endif +} +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_FPU == 1 ) + + void vPortTaskUsesFPU( void ) + { + /* A task is registering the fact that it needs an FPU context. Allocate a + buffer into which the context can be saved. */ + pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES ); + configASSERT( pucPortTaskFPUContextBuffer ); + + /* Initialise the floating point registers. */ + __asm volatile( "fninit" ); + } + +#endif /* configSUPPORT_FPU */ +/*-----------------------------------------------------------*/ + +void vPortAPICErrorHandler( void ) +{ +/* Variable to hold the APIC error status for viewing in the debugger. */ +volatile uint32_t ulErrorStatus = 0; + + portAPIC_ERROR_STATUS = 0; + ulErrorStatus = portAPIC_ERROR_STATUS; + ( void ) ulErrorStatus; + + /* Force an assert. */ + configASSERT( ulCriticalNesting == ~0UL ); +} +/*-----------------------------------------------------------*/ + +#if( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) + + void vPortCentralInterruptHandler( uint32_t ulVector ) + { + if( ulVector < portNUM_VECTORS ) + { + if( xInterruptHandlerTable[ ulVector ] != NULL ) + { + ( xInterruptHandlerTable[ ulVector ] )(); + } + } + + /* Check for a system stack overflow. */ + configASSERT( ulSystemStack[ 10 ] == portSTACK_WORD ); + configASSERT( ulSystemStack[ 12 ] == portSTACK_WORD ); + configASSERT( ulSystemStack[ 14 ] == portSTACK_WORD ); + } + +#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) + + BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber ) + { + BaseType_t xReturn; + + xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber ); + + if( xReturn != pdFAIL ) + { + /* Save the handler passed in by the application in the vector number + passed in. The addresses are then called from the central interrupt + handler. */ + xInterruptHandlerTable[ ulVectorNumber ] = pxHandler; + } + + return xReturn; + } + +#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber ) +{ +BaseType_t xReturn; + + xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber ); + + if( xReturn != pdFAIL ) + { + taskENTER_CRITICAL(); + { + /* Update the IDT to include the application defined handler. */ + prvSetInterruptGate( ( uint8_t ) ulVectorNumber, ( ISR_Handler_t ) pxHandler, portIDT_FLAGS ); + } + taskEXIT_CRITICAL(); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber ) +{ +BaseType_t xReturn; + + /* Check validity of vector number. */ + if( ulVectorNumber >= portNUM_VECTORS ) + { + /* Too high. */ + xReturn = pdFAIL; + } + else if( ulVectorNumber < portAPIC_MIN_ALLOWABLE_VECTOR ) + { + /* Too low. */ + xReturn = pdFAIL; + } + else if( ulVectorNumber == portAPIC_TIMER_INT_VECTOR ) + { + /* In use by FreeRTOS. */ + xReturn = pdFAIL; + } + else if( ulVectorNumber == portAPIC_YIELD_INT_VECTOR ) + { + /* In use by FreeRTOS. */ + xReturn = pdFAIL; + } + else if( ulVectorNumber == portAPIC_LVT_ERROR_VECTOR ) + { + /* In use by FreeRTOS. */ + xReturn = pdFAIL; + } + else if( ulVectorNumber == portAPIC_SPURIOUS_INT_VECTOR ) + { + /* In use by FreeRTOS. */ + xReturn = pdFAIL; + } + else if( xInterruptHandlerTable[ ulVectorNumber ] != NULL ) + { + /* Already in use by the application. */ + xReturn = pdFAIL; + } + else + { + xReturn = pdPASS; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vGenerateYieldInterrupt( void ) +{ + __asm volatile( portYIELD_INTERRUPT ); +} + + + + + + + + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/IA32_flat/portASM.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/IA32_flat/portASM.S new file mode 100644 index 0000000..a0fa0e8 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/IA32_flat/portASM.S @@ -0,0 +1,275 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +.file "portASM.S" +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vPortCentralInterruptHandler + .extern xTaskIncrementTick + .extern vPortAPICErrorHandler + .extern pucPortTaskFPUContextBuffer + .extern ulPortYieldPending + + .global vPortStartFirstTask + .global vPortCentralInterruptWrapper + .global vPortAPICErrorHandlerWrapper + .global vPortTimerHandler + .global vPortYieldCall + .global vPortAPICSpuriousHandler + + .text + +/*-----------------------------------------------------------*/ + +.align 4 +.func vPortYieldCall +vPortYieldCall: + /* Save general purpose registers. */ + pusha + + .if configSUPPORT_FPU == 1 + + /* If the task has a buffer allocated to save the FPU context then save + the FPU context now. */ + movl pucPortTaskFPUContextBuffer, %eax + test %eax, %eax + je 1f + fnsave ( %eax ) + fwait + + 1: + + /* Save the address of the FPU context, if any. */ + push pucPortTaskFPUContextBuffer + + .endif /* configSUPPORT_FPU */ + + /* Find the TCB. */ + movl pxCurrentTCB, %eax + + /* Stack location is first item in the TCB. */ + movl %esp, (%eax) + + call vTaskSwitchContext + + /* Find the location of pxCurrentTCB again - a callee saved register could + be used in place of eax to prevent this second load, but that then relies + on the compiler and other asm code. */ + movl pxCurrentTCB, %eax + movl (%eax), %esp + + .if configSUPPORT_FPU == 1 + + /* Restore address of task's FPU context buffer. */ + pop pucPortTaskFPUContextBuffer + + /* If the task has a buffer allocated in which its FPU context is saved, + then restore it now. */ + movl pucPortTaskFPUContextBuffer, %eax + test %eax, %eax + je 1f + frstor ( %eax ) + 1: + .endif + + popa + iret + +.endfunc +/*-----------------------------------------------------------*/ + +.align 4 +.func vPortStartFirstTask +vPortStartFirstTask: + + /* Find the TCB. */ + movl pxCurrentTCB, %eax + + /* Stack location is first item in the TCB. */ + movl (%eax), %esp + + /* Restore FPU context flag. */ + .if configSUPPORT_FPU == 1 + + pop pucPortTaskFPUContextBuffer + + .endif /* configSUPPORT_FPU */ + + /* Restore general purpose registers. */ + popa + iret +.endfunc +/*-----------------------------------------------------------*/ + +.align 4 +.func vPortAPICErrorHandlerWrapper +vPortAPICErrorHandlerWrapper: + pusha + call vPortAPICErrorHandler + popa + /* EOI. */ + movl $0x00, (0xFEE000B0) + iret +.endfunc +/*-----------------------------------------------------------*/ + +.align 4 +.func vPortTimerHandler +vPortTimerHandler: + + /* Save general purpose registers. */ + pusha + + /* Interrupts are not nested, so save the rest of the task context. */ + .if configSUPPORT_FPU == 1 + + /* If the task has a buffer allocated to save the FPU context then save the + FPU context now. */ + movl pucPortTaskFPUContextBuffer, %eax + test %eax, %eax + je 1f + fnsave ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */ + fwait + + 1: + /* Save the address of the FPU context, if any. */ + push pucPortTaskFPUContextBuffer + + .endif /* configSUPPORT_FPU */ + + /* Find the TCB. */ + movl pxCurrentTCB, %eax + + /* Stack location is first item in the TCB. */ + movl %esp, (%eax) + + /* Switch stacks. */ + movl ulTopOfSystemStack, %esp + movl %esp, %ebp + + /* Increment nesting count. */ + add $1, ulInterruptNesting + + call xTaskIncrementTick + + sti + + /* Is a switch to another task required? */ + test %eax, %eax + je _skip_context_switch + cli + call vTaskSwitchContext + +_skip_context_switch: + cli + + /* Decrement the variable used to determine if a switch to a system + stack is necessary. */ + sub $1, ulInterruptNesting + + /* Stack location is first item in the TCB. */ + movl pxCurrentTCB, %eax + movl (%eax), %esp + + .if configSUPPORT_FPU == 1 + + /* Restore address of task's FPU context buffer. */ + pop pucPortTaskFPUContextBuffer + + /* If the task has a buffer allocated in which its FPU context is saved, + then restore it now. */ + movl pucPortTaskFPUContextBuffer, %eax + test %eax, %eax + je 1f + frstor ( %eax ) + 1: + .endif + + popa + + /* EOI. */ + movl $0x00, (0xFEE000B0) + iret + +.endfunc +/*-----------------------------------------------------------*/ + +.if configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 + + .align 4 + .func vPortCentralInterruptWrapper + vPortCentralInterruptWrapper: + + portFREERTOS_INTERRUPT_ENTRY + + movl $0xFEE00170, %eax /* Highest In Service Register (ISR) long word. */ + movl $8, %ecx /* Loop counter. */ + + next_isr_long_word: + test %ecx, %ecx /* Loop counter reached 0? */ + je wrapper_epilogue /* Looked at all ISR registers without finding a bit set. */ + sub $1, %ecx /* Sub 1 from loop counter. */ + movl (%eax), %ebx /* Load next ISR long word. */ + sub $0x10, %eax /* Point to next ISR long word in case no bits are set in the current long word. */ + test %ebx, %ebx /* Are there any bits set? */ + je next_isr_long_word /* Look at next ISR long word if no bits were set. */ + sti + bsr %ebx, %ebx /* A bit was set, which one? */ + movl $32, %eax /* Destination operand for following multiplication. */ + mul %ecx /* Calculate base vector for current register, 32 vectors per register. */ + add %ebx, %eax /* Add bit offset into register to get final vector number. */ + push %eax /* Vector number is function parameter. */ + call vPortCentralInterruptHandler + pop %eax /* Remove parameter. */ + + wrapper_epilogue: + portFREERTOS_INTERRUPT_EXIT + + .endfunc + +.endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */ +/*-----------------------------------------------------------*/ + +.align 4 +.func vPortAPISpuriousHandler +vPortAPICSpuriousHandler: + iret + +.endfunc + +.end + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/IA32_flat/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/IA32_flat/portmacro.h new file mode 100644 index 0000000..5932015 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/IA32_flat/portmacro.h @@ -0,0 +1,292 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +typedef uint32_t TickType_t; +#define portMAX_DELAY ( ( TickType_t ) 0xffffffffUL ) + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 32 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* The interrupt priority (for vectors 16 to 255) is determined using vector/16. +The quotient is rounded to the nearest integer with 1 being the lowest priority +and 15 is the highest. Therefore the following two interrupts are at the lowest +priority. *NOTE 1* If the yield vector is changed then it must also be changed +in the portYIELD_INTERRUPT definition immediately below. */ +#define portAPIC_TIMER_INT_VECTOR ( 0x21 ) +#define portAPIC_YIELD_INT_VECTOR ( 0x20 ) + +/* Build yield interrupt instruction. */ +#define portYIELD_INTERRUPT "int $0x20" + +/* APIC register addresses. */ +#define portAPIC_EOI ( *( ( volatile uint32_t * ) 0xFEE000B0UL ) ) + +/* APIC bit definitions. */ +#define portAPIC_ENABLE_BIT ( 1UL << 8UL ) +#define portAPIC_TIMER_PERIODIC ( 1UL << 17UL ) +#define portAPIC_DISABLE ( 1UL << 16UL ) +#define portAPIC_NMI ( 4 << 8) +#define portAPIC_DIV_16 ( 0x03 ) + +/* Define local API register addresses. */ +#define portAPIC_ID_REGISTER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL ) ) ) +#define portAPIC_SPURIOUS_INT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL ) ) ) +#define portAPIC_LVT_TIMER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x320UL ) ) ) +#define portAPIC_TIMER_INITIAL_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x380UL ) ) ) +#define portAPIC_TIMER_CURRENT_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x390UL ) ) ) +#define portAPIC_TASK_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL ) ) ) +#define portAPIC_LVT_ERROR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x370UL ) ) ) +#define portAPIC_ERROR_STATUS ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x280UL ) ) ) +#define portAPIC_LDR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL ) ) ) +#define portAPIC_TMRDIV ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x3E0UL ) ) ) +#define portAPIC_LVT_PERF ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x340UL ) ) ) +#define portAPIC_LVT_LINT0 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x350UL ) ) ) +#define portAPIC_LVT_LINT1 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x360UL ) ) ) + +/* Don't yield if inside a critical section - instead hold the yield pending +so it is performed when the critical section is exited. */ +#define portYIELD() \ +{ \ +extern volatile uint32_t ulCriticalNesting; \ +extern volatile uint32_t ulPortYieldPending; \ + if( ulCriticalNesting != 0 ) \ + { \ + ulPortYieldPending = pdTRUE; \ + } \ + else \ + { \ + __asm volatile( portYIELD_INTERRUPT ); \ + } \ +} + +/* Called at the end of an ISR that can cause a context switch - pend a yield if +xSwithcRequired is not false. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern volatile uint32_t ulPortYieldPending; \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldPending = 1; \ + } \ +} + +/* Same as portEND_SWITCHING_ISR() - take your pick which name to use. */ +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + +/* Critical sections for use in interrupts. */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask( x ) + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); + +/* These macros do not globally disable/enable interrupts. They do mask off +interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portDISABLE_INTERRUPTS() __asm volatile( "cli" ) +#define portENABLE_INTERRUPTS() __asm volatile( "sti" ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not required for this port but included in case common demo code that uses these +macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Architecture specific optimisations. */ +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \ + __asm volatile( "bsr %1, %0\n\t" \ + :"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" ) + + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#define portNOP() __asm volatile( "NOP" ) + +/*----------------------------------------------------------- + * Misc + *----------------------------------------------------------*/ + +#define portNUM_VECTORS 256 +#define portMAX_PRIORITY 15 +typedef void ( *ISR_Handler_t ) ( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() +before any floating point instructions are executed. */ +#ifndef configSUPPORT_FPU + #define configSUPPORT_FPU 0 +#endif + +#if configSUPPORT_FPU == 1 + void vPortTaskUsesFPU( void ); + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() +#endif + +/* See the comments under the configUSE_COMMON_INTERRUPT_ENTRY_POINT definition +below. */ +BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber ); +BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber ); + +#ifndef configAPIC_BASE + /* configAPIC_BASE_ADDRESS sets the base address of the local APIC. It can + be overridden in FreeRTOSConfig.h should it not be constant. */ + #define configAPIC_BASE 0xFEE00000UL +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + /* The FreeRTOS scheduling algorithm selects the task that will enter the + Running state. configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how + that is done. + + If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to + enter the Running state is selected using a portable algorithm written in + C. This is the slowest method, but the algorithm does not restrict the + maximum number of unique RTOS task priorities that are available. + + If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to + enter the Running state is selected using a single assembly instruction. + This is the fastest method, but restricts the maximum number of unique RTOS + task priorities to 32 (the same task priority can be assigned to any number + of RTOS tasks). */ + #warning configUSE_PORT_OPTIMISED_TASK_SELECTION was not defined in FreeRTOSConfig.h and has been defaulted to 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#ifndef configUSE_COMMON_INTERRUPT_ENTRY_POINT + /* There are two ways of implementing interrupt handlers: + + 1) As standard C functions - + + This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT + is set to 1. The C function is installed using + xPortRegisterCInterruptHandler(). + + This is the simplest of the two methods but incurs a slightly longer + interrupt entry time. + + 2) By using an assembly stub that wraps the handler in the FreeRTOS + portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros. + + This method can always be used. It is slightly more complex than + method 1 but benefits from a faster interrupt entry time. */ + #warning configUSE_COMMON_INTERRUPT_ENTRY_POINT was not defined in FreeRTOSConfig.h and has been defaulted to 1. + #define configUSE_COMMON_INTERRUPT_ENTRY_POINT 1 +#endif + +#ifndef configISR_STACK_SIZE + /* Interrupt entry code will switch the stack in use to a dedicated system + stack. + + configISR_STACK_SIZE defines the number of 32-bit values that can be stored + on the system stack, and must be large enough to hold a potentially nested + interrupt stack frame. */ + + #error configISR_STACK_SIZE was not defined in FreeRTOSConfig.h. +#endif + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + /* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not + be called from an interrupt that has a priority above that set by + configMAX_API_CALL_INTERRUPT_PRIORITY. */ + #warning configMAX_API_CALL_INTERRUPT_PRIORITY was not defined in FreeRTOSConfig.h and has been defaulted to 10 + #define configMAX_API_CALL_INTERRUPT_PRIORITY 10 +#endif + +#ifndef configSUPPORT_FPU + #warning configSUPPORT_FPU was not defined in FreeRTOSConfig.h and has been defaulted to 0 + #define configSUPPORT_FPU 0 +#endif + +/* The value written to the task priority register to raise the interrupt mask +to the maximum from which FreeRTOS API calls can be made. */ +#define portAPIC_PRIORITY_SHIFT ( 4UL ) +#define portAPIC_MAX_SUB_PRIORITY ( 0x0fUL ) +#define portMAX_API_CALL_PRIORITY ( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY ) + +/* Asserts if interrupt safe FreeRTOS functions are called from a priority +above the max system call interrupt priority. */ +#define portAPIC_PROCESSOR_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL ) ) ) +#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) ) + +#ifdef __cplusplus + } /* extern C */ +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MCF5235/readme.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MCF5235/readme.md new file mode 100644 index 0000000..ebf6ea6 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MCF5235/readme.md @@ -0,0 +1,2 @@ +The MCF5235 port is deprecated. The last FreeRTOS version that includes this port is 10.4.3. + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MSP430F449/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MSP430F449/port.c new file mode 100644 index 0000000..5dc9d83 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MSP430F449/port.c @@ -0,0 +1,329 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + Changes from V2.5.2 + + + usCriticalNesting now has a volatile qualifier. +*/ + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430 port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Most ports implement critical sections by placing the interrupt flags on +the stack before disabling interrupts. Exiting the critical section is then +simply a case of popping the flags from the stack. As mspgcc does not use +a frame pointer this cannot be done as modifying the stack will clobber all +the stack variables. Instead each task maintains a count of the critical +section nesting depth. Each time a critical section is entered the count is +incremented. Each time a critical section is left the count is decremented - +with interrupts only being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + +/* + * Macro to save a task context to the task stack. This simply pushes all the + * general purpose msp430 registers onto the stack, followed by the + * usCriticalNesting value used by the task. Finally the resultant stack + * pointer value is saved into the task control block so it can be retrieved + * the next time the task executes. + */ +#define portSAVE_CONTEXT() \ + asm volatile ( "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "mov.w usCriticalNesting, r14 \n\t" \ + "push r14 \n\t" \ + "mov.w pxCurrentTCB, r12 \n\t" \ + "mov.w r1, @r12 \n\t" \ + ); + +/* + * Macro to restore a task context from the task stack. This is effectively + * the reverse of portSAVE_CONTEXT(). First the stack pointer value is + * loaded from the task control block. Next the value for usCriticalNesting + * used by the task is retrieved from the stack - followed by the value of all + * the general purpose msp430 registers. + * + * The bic instruction ensures there are no low power bits set in the status + * register that is about to be popped from the stack. + */ +#define portRESTORE_CONTEXT() \ + asm volatile ( "mov.w pxCurrentTCB, r12 \n\t" \ + "mov.w @r12, r1 \n\t" \ + "pop r15 \n\t" \ + "mov.w r15, usCriticalNesting \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "bic #(0xf0),0(r1) \n\t" \ + "reti \n\t" \ + ); +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x3333; + pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + executing an ISR. We want the stack to look just as if this has happened + so place a pointer to the start of the task on the stack first - followed + by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( StackType_t ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xcccc; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xeeee; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R15. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + /* The code generated by the mspgcc compiler does not maintain separate + stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + use the stack as per other ports. Instead a variable is used to keep + track of the critical section nesting. This variable has to be stored + as part of the task context and is initially set to zero. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT(); + + /* Should not get here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by portYIELD or taskYIELD. + * + * The first thing we do is save the registers so we can use a naked attribute. + */ +void vPortYield( void ) __attribute__ ( ( naked ) ); +void vPortYield( void ) +{ + /* We want the stack of the task being saved to look exactly as if the task + was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the + msp430 places the status register onto the stack. As this is a function + call and not an ISR we have to do this manually. */ + asm volatile ( "push r2" ); + _DINT(); + + /* Save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +static void prvSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt service routine used depends on whether the pre-emptive + * scheduler is being used or not. + */ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) ); + interrupt (TIMERA0_VECTOR) prvTickISR( void ) + { + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Increment the tick count then switch to the highest priority task + that is ready to run. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + } + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + interrupt (TIMERA0_VECTOR) prvTickISR( void ); + interrupt (TIMERA0_VECTOR) prvTickISR( void ) + { + xTaskIncrementTick(); + } +#endif + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MSP430F449/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MSP430F449/portmacro.h new file mode 100644 index 0000000..b805357 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MSP430F449/portmacro.h @@ -0,0 +1,128 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() asm volatile ( "DINT" ); asm volatile ( "NOP" ) +#define portENABLE_INTERRUPTS() asm volatile ( "EINT" ); asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ) __attribute__ ( ( naked ) ); +#define portYIELD() vPortYield() +#define portNOP() asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Hardwware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlaze/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlaze/port.c new file mode 100644 index 0000000..20f5377 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlaze/port.c @@ -0,0 +1,334 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MicroBlaze port. + *----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include + +/* Hardware includes. */ +#include +#include +#include + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port. +#endif + +/* Tasks are started with interrupts enabled. */ +#define portINITIAL_MSR_STATE ( ( StackType_t ) 0x02 ) + +/* Tasks are started with a critical section nesting of 0 - however prior +to the scheduler being commenced we don't want the critical nesting level +to reach zero, so it is initialised to a high value. */ +#define portINITIAL_NESTING_VALUE ( 0xff ) + +/* Our hardware setup only uses one counter. */ +#define portCOUNTER_0 0 + +/* The stack used by the ISR is filled with a known value to assist in +debugging. */ +#define portISR_STACK_FILL_VALUE 0x55555555 + +/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task +maintains it's own count, so this variable is saved as part of the task +context. */ +volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE; + +/* To limit the amount of stack required by each task, this port uses a +separate stack for interrupts. */ +uint32_t *pulISRStack; + +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been made. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +extern void *_SDA2_BASE_, *_SDA_BASE_; +const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_; +const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; + + /* Place a few bytes of known values on the bottom of the stack. + This is essential for the Microblaze port and these lines must + not be omitted. The parameter value will overwrite the + 0x22222222 value during the function prologue. */ + *pxTopOfStack = ( StackType_t ) 0x11111111; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22222222; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x33333333; + pxTopOfStack--; + + /* First stack an initial value for the critical section nesting. This + is initialised to zero as tasks are started with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */ + + /* Place an initial value for all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - small data area. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08; /* R8. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0a; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0b; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0c; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - small data read write area. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* R14. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0f; /* R15. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R16. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R17. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R18. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13; /* R19. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R20. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R21. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x16; /* R22. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x17; /* R23. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x18; /* R24. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R25. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1a; /* R26. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1b; /* R27. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1c; /* R28. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1d; /* R29. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1e; /* R30. */ + pxTopOfStack--; + + /* The MSR is stacked between R30 and R31. */ + *pxTopOfStack = portINITIAL_MSR_STATE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x1f; /* R31. */ + pxTopOfStack--; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void ( __FreeRTOS_interrupt_Handler )( void ); +extern void ( vStartFirstTask )( void ); + + + /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */ + asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \ + "sw r6, r1, r0 \n\t" \ + "lhu r7, r1, r0 \n\t" \ + "shi r7, r0, 0x12 \n\t" \ + "shi r6, r0, 0x16 " ); + + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + prvSetupTimerInterrupt(); + + /* Allocate the stack to be used by the interrupt handler. */ + pulISRStack = ( uint32_t * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ); + + /* Restore the context of the first task that is going to run. */ + if( pulISRStack != NULL ) + { + /* Fill the ISR stack with a known value to facilitate debugging. */ + memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ); + pulISRStack += ( configMINIMAL_STACK_SIZE - 1 ); + + /* Kick off the first task. */ + vStartFirstTask(); + } + + /* Should not get here as the tasks are now running! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +void vPortYield( void ) +{ +extern void VPortYieldASM( void ); + + /* Perform the context switch in a critical section to assure it is + not interrupted by the tick ISR. It is not a problem to do this as + each task maintains it's own interrupt status. */ + portENTER_CRITICAL(); + /* Jump directly to the yield function to ensure there is no + compiler generated prologue code. */ + asm volatile ( "bralid r14, VPortYieldASM \n\t" \ + "or r0, r0, r0 \n\t" ); + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. + */ +static void prvSetupTimerInterrupt( void ) +{ +XTmrCtr xTimer; +const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ; +UBaseType_t uxMask; + + /* The OPB timer1 is used to generate the tick. Use the provided library + functions to enable the timer and set the tick frequency. */ + XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID ); + XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); + XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue ); + XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK ); + + /* Set the timer interrupt enable bit while maintaining the other bit + states. */ + uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) ); + uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK; + XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) ); + + XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); + XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK ); + XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 ); +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt handler placed in the interrupt vector when the scheduler is + * started. The task context has already been saved when this is called. + * This handler determines the interrupt source and calls the relevant + * peripheral handler. + */ +void vTaskISRHandler( void ) +{ +static uint32_t ulPending; + + /* Which interrupts are pending? */ + ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) ); + + if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS ) + { + static XIntc_VectorTableEntry *pxTablePtr; + static XIntc_Config *pxConfig; + static uint32_t ulInterruptMask; + + ulInterruptMask = ( uint32_t ) 1 << ulPending; + + /* Get the configuration data using the device ID */ + pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ]; + + pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] ); + if( pxConfig->AckBeforeService & ( ulInterruptMask ) ) + { + XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask ); + pxTablePtr->Handler( pxTablePtr->CallBackRef ); + } + else + { + pxTablePtr->Handler( pxTablePtr->CallBackRef ); + XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask ); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Handler for the timer interrupt. + */ +void vTickISR( void *pvBaseAddress ) +{ +uint32_t ulCSR; + + /* Increment the RTOS tick - this might cause a task to unblock. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Clear the timer interrupt */ + ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0); + XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR ); +} +/*-----------------------------------------------------------*/ + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlaze/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlaze/portasm.s new file mode 100644 index 0000000..d6b7afa --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlaze/portasm.s @@ -0,0 +1,198 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + .extern pxCurrentTCB + .extern vTaskISRHandler + .extern vTaskSwitchContext + .extern uxCriticalNesting + .extern pulISRStack + + .global __FreeRTOS_interrupt_handler + .global VPortYieldASM + .global vStartFirstTask + + +.macro portSAVE_CONTEXT + /* Make room for the context on the stack. */ + addik r1, r1, -132 + /* Save r31 so it can then be used. */ + swi r31, r1, 4 + /* Copy the msr into r31 - this is stacked later. */ + mfs r31, rmsr + /* Stack general registers. */ + swi r30, r1, 12 + swi r29, r1, 16 + swi r28, r1, 20 + swi r27, r1, 24 + swi r26, r1, 28 + swi r25, r1, 32 + swi r24, r1, 36 + swi r23, r1, 40 + swi r22, r1, 44 + swi r21, r1, 48 + swi r20, r1, 52 + swi r19, r1, 56 + swi r18, r1, 60 + swi r17, r1, 64 + swi r16, r1, 68 + swi r15, r1, 72 + swi r13, r1, 80 + swi r12, r1, 84 + swi r11, r1, 88 + swi r10, r1, 92 + swi r9, r1, 96 + swi r8, r1, 100 + swi r7, r1, 104 + swi r6, r1, 108 + swi r5, r1, 112 + swi r4, r1, 116 + swi r3, r1, 120 + swi r2, r1, 124 + /* Stack the critical section nesting value. */ + lwi r3, r0, uxCriticalNesting + swi r3, r1, 128 + /* Save the top of stack value to the TCB. */ + lwi r3, r0, pxCurrentTCB + sw r1, r0, r3 + + .endm + +.macro portRESTORE_CONTEXT + /* Load the top of stack value from the TCB. */ + lwi r3, r0, pxCurrentTCB + lw r1, r0, r3 + /* Restore the general registers. */ + lwi r31, r1, 4 + lwi r30, r1, 12 + lwi r29, r1, 16 + lwi r28, r1, 20 + lwi r27, r1, 24 + lwi r26, r1, 28 + lwi r25, r1, 32 + lwi r24, r1, 36 + lwi r23, r1, 40 + lwi r22, r1, 44 + lwi r21, r1, 48 + lwi r20, r1, 52 + lwi r19, r1, 56 + lwi r18, r1, 60 + lwi r17, r1, 64 + lwi r16, r1, 68 + lwi r15, r1, 72 + lwi r14, r1, 76 + lwi r13, r1, 80 + lwi r12, r1, 84 + lwi r11, r1, 88 + lwi r10, r1, 92 + lwi r9, r1, 96 + lwi r8, r1, 100 + lwi r7, r1, 104 + lwi r6, r1, 108 + lwi r5, r1, 112 + lwi r4, r1, 116 + lwi r2, r1, 124 + + /* Load the critical nesting value. */ + lwi r3, r1, 128 + swi r3, r0, uxCriticalNesting + + /* Obtain the MSR value from the stack. */ + lwi r3, r1, 8 + + /* Are interrupts enabled in the MSR? If so return using an return from + interrupt instruction to ensure interrupts are enabled only once the task + is running again. */ + andi r3, r3, 2 + beqid r3, 36 + or r0, r0, r0 + + /* Reload the rmsr from the stack, clear the enable interrupt bit in the + value before saving back to rmsr register, then return enabling interrupts + as we return. */ + lwi r3, r1, 8 + andi r3, r3, ~2 + mts rmsr, r3 + lwi r3, r1, 120 + addik r1, r1, 132 + rtid r14, 0 + or r0, r0, r0 + + /* Reload the rmsr from the stack, place it in the rmsr register, and + return without enabling interrupts. */ + lwi r3, r1, 8 + mts rmsr, r3 + lwi r3, r1, 120 + addik r1, r1, 132 + rtsd r14, 0 + or r0, r0, r0 + + .endm + + .text + .align 2 + + +__FreeRTOS_interrupt_handler: + portSAVE_CONTEXT + /* Entered via an interrupt so interrupts must be enabled in msr. */ + ori r31, r31, 2 + /* Stack msr. */ + swi r31, r1, 8 + /* Stack the return address. As we entered via an interrupt we do + not need to modify the return address prior to stacking. */ + swi r14, r1, 76 + /* Now switch to use the ISR stack. */ + lwi r3, r0, pulISRStack + add r1, r3, r0 + bralid r15, vTaskISRHandler + or r0, r0, r0 + portRESTORE_CONTEXT + + +VPortYieldASM: + portSAVE_CONTEXT + /* Stack msr. */ + swi r31, r1, 8 + /* Modify the return address so we return to the instruction after the + exception. */ + addi r14, r14, 8 + swi r14, r1, 76 + /* Now switch to use the ISR stack. */ + lwi r3, r0, pulISRStack + add r1, r3, r0 + bralid r15, vTaskSwitchContext + or r0, r0, r0 + portRESTORE_CONTEXT + +vStartFirstTask: + portRESTORE_CONTEXT + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlaze/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlaze/portmacro.h new file mode 100644 index 0000000..e31cd6a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlaze/portmacro.h @@ -0,0 +1,127 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +void microblaze_disable_interrupts( void ); +void microblaze_enable_interrupts( void ); +#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts() +#define portENABLE_INTERRUPTS() microblaze_enable_interrupts() +/*-----------------------------------------------------------*/ + +/* Critical section macros. */ +void vPortEnterCritical( void ); +void vPortExitCritical( void ); +#define portENTER_CRITICAL() { \ + extern UBaseType_t uxCriticalNesting; \ + microblaze_disable_interrupts(); \ + uxCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() { \ + extern UBaseType_t uxCriticalNesting; \ + /* Interrupts are disabled, so we can */ \ + /* access the variable directly. */ \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + /* The nesting has unwound and we \ + can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ + } + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +void vPortYield( void ); +#define portYIELD() vPortYield() + +void vTaskSwitchContext(); +#define portYIELD_FROM_ISR() vTaskSwitchContext() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV8/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV8/port.c new file mode 100644 index 0000000..3814e26 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV8/port.c @@ -0,0 +1,453 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MicroBlaze port. + *----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include + +/* Hardware includes. */ +#include +#include +#include + +/* Tasks are started with a critical section nesting of 0 - however, prior to +the scheduler being commenced interrupts should not be enabled, so the critical +nesting variable is initialised to a non-zero value. */ +#define portINITIAL_NESTING_VALUE ( 0xff ) + +/* The bit within the MSR register that enabled/disables interrupts and +exceptions respectively. */ +#define portMSR_IE ( 0x02U ) +#define portMSR_EE ( 0x100U ) + +/* If the floating point unit is included in the MicroBlaze build, then the +FSR register is saved as part of the task context. portINITIAL_FSR is the value +given to the FSR register when the initial context is set up for a task being +created. */ +#define portINITIAL_FSR ( 0U ) +/*-----------------------------------------------------------*/ + +/* + * Initialise the interrupt controller instance. + */ +static int32_t prvInitialiseInterruptController( void ); + +/* Ensure the interrupt controller instance variable is initialised before it is + * used, and that the initialisation only happens once. + */ +static int32_t prvEnsureInterruptControllerIsInitialised( void ); + +/*-----------------------------------------------------------*/ + +/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task +maintains its own count, so this variable is saved as part of the task +context. */ +volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE; + +/* This port uses a separate stack for interrupts. This prevents the stack of +every task needing to be large enough to hold an entire interrupt stack on top +of the task stack. */ +uint32_t *pulISRStack; + +/* If an interrupt requests a context switch, then ulTaskSwitchRequested will +get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt +handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel +will call vTaskSwitchContext() to ensure the task that runs immediately after +the interrupt exists is the highest priority task that is able to run. This is +an unusual mechanism, but is used for this port because a single interrupt can +cause the servicing of multiple peripherals - and it is inefficient to call +vTaskSwitchContext() multiple times as each peripheral is serviced. */ +volatile uint32_t ulTaskSwitchRequested = 0UL; + +/* The instance of the interrupt controller used by this port. This is required +by the Xilinx library API functions. */ +static XIntc xInterruptControllerInstance; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been made. + * + * See the portable.h header file. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +extern void *_SDA2_BASE_, *_SDA_BASE_; +const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_; +const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; + + /* Place a few bytes of known values on the bottom of the stack. + This is essential for the Microblaze port and these lines must + not be omitted. */ + *pxTopOfStack = ( StackType_t ) 0x00000000; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00000000; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00000000; + pxTopOfStack--; + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + /* The FSR value placed in the initial task context is just 0. */ + *pxTopOfStack = portINITIAL_FSR; + pxTopOfStack--; + #endif + + /* The MSR value placed in the initial task context should have interrupts + disabled. Each task will enable interrupts automatically when it enters + the running state for the first time. */ + *pxTopOfStack = mfmsr() & ~portMSR_IE; + + #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) + { + /* Ensure exceptions are enabled for the task. */ + *pxTopOfStack |= portMSR_EE; + } + #endif + + pxTopOfStack--; + + /* First stack an initial value for the critical section nesting. This + is initialised to zero. */ + *pxTopOfStack = ( StackType_t ) 0x00; + + /* R0 is always zero. */ + /* R1 is the SP. */ + + /* Place an initial value for all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */ + + #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */ + pxTopOfStack--; + #else + pxTopOfStack-= 8; + #endif + + *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; /* R15 - return address for subroutine. */ + + #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */ + pxTopOfStack--; + #else + pxTopOfStack -= 4; + #endif + + *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */ + + #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + #else + pxTopOfStack -= 13; + #endif + + /* Return a pointer to the top of the stack that has been generated so this + can be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void ( vPortStartFirstTask )( void ); +extern uint32_t _stack[]; + + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. + + This port uses an application defined callback function to install the tick + interrupt handler because the kernel will run on lots of different + MicroBlaze and FPGA configurations - not all of which will have the same + timer peripherals defined or available. An example definition of + vApplicationSetupTimerInterrupt() is provided in the official demo + application that accompanies this port. */ + vApplicationSetupTimerInterrupt(); + + /* Reuse the stack from main() as the stack for the interrupts/exceptions. */ + pulISRStack = ( uint32_t * ) _stack; + + /* Ensure there is enough space for the functions called from the interrupt + service routines to write back into the stack frame of the caller. */ + pulISRStack -= 2; + + /* Restore the context of the first task that is going to run. From here + on, the created tasks will be executing. */ + vPortStartFirstTask(); + + /* Should not get here as the tasks are now running! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +void vPortYield( void ) +{ +extern void VPortYieldASM( void ); + + /* Perform the context switch in a critical section to assure it is + not interrupted by the tick ISR. It is not a problem to do this as + each task maintains its own interrupt status. */ + portENTER_CRITICAL(); + { + /* Jump directly to the yield function to ensure there is no + compiler generated prologue code. */ + asm volatile ( "bralid r14, VPortYieldASM \n\t" \ + "or r0, r0, r0 \n\t" ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vPortEnableInterrupt( uint8_t ucInterruptID ) +{ +int32_t lReturn; + + /* An API function is provided to enable an interrupt in the interrupt + controller because the interrupt controller instance variable is private + to this file. */ + lReturn = prvEnsureInterruptControllerIsInitialised(); + if( lReturn == pdPASS ) + { + XIntc_Enable( &xInterruptControllerInstance, ucInterruptID ); + } + + configASSERT( lReturn ); +} +/*-----------------------------------------------------------*/ + +void vPortDisableInterrupt( uint8_t ucInterruptID ) +{ +int32_t lReturn; + + /* An API function is provided to disable an interrupt in the interrupt + controller because the interrupt controller instance variable is private + to this file. */ + lReturn = prvEnsureInterruptControllerIsInitialised(); + + if( lReturn == pdPASS ) + { + XIntc_Disable( &xInterruptControllerInstance, ucInterruptID ); + } + + configASSERT( lReturn ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ) +{ +int32_t lReturn; + + /* An API function is provided to install an interrupt handler because the + interrupt controller instance variable is private to this file. */ + + lReturn = prvEnsureInterruptControllerIsInitialised(); + + if( lReturn == pdPASS ) + { + lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef ); + } + + if( lReturn == XST_SUCCESS ) + { + lReturn = pdPASS; + } + + configASSERT( lReturn == pdPASS ); + + return lReturn; +} +/*-----------------------------------------------------------*/ + +static int32_t prvEnsureInterruptControllerIsInitialised( void ) +{ +static int32_t lInterruptControllerInitialised = pdFALSE; +int32_t lReturn; + + /* Ensure the interrupt controller instance variable is initialised before + it is used, and that the initialisation only happens once. */ + if( lInterruptControllerInitialised != pdTRUE ) + { + lReturn = prvInitialiseInterruptController(); + + if( lReturn == pdPASS ) + { + lInterruptControllerInitialised = pdTRUE; + } + } + else + { + lReturn = pdPASS; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +/* + * Handler for the timer interrupt. This is the handler that the application + * defined callback function vApplicationSetupTimerInterrupt() should install. + */ +void vPortTickISR( void *pvUnused ) +{ +extern void vApplicationClearTimerInterrupt( void ); + + /* Ensure the unused parameter does not generate a compiler warning. */ + ( void ) pvUnused; + + /* This port uses an application defined callback function to clear the tick + interrupt because the kernel will run on lots of different MicroBlaze and + FPGA configurations - not all of which will have the same timer peripherals + defined or available. An example definition of + vApplicationClearTimerInterrupt() is provided in the official demo + application that accompanies this port. */ + vApplicationClearTimerInterrupt(); + + /* Increment the RTOS tick - this might cause a task to unblock. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Force vTaskSwitchContext() to be called as the interrupt exits. */ + ulTaskSwitchRequested = 1; + } +} +/*-----------------------------------------------------------*/ + +static int32_t prvInitialiseInterruptController( void ) +{ +int32_t lStatus; + + lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE ); + + if( lStatus == XST_SUCCESS ) + { + /* Initialise the exception table. */ + Xil_ExceptionInit(); + + /* Service all pending interrupts each time the handler is entered. */ + XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION ); + + /* Install exception handlers if the MicroBlaze is configured to handle + exceptions, and the application defined constant + configINSTALL_EXCEPTION_HANDLERS is set to 1. */ + #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) + { + vPortExceptionsInstallHandlers(); + } + #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */ + + /* Start the interrupt controller. Interrupts are enabled when the + scheduler starts. */ + lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE ); + + if( lStatus == XST_SUCCESS ) + { + lStatus = pdPASS; + } + else + { + lStatus = pdFAIL; + } + } + + configASSERT( lStatus == pdPASS ); + + return lStatus; +} +/*-----------------------------------------------------------*/ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV8/port_exceptions.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV8/port_exceptions.c new file mode 100644 index 0000000..9ebfb21 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV8/port_exceptions.c @@ -0,0 +1,283 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware includes. */ +#include +#include + +/* The Xilinx library defined exception entry point stacks a number of +registers. These definitions are offsets from the stack pointer to the various +stacked register values. */ +#define portexR3_STACK_OFFSET 4 +#define portexR4_STACK_OFFSET 5 +#define portexR5_STACK_OFFSET 6 +#define portexR6_STACK_OFFSET 7 +#define portexR7_STACK_OFFSET 8 +#define portexR8_STACK_OFFSET 9 +#define portexR9_STACK_OFFSET 10 +#define portexR10_STACK_OFFSET 11 +#define portexR11_STACK_OFFSET 12 +#define portexR12_STACK_OFFSET 13 +#define portexR15_STACK_OFFSET 16 +#define portexR18_STACK_OFFSET 19 +#define portexMSR_STACK_OFFSET 20 +#define portexR19_STACK_OFFSET -1 + +/* This is defined to equal the size, in bytes, of the stack frame generated by +the Xilinx standard library exception entry point. It is required to determine +the stack pointer value prior to the exception being entered. */ +#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL + +/* The number of bytes a MicroBlaze instruction consumes. */ +#define portexINSTRUCTION_SIZE 4 + +/* Exclude this entire file if the MicroBlaze is not configured to handle +exceptions, or the application defined configuration constant +configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ +#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) + +/* This variable is set in the exception entry code, before +vPortExceptionHandler is called. */ +uint32_t *pulStackPointerOnFunctionEntry = NULL; + +/* This is the structure that is filled with the MicroBlaze context as it +existed immediately prior to the exception occurrence. A pointer to this +structure is passed into the vApplicationExceptionRegisterDump() callback +function, if one is defined. */ +static xPortRegisterDump xRegisterDump; + +/* This is the FreeRTOS exception handler that is installed for all exception +types. It is called from vPortExceptionHanlderEntry() - which is itself defined +in portasm.S. */ +void vPortExceptionHandler( void *pvExceptionID ); +extern void vPortExceptionHandlerEntry( void *pvExceptionID ); + +/*-----------------------------------------------------------*/ + +/* vApplicationExceptionRegisterDump() is a callback function that the +application can optionally define to receive a populated xPortRegisterDump +structure. If the application chooses not to define a version of +vApplicationExceptionRegisterDump() then this weekly defined default +implementation will be called instead. */ +extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak)); +void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) +{ + ( void ) xRegisterDump; + + for( ;; ) + { + portNOP(); + } +} +/*-----------------------------------------------------------*/ + +void vPortExceptionHandler( void *pvExceptionID ) +{ +extern void *pxCurrentTCB; + + /* Fill an xPortRegisterDump structure with the MicroBlaze context as it + was immediately before the exception occurrence. */ + + /* First fill in the name and handle of the task that was in the Running + state when the exception occurred. */ + xRegisterDump.xCurrentTaskHandle = pxCurrentTCB; + xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL ); + + configASSERT( pulStackPointerOnFunctionEntry ); + + /* Obtain the values of registers that were stacked prior to this function + being called, and may have changed since they were stacked. */ + xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ]; + xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ]; + xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ]; + xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ]; + xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ]; + xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ]; + xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ]; + xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ]; + xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ]; + xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ]; + xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ]; + xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ]; + xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ]; + xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ]; + + /* Obtain the value of all other registers. */ + xRegisterDump.ulR2_small_data_area = mfgpr( R2 ); + xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 ); + xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 ); + xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 ); + xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 ); + xRegisterDump.ulR20 = mfgpr( R20 ); + xRegisterDump.ulR21 = mfgpr( R21 ); + xRegisterDump.ulR22 = mfgpr( R22 ); + xRegisterDump.ulR23 = mfgpr( R23 ); + xRegisterDump.ulR24 = mfgpr( R24 ); + xRegisterDump.ulR25 = mfgpr( R25 ); + xRegisterDump.ulR26 = mfgpr( R26 ); + xRegisterDump.ulR27 = mfgpr( R27 ); + xRegisterDump.ulR28 = mfgpr( R28 ); + xRegisterDump.ulR29 = mfgpr( R29 ); + xRegisterDump.ulR30 = mfgpr( R30 ); + xRegisterDump.ulR31 = mfgpr( R31 ); + xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE; + xRegisterDump.ulEAR = mfear(); + xRegisterDump.ulESR = mfesr(); + xRegisterDump.ulEDR = mfedr(); + + /* Move the saved program counter back to the instruction that was executed + when the exception occurred. This is only valid for certain types of + exception. */ + xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE; + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + { + xRegisterDump.ulFSR = mffsr(); + } + #else + { + xRegisterDump.ulFSR = 0UL; + } + #endif + + /* Also fill in a string that describes what type of exception this is. + The string uses the same ID names as defined in the MicroBlaze standard + library exception header files. */ + switch( ( uint32_t ) pvExceptionID ) + { + case XEXC_ID_FSL : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL"; + break; + + case XEXC_ID_UNALIGNED_ACCESS : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS"; + break; + + case XEXC_ID_ILLEGAL_OPCODE : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE"; + break; + + case XEXC_ID_M_AXI_I_EXCEPTION : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION"; + break; + + case XEXC_ID_M_AXI_D_EXCEPTION : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION"; + break; + + case XEXC_ID_DIV_BY_ZERO : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO"; + break; + + case XEXC_ID_STACK_VIOLATION : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU"; + break; + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + + case XEXC_ID_FPU : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value"; + break; + + #endif /* XPAR_MICROBLAZE_USE_FPU */ + } + + /* vApplicationExceptionRegisterDump() is a callback function that the + application can optionally define to receive the populated xPortRegisterDump + structure. If the application chooses not to define a version of + vApplicationExceptionRegisterDump() then the weekly defined default + implementation within this file will be called instead. */ + vApplicationExceptionRegisterDump( &xRegisterDump ); + + /* Must not attempt to leave this function! */ + for( ;; ) + { + portNOP(); + } +} +/*-----------------------------------------------------------*/ + +void vPortExceptionsInstallHandlers( void ) +{ +static uint32_t ulHandlersAlreadyInstalled = pdFALSE; + + if( ulHandlersAlreadyInstalled == pdFALSE ) + { + ulHandlersAlreadyInstalled = pdTRUE; + + #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1 + microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS ); + #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/ + + #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE ); + #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */ + + #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO ); + #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */ + + #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU ); + #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */ + + #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL ); + #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */ + + microblaze_enable_exceptions(); + } +} + +/* Exclude the entire file if the MicroBlaze is not configured to handle +exceptions, or the application defined configuration item +configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ +#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV8/portasm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV8/portasm.S new file mode 100644 index 0000000..9f260fd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV8/portasm.S @@ -0,0 +1,329 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/* Xilinx library includes. */ +#include "microblaze_exceptions_g.h" +#include "xparameters.h" + +/* The context is oversized to allow functions called from the ISR to write +back into the caller stack. */ +#if( XPAR_MICROBLAZE_USE_FPU != 0 ) + #define portCONTEXT_SIZE 136 + #define portMINUS_CONTEXT_SIZE -136 +#else + #define portCONTEXT_SIZE 132 + #define portMINUS_CONTEXT_SIZE -132 +#endif + +/* Offsets from the stack pointer at which saved registers are placed. */ +#define portR31_OFFSET 4 +#define portR30_OFFSET 8 +#define portR29_OFFSET 12 +#define portR28_OFFSET 16 +#define portR27_OFFSET 20 +#define portR26_OFFSET 24 +#define portR25_OFFSET 28 +#define portR24_OFFSET 32 +#define portR23_OFFSET 36 +#define portR22_OFFSET 40 +#define portR21_OFFSET 44 +#define portR20_OFFSET 48 +#define portR19_OFFSET 52 +#define portR18_OFFSET 56 +#define portR17_OFFSET 60 +#define portR16_OFFSET 64 +#define portR15_OFFSET 68 +#define portR14_OFFSET 72 +#define portR13_OFFSET 76 +#define portR12_OFFSET 80 +#define portR11_OFFSET 84 +#define portR10_OFFSET 88 +#define portR9_OFFSET 92 +#define portR8_OFFSET 96 +#define portR7_OFFSET 100 +#define portR6_OFFSET 104 +#define portR5_OFFSET 108 +#define portR4_OFFSET 112 +#define portR3_OFFSET 116 +#define portR2_OFFSET 120 +#define portCRITICAL_NESTING_OFFSET 124 +#define portMSR_OFFSET 128 +#define portFSR_OFFSET 132 + + .extern pxCurrentTCB + .extern XIntc_DeviceInterruptHandler + .extern vTaskSwitchContext + .extern uxCriticalNesting + .extern pulISRStack + .extern ulTaskSwitchRequested + .extern vPortExceptionHandler + .extern pulStackPointerOnFunctionEntry + + .global _interrupt_handler + .global VPortYieldASM + .global vPortStartFirstTask + .global vPortExceptionHandlerEntry + + +.macro portSAVE_CONTEXT + + /* Make room for the context on the stack. */ + addik r1, r1, portMINUS_CONTEXT_SIZE + + /* Stack general registers. */ + swi r31, r1, portR31_OFFSET + swi r30, r1, portR30_OFFSET + swi r29, r1, portR29_OFFSET + swi r28, r1, portR28_OFFSET + swi r27, r1, portR27_OFFSET + swi r26, r1, portR26_OFFSET + swi r25, r1, portR25_OFFSET + swi r24, r1, portR24_OFFSET + swi r23, r1, portR23_OFFSET + swi r22, r1, portR22_OFFSET + swi r21, r1, portR21_OFFSET + swi r20, r1, portR20_OFFSET + swi r19, r1, portR19_OFFSET + swi r18, r1, portR18_OFFSET + swi r17, r1, portR17_OFFSET + swi r16, r1, portR16_OFFSET + swi r15, r1, portR15_OFFSET + /* R14 is saved later as it needs adjustment if a yield is performed. */ + swi r13, r1, portR13_OFFSET + swi r12, r1, portR12_OFFSET + swi r11, r1, portR11_OFFSET + swi r10, r1, portR10_OFFSET + swi r9, r1, portR9_OFFSET + swi r8, r1, portR8_OFFSET + swi r7, r1, portR7_OFFSET + swi r6, r1, portR6_OFFSET + swi r5, r1, portR5_OFFSET + swi r4, r1, portR4_OFFSET + swi r3, r1, portR3_OFFSET + swi r2, r1, portR2_OFFSET + + /* Stack the critical section nesting value. */ + lwi r18, r0, uxCriticalNesting + swi r18, r1, portCRITICAL_NESTING_OFFSET + + /* Stack MSR. */ + mfs r18, rmsr + swi r18, r1, portMSR_OFFSET + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + /* Stack FSR. */ + mfs r18, rfsr + swi r18, r1, portFSR_OFFSET + #endif + + /* Save the top of stack value to the TCB. */ + lwi r3, r0, pxCurrentTCB + sw r1, r0, r3 + + .endm + +.macro portRESTORE_CONTEXT + + /* Load the top of stack value from the TCB. */ + lwi r18, r0, pxCurrentTCB + lw r1, r0, r18 + + /* Restore the general registers. */ + lwi r31, r1, portR31_OFFSET + lwi r30, r1, portR30_OFFSET + lwi r29, r1, portR29_OFFSET + lwi r28, r1, portR28_OFFSET + lwi r27, r1, portR27_OFFSET + lwi r26, r1, portR26_OFFSET + lwi r25, r1, portR25_OFFSET + lwi r24, r1, portR24_OFFSET + lwi r23, r1, portR23_OFFSET + lwi r22, r1, portR22_OFFSET + lwi r21, r1, portR21_OFFSET + lwi r20, r1, portR20_OFFSET + lwi r19, r1, portR19_OFFSET + lwi r17, r1, portR17_OFFSET + lwi r16, r1, portR16_OFFSET + lwi r15, r1, portR15_OFFSET + lwi r14, r1, portR14_OFFSET + lwi r13, r1, portR13_OFFSET + lwi r12, r1, portR12_OFFSET + lwi r11, r1, portR11_OFFSET + lwi r10, r1, portR10_OFFSET + lwi r9, r1, portR9_OFFSET + lwi r8, r1, portR8_OFFSET + lwi r7, r1, portR7_OFFSET + lwi r6, r1, portR6_OFFSET + lwi r5, r1, portR5_OFFSET + lwi r4, r1, portR4_OFFSET + lwi r3, r1, portR3_OFFSET + lwi r2, r1, portR2_OFFSET + + /* Reload the rmsr from the stack. */ + lwi r18, r1, portMSR_OFFSET + mts rmsr, r18 + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + /* Reload the FSR from the stack. */ + lwi r18, r1, portFSR_OFFSET + mts rfsr, r18 + #endif + + /* Load the critical nesting value. */ + lwi r18, r1, portCRITICAL_NESTING_OFFSET + swi r18, r0, uxCriticalNesting + + /* Test the critical nesting value. If it is non zero then the task last + exited the running state using a yield. If it is zero, then the task + last exited the running state through an interrupt. */ + xori r18, r18, 0 + bnei r18, exit_from_yield + + /* r18 was being used as a temporary. Now restore its true value from the + stack. */ + lwi r18, r1, portR18_OFFSET + + /* Remove the stack frame. */ + addik r1, r1, portCONTEXT_SIZE + + /* Return using rtid so interrupts are re-enabled as this function is + exited. */ + rtid r14, 0 + or r0, r0, r0 + + .endm + +/* This function is used to exit portRESTORE_CONTEXT() if the task being +returned to last left the Running state by calling taskYIELD() (rather than +being preempted by an interrupt). */ + .text + .align 4 +exit_from_yield: + + /* r18 was being used as a temporary. Now restore its true value from the + stack. */ + lwi r18, r1, portR18_OFFSET + + /* Remove the stack frame. */ + addik r1, r1, portCONTEXT_SIZE + + /* Return to the task. */ + rtsd r14, 0 + or r0, r0, r0 + + + .text + .align 4 +_interrupt_handler: + + portSAVE_CONTEXT + + /* Stack the return address. */ + swi r14, r1, portR14_OFFSET + + /* Switch to the ISR stack. */ + lwi r1, r0, pulISRStack + + /* The parameter to the interrupt handler. */ + ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE + + /* Execute any pending interrupts. */ + bralid r15, XIntc_DeviceInterruptHandler + or r0, r0, r0 + + /* See if a new task should be selected to execute. */ + lwi r18, r0, ulTaskSwitchRequested + or r18, r18, r0 + + /* If ulTaskSwitchRequested is already zero, then jump straight to + restoring the task that is already in the Running state. */ + beqi r18, task_switch_not_requested + + /* Set ulTaskSwitchRequested back to zero as a task switch is about to be + performed. */ + swi r0, r0, ulTaskSwitchRequested + + /* ulTaskSwitchRequested was not 0 when tested. Select the next task to + execute. */ + bralid r15, vTaskSwitchContext + or r0, r0, r0 + +task_switch_not_requested: + + /* Restore the context of the next task scheduled to execute. */ + portRESTORE_CONTEXT + + + .text + .align 4 +VPortYieldASM: + + portSAVE_CONTEXT + + /* Modify the return address so a return is done to the instruction after + the call to VPortYieldASM. */ + addi r14, r14, 8 + swi r14, r1, portR14_OFFSET + + /* Switch to use the ISR stack. */ + lwi r1, r0, pulISRStack + + /* Select the next task to execute. */ + bralid r15, vTaskSwitchContext + or r0, r0, r0 + + /* Restore the context of the next task scheduled to execute. */ + portRESTORE_CONTEXT + + .text + .align 4 +vPortStartFirstTask: + + portRESTORE_CONTEXT + + + +#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) + + .text + .align 4 +vPortExceptionHandlerEntry: + + /* Take a copy of the stack pointer before vPortExecptionHandler is called, + storing its value prior to the function stack frame being created. */ + swi r1, r0, pulStackPointerOnFunctionEntry + bralid r15, vPortExceptionHandler + or r0, r0, r0 + +#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV8/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV8/portmacro.h new file mode 100644 index 0000000..e1118ff --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV8/portmacro.h @@ -0,0 +1,370 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* BSP includes. */ +#include +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros and functions. */ +void microblaze_disable_interrupts( void ); +void microblaze_enable_interrupts( void ); +#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts() +#define portENABLE_INTERRUPTS() microblaze_enable_interrupts() +/*-----------------------------------------------------------*/ + +/* Critical section macros. */ +void vPortEnterCritical( void ); +void vPortExitCritical( void ); +#define portENTER_CRITICAL() { \ + extern volatile UBaseType_t uxCriticalNesting; \ + microblaze_disable_interrupts(); \ + uxCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() { \ + extern volatile UBaseType_t uxCriticalNesting; \ + /* Interrupts are disabled, so we can */ \ + /* access the variable directly. */ \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + /* The nesting has unwound and we \ + can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ + } + +/*-----------------------------------------------------------*/ + +/* The yield macro maps directly to the vPortYield() function. */ +void vPortYield( void ); +#define portYIELD() vPortYield() + +/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead +sets a flag to say that a yield has been requested. The interrupt exit code +then checks this flag, and calls vTaskSwitchContext() before restoring a task +context, if the flag is not false. This is done to prevent multiple calls to +vTaskSwitchContext() being made from a single interrupt, as a single interrupt +can result in multiple peripherals being serviced. */ +extern volatile uint32_t ulTaskSwitchRequested; +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } while( 0 ) + +#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + + /* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + return ucReturn; + } + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +/* The following structure is used by the FreeRTOS exception handler. It is +filled with the MicroBlaze context as it was at the time the exception occurred. +This is done as an aid to debugging exception occurrences. */ +typedef struct PORT_REGISTER_DUMP +{ + /* The following structure members hold the values of the MicroBlaze + registers at the time the exception was raised. */ + uint32_t ulR1_SP; + uint32_t ulR2_small_data_area; + uint32_t ulR3; + uint32_t ulR4; + uint32_t ulR5; + uint32_t ulR6; + uint32_t ulR7; + uint32_t ulR8; + uint32_t ulR9; + uint32_t ulR10; + uint32_t ulR11; + uint32_t ulR12; + uint32_t ulR13_read_write_small_data_area; + uint32_t ulR14_return_address_from_interrupt; + uint32_t ulR15_return_address_from_subroutine; + uint32_t ulR16_return_address_from_trap; + uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */ + uint32_t ulR18; + uint32_t ulR19; + uint32_t ulR20; + uint32_t ulR21; + uint32_t ulR22; + uint32_t ulR23; + uint32_t ulR24; + uint32_t ulR25; + uint32_t ulR26; + uint32_t ulR27; + uint32_t ulR28; + uint32_t ulR29; + uint32_t ulR30; + uint32_t ulR31; + uint32_t ulPC; + uint32_t ulESR; + uint32_t ulMSR; + uint32_t ulEAR; + uint32_t ulFSR; + uint32_t ulEDR; + + /* A human readable description of the exception cause. The strings used + are the same as the #define constant names found in the + microblaze_exceptions_i.h header file */ + int8_t *pcExceptionCause; + + /* The human readable name of the task that was running at the time the + exception occurred. This is the name that was given to the task when the + task was created using the FreeRTOS xTaskCreate() API function. */ + char *pcCurrentTaskName; + + /* The handle of the task that was running a the time the exception + occurred. */ + void * xCurrentTaskHandle; + +} xPortRegisterDump; + + +/* + * Installs pxHandler as the interrupt handler for the peripheral specified by + * the ucInterruptID parameter. + * + * ucInterruptID: + * + * The ID of the peripheral that will have pxHandler assigned as its interrupt + * handler. Peripheral IDs are defined in the xparameters.h header file, which + * is itself part of the BSP project. For example, in the official demo + * application for this port, xparameters.h defines the following IDs for the + * four possible interrupt sources: + * + * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. + * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. + * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. + * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. + * + * + * pxHandler: + * + * A pointer to the interrupt handler function itself. This must be a void + * function that takes a (void *) parameter. + * + * + * pvCallBackRef: + * + * The parameter passed into the handler function. In many cases this will not + * be used and can be NULL. Some times it is used to pass in a reference to + * the peripheral instance variable, so it can be accessed from inside the + * handler function. + * + * + * pdPASS is returned if the function executes successfully. Any other value + * being returned indicates that the function did not execute correctly. + */ +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ); + + +/* + * Enables the interrupt, within the interrupt controller, for the peripheral + * specified by the ucInterruptID parameter. + * + * ucInterruptID: + * + * The ID of the peripheral that will have its interrupt enabled in the + * interrupt controller. Peripheral IDs are defined in the xparameters.h header + * file, which is itself part of the BSP project. For example, in the official + * demo application for this port, xparameters.h defines the following IDs for + * the four possible interrupt sources: + * + * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. + * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. + * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. + * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. + * + */ +void vPortEnableInterrupt( uint8_t ucInterruptID ); + +/* + * Disables the interrupt, within the interrupt controller, for the peripheral + * specified by the ucInterruptID parameter. + * + * ucInterruptID: + * + * The ID of the peripheral that will have its interrupt disabled in the + * interrupt controller. Peripheral IDs are defined in the xparameters.h header + * file, which is itself part of the BSP project. For example, in the official + * demo application for this port, xparameters.h defines the following IDs for + * the four possible interrupt sources: + * + * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. + * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. + * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. + * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. + * + */ +void vPortDisableInterrupt( uint8_t ucInterruptID ); + +/* + * This is an application defined callback function used to install the tick + * interrupt handler. It is provided as an application callback because the + * kernel will run on lots of different MicroBlaze and FPGA configurations - not + * all of which will have the same timer peripherals defined or available. This + * example uses the AXI Timer 0. If that is available on your hardware platform + * then this example callback implementation should not require modification. + * The name of the interrupt handler that should be installed is vPortTickISR(), + * which the function below declares as an extern. + */ +void vApplicationSetupTimerInterrupt( void ); + +/* + * This is an application defined callback function used to clear whichever + * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback + * function - in this case the interrupt generated by the AXI timer. It is + * provided as an application callback because the kernel will run on lots of + * different MicroBlaze and FPGA configurations - not all of which will have the + * same timer peripherals defined or available. This example uses the AXI Timer 0. + * If that is available on your hardware platform then this example callback + * implementation should not require modification provided the example definition + * of vApplicationSetupTimerInterrupt() is also not modified. + */ +void vApplicationClearTimerInterrupt( void ); + +/* + * vPortExceptionsInstallHandlers() is only available when the MicroBlaze + * is configured to include exception functionality, and + * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h. + * + * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler + * for every possible exception cause. + * + * vPortExceptionsInstallHandlers() can be called explicitly from application + * code. After that is done, the default FreeRTOS exception handler that will + * have been installed can be replaced for any specific exception cause by using + * the standard Xilinx library function microblaze_register_exception_handler(). + * + * If vPortExceptionsInstallHandlers() is not called explicitly by the + * application, it will be called automatically by the kernel the first time + * xPortInstallInterruptHandler() is called. At that time, any exception + * handlers that may have already been installed will be replaced. + * + * See the description of vApplicationExceptionRegisterDump() for information + * on the processing performed by the FreeRTOS exception handler. + */ +void vPortExceptionsInstallHandlers( void ); + +/* + * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined + * in portmacro.h) with the MicroBlaze context, as it was at the time the + * exception occurred. The exception handler then calls + * vApplicationExceptionRegisterDump(), passing in the completed + * xPortRegisterDump structure as its parameter. + * + * The FreeRTOS kernel provides its own implementation of + * vApplicationExceptionRegisterDump(), but the kernel provided implementation + * is declared as being 'weak'. The weak definition allows the application + * writer to provide their own implementation, should they wish to use the + * register dump information. For example, an implementation could be provided + * that wrote the register dump data to a display, or a UART port. + */ +void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ); + + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV9/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV9/port.c new file mode 100644 index 0000000..413d479 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV9/port.c @@ -0,0 +1,491 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MicroBlaze port. + *----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include + +/* Hardware includes. */ +#include +#include +#include + +/* Tasks are started with a critical section nesting of 0 - however, prior to +the scheduler being commenced interrupts should not be enabled, so the critical +nesting variable is initialised to a non-zero value. */ +#define portINITIAL_NESTING_VALUE ( 0xff ) + +/* The bit within the MSR register that enabled/disables interrupts and +exceptions respectively. */ +#define portMSR_IE ( 0x02U ) +#define portMSR_EE ( 0x100U ) + +/* If the floating point unit is included in the MicroBlaze build, then the +FSR register is saved as part of the task context. portINITIAL_FSR is the value +given to the FSR register when the initial context is set up for a task being +created. */ +#define portINITIAL_FSR ( 0U ) + +/*-----------------------------------------------------------*/ + +/* + * Initialise the interrupt controller instance. + */ +static int32_t prvInitialiseInterruptController( void ); + +/* Ensure the interrupt controller instance variable is initialised before it is + * used, and that the initialisation only happens once. + */ +static int32_t prvEnsureInterruptControllerIsInitialised( void ); + +/*-----------------------------------------------------------*/ + +/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task +maintains its own count, so this variable is saved as part of the task +context. */ +volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE; + +/* This port uses a separate stack for interrupts. This prevents the stack of +every task needing to be large enough to hold an entire interrupt stack on top +of the task stack. */ +uint32_t *pulISRStack; + +/* If an interrupt requests a context switch, then ulTaskSwitchRequested will +get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt +handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel +will call vTaskSwitchContext() to ensure the task that runs immediately after +the interrupt exists is the highest priority task that is able to run. This is +an unusual mechanism, but is used for this port because a single interrupt can +cause the servicing of multiple peripherals - and it is inefficient to call +vTaskSwitchContext() multiple times as each peripheral is serviced. */ +volatile uint32_t ulTaskSwitchRequested = 0UL; + +/* The instance of the interrupt controller used by this port. This is required +by the Xilinx library API functions. */ +static XIntc xInterruptControllerInstance; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been made. + * + * See the portable.h header file. + */ +#if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) +#else +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +#endif +{ +extern void *_SDA2_BASE_, *_SDA_BASE_; +const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_; +const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; +extern void _start1( void ); + + /* Place a few bytes of known values on the bottom of the stack. + This is essential for the Microblaze port and these lines must + not be omitted. */ + *pxTopOfStack = ( StackType_t ) 0x00000000; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00000000; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00000000; + pxTopOfStack--; + + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + /* Store the stack limits. */ + *pxTopOfStack = (StackType_t) (pxTopOfStack + 3); + pxTopOfStack--; + *pxTopOfStack = (StackType_t) pxEndOfStack; + pxTopOfStack--; + #endif + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + /* The FSR value placed in the initial task context is just 0. */ + *pxTopOfStack = portINITIAL_FSR; + pxTopOfStack--; + #endif + + /* The MSR value placed in the initial task context should have interrupts + disabled. Each task will enable interrupts automatically when it enters + the running state for the first time. */ + *pxTopOfStack = mfmsr() & ~portMSR_IE; + + #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) + { + /* Ensure exceptions are enabled for the task. */ + *pxTopOfStack |= portMSR_EE; + } + #endif + + pxTopOfStack--; + + /* First stack an initial value for the critical section nesting. This + is initialised to zero. */ + *pxTopOfStack = ( StackType_t ) 0x00; + + /* R0 is always zero. */ + /* R1 is the SP. */ + + /* Place an initial value for all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */ + + #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; /* R8 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */ + pxTopOfStack--; + #else + pxTopOfStack-= 8; + #endif + + *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */ + + #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */ + pxTopOfStack--; + #else + pxTopOfStack -= 4; + #endif + + *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */ + + #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + #else + pxTopOfStack -= 13; + #endif + + /* Return a pointer to the top of the stack that has been generated so this + can be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void ( vPortStartFirstTask )( void ); +extern uint32_t _stack[]; + + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. + + This port uses an application defined callback function to install the tick + interrupt handler because the kernel will run on lots of different + MicroBlaze and FPGA configurations - not all of which will have the same + timer peripherals defined or available. An example definition of + vApplicationSetupTimerInterrupt() is provided in the official demo + application that accompanies this port. */ + vApplicationSetupTimerInterrupt(); + + /* Reuse the stack from main() as the stack for the interrupts/exceptions. */ + pulISRStack = ( uint32_t * ) _stack; + + /* Ensure there is enough space for the functions called from the interrupt + service routines to write back into the stack frame of the caller. */ + pulISRStack -= 2; + + /* Restore the context of the first task that is going to run. From here + on, the created tasks will be executing. */ + vPortStartFirstTask(); + + /* Should not get here as the tasks are now running! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +void vPortYield( void ) +{ +extern void VPortYieldASM( void ); + + /* Perform the context switch in a critical section to assure it is + not interrupted by the tick ISR. It is not a problem to do this as + each task maintains its own interrupt status. */ + portENTER_CRITICAL(); + { + /* Jump directly to the yield function to ensure there is no + compiler generated prologue code. */ + asm volatile ( "bralid r14, VPortYieldASM \n\t" \ + "or r0, r0, r0 \n\t" ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vPortEnableInterrupt( uint8_t ucInterruptID ) +{ +int32_t lReturn; + + /* An API function is provided to enable an interrupt in the interrupt + controller because the interrupt controller instance variable is private + to this file. */ + lReturn = prvEnsureInterruptControllerIsInitialised(); + if( lReturn == pdPASS ) + { + /* Critical section protects read/modify/writer operation inside + XIntc_Enable(). */ + portENTER_CRITICAL(); + { + XIntc_Enable( &xInterruptControllerInstance, ucInterruptID ); + } + portEXIT_CRITICAL(); + } + + configASSERT( lReturn == pdPASS ); +} +/*-----------------------------------------------------------*/ + +void vPortDisableInterrupt( uint8_t ucInterruptID ) +{ +int32_t lReturn; + + /* An API function is provided to disable an interrupt in the interrupt + controller because the interrupt controller instance variable is private + to this file. */ + lReturn = prvEnsureInterruptControllerIsInitialised(); + + if( lReturn == pdPASS ) + { + XIntc_Disable( &xInterruptControllerInstance, ucInterruptID ); + } + + configASSERT( lReturn == pdPASS ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ) +{ +int32_t lReturn; + + /* An API function is provided to install an interrupt handler because the + interrupt controller instance variable is private to this file. */ + + lReturn = prvEnsureInterruptControllerIsInitialised(); + + if( lReturn == pdPASS ) + { + lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef ); + } + + if( lReturn == XST_SUCCESS ) + { + lReturn = pdPASS; + } + + configASSERT( lReturn == pdPASS ); + + return lReturn; +} +/*-----------------------------------------------------------*/ + +void vPortRemoveInterruptHandler( uint8_t ucInterruptID ) +{ +int32_t lReturn; + + /* An API function is provided to remove an interrupt handler because the + interrupt controller instance variable is private to this file. */ + + lReturn = prvEnsureInterruptControllerIsInitialised(); + + if( lReturn == pdPASS ) + { + XIntc_Disconnect( &xInterruptControllerInstance, ucInterruptID ); + } + + configASSERT( lReturn == pdPASS ); +} +/*-----------------------------------------------------------*/ + +static int32_t prvEnsureInterruptControllerIsInitialised( void ) +{ +static int32_t lInterruptControllerInitialised = pdFALSE; +int32_t lReturn; + + /* Ensure the interrupt controller instance variable is initialised before + it is used, and that the initialisation only happens once. */ + if( lInterruptControllerInitialised != pdTRUE ) + { + lReturn = prvInitialiseInterruptController(); + + if( lReturn == pdPASS ) + { + lInterruptControllerInitialised = pdTRUE; + } + } + else + { + lReturn = pdPASS; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +/* + * Handler for the timer interrupt. This is the handler that the application + * defined callback function vApplicationSetupTimerInterrupt() should install. + */ +void vPortTickISR( void *pvUnused ) +{ +extern void vApplicationClearTimerInterrupt( void ); + + /* Ensure the unused parameter does not generate a compiler warning. */ + ( void ) pvUnused; + + /* This port uses an application defined callback function to clear the tick + interrupt because the kernel will run on lots of different MicroBlaze and + FPGA configurations - not all of which will have the same timer peripherals + defined or available. An example definition of + vApplicationClearTimerInterrupt() is provided in the official demo + application that accompanies this port. */ + vApplicationClearTimerInterrupt(); + + /* Increment the RTOS tick - this might cause a task to unblock. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Force vTaskSwitchContext() to be called as the interrupt exits. */ + ulTaskSwitchRequested = 1; + } +} +/*-----------------------------------------------------------*/ + +static int32_t prvInitialiseInterruptController( void ) +{ +int32_t lStatus; + + lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE ); + + if( lStatus == XST_SUCCESS ) + { + /* Initialise the exception table. */ + Xil_ExceptionInit(); + + /* Service all pending interrupts each time the handler is entered. */ + XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION ); + + /* Install exception handlers if the MicroBlaze is configured to handle + exceptions, and the application defined constant + configINSTALL_EXCEPTION_HANDLERS is set to 1. */ + #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) + { + vPortExceptionsInstallHandlers(); + } + #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */ + + /* Start the interrupt controller. Interrupts are enabled when the + scheduler starts. */ + lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE ); + + if( lStatus == XST_SUCCESS ) + { + lStatus = pdPASS; + } + else + { + lStatus = pdFAIL; + } + } + + configASSERT( lStatus == pdPASS ); + + return lStatus; +} +/*-----------------------------------------------------------*/ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV9/port_exceptions.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV9/port_exceptions.c new file mode 100644 index 0000000..9ebfb21 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV9/port_exceptions.c @@ -0,0 +1,283 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware includes. */ +#include +#include + +/* The Xilinx library defined exception entry point stacks a number of +registers. These definitions are offsets from the stack pointer to the various +stacked register values. */ +#define portexR3_STACK_OFFSET 4 +#define portexR4_STACK_OFFSET 5 +#define portexR5_STACK_OFFSET 6 +#define portexR6_STACK_OFFSET 7 +#define portexR7_STACK_OFFSET 8 +#define portexR8_STACK_OFFSET 9 +#define portexR9_STACK_OFFSET 10 +#define portexR10_STACK_OFFSET 11 +#define portexR11_STACK_OFFSET 12 +#define portexR12_STACK_OFFSET 13 +#define portexR15_STACK_OFFSET 16 +#define portexR18_STACK_OFFSET 19 +#define portexMSR_STACK_OFFSET 20 +#define portexR19_STACK_OFFSET -1 + +/* This is defined to equal the size, in bytes, of the stack frame generated by +the Xilinx standard library exception entry point. It is required to determine +the stack pointer value prior to the exception being entered. */ +#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL + +/* The number of bytes a MicroBlaze instruction consumes. */ +#define portexINSTRUCTION_SIZE 4 + +/* Exclude this entire file if the MicroBlaze is not configured to handle +exceptions, or the application defined configuration constant +configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ +#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) + +/* This variable is set in the exception entry code, before +vPortExceptionHandler is called. */ +uint32_t *pulStackPointerOnFunctionEntry = NULL; + +/* This is the structure that is filled with the MicroBlaze context as it +existed immediately prior to the exception occurrence. A pointer to this +structure is passed into the vApplicationExceptionRegisterDump() callback +function, if one is defined. */ +static xPortRegisterDump xRegisterDump; + +/* This is the FreeRTOS exception handler that is installed for all exception +types. It is called from vPortExceptionHanlderEntry() - which is itself defined +in portasm.S. */ +void vPortExceptionHandler( void *pvExceptionID ); +extern void vPortExceptionHandlerEntry( void *pvExceptionID ); + +/*-----------------------------------------------------------*/ + +/* vApplicationExceptionRegisterDump() is a callback function that the +application can optionally define to receive a populated xPortRegisterDump +structure. If the application chooses not to define a version of +vApplicationExceptionRegisterDump() then this weekly defined default +implementation will be called instead. */ +extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak)); +void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) +{ + ( void ) xRegisterDump; + + for( ;; ) + { + portNOP(); + } +} +/*-----------------------------------------------------------*/ + +void vPortExceptionHandler( void *pvExceptionID ) +{ +extern void *pxCurrentTCB; + + /* Fill an xPortRegisterDump structure with the MicroBlaze context as it + was immediately before the exception occurrence. */ + + /* First fill in the name and handle of the task that was in the Running + state when the exception occurred. */ + xRegisterDump.xCurrentTaskHandle = pxCurrentTCB; + xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL ); + + configASSERT( pulStackPointerOnFunctionEntry ); + + /* Obtain the values of registers that were stacked prior to this function + being called, and may have changed since they were stacked. */ + xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ]; + xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ]; + xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ]; + xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ]; + xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ]; + xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ]; + xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ]; + xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ]; + xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ]; + xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ]; + xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ]; + xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ]; + xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ]; + xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ]; + + /* Obtain the value of all other registers. */ + xRegisterDump.ulR2_small_data_area = mfgpr( R2 ); + xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 ); + xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 ); + xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 ); + xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 ); + xRegisterDump.ulR20 = mfgpr( R20 ); + xRegisterDump.ulR21 = mfgpr( R21 ); + xRegisterDump.ulR22 = mfgpr( R22 ); + xRegisterDump.ulR23 = mfgpr( R23 ); + xRegisterDump.ulR24 = mfgpr( R24 ); + xRegisterDump.ulR25 = mfgpr( R25 ); + xRegisterDump.ulR26 = mfgpr( R26 ); + xRegisterDump.ulR27 = mfgpr( R27 ); + xRegisterDump.ulR28 = mfgpr( R28 ); + xRegisterDump.ulR29 = mfgpr( R29 ); + xRegisterDump.ulR30 = mfgpr( R30 ); + xRegisterDump.ulR31 = mfgpr( R31 ); + xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE; + xRegisterDump.ulEAR = mfear(); + xRegisterDump.ulESR = mfesr(); + xRegisterDump.ulEDR = mfedr(); + + /* Move the saved program counter back to the instruction that was executed + when the exception occurred. This is only valid for certain types of + exception. */ + xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE; + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + { + xRegisterDump.ulFSR = mffsr(); + } + #else + { + xRegisterDump.ulFSR = 0UL; + } + #endif + + /* Also fill in a string that describes what type of exception this is. + The string uses the same ID names as defined in the MicroBlaze standard + library exception header files. */ + switch( ( uint32_t ) pvExceptionID ) + { + case XEXC_ID_FSL : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL"; + break; + + case XEXC_ID_UNALIGNED_ACCESS : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS"; + break; + + case XEXC_ID_ILLEGAL_OPCODE : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE"; + break; + + case XEXC_ID_M_AXI_I_EXCEPTION : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION"; + break; + + case XEXC_ID_M_AXI_D_EXCEPTION : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION"; + break; + + case XEXC_ID_DIV_BY_ZERO : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO"; + break; + + case XEXC_ID_STACK_VIOLATION : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU"; + break; + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + + case XEXC_ID_FPU : + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value"; + break; + + #endif /* XPAR_MICROBLAZE_USE_FPU */ + } + + /* vApplicationExceptionRegisterDump() is a callback function that the + application can optionally define to receive the populated xPortRegisterDump + structure. If the application chooses not to define a version of + vApplicationExceptionRegisterDump() then the weekly defined default + implementation within this file will be called instead. */ + vApplicationExceptionRegisterDump( &xRegisterDump ); + + /* Must not attempt to leave this function! */ + for( ;; ) + { + portNOP(); + } +} +/*-----------------------------------------------------------*/ + +void vPortExceptionsInstallHandlers( void ) +{ +static uint32_t ulHandlersAlreadyInstalled = pdFALSE; + + if( ulHandlersAlreadyInstalled == pdFALSE ) + { + ulHandlersAlreadyInstalled = pdTRUE; + + #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1 + microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS ); + #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/ + + #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE ); + #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */ + + #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO ); + #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */ + + #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU ); + #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */ + + #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL ); + #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */ + + microblaze_enable_exceptions(); + } +} + +/* Exclude the entire file if the MicroBlaze is not configured to handle +exceptions, or the application defined configuration item +configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ +#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV9/portasm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV9/portasm.S new file mode 100644 index 0000000..17f3ebd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV9/portasm.S @@ -0,0 +1,376 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/* Xilinx library includes. */ +#include "microblaze_exceptions_g.h" +#include "xparameters.h" + +/* Offsets from the stack pointer at which saved registers are placed. */ +#define portR31_OFFSET 4 +#define portR30_OFFSET 8 +#define portR29_OFFSET 12 +#define portR28_OFFSET 16 +#define portR27_OFFSET 20 +#define portR26_OFFSET 24 +#define portR25_OFFSET 28 +#define portR24_OFFSET 32 +#define portR23_OFFSET 36 +#define portR22_OFFSET 40 +#define portR21_OFFSET 44 +#define portR20_OFFSET 48 +#define portR19_OFFSET 52 +#define portR18_OFFSET 56 +#define portR17_OFFSET 60 +#define portR16_OFFSET 64 +#define portR15_OFFSET 68 +#define portR14_OFFSET 72 +#define portR13_OFFSET 76 +#define portR12_OFFSET 80 +#define portR11_OFFSET 84 +#define portR10_OFFSET 88 +#define portR9_OFFSET 92 +#define portR8_OFFSET 96 +#define portR7_OFFSET 100 +#define portR6_OFFSET 104 +#define portR5_OFFSET 108 +#define portR4_OFFSET 112 +#define portR3_OFFSET 116 +#define portR2_OFFSET 120 +#define portCRITICAL_NESTING_OFFSET 124 +#define portMSR_OFFSET 128 + +#if( XPAR_MICROBLAZE_USE_FPU != 0 ) + #define portFSR_OFFSET 132 + #if( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) + #define portSLR_OFFSET 136 + #define portSHR_OFFSET 140 + + #define portCONTEXT_SIZE 144 + #define portMINUS_CONTEXT_SIZE -144 + #else + #define portCONTEXT_SIZE 136 + #define portMINUS_CONTEXT_SIZE -136 + #endif +#else + #if( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) + #define portSLR_OFFSET 132 + #define portSHR_OFFSET 136 + + #define portCONTEXT_SIZE 140 + #define portMINUS_CONTEXT_SIZE -140 + #else + #define portCONTEXT_SIZE 132 + #define portMINUS_CONTEXT_SIZE -132 + #endif +#endif + + .extern pxCurrentTCB + .extern XIntc_DeviceInterruptHandler + .extern vTaskSwitchContext + .extern uxCriticalNesting + .extern pulISRStack + .extern ulTaskSwitchRequested + .extern vPortExceptionHandler + .extern pulStackPointerOnFunctionEntry + + .global _interrupt_handler + .global VPortYieldASM + .global vPortStartFirstTask + .global vPortExceptionHandlerEntry + + +.macro portSAVE_CONTEXT + + /* Make room for the context on the stack. */ + addik r1, r1, portMINUS_CONTEXT_SIZE + + /* Stack general registers. */ + swi r31, r1, portR31_OFFSET + swi r30, r1, portR30_OFFSET + swi r29, r1, portR29_OFFSET + swi r28, r1, portR28_OFFSET + swi r27, r1, portR27_OFFSET + swi r26, r1, portR26_OFFSET + swi r25, r1, portR25_OFFSET + swi r24, r1, portR24_OFFSET + swi r23, r1, portR23_OFFSET + swi r22, r1, portR22_OFFSET + swi r21, r1, portR21_OFFSET + swi r20, r1, portR20_OFFSET + swi r19, r1, portR19_OFFSET + swi r18, r1, portR18_OFFSET + swi r17, r1, portR17_OFFSET + swi r16, r1, portR16_OFFSET + swi r15, r1, portR15_OFFSET + /* R14 is saved later as it needs adjustment if a yield is performed. */ + swi r13, r1, portR13_OFFSET + swi r12, r1, portR12_OFFSET + swi r11, r1, portR11_OFFSET + swi r10, r1, portR10_OFFSET + swi r9, r1, portR9_OFFSET + swi r8, r1, portR8_OFFSET + swi r7, r1, portR7_OFFSET + swi r6, r1, portR6_OFFSET + swi r5, r1, portR5_OFFSET + swi r4, r1, portR4_OFFSET + swi r3, r1, portR3_OFFSET + swi r2, r1, portR2_OFFSET + + /* Stack the critical section nesting value. */ + lwi r18, r0, uxCriticalNesting + swi r18, r1, portCRITICAL_NESTING_OFFSET + + /* Stack MSR. */ + mfs r18, rmsr + swi r18, r1, portMSR_OFFSET + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + /* Stack FSR. */ + mfs r18, rfsr + swi r18, r1, portFSR_OFFSET + #endif + +#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) + /* Save the stack limits */ + mfs r18, rslr + swi r18, r1, portSLR_OFFSET + mfs r18, rshr + swi r18, r1, portSHR_OFFSET +#endif + + /* Save the top of stack value to the TCB. */ + lwi r3, r0, pxCurrentTCB + sw r1, r0, r3 + + .endm + +.macro portRESTORE_CONTEXT + + /* Load the top of stack value from the TCB. */ + lwi r18, r0, pxCurrentTCB + lw r1, r0, r18 + +#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) + /* Restore the stack limits -- must not load from r1 (Stack Pointer) + because if the address of load or store instruction is out of range, + it will trigger Stack Protection Violation exception. */ + or r18, r0, r1 + lwi r12, r18, portSLR_OFFSET + mts rslr, r12 + lwi r12, r18, portSHR_OFFSET + mts rshr, r12 +#endif + + /* Restore the general registers. */ + lwi r31, r1, portR31_OFFSET + lwi r30, r1, portR30_OFFSET + lwi r29, r1, portR29_OFFSET + lwi r28, r1, portR28_OFFSET + lwi r27, r1, portR27_OFFSET + lwi r26, r1, portR26_OFFSET + lwi r25, r1, portR25_OFFSET + lwi r24, r1, portR24_OFFSET + lwi r23, r1, portR23_OFFSET + lwi r22, r1, portR22_OFFSET + lwi r21, r1, portR21_OFFSET + lwi r20, r1, portR20_OFFSET + lwi r19, r1, portR19_OFFSET + lwi r17, r1, portR17_OFFSET + lwi r16, r1, portR16_OFFSET + lwi r15, r1, portR15_OFFSET + lwi r14, r1, portR14_OFFSET + lwi r13, r1, portR13_OFFSET + lwi r12, r1, portR12_OFFSET + lwi r11, r1, portR11_OFFSET + lwi r10, r1, portR10_OFFSET + lwi r9, r1, portR9_OFFSET + lwi r8, r1, portR8_OFFSET + lwi r7, r1, portR7_OFFSET + lwi r6, r1, portR6_OFFSET + lwi r5, r1, portR5_OFFSET + lwi r4, r1, portR4_OFFSET + lwi r3, r1, portR3_OFFSET + lwi r2, r1, portR2_OFFSET + + /* Reload the rmsr from the stack. */ + lwi r18, r1, portMSR_OFFSET + mts rmsr, r18 + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + /* Reload the FSR from the stack. */ + lwi r18, r1, portFSR_OFFSET + mts rfsr, r18 + #endif + + /* Load the critical nesting value. */ + lwi r18, r1, portCRITICAL_NESTING_OFFSET + swi r18, r0, uxCriticalNesting + + /* Test the critical nesting value. If it is non zero then the task last + exited the running state using a yield. If it is zero, then the task + last exited the running state through an interrupt. */ + xori r18, r18, 0 + bnei r18, exit_from_yield + + /* r18 was being used as a temporary. Now restore its true value from the + stack. */ + lwi r18, r1, portR18_OFFSET + + /* Remove the stack frame. */ + addik r1, r1, portCONTEXT_SIZE + + /* Return using rtid so interrupts are re-enabled as this function is + exited. */ + rtid r14, 0 + or r0, r0, r0 + + .endm + +/* This function is used to exit portRESTORE_CONTEXT() if the task being +returned to last left the Running state by calling taskYIELD() (rather than +being preempted by an interrupt). */ + .text + .align 4 +exit_from_yield: + + /* r18 was being used as a temporary. Now restore its true value from the + stack. */ + lwi r18, r1, portR18_OFFSET + + /* Remove the stack frame. */ + addik r1, r1, portCONTEXT_SIZE + + /* Return to the task. */ + rtsd r14, 0 + or r0, r0, r0 + + + .text + .align 4 +_interrupt_handler: + + portSAVE_CONTEXT + + /* Stack the return address. */ + swi r14, r1, portR14_OFFSET + + /* Switch to the ISR stack. */ + lwi r1, r0, pulISRStack + +#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) + ori r18, r0, _stack_end + mts rslr, r18 + ori r18, r0, _stack + mts rshr, r18 +#endif + + /* The parameter to the interrupt handler. */ + ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE + + /* Execute any pending interrupts. */ + bralid r15, XIntc_DeviceInterruptHandler + or r0, r0, r0 + + /* See if a new task should be selected to execute. */ + lwi r18, r0, ulTaskSwitchRequested + or r18, r18, r0 + + /* If ulTaskSwitchRequested is already zero, then jump straight to + restoring the task that is already in the Running state. */ + beqi r18, task_switch_not_requested + + /* Set ulTaskSwitchRequested back to zero as a task switch is about to be + performed. */ + swi r0, r0, ulTaskSwitchRequested + + /* ulTaskSwitchRequested was not 0 when tested. Select the next task to + execute. */ + bralid r15, vTaskSwitchContext + or r0, r0, r0 + +task_switch_not_requested: + + /* Restore the context of the next task scheduled to execute. */ + portRESTORE_CONTEXT + + + .text + .align 4 +VPortYieldASM: + + portSAVE_CONTEXT + + /* Modify the return address so a return is done to the instruction after + the call to VPortYieldASM. */ + addi r14, r14, 8 + swi r14, r1, portR14_OFFSET + + /* Switch to use the ISR stack. */ + lwi r1, r0, pulISRStack + +#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) + ori r18, r0, _stack_end + mts rslr, r18 + ori r18, r0, _stack + mts rshr, r18 +#endif + + /* Select the next task to execute. */ + bralid r15, vTaskSwitchContext + or r0, r0, r0 + + /* Restore the context of the next task scheduled to execute. */ + portRESTORE_CONTEXT + + .text + .align 4 +vPortStartFirstTask: + + portRESTORE_CONTEXT + + + +#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) + + .text + .align 4 +vPortExceptionHandlerEntry: + + /* Take a copy of the stack pointer before vPortExecptionHandler is called, + storing its value prior to the function stack frame being created. */ + swi r1, r0, pulStackPointerOnFunctionEntry + bralid r15, vPortExceptionHandler + or r0, r0, r0 + +#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV9/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV9/portmacro.h new file mode 100644 index 0000000..a510aad --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/MicroBlazeV9/portmacro.h @@ -0,0 +1,375 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* BSP includes. */ +#include +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros and functions. */ +void microblaze_disable_interrupts( void ); +void microblaze_enable_interrupts( void ); +#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts() +#define portENABLE_INTERRUPTS() microblaze_enable_interrupts() +/*-----------------------------------------------------------*/ + +/* Critical section macros. */ +void vPortEnterCritical( void ); +void vPortExitCritical( void ); +#define portENTER_CRITICAL() { \ + extern volatile UBaseType_t uxCriticalNesting; \ + microblaze_disable_interrupts(); \ + uxCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() { \ + extern volatile UBaseType_t uxCriticalNesting; \ + /* Interrupts are disabled, so we can */ \ + /* access the variable directly. */ \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + /* The nesting has unwound and we \ + can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ + } + +/*-----------------------------------------------------------*/ + +/* The yield macro maps directly to the vPortYield() function. */ +void vPortYield( void ); +#define portYIELD() vPortYield() + +/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead +sets a flag to say that a yield has been requested. The interrupt exit code +then checks this flag, and calls vTaskSwitchContext() before restoring a task +context, if the flag is not false. This is done to prevent multiple calls to +vTaskSwitchContext() being made from a single interrupt, as a single interrupt +can result in multiple peripherals being serviced. */ +extern volatile uint32_t ulTaskSwitchRequested; +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } while( 0 ) + +#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + + /* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + return ucReturn; + } + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) +#define portHAS_STACK_OVERFLOW_CHECKING 1 +#endif +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +/* The following structure is used by the FreeRTOS exception handler. It is +filled with the MicroBlaze context as it was at the time the exception occurred. +This is done as an aid to debugging exception occurrences. */ +typedef struct PORT_REGISTER_DUMP +{ + /* The following structure members hold the values of the MicroBlaze + registers at the time the exception was raised. */ + uint32_t ulR1_SP; + uint32_t ulR2_small_data_area; + uint32_t ulR3; + uint32_t ulR4; + uint32_t ulR5; + uint32_t ulR6; + uint32_t ulR7; + uint32_t ulR8; + uint32_t ulR9; + uint32_t ulR10; + uint32_t ulR11; + uint32_t ulR12; + uint32_t ulR13_read_write_small_data_area; + uint32_t ulR14_return_address_from_interrupt; + uint32_t ulR15_return_address_from_subroutine; + uint32_t ulR16_return_address_from_trap; + uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */ + uint32_t ulR18; + uint32_t ulR19; + uint32_t ulR20; + uint32_t ulR21; + uint32_t ulR22; + uint32_t ulR23; + uint32_t ulR24; + uint32_t ulR25; + uint32_t ulR26; + uint32_t ulR27; + uint32_t ulR28; + uint32_t ulR29; + uint32_t ulR30; + uint32_t ulR31; + uint32_t ulPC; + uint32_t ulESR; + uint32_t ulMSR; + uint32_t ulEAR; + uint32_t ulFSR; + uint32_t ulEDR; + + /* A human readable description of the exception cause. The strings used + are the same as the #define constant names found in the + microblaze_exceptions_i.h header file */ + int8_t *pcExceptionCause; + + /* The human readable name of the task that was running at the time the + exception occurred. This is the name that was given to the task when the + task was created using the FreeRTOS xTaskCreate() API function. */ + char *pcCurrentTaskName; + + /* The handle of the task that was running a the time the exception + occurred. */ + void * xCurrentTaskHandle; + +} xPortRegisterDump; + + +/* + * Installs pxHandler as the interrupt handler for the peripheral specified by + * the ucInterruptID parameter. + * + * ucInterruptID: + * + * The ID of the peripheral that will have pxHandler assigned as its interrupt + * handler. Peripheral IDs are defined in the xparameters.h header file, which + * is itself part of the BSP project. For example, in the official demo + * application for this port, xparameters.h defines the following IDs for the + * four possible interrupt sources: + * + * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. + * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. + * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. + * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. + * + * + * pxHandler: + * + * A pointer to the interrupt handler function itself. This must be a void + * function that takes a (void *) parameter. + * + * + * pvCallBackRef: + * + * The parameter passed into the handler function. In many cases this will not + * be used and can be NULL. Some times it is used to pass in a reference to + * the peripheral instance variable, so it can be accessed from inside the + * handler function. + * + * + * pdPASS is returned if the function executes successfully. Any other value + * being returned indicates that the function did not execute correctly. + */ +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ); + + +/* + * Enables the interrupt, within the interrupt controller, for the peripheral + * specified by the ucInterruptID parameter. + * + * ucInterruptID: + * + * The ID of the peripheral that will have its interrupt enabled in the + * interrupt controller. Peripheral IDs are defined in the xparameters.h header + * file, which is itself part of the BSP project. For example, in the official + * demo application for this port, xparameters.h defines the following IDs for + * the four possible interrupt sources: + * + * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. + * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. + * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. + * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. + * + */ +void vPortEnableInterrupt( uint8_t ucInterruptID ); + +/* + * Disables the interrupt, within the interrupt controller, for the peripheral + * specified by the ucInterruptID parameter. + * + * ucInterruptID: + * + * The ID of the peripheral that will have its interrupt disabled in the + * interrupt controller. Peripheral IDs are defined in the xparameters.h header + * file, which is itself part of the BSP project. For example, in the official + * demo application for this port, xparameters.h defines the following IDs for + * the four possible interrupt sources: + * + * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. + * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. + * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. + * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. + * + */ +void vPortDisableInterrupt( uint8_t ucInterruptID ); + +/* + * This is an application defined callback function used to install the tick + * interrupt handler. It is provided as an application callback because the + * kernel will run on lots of different MicroBlaze and FPGA configurations - not + * all of which will have the same timer peripherals defined or available. This + * example uses the AXI Timer 0. If that is available on your hardware platform + * then this example callback implementation should not require modification. + * The name of the interrupt handler that should be installed is vPortTickISR(), + * which the function below declares as an extern. + */ +void vApplicationSetupTimerInterrupt( void ); + +/* + * This is an application defined callback function used to clear whichever + * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback + * function - in this case the interrupt generated by the AXI timer. It is + * provided as an application callback because the kernel will run on lots of + * different MicroBlaze and FPGA configurations - not all of which will have the + * same timer peripherals defined or available. This example uses the AXI Timer 0. + * If that is available on your hardware platform then this example callback + * implementation should not require modification provided the example definition + * of vApplicationSetupTimerInterrupt() is also not modified. + */ +void vApplicationClearTimerInterrupt( void ); + +/* + * vPortExceptionsInstallHandlers() is only available when the MicroBlaze + * is configured to include exception functionality, and + * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h. + * + * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler + * for every possible exception cause. + * + * vPortExceptionsInstallHandlers() can be called explicitly from application + * code. After that is done, the default FreeRTOS exception handler that will + * have been installed can be replaced for any specific exception cause by using + * the standard Xilinx library function microblaze_register_exception_handler(). + * + * If vPortExceptionsInstallHandlers() is not called explicitly by the + * application, it will be called automatically by the kernel the first time + * xPortInstallInterruptHandler() is called. At that time, any exception + * handlers that may have already been installed will be replaced. + * + * See the description of vApplicationExceptionRegisterDump() for information + * on the processing performed by the FreeRTOS exception handler. + */ +void vPortExceptionsInstallHandlers( void ); + +/* + * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined + * in portmacro.h) with the MicroBlaze context, as it was at the time the + * exception occurred. The exception handler then calls + * vApplicationExceptionRegisterDump(), passing in the completed + * xPortRegisterDump structure as its parameter. + * + * The FreeRTOS kernel provides its own implementation of + * vApplicationExceptionRegisterDump(), but the kernel provided implementation + * is declared as being 'weak'. The weak definition allows the application + * writer to provide their own implementation, should they wish to use the + * register dump information. For example, an implementation could be provided + * that wrote the register dump data to a display, or a UART port. + */ +void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ); + + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/NiosII/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/NiosII/port.c new file mode 100644 index 0000000..4ba3d26 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/NiosII/port.c @@ -0,0 +1,209 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the NIOS2 port. + *----------------------------------------------------------*/ + +/* Standard Includes. */ +#include +#include + +/* Altera includes. */ +#include "sys/alt_irq.h" +#include "sys/alt_exceptions.h" +#include "altera_avalon_timer_regs.h" +#include "priv/alt_irq_table.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Interrupts are enabled. */ +#define portINITIAL_ESTATUS ( StackType_t ) 0x01 + +int _alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags); +/*-----------------------------------------------------------*/ + +/* + * Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * Call back for the alarm function. + */ +void vPortSysTickHandler( void * context); + +/*-----------------------------------------------------------*/ + +static void prvReadGp( uint32_t *ulValue ) +{ + asm( "stw gp, (%0)" :: "r"(ulValue) ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxFramePointer = pxTopOfStack - 1; +StackType_t xGlobalPointer; + + prvReadGp( &xGlobalPointer ); + + /* End of stack marker. */ + *pxTopOfStack = 0xdeadbeef; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) pxFramePointer; + pxTopOfStack--; + + *pxTopOfStack = xGlobalPointer; + + /* Space for R23 to R16. */ + pxTopOfStack -= 9; + + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_ESTATUS; + + /* Space for R15 to R5. */ + pxTopOfStack -= 12; + + *pxTopOfStack = ( StackType_t ) pvParameters; + + /* Space for R3 to R1, muldiv and RA. */ + pxTopOfStack -= 5; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + asm volatile ( " movia r2, restore_sp_from_pxCurrentTCB \n" + " jmp r2 " ); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the NIOS2 port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Try to register the interrupt handler. */ + if ( -EINVAL == _alt_ic_isr_register( SYS_CLK_IRQ_INTERRUPT_CONTROLLER_ID, SYS_CLK_IRQ, vPortSysTickHandler, 0x0, 0x0 ) ) + { + /* Failed to install the Interrupt Handler. */ + asm( "break" ); + } + else + { + /* Configure SysTick to interrupt at the requested rate. */ + IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK ); + IOWR_ALTERA_AVALON_TIMER_PERIODL( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) & 0xFFFF ); + IOWR_ALTERA_AVALON_TIMER_PERIODH( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) >> 16 ); + IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_ITO_MSK ); + } + + /* Clear any already pending interrupts generated by the Timer. */ + IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK ); +} +/*-----------------------------------------------------------*/ + +void vPortSysTickHandler( void * context) +{ + /* Increment the kernel tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Clear the interrupt. */ + IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK ); +} +/*-----------------------------------------------------------*/ + +/** This function is a re-implementation of the Altera provided function. + * The function is re-implemented to prevent it from enabling an interrupt + * when it is registered. Interrupts should only be enabled after the FreeRTOS.org + * kernel has its scheduler started so that contexts are saved and switched + * correctly. + */ +int _alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + int rc = -EINVAL; + alt_irq_context status; + int id = irq; /* IRQ interpreted as the interrupt ID. */ + + if (id < ALT_NIRQ) + { + /* + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all (); + + alt_irq[id].handler = isr; + alt_irq[id].context = isr_context; + + rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id); + + /* alt_irq_enable_all(status); This line is removed to prevent the interrupt from being immediately enabled. */ + } + + return rc; +} +/*-----------------------------------------------------------*/ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/NiosII/port_asm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/NiosII/port_asm.S new file mode 100644 index 0000000..fe98458 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/NiosII/port_asm.S @@ -0,0 +1,139 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +.extern vTaskSwitchContext + +.set noat + +# Exported to start the first task. +.globl restore_sp_from_pxCurrentTCB + +# Entry point for exceptions. +.section .exceptions.entry.user, "xa" + +# Save the entire context of a task. +save_context: + addi sp, sp, -116 # Create space on the stack. + stw ra, 0(sp) + # Leave a gap for muldiv 0 + stw at, 8(sp) + stw r2, 12(sp) + stw r3, 16(sp) + stw r4, 20(sp) + stw r5, 24(sp) + stw r6, 28(sp) + stw r7, 32(sp) + stw r8, 36(sp) + stw r9, 40(sp) + stw r10, 44(sp) + stw r11, 48(sp) + stw r12, 52(sp) + stw r13, 56(sp) + stw r14, 60(sp) + stw r15, 64(sp) + rdctl r5, estatus # Save the eStatus + stw r5, 68(sp) + addi r15, ea, -4 # Instruction that caused exception + stw r15, 72(sp) # Save as EA + stw r16, 76(sp) # Save the remaining registers + stw r17, 80(sp) + stw r18, 84(sp) + stw r19, 88(sp) + stw r20, 92(sp) + stw r21, 96(sp) + stw r22, 100(sp) + stw r23, 104(sp) + stw gp, 108(sp) + stw fp, 112(sp) + +save_sp_to_pxCurrentTCB: + movia et, pxCurrentTCB # Load the address of the pxCurrentTCB pointer + ldw et, (et) # Load the value of the pxCurrentTCB pointer + stw sp, (et) # Store the stack pointer into the top of the TCB + + br irq_test_user # skip the section .exceptions.entry + + .section .exceptions.irqtest, "xa" +irq_test_user: + + .section .exceptions.exit.user, "xa" +restore_sp_from_pxCurrentTCB: + movia et, pxCurrentTCB # Load the address of the pxCurrentTCB pointer + ldw et, (et) # Load the value of the pxCurrentTCB pointer + ldw sp, (et) # Load the stack pointer with the top value of the TCB + +restore_context: + ldw ra, 0(sp) # Restore the registers. + # Leave a gap for muldiv 0. + ldw at, 8(sp) + ldw r2, 12(sp) + ldw r3, 16(sp) + ldw r4, 20(sp) + ldw r5, 24(sp) + ldw r6, 28(sp) + ldw r7, 32(sp) + ldw r8, 36(sp) + ldw r9, 40(sp) + ldw r10, 44(sp) + ldw r11, 48(sp) + ldw r12, 52(sp) + ldw r13, 56(sp) + ldw r14, 60(sp) + ldw r15, 64(sp) + ldw et, 68(sp) # Load the eStatus + wrctl estatus, et # Write the eStatus + ldw ea, 72(sp) # Load the Program Counter + ldw r16, 76(sp) + ldw r17, 80(sp) + ldw r18, 84(sp) + ldw r19, 88(sp) + ldw r20, 92(sp) + ldw r21, 96(sp) + ldw r22, 100(sp) + ldw r23, 104(sp) + ldw gp, 108(sp) + ldw fp, 112(sp) + addi sp, sp, 116 # Release stack space + + eret # Return to address ea, loading eStatus into Status. + + .section .exceptions.soft, "xa" +soft_exceptions: + movhi r3, 0x003b /* upper half of trap opcode */ + ori r3, r3, 0x683a /* lower half of trap opcode */ + beq r2, r3, call_scheduler + br exceptions_unknown_user # its something else + +call_scheduler: + stw ea, 72(sp) # EA is PC+4 so will skip over instruction causing exception + call vTaskSwitchContext # Pick the next context. + br restore_sp_from_pxCurrentTCB # Switch in the task context and restore. + + .section .exceptions.unknown.user +exceptions_unknown_user: + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/NiosII/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/NiosII/portmacro.h new file mode 100644 index 0000000..07e1a12 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/NiosII/portmacro.h @@ -0,0 +1,110 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sys/alt_irq.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() asm volatile ( "NOP" ) +#define portCRITICAL_NESTING_IN_TCB 1 +/*-----------------------------------------------------------*/ + +extern void vTaskSwitchContext( void ); +#define portYIELD() asm volatile ( "trap" ); +#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 ) + + +/* Include the port_asm.S file where the Context saving/restoring is defined. */ +__asm__( "\n\t.globl save_context" ); + +/*-----------------------------------------------------------*/ + +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); + +#define portDISABLE_INTERRUPTS() alt_irq_disable_all() +#define portENABLE_INTERRUPTS() alt_irq_enable_all( 0x01 ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC405_Xilinx/FPU_Macros.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC405_Xilinx/FPU_Macros.h new file mode 100644 index 0000000..a9e37b5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC405_Xilinx/FPU_Macros.h @@ -0,0 +1,46 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* When switching out a task, if the task tag contains a buffer address then +save the flop context into the buffer. */ +#define traceTASK_SWITCHED_OUT() \ + if( pxCurrentTCB->pxTaskTag != NULL ) \ + { \ + extern void vPortSaveFPURegisters( void * ); \ + vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ + } + +/* When switching in a task, if the task tag contains a buffer address then +load the flop context from the buffer. */ +#define traceTASK_SWITCHED_IN() \ + if( pxCurrentTCB->pxTaskTag != NULL ) \ + { \ + extern void vPortRestoreFPURegisters( void * ); \ + vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ + } + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC405_Xilinx/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC405_Xilinx/port.c new file mode 100644 index 0000000..1cf424e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC405_Xilinx/port.c @@ -0,0 +1,261 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PPC405 port. + *----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "xtime_l.h" +#include "xintc.h" +#include "xintc_i.h" + +/*-----------------------------------------------------------*/ + +/* Definitions to set the initial MSR of each task. */ +#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL ) +#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL ) +#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL ) + +#if configUSE_FPU == 1 + #define portAPU_PRESENT ( 1UL << 25UL ) + #define portFCM_FPU_PRESENT ( 1UL << 13UL ) +#else + #define portAPU_PRESENT ( 0UL ) + #define portFCM_FPU_PRESENT ( 0UL ) +#endif + +#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT ) + + +extern const unsigned _SDA_BASE_; +extern const unsigned _SDA2_BASE_; + +/*-----------------------------------------------------------*/ + +/* + * Setup the system timer to generate the tick interrupt. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The handler for the tick interrupt - defined in portasm.s. + */ +extern void vPortTickISR( void ); + +/* + * The handler for the yield function - defined in portasm.s. + */ +extern void vPortYield( void ); + +/* + * Function to start the scheduler running by starting the highest + * priority task that has thus far been created. + */ +extern void vPortStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* Structure used to hold the state of the interrupt controller. */ +static XIntc xInterruptController; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if the task had been + * interrupted. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Place a known value at the bottom of the stack for debugging. */ + *pxTopOfStack = 0xDEADBEEF; + pxTopOfStack--; + + /* EABI stack frame. */ + pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */ + + /* Parameters in R13. */ + *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */ + pxTopOfStack -= 10; + + /* Parameters in R3. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + /* Parameters in R2. */ + *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */ + pxTopOfStack--; + + /* R1 is the stack pointer so is omitted. */ + + *pxTopOfStack = 0x10000001UL;; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* USPRG0. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* CR. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* XER. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* CTR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_MSR;/* SRR1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL;/* Backchain. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + prvSetupTimerInterrupt(); + XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 ); + vPortStartFirstTask(); + + /* Should not get here as the tasks are now running! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. + */ +static void prvSetupTimerInterrupt( void ) +{ +const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL ); + + XTime_PITClearInterrupt(); + XTime_FITClearInterrupt(); + XTime_WDTClearInterrupt(); + XTime_WDTDisableInterrupt(); + XTime_FITDisableInterrupt(); + + XExc_RegisterHandler( XEXC_ID_PIT_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 ); + + XTime_PITEnableAutoReload(); + XTime_PITSetInterval( ulInterval ); + XTime_PITEnableInterrupt(); +} +/*-----------------------------------------------------------*/ + +void vPortISRHandler( void *pvNullDoNotUse ) +{ +uint32_t ulInterruptStatus, ulInterruptMask = 1UL; +BaseType_t xInterruptNumber; +XIntc_Config *pxInterruptController; +XIntc_VectorTableEntry *pxTable; + + /* Just to remove compiler warning. */ + ( void ) pvNullDoNotUse; + + /* Get the configuration by using the device ID - in this case it is + assumed that only one interrupt controller is being used. */ + pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ]; + + /* Which interrupts are pending? */ + ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress ); + + for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ ) + { + if( ulInterruptStatus & 0x01UL ) + { + /* Clear the pending interrupt. */ + XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask ); + + /* Call the registered handler. */ + pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] ); + pxTable->Handler( pxTable->CallBackRef ); + } + + /* Check the next interrupt. */ + ulInterruptMask <<= 0x01UL; + ulInterruptStatus >>= 0x01UL; + + /* Have we serviced all interrupts? */ + if( ulInterruptStatus == 0UL ) + { + break; + } + } +} +/*-----------------------------------------------------------*/ + +void vPortSetupInterruptController( void ) +{ +extern void vPortISRWrapper( void ); + + /* Perform all library calls necessary to initialise the exception table + and interrupt controller. This assumes only one interrupt controller is in + use. */ + XExc_mDisableExceptions( XEXC_NON_CRITICAL ); + XExc_Init(); + + /* The library functions save the context - we then jump to a wrapper to + save the stack into the TCB. The wrapper then calls the handler defined + above. */ + XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL ); + XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID ); + XIntc_Start( &xInterruptController, XIN_REAL_MODE ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ) +{ +BaseType_t xReturn = pdFAIL; + + /* This function is defined here so the scope of xInterruptController can + remain within this file. */ + + if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) ) + { + XIntc_Enable( &xInterruptController, ucInterruptID ); + xReturn = pdPASS; + } + + return xReturn; +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC405_Xilinx/portasm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC405_Xilinx/portasm.S new file mode 100644 index 0000000..a08bcbe --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC405_Xilinx/portasm.S @@ -0,0 +1,383 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern xTaskIncrementTick + .extern vPortISRHandler + + .global vPortStartFirstTask + .global vPortYield + .global vPortTickISR + .global vPortISRWrapper + .global vPortSaveFPURegisters + .global vPortRestoreFPURegisters + +.set BChainField, 0 +.set NextLRField, BChainField + 4 +.set MSRField, NextLRField + 4 +.set PCField, MSRField + 4 +.set LRField, PCField + 4 +.set CTRField, LRField + 4 +.set XERField, CTRField + 4 +.set CRField, XERField + 4 +.set USPRG0Field, CRField + 4 +.set r0Field, USPRG0Field + 4 +.set r2Field, r0Field + 4 +.set r3r31Field, r2Field + 4 +.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4 + + +.macro portSAVE_STACK_POINTER_AND_LR + + /* Get the address of the TCB. */ + xor R0, R0, R0 + addis R2, R0, pxCurrentTCB@ha + lwz R2, pxCurrentTCB@l( R2 ) + + /* Store the stack pointer into the TCB */ + stw SP, 0( R2 ) + + /* Save the link register */ + stwu R1, -24( R1 ) + mflr R0 + stw R31, 20( R1 ) + stw R0, 28( R1 ) + mr R31, r1 + +.endm + +.macro portRESTORE_STACK_POINTER_AND_LR + + /* Restore the link register */ + lwz R11, 0( R1 ) + lwz R0, 4( R11 ) + mtlr R0 + lwz R31, -4( R11 ) + mr R1, R11 + + /* Get the address of the TCB. */ + xor R0, R0, R0 + addis SP, R0, pxCurrentTCB@ha + lwz SP, pxCurrentTCB@l( R1 ) + + /* Get the task stack pointer from the TCB. */ + lwz SP, 0( SP ) + +.endm + + +vPortStartFirstTask: + + /* Get the address of the TCB. */ + xor R0, R0, R0 + addis SP, R0, pxCurrentTCB@ha + lwz SP, pxCurrentTCB@l( SP ) + + /* Get the task stack pointer from the TCB. */ + lwz SP, 0( SP ) + + /* Restore MSR register to SRR1. */ + lwz R0, MSRField(R1) + mtsrr1 R0 + + /* Restore current PC location to SRR0. */ + lwz R0, PCField(R1) + mtsrr0 R0 + + /* Save USPRG0 register */ + lwz R0, USPRG0Field(R1) + mtspr 0x100,R0 + + /* Restore Condition register */ + lwz R0, CRField(R1) + mtcr R0 + + /* Restore Fixed Point Exception register */ + lwz R0, XERField(R1) + mtxer R0 + + /* Restore Counter register */ + lwz R0, CTRField(R1) + mtctr R0 + + /* Restore Link register */ + lwz R0, LRField(R1) + mtlr R0 + + /* Restore remaining GPR registers. */ + lmw R3,r3r31Field(R1) + + /* Restore r0 and r2. */ + lwz R0, r0Field(R1) + lwz R2, r2Field(R1) + + /* Remove frame from stack */ + addi R1,R1,IFrameSize + + /* Return into the first task */ + rfi + + + +vPortYield: + + portSAVE_STACK_POINTER_AND_LR + bl vTaskSwitchContext + portRESTORE_STACK_POINTER_AND_LR + blr + +vPortTickISR: + + portSAVE_STACK_POINTER_AND_LR + bl xTaskIncrementTick + + #if configUSE_PREEMPTION == 1 + bl vTaskSwitchContext + #endif + + /* Clear the interrupt */ + lis R0, 2048 + mttsr R0 + + portRESTORE_STACK_POINTER_AND_LR + blr + +vPortISRWrapper: + + portSAVE_STACK_POINTER_AND_LR + bl vPortISRHandler + portRESTORE_STACK_POINTER_AND_LR + blr + +#if configUSE_FPU == 1 + +vPortSaveFPURegisters: + + /* Enable APU and mark FPU as present. */ + mfmsr r0 + xor r30, r30, r30 + oris r30, r30, 512 + ori r30, r30, 8192 + or r0, r0, r30 + mtmsr r0 + +#ifdef USE_DP_FPU + + /* Buffer address is in r3. Save each flop register into an offset from + this buffer address. */ + stfd f0, 0(r3) + stfd f1, 8(r3) + stfd f2, 16(r3) + stfd f3, 24(r3) + stfd f4, 32(r3) + stfd f5, 40(r3) + stfd f6, 48(r3) + stfd f7, 56(r3) + stfd f8, 64(r3) + stfd f9, 72(r3) + stfd f10, 80(r3) + stfd f11, 88(r3) + stfd f12, 96(r3) + stfd f13, 104(r3) + stfd f14, 112(r3) + stfd f15, 120(r3) + stfd f16, 128(r3) + stfd f17, 136(r3) + stfd f18, 144(r3) + stfd f19, 152(r3) + stfd f20, 160(r3) + stfd f21, 168(r3) + stfd f22, 176(r3) + stfd f23, 184(r3) + stfd f24, 192(r3) + stfd f25, 200(r3) + stfd f26, 208(r3) + stfd f27, 216(r3) + stfd f28, 224(r3) + stfd f29, 232(r3) + stfd f30, 240(r3) + stfd f31, 248(r3) + + /* Also save the FPSCR. */ + mffs f31 + stfs f31, 256(r3) + +#else + + /* Buffer address is in r3. Save each flop register into an offset from + this buffer address. */ + stfs f0, 0(r3) + stfs f1, 4(r3) + stfs f2, 8(r3) + stfs f3, 12(r3) + stfs f4, 16(r3) + stfs f5, 20(r3) + stfs f6, 24(r3) + stfs f7, 28(r3) + stfs f8, 32(r3) + stfs f9, 36(r3) + stfs f10, 40(r3) + stfs f11, 44(r3) + stfs f12, 48(r3) + stfs f13, 52(r3) + stfs f14, 56(r3) + stfs f15, 60(r3) + stfs f16, 64(r3) + stfs f17, 68(r3) + stfs f18, 72(r3) + stfs f19, 76(r3) + stfs f20, 80(r3) + stfs f21, 84(r3) + stfs f22, 88(r3) + stfs f23, 92(r3) + stfs f24, 96(r3) + stfs f25, 100(r3) + stfs f26, 104(r3) + stfs f27, 108(r3) + stfs f28, 112(r3) + stfs f29, 116(r3) + stfs f30, 120(r3) + stfs f31, 124(r3) + + /* Also save the FPSCR. */ + mffs f31 + stfs f31, 128(r3) + +#endif + + blr + +#endif /* configUSE_FPU. */ + + +#if configUSE_FPU == 1 + +vPortRestoreFPURegisters: + + /* Enable APU and mark FPU as present. */ + mfmsr r0 + xor r30, r30, r30 + oris r30, r30, 512 + ori r30, r30, 8192 + or r0, r0, r30 + mtmsr r0 + +#ifdef USE_DP_FPU + + /* Buffer address is in r3. Restore each flop register from an offset + into this buffer. + + First the FPSCR. */ + lfs f31, 256(r3) + mtfsf f31, 7 + + lfd f0, 0(r3) + lfd f1, 8(r3) + lfd f2, 16(r3) + lfd f3, 24(r3) + lfd f4, 32(r3) + lfd f5, 40(r3) + lfd f6, 48(r3) + lfd f7, 56(r3) + lfd f8, 64(r3) + lfd f9, 72(r3) + lfd f10, 80(r3) + lfd f11, 88(r3) + lfd f12, 96(r3) + lfd f13, 104(r3) + lfd f14, 112(r3) + lfd f15, 120(r3) + lfd f16, 128(r3) + lfd f17, 136(r3) + lfd f18, 144(r3) + lfd f19, 152(r3) + lfd f20, 160(r3) + lfd f21, 168(r3) + lfd f22, 176(r3) + lfd f23, 184(r3) + lfd f24, 192(r3) + lfd f25, 200(r3) + lfd f26, 208(r3) + lfd f27, 216(r3) + lfd f28, 224(r3) + lfd f29, 232(r3) + lfd f30, 240(r3) + lfd f31, 248(r3) + +#else + + /* Buffer address is in r3. Restore each flop register from an offset + into this buffer. + + First the FPSCR. */ + lfs f31, 128(r3) + mtfsf f31, 7 + + lfs f0, 0(r3) + lfs f1, 4(r3) + lfs f2, 8(r3) + lfs f3, 12(r3) + lfs f4, 16(r3) + lfs f5, 20(r3) + lfs f6, 24(r3) + lfs f7, 28(r3) + lfs f8, 32(r3) + lfs f9, 36(r3) + lfs f10, 40(r3) + lfs f11, 44(r3) + lfs f12, 48(r3) + lfs f13, 52(r3) + lfs f14, 56(r3) + lfs f15, 60(r3) + lfs f16, 64(r3) + lfs f17, 68(r3) + lfs f18, 72(r3) + lfs f19, 76(r3) + lfs f20, 80(r3) + lfs f21, 84(r3) + lfs f22, 88(r3) + lfs f23, 92(r3) + lfs f24, 96(r3) + lfs f25, 100(r3) + lfs f26, 104(r3) + lfs f27, 108(r3) + lfs f28, 112(r3) + lfs f29, 116(r3) + lfs f30, 120(r3) + lfs f31, 124(r3) + +#endif + + blr + +#endif /* configUSE_FPU. */ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC405_Xilinx/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC405_Xilinx/portmacro.h new file mode 100644 index 0000000..0979da6 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC405_Xilinx/portmacro.h @@ -0,0 +1,119 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include "xexception_l.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* This port uses the critical nesting count from the TCB rather than +maintaining a separate value and then saving this value in the task stack. */ +#define portCRITICAL_NESTING_IN_TCB 1 + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL ); +#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL ); + +/*-----------------------------------------------------------*/ + +/* Critical section macros. */ +void vTaskEnterCritical( void ); +void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +void vPortYield( void ); +#define portYIELD() asm volatile ( "SC \n\t NOP" ) +#define portYIELD_FROM_ISR() vTaskSwitchContext() + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) + +/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */ +#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Port specific interrupt handling functions. */ +void vPortSetupInterruptController( void ); +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ); + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC440_Xilinx/FPU_Macros.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC440_Xilinx/FPU_Macros.h new file mode 100644 index 0000000..a9e37b5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC440_Xilinx/FPU_Macros.h @@ -0,0 +1,46 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* When switching out a task, if the task tag contains a buffer address then +save the flop context into the buffer. */ +#define traceTASK_SWITCHED_OUT() \ + if( pxCurrentTCB->pxTaskTag != NULL ) \ + { \ + extern void vPortSaveFPURegisters( void * ); \ + vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ + } + +/* When switching in a task, if the task tag contains a buffer address then +load the flop context from the buffer. */ +#define traceTASK_SWITCHED_IN() \ + if( pxCurrentTCB->pxTaskTag != NULL ) \ + { \ + extern void vPortRestoreFPURegisters( void * ); \ + vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ + } + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC440_Xilinx/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC440_Xilinx/port.c new file mode 100644 index 0000000..28c5fde --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC440_Xilinx/port.c @@ -0,0 +1,261 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PPC440 port. + *----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "xtime_l.h" +#include "xintc.h" +#include "xintc_i.h" + +/*-----------------------------------------------------------*/ + +/* Definitions to set the initial MSR of each task. */ +#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL ) +#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL ) +#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL ) + +#if configUSE_FPU == 1 + #define portAPU_PRESENT ( 1UL << 25UL ) + #define portFCM_FPU_PRESENT ( 1UL << 13UL ) +#else + #define portAPU_PRESENT ( 0UL ) + #define portFCM_FPU_PRESENT ( 0UL ) +#endif + +#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT ) + + +extern const unsigned _SDA_BASE_; +extern const unsigned _SDA2_BASE_; + +/*-----------------------------------------------------------*/ + +/* + * Setup the system timer to generate the tick interrupt. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The handler for the tick interrupt - defined in portasm.s. + */ +extern void vPortTickISR( void ); + +/* + * The handler for the yield function - defined in portasm.s. + */ +extern void vPortYield( void ); + +/* + * Function to start the scheduler running by starting the highest + * priority task that has thus far been created. + */ +extern void vPortStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* Structure used to hold the state of the interrupt controller. */ +static XIntc xInterruptController; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if the task had been + * interrupted. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Place a known value at the bottom of the stack for debugging. */ + *pxTopOfStack = 0xDEADBEEF; + pxTopOfStack--; + + /* EABI stack frame. */ + pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */ + + /* Parameters in R13. */ + *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */ + pxTopOfStack -= 10; + + /* Parameters in R3. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + /* Parameters in R2. */ + *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */ + pxTopOfStack--; + + /* R1 is the stack pointer so is omitted. */ + + *pxTopOfStack = 0x10000001UL;; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* USPRG0. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* CR. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* XER. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* CTR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_MSR;/* SRR1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL;/* Backchain. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + prvSetupTimerInterrupt(); + XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 ); + vPortStartFirstTask(); + + /* Should not get here as the tasks are now running! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. + */ +static void prvSetupTimerInterrupt( void ) +{ +const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL ); + + XTime_DECClearInterrupt(); + XTime_FITClearInterrupt(); + XTime_WDTClearInterrupt(); + XTime_WDTDisableInterrupt(); + XTime_FITDisableInterrupt(); + + XExc_RegisterHandler( XEXC_ID_DEC_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 ); + + XTime_DECEnableAutoReload(); + XTime_DECSetInterval( ulInterval ); + XTime_DECEnableInterrupt(); +} +/*-----------------------------------------------------------*/ + +void vPortISRHandler( void *pvNullDoNotUse ) +{ +uint32_t ulInterruptStatus, ulInterruptMask = 1UL; +BaseType_t xInterruptNumber; +XIntc_Config *pxInterruptController; +XIntc_VectorTableEntry *pxTable; + + /* Just to remove compiler warning. */ + ( void ) pvNullDoNotUse; + + /* Get the configuration by using the device ID - in this case it is + assumed that only one interrupt controller is being used. */ + pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ]; + + /* Which interrupts are pending? */ + ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress ); + + for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ ) + { + if( ulInterruptStatus & 0x01UL ) + { + /* Clear the pending interrupt. */ + XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask ); + + /* Call the registered handler. */ + pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] ); + pxTable->Handler( pxTable->CallBackRef ); + } + + /* Check the next interrupt. */ + ulInterruptMask <<= 0x01UL; + ulInterruptStatus >>= 0x01UL; + + /* Have we serviced all interrupts? */ + if( ulInterruptStatus == 0UL ) + { + break; + } + } +} +/*-----------------------------------------------------------*/ + +void vPortSetupInterruptController( void ) +{ +extern void vPortISRWrapper( void ); + + /* Perform all library calls necessary to initialise the exception table + and interrupt controller. This assumes only one interrupt controller is in + use. */ + XExc_mDisableExceptions( XEXC_NON_CRITICAL ); + XExc_Init(); + + /* The library functions save the context - we then jump to a wrapper to + save the stack into the TCB. The wrapper then calls the handler defined + above. */ + XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL ); + XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID ); + XIntc_Start( &xInterruptController, XIN_REAL_MODE ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ) +{ +BaseType_t xReturn = pdFAIL; + + /* This function is defined here so the scope of xInterruptController can + remain within this file. */ + + if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) ) + { + XIntc_Enable( &xInterruptController, ucInterruptID ); + xReturn = pdPASS; + } + + return xReturn; +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC440_Xilinx/portasm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC440_Xilinx/portasm.S new file mode 100644 index 0000000..a08bcbe --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC440_Xilinx/portasm.S @@ -0,0 +1,383 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern xTaskIncrementTick + .extern vPortISRHandler + + .global vPortStartFirstTask + .global vPortYield + .global vPortTickISR + .global vPortISRWrapper + .global vPortSaveFPURegisters + .global vPortRestoreFPURegisters + +.set BChainField, 0 +.set NextLRField, BChainField + 4 +.set MSRField, NextLRField + 4 +.set PCField, MSRField + 4 +.set LRField, PCField + 4 +.set CTRField, LRField + 4 +.set XERField, CTRField + 4 +.set CRField, XERField + 4 +.set USPRG0Field, CRField + 4 +.set r0Field, USPRG0Field + 4 +.set r2Field, r0Field + 4 +.set r3r31Field, r2Field + 4 +.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4 + + +.macro portSAVE_STACK_POINTER_AND_LR + + /* Get the address of the TCB. */ + xor R0, R0, R0 + addis R2, R0, pxCurrentTCB@ha + lwz R2, pxCurrentTCB@l( R2 ) + + /* Store the stack pointer into the TCB */ + stw SP, 0( R2 ) + + /* Save the link register */ + stwu R1, -24( R1 ) + mflr R0 + stw R31, 20( R1 ) + stw R0, 28( R1 ) + mr R31, r1 + +.endm + +.macro portRESTORE_STACK_POINTER_AND_LR + + /* Restore the link register */ + lwz R11, 0( R1 ) + lwz R0, 4( R11 ) + mtlr R0 + lwz R31, -4( R11 ) + mr R1, R11 + + /* Get the address of the TCB. */ + xor R0, R0, R0 + addis SP, R0, pxCurrentTCB@ha + lwz SP, pxCurrentTCB@l( R1 ) + + /* Get the task stack pointer from the TCB. */ + lwz SP, 0( SP ) + +.endm + + +vPortStartFirstTask: + + /* Get the address of the TCB. */ + xor R0, R0, R0 + addis SP, R0, pxCurrentTCB@ha + lwz SP, pxCurrentTCB@l( SP ) + + /* Get the task stack pointer from the TCB. */ + lwz SP, 0( SP ) + + /* Restore MSR register to SRR1. */ + lwz R0, MSRField(R1) + mtsrr1 R0 + + /* Restore current PC location to SRR0. */ + lwz R0, PCField(R1) + mtsrr0 R0 + + /* Save USPRG0 register */ + lwz R0, USPRG0Field(R1) + mtspr 0x100,R0 + + /* Restore Condition register */ + lwz R0, CRField(R1) + mtcr R0 + + /* Restore Fixed Point Exception register */ + lwz R0, XERField(R1) + mtxer R0 + + /* Restore Counter register */ + lwz R0, CTRField(R1) + mtctr R0 + + /* Restore Link register */ + lwz R0, LRField(R1) + mtlr R0 + + /* Restore remaining GPR registers. */ + lmw R3,r3r31Field(R1) + + /* Restore r0 and r2. */ + lwz R0, r0Field(R1) + lwz R2, r2Field(R1) + + /* Remove frame from stack */ + addi R1,R1,IFrameSize + + /* Return into the first task */ + rfi + + + +vPortYield: + + portSAVE_STACK_POINTER_AND_LR + bl vTaskSwitchContext + portRESTORE_STACK_POINTER_AND_LR + blr + +vPortTickISR: + + portSAVE_STACK_POINTER_AND_LR + bl xTaskIncrementTick + + #if configUSE_PREEMPTION == 1 + bl vTaskSwitchContext + #endif + + /* Clear the interrupt */ + lis R0, 2048 + mttsr R0 + + portRESTORE_STACK_POINTER_AND_LR + blr + +vPortISRWrapper: + + portSAVE_STACK_POINTER_AND_LR + bl vPortISRHandler + portRESTORE_STACK_POINTER_AND_LR + blr + +#if configUSE_FPU == 1 + +vPortSaveFPURegisters: + + /* Enable APU and mark FPU as present. */ + mfmsr r0 + xor r30, r30, r30 + oris r30, r30, 512 + ori r30, r30, 8192 + or r0, r0, r30 + mtmsr r0 + +#ifdef USE_DP_FPU + + /* Buffer address is in r3. Save each flop register into an offset from + this buffer address. */ + stfd f0, 0(r3) + stfd f1, 8(r3) + stfd f2, 16(r3) + stfd f3, 24(r3) + stfd f4, 32(r3) + stfd f5, 40(r3) + stfd f6, 48(r3) + stfd f7, 56(r3) + stfd f8, 64(r3) + stfd f9, 72(r3) + stfd f10, 80(r3) + stfd f11, 88(r3) + stfd f12, 96(r3) + stfd f13, 104(r3) + stfd f14, 112(r3) + stfd f15, 120(r3) + stfd f16, 128(r3) + stfd f17, 136(r3) + stfd f18, 144(r3) + stfd f19, 152(r3) + stfd f20, 160(r3) + stfd f21, 168(r3) + stfd f22, 176(r3) + stfd f23, 184(r3) + stfd f24, 192(r3) + stfd f25, 200(r3) + stfd f26, 208(r3) + stfd f27, 216(r3) + stfd f28, 224(r3) + stfd f29, 232(r3) + stfd f30, 240(r3) + stfd f31, 248(r3) + + /* Also save the FPSCR. */ + mffs f31 + stfs f31, 256(r3) + +#else + + /* Buffer address is in r3. Save each flop register into an offset from + this buffer address. */ + stfs f0, 0(r3) + stfs f1, 4(r3) + stfs f2, 8(r3) + stfs f3, 12(r3) + stfs f4, 16(r3) + stfs f5, 20(r3) + stfs f6, 24(r3) + stfs f7, 28(r3) + stfs f8, 32(r3) + stfs f9, 36(r3) + stfs f10, 40(r3) + stfs f11, 44(r3) + stfs f12, 48(r3) + stfs f13, 52(r3) + stfs f14, 56(r3) + stfs f15, 60(r3) + stfs f16, 64(r3) + stfs f17, 68(r3) + stfs f18, 72(r3) + stfs f19, 76(r3) + stfs f20, 80(r3) + stfs f21, 84(r3) + stfs f22, 88(r3) + stfs f23, 92(r3) + stfs f24, 96(r3) + stfs f25, 100(r3) + stfs f26, 104(r3) + stfs f27, 108(r3) + stfs f28, 112(r3) + stfs f29, 116(r3) + stfs f30, 120(r3) + stfs f31, 124(r3) + + /* Also save the FPSCR. */ + mffs f31 + stfs f31, 128(r3) + +#endif + + blr + +#endif /* configUSE_FPU. */ + + +#if configUSE_FPU == 1 + +vPortRestoreFPURegisters: + + /* Enable APU and mark FPU as present. */ + mfmsr r0 + xor r30, r30, r30 + oris r30, r30, 512 + ori r30, r30, 8192 + or r0, r0, r30 + mtmsr r0 + +#ifdef USE_DP_FPU + + /* Buffer address is in r3. Restore each flop register from an offset + into this buffer. + + First the FPSCR. */ + lfs f31, 256(r3) + mtfsf f31, 7 + + lfd f0, 0(r3) + lfd f1, 8(r3) + lfd f2, 16(r3) + lfd f3, 24(r3) + lfd f4, 32(r3) + lfd f5, 40(r3) + lfd f6, 48(r3) + lfd f7, 56(r3) + lfd f8, 64(r3) + lfd f9, 72(r3) + lfd f10, 80(r3) + lfd f11, 88(r3) + lfd f12, 96(r3) + lfd f13, 104(r3) + lfd f14, 112(r3) + lfd f15, 120(r3) + lfd f16, 128(r3) + lfd f17, 136(r3) + lfd f18, 144(r3) + lfd f19, 152(r3) + lfd f20, 160(r3) + lfd f21, 168(r3) + lfd f22, 176(r3) + lfd f23, 184(r3) + lfd f24, 192(r3) + lfd f25, 200(r3) + lfd f26, 208(r3) + lfd f27, 216(r3) + lfd f28, 224(r3) + lfd f29, 232(r3) + lfd f30, 240(r3) + lfd f31, 248(r3) + +#else + + /* Buffer address is in r3. Restore each flop register from an offset + into this buffer. + + First the FPSCR. */ + lfs f31, 128(r3) + mtfsf f31, 7 + + lfs f0, 0(r3) + lfs f1, 4(r3) + lfs f2, 8(r3) + lfs f3, 12(r3) + lfs f4, 16(r3) + lfs f5, 20(r3) + lfs f6, 24(r3) + lfs f7, 28(r3) + lfs f8, 32(r3) + lfs f9, 36(r3) + lfs f10, 40(r3) + lfs f11, 44(r3) + lfs f12, 48(r3) + lfs f13, 52(r3) + lfs f14, 56(r3) + lfs f15, 60(r3) + lfs f16, 64(r3) + lfs f17, 68(r3) + lfs f18, 72(r3) + lfs f19, 76(r3) + lfs f20, 80(r3) + lfs f21, 84(r3) + lfs f22, 88(r3) + lfs f23, 92(r3) + lfs f24, 96(r3) + lfs f25, 100(r3) + lfs f26, 104(r3) + lfs f27, 108(r3) + lfs f28, 112(r3) + lfs f29, 116(r3) + lfs f30, 120(r3) + lfs f31, 124(r3) + +#endif + + blr + +#endif /* configUSE_FPU. */ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC440_Xilinx/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC440_Xilinx/portmacro.h new file mode 100644 index 0000000..0979da6 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/PPC440_Xilinx/portmacro.h @@ -0,0 +1,119 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include "xexception_l.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* This port uses the critical nesting count from the TCB rather than +maintaining a separate value and then saving this value in the task stack. */ +#define portCRITICAL_NESTING_IN_TCB 1 + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL ); +#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL ); + +/*-----------------------------------------------------------*/ + +/* Critical section macros. */ +void vTaskEnterCritical( void ); +void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +void vPortYield( void ); +#define portYIELD() asm volatile ( "SC \n\t NOP" ) +#define portYIELD_FROM_ISR() vTaskSwitchContext() + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) + +/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */ +#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Port specific interrupt handling functions. */ +void vPortSetupInterruptController( void ); +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ); + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/Documentation.url b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/Documentation.url new file mode 100644 index 0000000..c7819d5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/Documentation.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,11 +[InternetShortcut] +IDList= +URL=https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h new file mode 100644 index 0000000..81d7a1a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h @@ -0,0 +1,108 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ + +/* + * This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy + * devices, developed and tested using the Vega board RV32M1RM. + */ + +#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ +#define __FREERTOS_RISC_V_EXTENSIONS_H__ + +#define portasmHAS_MTIME 0 + +/* Constants to define the additional registers found on the Pulpino RI5KY. */ +#define lpstart0 0x7b0 +#define lpend0 0x7b1 +#define lpcount0 0x7b2 +#define lpstart1 0x7b4 +#define lpend1 0x7b5 +#define lpcount1 0x7b6 + +/* Six additional registers to save and restore, as per the #defines above. */ +#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */ + +/* Save additional registers found on the Pulpino. */ +.macro portasmSAVE_ADDITIONAL_REGISTERS + addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */ + csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */ + csrr t1, lpend0 + csrr t2, lpcount0 + csrr t3, lpstart1 + csrr t4, lpend1 + csrr t5, lpcount1 + sw t0, 1 * portWORD_SIZE( sp ) + sw t1, 2 * portWORD_SIZE( sp ) + sw t2, 3 * portWORD_SIZE( sp ) + sw t3, 4 * portWORD_SIZE( sp ) + sw t4, 5 * portWORD_SIZE( sp ) + sw t5, 6 * portWORD_SIZE( sp ) + .endm + +/* Restore the additional registers found on the Pulpino. */ +.macro portasmRESTORE_ADDITIONAL_REGISTERS + lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */ + lw t1, 2 * portWORD_SIZE( sp ) + lw t2, 3 * portWORD_SIZE( sp ) + lw t3, 4 * portWORD_SIZE( sp ) + lw t4, 5 * portWORD_SIZE( sp ) + lw t5, 6 * portWORD_SIZE( sp ) + csrw lpstart0, t0 + csrw lpend0, t1 + csrw lpcount0, t2 + csrw lpstart1, t3 + csrw lpend1, t4 + csrw lpcount1, t5 + addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */ + .endm + +#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h new file mode 100644 index 0000000..6a08c1a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -0,0 +1,69 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RISCV_MTIME_CLINT_no_extensions + * + */ + + +#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ +#define __FREERTOS_RISC_V_EXTENSIONS_H__ + +#define portasmHAS_SIFIVE_CLINT 1 +#define portasmHAS_MTIME 1 +#define portasmADDITIONAL_CONTEXT_SIZE 0 + +.macro portasmSAVE_ADDITIONAL_REGISTERS + /* No additional registers to save, so this macro does nothing. */ + .endm + +.macro portasmRESTORE_ADDITIONAL_REGISTERS + /* No additional registers to restore, so this macro does nothing. */ + .endm + +#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h new file mode 100644 index 0000000..447cf29 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -0,0 +1,69 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RISCV_MTIME_CLINT_no_extensions + * + */ + + +#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ +#define __FREERTOS_RISC_V_EXTENSIONS_H__ + +#define portasmHAS_SIFIVE_CLINT 0 +#define portasmHAS_MTIME 0 +#define portasmADDITIONAL_CONTEXT_SIZE 0 + +.macro portasmSAVE_ADDITIONAL_REGISTERS + /* No additional registers to save, so this macro does nothing. */ + .endm + +.macro portasmRESTORE_ADDITIONAL_REGISTERS + /* No additional registers to restore, so this macro does nothing. */ + .endm + +#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h new file mode 100644 index 0000000..ab5d5d3 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -0,0 +1,69 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ + + +#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ +#define __FREERTOS_RISC_V_EXTENSIONS_H__ + +#define portasmHAS_SIFIVE_CLINT 1 +#define portasmHAS_MTIME 1 +#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */ + +.macro portasmSAVE_ADDITIONAL_REGISTERS + /* No additional registers to save, so this macro does nothing. */ + .endm + +.macro portasmRESTORE_ADDITIONAL_REGISTERS + /* No additional registers to restore, so this macro does nothing. */ + .endm + +#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/readme.txt new file mode 100644 index 0000000..69d98d9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/chip_specific_extensions/readme.txt @@ -0,0 +1,23 @@ +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/port.c new file mode 100644 index 0000000..d10a393 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/port.c @@ -0,0 +1,203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the RISC-V port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* Standard includes. */ +#include "string.h" + +#ifdef configCLINT_BASE_ADDRESS + #warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +#ifndef configMTIME_BASE_ADDRESS + #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +#ifndef configMTIMECMP_BASE_ADDRESS + #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +/* Let the user override the pre-loading of the initial RA. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS 0 +#endif + +/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS + * to use a statically allocated array as the interrupt stack. Alternative leave + * configISR_STACK_SIZE_WORDS undefined and update the linker script so that a + * linker variable names __freertos_irq_stack_top has the same value as the top + * of the stack used by main. Using the linker script method will repurpose the + * stack that was used by main before the scheduler was started for use as the + * interrupt stack after the scheduler has started. */ +#ifdef configISR_STACK_SIZE_WORDS + static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 }; + const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] ); + + /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for + the task stacks, and so will legitimately appear in many positions within + the ISR stack. */ + #define portISR_STACK_FILL_BYTE 0xee +#else + extern const uint32_t __freertos_irq_stack_top[]; + const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top; +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) __attribute__(( weak )); + +/*-----------------------------------------------------------*/ + +/* Used to program the machine timer compare register. */ +uint64_t ullNextTime = 0ULL; +const uint64_t *pullNextTime = &ullNextTime; +const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */ +uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS; +volatile uint64_t * pullMachineTimerCompareRegister = NULL; + +/* Holds the critical nesting value - deliberately non-zero at start up to + * ensure interrupts are not accidentally enabled before the scheduler starts. */ +size_t xCriticalNesting = ( size_t ) 0xaaaaaaaa; +size_t *pxCriticalNesting = &xCriticalNesting; + +/* Used to catch tasks that attempt to return from their implementing function. */ +size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS; + +/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task + * stack checking. A problem in the ISR stack will trigger an assert, not call + * the stack overflow hook function (because the stack overflow hook is specific + * to a task stack, not the ISR stack). */ +#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) + #warning This path not tested, or even compiled yet. + + static const uint8_t ucExpectedStackBytes[] = { + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \ + + #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) +#else + /* Define the function away. */ + #define portCHECK_ISR_STACK() +#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + +/*-----------------------------------------------------------*/ + +#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) + + void vPortSetupTimerInterrupt( void ) + { + uint32_t ulCurrentTimeHigh, ulCurrentTimeLow; + volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte type so high 32-bit word is 4 bytes up. */ + volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS ); + volatile uint32_t ulHartId; + + __asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) ); + pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) ); + + do + { + ulCurrentTimeHigh = *pulTimeHigh; + ulCurrentTimeLow = *pulTimeLow; + } while( ulCurrentTimeHigh != *pulTimeHigh ); + + ullNextTime = ( uint64_t ) ulCurrentTimeHigh; + ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */ + ullNextTime |= ( uint64_t ) ulCurrentTimeLow; + ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick; + *pullMachineTimerCompareRegister = ullNextTime; + + /* Prepare the time to use after the next tick interrupt. */ + ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick; + } + +#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void xPortStartFirstTask( void ); + + #if( configASSERT_DEFINED == 1 ) + { + /* Check alignment of the interrupt stack - which is the same as the + * stack that was being used by main() prior to the scheduler being + * started. */ + configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 ); + + #ifdef configISR_STACK_SIZE_WORDS + { + memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) ); + } + #endif /* configISR_STACK_SIZE_WORDS */ + } + #endif /* configASSERT_DEFINED */ + + /* If there is a CLINT then it is ok to use the default implementation + * in this file, otherwise vPortSetupTimerInterrupt() must be implemented to + * configure whichever clock is to be used to generate the tick interrupt. */ + vPortSetupTimerInterrupt(); + + #if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) ) + { + /* Enable mtime and external interrupts. 1<<7 for timer interrupt, + * 1<<11 for external interrupt. _RB_ What happens here when mtime is + * not present as with pulpino? */ + __asm volatile( "csrs mie, %0" :: "r"(0x880) ); + } + #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */ + + xPortStartFirstTask(); + + /* Should not get here as after calling xPortStartFirstTask() only tasks + * should be executing. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/portASM.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/portASM.S new file mode 100644 index 0000000..6d8bc97 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/portASM.S @@ -0,0 +1,384 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code which tailors the port to a specific RISC-V chip: + * + * + The code that is common to all RISC-V chips is implemented in + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one + * portASM.S file because the same file is used no matter which RISC-V chip is + * in use. + * + * + The code that tailors the kernel's RISC-V port to a specific RISC-V + * chip is implemented in freertos_risc_v_chip_specific_extensions.h. There + * is one freertos_risc_v_chip_specific_extensions.h that can be used with any + * RISC-V chip that both includes a standard CLINT and does not add to the + * base set of RISC-V registers. There are additional + * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations + * that do not include a standard CLINT or do add to the base set of RISC-V + * registers. + * + * CARE MUST BE TAKEN TO INCLDUE THE CORRECT + * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP + * IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h + * header file ensure the path to the correct header file is in the assembler's + * include path. + * + * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips + * that include a standard CLINT and do not add to the base set of RISC-V + * registers. + * + */ + +#include "portContext.h" + +/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line +definitions. */ +#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME ) + #error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +#ifdef portasmHAS_CLINT + #warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html + #define portasmHAS_MTIME portasmHAS_CLINT + #define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT +#endif + +#ifndef portasmHAS_MTIME + #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +#ifndef portasmHAS_SIFIVE_CLINT + #define portasmHAS_SIFIVE_CLINT 0 +#endif + +.global xPortStartFirstTask +.global pxPortInitialiseStack +.global freertos_risc_v_trap_handler +.global freertos_risc_v_exception_handler +.global freertos_risc_v_interrupt_handler +.global freertos_risc_v_mtimer_interrupt_handler + +.extern vTaskSwitchContext +.extern xTaskIncrementTick +.extern pullMachineTimerCompareRegister +.extern pullNextTime +.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */ +.extern xTaskReturnAddress + +.weak freertos_risc_v_application_exception_handler +.weak freertos_risc_v_application_interrupt_handler +/*-----------------------------------------------------------*/ + +.macro portUPDATE_MTIMER_COMPARE_REGISTER + load_x a0, pullMachineTimerCompareRegister /* Load address of compare register into a0. */ + load_x a1, pullNextTime /* Load the address of ullNextTime into a1. */ + + #if( __riscv_xlen == 32 ) + + /* Update the 64-bit mtimer compare match value in two 32-bit writes. */ + li a4, -1 + lw a2, 0(a1) /* Load the low word of ullNextTime into a2. */ + lw a3, 4(a1) /* Load the high word of ullNextTime into a3. */ + sw a4, 0(a0) /* Low word no smaller than old value to start with - will be overwritten below. */ + sw a3, 4(a0) /* Store high word of ullNextTime into compare register. No smaller than new value. */ + sw a2, 0(a0) /* Store low word of ullNextTime into compare register. */ + lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */ + add a4, t0, a2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */ + sltu t1, a4, a2 /* See if the sum of low words overflowed (what about the zero case?). */ + add t2, a3, t1 /* Add overflow to high word of ullNextTime. */ + sw a4, 0(a1) /* Store new low word of ullNextTime. */ + sw t2, 4(a1) /* Store new high word of ullNextTime. */ + + #endif /* __riscv_xlen == 32 */ + + #if( __riscv_xlen == 64 ) + + /* Update the 64-bit mtimer compare match value. */ + ld t2, 0(a1) /* Load ullNextTime into t2. */ + sd t2, 0(a0) /* Store ullNextTime into compare register. */ + ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */ + add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */ + sd t4, 0(a1) /* Store ullNextTime. */ + + #endif /* __riscv_xlen == 64 */ + .endm +/*-----------------------------------------------------------*/ + +/* + * Unlike other ports pxPortInitialiseStack() is written in assembly code as it + * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype + * for the function is as per the other ports: + * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ); + * + * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in + * a1, and pvParameters in a2. The new top of stack is passed out in a0. + * + * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers + * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed). + * + * Register ABI Name Description Saver + * x0 zero Hard-wired zero - + * x1 ra Return address Caller + * x2 sp Stack pointer Callee + * x3 gp Global pointer - + * x4 tp Thread pointer - + * x5-7 t0-2 Temporaries Caller + * x8 s0/fp Saved register/Frame pointer Callee + * x9 s1 Saved register Callee + * x10-11 a0-1 Function Arguments/return values Caller + * x12-17 a2-7 Function arguments Caller + * x18-27 s2-11 Saved registers Callee + * x28-31 t3-6 Temporaries Caller + * + * The RISC-V context is saved t FreeRTOS tasks in the following stack frame, + * where the global and thread pointers are currently assumed to be constant so + * are not saved: + * + * mstatus + * xCriticalNesting + * x31 + * x30 + * x29 + * x28 + * x27 + * x26 + * x25 + * x24 + * x23 + * x22 + * x21 + * x20 + * x19 + * x18 + * x17 + * x16 + * x15 + * x14 + * x13 + * x12 + * x11 + * pvParameters + * x9 + * x8 + * x7 + * x6 + * x5 + * portTASK_RETURN_ADDRESS + * [chip specific registers go here] + * pxCode + */ +pxPortInitialiseStack: + csrr t0, mstatus /* Obtain current mstatus value. */ + andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */ + addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */ + slli t1, t1, 4 + or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */ + + addi a0, a0, -portWORD_SIZE + store_x t0, 0(a0) /* mstatus onto the stack. */ + addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */ + store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */ + +#ifdef __riscv_32e + addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x11-x15. */ +#else + addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */ +#endif + store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */ + addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */ + load_x t0, xTaskReturnAddress + store_x t0, 0(a0) /* Return address onto the stack. */ + addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */ +chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */ + beq t0, x0, 1f /* No more chip specific registers to save. */ + addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */ + store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */ + addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */ + j chip_specific_stack_frame /* Until no more chip specific registers. */ +1: + addi a0, a0, -portWORD_SIZE + store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */ + ret +/*-----------------------------------------------------------*/ + +xPortStartFirstTask: + load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */ + load_x sp, 0( sp ) /* Read sp from first TCB member. */ + + load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */ + + portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ + + load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */ + load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */ + load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */ + load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */ + load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */ + load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */ + load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */ + load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */ + load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */ +#ifndef __riscv_32e + load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */ + load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */ + load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */ + load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */ + load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */ + load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */ + load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */ + load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */ + load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */ + load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */ + load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */ + load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */ + load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */ + load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */ + load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */ + load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */ +#endif + + load_x x5, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ + load_x x6, pxCriticalNesting /* Load the address of xCriticalNesting into x6. */ + store_x x5, 0( x6 ) /* Restore the critical nesting value for this task. */ + + load_x x5, portMSTATUS_OFFSET * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */ + addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */ + csrrw x0, mstatus, x5 /* Interrupts enabled from here! */ + + load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */ + load_x x6, 3 * portWORD_SIZE( sp ) /* Initial x6 (t1) value. */ + + addi sp, sp, portCONTEXT_SIZE + ret +/*-----------------------------------------------------------*/ + +freertos_risc_v_application_exception_handler: + csrr t0, mcause /* For viewing in the debugger only. */ + csrr t1, mepc /* For viewing in the debugger only */ + csrr t2, mstatus /* For viewing in the debugger only */ + j . +/*-----------------------------------------------------------*/ + +freertos_risc_v_application_interrupt_handler: + csrr t0, mcause /* For viewing in the debugger only. */ + csrr t1, mepc /* For viewing in the debugger only */ + csrr t2, mstatus /* For viewing in the debugger only */ + j . +/*-----------------------------------------------------------*/ + +.section .text.freertos_risc_v_exception_handler +freertos_risc_v_exception_handler: + portcontextSAVE_EXCEPTION_CONTEXT + /* a0 now contains mcause. */ + li t0, 11 /* 11 == environment call. */ + bne a0, t0, other_exception /* Not an M environment call, so some other exception. */ + call vTaskSwitchContext + portcontextRESTORE_CONTEXT + +other_exception: + call freertos_risc_v_application_exception_handler + portcontextRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + +.section .text.freertos_risc_v_interrupt_handler +freertos_risc_v_interrupt_handler: + portcontextSAVE_INTERRUPT_CONTEXT + call freertos_risc_v_application_interrupt_handler + portcontextRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + +.section .text.freertos_risc_v_mtimer_interrupt_handler +freertos_risc_v_mtimer_interrupt_handler: + portcontextSAVE_INTERRUPT_CONTEXT + portUPDATE_MTIMER_COMPARE_REGISTER + call xTaskIncrementTick + beqz a0, exit_without_context_switch /* Don't switch context if incrementing tick didn't unblock a task. */ + call vTaskSwitchContext +exit_without_context_switch: + portcontextRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + +.section .text.freertos_risc_v_trap_handler +.align 8 +freertos_risc_v_trap_handler: + portcontextSAVE_CONTEXT_INTERNAL + + csrr a0, mcause + csrr a1, mepc + + bge a0, x0, synchronous_exception + +asynchronous_interrupt: + store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */ + load_x sp, xISRStackTop /* Switch to ISR stack. */ + j handle_interrupt + +synchronous_exception: + addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exeption. */ + store_x a1, 0( sp ) /* Save updated exception return address. */ + load_x sp, xISRStackTop /* Switch to ISR stack. */ + j handle_exception + +handle_interrupt: +#if( portasmHAS_MTIME != 0 ) + + test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */ + addi t0, x0, 1 + slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */ + addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */ + bne a0, t1, application_interrupt_handler + + portUPDATE_MTIMER_COMPARE_REGISTER + call xTaskIncrementTick + beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */ + call vTaskSwitchContext + j processed_source + +#endif /* portasmHAS_MTIME */ + +application_interrupt_handler: + call freertos_risc_v_application_interrupt_handler + j processed_source + +handle_exception: + /* a0 contains mcause. */ + li t0, 11 /* 11 == environment call. */ + bne a0, t0, application_exception_handler /* Not an M environment call, so some other exception. */ + call vTaskSwitchContext + j processed_source + +application_exception_handler: + call freertos_risc_v_application_exception_handler + j processed_source /* No other exceptions handled yet. */ + +processed_source: + portcontextRESTORE_CONTEXT +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/portContext.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/portContext.h new file mode 100644 index 0000000..b834149 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/portContext.h @@ -0,0 +1,192 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTCONTEXT_H +#define PORTCONTEXT_H + +#if __riscv_xlen == 64 + #define portWORD_SIZE 8 + #define store_x sd + #define load_x ld +#elif __riscv_xlen == 32 + #define store_x sw + #define load_x lw + #define portWORD_SIZE 4 +#else + #error Assembler did not define __riscv_xlen +#endif + +#include "freertos_risc_v_chip_specific_extensions.h" + +/* Only the standard core registers are stored by default. Any additional + * registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and + * portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip + * specific version of freertos_risc_v_chip_specific_extensions.h. See the + * notes at the top of portASM.S file. */ +#ifdef __riscv_32e + #define portCONTEXT_SIZE ( 15 * portWORD_SIZE ) + #define portCRITICAL_NESTING_OFFSET 13 + #define portMSTATUS_OFFSET 14 +#else + #define portCONTEXT_SIZE ( 31 * portWORD_SIZE ) + #define portCRITICAL_NESTING_OFFSET 29 + #define portMSTATUS_OFFSET 30 +#endif + +/*-----------------------------------------------------------*/ + +.extern pxCurrentTCB +.extern xISRStackTop +.extern xCriticalNesting +.extern pxCriticalNesting +/*-----------------------------------------------------------*/ + +.macro portcontextSAVE_CONTEXT_INTERNAL + addi sp, sp, -portCONTEXT_SIZE + store_x x1, 1 * portWORD_SIZE( sp ) + store_x x5, 2 * portWORD_SIZE( sp ) + store_x x6, 3 * portWORD_SIZE( sp ) + store_x x7, 4 * portWORD_SIZE( sp ) + store_x x8, 5 * portWORD_SIZE( sp ) + store_x x9, 6 * portWORD_SIZE( sp ) + store_x x10, 7 * portWORD_SIZE( sp ) + store_x x11, 8 * portWORD_SIZE( sp ) + store_x x12, 9 * portWORD_SIZE( sp ) + store_x x13, 10 * portWORD_SIZE( sp ) + store_x x14, 11 * portWORD_SIZE( sp ) + store_x x15, 12 * portWORD_SIZE( sp ) +#ifndef __riscv_32e + store_x x16, 13 * portWORD_SIZE( sp ) + store_x x17, 14 * portWORD_SIZE( sp ) + store_x x18, 15 * portWORD_SIZE( sp ) + store_x x19, 16 * portWORD_SIZE( sp ) + store_x x20, 17 * portWORD_SIZE( sp ) + store_x x21, 18 * portWORD_SIZE( sp ) + store_x x22, 19 * portWORD_SIZE( sp ) + store_x x23, 20 * portWORD_SIZE( sp ) + store_x x24, 21 * portWORD_SIZE( sp ) + store_x x25, 22 * portWORD_SIZE( sp ) + store_x x26, 23 * portWORD_SIZE( sp ) + store_x x27, 24 * portWORD_SIZE( sp ) + store_x x28, 25 * portWORD_SIZE( sp ) + store_x x29, 26 * portWORD_SIZE( sp ) + store_x x30, 27 * portWORD_SIZE( sp ) + store_x x31, 28 * portWORD_SIZE( sp ) +#endif + + load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */ + store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */ + + + csrr t0, mstatus /* Required for MPIE bit. */ + store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) + + + portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */ + + load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */ + store_x sp, 0( t0 ) /* Write sp to first TCB member. */ + + .endm +/*-----------------------------------------------------------*/ + +.macro portcontextSAVE_EXCEPTION_CONTEXT + portcontextSAVE_CONTEXT_INTERNAL + csrr a0, mcause + csrr a1, mepc + addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */ + store_x a1, 0( sp ) /* Save updated exception return address. */ + load_x sp, xISRStackTop /* Switch to ISR stack. */ + .endm +/*-----------------------------------------------------------*/ + +.macro portcontextSAVE_INTERRUPT_CONTEXT + portcontextSAVE_CONTEXT_INTERNAL + csrr a0, mcause + csrr a1, mepc + store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */ + load_x sp, xISRStackTop /* Switch to ISR stack. */ + .endm +/*-----------------------------------------------------------*/ + +.macro portcontextRESTORE_CONTEXT + load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */ + load_x sp, 0( t1 ) /* Read sp from first TCB member. */ + + /* Load mepc with the address of the instruction in the task to run next. */ + load_x t0, 0( sp ) + csrw mepc, t0 + + /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ + portasmRESTORE_ADDITIONAL_REGISTERS + + /* Load mstatus with the interrupt enable bits used by the task. */ + load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) + csrw mstatus, t0 /* Required for MPIE bit. */ + + load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ + load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */ + store_x t0, 0( t1 ) /* Restore the critical nesting value for this task. */ + + load_x x1, 1 * portWORD_SIZE( sp ) + load_x x5, 2 * portWORD_SIZE( sp ) + load_x x6, 3 * portWORD_SIZE( sp ) + load_x x7, 4 * portWORD_SIZE( sp ) + load_x x8, 5 * portWORD_SIZE( sp ) + load_x x9, 6 * portWORD_SIZE( sp ) + load_x x10, 7 * portWORD_SIZE( sp ) + load_x x11, 8 * portWORD_SIZE( sp ) + load_x x12, 9 * portWORD_SIZE( sp ) + load_x x13, 10 * portWORD_SIZE( sp ) + load_x x14, 11 * portWORD_SIZE( sp ) + load_x x15, 12 * portWORD_SIZE( sp ) +#ifndef __riscv_32e + load_x x16, 13 * portWORD_SIZE( sp ) + load_x x17, 14 * portWORD_SIZE( sp ) + load_x x18, 15 * portWORD_SIZE( sp ) + load_x x19, 16 * portWORD_SIZE( sp ) + load_x x20, 17 * portWORD_SIZE( sp ) + load_x x21, 18 * portWORD_SIZE( sp ) + load_x x22, 19 * portWORD_SIZE( sp ) + load_x x23, 20 * portWORD_SIZE( sp ) + load_x x24, 21 * portWORD_SIZE( sp ) + load_x x25, 22 * portWORD_SIZE( sp ) + load_x x26, 23 * portWORD_SIZE( sp ) + load_x x27, 24 * portWORD_SIZE( sp ) + load_x x28, 25 * portWORD_SIZE( sp ) + load_x x29, 26 * portWORD_SIZE( sp ) + load_x x30, 27 * portWORD_SIZE( sp ) + load_x x31, 28 * portWORD_SIZE( sp ) +#endif + addi sp, sp, portCONTEXT_SIZE + + mret + .endm +/*-----------------------------------------------------------*/ + +#endif /* PORTCONTEXT_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/portmacro.h new file mode 100644 index 0000000..641626b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/portmacro.h @@ -0,0 +1,191 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#if __riscv_xlen == 64 + #define portSTACK_TYPE uint64_t + #define portBASE_TYPE int64_t + #define portUBASE_TYPE uint64_t + #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL + #define portPOINTER_SIZE_TYPE uint64_t +#elif __riscv_xlen == 32 + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE int32_t + #define portUBASE_TYPE uint32_t + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error Assembler did not define __riscv_xlen +#endif + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef portUBASE_TYPE UBaseType_t; +typedef portUBASE_TYPE TickType_t; + +/* Legacy type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#ifdef __riscv_32e + #define portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment requirements */ +#else + #define portBYTE_ALIGNMENT 16 +#endif +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +extern void vTaskSwitchContext( void ); +#define portYIELD() __asm volatile( "ecall" ); +#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portCRITICAL_NESTING_IN_TCB 0 + +#define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue + +#define portDISABLE_INTERRUPTS() __asm volatile( "csrc mstatus, 8" ) +#define portENABLE_INTERRUPTS() __asm volatile( "csrs mstatus, 8" ) + +extern size_t xCriticalNesting; +#define portENTER_CRITICAL() \ +{ \ + portDISABLE_INTERRUPTS(); \ + xCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ + xCriticalNesting--; \ + if( xCriticalNesting == 0 ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ +} + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo + * files (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/*-----------------------------------------------------------*/ + +#define portNOP() __asm volatile( " nop " ) +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__(( always_inline)) +#endif + +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the + * configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For + * backward compatibility derive the newer definitions from the old if the old + * definition is found. */ +#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) + /* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate + * there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP + * addresses to 0. */ + #define configMTIME_BASE_ADDRESS ( 0 ) + #define configMTIMECMP_BASE_ADDRESS ( 0 ) +#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) + /* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of + * the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses + * from the CLINT address. */ + #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL ) + #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL ) +#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS ) + #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/readme.txt new file mode 100644 index 0000000..69d98d9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RISC-V/readme.txt @@ -0,0 +1,23 @@ +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RL78/isr_support.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RL78/isr_support.h new file mode 100644 index 0000000..fa7ecb6 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RL78/isr_support.h @@ -0,0 +1,127 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Variables used by scheduler */ + .extern _pxCurrentTCB + .extern _usCriticalNesting + +/* + * portSAVE_CONTEXT MACRO + * Saves the context of the general purpose registers, CS and ES (only in far + * memory mode) registers the usCriticalNesting Value and the Stack Pointer + * of the active Task onto the task stack + */ + .macro portSAVE_CONTEXT + + SEL RB0 + + /* Save AX Register to stack. */ + PUSH AX + PUSH HL + /* Save CS register. */ + MOV A, CS + XCH A, X + /* Save ES register. */ + MOV A, ES + PUSH AX + /* Save the remaining general purpose registers from bank 0. */ + PUSH DE + PUSH BC + /* Save the other register banks - only necessary in the GCC port. */ + SEL RB1 + PUSH AX + PUSH BC + PUSH DE + PUSH HL + SEL RB2 + PUSH AX + PUSH BC + PUSH DE + PUSH HL + /* Registers in bank 3 are for ISR use only so don't need saving. */ + SEL RB0 + /* Save the usCriticalNesting value. */ + MOVW AX, !_usCriticalNesting + PUSH AX + /* Save the Stack pointer. */ + MOVW AX, !_pxCurrentTCB + MOVW HL, AX + MOVW AX, SP + MOVW [HL], AX + /* Switch stack pointers. */ + movw sp,#_stack /* Set stack pointer */ + + .endm + + +/* + * portRESTORE_CONTEXT MACRO + * Restores the task Stack Pointer then use this to restore usCriticalNesting, + * general purpose registers and the CS and ES (only in far memory mode) + * of the selected task from the task stack + */ +.macro portRESTORE_CONTEXT MACRO + SEL RB0 + /* Restore the Stack pointer. */ + MOVW AX, !_pxCurrentTCB + MOVW HL, AX + MOVW AX, [HL] + MOVW SP, AX + /* Restore usCriticalNesting value. */ + POP AX + MOVW !_usCriticalNesting, AX + /* Restore the alternative register banks - only necessary in the GCC + port. Register bank 3 is dedicated for interrupts use so is not saved or + restored. */ + SEL RB2 + POP HL + POP DE + POP BC + POP AX + SEL RB1 + POP HL + POP DE + POP BC + POP AX + SEL RB0 + /* Restore the necessary general purpose registers. */ + POP BC + POP DE + /* Restore the ES register. */ + POP AX + MOV ES, A + /* Restore the CS register. */ + XCH A, X + MOV CS, A + /* Restore general purpose register HL. */ + POP HL + /* Restore AX. */ + POP AX + + .endm + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RL78/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RL78/port.c new file mode 100644 index 0000000..f17aea7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RL78/port.c @@ -0,0 +1,212 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* The critical nesting value is initialised to a non zero value to ensure +interrupts don't accidentally become enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) + +/* Initial PSW value allocated to a newly created task. + * 11000110 + * ||||||||-------------- Fill byte + * |||||||--------------- Carry Flag cleared + * |||||----------------- In-service priority Flags set to low level + * ||||------------------ Register bank Select 0 Flag cleared + * |||------------------- Auxiliary Carry Flag cleared + * ||-------------------- Register bank Select 1 Flag cleared + * |--------------------- Zero Flag set + * ---------------------- Global Interrupt Flag set (enabled) + */ +#define portPSW ( 0xc6UL ) + +/* Each task maintains a count of the critical section nesting depth. Each time +a critical section is entered the count is incremented. Each time a critical +section is exited the count is decremented - with interrupts only being +re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as that could cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; + +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. + */ +__attribute__((weak)) void vApplicationSetupTimerInterrupt( void ); + +/* + * Starts the scheduler by loading the context of the first task to run. + * (defined in portasm.S). + */ +extern void vPortStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint32_t *pulLocal; + + /* Stack type and pointers to the stack type are both 2 bytes. */ + + /* Parameters are passed in on the stack, and written using a 32bit value + hence a space is left for the second two bytes. */ + pxTopOfStack--; + + /* Write in the parameter value. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( StackType_t ) pvParameters; + pxTopOfStack--; + + /* The return address, leaving space for the first two bytes of the + 32-bit value. */ + pxTopOfStack--; + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( uint32_t ) 0; + pxTopOfStack--; + + /* The start address / PSW value is also written in as a 32bit value, + so leave a space for the second two bytes. */ + pxTopOfStack--; + + /* Task function start address combined with the PSW. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + + /* An initial value for the AX register. */ + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + + /* An initial value for the HL register. */ + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + + /* CS and ES registers. */ + *pxTopOfStack = ( StackType_t ) 0x0F00; + pxTopOfStack--; + + /* The remaining general purpose registers bank 0 (DE and BC) and the other + two register banks...register bank 3 is dedicated for use by interrupts so + is not saved as part of the task context. */ + pxTopOfStack -= 10; + + /* Finally the critical section nesting count is set to zero when the task + first starts. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack that has beene generated so it + can be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + vApplicationSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + vPortStartFirstTask(); + + /* Execution should not reach here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the RL78 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +__attribute__((weak)) void vApplicationSetupTimerInterrupt( void ) +{ +const uint16_t usClockHz = 15000UL; /* Internal clock. */ +const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL; + + /* Use the internal 15K clock. */ + OSMC = ( unsigned char ) 0x16; + + #ifdef RTCEN + { + /* Supply the interval timer clock. */ + RTCEN = ( unsigned char ) 1U; + + /* Disable INTIT interrupt. */ + ITMK = ( unsigned char ) 1; + + /* Disable ITMC operation. */ + ITMC = ( unsigned char ) 0x0000; + + /* Clear INIT interrupt. */ + ITIF = ( unsigned char ) 0; + + /* Set interval and enable interrupt operation. */ + ITMC = usCompareMatch | 0x8000U; + + /* Enable INTIT interrupt. */ + ITMK = ( unsigned char ) 0; + } + #endif + + #ifdef TMKAEN + { + /* Supply the interval timer clock. */ + TMKAEN = ( unsigned char ) 1U; + + /* Disable INTIT interrupt. */ + TMKAMK = ( unsigned char ) 1; + + /* Disable ITMC operation. */ + ITMC = ( unsigned char ) 0x0000; + + /* Clear INIT interrupt. */ + TMKAIF = ( unsigned char ) 0; + + /* Set interval and enable interrupt operation. */ + ITMC = usCompareMatch | 0x8000U; + + /* Enable INTIT interrupt. */ + TMKAMK = ( unsigned char ) 0; + } + #endif +} +/*-----------------------------------------------------------*/ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RL78/portasm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RL78/portasm.S new file mode 100644 index 0000000..e1db8cb --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RL78/portasm.S @@ -0,0 +1,81 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + + .global _vPortYield + .global _vPortStartFirstTask + .global _vPortTickISR + + .extern _vTaskSwitchContext + .extern _xTaskIncrementTick + + .text + .align 2 + +/* FreeRTOS yield handler. This is installed as the BRK software interrupt +handler. */ +_vPortYield: + /* Save the context of the current task. */ + portSAVE_CONTEXT + /* Call the scheduler to select the next task. */ + call !!_vTaskSwitchContext + /* Restore the context of the next task to run. */ + portRESTORE_CONTEXT + retb + + +/* Starts the scheduler by restoring the context of the task that will execute +first. */ + .align 2 +_vPortStartFirstTask: + /* Restore the context of whichever task will execute first. */ + portRESTORE_CONTEXT + /* An interrupt stack frame is used so the task is started using RETI. */ + reti + +/* FreeRTOS tick handler. This is installed as the interval timer interrupt +handler. */ + .align 2 +_vPortTickISR: + + /* Save the context of the currently executing task. */ + portSAVE_CONTEXT + /* Call the RTOS tick function. */ + call !!_xTaskIncrementTick +#if configUSE_PREEMPTION == 1 + /* Select the next task to run. */ + call !!_vTaskSwitchContext +#endif + /* Retore the context of whichever task will run next. */ + portRESTORE_CONTEXT + reti + + .end + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RL78/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RL78/portmacro.h new file mode 100644 index 0000000..5f164ff --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RL78/portmacro.h @@ -0,0 +1,122 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short +#define portPOINTER_SIZE_TYPE uint16_t + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() __asm volatile ( "DI" ) +#define portENABLE_INTERRUPTS() __asm volatile ( "EI" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned short ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portYIELD() __asm volatile ( "BRK" ) +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 ) +#define portNOP() __asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Hardwware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX100/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX100/port.c new file mode 100644 index 0000000..0a5db55 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX100/port.c @@ -0,0 +1,701 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the SH2A port. + *----------------------------------------------------------*/ + +/* Standard C includes. */ +#include "limits.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) + +/* The peripheral clock is divided by this value before being supplying the +CMT. */ +#if ( configUSE_TICKLESS_IDLE == 0 ) + /* If tickless idle is not used then the divisor can be fixed. */ + #define portCLOCK_DIVISOR 8UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 ) + #define portCLOCK_DIVISOR 512UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 ) + #define portCLOCK_DIVISOR 128UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 ) + #define portCLOCK_DIVISOR 32UL +#else + #define portCLOCK_DIVISOR 8UL +#endif + +/* These macros allow a critical section to be added around the call to +xTaskIncrementTick(), which is only ever called from interrupts at the kernel +priority - ie a known priority. Therefore these local macros are a slight +optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, +which would require the old IPL to be read first and stored in a local variable. */ +#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) +#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) ) + +/* Keys required to lock and unlock access to certain system registers +respectively. */ +#define portUNLOCK_KEY 0xA50B +#define portLOCK_KEY 0xA500 + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ) __attribute__((naked)); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vPortSoftwareInterruptISR, VECT( ICU, SWINT ) ) + R_BSP_ATTRIB_INTERRUPT void vPortSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vPortSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vPortTickISR, _VECT( configTICK_VECTOR ) ) + R_BSP_ATTRIB_INTERRUPT void vPortTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */ + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vPortTickISR( void ) __attribute__( ( interrupt ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/* + * Sets up the periodic ISR used for the RTOS tick using the CMT. + * The application writer can define configSETUP_TICK_INTERRUPT() (in + * FreeRTOSConfig.h) such that their own tick interrupt configuration is used + * in place of prvSetupTimerInterrupt(). + */ +static void prvSetupTimerInterrupt( void ); +#ifndef configSETUP_TICK_INTERRUPT + /* The user has not provided their own tick interrupt configuration so use + the definition in this file (which uses the interval timer). */ + #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt() +#endif /* configSETUP_TICK_INTERRUPT */ + +/* + * Called after the sleep mode registers have been configured, prvSleep() + * executes the pre and post sleep macros, and actually calls the wait + * instruction. + */ +#if configUSE_TICKLESS_IDLE == 1 + static void prvSleep( TickType_t xExpectedIdleTime ); +#endif /* configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +/* Used in the context save and restore code. */ +extern void *pxCurrentTCB; + +/* Calculate how many clock increments make up a single tick period. */ +static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + +#if configUSE_TICKLESS_IDLE == 1 + + /* Holds the maximum number of ticks that can be suppressed - which is + basically how far into the future an interrupt can be generated. Set + during initialisation. This is the maximum possible value that the + compare match register can hold divided by ulMatchValueForOneTick. */ + static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + + /* Flag set from the tick interrupt to allow the sleep processing to know if + sleep mode was exited because of a tick interrupt, or an interrupt + generated by something else. */ + static volatile uint32_t ulTickFlag = pdFALSE; + + /* The CMT counter is stopped temporarily each time it is re-programmed. + The following constant offsets the CMT counter match value by the number of + CMT counts that would typically be missed while the counter was stopped to + compensate for the lost time. The large difference between the divided CMT + clock and the CPU clock means it is likely ulStoppedTimerCompensation will + equal zero - and be optimised away. */ + static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) ); + +#endif + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Offset to end up on 8 byte boundary. */ + pxTopOfStack--; + + /* R0 is not included as it is the stack pointer. */ + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xaaaabbbb; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + /* Leave space for the registers that will get popped from the stack + when the task first starts executing. */ + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate + the tick interrupt. This way the application can decide which + peripheral to use. If tickless mode is used then the default + implementation defined in this file (which uses CMT0) should not be + overridden. */ + configSETUP_TICK_INTERRUPT(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Execution should not reach here as the tasks are now running! + prvSetupTimerInterrupt() is called here to prevent the compiler outputting + a warning about a statically declared function not being referenced in the + case that the application writer has provided their own tick interrupt + configuration routine (and defined configSETUP_TICK_INTERRUPT() such that + their own routine will be called in place of prvSetupTimerInterrupt()). */ + prvSetupTimerInterrupt(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvStartFirstTask( void ) +{ + __asm volatile + ( + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + "SETPSW U \n" \ + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "MOV.L [R15], R0 \n" \ + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15 \n" \ + + /* R1 to R15 - R0 is not included as it is the SP. */ + "POPM R1-R15 \n" \ + + /* This pops the remaining registers. */ + "RTE \n" \ + "NOP \n" \ + "NOP \n" + ); +} +/*-----------------------------------------------------------*/ + +void vPortSoftwareInterruptISR( void ) +{ + __asm volatile + ( + /* Re-enable interrupts. */ + "SETPSW I \n" \ + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + "PUSH.L R15 \n" \ + + /* Read the user stack pointer. */ + "MVFC USP, R15 \n" \ + + /* Move the address down to the data being moved. */ + "SUB #12, R15 \n" \ + "MVTC R15, USP \n" \ + + /* Copy the data across, R15, then PC, then PSW. */ + "MOV.L [ R0 ], [ R15 ] \n" \ + "MOV.L 4[ R0 ], 4[ R15 ] \n" \ + "MOV.L 8[ R0 ], 8[ R15 ] \n" \ + + /* Move the interrupt stack pointer to its new correct position. */ + "ADD #12, R0 \n" \ + + /* All the rest of the registers are saved directly to the user stack. */ + "SETPSW U \n" \ + + /* Save the rest of the general registers (R15 has been saved already). */ + "PUSHM R1-R14 \n" \ + + /* Save the accumulator. */ + "MVFACHI R15 \n" \ + "PUSH.L R15 \n" \ + + /* Middle word. */ + "MVFACMI R15 \n" \ + + /* Shifted left as it is restored to the low order word. */ + "SHLL #16, R15 \n" \ + "PUSH.L R15 \n" \ + + /* Save the stack pointer to the TCB. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L R0, [ R15 ] \n" \ + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + "MVTIPL %0 \n" \ + + /* Select the next task to run. */ + "BSR.A _vTaskSwitchContext \n" \ + + /* Reset the interrupt mask as no more data structure access is required. */ + "MVTIPL %1 \n" \ + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + "MOV.L #_pxCurrentTCB,R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L [ R15 ], R0 \n" \ + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + "POP R15 \n" \ + "MVTACLO R15 \n" \ + "POP R15 \n" \ + "MVTACHI R15 \n" \ + "POPM R1-R15 \n" \ + "RTE \n" \ + "NOP \n" \ + "NOP " + :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY) + ); +} +/*-----------------------------------------------------------*/ + +void vPortTickISR( void ) +{ + /* Re-enabled interrupts. */ + __asm volatile( "SETPSW I" ); + + /* Increment the tick, and perform any processing the new tick value + necessitates. Ensure IPL is at the max syscall value first. */ + portDISABLE_INTERRUPTS_FROM_KERNEL_ISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + portENABLE_INTERRUPTS_FROM_KERNEL_ISR(); + + #if configUSE_TICKLESS_IDLE == 1 + { + /* The CPU woke because of a tick. */ + ulTickFlag = pdTRUE; + + /* If this is the first tick since exiting tickless mode then the CMT + compare match value needs resetting. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + } + #endif +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortGetIPL( void ) +{ + __asm volatile + ( + "MVFC PSW, R1 \n" \ + "SHLR #24, R1 \n" \ + "RTS " + ); + + /* This will never get executed, but keeps the compiler from complaining. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortSetIPL( uint32_t ulNewIPL ) +{ + __asm volatile + ( + "PUSH R5 \n" \ + "MVFC PSW, R5 \n" \ + "SHLL #24, R1 \n" \ + "AND #-0F000001H, R5 \n" \ + "OR R1, R5 \n" \ + "MVTC R5, PSW \n" \ + "POP R5 \n" \ + "RTS " + ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Unlock. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Enable CMT0. */ + MSTP( CMT0 ) = 0; + + /* Lock again. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + + /* Divide the PCLK. */ + #if portCLOCK_DIVISOR == 512 + { + CMT0.CMCR.BIT.CKS = 3; + } + #elif portCLOCK_DIVISOR == 128 + { + CMT0.CMCR.BIT.CKS = 2; + } + #elif portCLOCK_DIVISOR == 32 + { + CMT0.CMCR.BIT.CKS = 1; + } + #elif portCLOCK_DIVISOR == 8 + { + CMT0.CMCR.BIT.CKS = 0; + } + #else + { + #error Invalid portCLOCK_DIVISOR setting + } + #endif + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + static void prvSleep( TickType_t xExpectedIdleTime ) + { + /* Allow the application to define some pre-sleep processing. */ + configPRE_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING() + means the application defined code has already executed the WAIT + instruction. */ + if( xExpectedIdleTime > 0 ) + { + __asm volatile( "WAIT" ); + } + + /* Allow the application to define some post sleep processing. */ + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount; + eSleepModeStatus eSleepAction; + + /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* Make sure the CMT reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Calculate the reload value required to wait xExpectedIdleTime tick + periods. */ + ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime; + if( ulMatchValue > ulStoppedTimerCompensation ) + { + /* Compensate for the fact that the CMT is going to be stopped + momentarily. */ + ulMatchValue -= ulStoppedTimerCompensation; + } + + /* Stop the CMT momentarily. The time the CMT is stopped for is + accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + /* Critical section using the global interrupt bit as the i bit is + automatically reset by the WAIT instruction. */ + __asm volatile( "CLRPSW i" ); + + /* The tick flag is set to false before sleeping. If it is true when + sleep mode is exited then sleep mode was probably exited because the + tick was suppressed for the entire xExpectedIdleTime period. */ + ulTickFlag = pdFALSE; + + /* If a context switch is pending then abandon the low power entry as + the context switch might have been pended by an external interrupt that + requires processing. */ + eSleepAction = eTaskConfirmSleepModeStatus(); + if( eSleepAction == eAbortSleep ) + { + /* Restart tick. */ + CMT.CMSTR0.BIT.STR0 = 1; + __asm volatile( "SETPSW i" ); + } + else if( eSleepAction == eNoTasksWaitingTimeout ) + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for software standby with all clocks stopped. */ + SYSTEM.SBYCR.BIT.SSBY = 1; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Sleep until something happens. Calling prvSleep() will + automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Restart the CMT. */ + CMT.CMSTR0.BIT.STR0 = 1; + } + else + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for deep sleep mode. */ + SYSTEM.MSTPCRC.BIT.DSLPE = 1; + SYSTEM.MSTPCRA.BIT.MSTPA28 = 1; + SYSTEM.SBYCR.BIT.SSBY = 0; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Adjust the match value to take into account that the current + time slice is already partially complete. */ + ulMatchValue -= ( uint32_t ) CMT0.CMCNT; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* Restart the CMT to count up to the new match value. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Sleep until something happens. Calling prvSleep() will + automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Stop CMT. Again, the time the SysTick is stopped for is + accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + ulCurrentCount = ( uint32_t ) CMT0.CMCNT; + + if( ulTickFlag != pdFALSE ) + { + /* The tick interrupt has already executed, although because + this function is called with the scheduler suspended the actual + tick processing will not occur until after this function has + exited. Reset the match value with whatever remains of this + tick period. */ + ulMatchValue = ulMatchValueForOneTick - ulCurrentCount; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* The tick interrupt handler will already have pended the tick + processing in the kernel. As the pending tick will be + processed as soon as this function exits, the tick value + maintained by the tick is stepped forward by one less than the + time spent sleeping. The actual stepping of the tick appears + later in this function. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + How many complete tick periods passed while the processor was + sleeping? */ + ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick; + + /* The match value is set to whatever fraction of a single tick + period remains. */ + ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick ); + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + } + + /* Restart the CMT so it runs up to the match value. The match value + will get set to the value required to generate exactly one tick period + the next time the CMT interrupt executes. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Wind the tick forward by the number of tick periods that the CPU + remained in a low power state. */ + vTaskStepTick( ulCompleteTickPeriods ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX100/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX100/portmacro.h new file mode 100644 index 0000000..ad70356 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX100/portmacro.h @@ -0,0 +1,150 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ +#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 +#endif + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile( "NOP" ) + +/* Save clobbered register, set ITU SWINR (at address 0x872E0), read the value +back to ensure it is set before continuing, then restore the clobbered +register. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "MOV.L #0x872E0, r5 \n\t" \ + "MOV.B #1, [r5] \n\t" \ + "MOV.L [r5], r5 \n\t" \ + ::: "r5" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) { portYIELD(); } } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) +#else + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +uint32_t ulPortGetIPL( void ) __attribute__((naked)); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked)); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) + +/* Tickless idle/low power functionality. */ +#if configUSE_TICKLESS_IDLE == 1 + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX100/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX100/readme.txt new file mode 100644 index 0000000..9e89a09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX100/readme.txt @@ -0,0 +1,72 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX200/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX200/port.c new file mode 100644 index 0000000..1e4bfa8 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX200/port.c @@ -0,0 +1,436 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the SH2A port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/* These macros allow a critical section to be added around the call to +xTaskIncrementTick(), which is only ever called from interrupts at the kernel +priority - ie a known priority. Therefore these local macros are a slight +optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, +which would require the old IPL to be read first and stored in a local variable. */ +#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) +#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ) __attribute__((naked)); + + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) ) + R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) ) + R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */ + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vTickISR( void ) __attribute__( ( interrupt ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +extern void *pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 1. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvStartFirstTask( void ) +{ + __asm volatile + ( + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + "SETPSW U \n" \ + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "MOV.L [R15], R0 \n" \ + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + + /* Floating point status word. */ + "MVTC R15, FPSW \n" \ + + /* R1 to R15 - R0 is not included as it is the SP. */ + "POPM R1-R15 \n" \ + + /* This pops the remaining registers. */ + "RTE \n" \ + "NOP \n" \ + "NOP \n" + ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + __asm volatile + ( + /* Re-enable interrupts. */ + "SETPSW I \n" \ + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + "PUSH.L R15 \n" \ + + /* Read the user stack pointer. */ + "MVFC USP, R15 \n" \ + + /* Move the address down to the data being moved. */ + "SUB #12, R15 \n" \ + "MVTC R15, USP \n" \ + + /* Copy the data across, R15, then PC, then PSW. */ + "MOV.L [ R0 ], [ R15 ] \n" \ + "MOV.L 4[ R0 ], 4[ R15 ] \n" \ + "MOV.L 8[ R0 ], 8[ R15 ] \n" \ + + /* Move the interrupt stack pointer to its new correct position. */ + "ADD #12, R0 \n" \ + + /* All the rest of the registers are saved directly to the user stack. */ + "SETPSW U \n" \ + + /* Save the rest of the general registers (R15 has been saved already). */ + "PUSHM R1-R14 \n" \ + + /* Save the FPSW and accumulator. */ + "MVFC FPSW, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + /* Low order word. */ + "MVFACLO #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + /* Low order word. */ + "MVFACLO #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + + /* Save the stack pointer to the TCB. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L R0, [ R15 ] \n" \ + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + "MVTIPL %0 \n" \ + + /* Select the next task to run. */ + "BSR.A _vTaskSwitchContext \n" \ + + /* Reset the interrupt mask as no more data structure access is required. */ + "MVTIPL %1 \n" \ + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + "MOV.L #_pxCurrentTCB,R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L [ R15 ], R0 \n" \ + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + "MVTC R15, FPSW \n" \ + "POPM R1-R15 \n" \ + "RTE \n" \ + "NOP \n" \ + "NOP " + :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY) + ); +} +/*-----------------------------------------------------------*/ + +void vTickISR( void ) +{ + /* Re-enabled interrupts. */ + __asm volatile( "SETPSW I" ); + + /* Increment the tick, and perform any processing the new tick value + necessitates. Ensure IPL is at the max syscall value first. */ + portMASK_INTERRUPTS_FROM_KERNEL_ISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + portUNMASK_INTERRUPTS_FROM_KERNEL_ISR(); +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortGetIPL( void ) +{ + __asm volatile + ( + "MVFC PSW, R1 \n" \ + "SHLR #24, R1 \n" \ + "RTS " + ); + + /* This will never get executed, but keeps the compiler from complaining. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortSetIPL( uint32_t ulNewIPL ) +{ + __asm volatile + ( + "PUSH R5 \n" \ + "MVFC PSW, R5 \n" \ + "SHLL #24, R1 \n" \ + "AND #-0F000001H, R5 \n" \ + "OR R1, R5 \n" \ + "MVTC R5, PSW \n" \ + "POP R5 \n" \ + "RTS " + ); +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX200/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX200/portmacro.h new file mode 100644 index 0000000..dec122b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX200/portmacro.h @@ -0,0 +1,145 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ +#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 +#endif + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile( "NOP" ) + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" +where portITU_SWINTR is the location of the software interrupt register +(0x000872E0). Don't rely on the assembler to select a register, so instead +save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD() + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) +#else + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +uint32_t ulPortGetIPL( void ) __attribute__((naked)); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked)); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600/port.c new file mode 100644 index 0000000..f79d198 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600/port.c @@ -0,0 +1,389 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the SH2A port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/* These macros allow a critical section to be added around the call to +xTaskIncrementTick(), which is only ever called from interrupts at the kernel +priority - ie a known priority. Therefore these local macros are a slight +optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, +which would require the old IPL to be read first and stored in a local variable. */ +#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) +#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ) __attribute__((naked)); +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) ) + R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) ) + R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */ + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vTickISR( void ) __attribute__( ( interrupt ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +extern void *pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvStartFirstTask( void ) +{ + __asm volatile + ( + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + "SETPSW U \n" \ + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "MOV.L [R15], R0 \n" \ + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15 \n" \ + "POP R15 \n" \ + + /* Floating point status word. */ + "MVTC R15, FPSW \n" \ + + /* R1 to R15 - R0 is not included as it is the SP. */ + "POPM R1-R15 \n" \ + + /* This pops the remaining registers. */ + "RTE \n" \ + "NOP \n" \ + "NOP \n" + ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + __asm volatile + ( + /* Re-enable interrupts. */ + "SETPSW I \n" \ + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + "PUSH.L R15 \n" \ + + /* Read the user stack pointer. */ + "MVFC USP, R15 \n" \ + + /* Move the address down to the data being moved. */ + "SUB #12, R15 \n" \ + "MVTC R15, USP \n" \ + + /* Copy the data across, R15, then PC, then PSW. */ + "MOV.L [ R0 ], [ R15 ] \n" \ + "MOV.L 4[ R0 ], 4[ R15 ] \n" \ + "MOV.L 8[ R0 ], 8[ R15 ] \n" \ + + /* Move the interrupt stack pointer to its new correct position. */ + "ADD #12, R0 \n" \ + + /* All the rest of the registers are saved directly to the user stack. */ + "SETPSW U \n" \ + + /* Save the rest of the general registers (R15 has been saved already). */ + "PUSHM R1-R14 \n" \ + + /* Save the FPSW and accumulator. */ + "MVFC FPSW, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI R15 \n" \ + "PUSH.L R15 \n" \ + + /* Middle word. */ + "MVFACMI R15 \n" \ + + /* Shifted left as it is restored to the low order word. */ + "SHLL #16, R15 \n" \ + "PUSH.L R15 \n" \ + + /* Save the stack pointer to the TCB. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L R0, [ R15 ] \n" \ + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + "MVTIPL %0 \n" \ + + /* Select the next task to run. */ + "BSR.A _vTaskSwitchContext \n" \ + + /* Reset the interrupt mask as no more data structure access is required. */ + "MVTIPL %1 \n" \ + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + "MOV.L #_pxCurrentTCB,R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L [ R15 ], R0 \n" \ + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + "POP R15 \n" \ + "MVTACLO R15 \n" \ + "POP R15 \n" \ + "MVTACHI R15 \n" \ + "POP R15 \n" \ + "MVTC R15, FPSW \n" \ + "POPM R1-R15 \n" \ + "RTE \n" \ + "NOP \n" \ + "NOP " + :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY) + ); +} +/*-----------------------------------------------------------*/ + +void vTickISR( void ) +{ + /* Re-enabled interrupts. */ + __asm volatile( "SETPSW I" ); + + /* Increment the tick, and perform any processing the new tick value + necessitates. Ensure IPL is at the max syscall value first. */ + portDISABLE_INTERRUPTS_FROM_KERNEL_ISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + portENABLE_INTERRUPTS_FROM_KERNEL_ISR(); +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortGetIPL( void ) +{ + __asm volatile + ( + "MVFC PSW, R1 \n" \ + "SHLR #24, R1 \n" \ + "RTS " + ); + + /* This will never get executed, but keeps the compiler from complaining. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortSetIPL( uint32_t ulNewIPL ) +{ + /* Avoid compiler warning about unreferenced parameter. */ + ( void ) ulNewIPL; + + __asm volatile + ( + "PUSH R5 \n" \ + "MVFC PSW, R5 \n" \ + "SHLL #24, R1 \n" \ + "AND #-0F000001H, R5 \n" \ + "OR R1, R5 \n" \ + "MVTC R5, PSW \n" \ + "POP R5 \n" \ + "RTS " + ); +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600/portmacro.h new file mode 100644 index 0000000..865cb95 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600/portmacro.h @@ -0,0 +1,145 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ +#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 +#endif + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile( "NOP" ) + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" +where portITU_SWINTR is the location of the software interrupt register +(0x000872E0). Don't rely on the assembler to select a register, so instead +save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) +#else + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +uint32_t ulPortGetIPL( void ) __attribute__((naked)); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked)); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600/readme.txt new file mode 100644 index 0000000..9e89a09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600/readme.txt @@ -0,0 +1,72 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600v2/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600v2/port.c new file mode 100644 index 0000000..8a7e3c4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600v2/port.c @@ -0,0 +1,433 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the SH2A port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/* These macros allow a critical section to be added around the call to +xTaskIncrementTick(), which is only ever called from interrupts at the kernel +priority - ie a known priority. Therefore these local macros are a slight +optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, +which would require the old IPL to be read first and stored in a local variable. */ +#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) +#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ) __attribute__((naked)); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) +R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) ) +R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ +void vSoftwareInterruptISR( void ) __attribute__((naked)); +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) ) + R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */ + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vTickISR( void ) __attribute__( ( interrupt ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ +/*-----------------------------------------------------------*/ + +extern void *pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 1. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvStartFirstTask( void ) +{ + __asm volatile + ( + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + "SETPSW U \n" \ + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "MOV.L [R15], R0 \n" \ + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + + /* Floating point status word. */ + "MVTC R15, FPSW \n" \ + + /* R1 to R15 - R0 is not included as it is the SP. */ + "POPM R1-R15 \n" \ + + /* This pops the remaining registers. */ + "RTE \n" \ + "NOP \n" \ + "NOP \n" + ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + __asm volatile + ( + /* Re-enable interrupts. */ + "SETPSW I \n" \ + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + "PUSH.L R15 \n" \ + + /* Read the user stack pointer. */ + "MVFC USP, R15 \n" \ + + /* Move the address down to the data being moved. */ + "SUB #12, R15 \n" \ + "MVTC R15, USP \n" \ + + /* Copy the data across, R15, then PC, then PSW. */ + "MOV.L [ R0 ], [ R15 ] \n" \ + "MOV.L 4[ R0 ], 4[ R15 ] \n" \ + "MOV.L 8[ R0 ], 8[ R15 ] \n" \ + + /* Move the interrupt stack pointer to its new correct position. */ + "ADD #12, R0 \n" \ + + /* All the rest of the registers are saved directly to the user stack. */ + "SETPSW U \n" \ + + /* Save the rest of the general registers (R15 has been saved already). */ + "PUSHM R1-R14 \n" \ + + /* Save the FPSW and accumulator. */ + "MVFC FPSW, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + /* Low order word. */ + "MVFACLO #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + /* Low order word. */ + "MVFACLO #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + + /* Save the stack pointer to the TCB. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L R0, [ R15 ] \n" \ + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + "MVTIPL %0 \n" \ + + /* Select the next task to run. */ + "BSR.A _vTaskSwitchContext \n" \ + + /* Reset the interrupt mask as no more data structure access is required. */ + "MVTIPL %1 \n" \ + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + "MOV.L #_pxCurrentTCB,R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L [ R15 ], R0 \n" \ + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + "MVTC R15, FPSW \n" \ + "POPM R1-R15 \n" \ + "RTE \n" \ + "NOP \n" \ + "NOP " + :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY) + ); +} +/*-----------------------------------------------------------*/ + +void vTickISR( void ) +{ + /* Re-enabled interrupts. */ + __asm volatile( "SETPSW I" ); + + /* Increment the tick, and perform any processing the new tick value + necessitates. Ensure IPL is at the max syscall value first. */ + portMASK_INTERRUPTS_FROM_KERNEL_ISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + portUNMASK_INTERRUPTS_FROM_KERNEL_ISR(); +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortGetIPL( void ) +{ + __asm volatile + ( + "MVFC PSW, R1 \n" \ + "SHLR #24, R1 \n" \ + "RTS " + ); + + /* This will never get executed, but keeps the compiler from complaining. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortSetIPL( uint32_t ulNewIPL ) +{ + /* Avoid compiler warning about unreferenced parameter. */ + ( void ) ulNewIPL; + + __asm volatile + ( + "PUSH R5 \n" \ + "MVFC PSW, R5 \n" \ + "SHLL #24, R1 \n" \ + "AND #-0F000001H, R5 \n" \ + "OR R1, R5 \n" \ + "MVTC R5, PSW \n" \ + "POP R5 \n" \ + "RTS " + ); +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600v2/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600v2/portmacro.h new file mode 100644 index 0000000..865cb95 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600v2/portmacro.h @@ -0,0 +1,145 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ +#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 +#endif + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile( "NOP" ) + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" +where portITU_SWINTR is the location of the software interrupt register +(0x000872E0). Don't rely on the assembler to select a register, so instead +save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) +#else + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +uint32_t ulPortGetIPL( void ) __attribute__((naked)); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked)); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600v2/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600v2/readme.txt new file mode 100644 index 0000000..9e89a09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX600v2/readme.txt @@ -0,0 +1,72 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX700v3_DPFPU/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX700v3_DPFPU/port.c new file mode 100644 index 0000000..419b91c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX700v3_DPFPU/port.c @@ -0,0 +1,622 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the RXv3 DPFPU port. +*----------------------------------------------------------*/ + +#warning Testing for DFPU support in this port is not yet complete + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DCMR ( ( StackType_t ) 0x00000000 ) +#define portINITIAL_DECNT ( ( StackType_t ) 0x00000001 ) + +/* Tasks are not created with a DPFPU context, but can be given a DPFPU context + * after they have been created. A variable is stored as part of the tasks context + * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or + * any other value if the task does have a DPFPU context. */ +#define portNO_DPFPU_CONTEXT ( ( StackType_t ) 0 ) +#define portHAS_DPFPU_CONTEXT ( ( StackType_t ) 1 ) + +/* The space on the stack required to hold the DPFPU data registers. This is 16 + * 64-bit registers. */ +#define portDPFPU_DATA_REGISTER_WORDS ( 16 * 2 ) + +/* These macros allow a critical section to be added around the call to + * xTaskIncrementTick(), which is only ever called from interrupts at the kernel + * priority - ie a known priority. Therefore these local macros are a slight + * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, + * which would require the old IPL to be read first and stored in a local variable. */ +#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) ) + R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) ) + R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */ + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vTickISR( void ) __attribute__( ( interrupt ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +/* Saved as part of the task context. If ulPortTaskHasDPFPUContext is non-zero + * then a DPFPU context must be saved and restored for the task. */ +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + StackType_t ulPortTaskHasDPFPUContext = portNO_DPFPU_CONTEXT; + +#endif /* configUSE_TASK_DPFPU_SUPPORT */ + +/* This is accessed by the inline assembler functions so is file scope for + * convenience. */ +extern void * pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= 15; + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 0. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + { + /* The task will start without a DPFPU context. A task that + * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before + * executing any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_DPFPU_CONTEXT; + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + { + /* The task will start with a DPFPU context. Leave enough + * space for the registers - and ensure they are initialised if desired. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1515.1515; /* DR15. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1414.1414; /* DR14. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1313.1313; /* DR13. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1212.1212; /* DR12. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1111.1111; /* DR11. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1010.1010; /* DR10. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 909.0909; /* DR9. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 808.0808; /* DR8. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 707.0707; /* DR7. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 606.0606; /* DR6. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 505.0505; /* DR5. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 404.0404; /* DR4. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 303.0303; /* DR3. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 202.0202; /* DR2. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 101.0101; /* DR1. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 9876.54321;/* DR0. */ + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) ); + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DCMR; /* DCMR. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DPSW; /* DPSW. */ + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 ) + { + /* Omit DPFPU support. */ + } + #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + { + #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined. + } + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + void vPortTaskUsesDPFPU( void ) + { + /* A task is registering the fact that it needs a DPFPU context. Set the + * DPFPU flag (which is saved as part of the task context). */ + ulPortTaskHasDPFPUContext = portHAS_DPFPU_CONTEXT; + } + +#endif /* configUSE_TASK_DPFPU_SUPPORT */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvStartFirstTask( void ) +{ + __asm volatile + ( + + /* When starting the scheduler there is nothing that needs moving to the + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ + "SETPSW U \n"\ + + + /* Obtain the location of the stack associated with which ever task + * pxCurrentTCB is currently pointing to. */ + "MOV.L #_pxCurrentTCB, R15 \n"\ + "MOV.L [R15], R15 \n"\ + "MOV.L [R15], R0 \n"\ + + + /* Restore the registers from the stack of the task pointed to by + * pxCurrentTCB. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* The restored ulPortTaskHasDPFPUContext is to be zero here. + * So, it is never necessary to restore the DPFPU context here. */ + "POP R15 \n"\ + "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n"\ + "MOV.L R15, [R14] \n"\ + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + + /* Restore the DPFPU context. */ + "DPOPM.L DPSW-DECNT \n"\ + "DPOPM.D DR0-DR15 \n"\ + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + "POP R15 \n"\ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n"\ + "POP R15 \n"\ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n"\ + "POP R15 \n"\ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n"\ + "POP R15 \n"\ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n"\ + "POP R15 \n"\ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n"\ + "POP R15 \n"\ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n"\ + "POP R15 \n"\ + + /* Floating point status word. */ + "MVTC R15, FPSW \n"\ + + /* R1 to R15 - R0 is not included as it is the SP. */ + "POPM R1-R15 \n"\ + + /* This pops the remaining registers. */ + "RTE \n"\ + "NOP \n"\ + "NOP \n" + ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + __asm volatile + ( + /* Re-enable interrupts. */ + "SETPSW I \n"\ + + + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ + "PUSH.L R15 \n"\ + + /* Read the user stack pointer. */ + "MVFC USP, R15 \n"\ + + /* Move the address down to the data being moved. */ + "SUB #12, R15 \n"\ + "MVTC R15, USP \n"\ + + /* Copy the data across, R15, then PC, then PSW. */ + "MOV.L [ R0 ], [ R15 ] \n"\ + "MOV.L 4[ R0 ], 4[ R15 ] \n"\ + "MOV.L 8[ R0 ], 8[ R15 ] \n"\ + + /* Move the interrupt stack pointer to its new correct position. */ + "ADD #12, R0 \n"\ + + /* All the rest of the registers are saved directly to the user stack. */ + "SETPSW U \n"\ + + /* Save the rest of the general registers (R15 has been saved already). */ + "PUSHM R1-R14 \n"\ + + /* Save the FPSW and accumulators. */ + "MVFC FPSW, R15 \n"\ + "PUSH.L R15 \n"\ + "MVFACGU #0, A1, R15 \n"\ + "PUSH.L R15 \n"\ + "MVFACHI #0, A1, R15 \n"\ + "PUSH.L R15 \n"\ + "MVFACLO #0, A1, R15 \n" /* Low order word. */ \ + "PUSH.L R15 \n"\ + "MVFACGU #0, A0, R15 \n"\ + "PUSH.L R15 \n"\ + "MVFACHI #0, A0, R15 \n"\ + "PUSH.L R15 \n"\ + "MVFACLO #0, A0, R15 \n" /* Low order word. */ \ + "PUSH.L R15 \n"\ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* Does the task have a DPFPU context that needs saving? If + * ulPortTaskHasDPFPUContext is 0 then no. */ + "MOV.L #_ulPortTaskHasDPFPUContext, R15 \n"\ + "MOV.L [R15], R15 \n"\ + "CMP #0, R15 \n"\ + + /* Save the DPFPU context, if any. */ + "BEQ.B ?+ \n"\ + "DPUSHM.D DR0-DR15 \n"\ + "DPUSHM.L DPSW-DECNT \n"\ + "?: \n"\ + + /* Save ulPortTaskHasDPFPUContext itself. */ + "PUSH.L R15 \n"\ + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + + /* Save the DPFPU context, always. */ + "DPUSHM.D DR0-DR15 \n"\ + "DPUSHM.L DPSW-DECNT \n"\ + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + + /* Save the stack pointer to the TCB. */ + "MOV.L #_pxCurrentTCB, R15 \n"\ + "MOV.L [ R15 ], R15 \n"\ + "MOV.L R0, [ R15 ] \n"\ + + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + * structures are being accessed. */ + "MVTIPL %0 \n"\ + + /* Select the next task to run. */ + "BSR.A _vTaskSwitchContext \n"\ + + /* Reset the interrupt mask as no more data structure access is required. */ + "MVTIPL %1 \n"\ + + + /* Load the stack pointer of the task that is now selected as the Running + * state task from its TCB. */ + "MOV.L #_pxCurrentTCB,R15 \n"\ + "MOV.L [ R15 ], R15 \n"\ + "MOV.L [ R15 ], R0 \n"\ + + + /* Restore the context of the new task. The PSW (Program Status Word) and + * PC will be popped by the RTE instruction. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* Is there a DPFPU context to restore? If the restored + * ulPortTaskHasDPFPUContext is zero then no. */ + "POP R15 \n"\ + "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n"\ + "MOV.L R15, [R14] \n"\ + "CMP #0, R15 \n"\ + + /* Restore the DPFPU context, if any. */ + "BEQ.B ?+ \n"\ + "DPOPM.L DPSW-DECNT \n"\ + "DPOPM.D DR0-DR15 \n"\ + "?: \n"\ + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + + /* Restore the DPFPU context, always. */ + "DPOPM.L DPSW-DECNT \n"\ + "DPOPM.D DR0-DR15 \n"\ + + #endif /* if( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + "POP R15 \n"\ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n"\ + "POP R15 \n"\ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n"\ + "POP R15 \n"\ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n"\ + "POP R15 \n"\ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n"\ + "POP R15 \n"\ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n"\ + "POP R15 \n"\ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n"\ + "POP R15 \n"\ + "MVTC R15, FPSW \n"\ + "POPM R1-R15 \n"\ + "RTE \n"\ + "NOP \n"\ + "NOP " + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void vTickISR( void ) +{ + /* Re-enabled interrupts. */ + __asm volatile ( "SETPSW I"); + + /* Increment the tick, and perform any processing the new tick value + * necessitates. Ensure IPL is at the max syscall value first. */ + portMASK_INTERRUPTS_FROM_KERNEL_ISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + portUNMASK_INTERRUPTS_FROM_KERNEL_ISR(); +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortGetIPL( void ) +{ + __asm volatile + ( + "MVFC PSW, R1 \n"\ + "SHLR #24, R1 \n"\ + "RTS " + ); + + /* This will never get executed, but keeps the compiler from complaining. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortSetIPL( uint32_t ulNewIPL ) +{ + /* Avoid compiler warning about unreferenced parameter. */ + ( void ) ulNewIPL; + + __asm volatile + ( + "PUSH R5 \n"\ + "MVFC PSW, R5 \n"\ + "SHLL #24, R1 \n"\ + "AND #-0F000001H, R5 \n"\ + "OR R1, R5 \n"\ + "MVTC R5, PSW \n"\ + "POP R5 \n"\ + "RTS " + ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX700v3_DPFPU/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX700v3_DPFPU/portmacro.h new file mode 100644 index 0000000..a254703 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX700v3_DPFPU/portmacro.h @@ -0,0 +1,187 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ + #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 + #endif + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will + * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before + * making use of any DPFPU registers. If configUSE_TASK_DPFPU_SUPPORT is set to 2 then + * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has + * no effect. If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care + * of any DPFPU context (even if DPFPU registers are used). */ + #ifndef configUSE_TASK_DPFPU_SUPPORT + #define configUSE_TASK_DPFPU_SUPPORT 1 + #endif + +/*-----------------------------------------------------------*/ + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ + #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ + #define portSTACK_GROWTH -1 + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portNOP() __asm volatile ( "NOP" ) + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ + #define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n"\ + "MOV.L #0x872E0, R10 \n"\ + "MOV.B #0x1, [R10] \n"\ + "CMP [R10].UB, R10 \n"\ + "POP R10 \n"\ + :::"cc" \ + ) + + #define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 ) + +/* Workaround to reduce errors/warnings caused by e2 studio CDT's INDEXER and CODAN. */ + #ifdef __CDT_PARSER__ + #ifndef __asm + #define __asm asm + #endif + #ifndef __attribute__ + #define __attribute__( ... ) + #endif + #endif + +/* These macros should not be called directly, but through the + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ + #define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0") + #ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #else + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #endif + +/* Critical nesting counts are stored in the TCB. */ + #define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ + uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); + void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/*-----------------------------------------------------------*/ + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or left undefined) then tasks are + * created without a DPFPU context and must call vPortTaskUsesDPFPU() to give + * themselves a DPFPU context before using any DPFPU instructions. If + * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context + * by default. */ + #if( configUSE_TASK_DPFPU_SUPPORT == 1 ) + void vPortTaskUsesDPFPU( void ); + #else +/* Each task has a DPFPU context already, so define this function away to + * nothing to prevent it being called accidentally. */ + #define vPortTaskUsesDPFPU() + #endif + #define portTASK_USES_DPFPU() vPortTaskUsesDPFPU() + +/* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */ + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU() + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX700v3_DPFPU/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX700v3_DPFPU/readme.txt new file mode 100644 index 0000000..9e89a09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/RX700v3_DPFPU/readme.txt @@ -0,0 +1,72 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/STR75x/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/STR75x/port.c new file mode 100644 index 0000000..f442f34 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/STR75x/port.c @@ -0,0 +1,198 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ST STR75x ARM7 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include "75x_tb.h" +#include "75x_eic.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Prescale used on the timer clock when calculating the tick period. */ +#define portPRESCALE 20 + + +/*-----------------------------------------------------------*/ + +/* Setup the TB to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortISRStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +EIC_IRQInitTypeDef EIC_IRQInitStructure; +TB_InitTypeDef TB_InitStructure; + + /* Setup the EIC for the TB. */ + EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; + EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel; + EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; + EIC_IRQInit(&EIC_IRQInitStructure); + + /* Setup the TB for the generation of the tick interrupt. */ + TB_InitStructure.TB_Mode = TB_Mode_Timing; + TB_InitStructure.TB_CounterMode = TB_CounterMode_Down; + TB_InitStructure.TB_Prescaler = portPRESCALE - 1; + TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ ); + TB_Init(&TB_InitStructure); + + /* Enable TB Update interrupt */ + TB_ITConfig(TB_IT_Update, ENABLE); + + /* Clear TB Update interrupt pending bit */ + TB_ClearITPendingBit(TB_IT_Update); + + /* Enable TB */ + TB_Cmd(ENABLE); +} +/*-----------------------------------------------------------*/ + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/STR75x/portISR.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/STR75x/portISR.c new file mode 100644 index 0000000..6c91925 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/STR75x/portISR.c @@ -0,0 +1,183 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +volatile uint32_t ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); +} +/*-----------------------------------------------------------*/ + +void vPortTickISR( void ) +{ + /* Increment the RTOS tick count, then look for the highest priority + task that is ready to run. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Ready for the next interrupt. */ + TB_ClearITPendingBit( TB_IT_Update ); +} + +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + void vPortDisableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/STR75x/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/STR75x/portmacro.h new file mode 100644 index 0000000..9af3a01 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/STR75x/portmacro.h @@ -0,0 +1,142 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm volatile ( "SWI 0" ) +#define portNOP() asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/TriCore_1782/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/TriCore_1782/port.c new file mode 100644 index 0000000..562b64a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/TriCore_1782/port.c @@ -0,0 +1,542 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* TriCore specific includes. */ +#include +#include +#include +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "list.h" + +#if configCHECK_FOR_STACK_OVERFLOW > 0 + #error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA. CSA starvation, loosely equivalent to stack overflow, will result in a trap exception." + /* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */ +#endif /* configCHECK_FOR_STACK_OVERFLOW */ + + +/*-----------------------------------------------------------*/ + +/* System register Definitions. */ +#define portSYSTEM_PROGRAM_STATUS_WORD ( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */ +#define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD ( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */ +#define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD ( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */ +#define portINITIAL_PCXI_UPPER_CONTEXT_WORD ( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */ +#define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */ + +/* CSA manipulation macros. */ +#define portCSA_FCX_MASK ( 0x000FFFFFUL ) + +/* OS Interrupt and Trap mechanisms. */ +#define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) ) +#define portSYSCALL_TRAP ( 6 ) + +/* Each CSA contains 16 words of data. */ +#define portNUM_WORDS_IN_CSA ( 16 ) + +/* The interrupt enable bit in the PCP_SRC register. */ +#define portENABLE_CPU_INTERRUPT ( 1U << 12U ) +/*-----------------------------------------------------------*/ + +/* + * Perform any hardware configuration necessary to generate the tick interrupt. + */ +static void prvSystemTickHandler( int ) __attribute__((longcall)); +static void prvSetupTimerInterrupt( void ); + +/* + * Trap handler for yields. + */ +static void prvTrapYield( int iTrapIdentification ); + +/* + * Priority 1 interrupt handler for yields pended from an interrupt. + */ +static void prvInterruptYield( int iTrapIdentification ); + +/*-----------------------------------------------------------*/ + +/* This reference is required by the save/restore context macros. */ +extern volatile uint32_t *pxCurrentTCB; + +/* Precalculate the compare match value at compile time. */ +static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ); + +/*-----------------------------------------------------------*/ + +StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint32_t *pulUpperCSA = NULL; +uint32_t *pulLowerCSA = NULL; + + /* 16 Address Registers (4 Address registers are global), 16 Data + Registers, and 3 System Registers. + + There are 3 registers that track the CSAs. + FCX points to the head of globally free set of CSAs. + PCX for the task needs to point to Lower->Upper->NULL arrangement. + LCX points to the last free CSA so that corrective action can be taken. + + Need two CSAs to store the context of a task. + The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL. + The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext. + The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR. + The Lower Context points to the Upper Context ready for the return from the interrupt handler. + + The Real stack pointer for the task is stored in the A10 which is restored + with the upper context. */ + + /* Have to disable interrupts here because the CSAs are going to be + manipulated. */ + portENTER_CRITICAL(); + { + /* DSync to ensure that buffering is not a problem. */ + _dsync(); + + /* Consume two free CSAs. */ + pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) ); + if( NULL != pulLowerCSA ) + { + /* The Lower Links to the Upper. */ + pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] ); + } + + /* Check that we have successfully reserved two CSAs. */ + if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) ) + { + /* Remove the two consumed CSAs from the free CSA list. */ + _disable(); + _dsync(); + _mtcr( $FCX, pulUpperCSA[ 0 ] ); + _isync(); + _enable(); + } + else + { + /* Simply trigger a context list depletion trap. */ + _svlcx(); + } + } + portEXIT_CRITICAL(); + + /* Clear the upper CSA. */ + memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) ); + + /* Upper Context. */ + pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack; /* A10; Stack Return aka Stack Pointer */ + pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */ + + /* Clear the lower CSA. */ + memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) ); + + /* Lower Context. */ + pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4; Address Type Parameter Register */ + pulLowerCSA[ 1 ] = ( uint32_t ) pxCode; /* A11; Return Address aka RA */ + + /* PCXI pointing to the Upper context. */ + pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) ); + + /* Save the link to the CSA in the top of stack. */ + pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA ); + + /* DSync to ensure that buffering is not a problem. */ + _dsync(); + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +int32_t xPortStartScheduler( void ) +{ +extern void vTrapInstallHandlers( void ); +uint32_t ulMFCR = 0UL; +uint32_t *pulUpperCSA = NULL; +uint32_t *pulLowerCSA = NULL; + + /* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable + when this function is called. */ + + /* Set-up the timer interrupt. */ + prvSetupTimerInterrupt(); + + /* Install the Trap Handlers. */ + vTrapInstallHandlers(); + + /* Install the Syscall Handler for yield calls. */ + if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) ) + { + /* Failed to install the yield handler, force an assert. */ + configASSERT( ( ( volatile void * ) NULL ) ); + } + + /* Enable then install the priority 1 interrupt for pending context + switches from an ISR. See mod_SRC in the TriCore manual. */ + CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY ); + if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) ) + { + /* Failed to install the yield handler, force an assert. */ + configASSERT( ( ( volatile void * ) NULL ) ); + } + + _disable(); + + /* Load the initial SYSCON. */ + _mtcr( $SYSCON, portINITIAL_SYSCON ); + _isync(); + + /* ENDINIT has already been applied in the 'cstart.c' code. */ + + /* Clear the PSW.CDC to enable the use of an RFE without it generating an + exception because this code is not genuinely in an exception. */ + ulMFCR = __MFCR( $PSW ); + ulMFCR &= portRESTORE_PSW_MASK; + _dsync(); + _mtcr( $PSW, ulMFCR ); + _isync(); + + /* Finally, perform the equivalent of a portRESTORE_CONTEXT() */ + pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) ); + pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] ); + _dsync(); + _mtcr( $PCXI, *pxCurrentTCB ); + _isync(); + _nop(); + _rslcx(); + _nop(); + + /* Return to the first task selected to execute. */ + __asm volatile( "rfe" ); + + /* Will not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Set-up the clock divider. */ + unlock_wdtcon(); + { + /* Wait until access to Endint protected register is enabled. */ + while( 0 != ( WDT_CON0.reg & 0x1UL ) ); + + /* RMC == 1 so STM Clock == FPI */ + STM_CLC.reg = ( 1UL << 8 ); + } + lock_wdtcon(); + + /* Determine how many bits are used without changing other bits in the CMCON register. */ + STM_CMCON.reg &= ~( 0x1fUL ); + STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) ); + + /* Take into account the current time so a tick doesn't happen immediately. */ + STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg; + + if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) ) + { + /* Set-up the interrupt. */ + STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL ); + + /* Enable the Interrupt. */ + STM_ISRR.reg &= ~( 0x03UL ); + STM_ISRR.reg |= 0x1UL; + STM_ISRR.reg &= ~( 0x07UL ); + STM_ICR.reg |= 0x1UL; + } + else + { + /* Failed to install the Tick Interrupt. */ + configASSERT( ( ( volatile void * ) NULL ) ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSystemTickHandler( int iArg ) +{ +uint32_t ulSavedInterruptMask; +uint32_t *pxUpperCSA = NULL; +uint32_t xUpperCSA = 0UL; +extern volatile uint32_t *pxCurrentTCB; +int32_t lYieldRequired; + + /* Just to avoid compiler warnings about unused parameters. */ + ( void ) iArg; + + /* Clear the interrupt source. */ + STM_ISRR.reg = 1UL; + + /* Reload the Compare Match register for X ticks into the future. + + If critical section or interrupt nesting budgets are exceeded, then + it is possible that the calculated next compare match value is in the + past. If this occurs (unlikely), it is possible that the resulting + time slippage will exceed a single tick period. Any adverse effect of + this is time bounded by the fact that only the first n bits of the 56 bit + STM timer are being used for a compare match, so another compare match + will occur after an overflow in just those n bits (not the entire 56 bits). + As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz, + a missed tick could result in the next tick interrupt occurring within a + time that is 1.7 times the desired period. The fact that this is greater + than a single tick period is an effect of using a timer that cannot be + automatically reset, in hardware, by the occurrence of a tick interrupt. + Changing the tick source to a timer that has an automatic reset on compare + match (such as a GPTA timer) will reduce the maximum possible additional + period to exactly 1 times the desired period. */ + STM_CMP0.reg += ulCompareMatchValue; + + /* Kernel API calls require Critical Sections. */ + ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the Tick. */ + lYieldRequired = xTaskIncrementTick(); + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); + + if( lYieldRequired != pdFALSE ) + { + /* Save the context of a task. + The upper context is automatically saved when entering a trap or interrupt. + Need to save the lower context as well and copy the PCXI CSA ID into + pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the + TCB of a task. + + Call vTaskSwitchContext to select the next task, note that this changes the + value of pxCurrentTCB so that it needs to be reloaded. + + Call vPortSetMPURegisterSetOne to change the MPU mapping for the task + that has just been switched in. + + Load the context of the task. + Need to restore the lower context by loading the CSA from + pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack). + In the Interrupt handler post-amble, RSLCX will restore the lower context + of the task. RFE will restore the upper context of the task, jump to the + return address and restore the previous state of interrupts being + enabled/disabled. */ + _disable(); + _dsync(); + xUpperCSA = __MFCR( $PCXI ); + pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA ); + *pxCurrentTCB = pxUpperCSA[ 0 ]; + vTaskSwitchContext(); + pxUpperCSA[ 0 ] = *pxCurrentTCB; + CPU_SRC0.bits.SETR = 0; + _isync(); + } +} +/*-----------------------------------------------------------*/ + +/* + * When a task is deleted, it is yielded permanently until the IDLE task + * has an opportunity to reclaim the memory that that task was using. + * Typically, the memory used by a task is the TCB and Stack but in the + * TriCore this includes the CSAs that were consumed as part of the Call + * Stack. These CSAs can only be returned to the Globally Free Pool when + * they are not part of the current Call Stack, hence, delaying the + * reclamation until the IDLE task is freeing the task's other resources. + * This function uses the head of the linked list of CSAs (from when the + * task yielded for the last time) and finds the tail (the very bottom of + * the call stack) and inserts this list at the head of the Free list, + * attaching the existing Free List to the tail of the reclaimed call stack. + * + * NOTE: the IDLE task needs processing time to complete this function + * and in heavily loaded systems, the Free CSAs may be consumed faster + * than they can be freed assuming that tasks are being spawned and + * deleted frequently. + */ +void vPortReclaimCSA( uint32_t *pxTCB ) +{ +uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA; +uint32_t *pulNextCSA; + + /* A pointer to the first CSA in the list of CSAs consumed by the task is + stored in the first element of the tasks TCB structure (where the stack + pointer would be on a traditional stack based architecture). */ + pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK; + + /* Mask off everything in the CSA link field other than the address. If + the address is NULL, then the CSA is not linking anywhere and there is + nothing to do. */ + pxTailCSA = pxHeadCSA; + + /* Convert the link value to contain just a raw address and store this + in a local variable. */ + pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA ); + + /* Iterate over the CSAs that were consumed as part of the task. The + first field in the CSA is the pointer to then next CSA. Mask off + everything in the pointer to the next CSA, other than the link address. + If this is NULL, then the CSA currently being pointed to is the last in + the chain. */ + while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) ) + { + /* Clear all bits of the pointer to the next in the chain, other + than the address bits themselves. */ + pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK; + + /* Move the pointer to point to the next CSA in the list. */ + pxTailCSA = pulNextCSA[ 0 ]; + + /* Update the local pointer to the CSA. */ + pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA ); + } + + _disable(); + { + /* Look up the current free CSA head. */ + _dsync(); + pxFreeCSA = __MFCR( $FCX ); + + /* Join the current Free onto the Tail of what is being reclaimed. */ + portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA; + + /* Move the head of the reclaimed into the Free. */ + _dsync(); + _mtcr( $FCX, pxHeadCSA ); + _isync(); + } + _enable(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Nothing to do. Unlikely to want to end. */ +} +/*-----------------------------------------------------------*/ + +static void prvTrapYield( int iTrapIdentification ) +{ +uint32_t *pxUpperCSA = NULL; +uint32_t xUpperCSA = 0UL; +extern volatile uint32_t *pxCurrentTCB; + + switch( iTrapIdentification ) + { + case portSYSCALL_TASK_YIELD: + /* Save the context of a task. + The upper context is automatically saved when entering a trap or interrupt. + Need to save the lower context as well and copy the PCXI CSA ID into + pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the + TCB of a task. + + Call vTaskSwitchContext to select the next task, note that this changes the + value of pxCurrentTCB so that it needs to be reloaded. + + Call vPortSetMPURegisterSetOne to change the MPU mapping for the task + that has just been switched in. + + Load the context of the task. + Need to restore the lower context by loading the CSA from + pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack). + In the Interrupt handler post-amble, RSLCX will restore the lower context + of the task. RFE will restore the upper context of the task, jump to the + return address and restore the previous state of interrupts being + enabled/disabled. */ + _disable(); + _dsync(); + xUpperCSA = __MFCR( $PCXI ); + pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA ); + *pxCurrentTCB = pxUpperCSA[ 0 ]; + vTaskSwitchContext(); + pxUpperCSA[ 0 ] = *pxCurrentTCB; + CPU_SRC0.bits.SETR = 0; + _isync(); + break; + + default: + /* Unimplemented trap called. */ + configASSERT( ( ( volatile void * ) NULL ) ); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvInterruptYield( int iId ) +{ +uint32_t *pxUpperCSA = NULL; +uint32_t xUpperCSA = 0UL; +extern volatile uint32_t *pxCurrentTCB; + + /* Just to remove compiler warnings. */ + ( void ) iId; + + /* Save the context of a task. + The upper context is automatically saved when entering a trap or interrupt. + Need to save the lower context as well and copy the PCXI CSA ID into + pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the + TCB of a task. + + Call vTaskSwitchContext to select the next task, note that this changes the + value of pxCurrentTCB so that it needs to be reloaded. + + Call vPortSetMPURegisterSetOne to change the MPU mapping for the task + that has just been switched in. + + Load the context of the task. + Need to restore the lower context by loading the CSA from + pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack). + In the Interrupt handler post-amble, RSLCX will restore the lower context + of the task. RFE will restore the upper context of the task, jump to the + return address and restore the previous state of interrupts being + enabled/disabled. */ + _disable(); + _dsync(); + xUpperCSA = __MFCR( $PCXI ); + pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA ); + *pxCurrentTCB = pxUpperCSA[ 0 ]; + vTaskSwitchContext(); + pxUpperCSA[ 0 ] = *pxCurrentTCB; + CPU_SRC0.bits.SETR = 0; + _isync(); +} +/*-----------------------------------------------------------*/ + +uint32_t uxPortSetInterruptMaskFromISR( void ) +{ +uint32_t uxReturn = 0UL; + + _disable(); + uxReturn = __MFCR( $ICR ); + _mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) ); + _isync(); + _enable(); + + /* Return just the interrupt mask bits. */ + return ( uxReturn & portCCPN_MASK ); +} +/*-----------------------------------------------------------*/ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/TriCore_1782/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/TriCore_1782/portmacro.h new file mode 100644 index 0000000..83de733 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/TriCore_1782/portmacro.h @@ -0,0 +1,174 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* System Includes. */ +#include +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*---------------------------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() __asm volatile( " nop " ) +#define portCRITICAL_NESTING_IN_TCB 1 +#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL 1 + + +/*---------------------------------------------------------------------------*/ + +typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS; + +/* Define away the instruction from the Restore Context Macro. */ +#define portPRIVILEGE_BIT 0x0UL + +#define portCCPN_MASK ( 0x000000FFUL ) + +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() +/*---------------------------------------------------------------------------*/ + +/* CSA Manipulation. */ +#define portCSA_TO_ADDRESS( pCSA ) ( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) ) +#define portADDRESS_TO_CSA( pAddress ) ( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) ) +/*---------------------------------------------------------------------------*/ + +#define portYIELD() _syscall( 0 ) +/* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */ +#define portSYSCALL_TASK_YIELD 0 +#define portSYSCALL_RAISE_PRIORITY 1 +/*---------------------------------------------------------------------------*/ + +/* Critical section management. */ + +/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ +#define portDISABLE_INTERRUPTS() { \ + uint32_t ulICR; \ + _disable(); \ + ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ + ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ + ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \ + _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ + _isync(); \ + _enable(); \ + } + +/* Clear ICR.CCPN to allow all interrupt priorities. */ +#define portENABLE_INTERRUPTS() { \ + uint32_t ulICR; \ + _disable(); \ + ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ + ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ + _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ + _isync(); \ + _enable(); \ + } + +/* Set ICR.CCPN to uxSavedMaskValue. */ +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) { \ + uint32_t ulICR; \ + _disable(); \ + ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ + ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ + ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \ + _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ + _isync(); \ + _enable(); \ + } + + +/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */ +extern uint32_t uxPortSetInterruptMaskFromISR( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR() + +/* Pend a priority 1 interrupt, which will take care of the context switch. */ +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); } } while( 0 ) + +/*---------------------------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*---------------------------------------------------------------------------*/ + +/* + * Port specific clean up macro required to free the CSAs that were consumed by + * a task that has since been deleted. + */ +void vPortReclaimCSA( uint32_t *pxTCB ); +#define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/TriCore_1782/porttrap.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/TriCore_1782/porttrap.c new file mode 100644 index 0000000..f06cf83 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/GCC/TriCore_1782/porttrap.c @@ -0,0 +1,282 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" + +/* Machine includes */ +#include +#include +#include +/*---------------------------------------------------------------------------*/ + +/* + * This reference is required by the Save/Restore Context Macros. + */ +extern volatile uint32_t *pxCurrentTCB; +/*-----------------------------------------------------------*/ + +/* + * This file contains base definitions for all of the possible traps in the system. + * It is suggested to provide implementations for all of the traps but for + * the time being they simply trigger a DEBUG instruction so that it is easy + * to see what caused a particular trap. + * + * Trap Class 6, the SYSCALL, is used exclusively by the operating system. + */ + +/* The Trap Classes. */ +#define portMMU_TRAP 0 +#define portIPT_TRAP 1 +#define portIE_TRAP 2 +#define portCM_TRAP 3 +#define portSBP_TRAP 4 +#define portASSERT_TRAP 5 +#define portNMI_TRAP 7 + +/* MMU Trap Identifications. */ +#define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0 +#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1 + +/* Internal Protection Trap Identifications. */ +#define portTIN_IPT_PRIVILIGED_INSTRUCTION 1 +#define portTIN_IPT_MEMORY_PROTECTION_READ 2 +#define portTIN_IPT_MEMORY_PROTECTION_WRITE 3 +#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4 +#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5 +#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6 +#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7 + +/* Instruction Error Trap Identifications. */ +#define portTIN_IE_ILLEGAL_OPCODE 1 +#define portTIN_IE_UNIMPLEMENTED_OPCODE 2 +#define portTIN_IE_INVALID_OPERAND 3 +#define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4 +#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5 + +/* Context Management Trap Identifications. */ +#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1 +#define portTIN_CM_CALL_DEPTH_OVERFLOW 2 +#define portTIN_CM_CALL_DEPTH_UNDEFLOW 3 +#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4 +#define portTIN_CM_CALL_STACK_UNDERFLOW 5 +#define portTIN_CM_CONTEXT_TYPE 6 +#define portTIN_CM_NESTING_ERROR 7 + +/* System Bus and Peripherals Trap Identifications. */ +#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1 +#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2 +#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3 +#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4 +#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5 +#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6 + +/* Assertion Trap Identifications. */ +#define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1 +#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2 + +/* Non-maskable Interrupt Trap Identifications. */ +#define portTIN_NMI_NON_MASKABLE_INTERRUPT 0 +/*---------------------------------------------------------------------------*/ + +void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +/*---------------------------------------------------------------------------*/ + +void vTrapInstallHandlers( void ) +{ + if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) ) + { + _debug(); + } + + if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) ) + { + _debug(); + } + + if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) ) + { + _debug(); + } + + if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) ) + { + _debug(); + } + + if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) ) + { + _debug(); + } + + if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) ) + { + _debug(); + } + + if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) ) + { + _debug(); + } +} +/*-----------------------------------------------------------*/ + +void vMMUTrap( int iTrapIdentification ) +{ + switch( iTrapIdentification ) + { + case portTIN_MMU_VIRTUAL_ADDRESS_FILL: + case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION: + default: + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ + +void vInternalProtectionTrap( int iTrapIdentification ) +{ + /* Deliberate fall through to default. */ + switch( iTrapIdentification ) + { + case portTIN_IPT_PRIVILIGED_INSTRUCTION: + /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */ + + case portTIN_IPT_MEMORY_PROTECTION_READ: + /* Load word using invalid address. */ + + case portTIN_IPT_MEMORY_PROTECTION_WRITE: + /* Store Word using invalid address. */ + + case portTIN_IPT_MEMORY_PROTECTION_EXECUTION: + /* PC jumped to an address outside of the valid range. */ + + case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS: + /* Access to a peripheral denied at current execution level. */ + + case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS: + /* NULL Pointer. */ + + case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION: + /* Tried to modify a global address pointer register. */ + + default: + + pxCurrentTCB[ 0 ] = __MFCR( $PCXI ); + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ + +void vInstructionErrorTrap( int iTrapIdentification ) +{ + /* Deliberate fall through to default. */ + switch( iTrapIdentification ) + { + case portTIN_IE_ILLEGAL_OPCODE: + case portTIN_IE_UNIMPLEMENTED_OPCODE: + case portTIN_IE_INVALID_OPERAND: + case portTIN_IE_DATA_ADDRESS_ALIGNMENT: + case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS: + default: + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ + +void vContextManagementTrap( int iTrapIdentification ) +{ + /* Deliberate fall through to default. */ + switch( iTrapIdentification ) + { + case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION: + case portTIN_CM_CALL_DEPTH_OVERFLOW: + case portTIN_CM_CALL_DEPTH_UNDEFLOW: + case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW: + case portTIN_CM_CALL_STACK_UNDERFLOW: + case portTIN_CM_CONTEXT_TYPE: + case portTIN_CM_NESTING_ERROR: + default: + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ + +void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) +{ + /* Deliberate fall through to default. */ + switch( iTrapIdentification ) + { + case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR: + case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR: + case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR: + case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR: + case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR: + case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR: + default: + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ + +void vAssertionTrap( int iTrapIdentification ) +{ + /* Deliberate fall through to default. */ + switch( iTrapIdentification ) + { + case portTIN_ASSERT_ARITHMETIC_OVERFLOW: + case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW: + default: + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ + +void vNonMaskableInterruptTrap( int iTrapIdentification ) +{ + /* Deliberate fall through to default. */ + switch( iTrapIdentification ) + { + case portTIN_NMI_NON_MASKABLE_INTERRUPT: + default: + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/78K0R/ISR_Support.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/78K0R/ISR_Support.h new file mode 100644 index 0000000..b441a2c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/78K0R/ISR_Support.h @@ -0,0 +1,83 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +#include "FreeRTOSConfig.h" + +; Variables used by scheduler +;------------------------------------------------------------------------------ + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +;------------------------------------------------------------------------------ +; portSAVE_CONTEXT MACRO +; Saves the context of the general purpose registers, CS and ES (only in far +; memory mode) registers the usCriticalNesting Value and the Stack Pointer +; of the active Task onto the task stack +;------------------------------------------------------------------------------ +portSAVE_CONTEXT MACRO + + PUSH AX ; Save AX Register to stack. + PUSH HL + MOV A, CS ; Save CS register. + XCH A, X + MOV A, ES ; Save ES register. + PUSH AX + PUSH DE ; Save the remaining general purpose registers. + PUSH BC + MOVW AX, usCriticalNesting ; Save the usCriticalNesting value. + PUSH AX + MOVW AX, pxCurrentTCB ; Save the Stack pointer. + MOVW HL, AX + MOVW AX, SP + MOVW [HL], AX + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; portRESTORE_CONTEXT MACRO +; Restores the task Stack Pointer then use this to restore usCriticalNesting, +; general purpose registers and the CS and ES (only in far memory mode) +; of the selected task from the task stack +;------------------------------------------------------------------------------ +portRESTORE_CONTEXT MACRO + MOVW AX, pxCurrentTCB ; Restore the Stack pointer. + MOVW HL, AX + MOVW AX, [HL] + MOVW SP, AX + POP AX ; Restore usCriticalNesting value. + MOVW usCriticalNesting, AX + POP BC ; Restore the necessary general purpose registers. + POP DE + POP AX ; Restore the ES register. + MOV ES, A + XCH A, X ; Restore the CS register. + MOV CS, A + POP HL ; Restore general purpose register HL. + POP AX ; Restore AX. + ENDM +;------------------------------------------------------------------------------ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/78K0R/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/78K0R/port.c new file mode 100644 index 0000000..1ba8840 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/78K0R/port.c @@ -0,0 +1,226 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* The critical nesting value is initialised to a non zero value to ensure +interrupts don't accidentally become enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING (( uint16_t ) 10) + +/* Initial PSW value allocated to a newly created task. + * 1100011000000000 + * ||||||||-------------- Fill byte + * |||||||--------------- Carry Flag cleared + * |||||----------------- In-service priority Flags set to low level + * ||||------------------ Register bank Select 0 Flag cleared + * |||------------------- Auxiliary Carry Flag cleared + * ||-------------------- Register bank Select 1 Flag cleared + * |--------------------- Zero Flag set + * ---------------------- Global Interrupt Flag set (enabled) + */ +#define portPSW (0xc6UL) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Most ports implement critical sections by placing the interrupt flags on +the stack before disabling interrupts. Exiting the critical section is then +simply a case of popping the flags from the stack. As 78K0 IAR does not use +a frame pointer this cannot be done as modifying the stack will clobber all +the stack variables. Instead each task maintains a count of the critical +section nesting depth. Each time a critical section is entered the count is +incremented. Each time a critical section is left the count is decremented - +with interrupts only being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint32_t *pulLocal; + + #if configMEMORY_MODE == 1 + { + /* Parameters are passed in on the stack, and written using a 32bit value + hence a space is left for the second two bytes. */ + pxTopOfStack--; + + /* Write in the parameter value. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( uint32_t ) pvParameters; + pxTopOfStack--; + + /* These values are just spacers. The return address of the function + would normally be written here. */ + *pxTopOfStack = ( StackType_t ) 0xcdcd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xcdcd; + pxTopOfStack--; + + /* The start address / PSW value is also written in as a 32bit value, + so leave a space for the second two bytes. */ + pxTopOfStack--; + + /* Task function start address combined with the PSW. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + + /* An initial value for the AX register. */ + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + } + #else + { + /* Task function address is written to the stack first. As it is + written as a 32bit value a space is left on the stack for the second + two bytes. */ + pxTopOfStack--; + + /* Task function start address combined with the PSW. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + + /* The parameter is passed in AX. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + } + #endif + + /* An initial value for the HL register. */ + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + + /* CS and ES registers. */ + *pxTopOfStack = ( StackType_t ) 0x0F00; + pxTopOfStack--; + + /* Finally the remaining general purpose registers DE and BC */ + *pxTopOfStack = ( StackType_t ) 0xDEDE; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBCBC; + pxTopOfStack--; + + /* Finally the critical section nesting count is set to zero when the task + first starts. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + vPortStart(); + + /* Should not get here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the 78K0R port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Setup channel 5 of the TAU to generate the tick interrupt. */ + + /* First the Timer Array Unit has to be enabled. */ + TAU0EN = 1; + + /* To configure the Timer Array Unit all Channels have to first be stopped. */ + TT0 = 0xff; + + /* Interrupt of Timer Array Unit Channel 5 is disabled to set the interrupt + priority. */ + TMMK05 = 1; + + /* Clear Timer Array Unit Channel 5 interrupt flag. */ + TMIF05 = 0; + + /* Set Timer Array Unit Channel 5 interrupt priority */ + TMPR005 = 0; + TMPR105 = 0; + + /* Set Timer Array Unit Channel 5 Mode as interval timer. */ + TMR05 = 0x0000; + + /* Set the compare match value according to the tick rate we want. */ + TDR05 = ( TickType_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + + /* Set Timer Array Unit Channel 5 output mode */ + TOM0 &= ~0x0020; + + /* Set Timer Array Unit Channel 5 output level */ + TOL0 &= ~0x0020; + + /* Set Timer Array Unit Channel 5 output enable */ + TOE0 &= ~0x0020; + + /* Interrupt of Timer Array Unit Channel 5 enabled */ + TMMK05 = 0; + + /* Start Timer Array Unit Channel 5.*/ + TS0 |= 0x0020; +} +/*-----------------------------------------------------------*/ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/78K0R/portasm.s26 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/78K0R/portasm.s26 new file mode 100644 index 0000000..45e3033 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/78K0R/portasm.s26 @@ -0,0 +1,139 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +#include "ISR_Support.h" +;------------------------------------------------------------------------------ + +#if __CORE__ != __78K0R__ + #error "This file is only for 78K0R Devices" +#endif + +#define CS 0xFFFFC +#define ES 0xFFFFD + +; Functions implemented in this file +;------------------------------------------------------------------------------ + PUBLIC vPortYield + PUBLIC vPortStart + +; Functions used by scheduler +;------------------------------------------------------------------------------ + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + +; Tick ISR Prototype +;------------------------------------------------------------------------------ +; EXTERN ?CL78K0R_V2_L00 + + PUBWEAK `??MD_INTTM05??INTVEC 68` + PUBLIC MD_INTTM05 + +MD_INTTM05 SYMBOL "MD_INTTM05" +`??MD_INTTM05??INTVEC 68` SYMBOL "??INTVEC 68", MD_INTTM05 + + + +;------------------------------------------------------------------------------ +; Yield to another task. Implemented as a software interrupt. The return +; address and PSW will have been saved to the stack automatically before +; this code runs. +; +; Input: NONE +; +; Call: CALL vPortYield +; +; Output: NONE +; +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler to select the next task. + portRESTORE_CONTEXT ; Restore the context of the next task to run. + retb + + +;------------------------------------------------------------------------------ +; Restore the context of the first task that is going to run. +; +; Input: NONE +; +; Call: CALL vPortStart +; +; Output: NONE +; +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortStart: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + reti ; An interrupt stack frame is used so the task + ; is started using a RETI instruction. + +;------------------------------------------------------------------------------ +; Perform the necessary steps of the Tick Count Increment and Task Switch +; depending on the chosen kernel configuration +; +; Input: NONE +; +; Call: ISR +; +; Output: NONE +; +;------------------------------------------------------------------------------ + +MD_INTTM05: + + portSAVE_CONTEXT ; Save the context of the current task. + call xTaskIncrementTick ; Call the timer tick function. +#if configUSE_PREEMPTION == 1 + call vTaskSwitchContext ; Call the scheduler to select the next task. +#endif + portRESTORE_CONTEXT ; Restore the context of the next task to run. + reti + + + +; REQUIRE ?CL78K0R_V2_L00 + COMMON INTVEC:CODE:ROOT(1) ; Set ISR location to the Interrupt vector table. + ORG 68 +`??MD_INTTM05??INTVEC 68`: + DW MD_INTTM05 + + COMMON INTVEC:CODE:ROOT(1) ; Set ISR location to the Interrupt vector table. + ORG 126 +`??vPortYield??INTVEC 126`: + DW vPortYield + + ; Set value for the usCriticalNesting. + RSEG NEAR_ID:CONST:SORT:NOROOT(1) +`?`: + DW 10 + +;#endif + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/78K0R/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/78K0R/portmacro.h new file mode 100644 index 0000000..bf2684f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/78K0R/portmacro.h @@ -0,0 +1,146 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if (configUSE_16_BIT_TICKS==1) + typedef unsigned int TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() __asm ( "DI" ) +#define portENABLE_INTERRUPTS() __asm ( "EI" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortStart( void ); +#define portYIELD() __asm( "BRK" ) +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 ) +#define portNOP() __asm( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Hardwware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + + +static __interrupt void P0_isr (void); + +/* --------------------------------------------------------------------------*/ +/* Option-bytes and security ID */ +/* --------------------------------------------------------------------------*/ +#define OPT_BYTES_SIZE 4 +#define SECU_ID_SIZE 10 +#define WATCHDOG_DISABLED 0x00 +#define LVI_ENABLED 0xFE +#define LVI_DISABLED 0xFF +#define RESERVED_FF 0xFF +#define OCD_DISABLED 0x04 +#define OCD_ENABLED 0x81 +#define OCD_ENABLED_ERASE 0x80 + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA5_No_GIC/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA5_No_GIC/port.c new file mode 100644 index 0000000..3f9de4d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA5_No_GIC/port.c @@ -0,0 +1,301 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* IAR includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt. A default that uses the PIT is provided in the official demo application. +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt. A default that uses the PIT is provided in the official demo application. +#endif + +/* A critical section is exited when the critical section nesting count reaches +this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Tasks are not created with a floating point context, but can be given a +floating point context after they have been created. A variable is stored as +part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task +does not have an FPU context, or any other value if the task does have an FPU +context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user +mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This +variable has to be stored as part of the task context and must be initialised to +a non zero value to ensure interrupts don't inadvertently become unmasked before +the scheduler starts. As it is stored as part of the task context it will +automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero +then a floating point context must be saved and restored for the task. */ +uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if +if the nesting depth is 0. */ +uint32_t ulPortInterruptNesting = 0UL; + + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. + + The fist real value on the stack is the status register, which is set for + system mode, with interrupts enabled. A few NULLs are added first to ensure + GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + the floating point hardware must call vPortTaskUsesFPU() before executing + any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +uint32_t ulAPSR; + + /* Only continue if the CPU is not in User mode. The CPU must be in a + Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + vPortRestoreTaskContext(); + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + a non-privileged mode or the binary point register was not set to its lowest + possible value. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + should be unmasked. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + portDISABLE_INTERRUPTS(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + portENABLE_INTERRUPTS(); + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ +uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); +} +/*-----------------------------------------------------------*/ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA5_No_GIC/portASM.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA5_No_GIC/portASM.h new file mode 100644 index 0000000..16a2cb2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA5_No_GIC/portASM.h @@ -0,0 +1,114 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + EXTERN vTaskSwitchContext + EXTERN ulCriticalNesting + EXTERN pxCurrentTCB + EXTERN ulPortTaskHasFPUContext + EXTERN ulAsmAPIPriorityMask + +portSAVE_CONTEXT macro + + ; Save the LR and SPSR onto the system mode stack before switching to + ; system mode to save the remaining system mode registers + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + ; Push the critical nesting count + LDR R2, =ulCriticalNesting + LDR R1, [R2] + PUSH {R1} + + ; Does the task have a floating point context that needs saving? If + ; ulPortTaskHasFPUContext is 0 then no. + LDR R2, =ulPortTaskHasFPUContext + LDR R3, [R2] + CMP R3, #0 + + ; Save the floating point context, if any + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} +#if configFPU_D32 == 1 + VPUSHNE {D16-D31} +#endif ; configFPU_D32 + PUSHNE {R1} + + ; Save ulPortTaskHasFPUContext itself + PUSH {R3} + + ; Save the stack pointer in the TCB + LDR R0, =pxCurrentTCB + LDR R1, [R0] + STR SP, [R1] + + endm + +; /**********************************************************************/ + +portRESTORE_CONTEXT macro + + ; Set the SP to point to the stack of the task being restored. + LDR R0, =pxCurrentTCB + LDR R1, [R0] + LDR SP, [R1] + + ; Is there a floating point context to restore? If the restored + ; ulPortTaskHasFPUContext is zero then no. + LDR R0, =ulPortTaskHasFPUContext + POP {R1} + STR R1, [R0] + CMP R1, #0 + + ; Restore the floating point context, if any + POPNE {R0} +#if configFPU_D32 == 1 + VPOPNE {D16-D31} +#endif ; configFPU_D32 + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + ; Restore the critical section nesting depth + LDR R0, =ulCriticalNesting + POP {R1} + STR R1, [R0] + + ; Restore all system mode registers other than the SP (which is already + ; being used) + POP {R0-R12, R14} + + ; Return to the task code, loading CPSR on the way. CPSR has the interrupt + ; enable bit set appropriately for the task about to execute. + RFEIA sp! + + endm + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA5_No_GIC/portASM.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA5_No_GIC/portASM.s new file mode 100644 index 0000000..90835d0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA5_No_GIC/portASM.s @@ -0,0 +1,177 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + INCLUDE FreeRTOSConfig.h + INCLUDE portmacro.h + + EXTERN vTaskSwitchContext + EXTERN ulPortYieldRequired + EXTERN ulPortInterruptNesting + EXTERN vApplicationIRQHandler + + PUBLIC FreeRTOS_SWI_Handler + PUBLIC FreeRTOS_IRQ_Handler + PUBLIC vPortRestoreTaskContext + +SYS_MODE EQU 0x1f +SVC_MODE EQU 0x13 +IRQ_MODE EQU 0x12 + + SECTION .text:CODE:ROOT(2) + ARM + + INCLUDE portASM.h + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC handler is used to yield a task. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_SWI_Handler + + PRESERVE8 + + ; Save the context of the current task and select a new task to run. + portSAVE_CONTEXT + LDR R0, =vTaskSwitchContext + BLX R0 + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; vPortRestoreTaskContext is used to start the scheduler. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortRestoreTaskContext + + PRESERVE8 + + ; Switch to system mode + CPS #SYS_MODE + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; IRQ interrupt handler used when individual priorities cannot be masked +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_IRQ_Handler + + PRESERVE8 + + ; Return to the interrupted instruction. + SUB lr, lr, #4 + + ; Push the return address and SPSR + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + ; Change to supervisor mode to allow reentry. + CPS #SVC_MODE + + ; Push used registers. + PUSH {r0-r4, r12} + + ; Increment nesting count. r3 holds the address of ulPortInterruptNesting + ; for future use. r1 holds the original ulPortInterruptNesting value for + ; future use. + LDR r3, =ulPortInterruptNesting + LDR r1, [r3] + ADD r4, r1, #1 + STR r4, [r3] + + ; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + ; future use. + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + PUSH {r0-r4, lr} + + ; Call the port part specific handler. + LDR r0, =vApplicationIRQHandler + BLX r0 + POP {r0-r4, lr} + ADD sp, sp, r2 + + CPSID i + + ; Write to the EOI register. + LDR r4, =configEOI_ADDRESS + STR r0, [r4] + + ; Restore the old nesting count + STR r1, [r3] + + ; A context switch is never performed if the nesting count is not 0. + CMP r1, #0 + BNE exit_without_switch + + ; Did the interrupt request a context switch? r1 holds the address of + ; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + ; use. + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch + ; No context switch. Restore used registers, LR_irq and SPSR before + ; returning. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit + ; A context switch is to be performed. Clear the context switch pending + ; flag. + MOV r0, #0 + STR r0, [r1] + + ; Restore used registers, LR-irq and SPSR before saving the context + ; to the task stack. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + ; Call the function that selects the new task to execute. + ; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + ; instructions, or 8 byte aligned stack allocated data. LR does not need + ; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. + LDR r0, =vTaskSwitchContext + BLX r0 + + ; Restore the context of, and branch to, the task selected to execute next. + portRESTORE_CONTEXT + + END + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA5_No_GIC/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA5_No_GIC/portmacro.h new file mode 100644 index 0000000..ca2366a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA5_No_GIC/portmacro.h @@ -0,0 +1,163 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* IAR includes. */ +#ifdef __ICCARM__ + + #include + + #ifdef __cplusplus + extern "C" { + #endif + + /*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + + /* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + + /*-----------------------------------------------------------*/ + + /* Hardware specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + + /*-----------------------------------------------------------*/ + + /* Task utilities. */ + + /* Called at the end of an ISR that can cause a context switch. */ + #define portEND_SWITCHING_ISR( xSwitchRequired )\ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } + + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + #define portYIELD() __asm volatile ( "SWI 0" ); __ISB() + + + /*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + extern uint32_t ulPortSetInterruptMask( void ); + extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); + + #define portENTER_CRITICAL() vPortEnterCritical(); + #define portEXIT_CRITICAL() vPortExitCritical(); + #define portDISABLE_INTERRUPTS() __disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */ + #define portENABLE_INTERRUPTS() __enable_irq() + #define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */ + #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) __set_interrupt_state(x) + + /*-----------------------------------------------------------*/ + + /* Task function macros as described on the FreeRTOS.org WEB site. These are + not required for this port but included in case common demo code that uses these + macros is used. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + + /* Prototype of the FreeRTOS tick handler. This must be installed as the + handler for whichever peripheral is used to generate the RTOS tick. */ + void FreeRTOS_Tick_Handler( void ); + + /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + before any floating point instructions are executed. */ + void vPortTaskUsesFPU( void ); + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + + /* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + #define portNOP() __asm volatile( "NOP" ) + + + #ifdef __cplusplus + } /* extern C */ + #endif + + /* Suppress warnings that are generated by the IAR tools, but cannot be + fixed in the source code because to do so would cause other compilers to + generate warnings. */ + #pragma diag_suppress=Pe191 + #pragma diag_suppress=Pa082 + +#endif /* __ICCARM__ */ + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA9/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA9/port.c new file mode 100644 index 0000000..b5fe3f2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA9/port.c @@ -0,0 +1,440 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* IAR includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS + #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET + #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #define configCLEAR_TICK_INTERRUPT() +#endif + +/* A critical section is exited when the critical section nesting count reaches +this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* In all GICs 255 can be written to the priority mask register to unmask all +(but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) + +/* Tasks are not created with a floating point context, but can be given a +floating point context after they have been created. A variable is stored as +part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task +does not have an FPU context, or any other value if the task does have an FPU +context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary +point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user +mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* Macro to unmask all interrupt priorities. */ +#define portCLEAR_INTERRUPT_MASK() \ +{ \ + __disable_irq(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm( "DSB \n" \ + "ISB \n" ); \ + __enable_irq(); \ +} + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This +variable has to be stored as part of the task context and must be initialised to +a non zero value to ensure interrupts don't inadvertently become unmasked before +the scheduler starts. As it is stored as part of the task context it will +automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero +then a floating point context must be saved and restored for the task. */ +uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if +if the nesting depth is 0. */ +uint32_t ulPortInterruptNesting = 0UL; + + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. + + The fist real value on the stack is the status register, which is set for + system mode, with interrupts enabled. A few NULLs are added first to ensure + GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + the floating point hardware must call vPortTaskUsesFPU() before executing + any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +uint32_t ulAPSR; + + /* Only continue if the CPU is not in User mode. The CPU must be in a + Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Only continue if the binary point value is set to its lowest possible + setting. See the comments in vPortValidateInterruptPriority() below for + more information. */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + + if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) + { + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + __enable_irq(); + vPortRestoreTaskContext(); + } + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + a non-privileged mode or the binary point register was not set to its lowest + possible value. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + ulPortSetInterruptMask(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + should be unmasked. */ + portCLEAR_INTERRUPT_MASK(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* Set interrupt mask before altering scheduler structures. The tick + handler runs at the lowest priority, so interrupts cannot already be masked, + so there is no need to save and restore the current mask value. */ + __disable_irq(); + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm( "DSB \n" + "ISB \n" ); + __enable_irq(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK(); + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ +uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( uint32_t ulNewMaskValue ) +{ + if( ulNewMaskValue == pdFALSE ) + { + portCLEAR_INTERRUPT_MASK(); + } +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortSetInterruptMask( void ) +{ +uint32_t ulReturn; + + __disable_irq(); + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + /* Interrupts were already masked. */ + ulReturn = pdTRUE; + } + else + { + ulReturn = pdFALSE; + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm( "DSB \n" + "ISB \n" ); + } + __enable_irq(); + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +#if( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* The following assertion will fail if a service routine (ISR) for + an interrupt that has been assigned a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + function. ISR safe FreeRTOS API functions must *only* be called + from interrupts that have been assigned a priority at or below + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Numerically low interrupt priority numbers represent logically high + interrupt priorities, therefore the priority of the interrupt must + be set to a value equal to or numerically *higher* than + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + FreeRTOS maintains separate thread and ISR API functions to ensure + interrupt entry is as fast and simple as possible. + + The following links provide detailed information: + https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + + /* Priority grouping: The interrupt controller (GIC) allows the bits + that define each interrupt's priority to be split between bits that + define the interrupt's pre-emption priority bits and bits that define + the interrupt's sub-priority. For simplicity all bits must be defined + to be pre-emption priority bits. The following assertion will fail if + this is not the case (if some bits represent a sub-priority). + + The priority grouping is configured by the GIC's binary point register + (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest + possible value (which may be above 0). */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + } + +#endif /* configASSERT_DEFINED */ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA9/portASM.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA9/portASM.h new file mode 100644 index 0000000..1733aef --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA9/portASM.h @@ -0,0 +1,116 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + EXTERN vTaskSwitchContext + EXTERN ulCriticalNesting + EXTERN pxCurrentTCB + EXTERN ulPortTaskHasFPUContext + EXTERN ulAsmAPIPriorityMask + +portSAVE_CONTEXT macro + + ; Save the LR and SPSR onto the system mode stack before switching to + ; system mode to save the remaining system mode registers + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + ; Push the critical nesting count + LDR R2, =ulCriticalNesting + LDR R1, [R2] + PUSH {R1} + + ; Does the task have a floating point context that needs saving? If + ; ulPortTaskHasFPUContext is 0 then no. + LDR R2, =ulPortTaskHasFPUContext + LDR R3, [R2] + CMP R3, #0 + + ; Save the floating point context, if any + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} + VPUSHNE {D16-D31} + PUSHNE {R1} + + ; Save ulPortTaskHasFPUContext itself + PUSH {R3} + + ; Save the stack pointer in the TCB + LDR R0, =pxCurrentTCB + LDR R1, [R0] + STR SP, [R1] + + endm + +; /**********************************************************************/ + +portRESTORE_CONTEXT macro + + ; Set the SP to point to the stack of the task being restored. + LDR R0, =pxCurrentTCB + LDR R1, [R0] + LDR SP, [R1] + + ; Is there a floating point context to restore? If the restored + ; ulPortTaskHasFPUContext is zero then no. + LDR R0, =ulPortTaskHasFPUContext + POP {R1} + STR R1, [R0] + CMP R1, #0 + + ; Restore the floating point context, if any + POPNE {R0} + VPOPNE {D16-D31} + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + ; Restore the critical section nesting depth + LDR R0, =ulCriticalNesting + POP {R1} + STR R1, [R0] + + ; Ensure the priority mask is correct for the critical nesting depth + LDR R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS + CMP R1, #0 + MOVEQ R4, #255 + LDRNE R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) + STR R4, [r2] + + ; Restore all system mode registers other than the SP (which is already + ; being used) + POP {R0-R12, R14} + + ; Return to the task code, loading CPSR on the way. + RFEIA sp! + + endm + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA9/portASM.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA9/portASM.s new file mode 100644 index 0000000..9e92204 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA9/portASM.s @@ -0,0 +1,178 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + INCLUDE FreeRTOSConfig.h + INCLUDE portmacro.h + + EXTERN vApplicationIRQHandler + EXTERN vTaskSwitchContext + EXTERN ulPortYieldRequired + EXTERN ulPortInterruptNesting + + PUBLIC FreeRTOS_SWI_Handler + PUBLIC FreeRTOS_IRQ_Handler + PUBLIC vPortRestoreTaskContext + +SYS_MODE EQU 0x1f +SVC_MODE EQU 0x13 +IRQ_MODE EQU 0x12 + + + SECTION .text:CODE:ROOT(2) + ARM + + INCLUDE portASM.h + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC handler is used to yield a task. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_SWI_Handler + + PRESERVE8 + + ; Save the context of the current task and select a new task to run. + portSAVE_CONTEXT + LDR R0, =vTaskSwitchContext + BLX R0 + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; vPortRestoreTaskContext is used to start the scheduler. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortRestoreTaskContext + ; Switch to system mode + CPS #SYS_MODE + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; PL390 GIC interrupt handler +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_IRQ_Handler + + ; Return to the interrupted instruction. + SUB lr, lr, #4 + + ; Push the return address and SPSR + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + ; Change to supervisor mode to allow reentry. + CPS #SVC_MODE + + ; Push used registers. + PUSH {r0-r4, r12} + + ; Increment nesting count. r3 holds the address of ulPortInterruptNesting + ; for future use. r1 holds the original ulPortInterruptNesting value for + ; future use. + LDR r3, =ulPortInterruptNesting + LDR r1, [r3] + ADD r4, r1, #1 + STR r4, [r3] + + ; Read value from the interrupt acknowledge register, which is stored in r0 + ; for future parameter and interrupt clearing use. + LDR r2, =portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS + LDR r0, [r2] + + ; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + ; future use. _RB_ Is this ever necessary if start of stack is 8-byte aligned? + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + ; Call the interrupt handler. r4 is pushed to maintain alignment. + PUSH {r0-r4, lr} + LDR r1, =vApplicationIRQHandler + BLX r1 + POP {r0-r4, lr} + ADD sp, sp, r2 + + CPSID i + + ; Write the value read from ICCIAR to ICCEOIR + LDR r4, =portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS + STR r0, [r4] + + ; Restore the old nesting count + STR r1, [r3] + + ; A context switch is never performed if the nesting count is not 0 + CMP r1, #0 + BNE exit_without_switch + + ; Did the interrupt request a context switch? r1 holds the address of + ; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + ; use. + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch + ; No context switch. Restore used registers, LR_irq and SPSR before + ; returning. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit + ; A context switch is to be performed. Clear the context switch pending + ; flag. + MOV r0, #0 + STR r0, [r1] + + ; Restore used registers, LR-irq and SPSR before saving the context + ; to the task stack. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + ; Call the function that selects the new task to execute. + ; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + ; instructions, or 8 byte aligned stack allocated data. LR does not need + ; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. + LDR r0, =vTaskSwitchContext + BLX r0 + + ; Restore the context of, and branch to, the task selected to execute next. + portRESTORE_CONTEXT + + + END + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA9/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA9/portmacro.h new file mode 100644 index 0000000..43541ea --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CA9/portmacro.h @@ -0,0 +1,217 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* IAR includes. */ +#ifdef __ICCARM__ + + #include + + #ifdef __cplusplus + extern "C" { + #endif + + /*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + + /* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + + /*-----------------------------------------------------------*/ + + /* Hardware specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + + /*-----------------------------------------------------------*/ + + /* Task utilities. */ + + /* Called at the end of an ISR that can cause a context switch. */ + #define portEND_SWITCHING_ISR( xSwitchRequired )\ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } + + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + #define portYIELD() __asm( "SWI 0" ); + + + /*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + extern uint32_t ulPortSetInterruptMask( void ); + extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); + + /* These macros do not globally disable/enable interrupts. They do mask off + interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ + #define portENTER_CRITICAL() vPortEnterCritical(); + #define portEXIT_CRITICAL() vPortExitCritical(); + #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() + #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif + + /*-----------------------------------------------------------*/ + + /* Task function macros as described on the FreeRTOS.org WEB site. These are + not required for this port but included in case common demo code that uses these + macros is used. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + + /* Prototype of the FreeRTOS tick handler. This must be installed as the + handler for whichever peripheral is used to generate the RTOS tick. */ + void FreeRTOS_Tick_Handler( void ); + + /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + before any floating point instructions are executed. */ + void vPortTaskUsesFPU( void ); + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + + #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) + #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + + /* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif /* configASSERT */ + + #define portNOP() __asm volatile( "NOP" ) + + + #ifdef __cplusplus + } /* extern C */ + #endif + + /* Suppress warnings that are generated by the IAR tools, but cannot be + fixed in the source code because to do so would cause other compilers to + generate warnings. */ + #pragma diag_suppress=Pe191 + #pragma diag_suppress=Pa082 + +#endif /* __ICCARM__ */ + + +/* The number of bits to shift for an interrupt priority is dependent on the +number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif + +/* Interrupt controller access addresses. */ +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) + +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM0/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM0/port.c new file mode 100644 index 0000000..d0ecaa3 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM0/port.c @@ -0,0 +1,443 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM0 port. +*----------------------------------------------------------*/ + +/* IAR includes. */ +#include "intrinsics.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is + * defined. The value 255 should also ensure backward compatibility. + * FreeRTOS.org versions prior to V4.3.0 did not include this definition. */ +#ifndef configKERNEL_INTERRUPT_PRIORITY + #define configKERNEL_INTERRUPT_PRIORITY 0 +#endif + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#ifndef portMISSED_COUNTS_FACTOR + #define portMISSED_COUNTS_FACTOR ( 45UL ) +#endif + +/* The number of SysTick increments that make up one tick period. */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11..R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET; + + /* Barriers are normally not required but do ensure the code is completely + * within the specified behaviour for the architecture. */ + __DSB(); + __ISB(); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + __DSB(); + __ISB(); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_interrupt() + * call above. */ + __enable_interrupt(); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __DSB(); + __WFI(); + __ISB(); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __enable_interrupt(); + __DSB(); + __ISB(); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrpts enabled. */ + __enable_interrupt(); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM0/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM0/portasm.s new file mode 100644 index 0000000..3e90c3f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM0/portasm.s @@ -0,0 +1,132 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include + + RSEG CODE:CODE(2) + thumb + + EXTERN vPortYieldFromISR + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + + PUBLIC vSetMSP + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + PUBLIC ulSetInterruptMaskFromISR + PUBLIC vClearInterruptMaskFromISR + +/*-----------------------------------------------------------*/ + +vSetMSP + msr msp, r0 + bx lr + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + + ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [r3] + + subs r0, r0, #32 /* Make space for the remaining low registers. */ + str r0, [r2] /* Save the new top of stack. */ + stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */ + mov r4, r8 /* Store the high registers. */ + mov r5, r9 + mov r6, r10 + mov r7, r11 + stmia r0!, {r4-r7} + + push {r3, r14} + cpsid i + bl vTaskSwitchContext + cpsie i + pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */ + + ldr r1, [r2] + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ + adds r0, r0, #16 /* Move to the high registers. */ + ldmia r0!, {r4-r7} /* Pop the high registers. */ + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + + msr psp, r0 /* Remember the new top of stack for the task. */ + + subs r0, r0, #32 /* Go back for the low registers that are not automatically restored. */ + ldmia r0!, {r4-r7} /* Pop low registers. */ + + bx r3 + +/*-----------------------------------------------------------*/ + +vPortSVCHandler; + /* This function is no longer used, but retained for backward + compatibility. */ + bx lr + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask + /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector + table offset register that can be used to locate the initial stack value. + Not all M0 parts have the application vector table at address 0. */ + + ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */ + ldr r1, [r3] + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + movs r0, #2 /* Switch to the psp stack. */ + msr CONTROL, r0 + isb + pop {r0-r5} /* Pop the registers that are saved automatically. */ + mov lr, r5 /* lr is now in r5. */ + pop {r3} /* The return address is now in r3. */ + pop {r2} /* Pop and discard the XPSR. */ + cpsie i /* The first task has its context and interrupts can be enabled. */ + bx r3 /* Jump to the user defined task code. */ + +/*-----------------------------------------------------------*/ + +ulSetInterruptMaskFromISR + mrs r0, PRIMASK + cpsid i + bx lr + +/*-----------------------------------------------------------*/ + +vClearInterruptMaskFromISR + msr PRIMASK, r0 + bx lr + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM0/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM0/portmacro.h new file mode 100644 index 0000000..dadb3b1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM0/portmacro.h @@ -0,0 +1,137 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + extern void vPortYield( void ); + #define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 ) + #define portNVIC_PENDSVSET 0x10000000 + #define portYIELD() vPortYield() + #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif + +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + extern uint32_t ulSetInterruptMaskFromISR( void ); + extern void vClearInterruptMaskFromISR( uint32_t ulMask ); + + #define portDISABLE_INTERRUPTS() __asm volatile ( "cpsid i" ) + #define portENABLE_INTERRUPTS() __asm volatile ( "cpsie i" ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x ) + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + + #define portNOP() + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ + #pragma diag_suppress=Pa082 + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/portasm.h new file mode 100644 index 0000000..d2152e1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/portasm.s new file mode 100644 index 0000000..35d4795 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/portasm.s @@ -0,0 +1,391 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + beq running_privileged /* If the result of previous AND operation was 0, branch. */ + movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + bx lr /* Return. */ + running_privileged: + movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + orrs r0, r1 /* r0 = r0 | r1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + movs r5, #1 /* r5 = 1. */ + bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + movs r5, #4 /* r5 = 4. */ + str r5, [r2] /* Program RNR = 4. */ + ldmia r3!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write first set of RBAR/RLAR registers. */ + movs r5, #5 /* r5 = 5. */ + str r5, [r2] /* Program RNR = 5. */ + ldmia r3!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write second set of RBAR/RLAR registers. */ + movs r5, #6 /* r5 = 6. */ + str r5, [r2] /* Program RNR = 6. */ + ldmia r3!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write third set of RBAR/RLAR registers. */ + movs r5, #7 /* r5 = 7. */ + str r5, [r2] /* Program RNR = 7. */ + ldmia r3!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + movs r5, #1 /* r5 = 1. */ + orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + ldr r5, =xSecureContext + str r1, [r5] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + msr control, r3 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r4 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r3 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + movs r1, #1 /* r1 = 1. */ + bics r0, r1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, PRIMASK + cpsid i + bx lr +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr PRIMASK, r0 + bx lr +/*-----------------------------------------------------------*/ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + push {r0-r2, r14} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r3} /* LR is now in r3. */ + mov lr, r3 /* LR = r3. */ + lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ +#if ( configENABLE_MPU == 1 ) + subs r2, r2, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ +#else /* configENABLE_MPU */ + subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ +#endif /* configENABLE_MPU */ + b select_next_task + + save_ns_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + #if ( configENABLE_MPU == 1 ) + subs r2, r2, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + adds r2, r2, #16 /* r2 = r2 + 16. */ + stmia r2!, {r4-r7} /* Store the low registers that are not saved automatically. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r2!, {r4-r7} /* Store the high registers that are not saved automatically. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + subs r2, r2, #48 /* r2 = r2 - 48. */ + stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r2!, {r4-r7} /* Store the high registers that are not saved automatically. */ + #endif /* configENABLE_MPU */ + + select_next_task: + cpsid i + bl vTaskSwitchContext + cpsie i + + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + #if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r3] /* Read the value of MPU_CTRL. */ + movs r5, #1 /* r5 = 1. */ + bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */ + str r4, [r3] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */ + ldr r3, =0xe000edc0 /* r3 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r3] /* Program MAIR0. */ + ldr r4, =0xe000ed98 /* r4 = 0xe000ed98 [Location of RNR]. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + movs r5, #4 /* r5 = 4. */ + str r5, [r4] /* Program RNR = 4. */ + ldmia r1!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r6,r7} /* Write first set of RBAR/RLAR registers. */ + movs r5, #5 /* r5 = 5. */ + str r5, [r4] /* Program RNR = 5. */ + ldmia r1!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r6,r7} /* Write second set of RBAR/RLAR registers. */ + movs r5, #6 /* r5 = 6. */ + str r5, [r4] /* Program RNR = 6. */ + ldmia r1!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r6,r7} /* Write third set of RBAR/RLAR registers. */ + movs r5, #7 /* r5 = 7. */ + str r5, [r4] /* Program RNR = 7. */ + ldmia r1!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r3] /* Read the value of MPU_CTRL. */ + movs r5, #1 /* r5 = 1. */ + orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */ + str r4, [r3] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + + #if ( configENABLE_MPU == 1 ) + ldmia r2!, {r0, r1, r3, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r3 /* Restore the CONTROL register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + #else /* configENABLE_MPU */ + ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + #endif /* configENABLE_MPU */ + + restore_ns_context: + adds r2, r2, #16 /* Move to the high registers. */ + ldmia r2!, {r4-r7} /* Restore the high registers that are not automatically restored. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + subs r2, r2, #32 /* Go back to the low registers. */ + ldmia r2!, {r4-r7} /* Restore the low registers that are not automatically restored. */ + bx lr +/*-----------------------------------------------------------*/ + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stacking_used_msp + mrs r0, psp + b vPortSVCHandler_C + stacking_used_msp: + mrs r0, msp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + bne free_secure_context /* Branch if r1 != 0. */ + bx lr /* There is no secure context (xSecureContext is NULL). */ + free_secure_context: + svc 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/portmacro.h new file mode 100644 index 0000000..a8e2c6a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/portmacro.h @@ -0,0 +1,78 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h new file mode 100644 index 0000000..26aa668 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_context.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_context.c new file mode 100644 index 0000000..a63d59e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_context.c @@ -0,0 +1,351 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Ontain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_context.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_context.h new file mode 100644 index 0000000..ba883ed --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_context.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s new file mode 100644 index 0000000..b89a865 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s @@ -0,0 +1,88 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */ + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + stmia r1!, {r2} /* Store CONTROL value on the stack. */ +#else /* configENABLE_MPU */ + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ +#endif /* configENABLE_MPU */ + + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_heap.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_heap.c new file mode 100644 index 0000000..19a7fae --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_heap.c @@ -0,0 +1,451 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart, * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/** + * @brief Gets set to the top bit of an size_t type. + * + * When this bit in the xBlockSize member of an BlockLink_t structure is set + * then the block belongs to the application. When the bit is free the block is + * still part of the free heap space. + */ +static size_t xBlockAllocatedBit = 0; +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink; + void * pvReturn = NULL; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size is increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number of + * bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); + secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_heap.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_heap.h new file mode 100644 index 0000000..0009003 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_init.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_init.c new file mode 100644 index 0000000..a21ea1c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_init.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_init.h new file mode 100644 index 0000000..2a0352c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_port_macros.h new file mode 100644 index 0000000..d8ab67a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h new file mode 100644 index 0000000..d2152e1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s new file mode 100644 index 0000000..e6e1251 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s @@ -0,0 +1,310 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + beq running_privileged /* If the result of previous AND operation was 0, branch. */ + movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + bx lr /* Return. */ + running_privileged: + movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ + +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + orrs r0, r1 /* r0 = r0 | r1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + movs r4, #1 /* r4 = 1. */ + bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */ + str r3, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r2] /* Program RNR = 4. */ + ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */ + movs r4, #5 /* r4 = 5. */ + str r4, [r2] /* Program RNR = 5. */ + ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */ + movs r4, #6 /* r4 = 6. */ + str r4, [r2] /* Program RNR = 6. */ + ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */ + movs r4, #7 /* r4 = 7. */ + str r4, [r2] /* Program RNR = 7. */ + ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + movs r4, #1 /* r4 = 1. */ + orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */ + str r3, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + msr control, r2 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r3 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r2 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + movs r1, #1 /* r1 = 1. */ + bics r0, r1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ + nop +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, PRIMASK + cpsid i + bx lr +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr PRIMASK, r0 + bx lr +/*-----------------------------------------------------------*/ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ +#if ( configENABLE_MPU == 1 ) + subs r0, r0, #44 /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r2, control /* r2 = CONTROL. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r0!, {r1-r7} /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */ +#else /* configENABLE_MPU */ + subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */ +#endif /* configENABLE_MPU */ + + cpsid i + bl vTaskSwitchContext + cpsie i + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + movs r4, #1 /* r4 = 1. */ + bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */ + str r3, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r2] /* Program RNR = 4. */ + ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */ + movs r4, #5 /* r4 = 5. */ + str r4, [r2] /* Program RNR = 5. */ + ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */ + movs r4, #6 /* r4 = 6. */ + str r4, [r2] /* Program RNR = 6. */ + ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */ + movs r4, #7 /* r4 = 7. */ + str r4, [r2] /* Program RNR = 7. */ + ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + movs r4, #1 /* r4 = 1. */ + orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */ + str r3, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + adds r0, r0, #28 /* Move to the high registers. */ + ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + subs r0, r0, #44 /* Move to the starting of the saved context. */ + ldmia r0!, {r1-r7} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r2 /* Restore the CONTROL register value for the task. */ + bx r3 +#else /* configENABLE_MPU */ + adds r0, r0, #24 /* Move to the high registers. */ + ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + subs r0, r0, #40 /* Move to the starting of the saved context. */ + ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + bx r3 +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stacking_used_msp + mrs r0, psp + b vPortSVCHandler_C + stacking_used_msp: + mrs r0, msp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h new file mode 100644 index 0000000..a8e2c6a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h @@ -0,0 +1,78 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 0000000..26aa668 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM3/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM3/port.c new file mode 100644 index 0000000..29b15e2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM3/port.c @@ -0,0 +1,610 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM3 port. +*----------------------------------------------------------*/ + +/* IAR includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is + * defined. The value 255 should also ensure backward compatibility. + * FreeRTOS.org versions prior to V4.3.0 did not include this definition. */ +#ifndef configKERNEL_INTERRUPT_PRIORITY + #define configKERNEL_INTERRUPT_PRIORITY 255 +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_interrupt() + * call above. */ + __enable_interrupt(); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __DSB(); + __WFI(); + __ISB(); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __enable_interrupt(); + __DSB(); + __ISB(); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __enable_interrupt(); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM3/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM3/portasm.s new file mode 100644 index 0000000..03786e0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM3/portasm.s @@ -0,0 +1,104 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include + + RSEG CODE:CODE(2) + thumb + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + + + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + isb + ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [r3] + + stmdb r0!, {r4-r11} /* Save the remaining registers. */ + str r0, [r2] /* Save the new top of stack into the first member of the TCB. */ + + stmdb sp!, {r3, r14} + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r3, r14} + + ldr r1, [r3] + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ + ldmia r0!, {r4-r11} /* Pop the registers. */ + msr psp, r0 + isb + bx r14 + + +/*-----------------------------------------------------------*/ + +vPortSVCHandler: + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r1, [r3] + ldr r0, [r1] + /* Pop the core registers. */ + ldmia r0!, {r4-r11} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + orr r14, r14, #13 + bx r14 + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Call SVC to start the first task, ensuring interrupts are enabled. */ + cpsie i + cpsie f + dsb + isb + svc 0 + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM3/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM3/portmacro.h new file mode 100644 index 0000000..5cef825 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM3/portmacro.h @@ -0,0 +1,208 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* IAR includes. */ + #include + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Compiler directives. */ + #define portWEAK_SYMBOL __attribute__( ( weak ) ) + +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __DSB(); \ + __ISB(); \ + } + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + + #define portDISABLE_INTERRUPTS() \ + { \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + } + + #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + #define portINLINE __inline + + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) + { + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ + #pragma diag_suppress=Pe191 + #pragma diag_suppress=Pa082 + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/portasm.h new file mode 100644 index 0000000..d2152e1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/portasm.s new file mode 100644 index 0000000..deb3626 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/portasm.s @@ -0,0 +1,353 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r2] /* Program RNR = 4. */ + adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + ldr r5, =xSecureContext + str r1, [r5] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + msr control, r3 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r4 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + push {r0-r2, r14} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r3} /* LR is now in r3. */ + mov lr, r3 /* LR = r3. */ + lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ +#if ( configENABLE_MPU == 1 ) + subs r2, r2, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ +#else /* configENABLE_MPU */ + subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ +#endif /* configENABLE_MPU */ + b select_next_task + + save_ns_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( configENABLE_MPU == 1 ) + subs r2, r2, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + adds r2, r2, #16 /* r2 = r2 + 16. */ + stm r2, {r4-r11} /* Store the registers that are not saved automatically. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + subs r2, r2, #16 /* r2 = r2 - 16. */ + stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + adds r2, r2, #12 /* r2 = r2 + 12. */ + stm r2, {r4-r11} /* Store the registers that are not saved automatically. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + subs r2, r2, #12 /* r2 = r2 - 12. */ + stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + #if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r3] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r3] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */ + ldr r3, =0xe000edc0 /* r3 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r3] /* Program MAIR0. */ + ldr r3, =0xe000ed98 /* r3 = 0xe000ed98 [Location of RNR]. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r3] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r3!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r3] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r3] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + + #if ( configENABLE_MPU == 1 ) + ldmia r2!, {r0, r1, r3, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r3 /* Restore the CONTROL register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + #else /* configENABLE_MPU */ + ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + #endif /* configENABLE_MPU */ + + restore_ns_context: + ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr +/*-----------------------------------------------------------*/ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + /* r0 = uint32_t *pulTCB. */ + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + it ne + svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/portmacro.h new file mode 100644 index 0000000..75bdbb7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/portmacro.h @@ -0,0 +1,78 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h new file mode 100644 index 0000000..26aa668 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_context.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_context.c new file mode 100644 index 0000000..a63d59e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_context.c @@ -0,0 +1,351 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Ontain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_context.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_context.h new file mode 100644 index 0000000..ba883ed --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_context.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s new file mode 100644 index 0000000..62a0cbf --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */ + vldmia r1!, {s0} /* Nullify the effect of the previous statement. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + stmdb r1!, {r2} /* Store CONTROL value on the stack. */ +#endif /* configENABLE_MPU */ + + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_heap.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_heap.c new file mode 100644 index 0000000..19a7fae --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_heap.c @@ -0,0 +1,451 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart, * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/** + * @brief Gets set to the top bit of an size_t type. + * + * When this bit in the xBlockSize member of an BlockLink_t structure is set + * then the block belongs to the application. When the bit is free the block is + * still part of the free heap space. + */ +static size_t xBlockAllocatedBit = 0; +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink; + void * pvReturn = NULL; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size is increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number of + * bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); + secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_heap.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_heap.h new file mode 100644 index 0000000..0009003 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_init.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_init.c new file mode 100644 index 0000000..a21ea1c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_init.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_init.h new file mode 100644 index 0000000..2a0352c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_port_macros.h new file mode 100644 index 0000000..d8ab67a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h new file mode 100644 index 0000000..d2152e1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s new file mode 100644 index 0000000..47f5ae7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s @@ -0,0 +1,262 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r3, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r3, #4 /* r3 = 4. */ + str r3, [r2] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + msr control, r2 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r2 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ +#if ( configENABLE_MPU == 1 ) + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r2, control /* r2 = CONTROL. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */ +#else /* configENABLE_MPU */ + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ +#endif /* configENABLE_MPU */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r3, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r3, #4 /* r3 = 4. */ + str r3, [r2] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */ +#else /* configENABLE_MPU */ + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ +#endif /* configENABLE_MPU */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + #if ( configENABLE_MPU == 1 ) + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r2 /* Restore the CONTROL register value for the task. */ +#else /* configENABLE_MPU */ + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ +#endif /* configENABLE_MPU */ + msr psp, r0 /* Remember the new top of stack for the task. */ + bx r3 +/*-----------------------------------------------------------*/ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h new file mode 100644 index 0000000..75bdbb7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h @@ -0,0 +1,78 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 0000000..4a5222b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,315 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + * + * Copyright 2019-2020 MicroEJ Corp. This file has been modified by MicroEJ Corp. + * 1. Patch for SystemView support + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) { if( xSwitchRequired ) { traceISR_EXIT_TO_SCHEDULER(); portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } else { traceISR_EXIT(); } } + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F/port.c new file mode 100644 index 0000000..9edc396 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F/port.c @@ -0,0 +1,647 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F port. +*----------------------------------------------------------*/ + +/* IAR includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __ARMVFP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 + * r0p1 port. */ +#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Turn the VFP on. + */ +extern void vPortEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* This port can be used on all revisions of the Cortex-M7 core other than + * the r0p1 parts. r0p1 parts should use the port from the + * /source/portable/GCC/ARM_CM7/r0p1 directory. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_interrupt() + * call above. */ + __enable_interrupt(); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __DSB(); + __WFI(); + __ISB(); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __enable_interrupt(); + __DSB(); + __ISB(); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __enable_interrupt(); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F/portasm.s new file mode 100644 index 0000000..84b4417 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F/portasm.s @@ -0,0 +1,150 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include + + RSEG CODE:CODE(2) + thumb + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + PUBLIC vPortEnableVFP + + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + isb + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r2, [r3] + + /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + /* Save the core registers. */ + stmdb r0!, {r4-r11, r14} + + /* Save the new top of stack into the first member of the TCB. */ + str r0, [r2] + + stmdb sp!, {r0, r3} + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [r3] + ldr r0, [r1] + + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + + /* Is the task using the FPU context? If so, pop the high vfp registers + too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */ + #if WORKAROUND_PMU_CM001 == 1 + push { r14 } + pop { pc } + #endif + #endif + + bx r14 + + +/*-----------------------------------------------------------*/ + +vPortSVCHandler: + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r1, [r3] + ldr r0, [r1] + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Clear the bit that indicates the FPU is in use in case the FPU was used + before the scheduler was started - which would otherwise result in the + unnecessary leaving of space in the SVC stack for lazy saving of FPU + registers. */ + mov r0, #0 + msr control, r0 + /* Call SVC to start the first task. */ + cpsie i + cpsie f + dsb + isb + svc 0 + +/*-----------------------------------------------------------*/ + +vPortEnableVFP: + /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 + ldr r1, [r0] + + /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [r0] + bx r14 + + + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F/portmacro.h new file mode 100644 index 0000000..9c01f1e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F/portmacro.h @@ -0,0 +1,207 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* IAR includes. */ + #include + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Compiler directives. */ + #define portWEAK_SYMBOL __attribute__( ( weak ) ) + +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __DSB(); \ + __ISB(); \ + } + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + + #define portDISABLE_INTERRUPTS() \ + { \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + } + + #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + #define portINLINE __inline + + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) + { + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ + #pragma diag_suppress=Pe191 + #pragma diag_suppress=Pa082 + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F_MPU/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F_MPU/port.c new file mode 100644 index 0000000..ddc0db2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F_MPU/port.c @@ -0,0 +1,837 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F MPU port. +*----------------------------------------------------------*/ + +/* IAR includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#ifndef __ARMVFP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS + #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security." + #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1 +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL ) + +/* Constants required to access and manipulate the MPU. */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) ) +#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portMPU_ENABLE ( 0x01UL ) +#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) +#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) +#define portMPU_REGION_VALID ( 0x10UL ) +#define portMPU_REGION_ENABLE ( 0x01UL ) +#define portPERIPHERALS_START_ADDRESS 0x40000000UL +#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL + +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure + * that a work around is active for errata 837070. */ +#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) +#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) +#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) + +/* Offsets in the stack to the parameters when inside the SVC handler. */ +#define portOFFSET_TO_PC ( 6 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* + * Configure a number of standard MPU regions that are used by all tasks. + */ +static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; + +/* + * Return the smallest MPU region size that a given number of bytes will fit + * into. The region size is returned as the value that should be programmed + * into the region attribute register for that region. + */ +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION; + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION; + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION; + +/* + * Turn the VFP on. + */ +extern void vPortEnableVFP( void ); + +/* + * The C portion of the SVC handler. + */ +void vPortSVCHandler_C( uint32_t * pulParam ); + +/* + * Called from the SVC handler used to start the scheduler. + */ +extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * @brief Exit from critical section. + */ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortExitCritical( void ) PRIVILEGED_FUNCTION; +#endif +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED; + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED; + } + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulParam ) +{ + uint8_t ucSVCNumber; + uint32_t ulPC; + + #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + + /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first + * argument (r0) is pulParam[ 0 ]. */ + ulPC = pulParam[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + case portSVC_START_SCHEDULER: + portNVIC_SHPR2_REG |= portNVIC_SVC_PRI; + vPortRestoreContextOfFirstTask(); + break; + + case portSVC_YIELD: + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required + * but do ensure the code is completely + * within the specified behaviour for the + * architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); + + break; + + #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) + case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the + * svc was raised from any of the + * system calls. */ + + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + __asm volatile + ( + " mrs r1, control \n"/* Obtain current control value. */ + " bic r1, r1, #1 \n"/* Set privilege bit. */ + " msr control, r1 \n"/* Write back new control value. */ + ::: "r1", "memory" + ); + } + + break; + #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + case portSVC_RAISE_PRIVILEGE: + __asm volatile + ( + " mrs r1, control \n"/* Obtain current control value. */ + " bic r1, r1, #1 \n"/* Set privilege bit. */ + " msr control, r1 \n"/* Write back new control value. */ + ::: "r1", "memory" + ); + break; + #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + + default: /* Unknown SVC call. */ + break; + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) ); + #else + /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define + * configENABLE_ERRATA_837070_WORKAROUND to 1 in your + * FreeRTOSConfig.h. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + #endif + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Configure the regions in the MPU that are common to all tasks. */ + prvSetupMPU(); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } + } +#else + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +#endif +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#else + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +#endif +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupMPU( void ) +{ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __FLASH_segment_start__[]; + extern uint32_t __FLASH_segment_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check the expected MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* First setup the unprivileged flash for unprivileged read only access. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portUNPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) | + ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged flash for privileged only access. This is where + * the kernel code is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) | + ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged data RAM region. This is where the kernel data + * is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_RAM_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) | + ( portMPU_REGION_ENABLE ); + + /* By default allow everything to access the general peripherals. The + * system peripherals and registers are protected. */ + portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) | + ( portMPU_REGION_VALID ) | + ( portGENERAL_PERIPHERALS_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) | + ( portMPU_REGION_ENABLE ); + + /* Enable the memory fault exception. */ + portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE; + + /* Enable the MPU with the background region configured. */ + portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE ); + } +} +/*-----------------------------------------------------------*/ + +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) +{ + uint32_t ulRegionSize, ulReturnValue = 4; + + /* 32 is the smallest region size, 31 is the largest valid value for + * ulReturnValue. */ + for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) ) + { + if( ulActualSizeInBytes <= ulRegionSize ) + { + break; + } + else + { + ulReturnValue++; + } + } + + /* Shift the code by one before returning so it can be written directly + * into the the correct bit position of the attribute register. */ + return( ulReturnValue << 1UL ); +} +/*-----------------------------------------------------------*/ + +void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) +{ + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + int32_t lIndex; + uint32_t ul; + + if( xRegions == NULL ) + { + /* No MPU regions are specified so allow access to all RAM. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Invalidate user configurable regions. */ + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + } + } + else + { + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that the + * stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) pxBottomOfStack ) | + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( portMPU_REGION_ENABLE ); + } + + lIndex = 0; + + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) + { + /* Translate the generic region definition contained in + * xRegions into the CM4 specific MPU settings that are then + * stored in xMPUSettings. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = + ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | + ( portMPU_REGION_VALID ) | + ( ul - 1UL ); /* Region number. */ + + xMPUSettings->xRegion[ ul ].ulRegionAttribute = + ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | + ( xRegions[ lIndex ].ulParameters ) | + ( portMPU_REGION_ENABLE ); + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + } + + lIndex++; + } + } +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F_MPU/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F_MPU/portasm.s new file mode 100644 index 0000000..ce6f705 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F_MPU/portasm.s @@ -0,0 +1,264 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include + + RSEG CODE:CODE(2) + thumb + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + PUBLIC vPortEnableVFP + PUBLIC vPortRestoreContextOfFirstTask + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + isb + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r2, [r3] + + /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + /* Save the core registers. */ + mrs r1, control + stmdb r0!, {r1, r4-r11, r14} + + /* Save the new top of stack into the first member of the TCB. */ + str r0, [r2] + + stmdb sp!, {r0, r3} + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsid i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + msr basepri, r0 + dsb + isb + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsie i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [r3] + ldr r0, [r1] + /* Move onto the second item in the TCB... */ + add r1, r1, #4 + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + bic r3, r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + str r3, [r2] /* Disable MPU. */ + + /* Region Base Address register. */ + ldr r2, =0xe000ed9c + /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + ldmia r1!, {r4-r11} + /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r2, {r4-r11} + + #ifdef configTOTAL_MPU_REGIONS + #if ( configTOTAL_MPU_REGIONS == 16 ) + /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + ldmia r1!, {r4-r11} + /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + stmia r2, {r4-r11} + /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ + ldmia r1!, {r4-r11} + /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ + stmia r2, {r4-r11} + #endif /* configTOTAL_MPU_REGIONS == 16. */ + #endif /* configTOTAL_MPU_REGIONS */ + + ldr r2, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + str r3, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + /* Pop the registers that are not automatically saved on exception entry. */ + ldmia r0!, {r3-r11, r14} + msr control, r3 + + /* Is the task using the FPU context? If so, pop the high vfp registers + too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + + bx r14 + + +/*-----------------------------------------------------------*/ + +vPortSVCHandler: + #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + #else + mrs r0, psp + #endif + b vPortSVCHandler_C + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask: + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Clear the bit that indicates the FPU is in use in case the FPU was used + before the scheduler was started - which would otherwise result in the + unnecessary leaving of space in the SVC stack for lazy saving of FPU + registers. */ + mov r0, #0 + msr control, r0 + /* Call SVC to start the first task. */ + cpsie i + cpsie f + dsb + isb + svc 0 + +/*-----------------------------------------------------------*/ + +vPortRestoreContextOfFirstTask: + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Restore the context. */ + ldr r3, =pxCurrentTCB + ldr r1, [r3] + /* The first item in the TCB is the task top of stack. */ + ldr r0, [r1] + /* Move onto the second item in the TCB... */ + add r1, r1, #4 + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + bic r3, r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + str r3, [r2] /* Disable MPU. */ + + /* Region Base Address register. */ + ldr r2, =0xe000ed9c + /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + ldmia r1!, {r4-r11} + /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r2, {r4-r11} + + #ifdef configTOTAL_MPU_REGIONS + #if ( configTOTAL_MPU_REGIONS == 16 ) + /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + ldmia r1!, {r4-r11} + /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + stmia r2, {r4-r11} + /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ + ldmia r1!, {r4-r11} + /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ + stmia r2, {r4-r11} + #endif /* configTOTAL_MPU_REGIONS == 16. */ + #endif /* configTOTAL_MPU_REGIONS */ + + ldr r2, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + str r3, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + /* Pop the registers that are not automatically saved on exception entry. */ + ldmia r0!, {r3-r11, r14} + msr control, r3 + /* Restore the task stack pointer. */ + msr psp, r0 + mov r0, #0 + msr basepri, r0 + bx r14 + +/*-----------------------------------------------------------*/ + +vPortEnableVFP: + /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 + ldr r1, [r0] + + /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [r0] + bx r14 + +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F_MPU/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F_MPU/portmacro.h new file mode 100644 index 0000000..c540270 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM4F_MPU/portmacro.h @@ -0,0 +1,369 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* IAR includes. */ +#include + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif + +/*-----------------------------------------------------------*/ + +/* MPU specific constants. */ +#define portUSING_MPU_WRAPPERS 1 +#define portPRIVILEGE_BIT ( 0x80000000UL ) + +#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) +#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) +#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) +#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) + +/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size + * Register (RASR). */ +#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) +#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* + * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the + * memory type, and where necessary the cacheable and shareable properties + * of the memory region. + * + * The TEX, C, and B bits together indicate the memory type of the region, + * and: + * - For Normal memory, the cacheable properties of the region. + * - For Device memory, whether the region is shareable. + * + * For Normal memory regions, the S bit indicates whether the region is + * shareable. For Strongly-ordered and Device memory, the S bit is ignored. + * + * See the following two tables for setting TEX, S, C and B bits for + * unprivileged flash, privileged flash and privileged RAM regions. + * + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 1 | Device | Shared device | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 0 | Device | Non-shared device | Not shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 1 | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 011 | X | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved | + | | | | | outer cacheability rules that must be exported on the | | + | | | | | bus. See the table below for the cacheability policy | | + | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | + +-----------------------------------------+----------------------------------------+ + | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy | + +-----------------------------------------+----------------------------------------+ + | 00 | Non-cacheable | + +-----------------------------------------+----------------------------------------+ + | 01 | Write-back, write and read allocate | + +-----------------------------------------+----------------------------------------+ + | 10 | Write-through, no write allocate | + +-----------------------------------------+----------------------------------------+ + | 11 | Write-back, no write allocate | + +-----------------------------------------+----------------------------------------+ + */ + +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash + * region. */ +#ifndef configTEX_S_C_B_FLASH + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_FLASH ( 0x07UL ) +#endif + +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM + * region. */ +#ifndef configTEX_S_C_B_SRAM + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_SRAM ( 0x07UL ) +#endif + +#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL ) +#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL ) +#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL ) +#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL ) +#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portFIRST_CONFIGURABLE_REGION ( 0UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL ) +#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL ) +#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */ + +#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" ) + +typedef struct MPU_REGION_REGISTERS +{ + uint32_t ulRegionBaseAddress; + uint32_t ulRegionAttribute; +} xMPU_REGION_REGISTERS; + +typedef struct MPU_SETTINGS +{ + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ]; +} xMPU_SETTINGS; + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* SVC numbers for various services. */ +#define portSVC_START_SCHEDULER 0 +#define portSVC_YIELD 1 +#define portSVC_RAISE_PRIVILEGE 2 + +/* Scheduler utilities. */ + +#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" ) +#define portYIELD_WITHIN_API() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __DSB(); \ + __ISB(); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API(); } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#if( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + #define portDISABLE_INTERRUPTS() \ + { \ + __disable_interrupt(); \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + __enable_interrupt(); \ + } +#else + #define portDISABLE_INTERRUPTS() \ + { \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + } +#endif + +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + + +/*-----------------------------------------------------------*/ + +extern BaseType_t xIsPrivileged( void ); +extern void vResetPrivilege( void ); + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +#define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + */ +#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ +#define portRESET_PRIVILEGE() vResetPrivilege() +/*-----------------------------------------------------------*/ + +#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html" + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 +#endif +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 +#pragma diag_suppress=Be006 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/portasm.h new file mode 100644 index 0000000..58eb5cd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/portasm.s new file mode 100644 index 0000000..e4d5234 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/portasm.s @@ -0,0 +1,353 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r2] /* Program RNR = 4. */ + adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + ldr r5, =xSecureContext + str r1, [r5] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + msr control, r3 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r4 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + push {r0-r2, r14} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r3} /* LR is now in r3. */ + mov lr, r3 /* LR = r3. */ + lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ +#if ( configENABLE_MPU == 1 ) + subs r2, r2, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ +#else /* configENABLE_MPU */ + subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ +#endif /* configENABLE_MPU */ + b select_next_task + + save_ns_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( configENABLE_MPU == 1 ) + subs r2, r2, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + adds r2, r2, #16 /* r2 = r2 + 16. */ + stm r2, {r4-r11} /* Store the registers that are not saved automatically. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + subs r2, r2, #16 /* r2 = r2 - 16. */ + stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + adds r2, r2, #12 /* r2 = r2 + 12. */ + stm r2, {r4-r11} /* Store the registers that are not saved automatically. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + subs r2, r2, #12 /* r2 = r2 - 12. */ + stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + #if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r3] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r3] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */ + ldr r3, =0xe000edc0 /* r3 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r3] /* Program MAIR0. */ + ldr r3, =0xe000ed98 /* r3 = 0xe000ed98 [Location of RNR]. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r3] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r3!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r3] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r3] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + + #if ( configENABLE_MPU == 1 ) + ldmia r2!, {r0, r1, r3, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r3 /* Restore the CONTROL register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + #else /* configENABLE_MPU */ + ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + #endif /* configENABLE_MPU */ + + restore_ns_context: + ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr +/*-----------------------------------------------------------*/ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + /* r0 = uint32_t *pulTCB. */ + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + it ne + svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/portmacro.h new file mode 100644 index 0000000..a2ec280 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/portmacro.h @@ -0,0 +1,83 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M55" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h new file mode 100644 index 0000000..26aa668 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_context.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_context.c new file mode 100644 index 0000000..dbe45b7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_context.c @@ -0,0 +1,351 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Ontain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_context.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_context.h new file mode 100644 index 0000000..9ba64b5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_context.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s new file mode 100644 index 0000000..d4f2a3e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */ + vldmia r1!, {s0} /* Nullify the effect of the previous statement. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + stmdb r1!, {r2} /* Store CONTROL value on the stack. */ +#endif /* configENABLE_MPU */ + + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_heap.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_heap.c new file mode 100644 index 0000000..41cee90 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_heap.c @@ -0,0 +1,451 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart, * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/** + * @brief Gets set to the top bit of an size_t type. + * + * When this bit in the xBlockSize member of an BlockLink_t structure is set + * then the block belongs to the application. When the bit is free the block is + * still part of the free heap space. + */ +static size_t xBlockAllocatedBit = 0; +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink; + void * pvReturn = NULL; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size is increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number of + * bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); + secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_heap.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_heap.h new file mode 100644 index 0000000..217db7a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_init.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_init.c new file mode 100644 index 0000000..e28974a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_init.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_init.h new file mode 100644 index 0000000..5871002 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_port_macros.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_port_macros.h new file mode 100644 index 0000000..31e4140 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h new file mode 100644 index 0000000..58eb5cd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s new file mode 100644 index 0000000..0b9051a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s @@ -0,0 +1,262 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r3, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r3, #4 /* r3 = 4. */ + str r3, [r2] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + msr control, r2 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r2 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ +#if ( configENABLE_MPU == 1 ) + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r2, control /* r2 = CONTROL. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */ +#else /* configENABLE_MPU */ + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ +#endif /* configENABLE_MPU */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r3, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r3, #4 /* r3 = 4. */ + str r3, [r2] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */ +#else /* configENABLE_MPU */ + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ +#endif /* configENABLE_MPU */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + #if ( configENABLE_MPU == 1 ) + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r2 /* Restore the CONTROL register value for the task. */ +#else /* configENABLE_MPU */ + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ +#endif /* configENABLE_MPU */ + msr psp, r0 /* Remember the new top of stack for the task. */ + bx r3 +/*-----------------------------------------------------------*/ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h new file mode 100644 index 0000000..a2ec280 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h @@ -0,0 +1,83 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M55" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 0000000..26aa668 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM7/ReadMe.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM7/ReadMe.txt new file mode 100644 index 0000000..2116456 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM7/ReadMe.txt @@ -0,0 +1,18 @@ +There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers. +The best option depends on the revision of the ARM Cortex-M7 core in use. The +revision is specified by an 'r' number, and a 'p' number, so will look something +like 'r0p1'. Check the documentation for the microcontroller in use to find the +revision of the Cortex-M7 core used in that microcontroller. If in doubt, use +the FreeRTOS port provided specifically for r0p1 revisions, as that can be used +with all core revisions. + +The first option is to use the ARM Cortex-M4F port, and the second option is to +use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround. + +If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be +used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in +the /FreeRTOS/Source/portable/IAR/ARM_CM4F directory. + +If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM +Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1 +directory. \ No newline at end of file diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM7/r0p1/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM7/r0p1/port.c new file mode 100644 index 0000000..2633b33 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM7/r0p1/port.c @@ -0,0 +1,635 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM7 port. +*----------------------------------------------------------*/ + +/* IAR includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __ARMVFP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Turn the VFP on. + */ +extern void vPortEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_interrupt() + * call above. */ + __enable_interrupt(); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __DSB(); + __WFI(); + __ISB(); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __enable_interrupt(); + __DSB(); + __ISB(); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __enable_interrupt(); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM7/r0p1/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM7/r0p1/portasm.s new file mode 100644 index 0000000..5704810 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM7/r0p1/portasm.s @@ -0,0 +1,152 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include + + RSEG CODE:CODE(2) + thumb + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + PUBLIC vPortEnableVFP + + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + isb + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r2, [r3] + + /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + /* Save the core registers. */ + stmdb r0!, {r4-r11, r14} + + /* Save the new top of stack into the first member of the TCB. */ + str r0, [r2] + + stmdb sp!, {r0, r3} + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + cpsid i + msr basepri, r0 + dsb + isb + cpsie i + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [r3] + ldr r0, [r1] + + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + + /* Is the task using the FPU context? If so, pop the high vfp registers + too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */ + #if WORKAROUND_PMU_CM001 == 1 + push { r14 } + pop { pc } + #endif + #endif + + bx r14 + + +/*-----------------------------------------------------------*/ + +vPortSVCHandler: + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r1, [r3] + ldr r0, [r1] + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Clear the bit that indicates the FPU is in use in case the FPU was used + before the scheduler was started - which would otherwise result in the + unnecessary leaving of space in the SVC stack for lazy saving of FPU + registers. */ + mov r0, #0 + msr control, r0 + /* Call SVC to start the first task. */ + cpsie i + cpsie f + dsb + isb + svc 0 + +/*-----------------------------------------------------------*/ + +vPortEnableVFP: + /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 + ldr r1, [r0] + + /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [r0] + bx r14 + + + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM7/r0p1/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM7/r0p1/portmacro.h new file mode 100644 index 0000000..fdab70c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM7/r0p1/portmacro.h @@ -0,0 +1,210 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* IAR includes. */ + #include + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Compiler directives. */ + #define portWEAK_SYMBOL __attribute__( ( weak ) ) + +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __DSB(); \ + __ISB(); \ + } + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + + #define portDISABLE_INTERRUPTS() \ + { \ + /* Errata work around. */ \ + __disable_interrupt(); \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + __enable_interrupt(); \ + } + + #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + #define portINLINE __inline + + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) + { + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ + #pragma diag_suppress=Pe191 + #pragma diag_suppress=Pa082 + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/portasm.h new file mode 100644 index 0000000..d2152e1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/portasm.s new file mode 100644 index 0000000..deb3626 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/portasm.s @@ -0,0 +1,353 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r2] /* Program RNR = 4. */ + adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + ldr r5, =xSecureContext + str r1, [r5] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + msr control, r3 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r4 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + push {r0-r2, r14} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r3} /* LR is now in r3. */ + mov lr, r3 /* LR = r3. */ + lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ +#if ( configENABLE_MPU == 1 ) + subs r2, r2, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ +#else /* configENABLE_MPU */ + subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ +#endif /* configENABLE_MPU */ + b select_next_task + + save_ns_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + #if ( configENABLE_MPU == 1 ) + subs r2, r2, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + adds r2, r2, #16 /* r2 = r2 + 16. */ + stm r2, {r4-r11} /* Store the registers that are not saved automatically. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + subs r2, r2, #16 /* r2 = r2 - 16. */ + stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + adds r2, r2, #12 /* r2 = r2 + 12. */ + stm r2, {r4-r11} /* Store the registers that are not saved automatically. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + subs r2, r2, #12 /* r2 = r2 - 12. */ + stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + #if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r3] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r3] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */ + ldr r3, =0xe000edc0 /* r3 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r3] /* Program MAIR0. */ + ldr r3, =0xe000ed98 /* r3 = 0xe000ed98 [Location of RNR]. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r3] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r3!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r3] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r3] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + + #if ( configENABLE_MPU == 1 ) + ldmia r2!, {r0, r1, r3, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r3 /* Restore the CONTROL register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + #else /* configENABLE_MPU */ + ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + #endif /* configENABLE_MPU */ + + restore_ns_context: + ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr +/*-----------------------------------------------------------*/ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + /* r0 = uint32_t *pulTCB. */ + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + it ne + svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/portmacro.h new file mode 100644 index 0000000..59fc09b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/portmacro.h @@ -0,0 +1,83 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M85" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h new file mode 100644 index 0000000..26aa668 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_context.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_context.c new file mode 100644 index 0000000..a63d59e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_context.c @@ -0,0 +1,351 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Ontain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_context.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_context.h new file mode 100644 index 0000000..ba883ed --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_context.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s new file mode 100644 index 0000000..62a0cbf --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */ + vldmia r1!, {s0} /* Nullify the effect of the previous statement. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + stmdb r1!, {r2} /* Store CONTROL value on the stack. */ +#endif /* configENABLE_MPU */ + + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_heap.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_heap.c new file mode 100644 index 0000000..19a7fae --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_heap.c @@ -0,0 +1,451 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart, * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/** + * @brief Gets set to the top bit of an size_t type. + * + * When this bit in the xBlockSize member of an BlockLink_t structure is set + * then the block belongs to the application. When the bit is free the block is + * still part of the free heap space. + */ +static size_t xBlockAllocatedBit = 0; +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink; + void * pvReturn = NULL; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size is increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number of + * bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); + secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_heap.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_heap.h new file mode 100644 index 0000000..0009003 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_init.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_init.c new file mode 100644 index 0000000..a21ea1c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_init.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_init.h new file mode 100644 index 0000000..2a0352c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_port_macros.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_port_macros.h new file mode 100644 index 0000000..d8ab67a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/port.c new file mode 100644 index 0000000..3efc4d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/port.c @@ -0,0 +1,1203 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h new file mode 100644 index 0000000..d2152e1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s new file mode 100644 index 0000000..47f5ae7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s @@ -0,0 +1,262 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r3, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r3, #4 /* r3 = 4. */ + str r3, [r2] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + msr control, r2 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r2 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ +#if ( configENABLE_MPU == 1 ) + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r2, control /* r2 = CONTROL. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */ +#else /* configENABLE_MPU */ + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ +#endif /* configENABLE_MPU */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r3, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r3, #4 /* r3 = 4. */ + str r3, [r2] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */ +#else /* configENABLE_MPU */ + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ +#endif /* configENABLE_MPU */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + #if ( configENABLE_MPU == 1 ) + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r2 /* Restore the CONTROL register value for the task. */ +#else /* configENABLE_MPU */ + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ +#endif /* configENABLE_MPU */ + msr psp, r0 /* Remember the new top of stack for the task. */ + bx r3 +/*-----------------------------------------------------------*/ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h new file mode 100644 index 0000000..59fc09b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h @@ -0,0 +1,83 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "portmacrocommon.h" + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M85" +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +#if( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus + } +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 0000000..26aa668 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,311 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H + #define PORTMACROCOMMON_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACROCOMMON_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CRx_No_GIC/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CRx_No_GIC/port.c new file mode 100644 index 0000000..9cb0591 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CRx_No_GIC/port.c @@ -0,0 +1,317 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt. +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt. +#endif + +/* A critical section is exited when the critical section nesting count reaches +this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Tasks are not created with a floating point context, but can be given a +floating point context after they have been created. A variable is stored as +part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task +does not have an FPU context, or any other value if the task does have an FPU +context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user +mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* Let the user override the pre-loading of the initial LR with the address of +prvTaskExitError() in case it messes up unwinding of the stack in the +debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This +variable has to be stored as part of the task context and must be initialised to +a non zero value to ensure interrupts don't inadvertently become unmasked before +the scheduler starts. As it is stored as part of the task context it will +automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then +a floating point context must be saved and restored for the task. */ +volatile uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +volatile uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if +if the nesting depth is 0. */ +volatile uint32_t ulPortInterruptNesting = 0UL; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. + + The fist real value on the stack is the status register, which is set for + system mode, with interrupts enabled. A few NULLs are added first to ensure + GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + the floating point hardware must call vPortTaskUsesFPU() before executing + any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +uint32_t ulAPSR; + + /* Only continue if the CPU is not in User mode. The CPU must be in a + Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Start the timer that generates the tick ISR. */ + portDISABLE_INTERRUPTS(); + configSETUP_TICK_INTERRUPT(); + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + a non-privileged mode or the binary point register was not set to its lowest + possible value. prvTaskExitError() is referenced to prevent a compiler + warning about it being defined but not referenced in the case that the user + defines their own exit address. */ + ( void ) prvTaskExitError; + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + should be unmasked. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ +uint32_t ulInterruptStatus; + + ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus ); + + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ +uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); +} +/*-----------------------------------------------------------*/ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CRx_No_GIC/portASM.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CRx_No_GIC/portASM.s new file mode 100644 index 0000000..e2f882c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CRx_No_GIC/portASM.s @@ -0,0 +1,248 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +#include "FreeRTOSConfig.h" + + SECTION .text:CODE:ROOT(2) + arm + + /* Variables and functions. */ + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vApplicationIRQHandler + EXTERN ulPortInterruptNesting + EXTERN ulPortTaskHasFPUContext + EXTERN ulPortYieldRequired + EXTERN ulCriticalNesting + + PUBLIC FreeRTOS_IRQ_Handler + PUBLIC FreeRTOS_SVC_Handler + PUBLIC vPortRestoreTaskContext + +SYS_MODE EQU 0x1f +SVC_MODE EQU 0x13 +IRQ_MODE EQU 0x12 + +portSAVE_CONTEXT MACRO + + /* Save the LR and SPSR onto the system mode stack before switching to + system mode to save the remaining system mode registers. */ + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + /* Push the critical nesting count. */ + LDR R2, =ulCriticalNesting + LDR R1, [R2] + PUSH {R1} + + /* Does the task have a floating point context that needs saving? If + ulPortTaskHasFPUContext is 0 then no. */ + LDR R2, =ulPortTaskHasFPUContext + LDR R3, [R2] + CMP R3, #0 + + /* Save the floating point context, if any. */ + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} +#if configFPU_D32 == 1 + VPUSHNE {D16-D31} +#endif /* configFPU_D32 */ + PUSHNE {R1} + + /* Save ulPortTaskHasFPUContext itself. */ + PUSH {R3} + + /* Save the stack pointer in the TCB. */ + LDR R0, =pxCurrentTCB + LDR R1, [R0] + STR SP, [R1] + + ENDM + +; /**********************************************************************/ + +portRESTORE_CONTEXT MACRO + + /* Set the SP to point to the stack of the task being restored. */ + LDR R0, =pxCurrentTCB + LDR R1, [R0] + LDR SP, [R1] + + /* Is there a floating point context to restore? If the restored + ulPortTaskHasFPUContext is zero then no. */ + LDR R0, =ulPortTaskHasFPUContext + POP {R1} + STR R1, [R0] + CMP R1, #0 + + /* Restore the floating point context, if any. */ + POPNE {R0} +#if configFPU_D32 == 1 + VPOPNE {D16-D31} +#endif /* configFPU_D32 */ + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + /* Restore the critical section nesting depth. */ + LDR R0, =ulCriticalNesting + POP {R1} + STR R1, [R0] + + /* Restore all system mode registers other than the SP (which is already + being used). */ + POP {R0-R12, R14} + + /* Return to the task code, loading CPSR on the way. */ + RFEIA sp! + + ENDM + + + + +/****************************************************************************** + * SVC handler is used to yield. + *****************************************************************************/ +FreeRTOS_SVC_Handler: + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + LDR R0, =vTaskSwitchContext + BLX R0 + portRESTORE_CONTEXT + + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ +vPortRestoreTaskContext: + /* Switch to system mode. */ + CPS #SYS_MODE + portRESTORE_CONTEXT + +FreeRTOS_IRQ_Handler: + /* Return to the interrupted instruction. */ + SUB lr, lr, #4 + + /* Push the return address and SPSR. */ + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + /* Change to supervisor mode to allow reentry. */ + CPS #SVC_MODE + + /* Push used registers. */ + PUSH {r0-r3, r12} + + /* Increment nesting count. r3 holds the address of ulPortInterruptNesting + for future use. r1 holds the original ulPortInterruptNesting value for + future use. */ + LDR r3, =ulPortInterruptNesting + LDR r1, [r3] + ADD r0, r1, #1 + STR r0, [r3] + + /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + future use. */ + MOV r0, sp + AND r2, r0, #4 + SUB sp, sp, r2 + + /* Call the interrupt handler. */ + PUSH {r0-r3, lr} + LDR r1, =vApplicationIRQHandler + BLX r1 + POP {r0-r3, lr} + ADD sp, sp, r2 + + CPSID i + DSB + ISB + + /* Write to the EOI register. */ + LDR r2, =configEOI_ADDRESS + STR r0, [r2] + + /* Restore the old nesting count. */ + STR r1, [r3] + + /* A context switch is never performed if the nesting count is not 0. */ + CMP r1, #0 + BNE exit_without_switch + + /* Did the interrupt request a context switch? r1 holds the address of + ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + use. */ + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch: + /* No context switch. Restore used registers, LR_irq and SPSR before + returning. */ + POP {r0-r3, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit: + /* A context swtich is to be performed. Clear the context switch pending + flag. */ + MOV r0, #0 + STR r0, [r1] + + /* Restore used registers, LR-irq and SPSR before saving the context + to the task stack. */ + POP {r0-r3, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + /* Call the function that selects the new task to execute. + vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + instructions, or 8 byte aligned stack allocated data. LR does not need + saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */ + LDR R0, =vTaskSwitchContext + BLX R0 + + /* Restore the context of, and branch to, the task selected to execute + next. */ + portRESTORE_CONTEXT + + END + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CRx_No_GIC/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CRx_No_GIC/portmacro.h new file mode 100644 index 0000000..1d4c029 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ARM_CRx_No_GIC/portmacro.h @@ -0,0 +1,182 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +typedef uint32_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do +not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired )\ +{ \ +extern volatile uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ +} + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm volatile ( "SWI 0 \n" \ + "ISB " ); + + +/*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); +extern void vPortInstallFreeRTOSVectorTable( void ); + +/* The I bit within the CPSR. */ +#define portINTERRUPT_ENABLE_BIT ( 1 << 7 ) + +/* In the absence of a priority mask register, these functions and macros +globally enable and disable interrupts. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ); +#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \ + "DSB \n" \ + "ISB " ); +#pragma inline +static inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void ) +{ +volatile uint32_t ulCPSR; + + __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) ); + ulCPSR &= portINTERRUPT_ENABLE_BIT; + portDISABLE_INTERRUPTS(); + return ulCPSR; +} + +#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) do { if( x == 0 ) portENABLE_INTERRUPTS(); } while( 0 ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not required for this port but included in case common demo code that uses these +macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the +handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() +before any floating point instructions are executed. */ +void vPortTaskUsesFPU( void ); +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#define portNOP() __asm volatile( "NOP" ) +#define portINLINE inline + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in +the source code because to do so would cause other compilers to generate +warnings. */ +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 + +#ifdef __cplusplus + } /* extern C */ +#endif + + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ATMega323/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ATMega323/port.c new file mode 100644 index 0000000..41ba192 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ATMega323/port.c @@ -0,0 +1,340 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include + +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the AVR/IAR port. + *----------------------------------------------------------*/ + +/* Start tasks with interrupts enables. */ +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) + +/* Hardware constants for timer 1. */ +#define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) 0x08 ) +#define portPRESCALE_64 ( ( uint8_t ) 0x03 ) +#define portCLOCK_PRESCALER ( ( uint32_t ) 64 ) +#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) 0x10 ) + +/* The number of bytes used on the hardware stack by the task start address. */ +#define portBYTES_USED_BY_RETURN_ADDRESS ( 2 ) +/*-----------------------------------------------------------*/ + +/* Stores the critical section nesting. This must not be initialised to 0. +It will be initialised when a task starts. */ +#define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 ) +UBaseType_t uxCriticalNesting = 0x50; + + +/* + * Perform hardware setup to enable ticks from timer 1, compare match A. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The IAR compiler does not have full support for inline assembler, so + * these are defined in the portmacro assembler file. + */ +extern void vPortYieldFromTick( void ); +extern void vPortStart( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint16_t usAddress; +StackType_t *pxTopOfHardwareStack; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + + /* Remember where the top of the hardware stack is - this is required + below. */ + pxTopOfHardwareStack = pxTopOfStack; + + + /* Simulate how the stack would look after a call to vPortYield(). */ + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + + + /* The IAR compiler requires two stacks per task. First there is the + hardware call stack which uses the AVR stack pointer. Second there is the + software stack (local variables, parameter passing, etc.) which uses the + AVR Y register. + + This function places both stacks within the memory block passed in as the + first parameter. The hardware stack is placed at the bottom of the memory + block. A gap is then left for the hardware stack to grow. Next the software + stack is placed. The amount of space between the software and hardware + stacks is defined by configCALL_STACK_SIZE. + + + + The first part of the stack is the hardware stack. Place the start + address of the task on the hardware stack. */ + usAddress = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + + /* Leave enough space for the hardware stack before starting the software + stack. The '- 2' is because we have already used two spaces for the + address of the start of the task. */ + pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); + + + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + portSAVE_CONTEXT places the flags on the stack immediately after r0 + to ensure the interrupts get disabled as soon as possible, and so ensuring + the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next place the address of the hardware stack. This is required so + the AVR stack pointer can be restored to point to the hardware stack. */ + pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS; + usAddress = ( uint16_t ) pxTopOfHardwareStack; + + /* SPL */ + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* SPH */ + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + + + + /* Now the remaining registers. */ + *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ + pxTopOfStack--; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ + pxTopOfStack--; + + /* The Y register is not stored as it is used as the software stack and + gets saved into the task control block. */ + + *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ + + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. + Normally we would just call portRESTORE_CONTEXT() here, but as the IAR + compiler does not fully support inline assembler we have to make a call.*/ + vPortStart(); + + /* Should not get here! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup timer 1 compare match A to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ +uint32_t ulCompareMatch; +uint8_t ucHighByte, ucLowByte; + + /* Using 16bit timer 1 to generate the tick. Correct fuses must be + selected for the configCPU_CLOCK_HZ clock. */ + + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* We only have 16 bits so have to scale to get our required tick rate. */ + ulCompareMatch /= portCLOCK_PRESCALER; + + /* Adjust for correct value. */ + ulCompareMatch -= ( uint32_t ) 1; + + /* Setup compare match value for compare match A. Interrupts are disabled + before this is called so we need not worry here. */ + ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); + ulCompareMatch >>= 8; + ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); + OCR1AH = ucHighByte; + OCR1AL = ucLowByte; + + /* Setup clock source and compare match behaviour. */ + ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64; + TCCR1B = ucLowByte; + + /* Enable the interrupt - this is okay as interrupt are currently globally + disabled. */ + TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a __task attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + __task void SIG_OUTPUT_COMPARE1A( void ) + { + vPortYieldFromTick(); + asm( "reti" ); + } + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + * + * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90. DO NOT INSTALL + * IT HERE USING THE USUAL PRAGMA. + */ + __interrupt void SIG_OUTPUT_COMPARE1A( void ) + { + xTaskIncrementTick(); + } +#endif +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + if( uxCriticalNesting == portNO_CRITICAL_NESTING ) + { + portENABLE_INTERRUPTS(); + } +} + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ATMega323/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ATMega323/portmacro.h new file mode 100644 index 0000000..88c4c46 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ATMega323/portmacro.h @@ -0,0 +1,113 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V1.2.3 + + + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it + base 16. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char +#define portPOINTER_SIZE_TYPE uint16_t + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif + +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#define portDISABLE_INTERRUPTS() asm( "cli" ) +#define portENABLE_INTERRUPTS() asm( "sei" ) +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm( "nop" ) +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +void vPortYield( void ); +#define portYIELD() vPortYield() + +#ifdef IAR_MEGA_AVR + #define outb( PORT, VALUE ) PORT = VALUE +#endif +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ATMega323/portmacro.s90 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ATMega323/portmacro.s90 new file mode 100644 index 0000000..7237c14 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/ATMega323/portmacro.s90 @@ -0,0 +1,246 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +#include + +; Declare all extern symbols here - including any ISRs that are referenced in +; the vector table. + +; ISR functions +; ------------- +EXTERN SIG_OUTPUT_COMPARE1A +EXTERN SIG_UART_RECV +EXTERN SIG_UART_DATA + + +; Functions used by scheduler +; --------------------------- +EXTERN vTaskSwitchContext +EXTERN pxCurrentTCB +EXTERN xTaskIncrementTick +EXTERN uxCriticalNesting + +; Functions implemented in this file +; ---------------------------------- +PUBLIC vPortYield +PUBLIC vPortYieldFromTick +PUBLIC vPortStart + + +; Interrupt vector table. +; ----------------------- +; +; For simplicity the RTOS tick interrupt routine uses the __task keyword. +; As the IAR compiler does not permit a function to be declared using both +; __task and __interrupt, the use of __task necessitates that the interrupt +; vector table be setup manually. +; +; To write an ISR, implement the ISR function using the __interrupt keyword +; but do not install the interrupt using the "#pragma vector=ABC" method. +; Instead manually place the name of the ISR in the vector table using an +; ORG and jmp instruction as demonstrated below. +; You will also have to add an EXTERN statement at the top of the file. + + ASEG + + + ORG TIMER1_COMPA_vect ; Vector address + jmp SIG_OUTPUT_COMPARE1A ; ISR + + ORG USART_RXC_vect ; Vector address + jmp SIG_UART_RECV ; ISR + + ORG USART_UDRE_vect ; Vector address + jmp SIG_UART_DATA ; ISR + + + RSEG CODE + + + +; Saving and Restoring a Task Context and Task Switching +; ------------------------------------------------------ +; +; The IAR compiler does not fully support inline assembler, so saving and +; restoring a task context has to be written in an asm file. +; +; vPortYield() and vPortYieldFromTick() are usually written in C. Doing +; so in this case would required calls to be made to portSAVE_CONTEXT() and +; portRESTORE_CONTEXT(). This is dis-advantageous as the context switch +; function would require two extra jump and return instructions over the +; WinAVR equivalent. +; +; To avoid this I have opted to implement both vPortYield() and +; vPortYieldFromTick() in this assembly file. For convenience +; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros. + +portSAVE_CONTEXT MACRO + st -y, r0 ; First save the r0 register - we need to use this. + in r0, SREG ; Obtain the SREG value so we can disable interrupts... + cli ; ... as soon as possible. + st -y, r0 ; Store the SREG as it was before we disabled interrupts. + + in r0, SPL ; Next store the hardware stack pointer. The IAR... + st -y, r0 ; ... compiler uses the hardware stack as a call stack ... + in r0, SPH ; ... only. + st -y, r0 + + st -y, r1 ; Now store the rest of the registers. Dont store the ... + st -y, r2 ; ... the Y register here as it is used as the software + st -y, r3 ; stack pointer and will get saved into the TCB. + st -y, r4 + st -y, r5 + st -y, r6 + st -y, r7 + st -y, r8 + st -y, r9 + st -y, r10 + st -y, r11 + st -y, r12 + st -y, r13 + st -y, r14 + st -y, r15 + st -y, r16 + st -y, r17 + st -y, r18 + st -y, r19 + st -y, r20 + st -y, r21 + st -y, r22 + st -y, r23 + st -y, r24 + st -y, r25 + st -y, r26 + st -y, r27 + st -y, r30 + st -y, r31 + lds r0, uxCriticalNesting + st -y, r0 ; Store the critical nesting counter. + + lds r26, pxCurrentTCB ; Finally save the software stack pointer (Y ... + lds r27, pxCurrentTCB + 1 ; ... register) into the TCB. + st x+, r28 + st x+, r29 + + ENDM + + +portRESTORE_CONTEXT MACRO + lds r26, pxCurrentTCB + lds r27, pxCurrentTCB + 1 ; Restore the software stack pointer from ... + ld r28, x+ ; the TCB into the software stack pointer (... + ld r29, x+ ; ... the Y register). + + ld r0, y+ + sts uxCriticalNesting, r0 + ld r31, y+ ; Restore the registers down to R0. The Y + ld r30, y+ ; register is missing from this list as it + ld r27, y+ ; has already been restored. + ld r26, y+ + ld r25, y+ + ld r24, y+ + ld r23, y+ + ld r22, y+ + ld r21, y+ + ld r20, y+ + ld r19, y+ + ld r18, y+ + ld r17, y+ + ld r16, y+ + ld r15, y+ + ld r14, y+ + ld r13, y+ + ld r12, y+ + ld r11, y+ + ld r10, y+ + ld r9, y+ + ld r8, y+ + ld r7, y+ + ld r6, y+ + ld r5, y+ + ld r4, y+ + ld r3, y+ + ld r2, y+ + ld r1, y+ + + ld r0, y+ ; The next thing on the stack is the ... + out SPH, r0 ; ... hardware stack pointer. + ld r0, y+ + out SPL, r0 + + ld r0, y+ ; Next there is the SREG register. + out SREG, r0 + + ld r0, y+ ; Finally we have finished with r0, so restore r0. + + ENDM + + + +; vPortYield() and vPortYieldFromTick() +; ------------------------------------- +; +; Manual and preemptive context switch functions respectively. +; The IAR compiler does not fully support inline assembler, +; so these are implemented here rather than the more usually +; place of within port.c. + +vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +vPortYieldFromTick: + portSAVE_CONTEXT ; Save the context of the current task. + call xTaskIncrementTick ; Call the timer tick function. + tst r16 + breq SkipTaskSwitch + call vTaskSwitchContext ; Call the scheduler. +SkipTaskSwitch: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +; vPortStart() +; ------------ +; +; Again due to the lack of inline assembler, this is required +; to get access to the portRESTORE_CONTEXT macro. + +vPortStart: + portRESTORE_CONTEXT + ret + + +; Just a filler for unused interrupt vectors. +vNoISR: + reti + + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/exception.s82 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/exception.s82 new file mode 100644 index 0000000..4ed5f50 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/exception.s82 @@ -0,0 +1,340 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Exception and interrupt vectors. + * + * This file maps all events supported by an AVR32UC. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32UC devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + https://www.microchip.com \n + * Support and FAQ: https://www.microchip.com/support + * + ******************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "intc.h" + + +//! @{ +//! \verbatim + + +// Start of Exception Vector Table. + + // EVBA must be aligned with a power of two strictly greater than the EVBA- + // relative offset of the last vector. + COMMON EVTAB:CODE:ROOT(9) + + + // Force EVBA initialization. + EXTERN ??init_EVBA + REQUIRE ??init_EVBA + + // Export symbol. + PUBLIC ??EVBA + PUBLIC _evba +??EVBA: +_evba: + + ORG 0x000 + // Unrecoverable Exception. +_handle_Unrecoverable_Exception: + rjmp $ + + ORG 0x004 + // TLB Multiple Hit: UNUSED IN AVR32UC. +_handle_TLB_Multiple_Hit: + rjmp $ + + ORG 0x008 + // Bus Error Data Fetch. +_handle_Bus_Error_Data_Fetch: + rjmp $ + + ORG 0x00C + // Bus Error Instruction Fetch. +_handle_Bus_Error_Instruction_Fetch: + rjmp $ + + ORG 0x010 + // NMI. +_handle_NMI: + rjmp $ + + ORG 0x014 + // Instruction Address. +_handle_Instruction_Address: + rjmp $ + + ORG 0x018 + // ITLB Protection. +_handle_ITLB_Protection: + rjmp $ + + ORG 0x01C + // Breakpoint. +_handle_Breakpoint: + rjmp $ + + ORG 0x020 + // Illegal Opcode. +_handle_Illegal_Opcode: + rjmp $ + + ORG 0x024 + // Unimplemented Instruction. +_handle_Unimplemented_Instruction: + rjmp $ + + ORG 0x028 + // Privilege Violation. +_handle_Privilege_Violation: + rjmp $ + + ORG 0x02C + // Floating-Point: UNUSED IN AVR32UC. +_handle_Floating_Point: + rjmp $ + + ORG 0x030 + // Coprocessor Absent: UNUSED IN AVR32UC. +_handle_Coprocessor_Absent: + rjmp $ + + ORG 0x034 + // Data Address (Read). +_handle_Data_Address_Read: + rjmp $ + + ORG 0x038 + // Data Address (Write). +_handle_Data_Address_Write: + rjmp $ + + ORG 0x03C + // DTLB Protection (Read). +_handle_DTLB_Protection_Read: + rjmp $ + + ORG 0x040 + // DTLB Protection (Write). +_handle_DTLB_Protection_Write: + rjmp $ + + ORG 0x044 + // DTLB Modified: UNUSED IN AVR32UC. +_handle_DTLB_Modified: + rjmp $ + + ORG 0x050 + // ITLB Miss: UNUSED IN AVR32UC. +_handle_ITLB_Miss: + rjmp $ + + ORG 0x060 + // DTLB Miss (Read): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Read: + rjmp $ + + ORG 0x070 + // DTLB Miss (Write): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Write: + rjmp $ + + ORG 0x100 + // Supervisor Call. +_handle_Supervisor_Call: + lddpc pc, __SCALLYield + + +// Interrupt support. +// The interrupt controller must provide the offset address relative to EVBA. +// Important note: +// All interrupts call a C function named _get_interrupt_handler. +// This function will read group and interrupt line number to then return in +// R12 a pointer to a user-provided interrupt handler. + + ALIGN 2 + +_int0: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int0_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int0_normal: +#endif + mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int1: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int1_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int1_normal: +#endif + mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int2: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int2_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int2_normal: +#endif + mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int3: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int3_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int3_normal: +#endif + mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + + +// Constant data area. + + ALIGN 2 + + // Import symbols. + EXTERN SCALLYield + EXTERN _get_interrupt_handler +__SCALLYield: + DC32 SCALLYield +__get_interrupt_handler: + DC32 _get_interrupt_handler + + // Values to store in the interrupt priority registers for the various interrupt priority levels. + // The interrupt priority registers contain the interrupt priority level and + // the EVBA-relative interrupt vector offset. + PUBLIC ipr_val +ipr_val: + DC32 (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\ + (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\ + (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\ + (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba) + + + END + + +//! \endverbatim +//! @} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/port.c new file mode 100644 index 0000000..80cfd9d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/port.c @@ -0,0 +1,435 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS port source for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + * https://www.microchip.com \n + * Support and FAQ: https://www.microchip.com/support/ + * + *****************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* AVR32 UC3 includes. */ +#include +#include +#include "gpio.h" + +#if configDBG + #include "usart.h" +#endif + +#if( configTICK_USE_TC==1 ) + #include "tc.h" +#endif + + +/* Constants required to setup the task context. */ +#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */ +#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 ) + +/* Each task maintains its own critical nesting variable. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +#if( configTICK_USE_TC==0 ) + static void prvScheduleNextTick( void ); +#else + static void prvClearTcInt( void ); +#endif + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ + +/* + * Low-level initialization routine called during startup, before the main + * function. + */ +int __low_level_init(void) +{ + #if configHEAP_INIT + #pragma segment = "HEAP" + BaseType_t *pxMem; + #endif + + /* Enable exceptions. */ + ENABLE_ALL_EXCEPTIONS(); + + /* Initialize interrupt handling. */ + INTC_init_interrupts(); + + #if configHEAP_INIT + { + /* Initialize the heap used by malloc. */ + for( pxMem = __segment_begin( "HEAP" ); pxMem < ( BaseType_t * ) __segment_end( "HEAP" ); ) + { + *pxMem++ = 0xA5A5A5A5; + } + } + #endif + + /* Code section present if and only if the debug trace is activated. */ + #if configDBG + { + static const gpio_map_t DBG_USART_GPIO_MAP = + { + { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION }, + { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION } + }; + + static const usart_options_t DBG_USART_OPTIONS = + { + .baudrate = configDBG_USART_BAUDRATE, + .charlength = 8, + .paritytype = USART_NO_PARITY, + .stopbits = USART_1_STOPBIT, + .channelmode = USART_NORMAL_CHMODE + }; + + /* Initialize the USART used for the debug trace with the configured parameters. */ + extern volatile avr32_usart_t *volatile stdio_usart_base; + stdio_usart_base = configDBG_USART; + gpio_enable_module( DBG_USART_GPIO_MAP, + sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) ); + usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ); + } + #endif + + /* Request initialization of data segments. */ + return 1; +} +/*-----------------------------------------------------------*/ + +/* Added as there is no such function in FreeRTOS. */ +void *pvPortRealloc( void *pv, size_t xWantedSize ) +{ +void *pvReturn; + + vTaskSuspendAll(); + { + pvReturn = realloc( pv, xWantedSize ); + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +/* The cooperative scheduler requires a normal IRQ service routine to +simply increment the system tick. */ +/* The preemptive scheduler is defined as "naked" as the full context is saved +on entry as part of the context switch. */ +#pragma shadow_registers = full // Naked. +static void vTick( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_OS_INT(); + + #if( configTICK_USE_TC==1 ) + /* Clear the interrupt flag. */ + prvClearTcInt(); + #else + /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) + clock cycles from now. */ + prvScheduleNextTick(); + #endif + + /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS + calls in a critical section . */ + portENTER_CRITICAL(); + xTaskIncrementTick(); + portEXIT_CRITICAL(); + + /* Restore the context of the "elected task". */ + portRESTORE_CONTEXT_OS_INT(); +} +/*-----------------------------------------------------------*/ + +#pragma shadow_registers = full // Naked. +void SCALLYield( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_SCALL(); + vTaskSwitchContext(); + portRESTORE_CONTEXT_SCALL(); +} +/*-----------------------------------------------------------*/ + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +#pragma optimize = no_inline +void vPortEnterCritical( void ) +{ + /* Disable interrupts */ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +#pragma optimize = no_inline +void vPortExitCritical( void ) +{ + if(ulCriticalNesting > portNO_CRITICAL_NESTING) + { + ulCriticalNesting--; + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable all interrupt/exception. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* When the task starts, it will expect to find the function parameter in R12. */ + pxTopOfStack--; + *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */ + *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */ + *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */ + *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */ + *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */ + *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */ + *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */ + *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + portRESTORE_CONTEXT(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR32 port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) +clock cycles from now. */ +#if( configTICK_USE_TC==0 ) + static void prvScheduleFirstTick(void) + { + uint32_t lCycles; + + lCycles = Get_system_register(AVR32_COUNT); + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception + // generation feature does not get disabled. + if(0 == lCycles) + { + lCycles++; + } + Set_system_register(AVR32_COMPARE, lCycles); + } + + #pragma optimize = no_inline + static void prvScheduleNextTick(void) + { + uint32_t lCycles, lCount; + + lCycles = Get_system_register(AVR32_COMPARE); + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception + // generation feature does not get disabled. + if(0 == lCycles) + { + lCycles++; + } + lCount = Get_system_register(AVR32_COUNT); + if( lCycles < lCount ) + { // We missed a tick, recover for the next. + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + } + Set_system_register(AVR32_COMPARE, lCycles); + } +#else + #pragma optimize = no_inline + static void prvClearTcInt(void) + { + AVR32_TC.channel[configTICK_TC_CHANNEL].sr; + } +#endif +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt(void) +{ + #if( configTICK_USE_TC==1 ) + + volatile avr32_tc_t *tc = &AVR32_TC; + + // Options for waveform genration. + tc_waveform_opt_t waveform_opt = + { + .channel = configTICK_TC_CHANNEL, /* Channel selection. */ + + .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */ + .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */ + .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */ + .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */ + + .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */ + .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */ + .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */ + .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */ + + .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */ + .enetrg = FALSE, /* External event trigger enable. */ + .eevt = 0, /* External event selection. */ + .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */ + .cpcdis = FALSE, /* Counter disable when RC compare. */ + .cpcstop = FALSE, /* Counter clock stopped with RC compare. */ + + .burst = FALSE, /* Burst signal selection. */ + .clki = FALSE, /* Clock inversion. */ + .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */ + }; + + tc_interrupt_t tc_interrupt = + { + .etrgs=0, + .ldrbs=0, + .ldras=0, + .cpcs =1, + .cpbs =0, + .cpas =0, + .lovrs=0, + .covfs=0, + }; + + #endif + + /* Disable all interrupt/exception. */ + portDISABLE_INTERRUPTS(); + + /* Register the compare interrupt handler to the interrupt controller and + enable the compare interrupt. */ + + #if( configTICK_USE_TC==1 ) + { + INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0); + + /* Initialize the timer/counter. */ + tc_init_waveform(tc, &waveform_opt); + + /* Set the compare triggers. + Remember TC counter is 16-bits, so counting second is not possible! + That's why we configure it to count ms. */ + tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ ); + + tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt ); + + /* Start the timer/counter. */ + tc_start(tc, configTICK_TC_CHANNEL); + } + #else + { + INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0); + prvScheduleFirstTick(); + } + #endif +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/portmacro.h new file mode 100644 index 0000000..52c3586 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/portmacro.h @@ -0,0 +1,684 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS port header for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + * https://www.microchip.com + * Support and FAQ: https://www.microchip.com/support + * + *****************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ +#include +#include "intc.h" +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS ) +#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS ) +#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS ) + +#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL) + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() {__asm__ __volatile__ ("nop");} +/*-----------------------------------------------------------*/ + + +/*-----------------------------------------------------------*/ + +/* INTC-specific. */ +#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception() +#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception() + +#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt() +#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt() + +#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev) +#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev) + + +/* + * Debug trace. + * Activated if and only if configDBG is nonzero. + * Prints a formatted string to stdout. + * The current source file name and line number are output with a colon before + * the formatted string. + * A carriage return and a linefeed are appended to the output. + * stdout is redirected to the USART configured by configDBG_USART. + * The parameters are the same as for the standard printf function. + * There is no return value. + * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc, + * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock. + */ +#if configDBG + #define portDBG_TRACE(...) \ + { \ + fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout); \ + printf(__VA_ARGS__); \ + fputs("\r\n", stdout); \ + } +#else + #define portDBG_TRACE(...) +#endif + + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS() +#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS() + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); + + +/* Added as there is no such function in FreeRTOS. */ +extern void *pvPortRealloc( void *pv, size_t xSize ); +/*-----------------------------------------------------------*/ + + +/*=============================================================================================*/ + +/* + * Restore Context for cases other than INTi. + */ +#define portRESTORE_CONTEXT() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + /* R0-R7 should not be used below this line */ \ + /* Skip PC and SR (will do it at the end) */ \ + "sub sp, -2*4 \n\t"\ + /* Restore R8..R12 and LR */ \ + "ldm sp++, r8-r12, lr \n\t"\ + /* Restore SR */ \ + "ld.w r0, sp[-8*4] \n\t" /* R0 is modified, is restored later. */\ + "mtsr "ASTRINGZ(AVR32_SR)", r0 \n\t"\ + /* Restore r0 */ \ + "ld.w r0, sp[-9*4] \n\t"\ + /* Restore PC */ \ + "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ +} + + +/* + * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions. + * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception. + * + * Had to make different versions because registers saved on the system stack + * are not the same between INT0..3 exceptions and the scall exception. + */ + +// Task context stack layout: + // R8 (*) + // R9 (*) + // R10 (*) + // R11 (*) + // R12 (*) + // R14/LR (*) + // R15/PC (*) + // SR (*) + // R0 + // R1 + // R2 + // R3 + // R4 + // R5 + // R6 + // R7 + // ulCriticalNesting +// (*) automatically done for INT0..INT3, but not for SCALL + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ +#define portSAVE_CONTEXT_OS_INT() \ +{ \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ("stm --sp, r0-r7"); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ +} + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ +#define portRESTORE_CONTEXT_OS_INT() \ +{ \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ +} + +#else + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ +#define portSAVE_CONTEXT_OS_INT() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0 \n\t"\ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + /* NOTE: we don't enter a critical section here because all interrupt handlers */ \ + /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \ + /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \ + /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp \n"\ + \ + "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \ + ); \ +} + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ +#define portRESTORE_CONTEXT_OS_INT() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + __asm__ __volatile__ ( \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__) \ + ); \ + \ + /* Else */ \ + /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + /* Restore all registers */ \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n"\ + \ + "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ +} + +#endif + + +/* + * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception. + * + * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode. + * + */ +#define portSAVE_CONTEXT_SCALL() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ + /* If SR[M2:M0] == 001 */ \ + /* PC and SR are on the stack. */ \ + /* Else (other modes) */ \ + /* Nothing on the stack. */ \ + \ + /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ + /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ + /* in an interrupt|exception handler. */ \ + \ + __asm__ __volatile__ ( \ + /* in order to save R0-R7 */ \ + "sub sp, 6*4 \n\t"\ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* in order to save R8-R12 and LR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp,-16*4 \n\t"\ + /* Copy PC and SR in other places in the stack. */ \ + "ld.w r0, r7[-2*4] \n\t" /* Read SR */\ + "st.w r7[-8*4], r0 \n\t" /* Copy SR */\ + "ld.w r0, r7[-1*4] \n\t" /* Read PC */\ + "st.w r7[-7*4], r0 \n\t" /* Copy PC */\ + \ + /* Save R8..R12 and LR on the stack. */ \ + "stm --r7, r8-r12, lr \n\t"\ + \ + /* Arriving here we have the following stack organizations: */ \ + /* R8..R12, LR, PC, SR, R0..R7. */ \ + \ + /* Now we can finalize the save. */ \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0" \ + ); \ + \ + /* Disable the its which may cause a context switch (i.e. cause a change of */ \ + /* pxCurrentTCB). */ \ + /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ + /* critical section because it is a global structure. */ \ + portENTER_CRITICAL(); \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + __asm__ __volatile__ ( \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp" \ + ); \ +} + +/* + * portRESTORE_CONTEXT() for SupervisorCALL exception. + */ +#define portRESTORE_CONTEXT_SCALL() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + __asm__ __volatile__ ( \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0]" \ + ); \ + \ + /* Leave pxCurrentTCB variable access critical section */ \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* skip PC and SR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp, -10*4 \n\t"\ + /* Restore r8-r12 and LR */ \ + "ldm r7++, r8-r12, lr \n\t"\ + \ + /* RETS will take care of the extra PC and SR restore. */ \ + /* So, we have to prepare the stack for this. */ \ + "ld.w r0, r7[-8*4] \n\t" /* Read SR */\ + "st.w r7[-2*4], r0 \n\t" /* Copy SR */\ + "ld.w r0, r7[-7*4] \n\t" /* Read PC */\ + "st.w r7[-1*4], r0 \n\t" /* Copy PC */\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + "sub sp, -6*4 \n\t"\ + \ + "rets" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ +} + + +/* + * The ISR used depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ +#define portENTER_SWITCHING_ISR() \ +{ \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ("stm --sp, r0-r7"); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ +} + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ +#define portEXIT_SWITCHING_ISR() \ +{ \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ +} + +#else + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ +#define portENTER_SWITCHING_ISR() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0 \n\t"\ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp \n"\ + \ + "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \ + ); \ +} + + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ +#define portEXIT_SWITCHING_ISR() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \ + /* did not previously save SP in its TCB. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\ + \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\ + "brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C" \ + ); \ + \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n"\ + \ + "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ +} + +#endif + + +#define portYIELD() {__asm__ __volatile__ ("scall");} + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/read.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/read.c new file mode 100644 index 0000000..a98822d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/read.c @@ -0,0 +1,123 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief System-specific implementation of the \ref __read function used by + the standard library. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + * https://www.microchip.com \n + * Support and FAQ: https://www.microchip.com/support/ + * + ******************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include "usart.h" + + +_STD_BEGIN + + +#pragma module_name = "?__read" + + +extern volatile avr32_usart_t *volatile stdio_usart_base; + + +/*! \brief Reads a number of bytes, at most \a size, into the memory area + * pointed to by \a buffer. + * + * \param handle File handle to read from. + * \param buffer Pointer to buffer to write read bytes to. + * \param size Number of bytes to read. + * + * \return The number of bytes read, \c 0 at the end of the file, or + * \c _LLIO_ERROR on failure. + */ +size_t __read(int handle, uint8_t *buffer, size_t size) +{ + int nChars = 0; + + // This implementation only reads from stdin. + // For all other file handles, it returns failure. + if (handle != _LLIO_STDIN) + { + return _LLIO_ERROR; + } + + for (; size > 0; --size) + { + int c = usart_getchar(stdio_usart_base); + if (c < 0) + break; + + *buffer++ = c; + ++nChars; + } + + return nChars; +} + + +_STD_END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/write.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/write.c new file mode 100644 index 0000000..2302f51 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR32_UC3/write.c @@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief System-specific implementation of the \ref __write function used by + the standard library. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + * https://www.microchip.com \n + * Support and FAQ: https://www.microchip.com/support + * + ******************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include "usart.h" + + +_STD_BEGIN + + +#pragma module_name = "?__write" + + +//! Pointer to the base of the USART module instance to use for stdio. +__no_init volatile avr32_usart_t *volatile stdio_usart_base; + + +/*! \brief Writes a number of bytes, at most \a size, from the memory area + * pointed to by \a buffer. + * + * If \a buffer is zero then \ref __write performs flushing of internal buffers, + * if any. In this case, \a handle can be \c -1 to indicate that all handles + * should be flushed. + * + * \param handle File handle to write to. + * \param buffer Pointer to buffer to read bytes to write from. + * \param size Number of bytes to write. + * + * \return The number of bytes written, or \c _LLIO_ERROR on failure. + */ +size_t __write(int handle, const uint8_t *buffer, size_t size) +{ + size_t nChars = 0; + + if (buffer == 0) + { + // This means that we should flush internal buffers. + return 0; + } + + // This implementation only writes to stdout and stderr. + // For all other file handles, it returns failure. + if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) + { + return _LLIO_ERROR; + } + + for (; size != 0; --size) + { + if (usart_putchar(stdio_usart_base, *buffer++) < 0) + { + return _LLIO_ERROR; + } + + ++nChars; + } + + return nChars; +} + + +_STD_END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_AVRDx/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_AVRDx/port.c new file mode 100644 index 0000000..f154614 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_AVRDx/port.c @@ -0,0 +1,301 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include "porthardware.h" +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the AVR port. +*----------------------------------------------------------*/ + +/* Start tasks with interrupts enables. */ +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) + +/*-----------------------------------------------------------*/ + + +#define portBYTES_USED_BY_RETURN_ADDRESS 2 +#define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 ) + +/* Stores the critical section nesting. This must not be initialised to 0. + * It will be initialised when a task starts. */ +UBaseType_t uxCriticalNesting = 0x50; + +/* + * Setup timer to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The IAR compiler does not have full support for inline assembler, so + * these are defined in the portmacro assembler file. + */ +extern void vPortYieldFromTick( void ); +extern void vPortStart( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint16_t usAddress; + StackType_t * pxTopOfHardwareStack; + + /* Simulate how the stack would look after a call to vPortYield(). */ + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* The IAR compiler requires two stacks per task. First there is the + * hardware call stack which uses the AVR stack pointer. Second there is the + * software stack (local variables, parameter passing, etc.) which uses the + * AVR Y register. + * This function places both stacks within the memory block passed in as the + * first parameter. The hardware stack is placed at the bottom of the memory + * block. A gap is then left for the hardware stack to grow. Next the software + * stack is placed. The amount of space between the software and hardware + * stacks is defined by configCALL_STACK_SIZE. + * The first part of the stack is the hardware stack. Place the start + * address of the task on the hardware stack. */ + + /* Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging. */ + /**pxTopOfStack = 0x11; */ + /*pxTopOfStack--; */ + /**pxTopOfStack = 0x22; */ + /*pxTopOfStack--; */ + /**pxTopOfStack = 0x33; */ + /*pxTopOfStack--; */ + + /* Remember where the top of the hardware stack is - this is required + * below. */ + pxTopOfHardwareStack = pxTopOfStack; + + usAddress = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* Leave enough space for the hardware stack before starting the software + * stack. The '- 2' is because we have already used two spaces for the + * address of the start of the task. */ + pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */ + pxTopOfStack--; + + /* Next place the address of the hardware stack. This is required so + * the AVR stack pointer can be restored to point to the hardware stack. */ + pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS; + usAddress = ( uint16_t ) pxTopOfHardwareStack; + + /* SPL */ + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* SPH */ + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* Now the remaining registers. */ + *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ + pxTopOfStack--; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ + pxTopOfStack--; + + /* The Y register is not stored as it is used as the software stack and + * gets saved into the task control block. */ + + *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ + + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. + * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR + * compiler does not fully support inline assembler we have to make a call.*/ + vPortStart(); + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* vPortEndScheduler is not implemented in this port. */ +} + +/*-----------------------------------------------------------*/ + +/* + * Setup timer to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ + TICK_init(); +} + +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + +/* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + + __task void TICK_INT( void ) + { + vPortYieldFromTick(); + asm ( "reti" ); + } +#else + +/* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + + __interrupt void TICK_INT( void ) + { + /* Clear tick interrupt flag. */ + INT_FLAGS = INT_MASK; + + xTaskIncrementTick(); + } +#endif /* if configUSE_PREEMPTION == 1 */ + +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} + +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + + if( uxCriticalNesting == portNO_CRITICAL_NESTING ) + { + portENABLE_INTERRUPTS(); + } +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_AVRDx/porthardware.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_AVRDx/porthardware.h new file mode 100644 index 0000000..3bd5f65 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_AVRDx/porthardware.h @@ -0,0 +1,129 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +#ifndef PORTHARDWARE_H +#define PORTHARDWARE_H + +#ifndef __IAR_SYSTEMS_ASM__ + #include +#endif +#include "FreeRTOSConfig.h" + +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMER_INSTANCE == 0 ) + + #define TICK_INT_vect TCB0_INT_vect + #define INT_FLAGS TCB0_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB0.INTCTRL = TCB_CAPT_bm; \ + TCB0.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 1 ) + + #define TICK_INT_vect TCB1_INT_vect + #define INT_FLAGS TCB1_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB1.INTCTRL = TCB_CAPT_bm; \ + TCB1.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 2 ) + + #define TICK_INT_vect TCB2_INT_vect + #define INT_FLAGS TCB2_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB2.INTCTRL = TCB_CAPT_bm; \ + TCB2.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 3 ) + + #define TICK_INT_vect TCB3_INT_vect + #define INT_FLAGS TCB3_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB3.INTCTRL = TCB_CAPT_bm; \ + TCB3.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 4 ) + + #define TICK_INT_vect TCB4_INT_vect + #define INT_FLAGS TCB4_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB4.INTCTRL = TCB_CAPT_bm; \ + TCB4.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 5 ) + + #define TICK_INT_vect RTC_CNT_vect + #define INT_FLAGS RTC_INTFLAGS + #define INT_MASK RTC_OVF_bm + +/* Hertz to period for RTC setup */ + #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) ) + #define TICK_init() \ + { \ + while( RTC.STATUS > 0 ) {; } \ + RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ + RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \ + RTC.INTCTRL |= 1 << RTC_OVF_bp; \ + } + +#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */ + #undef TICK_INT_vect + #undef INT_FLAGS + #undef INT_MASK + #undef TICK_init() + #error Invalid timer setting. +#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */ + +/*-----------------------------------------------------------*/ + +#endif /* PORTHARDWARE_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_AVRDx/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_AVRDx/portmacro.h new file mode 100644 index 0000000..53cdfae --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_AVRDx/portmacro.h @@ -0,0 +1,109 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +#define portPOINTER_SIZE_TYPE uint16_t + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif + +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#define portDISABLE_INTERRUPTS() asm ( "cli" ) +#define portENABLE_INTERRUPTS() asm ( "sei" ) +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm ( "nop" ) +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() + +extern void vPortYieldFromISR( void ); +#define portYIELD_FROM_ISR() vPortYieldFromISR() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_AVRDx/portmacro.s90 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_AVRDx/portmacro.s90 new file mode 100644 index 0000000..8863d9a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_AVRDx/portmacro.s90 @@ -0,0 +1,255 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +#include "porthardware.h" + +; Declare all extern symbols here - including any ISRs that are referenced in +; the vector table. + +; ISR functions +; ------------- +EXTERN TICK_INT + +; Functions used by scheduler +; --------------------------- +EXTERN vTaskSwitchContext +EXTERN pxCurrentTCB +EXTERN xTaskIncrementTick +EXTERN uxCriticalNesting + +; Functions implemented in this file +; ---------------------------------- +PUBLIC vPortYield +PUBLIC vPortYieldFromTick +PUBLIC vPortYieldFromISR +PUBLIC vPortStart + +; Interrupt vector table. +; ----------------------- +; +; For simplicity the RTOS tick interrupt routine uses the __task keyword. +; As the IAR compiler does not permit a function to be declared using both +; __task and __interrupt, the use of __task necessitates that the interrupt +; vector table be setup manually. +; +; To write an ISR, implement the ISR function using the __interrupt keyword +; but do not install the interrupt using the "#pragma vector=ABC" method. +; Instead manually place the name of the ISR in the vector table using an +; ORG and jmp instruction as demonstrated below. +; You will also have to add an EXTERN statement at the top of the file. + + ASEG + + ORG TICK_INT_vect ; Vector address + jmp TICK_INT ; ISR + + RSEG CODE + +CLR_INT MACRO FLAG_REG, FLAG_MASK + st -y, r16 + ldi r16, FLAG_MASK + sts FLAG_REG, r16 + ld r16, y+ + + ENDM + +; Saving and Restoring a Task Context and Task Switching +; ------------------------------------------------------ +; +; The IAR compiler does not fully support inline assembler, so saving and +; restoring a task context has to be written in an asm file. +; +; vPortYield() and vPortYieldFromTick() are usually written in C. Doing +; so in this case would required calls to be made to portSAVE_CONTEXT() and +; portRESTORE_CONTEXT(). This is dis-advantageous as the context switch +; function would require two extra jump and return instructions over the +; WinAVR equivalent. +; +; To avoid this I have opted to implement both vPortYield() and +; vPortYieldFromTick() in this assembly file. For convenience +; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros. + +portSAVE_CONTEXT MACRO + st -y, r0 ; First save the r0 register - we need to use this. + in r0, SREG ; Obtain the SREG value so we can disable interrupts... + cli ; ... as soon as possible. + st -y, r0 ; Store the SREG as it was before we disabled interrupts. + + in r0, RAMPZ + st -y, r0 + + in r0, SPL ; Next store the hardware stack pointer. The IAR... + st -y, r0 ; ... compiler uses the hardware stack as a call stack ... + in r0, SPH ; ... only. + st -y, r0 + + st -y, r1 ; Now store the rest of the registers. Dont store the ... + st -y, r2 ; ... the Y register here as it is used as the software + st -y, r3 ; stack pointer and will get saved into the TCB. + st -y, r4 + st -y, r5 + st -y, r6 + st -y, r7 + st -y, r8 + st -y, r9 + st -y, r10 + st -y, r11 + st -y, r12 + st -y, r13 + st -y, r14 + st -y, r15 + st -y, r16 + st -y, r17 + st -y, r18 + st -y, r19 + st -y, r20 + st -y, r21 + st -y, r22 + st -y, r23 + st -y, r24 + st -y, r25 + st -y, r26 + st -y, r27 + st -y, r30 + st -y, r31 + + lds r0, uxCriticalNesting + st -y, r0 ; Store the critical nesting counter. + + lds r26, pxCurrentTCB ; Finally save the software stack pointer (Y ... + lds r27, pxCurrentTCB + 1 ; ... register) into the TCB. + st x+, r28 + st x+, r29 + + ENDM + + +portRESTORE_CONTEXT MACRO + lds r26, pxCurrentTCB + lds r27, pxCurrentTCB + 1 ; Restore the software stack pointer from ... + ld r28, x+ ; the TCB into the software stack pointer (... + ld r29, x+ ; ... the Y register). + + ld r0, y+ + sts uxCriticalNesting, r0 + + ld r31, y+ ; Restore the registers down to R0. The Y + ld r30, y+ ; register is missing from this list as it + ld r27, y+ ; has already been restored. + ld r26, y+ + ld r25, y+ + ld r24, y+ + ld r23, y+ + ld r22, y+ + ld r21, y+ + ld r20, y+ + ld r19, y+ + ld r18, y+ + ld r17, y+ + ld r16, y+ + ld r15, y+ + ld r14, y+ + ld r13, y+ + ld r12, y+ + ld r11, y+ + ld r10, y+ + ld r9, y+ + ld r8, y+ + ld r7, y+ + ld r6, y+ + ld r5, y+ + ld r4, y+ + ld r3, y+ + ld r2, y+ + ld r1, y+ + + ld r0, y+ ; The next thing on the stack is the ... + out SPH, r0 ; ... hardware stack pointer. + ld r0, y+ + out SPL, r0 + + ld r0, y+ + out RAMPZ, r0 + + ld r0, y+ ; Next there is the SREG register. + out SREG, r0 + + ld r0, y+ ; Finally we have finished with r0, so restore r0. + + ENDM + + + +; vPortYield(), vPortYieldFromTick() and vPortYieldFromISR() +; ------------------------------------- +; +; Manual and preemptive context switch functions respectively. +; The IAR compiler does not fully support inline assembler, +; so these are implemented here rather than the more usually +; place of within port.c. + +vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +vPortYieldFromTick: + CLR_INT INT_FLAGS, INT_MASK ; Clear tick interrupt flag + + portSAVE_CONTEXT ; Save the context of the current task. + call xTaskIncrementTick ; Call the timer tick function. + tst r16 + breq SkipTaskSwitch + call vTaskSwitchContext ; Call the scheduler. + +SkipTaskSwitch: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + reti ; ... scheduler decided should run. + +vPortYieldFromISR: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + reti ; ... scheduler decided should run. + +; vPortStart() +; ------------ +; +; Again due to the lack of inline assembler, this is required +; to get access to the portRESTORE_CONTEXT macro. + +vPortStart: + portRESTORE_CONTEXT + ret + +; Just a filler for unused interrupt vectors. +vNoISR: + reti + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_Mega0/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_Mega0/port.c new file mode 100644 index 0000000..cd9cd15 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_Mega0/port.c @@ -0,0 +1,299 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include "porthardware.h" +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the AVR port. +*----------------------------------------------------------*/ + +/* Start tasks with interrupts enables. */ +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) + +/*-----------------------------------------------------------*/ + + +#define portBYTES_USED_BY_RETURN_ADDRESS 2 +#define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 ) + +/* Stores the critical section nesting. This must not be initialised to 0. + * It will be initialised when a task starts. */ +UBaseType_t uxCriticalNesting = 0x50; + +/* + * Setup timer to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The IAR compiler does not have full support for inline assembler, so + * these are defined in the portmacro assembler file. + */ +extern void vPortYieldFromTick( void ); +extern void vPortStart( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint16_t usAddress; + StackType_t * pxTopOfHardwareStack; + + /* Simulate how the stack would look after a call to vPortYield(). */ + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* The IAR compiler requires two stacks per task. First there is the + * hardware call stack which uses the AVR stack pointer. Second there is the + * software stack (local variables, parameter passing, etc.) which uses the + * AVR Y register. + * This function places both stacks within the memory block passed in as the + * first parameter. The hardware stack is placed at the bottom of the memory + * block. A gap is then left for the hardware stack to grow. Next the software + * stack is placed. The amount of space between the software and hardware + * stacks is defined by configCALL_STACK_SIZE. + * The first part of the stack is the hardware stack. Place the start + * address of the task on the hardware stack. */ + + /* Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging. */ + /**pxTopOfStack = 0x11; */ + /*pxTopOfStack--; */ + /**pxTopOfStack = 0x22; */ + /*pxTopOfStack--; */ + /**pxTopOfStack = 0x33; */ + /*pxTopOfStack--; */ + + /* Remember where the top of the hardware stack is - this is required + * below. */ + pxTopOfHardwareStack = pxTopOfStack; + + usAddress = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* Leave enough space for the hardware stack before starting the software + * stack. The '- 2' is because we have already used two spaces for the + * address of the start of the task. */ + pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next place the address of the hardware stack. This is required so + * the AVR stack pointer can be restored to point to the hardware stack. */ + pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS; + usAddress = ( uint16_t ) pxTopOfHardwareStack; + + /* SPL */ + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* SPH */ + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* Now the remaining registers. */ + *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ + pxTopOfStack--; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ + pxTopOfStack--; + + /* The Y register is not stored as it is used as the software stack and + * gets saved into the task control block. */ + + *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ + + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. + * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR + * compiler does not fully support inline assembler we have to make a call.*/ + vPortStart(); + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* vPortEndScheduler is not implemented in this port. */ +} + +/*-----------------------------------------------------------*/ + +/* + * Setup timer to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ + TICK_init(); +} + +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + +/* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + + __task void TICK_INT( void ) + { + vPortYieldFromTick(); + asm ( "reti" ); + } +#else + +/* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + + __interrupt void TICK_INT( void ) + { + /* Clear tick interrupt flag. */ + INT_FLAGS = INT_MASK; + + xTaskIncrementTick(); + } +#endif /* if configUSE_PREEMPTION == 1 */ + +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} + +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + + if( uxCriticalNesting == portNO_CRITICAL_NESTING ) + { + portENABLE_INTERRUPTS(); + } +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_Mega0/porthardware.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_Mega0/porthardware.h new file mode 100644 index 0000000..4f4cca4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_Mega0/porthardware.h @@ -0,0 +1,116 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +#ifndef PORTHARDWARE_H +#define PORTHARDWARE_H + +#ifndef __IAR_SYSTEMS_ASM__ + #include +#endif +#include "FreeRTOSConfig.h" + +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMER_INSTANCE == 0 ) + + #define TICK_INT_vect TCB0_INT_vect + #define INT_FLAGS TCB0_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB0.INTCTRL = TCB_CAPT_bm; \ + TCB0.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 1 ) + + #define TICK_INT_vect TCB1_INT_vect + #define INT_FLAGS TCB1_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB1.INTCTRL = TCB_CAPT_bm; \ + TCB1.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 2 ) + + #define TICK_INT_vect TCB2_INT_vect + #define INT_FLAGS TCB2_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB2.INTCTRL = TCB_CAPT_bm; \ + TCB2.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 3 ) + + #define TICK_INT_vect TCB3_INT_vect + #define INT_FLAGS TCB3_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB3.INTCTRL = TCB_CAPT_bm; \ + TCB3.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 4 ) + + #define TICK_INT_vect RTC_CNT_vect + #define INT_FLAGS RTC_INTFLAGS + #define INT_MASK RTC_OVF_bm + +/* Hertz to period for RTC setup */ + #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) ) + #define TICK_init() \ + { \ + while( RTC.STATUS > 0 ) {; } \ + RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ + RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \ + RTC.INTCTRL |= 1 << RTC_OVF_bp; \ + } + +#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */ + #undef TICK_INT_vect + #undef INT_FLAGS + #undef INT_MASK + #undef TICK_init() + #error Invalid timer setting. +#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */ + +/*-----------------------------------------------------------*/ + +#endif /* PORTHARDWARE_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_Mega0/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_Mega0/portmacro.h new file mode 100644 index 0000000..53cdfae --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_Mega0/portmacro.h @@ -0,0 +1,109 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +#define portPOINTER_SIZE_TYPE uint16_t + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif + +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#define portDISABLE_INTERRUPTS() asm ( "cli" ) +#define portENABLE_INTERRUPTS() asm ( "sei" ) +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm ( "nop" ) +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() + +extern void vPortYieldFromISR( void ); +#define portYIELD_FROM_ISR() vPortYieldFromISR() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_Mega0/portmacro.s90 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_Mega0/portmacro.s90 new file mode 100644 index 0000000..2db3d34 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AVR_Mega0/portmacro.s90 @@ -0,0 +1,249 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +#include "porthardware.h" + +; Declare all extern symbols here - including any ISRs that are referenced in +; the vector table. + +; ISR functions +; ------------- +EXTERN TICK_INT + +; Functions used by scheduler +; --------------------------- +EXTERN vTaskSwitchContext +EXTERN pxCurrentTCB +EXTERN xTaskIncrementTick +EXTERN uxCriticalNesting + +; Functions implemented in this file +; ---------------------------------- +PUBLIC vPortYield +PUBLIC vPortYieldFromTick +PUBLIC vPortYieldFromISR +PUBLIC vPortStart + +; Interrupt vector table. +; ----------------------- +; +; For simplicity the RTOS tick interrupt routine uses the __task keyword. +; As the IAR compiler does not permit a function to be declared using both +; __task and __interrupt, the use of __task necessitates that the interrupt +; vector table be setup manually. +; +; To write an ISR, implement the ISR function using the __interrupt keyword +; but do not install the interrupt using the "#pragma vector=ABC" method. +; Instead manually place the name of the ISR in the vector table using an +; ORG and jmp instruction as demonstrated below. +; You will also have to add an EXTERN statement at the top of the file. + + ASEG + + ORG TICK_INT_vect ; Vector address + jmp TICK_INT ; ISR + + RSEG CODE + +CLR_INT MACRO FLAG_REG, FLAG_MASK + st -y, r16 + ldi r16, FLAG_MASK + sts FLAG_REG, r16 + ld r16, y+ + + ENDM + +; Saving and Restoring a Task Context and Task Switching +; ------------------------------------------------------ +; +; The IAR compiler does not fully support inline assembler, so saving and +; restoring a task context has to be written in an asm file. +; +; vPortYield() and vPortYieldFromTick() are usually written in C. Doing +; so in this case would required calls to be made to portSAVE_CONTEXT() and +; portRESTORE_CONTEXT(). This is dis-advantageous as the context switch +; function would require two extra jump and return instructions over the +; WinAVR equivalent. +; +; To avoid this I have opted to implement both vPortYield() and +; vPortYieldFromTick() in this assembly file. For convenience +; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros. + +portSAVE_CONTEXT MACRO + st -y, r0 ; First save the r0 register - we need to use this. + in r0, SREG ; Obtain the SREG value so we can disable interrupts... + cli ; ... as soon as possible. + st -y, r0 ; Store the SREG as it was before we disabled interrupts. + + in r0, SPL ; Next store the hardware stack pointer. The IAR... + st -y, r0 ; ... compiler uses the hardware stack as a call stack ... + in r0, SPH ; ... only. + st -y, r0 + + st -y, r1 ; Now store the rest of the registers. Dont store the ... + st -y, r2 ; ... the Y register here as it is used as the software + st -y, r3 ; stack pointer and will get saved into the TCB. + st -y, r4 + st -y, r5 + st -y, r6 + st -y, r7 + st -y, r8 + st -y, r9 + st -y, r10 + st -y, r11 + st -y, r12 + st -y, r13 + st -y, r14 + st -y, r15 + st -y, r16 + st -y, r17 + st -y, r18 + st -y, r19 + st -y, r20 + st -y, r21 + st -y, r22 + st -y, r23 + st -y, r24 + st -y, r25 + st -y, r26 + st -y, r27 + st -y, r30 + st -y, r31 + + lds r0, uxCriticalNesting + st -y, r0 ; Store the critical nesting counter. + + lds r26, pxCurrentTCB ; Finally save the software stack pointer (Y ... + lds r27, pxCurrentTCB + 1 ; ... register) into the TCB. + st x+, r28 + st x+, r29 + + ENDM + + +portRESTORE_CONTEXT MACRO + lds r26, pxCurrentTCB + lds r27, pxCurrentTCB + 1 ; Restore the software stack pointer from ... + ld r28, x+ ; the TCB into the software stack pointer (... + ld r29, x+ ; ... the Y register). + + ld r0, y+ + sts uxCriticalNesting, r0 + + ld r31, y+ ; Restore the registers down to R0. The Y + ld r30, y+ ; register is missing from this list as it + ld r27, y+ ; has already been restored. + ld r26, y+ + ld r25, y+ + ld r24, y+ + ld r23, y+ + ld r22, y+ + ld r21, y+ + ld r20, y+ + ld r19, y+ + ld r18, y+ + ld r17, y+ + ld r16, y+ + ld r15, y+ + ld r14, y+ + ld r13, y+ + ld r12, y+ + ld r11, y+ + ld r10, y+ + ld r9, y+ + ld r8, y+ + ld r7, y+ + ld r6, y+ + ld r5, y+ + ld r4, y+ + ld r3, y+ + ld r2, y+ + ld r1, y+ + + ld r0, y+ ; The next thing on the stack is the ... + out SPH, r0 ; ... hardware stack pointer. + ld r0, y+ + out SPL, r0 + + ld r0, y+ ; Next there is the SREG register. + out SREG, r0 + + ld r0, y+ ; Finally we have finished with r0, so restore r0. + + ENDM + + + +; vPortYield(), vPortYieldFromTick() and vPortYieldFromISR() +; ------------------------------------- +; +; Manual and preemptive context switch functions respectively. +; The IAR compiler does not fully support inline assembler, +; so these are implemented here rather than the more usually +; place of within port.c. + +vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +vPortYieldFromTick: + CLR_INT INT_FLAGS, INT_MASK ; Clear tick interrupt flag + + portSAVE_CONTEXT ; Save the context of the current task. + call xTaskIncrementTick ; Call the timer tick function. + tst r16 + breq SkipTaskSwitch + call vTaskSwitchContext ; Call the scheduler. + +SkipTaskSwitch: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + reti ; ... scheduler decided should run. + +vPortYieldFromISR: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + reti ; ... scheduler decided should run. + +; vPortStart() +; ------------ +; +; Again due to the lack of inline assembler, this is required +; to get access to the portRESTORE_CONTEXT macro. + +vPortStart: + portRESTORE_CONTEXT + ret + +; Just a filler for unused interrupt vectors. +vNoISR: + reti + +END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h new file mode 100644 index 0000000..8f9ddb4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h @@ -0,0 +1,1914 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S64.h +// Object : AT91SAM7S64 definitions +// Generated : AT91 SW Application Group 07/16/2004 (07:43:08) +// +// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// +// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// +// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// +// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// +// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// +// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// +// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// +// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// +// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// +// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// +// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// +// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// +// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S64_H +#define AT91SAM7S64_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYSC { + AT91_REG SYSC_AIC_SMR[32]; // Source Mode Register + AT91_REG SYSC_AIC_SVR[32]; // Source Vector Register + AT91_REG SYSC_AIC_IVR; // IRQ Vector Register + AT91_REG SYSC_AIC_FVR; // FIQ Vector Register + AT91_REG SYSC_AIC_ISR; // Interrupt Status Register + AT91_REG SYSC_AIC_IPR; // Interrupt Pending Register + AT91_REG SYSC_AIC_IMR; // Interrupt Mask Register + AT91_REG SYSC_AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG SYSC_AIC_IECR; // Interrupt Enable Command Register + AT91_REG SYSC_AIC_IDCR; // Interrupt Disable Command Register + AT91_REG SYSC_AIC_ICCR; // Interrupt Clear Command Register + AT91_REG SYSC_AIC_ISCR; // Interrupt Set Command Register + AT91_REG SYSC_AIC_EOICR; // End of Interrupt Command Register + AT91_REG SYSC_AIC_SPU; // Spurious Vector Register + AT91_REG SYSC_AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG SYSC_AIC_FFER; // Fast Forcing Enable Register + AT91_REG SYSC_AIC_FFDR; // Fast Forcing Disable Register + AT91_REG SYSC_AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG SYSC_DBGU_CR; // Control Register + AT91_REG SYSC_DBGU_MR; // Mode Register + AT91_REG SYSC_DBGU_IER; // Interrupt Enable Register + AT91_REG SYSC_DBGU_IDR; // Interrupt Disable Register + AT91_REG SYSC_DBGU_IMR; // Interrupt Mask Register + AT91_REG SYSC_DBGU_CSR; // Channel Status Register + AT91_REG SYSC_DBGU_RHR; // Receiver Holding Register + AT91_REG SYSC_DBGU_THR; // Transmitter Holding Register + AT91_REG SYSC_DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG SYSC_DBGU_C1R; // Chip ID1 Register + AT91_REG SYSC_DBGU_C2R; // Chip ID2 Register + AT91_REG SYSC_DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG SYSC_DBGU_RPR; // Receive Pointer Register + AT91_REG SYSC_DBGU_RCR; // Receive Counter Register + AT91_REG SYSC_DBGU_TPR; // Transmit Pointer Register + AT91_REG SYSC_DBGU_TCR; // Transmit Counter Register + AT91_REG SYSC_DBGU_RNPR; // Receive Next Pointer Register + AT91_REG SYSC_DBGU_RNCR; // Receive Next Counter Register + AT91_REG SYSC_DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG SYSC_DBGU_TNCR; // Transmit Next Counter Register + AT91_REG SYSC_DBGU_PTCR; // PDC Transfer Control Register + AT91_REG SYSC_DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG SYSC_PIOA_PER; // PIO Enable Register + AT91_REG SYSC_PIOA_PDR; // PIO Disable Register + AT91_REG SYSC_PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG SYSC_PIOA_OER; // Output Enable Register + AT91_REG SYSC_PIOA_ODR; // Output Disable Registerr + AT91_REG SYSC_PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG SYSC_PIOA_IFER; // Input Filter Enable Register + AT91_REG SYSC_PIOA_IFDR; // Input Filter Disable Register + AT91_REG SYSC_PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG SYSC_PIOA_SODR; // Set Output Data Register + AT91_REG SYSC_PIOA_CODR; // Clear Output Data Register + AT91_REG SYSC_PIOA_ODSR; // Output Data Status Register + AT91_REG SYSC_PIOA_PDSR; // Pin Data Status Register + AT91_REG SYSC_PIOA_IER; // Interrupt Enable Register + AT91_REG SYSC_PIOA_IDR; // Interrupt Disable Register + AT91_REG SYSC_PIOA_IMR; // Interrupt Mask Register + AT91_REG SYSC_PIOA_ISR; // Interrupt Status Register + AT91_REG SYSC_PIOA_MDER; // Multi-driver Enable Register + AT91_REG SYSC_PIOA_MDDR; // Multi-driver Disable Register + AT91_REG SYSC_PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG SYSC_PIOA_PPUDR; // Pull-up Disable Register + AT91_REG SYSC_PIOA_PPUER; // Pull-up Enable Register + AT91_REG SYSC_PIOA_PPUSR; // Pad Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG SYSC_PIOA_ASR; // Select A Register + AT91_REG SYSC_PIOA_BSR; // Select B Register + AT91_REG SYSC_PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG SYSC_PIOA_OWER; // Output Write Enable Register + AT91_REG SYSC_PIOA_OWDR; // Output Write Disable Register + AT91_REG SYSC_PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG SYSC_PMC_SCER; // System Clock Enable Register + AT91_REG SYSC_PMC_SCDR; // System Clock Disable Register + AT91_REG SYSC_PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG SYSC_PMC_PCER; // Peripheral Clock Enable Register + AT91_REG SYSC_PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG SYSC_PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG SYSC_PMC_MOR; // Main Oscillator Register + AT91_REG SYSC_PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG SYSC_PMC_PLLR; // PLL Register + AT91_REG SYSC_PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG SYSC_PMC_PCKR[8]; // Programmable Clock Register + AT91_REG SYSC_PMC_IER; // Interrupt Enable Register + AT91_REG SYSC_PMC_IDR; // Interrupt Disable Register + AT91_REG SYSC_PMC_SR; // Status Register + AT91_REG SYSC_PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved17[36]; // + AT91_REG SYSC_RSTC_RCR; // Reset Control Register + AT91_REG SYSC_RSTC_RSR; // Reset Status Register + AT91_REG SYSC_RSTC_RMR; // Reset Mode Register + AT91_REG Reserved18[5]; // + AT91_REG SYSC_RTTC_RTMR; // Real-time Mode Register + AT91_REG SYSC_RTTC_RTAR; // Real-time Alarm Register + AT91_REG SYSC_RTTC_RTVR; // Real-time Value Register + AT91_REG SYSC_RTTC_RTSR; // Real-time Status Register + AT91_REG SYSC_PITC_PIMR; // Period Interval Mode Register + AT91_REG SYSC_PITC_PISR; // Period Interval Status Register + AT91_REG SYSC_PITC_PIVR; // Period Interval Value Register + AT91_REG SYSC_PITC_PIIR; // Period Interval Image Register + AT91_REG SYSC_WDTC_WDCR; // Watchdog Control Register + AT91_REG SYSC_WDTC_WDMR; // Watchdog Mode Register + AT91_REG SYSC_WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved19[5]; // + AT91_REG SYSC_SYSC_VRPM; // Voltage Regulator Power Mode Register +} AT91S_SYSC, *AT91PS_SYSC; + +// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- +#define AT91C_SYSC_PSTDBY ((unsigned int) 0x1 << 0) // (SYSC) Voltage Regulator Power Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_C1R; // Chip ID1 Register + AT91_REG DBGU_C2R; // Chip ID2 Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral Data Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pad Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[8]; // Programmable Clock Register + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_SYSC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_SYSC_ICERST ((unsigned int) 0x1 << 1) // (RSTC) ICE Interface Reset +#define AT91C_SYSC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_SYSC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_SYSC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_SYSC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_SYSC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brown-out Detection Status +#define AT91C_SYSC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_SYSC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_SYSC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_SYSC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_SYSC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_SYSC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brown-out Reset. +#define AT91C_SYSC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_SYSC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_SYSC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_SYSC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_SYSC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_SYSC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_SYSC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_SYSC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_SYSC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_SYSC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_SYSC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_SYSC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_SYSC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_SYSC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_SYSC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_SYSC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_SYSC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_SYSC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_SYSC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_SYSC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_SYSC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_SYSC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_SYSC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_SYSC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_SYSC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_SYSC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_SYSC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_SYSC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_SYSC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 2) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG SSC_RC0R; // Receive Compare 0 Register + AT91_REG SSC_RC1R; // Receive Compare 1 Register + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved2[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG US_XXR; // XON_XOFF Register + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved1[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG TWI_SMR; // Slave Mode Register + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved0[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled +#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read +#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access +#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0 +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4 +#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5 +#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6 +#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register + AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 +// ***************************************************************************** +// ========== Register definition for SYSC peripheral ========== +#define AT91C_SYSC_SYSC_VRPM ((AT91_REG *) 0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC) Receive Compare 0 Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC) Receive Compare 1 Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +#define AT91C_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +#define AT91C_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +#define AT91C_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved +#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved +#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved +#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved +#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved +#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_BASE_SYSC ((AT91PS_SYSC) 0xFFFFF000) // (SYSC) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte) + +#endif diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h new file mode 100644 index 0000000..7d2657a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h @@ -0,0 +1,1812 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S64.h +// Object : AT91SAM7S64 definitions +// Generated : AT91 SW Application Group 07/16/2004 (07:43:09) +// +// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// +// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// +// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// +// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// +// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// +// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// +// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// +// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// +// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// +// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// +// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// +// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// +// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +// *** Register offset in AT91S_SYSC structure *** +#define SYSC_AIC_SMR ( 0) // Source Mode Register +#define SYSC_AIC_SVR (128) // Source Vector Register +#define SYSC_AIC_IVR (256) // IRQ Vector Register +#define SYSC_AIC_FVR (260) // FIQ Vector Register +#define SYSC_AIC_ISR (264) // Interrupt Status Register +#define SYSC_AIC_IPR (268) // Interrupt Pending Register +#define SYSC_AIC_IMR (272) // Interrupt Mask Register +#define SYSC_AIC_CISR (276) // Core Interrupt Status Register +#define SYSC_AIC_IECR (288) // Interrupt Enable Command Register +#define SYSC_AIC_IDCR (292) // Interrupt Disable Command Register +#define SYSC_AIC_ICCR (296) // Interrupt Clear Command Register +#define SYSC_AIC_ISCR (300) // Interrupt Set Command Register +#define SYSC_AIC_EOICR (304) // End of Interrupt Command Register +#define SYSC_AIC_SPU (308) // Spurious Vector Register +#define SYSC_AIC_DCR (312) // Debug Control Register (Protect) +#define SYSC_AIC_FFER (320) // Fast Forcing Enable Register +#define SYSC_AIC_FFDR (324) // Fast Forcing Disable Register +#define SYSC_AIC_FFSR (328) // Fast Forcing Status Register +#define SYSC_DBGU_CR (512) // Control Register +#define SYSC_DBGU_MR (516) // Mode Register +#define SYSC_DBGU_IER (520) // Interrupt Enable Register +#define SYSC_DBGU_IDR (524) // Interrupt Disable Register +#define SYSC_DBGU_IMR (528) // Interrupt Mask Register +#define SYSC_DBGU_CSR (532) // Channel Status Register +#define SYSC_DBGU_RHR (536) // Receiver Holding Register +#define SYSC_DBGU_THR (540) // Transmitter Holding Register +#define SYSC_DBGU_BRGR (544) // Baud Rate Generator Register +#define SYSC_DBGU_C1R (576) // Chip ID1 Register +#define SYSC_DBGU_C2R (580) // Chip ID2 Register +#define SYSC_DBGU_FNTR (584) // Force NTRST Register +#define SYSC_DBGU_RPR (768) // Receive Pointer Register +#define SYSC_DBGU_RCR (772) // Receive Counter Register +#define SYSC_DBGU_TPR (776) // Transmit Pointer Register +#define SYSC_DBGU_TCR (780) // Transmit Counter Register +#define SYSC_DBGU_RNPR (784) // Receive Next Pointer Register +#define SYSC_DBGU_RNCR (788) // Receive Next Counter Register +#define SYSC_DBGU_TNPR (792) // Transmit Next Pointer Register +#define SYSC_DBGU_TNCR (796) // Transmit Next Counter Register +#define SYSC_DBGU_PTCR (800) // PDC Transfer Control Register +#define SYSC_DBGU_PTSR (804) // PDC Transfer Status Register +#define SYSC_PIOA_PER (1024) // PIO Enable Register +#define SYSC_PIOA_PDR (1028) // PIO Disable Register +#define SYSC_PIOA_PSR (1032) // PIO Status Register +#define SYSC_PIOA_OER (1040) // Output Enable Register +#define SYSC_PIOA_ODR (1044) // Output Disable Registerr +#define SYSC_PIOA_OSR (1048) // Output Status Register +#define SYSC_PIOA_IFER (1056) // Input Filter Enable Register +#define SYSC_PIOA_IFDR (1060) // Input Filter Disable Register +#define SYSC_PIOA_IFSR (1064) // Input Filter Status Register +#define SYSC_PIOA_SODR (1072) // Set Output Data Register +#define SYSC_PIOA_CODR (1076) // Clear Output Data Register +#define SYSC_PIOA_ODSR (1080) // Output Data Status Register +#define SYSC_PIOA_PDSR (1084) // Pin Data Status Register +#define SYSC_PIOA_IER (1088) // Interrupt Enable Register +#define SYSC_PIOA_IDR (1092) // Interrupt Disable Register +#define SYSC_PIOA_IMR (1096) // Interrupt Mask Register +#define SYSC_PIOA_ISR (1100) // Interrupt Status Register +#define SYSC_PIOA_MDER (1104) // Multi-driver Enable Register +#define SYSC_PIOA_MDDR (1108) // Multi-driver Disable Register +#define SYSC_PIOA_MDSR (1112) // Multi-driver Status Register +#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register +#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register +#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register +#define SYSC_PIOA_ASR (1136) // Select A Register +#define SYSC_PIOA_BSR (1140) // Select B Register +#define SYSC_PIOA_ABSR (1144) // AB Select Status Register +#define SYSC_PIOA_OWER (1184) // Output Write Enable Register +#define SYSC_PIOA_OWDR (1188) // Output Write Disable Register +#define SYSC_PIOA_OWSR (1192) // Output Write Status Register +#define SYSC_PMC_SCER (3072) // System Clock Enable Register +#define SYSC_PMC_SCDR (3076) // System Clock Disable Register +#define SYSC_PMC_SCSR (3080) // System Clock Status Register +#define SYSC_PMC_PCER (3088) // Peripheral Clock Enable Register +#define SYSC_PMC_PCDR (3092) // Peripheral Clock Disable Register +#define SYSC_PMC_PCSR (3096) // Peripheral Clock Status Register +#define SYSC_PMC_MOR (3104) // Main Oscillator Register +#define SYSC_PMC_MCFR (3108) // Main Clock Frequency Register +#define SYSC_PMC_PLLR (3116) // PLL Register +#define SYSC_PMC_MCKR (3120) // Master Clock Register +#define SYSC_PMC_PCKR (3136) // Programmable Clock Register +#define SYSC_PMC_IER (3168) // Interrupt Enable Register +#define SYSC_PMC_IDR (3172) // Interrupt Disable Register +#define SYSC_PMC_SR (3176) // Status Register +#define SYSC_PMC_IMR (3180) // Interrupt Mask Register +#define SYSC_RSTC_RCR (3328) // Reset Control Register +#define SYSC_RSTC_RSR (3332) // Reset Status Register +#define SYSC_RSTC_RMR (3336) // Reset Mode Register +#define SYSC_RTTC_RTMR (3360) // Real-time Mode Register +#define SYSC_RTTC_RTAR (3364) // Real-time Alarm Register +#define SYSC_RTTC_RTVR (3368) // Real-time Value Register +#define SYSC_RTTC_RTSR (3372) // Real-time Status Register +#define SYSC_PITC_PIMR (3376) // Period Interval Mode Register +#define SYSC_PITC_PISR (3380) // Period Interval Status Register +#define SYSC_PITC_PIVR (3384) // Period Interval Value Register +#define SYSC_PITC_PIIR (3388) // Period Interval Image Register +#define SYSC_WDTC_WDCR (3392) // Watchdog Control Register +#define SYSC_WDTC_WDMR (3396) // Watchdog Mode Register +#define SYSC_WDTC_WDSR (3400) // Watchdog Status Register +#define SYSC_SYSC_VRPM (3424) // Voltage Regulator Power Mode Register +// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- +#define AT91C_SYSC_PSTDBY (0x1 << 0) // (SYSC) Voltage Regulator Power Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_C1R (64) // Chip ID1 Register +#define DBGU_C2R (68) // Chip ID2 Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral Data Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pad Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLR (12) // PLL Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MOR (32) // Main Oscillator Register +#define PMC_MCFR (36) // Main Clock Frequency Register +#define PMC_PLLR (44) // PLL Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RSTC structure *** +#define RSTC_RCR ( 0) // Reset Control Register +#define RSTC_RSR ( 4) // Reset Status Register +#define RSTC_RMR ( 8) // Reset Mode Register +// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_SYSC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_SYSC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset +#define AT91C_SYSC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_SYSC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_SYSC_KEY (0xFF << 24) // (RSTC) Password +// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_SYSC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_SYSC_BODSTS (0x1 << 1) // (RSTC) Brown-out Detection Status +#define AT91C_SYSC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_SYSC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_SYSC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_SYSC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_SYSC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_SYSC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brown-out Reset. +#define AT91C_SYSC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_SYSC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_SYSC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_SYSC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_SYSC_ERSTL (0xF << 8) // (RSTC) User Reset Enable +#define AT91C_SYSC_BODIEN (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTTC structure *** +#define RTTC_RTMR ( 0) // Real-time Mode Register +#define RTTC_RTAR ( 4) // Real-time Alarm Register +#define RTTC_RTVR ( 8) // Real-time Value Register +#define RTTC_RTSR (12) // Real-time Status Register +// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_SYSC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_SYSC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_SYSC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_SYSC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_SYSC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_SYSC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_SYSC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_SYSC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PITC structure *** +#define PITC_PIMR ( 0) // Period Interval Mode Register +#define PITC_PISR ( 4) // Period Interval Status Register +#define PITC_PIVR ( 8) // Period Interval Value Register +#define PITC_PIIR (12) // Period Interval Image Register +// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_SYSC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_SYSC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_SYSC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_SYSC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_SYSC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_SYSC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_WDTC structure *** +#define WDTC_WDCR ( 0) // Watchdog Control Register +#define WDTC_WDMR ( 4) // Watchdog Mode Register +#define WDTC_WDSR ( 8) // Watchdog Status Register +// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_SYSC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_SYSC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_SYSC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_SYSC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_SYSC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_SYSC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_SYSC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_SYSC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_SYSC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_FMR (96) // MC Flash Mode Register +#define MC_FCR (100) // MC Flash Command Register +#define MC_FSR (104) // MC Flash Status Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 2) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +// *** Register offset in AT91S_ADC structure *** +#define ADC_CR ( 0) // ADC Control Register +#define ADC_MR ( 4) // ADC Mode Register +#define ADC_CHER (16) // ADC Channel Enable Register +#define ADC_CHDR (20) // ADC Channel Disable Register +#define ADC_CHSR (24) // ADC Channel Status Register +#define ADC_SR (28) // ADC Status Register +#define ADC_LCDR (32) // ADC Last Converted Data Register +#define ADC_IER (36) // ADC Interrupt Enable Register +#define ADC_IDR (40) // ADC Interrupt Disable Register +#define ADC_IMR (44) // ADC Interrupt Mask Register +#define ADC_CDR0 (48) // ADC Channel Data Register 0 +#define ADC_CDR1 (52) // ADC Channel Data Register 1 +#define ADC_CDR2 (56) // ADC Channel Data Register 2 +#define ADC_CDR3 (60) // ADC Channel Data Register 3 +#define ADC_CDR4 (64) // ADC Channel Data Register 4 +#define ADC_CDR5 (68) // ADC Channel Data Register 5 +#define ADC_CDR6 (72) // ADC Channel Data Register 6 +#define ADC_CDR7 (76) // ADC Channel Data Register 7 +#define ADC_RPR (256) // Receive Pointer Register +#define ADC_RCR (260) // Receive Counter Register +#define ADC_TPR (264) // Transmit Pointer Register +#define ADC_TCR (268) // Transmit Counter Register +#define ADC_RNPR (272) // Receive Next Pointer Register +#define ADC_RNCR (276) // Receive Next Counter Register +#define ADC_TNPR (280) // Transmit Next Pointer Register +#define ADC_TNCR (284) // Transmit Next Counter Register +#define ADC_PTCR (288) // PDC Transfer Control Register +#define ADC_PTSR (292) // PDC Transfer Status Register +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_RC0R (56) // Receive Compare 0 Register +#define SSC_RC1R (60) // Receive Compare 1 Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_XXR (72) // XON_XOFF Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_SMR ( 8) // Slave Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled +#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read +#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access +#define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_NONE (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_RISING (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_FALLING (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_BOTH (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRCS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x1 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x1 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA2 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC_CH structure *** +#define PWMC_CMR ( 0) // Channel Mode Register +#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register +#define PWMC_CPRDR ( 8) // Channel Period Register +#define PWMC_CCNTR (12) // Channel Counter Register +#define PWMC_CUPDR (16) // Channel Update Register +#define PWMC_Reserved (20) // Reserved +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC structure *** +#define PWMC_MR ( 0) // PWMC Mode Register +#define PWMC_ENA ( 4) // PWMC Enable Register +#define PWMC_DIS ( 8) // PWMC Disable Register +#define PWMC_SR (12) // PWMC Status Register +#define PWMC_IER (16) // PWMC Interrupt Enable Register +#define PWMC_IDR (20) // PWMC Interrupt Disable Register +#define PWMC_IMR (24) // PWMC Interrupt Mask Register +#define PWMC_ISR (28) // PWMC Interrupt Status Register +#define PWMC_VR (252) // PWMC Version Register +#define PWMC_CH (512) // PWMC Channel 0 +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4 +#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5 +#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6 +#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 +// ***************************************************************************** +// ========== Register definition for SYSC peripheral ========== +#define AT91C_SYSC_SYSC_VRPM (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_C1R (0xFFFFF240) // (DBGU) Chip ID1 Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pad Pull-up Status Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register +#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register +#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register +#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register +#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register +#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register +#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_RC0R (0xFFFD4038) // (SSC) Receive Compare 0 Register +#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_RC1R (0xFFFD403C) // (SSC) Receive Compare 1 Register +#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_XXR (0xFFFC0048) // (US0) XON_XOFF Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_SMR (0xFFFB8008) // (TWI) Slave Mode Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register +#define AT91C_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register +#define AT91C_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +#define AT91C_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register +#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ( 3) // Reserved +#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_15_Reserved (15) // Reserved +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_BASE_SYSC (0xFFFFF000) // (SYSC) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte) +#define AT91C_IFLASH (0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE (0x00010000) // Internal ROM size in byte (64 Kbyte) + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h new file mode 100644 index 0000000..ae4f35f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h @@ -0,0 +1,2715 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X128.h +// Object : AT91SAM7X128 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:23) +// +// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X128_H +#define AT91SAM7X128_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte) + +#endif diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h new file mode 100644 index 0000000..96b680a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h @@ -0,0 +1,2446 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X128.h +// Object : AT91SAM7X128 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:23) +// +// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_CIDR (64) // Chip ID Register +#define DBGU_EXID (68) // Chip ID Extension Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLR (12) // PLL Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MOR (32) // Main Oscillator Register +#define PMC_MCFR (36) // Main Clock Frequency Register +#define PMC_PLLR (44) // PLL Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RSTC structure *** +#define RSTC_RCR ( 0) // Reset Control Register +#define RSTC_RSR ( 4) // Reset Status Register +#define RSTC_RMR ( 8) // Reset Mode Register +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTTC structure *** +#define RTTC_RTMR ( 0) // Real-time Mode Register +#define RTTC_RTAR ( 4) // Real-time Alarm Register +#define RTTC_RTVR ( 8) // Real-time Value Register +#define RTTC_RTSR (12) // Real-time Status Register +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PITC structure *** +#define PITC_PIMR ( 0) // Period Interval Mode Register +#define PITC_PISR ( 4) // Period Interval Status Register +#define PITC_PIVR ( 8) // Period Interval Value Register +#define PITC_PIIR (12) // Period Interval Image Register +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_WDTC structure *** +#define WDTC_WDCR ( 0) // Watchdog Control Register +#define WDTC_WDMR ( 4) // Watchdog Mode Register +#define WDTC_WDSR ( 8) // Watchdog Status Register +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_VREG structure *** +#define VREG_MR ( 0) // Voltage Regulator Mode Register +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_FMR (96) // MC Flash Mode Register +#define MC_FCR (100) // MC Flash Command Register +#define MC_FSR (104) // MC Flash Status Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC_CH structure *** +#define PWMC_CMR ( 0) // Channel Mode Register +#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register +#define PWMC_CPRDR ( 8) // Channel Period Register +#define PWMC_CCNTR (12) // Channel Counter Register +#define PWMC_CUPDR (16) // Channel Update Register +#define PWMC_Reserved (20) // Reserved +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC structure *** +#define PWMC_MR ( 0) // PWMC Mode Register +#define PWMC_ENA ( 4) // PWMC Enable Register +#define PWMC_DIS ( 8) // PWMC Disable Register +#define PWMC_SR (12) // PWMC Status Register +#define PWMC_IER (16) // PWMC Interrupt Enable Register +#define PWMC_IDR (20) // PWMC Interrupt Disable Register +#define PWMC_IMR (24) // PWMC Interrupt Mask Register +#define PWMC_ISR (28) // PWMC Interrupt Status Register +#define PWMC_VR (252) // PWMC Version Register +#define PWMC_CH (512) // PWMC Channel +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +#define UDP_TXVC (116) // Transceiver Control Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN_MB structure *** +#define CAN_MB_MMR ( 0) // MailBox Mode Register +#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register +#define CAN_MB_MID ( 8) // MailBox ID Register +#define CAN_MB_MFID (12) // MailBox Family ID Register +#define CAN_MB_MSR (16) // MailBox Status Register +#define CAN_MB_MDL (20) // MailBox Data Low Register +#define CAN_MB_MDH (24) // MailBox Data High Register +#define CAN_MB_MCR (28) // MailBox Control Register +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN structure *** +#define CAN_MR ( 0) // Mode Register +#define CAN_IER ( 4) // Interrupt Enable Register +#define CAN_IDR ( 8) // Interrupt Disable Register +#define CAN_IMR (12) // Interrupt Mask Register +#define CAN_SR (16) // Status Register +#define CAN_BR (20) // Baudrate Register +#define CAN_TIM (24) // Timer Register +#define CAN_TIMESTP (28) // Time Stamp Register +#define CAN_ECR (32) // Error Counter Register +#define CAN_TCR (36) // Transfer Command Register +#define CAN_ACR (40) // Abort Command Register +#define CAN_VR (252) // Version Register +#define CAN_MB0 (512) // CAN Mailbox 0 +#define CAN_MB1 (544) // CAN Mailbox 1 +#define CAN_MB2 (576) // CAN Mailbox 2 +#define CAN_MB3 (608) // CAN Mailbox 3 +#define CAN_MB4 (640) // CAN Mailbox 4 +#define CAN_MB5 (672) // CAN Mailbox 5 +#define CAN_MB6 (704) // CAN Mailbox 6 +#define CAN_MB7 (736) // CAN Mailbox 7 +#define CAN_MB8 (768) // CAN Mailbox 8 +#define CAN_MB9 (800) // CAN Mailbox 9 +#define CAN_MB10 (832) // CAN Mailbox 10 +#define CAN_MB11 (864) // CAN Mailbox 11 +#define CAN_MB12 (896) // CAN Mailbox 12 +#define CAN_MB13 (928) // CAN Mailbox 13 +#define CAN_MB14 (960) // CAN Mailbox 14 +#define CAN_MB15 (992) // CAN Mailbox 15 +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +// *** Register offset in AT91S_EMAC structure *** +#define EMAC_NCR ( 0) // Network Control Register +#define EMAC_NCFGR ( 4) // Network Configuration Register +#define EMAC_NSR ( 8) // Network Status Register +#define EMAC_TSR (20) // Transmit Status Register +#define EMAC_RBQP (24) // Receive Buffer Queue Pointer +#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer +#define EMAC_RSR (32) // Receive Status Register +#define EMAC_ISR (36) // Interrupt Status Register +#define EMAC_IER (40) // Interrupt Enable Register +#define EMAC_IDR (44) // Interrupt Disable Register +#define EMAC_IMR (48) // Interrupt Mask Register +#define EMAC_MAN (52) // PHY Maintenance Register +#define EMAC_PTR (56) // Pause Time Register +#define EMAC_PFR (60) // Pause Frames received Register +#define EMAC_FTO (64) // Frames Transmitted OK Register +#define EMAC_SCF (68) // Single Collision Frame Register +#define EMAC_MCF (72) // Multiple Collision Frame Register +#define EMAC_FRO (76) // Frames Received OK Register +#define EMAC_FCSE (80) // Frame Check Sequence Error Register +#define EMAC_ALE (84) // Alignment Error Register +#define EMAC_DTF (88) // Deferred Transmission Frame Register +#define EMAC_LCOL (92) // Late Collision Register +#define EMAC_ECOL (96) // Excessive Collision Register +#define EMAC_TUND (100) // Transmit Underrun Error Register +#define EMAC_CSE (104) // Carrier Sense Error Register +#define EMAC_RRE (108) // Receive Ressource Error Register +#define EMAC_ROV (112) // Receive Overrun Errors Register +#define EMAC_RSE (116) // Receive Symbol Errors Register +#define EMAC_ELE (120) // Excessive Length Errors Register +#define EMAC_RJA (124) // Receive Jabbers Register +#define EMAC_USF (128) // Undersize Frames Register +#define EMAC_STE (132) // SQE Test Error Register +#define EMAC_RLE (136) // Receive Length Field Mismatch Register +#define EMAC_TPF (140) // Transmitted Pause Frames Register +#define EMAC_HRB (144) // Hash Address Bottom[31:0] +#define EMAC_HRT (148) // Hash Address Top[63:32] +#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (184) // Type ID Checking Register +#define EMAC_TPQ (188) // Transmit Pause Quantum Register +#define EMAC_USRIO (192) // USER Input/Output Register +#define EMAC_WOL (196) // Wake On LAN Register +#define EMAC_REV (252) // Revision Register +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +// *** Register offset in AT91S_ADC structure *** +#define ADC_CR ( 0) // ADC Control Register +#define ADC_MR ( 4) // ADC Mode Register +#define ADC_CHER (16) // ADC Channel Enable Register +#define ADC_CHDR (20) // ADC Channel Disable Register +#define ADC_CHSR (24) // ADC Channel Status Register +#define ADC_SR (28) // ADC Status Register +#define ADC_LCDR (32) // ADC Last Converted Data Register +#define ADC_IER (36) // ADC Interrupt Enable Register +#define ADC_IDR (40) // ADC Interrupt Disable Register +#define ADC_IMR (44) // ADC Interrupt Mask Register +#define ADC_CDR0 (48) // ADC Channel Data Register 0 +#define ADC_CDR1 (52) // ADC Channel Data Register 1 +#define ADC_CDR2 (56) // ADC Channel Data Register 2 +#define ADC_CDR3 (60) // ADC Channel Data Register 3 +#define ADC_CDR4 (64) // ADC Channel Data Register 4 +#define ADC_CDR5 (68) // ADC Channel Data Register 5 +#define ADC_CDR6 (72) // ADC Channel Data Register 6 +#define ADC_CDR7 (76) // ADC Channel Data Register 7 +#define ADC_RPR (256) // Receive Pointer Register +#define ADC_RCR (260) // Receive Counter Register +#define ADC_TPR (264) // Transmit Pointer Register +#define ADC_TCR (268) // Transmit Counter Register +#define ADC_RNPR (272) // Receive Next Pointer Register +#define ADC_RNCR (276) // Receive Next Counter Register +#define ADC_TNPR (280) // Transmit Next Pointer Register +#define ADC_TNCR (284) // Transmit Next Counter Register +#define ADC_PTCR (288) // PDC Transfer Control Register +#define ADC_PTSR (292) // PDC Transfer Status Register +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_AES structure *** +#define AES_CR ( 0) // Control Register +#define AES_MR ( 4) // Mode Register +#define AES_IER (16) // Interrupt Enable Register +#define AES_IDR (20) // Interrupt Disable Register +#define AES_IMR (24) // Interrupt Mask Register +#define AES_ISR (28) // Interrupt Status Register +#define AES_KEYWxR (32) // Key Word x Register +#define AES_IDATAxR (64) // Input Data x Register +#define AES_ODATAxR (80) // Output Data x Register +#define AES_IVxR (96) // Initialization Vector x Register +#define AES_VR (252) // AES Version Register +#define AES_RPR (256) // Receive Pointer Register +#define AES_RCR (260) // Receive Counter Register +#define AES_TPR (264) // Transmit Pointer Register +#define AES_TCR (268) // Transmit Counter Register +#define AES_RNPR (272) // Receive Next Pointer Register +#define AES_RNCR (276) // Receive Next Counter Register +#define AES_TNPR (280) // Transmit Next Pointer Register +#define AES_TNCR (284) // Transmit Next Counter Register +#define AES_PTCR (288) // PDC Transfer Control Register +#define AES_PTSR (292) // PDC Transfer Status Register +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_TDES structure *** +#define TDES_CR ( 0) // Control Register +#define TDES_MR ( 4) // Mode Register +#define TDES_IER (16) // Interrupt Enable Register +#define TDES_IDR (20) // Interrupt Disable Register +#define TDES_IMR (24) // Interrupt Mask Register +#define TDES_ISR (28) // Interrupt Status Register +#define TDES_KEY1WxR (32) // Key 1 Word x Register +#define TDES_KEY2WxR (40) // Key 2 Word x Register +#define TDES_KEY3WxR (48) // Key 3 Word x Register +#define TDES_IDATAxR (64) // Input Data x Register +#define TDES_ODATAxR (80) // Output Data x Register +#define TDES_IVxR (96) // Initialization Vector x Register +#define TDES_VR (252) // TDES Version Register +#define TDES_RPR (256) // Receive Pointer Register +#define TDES_RCR (260) // Receive Counter Register +#define TDES_TPR (264) // Transmit Pointer Register +#define TDES_TCR (268) // Transmit Counter Register +#define TDES_RNPR (272) // Receive Next Pointer Register +#define TDES_RNCR (276) // Receive Next Counter Register +#define TDES_TNPR (280) // Transmit Next Pointer Register +#define TDES_TNCR (284) // Transmit Next Counter Register +#define TDES_PTCR (288) // PDC Transfer Control Register +#define TDES_PTSR (292) // PDC Transfer Status Register +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES (19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbyte) +#define AT91C_IFLASH (0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE (0x00020000) // Internal ROM size in byte (128 Kbyte) + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h new file mode 100644 index 0000000..6b73f8a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h @@ -0,0 +1,2715 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// +// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) + +#endif diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h new file mode 100644 index 0000000..5b8dfe8 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h @@ -0,0 +1,2446 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// +// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_CIDR (64) // Chip ID Register +#define DBGU_EXID (68) // Chip ID Extension Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLR (12) // PLL Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MOR (32) // Main Oscillator Register +#define PMC_MCFR (36) // Main Clock Frequency Register +#define PMC_PLLR (44) // PLL Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RSTC structure *** +#define RSTC_RCR ( 0) // Reset Control Register +#define RSTC_RSR ( 4) // Reset Status Register +#define RSTC_RMR ( 8) // Reset Mode Register +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTTC structure *** +#define RTTC_RTMR ( 0) // Real-time Mode Register +#define RTTC_RTAR ( 4) // Real-time Alarm Register +#define RTTC_RTVR ( 8) // Real-time Value Register +#define RTTC_RTSR (12) // Real-time Status Register +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PITC structure *** +#define PITC_PIMR ( 0) // Period Interval Mode Register +#define PITC_PISR ( 4) // Period Interval Status Register +#define PITC_PIVR ( 8) // Period Interval Value Register +#define PITC_PIIR (12) // Period Interval Image Register +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_WDTC structure *** +#define WDTC_WDCR ( 0) // Watchdog Control Register +#define WDTC_WDMR ( 4) // Watchdog Mode Register +#define WDTC_WDSR ( 8) // Watchdog Status Register +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_VREG structure *** +#define VREG_MR ( 0) // Voltage Regulator Mode Register +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_FMR (96) // MC Flash Mode Register +#define MC_FCR (100) // MC Flash Command Register +#define MC_FSR (104) // MC Flash Status Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC_CH structure *** +#define PWMC_CMR ( 0) // Channel Mode Register +#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register +#define PWMC_CPRDR ( 8) // Channel Period Register +#define PWMC_CCNTR (12) // Channel Counter Register +#define PWMC_CUPDR (16) // Channel Update Register +#define PWMC_Reserved (20) // Reserved +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC structure *** +#define PWMC_MR ( 0) // PWMC Mode Register +#define PWMC_ENA ( 4) // PWMC Enable Register +#define PWMC_DIS ( 8) // PWMC Disable Register +#define PWMC_SR (12) // PWMC Status Register +#define PWMC_IER (16) // PWMC Interrupt Enable Register +#define PWMC_IDR (20) // PWMC Interrupt Disable Register +#define PWMC_IMR (24) // PWMC Interrupt Mask Register +#define PWMC_ISR (28) // PWMC Interrupt Status Register +#define PWMC_VR (252) // PWMC Version Register +#define PWMC_CH (512) // PWMC Channel +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +#define UDP_TXVC (116) // Transceiver Control Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN_MB structure *** +#define CAN_MB_MMR ( 0) // MailBox Mode Register +#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register +#define CAN_MB_MID ( 8) // MailBox ID Register +#define CAN_MB_MFID (12) // MailBox Family ID Register +#define CAN_MB_MSR (16) // MailBox Status Register +#define CAN_MB_MDL (20) // MailBox Data Low Register +#define CAN_MB_MDH (24) // MailBox Data High Register +#define CAN_MB_MCR (28) // MailBox Control Register +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN structure *** +#define CAN_MR ( 0) // Mode Register +#define CAN_IER ( 4) // Interrupt Enable Register +#define CAN_IDR ( 8) // Interrupt Disable Register +#define CAN_IMR (12) // Interrupt Mask Register +#define CAN_SR (16) // Status Register +#define CAN_BR (20) // Baudrate Register +#define CAN_TIM (24) // Timer Register +#define CAN_TIMESTP (28) // Time Stamp Register +#define CAN_ECR (32) // Error Counter Register +#define CAN_TCR (36) // Transfer Command Register +#define CAN_ACR (40) // Abort Command Register +#define CAN_VR (252) // Version Register +#define CAN_MB0 (512) // CAN Mailbox 0 +#define CAN_MB1 (544) // CAN Mailbox 1 +#define CAN_MB2 (576) // CAN Mailbox 2 +#define CAN_MB3 (608) // CAN Mailbox 3 +#define CAN_MB4 (640) // CAN Mailbox 4 +#define CAN_MB5 (672) // CAN Mailbox 5 +#define CAN_MB6 (704) // CAN Mailbox 6 +#define CAN_MB7 (736) // CAN Mailbox 7 +#define CAN_MB8 (768) // CAN Mailbox 8 +#define CAN_MB9 (800) // CAN Mailbox 9 +#define CAN_MB10 (832) // CAN Mailbox 10 +#define CAN_MB11 (864) // CAN Mailbox 11 +#define CAN_MB12 (896) // CAN Mailbox 12 +#define CAN_MB13 (928) // CAN Mailbox 13 +#define CAN_MB14 (960) // CAN Mailbox 14 +#define CAN_MB15 (992) // CAN Mailbox 15 +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +// *** Register offset in AT91S_EMAC structure *** +#define EMAC_NCR ( 0) // Network Control Register +#define EMAC_NCFGR ( 4) // Network Configuration Register +#define EMAC_NSR ( 8) // Network Status Register +#define EMAC_TSR (20) // Transmit Status Register +#define EMAC_RBQP (24) // Receive Buffer Queue Pointer +#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer +#define EMAC_RSR (32) // Receive Status Register +#define EMAC_ISR (36) // Interrupt Status Register +#define EMAC_IER (40) // Interrupt Enable Register +#define EMAC_IDR (44) // Interrupt Disable Register +#define EMAC_IMR (48) // Interrupt Mask Register +#define EMAC_MAN (52) // PHY Maintenance Register +#define EMAC_PTR (56) // Pause Time Register +#define EMAC_PFR (60) // Pause Frames received Register +#define EMAC_FTO (64) // Frames Transmitted OK Register +#define EMAC_SCF (68) // Single Collision Frame Register +#define EMAC_MCF (72) // Multiple Collision Frame Register +#define EMAC_FRO (76) // Frames Received OK Register +#define EMAC_FCSE (80) // Frame Check Sequence Error Register +#define EMAC_ALE (84) // Alignment Error Register +#define EMAC_DTF (88) // Deferred Transmission Frame Register +#define EMAC_LCOL (92) // Late Collision Register +#define EMAC_ECOL (96) // Excessive Collision Register +#define EMAC_TUND (100) // Transmit Underrun Error Register +#define EMAC_CSE (104) // Carrier Sense Error Register +#define EMAC_RRE (108) // Receive Ressource Error Register +#define EMAC_ROV (112) // Receive Overrun Errors Register +#define EMAC_RSE (116) // Receive Symbol Errors Register +#define EMAC_ELE (120) // Excessive Length Errors Register +#define EMAC_RJA (124) // Receive Jabbers Register +#define EMAC_USF (128) // Undersize Frames Register +#define EMAC_STE (132) // SQE Test Error Register +#define EMAC_RLE (136) // Receive Length Field Mismatch Register +#define EMAC_TPF (140) // Transmitted Pause Frames Register +#define EMAC_HRB (144) // Hash Address Bottom[31:0] +#define EMAC_HRT (148) // Hash Address Top[63:32] +#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (184) // Type ID Checking Register +#define EMAC_TPQ (188) // Transmit Pause Quantum Register +#define EMAC_USRIO (192) // USER Input/Output Register +#define EMAC_WOL (196) // Wake On LAN Register +#define EMAC_REV (252) // Revision Register +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +// *** Register offset in AT91S_ADC structure *** +#define ADC_CR ( 0) // ADC Control Register +#define ADC_MR ( 4) // ADC Mode Register +#define ADC_CHER (16) // ADC Channel Enable Register +#define ADC_CHDR (20) // ADC Channel Disable Register +#define ADC_CHSR (24) // ADC Channel Status Register +#define ADC_SR (28) // ADC Status Register +#define ADC_LCDR (32) // ADC Last Converted Data Register +#define ADC_IER (36) // ADC Interrupt Enable Register +#define ADC_IDR (40) // ADC Interrupt Disable Register +#define ADC_IMR (44) // ADC Interrupt Mask Register +#define ADC_CDR0 (48) // ADC Channel Data Register 0 +#define ADC_CDR1 (52) // ADC Channel Data Register 1 +#define ADC_CDR2 (56) // ADC Channel Data Register 2 +#define ADC_CDR3 (60) // ADC Channel Data Register 3 +#define ADC_CDR4 (64) // ADC Channel Data Register 4 +#define ADC_CDR5 (68) // ADC Channel Data Register 5 +#define ADC_CDR6 (72) // ADC Channel Data Register 6 +#define ADC_CDR7 (76) // ADC Channel Data Register 7 +#define ADC_RPR (256) // Receive Pointer Register +#define ADC_RCR (260) // Receive Counter Register +#define ADC_TPR (264) // Transmit Pointer Register +#define ADC_TCR (268) // Transmit Counter Register +#define ADC_RNPR (272) // Receive Next Pointer Register +#define ADC_RNCR (276) // Receive Next Counter Register +#define ADC_TNPR (280) // Transmit Next Pointer Register +#define ADC_TNCR (284) // Transmit Next Counter Register +#define ADC_PTCR (288) // PDC Transfer Control Register +#define ADC_PTSR (292) // PDC Transfer Status Register +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_AES structure *** +#define AES_CR ( 0) // Control Register +#define AES_MR ( 4) // Mode Register +#define AES_IER (16) // Interrupt Enable Register +#define AES_IDR (20) // Interrupt Disable Register +#define AES_IMR (24) // Interrupt Mask Register +#define AES_ISR (28) // Interrupt Status Register +#define AES_KEYWxR (32) // Key Word x Register +#define AES_IDATAxR (64) // Input Data x Register +#define AES_ODATAxR (80) // Output Data x Register +#define AES_IVxR (96) // Initialization Vector x Register +#define AES_VR (252) // AES Version Register +#define AES_RPR (256) // Receive Pointer Register +#define AES_RCR (260) // Receive Counter Register +#define AES_TPR (264) // Transmit Pointer Register +#define AES_TCR (268) // Transmit Counter Register +#define AES_RNPR (272) // Receive Next Pointer Register +#define AES_RNCR (276) // Receive Next Counter Register +#define AES_TNPR (280) // Transmit Next Pointer Register +#define AES_TNCR (284) // Transmit Next Counter Register +#define AES_PTCR (288) // PDC Transfer Control Register +#define AES_PTSR (292) // PDC Transfer Status Register +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_TDES structure *** +#define TDES_CR ( 0) // Control Register +#define TDES_MR ( 4) // Mode Register +#define TDES_IER (16) // Interrupt Enable Register +#define TDES_IDR (20) // Interrupt Disable Register +#define TDES_IMR (24) // Interrupt Mask Register +#define TDES_ISR (28) // Interrupt Status Register +#define TDES_KEY1WxR (32) // Key 1 Word x Register +#define TDES_KEY2WxR (40) // Key 2 Word x Register +#define TDES_KEY3WxR (48) // Key 3 Word x Register +#define TDES_IDATAxR (64) // Input Data x Register +#define TDES_ODATAxR (80) // Output Data x Register +#define TDES_IVxR (96) // Initialization Vector x Register +#define TDES_VR (252) // TDES Version Register +#define TDES_RPR (256) // Receive Pointer Register +#define TDES_RCR (260) // Receive Counter Register +#define TDES_TPR (264) // Transmit Pointer Register +#define TDES_TCR (268) // Transmit Counter Register +#define TDES_RNPR (272) // Receive Next Pointer Register +#define TDES_RNCR (276) // Receive Next Counter Register +#define TDES_TNPR (280) // Transmit Next Pointer Register +#define TDES_TNCR (284) // Transmit Next Counter Register +#define TDES_PTCR (288) // PDC Transfer Control Register +#define TDES_PTSR (292) // PDC Transfer Status Register +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES (19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH (0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE (0x00040000) // Internal ROM size in byte (256 Kbyte) + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/ISR_Support.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/ISR_Support.h new file mode 100644 index 0000000..b48841a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/ISR_Support.h @@ -0,0 +1,106 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h new file mode 100644 index 0000000..9d012c4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h @@ -0,0 +1,3265 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7S64.h +//* Object : AT91SAM7S64 inlined functions +//* Generated : AT91 SW Application Group 07/16/2004 (07:43:09) +//* +//* CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003// +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// +//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002// +//*---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7S64_H +#define lib_AT91SAM7S64_H + +/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg endpoints to be enabled +{ + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg endpoints to be enabled +{ + pUDP->UDP_GLBSTATE &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA10_DTXD ) | + ((unsigned int) AT91C_PA9_DRXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA14_PWM3 ) | + ((unsigned int) AT91C_PA7_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PA25_PWM2 ) | + ((unsigned int) AT91C_PA13_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PA24_PWM1 ) | + ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PA23_PWM0 ) | + ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA17_TD ) | + ((unsigned int) AT91C_PA15_TF ) | + ((unsigned int) AT91C_PA19_RK ) | + ((unsigned int) AT91C_PA18_RD ) | + ((unsigned int) AT91C_PA20_RF ) | + ((unsigned int) AT91C_PA16_TK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPIO +//* \brief Configure PIO controllers to drive SPI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_NPCS0 ) | + ((unsigned int) AT91C_PA13_MOSI ) | + ((unsigned int) AT91C_PA31_NPCS1 ) | + ((unsigned int) AT91C_PA12_MISO ) | + ((unsigned int) AT91C_PA14_SPCK ), // Peripheral A + ((unsigned int) AT91C_PA9_NPCS1 ) | + ((unsigned int) AT91C_PA30_NPCS2 ) | + ((unsigned int) AT91C_PA10_NPCS2 ) | + ((unsigned int) AT91C_PA22_NPCS3 ) | + ((unsigned int) AT91C_PA3_NPCS3 ) | + ((unsigned int) AT91C_PA5_NPCS3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA26_TIOA2 ) | + ((unsigned int) AT91C_PA27_TIOB2 ) | + ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TIOA1 ) | + ((unsigned int) AT91C_PA16_TIOB1 ) | + ((unsigned int) AT91C_PA28_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA0_TIOA0 ) | + ((unsigned int) AT91C_PA1_TIOB0 ) | + ((unsigned int) AT91C_PA4_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA17_PCK1 ) | + ((unsigned int) AT91C_PA21_PCK1 ) | + ((unsigned int) AT91C_PA31_PCK2 ) | + ((unsigned int) AT91C_PA18_PCK2 ) | + ((unsigned int) AT91C_PA6_PCK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA3_TWD ) | + ((unsigned int) AT91C_PA4_TWCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA21_RXD1 ) | + ((unsigned int) AT91C_PA27_DTR1 ) | + ((unsigned int) AT91C_PA26_DCD1 ) | + ((unsigned int) AT91C_PA22_TXD1 ) | + ((unsigned int) AT91C_PA24_RTS1 ) | + ((unsigned int) AT91C_PA23_SCK1 ) | + ((unsigned int) AT91C_PA28_DSR1 ) | + ((unsigned int) AT91C_PA29_RI1 ) | + ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA5_RXD0 ) | + ((unsigned int) AT91C_PA6_TXD0 ) | + ((unsigned int) AT91C_PA7_RTS0 ) | + ((unsigned int) AT91C_PA8_CTS0 ), // Peripheral A + ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A + ((unsigned int) AT91C_PA20_IRQ0 ) | + ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B +} + +#endif // lib_AT91SAM7S64_H diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h new file mode 100644 index 0000000..805a2bc --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h @@ -0,0 +1,4558 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X128.h +//* Object : AT91SAM7X128 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:23) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7X128_H +#define lib_AT91SAM7X128_H + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR RSTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSoftReset +//* \brief Start Software Reset +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSoftReset( + AT91PS_RSTC pRSTC, + unsigned int reset) +{ + pRSTC->RSTC_RCR = (0xA5000000 | reset); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSetMode +//* \brief Set Reset Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSetMode( + AT91PS_RSTC pRSTC, + unsigned int mode) +{ + pRSTC->RSTC_RMR = (0xA5000000 | mode); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetMode +//* \brief Get Reset Mode +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetMode( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetStatus +//* \brief Get Reset Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetStatus( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RSR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTIsSoftRstActive +//* \brief Return !=0 if software reset is still not completed +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTIsSoftRstActive( + AT91PS_RSTC pRSTC) +{ + return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); +} +/* ***************************************************************************** + SOFTWARE API FOR RTTC + ***************************************************************************** */ +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_SetRTT_TimeBase() +//* \brief Set the RTT prescaler according to the TimeBase in ms +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetTimeBase( + AT91PS_RTTC pRTTC, + unsigned int ms) +{ + if (ms > 2000) + return 1; // AT91C_TIME_OUT_OF_RANGE + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); + return 0; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTSetPrescaler() +//* \brief Set the new prescaler value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetPrescaler( + AT91PS_RTTC pRTTC, + unsigned int rtpres) +{ + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); + return (pRTTC->RTTC_RTMR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTRestart() +//* \brief Restart the RTT prescaler +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTRestart( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; +} + + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmINT() +//* \brief Enable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearAlarmINT() +//* \brief Disable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetRttIncINT() +//* \brief Enable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearRttIncINT() +//* \brief Disable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmValue() +//* \brief Set RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmValue( + AT91PS_RTTC pRTTC, unsigned int alarm) +{ + pRTTC->RTTC_RTAR = alarm; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_GetAlarmValue() +//* \brief Get RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetAlarmValue( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTAR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTGetStatus() +//* \brief Read the RTT status +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetStatus( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTSR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ReadValue() +//* \brief Read the RTT value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTReadValue( + AT91PS_RTTC pRTTC) +{ + register volatile unsigned int val1,val2; + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while(val1 != val2); + return(val1); +} +/* ***************************************************************************** + SOFTWARE API FOR PITC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITInit +//* \brief System timer init : period in �second, system clock freq in MHz +//*---------------------------------------------------------------------------- +__inline void AT91F_PITInit( + AT91PS_PITC pPITC, + unsigned int period, + unsigned int pit_frequency) +{ + pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 + pPITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITSetPIV +//* \brief Set the PIT Periodic Interval Value +//*---------------------------------------------------------------------------- +__inline void AT91F_PITSetPIV( + AT91PS_PITC pPITC, + unsigned int piv) +{ + pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITEnableInt +//* \brief Enable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITEnableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITDisableInt +//* \brief Disable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITDisableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetMode +//* \brief Read PIT mode register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetMode( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetStatus +//* \brief Read PIT status register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetStatus( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PISR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIIR +//* \brief Read PIT CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIIR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIIR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIVR +//* \brief Read System timer CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIVR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIVR); +} +/* ***************************************************************************** + SOFTWARE API FOR WDTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSetMode +//* \brief Set Watchdog Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTSetMode( + AT91PS_WDTC pWDTC, + unsigned int Mode) +{ + pWDTC->WDTC_WDMR = Mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTRestart +//* \brief Restart Watchdog +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTRestart( + AT91PS_WDTC pWDTC) +{ + pWDTC->WDTC_WDCR = 0xA5000001; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSGettatus +//* \brief Get Watchdog Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTSGettatus( + AT91PS_WDTC pWDTC) +{ + return(pWDTC->WDTC_WDSR & 0x3); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTGetPeriod +//* \brief Translate ms into Watchdog Compatible value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) +{ + if ((ms < 4) || (ms > 16000)) + return 0; + return((ms << 8) / 1000); +} +/* ***************************************************************************** + SOFTWARE API FOR VREG + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Enable_LowPowerMode +//* \brief Enable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Enable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR |= AT91C_VREG_PSTDBY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Disable_LowPowerMode +//* \brief Disable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Disable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; +}/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; + pUDP->UDP_RSTEP = 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR CAN + ***************************************************************************** */ +#define STANDARD_FORMAT 0 +#define EXTENDED_FORMAT 1 + +//*---------------------------------------------------------------------------- +//* \fn AT91F_InitMailboxRegisters() +//* \brief Configure the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, + int mode_reg, + int acceptance_mask_reg, + int id_reg, + int data_low_reg, + int data_high_reg, + int control_reg) +{ + CAN_Mailbox->CAN_MB_MCR = 0x0; + CAN_Mailbox->CAN_MB_MMR = mode_reg; + CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; + CAN_Mailbox->CAN_MB_MID = id_reg; + CAN_Mailbox->CAN_MB_MDL = data_low_reg; + CAN_Mailbox->CAN_MB_MDH = data_high_reg; + CAN_Mailbox->CAN_MB_MCR = control_reg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EnableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_EnableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR |= AT91C_CAN_CANEN; + + // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver + while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DisableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_DisableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR &= ~AT91C_CAN_CANEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_EnableIt +//* \brief Enable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_EnableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pCAN->CAN_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_DisableIt +//* \brief Disable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_DisableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pCAN->CAN_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetStatus +//* \brief Return CAN Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInterruptMaskStatus +//* \brief Return CAN Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsInterruptMasked +//* \brief Test if CAN Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsInterruptMasked( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsStatusSet +//* \brief Test if CAN Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsStatusSet( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgModeReg +//* \brief Configure the Mode Register of the CAN controller +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgModeReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pCAN->CAN_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetModeReg +//* \brief Return the Mode Register of the CAN controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetModeReg ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgBaudrateReg +//* \brief Configure the Baudrate of the CAN controller for the network +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgBaudrateReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int baudrate_cfg) +{ + //* Write to the BR register + pCAN->CAN_BR = baudrate_cfg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetBaudrate +//* \brief Return the Baudrate of the CAN controller for the network value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetBaudrate ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_BR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInternalCounter +//* \brief Return CAN Timer Regsiter Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInternalCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetTimestamp +//* \brief Return CAN Timestamp Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetTimestamp ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIMESTP; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetErrorCounter +//* \brief Return CAN Error Counter Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetErrorCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_ECR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitTransferRequest +//* \brief Request for a transfer on the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitTransferRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int transfer_cmd) +{ + pCAN->CAN_TCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitAbortRequest +//* \brief Abort the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitAbortRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int abort_cmd) +{ + pCAN->CAN_ACR = abort_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageModeReg +//* \brief Program the Message Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mode) +{ + CAN_Mailbox->CAN_MB_MMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageModeReg +//* \brief Return the Message Mode Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageIDReg +//* \brief Program the Message ID Register +//* \brief Version == 0 for Standard messsage, Version == 1 for Extended +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int id, + unsigned char version) +{ + if(version==0) // IDvA Standard Format + CAN_Mailbox->CAN_MB_MID = id<<18; + else // IDvB Extended Format + CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageIDReg +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg +//* \brief Program the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mask) +{ + CAN_Mailbox->CAN_MB_MAM = mask; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg +//* \brief Return the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MAM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetFamilyID +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetFamilyID ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MFID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageCtrl +//* \brief Request and config for a transfer on the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageCtrlReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int message_ctrl_cmd) +{ + CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageStatus +//* \brief Return CAN Mailbox Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageStatus ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataLow +//* \brief Program data low value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDL = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataLow +//* \brief Return data low value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataHigh +//* \brief Program data high value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDH = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataHigh +//* \brief Return data high value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDH; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_Open +//* \brief Open a CAN Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} +/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR AES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_EnableIt +//* \brief Enable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_EnableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pAES->AES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_DisableIt +//* \brief Disable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_DisableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pAES->AES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetStatus +//* \brief Return AES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetInterruptMaskStatus +//* \brief Return AES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsInterruptMasked +//* \brief Test if AES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsInterruptMasked( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsStatusSet +//* \brief Test if AES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsStatusSet( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgModeReg +//* \brief Configure the Mode Register of the AES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgModeReg ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pAES->AES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetModeReg +//* \brief Return the Mode Register of the AES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetModeReg ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + return pAES->AES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_StartProcessing ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SoftReset +//* \brief Reset AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SoftReset ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_LoadNewSeed +//* \brief Load New Seed in the random number generator +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_LoadNewSeed ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_LOADSEED; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetCryptoKey +//* \brief Set Cryptographic Key x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetCryptoKey ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int keyword + ) +{ + pAES->AES_KEYWxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_InputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int indata + ) +{ + pAES->AES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetOutputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index + ) +{ + return pAES->AES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetInitializationVector +//* \brief Set Initialization Vector (or Counter) x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetInitializationVector ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int initvector + ) +{ + pAES->AES_IVxR[index] = initvector; +} + +/* ***************************************************************************** + SOFTWARE API FOR TDES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_EnableIt +//* \brief Enable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_EnableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pTDES->TDES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_DisableIt +//* \brief Disable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_DisableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pTDES->TDES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetStatus +//* \brief Return TDES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetInterruptMaskStatus +//* \brief Return TDES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsInterruptMasked +//* \brief Test if TDES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsInterruptMasked( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsStatusSet +//* \brief Test if TDES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsStatusSet( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgModeReg +//* \brief Configure the Mode Register of the TDES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgModeReg ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pTDES->TDES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetModeReg +//* \brief Return the Mode Register of the TDES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetModeReg ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + return pTDES->TDES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_StartProcessing ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SoftReset +//* \brief Reset TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SoftReset ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey1 +//* \brief Set Cryptographic Key 1 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey1 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY1WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey2 +//* \brief Set Cryptographic Key 2 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey2 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY2WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey3 +//* \brief Set Cryptographic Key 3 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey3 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY3WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_InputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int indata + ) +{ + pTDES->TDES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetOutputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index + ) +{ + return pTDES->TDES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetInitializationVector +//* \brief Set Initialization Vector x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetInitializationVector ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int initvector + ) +{ + pTDES->TDES_IVxR[index] = initvector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA27_DRXD ) | + ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB30_PCK2 ) | + ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A + ((unsigned int) AT91C_PB20_PCK0 ) | + ((unsigned int) AT91C_PB0_PCK0 ) | + ((unsigned int) AT91C_PB22_PCK2 ) | + ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA30_PCK2 ) | + ((unsigned int) AT91C_PA13_PCK1 ) | + ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_CfgPMC +//* \brief Enable Peripheral clock in PMC for VREG +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RSTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA25_RK ) | + ((unsigned int) AT91C_PA22_TK ) | + ((unsigned int) AT91C_PA21_TF ) | + ((unsigned int) AT91C_PA24_RD ) | + ((unsigned int) AT91C_PA26_RF ) | + ((unsigned int) AT91C_PA23_TD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for WDTC +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB26_RI1 ) | + ((unsigned int) AT91C_PB24_DSR1 ) | + ((unsigned int) AT91C_PB23_DCD1 ) | + ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA7_SCK1 ) | + ((unsigned int) AT91C_PA8_RTS1 ) | + ((unsigned int) AT91C_PA6_TXD1 ) | + ((unsigned int) AT91C_PA5_RXD1 ) | + ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_RXD0 ) | + ((unsigned int) AT91C_PA4_CTS0 ) | + ((unsigned int) AT91C_PA3_RTS0 ) | + ((unsigned int) AT91C_PA2_SCK0 ) | + ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI1 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPIO +//* \brief Configure PIO controllers to drive SPI1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB16_NPCS13 ) | + ((unsigned int) AT91C_PB10_NPCS11 ) | + ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA4_NPCS13 ) | + ((unsigned int) AT91C_PA29_NPCS13 ) | + ((unsigned int) AT91C_PA21_NPCS10 ) | + ((unsigned int) AT91C_PA22_SPCK1 ) | + ((unsigned int) AT91C_PA25_NPCS11 ) | + ((unsigned int) AT91C_PA2_NPCS11 ) | + ((unsigned int) AT91C_PA24_MISO1 ) | + ((unsigned int) AT91C_PA3_NPCS12 ) | + ((unsigned int) AT91C_PA26_NPCS12 ) | + ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI0 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPIO +//* \brief Configure PIO controllers to drive SPI0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB13_NPCS01 ) | + ((unsigned int) AT91C_PB17_NPCS03 ) | + ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA16_MISO0 ) | + ((unsigned int) AT91C_PA13_NPCS01 ) | + ((unsigned int) AT91C_PA15_NPCS03 ) | + ((unsigned int) AT91C_PA17_MOSI0 ) | + ((unsigned int) AT91C_PA18_SPCK0 ) | + ((unsigned int) AT91C_PA14_NPCS02 ) | + ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A + ((unsigned int) AT91C_PA7_NPCS01 ) | + ((unsigned int) AT91C_PA9_NPCS03 ) | + ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PITC +//*---------------------------------------------------------------------------- +__inline void AT91F_PITC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ0 ) | + ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A + ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgPMC +//* \brief Enable Peripheral clock in PMC for AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_AES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_TWCK ) | + ((unsigned int) AT91C_PA10_TWD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A + ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RTTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RTTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgPMC +//* \brief Enable Peripheral clock in PMC for TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TDES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPMC +//* \brief Enable Peripheral clock in PMC for EMAC +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_EMAC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPIO +//* \brief Configure PIO controllers to drive EMAC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB2_ETX0 ) | + ((unsigned int) AT91C_PB12_ETXER ) | + ((unsigned int) AT91C_PB16_ECOL ) | + ((unsigned int) AT91C_PB11_ETX3 ) | + ((unsigned int) AT91C_PB6_ERX1 ) | + ((unsigned int) AT91C_PB15_ERXDV ) | + ((unsigned int) AT91C_PB13_ERX2 ) | + ((unsigned int) AT91C_PB3_ETX1 ) | + ((unsigned int) AT91C_PB8_EMDC ) | + ((unsigned int) AT91C_PB5_ERX0 ) | + //((unsigned int) AT91C_PB18_EF100 ) | + ((unsigned int) AT91C_PB14_ERX3 ) | + ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | + ((unsigned int) AT91C_PB1_ETXEN ) | + ((unsigned int) AT91C_PB10_ETX2 ) | + ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | + ((unsigned int) AT91C_PB9_EMDIO ) | + ((unsigned int) AT91C_PB7_ERXER ) | + ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB23_TIOA0 ) | + ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A + ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB25_TIOA1 ) | + ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A + ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB28_TIOB2 ) | + ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A + 0); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOB_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOB +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOB_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOB)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPMC +//* \brief Enable Peripheral clock in PMC for CAN +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_CAN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPIO +//* \brief Configure PIO controllers to drive CAN signals +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA20_CANTX ) | + ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +#endif // lib_AT91SAM7X128_H diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h new file mode 100644 index 0000000..02ee900 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h @@ -0,0 +1,4558 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X256.h +//* Object : AT91SAM7X256 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7X256_H +#define lib_AT91SAM7X256_H + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR RSTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSoftReset +//* \brief Start Software Reset +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSoftReset( + AT91PS_RSTC pRSTC, + unsigned int reset) +{ + pRSTC->RSTC_RCR = (0xA5000000 | reset); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSetMode +//* \brief Set Reset Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSetMode( + AT91PS_RSTC pRSTC, + unsigned int mode) +{ + pRSTC->RSTC_RMR = (0xA5000000 | mode); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetMode +//* \brief Get Reset Mode +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetMode( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetStatus +//* \brief Get Reset Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetStatus( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RSR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTIsSoftRstActive +//* \brief Return !=0 if software reset is still not completed +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTIsSoftRstActive( + AT91PS_RSTC pRSTC) +{ + return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); +} +/* ***************************************************************************** + SOFTWARE API FOR RTTC + ***************************************************************************** */ +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_SetRTT_TimeBase() +//* \brief Set the RTT prescaler according to the TimeBase in ms +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetTimeBase( + AT91PS_RTTC pRTTC, + unsigned int ms) +{ + if (ms > 2000) + return 1; // AT91C_TIME_OUT_OF_RANGE + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); + return 0; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTSetPrescaler() +//* \brief Set the new prescaler value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetPrescaler( + AT91PS_RTTC pRTTC, + unsigned int rtpres) +{ + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); + return (pRTTC->RTTC_RTMR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTRestart() +//* \brief Restart the RTT prescaler +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTRestart( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; +} + + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmINT() +//* \brief Enable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearAlarmINT() +//* \brief Disable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetRttIncINT() +//* \brief Enable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearRttIncINT() +//* \brief Disable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmValue() +//* \brief Set RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmValue( + AT91PS_RTTC pRTTC, unsigned int alarm) +{ + pRTTC->RTTC_RTAR = alarm; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_GetAlarmValue() +//* \brief Get RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetAlarmValue( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTAR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTGetStatus() +//* \brief Read the RTT status +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetStatus( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTSR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ReadValue() +//* \brief Read the RTT value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTReadValue( + AT91PS_RTTC pRTTC) +{ + register volatile unsigned int val1,val2; + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while(val1 != val2); + return(val1); +} +/* ***************************************************************************** + SOFTWARE API FOR PITC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITInit +//* \brief System timer init : period in �second, system clock freq in MHz +//*---------------------------------------------------------------------------- +__inline void AT91F_PITInit( + AT91PS_PITC pPITC, + unsigned int period, + unsigned int pit_frequency) +{ + pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 + pPITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITSetPIV +//* \brief Set the PIT Periodic Interval Value +//*---------------------------------------------------------------------------- +__inline void AT91F_PITSetPIV( + AT91PS_PITC pPITC, + unsigned int piv) +{ + pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITEnableInt +//* \brief Enable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITEnableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITDisableInt +//* \brief Disable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITDisableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetMode +//* \brief Read PIT mode register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetMode( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetStatus +//* \brief Read PIT status register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetStatus( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PISR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIIR +//* \brief Read PIT CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIIR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIIR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIVR +//* \brief Read System timer CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIVR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIVR); +} +/* ***************************************************************************** + SOFTWARE API FOR WDTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSetMode +//* \brief Set Watchdog Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTSetMode( + AT91PS_WDTC pWDTC, + unsigned int Mode) +{ + pWDTC->WDTC_WDMR = Mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTRestart +//* \brief Restart Watchdog +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTRestart( + AT91PS_WDTC pWDTC) +{ + pWDTC->WDTC_WDCR = 0xA5000001; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSGettatus +//* \brief Get Watchdog Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTSGettatus( + AT91PS_WDTC pWDTC) +{ + return(pWDTC->WDTC_WDSR & 0x3); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTGetPeriod +//* \brief Translate ms into Watchdog Compatible value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) +{ + if ((ms < 4) || (ms > 16000)) + return 0; + return((ms << 8) / 1000); +} +/* ***************************************************************************** + SOFTWARE API FOR VREG + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Enable_LowPowerMode +//* \brief Enable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Enable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR |= AT91C_VREG_PSTDBY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Disable_LowPowerMode +//* \brief Disable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Disable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; +}/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; + pUDP->UDP_RSTEP = 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR CAN + ***************************************************************************** */ +#define STANDARD_FORMAT 0 +#define EXTENDED_FORMAT 1 + +//*---------------------------------------------------------------------------- +//* \fn AT91F_InitMailboxRegisters() +//* \brief Configure the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, + int mode_reg, + int acceptance_mask_reg, + int id_reg, + int data_low_reg, + int data_high_reg, + int control_reg) +{ + CAN_Mailbox->CAN_MB_MCR = 0x0; + CAN_Mailbox->CAN_MB_MMR = mode_reg; + CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; + CAN_Mailbox->CAN_MB_MID = id_reg; + CAN_Mailbox->CAN_MB_MDL = data_low_reg; + CAN_Mailbox->CAN_MB_MDH = data_high_reg; + CAN_Mailbox->CAN_MB_MCR = control_reg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EnableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_EnableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR |= AT91C_CAN_CANEN; + + // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver + while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DisableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_DisableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR &= ~AT91C_CAN_CANEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_EnableIt +//* \brief Enable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_EnableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pCAN->CAN_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_DisableIt +//* \brief Disable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_DisableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pCAN->CAN_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetStatus +//* \brief Return CAN Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInterruptMaskStatus +//* \brief Return CAN Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsInterruptMasked +//* \brief Test if CAN Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsInterruptMasked( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsStatusSet +//* \brief Test if CAN Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsStatusSet( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgModeReg +//* \brief Configure the Mode Register of the CAN controller +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgModeReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pCAN->CAN_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetModeReg +//* \brief Return the Mode Register of the CAN controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetModeReg ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgBaudrateReg +//* \brief Configure the Baudrate of the CAN controller for the network +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgBaudrateReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int baudrate_cfg) +{ + //* Write to the BR register + pCAN->CAN_BR = baudrate_cfg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetBaudrate +//* \brief Return the Baudrate of the CAN controller for the network value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetBaudrate ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_BR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInternalCounter +//* \brief Return CAN Timer Regsiter Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInternalCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetTimestamp +//* \brief Return CAN Timestamp Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetTimestamp ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIMESTP; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetErrorCounter +//* \brief Return CAN Error Counter Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetErrorCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_ECR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitTransferRequest +//* \brief Request for a transfer on the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitTransferRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int transfer_cmd) +{ + pCAN->CAN_TCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitAbortRequest +//* \brief Abort the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitAbortRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int abort_cmd) +{ + pCAN->CAN_ACR = abort_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageModeReg +//* \brief Program the Message Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mode) +{ + CAN_Mailbox->CAN_MB_MMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageModeReg +//* \brief Return the Message Mode Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageIDReg +//* \brief Program the Message ID Register +//* \brief Version == 0 for Standard messsage, Version == 1 for Extended +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int id, + unsigned char version) +{ + if(version==0) // IDvA Standard Format + CAN_Mailbox->CAN_MB_MID = id<<18; + else // IDvB Extended Format + CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageIDReg +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg +//* \brief Program the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mask) +{ + CAN_Mailbox->CAN_MB_MAM = mask; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg +//* \brief Return the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MAM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetFamilyID +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetFamilyID ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MFID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageCtrl +//* \brief Request and config for a transfer on the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageCtrlReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int message_ctrl_cmd) +{ + CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageStatus +//* \brief Return CAN Mailbox Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageStatus ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataLow +//* \brief Program data low value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDL = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataLow +//* \brief Return data low value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataHigh +//* \brief Program data high value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDH = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataHigh +//* \brief Return data high value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDH; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_Open +//* \brief Open a CAN Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} +/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR AES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_EnableIt +//* \brief Enable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_EnableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pAES->AES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_DisableIt +//* \brief Disable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_DisableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pAES->AES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetStatus +//* \brief Return AES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetInterruptMaskStatus +//* \brief Return AES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsInterruptMasked +//* \brief Test if AES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsInterruptMasked( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsStatusSet +//* \brief Test if AES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsStatusSet( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgModeReg +//* \brief Configure the Mode Register of the AES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgModeReg ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pAES->AES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetModeReg +//* \brief Return the Mode Register of the AES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetModeReg ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + return pAES->AES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_StartProcessing ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SoftReset +//* \brief Reset AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SoftReset ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_LoadNewSeed +//* \brief Load New Seed in the random number generator +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_LoadNewSeed ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_LOADSEED; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetCryptoKey +//* \brief Set Cryptographic Key x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetCryptoKey ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int keyword + ) +{ + pAES->AES_KEYWxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_InputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int indata + ) +{ + pAES->AES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetOutputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index + ) +{ + return pAES->AES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetInitializationVector +//* \brief Set Initialization Vector (or Counter) x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetInitializationVector ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int initvector + ) +{ + pAES->AES_IVxR[index] = initvector; +} + +/* ***************************************************************************** + SOFTWARE API FOR TDES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_EnableIt +//* \brief Enable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_EnableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pTDES->TDES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_DisableIt +//* \brief Disable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_DisableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pTDES->TDES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetStatus +//* \brief Return TDES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetInterruptMaskStatus +//* \brief Return TDES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsInterruptMasked +//* \brief Test if TDES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsInterruptMasked( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsStatusSet +//* \brief Test if TDES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsStatusSet( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgModeReg +//* \brief Configure the Mode Register of the TDES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgModeReg ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pTDES->TDES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetModeReg +//* \brief Return the Mode Register of the TDES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetModeReg ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + return pTDES->TDES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_StartProcessing ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SoftReset +//* \brief Reset TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SoftReset ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey1 +//* \brief Set Cryptographic Key 1 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey1 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY1WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey2 +//* \brief Set Cryptographic Key 2 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey2 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY2WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey3 +//* \brief Set Cryptographic Key 3 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey3 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY3WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_InputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int indata + ) +{ + pTDES->TDES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetOutputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index + ) +{ + return pTDES->TDES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetInitializationVector +//* \brief Set Initialization Vector x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetInitializationVector ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int initvector + ) +{ + pTDES->TDES_IVxR[index] = initvector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA27_DRXD ) | + ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB30_PCK2 ) | + ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A + ((unsigned int) AT91C_PB20_PCK0 ) | + ((unsigned int) AT91C_PB0_PCK0 ) | + ((unsigned int) AT91C_PB22_PCK2 ) | + ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA30_PCK2 ) | + ((unsigned int) AT91C_PA13_PCK1 ) | + ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_CfgPMC +//* \brief Enable Peripheral clock in PMC for VREG +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RSTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA25_RK ) | + ((unsigned int) AT91C_PA22_TK ) | + ((unsigned int) AT91C_PA21_TF ) | + ((unsigned int) AT91C_PA24_RD ) | + ((unsigned int) AT91C_PA26_RF ) | + ((unsigned int) AT91C_PA23_TD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for WDTC +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB26_RI1 ) | + ((unsigned int) AT91C_PB24_DSR1 ) | + ((unsigned int) AT91C_PB23_DCD1 ) | + ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA7_SCK1 ) | + ((unsigned int) AT91C_PA8_RTS1 ) | + ((unsigned int) AT91C_PA6_TXD1 ) | + ((unsigned int) AT91C_PA5_RXD1 ) | + ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_RXD0 ) | + ((unsigned int) AT91C_PA4_CTS0 ) | + ((unsigned int) AT91C_PA3_RTS0 ) | + ((unsigned int) AT91C_PA2_SCK0 ) | + ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI1 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPIO +//* \brief Configure PIO controllers to drive SPI1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB16_NPCS13 ) | + ((unsigned int) AT91C_PB10_NPCS11 ) | + ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA4_NPCS13 ) | + ((unsigned int) AT91C_PA29_NPCS13 ) | + ((unsigned int) AT91C_PA21_NPCS10 ) | + ((unsigned int) AT91C_PA22_SPCK1 ) | + ((unsigned int) AT91C_PA25_NPCS11 ) | + ((unsigned int) AT91C_PA2_NPCS11 ) | + ((unsigned int) AT91C_PA24_MISO1 ) | + ((unsigned int) AT91C_PA3_NPCS12 ) | + ((unsigned int) AT91C_PA26_NPCS12 ) | + ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI0 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPIO +//* \brief Configure PIO controllers to drive SPI0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB13_NPCS01 ) | + ((unsigned int) AT91C_PB17_NPCS03 ) | + ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA16_MISO0 ) | + ((unsigned int) AT91C_PA13_NPCS01 ) | + ((unsigned int) AT91C_PA15_NPCS03 ) | + ((unsigned int) AT91C_PA17_MOSI0 ) | + ((unsigned int) AT91C_PA18_SPCK0 ) | + ((unsigned int) AT91C_PA14_NPCS02 ) | + ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A + ((unsigned int) AT91C_PA7_NPCS01 ) | + ((unsigned int) AT91C_PA9_NPCS03 ) | + ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PITC +//*---------------------------------------------------------------------------- +__inline void AT91F_PITC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ0 ) | + ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A + ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgPMC +//* \brief Enable Peripheral clock in PMC for AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_AES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_TWCK ) | + ((unsigned int) AT91C_PA10_TWD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A + ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RTTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RTTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgPMC +//* \brief Enable Peripheral clock in PMC for TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TDES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPMC +//* \brief Enable Peripheral clock in PMC for EMAC +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_EMAC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPIO +//* \brief Configure PIO controllers to drive EMAC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB2_ETX0 ) | + ((unsigned int) AT91C_PB12_ETXER ) | + ((unsigned int) AT91C_PB16_ECOL ) | + ((unsigned int) AT91C_PB11_ETX3 ) | + ((unsigned int) AT91C_PB6_ERX1 ) | + ((unsigned int) AT91C_PB15_ERXDV ) | + ((unsigned int) AT91C_PB13_ERX2 ) | + ((unsigned int) AT91C_PB3_ETX1 ) | + ((unsigned int) AT91C_PB8_EMDC ) | + ((unsigned int) AT91C_PB5_ERX0 ) | + //((unsigned int) AT91C_PB18_EF100 ) | + ((unsigned int) AT91C_PB14_ERX3 ) | + ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | + ((unsigned int) AT91C_PB1_ETXEN ) | + ((unsigned int) AT91C_PB10_ETX2 ) | + ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | + ((unsigned int) AT91C_PB9_EMDIO ) | + ((unsigned int) AT91C_PB7_ERXER ) | + ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB23_TIOA0 ) | + ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A + ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB25_TIOA1 ) | + ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A + ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB28_TIOB2 ) | + ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A + 0); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOB_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOB +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOB_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOB)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPMC +//* \brief Enable Peripheral clock in PMC for CAN +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_CAN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPIO +//* \brief Configure PIO controllers to drive CAN signals +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA20_CANTX ) | + ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +#endif // lib_AT91SAM7X256_H diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/port.c new file mode 100644 index 0000000..5d4badf --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/port.c @@ -0,0 +1,260 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Atmel ARM7 port. + *----------------------------------------------------------*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) +/*-----------------------------------------------------------*/ + +/* Setup the PIT to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + static __arm __irq void vPortNonPreemptiveTick( void ); + static __arm __irq void vPortNonPreemptiveTick( void ) + { + uint32_t ulDummy; + + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + xTaskIncrementTick(); + + /* Clear the PIT interrupt. */ + ulDummy = AT91C_BASE_PITC->PITC_PIVR; + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = ulDummy; + } + +#else + + /* Currently the IAR port requires the preemptive tick function to be + defined in an asm file. */ + +#endif + +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +AT91PS_PITC pxPIT = AT91C_BASE_PITC; + + /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends + on whether the preemptive or cooperative scheduler is being used. */ + #if configUSE_PREEMPTION == 0 + + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick ); + + #else + + extern void ( vPortPreemptiveTick )( void ); + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick ); + + #endif + + /* Configure the PIT period. */ + pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; + + /* Enable the interrupt. Global interrupts are disables at this point so + this is safe. */ + AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/portasm.s79 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/portasm.s79 new file mode 100644 index 0000000..0655206 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/portasm.s79 @@ -0,0 +1,89 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + + PUBLIC vPortYieldProcessor + PUBLIC vPortPreemptiveTick + PUBLIC vPortStartFirstTask + +#include "AT91SAM7S64_inc.h" +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get installed if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTick: + portSAVE_CONTEXT ; Save the context of the current task. + + LDR R0, =xTaskIncrementTick ; Increment the tick count - this may wake a task. + mov lr, pc + BX R0 + + CMP R0, #0 + BEQ SkipContextSwitch + LDR R0, =vTaskSwitchContext ; Select the next task to execute. + mov lr, pc + BX R0 +SkipContextSwitch + LDR R14, =AT91C_BASE_PITC ; Clear the PIT interrupt + LDR R0, [R14, #PITC_PIVR ] + + LDR R14, =AT91C_BASE_AIC ; Mark the End of Interrupt on the AIC + STR R14, [R14, #AIC_EOICR] + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/portmacro.h new file mode 100644 index 0000000..76ae207 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM7S64/portmacro.h @@ -0,0 +1,112 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM9XE/ISR_Support.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM9XE/ISR_Support.h new file mode 100644 index 0000000..0a410dc --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM9XE/ISR_Support.h @@ -0,0 +1,105 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM9XE/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM9XE/port.c new file mode 100644 index 0000000..d09f727 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM9XE/port.c @@ -0,0 +1,257 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Atmel ARM7 port. + *----------------------------------------------------------*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware includes. */ +#include +#include +#include +#include +#include +#include +#include +#include + +/*-----------------------------------------------------------*/ + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to setup the PIT. */ +#define port1MHz_IN_Hz ( 1000000ul ) +#define port1SECOND_IN_uS ( 1000000.0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) +/*-----------------------------------------------------------*/ + +/* Setup the PIT to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* The PIT interrupt handler - the RTOS tick. */ +static void vPortTickISR( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +static __arm void vPortTickISR( void ) +{ +volatile uint32_t ulDummy; + + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Clear the PIT interrupt. */ + ulDummy = AT91C_BASE_PITC->PITC_PIVR; + + /* To remove compiler warning. */ + ( void ) ulDummy; + + /* The AIC is cleared in the asm wrapper, outside of this function. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +const uint32_t ulPeriodIn_uS = ( 1.0 / ( double ) configTICK_RATE_HZ ) * port1SECOND_IN_uS; + + /* Setup the PIT for the required frequency. */ + PIT_Init( ulPeriodIn_uS, BOARD_MCK / port1MHz_IN_Hz ); + + /* Setup the PIT interrupt. */ + AIC_DisableIT( AT91C_ID_SYS ); + AIC_ConfigureIT( AT91C_ID_SYS, AT91C_AIC_PRIOR_LOWEST, vPortTickISR ); + AIC_EnableIT( AT91C_ID_SYS ); + PIT_EnableIT(); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_irq(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_irq(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM9XE/portasm.s79 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM9XE/portasm.s79 new file mode 100644 index 0000000..919a6ca --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM9XE/portasm.s79 @@ -0,0 +1,61 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM9XE/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM9XE/portmacro.h new file mode 100644 index 0000000..43b36f7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/AtmelSAM9XE/portmacro.h @@ -0,0 +1,115 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_irq() +#define portENABLE_INTERRUPTS() __enable_irq() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/LPC2000/ISR_Support.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/LPC2000/ISR_Support.h new file mode 100644 index 0000000..b48841a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/LPC2000/ISR_Support.h @@ -0,0 +1,106 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/LPC2000/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/LPC2000/port.c new file mode 100644 index 0000000..b5b714f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/LPC2000/port.c @@ -0,0 +1,318 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Philips ARM7 port. + *----------------------------------------------------------*/ + +/* + Changes from V3.2.2 + + + Bug fix - The prescale value for the timer setup is now written to T0PR + instead of T0PC. This bug would have had no effect unless a prescale + value was actually used. +*/ + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the PIT to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + static __arm __irq void vPortNonPreemptiveTick( void ); + static __arm __irq void vPortNonPreemptiveTick( void ) + { + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + xTaskIncrementTick(); + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#else + + /* This function is called from an asm wrapper, so does not require the __irq + keyword. */ + void vPortPreemptiveTick( void ); + void vPortPreemptiveTick( void ) + { + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* The new tick value might unblock a task. Ensure the highest task that + is ready to execute is the task that will execute when the tick ISR + exits. */ + vTaskSwitchContext(); + } + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#endif + +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +uint32_t ulCompareMatch; + + /* A 1ms tick does not require the use of the timer prescale. This is + defaulted to zero but can be used if necessary. */ + T0PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + + T0MR0 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; + + /* Setup the VIC for the timer. */ + VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); + VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; + + /* The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + extern void ( vPortPreemptiveTickEntry )( void ); + + VICVectAddr0 = ( uint32_t ) vPortPreemptiveTickEntry; + } + #else + { + extern void ( vNonPreemptiveTick )( void ); + + VICVectAddr0 = ( int32_t ) vPortNonPreemptiveTick; + } + #endif + + VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; + + /* Start the timer - interrupts are disabled when this function is called + so it is okay to do this here. */ + T0TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/LPC2000/portasm.s79 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/LPC2000/portasm.s79 new file mode 100644 index 0000000..f0c3be7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/LPC2000/portasm.s79 @@ -0,0 +1,77 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + EXTERN vPortPreemptiveTick + + PUBLIC vPortPreemptiveTickEntry + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get installed if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTickEntry: +#if configUSE_PREEMPTION == 1 + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vPortPreemptiveTick; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. +#endif + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/LPC2000/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/LPC2000/portmacro.h new file mode 100644 index 0000000..b60464e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/LPC2000/portmacro.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430/port.c new file mode 100644 index 0000000..30f97bb --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430/port.c @@ -0,0 +1,174 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430 port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void vPortSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x3333; + pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + executing an ISR. We want the stack to look just as if this has happened + so place a pointer to the start of the task on the stack first - followed + by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( StackType_t ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xbbbb; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R15. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xeeee; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xffff; + pxTopOfStack--; + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +void vPortSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430/portasm.h new file mode 100644 index 0000000..9f10f05 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430/portasm.h @@ -0,0 +1,85 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTASM_H +#define PORTASM_H + +portSAVE_CONTEXT macro + + IMPORT pxCurrentTCB + IMPORT usCriticalNesting + + /* Save the remaining registers. */ + push r4 + push r5 + push r6 + push r7 + push r8 + push r9 + push r10 + push r11 + push r12 + push r13 + push r14 + push r15 + mov.w &usCriticalNesting, r14 + push r14 + mov.w &pxCurrentTCB, r12 + mov.w r1, 0(r12) + endm +/*-----------------------------------------------------------*/ + +portRESTORE_CONTEXT macro + mov.w &pxCurrentTCB, r12 + mov.w @r12, r1 + pop r15 + mov.w r15, &usCriticalNesting + pop r15 + pop r14 + pop r13 + pop r12 + pop r11 + pop r10 + pop r9 + pop r8 + pop r7 + pop r6 + pop r5 + pop r4 + + /* The last thing on the stack will be the status register. + Ensure the power down bits are clear ready for the next + time this power down register is popped from the stack. */ + bic.w #0xf0,0(SP) + + reti + endm +/*-----------------------------------------------------------*/ + +#endif + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430/portext.s43 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430/portext.s43 new file mode 100644 index 0000000..5c27134 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430/portext.s43 @@ -0,0 +1,107 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +#include "FreeRTOSConfig.h" +#include "portasm.h" + + IMPORT xTaskIncrementTick + IMPORT vTaskSwitchContext + IMPORT vPortSetupTimerInterrupt + + EXPORT vTickISR + EXPORT vPortYield + EXPORT xPortStartScheduler + + RSEG CODE + +/* + * The RTOS tick ISR. + * + * If the cooperative scheduler is in use this simply increments the tick + * count. + * + * If the preemptive scheduler is in use a context switch can also occur. + */ +vTickISR: + portSAVE_CONTEXT + + call #xTaskIncrementTick + cmp.w #0x0, R12 + jeq SkipContextSwitch + call #vTaskSwitchContext +SkipContextSwitch: + + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Manual context switch called by the portYIELD() macro. + */ +vPortYield: + + /* Mimic an interrupt by pushing the SR. */ + push SR + + /* Now the SR is stacked we can disable interrupts. */ + dint + + /* Save the context of the current task. */ + portSAVE_CONTEXT + + /* Switch to the highest priority task that is ready to run. */ + call #vTaskSwitchContext + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Start off the scheduler by initialising the RTOS tick timer, then restoring + * the context of the first task. + */ +xPortStartScheduler: + + /* Setup the hardware to generate the tick. Interrupts are disabled + when this function is called. */ + call #vPortSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + + /* Install vTickISR as the timer A0 interrupt. */ + ASEG + ORG 0xFFE0 + TIMERA0_VECTOR + + _vTickISR_: DC16 vTickISR + + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430/portmacro.h new file mode 100644 index 0000000..ed0602d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430/portmacro.h @@ -0,0 +1,134 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _DINT(); _NOP() +#define portENABLE_INTERRUPTS() _EINT(); _NOP() +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() +#define portPOINTER_SIZE_TYPE uint16_t +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#if configINTERRUPT_EXAMPLE_METHOD == 2 + +extern void vTaskSwitchContext( void ); +#define portYIELD_FROM_ISR( x ) do { if( x ) vTaskSwitchContext(); } while( 0 ) + +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430X/data_model.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430X/data_model.h new file mode 100644 index 0000000..17f3a77 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430X/data_model.h @@ -0,0 +1,64 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef DATA_MODEL_H +#define DATA_MODEL_H + +#if __DATA_MODEL__ == __DATA_MODEL_SMALL__ + #define pushm_x pushm.w + #define popm_x popm.w + #define push_x push.w + #define pop_x pop.w + #define mov_x mov.w + #define cmp_x cmp.w +#endif + +#if __DATA_MODEL__ == __DATA_MODEL_MEDIUM__ + #define pushm_x pushm.a + #define popm_x popm.a + #define push_x pushx.a + #define pop_x popx.a + #define mov_x mov.w + #define cmp_x cmp.w +#endif + +#if __DATA_MODEL__ == __DATA_MODEL_LARGE__ + #define pushm_x pushm.a + #define popm_x popm.a + #define push_x pushx.a + #define pop_x popx.a + #define mov_x movx.a + #define cmp_x cmpx.a +#endif + +#ifndef pushm_x + #error The assembler options must define one of the following symbols: __DATA_MODEL_SMALL__, __DATA_MODEL_MEDIUM__, or __DATA_MODEL_LARGE__ +#endif + +#endif /* DATA_MODEL_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430X/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430X/port.c new file mode 100644 index 0000000..012f4e9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430X/port.c @@ -0,0 +1,183 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430X port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void vPortSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint16_t *pusTopOfStack; +uint32_t *pulTopOfStack; + + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x3333; + */ + + /* StackType_t is either 16 bits or 32 bits depending on the data model. + Some stacked items do not change size depending on the data model so have + to be explicitly cast to the correct size so this function will work + whichever data model is being used. */ + if( sizeof( StackType_t ) == sizeof( uint16_t ) ) + { + /* Make room for a 20 bit value stored as a 32 bit value. */ + pusTopOfStack = ( uint16_t * ) pxTopOfStack; + pusTopOfStack--; + pulTopOfStack = ( uint32_t * ) pusTopOfStack; + } + else + { + pulTopOfStack = ( uint32_t * ) pxTopOfStack; + } + *pulTopOfStack = ( uint32_t ) pxCode; + + pusTopOfStack = ( uint16_t * ) pulTopOfStack; + pusTopOfStack--; + *pusTopOfStack = portFLAGS_INT_ENABLED; + pusTopOfStack -= ( sizeof( StackType_t ) / 2 ); + + /* From here on the size of stacked items depends on the memory model. */ + pxTopOfStack = ( StackType_t * ) pusTopOfStack; + + /* Next the general purpose registers. */ + #ifdef PRELOAD_REGISTER_VALUES + *pxTopOfStack = ( StackType_t ) 0xffff; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xeeee; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x4444; + pxTopOfStack--; + #else + pxTopOfStack -= 3; + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack -= 9; + #endif + + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. + */ +void vPortSetupTimerInterrupt( void ) +{ + vApplicationSetupTimerInterrupt(); +} +/*-----------------------------------------------------------*/ + +#pragma vector=configTICK_VECTOR +__interrupt __raw void vTickISREntry( void ) +{ +extern void vPortTickISR( void ); + + __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF ); + vPortTickISR(); +} + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430X/portext.s43 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430X/portext.s43 new file mode 100644 index 0000000..6293c63 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430X/portext.s43 @@ -0,0 +1,139 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +#include "msp430.h" +#include "FreeRTOSConfig.h" +#include "data_model.h" + + IMPORT xTaskIncrementTick + IMPORT vTaskSwitchContext + IMPORT vPortSetupTimerInterrupt + IMPORT pxCurrentTCB + IMPORT usCriticalNesting + + EXPORT vPortTickISR + EXPORT vPortYield + EXPORT xPortStartScheduler + +portSAVE_CONTEXT macro + + /* Save the remaining registers. */ + pushm_x #12, r15 + mov.w &usCriticalNesting, r14 + push_x r14 + mov_x &pxCurrentTCB, r12 + mov_x sp, 0( r12 ) + endm +/*-----------------------------------------------------------*/ + +portRESTORE_CONTEXT macro + + mov_x &pxCurrentTCB, r12 + mov_x @r12, sp + pop_x r15 + mov.w r15, &usCriticalNesting + popm_x #12, r15 + nop + pop.w sr + nop + reta + endm +/*-----------------------------------------------------------*/ + + +/* + * The RTOS tick ISR. + * + * If the cooperative scheduler is in use this simply increments the tick + * count. + * + * If the preemptive scheduler is in use a context switch can also occur. + */ + + RSEG CODE + EVEN + +vPortTickISR: + + /* The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs + to save it manually before it gets modified (interrupts get disabled). + Entering through this interrupt means the SR is already on the stack, but + this keeps the stack frames identical. */ + push.w sr + portSAVE_CONTEXT + + calla #xTaskIncrementTick + cmp.w #0x0, R12 + jeq SkipContextSwitch + calla #vTaskSwitchContext +SkipContextSwitch: + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by the portYIELD() macro. + */ + EVEN + +vPortYield: + + /* The sr needs saving before it is modified. */ + push.w sr + + /* Now the SR is stacked interrupts can be disabled. */ + dint + nop + + /* Save the context of the current task. */ + portSAVE_CONTEXT + + /* Select the next task to run. */ + calla #vTaskSwitchContext + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Start off the scheduler by initialising the RTOS tick timer, then restoring + * the context of the first task. + */ + EVEN + +xPortStartScheduler: + + /* Setup the hardware to generate the tick. Interrupts are disabled + when this function is called. */ + calla #vPortSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430X/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430X/portmacro.h new file mode 100644 index 0000000..c8cd76c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/MSP430X/portmacro.h @@ -0,0 +1,143 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Hardware includes. */ +#include "msp430.h" + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portBASE_TYPE short + +/* The stack type changes depending on the data model. */ +#if( __DATA_MODEL__ == __DATA_MODEL_SMALL__ ) + #define portSTACK_TYPE uint16_t + #define portPOINTER_SIZE_TYPE uint16_t +#else + #define portSTACK_TYPE uint32_t +#endif + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _DINT(); _NOP() +#define portENABLE_INTERRUPTS() _EINT(); _NOP() +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define portYIELD_FROM_ISR( x ) do { if( x ) vPortYield(); } while( 0 ) + +void vApplicationSetupTimerInterrupt( void ); + +/* sizeof( int ) != sizeof( long ) so a full printf() library is required if +run time stats information is to be displayed. */ +#define portLU_PRINTF_SPECIFIER_REQUIRED + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/Documentation.url b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/Documentation.url new file mode 100644 index 0000000..c7819d5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/Documentation.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,11 +[InternetShortcut] +IDList= +URL=https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h new file mode 100644 index 0000000..b880084 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -0,0 +1,69 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ + + +#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ +#define __FREERTOS_RISC_V_EXTENSIONS_H__ + +#define portasmHAS_SIFIVE_CLINT 1 +#define portasmHAS_MTIME 1 +#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */ + +portasmSAVE_ADDITIONAL_REGISTERS MACRO + /* No additional registers to save, so this macro does nothing. */ + ENDM + +portasmRESTORE_ADDITIONAL_REGISTERS MACRO + /* No additional registers to restore, so this macro does nothing. */ + ENDM + +#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/chip_specific_extensions/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/chip_specific_extensions/readme.txt new file mode 100644 index 0000000..69d98d9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/chip_specific_extensions/readme.txt @@ -0,0 +1,23 @@ +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/port.c new file mode 100644 index 0000000..289c8bd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/port.c @@ -0,0 +1,213 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the RISC-V RV32 port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* Standard includes. */ +#include "string.h" + +#ifdef configCLINT_BASE_ADDRESS + #warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +#ifndef configMTIME_BASE_ADDRESS + #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +#ifndef configMTIMECMP_BASE_ADDRESS + #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +/* Let the user override the pre-loading of the initial LR with the address of +prvTaskExitError() in case it messes up unwinding of the stack in the +debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS +to use a statically allocated array as the interrupt stack. Alternative leave +configISR_STACK_SIZE_WORDS undefined and update the linker script so that a +linker variable names __freertos_irq_stack_top has the same value as the top +of the stack used by main. Using the linker script method will repurpose the +stack that was used by main before the scheduler was started for use as the +interrupt stack after the scheduler has started. */ +#ifdef configISR_STACK_SIZE_WORDS + static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 }; + const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] ); + + /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for + the task stacks, and so will legitimately appear in many positions within + the ISR stack. */ + #define portISR_STACK_FILL_BYTE 0xee +#else + extern const uint32_t __freertos_irq_stack_top[]; + const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top; +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) __attribute__(( weak )); + +/*-----------------------------------------------------------*/ + +/* Used to program the machine timer compare register. */ +uint64_t ullNextTime = 0ULL; +const uint64_t *pullNextTime = &ullNextTime; +const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */ +uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS; +volatile uint64_t * pullMachineTimerCompareRegister = NULL; + +/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task +stack checking. A problem in the ISR stack will trigger an assert, not call the +stack overflow hook function (because the stack overflow hook is specific to a +task stack, not the ISR stack). */ +#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) + #warning This path not tested, or even compiled yet. + + static const uint8_t ucExpectedStackBytes[] = { + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \ + + #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) +#else + /* Define the function away. */ + #define portCHECK_ISR_STACK() +#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + +/*-----------------------------------------------------------*/ + +#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) + + void vPortSetupTimerInterrupt( void ) + { + uint32_t ulCurrentTimeHigh, ulCurrentTimeLow; + volatile uint32_t * const pulTimeHigh = ( uint32_t * ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte typer so high 32-bit word is 4 bytes up. */ + volatile uint32_t * const pulTimeLow = ( uint32_t * ) ( configMTIME_BASE_ADDRESS ); + volatile uint32_t ulHartId; + + __asm volatile( "csrr %0, 0xf14" : "=r"( ulHartId ) ); /* 0xf14 is hartid. */ + pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) ); + + do + { + ulCurrentTimeHigh = *pulTimeHigh; + ulCurrentTimeLow = *pulTimeLow; + } while( ulCurrentTimeHigh != *pulTimeHigh ); + + ullNextTime = ( uint64_t ) ulCurrentTimeHigh; + ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */ + ullNextTime |= ( uint64_t ) ulCurrentTimeLow; + ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick; + *pullMachineTimerCompareRegister = ullNextTime; + + /* Prepare the time to use after the next tick interrupt. */ + ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick; + } + +#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void xPortStartFirstTask( void ); + + #if( configASSERT_DEFINED == 1 ) + { + volatile uint32_t mtvec = 0; + + /* Check the least significant two bits of mtvec are 00 - indicating + single vector mode. */ + __asm volatile( "csrr %0, 0x305" : "=r"( mtvec ) ); /* 0x305 is mtvec. */ + configASSERT( ( mtvec & 0x03UL ) == 0 ); + + /* Check alignment of the interrupt stack - which is the same as the + stack that was being used by main() prior to the scheduler being + started. */ + configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 ); + + #ifdef configISR_STACK_SIZE_WORDS + { + memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) ); + } + #endif /* configISR_STACK_SIZE_WORDS */ + } + #endif /* configASSERT_DEFINED */ + + /* If there is a CLINT then it is ok to use the default implementation + in this file, otherwise vPortSetupTimerInterrupt() must be implemented to + configure whichever clock is to be used to generate the tick interrupt. */ + vPortSetupTimerInterrupt(); + + #if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) ) + { + /* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11 + for external interrupt. _RB_ What happens here when mtime is not present as + with pulpino? */ + __asm volatile( "csrs 0x304, %0" :: "r"(0x880) ); /* 0x304 is mie. */ + } + #else + { + /* Enable external interrupts. */ + __asm volatile( "csrs 0x304, %0" :: "r"(0x800) ); /* 304 is mie. */ + } + #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */ + + xPortStartFirstTask(); + + /* Should not get here as after calling xPortStartFirstTask() only tasks + should be executing. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ + for( ;; ); +} + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/portASM.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/portASM.s new file mode 100644 index 0000000..9c864b5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/portASM.s @@ -0,0 +1,448 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code which tailors the port to a specific RISC-V chip: + * + * + The code that is common to all RISC-V chips is implemented in + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one + * portASM.S file because the same file is used no matter which RISC-V chip is + * in use. + * + * + The code that tailors the kernel's RISC-V port to a specific RISC-V + * chip is implemented in freertos_risc_v_chip_specific_extensions.h. There + * is one freertos_risc_v_chip_specific_extensions.h that can be used with any + * RISC-V chip that both includes a standard CLINT and does not add to the + * base set of RISC-V registers. There are additional + * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations + * that do not include a standard CLINT or do add to the base set of RISC-V + * registers. + * + * CARE MUST BE TAKEN TO INCLDUE THE CORRECT + * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP + * IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h + * header file ensure the path to the correct header file is in the assembler's + * include path. + * + * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips + * that include a standard CLINT and do not add to the base set of RISC-V + * registers. + * + */ +#if __riscv_xlen == 64 + #define portWORD_SIZE 8 + #define store_x sd + #define load_x ld +#elif __riscv_xlen == 32 + #define store_x sw + #define load_x lw + #define portWORD_SIZE 4 +#else + #error Assembler did not define __riscv_xlen +#endif + +#include "freertos_risc_v_chip_specific_extensions.h" + +/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line +definitions. */ +#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME ) + #error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +#ifdef portasmHAS_CLINT + #warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html + #define portasmHAS_MTIME portasmHAS_CLINT + #define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT +#endif + +#ifndef portasmHAS_MTIME + #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +#ifndef portasmHANDLE_INTERRUPT + #error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assembler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file. https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + + +#ifndef portasmHAS_SIFIVE_CLINT + #define portasmHAS_SIFIVE_CLINT 0 +#endif + +/* CSR definitions. */ +#define CSR_MSTATUS 0x300 +#define CSR_MTVEC 0x305 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 + + +/* Only the standard core registers are stored by default. Any additional +registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and +portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip +specific version of freertos_risc_v_chip_specific_extensions.h. See the notes +at the top of this file. */ +#define portCONTEXT_SIZE ( 30 * portWORD_SIZE ) + + PUBLIC xPortStartFirstTask + PUBLIC freertos_risc_v_trap_handler + PUBLIC pxPortInitialiseStack + EXTERN pxCurrentTCB + EXTERN ulPortTrapHandler + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + EXTERN Timer_IRQHandler + EXTERN pullMachineTimerCompareRegister + EXTERN pullNextTime + EXTERN uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */ + EXTERN xISRStackTop + EXTERN portasmHANDLE_INTERRUPT + +/*-----------------------------------------------------------*/ + + SECTION `.text`:CODE:NOROOT(2) + CODE + +freertos_risc_v_trap_handler: + addi sp, sp, -portCONTEXT_SIZE + store_x x1, 1 * portWORD_SIZE( sp ) + store_x x5, 2 * portWORD_SIZE( sp ) + store_x x6, 3 * portWORD_SIZE( sp ) + store_x x7, 4 * portWORD_SIZE( sp ) + store_x x8, 5 * portWORD_SIZE( sp ) + store_x x9, 6 * portWORD_SIZE( sp ) + store_x x10, 7 * portWORD_SIZE( sp ) + store_x x11, 8 * portWORD_SIZE( sp ) + store_x x12, 9 * portWORD_SIZE( sp ) + store_x x13, 10 * portWORD_SIZE( sp ) + store_x x14, 11 * portWORD_SIZE( sp ) + store_x x15, 12 * portWORD_SIZE( sp ) + store_x x16, 13 * portWORD_SIZE( sp ) + store_x x17, 14 * portWORD_SIZE( sp ) + store_x x18, 15 * portWORD_SIZE( sp ) + store_x x19, 16 * portWORD_SIZE( sp ) + store_x x20, 17 * portWORD_SIZE( sp ) + store_x x21, 18 * portWORD_SIZE( sp ) + store_x x22, 19 * portWORD_SIZE( sp ) + store_x x23, 20 * portWORD_SIZE( sp ) + store_x x24, 21 * portWORD_SIZE( sp ) + store_x x25, 22 * portWORD_SIZE( sp ) + store_x x26, 23 * portWORD_SIZE( sp ) + store_x x27, 24 * portWORD_SIZE( sp ) + store_x x28, 25 * portWORD_SIZE( sp ) + store_x x29, 26 * portWORD_SIZE( sp ) + store_x x30, 27 * portWORD_SIZE( sp ) + store_x x31, 28 * portWORD_SIZE( sp ) + + csrr t0, CSR_MSTATUS /* Required for MPIE bit. */ + store_x t0, 29 * portWORD_SIZE( sp ) + + portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */ + + load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */ + store_x sp, 0( t0 ) /* Write sp to first TCB member. */ + + csrr a0, CSR_MCAUSE + csrr a1, CSR_MEPC + +test_if_asynchronous: + srli a2, a0, __riscv_xlen - 1 /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */ + beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */ + store_x a1, 0( sp ) /* Asynch so save unmodified exception return address. */ + +handle_asynchronous: + +#if( portasmHAS_MTIME != 0 ) + + test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */ + + addi t0, x0, 1 + + slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */ + addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */ + bne a0, t1, test_if_external_interrupt + + load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */ + load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */ + + #if( __riscv_xlen == 32 ) + + /* Update the 64-bit mtimer compare match value in two 32-bit writes. */ + li t4, -1 + lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */ + lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */ + sw t4, 0(t0) /* Low word no smaller than old value to start with - will be overwritten below. */ + sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */ + sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */ + lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */ + add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */ + sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */ + add t6, t3, t5 /* Add overflow to high word of ullNextTime. */ + sw t4, 0(t1) /* Store new low word of ullNextTime. */ + sw t6, 4(t1) /* Store new high word of ullNextTime. */ + + #endif /* __riscv_xlen == 32 */ + + #if( __riscv_xlen == 64 ) + + /* Update the 64-bit mtimer compare match value. */ + ld t2, 0(t1) /* Load ullNextTime into t2. */ + sd t2, 0(t0) /* Store ullNextTime into compare register. */ + ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */ + add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */ + sd t4, 0(t1) /* Store ullNextTime. */ + + #endif /* __riscv_xlen == 64 */ + + load_x sp, xISRStackTop /* Switch to ISR stack before function call. */ + jal xTaskIncrementTick + beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */ + jal vTaskSwitchContext + j processed_source + + test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */ + addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */ + bne a0, t1, as_yet_unhandled /* Something as yet unhandled. */ + +#endif /* portasmHAS_MTIME */ + + load_x sp, xISRStackTop /* Switch to ISR stack before function call. */ + jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */ + j processed_source + +handle_synchronous: + addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */ + store_x a1, 0( sp ) /* Save updated exception return address. */ + +test_if_environment_call: + li t0, 11 /* 11 == environment call. */ + bne a0, t0, is_exception /* Not an M environment call, so some other exception. */ + load_x sp, xISRStackTop /* Switch to ISR stack before function call. */ + jal vTaskSwitchContext + j processed_source + +is_exception: + csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */ + csrr t1, CSR_MEPC /* For viewing in the debugger only */ + csrr t2, CSR_MSTATUS + j is_exception /* No other exceptions handled yet. */ + +as_yet_unhandled: + csrr t0, mcause /* For viewing in the debugger only. */ + j as_yet_unhandled + +processed_source: + load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */ + load_x sp, 0( t1 ) /* Read sp from first TCB member. */ + + /* Load mret with the address of the next instruction in the task to run next. */ + load_x t0, 0( sp ) + csrw CSR_MEPC, t0 + + portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ + + /* Load mstatus with the interrupt enable bits used by the task. */ + load_x t0, 29 * portWORD_SIZE( sp ) + csrw CSR_MSTATUS, t0 /* Required for MPIE bit. */ + + load_x x1, 1 * portWORD_SIZE( sp ) + load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */ + load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */ + load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */ + load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */ + load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */ + load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */ + load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */ + load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */ + load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */ + load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */ + load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */ + load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */ + load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */ + load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */ + load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */ + load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */ + load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */ + load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */ + load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */ + load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */ + load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */ + load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */ + load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */ + load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */ + load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */ + load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */ + load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */ + addi sp, sp, portCONTEXT_SIZE + + mret + +/*-----------------------------------------------------------*/ + +xPortStartFirstTask: + +#if( portasmHAS_SIFIVE_CLINT != 0 ) + /* If there is a clint then interrupts can branch directly to the FreeRTOS + trap handler. Otherwise the interrupt controller will need to be configured + outside of this file. */ + la t0, freertos_risc_v_trap_handler + csrw CSR_MTVEC, t0 +#endif /* portasmHAS_CLILNT */ + + load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */ + load_x sp, 0( sp ) /* Read sp from first TCB member. */ + + load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */ + + portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ + + load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */ + load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */ + load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */ + load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */ + load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */ + load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */ + load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */ + load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */ + load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */ + load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */ + load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */ + load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */ + load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */ + load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */ + load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */ + load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */ + load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */ + load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */ + load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */ + load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */ + load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */ + load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */ + load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */ + load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */ + load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */ + load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */ + + load_x x5, 29 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0) */ + addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */ + csrrw x0, CSR_MSTATUS, x5 /* Interrupts enabled from here! */ + load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */ + addi sp, sp, portCONTEXT_SIZE + ret + +/*-----------------------------------------------------------*/ + +/* + * Unlike other ports pxPortInitialiseStack() is written in assembly code as it + * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype + * for the function is as per the other ports: + * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ); + * + * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in + * a1, and pvParameters in a2. The new top of stack is passed out in a0. + * + * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers + * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed). + * + * Register ABI Name Description Saver + * x0 zero Hard-wired zero - + * x1 ra Return address Caller + * x2 sp Stack pointer Callee + * x3 gp Global pointer - + * x4 tp Thread pointer - + * x5-7 t0-2 Temporaries Caller + * x8 s0/fp Saved register/Frame pointer Callee + * x9 s1 Saved register Callee + * x10-11 a0-1 Function Arguments/return values Caller + * x12-17 a2-7 Function arguments Caller + * x18-27 s2-11 Saved registers Callee + * x28-31 t3-6 Temporaries Caller + * + * The RISC-V context is saved t FreeRTOS tasks in the following stack frame, + * where the global and thread pointers are currently assumed to be constant so + * are not saved: + * + * mstatus + * x31 + * x30 + * x29 + * x28 + * x27 + * x26 + * x25 + * x24 + * x23 + * x22 + * x21 + * x20 + * x19 + * x18 + * x17 + * x16 + * x15 + * x14 + * x13 + * x12 + * x11 + * pvParameters + * x9 + * x8 + * x7 + * x6 + * x5 + * portTASK_RETURN_ADDRESS + * [chip specific registers go here] + * pxCode + */ +pxPortInitialiseStack: + + csrr t0, CSR_MSTATUS /* Obtain current mstatus value. */ + andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */ + addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */ + slli t1, t1, 4 + or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */ + + addi a0, a0, -portWORD_SIZE + store_x t0, 0(a0) /* mstatus onto the stack. */ + addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */ + store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */ + addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */ + store_x x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */ + addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */ +chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */ + beq t0, x0, no_more_regs /* No more chip specific registers to save. */ + addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */ + store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */ + addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */ + j chip_specific_stack_frame /* Until no more chip specific registers. */ +no_more_regs: + addi a0, a0, -portWORD_SIZE + store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */ + ret + +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/portmacro.h new file mode 100644 index 0000000..23dd200 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/portmacro.h @@ -0,0 +1,178 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include "intrinsics.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#if __riscv_xlen == 64 + #define portSTACK_TYPE uint64_t + #define portBASE_TYPE int64_t + #define portUBASE_TYPE uint64_t + #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL + #define portPOINTER_SIZE_TYPE uint64_t +#elif __riscv_xlen == 32 + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE int32_t + #define portUBASE_TYPE uint32_t + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error Assembler did not define __riscv_xlen +#endif + + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef portUBASE_TYPE UBaseType_t; +typedef portUBASE_TYPE TickType_t; + +/* Legacy type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do +not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#ifdef __riscv64 + #error This is the RV32 port that has not yet been adapted for 64. + #define portBYTE_ALIGNMENT 16 +#else + #define portBYTE_ALIGNMENT 16 +#endif +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +extern void vTaskSwitchContext( void ); +#define portYIELD() __asm volatile( "ecall" ); +#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ +#define portCRITICAL_NESTING_IN_TCB 1 +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); + +#define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + + #error configUSE_PORT_OPTIMISED_TASK_SELECTION cannot yet be used in the IAR RISC-V port, the CLZ instruction needs to be emulated. + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not necessary for to use this port. They are defined so the common demo files +(which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/*-----------------------------------------------------------*/ + +#define portNOP() __asm volatile ( " nop " ) + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__(( always_inline)) +#endif + +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) + + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in +the source code because to do so would cause other compilers to generate +warnings. */ +#pragma diag_suppress=Pa082 + +/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the +configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For +backward compatibility derive the newer definitions from the old if the old +definition is found. */ +#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) + /* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate + there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP + addresses to 0. */ + #define configMTIME_BASE_ADDRESS ( 0 ) + #define configMTIMECMP_BASE_ADDRESS ( 0 ) +#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) + /* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of + the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses + from the CLINT address. */ + #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL ) + #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL ) +#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS ) + #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + + + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/readme.txt new file mode 100644 index 0000000..69d98d9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RISC-V/readme.txt @@ -0,0 +1,23 @@ +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RL78/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RL78/port.c new file mode 100644 index 0000000..61b6fe4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RL78/port.c @@ -0,0 +1,210 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* The critical nesting value is initialised to a non zero value to ensure +interrupts don't accidentally become enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) + +/* Initial PSW value allocated to a newly created task. + * 1100011000000000 + * ||||||||-------------- Fill byte + * |||||||--------------- Carry Flag cleared + * |||||----------------- In-service priority Flags set to low level + * ||||------------------ Register bank Select 0 Flag cleared + * |||------------------- Auxiliary Carry Flag cleared + * ||-------------------- Register bank Select 1 Flag cleared + * |--------------------- Zero Flag set + * ---------------------- Global Interrupt Flag set (enabled) + */ +#define portPSW ( 0xc6UL ) + +/* The address of the pxCurrentTCB variable, but don't know or need to know its +type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each time +a critical section is entered the count is incremented. Each time a critical +section is exited the count is decremented - with interrupts only being +re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as that could cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; + +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. + */ +extern void vApplicationSetupTimerInterrupt( void ); + +/* + * Starts the scheduler by loading the context of the first Task to run. + * (implemented in portasm.s). + */ +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint32_t *pulLocal; + + /* With large code and large data sizeof( StackType_t ) == 2, and + sizeof( StackType_t * ) == 4. With small code and small data + sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */ + + #if __DATA_MODEL__ == __DATA_MODEL_FAR__ + { + /* Far pointer parameters are passed using the A:DE registers (24-bit). + Although they are stored in memory as a 32-bit value. Hence decrement + the stack pointer, so 2 bytes are left for the contents of A, before + storing the pvParameters value. */ + pxTopOfStack--; + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( uint32_t ) pvParameters; + pxTopOfStack--; + + /* The return address is a 32-bit value. So decrement the stack pointer + in order to make extra room needed to store the correct value. See the + comments above the prvTaskExitError() prototype at the top of this file. */ + pxTopOfStack--; + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( uint32_t ) prvTaskExitError; + pxTopOfStack--; + + /* The task function start address combined with the PSW is also stored + as a 32-bit value. So leave a space for the second two bytes. */ + pxTopOfStack--; + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + + /* An initial value for the AX register. */ + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + } + #else + { + /* The return address, leaving space for the first two bytes of the + 32-bit value. See the comments above the prvTaskExitError() prototype + at the top of this file. */ + pxTopOfStack--; + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( uint32_t ) prvTaskExitError; + pxTopOfStack--; + + /* Task function. Again as it is written as a 32-bit value a space is + left on the stack for the second two bytes. */ + pxTopOfStack--; + + /* Task function start address combined with the PSW. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + + /* The parameter is passed in AX. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + } + #endif + + /* An initial value for the HL register. */ + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + + /* CS and ES registers. */ + *pxTopOfStack = ( StackType_t ) 0x0F00; + pxTopOfStack--; + + /* The remaining general purpose registers DE and BC */ + *pxTopOfStack = ( StackType_t ) 0xDEDE; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBCBC; + pxTopOfStack--; + + /* Finally the critical section nesting count is set to zero when the task + first starts. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack that has been generated so + it can be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( usCriticalNesting == ~0U ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + vApplicationSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + vPortStartFirstTask(); + + /* Execution should not reach here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the RL78 port will get stopped. */ +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RL78/portasm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RL78/portasm.s new file mode 100644 index 0000000..b7e303e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RL78/portasm.s @@ -0,0 +1,84 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +#include "portmacro.h" + + EXTERN _vTaskSwitchContext + EXTERN _xTaskIncrementTick + + EXTERN _interrupt_vector_table + + PUBLIC _vPortYield + PUBLIC _vPortStartFirstTask + PUBLIC _vPortTickISR + +#if !defined(__IASMRL78__) || (__VER__ < 310) + #error "This port requires the IAR Assembler for RL78 version 3.10 or later." +#endif + +;------------------------------------------------------------------------------- +; FreeRTOS yield handler. This is installed as the BRK software interrupt +; handler. +;------------------------------------------------------------------------------- + SECTION `.text`:CODE:ROOT(1) +_vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + RCALL (_vTaskSwitchContext) ; Call the scheduler to select the next task. + portRESTORE_CONTEXT ; Restore the context of the next task to run. + RETB +;------------------------------------------------------------------------------- + + +;------------------------------------------------------------------------------- +; Starts the scheduler by restoring the context of the task that will execute +; first. +;------------------------------------------------------------------------------- + SECTION `.text`:CODE:ROOT(1) +_vPortStartFirstTask: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + RETI ; An interrupt stack frame is used so the + ; task is started using a RETI instruction. +;------------------------------------------------------------------------------- + + +;------------------------------------------------------------------------------- +; FreeRTOS Timer Tick handler. +; This is installed as the interval timer interrupt handler. +;------------------------------------------------------------------------------- + SECTION `.text`:CODE:ROOT(1) +_vPortTickISR: + portSAVE_CONTEXT ; Save the context of the current task. + RCALL (_xTaskIncrementTick) ; Call the timer tick function. + CMPW AX, #0x00 + SKZ + RCALL (_vTaskSwitchContext) ; Call the scheduler to select the next task. + portRESTORE_CONTEXT ; Restore the context of the next task to run. + RETI +;------------------------------------------------------------------------------- + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RL78/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RL78/portmacro.h new file mode 100644 index 0000000..3a983a7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RL78/portmacro.h @@ -0,0 +1,228 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __IAR_SYSTEMS_ICC__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#if __DATA_MODEL__ == __DATA_MODEL_FAR__ && __CODE_MODEL__ == __CODE_MODEL_NEAR__ + #warning This port has not been tested with your selected memory model combination. If a far data model is required it is recommended to also use a far code model. +#endif + +#if __DATA_MODEL__ == __DATA_MODEL_NEAR__ && __CODE_MODEL__ == __CODE_MODEL_FAR__ + #warning This port has not been tested with your selected memory model combination. If a far code model is required it is recommended to also use a far data model. +#endif + +/* Type definitions. */ + +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if __DATA_MODEL__ == __DATA_MODEL_FAR__ + #define portPOINTER_SIZE_TYPE uint32_t +#else + #define portPOINTER_SIZE_TYPE uint16_t +#endif + + +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned int TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() __asm ( "DI" ) +#define portENABLE_INTERRUPTS() __asm ( "EI" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count when leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portNOP() __asm( "NOP" ) +#define portYIELD() __asm( "BRK" ) +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 ) +/*-----------------------------------------------------------*/ + +/* Hardwware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __IAR_SYSTEMS_ICC__ */ + +;//----------------------------------------------------------------------------- +;// The macros below are processed for asm sources which include portmacro.h. +;//----------------------------------------------------------------------------- +#ifdef __IAR_SYSTEMS_ASM__ + +;/* Functions and variables used by this file. */ +;//----------------------------------------------------------------------------- + EXTERN _pxCurrentTCB + EXTERN _usCriticalNesting + +;/* Macro used to declutter calls, depends on the selected code model. */ +;//----------------------------------------------------------------------------- +#if __CODE_MODEL__ == __CODE_MODEL_FAR__ + #define RCALL(X) CALL F:X +#else + #define RCALL(X) CALL X +#endif + + +;/*----------------------------------------------------------------------------- +; * portSAVE_CONTEXT MACRO +; * Saves the context of the general purpose registers, CS and ES (only in __far +; * memory mode) registers the _usCriticalNesting value and the Stack Pointer +; * of the active Task onto the task stack. +; *---------------------------------------------------------------------------*/ +portSAVE_CONTEXT MACRO + PUSH AX ; // Save AX Register to stack. + PUSH HL +#if __CODE_MODEL__ == __CODE_MODEL_FAR__ + MOV A, CS ; // Save CS register. + XCH A, X + MOV A, ES ; // Save ES register. + PUSH AX +#else + MOV A, CS ; // Save CS register. + PUSH AX +#endif + PUSH DE ; // Save the remaining general purpose registers. + PUSH BC + MOVW AX, _usCriticalNesting ; // Save the _usCriticalNesting value. + PUSH AX + MOVW AX, _pxCurrentTCB ; // Save the Task stack pointer. + MOVW HL, AX + MOVW AX, SP + MOVW [HL], AX + ENDM +;//----------------------------------------------------------------------------- + + +;/*----------------------------------------------------------------------------- +; * portRESTORE_CONTEXT MACRO +; * Restores the task Stack Pointer then use this to restore _usCriticalNesting, +; * general purpose registers and the CS and ES (only in __far memory mode) +; * of the selected task from the task stack. +; *---------------------------------------------------------------------------*/ +portRESTORE_CONTEXT MACRO + MOVW AX, _pxCurrentTCB ; // Restore the Task stack pointer. + MOVW HL, AX + MOVW AX, [HL] + MOVW SP, AX + POP AX ; // Restore _usCriticalNesting value. + MOVW _usCriticalNesting, AX + POP BC ; // Restore the necessary general purpose registers. + POP DE +#if __CODE_MODEL__ == __CODE_MODEL_FAR__ + POP AX ; // Restore the ES register. + MOV ES, A + XCH A, X ; // Restore the CS register. + MOV CS, A +#else + POP AX + MOV CS, A ; // Restore CS register. +#endif + POP HL ; // Restore general purpose register HL. + POP AX ; // Restore AX. + ENDM +;//----------------------------------------------------------------------------- + +#endif /* __IAR_SYSTEMS_ASM__ */ + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX100/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX100/port.c new file mode 100644 index 0000000..634f4a1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX100/port.c @@ -0,0 +1,517 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the SH2A port. + *----------------------------------------------------------*/ + +/* Standard C includes. */ +#include "limits.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include "machine.h" + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) + +/* The peripheral clock is divided by this value before being supplying the +CMT. */ +#if ( configUSE_TICKLESS_IDLE == 0 ) + /* If tickless idle is not used then the divisor can be fixed. */ + #define portCLOCK_DIVISOR 8UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 ) + #define portCLOCK_DIVISOR 512UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 ) + #define portCLOCK_DIVISOR 128UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 ) + #define portCLOCK_DIVISOR 32UL +#else + #define portCLOCK_DIVISOR 8UL +#endif + + +/* Keys required to lock and unlock access to certain system registers +respectively. */ +#define portUNLOCK_KEY 0xA50B +#define portLOCK_KEY 0xA500 + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +extern void prvStartFirstTask( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +__interrupt static void prvTickISR( void ); + +/* + * Sets up the periodic ISR used for the RTOS tick using the CMT. + * The application writer can define configSETUP_TICK_INTERRUPT() (in + * FreeRTOSConfig.h) such that their own tick interrupt configuration is used + * in place of prvSetupTimerInterrupt(). + */ +static void prvSetupTimerInterrupt( void ); +#ifndef configSETUP_TICK_INTERRUPT + /* The user has not provided their own tick interrupt configuration so use + the definition in this file (which uses the interval timer). */ + #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt() +#endif /* configSETUP_TICK_INTERRUPT */ + +/* + * Called after the sleep mode registers have been configured, prvSleep() + * executes the pre and post sleep macros, and actually calls the wait + * instruction. + */ +#if configUSE_TICKLESS_IDLE == 1 + static void prvSleep( TickType_t xExpectedIdleTime ); +#endif /* configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +extern void *pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* Calculate how many clock increments make up a single tick period. */ +static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + +#if configUSE_TICKLESS_IDLE == 1 + + /* Holds the maximum number of ticks that can be suppressed - which is + basically how far into the future an interrupt can be generated. Set + during initialisation. This is the maximum possible value that the + compare match register can hold divided by ulMatchValueForOneTick. */ + static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + + /* Flag set from the tick interrupt to allow the sleep processing to know if + sleep mode was exited because of a tick interrupt, or an interrupt + generated by something else. */ + static volatile uint32_t ulTickFlag = pdFALSE; + + /* The CMT counter is stopped temporarily each time it is re-programmed. + The following constant offsets the CMT counter match value by the number of + CMT counts that would typically be missed while the counter was stopped to + compensate for the lost time. The large difference between the divided CMT + clock and the CPU clock means it is likely ulStoppedTimerCompensation will + equal zero - and be optimised away. */ + static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) ); + +#endif + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Offset to end up on 8 byte boundary. */ + pxTopOfStack--; + + /* R0 is not included as it is the stack pointer. */ + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xaaaabbbb; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + /* Leave space for the registers that will get popped from the stack + when the task first starts executing. */ + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate + the tick interrupt. This way the application can decide which + peripheral to use. If tickless mode is used then the default + implementation defined in this file (which uses CMT0) should not be + overridden. */ + configSETUP_TICK_INTERRUPT(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Execution should not reach here as the tasks are now running! + prvSetupTimerInterrupt() is called here to prevent the compiler outputting + a warning about a statically declared function not being referenced in the + case that the application writer has provided their own tick interrupt + configuration routine (and defined configSETUP_TICK_INTERRUPT() such that + their own routine will be called in place of prvSetupTimerInterrupt()). */ + prvSetupTimerInterrupt(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma vector = configTICK_VECTOR +__interrupt static void prvTickISR( void ) +{ + /* Re-enable interrupts. */ + __enable_interrupt(); + + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY ); + + #if configUSE_TICKLESS_IDLE == 1 + { + /* The CPU woke because of a tick. */ + ulTickFlag = pdTRUE; + + /* If this is the first tick since exiting tickless mode then the CMT + compare match value needs resetting. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + } + #endif +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Unlock. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Enable CMT0. */ + MSTP( CMT0 ) = 0; + + /* Lock again. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + + /* Divide the PCLK. */ + #if portCLOCK_DIVISOR == 512 + { + CMT0.CMCR.BIT.CKS = 3; + } + #elif portCLOCK_DIVISOR == 128 + { + CMT0.CMCR.BIT.CKS = 2; + } + #elif portCLOCK_DIVISOR == 32 + { + CMT0.CMCR.BIT.CKS = 1; + } + #elif portCLOCK_DIVISOR == 8 + { + CMT0.CMCR.BIT.CKS = 0; + } + #else + { + #error Invalid portCLOCK_DIVISOR setting + } + #endif + + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + static void prvSleep( TickType_t xExpectedIdleTime ) + { + /* Allow the application to define some pre-sleep processing. */ + configPRE_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING() + means the application defined code has already executed the WAIT + instruction. */ + if( xExpectedIdleTime > 0 ) + { + __wait_for_interrupt(); + } + + /* Allow the application to define some post sleep processing. */ + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount; + eSleepModeStatus eSleepAction; + + /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* Make sure the CMT reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Calculate the reload value required to wait xExpectedIdleTime tick + periods. */ + ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime; + if( ulMatchValue > ulStoppedTimerCompensation ) + { + /* Compensate for the fact that the CMT is going to be stopped + momentarily. */ + ulMatchValue -= ulStoppedTimerCompensation; + } + + /* Stop the CMT momentarily. The time the CMT is stopped for is + accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + /* Critical section using the global interrupt bit as the i bit is + automatically reset by the WAIT instruction. */ + __disable_interrupt(); + + /* The tick flag is set to false before sleeping. If it is true when + sleep mode is exited then sleep mode was probably exited because the + tick was suppressed for the entire xExpectedIdleTime period. */ + ulTickFlag = pdFALSE; + + /* If a context switch is pending then abandon the low power entry as + the context switch might have been pended by an external interrupt that + requires processing. */ + eSleepAction = eTaskConfirmSleepModeStatus(); + if( eSleepAction == eAbortSleep ) + { + /* Restart tick. */ + CMT.CMSTR0.BIT.STR0 = 1; + __enable_interrupt(); + } + else if( eSleepAction == eNoTasksWaitingTimeout ) + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for software standby with all clocks stopped. */ + SYSTEM.SBYCR.BIT.SSBY = 1; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Sleep until something happens. Calling prvSleep() will + automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Restart the CMT. */ + CMT.CMSTR0.BIT.STR0 = 1; + } + else + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for deep sleep mode. */ + SYSTEM.MSTPCRC.BIT.DSLPE = 1; + SYSTEM.MSTPCRA.BIT.MSTPA28 = 1; + SYSTEM.SBYCR.BIT.SSBY = 0; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Adjust the match value to take into account that the current + time slice is already partially complete. */ + ulMatchValue -= ( uint32_t ) CMT0.CMCNT; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* Restart the CMT to count up to the new match value. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Sleep until something happens. Calling prvSleep() will + automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Stop CMT. Again, the time the SysTick is stopped for is + accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + ulCurrentCount = ( uint32_t ) CMT0.CMCNT; + + if( ulTickFlag != pdFALSE ) + { + /* The tick interrupt has already executed, although because + this function is called with the scheduler suspended the actual + tick processing will not occur until after this function has + exited. Reset the match value with whatever remains of this + tick period. */ + ulMatchValue = ulMatchValueForOneTick - ulCurrentCount; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* The tick interrupt handler will already have pended the tick + processing in the kernel. As the pending tick will be + processed as soon as this function exits, the tick value + maintained by the tick is stepped forward by one less than the + time spent sleeping. The actual stepping of the tick appears + later in this function. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + How many complete tick periods passed while the processor was + sleeping? */ + ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick; + + /* The match value is set to whatever fraction of a single tick + period remains. */ + ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick ); + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + } + + /* Restart the CMT so it runs up to the match value. The match value + will get set to the value required to generate exactly one tick period + the next time the CMT interrupt executes. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Wind the tick forward by the number of tick periods that the CPU + remained in a low power state. */ + vTaskStepTick( ulCompleteTickPeriods ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX100/port_asm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX100/port_asm.s new file mode 100644 index 0000000..fcd3cd3 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX100/port_asm.s @@ -0,0 +1,152 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "PriorityDefinitions.h" + + PUBLIC _prvStartFirstTask + PUBLIC ___interrupt_27 + + EXTERN _pxCurrentTCB + EXTERN _vTaskSwitchContext + + RSEG CODE:CODE(4) + +_prvStartFirstTask: + + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15 + + /* R1 to R15 - R0 is not included as it is the SP. */ + POPM R1-R15 + + /* This pops the remaining registers. */ + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + +/* The software interrupt - overwrite the default 'weak' definition. */ +___interrupt_27: + + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across, R15, then PC, then PSW. */ + MOV.L [ R0 ], [ R15 ] + MOV.L 4[ R0 ], 4[ R15 ] + MOV.L 8[ R0 ], 8[ R15 ] + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the accumulator. */ + MVFACHI R15 + PUSH.L R15 + + /* Middle word. */ + MVFACMI R15 + + /* Shifted left as it is restored to the low order word. */ + SHLL #16, R15 + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15 + POP R15 + MVTACHI R15 + POPM R1-R15 + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX100/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX100/portmacro.h new file mode 100644 index 0000000..7798c1c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX100/portmacro.h @@ -0,0 +1,151 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Hardware specifics. */ +#include "machine.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() + +#define portYIELD() \ + __asm volatile \ + ( \ + "MOV.L #0x872E0, R15 \n" \ + "MOV.B #1, [R15] \n" \ + "MOV.L [R15], R15 \n" \ + ::: "R15" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) { portYIELD(); } } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) + +/* Tickless idle/low power functionality. */ +#if configUSE_TICKLESS_IDLE == 1 + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Prevent warnings of undefined behaviour: the order of volatile accesses is +undefined - all warnings have been manually checked and are not an issue, and +the warnings cannot be prevent by code changes without undesirable effects. */ +#pragma diag_suppress=Pa082 + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX100/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX100/readme.txt new file mode 100644 index 0000000..9e89a09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX100/readme.txt @@ -0,0 +1,72 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX600/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX600/port.c new file mode 100644 index 0000000..653fcff --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX600/port.c @@ -0,0 +1,194 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the SH2A port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +extern void prvStartFirstTask( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +__interrupt void vTickISR( void ); + +/*-----------------------------------------------------------*/ + +extern void *pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma vector = configTICK_VECTOR +__interrupt void vTickISR( void ) +{ + /* Re-enable interrupts. */ + __enable_interrupt(); + + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX600/port_asm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX600/port_asm.s new file mode 100644 index 0000000..4b670ff --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX600/port_asm.s @@ -0,0 +1,160 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "PriorityDefinitions.h" + + PUBLIC _prvStartFirstTask + PUBLIC ___interrupt_27 + + EXTERN _pxCurrentTCB + EXTERN _vTaskSwitchContext + + RSEG CODE:CODE(4) + +_prvStartFirstTask: + + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15 + POP R15 + + /* Floating point status word. */ + MVTC R15, FPSW + + /* R1 to R15 - R0 is not included as it is the SP. */ + POPM R1-R15 + + /* This pops the remaining registers. */ + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + +/* The software interrupt - overwrite the default 'weak' definition. */ +___interrupt_27: + + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across, R15, then PC, then PSW. */ + MOV.L [ R0 ], [ R15 ] + MOV.L 4[ R0 ], 4[ R15 ] + MOV.L 8[ R0 ], 8[ R15 ] + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulator. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACHI R15 + PUSH.L R15 + + /* Middle word. */ + MVFACMI R15 + + /* Shifted left as it is restored to the low order word. */ + SHLL #16, R15 + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15 + POP R15 + MVTACHI R15 + POP R15 + MVTC R15, FPSW + POPM R1-R15 + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX600/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX600/portmacro.h new file mode 100644 index 0000000..f6545c7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX600/portmacro.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" +where portITU_SWINTR is the location of the software interrupt register +(0x000872E0). Don't rely on the assembler to select a register, so instead +save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX600/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX600/readme.txt new file mode 100644 index 0000000..9e89a09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX600/readme.txt @@ -0,0 +1,72 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX700v3_DPFPU/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX700v3_DPFPU/port.c new file mode 100644 index 0000000..2027cbf --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX700v3_DPFPU/port.c @@ -0,0 +1,568 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the RXv3 DPFPU port. +*----------------------------------------------------------*/ + +#warning Testing for DFPU support in this port is not yet complete + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DCMR ( ( StackType_t ) 0x00000000 ) +#define portINITIAL_DECNT ( ( StackType_t ) 0x00000001 ) + +/* Tasks are not created with a DPFPU context, but can be given a DPFPU context + * after they have been created. A variable is stored as part of the tasks context + * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or + * any other value if the task does have a DPFPU context. */ +#define portNO_DPFPU_CONTEXT ( ( StackType_t ) 0 ) +#define portHAS_DPFPU_CONTEXT ( ( StackType_t ) 1 ) + +/* The space on the stack required to hold the DPFPU data registers. This is 16 + * 64-bit registers. */ +#define portDPFPU_DATA_REGISTER_WORDS ( 16 * 2 ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +__interrupt void vSoftwareInterruptISR( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +__interrupt void vTickISR( void ); + +/*-----------------------------------------------------------*/ + +/* Saved as part of the task context. If ulPortTaskHasDPFPUContext is non-zero + * then a DPFPU context must be saved and restored for the task. */ +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + StackType_t ulPortTaskHasDPFPUContext = portNO_DPFPU_CONTEXT; + +#endif /* configUSE_TASK_DPFPU_SUPPORT */ + +/* This is accessed by the inline assembler functions so is file scope for + * convenience. */ +extern void * pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= 15; + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 0. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + { + /* The task will start without a DPFPU context. A task that + * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before + * executing any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_DPFPU_CONTEXT; + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + { + /* The task will start with a DPFPU context. Leave enough + * space for the registers - and ensure they are initialised if desired. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1515.1515; /* DR15. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1414.1414; /* DR14. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1313.1313; /* DR13. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1212.1212; /* DR12. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1111.1111; /* DR11. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1010.1010; /* DR10. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 909.0909; /* DR9. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 808.0808; /* DR8. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 707.0707; /* DR7. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 606.0606; /* DR6. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 505.0505; /* DR5. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 404.0404; /* DR4. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 303.0303; /* DR3. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 202.0202; /* DR2. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 101.0101; /* DR1. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 9876.54321;/* DR0. */ + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) ); + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DCMR; /* DCMR. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DPSW; /* DPSW. */ + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 ) + { + /* Omit DPFPU support. */ + } + #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + { + #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined. + } + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + void vPortTaskUsesDPFPU( void ) + { + /* A task is registering the fact that it needs a DPFPU context. Set the + * DPFPU flag (which is saved as part of the task context). */ + ulPortTaskHasDPFPUContext = portHAS_DPFPU_CONTEXT; + } + +#endif /* configUSE_TASK_DPFPU_SUPPORT */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); + + /* The following line is just to prevent the symbol getting optimised away. */ + ( void ) vTaskSwitchContext(); +} +/*-----------------------------------------------------------*/ + +static void prvStartFirstTask( void ) +{ + __asm volatile + ( + + /* When starting the scheduler there is nothing that needs moving to the + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ + "SETPSW U \n"\ + + + /* Obtain the location of the stack associated with which ever task + * pxCurrentTCB is currently pointing to. */ + "MOV.L #_pxCurrentTCB, R15 \n"\ + "MOV.L [R15], R15 \n"\ + "MOV.L [R15], R0 \n"\ + + + /* Restore the registers from the stack of the task pointed to by + * pxCurrentTCB. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* The restored ulPortTaskHasDPFPUContext is to be zero here. + * So, it is never necessary to restore the DPFPU context here. */ + "POP R15 \n"\ + "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n"\ + "MOV.L R15, [R14] \n"\ + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + + /* Restore the DPFPU context. */ + "DPOPM.L DPSW-DECNT \n"\ + "DPOPM.D DR0-DR15 \n"\ + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + "POP R15 \n"\ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n"\ + "POP R15 \n"\ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n"\ + "POP R15 \n"\ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n"\ + "POP R15 \n"\ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n"\ + "POP R15 \n"\ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n"\ + "POP R15 \n"\ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n"\ + "POP R15 \n"\ + + /* Floating point status word. */ + "MVTC R15, FPSW \n"\ + + /* R1 to R15 - R0 is not included as it is the SP. */ + "POPM R1-R15 \n"\ + + /* This pops the remaining registers. */ + "RTE \n"\ + "NOP \n"\ + "NOP \n" + ); +} +/*-----------------------------------------------------------*/ + +#pragma vector = VECT( ICU, SWINT ) +__interrupt void vSoftwareInterruptISR( void ) +{ + __asm volatile + ( + /* Re-enable interrupts. */ + "SETPSW I \n"\ + + + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ + "PUSH.L R15 \n"\ + + /* Read the user stack pointer. */ + "MVFC USP, R15 \n"\ + + /* Move the address down to the data being moved. */ + "SUB #12, R15 \n"\ + "MVTC R15, USP \n"\ + + /* Copy the data across, R15, then PC, then PSW. */ + "MOV.L [ R0 ], [ R15 ] \n"\ + "MOV.L 4[ R0 ], 4[ R15 ] \n"\ + "MOV.L 8[ R0 ], 8[ R15 ] \n"\ + + /* Move the interrupt stack pointer to its new correct position. */ + "ADD #12, R0 \n"\ + + /* All the rest of the registers are saved directly to the user stack. */ + "SETPSW U \n"\ + + /* Save the rest of the general registers (R15 has been saved already). */ + "PUSHM R1-R14 \n"\ + + /* Save the FPSW and accumulators. */ + "MVFC FPSW, R15 \n"\ + "PUSH.L R15 \n"\ + "MVFACGU #0, A1, R15 \n"\ + "PUSH.L R15 \n"\ + "MVFACHI #0, A1, R15 \n"\ + "PUSH.L R15 \n"\ + "MVFACLO #0, A1, R15 \n" /* Low order word. */ \ + "PUSH.L R15 \n"\ + "MVFACGU #0, A0, R15 \n"\ + "PUSH.L R15 \n"\ + "MVFACHI #0, A0, R15 \n"\ + "PUSH.L R15 \n"\ + "MVFACLO #0, A0, R15 \n" /* Low order word. */ \ + "PUSH.L R15 \n"\ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* Does the task have a DPFPU context that needs saving? If + * ulPortTaskHasDPFPUContext is 0 then no. */ + "MOV.L #_ulPortTaskHasDPFPUContext, R15 \n"\ + "MOV.L [R15], R15 \n"\ + "CMP #0, R15 \n"\ + + /* Save the DPFPU context, if any. */ + "BEQ.B __lab1 \n"\ + "DPUSHM.D DR0-DR15 \n"\ + "DPUSHM.L DPSW-DECNT \n"\ + "__lab1: \n"\ + + /* Save ulPortTaskHasDPFPUContext itself. */ + "PUSH.L R15 \n"\ + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + + /* Save the DPFPU context, always. */ + "DPUSHM.D DR0-DR15 \n"\ + "DPUSHM.L DPSW-DECNT \n"\ + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + + /* Save the stack pointer to the TCB. */ + "MOV.L #_pxCurrentTCB, R15 \n"\ + "MOV.L [ R15 ], R15 \n"\ + "MOV.L R0, [ R15 ] \n"\ + + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + * structures are being accessed. */ + "MVTIPL %0 \n"\ + + /* Select the next task to run. */ + "BSR.A _vTaskSwitchContext \n"\ + + /* Reset the interrupt mask as no more data structure access is required. */ + "MVTIPL %1 \n"\ + + + /* Load the stack pointer of the task that is now selected as the Running + * state task from its TCB. */ + "MOV.L #_pxCurrentTCB,R15 \n"\ + "MOV.L [ R15 ], R15 \n"\ + "MOV.L [ R15 ], R0 \n"\ + + + /* Restore the context of the new task. The PSW (Program Status Word) and + * PC will be popped by the RTE instruction. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* Is there a DPFPU context to restore? If the restored + * ulPortTaskHasDPFPUContext is zero then no. */ + "POP R15 \n"\ + "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n"\ + "MOV.L R15, [R14] \n"\ + "CMP #0, R15 \n"\ + + /* Restore the DPFPU context, if any. */ + "BEQ.B __lab2 \n"\ + "DPOPM.L DPSW-DECNT \n"\ + "DPOPM.D DR0-DR15 \n"\ + "__lab2: \n"\ + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + + /* Restore the DPFPU context, always. */ + "DPOPM.L DPSW-DECNT \n"\ + "DPOPM.D DR0-DR15 \n"\ + + #endif /* if( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + "POP R15 \n"\ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n"\ + "POP R15 \n"\ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n"\ + "POP R15 \n"\ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n"\ + "POP R15 \n"\ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n"\ + "POP R15 \n"\ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n"\ + "POP R15 \n"\ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n"\ + "POP R15 \n"\ + "MVTC R15, FPSW \n"\ + "POPM R1-R15 \n"\ + "RTE \n"\ + "NOP \n"\ + "NOP " + portCDT_NO_PARSE( :: ) "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +#pragma vector = _VECT( configTICK_VECTOR ) +__interrupt void vTickISR( void ) +{ + /* Re-enable interrupts. */ + __enable_interrupt(); + + /* Increment the tick, and perform any processing the new tick value + * necessitates. Ensure IPL is at the max syscall value first. */ + __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX700v3_DPFPU/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX700v3_DPFPU/portmacro.h new file mode 100644 index 0000000..69fa6ee --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX700v3_DPFPU/portmacro.h @@ -0,0 +1,196 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + +/* Hardware specifics. */ + #include + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ + #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 + #endif + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will + * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before + * making use of any DPFPU registers. If configUSE_TASK_DPFPU_SUPPORT is set to 2 then + * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has + * no effect. If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care + * of any DPFPU context (even if DPFPU registers are used). */ + #ifndef configUSE_TASK_DPFPU_SUPPORT + #define configUSE_TASK_DPFPU_SUPPORT 1 + #endif + +/*-----------------------------------------------------------*/ + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ + #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ + #define portSTACK_GROWTH -1 + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portNOP() __no_operation() + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ + #define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n"\ + "MOV.L #0x872E0, R10 \n"\ + "MOV.B #0x1, [R10] \n"\ + "CMP [R10].UB, R10 \n"\ + "POP R10 \n"\ + portCDT_NO_PARSE( ::: ) "cc"\ + ) + + #define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 ) + +/* Workaround to reduce errors/warnings caused by e2 studio CDT's INDEXER and CODAN. */ + #ifdef __CDT_PARSER__ + #ifndef __asm + #define __asm asm + #endif + #ifndef __attribute__ + #define __attribute__( ... ) + #endif + #define portCDT_NO_PARSE( token ) + #else + #define portCDT_NO_PARSE( token ) token + #endif + +/* These macros should not be called directly, but through the + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ + #define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) + #ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #endif + +/* Critical nesting counts are stored in the TCB. */ + #define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ + #define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/*-----------------------------------------------------------*/ + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or left undefined) then tasks are + * created without a DPFPU context and must call vPortTaskUsesDPFPU() to give + * themselves a DPFPU context before using any DPFPU instructions. If + * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context + * by default. */ + #if( configUSE_TASK_DPFPU_SUPPORT == 1 ) + void vPortTaskUsesDPFPU( void ); + #else +/* Each task has a DPFPU context already, so define this function away to + * nothing to prevent it being called accidentally. */ + #define vPortTaskUsesDPFPU() + #endif + #define portTASK_USES_DPFPU() vPortTaskUsesDPFPU() + +/* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */ + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU() + +/* Prevent warnings of undefined behaviour: the order of volatile accesses is + * undefined - all warnings have been manually checked and are not an issue, and + * the warnings cannot be prevent by code changes without undesirable effects. */ + #pragma diag_suppress=Pa082 + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX700v3_DPFPU/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX700v3_DPFPU/readme.txt new file mode 100644 index 0000000..9e89a09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RX700v3_DPFPU/readme.txt @@ -0,0 +1,72 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RXv2/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RXv2/port.c new file mode 100644 index 0000000..bcf7e1d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RXv2/port.c @@ -0,0 +1,202 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the SH2A port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +extern void prvStartFirstTask( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +__interrupt void vTickISR( void ); + +/*-----------------------------------------------------------*/ + +extern void *pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 1. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma vector = configTICK_VECTOR +__interrupt void vTickISR( void ) +{ + /* Re-enable interrupts. */ + __enable_interrupt(); + + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RXv2/port_asm.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RXv2/port_asm.s new file mode 100644 index 0000000..84ce508 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RXv2/port_asm.s @@ -0,0 +1,201 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "PriorityDefinitions.h" + + PUBLIC _prvStartFirstTask + PUBLIC ___interrupt_27 + + EXTERN _pxCurrentTCB + EXTERN _vTaskSwitchContext + + RSEG CODE:CODE(4) + +_prvStartFirstTask: + + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + + /* Floating point status word. */ + MVTC R15, FPSW + + /* R1 to R15 - R0 is not included as it is the SP. */ + POPM R1-R15 + + /* This pops the remaining registers. */ + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + +/* The software interrupt - overwrite the default 'weak' definition. */ +___interrupt_27: + + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across, R15, then PC, then PSW. */ + MOV.L [ R0 ], [ R15 ] + MOV.L 4[ R0 ], 4[ R15 ] + MOV.L 8[ R0 ], 8[ R15 ] + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulator. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACGU #0, A1, R15 + PUSH.L R15 + MVFACHI #0, A1, R15 + PUSH.L R15 + /* Low order word. */ + MVFACLO #0, A1, R15 + PUSH.L R15 + MVFACGU #0, A0, R15 + PUSH.L R15 + MVFACHI #0, A0, R15 + PUSH.L R15 + /* Low order word. */ + MVFACLO #0, A0, R15 + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + MVTC R15, FPSW + POPM R1-R15 + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RXv2/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RXv2/portmacro.h new file mode 100644 index 0000000..6a0caff --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RXv2/portmacro.h @@ -0,0 +1,145 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" +where portITU_SWINTR is the location of the software interrupt register +(0x000872E0). Don't rely on the assembler to select a register, so instead +save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Prevent warnings of undefined behaviour: the order of volatile accesses is +undefined - all warnings have been manually checked and are not an issue, and +the warnings cannot be prevent by code changes without undesirable effects. */ +#pragma diag_suppress=Pa082 + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RXv2/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RXv2/readme.txt new file mode 100644 index 0000000..9e89a09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/RXv2/readme.txt @@ -0,0 +1,72 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR71x/ISR_Support.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR71x/ISR_Support.h new file mode 100644 index 0000000..b48841a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR71x/ISR_Support.h @@ -0,0 +1,106 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR71x/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR71x/port.c new file mode 100644 index 0000000..fa0d7e6 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR71x/port.c @@ -0,0 +1,259 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ST STR71x ARM7 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include "wdg.h" +#include "eic.h" + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +#define portMICROS_PER_SECOND 1000000 + +/*-----------------------------------------------------------*/ + +/* Setup the watchdog to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/* Tick interrupt routines for cooperative and preemptive operation +respectively. The preemptive version is not defined as __irq as it is called +from an asm wrapper function. */ +__arm __irq void vPortNonPreemptiveTick( void ); +void vPortPreemptiveTick( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* The cooperative scheduler requires a normal IRQ service routine to +simply increment the system tick. */ +__arm __irq void vPortNonPreemptiveTick( void ) +{ + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + xTaskIncrementTick(); + + /* Clear the interrupt in the watchdog and EIC. */ + WDG->SR = 0x0000; + portCLEAR_EIC(); +} +/*-----------------------------------------------------------*/ + +/* This function is called from an asm wrapper, so does not require the __irq +keyword. */ +void vPortPreemptiveTick( void ) +{ + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Select a new task to execute. */ + vTaskSwitchContext(); + } + + /* Clear the interrupt in the watchdog and EIC. */ + WDG->SR = 0x0000; + portCLEAR_EIC(); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Set the watchdog up to generate a periodic tick. */ + WDG_ECITConfig( DISABLE ); + WDG_CntOnOffConfig( DISABLE ); + WDG_PeriodValueConfig( portMICROS_PER_SECOND / configTICK_RATE_HZ ); + + /* Setup the tick interrupt in the EIC. */ + EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 ); + EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE ); + EIC_IRQConfig( ENABLE ); + WDG_ECITConfig( ENABLE ); + + /* Start the timer - interrupts are actually disabled at this point so + it is safe to do this here. */ + WDG_CntOnOffConfig( ENABLE ); +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR71x/portasm.s79 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR71x/portasm.s79 new file mode 100644 index 0000000..fe220bc --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR71x/portasm.s79 @@ -0,0 +1,77 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + RSEG ICODE:CODE + CODE32 + + EXTERN vPortPreemptiveTick + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + PUBLIC vPortPreemptiveTickISR + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get used if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTickISR: + portSAVE_CONTEXT ; Save the context of the current task. + + LDR R0, =vPortPreemptiveTick ; Increment the tick count - this may wake a task. + MOV lr, pc + BX R0 + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR71x/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR71x/portmacro.h new file mode 100644 index 0000000..188abd6 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR71x/portmacro.h @@ -0,0 +1,122 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* EIC utilities. */ +#define portEIC_CICR_ADDR *( ( uint32_t * ) 0xFFFFF804 ) +#define portEIC_IPR_ADDR *( ( uint32_t * ) 0xFFFFF840 ) +#define portCLEAR_EIC() portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR75x/ISR_Support.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR75x/ISR_Support.h new file mode 100644 index 0000000..b48841a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR75x/ISR_Support.h @@ -0,0 +1,106 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR75x/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR75x/port.c new file mode 100644 index 0000000..32f6ea9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR75x/port.c @@ -0,0 +1,238 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ST STR75x ARM7 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include "75x_tb.h" +#include "75x_eic.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Prescale used on the timer clock when calculating the tick period. */ +#define portPRESCALE 20 + + +/*-----------------------------------------------------------*/ + +/* Setup the TB to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/* Tick interrupt routines for preemptive operation. */ +__arm void vPortPreemptiveTick( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +__arm void vPortPreemptiveTick( void ) +{ + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Select a new task to execute. */ + vTaskSwitchContext(); + } + + TB_ClearITPendingBit( TB_IT_Update ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +EIC_IRQInitTypeDef EIC_IRQInitStructure; +TB_InitTypeDef TB_InitStructure; + + /* Setup the EIC for the TB. */ + EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; + EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel; + EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; + EIC_IRQInit(&EIC_IRQInitStructure); + + /* Setup the TB for the generation of the tick interrupt. */ + TB_InitStructure.TB_Mode = TB_Mode_Timing; + TB_InitStructure.TB_CounterMode = TB_CounterMode_Down; + TB_InitStructure.TB_Prescaler = portPRESCALE - 1; + TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ ); + TB_Init(&TB_InitStructure); + + /* Enable TB Update interrupt */ + TB_ITConfig(TB_IT_Update, ENABLE); + + /* Clear TB Update interrupt pending bit */ + TB_ClearITPendingBit(TB_IT_Update); + + /* Enable TB */ + TB_Cmd(ENABLE); +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR75x/portasm.s79 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR75x/portasm.s79 new file mode 100644 index 0000000..845b8b9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR75x/portasm.s79 @@ -0,0 +1,64 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + RSEG ICODE:CODE + CODE32 + + EXTERN vPortPreemptiveTick + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR75x/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR75x/portmacro.h new file mode 100644 index 0000000..db31fcf --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR75x/portmacro.h @@ -0,0 +1,113 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR91x/ISR_Support.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR91x/ISR_Support.h new file mode 100644 index 0000000..6e5516c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR91x/ISR_Support.h @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR91x/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR91x/port.c new file mode 100644 index 0000000..0a811d3 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR91x/port.c @@ -0,0 +1,422 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ST STR91x ARM9 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include "91x_lib.h" + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configUSE_WATCHDOG_TICK + #error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively. +#endif + +/* Constants required to setup the initial stack. */ +#ifndef _RUN_TASK_IN_ARM_MODE_ + #define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#else + #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#endif + +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +#ifndef abs + #define abs(x) ((x)>0 ? (x) : -(x)) +#endif + +/** + * Toggle a led using the following algorithm: + * if ( GPIO_ReadBit(GPIO9, GPIO_Pin_2) ) + * { + * GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET ); + * } + * else + * { + * GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET ); + * } + * + */ +#define TOGGLE_LED(port,pin) \ + if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET ) \ + { \ + (port)->DR[(pin) <<2] = 0x00; \ + } \ + else \ + { \ + (port)->DR[(pin) <<2] = (pin); \ + } + + +/*-----------------------------------------------------------*/ + +/* Setup the watchdog to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/* Tick interrupt routines for cooperative and preemptive operation +respectively. The preemptive version is not defined as __irq as it is called +from an asm wrapper function. */ +void WDG_IRQHandler( void ); + +/* VIC interrupt default handler. */ +static void prvDefaultHandler( void ); + +#if configUSE_WATCHDOG_TICK == 0 + /* Used to update the OCR timer register */ + static u16 s_nPulseLength; +#endif + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* This function is called from an asm wrapper, so does not require the __irq +keyword. */ +#if configUSE_WATCHDOG_TICK == 1 + + static void prvFindFactors(u32 n, u16 *a, u32 *b) + { + /* This function is copied from the ST STR7 library and is + copyright STMicroelectronics. Reproduced with permission. */ + + u32 b0; + u16 a0; + int32_t err, err_min=n; + + *a = a0 = ((n-1)/65536ul) + 1; + *b = b0 = n / *a; + + for (; *a <= 256; (*a)++) + { + *b = n / *a; + err = (int32_t)*a * (int32_t)*b - (int32_t)n; + if (abs(err) > (*a / 2)) + { + (*b)++; + err = (int32_t)*a * (int32_t)*b - (int32_t)n; + } + if (abs(err) < abs(err_min)) + { + err_min = err; + a0 = *a; + b0 = *b; + if (err == 0) break; + } + } + + *a = a0; + *b = b0; + } + /*-----------------------------------------------------------*/ + + static void prvSetupTimerInterrupt( void ) + { + WDG_InitTypeDef xWdg; + uint16_t a; + uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b; + + /* Configure the watchdog as a free running timer that generates a + periodic interrupt. */ + + SCU_APBPeriphClockConfig( __WDG, ENABLE ); + WDG_DeInit(); + WDG_StructInit(&xWdg); + prvFindFactors( n, &a, &b ); + xWdg.WDG_Prescaler = a - 1; + xWdg.WDG_Preload = b - 1; + WDG_Init( &xWdg ); + WDG_ITConfig(ENABLE); + + /* Configure the VIC for the WDG interrupt. */ + VIC_Config( WDG_ITLine, VIC_IRQ, 10 ); + VIC_ITCmd( WDG_ITLine, ENABLE ); + + /* Install the default handlers for both VIC's. */ + VIC0->DVAR = ( uint32_t ) prvDefaultHandler; + VIC1->DVAR = ( uint32_t ) prvDefaultHandler; + + WDG_Cmd(ENABLE); + } + /*-----------------------------------------------------------*/ + + void WDG_IRQHandler( void ) + { + { + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Select a new task to execute. */ + vTaskSwitchContext(); + } + + /* Clear the interrupt in the watchdog. */ + WDG->SR &= ~0x0001; + } + } + +#else + + static void prvFindFactors(u32 n, u8 *a, u16 *b) + { + /* This function is copied from the ST STR7 library and is + copyright STMicroelectronics. Reproduced with permission. */ + + u16 b0; + u8 a0; + int32_t err, err_min=n; + + + *a = a0 = ((n-1)/256) + 1; + *b = b0 = n / *a; + + for (; *a <= 256; (*a)++) + { + *b = n / *a; + err = (int32_t)*a * (int32_t)*b - (int32_t)n; + if (abs(err) > (*a / 2)) + { + (*b)++; + err = (int32_t)*a * (int32_t)*b - (int32_t)n; + } + if (abs(err) < abs(err_min)) + { + err_min = err; + a0 = *a; + b0 = *b; + if (err == 0) break; + } + } + + *a = a0; + *b = b0; + } + /*-----------------------------------------------------------*/ + + static void prvSetupTimerInterrupt( void ) + { + uint8_t a; + uint16_t b; + uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ; + + TIM_InitTypeDef timer; + + SCU_APBPeriphClockConfig( __TIM23, ENABLE ); + TIM_DeInit(TIM2); + TIM_StructInit(&timer); + prvFindFactors( n, &a, &b ); + + timer.TIM_Mode = TIM_OCM_CHANNEL_1; + timer.TIM_OC1_Modes = TIM_TIMING; + timer.TIM_Clock_Source = TIM_CLK_APB; + timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING; + timer.TIM_Prescaler = a-1; + timer.TIM_Pulse_Level_1 = TIM_HIGH; + timer.TIM_Pulse_Length_1 = s_nPulseLength = b-1; + + TIM_Init (TIM2, &timer); + TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE); + /* Configure the VIC for the WDG interrupt. */ + VIC_Config( TIM2_ITLine, VIC_IRQ, 10 ); + VIC_ITCmd( TIM2_ITLine, ENABLE ); + + /* Install the default handlers for both VIC's. */ + VIC0->DVAR = ( uint32_t ) prvDefaultHandler; + VIC1->DVAR = ( uint32_t ) prvDefaultHandler; + + TIM_CounterCmd(TIM2, TIM_CLEAR); + TIM_CounterCmd(TIM2, TIM_START); + } + /*-----------------------------------------------------------*/ + + void TIM2_IRQHandler( void ) + { + /* Reset the timer counter to avioid overflow. */ + TIM2->OC1R += s_nPulseLength; + + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Select a new task to run. */ + vTaskSwitchContext(); + } + + /* Clear the interrupt in the watchdog. */ + TIM2->SR &= ~TIM_FLAG_OC1; + } + +#endif /* USE_WATCHDOG_TICK */ + +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvDefaultHandler( void ) +{ +} + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR91x/portasm.s79 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR91x/portasm.s79 new file mode 100644 index 0000000..25bd178 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR91x/portasm.s79 @@ -0,0 +1,61 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + MOV lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR91x/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR91x/portmacro.h new file mode 100644 index 0000000..9779c3e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/STR91x/portmacro.h @@ -0,0 +1,115 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() + + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/ISR_Support.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/ISR_Support.h new file mode 100644 index 0000000..5f59b51 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/ISR_Support.h @@ -0,0 +1,150 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +#include "FreeRTOSConfig.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack +#if configDATA_MODE == 1 ; Using the Tiny data model + prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers + sst.w r19,72[ep] + sst.w r18,68[ep] + sst.w r17,64[ep] + sst.w r16,60[ep] + sst.w r15,56[ep] + sst.w r14,52[ep] + sst.w r13,48[ep] + sst.w r12,44[ep] + sst.w r11,40[ep] + sst.w r10,36[ep] + sst.w r9,32[ep] + sst.w r8,28[ep] + sst.w r7,24[ep] + sst.w r6,20[ep] + sst.w r5,16[ep] + sst.w r4,12[ep] +#else ; Using the Small/Large data model + prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers + sst.w r19,68[ep] + sst.w r18,64[ep] + sst.w r17,60[ep] + sst.w r16,56[ep] + sst.w r15,52[ep] + sst.w r14,48[ep] + sst.w r13,44[ep] + sst.w r12,40[ep] + sst.w r11,36[ep] + sst.w r10,32[ep] + sst.w r9,28[ep] + sst.w r8,24[ep] + sst.w r7,20[ep] + sst.w r6,16[ep] + sst.w r5,12[ep] +#endif /* configDATA_MODE */ + sst.w r2,8[ep] + sst.w r1,4[ep] + MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack + ld.w lw1(usCriticalNesting)[r1],r2 + sst.w r2,0[ep] + MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB + ld.w lw1(pxCurrentTCB)[r1],r2 + st.w sp,0[r2] + ENDM + + +portRESTORE_CONTEXT MACRO + + MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address + ld.w lw1(pxCurrentTCB)[r1],sp + MOV sp,r1 + ld.w 0[r1],sp ; load stackpointer + MOV sp,ep ; set stack pointer to element pointer + sld.w 0[ep],r1 ; load usCriticalNesting value from stack + MOVHI hi1(usCriticalNesting),r0,r2 + st.w r1,lw1(usCriticalNesting)[r2] + sld.w 4[ep],r1 ; restore general purpose registers + sld.w 8[ep],r2 +#if configDATA_MODE == 1 ; Using Tiny data model + sld.w 12[ep],r4 + sld.w 16[ep],r5 + sld.w 20[ep],r6 + sld.w 24[ep],r7 + sld.w 28[ep],r8 + sld.w 32[ep],r9 + sld.w 36[ep],r10 + sld.w 40[ep],r11 + sld.w 44[ep],r12 + sld.w 48[ep],r13 + sld.w 52[ep],r14 + sld.w 56[ep],r15 + sld.w 60[ep],r16 + sld.w 64[ep],r17 + sld.w 68[ep],r18 + sld.w 72[ep],r19 + dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30} +#else ; Using Small/Large data model + sld.w 12[ep],r5 + sld.w 16[ep],r6 + sld.w 20[ep],r7 + sld.w 24[ep],r8 + sld.w 28[ep],r9 + sld.w 32[ep],r10 + sld.w 36[ep],r11 + sld.w 40[ep],r12 + sld.w 44[ep],r13 + sld.w 48[ep],r14 + sld.w 52[ep],r15 + sld.w 56[ep],r16 + sld.w 60[ep],r17 + sld.w 64[ep],r18 + sld.w 68[ep],r19 + dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30} +#endif /* configDATA_MODE */ + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI + + ENDM diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/port.c new file mode 100644 index 0000000..2b8c4e5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/port.c @@ -0,0 +1,184 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Critical nesting should be initialised to a non zero value so interrupts don't +accidentally get enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING (( StackType_t ) 10) + +/* The PSW value assigned to tasks when they start to run for the first time. */ +#define portPSW (( StackType_t ) 0x00000000) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Keeps track of the nesting level of critical sections. */ +volatile StackType_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + +/* Sets up the timer to generate the tick interrupt. */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */ + pxTopOfStack--; + *pxTopOfStack = portPSW; /* Initial PSW value */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x20202020; /* Initial Value of R20 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x21212121; /* Initial Value of R21 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R22 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x23232323; /* Initial Value of R23 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x24242424; /* Initial Value of R24 */ + pxTopOfStack--; +#if (__DATA_MODEL__ == 0) || (__DATA_MODEL__ == 1) + *pxTopOfStack = ( StackType_t ) 0x25252525; /* Initial Value of R25 */ + pxTopOfStack--; +#endif /* configDATA_MODE */ + *pxTopOfStack = ( StackType_t ) 0x26262626; /* Initial Value of R26 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x27272727; /* Initial Value of R27 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x28282828; /* Initial Value of R28 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x29292929; /* Initial Value of R29 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x30303030; /* Initial Value of R30 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19191919; /* Initial Value of R19 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x18181818; /* Initial Value of R18 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x17171717; /* Initial Value of R17 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x16161616; /* Initial Value of R16 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15151515; /* Initial Value of R15 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14141414; /* Initial Value of R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13131313; /* Initial Value of R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* Initial Value of R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* Initial Value of R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* Initial Value of R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x99999999; /* Initial Value of R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x88888888; /* Initial Value of R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x77777777; /* Initial Value of R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x66666666; /* Initial Value of R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x55555555; /* Initial Value of R05 */ + pxTopOfStack--; +#if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1 + *pxTopOfStack = ( StackType_t ) 0x44444444; /* Initial Value of R04 */ + pxTopOfStack--; +#endif /* configDATA_MODE */ + *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R02 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 is expected to hold the function parameter*/ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* + * Return a pointer to the top of the stack we have generated so this can + * be stored in the task control block for the task. + */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + vPortStart(); + + /* Should not get here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the V850ES/Fx3 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses + */ +static void prvSetupTimerInterrupt( void ) +{ + TM0CE = 0; /* TMM0 operation disable */ + TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */ + TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */ + + #ifdef __IAR_V850ES_Fx3__ + { + TM0CMP0 = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */ + } + #else + { + TM0CMP0 = (configCPU_CLOCK_HZ / configTICK_RATE_HZ); + } + #endif + + TM0EQIC0 &= 0xF8; + TM0CTL0 = 0x00; + TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */ + TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */ + TM0CE = 1; /* TMM0 operation enable */ +} +/*-----------------------------------------------------------*/ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/portasm.s85 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/portasm.s85 new file mode 100644 index 0000000..eb71a2d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/portasm.s85 @@ -0,0 +1,316 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ +; Note: Select the correct include files for the device used by the application. +#include "FreeRTOSConfig.h" +;------------------------------------------------------------------------------ + +; Functions used by scheduler +;------------------------------------------------------------------------------ + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + +; Variables used by scheduler +;------------------------------------------------------------------------------ + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +; Functions implemented in this file +;------------------------------------------------------------------------------ + PUBLIC vPortYield + PUBLIC vPortStart + +; Security ID definition +;------------------------------------------------------------------------------ +#define CG_SECURITY0 0FFH +#define CG_SECURITY1 0FFH +#define CG_SECURITY2 0FFH +#define CG_SECURITY3 0FFH +#define CG_SECURITY4 0FFH +#define CG_SECURITY5 0FFH +#define CG_SECURITY6 0FFH +#define CG_SECURITY7 0FFH +#define CG_SECURITY8 0FFH +#define CG_SECURITY9 0FFH + +; Tick ISR Prototype +;------------------------------------------------------------------------------ + PUBWEAK `??MD_INTTM0EQ0??INTVEC 640` + PUBLIC MD_INTTM0EQ0 + +MD_INTTM0EQ0 SYMBOL "MD_INTTM0EQ0" +`??MD_INTTM0EQ0??INTVEC 640` SYMBOL "??INTVEC 640", MD_INTTM0EQ0 + +;------------------------------------------------------------------------------ +; portSAVE_CONTEXT MACRO +; Saves the context of the remaining general purpose registers +; and the usCriticalNesting Value of the active Task onto the task stack +; saves stack pointer to the TCB +;------------------------------------------------------------------------------ +portSAVE_CONTEXT MACRO +#if configDATA_MODE == 1 ; Using the Tiny data model + prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers + sst.w r19,72[ep] + sst.w r18,68[ep] + sst.w r17,64[ep] + sst.w r16,60[ep] + sst.w r15,56[ep] + sst.w r14,52[ep] + sst.w r13,48[ep] + sst.w r12,44[ep] + sst.w r11,40[ep] + sst.w r10,36[ep] + sst.w r9,32[ep] + sst.w r8,28[ep] + sst.w r7,24[ep] + sst.w r6,20[ep] + sst.w r5,16[ep] + sst.w r4,12[ep] +#else ; Using the Small/Large data model + prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers + sst.w r19,68[ep] + sst.w r18,64[ep] + sst.w r17,60[ep] + sst.w r16,56[ep] + sst.w r15,52[ep] + sst.w r14,48[ep] + sst.w r13,44[ep] + sst.w r12,40[ep] + sst.w r11,36[ep] + sst.w r10,32[ep] + sst.w r9,28[ep] + sst.w r8,24[ep] + sst.w r7,20[ep] + sst.w r6,16[ep] + sst.w r5,12[ep] +#endif /* configDATA_MODE */ + sst.w r2,8[ep] + sst.w r1,4[ep] + MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack + ld.w lw1(usCriticalNesting)[r1],r2 + sst.w r2,0[ep] + MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB + ld.w lw1(pxCurrentTCB)[r1],r2 + st.w sp,0[r2] + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; portRESTORE_CONTEXT MACRO +; Gets stack pointer from the current TCB +; Restores the context of the usCriticalNesting value and general purpose +; registers of the selected task from the task stack +;------------------------------------------------------------------------------ +portRESTORE_CONTEXT MACRO + MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address + ld.w lw1(pxCurrentTCB)[r1],sp + MOV sp,r1 + ld.w 0[r1],sp ; load stackpointer + MOV sp,ep ; set stack pointer to element pointer + sld.w 0[ep],r1 ; load usCriticalNesting value from stack + MOVHI hi1(usCriticalNesting),r0,r2 + st.w r1,lw1(usCriticalNesting)[r2] + sld.w 4[ep],r1 ; restore general purpose registers + sld.w 8[ep],r2 +#if configDATA_MODE == 1 ; Using Tiny data model + sld.w 12[ep],r4 + sld.w 16[ep],r5 + sld.w 20[ep],r6 + sld.w 24[ep],r7 + sld.w 28[ep],r8 + sld.w 32[ep],r9 + sld.w 36[ep],r10 + sld.w 40[ep],r11 + sld.w 44[ep],r12 + sld.w 48[ep],r13 + sld.w 52[ep],r14 + sld.w 56[ep],r15 + sld.w 60[ep],r16 + sld.w 64[ep],r17 + sld.w 68[ep],r18 + sld.w 72[ep],r19 + dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30} +#else ; Using Small/Large data model + sld.w 12[ep],r5 + sld.w 16[ep],r6 + sld.w 20[ep],r7 + sld.w 24[ep],r8 + sld.w 28[ep],r9 + sld.w 32[ep],r10 + sld.w 36[ep],r11 + sld.w 40[ep],r12 + sld.w 44[ep],r13 + sld.w 48[ep],r14 + sld.w 52[ep],r15 + sld.w 56[ep],r16 + sld.w 60[ep],r17 + sld.w 64[ep],r18 + sld.w 68[ep],r19 + dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30} +#endif /* configDATA_MODE */ + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Restore the context of the first task that is going to run. +; +; Input: NONE +; +; Call: CALL vPortStart +; +; Output: NONE +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortStart: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ld.w 0[sp],lp + ldsr lp,5 ; restore PSW + DI + ld.w 4[sp],lp ; restore LP + ld.w 8[sp],lp ; restore LP + ADD 0x0C,sp ; set SP to right position + EI + jmp [lp] +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Port Yield function to check for a Task switch in the cooperative and +; preemptive mode +; +; Input: NONE +; +; Call: CALL vPortYield +; +; Output: NONE +;------------------------------------------------------------------------------ + + RSEG CODE:CODE +vPortYield: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Perform the necessary steps of the Tick Count Increment and Task Switch +; depending on the chosen kernel configuration +; +; Input: NONE +; +; Call: ISR +; +; Output: NONE +;------------------------------------------------------------------------------ +#if configUSE_PREEMPTION == 1 ; use preemptive kernel mode + +MD_INTTM0EQ0: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl xTaskIncrementTick,lp ; Call the timer tick function. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI +;------------------------------------------------------------------------------ +#else ; use cooperative kernel mode + +MD_INTTM0EQ0: + prepare {lp,ep},8,sp + sst.w r1,4[ep] + sst.w r5,0[ep] + jarl xTaskIncrementTick,lp ; Call the timer tick function. + sld.w 0[ep],r5 + sld.w 4[ep],r1 + dispose 8,{lp,ep} + RETI +#endif /* configUSE_PREEMPTION */ + +;------------------------------------------------------------------------------ + COMMON INTVEC:CODE:ROOT(2) + ORG 640 +`??MD_INTTM0EQ0??INTVEC 640`: + JR MD_INTTM0EQ0 + + RSEG NEAR_ID:CONST:SORT:NOROOT(2) +`?`: + DW 10 + + COMMON INTVEC:CODE:ROOT(2) + ORG 40H +`??vPortYield??INTVEC 40`: + JR vPortYield + +;------------------------------------------------------------------------------ +; set microcontroller security ID + + COMMON INTVEC:CODE:ROOT(2) + ORG 70H +`SECUID`: + DB CG_SECURITY0 + DB CG_SECURITY1 + DB CG_SECURITY2 + DB CG_SECURITY3 + DB CG_SECURITY4 + DB CG_SECURITY5 + DB CG_SECURITY6 + DB CG_SECURITY7 + DB CG_SECURITY8 + DB CG_SECURITY9 + + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/portasm_Fx3.s85 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/portasm_Fx3.s85 new file mode 100644 index 0000000..638f25e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/portasm_Fx3.s85 @@ -0,0 +1,336 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ +; Note: Select the correct include files for the device used by the application. +#include "FreeRTOSConfig.h" +;------------------------------------------------------------------------------ + +; Functions used by scheduler +;------------------------------------------------------------------------------ + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + +; Variables used by scheduler +;------------------------------------------------------------------------------ + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +; Functions implemented in this file +;------------------------------------------------------------------------------ + PUBLIC vPortYield + PUBLIC vPortStart + +; Security ID definition +;------------------------------------------------------------------------------ +#define CG_SECURITY0 0FFH +#define CG_SECURITY1 0FFH +#define CG_SECURITY2 0FFH +#define CG_SECURITY3 0FFH +#define CG_SECURITY4 0FFH +#define CG_SECURITY5 0FFH +#define CG_SECURITY6 0FFH +#define CG_SECURITY7 0FFH +#define CG_SECURITY8 0FFH +#define CG_SECURITY9 0FFH + +; Option Byte definitions +;------------------------------------------------------------------------------ +#define CG_OPTION7A 0x00 +#define CG_OPTION7B 0x04 +#define OPT7C 0x00 +#define OPT7D 0x00 +#define OPT7E 0x00 +#define OPT7F 0x00 + +; Tick ISR Prototype +;------------------------------------------------------------------------------ + PUBWEAK `??MD_INTTM0EQ0??INTVEC 608` + PUBLIC MD_INTTM0EQ0 + +MD_INTTM0EQ0 SYMBOL "MD_INTTM0EQ0" +`??MD_INTTM0EQ0??INTVEC 608` SYMBOL "??INTVEC 608", MD_INTTM0EQ0 + +;------------------------------------------------------------------------------ +; portSAVE_CONTEXT MACRO +; Saves the context of the remaining general purpose registers +; and the usCriticalNesting Value of the active Task onto the task stack +; saves stack pointer to the TCB +;------------------------------------------------------------------------------ +portSAVE_CONTEXT MACRO +#if configDATA_MODE == 1 ; Using the Tiny data model + prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers + sst.w r19,72[ep] + sst.w r18,68[ep] + sst.w r17,64[ep] + sst.w r16,60[ep] + sst.w r15,56[ep] + sst.w r14,52[ep] + sst.w r13,48[ep] + sst.w r12,44[ep] + sst.w r11,40[ep] + sst.w r10,36[ep] + sst.w r9,32[ep] + sst.w r8,28[ep] + sst.w r7,24[ep] + sst.w r6,20[ep] + sst.w r5,16[ep] + sst.w r4,12[ep] +#else ; Using the Small/Large data model + prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers + sst.w r19,68[ep] + sst.w r18,64[ep] + sst.w r17,60[ep] + sst.w r16,56[ep] + sst.w r15,52[ep] + sst.w r14,48[ep] + sst.w r13,44[ep] + sst.w r12,40[ep] + sst.w r11,36[ep] + sst.w r10,32[ep] + sst.w r9,28[ep] + sst.w r8,24[ep] + sst.w r7,20[ep] + sst.w r6,16[ep] + sst.w r5,12[ep] +#endif /* configDATA_MODE */ + sst.w r2,8[ep] + sst.w r1,4[ep] + MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack + ld.w lw1(usCriticalNesting)[r1],r2 + sst.w r2,0[ep] + MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB + ld.w lw1(pxCurrentTCB)[r1],r2 + st.w sp,0[r2] + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; portRESTORE_CONTEXT MACRO +; Gets stack pointer from the current TCB +; Restores the context of the usCriticalNesting value and general purpose +; registers of the selected task from the task stack +;------------------------------------------------------------------------------ +portRESTORE_CONTEXT MACRO + MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address + ld.w lw1(pxCurrentTCB)[r1],sp + MOV sp,r1 + ld.w 0[r1],sp ; load stackpointer + MOV sp,ep ; set stack pointer to element pointer + sld.w 0[ep],r1 ; load usCriticalNesting value from stack + MOVHI hi1(usCriticalNesting),r0,r2 + st.w r1,lw1(usCriticalNesting)[r2] + sld.w 4[ep],r1 ; restore general purpose registers + sld.w 8[ep],r2 +#if configDATA_MODE == 1 ; Using Tiny data model + sld.w 12[ep],r4 + sld.w 16[ep],r5 + sld.w 20[ep],r6 + sld.w 24[ep],r7 + sld.w 28[ep],r8 + sld.w 32[ep],r9 + sld.w 36[ep],r10 + sld.w 40[ep],r11 + sld.w 44[ep],r12 + sld.w 48[ep],r13 + sld.w 52[ep],r14 + sld.w 56[ep],r15 + sld.w 60[ep],r16 + sld.w 64[ep],r17 + sld.w 68[ep],r18 + sld.w 72[ep],r19 + dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30} +#else ; Using Small/Large data model + sld.w 12[ep],r5 + sld.w 16[ep],r6 + sld.w 20[ep],r7 + sld.w 24[ep],r8 + sld.w 28[ep],r9 + sld.w 32[ep],r10 + sld.w 36[ep],r11 + sld.w 40[ep],r12 + sld.w 44[ep],r13 + sld.w 48[ep],r14 + sld.w 52[ep],r15 + sld.w 56[ep],r16 + sld.w 60[ep],r17 + sld.w 64[ep],r18 + sld.w 68[ep],r19 + dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30} +#endif /* configDATA_MODE */ + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Restore the context of the first task that is going to run. +; +; Input: NONE +; +; Call: CALL vPortStart +; +; Output: NONE +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortStart: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ld.w 0[sp],lp + ldsr lp,5 ; restore PSW + DI + ld.w 4[sp],lp ; restore LP + ld.w 8[sp],lp ; restore LP + ADD 0x0C,sp ; set SP to right position + EI + jmp [lp] +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Port Yield function to check for a Task switch in the cooperative and +; preemptive mode +; +; Input: NONE +; +; Call: CALL vPortYield +; +; Output: NONE +;------------------------------------------------------------------------------ + + RSEG CODE:CODE +vPortYield: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Perform the necessary steps of the Tick Count Increment and Task Switch +; depending on the chosen kernel configuration +; +; Input: NONE +; +; Call: ISR +; +; Output: NONE +;------------------------------------------------------------------------------ +#if configUSE_PREEMPTION == 1 ; use preemptive kernel mode + +MD_INTTM0EQ0: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl xTaskIncrementTick,lp ; Call the timer tick function. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI +;------------------------------------------------------------------------------ +#else ; use cooperative kernel mode + +MD_INTTM0EQ0: + prepare {lp,ep},8,sp + sst.w r1,4[ep] + sst.w r5,0[ep] + jarl xTaskIncrementTick,lp ; Call the timer tick function. + sld.w 0[ep],r5 + sld.w 4[ep],r1 + dispose 8,{lp,ep} + RETI +#endif /* configUSE_PREEMPTION */ + +;------------------------------------------------------------------------------ + COMMON INTVEC:CODE:ROOT(2) + ORG 608 +`??MD_INTTM0EQ0??INTVEC 608`: + JR MD_INTTM0EQ0 + + RSEG NEAR_ID:CONST:SORT:NOROOT(2) +`?`: + DW 10 + + COMMON INTVEC:CODE:ROOT(2) + ORG 40H +`??vPortYield??INTVEC 40`: + JR vPortYield + +;------------------------------------------------------------------------------ +; set microcontroller security ID + + COMMON INTVEC:CODE:ROOT(2) + ORG 70H +`SECUID`: + DB CG_SECURITY0 + DB CG_SECURITY1 + DB CG_SECURITY2 + DB CG_SECURITY3 + DB CG_SECURITY4 + DB CG_SECURITY5 + DB CG_SECURITY6 + DB CG_SECURITY7 + DB CG_SECURITY8 + DB CG_SECURITY9 + +;------------------------------------------------------------------------------ +; set microcontroller option bytes + + COMMON INTVEC:CODE:ROOT(2) + ORG 7AH +`OPTBYTES`: + DB CG_OPTION7A + DB CG_OPTION7B + DB OPT7C + DB OPT7D + DB OPT7E + DB OPT7F + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/portasm_Hx2.s85 b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/portasm_Hx2.s85 new file mode 100644 index 0000000..ba96344 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/portasm_Hx2.s85 @@ -0,0 +1,351 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ +; Note: Select the correct include files for the device used by the application. +#include "FreeRTOSConfig.h" +;------------------------------------------------------------------------------ + +; Functions used by scheduler +;------------------------------------------------------------------------------ + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + +; Variables used by scheduler +;------------------------------------------------------------------------------ + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +; Functions implemented in this file +;------------------------------------------------------------------------------ + PUBLIC vPortYield + PUBLIC vPortStart + +; Security ID definition +;------------------------------------------------------------------------------ +#define CG_SECURITY0 0FFH +#define CG_SECURITY1 0FFH +#define CG_SECURITY2 0FFH +#define CG_SECURITY3 0FFH +#define CG_SECURITY4 0FFH +#define CG_SECURITY5 0FFH +#define CG_SECURITY6 0FFH +#define CG_SECURITY7 0FFH +#define CG_SECURITY8 0FFH +#define CG_SECURITY9 0FFH + +; Tick ISR Prototype +;------------------------------------------------------------------------------ + PUBWEAK `??MD_INTTM0EQ0??INTVEC 544` + PUBLIC MD_INTTM0EQ0 + +MD_INTTM0EQ0 SYMBOL "MD_INTTM0EQ0" +`??MD_INTTM0EQ0??INTVEC 544` SYMBOL "??INTVEC 544", MD_INTTM0EQ0 + +;------------------------------------------------------------------------------ +; portSAVE_CONTEXT MACRO +; Saves the context of the remaining general purpose registers +; and the usCriticalNesting Value of the active Task onto the task stack +; saves stack pointer to the TCB +;------------------------------------------------------------------------------ +portSAVE_CONTEXT MACRO +#if configDATA_MODE == 1 ; Using the Tiny data model + prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers + sst.w r19,72[ep] + sst.w r18,68[ep] + sst.w r17,64[ep] + sst.w r16,60[ep] + sst.w r15,56[ep] + sst.w r14,52[ep] + sst.w r13,48[ep] + sst.w r12,44[ep] + sst.w r11,40[ep] + sst.w r10,36[ep] + sst.w r9,32[ep] + sst.w r8,28[ep] + sst.w r7,24[ep] + sst.w r6,20[ep] + sst.w r5,16[ep] + sst.w r4,12[ep] +#else ; Using the Small/Large data model + prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers + sst.w r19,68[ep] + sst.w r18,64[ep] + sst.w r17,60[ep] + sst.w r16,56[ep] + sst.w r15,52[ep] + sst.w r14,48[ep] + sst.w r13,44[ep] + sst.w r12,40[ep] + sst.w r11,36[ep] + sst.w r10,32[ep] + sst.w r9,28[ep] + sst.w r8,24[ep] + sst.w r7,20[ep] + sst.w r6,16[ep] + sst.w r5,12[ep] +#endif /* configDATA_MODE */ + sst.w r2,8[ep] + sst.w r1,4[ep] + MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack + ld.w lw1(usCriticalNesting)[r1],r2 + sst.w r2,0[ep] + MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB + ld.w lw1(pxCurrentTCB)[r1],r2 + st.w sp,0[r2] + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; portRESTORE_CONTEXT MACRO +; Gets stack pointer from the current TCB +; Restores the context of the usCriticalNesting value and general purpose +; registers of the selected task from the task stack +;------------------------------------------------------------------------------ +portRESTORE_CONTEXT MACRO + MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address + ld.w lw1(pxCurrentTCB)[r1],sp + MOV sp,r1 + ld.w 0[r1],sp ; load stackpointer + MOV sp,ep ; set stack pointer to element pointer + sld.w 0[ep],r1 ; load usCriticalNesting value from stack + MOVHI hi1(usCriticalNesting),r0,r2 + st.w r1,lw1(usCriticalNesting)[r2] + sld.w 4[ep],r1 ; restore general purpose registers + sld.w 8[ep],r2 +#if configDATA_MODE == 1 ; Using Tiny data model + sld.w 12[ep],r4 + sld.w 16[ep],r5 + sld.w 20[ep],r6 + sld.w 24[ep],r7 + sld.w 28[ep],r8 + sld.w 32[ep],r9 + sld.w 36[ep],r10 + sld.w 40[ep],r11 + sld.w 44[ep],r12 + sld.w 48[ep],r13 + sld.w 52[ep],r14 + sld.w 56[ep],r15 + sld.w 60[ep],r16 + sld.w 64[ep],r17 + sld.w 68[ep],r18 + sld.w 72[ep],r19 + dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30} +#else ; Using Small/Large data model + sld.w 12[ep],r5 + sld.w 16[ep],r6 + sld.w 20[ep],r7 + sld.w 24[ep],r8 + sld.w 28[ep],r9 + sld.w 32[ep],r10 + sld.w 36[ep],r11 + sld.w 40[ep],r12 + sld.w 44[ep],r13 + sld.w 48[ep],r14 + sld.w 52[ep],r15 + sld.w 56[ep],r16 + sld.w 60[ep],r17 + sld.w 64[ep],r18 + sld.w 68[ep],r19 + dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30} +#endif /* configDATA_MODE */ + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Restore the context of the first task that is going to run. +; +; Input: NONE +; +; Call: CALL vPortStart +; +; Output: NONE +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortStart: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ld.w 0[sp],lp + ldsr lp,5 ; restore PSW + DI + ld.w 4[sp],lp ; restore LP + ld.w 8[sp],lp ; restore LP + ADD 0x0C,sp ; set SP to right position + EI + jmp [lp] +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Port Yield function to check for a Task switch in the cooperative and +; preemptive mode +; +; Input: NONE +; +; Call: CALL vPortYield +; +; Output: NONE +;------------------------------------------------------------------------------ + + RSEG CODE:CODE +vPortYield: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Perform the necessary steps of the Tick Count Increment and Task Switch +; depending on the chosen kernel configuration +; +; Input: NONE +; +; Call: ISR +; +; Output: NONE +;------------------------------------------------------------------------------ +#if configUSE_PREEMPTION == 1 ; use preemptive kernel mode + +MD_INTTM0EQ0: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl xTaskIncrementTick,lp ; Call the timer tick function. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI +;------------------------------------------------------------------------------ +#else ; use cooperative kernel mode + +MD_INTTM0EQ0: + prepare {lp,ep},8,sp + sst.w r1,4[ep] + sst.w r5,0[ep] + jarl xTaskIncrementTick,lp ; Call the timer tick function. + sld.w 0[ep],r5 + sld.w 4[ep],r1 + dispose 8,{lp,ep} + RETI +#endif /* configUSE_PREEMPTION */ + +;------------------------------------------------------------------------------ + COMMON INTVEC:CODE:ROOT(2) + ORG 544 +`??MD_INTTM0EQ0??INTVEC 544`: + JR MD_INTTM0EQ0 + + RSEG NEAR_ID:CONST:SORT:NOROOT(2) +`?`: + DW 10 + + COMMON INTVEC:CODE:ROOT(2) + ORG 40H +`??vPortYield??INTVEC 40`: + JR vPortYield + +;------------------------------------------------------------------------------ +; set microcontroller security ID + + COMMON INTVEC:CODE:ROOT(2) + ORG 70H +`SECUID`: + DB CG_SECURITY0 + DB CG_SECURITY1 + DB CG_SECURITY2 + DB CG_SECURITY3 + DB CG_SECURITY4 + DB CG_SECURITY5 + DB CG_SECURITY6 + DB CG_SECURITY7 + DB CG_SECURITY8 + DB CG_SECURITY9 + + +; set microcontroller Option bytes + + COMMON INTVEC:CODE:ROOT(2) + ORG 122 +`OPTBYTES`: + DB 0xFD + DB 0xFF + DB 0xFF + DB 0xFF + DB 0xFF + DB 0xFF + +#if configOCD_USAGE == 1 + + COMMON INTVEC:CODE:ROOT(4) + ORG 0x230 + PUBLIC ROM_INT2 +ROM_INT2: + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + + + COMMON INTVEC:CODE:ROOT(4) + ORG 0x60 + PUBLIC ROM_INT +ROM_INT: + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + +#endif /* configOCD_USAGE */ + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/portmacro.h new file mode 100644 index 0000000..af6f28f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/IAR/V850ES/portmacro.h @@ -0,0 +1,136 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned int +#define portBASE_TYPE int + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if (configUSE_16_BIT_TICKS==1) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() __asm ( "DI" ) +#define portENABLE_INTERRUPTS() __asm ( "EI" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( UBaseType_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ); +extern void vPortStart( void ); +extern void portSAVE_CONTEXT( void ); +extern void portRESTORE_CONTEXT( void ); +#define portYIELD() __asm ( "trap 0" ) +#define portNOP() __asm ( "NOP" ) +extern void vTaskSwitchContext( void ); +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 ) + +/*-----------------------------------------------------------*/ + +/* Hardwware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Keil/See-also-the-RVDS-directory.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Keil/See-also-the-RVDS-directory.txt new file mode 100644 index 0000000..bd7fab7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Keil/See-also-the-RVDS-directory.txt @@ -0,0 +1 @@ +Nothing to see here. \ No newline at end of file diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC18F/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC18F/port.c new file mode 100644 index 0000000..1747439 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC18F/port.c @@ -0,0 +1,616 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes between V1.2.4 and V1.2.5 + + + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global + interrupt flag setting. Using the two bits defined within + portINITAL_INTERRUPT_STATE was causing the w register to get clobbered + before the test was performed. + +Changes from V1.2.5 + + + Set the interrupt vector address to 0x08. Previously it was at the + incorrect address for compatibility mode of 0x18. + +Changes from V2.1.1 + + + PCLATU and PCLATH are now saved as part of the context. This allows + function pointers to be used within tasks. Thanks to Javier Espeche + for the enhancement. + +Changes from V2.3.1 + + + TABLAT is now saved as part of the task context. + +Changes from V3.2.0 + + + TBLPTRU is now initialised to zero as the MPLAB compiler expects this + value and does not write to the register. +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPLAB library include file. */ +#include "timers.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC port. + *----------------------------------------------------------*/ + +/* Hardware setup for tick. */ +#define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 ) + +/* Initial interrupt enable state for newly created tasks. This value is +copied into INTCON when a task switches in for the first time. */ +#define portINITAL_INTERRUPT_STATE 0xc0 + +/* Just the bit within INTCON for the global interrupt flag. */ +#define portGLOBAL_INTERRUPT_FLAG 0x80 + +/* Constant used for context switch macro when we require the interrupt +enable state to be unchanged when the interrupted task is switched back in. */ +#define portINTERRUPTS_UNCHANGED 0x00 + +/* Some memory areas get saved as part of the task context. These memory +area's get used by the compiler for temporary storage, especially when +performing mathematical operations, or when using 32bit data types. This +constant defines the size of memory area which must be saved. */ +#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* IO port constants. */ +#define portBIT_SET ( ( uint8_t ) 1 ) +#define portBIT_CLEAR ( ( uint8_t ) 0 ) + +/* + * The serial port ISR's are defined in serial.c, but are called from portable + * as they use the same vector as the tick ISR. + */ +void vSerialTxISR( void ); +void vSerialRxISR( void ); + +/* + * Perform hardware setup to enable ticks. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * ISR to maintain the tick, and perform tick context switches if the + * preemptive scheduler is being used. + */ +static void prvTickISR( void ); + +/* + * ISR placed on the low priority vector. This calls the appropriate ISR for + * the actual interrupt. + */ +static void prvLowInterrupt( void ); + +/* + * Macro that pushes all the registers that make up the context of a task onto + * the stack, then saves the new top of stack into the TCB. + * + * If this is called from an ISR then the interrupt enable bits must have been + * set for the ISR to ever get called. Therefore we want to save the INTCON + * register with the enable bits forced to be set - and ucForcedInterruptFlags + * must contain these bit settings. This means the interrupts will again be + * enabled when the interrupted task is switched back in. + * + * If this is called from a manual context switch (i.e. from a call to yield), + * then we want to save the INTCON so it is restored with its current state, + * and ucForcedInterruptFlags must be 0. This allows a yield from within + * a critical section. + * + * The compiler uses some locations at the bottom of the memory for temporary + * storage during math and other computations. This is especially true if + * 32bit data types are utilised (as they are by the scheduler). The .tmpdata + * and MATH_DATA sections have to be stored in there entirety as part of a task + * context. This macro stores from data address 0x00 to + * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo + * applications but you should check the map file for your project to ensure + * this is sufficient for your needs. It is not clear whether this size is + * fixed for all compilations or has the potential to be program specific. + */ +#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \ +{ \ + _asm \ + /* Save the status and WREG registers first, as these will get modified \ + by the operations below. */ \ + MOVFF WREG, PREINC1 \ + MOVFF STATUS, PREINC1 \ + /* Save the INTCON register with the appropriate bits forced if \ + necessary - as described above. */ \ + MOVFF INTCON, WREG \ + IORLW ucForcedInterruptFlags \ + MOVFF WREG, PREINC1 \ + _endasm \ + \ + portDISABLE_INTERRUPTS(); \ + \ + _asm \ + /* Store the necessary registers to the stack. */ \ + MOVFF BSR, PREINC1 \ + MOVFF FSR2L, PREINC1 \ + MOVFF FSR2H, PREINC1 \ + MOVFF FSR0L, PREINC1 \ + MOVFF FSR0H, PREINC1 \ + MOVFF TABLAT, PREINC1 \ + MOVFF TBLPTRU, PREINC1 \ + MOVFF TBLPTRH, PREINC1 \ + MOVFF TBLPTRL, PREINC1 \ + MOVFF PRODH, PREINC1 \ + MOVFF PRODL, PREINC1 \ + MOVFF PCLATU, PREINC1 \ + MOVFF PCLATH, PREINC1 \ + /* Store the .tempdata and MATH_DATA areas as described above. */ \ + CLRF FSR0L, 0 \ + CLRF FSR0H, 0 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF INDF0, PREINC1 \ + MOVFF FSR0L, PREINC1 \ + MOVFF FSR0H, PREINC1 \ + /* Store the hardware stack pointer in a temp register before we \ + modify it. */ \ + MOVFF STKPTR, FSR0L \ + _endasm \ + \ + /* Store each address from the hardware stack. */ \ + while( STKPTR > ( uint8_t ) 0 ) \ + { \ + _asm \ + MOVFF TOSL, PREINC1 \ + MOVFF TOSH, PREINC1 \ + MOVFF TOSU, PREINC1 \ + POP \ + _endasm \ + } \ + \ + _asm \ + /* Store the number of addresses on the hardware stack (from the \ + temporary register). */ \ + MOVFF FSR0L, PREINC1 \ + MOVF PREINC1, 1, 0 \ + _endasm \ + \ + /* Save the new top of the software stack in the TCB. */ \ + _asm \ + MOVFF pxCurrentTCB, FSR0L \ + MOVFF pxCurrentTCB + 1, FSR0H \ + MOVFF FSR1L, POSTINC0 \ + MOVFF FSR1H, POSTINC0 \ + _endasm \ +} +/*-----------------------------------------------------------*/ + +/* + * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more + * details. + */ +#define portRESTORE_CONTEXT() \ +{ \ + _asm \ + /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \ + MOVFF pxCurrentTCB, FSR0L \ + MOVFF pxCurrentTCB + 1, FSR0H \ + \ + /* De-reference FSR0 to set the address it holds into FSR1. \ + (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \ + MOVFF POSTINC0, FSR1L \ + MOVFF POSTINC0, FSR1H \ + \ + /* How many return addresses are there on the hardware stack? Discard \ + the first byte as we are pointing to the next free space. */ \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, FSR0L \ + _endasm \ + \ + /* Fill the hardware stack from our software stack. */ \ + STKPTR = 0; \ + \ + while( STKPTR < FSR0L ) \ + { \ + _asm \ + PUSH \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSU, 0 \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSH, 0 \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSL, 0 \ + _endasm \ + } \ + \ + _asm \ + /* Restore the .tmpdata and MATH_DATA memory. */ \ + MOVFF POSTDEC1, FSR0H \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, INDF0 \ + /* Restore the other registers forming the tasks context. */ \ + MOVFF POSTDEC1, PCLATH \ + MOVFF POSTDEC1, PCLATU \ + MOVFF POSTDEC1, PRODL \ + MOVFF POSTDEC1, PRODH \ + MOVFF POSTDEC1, TBLPTRL \ + MOVFF POSTDEC1, TBLPTRH \ + MOVFF POSTDEC1, TBLPTRU \ + MOVFF POSTDEC1, TABLAT \ + MOVFF POSTDEC1, FSR0H \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, FSR2H \ + MOVFF POSTDEC1, FSR2L \ + MOVFF POSTDEC1, BSR \ + /* The next byte is the INTCON register. Read this into WREG as some \ + manipulation is required. */ \ + MOVFF POSTDEC1, WREG \ + _endasm \ + \ + /* From the INTCON register, only the interrupt enable bits form part \ + of the tasks context. It is perfectly legitimate for another task to \ + have modified any other bits. We therefore only restore the top two bits. \ + */ \ + if( WREG & portGLOBAL_INTERRUPT_FLAG ) \ + { \ + _asm \ + MOVFF POSTDEC1, STATUS \ + MOVFF POSTDEC1, WREG \ + /* Return enabling interrupts. */ \ + RETFIE 0 \ + _endasm \ + } \ + else \ + { \ + _asm \ + MOVFF POSTDEC1, STATUS \ + MOVFF POSTDEC1, WREG \ + /* Return without effecting interrupts. The context may have \ + been saved from a critical region. */ \ + RETURN 0 \ + _endasm \ + } \ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint32_t ulAddress; +uint8_t ucBlock; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11; + pxTopOfStack++; + *pxTopOfStack = 0x22; + pxTopOfStack++; + *pxTopOfStack = 0x33; + pxTopOfStack++; + + + /* Simulate how the stack would look after a call to vPortYield() generated + by the compiler. + + First store the function parameters. This is where the task will expect to + find them when it starts running. */ + ulAddress = ( uint32_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff ); + pxTopOfStack++; + + ulAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff ); + pxTopOfStack++; + + /* Next we just leave a space. When a context is saved the stack pointer + is incremented before it is used so as not to corrupt whatever the stack + pointer is actually pointing to. This is especially necessary during + function epilogue code generated by the compiler. */ + *pxTopOfStack = 0x44; + pxTopOfStack++; + + /* Next are all the registers that form part of the task context. */ + + *pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */ + pxTopOfStack++; + + /* INTCON is saved with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */ + pxTopOfStack++; + + /* Next the .tmpdata and MATH_DATA sections. */ + for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ ) + { + *pxTopOfStack = ( StackType_t ) ucBlock; + *pxTopOfStack++; + } + + /* Store the top of the global data section. */ + *pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x00; /* High. */ + pxTopOfStack++; + + /* The only function return address so far is the address of the + task. */ + ulAddress = ( uint32_t ) pxCode; + + /* TOS low. */ + *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff ); + pxTopOfStack++; + ulAddress >>= 8; + + /* TOS high. */ + *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff ); + pxTopOfStack++; + ulAddress >>= 8; + + /* TOS even higher. */ + *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff ); + pxTopOfStack++; + + /* Store the number of return addresses on the hardware stack - so far only + the address of the task entry point. */ + *pxTopOfStack = ( StackType_t ) 1; + pxTopOfStack++; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup a timer for the tick ISR is using the preemptive scheduler. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task to run. */ + portRESTORE_CONTEXT(); + + /* Should not get here. Use the function name to stop compiler warnings. */ + ( void ) prvLowInterrupt; + ( void ) prvTickISR; + + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the scheduler for the PIC port will get stopped + once running. If required disable the tick interrupt here, then return + to xPortStartScheduler(). */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. This is similar to the tick context switch, + * but does not increment the tick count. It must be identical to the + * tick context switch in how it stores the stack of a task. + */ +void vPortYield( void ) +{ + /* This can get called with interrupts either enabled or disabled. We + will save the INTCON register with the interrupt enable bits unmodified. */ + portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED ); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Start executing the task we have just switched to. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Vector for ISR. Nothing here must alter any registers! + */ +#pragma code high_vector=0x08 +static void prvLowInterrupt( void ) +{ + /* Was the interrupt the tick? */ + if( PIR1bits.CCP1IF ) + { + _asm + goto prvTickISR + _endasm + } + + /* Was the interrupt a byte being received? */ + if( PIR1bits.RCIF ) + { + _asm + goto vSerialRxISR + _endasm + } + + /* Was the interrupt the Tx register becoming empty? */ + if( PIR1bits.TXIF ) + { + if( PIE1bits.TXIE ) + { + _asm + goto vSerialTxISR + _endasm + } + } +} +#pragma code + +/*-----------------------------------------------------------*/ + +/* + * ISR for the tick. + * This increments the tick count and, if using the preemptive scheduler, + * performs a context switch. This must be identical to the manual + * context switch in how it stores the context of a task. + */ +static void prvTickISR( void ) +{ + /* Interrupts must have been enabled for the ISR to fire, so we have to + save the context with interrupts enabled. */ + portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG ); + PIR1bits.CCP1IF = 0; + + /* Maintain the tick count. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + } + + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. + */ +static void prvSetupTimerInterrupt( void ) +{ +const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ ); +uint32_t ulCompareValue; +uint8_t ucByte; + + /* Interrupts are disabled when this function is called. + + Setup CCP1 to provide the tick interrupt using a compare match on timer + 1. + + Clear the time count then setup timer. */ + TMR1H = ( uint8_t ) 0x00; + TMR1L = ( uint8_t ) 0x00; + + /* Set the compare match value. */ + ulCompareValue = ulConstCompareValue; + CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff ); + ulCompareValue >>= ( uint32_t ) 8; + CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff ); + + CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */ + CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */ + CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */ + CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */ + PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */ + + /* We are only going to use the global interrupt bit, so set the peripheral + bit to true. */ + INTCONbits.GIEL = portBIT_SET; + + /* Provided library function for setting up the timer that will produce the + tick. */ + OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 ); +} + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC18F/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC18F/portmacro.h new file mode 100644 index 0000000..81f092f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC18F/portmacro.h @@ -0,0 +1,113 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portGLOBAL_INT_ENABLE_BIT 0x80 +#define portSTACK_GROWTH 1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() INTCONbits.GIEH = 0; +#define portENABLE_INTERRUPTS() INTCONbits.GIEH = 1; + +/* Push the INTCON register onto the stack, then disable interrupts. */ +#define portENTER_CRITICAL() POSTINC1 = INTCON; \ + INTCONbits.GIEH = 0; + +/* Retrieve the INTCON register from the stack, and enable interrupts +if they were saved as being enabled. Don't modify any other bits +within the INTCON register as these may have lagitimately have been +modified within the critical region. */ +#define portEXIT_CRITICAL() _asm \ + MOVF POSTDEC1, 1, 0 \ + _endasm \ + if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \ + { \ + portENABLE_INTERRUPTS(); \ + } +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +/* Required by the kernel aware debugger. */ +#ifdef __DEBUG + #define portREMOVE_STATIC_QUALIFIER +#endif + + +#define portNOP() _asm \ + NOP \ + _endasm + +#endif /* PORTMACRO_H */ + diff --git a/nxpvee-mimxrt595-evk-round-apps/src/main/resources/.gitkeep b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC18F/stdio.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-apps/src/main/resources/.gitkeep rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC18F/stdio.h diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC24_dsPIC/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC24_dsPIC/port.c new file mode 100644 index 0000000..e0a1298 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC24_dsPIC/port.c @@ -0,0 +1,334 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + Changes from V4.2.1 + + + Introduced the configKERNEL_INTERRUPT_PRIORITY definition. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC24 port. + *----------------------------------------------------------*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware specifics. */ +#define portBIT_SET 1 +#define portTIMER_PRESCALE 8 +#define portINITIAL_SR 0 + +/* Defined for backward compatability with project created prior to +FreeRTOS.org V4.3.0. */ +#ifndef configKERNEL_INTERRUPT_PRIORITY + #define configKERNEL_INTERRUPT_PRIORITY 1 +#endif + +/* Use _T1Interrupt as the interrupt handler name if the application writer has +not provided their own. */ +#ifndef configTICK_INTERRUPT_HANDLER + #define configTICK_INTERRUPT_HANDLER _T1Interrupt +#endif /* configTICK_INTERRUPT_HANDLER */ + +/* The program counter is only 23 bits. */ +#define portUNUSED_PR_BITS 0x7f + +/* Records the nesting depth of calls to portENTER_CRITICAL(). */ +UBaseType_t uxCriticalNesting = 0xef; + +#if configKERNEL_INTERRUPT_PRIORITY != 1 + #error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 ) +#endif + +#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) + + #ifdef __HAS_EDS__ + #define portRESTORE_CONTEXT() \ + asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ + "MOV [W0], W15 \n" \ + "POP W0 \n" /* Restore the critical nesting counter for the task. */ \ + "MOV W0, _uxCriticalNesting \n" \ + "POP DSWPAG \n" \ + "POP DSRPAG \n" \ + "POP CORCON \n" \ + "POP TBLPAG \n" \ + "POP RCOUNT \n" /* Restore the registers from the stack. */ \ + "POP W14 \n" \ + "POP.D W12 \n" \ + "POP.D W10 \n" \ + "POP.D W8 \n" \ + "POP.D W6 \n" \ + "POP.D W4 \n" \ + "POP.D W2 \n" \ + "POP.D W0 \n" \ + "POP SR " ); + #else /* __HAS_EDS__ */ + #define portRESTORE_CONTEXT() \ + asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ + "MOV [W0], W15 \n" \ + "POP W0 \n" /* Restore the critical nesting counter for the task. */ \ + "MOV W0, _uxCriticalNesting \n" \ + "POP PSVPAG \n" \ + "POP CORCON \n" \ + "POP TBLPAG \n" \ + "POP RCOUNT \n" /* Restore the registers from the stack. */ \ + "POP W14 \n" \ + "POP.D W12 \n" \ + "POP.D W10 \n" \ + "POP.D W8 \n" \ + "POP.D W6 \n" \ + "POP.D W4 \n" \ + "POP.D W2 \n" \ + "POP.D W0 \n" \ + "POP SR " ); + #endif /* __HAS_EDS__ */ +#endif /* defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) */ + +#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) + + #define portRESTORE_CONTEXT() \ + asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ + "MOV [W0], W15 \n" \ + "POP W0 \n" /* Restore the critical nesting counter for the task. */ \ + "MOV W0, _uxCriticalNesting \n" \ + "POP PSVPAG \n" \ + "POP CORCON \n" \ + "POP DOENDH \n" \ + "POP DOENDL \n" \ + "POP DOSTARTH \n" \ + "POP DOSTARTL \n" \ + "POP DCOUNT \n" \ + "POP ACCBU \n" \ + "POP ACCBH \n" \ + "POP ACCBL \n" \ + "POP ACCAU \n" \ + "POP ACCAH \n" \ + "POP ACCAL \n" \ + "POP TBLPAG \n" \ + "POP RCOUNT \n" /* Restore the registers from the stack. */ \ + "POP W14 \n" \ + "POP.D W12 \n" \ + "POP.D W10 \n" \ + "POP.D W8 \n" \ + "POP.D W6 \n" \ + "POP.D W4 \n" \ + "POP.D W2 \n" \ + "POP.D W0 \n" \ + "POP SR " ); + +#endif /* defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) */ + +#ifndef portRESTORE_CONTEXT + #error Unrecognised device selected + + /* Note: dsPIC parts with EDS are not supported as there is no easy way to + recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */ +#endif + +/* + * Setup the timer used to generate the tick interrupt. + */ +void vApplicationSetupTickTimerInterrupt( void ); + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint16_t usCode; +UBaseType_t i; + +const StackType_t xInitialStack[] = +{ + 0x1111, /* W1 */ + 0x2222, /* W2 */ + 0x3333, /* W3 */ + 0x4444, /* W4 */ + 0x5555, /* W5 */ + 0x6666, /* W6 */ + 0x7777, /* W7 */ + 0x8888, /* W8 */ + 0x9999, /* W9 */ + 0xaaaa, /* W10 */ + 0xbbbb, /* W11 */ + 0xcccc, /* W12 */ + 0xdddd, /* W13 */ + 0xeeee, /* W14 */ + 0xcdce, /* RCOUNT */ + 0xabac, /* TBLPAG */ + + /* dsPIC specific registers. */ + #if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) + 0x0202, /* ACCAL */ + 0x0303, /* ACCAH */ + 0x0404, /* ACCAU */ + 0x0505, /* ACCBL */ + 0x0606, /* ACCBH */ + 0x0707, /* ACCBU */ + 0x0808, /* DCOUNT */ + 0x090a, /* DOSTARTL */ + 0x1010, /* DOSTARTH */ + 0x1110, /* DOENDL */ + 0x1212, /* DOENDH */ + #endif +}; + + /* Setup the stack as if a yield had occurred. + + Save the low bytes of the program counter. */ + usCode = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) usCode; + pxTopOfStack++; + + /* Save the high byte of the program counter. This will always be zero + here as it is passed in a 16bit pointer. If the address is greater than + 16 bits then the pointer will point to a jump table. */ + *pxTopOfStack = ( StackType_t ) 0; + pxTopOfStack++; + + /* Status register with interrupts enabled. */ + *pxTopOfStack = portINITIAL_SR; + pxTopOfStack++; + + /* Parameters are passed in W0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack++; + + for( i = 0; i < ( sizeof( xInitialStack ) / sizeof( StackType_t ) ); i++ ) + { + *pxTopOfStack = xInitialStack[ i ]; + pxTopOfStack++; + } + + *pxTopOfStack = CORCON; + pxTopOfStack++; + + #if defined(__HAS_EDS__) + *pxTopOfStack = DSRPAG; + pxTopOfStack++; + *pxTopOfStack = DSWPAG; + pxTopOfStack++; + #else /* __HAS_EDS__ */ + *pxTopOfStack = PSVPAG; + pxTopOfStack++; + #endif /* __HAS_EDS__ */ + + /* Finally the critical nesting depth. */ + *pxTopOfStack = 0x00; + pxTopOfStack++; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup a timer for the tick ISR. */ + vApplicationSetupTickTimerInterrupt(); + + /* Restore the context of the first task to run. */ + portRESTORE_CONTEXT(); + + /* Simulate the end of the yield function. */ + asm volatile ( "return" ); + + /* Should not reach here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. + */ +__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void ) +{ +const uint32_t ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1; + + /* Prescale of 8. */ + T1CON = 0; + TMR1 = 0; + + PR1 = ( uint16_t ) ulCompareMatch; + + /* Setup timer 1 interrupt priority. */ + IPC0bits.T1IP = configKERNEL_INTERRUPT_PRIORITY; + + /* Clear the interrupt as a starting condition. */ + IFS0bits.T1IF = 0; + + /* Enable the interrupt. */ + IEC0bits.T1IE = 1; + + /* Setup the prescale value. */ + T1CONbits.TCKPS0 = 1; + T1CONbits.TCKPS1 = 0; + + /* Start the timer. */ + T1CONbits.TON = 1; +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void __attribute__((__interrupt__, auto_psv)) configTICK_INTERRUPT_HANDLER( void ) +{ + /* Clear the timer interrupt. */ + IFS0bits.T1IF = 0; + + if( xTaskIncrementTick() != pdFALSE ) + { + portYIELD(); + } +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S new file mode 100644 index 0000000..17582e9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S @@ -0,0 +1,93 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) + + .global _vPortYield + .extern _vTaskSwitchContext + .extern uxCriticalNesting + +_vPortYield: + + PUSH SR /* Save the SR used by the task.... */ + PUSH W0 /* ....then disable interrupts. */ + MOV #32, W0 + MOV W0, SR + PUSH W1 /* Save registers to the stack. */ + PUSH.D W2 + PUSH.D W4 + PUSH.D W6 + PUSH.D W8 + PUSH.D W10 + PUSH.D W12 + PUSH W14 + PUSH RCOUNT + PUSH TBLPAG + + PUSH CORCON + #ifdef __HAS_EDS__ + PUSH DSRPAG + PUSH DSWPAG + #else + PUSH PSVPAG + #endif /* __HAS_EDS__ */ + MOV _uxCriticalNesting, W0 /* Save the critical nesting counter for the task. */ + PUSH W0 + MOV _pxCurrentTCB, W0 /* Save the new top of stack into the TCB. */ + MOV W15, [W0] + + call _vTaskSwitchContext + + MOV _pxCurrentTCB, W0 /* Restore the stack pointer for the task. */ + MOV [W0], W15 + POP W0 /* Restore the critical nesting counter for the task. */ + MOV W0, _uxCriticalNesting + #ifdef __HAS_EDS__ + POP DSWPAG + POP DSRPAG + #else + POP PSVPAG + #endif /* __HAS_EDS__ */ + POP CORCON + POP TBLPAG + POP RCOUNT /* Restore the registers from the stack. */ + POP W14 + POP.D W12 + POP.D W10 + POP.D W8 + POP.D W6 + POP.D W4 + POP.D W2 + POP.D W0 + POP SR + + return + + .end + +#endif /* defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S new file mode 100644 index 0000000..4458e0e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S @@ -0,0 +1,107 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) + + .global _vPortYield + .extern _vTaskSwitchContext + .extern uxCriticalNesting + +_vPortYield: + + PUSH SR /* Save the SR used by the task.... */ + PUSH W0 /* ....then disable interrupts. */ + MOV #32, W0 + MOV W0, SR + PUSH W1 /* Save registers to the stack. */ + PUSH.D W2 + PUSH.D W4 + PUSH.D W6 + PUSH.D W8 + PUSH.D W10 + PUSH.D W12 + PUSH W14 + PUSH RCOUNT + PUSH TBLPAG + PUSH ACCAL + PUSH ACCAH + PUSH ACCAU + PUSH ACCBL + PUSH ACCBH + PUSH ACCBU + PUSH DCOUNT + PUSH DOSTARTL + PUSH DOSTARTH + PUSH DOENDL + PUSH DOENDH + + + PUSH CORCON + PUSH PSVPAG + MOV _uxCriticalNesting, W0 /* Save the critical nesting counter for the task. */ + PUSH W0 + MOV _pxCurrentTCB, W0 /* Save the new top of stack into the TCB. */ + MOV W15, [W0] + + call _vTaskSwitchContext + + MOV _pxCurrentTCB, W0 /* Restore the stack pointer for the task. */ + MOV [W0], W15 + POP W0 /* Restore the critical nesting counter for the task. */ + MOV W0, _uxCriticalNesting + POP PSVPAG + POP CORCON + POP DOENDH + POP DOENDL + POP DOSTARTH + POP DOSTARTL + POP DCOUNT + POP ACCBU + POP ACCBH + POP ACCBL + POP ACCAU + POP ACCAH + POP ACCAL + POP TBLPAG + POP RCOUNT /* Restore the registers from the stack. */ + POP W14 + POP.D W12 + POP.D W10 + POP.D W8 + POP.D W6 + POP.D W4 + POP.D W2 + POP.D W0 + POP SR + + return + + .end + +#endif /* defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC24_dsPIC/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC24_dsPIC/portmacro.h new file mode 100644 index 0000000..69d6cd2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC24_dsPIC/portmacro.h @@ -0,0 +1,112 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +/* 16-bit tick type on a 16-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH 1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY ); __asm volatile ( "NOP" ) +#define portENABLE_INTERRUPTS() SET_CPU_IPL( 0 ) + +/* Note that exiting a critical sectino will set the IPL bits to 0, nomatter +what their value was prior to entering the critical section. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ); +#define portYIELD() asm volatile ( "CALL _vPortYield \n" \ + "NOP " ); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +/* Required by the kernel aware debugger. */ +#ifdef __DEBUG + #define portREMOVE_STATIC_QUALIFIER +#endif + +#define portNOP() asm volatile ( "NOP" ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MEC14xx/ISR_Support.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MEC14xx/ISR_Support.h new file mode 100644 index 0000000..3349ead --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MEC14xx/ISR_Support.h @@ -0,0 +1,215 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" + +#define portCONTEXT_SIZE 132 +#define portEPC_STACK_LOCATION 124 +#define portSTATUS_STACK_LOCATION 128 + +#ifdef __LANGUAGE_ASSEMBLY__ + +/******************************************************************/ +.macro portSAVE_CONTEXT + + /* Make room for the context. First save the current status so it can be + manipulated, and the cause and EPC registers so their original values are + captured. */ + mfc0 k0, _CP0_CAUSE + addiu sp, sp, -portCONTEXT_SIZE + mfc0 k1, _CP0_STATUS + + /* Also save s6 and s5 so they can be used. Any nesting interrupts should + maintain the values of these registers across the ISR. */ + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + + /* Prepare to enable interrupts above the current priority. + k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */ + srl k0, k0, 0xa + + /* Insert bit field. 7 bits k0[6:0] to k1[16:10] */ + ins k1, k0, 10, 7 + + /* Sets CP0.Status.IPL = CP0.Cause.RIPL + Copy the MSB of the IPL, but it would be an error if it was set anyway. */ + srl k0, k0, 0x7 + + /* MSB of IPL is bit[18] of CP0.Status */ + ins k1, k0, 18, 1 + + /* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM, + b[3]=Rsvd, b[2]=ERL, b[1]=EXL + Setting EXL=0 allows higher priority interrupts + to preempt this handler */ + ins k1, zero, 1, 4 + + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Check the nesting count value. */ + la k0, uxInterruptNesting + lw s6, (k0) + + /* If the nesting count is 0 then swap to the the system stack, otherwise + the system stack is already being used. */ + bne s6, zero, 1f + nop + + /* Swap to the system stack. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Increment and save the nesting count. */ +1: addiu s6, s6, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. No other s registers need be + saved. */ + sw ra, 120(s5) /* Return address (RA=R31) */ + sw s8, 116(s5) /* Frame Pointer (FP=R30) */ + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s6, portEPC_STACK_LOCATION(s5) + sw $1, 16(s5) + + /* MEC14xx does not have DSP, removed 7 words */ + mfhi s6 + sw s6, 12(s5) + mflo s6 + sw s6, 8(s5) + + /* Update the task stack pointer value if nesting is zero. */ + la s6, uxInterruptNesting + lw s6, (s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + + /* Save the stack pointer. */ + la s6, uxSavedTaskStackPointer + sw s5, (s6) +1: + .endm + +/******************************************************************/ +.macro portRESTORE_CONTEXT + + /* Restore the stack pointer from the TCB. This is only done if the + nesting count is 1. */ + la s6, uxInterruptNesting + lw s6, (s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + la s6, uxSavedTaskStackPointer + lw s5, (s6) + + /* Restore the context. + MCHP MEC14xx does not include DSP */ +1: + lw s6, 8(s5) + mtlo s6 + lw s6, 12(s5) + mthi s6 + lw $1, 16(s5) + + /* s6 is loaded as it was used as a scratch register and therefore saved + as part of the interrupt context. */ + lw s6, 44(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Decrement the nesting count. */ + la k0, uxInterruptNesting + lw k1, (k0) + addiu k1, k1, -1 + sw k1, 0(k0) + + lw k0, portSTATUS_STACK_LOCATION(s5) + lw k1, portEPC_STACK_LOCATION(s5) + + /* Leave the stack in its original state. First load sp from s5, then + restore s5 from the stack. */ + add sp, zero, s5 + lw s5, 40(sp) + addiu sp, sp, portCONTEXT_SIZE + + mtc0 k0, _CP0_STATUS + mtc0 k1, _CP0_EPC + ehb + eret + nop + + .endm + +#endif /* #ifdef __LANGUAGE_ASSEMBLY__ */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MEC14xx/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MEC14xx/port.c new file mode 100644 index 0000000..4be946a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MEC14xx/port.c @@ -0,0 +1,346 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC32MEC14xx port. + *----------------------------------------------------------*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Microchip includes. */ +#include +#include + +#if !defined(__MEC__) + #error This port is designed to work with XC32 on MEC14xx. Please update your C compiler version or settings. +#endif + +#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0 +#endif + +/* Bits within various registers. */ +#define portIE_BIT ( 0x00000001 ) +#define portEXL_BIT ( 0x00000002 ) + +/* The EXL bit is set to ensure interrupts do not occur while the context of +the first task is being restored. MEC14xx does not have DSP HW. */ +#define portINITIAL_SR ( portIE_BIT | portEXL_BIT ) + +/* MEC14xx RTOS Timer MMCR's. */ +#define portMMCR_RTMR_PRELOAD *((volatile uint32_t *)(0xA0007404ul)) +#define portMMCR_RTMR_CONTROL *((volatile uint32_t *)(0xA0007408ul)) + +/* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled +peripheral space. */ +#define portGIRQ23_RTOS_TIMER_BITPOS ( 4 ) +#define portGIRQ23_RTOS_TIMER_MASK ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) ) +#define portMMCR_JTVIC_GIRQ23_SRC *((volatile uint32_t *)(0xBFFFC0F0ul)) +#define portMMCR_JTVIC_GIRQ23_SETEN *((volatile uint32_t *)(0xBFFFC0F4ul)) +#define portMMCR_JTVIC_GIRQ23_PRIA *((volatile uint32_t *)(0xBFFFC3F0ul)) + +/* MIPS Software Interrupts are routed through JTVIC GIRQ24 */ +#define portGIRQ24_M14K_SOFTIRQ0_BITPOS ( 1 ) +#define portGIRQ24_M14K_SOFTIRQ0_MASK ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) ) +#define portMMCR_JTVIC_GIRQ24_SRC *((volatile uint32_t *)(0xBFFFC100ul)) +#define portMMCR_JTVIC_GIRQ24_SETEN *((volatile uint32_t *)(0xBFFFC104ul)) +#define portMMCR_JTVIC_GIRQ24_PRIA *((volatile uint32_t *)(0xBFFFC400ul)) + +/* +By default port.c generates its tick interrupt from the RTOS timer. The user +can override this behaviour by: + 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(), + which is the function that configures the timer. The function is defined + as a weak symbol in this file so if the same function name is used in the + application code then the version in the application code will be linked + into the application in preference to the version defined in this file. + 2: Provide a vector implementation in port_asm.S that overrides the default + behaviour for the specified interrupt vector. + 3: Specify the correct bit to clear the interrupt during the timer interrupt + handler. +*/ +#ifndef configTICK_INTERRUPT_VECTOR + #define configTICK_INTERRUPT_VECTOR girq23_b4 + #define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK +#else + #ifndef configCLEAR_TICK_TIMER_INTERRUPT + #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code. + #endif +#endif + +/* Let the user override the pre-loading of the initial RA with the address of +prvTaskExitError() in case it messes up unwinding of the stack in the debugger - +in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task +stack checking. A problem in the ISR stack will trigger an assert, not call the +stack overflow hook function (because the stack overflow hook is specific to a +task stack, not the ISR stack). */ +#if( configCHECK_FOR_STACK_OVERFLOW > 2 ) + + /* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for + the task stacks, and so will legitimately appear in many positions within + the ISR stack. */ + #define portISR_STACK_FILL_BYTE 0xee + + static const uint8_t ucExpectedStackBytes[] = { + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \ + + #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) +#else + /* Define the function away. */ + #define portCHECK_ISR_STACK() +#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + + +/*-----------------------------------------------------------*/ + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Records the interrupt nesting depth. This is initialised to one as it is +decremented to 0 when the first task starts. */ +volatile UBaseType_t uxInterruptNesting = 0x01; + +/* Stores the task stack pointer when a switch is made to use the system stack. */ +UBaseType_t uxSavedTaskStackPointer = 0; + +/* The stack used by interrupt service routines that cause a context switch. */ +StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 }; + +/* The top of stack value ensures there is enough space to store 6 registers on +the callers stack, as some functions seem to want to do this. */ +const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Ensure byte alignment is maintained when leaving this function. */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0xDEADBEEF; + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) ulPortGetCP0Cause(); + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) portINITIAL_SR; /* CP0_STATUS */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */ + pxTopOfStack -= 15; + + *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */ + pxTopOfStack -= 15; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static __inline uint32_t prvDisableInterrupt( void ) +{ +uint32_t prev_state; + + __asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" ); + return prev_state; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxSavedTaskStackPointer == 0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. This function uses the RTOS timer. + * The function is declared weak so an application writer can use a different + * timer by redefining this implementation. If a different timer is used then + * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to + * ensure the RTOS provided tick interrupt handler is installed on the correct + * vector number. + */ +__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void ) +{ +/* MEC14xx RTOS Timer whose input clock is 32KHz. */ +const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) ); + + configASSERT( ulPreload != 0UL ); + + /* Configure the RTOS timer. */ + portMMCR_RTMR_CONTROL = 0ul; + portMMCR_RTMR_PRELOAD = ulPreload; + + /* Configure interrupts from the RTOS timer. */ + portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK ); + portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 ); + portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) ) << 16 ); + portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK ); + + /* Enable the RTOS timer. */ + portMMCR_RTMR_CONTROL = 0x0Fu; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler(void) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxInterruptNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); +extern void *pxCurrentTCB; + + #if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) + { + /* Fill the ISR stack to make it easy to asses how much is being used. */ + memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) ); + } + #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + + /* Clear the software interrupt flag. */ + portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK); + + /* Set software timer priority. Each GIRQn has one nibble containing its + priority */ + portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul); + portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 ); + + /* Enable software interrupt. */ + portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK ); + + /* Setup the timer to generate the tick. Interrupts will have been disabled + by the time we get here. */ + vApplicationSetupTickTimerInterrupt(); + + /* Start the highest priority task that has been created so far. Its stack + location is loaded into uxSavedTaskStackPointer. */ + uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB; + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + exit error function to prevent compiler warnings about a static function + not being called in the case that the application writer overrides this + functionality by defining configTASK_RETURN_ADDRESS. */ + prvTaskExitError(); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortIncrementTick( void ) +{ +UBaseType_t uxSavedStatus; +uint32_t ulCause; + + uxSavedStatus = uxPortSetInterruptMaskFromISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + ulCause = ulPortGetCP0Cause(); + ulCause |= ( 1ul << 8UL ); + vPortSetCP0Cause( ulCause ); + } + } + vPortClearInterruptMaskFromISR( uxSavedStatus ); + + /* Look for the ISR stack getting near or past its limit. */ + portCHECK_ISR_STACK(); + + /* Clear timer interrupt. */ + configCLEAR_TICK_TIMER_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxPortSetInterruptMaskFromISR( void ) +{ +UBaseType_t uxSavedStatusRegister; + + prvDisableInterrupt(); + uxSavedStatusRegister = ulPortGetCP0Status() | 0x01; + + /* This clears the IPL bits, then sets them to + configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called + from an interrupt that has a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action + can only result in the IPL being unchanged or raised, and therefore never + lowered. */ + vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ); + + return uxSavedStatusRegister; +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister ) +{ + vPortSetCP0Status( uxSavedStatusRegister ); +} +/*-----------------------------------------------------------*/ + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MEC14xx/port_asm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MEC14xx/port_asm.S new file mode 100644 index 0000000..292afb2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MEC14xx/port_asm.S @@ -0,0 +1,349 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + +/* Microchip includes. */ +#include +#include + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vPortIncrementTick + .extern xISRStackTop + + PORT_CPP_JTVIC_BASE = 0xBFFFC000 + PORT_CCP_JTVIC_GIRQ24_SRC = 0xBFFFC100 + + .global vPortStartFirstTask .text + .global vPortYieldISR .text + .global vPortTickInterruptHandler .text + + +/******************************************************************/ + + +/*************************************************************** +* The following is needed to locate the +* vPortTickInterruptHandler function into the correct vector +* MEC14xx - This ISR will only be used if HW timers' interrupts +* in GIRQ23 are disaggregated. +* +***************************************************************/ + + .set noreorder + .set noat + .set micromips + + .section .text, code + .ent vPortTickInterruptHandler + +#if configTIMERS_DISAGGREGATED_ISRS == 0 + + .globl girq23_isr + +girq23_isr: +vPortTickInterruptHandler: + + portSAVE_CONTEXT + + jal girq23_handler + nop + + portRESTORE_CONTEXT + +.end vPortTickInterruptHandler + +#else + + .globl girq23_b4 + +girq23_b4: +vPortTickInterruptHandler: + + portSAVE_CONTEXT + + jal vPortIncrementTick + nop + + portRESTORE_CONTEXT + +.end vPortTickInterruptHandler + +#endif /* #if configTIMERS_DISAGGREGATED_ISRS == 0 */ + +/******************************************************************/ + + .set micromips + .set noreorder + .set noat + + .section .text, code + .ent vPortStartFirstTask + +vPortStartFirstTask: + + /* Simply restore the context of the highest priority task that has + been created so far. */ + portRESTORE_CONTEXT + +.end vPortStartFirstTask + + + +/*******************************************************************/ + +/*************************************************************** +* The following is needed to locate the vPortYieldISR function into the correct +* vector. +***************************************************************/ + + .set micromips + .set noreorder + .set noat + + .section .text, code + + .global vPortYieldISR + + +#if configCPU_DISAGGREGATED_ISRS == 0 + .global girq24_isr + .ent girq24_isr +girq24_isr: + la k0, PORT_CPP_JTVIC_BASE + lw k0, 0x10C(k0) + andi k1, k0, 0x2 + bgtz k1, vPortYieldISR + nop + + portSAVE_CONTEXT + + jal girq24_b_0_2 + + portRESTORE_CONTEXT + + .end girq24_isr + +#else + .global girq24_b1 +girq24_b1: +#endif + .ent vPortYieldISR +vPortYieldISR: + + /* Make room for the context. First save the current status so it can be + manipulated, and the cause and EPC registers so thier original values + are captured. */ + addiu sp, sp, -portCONTEXT_SIZE + mfc0 k1, _CP0_STATUS + + /* Also save s6 and s5 so they can be used. Any nesting interrupts should + maintain the values of these registers across the ISR. */ + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + + /* Prepare to re-enable interrupts above the kernel priority. */ + ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */ + ins k1, zero, 18, 1 /* Clear IPL bit 7 */ + ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) + ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */ + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Swap to the system stack. This is not conditional on the nesting + count as this interrupt is always the lowest priority and therefore + the nesting is always 0. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Set the nesting count. */ + la k0, uxInterruptNesting + addiu s6, zero, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved with the rest of the context + after interrupts are enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. */ + sw ra, 120(s5) + sw s8, 116(s5) + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s7, 48(s5) + sw s6, portEPC_STACK_LOCATION(s5) + /* s5 and s6 has already been saved. */ + sw s4, 36(s5) + sw s3, 32(s5) + sw s2, 28(s5) + sw s1, 24(s5) + sw s0, 20(s5) + sw $1, 16(s5) + + /* s7 is used as a scratch register as this should always be saved acro ss + nesting interrupts. */ + mfhi s7 + sw s7, 12(s5) + mflo s7 + sw s7, 8(s5) + + /* Save the stack pointer to the task. */ + la s7, pxCurrentTCB + lw s7, (s7) + sw s5, (s7) + + /* Set the interrupt mask to the max priority that can use the API. + The yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY + which is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only + ever raise the IPL value and never lower it. */ + di + ehb + mfc0 s7, _CP0_STATUS + ins s7, zero, 10, 7 + ins s7, zero, 18, 1 + ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1 + + /* This mtc0 re-enables interrupts, but only above + configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 s6, _CP0_STATUS + ehb + + /* Clear the software interrupt in the core. */ + mfc0 s6, _CP0_CAUSE + ins s6, zero, 8, 1 + mtc0 s6, _CP0_CAUSE + ehb + + /* Clear the interrupt in the interrupt controller. + MEC14xx GIRQ24 Source bit[1] = 1 to clear */ + la s6, PORT_CCP_JTVIC_GIRQ24_SRC + addiu s4, zero, 2 + sw s4, (s6) + jal vTaskSwitchContext + nop + + /* Clear the interrupt mask again. The saved status value is still in s7 */ + mtc0 s7, _CP0_STATUS + ehb + + /* Restore the stack pointer from the TCB. */ + la s0, pxCurrentTCB + lw s0, (s0) + lw s5, (s0) + + /* Restore the rest of the context. */ + lw s0, 8(s5) + mtlo s0 + lw s0, 12(s5) + mthi s0 + + lw $1, 16(s5) + lw s0, 20(s5) + lw s1, 24(s5) + lw s2, 28(s5) + lw s3, 32(s5) + lw s4, 36(s5) + + /* s5 is loaded later. */ + lw s6, 44(s5) + lw s7, 48(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Set nesting back to zero. As the lowest priority interrupt this + interrupt cannot have nested. */ + la k0, uxInterruptNesting + sw zero, 0(k0) + + /* Switch back to use the real stack pointer. */ + add sp, zero, s5 + + /* Restore the real s5 value. */ + lw s5, 40(sp) + + /* Pop the status and epc values. */ + lw k1, portSTATUS_STACK_LOCATION(sp) + lw k0, portEPC_STACK_LOCATION(sp) + + /* Remove stack frame. */ + addiu sp, sp, portCONTEXT_SIZE + + mtc0 k1, _CP0_STATUS + mtc0 k0, _CP0_EPC + ehb + eret + nop + +.end vPortYieldISR + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MEC14xx/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MEC14xx/portmacro.h new file mode 100644 index 0000000..beac82b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MEC14xx/portmacro.h @@ -0,0 +1,250 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portIPL_SHIFT ( 10UL ) +/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should +never have higher IPL bits set anyway. */ +#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT ) +#define portSW0_BIT ( 0x01 << 8 ) + +/* Interrupt priority conversion */ +#define portIPL_TO_CODE( iplNumber ) ( ( iplNumber >> 1 ) & 0x03ul ) +#define portCODE_TO_IPL( iplCode ) ( ( iplCode << 1 ) | 0x01ul ) + +/*-----------------------------------------------------------*/ + +static inline uint32_t ulPortGetCP0Status( void ) +{ +uint32_t rv; + + __asm volatile( + "\n\t" + "mfc0 %0,$12,0 \n\t" + : "=r" ( rv ) :: ); + + return rv; +} +/*-----------------------------------------------------------*/ + +static inline void vPortSetCP0Status( uint32_t new_status) +{ + ( void ) new_status; + + __asm__ __volatile__( + "\n\t" + "mtc0 %0,$12,0 \n\t" + "ehb \n\t" + : + :"r" ( new_status ) : ); +} +/*-----------------------------------------------------------*/ + +static inline uint32_t ulPortGetCP0Cause( void ) +{ +uint32_t rv; + + __asm volatile( + "\n\t" + "mfc0 %0,$13,0 \n\t" + : "=r" ( rv ) :: ); + + return rv; +} +/*-----------------------------------------------------------*/ + +static inline void vPortSetCP0Cause( uint32_t new_cause ) +{ + ( void ) new_cause; + + __asm__ __volatile__( + "\n\t" + "mtc0 %0,$13,0 \n\t" + "ehb \n\t" + : + :"r" ( new_cause ) : ); +} +/*-----------------------------------------------------------*/ + +/* This clears the IPL bits, then sets them to +configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if +configASSERT() is defined to ensure an assertion handler does not inadvertently +attempt to lower the IPL when the call to assert was triggered because the IPL +value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR +safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are +those that end in FromISR. FreeRTOS maintains a separate interrupt API to +ensure API function and interrupt entry is as fast and as simple as possible. */ +#ifdef configASSERT + #define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulStatus; \ + /* Mask interrupts at and below the kernel interrupt priority. */ \ + ulStatus = ulPortGetCP0Status(); \ + /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \ + if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \ + { \ + ulStatus &= ~portALL_IPL_BITS; \ + vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \ + } \ + } +#else /* configASSERT */ + #define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulStatus; \ + /* Mask interrupts at and below the kernel interrupt priority. */ \ + ulStatus = ulPortGetCP0Status(); \ + ulStatus &= ~portALL_IPL_BITS; \ + vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \ + } +#endif /* configASSERT */ + +#define portENABLE_INTERRUPTS() \ +{ \ +uint32_t ulStatus; \ + /* Unmask all interrupts. */ \ + ulStatus = ulPortGetCP0Status(); \ + ulStatus &= ~portALL_IPL_BITS; \ + vPortSetCP0Status( ulStatus ); \ +} + + +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portCRITICAL_NESTING_IN_TCB 1 +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +extern UBaseType_t uxPortSetInterruptMaskFromISR(); +extern void vPortClearInterruptMaskFromISR( UBaseType_t ); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister ) + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) ) + +#endif /* taskRECORD_READY_PRIORITY */ + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +#define portYIELD() \ +{ \ +uint32_t ulCause; \ + /* Trigger software interrupt. */ \ + ulCause = ulPortGetCP0Cause(); \ + ulCause |= portSW0_BIT; \ + vPortSetCP0Cause( ulCause ); \ +} + +extern volatile UBaseType_t uxInterruptNesting; +#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 ) + +#define portNOP() __asm volatile ( "nop" ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) { portYIELD(); } } while( 0 ) + +/* Required by the kernel aware debugger. */ +#ifdef __DEBUG + #define portREMOVE_STATIC_QUALIFIER +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MX/ISR_Support.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MX/ISR_Support.h new file mode 100644 index 0000000..6c624f4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MX/ISR_Support.h @@ -0,0 +1,192 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" + +#define portCONTEXT_SIZE 132 +#define portEPC_STACK_LOCATION 124 +#define portSTATUS_STACK_LOCATION 128 + +/******************************************************************/ +.macro portSAVE_CONTEXT + + /* Make room for the context. First save the current status so it can be + manipulated, and the cause and EPC registers so their original values are + captured. */ + mfc0 k0, _CP0_CAUSE + addiu sp, sp, -portCONTEXT_SIZE + mfc0 k1, _CP0_STATUS + + /* Also save s6 and s5 so they can be used. Any nesting interrupts should + maintain the values of these registers across the ISR. */ + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + + /* Prepare to enable interrupts above the current priority. */ + srl k0, k0, 0xa + ins k1, k0, 10, 6 + ins k1, zero, 1, 4 + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Check the nesting count value. */ + la k0, uxInterruptNesting + lw s6, (k0) + + /* If the nesting count is 0 then swap to the the system stack, otherwise + the system stack is already being used. */ + bne s6, zero, 1f + nop + + /* Swap to the system stack. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Increment and save the nesting count. */ +1: addiu s6, s6, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. No other s registers need be + saved. */ + sw ra, 120(s5) + sw s8, 116(s5) + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s6, portEPC_STACK_LOCATION(s5) + sw $1, 16(s5) + + /* s6 is used as a scratch register. */ + mfhi s6 + sw s6, 12(s5) + mflo s6 + sw s6, 8(s5) + + /* Update the task stack pointer value if nesting is zero. */ + la s6, uxInterruptNesting + lw s6, (s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + + /* Save the stack pointer. */ + la s6, uxSavedTaskStackPointer + sw s5, (s6) +1: + .endm + +/******************************************************************/ +.macro portRESTORE_CONTEXT + + /* Restore the stack pointer from the TCB. This is only done if the + nesting count is 1. */ + la s6, uxInterruptNesting + lw s6, (s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + la s6, uxSavedTaskStackPointer + lw s5, (s6) + + /* Restore the context. */ +1: lw s6, 8(s5) + mtlo s6 + lw s6, 12(s5) + mthi s6 + lw $1, 16(s5) + /* s6 is loaded as it was used as a scratch register and therefore saved + as part of the interrupt context. */ + lw s6, 44(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Decrement the nesting count. */ + la k0, uxInterruptNesting + lw k1, (k0) + addiu k1, k1, -1 + sw k1, 0(k0) + + lw k0, portSTATUS_STACK_LOCATION(s5) + lw k1, portEPC_STACK_LOCATION(s5) + + /* Leave the stack in its original state. First load sp from s5, then + restore s5 from the stack. */ + add sp, zero, s5 + lw s5, 40(sp) + addiu sp, sp, portCONTEXT_SIZE + + mtc0 k0, _CP0_STATUS + mtc0 k1, _CP0_EPC + ehb + eret + nop + + .endm + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MX/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MX/port.c new file mode 100644 index 0000000..d4b5675 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MX/port.c @@ -0,0 +1,335 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC32MX port. + *----------------------------------------------------------*/ + +#ifndef __XC + #error This port is designed to work with XC32. Please update your C compiler version. +#endif + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware specifics. */ +#define portTIMER_PRESCALE 8 +#define portPRESCALE_BITS 1 + +/* Bits within various registers. */ +#define portIE_BIT ( 0x00000001 ) +#define portEXL_BIT ( 0x00000002 ) + +/* Bits within the CAUSE register. */ +#define portCORE_SW_0 ( 0x00000100 ) +#define portCORE_SW_1 ( 0x00000200 ) + +/* The EXL bit is set to ensure interrupts do not occur while the context of +the first task is being restored. */ +#define portINITIAL_SR ( portIE_BIT | portEXL_BIT ) + +/* +By default port.c generates its tick interrupt from TIMER1. The user can +override this behaviour by: + 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(), + which is the function that configures the timer. The function is defined + as a weak symbol in this file so if the same function name is used in the + application code then the version in the application code will be linked + into the application in preference to the version defined in this file. + 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used + to generate the tick interrupt. For example, when timer 1 is used then + configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR. + configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h. + 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the + timer used to generate the tick interrupt. For example, when timer 1 is + used configCLEAR_TICK_TIMER_INTERRUPT() is defined to + IFS0CLR = _IFS0_T1IF_MASK. +*/ +#ifndef configTICK_INTERRUPT_VECTOR + #define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR + #define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK +#else + #ifndef configCLEAR_TICK_TIMER_INTERRUPT + #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code. + #endif +#endif + +/* Let the user override the pre-loading of the initial RA with the address of +prvTaskExitError() in case it messes up unwinding of the stack in the +debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task +stack checking. A problem in the ISR stack will trigger an assert, not call the +stack overflow hook function (because the stack overflow hook is specific to a +task stack, not the ISR stack). */ +#if( configCHECK_FOR_STACK_OVERFLOW > 2 ) + + /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for + the task stacks, and so will legitimately appear in many positions within + the ISR stack. */ + #define portISR_STACK_FILL_BYTE 0xee + + static const uint8_t ucExpectedStackBytes[] = { + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \ + + #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) +#else + /* Define the function away. */ + #define portCHECK_ISR_STACK() +#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + +/*-----------------------------------------------------------*/ + + +/* + * Place the prototype here to ensure the interrupt vector is correctly installed. + * Note that because the interrupt is written in assembly, the IPL setting in the + * following line of code has no effect. The interrupt priority is set by the + * call to ConfigIntTimer1() in vApplicationSetupTickTimerInterrupt(). + */ +extern void __attribute__( (interrupt(IPL1AUTO), vector( configTICK_INTERRUPT_VECTOR ))) vPortTickInterruptHandler( void ); + +/* + * The software interrupt handler that performs the yield. Note that, because + * the interrupt is written in assembly, the IPL setting in the following line of + * code has no effect. The interrupt priority is set by the call to + * mConfigIntCoreSW0() in xPortStartScheduler(). + */ +void __attribute__( (interrupt(IPL1AUTO), vector(_CORE_SOFTWARE_0_VECTOR))) vPortYieldISR( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Records the interrupt nesting depth. This is initialised to one as it is +decremented to 0 when the first task starts. */ +volatile UBaseType_t uxInterruptNesting = 0x01; + +/* Stores the task stack pointer when a switch is made to use the system stack. */ +UBaseType_t uxSavedTaskStackPointer = 0; + +/* The stack used by interrupt service routines that cause a context switch. */ +__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 }; + +/* The top of stack value ensures there is enough space to store 6 registers on +the callers stack, as some functions seem to want to do this. */ +const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Ensure 8 byte alignment is maintained when the context is popped from + * stack. The size of the context is 33 words (132 bytes). */ + pxTopOfStack--; + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0xDEADBEEF; + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) _CP0_GET_CAUSE(); + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */ + pxTopOfStack -= 15; + + *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */ + pxTopOfStack -= 15; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxSavedTaskStackPointer == 0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. This function uses peripheral timer 1. + * The function is declared weak so an application writer can use a different + * timer by redefining this implementation. If a different timer is used then + * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to + * ensure the RTOS provided tick interrupt handler is installed on the correct + * vector number. When Timer 1 is used the vector number is defined as + * _TIMER_1_VECTOR. + */ +__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void ) +{ +const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1; + + T1CON = 0x0000; + T1CONbits.TCKPS = portPRESCALE_BITS; + PR1 = ulCompareMatch; + IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY; + + /* Clear the interrupt as a starting condition. */ + IFS0bits.T1IF = 0; + + /* Enable the interrupt. */ + IEC0bits.T1IE = 1; + + /* Start the timer. */ + T1CONbits.TON = 1; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler(void) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxInterruptNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); +extern void *pxCurrentTCB; + + #if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) + { + /* Fill the ISR stack to make it easy to asses how much is being used. */ + memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) ); + } + #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + + /* Clear the software interrupt flag. */ + IFS0CLR = _IFS0_CS0IF_MASK; + + /* Set software timer priority. */ + IPC0CLR = _IPC0_CS0IP_MASK; + IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION ); + + /* Enable software interrupt. */ + IEC0CLR = _IEC0_CS0IE_MASK; + IEC0SET = 1 << _IEC0_CS0IE_POSITION; + + /* Setup the timer to generate the tick. Interrupts will have been + disabled by the time we get here. */ + vApplicationSetupTickTimerInterrupt(); + + /* Kick off the highest priority task that has been created so far. + Its stack location is loaded into uxSavedTaskStackPointer. */ + uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB; + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + exit error function to prevent compiler warnings about a static function + not being called in the case that the application writer overrides this + functionality by defining configTASK_RETURN_ADDRESS. */ + prvTaskExitError(); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortIncrementTick( void ) +{ +UBaseType_t uxSavedStatus; + + uxSavedStatus = uxPortSetInterruptMaskFromISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + _CP0_BIS_CAUSE( portCORE_SW_0 ); + } + } + vPortClearInterruptMaskFromISR( uxSavedStatus ); + + /* Look for the ISR stack getting near or past its limit. */ + portCHECK_ISR_STACK(); + + /* Clear timer interrupt. */ + configCLEAR_TICK_TIMER_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxPortSetInterruptMaskFromISR( void ) +{ +UBaseType_t uxSavedStatusRegister; + + __builtin_disable_interrupts(); + uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01; + /* This clears the IPL bits, then sets them to + configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called + from an interrupt that has a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action + can only result in the IPL being unchanged or raised, and therefore never + lowered. */ + _CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ); + + return uxSavedStatusRegister; +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister ) +{ + _CP0_SET_STATUS( uxSavedStatusRegister ); +} +/*-----------------------------------------------------------*/ + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MX/port_asm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MX/port_asm.S new file mode 100644 index 0000000..109fdee --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MX/port_asm.S @@ -0,0 +1,269 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include +#include "ISR_Support.h" + + + .set nomips16 + .set noreorder + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vPortIncrementTick + .extern xISRStackTop + + .global vPortStartFirstTask + .global vPortYieldISR + .global vPortTickInterruptHandler + + +/******************************************************************/ + + .set noreorder + .set noat + .ent vPortTickInterruptHandler + +vPortTickInterruptHandler: + + portSAVE_CONTEXT + + jal vPortIncrementTick + nop + + portRESTORE_CONTEXT + + .end vPortTickInterruptHandler + +/******************************************************************/ + + .set noreorder + .set noat + .ent vPortStartFirstTask + +vPortStartFirstTask: + + /* Simply restore the context of the highest priority task that has been + created so far. */ + portRESTORE_CONTEXT + + .end vPortStartFirstTask + + + +/*******************************************************************/ + + .set noreorder + .set noat + .ent vPortYieldISR + +vPortYieldISR: + + /* Make room for the context. First save the current status so it can be + manipulated. */ + addiu sp, sp, -portCONTEXT_SIZE + mfc0 k1, _CP0_STATUS + + /* Also save s6 and s5 so they can be used. Any nesting interrupts should + maintain the values of these registers across the ISR. */ + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + + /* Prepare to re-enabled interrupt above the kernel priority. */ + ins k1, zero, 10, 6 + ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) + ins k1, zero, 1, 4 + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Swap to the system stack. This is not conditional on the nesting + count as this interrupt is always the lowest priority and therefore + the nesting is always 0. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Set the nesting count. */ + la k0, uxInterruptNesting + addiu s6, zero, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved with the rest of the context + after interrupts are enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. */ + sw ra, 120(s5) + sw s8, 116(s5) + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s7, 48(s5) + sw s6, portEPC_STACK_LOCATION(s5) + /* s5 and s6 has already been saved. */ + sw s4, 36(s5) + sw s3, 32(s5) + sw s2, 28(s5) + sw s1, 24(s5) + sw s0, 20(s5) + sw $1, 16(s5) + + /* s7 is used as a scratch register as this should always be saved across + nesting interrupts. */ + mfhi s7 + sw s7, 12(s5) + mflo s7 + sw s7, 8(s5) + + /* Save the stack pointer to the task. */ + la s7, pxCurrentTCB + lw s7, (s7) + sw s5, (s7) + + /* Set the interrupt mask to the max priority that can use the API. The + yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which + is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever + raise the IPL value and never lower it. */ + di + ehb + mfc0 s7, _CP0_STATUS + ins s7, zero, 10, 6 + ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1 + + /* This mtc0 re-enables interrupts, but only above + configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 s6, _CP0_STATUS + ehb + + /* Clear the software interrupt in the core. */ + mfc0 s6, _CP0_CAUSE + ins s6, zero, 8, 1 + mtc0 s6, _CP0_CAUSE + ehb + + /* Clear the interrupt in the interrupt controller. */ + la s6, IFS0CLR + addiu s4, zero, 2 + sw s4, (s6) + + jal vTaskSwitchContext + nop + + /* Clear the interrupt mask again. The saved status value is still in s7. */ + mtc0 s7, _CP0_STATUS + ehb + + /* Restore the stack pointer from the TCB. */ + la s0, pxCurrentTCB + lw s0, (s0) + lw s5, (s0) + + /* Restore the rest of the context. */ + lw s0, 8(s5) + mtlo s0 + lw s0, 12(s5) + mthi s0 + lw $1, 16(s5) + lw s0, 20(s5) + lw s1, 24(s5) + lw s2, 28(s5) + lw s3, 32(s5) + lw s4, 36(s5) + /* s5 is loaded later. */ + lw s6, 44(s5) + lw s7, 48(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Set nesting back to zero. As the lowest priority interrupt this + interrupt cannot have nested. */ + la k0, uxInterruptNesting + sw zero, 0(k0) + + /* Switch back to use the real stack pointer. */ + add sp, zero, s5 + + /* Restore the real s5 value. */ + lw s5, 40(sp) + + /* Pop the status and epc values. */ + lw k1, portSTATUS_STACK_LOCATION(sp) + lw k0, portEPC_STACK_LOCATION(sp) + + /* Remove stack frame. */ + addiu sp, sp, portCONTEXT_SIZE + + mtc0 k1, _CP0_STATUS + mtc0 k0, _CP0_EPC + ehb + eret + nop + + .end vPortYieldISR + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MX/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MX/portmacro.h new file mode 100644 index 0000000..9cc22d1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MX/portmacro.h @@ -0,0 +1,202 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* System include files */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portIPL_SHIFT ( 10UL ) +#define portALL_IPL_BITS ( 0x3fUL << portIPL_SHIFT ) +#define portSW0_BIT ( 0x01 << 8 ) + +/* This clears the IPL bits, then sets them to +configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if +configASSERT() is defined to ensure an assertion handler does not inadvertently +attempt to lower the IPL when the call to assert was triggered because the IPL +value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR +safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are +those that end in FromISR. FreeRTOS maintains a separate interrupt API to +ensure API function and interrupt entry is as fast and as simple as possible. */ +#ifdef configASSERT + #define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulStatus; \ + \ + /* Mask interrupts at and below the kernel interrupt priority. */ \ + ulStatus = _CP0_GET_STATUS(); \ + \ + /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \ + if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \ + { \ + ulStatus &= ~portALL_IPL_BITS; \ + _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \ + } \ + } +#else /* configASSERT */ + #define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulStatus; \ + \ + /* Mask interrupts at and below the kernel interrupt priority. */ \ + ulStatus = _CP0_GET_STATUS(); \ + ulStatus &= ~portALL_IPL_BITS; \ + _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \ + } +#endif /* configASSERT */ + +#define portENABLE_INTERRUPTS() \ +{ \ +uint32_t ulStatus; \ + \ + /* Unmask all interrupts. */ \ + ulStatus = _CP0_GET_STATUS(); \ + ulStatus &= ~portALL_IPL_BITS; \ + _CP0_SET_STATUS( ulStatus ); \ +} + + +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portCRITICAL_NESTING_IN_TCB 1 +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +extern UBaseType_t uxPortSetInterruptMaskFromISR(); +extern void vPortClearInterruptMaskFromISR( UBaseType_t ); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister ) + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) ) + +#endif /* taskRECORD_READY_PRIORITY */ + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +#define portYIELD() \ +{ \ +uint32_t ulCause; \ + \ + /* Trigger software interrupt. */ \ + ulCause = _CP0_GET_CAUSE(); \ + ulCause |= portSW0_BIT; \ + _CP0_SET_CAUSE( ulCause ); \ +} + +extern volatile UBaseType_t uxInterruptNesting; +#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 ) + +#define portNOP() __asm volatile ( "nop" ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) { portYIELD(); } } while( 0 ) + +/* Required by the kernel aware debugger. */ +#ifdef __DEBUG + #define portREMOVE_STATIC_QUALIFIER +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MZ/ISR_Support.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MZ/ISR_Support.h new file mode 100644 index 0000000..0e84909 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MZ/ISR_Support.h @@ -0,0 +1,433 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" + +#define portCONTEXT_SIZE 160 +#define portEPC_STACK_LOCATION 152 +#define portSTATUS_STACK_LOCATION 156 +#define portFPCSR_STACK_LOCATION 0 +#define portTASK_HAS_FPU_STACK_LOCATION 0 +#define portFPU_CONTEXT_SIZE 264 + +/******************************************************************/ +.macro portSAVE_FPU_REGS offset, base + /* Macro to assist with saving just the FPU registers to the + * specified address and base offset, + * offset is a constant, base is the base pointer register */ + + sdc1 $f31, \offset + 248(\base) + sdc1 $f30, \offset + 240(\base) + sdc1 $f29, \offset + 232(\base) + sdc1 $f28, \offset + 224(\base) + sdc1 $f27, \offset + 216(\base) + sdc1 $f26, \offset + 208(\base) + sdc1 $f25, \offset + 200(\base) + sdc1 $f24, \offset + 192(\base) + sdc1 $f23, \offset + 184(\base) + sdc1 $f22, \offset + 176(\base) + sdc1 $f21, \offset + 168(\base) + sdc1 $f20, \offset + 160(\base) + sdc1 $f19, \offset + 152(\base) + sdc1 $f18, \offset + 144(\base) + sdc1 $f17, \offset + 136(\base) + sdc1 $f16, \offset + 128(\base) + sdc1 $f15, \offset + 120(\base) + sdc1 $f14, \offset + 112(\base) + sdc1 $f13, \offset + 104(\base) + sdc1 $f12, \offset + 96(\base) + sdc1 $f11, \offset + 88(\base) + sdc1 $f10, \offset + 80(\base) + sdc1 $f9, \offset + 72(\base) + sdc1 $f8, \offset + 64(\base) + sdc1 $f7, \offset + 56(\base) + sdc1 $f6, \offset + 48(\base) + sdc1 $f5, \offset + 40(\base) + sdc1 $f4, \offset + 32(\base) + sdc1 $f3, \offset + 24(\base) + sdc1 $f2, \offset + 16(\base) + sdc1 $f1, \offset + 8(\base) + sdc1 $f0, \offset + 0(\base) + + .endm + +/******************************************************************/ +.macro portLOAD_FPU_REGS offset, base + /* Macro to assist with loading just the FPU registers from the + * specified address and base offset, offset is a constant, + * base is the base pointer register */ + + ldc1 $f0, \offset + 0(\base) + ldc1 $f1, \offset + 8(\base) + ldc1 $f2, \offset + 16(\base) + ldc1 $f3, \offset + 24(\base) + ldc1 $f4, \offset + 32(\base) + ldc1 $f5, \offset + 40(\base) + ldc1 $f6, \offset + 48(\base) + ldc1 $f7, \offset + 56(\base) + ldc1 $f8, \offset + 64(\base) + ldc1 $f9, \offset + 72(\base) + ldc1 $f10, \offset + 80(\base) + ldc1 $f11, \offset + 88(\base) + ldc1 $f12, \offset + 96(\base) + ldc1 $f13, \offset + 104(\base) + ldc1 $f14, \offset + 112(\base) + ldc1 $f15, \offset + 120(\base) + ldc1 $f16, \offset + 128(\base) + ldc1 $f17, \offset + 136(\base) + ldc1 $f18, \offset + 144(\base) + ldc1 $f19, \offset + 152(\base) + ldc1 $f20, \offset + 160(\base) + ldc1 $f21, \offset + 168(\base) + ldc1 $f22, \offset + 176(\base) + ldc1 $f23, \offset + 184(\base) + ldc1 $f24, \offset + 192(\base) + ldc1 $f25, \offset + 200(\base) + ldc1 $f26, \offset + 208(\base) + ldc1 $f27, \offset + 216(\base) + ldc1 $f28, \offset + 224(\base) + ldc1 $f29, \offset + 232(\base) + ldc1 $f30, \offset + 240(\base) + ldc1 $f31, \offset + 248(\base) + + .endm + +/******************************************************************/ +.macro portSAVE_CONTEXT + + /* Make room for the context. First save the current status so it can be + manipulated, and the cause and EPC registers so their original values are + captured. */ + mfc0 k0, _CP0_CAUSE + addiu sp, sp, -portCONTEXT_SIZE + + #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + /* Test if we are already using the system stack. Only tasks may use the + FPU so if we are already in a nested interrupt then the FPU context does + not require saving. */ + la k1, uxInterruptNesting + lw k1, 0(k1) + bne k1, zero, 2f + nop + + /* Test if the current task needs the FPU context saving. */ + la k1, ulTaskHasFPUContext + lw k1, 0(k1) + beq k1, zero, 1f + nop + + /* Adjust the stack to account for the additional FPU context.*/ + addiu sp, sp, -portFPU_CONTEXT_SIZE + + 1: + /* Save the ulTaskHasFPUContext flag. */ + sw k1, portTASK_HAS_FPU_STACK_LOCATION(sp) + + 2: + #endif + + mfc0 k1, _CP0_STATUS + + /* Also save s7, s6 and s5 so they can be used. Any nesting interrupts + should maintain the values of these registers across the ISR. */ + sw s7, 48(sp) + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + + /* Prepare to enable interrupts above the current priority. */ + srl k0, k0, 0xa + ins k1, k0, 10, 7 + srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */ + ins k1, k0, 18, 1 + ins k1, zero, 1, 4 + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Check the nesting count value. */ + la k0, uxInterruptNesting + lw s6, (k0) + + /* If the nesting count is 0 then swap to the the system stack, otherwise + the system stack is already being used. */ + bne s6, zero, 1f + nop + + /* Swap to the system stack. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Increment and save the nesting count. */ +1: addiu s6, s6, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. No other s registers need be + saved. */ + sw ra, 120(s5) + sw s8, 116(s5) + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s6, portEPC_STACK_LOCATION(s5) + sw $1, 16(s5) + + /* Save the AC0, AC1, AC2, AC3 registers from the DSP. s6 is used as a + scratch register. */ + mfhi s6, $ac1 + sw s6, 128(s5) + mflo s6, $ac1 + sw s6, 124(s5) + + mfhi s6, $ac2 + sw s6, 136(s5) + mflo s6, $ac2 + sw s6, 132(s5) + + mfhi s6, $ac3 + sw s6, 144(s5) + mflo s6, $ac3 + sw s6, 140(s5) + + /* Save the DSP Control register */ + rddsp s6 + sw s6, 148(s5) + + /* ac0 is done separately to match the MX port. */ + mfhi s6, $ac0 + sw s6, 12(s5) + mflo s6, $ac0 + sw s6, 8(s5) + + /* Save the FPU context if the nesting count was zero. */ + #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + la s6, uxInterruptNesting + lw s6, 0(s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + + /* Test if the current task needs the FPU context saving. */ + lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5) + beq s6, zero, 1f + nop + + /* Save the FPU registers. */ + portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5 + + /* Save the FPU status register */ + cfc1 s6, $f31 + sw s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5) + + 1: + #endif + + /* Update the task stack pointer value if nesting is zero. */ + la s6, uxInterruptNesting + lw s6, (s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + + /* Save the stack pointer. */ + la s6, uxSavedTaskStackPointer + sw s5, (s6) +1: + .endm + +/******************************************************************/ +.macro portRESTORE_CONTEXT + + /* Restore the stack pointer from the TCB. This is only done if the + nesting count is 1. */ + la s6, uxInterruptNesting + lw s6, (s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + la s6, uxSavedTaskStackPointer + lw s5, (s6) + + #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + /* Restore the FPU context if required. */ + lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5) + beq s6, zero, 1f + nop + + /* Restore the FPU registers. */ + portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5 + + /* Restore the FPU status register. */ + lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5) + ctc1 s6, $f31 + #endif + +1: + + /* Restore the context. */ + lw s6, 128(s5) + mthi s6, $ac1 + lw s6, 124(s5) + mtlo s6, $ac1 + + lw s6, 136(s5) + mthi s6, $ac2 + lw s6, 132(s5) + mtlo s6, $ac2 + + lw s6, 144(s5) + mthi s6, $ac3 + lw s6, 140(s5) + mtlo s6, $ac3 + + /* Restore DSPControl. */ + lw s6, 148(s5) + wrdsp s6 + + lw s6, 8(s5) + mtlo s6, $ac0 + lw s6, 12(s5) + mthi s6, $ac0 + lw $1, 16(s5) + + /* s6 is loaded as it was used as a scratch register and therefore saved + as part of the interrupt context. */ + lw s7, 48(s5) + lw s6, 44(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Decrement the nesting count. */ + la k0, uxInterruptNesting + lw k1, (k0) + addiu k1, k1, -1 + sw k1, 0(k0) + + #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + /* If the nesting count is now zero then the FPU context may be restored. */ + bne k1, zero, 1f + nop + + /* Restore the value of ulTaskHasFPUContext */ + la k0, ulTaskHasFPUContext + lw k1, 0(s5) + sw k1, 0(k0) + + /* If the task does not have an FPU context then adjust the stack normally. */ + beq k1, zero, 1f + nop + + /* Restore the STATUS and EPC registers */ + lw k0, portSTATUS_STACK_LOCATION(s5) + lw k1, portEPC_STACK_LOCATION(s5) + + /* Leave the stack in its original state. First load sp from s5, then + restore s5 from the stack. */ + add sp, zero, s5 + lw s5, 40(sp) + + /* Adjust the stack pointer to remove the FPU context */ + addiu sp, sp, portFPU_CONTEXT_SIZE + beq zero, zero, 2f + nop + + 1: /* Restore the STATUS and EPC registers */ + lw k0, portSTATUS_STACK_LOCATION(s5) + lw k1, portEPC_STACK_LOCATION(s5) + + /* Leave the stack in its original state. First load sp from s5, then + restore s5 from the stack. */ + add sp, zero, s5 + lw s5, 40(sp) + + 2: /* Adjust the stack pointer */ + addiu sp, sp, portCONTEXT_SIZE + + #else + + /* Restore the frame when there is no hardware FP support. */ + lw k0, portSTATUS_STACK_LOCATION(s5) + lw k1, portEPC_STACK_LOCATION(s5) + + /* Leave the stack in its original state. First load sp from s5, then + restore s5 from the stack. */ + add sp, zero, s5 + lw s5, 40(sp) + + addiu sp, sp, portCONTEXT_SIZE + + #endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + + mtc0 k0, _CP0_STATUS + mtc0 k1, _CP0_EPC + ehb + eret + nop + + .endm + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MZ/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MZ/port.c new file mode 100644 index 0000000..894ba7e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MZ/port.c @@ -0,0 +1,373 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC32MZ port. + *----------------------------------------------------------*/ + +/* Microchip specific headers. */ +#include + +/* Standard headers. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +#if !defined(__PIC32MZ__) + #error This port is designed to work with XC32 on PIC32MZ MCUs. Please update your C compiler version or settings. +#endif + +#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0 +#endif + +/* Hardware specifics. */ +#define portTIMER_PRESCALE 8 +#define portPRESCALE_BITS 1 + +/* Bits within various registers. */ +#define portIE_BIT ( 0x00000001 ) +#define portEXL_BIT ( 0x00000002 ) +#define portMX_BIT ( 0x01000000 ) /* Allow access to DSP instructions. */ +#define portCU1_BIT ( 0x20000000 ) /* enable CP1 for parts with hardware. */ +#define portFR_BIT ( 0x04000000 ) /* Enable 64 bit floating point registers. */ + +/* Bits within the CAUSE register. */ +#define portCORE_SW_0 ( 0x00000100 ) +#define portCORE_SW_1 ( 0x00000200 ) + +/* The EXL bit is set to ensure interrupts do not occur while the context of +the first task is being restored. */ +#if ( __mips_hard_float == 1 ) + #define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT ) +#else + #define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT ) +#endif + +/* The initial value to store into the FPU status and control register. This is + only used on parts that support a hardware FPU. */ +#define portINITIAL_FPSCR (0x1000000) /* High perf on denormal ops */ + + +/* +By default port.c generates its tick interrupt from TIMER1. The user can +override this behaviour by: + 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(), + which is the function that configures the timer. The function is defined + as a weak symbol in this file so if the same function name is used in the + application code then the version in the application code will be linked + into the application in preference to the version defined in this file. + 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used + to generate the tick interrupt. For example, when timer 1 is used then + configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR. + configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h. + 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the + timer used to generate the tick interrupt. For example, when timer 1 is + used configCLEAR_TICK_TIMER_INTERRUPT() is defined to + IFS0CLR = _IFS0_T1IF_MASK. +*/ +#ifndef configTICK_INTERRUPT_VECTOR + #define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR + #define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK +#else + #ifndef configCLEAR_TICK_TIMER_INTERRUPT + #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code. + #endif +#endif + +/* Let the user override the pre-loading of the initial RA with the address of +prvTaskExitError() in case it messes up unwinding of the stack in the +debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task +stack checking. A problem in the ISR stack will trigger an assert, not call the +stack overflow hook function (because the stack overflow hook is specific to a +task stack, not the ISR stack). */ +#if( configCHECK_FOR_STACK_OVERFLOW > 2 ) + + /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for + the task stacks, and so will legitimately appear in many positions within + the ISR stack. */ + #define portISR_STACK_FILL_BYTE 0xee + + static const uint8_t ucExpectedStackBytes[] = { + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \ + + #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) +#else + /* Define the function away. */ + #define portCHECK_ISR_STACK() +#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + +/*-----------------------------------------------------------*/ + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Records the interrupt nesting depth. This is initialised to one as it is +decremented to 0 when the first task starts. */ +volatile UBaseType_t uxInterruptNesting = 0x01; + +/* Stores the task stack pointer when a switch is made to use the system stack. */ +UBaseType_t uxSavedTaskStackPointer = 0; + +/* The stack used by interrupt service routines that cause a context switch. */ +__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 }; + +/* The top of stack value ensures there is enough space to store 6 registers on +the callers stack, as some functions seem to want to do this. 8 byte alignment +is required to allow double word floating point stack pushes generated by the +compiler. */ +const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] ); + +/* Saved as part of the task context. Set to pdFALSE if the task does not + require an FPU context. */ +#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + uint32_t ulTaskHasFPUContext = 0; +#endif + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Ensure 8 byte alignment is maintained when leaving this function. */ + pxTopOfStack--; + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0xDEADBEEF; + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) _CP0_GET_CAUSE(); + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0x00000000; /* DSPControl */ + pxTopOfStack -= 7; /* Includes space for AC1 - AC3. */ + + *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */ + pxTopOfStack -= 15; + + *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */ + pxTopOfStack -= 15; + + *pxTopOfStack = (StackType_t) pdFALSE; /*by default disable FPU context save on parts with FPU */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxSavedTaskStackPointer == 0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. This function uses peripheral timer 1. + * The function is declared weak so an application writer can use a different + * timer by redefining this implementation. If a different timer is used then + * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to + * ensure the RTOS provided tick interrupt handler is installed on the correct + * vector number. When Timer 1 is used the vector number is defined as + * _TIMER_1_VECTOR. + */ +__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void ) +{ +const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1UL; + + T1CON = 0x0000; + T1CONbits.TCKPS = portPRESCALE_BITS; + PR1 = ulCompareMatch; + IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY; + + /* Clear the interrupt as a starting condition. */ + IFS0bits.T1IF = 0; + + /* Enable the interrupt. */ + IEC0bits.T1IE = 1; + + /* Start the timer. */ + T1CONbits.TON = 1; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler(void) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxInterruptNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); +extern void *pxCurrentTCB; + + #if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) + { + /* Fill the ISR stack to make it easy to asses how much is being used. */ + memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) ); + } + #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + + /* Clear the software interrupt flag. */ + IFS0CLR = _IFS0_CS0IF_MASK; + + /* Set software timer priority. */ + IPC0CLR = _IPC0_CS0IP_MASK; + IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION ); + + /* Enable software interrupt. */ + IEC0CLR = _IEC0_CS0IE_MASK; + IEC0SET = 1 << _IEC0_CS0IE_POSITION; + + /* Setup the timer to generate the tick. Interrupts will have been + disabled by the time we get here. */ + vApplicationSetupTickTimerInterrupt(); + + /* Kick off the highest priority task that has been created so far. + Its stack location is loaded into uxSavedTaskStackPointer. */ + uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB; + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + exit error function to prevent compiler warnings about a static function + not being called in the case that the application writer overrides this + functionality by defining configTASK_RETURN_ADDRESS. */ + prvTaskExitError(); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortIncrementTick( void ) +{ +UBaseType_t uxSavedStatus; + + uxSavedStatus = uxPortSetInterruptMaskFromISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + _CP0_BIS_CAUSE( portCORE_SW_0 ); + } + } + vPortClearInterruptMaskFromISR( uxSavedStatus ); + + /* Look for the ISR stack getting near or past its limit. */ + portCHECK_ISR_STACK(); + + /* Clear timer interrupt. */ + configCLEAR_TICK_TIMER_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxPortSetInterruptMaskFromISR( void ) +{ +UBaseType_t uxSavedStatusRegister; + + __builtin_disable_interrupts(); + uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01; + /* This clears the IPL bits, then sets them to + configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called + from an interrupt that has a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action + can only result in the IPL being unchanged or raised, and therefore never + lowered. */ + _CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ); + + return uxSavedStatusRegister; +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister ) +{ + _CP0_SET_STATUS( uxSavedStatusRegister ); +} +/*-----------------------------------------------------------*/ + +#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + + void vPortTaskUsesFPU(void) + { + extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit ); + + portENTER_CRITICAL(); + + /* Initialise the floating point status register. */ + vPortInitialiseFPSCR(portINITIAL_FPSCR); + + /* A task is registering the fact that it needs a FPU context. Set the + FPU flag (saved as part of the task context). */ + ulTaskHasFPUContext = pdTRUE; + + portEXIT_CRITICAL(); + } + +#endif /* __mips_hard_float == 1 */ + +/*-----------------------------------------------------------*/ + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MZ/port_asm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MZ/port_asm.S new file mode 100644 index 0000000..e729afa --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MZ/port_asm.S @@ -0,0 +1,769 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vPortIncrementTick + .extern xISRStackTop + .extern ulTaskHasFPUContext + + .global vPortStartFirstTask + .global vPortYieldISR + .global vPortTickInterruptHandler + .global vPortInitialiseFPSCR + + +/******************************************************************/ + + .set nomips16 + .set nomicromips + .set noreorder + .set noat + + /*************************************************************** + * The following is needed to locate the + * vPortTickInterruptHandler function into the correct vector + ***************************************************************/ + #ifdef configTICK_INTERRUPT_VECTOR + #if (configTICK_INTERRUPT_VECTOR == _CORE_TIMER_VECTOR) + .equ __vector_dispatch_0, vPortTickInterruptHandler + .global __vector_dispatch_0 + .section .vector_0, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_1_VECTOR) + .equ __vector_dispatch_4, vPortTickInterruptHandler + .global __vector_dispatch_4 + .section .vector_4, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_2_VECTOR) + .equ __vector_dispatch_9, vPortTickInterruptHandler + .global __vector_dispatch_9 + .section .vector_9, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_3_VECTOR) + .equ __vector_dispatch_14, vPortTickInterruptHandler + .global __vector_dispatch_14 + .section .vector_14, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_4_VECTOR) + .equ __vector_dispatch_19, vPortTickInterruptHandler + .global __vector_dispatch_19 + .section .vector_19, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_5_VECTOR) + .equ __vector_dispatch_24, vPortTickInterruptHandler + .global __vector_dispatch_24 + .section .vector_24, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_6_VECTOR) + .equ __vector_dispatch_28, vPortTickInterruptHandler + .global __vector_dispatch_28 + .section .vector_28, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_7_VECTOR) + .equ __vector_dispatch_32, vPortTickInterruptHandler + .global __vector_dispatch_32 + .section .vector_32, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_8_VECTOR) + .equ __vector_dispatch_36, vPortTickInterruptHandler + .global __vector_dispatch_36 + .section .vector_36, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_9_VECTOR) + .equ __vector_dispatch_40, vPortTickInterruptHandler + .global __vector_dispatch_40 + .section .vector_40, code, keep + #endif + #else + .equ __vector_dispatch_4, vPortTickInterruptHandler + .global __vector_dispatch_4 + .section .vector_4, code, keep + #endif + + .ent vPortTickInterruptHandler + +vPortTickInterruptHandler: + + portSAVE_CONTEXT + + jal vPortIncrementTick + nop + + portRESTORE_CONTEXT + + .end vPortTickInterruptHandler + +/******************************************************************/ + + .set noreorder + .set noat + .section .text, code + .ent vPortStartFirstTask + +vPortStartFirstTask: + + /* Simply restore the context of the highest priority task that has been + created so far. */ + portRESTORE_CONTEXT + + .end vPortStartFirstTask + + + +/*******************************************************************/ + + .set nomips16 + .set nomicromips + .set noreorder + .set noat + /*************************************************************** + * The following is needed to locate the vPortYieldISR function + * into the correct vector + ***************************************************************/ + .equ __vector_dispatch_1, vPortYieldISR + .global __vector_dispatch_1 + .section .vector_1, code + + .ent vPortYieldISR +vPortYieldISR: + + #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + /* Code sequence for FPU support, the context save requires advance + knowledge of the stack frame size and if the current task actually uses the + FPU. */ + + /* Make room for the context. First save the current status so it can be + manipulated, and the cause and EPC registers so their original values are + captured. */ + la k0, ulTaskHasFPUContext + lw k0, 0(k0) + beq k0, zero, 1f + addiu sp, sp, -portCONTEXT_SIZE /* always reserve space for the context. */ + addiu sp, sp, -portFPU_CONTEXT_SIZE /* reserve additional space for the FPU context. */ + 1: + mfc0 k1, _CP0_STATUS + + /* Also save s6 and s5 so they can be used. Any nesting interrupts should + maintain the values of these registers across the ISR. */ + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + sw k0, portTASK_HAS_FPU_STACK_LOCATION(sp) + + /* Prepare to re-enabled interrupts above the kernel priority. */ + ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */ + ins k1, zero, 18, 1 /* Clear IPL bit 7. It would be an error here if this bit were set anyway. */ + ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) + ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */ + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Swap to the system stack. This is not conditional on the nesting + count as this interrupt is always the lowest priority and therefore + the nesting is always 0. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Set the nesting count. */ + la k0, uxInterruptNesting + addiu s6, zero, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved with the rest of the context + after interrupts are enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. */ + sw ra, 120(s5) + sw s8, 116(s5) + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s7, 48(s5) + sw s6, portEPC_STACK_LOCATION(s5) + /* s5 and s6 has already been saved. */ + sw s4, 36(s5) + sw s3, 32(s5) + sw s2, 28(s5) + sw s1, 24(s5) + sw s0, 20(s5) + sw $1, 16(s5) + + /* s7 is used as a scratch register as this should always be saved across + nesting interrupts. */ + + /* Save the AC0, AC1, AC2 and AC3. */ + mfhi s7, $ac1 + sw s7, 128(s5) + mflo s7, $ac1 + sw s7, 124(s5) + + mfhi s7, $ac2 + sw s7, 136(s5) + mflo s7, $ac2 + sw s7, 132(s5) + + mfhi s7, $ac3 + sw s7, 144(s5) + mflo s7, $ac3 + sw s7, 140(s5) + + rddsp s7 + sw s7, 148(s5) + + mfhi s7, $ac0 + sw s7, 12(s5) + mflo s7, $ac0 + sw s7, 8(s5) + + /* Test if FPU context save is required. */ + lw s7, portTASK_HAS_FPU_STACK_LOCATION(s5) + beq s7, zero, 1f + nop + + /* Save the FPU registers above the normal context. */ + portSAVE_FPU_REGS (portCONTEXT_SIZE + 8), s5 + + /* Save the FPU status register */ + cfc1 s7, $f31 + sw s7, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5) + + 1: + /* Save the stack pointer to the task. */ + la s7, pxCurrentTCB + lw s7, (s7) + sw s5, (s7) + + /* Set the interrupt mask to the max priority that can use the API. The + yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which + is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever + raise the IPL value and never lower it. */ + di + ehb + mfc0 s7, _CP0_STATUS + ins s7, zero, 10, 7 + ins s7, zero, 18, 1 + ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1 + + /* This mtc0 re-enables interrupts, but only above + configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 s6, _CP0_STATUS + ehb + + /* Clear the software interrupt in the core. */ + mfc0 s6, _CP0_CAUSE + ins s6, zero, 8, 1 + mtc0 s6, _CP0_CAUSE + ehb + + /* Clear the interrupt in the interrupt controller. */ + la s6, IFS0CLR + addiu s4, zero, 2 + sw s4, (s6) + + jal vTaskSwitchContext + nop + + /* Clear the interrupt mask again. The saved status value is still in s7. */ + mtc0 s7, _CP0_STATUS + ehb + + /* Restore the stack pointer from the TCB. */ + la s0, pxCurrentTCB + lw s0, (s0) + lw s5, (s0) + + /* Test if the FPU context needs restoring. */ + lw s0, portTASK_HAS_FPU_STACK_LOCATION(s5) + beq s0, zero, 1f + nop + + /* Restore the FPU status register. */ + lw s0, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5) + ctc1 s0, $f31 + + /* Restore the FPU registers. */ + portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5 + + 1: + /* Restore the rest of the context. */ + lw s0, 128(s5) + mthi s0, $ac1 + lw s0, 124(s5) + mtlo s0, $ac1 + + lw s0, 136(s5) + mthi s0, $ac2 + lw s0, 132(s5) + mtlo s0, $ac2 + + lw s0, 144(s5) + mthi s0, $ac3 + lw s0, 140(s5) + mtlo s0, $ac3 + + lw s0, 148(s5) + wrdsp s0 + + lw s0, 8(s5) + mtlo s0, $ac0 + lw s0, 12(s5) + mthi s0, $ac0 + + lw $1, 16(s5) + lw s0, 20(s5) + lw s1, 24(s5) + lw s2, 28(s5) + lw s3, 32(s5) + lw s4, 36(s5) + + /* s5 is loaded later. */ + lw s6, 44(s5) + lw s7, 48(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Set nesting back to zero. As the lowest priority interrupt this + interrupt cannot have nested. */ + la k0, uxInterruptNesting + sw zero, 0(k0) + + /* Switch back to use the real stack pointer. */ + add sp, zero, s5 + + /* Restore the real s5 value. */ + lw s5, 40(sp) + + /* Pop the FPU context value from the stack */ + lw k0, portTASK_HAS_FPU_STACK_LOCATION(sp) + la k1, ulTaskHasFPUContext + sw k0, 0(k1) + beq k0, zero, 1f + nop + + /* task has FPU context so adjust the stack frame after popping the + status and epc values. */ + lw k1, portSTATUS_STACK_LOCATION(sp) + lw k0, portEPC_STACK_LOCATION(sp) + addiu sp, sp, portFPU_CONTEXT_SIZE + beq zero, zero, 2f + nop + + 1: + /* Pop the status and epc values. */ + lw k1, portSTATUS_STACK_LOCATION(sp) + lw k0, portEPC_STACK_LOCATION(sp) + + 2: + /* Remove stack frame. */ + addiu sp, sp, portCONTEXT_SIZE + + #else + /* Code sequence for no FPU support, the context save requires advance + knowledge of the stack frame size when no FPU is being used */ + + /* Make room for the context. First save the current status so it can be + manipulated, and the cause and EPC registers so thier original values are + captured. */ + addiu sp, sp, -portCONTEXT_SIZE + mfc0 k1, _CP0_STATUS + + /* Also save s6 and s5 so they can be used. Any nesting interrupts should + maintain the values of these registers across the ISR. */ + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + + /* Prepare to re-enabled interrupts above the kernel priority. */ + ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */ + ins k1, zero, 18, 1 /* Clear IPL bit 7. It would be an error here if this bit were set anyway. */ + ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) + ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */ + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Swap to the system stack. This is not conditional on the nesting + count as this interrupt is always the lowest priority and therefore + the nesting is always 0. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Set the nesting count. */ + la k0, uxInterruptNesting + addiu s6, zero, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved with the rest of the context + after interrupts are enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. */ + sw ra, 120(s5) + sw s8, 116(s5) + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s7, 48(s5) + sw s6, portEPC_STACK_LOCATION(s5) + /* s5 and s6 has already been saved. */ + sw s4, 36(s5) + sw s3, 32(s5) + sw s2, 28(s5) + sw s1, 24(s5) + sw s0, 20(s5) + sw $1, 16(s5) + + /* s7 is used as a scratch register as this should always be saved across + nesting interrupts. */ + + /* Save the AC0, AC1, AC2 and AC3. */ + mfhi s7, $ac1 + sw s7, 128(s5) + mflo s7, $ac1 + sw s7, 124(s5) + + mfhi s7, $ac2 + sw s7, 136(s5) + mflo s7, $ac2 + sw s7, 132(s5) + + mfhi s7, $ac3 + sw s7, 144(s5) + mflo s7, $ac3 + sw s7, 140(s5) + + rddsp s7 + sw s7, 148(s5) + + mfhi s7, $ac0 + sw s7, 12(s5) + mflo s7, $ac0 + sw s7, 8(s5) + + /* Save the stack pointer to the task. */ + la s7, pxCurrentTCB + lw s7, (s7) + sw s5, (s7) + + /* Set the interrupt mask to the max priority that can use the API. The + yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which + is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever + raise the IPL value and never lower it. */ + di + ehb + mfc0 s7, _CP0_STATUS + ins s7, zero, 10, 7 + ins s7, zero, 18, 1 + ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1 + + /* This mtc0 re-enables interrupts, but only above + configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 s6, _CP0_STATUS + ehb + + /* Clear the software interrupt in the core. */ + mfc0 s6, _CP0_CAUSE + ins s6, zero, 8, 1 + mtc0 s6, _CP0_CAUSE + ehb + + /* Clear the interrupt in the interrupt controller. */ + la s6, IFS0CLR + addiu s4, zero, 2 + sw s4, (s6) + + jal vTaskSwitchContext + nop + + /* Clear the interrupt mask again. The saved status value is still in s7. */ + mtc0 s7, _CP0_STATUS + ehb + + /* Restore the stack pointer from the TCB. */ + la s0, pxCurrentTCB + lw s0, (s0) + lw s5, (s0) + + /* Restore the rest of the context. */ + lw s0, 128(s5) + mthi s0, $ac1 + lw s0, 124(s5) + mtlo s0, $ac1 + + lw s0, 136(s5) + mthi s0, $ac2 + lw s0, 132(s5) + mtlo s0, $ac2 + + lw s0, 144(s5) + mthi s0, $ac3 + lw s0, 140(s5) + mtlo s0, $ac3 + + lw s0, 148(s5) + wrdsp s0 + + lw s0, 8(s5) + mtlo s0, $ac0 + lw s0, 12(s5) + mthi s0, $ac0 + + lw $1, 16(s5) + lw s0, 20(s5) + lw s1, 24(s5) + lw s2, 28(s5) + lw s3, 32(s5) + lw s4, 36(s5) + + /* s5 is loaded later. */ + lw s6, 44(s5) + lw s7, 48(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Set nesting back to zero. As the lowest priority interrupt this + interrupt cannot have nested. */ + la k0, uxInterruptNesting + sw zero, 0(k0) + + /* Switch back to use the real stack pointer. */ + add sp, zero, s5 + + /* Restore the real s5 value. */ + lw s5, 40(sp) + + /* Pop the status and epc values. */ + lw k1, portSTATUS_STACK_LOCATION(sp) + lw k0, portEPC_STACK_LOCATION(sp) + + /* Remove stack frame. */ + addiu sp, sp, portCONTEXT_SIZE + + #endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */ + + /* Restore the status and EPC registers and return */ + mtc0 k1, _CP0_STATUS + mtc0 k0, _CP0_EPC + ehb + eret + nop + + .end vPortYieldISR + +/******************************************************************/ + +#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + + .macro portFPUSetAndInc reg, dest + mtc1 \reg, \dest + cvt.d.w \dest, \dest + addiu \reg, \reg, 1 + .endm + + .set noreorder + .set noat + .section .text, code + .ent vPortInitialiseFPSCR + +vPortInitialiseFPSCR: + + /* Initialize the floating point status register in CP1. The initial + value is passed in a0. */ + ctc1 a0, $f31 + + /* Clear the FPU registers */ + addiu a0, zero, 0x0000 + portFPUSetAndInc a0, $f0 + portFPUSetAndInc a0, $f1 + portFPUSetAndInc a0, $f2 + portFPUSetAndInc a0, $f3 + portFPUSetAndInc a0, $f4 + portFPUSetAndInc a0, $f5 + portFPUSetAndInc a0, $f6 + portFPUSetAndInc a0, $f7 + portFPUSetAndInc a0, $f8 + portFPUSetAndInc a0, $f9 + portFPUSetAndInc a0, $f10 + portFPUSetAndInc a0, $f11 + portFPUSetAndInc a0, $f12 + portFPUSetAndInc a0, $f13 + portFPUSetAndInc a0, $f14 + portFPUSetAndInc a0, $f15 + portFPUSetAndInc a0, $f16 + portFPUSetAndInc a0, $f17 + portFPUSetAndInc a0, $f18 + portFPUSetAndInc a0, $f19 + portFPUSetAndInc a0, $f20 + portFPUSetAndInc a0, $f21 + portFPUSetAndInc a0, $f22 + portFPUSetAndInc a0, $f23 + portFPUSetAndInc a0, $f24 + portFPUSetAndInc a0, $f25 + portFPUSetAndInc a0, $f26 + portFPUSetAndInc a0, $f27 + portFPUSetAndInc a0, $f28 + portFPUSetAndInc a0, $f29 + portFPUSetAndInc a0, $f30 + portFPUSetAndInc a0, $f31 + + jr ra + nop + + .end vPortInitialiseFPSCR + +#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */ + +#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + + /**********************************************************************/ + /* Test read back */ + /* a0 = address to store registers */ + + .set noreorder + .set noat + .section .text, code + .ent vPortFPUReadback + .global vPortFPUReadback + +vPortFPUReadback: + sdc1 $f0, 0(a0) + sdc1 $f1, 8(a0) + sdc1 $f2, 16(a0) + sdc1 $f3, 24(a0) + sdc1 $f4, 32(a0) + sdc1 $f5, 40(a0) + sdc1 $f6, 48(a0) + sdc1 $f7, 56(a0) + sdc1 $f8, 64(a0) + sdc1 $f9, 72(a0) + sdc1 $f10, 80(a0) + sdc1 $f11, 88(a0) + sdc1 $f12, 96(a0) + sdc1 $f13, 104(a0) + sdc1 $f14, 112(a0) + sdc1 $f15, 120(a0) + sdc1 $f16, 128(a0) + sdc1 $f17, 136(a0) + sdc1 $f18, 144(a0) + sdc1 $f19, 152(a0) + sdc1 $f20, 160(a0) + sdc1 $f21, 168(a0) + sdc1 $f22, 176(a0) + sdc1 $f23, 184(a0) + sdc1 $f24, 192(a0) + sdc1 $f25, 200(a0) + sdc1 $f26, 208(a0) + sdc1 $f27, 216(a0) + sdc1 $f28, 224(a0) + sdc1 $f29, 232(a0) + sdc1 $f30, 240(a0) + sdc1 $f31, 248(a0) + + jr ra + nop + + .end vPortFPUReadback + +#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */ + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MZ/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MZ/portmacro.h new file mode 100644 index 0000000..2627cce --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MPLAB/PIC32MZ/portmacro.h @@ -0,0 +1,213 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* System include files */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portIPL_SHIFT ( 10UL ) +/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should +never have higher IPL bits set anyway. */ +#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT ) +#define portSW0_BIT ( 0x01 << 8 ) + +/* This clears the IPL bits, then sets them to +configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if +configASSERT() is defined to ensure an assertion handler does not inadvertently +attempt to lower the IPL when the call to assert was triggered because the IPL +value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR +safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are +those that end in FromISR. FreeRTOS maintains a separate interrupt API to +ensure API function and interrupt entry is as fast and as simple as possible. */ +#ifdef configASSERT + #define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulStatus; \ + \ + /* Mask interrupts at and below the kernel interrupt priority. */ \ + ulStatus = _CP0_GET_STATUS(); \ + \ + /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \ + if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \ + { \ + ulStatus &= ~portALL_IPL_BITS; \ + _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \ + } \ + } +#else /* configASSERT */ + #define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulStatus; \ + \ + /* Mask interrupts at and below the kernel interrupt priority. */ \ + ulStatus = _CP0_GET_STATUS(); \ + ulStatus &= ~portALL_IPL_BITS; \ + _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \ + } +#endif /* configASSERT */ + +#define portENABLE_INTERRUPTS() \ +{ \ +uint32_t ulStatus; \ + \ + /* Unmask all interrupts. */ \ + ulStatus = _CP0_GET_STATUS(); \ + ulStatus &= ~portALL_IPL_BITS; \ + _CP0_SET_STATUS( ulStatus ); \ +} + + +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portCRITICAL_NESTING_IN_TCB 1 +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +extern UBaseType_t uxPortSetInterruptMaskFromISR(); +extern void vPortClearInterruptMaskFromISR( UBaseType_t ); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister ) + +#if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + #error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module. +#endif + +#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + void vPortTaskUsesFPU( void ); + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) ) + +#endif /* taskRECORD_READY_PRIORITY */ + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +#define portYIELD() \ +{ \ +uint32_t ulCause; \ + \ + /* Trigger software interrupt. */ \ + ulCause = _CP0_GET_CAUSE(); \ + ulCause |= portSW0_BIT; \ + _CP0_SET_CAUSE( ulCause ); \ +} + +extern volatile UBaseType_t uxInterruptNesting; +#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 ) + +#define portNOP() __asm volatile ( "nop" ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) { portYIELD(); } } while( 0 ) + +/* Required by the kernel aware debugger. */ +#ifdef __DEBUG + #define portREMOVE_STATIC_QUALIFIER +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MSVC-MingW/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MSVC-MingW/port.c new file mode 100644 index 0000000..de06d37 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MSVC-MingW/port.c @@ -0,0 +1,700 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifdef __GNUC__ + #include "mmsystem.h" +#else + #pragma comment(lib, "winmm.lib") +#endif + +#define portMAX_INTERRUPTS ( ( uint32_t ) sizeof( uint32_t ) * 8UL ) /* The number of bits in an uint32_t. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* The priorities at which the various components of the simulation execute. */ +#define portDELETE_SELF_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL /* Must be highest. */ +#define portSIMULATED_INTERRUPTS_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL +#define portSIMULATED_TIMER_THREAD_PRIORITY THREAD_PRIORITY_HIGHEST +#define portTASK_THREAD_PRIORITY THREAD_PRIORITY_ABOVE_NORMAL + +/* + * Created as a high priority thread, this function uses a timer to simulate + * a tick interrupt being generated on an embedded target. In this Windows + * environment the timer does not achieve anything approaching real time + * performance though. + */ +static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter ); + +/* + * Process all the simulated interrupts - each represented by a bit in + * ulPendingInterrupts variable. + */ +static void prvProcessSimulatedInterrupts( void ); + +/* + * Interrupt handlers used by the kernel itself. These are executed from the + * simulated interrupt handler thread. + */ +static uint32_t prvProcessYieldInterrupt( void ); +static uint32_t prvProcessTickInterrupt( void ); + +/* + * Exiting a critical section will cause the calling task to block on yield + * event to wait for an interrupt to process if an interrupt was pended while + * inside the critical section. This variable protects against a recursive + * attempt to obtain pvInterruptEventMutex if a critical section is used inside + * an interrupt handler itself. + */ +volatile BaseType_t xInsideInterrupt = pdFALSE; + +/* + * Called when the process exits to let Windows know the high timer resolution + * is no longer required. + */ +static BOOL WINAPI prvEndProcess( DWORD dwCtrlType ); + +/*-----------------------------------------------------------*/ + +/* The WIN32 simulator runs each task in a thread. The context switching is +managed by the threads, so the task stack does not have to be managed directly, +although the task stack is still used to hold an xThreadState structure this is +the only thing it will ever hold. The structure indirectly maps the task handle +to a thread handle. */ +typedef struct +{ + /* Handle of the thread that executes the task. */ + void *pvThread; + + /* Event used to make sure the thread does not execute past a yield point + between the call to SuspendThread() to suspend the thread and the + asynchronous SuspendThread() operation actually being performed. */ + void *pvYieldEvent; +} ThreadState_t; + +/* Simulated interrupts waiting to be processed. This is a bit mask where each +bit represents one interrupt, so a maximum of 32 interrupts can be simulated. */ +static volatile uint32_t ulPendingInterrupts = 0UL; + +/* An event used to inform the simulated interrupt processing thread (a high +priority thread that simulated interrupt processing) that an interrupt is +pending. */ +static void *pvInterruptEvent = NULL; + +/* Mutex used to protect all the simulated interrupt variables that are accessed +by multiple threads. */ +static void *pvInterruptEventMutex = NULL; + +/* The critical nesting count for the currently executing task. This is +initialised to a non-zero value so interrupts do not become enabled during +the initialisation phase. As each task has its own critical nesting value +ulCriticalNesting will get set to zero when the first task runs. This +initialisation is probably not critical in this simulated environment as the +simulated interrupt handlers do not get created until the FreeRTOS scheduler is +started anyway. */ +static volatile uint32_t ulCriticalNesting = 9999UL; + +/* Handlers for all the simulated software interrupts. The first two positions +are used for the Yield and Tick interrupts so are handled slightly differently, +all the other interrupts can be user defined. */ +static uint32_t (*ulIsrHandler[ portMAX_INTERRUPTS ])( void ) = { 0 }; + +/* Pointer to the TCB of the currently executing task. */ +extern void * volatile pxCurrentTCB; + +/* Used to ensure nothing is processed during the startup sequence. */ +static BaseType_t xPortRunning = pdFALSE; + +/*-----------------------------------------------------------*/ + +static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter ) +{ +TickType_t xMinimumWindowsBlockTime; +TIMECAPS xTimeCaps; + + /* Set the timer resolution to the maximum possible. */ + if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR ) + { + xMinimumWindowsBlockTime = ( TickType_t ) xTimeCaps.wPeriodMin; + timeBeginPeriod( xTimeCaps.wPeriodMin ); + + /* Register an exit handler so the timeBeginPeriod() function can be + matched with a timeEndPeriod() when the application exits. */ + SetConsoleCtrlHandler( prvEndProcess, TRUE ); + } + else + { + xMinimumWindowsBlockTime = ( TickType_t ) 20; + } + + /* Just to prevent compiler warnings. */ + ( void ) lpParameter; + + for( ;; ) + { + /* Wait until the timer expires and we can access the simulated interrupt + variables. *NOTE* this is not a 'real time' way of generating tick + events as the next wake time should be relative to the previous wake + time, not the time that Sleep() is called. It is done this way to + prevent overruns in this very non real time simulated/emulated + environment. */ + if( portTICK_PERIOD_MS < xMinimumWindowsBlockTime ) + { + Sleep( xMinimumWindowsBlockTime ); + } + else + { + Sleep( portTICK_PERIOD_MS ); + } + + configASSERT( xPortRunning ); + + /* Can't proceed if in a critical section as pvInterruptEventMutex won't + be available. */ + WaitForSingleObject( pvInterruptEventMutex, INFINITE ); + + /* The timer has expired, generate the simulated tick event. */ + ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK ); + + /* The interrupt is now pending - notify the simulated interrupt + handler thread. Must be outside of a critical section to get here so + the handler thread can execute immediately pvInterruptEventMutex is + released. */ + configASSERT( ulCriticalNesting == 0UL ); + SetEvent( pvInterruptEvent ); + + /* Give back the mutex so the simulated interrupt handler unblocks + and can access the interrupt handler variables. */ + ReleaseMutex( pvInterruptEventMutex ); + } + + #ifdef __GNUC__ + /* Should never reach here - MingW complains if you leave this line out, + MSVC complains if you put it in. */ + return 0; + #endif +} +/*-----------------------------------------------------------*/ + +static BOOL WINAPI prvEndProcess( DWORD dwCtrlType ) +{ +TIMECAPS xTimeCaps; + + ( void ) dwCtrlType; + + if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR ) + { + /* Match the call to timeBeginPeriod( xTimeCaps.wPeriodMin ) made when + the process started with a timeEndPeriod() as the process exits. */ + timeEndPeriod( xTimeCaps.wPeriodMin ); + } + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +ThreadState_t *pxThreadState = NULL; +int8_t *pcTopOfStack = ( int8_t * ) pxTopOfStack; +const SIZE_T xStackSize = 1024; /* Set the size to a small number which will get rounded up to the minimum possible. */ + + /* In this simulated case a stack is not initialised, but instead a thread + is created that will execute the task being created. The thread handles + the context switching itself. The ThreadState_t object is placed onto + the stack that was created for the task - so the stack buffer is still + used, just not in the conventional way. It will not be used for anything + other than holding this structure. */ + pxThreadState = ( ThreadState_t * ) ( pcTopOfStack - sizeof( ThreadState_t ) ); + + /* Create the event used to prevent the thread from executing past its yield + point if the SuspendThread() call that suspends the thread does not take + effect immediately (it is an asynchronous call). */ + pxThreadState->pvYieldEvent = CreateEvent( NULL, /* Default security attributes. */ + FALSE, /* Auto reset. */ + FALSE, /* Start not signalled. */ + NULL );/* No name. */ + + /* Create the thread itself. */ + pxThreadState->pvThread = CreateThread( NULL, xStackSize, ( LPTHREAD_START_ROUTINE ) pxCode, pvParameters, CREATE_SUSPENDED | STACK_SIZE_PARAM_IS_A_RESERVATION, NULL ); + configASSERT( pxThreadState->pvThread ); /* See comment where TerminateThread() is called. */ + SetThreadAffinityMask( pxThreadState->pvThread, 0x01 ); + SetThreadPriorityBoost( pxThreadState->pvThread, TRUE ); + SetThreadPriority( pxThreadState->pvThread, portTASK_THREAD_PRIORITY ); + + return ( StackType_t * ) pxThreadState; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +void *pvHandle = NULL; +int32_t lSuccess; +ThreadState_t *pxThreadState = NULL; +SYSTEM_INFO xSystemInfo; + + /* This port runs windows threads with extremely high priority. All the + threads execute on the same core - to prevent locking up the host only start + if the host has multiple cores. */ + GetSystemInfo( &xSystemInfo ); + if( xSystemInfo.dwNumberOfProcessors <= 1 ) + { + printf( "This version of the FreeRTOS Windows port can only be used on multi-core hosts.\r\n" ); + lSuccess = pdFAIL; + } + else + { + lSuccess = pdPASS; + + /* The highest priority class is used to [try to] prevent other Windows + activity interfering with FreeRTOS timing too much. */ + if( SetPriorityClass( GetCurrentProcess(), REALTIME_PRIORITY_CLASS ) == 0 ) + { + printf( "SetPriorityClass() failed\r\n" ); + } + + /* Install the interrupt handlers used by the scheduler itself. */ + vPortSetInterruptHandler( portINTERRUPT_YIELD, prvProcessYieldInterrupt ); + vPortSetInterruptHandler( portINTERRUPT_TICK, prvProcessTickInterrupt ); + + /* Create the events and mutexes that are used to synchronise all the + threads. */ + pvInterruptEventMutex = CreateMutex( NULL, FALSE, NULL ); + pvInterruptEvent = CreateEvent( NULL, FALSE, FALSE, NULL ); + + if( ( pvInterruptEventMutex == NULL ) || ( pvInterruptEvent == NULL ) ) + { + lSuccess = pdFAIL; + } + + /* Set the priority of this thread such that it is above the priority of + the threads that run tasks. This higher priority is required to ensure + simulated interrupts take priority over tasks. */ + pvHandle = GetCurrentThread(); + if( pvHandle == NULL ) + { + lSuccess = pdFAIL; + } + } + + if( lSuccess == pdPASS ) + { + if( SetThreadPriority( pvHandle, portSIMULATED_INTERRUPTS_THREAD_PRIORITY ) == 0 ) + { + lSuccess = pdFAIL; + } + SetThreadPriorityBoost( pvHandle, TRUE ); + SetThreadAffinityMask( pvHandle, 0x01 ); + } + + if( lSuccess == pdPASS ) + { + /* Start the thread that simulates the timer peripheral to generate + tick interrupts. The priority is set below that of the simulated + interrupt handler so the interrupt event mutex is used for the + handshake / overrun protection. */ + pvHandle = CreateThread( NULL, 0, prvSimulatedPeripheralTimer, NULL, CREATE_SUSPENDED, NULL ); + if( pvHandle != NULL ) + { + SetThreadPriority( pvHandle, portSIMULATED_TIMER_THREAD_PRIORITY ); + SetThreadPriorityBoost( pvHandle, TRUE ); + SetThreadAffinityMask( pvHandle, 0x01 ); + ResumeThread( pvHandle ); + } + + /* Start the highest priority task by obtaining its associated thread + state structure, in which is stored the thread handle. */ + pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB ); + ulCriticalNesting = portNO_CRITICAL_NESTING; + + /* Start the first task. */ + ResumeThread( pxThreadState->pvThread ); + + /* Handle all simulated interrupts - including yield requests and + simulated ticks. */ + prvProcessSimulatedInterrupts(); + } + + /* Would not expect to return from prvProcessSimulatedInterrupts(), so should + not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static uint32_t prvProcessYieldInterrupt( void ) +{ + /* Always return true as this is a yield. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +static uint32_t prvProcessTickInterrupt( void ) +{ +uint32_t ulSwitchRequired; + + /* Process the tick itself. */ + configASSERT( xPortRunning ); + ulSwitchRequired = ( uint32_t ) xTaskIncrementTick(); + + return ulSwitchRequired; +} +/*-----------------------------------------------------------*/ + +static void prvProcessSimulatedInterrupts( void ) +{ +uint32_t ulSwitchRequired, i; +ThreadState_t *pxThreadState; +void *pvObjectList[ 2 ]; +CONTEXT xContext; + + /* Going to block on the mutex that ensured exclusive access to the simulated + interrupt objects, and the event that signals that a simulated interrupt + should be processed. */ + pvObjectList[ 0 ] = pvInterruptEventMutex; + pvObjectList[ 1 ] = pvInterruptEvent; + + /* Create a pending tick to ensure the first task is started as soon as + this thread pends. */ + ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK ); + SetEvent( pvInterruptEvent ); + + xPortRunning = pdTRUE; + + for(;;) + { + xInsideInterrupt = pdFALSE; + WaitForMultipleObjects( sizeof( pvObjectList ) / sizeof( void * ), pvObjectList, TRUE, INFINITE ); + + /* Cannot be in a critical section to get here. Tasks that exit a + critical section will block on a yield mutex to wait for an interrupt to + process if an interrupt was set pending while the task was inside the + critical section. xInsideInterrupt prevents interrupts that contain + critical sections from doing the same. */ + xInsideInterrupt = pdTRUE; + + /* Used to indicate whether the simulated interrupt processing has + necessitated a context switch to another task/thread. */ + ulSwitchRequired = pdFALSE; + + /* For each interrupt we are interested in processing, each of which is + represented by a bit in the 32bit ulPendingInterrupts variable. */ + for( i = 0; i < portMAX_INTERRUPTS; i++ ) + { + /* Is the simulated interrupt pending? */ + if( ( ulPendingInterrupts & ( 1UL << i ) ) != 0 ) + { + /* Is a handler installed? */ + if( ulIsrHandler[ i ] != NULL ) + { + /* Run the actual handler. Handlers return pdTRUE if they + necessitate a context switch. */ + if( ulIsrHandler[ i ]() != pdFALSE ) + { + /* A bit mask is used purely to help debugging. */ + ulSwitchRequired |= ( 1 << i ); + } + } + + /* Clear the interrupt pending bit. */ + ulPendingInterrupts &= ~( 1UL << i ); + } + } + + if( ulSwitchRequired != pdFALSE ) + { + void *pvOldCurrentTCB; + + pvOldCurrentTCB = pxCurrentTCB; + + /* Select the next task to run. */ + vTaskSwitchContext(); + + /* If the task selected to enter the running state is not the task + that is already in the running state. */ + if( pvOldCurrentTCB != pxCurrentTCB ) + { + /* Suspend the old thread. In the cases where the (simulated) + interrupt is asynchronous (tick event swapping a task out rather + than a task blocking or yielding) it doesn't matter if the + 'suspend' operation doesn't take effect immediately - if it + doesn't it would just be like the interrupt occurring slightly + later. In cases where the yield was caused by a task blocking + or yielding then the task will block on a yield event after the + yield operation in case the 'suspend' operation doesn't take + effect immediately. */ + pxThreadState = ( ThreadState_t *) *( ( size_t * ) pvOldCurrentTCB ); + SuspendThread( pxThreadState->pvThread ); + + /* Ensure the thread is actually suspended by performing a + synchronous operation that can only complete when the thread is + actually suspended. The below code asks for dummy register + data. Experimentation shows that these two lines don't appear + to do anything now, but according to + https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743 + they do - so as they do not harm (slight run-time hit). */ + xContext.ContextFlags = CONTEXT_INTEGER; + ( void ) GetThreadContext( pxThreadState->pvThread, &xContext ); + + /* Obtain the state of the task now selected to enter the + Running state. */ + pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB ); + + /* pxThreadState->pvThread can be NULL if the task deleted + itself - but a deleted task should never be resumed here. */ + configASSERT( pxThreadState->pvThread != NULL ); + ResumeThread( pxThreadState->pvThread ); + } + } + + /* If the thread that is about to be resumed stopped running + because it yielded then it will wait on an event when it resumed + (to ensure it does not continue running after the call to + SuspendThread() above as SuspendThread() is asynchronous). + Signal the event to ensure the thread can proceed now it is + valid for it to do so. Signaling the event is benign in the case that + the task was switched out asynchronously by an interrupt as the event + is reset before the task blocks on it. */ + pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB ); + SetEvent( pxThreadState->pvYieldEvent ); + ReleaseMutex( pvInterruptEventMutex ); + } +} +/*-----------------------------------------------------------*/ + +void vPortDeleteThread( void *pvTaskToDelete ) +{ +ThreadState_t *pxThreadState; +uint32_t ulErrorCode; + + /* Remove compiler warnings if configASSERT() is not defined. */ + ( void ) ulErrorCode; + + /* Find the handle of the thread being deleted. */ + pxThreadState = ( ThreadState_t * ) ( *( size_t *) pvTaskToDelete ); + + /* Check that the thread is still valid, it might have been closed by + vPortCloseRunningThread() - which will be the case if the task associated + with the thread originally deleted itself rather than being deleted by a + different task. */ + if( pxThreadState->pvThread != NULL ) + { + WaitForSingleObject( pvInterruptEventMutex, INFINITE ); + + /* !!! This is not a nice way to terminate a thread, and will eventually + result in resources being depleted if tasks frequently delete other + tasks (rather than deleting themselves) as the task stacks will not be + freed. */ + ulErrorCode = TerminateThread( pxThreadState->pvThread, 0 ); + configASSERT( ulErrorCode ); + + ulErrorCode = CloseHandle( pxThreadState->pvThread ); + configASSERT( ulErrorCode ); + + ReleaseMutex( pvInterruptEventMutex ); + } +} +/*-----------------------------------------------------------*/ + +void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield ) +{ +ThreadState_t *pxThreadState; +void *pvThread; +uint32_t ulErrorCode; + + /* Remove compiler warnings if configASSERT() is not defined. */ + ( void ) ulErrorCode; + + /* Find the handle of the thread being deleted. */ + pxThreadState = ( ThreadState_t * ) ( *( size_t *) pvTaskToDelete ); + pvThread = pxThreadState->pvThread; + + /* Raise the Windows priority of the thread to ensure the FreeRTOS scheduler + does not run and swap it out before it is closed. If that were to happen + the thread would never run again and effectively be a thread handle and + memory leak. */ + SetThreadPriority( pvThread, portDELETE_SELF_THREAD_PRIORITY ); + + /* This function will not return, therefore a yield is set as pending to + ensure a context switch occurs away from this thread on the next tick. */ + *pxPendYield = pdTRUE; + + /* Mark the thread associated with this task as invalid so + vPortDeleteThread() does not try to terminate it. */ + pxThreadState->pvThread = NULL; + + /* Close the thread. */ + ulErrorCode = CloseHandle( pvThread ); + configASSERT( ulErrorCode ); + + /* This is called from a critical section, which must be exited before the + thread stops. */ + taskEXIT_CRITICAL(); + CloseHandle( pxThreadState->pvYieldEvent ); + ExitThread( 0 ); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + exit( 0 ); +} +/*-----------------------------------------------------------*/ + +void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber ) +{ +ThreadState_t *pxThreadState = ( ThreadState_t *) *( ( size_t * ) pxCurrentTCB ); + + configASSERT( xPortRunning ); + + if( ( ulInterruptNumber < portMAX_INTERRUPTS ) && ( pvInterruptEventMutex != NULL ) ) + { + WaitForSingleObject( pvInterruptEventMutex, INFINITE ); + ulPendingInterrupts |= ( 1 << ulInterruptNumber ); + + /* The simulated interrupt is now held pending, but don't actually + process it yet if this call is within a critical section. It is + possible for this to be in a critical section as calls to wait for + mutexes are accumulative. If in a critical section then the event + will get set when the critical section nesting count is wound back + down to zero. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + SetEvent( pvInterruptEvent ); + + /* Going to wait for an event - make sure the event is not already + signaled. */ + ResetEvent( pxThreadState->pvYieldEvent ); + } + + ReleaseMutex( pvInterruptEventMutex ); + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* An interrupt was pended so ensure to block to allow it to + execute. In most cases the (simulated) interrupt will have + executed before the next line is reached - so this is just to make + sure. */ + WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE ); + } + } +} +/*-----------------------------------------------------------*/ + +void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) ) +{ + if( ulInterruptNumber < portMAX_INTERRUPTS ) + { + if( pvInterruptEventMutex != NULL ) + { + WaitForSingleObject( pvInterruptEventMutex, INFINITE ); + ulIsrHandler[ ulInterruptNumber ] = pvHandler; + ReleaseMutex( pvInterruptEventMutex ); + } + else + { + ulIsrHandler[ ulInterruptNumber ] = pvHandler; + } + } +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + if( xPortRunning == pdTRUE ) + { + /* The interrupt event mutex is held for the entire critical section, + effectively disabling (simulated) interrupts. */ + WaitForSingleObject( pvInterruptEventMutex, INFINITE ); + } + + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ +int32_t lMutexNeedsReleasing; + + /* The interrupt event mutex should already be held by this thread as it was + obtained on entry to the critical section. */ + lMutexNeedsReleasing = pdTRUE; + + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + ulCriticalNesting--; + + /* Don't need to wait for any pending interrupts to execute if the + critical section was exited from inside an interrupt. */ + if( ( ulCriticalNesting == portNO_CRITICAL_NESTING ) && ( xInsideInterrupt == pdFALSE ) ) + { + /* Were any interrupts set to pending while interrupts were + (simulated) disabled? */ + if( ulPendingInterrupts != 0UL ) + { + ThreadState_t *pxThreadState = ( ThreadState_t *) *( ( size_t * ) pxCurrentTCB ); + + configASSERT( xPortRunning ); + + /* The interrupt won't actually executed until + pvInterruptEventMutex is released as it waits on both + pvInterruptEventMutex and pvInterruptEvent. + pvInterruptEvent is only set when the simulated + interrupt is pended if the interrupt is pended + from outside a critical section - hence it is set + here. */ + SetEvent( pvInterruptEvent ); + /* The calling task is going to wait for an event to ensure the + interrupt that is pending executes immediately after the + critical section is exited - so make sure the event is not + already signaled. */ + ResetEvent( pxThreadState->pvYieldEvent ); + + /* Mutex will be released now so the (simulated) interrupt can + execute, so does not require releasing on function exit. */ + lMutexNeedsReleasing = pdFALSE; + ReleaseMutex( pvInterruptEventMutex ); + WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE ); + } + } + } + + if( pvInterruptEventMutex != NULL ) + { + if( lMutexNeedsReleasing == pdTRUE ) + { + configASSERT( xPortRunning ); + ReleaseMutex( pvInterruptEventMutex ); + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MSVC-MingW/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MSVC-MingW/portmacro.h new file mode 100644 index 0000000..edf2cc7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MSVC-MingW/portmacro.h @@ -0,0 +1,163 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include +#include + +/****************************************************************************** + Defines +******************************************************************************/ +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE size_t +#define portBASE_TYPE long +#define portPOINTER_SIZE_TYPE size_t + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32/64-bit tick type on a 32/64-bit architecture, so reads of the tick + count do not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portINLINE __inline + +#if defined( __x86_64__) || defined( _M_X64 ) + #define portBYTE_ALIGNMENT 8 +#else + #define portBYTE_ALIGNMENT 4 +#endif + +#define portYIELD() vPortGenerateSimulatedInterrupt( portINTERRUPT_YIELD ) + + +extern volatile BaseType_t xInsideInterrupt; +#define portSOFTWARE_BARRIER() while( xInsideInterrupt != pdFALSE ) + + +/* Simulated interrupts return pdFALSE if no context switch should be performed, +or a non-zero number if a context switch should be performed. */ +#define portYIELD_FROM_ISR( x ) ( void ) x +#define portEND_SWITCHING_ISR( x ) portYIELD_FROM_ISR( ( x ) ) + +void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield ); +void vPortDeleteThread( void *pvThreadToDelete ); +#define portCLEAN_UP_TCB( pxTCB ) vPortDeleteThread( pxTCB ) +#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortCloseRunningThread( ( pvTaskToDelete ), ( pxPendYield ) ) +#define portDISABLE_INTERRUPTS() vPortEnterCritical() +#define portENABLE_INTERRUPTS() vPortExitCritical() + +/* Critical section handling. */ +void vPortEnterCritical( void ); +void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + + /*-----------------------------------------------------------*/ + + #ifdef __GNUC__ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \ + __asm volatile( "bsr %1, %0\n\t" \ + :"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" ) + #else + /* BitScanReverse returns the bit position of the most significant '1' + in the word. */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) _BitScanReverse( ( DWORD * ) &( uxTopPriority ), ( uxReadyPriorities ) ) + #endif /* __GNUC__ */ + +#endif /* taskRECORD_READY_PRIORITY */ + +#ifndef __GNUC__ + __pragma( warning( disable:4211 ) ) /* Nonstandard extension used, as extern is only nonstandard to MSVC. */ +#endif + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portINTERRUPT_YIELD ( 0UL ) +#define portINTERRUPT_TICK ( 1UL ) + +/* + * Raise a simulated interrupt represented by the bit mask in ulInterruptMask. + * Each bit can be used to represent an individual interrupt - with the first + * two bits being used for the Yield and Tick interrupts respectively. +*/ +void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber ); + +/* + * Install an interrupt handler to be called by the simulated interrupt handler + * thread. The interrupt number must be above any used by the kernel itself + * (at the time of writing the kernel was using interrupt numbers 0, 1, and 2 + * as defined above). The number must also be lower than 32. + * + * Interrupt handler functions must return a non-zero value if executing the + * handler resulted in a task switch being required. + */ +void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) ); + +#endif + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/ReadMe.url b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/ReadMe.url new file mode 100644 index 0000000..4d2d044 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/ReadMe.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +URL=https://www.FreeRTOS.org/a00111.html +IDList= diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_1.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_1.c new file mode 100644 index 0000000..69c906a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_1.c @@ -0,0 +1,152 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * The simplest possible implementation of pvPortMalloc(). Note that this + * implementation does NOT allow allocated memory to be freed again. + * + * See heap_2.c, heap_3.c and heap_4.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +/* A few bytes might be lost to byte aligning the heap start address. */ +#define configADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT ) + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#else + static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/* Index into the ucHeap array. */ +static size_t xNextFreeByte = ( size_t ) 0; + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + void * pvReturn = NULL; + static uint8_t * pucAlignedHeap = NULL; + + /* Ensure that blocks are always aligned. */ + #if ( portBYTE_ALIGNMENT != 1 ) + { + if( xWantedSize & portBYTE_ALIGNMENT_MASK ) + { + /* Byte alignment required. Check for overflow. */ + if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) > xWantedSize ) + { + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + } + else + { + xWantedSize = 0; + } + } + } + #endif /* if ( portBYTE_ALIGNMENT != 1 ) */ + + vTaskSuspendAll(); + { + if( pucAlignedHeap == NULL ) + { + /* Ensure the heap starts on a correctly aligned boundary. */ + pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) & ucHeap[ portBYTE_ALIGNMENT - 1 ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); + } + + /* Check there is enough room left for the allocation and. */ + if( ( xWantedSize > 0 ) && /* valid size */ + ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) && + ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) ) /* Check for overflow. */ + { + /* Return the next free byte then increment the index past this + * block. */ + pvReturn = pucAlignedHeap + xNextFreeByte; + xNextFreeByte += xWantedSize; + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + vApplicationMallocFailedHook(); + } + } + #endif + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + /* Memory cannot be freed using this scheme. See heap_2.c, heap_3.c and + * heap_4.c for alternative implementations, and the memory management pages of + * https://www.FreeRTOS.org for more information. */ + ( void ) pv; + + /* Force an assert as it is invalid to call this function. */ + configASSERT( pv == NULL ); +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* Only required when static memory is not cleared. */ + xNextFreeByte = ( size_t ) 0; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return( configADJUSTED_HEAP_SIZE - xNextFreeByte ); +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_2.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_2.c new file mode 100644 index 0000000..f362bb4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_2.c @@ -0,0 +1,362 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * A sample implementation of pvPortMalloc() and vPortFree() that permits + * allocated blocks to be freed, but does not combine adjacent free blocks + * into a single larger block (and so will fragment memory). See heap_4.c for + * an equivalent that does combine adjacent blocks into single larger blocks. + * + * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +#ifndef configHEAP_CLEAR_MEMORY_ON_FREE + #define configHEAP_CLEAR_MEMORY_ON_FREE 0 +#endif + +/* A few bytes might be lost to byte aligning the heap start address. */ +#define configADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT ) + +/* Assumes 8bit bytes! */ +#define heapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define heapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if multiplying a and b will result in overflow. */ +#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) ) + +/* Check if adding a and b will result in overflow. */ +#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define heapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ) ) +#define heapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define heapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define heapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK ) +#define heapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK ) + +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#else + PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + + +/* Define the linked list structure. This is used to link free blocks in order + * of their size. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */ + size_t xBlockSize; /*<< The size of the free block. */ +} BlockLink_t; + + +static const uint16_t heapSTRUCT_SIZE = ( ( sizeof( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ) ); +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) ) + +/* Create a couple of list links to mark the start and end of the list. */ +PRIVILEGED_DATA static BlockLink_t xStart, xEnd; + +/* Keeps track of the number of free bytes remaining, but says nothing about + * fragmentation. */ +PRIVILEGED_DATA static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE; + +/*-----------------------------------------------------------*/ + +/* + * Initialises the heap structures before their first use. + */ +static void prvHeapInit( void ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */ + +/* + * Insert a block into the list of free blocks - which is ordered by size of + * the block. Small blocks at the start of the list and large blocks at the end + * of the list. + */ +#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \ + { \ + BlockLink_t * pxIterator; \ + size_t xBlockSize; \ + \ + xBlockSize = pxBlockToInsert->xBlockSize; \ + \ + /* Iterate through the list until a block is found that has a larger size */ \ + /* than the block we are inserting. */ \ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \ + { \ + /* There is nothing to do here - just iterate to the correct position. */ \ + } \ + \ + /* Update the list to include the block being inserted in the correct */ \ + /* position. */ \ + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \ + pxIterator->pxNextFreeBlock = pxBlockToInsert; \ + } +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + PRIVILEGED_DATA static BaseType_t xHeapHasBeenInitialised = pdFALSE; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + + vTaskSuspendAll(); + { + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( xHeapHasBeenInitialised == pdFALSE ) + { + prvHeapInit(); + xHeapHasBeenInitialised = pdTRUE; + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. Some + * additional increment may also be needed for alignment. */ + xAdditionalRequiredSize = heapSTRUCT_SIZE + portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); + + if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + + /* Check the block size we are trying to allocate is not so large that the + * top bit is set. The top bit of the block size member of the BlockLink_t + * structure is used to determine who owns the block - the application or + * the kernel, so it must be free. */ + if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Blocks are stored in byte order - traverse the list from the start + * (smallest) block until one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If we found the end marker then a block of adequate size was not found. */ + if( pxBlock != &xEnd ) + { + /* Return the memory space - jumping over the BlockLink_t structure + * at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE ); + + /* This block is being returned for use so must be taken out of the + * list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new block + * following the number of bytes requested. The void cast is + * used to prevent byte alignment warnings from the compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned + * by the application and has no "next" block. */ + heapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + } + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + vApplicationMallocFailedHook(); + } + } + #endif + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= heapSTRUCT_SIZE; + + /* This unexpected casting is to keep some compilers from issuing + * byte alignment warnings. */ + pxLink = ( void * ) puc; + + configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + configASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + heapFREE_BLOCK( pxLink ); + #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 ) + { + ( void ) memset( puc + heapSTRUCT_SIZE, 0, pxLink->xBlockSize - heapSTRUCT_SIZE ); + } + #endif + + vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + } + ( void ) xTaskResumeAll(); + } + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +void * pvPortCalloc( size_t xNum, + size_t xSize ) +{ + void * pv = NULL; + + if( heapMULTIPLY_WILL_OVERFLOW( xNum, xSize ) == 0 ) + { + pv = pvPortMalloc( xNum * xSize ); + + if( pv != NULL ) + { + ( void ) memset( pv, 0, xNum * xSize ); + } + } + + return pv; +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + + /* Ensure the heap starts on a correctly aligned boundary. */ + pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) & ucHeap[ portBYTE_ALIGNMENT - 1 ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* xEnd is used to mark the end of the list of free blocks. */ + xEnd.xBlockSize = configADJUSTED_HEAP_SIZE; + xEnd.pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space. */ + pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE; + pxFirstFreeBlock->pxNextFreeBlock = &xEnd; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_3.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_3.c new file mode 100644 index 0000000..70d73d7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_3.c @@ -0,0 +1,94 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Implementation of pvPortMalloc() and vPortFree() that relies on the + * compilers own malloc() and free() implementations. + * + * This file can only be used if the linker is configured to to generate + * a heap memory area. + * + * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ + +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + void * pvReturn; + + vTaskSuspendAll(); + { + pvReturn = malloc( xWantedSize ); + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + vApplicationMallocFailedHook(); + } + } + #endif + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + if( pv != NULL ) + { + vTaskSuspendAll(); + { + free( pv ); + traceFREE( pv, 0 ); + } + ( void ) xTaskResumeAll(); + } +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_4.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_4.c new file mode 100644 index 0000000..3af0caf --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_4.c @@ -0,0 +1,537 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * A sample implementation of pvPortMalloc() and vPortFree() that combines + * (coalescences) adjacent memory blocks as they are freed, and in so doing + * limits memory fragmentation. + * + * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +#ifndef configHEAP_CLEAR_MEMORY_ON_FREE + #define configHEAP_CLEAR_MEMORY_ON_FREE 0 +#endif + +/* Block sizes must not get too small. */ +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define heapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define heapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if multiplying a and b will result in overflow. */ +#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) ) + +/* Check if adding a and b will result in overflow. */ +#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define heapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ) ) +#define heapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define heapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define heapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK ) +#define heapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK ) + +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#else + PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/* Define the linked list structure. This is used to link free blocks in order + * of their memory address. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */ + size_t xBlockSize; /*<< The size of the free block. */ +} BlockLink_t; + +/*-----------------------------------------------------------*/ + +/* + * Inserts a block of memory that is being freed into the correct position in + * the list of free memory blocks. The block being freed will be merged with + * the block in front it and/or the block behind it if the memory blocks are + * adjacent to each other. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION; + +/* + * Called automatically to setup the required heap structures the first time + * pvPortMalloc() is called. + */ +static void prvHeapInit( void ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +/* The size of the structure placed at the beginning of each allocated memory + * block must by correctly byte aligned. */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + +/* Create a couple of list links to mark the start and end of the list. */ +PRIVILEGED_DATA static BlockLink_t xStart; +PRIVILEGED_DATA static BlockLink_t * pxEnd = NULL; + +/* Keeps track of the number of calls to allocate and free memory as well as the + * number of free bytes remaining, but says nothing about fragmentation. */ +PRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U; +PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0; + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + + vTaskSuspendAll(); + { + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. Some + * additional increment may also be needed for alignment. */ + xAdditionalRequiredSize = xHeapStructSize + portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); + + if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the block size we are trying to allocate is not so large that the + * top bit is set. The top bit of the block size member of the BlockLink_t + * structure is used to determine who owns the block - the application or + * the kernel, so it must be free. */ + if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size + * was not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the + * single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned + * by the application and has no "next" block. */ + heapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + xNumberOfSuccessfulAllocations++; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */ + + configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + configASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + heapFREE_BLOCK( pxLink ); + #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 ) + { + ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize ); + } + #endif + + vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + xNumberOfSuccessfulFrees++; + } + ( void ) xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +void * pvPortCalloc( size_t xNum, + size_t xSize ) +{ + void * pv = NULL; + + if( heapMULTIPLY_WILL_OVERFLOW( xNum, xSize ) == 0 ) + { + pv = pvPortMalloc( xNum * xSize ); + + if( pv != NULL ) + { + ( void ) memset( pv, 0, xNum * xSize ); + } + } + + return pv; +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + portPOINTER_SIZE_TYPE uxAddress; + size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( portPOINTER_SIZE_TYPE ) ucHeap; + + if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( portBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( portPOINTER_SIZE_TYPE ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( portPOINTER_SIZE_TYPE ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); + pxEnd = ( BlockLink_t * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock ); + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void vPortGetHeapStats( HeapStats_t * pxHeapStats ) +{ + BlockLink_t * pxBlock; + size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */ + + vTaskSuspendAll(); + { + pxBlock = xStart.pxNextFreeBlock; + + /* pxBlock will be NULL if the heap has not been initialised. The heap + * is initialised automatically when the first allocation is made. */ + if( pxBlock != NULL ) + { + while( pxBlock != pxEnd ) + { + /* Increment the number of blocks and record the largest block seen + * so far. */ + xBlocks++; + + if( pxBlock->xBlockSize > xMaxSize ) + { + xMaxSize = pxBlock->xBlockSize; + } + + if( pxBlock->xBlockSize < xMinSize ) + { + xMinSize = pxBlock->xBlockSize; + } + + /* Move to the next block in the chain until the last block is + * reached. */ + pxBlock = pxBlock->pxNextFreeBlock; + } + } + } + ( void ) xTaskResumeAll(); + + pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize; + pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize; + pxHeapStats->xNumberOfFreeBlocks = xBlocks; + + taskENTER_CRITICAL(); + { + pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining; + pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations; + pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees; + pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining; + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_5.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_5.c new file mode 100644 index 0000000..75fe5f1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MemMang/heap_5.c @@ -0,0 +1,594 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * A sample implementation of pvPortMalloc() that allows the heap to be defined + * across multiple non-contigous blocks and combines (coalescences) adjacent + * memory blocks as they are freed. + * + * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative + * implementations, and the memory management pages of https://www.FreeRTOS.org + * for more information. + * + * Usage notes: + * + * vPortDefineHeapRegions() ***must*** be called before pvPortMalloc(). + * pvPortMalloc() will be called if any task objects (tasks, queues, event + * groups, etc.) are created, therefore vPortDefineHeapRegions() ***must*** be + * called before any other objects are defined. + * + * vPortDefineHeapRegions() takes a single parameter. The parameter is an array + * of HeapRegion_t structures. HeapRegion_t is defined in portable.h as + * + * typedef struct HeapRegion + * { + * uint8_t *pucStartAddress; << Start address of a block of memory that will be part of the heap. + * size_t xSizeInBytes; << Size of the block of memory. + * } HeapRegion_t; + * + * The array is terminated using a NULL zero sized region definition, and the + * memory regions defined in the array ***must*** appear in address order from + * low address to high address. So the following is a valid example of how + * to use the function. + * + * HeapRegion_t xHeapRegions[] = + * { + * { ( uint8_t * ) 0x80000000UL, 0x10000 }, << Defines a block of 0x10000 bytes starting at address 0x80000000 + * { ( uint8_t * ) 0x90000000UL, 0xa0000 }, << Defines a block of 0xa0000 bytes starting at address of 0x90000000 + * { NULL, 0 } << Terminates the array. + * }; + * + * vPortDefineHeapRegions( xHeapRegions ); << Pass the array into vPortDefineHeapRegions(). + * + * Note 0x80000000 is the lower address so appears in the array first. + * + */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +#ifndef configHEAP_CLEAR_MEMORY_ON_FREE + #define configHEAP_CLEAR_MEMORY_ON_FREE 0 +#endif + +/* Block sizes must not get too small. */ +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define heapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define heapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if multiplying a and b will result in overflow. */ +#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) ) + +/* Check if adding a and b will result in overflow. */ +#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define heapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ) ) +#define heapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define heapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define heapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK ) +#define heapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK ) + +/*-----------------------------------------------------------*/ + +/* Define the linked list structure. This is used to link free blocks in order + * of their memory address. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */ + size_t xBlockSize; /*<< The size of the free block. */ +} BlockLink_t; + +/*-----------------------------------------------------------*/ + +/* + * Inserts a block of memory that is being freed into the correct position in + * the list of free memory blocks. The block being freed will be merged with + * the block in front it and/or the block behind it if the memory blocks are + * adjacent to each other. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); + +/*-----------------------------------------------------------*/ + +/* The size of the structure placed at the beginning of each allocated memory + * block must by correctly byte aligned. */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + +/* Create a couple of list links to mark the start and end of the list. */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/* Keeps track of the number of calls to allocate and free memory as well as the + * number of free bytes remaining, but says nothing about fragmentation. */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; +static size_t xNumberOfSuccessfulAllocations = 0; +static size_t xNumberOfSuccessfulFrees = 0; + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + + /* The heap must be initialised before the first call to + * prvPortMalloc(). */ + configASSERT( pxEnd ); + + vTaskSuspendAll(); + { + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. Some + * additional increment may also be needed for alignment. */ + xAdditionalRequiredSize = xHeapStructSize + portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); + + if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the block size we are trying to allocate is not so large that the + * top bit is set. The top bit of the block size member of the BlockLink_t + * structure is used to determine who owns the block - the application or + * the kernel, so it must be free. */ + if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size + * was not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + + /* Calculate the sizes of two blocks split from the + * single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned + * by the application and has no "next" block. */ + heapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + xNumberOfSuccessfulAllocations++; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */ + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + configASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + heapFREE_BLOCK( pxLink ); + #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 ) + { + ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize ); + } + #endif + + vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + xNumberOfSuccessfulFrees++; + } + ( void ) xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void * pvPortCalloc( size_t xNum, + size_t xSize ) +{ + void * pv = NULL; + + if( heapMULTIPLY_WILL_OVERFLOW( xNum, xSize ) == 0 ) + { + pv = pvPortMalloc( xNum * xSize ); + + if( pv != NULL ) + { + ( void ) memset( pv, 0, xNum * xSize ); + } + } + + return pv; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) +{ + BlockLink_t * pxFirstFreeBlockInRegion = NULL; + BlockLink_t * pxPreviousFreeBlock; + portPOINTER_SIZE_TYPE xAlignedHeap; + size_t xTotalRegionSize, xTotalHeapSize = 0; + BaseType_t xDefinedRegions = 0; + portPOINTER_SIZE_TYPE xAddress; + const HeapRegion_t * pxHeapRegion; + + /* Can only call once! */ + configASSERT( pxEnd == NULL ); + + pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] ); + + while( pxHeapRegion->xSizeInBytes > 0 ) + { + xTotalRegionSize = pxHeapRegion->xSizeInBytes; + + /* Ensure the heap region starts on a correctly aligned boundary. */ + xAddress = ( portPOINTER_SIZE_TYPE ) pxHeapRegion->pucStartAddress; + + if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + { + xAddress += ( portBYTE_ALIGNMENT - 1 ); + xAddress &= ~portBYTE_ALIGNMENT_MASK; + + /* Adjust the size for the bytes lost to alignment. */ + xTotalRegionSize -= ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxHeapRegion->pucStartAddress ); + } + + xAlignedHeap = xAddress; + + /* Set xStart if it has not already been set. */ + if( xDefinedRegions == 0 ) + { + /* xStart is used to hold a pointer to the first item in the list of + * free blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + } + else + { + /* Should only get here if one region has already been added to the + * heap. */ + configASSERT( pxEnd != NULL ); + + /* Check blocks are passed in with increasing start addresses. */ + configASSERT( xAddress > ( size_t ) pxEnd ); + } + + /* Remember the location of the end marker in the previous region, if + * any. */ + pxPreviousFreeBlock = pxEnd; + + /* pxEnd is used to mark the end of the list of free blocks and is + * inserted at the end of the region space. */ + xAddress = xAlignedHeap + xTotalRegionSize; + xAddress -= xHeapStructSize; + xAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + pxEnd = ( BlockLink_t * ) xAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block in this region that is + * sized to take up the entire heap region minus the space taken by the + * free block structure. */ + pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap; + pxFirstFreeBlockInRegion->xBlockSize = ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlockInRegion ); + pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd; + + /* If this is not the first region that makes up the entire heap space + * then link the previous region to this region. */ + if( pxPreviousFreeBlock != NULL ) + { + pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion; + } + + xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize; + + /* Move onto the next HeapRegion_t structure. */ + xDefinedRegions++; + pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] ); + } + + xMinimumEverFreeBytesRemaining = xTotalHeapSize; + xFreeBytesRemaining = xTotalHeapSize; + + /* Check something was actually defined before it is accessed. */ + configASSERT( xTotalHeapSize ); +} +/*-----------------------------------------------------------*/ + +void vPortGetHeapStats( HeapStats_t * pxHeapStats ) +{ + BlockLink_t * pxBlock; + size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */ + + vTaskSuspendAll(); + { + pxBlock = xStart.pxNextFreeBlock; + + /* pxBlock will be NULL if the heap has not been initialised. The heap + * is initialised automatically when the first allocation is made. */ + if( pxBlock != NULL ) + { + while( pxBlock != pxEnd ) + { + /* Increment the number of blocks and record the largest block seen + * so far. */ + xBlocks++; + + if( pxBlock->xBlockSize > xMaxSize ) + { + xMaxSize = pxBlock->xBlockSize; + } + + /* Heap five will have a zero sized block at the end of each + * each region - the block is only used to link to the next + * heap region so it not a real block. */ + if( pxBlock->xBlockSize != 0 ) + { + if( pxBlock->xBlockSize < xMinSize ) + { + xMinSize = pxBlock->xBlockSize; + } + } + + /* Move to the next block in the chain until the last block is + * reached. */ + pxBlock = pxBlock->pxNextFreeBlock; + } + } + } + ( void ) xTaskResumeAll(); + + pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize; + pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize; + pxHeapStats->xNumberOfFreeBlocks = xBlocks; + + taskENTER_CRITICAL(); + { + pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining; + pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations; + pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees; + pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining; + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MikroC/ARM_CM4F/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MikroC/ARM_CM4F/port.c new file mode 100644 index 0000000..62ee42a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MikroC/ARM_CM4F/port.c @@ -0,0 +1,841 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* Cannot find a weak linkage attribute, so the + * configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if the + * application writer wants to provide their own implementation of + * vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION + * is defined. */ +#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION + #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0 +#endif + +/* Manual definition of missing asm names. */ +#define psp 9 +#define basepri 17 +#define msp 8 +#define ipsr 5 +#define control 20 + +/* From port.c. */ +extern void * pxCurrentTCB; + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask( void ); + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + /* Sometimes the parameters are loaded from the stack. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) iv IVT_INT_SVCall ics ICS_OFF +{ + __asm { +/* *INDENT-OFF* */ + ldr r3, =_pxCurrentTCB /* Restore the context. */ + ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ + ldm r0 !, ( r4 - r11, r14 ) /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + msr psp, r0 /* Restore the task stack pointer. */ + isb + mov r0, #0 + msr basepri, r0 + bx r14 +/* *INDENT-ON* */ + }; +} +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask( void ) +{ + __asm { +/* *INDENT-OFF* */ + ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [ r0 ] + ldr r0, [ r0 ] + msr msp, r0 /* Set the msp back to the start of the stack. */ + + /* Clear the bit that indicates the FPU is in use in case the FPU was used + * before the scheduler was started - which would otherwise result in the + * unnecessary leaving of space in the SVC stack for lazy saving of FPU + * registers. */ + mov r0, #0 + msr control, r0 + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc #0 /* System call to start first task. */ + nop +/* *INDENT-ON* */ + }; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* The kernel interrupt priority should be set to the lowest + * priority. */ + configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. */ + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +const uint8_t ucMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY; +void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF +{ + __asm { + #ifdef HW_DEBUG +/* *INDENT-OFF* */ + + /* The function is not truly naked, so add back the 4 bytes subtracted + * from the stack pointer by the function prologue. */ + add sp, sp, # 4 + #endif + mrs r0, psp + isb + + ldr r3, =_pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [ r3 ] + + tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */ + it eq + vstmdbeq r0 !, ( s16 - s31 ) + + stmdb r0 !, ( r4 - r11, r14 ) /* Save the core registers. */ + + str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */ + + stmdb sp !, ( r0, r3 ) + ldr r0, = _ucMaxSyscallInterruptPriority + ldr r1, [ r0 ] + msr basepri, r1 + dsb + isb + bl _vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldm sp !, ( r0, r3 ) + + ldr r1, [ r3 ] /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r0, [ r1 ] + + ldm r0 !, ( r4 - r11, r14 ) /* Pop the core registers. */ + + tst r14, #0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */ + it eq + vldmiaeq r0 !, ( s16 - s31 ) + + msr psp, r0 + isb + bx r14 +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known - therefore the slightly faster portDISABLE_INTERRUPTS() function is + * used in place of portSET_INTERRUPT_MASK_FROM_ISR(). */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_TICKLESS_IDLE == 1 ) && ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) ) + + void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm { + "cpsid i" + }; + __asm { + "dsb" + }; + __asm { + "isb" + }; + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm { + "cpsie i" + }; + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm { + "dsb" + }; + __asm { + "wfi" + }; + __asm { + "isb" + }; + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __asm { + "cpsie i" + }; + __asm { + "dsb" + }; + __asm { + "isb" + }; + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm { + "cpsid i" + }; + __asm { + "dsb" + }; + __asm { + "isb" + }; + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm { + "cpsie i" + }; + } + } + + #endif /* #if configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ + #if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) + + void vPortSetupTimerInterrupt( void ) + { + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Reset SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); + } + + #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */ +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm { +/* *INDENT-OFF* */ + ldr r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */ + ldr r1, [ r0 ] + + orr r1, r1, #0xF00000 /* Enable CP10 and CP11 coprocessors, then save back. */ + str r1, [ r0 ] + bx r14 +/* *INDENT-ON* */ + }; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + if( CPU_REG_GET( CPU_IPSR ) == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + + #if ( configASSERT_DEFINED == 1 ) + +/* Limitations in the MikroC inline asm means ulCurrentInterrupt has to be + * global - which makes vPortValidateInterruptPriority() non re-entrant. + * However that should not matter as an interrupt can only itself be + * interrupted by a higher priority interrupt. That means if + * ulCurrentInterrupt, so ulCurrentInterrupt getting corrupted cannot lead to + * an invalid interrupt priority being missed. */ + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + void vPortValidateInterruptPriority( void ) + { + /* Obtain the number of the currently executing interrupt. */ + __asm { +/* *INDENT-OFF* */ + push( r0, r1 ) + mrs r0, ipsr + ldr r1, =_ulCurrentInterrupt + str r0, [ r1 ] + pop( r0, r1 ) +/* *INDENT-ON* */ + }; + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = *( ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + ulCurrentInterrupt ) ); + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + + #endif /* configASSERT_DEFINED */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MikroC/ARM_CM4F/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MikroC/ARM_CM4F/portmacro.h new file mode 100644 index 0000000..ffb69d9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/MikroC/ARM_CM4F/portmacro.h @@ -0,0 +1,190 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* The compiler needs to be told functions that are only referenced by pointer + * are to be included in the build. NOTE: Omitting these lines will result in a + * run-time crash, not a linker error! */ + #pragma funcall vTaskStartScheduler prvIdleTask + #pragma funcall xTimerCreateTimerTask prvTimerTask + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm{ dsb }; \ + __asm{ isb }; \ + } + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + #define portDISABLE_INTERRUPTS() CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm{ dsb }; __asm{ isb } + #define portENABLE_INTERRUPTS() CPU_REG_SET( CPU_BASEPRI, 0 ); + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) CPU_REG_SET( CPU_BASEPRI, x ); /* Barrier instructions not used as this is only used to lower the basepri. */ + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + BaseType_t xPortIsInsideInterrupt( void ); + +/*-----------------------------------------------------------*/ + + static inline uint32_t ulPortRaiseBASEPRI( void ) + { + uint32_t ulOriginalBASEPRI; + + ulOriginalBASEPRI = CPU_REG_GET( CPU_BASEPRI ); + CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY ); + __asm{ dsb }; + __asm{ isb }; + return ulOriginalBASEPRI; + } +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/large_untested/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/large_untested/port.c new file mode 100644 index 0000000..1880af7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/large_untested/port.c @@ -0,0 +1,240 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Tern EE 186 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/* The timer increments every four clocks, hence the divide by 4. */ +#define portTIMER_COMPARE ( uint16_t ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( uint32_t ) 4 ) + +/* From the RDC data sheet. */ +#define portENABLE_TIMER_AND_INTERRUPT ( uint16_t ) 0xe001 + +/* Interrupt control. */ +#define portEIO_REGISTER 0xff22 +#define portCLEAR_INTERRUPT 0x0008 + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetupTimerInterrupt( void ); + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/* The timer initialisation functions leave interrupts enabled, +which is not what we want. This ISR is installed temporarily in case +the timer fires before we get a change to disable interrupts again. */ +static void __interrupt __far prvDummyISR( void ); + +/*-----------------------------------------------------------*/ +/* See header file for description. */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t DS_Reg = 0; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + function call with parameters preamble. */ + + *pxTopOfStack = FP_SEG( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* Next the status register and interrupt return address. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */ + pxTopOfStack--; + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + *pxTopOfStack = DS_Reg; /* DS */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Put our manual switch (yield) function on a known + vector. */ + setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Setup the tick interrupt. */ + prvSetupTimerInterrupt(); + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + + /* Should not get here! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvDummyISR( void ) +{ + /* The timer initialisation functions leave interrupts enabled, + which is not what we want. This ISR is installed temporarily in case + the timer fires before we get a change to disable interrupts again. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + } + + /* Reset interrupt. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + xTaskIncrementTick(); + + /* Reset interrupt. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +const uint16_t usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT; +const uint16_t usT2_IRQ = 0x13; + + /* Configure the timer, the dummy handler is used here as the init + function leaves interrupts enabled. */ + t2_init( usTimerAMode, usTimerACompare, prvDummyISR ); + + /* Disable interrupts again before installing the real handlers. */ + portDISABLE_INTERRUPTS(); + + #if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + setvect( usT2_IRQ, prvPreemptiveTick ); + #else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + setvect( usT2_IRQ, prvNonPreemptiveTick ); + #endif +} + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/large_untested/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/large_untested/portasm.h new file mode 100644 index 0000000..6e8cc03 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/large_untested/portasm.h @@ -0,0 +1,77 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portSWITCH_CONTEXT( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +#define portSWITCH_CONTEXT() \ + asm { mov ax, seg pxCurrentTCB } \ + asm { mov ds, ax } \ + asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \ + asm { mov es:0x2[ bx ], ss } \ + asm { mov es:[ bx ], sp } \ + asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \ + asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \ + asm { mov ds, ax } \ + asm { les bx, dword ptr pxCurrentTCB } \ + asm { mov ss, es:[ bx + 2 ] } \ + asm { mov sp, es:[ bx ] } + +#define portFIRST_CONTEXT() \ + asm { mov ax, seg pxCurrentTCB } \ + asm { mov ds, ax } \ + asm { les bx, dword ptr pxCurrentTCB } \ + asm { mov ss, es:[ bx + 2 ] } \ + asm { mov sp, es:[ bx ] } \ + asm { pop bp } \ + asm { pop di } \ + asm { pop si } \ + asm { pop ds } \ + asm { pop es } \ + asm { pop dx } \ + asm { pop cx } \ + asm { pop bx } \ + asm { pop ax } \ + asm { iret } + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/large_untested/portmacro.h new file mode 100644 index 0000000..aabdd9a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/large_untested/portmacro.h @@ -0,0 +1,107 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/small/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/small/port.c new file mode 100644 index 0000000..5e5ddad --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/small/port.c @@ -0,0 +1,220 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Tern EE 186 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/* The timer increments every four clocks, hence the divide by 4. */ +#define portPRESCALE_VALUE ( 16 ) +#define portTIMER_COMPARE ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 4UL ) ) + +/* From the RDC data sheet. */ +#define portENABLE_TIMER_AND_INTERRUPT ( uint16_t ) 0xe00b +#define portENABLE_TIMER ( uint16_t ) 0xC001 + +/* Interrupt control. */ +#define portEIO_REGISTER 0xff22 +#define portCLEAR_INTERRUPT 0x0008 + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetupTimerInterrupt( void ); + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/*-----------------------------------------------------------*/ +/* See header file for description. */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t DS_Reg = 0; + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + function call with parameters preamble. */ + + *pxTopOfStack = FP_OFF( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* Next the status register and interrupt return address. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */ + pxTopOfStack--; + + *pxTopOfStack = DS_Reg; /* DS */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Put our manual switch (yield) function on a known + vector. */ + setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Setup the tick interrupt. */ + prvSetupTimerInterrupt(); + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + + /* Should not get here! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch in the context of the next task to be run. */ + portEND_SWITCHING_ISR(); + } + + /* Reset interrupt. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + xTaskIncrementTick(); + + /* Reset interrupt. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portEND_SWITCHING_ISR(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +const uint32_t ulCompareValue = portTIMER_COMPARE; +uint16_t usTimerCompare; + + usTimerCompare = ( uint16_t ) ( ulCompareValue >> 4 ); + t2_init( portENABLE_TIMER, portPRESCALE_VALUE, NULL ); + + #if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvPreemptiveTick ); + #else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvNonPreemptiveTick ); + #endif +} + + + + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/small/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/small/portasm.h new file mode 100644 index 0000000..82ead2b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/small/portasm.h @@ -0,0 +1,73 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORT_ASM_H +#define PORT_ASM_H + +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portEND_SWITCHING_ISR( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +#define portEND_SWITCHING_ISR() \ + asm { mov bx, [pxCurrentTCB] } \ + asm { mov word ptr [bx], sp } \ + asm { call far ptr vTaskSwitchContext } \ + asm { mov bx, [pxCurrentTCB] } \ + asm { mov sp, [bx] } + +#define portFIRST_CONTEXT() \ + asm { mov bx, [pxCurrentTCB] } \ + asm { mov sp, [bx] } \ + asm { pop bp } \ + asm { pop di } \ + asm { pop si } \ + asm { pop ds } \ + asm { pop es } \ + asm { pop dx } \ + asm { pop cx } \ + asm { pop bx } \ + asm { pop ax } \ + asm { iret } + + +#endif + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/small/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/small/portmacro.h new file mode 100644 index 0000000..c08a174 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Paradigm/Tern_EE/small/portmacro.h @@ -0,0 +1,108 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +typedef void ( __interrupt __far *pxISR )(); + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM7_LPC21xx/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM7_LPC21xx/port.c new file mode 100644 index 0000000..13cc539 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM7_LPC21xx/port.c @@ -0,0 +1,292 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) + +/*-----------------------------------------------------------*/ + +/* The code generated by the Keil compiler does not maintain separate +stack and frame pointers. The portENTER_CRITICAL macro cannot therefore +use the stack as per other ports. Instead a variable is used to keep +track of the critical section nesting. This variable has to be stored +as part of the task context and must be initialised to a non zero value. */ + +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortStartFirstSTask() is defined in portISR.c. + */ +extern __asm void vPortStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. + + Remember where the top of the (simulated) stack is before we place + anything on it. */ + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* The code generated by the Keil compiler does not maintain separate + stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + use the stack as per other ports. Instead a variable is used to keep + track of the critical section nesting. This variable has to be stored + as part of the task context and is initially set to zero. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. */ + prvSetupTimerInterrupt(); + + /* Start the first task. This is done from portISR.c as ARM mode must be + used. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. If this is required - stop the tick ISR then + return back to main. */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + + /* + * The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. + */ + void vNonPreemptiveTick( void ) __irq; + void vNonPreemptiveTick( void ) __irq + { + /* Increment the tick count - this may make a delaying task ready + to run - but a context switch is not performed. */ + xTaskIncrementTick(); + + T0IR = portTIMER_MATCH_ISR_BIT; /* Clear the timer event */ + VICVectAddr = portCLEAR_VIC_INTERRUPT; /* Acknowledge the Interrupt */ + } + + #else + + /* + ************************************************************************** + * The preemptive scheduler ISR is written in assembler and can be found + * in the portASM.s file. This will only get used if portUSE_PREEMPTION + * is set to 1 in portmacro.h + ************************************************************************** + */ + + void vPreemptiveTick( void ); + +#endif +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +uint32_t ulCompareMatch; + + /* A 1ms tick does not require the use of the timer prescale. This is + defaulted to zero but can be used if necessary. */ + T0PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + + T0MR0 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; + + /* Setup the VIC for the timer. */ + VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); + VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; + + /* The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + VICVectAddr0 = ( uint32_t ) vPreemptiveTick; + } + #else + { + VICVectAddr0 = ( uint32_t ) vNonPreemptiveTick; + } + #endif + + VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; + + /* Start the timer - interrupts are disabled when this function is called + so it is okay to do this here. */ + T0TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + __disable_irq(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + __enable_irq(); + } + } +} +/*-----------------------------------------------------------*/ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM7_LPC21xx/portASM.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM7_LPC21xx/portASM.s new file mode 100644 index 0000000..70e26c8 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM7_LPC21xx/portASM.s @@ -0,0 +1,125 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + INCLUDE portmacro.inc + + IMPORT vTaskSwitchContext + IMPORT xTaskIncrementTick + + EXPORT vPortYieldProcessor + EXPORT vPortStartFirstTask + EXPORT vPreemptiveTick + EXPORT vPortYield + + +VICVECTADDR EQU 0xFFFFF030 +T0IR EQU 0xE0004000 +T0MATCHBIT EQU 0x00000001 + + ARM + AREA PORT_ASM, CODE, READONLY + + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is done by just restoring the context +; setup by pxPortInitialiseStack +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask + + PRESERVE8 + + portRESTORE_CONTEXT + +vPortYield + + PRESERVE8 + + SVC 0 + bx lr + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Interrupt service routine for the SWI interrupt. The vector table is +; configured in the startup.s file. +; +; vPortYieldProcessor() is used to manually force a context switch. The +; SWI interrupt is generated by a call to taskYIELD() or portYIELD(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +vPortYieldProcessor + + PRESERVE8 + + ; Within an IRQ ISR the link register has an offset from the true return + ; address, but an SWI ISR does not. Add the offset manually so the same + ; ISR return code can be used in both cases. + ADD LR, LR, #4 + + ; Perform the context switch. + portSAVE_CONTEXT ; Save current task context + LDR R0, =vTaskSwitchContext ; Get the address of the context switch function + MOV LR, PC ; Store the return address + BX R0 ; Call the contedxt switch function + portRESTORE_CONTEXT ; restore the context of the selected task + + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Interrupt service routine for preemptive scheduler tick timer +; Only used if portUSE_PREEMPTION is set to 1 in portmacro.h +; +; Uses timer 0 of LPC21XX Family +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +vPreemptiveTick + + PRESERVE8 + + portSAVE_CONTEXT ; Save the context of the current task. + + LDR R0, =xTaskIncrementTick ; Increment the tick count. + MOV LR, PC ; This may make a delayed task ready + BX R0 ; to run. + + CMP R0, #0 + BEQ SkipContextSwitch + LDR R0, =vTaskSwitchContext ; Find the highest priority task that + MOV LR, PC ; is ready to run. + BX R0 +SkipContextSwitch + MOV R0, #T0MATCHBIT ; Clear the timer event + LDR R1, =T0IR + STR R0, [R1] + + LDR R0, =VICVECTADDR ; Acknowledge the interrupt + STR R0,[R0] + + portRESTORE_CONTEXT ; Restore the context of the highest + ; priority task that is ready to run. + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM7_LPC21xx/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM7_LPC21xx/portmacro.h new file mode 100644 index 0000000..4e43f41 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM7_LPC21xx/portmacro.h @@ -0,0 +1,151 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/*----------------------------------------------------------- + * ISR entry and exit macros. These are only required if a task switch + * is required from an ISR. + *----------------------------------------------------------*/ + +/* If a switch is required then we just need to call */ +/* vTaskSwitchContext() as the context has already been */ +/* saved. */ + +#define portEXIT_SWITCHING_ISR(SwitchRequired) \ +{ \ +extern void vTaskSwitchContext(void); \ + \ + if(SwitchRequired) \ + { \ + vTaskSwitchContext(); \ + } \ +} \ + +extern void vPortYield( void ); +#define portYIELD() vPortYield() + + +/* Critical section management. */ + +/* + ****************************************************************** + * We don't need to worry about whether we're in ARM or + * THUMB mode with the Keil Real View compiler when enabling + * or disabling interrupts as the compiler's intrinsic functions + * take care of that for us. + ******************************************************************* + */ +#define portDISABLE_INTERRUPTS() __disable_irq() +#define portENABLE_INTERRUPTS() __enable_irq() + + +/*----------------------------------------------------------- + * Critical section control + * + * The code generated by the Keil compiler does not maintain separate + * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + * use the stack as per other ports. Instead a variable is used to keep + * track of the critical section nesting. This necessitates the use of a + * function in place of the macro. + *----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline +#define register +#define portNOP() __asm{ NOP } +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM7_LPC21xx/portmacro.inc b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM7_LPC21xx/portmacro.inc new file mode 100644 index 0000000..50f93bb --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM7_LPC21xx/portmacro.inc @@ -0,0 +1,92 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + IMPORT ulCriticalNesting ; + IMPORT pxCurrentTCB ; + + + MACRO + portRESTORE_CONTEXT + + + LDR R0, =pxCurrentTCB ; Set the LR to the task stack. The location was... + LDR R0, [R0] ; ... stored in pxCurrentTCB + LDR LR, [R0] + + LDR R0, =ulCriticalNesting ; The critical nesting depth is the first item on... + LDMFD LR!, {R1} ; ...the stack. Load it into the ulCriticalNesting var. + STR R1, [R0] ; + + LDMFD LR!, {R0} ; Get the SPSR from the stack. + MSR SPSR_cxsf, R0 ; + + LDMFD LR, {R0-R14}^ ; Restore all system mode registers for the task. + NOP ; + + LDR LR, [LR, #+60] ; Restore the return address + + ; And return - correcting the offset in the LR to obtain ... + SUBS PC, LR, #4 ; ...the correct address. + + MEND + +; /**********************************************************************/ + + MACRO + portSAVE_CONTEXT + + + STMDB SP!, {R0} ; Store R0 first as we need to use it. + + STMDB SP,{SP}^ ; Set R0 to point to the task stack pointer. + NOP ; + SUB SP, SP, #4 ; + LDMIA SP!,{R0} ; + + STMDB R0!, {LR} ; Push the return address onto the stack. + MOV LR, R0 ; Now we have saved LR we can use it instead of R0. + LDMIA SP!, {R0} ; Pop R0 so we can save it onto the system mode stack. + + STMDB LR,{R0-LR}^ ; Push all the system mode registers onto the task stack. + NOP ; + SUB LR, LR, #60 ; + + MRS R0, SPSR ; Push the SPSR onto the task stack. + STMDB LR!, {R0} ; + + LDR R0, =ulCriticalNesting ; + LDR R0, [R0] ; + STMDB LR!, {R0} ; + + LDR R0, =pxCurrentTCB ; Store the new top of stack for the task. + LDR R1, [R0] ; + STR LR, [R1] ; + + MEND + + END diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CA9/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CA9/port.c new file mode 100644 index 0000000..51815b0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CA9/port.c @@ -0,0 +1,481 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS + #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET + #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #define configCLEAR_TICK_INTERRUPT() +#endif + +/* The number of bits to shift for an interrupt priority is dependent on the +number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif + +/* A critical section is exited when the critical section nesting count reaches +this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* In all GICs 255 can be written to the priority mask register to unmask all +(but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) + +/* Tasks are not created with a floating point context, but can be given a +floating point context after they have been created. A variable is stored as +part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task +does not have an FPU context, or any other value if the task does have an FPU +context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Interrupt controller access addresses. */ +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) + +/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary +point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user +mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* Macro to unmask all interrupt priorities. */ +#define portCLEAR_INTERRUPT_MASK() \ +{ \ + __disable_irq(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm( "DSB \n" \ + "ISB \n" ); \ + __enable_irq(); \ +} + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This +variable has to be stored as part of the task context and must be initialised to +a non zero value to ensure interrupts don't inadvertently become unmasked before +the scheduler starts. As it is stored as part of the task context it will +automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Used to pass constants into the ASM code. The address at which variables are +placed is the constant value so indirect loads in the asm code are not +required. */ +uint32_t ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) ); +uint32_t ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) ); +uint32_t ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) ); +uint32_t ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) ); + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then +a floating point context must be saved and restored for the task. */ +uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if +if the nesting depth is 0. */ +uint32_t ulPortInterruptNesting = 0UL; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. + + The fist real value on the stack is the status register, which is set for + system mode, with interrupts enabled. A few NULLs are added first to ensure + GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + the floating point hardware must call vPortTaskUsesFPU() before executing + any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +uint32_t ulAPSR; + + /* Only continue if the CPU is not in User mode. The CPU must be in a + Privileged mode for the scheduler to start. */ + __asm( "MRS ulAPSR, APSR" ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Only continue if the binary point value is set to its lowest possible + setting. See the comments in vPortValidateInterruptPriority() below for + more information. */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + + if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) + { + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + __enable_irq(); + vPortRestoreTaskContext(); + } + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + a non-privileged mode or the binary point register was not set to its lowest + possible value. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + ulPortSetInterruptMask(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + should be unmasked. */ + portCLEAR_INTERRUPT_MASK(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* Set interrupt mask before altering scheduler structures. The tick + handler runs at the lowest priority, so interrupts cannot already be masked, + so there is no need to save and restore the current mask value. */ + __disable_irq(); + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm( "DSB \n" + "ISB \n" ); + __enable_irq(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK(); + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ +uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm( "FMXR FPSCR, ulInitialFPSCR" ); +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( uint32_t ulNewMaskValue ) +{ + if( ulNewMaskValue == pdFALSE ) + { + portCLEAR_INTERRUPT_MASK(); + } +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortSetInterruptMask( void ) +{ +uint32_t ulReturn; + + __disable_irq(); + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + /* Interrupts were already masked. */ + ulReturn = pdTRUE; + } + else + { + ulReturn = pdFALSE; + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm( "DSB \n" + "ISB \n" ); + } + __enable_irq(); + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +#if( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* The following assertion will fail if a service routine (ISR) for + an interrupt that has been assigned a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + function. ISR safe FreeRTOS API functions must *only* be called + from interrupts that have been assigned a priority at or below + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Numerically low interrupt priority numbers represent logically high + interrupt priorities, therefore the priority of the interrupt must + be set to a value equal to or numerically *higher* than + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + FreeRTOS maintains separate thread and ISR API functions to ensure + interrupt entry is as fast and simple as possible. + + The following links provide detailed information: + https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + + /* Priority grouping: The interrupt controller (GIC) allows the bits + that define each interrupt's priority to be split between bits that + define the interrupt's pre-emption priority bits and bits that define + the interrupt's sub-priority. For simplicity all bits must be defined + to be pre-emption priority bits. The following assertion will fail if + this is not the case (if some bits represent a sub-priority). + + The priority grouping is configured by the GIC's binary point register + (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest + possible value (which may be above 0). */ + configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE ); + } + +#endif /* configASSERT_DEFINED */ + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CA9/portASM.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CA9/portASM.s new file mode 100644 index 0000000..9d4db93 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CA9/portASM.s @@ -0,0 +1,175 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + INCLUDE portmacro.inc + + IMPORT vApplicationIRQHandler + IMPORT vTaskSwitchContext + IMPORT ulPortYieldRequired + IMPORT ulPortInterruptNesting + IMPORT vTaskSwitchContext + IMPORT ulICCIAR + IMPORT ulICCEOIR + + EXPORT FreeRTOS_SWI_Handler + EXPORT FreeRTOS_IRQ_Handler + EXPORT vPortRestoreTaskContext + + ARM + AREA PORT_ASM, CODE, READONLY + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC handler is used to yield a task. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_SWI_Handler + + PRESERVE8 + + ; Save the context of the current task and select a new task to run. + portSAVE_CONTEXT + LDR R0, =vTaskSwitchContext + BLX R0 + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; vPortRestoreTaskContext is used to start the scheduler. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortRestoreTaskContext + ; Switch to system mode + CPS #SYS_MODE + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; PL390 GIC interrupt handler +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_IRQ_Handler + + ; Return to the interrupted instruction. + SUB lr, lr, #4 + + ; Push the return address and SPSR + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + ; Change to supervisor mode to allow reentry. + CPS #SVC_MODE + + ; Push used registers. + PUSH {r0-r4, r12} + + ; Increment nesting count. r3 holds the address of ulPortInterruptNesting + ; for future use. r1 holds the original ulPortInterruptNesting value for + ; future use. + LDR r3, =ulPortInterruptNesting + LDR r1, [r3] + ADD r4, r1, #1 + STR r4, [r3] + + ; Read value from the interrupt acknowledge register, which is stored in r0 + ; for future parameter and interrupt clearing use. + LDR r2, =ulICCIAR + LDR r0, [r2] + + ; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + ; future use. _RB_ Does this ever actually need to be done provided the + ; start of the stack is 8-byte aligned? + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + ; Call the interrupt handler. r4 is pushed to maintain alignment. + PUSH {r0-r4, lr} + LDR r1, =vApplicationIRQHandler + BLX r1 + POP {r0-r4, lr} + ADD sp, sp, r2 + + CPSID i + + ; Write the value read from ICCIAR to ICCEOIR + LDR r4, =ulICCEOIR + STR r0, [r4] + + ; Restore the old nesting count + STR r1, [r3] + + ; A context switch is never performed if the nesting count is not 0 + CMP r1, #0 + BNE exit_without_switch + + ; Did the interrupt request a context switch? r1 holds the address of + ; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + ; use. + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch + ; No context switch. Restore used registers, LR_irq and SPSR before + ; returning. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit + ; A context swtich is to be performed. Clear the context switch pending + ; flag. + MOV r0, #0 + STR r0, [r1] + + ; Restore used registers, LR-irq and SPSR before saving the context + ; to the task stack. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + ; Call the function that selects the new task to execute. + ; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + ; instructions, or 8 byte aligned stack allocated data. LR does not need + ; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. + LDR r0, =vTaskSwitchContext + BLX r0 + + ; Restore the context of, and branch to, the task selected to execute next. + portRESTORE_CONTEXT + + + END + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CA9/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CA9/portmacro.h new file mode 100644 index 0000000..e2051e1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CA9/portmacro.h @@ -0,0 +1,172 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired )\ +{ \ +extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ +} + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm( "SWI 0" ); + + +/*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); + +/* These macros do not globally disable/enable interrupts. They do mask off +interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() +#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not required for this port but included in case common demo code that uses these +macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the +handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() +before any floating point instructions are executed. */ +void vPortTaskUsesFPU( void ); +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +#define portNOP() __nop() + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CA9/portmacro.inc b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CA9/portmacro.inc new file mode 100644 index 0000000..2e6a910 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CA9/portmacro.inc @@ -0,0 +1,121 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +SYS_MODE EQU 0x1f +SVC_MODE EQU 0x13 +IRQ_MODE EQU 0x12 + + IMPORT ulCriticalNesting + IMPORT pxCurrentTCB + IMPORT ulPortTaskHasFPUContext + IMPORT ulAsmAPIPriorityMask + IMPORT ulICCPMR + + + MACRO + portSAVE_CONTEXT + + ; Save the LR and SPSR onto the system mode stack before switching to + ; system mode to save the remaining system mode registers + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + ; Push the critical nesting count + LDR R2, =ulCriticalNesting + LDR R1, [R2] + PUSH {R1} + + ; Does the task have a floating point context that needs saving? If + ; ulPortTaskHasFPUContext is 0 then no. + LDR R2, =ulPortTaskHasFPUContext + LDR R3, [R2] + CMP R3, #0 + + ; Save the floating point context, if any + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} + VPUSHNE {D16-D31} + PUSHNE {R1} + + ; Save ulPortTaskHasFPUContext itself + PUSH {R3} + + ; Save the stack pointer in the TCB + LDR R0, =pxCurrentTCB + LDR R1, [R0] + STR SP, [R1] + + MEND + +; /**********************************************************************/ + + MACRO + portRESTORE_CONTEXT + + ; Set the SP to point to the stack of the task being restored. + LDR R0, =pxCurrentTCB + LDR R1, [R0] + LDR SP, [R1] + + ; Is there a floating point context to restore? If the restored + ; ulPortTaskHasFPUContext is zero then no. + LDR R0, =ulPortTaskHasFPUContext + POP {R1} + STR R1, [R0] + CMP R1, #0 + + ; Restore the floating point context, if any + POPNE {R0} + VPOPNE {D16-D31} + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + ; Restore the critical section nesting depth + LDR R0, =ulCriticalNesting + POP {R1} + STR R1, [R0] + + ; Ensure the priority mask is correct for the critical nesting depth + LDR R2, =ulICCPMR + CMP R1, #0 + MOVEQ R4, #255 + LDRNE R4, =ulAsmAPIPriorityMask + STR R4, [r2] + + ; Restore all system mode registers other than the SP (which is already + ; being used) + POP {R0-R12, R14} + + ; Return to the task code, loading CPSR on the way. + RFEIA sp! + + MEND + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM0/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM0/port.c new file mode 100644 index 0000000..481e7da --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM0/port.c @@ -0,0 +1,549 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM0 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#ifndef portMISSED_COUNTS_FACTOR + #define portMISSED_COUNTS_FACTOR ( 45UL ) +#endif + +/* Constants used with memory barrier intrinsics. */ +#define portSY_FULL_READ_WRITE ( 15 ) + +/* Legacy macro for backward compatibility only. This macro used to be used to + * replace the function that configures the clock used to generate the tick + * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so + * the application writer can override it by simply defining a function of the + * same name (vApplicationSetupTickInterrupt()). */ +#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION + #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0 +#endif + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* The number of SysTick increments that make up one tick period. */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11..R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + /* This function is no longer used, but retained for backward + * compatibility. */ +} +/*-----------------------------------------------------------*/ + +__asm void prvPortStartFirstTask( void ) +{ + extern pxCurrentTCB; + + PRESERVE8 + + /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector + * table offset register that can be used to locate the initial stack value. + * Not all M0 parts have the application vector table at address 0. */ +/* *INDENT-OFF* */ + + ldr r3, = pxCurrentTCB /* Obtain location of pxCurrentTCB. */ + ldr r1, [ r3 ] + ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ + adds r0, # 32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + movs r0, # 2 /* Switch to the psp stack. */ + msr CONTROL, r0 + isb + pop { r0 - r5 } /* Pop the registers that are saved automatically. */ + mov lr, r5 /* lr is now in r5. */ + pop { r3 } /* The return address is now in r3. */ + pop { r2 } /* Pop and discard the XPSR. */ + cpsie i /* The first task has its context and interrupts can be enabled. */ + bx r3 /* Finally, jump to the user defined task code. */ + + ALIGN +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is completely + * within the specified behaviour for the architecture. */ + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +__asm uint32_t ulSetInterruptMaskFromISR( void ) +{ +/* *INDENT-OFF* */ + mrs r0, PRIMASK + cpsid i + bx lr +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void vClearInterruptMaskFromISR( uint32_t ulMask ) +{ +/* *INDENT-OFF* */ + msr PRIMASK, r0 + bx lr +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void xPortPendSVHandler( void ) +{ + extern vTaskSwitchContext + extern pxCurrentTCB + +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, psp + + ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [ r3 ] + + subs r0, # 32 /* Make space for the remaining low registers. */ + str r0, [ r2 ] /* Save the new top of stack. */ + stmia r0 !, { r4 - r7 } /* Store the low registers that are not saved automatically. */ + mov r4, r8 /* Store the high registers. */ + mov r5, r9 + mov r6, r10 + mov r7, r11 + stmia r0 !, { r4 - r7 } + + push { r3, r14 } + cpsid i + bl vTaskSwitchContext + cpsie i + pop { r2, r3 } /* lr goes in r3. r2 now holds tcb pointer. */ + + ldr r1, [ r2 ] + ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ + adds r0, # 16 /* Move to the high registers. */ + ldmia r0 !, { r4 - r7 } /* Pop the high registers. */ + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + + msr psp, r0 /* Remember the new top of stack for the task. */ + + subs r0, # 32 /* Go back for the low registers that are not automatically restored. */ + ldmia r0 !, { r4 - r7 } /* Pop low registers. */ + + bx r3 + ALIGN +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) + + __weak void vPortSetupTimerInterrupt( void ) + { + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR; + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + +#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_irq() call + * above. */ + __enable_irq(); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __dsb( portSY_FULL_READ_WRITE ); + __wfi(); + __isb( portSY_FULL_READ_WRITE ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __enable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD + * again, then set portNVIC_SYSTICK_LOAD back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrpts enabled. */ + __enable_irq(); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM0/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM0/portmacro.h new file mode 100644 index 0000000..a16a399 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM0/portmacro.h @@ -0,0 +1,125 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + extern void vPortYield( void ); + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portYIELD() vPortYield() + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + extern uint32_t ulSetInterruptMaskFromISR( void ); + extern void vClearInterruptMaskFromISR( uint32_t ulMask ); + + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x ) + #define portDISABLE_INTERRUPTS() __disable_irq() + #define portENABLE_INTERRUPTS() __enable_irq() + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + + #define portNOP() + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM3/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM3/port.c new file mode 100644 index 0000000..9bfd112 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM3/port.c @@ -0,0 +1,718 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM3 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configKERNEL_INTERRUPT_PRIORITY + #define configKERNEL_INTERRUPT_PRIORITY 255 +#endif + +#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Legacy macro for backward compatibility only. This macro used to be used to + * replace the function that configures the clock used to generate the tick + * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so + * the application writer can override it by simply defining a function of the + * same name (vApplicationSetupTickInterrupt()). */ +#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION + #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0 +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +__asm void vPortSVCHandler( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + ldr r3, = pxCurrentTCB /* Restore the context. */ + ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ + ldmia r0 !, { r4 - r11 } /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + msr psp, r0 /* Restore the task stack pointer. */ + isb + mov r0, # 0 + msr basepri, r0 + orr r14, # 0xd + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void prvStartFirstTask( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [ r0 ] + ldr r0, [ r0 ] + + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Globally enable interrupts. */ + cpsie i + cpsie f + dsb + isb + /* Call SVC to start the first task. */ + svc 0 + nop + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* The kernel interrupt priority should be set to the lowest + * priority. */ + configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + prvStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +__asm void xPortPendSVHandler( void ) +{ + extern uxCriticalNesting; + extern pxCurrentTCB; + extern vTaskSwitchContext; + +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, psp + isb + + ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [ r3 ] + + stmdb r0 !, { r4 - r11 } /* Save the remaining registers. */ + str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */ + + stmdb sp !, { r3, r14 } + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp !, { r3, r14 } + + ldr r1, [ r3 ] + ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ + ldmia r0 !, { r4 - r11 } /* Pop the registers and the critical nesting count. */ + msr psp, r0 + isb + bx r14 + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known - therefore the slightly faster vPortRaiseBASEPRI() function is used + * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */ + vPortRaiseBASEPRI(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + + vPortClearBASEPRIFromISR(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_irq() call + * above. */ + __enable_irq(); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __dsb( portSY_FULL_READ_WRITE ); + __wfi(); + __isb( portSY_FULL_READ_WRITE ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __enable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __enable_irq(); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +/* + * Setup the SysTick timer to generate the tick interrupts at the required + * frequency. + */ +#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) + + __weak void vPortSetupTimerInterrupt( void ) + { + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); + } + +#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */ +/*-----------------------------------------------------------*/ + +__asm uint32_t vPortGetIPSR( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, ipsr + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + ulCurrentInterrupt = vPortGetIPSR(); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM3/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM3/portmacro.h new file mode 100644 index 0000000..88a6d2e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM3/portmacro.h @@ -0,0 +1,266 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + +/* Constants used with memory barrier intrinsics. */ + #define portSY_FULL_READ_WRITE ( 15 ) + +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __dsb( portSY_FULL_READ_WRITE ); \ + __isb( portSY_FULL_READ_WRITE ); \ + } +/*-----------------------------------------------------------*/ + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + + #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() + #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Port specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) + + #endif /* taskRECORD_READY_PRIORITY */ +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + #define portINLINE __inline + + #ifndef portFORCE_INLINE + #define portFORCE_INLINE __forceinline + #endif + +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) + { + __asm + { + /* Barrier instructions are not used as this function is only used to + * lower the BASEPRI value. */ +/* *INDENT-OFF* */ + msr basepri, ulBASEPRI +/* *INDENT-ON* */ + } + } +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE void vPortRaiseBASEPRI( void ) + { + uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + msr basepri, ulNewBASEPRI + dsb + isb +/* *INDENT-ON* */ + } + } +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) + { + __asm + { + /* Set BASEPRI to 0 so no interrupts are masked. This function is only + * used to lower the mask in an interrupt, so memory barriers are not + * used. */ +/* *INDENT-OFF* */ + msr basepri, # 0 +/* *INDENT-ON* */ + } + } +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) + { + uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + mrs ulReturn, basepri + msr basepri, ulNewBASEPRI + dsb + isb +/* *INDENT-ON* */ + } + + return ulReturn; + } +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) + { + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm + { +/* *INDENT-OFF* */ + mrs ulCurrentInterrupt, ipsr +/* *INDENT-ON* */ + } + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; + } + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM4F/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM4F/port.c new file mode 100644 index 0000000..4faedca --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM4F/port.c @@ -0,0 +1,810 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __TARGET_FPU_VFP + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Legacy macro for backward compatibility only. This macro used to be used to + * replace the function that configures the clock used to generate the tick + * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so + * the application writer can override it by simply defining a function of the + * same name (vApplicationSetupTickInterrupt()). */ +#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION + #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0 +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 + * r0p1 port. */ +#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvStartFirstTask( void ); + +/* + * Functions defined in portasm.s to enable the VFP. + */ +static void prvEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +__asm void vPortSVCHandler( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r1, [ r3 ] + ldr r0, [ r1 ] + /* Pop the core registers. */ + ldmia r0!, {r4-r11,r14} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void prvStartFirstTask( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [ r0 ] + ldr r0, [ r0 ] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + + /* Clear the bit that indicates the FPU is in use in case the FPU was used + * before the scheduler was started - which would otherwise result in the + * unnecessary leaving of space in the SVC stack for lazy saving of FPU + * registers. */ + mov r0, #0 + msr control, r0 + /* Globally enable interrupts. */ + cpsie i + cpsie f + dsb + isb + /* Call SVC to start the first task. */ + svc 0 + nop + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void prvEnableVFP( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 + ldr r1, [ r0 ] + + /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [ r0 ] + bx r14 + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* This port can be used on all revisions of the Cortex-M7 core other than + * the r0p1 parts. r0p1 parts should use the port from the + * /source/portable/GCC/ARM_CM7/r0p1 directory. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* The kernel interrupt priority should be set to the lowest + * priority. */ + configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + prvEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +__asm void xPortPendSVHandler( void ) +{ + extern uxCriticalNesting; + extern pxCurrentTCB; + extern vTaskSwitchContext; + +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, psp + isb + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r2, [ r3 ] + + /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + /* Save the core registers. */ + stmdb r0!, {r4-r11, r14} + + /* Save the new top of stack into the first member of the TCB. */ + str r0, [ r2 ] + + stmdb sp!, {r0, r3} + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [ r3 ] + ldr r0, [ r1 ] + + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + + /* Is the task using the FPU context? If so, pop the high vfp registers + * too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */ + #if WORKAROUND_PMU_CM001 == 1 + push { r14 } + pop { pc } + nop + #endif + #endif + + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known - therefore the slightly faster vPortRaiseBASEPRI() function is used + * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */ + vPortRaiseBASEPRI(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + + vPortClearBASEPRIFromISR(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_irq() call + * above. */ + __enable_irq(); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __dsb( portSY_FULL_READ_WRITE ); + __wfi(); + __isb( portSY_FULL_READ_WRITE ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __enable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __enable_irq(); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +/* + * Setup the SysTick timer to generate the tick interrupts at the required + * frequency. + */ +#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) + + __weak void vPortSetupTimerInterrupt( void ) + { + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); + } + +#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */ +/*-----------------------------------------------------------*/ + +__asm uint32_t vPortGetIPSR( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, ipsr + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + ulCurrentInterrupt = vPortGetIPSR(); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM4F/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM4F/portmacro.h new file mode 100644 index 0000000..4edfade --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM4F/portmacro.h @@ -0,0 +1,265 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + +/* Constants used with memory barrier intrinsics. */ + #define portSY_FULL_READ_WRITE ( 15 ) + +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __dsb( portSY_FULL_READ_WRITE ); \ + __isb( portSY_FULL_READ_WRITE ); \ + } +/*-----------------------------------------------------------*/ + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + + #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() + #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Port specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) + + #endif /* taskRECORD_READY_PRIORITY */ +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + #define portINLINE __inline + + #ifndef portFORCE_INLINE + #define portFORCE_INLINE __forceinline + #endif + +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) + { + __asm + { + /* Barrier instructions are not used as this function is only used to + * lower the BASEPRI value. */ +/* *INDENT-OFF* */ + msr basepri, ulBASEPRI +/* *INDENT-ON* */ + } + } +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE void vPortRaiseBASEPRI( void ) + { + uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + msr basepri, ulNewBASEPRI + dsb + isb +/* *INDENT-ON* */ + } + } +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) + { + __asm + { + /* Set BASEPRI to 0 so no interrupts are masked. This function is only + * used to lower the mask in an interrupt, so memory barriers are not + * used. */ +/* *INDENT-OFF* */ + msr basepri, # 0 +/* *INDENT-ON* */ + } + } +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) + { + uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + mrs ulReturn, basepri + msr basepri, ulNewBASEPRI + dsb + isb +/* *INDENT-ON* */ + } + + return ulReturn; + } +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) + { + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm + { +/* *INDENT-OFF* */ + mrs ulCurrentInterrupt, ipsr +/* *INDENT-ON* */ + } + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; + } + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM4_MPU/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM4_MPU/port.c new file mode 100644 index 0000000..ea57753 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM4_MPU/port.c @@ -0,0 +1,1043 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4 MPU port. +*----------------------------------------------------------*/ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __TARGET_FPU_VFP + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS + #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security." + #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1 +#endif + +/* Constants required to access and manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL ) + +/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure + * that a work around is active for errata 837070. */ +#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +/* Constants required to access and manipulate the MPU. */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) ) +#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portMPU_ENABLE ( 0x01UL ) +#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) +#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) +#define portMPU_REGION_VALID ( 0x10UL ) +#define portMPU_REGION_ENABLE ( 0x01UL ) +#define portPERIPHERALS_START_ADDRESS 0x40000000UL +#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL + +/* Constants required to access and manipulate the SysTick. */ +#define portNVIC_SYSTICK_CLK ( 0x00000004UL ) +#define portNVIC_SYSTICK_INT ( 0x00000002UL ) +#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) +#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000UL ) +#define portINITIAL_EXC_RETURN ( 0xfffffffdUL ) +#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) +#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Offsets in the stack to the parameters when inside the SVC handler. */ +#define portOFFSET_TO_PC ( 6 ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Each task maintains its own interrupt status in the critical nesting + * variable. Note this is not saved as part of the task context as context + * switches can only occur when uxCriticalNesting is zero. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * Setup the timer to generate the tick interrupts. + */ +void vSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/* + * Configure a number of standard MPU regions that are used by all tasks. + */ +static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION; + +/* + * Return the smallest MPU region size that a given number of bytes will fit + * into. The region size is returned as the value that should be programmed + * into the region attribute register for that region. + */ +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION; + +/* + * Standard FreeRTOS exception handlers. + */ +void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION; +void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION; +void vPortSVCHandler( void ) PRIVILEGED_FUNCTION; + +/* + * Starts the scheduler by restoring the context of the first task to run. + */ +static void prvRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION; + +/* + * C portion of the SVC handler. The SVC handler is split between an asm entry + * and a C wrapper for simplicity of coding and maintenance. + */ +void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( used ) ) PRIVILEGED_FUNCTION; + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP( void ); + +/* + * Utility function. + */ +static uint32_t prvPortGetIPSR( void ); + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ); + +/** + * @brief Enter critical section. + */ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * @brief Exit from critical section. + */ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortExitCritical( void ) PRIVILEGED_FUNCTION; +#endif +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = 0; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED; + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED; + } + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void prvSVCHandler( uint32_t * pulParam ) +{ + uint8_t ucSVCNumber; + uint32_t ulReg, ulPC; + + #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) + extern uint32_t __syscalls_flash_start__; + extern uint32_t __syscalls_flash_end__; + #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + + /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first + * argument (r0) is pulParam[ 0 ]. */ + ulPC = pulParam[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + case portSVC_START_SCHEDULER: + portNVIC_SHPR2_REG |= portNVIC_SVC_PRI; + prvRestoreContextOfFirstTask(); + break; + + case portSVC_YIELD: + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required + * but do ensure the code is completely + * within the specified behaviour for the + * architecture. */ + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + break; + + #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) + case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the + * svc was raised from any of the + * system calls. */ + + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + __asm + { +/* *INDENT-OFF* */ + mrs ulReg, control /* Obtain current control value. */ + bic ulReg, # 1 /* Set privilege bit. */ + msr control, ulReg /* Write back new control value. */ +/* *INDENT-ON* */ + } + } + + break; + #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + case portSVC_RAISE_PRIVILEGE: + __asm + { +/* *INDENT-OFF* */ + mrs ulReg, control /* Obtain current control value. */ + bic ulReg, # 1 /* Set privilege bit. */ + msr control, ulReg /* Write back new control value. */ +/* *INDENT-ON* */ + } + break; + #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + + default: /* Unknown SVC call. */ + break; + } +} +/*-----------------------------------------------------------*/ + +__asm void vPortSVCHandler( void ) +{ + extern prvSVCHandler + +/* *INDENT-OFF* */ + PRESERVE8 + + /* Assumes psp was in use. */ + #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ + tst lr, # 4 + ite eq + mrseq r0, msp + mrsne r0, psp + #else + mrs r0, psp + #endif + + b prvSVCHandler +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void prvRestoreContextOfFirstTask( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [ r0 ] + ldr r0, [ r0 ] + msr msp, r0 /* Set the msp back to the start of the stack. */ + ldr r3, =pxCurrentTCB /* Restore the context. */ + ldr r1, [ r3 ] + ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */ + add r1, r1, #4 /* Move onto the second item in the TCB... */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ + bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + str r3, [ r2 ] /* Disable MPU. */ + + ldr r2, =0xe000ed9c /* Region Base Address register. */ + ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ + stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ + #endif /* configTOTAL_MPU_REGIONS == 16. */ + + ldr r2, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ + orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + str r3, [ r2 ] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + ldmia r0 !, { r3 - r11, r14 } /* Pop the registers that are not automatically saved on exception entry. */ + msr control, r3 + msr psp, r0 /* Restore the task stack pointer. */ + mov r0, #0 + msr basepri, r0 + bx r14 + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) ); + #else + /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define + * configENABLE_ERRATA_837070_WORKAROUND to 1 in your + * FreeRTOSConfig.h. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + #endif + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the same priority as the kernel, and the SVC + * handler higher priority so it can be used to exit a critical section (where + * lower priorities are masked). */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Configure the regions in the MPU that are common to all tasks. */ + prvSetupMPU(); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +__asm void prvStartFirstTask( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [ r0 ] + ldr r0, [ r0 ] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + + /* Clear the bit that indicates the FPU is in use in case the FPU was used + * before the scheduler was started - which would otherwise result in the + * unnecessary leaving of space in the SVC stack for lazy saving of FPU + * registers. */ + mov r0, #0 + msr control, r0 + /* Globally enable interrupts. */ + cpsie i + cpsie f + dsb + isb + svc portSVC_START_SCHEDULER /* System call to start first task. */ + nop + nop +/* *INDENT-ON* */ +} + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + } +#else + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +#endif +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ +#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#else + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +#endif +} +/*-----------------------------------------------------------*/ + +__asm void xPortPendSVHandler( void ) +{ + extern uxCriticalNesting; + extern pxCurrentTCB; + extern vTaskSwitchContext; + +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, psp + + ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [ r3 ] + + tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */ + it eq + vstmdbeq r0 !, { s16 - s31 } + + mrs r1, control + stmdb r0 !, { r1, r4 - r11, r14 } /* Save the remaining registers. */ + str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */ + + stmdb sp !, { r0, r3 } + mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsid i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + msr basepri, r0 + dsb + isb + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsie i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp !, { r0, r3 } + /* Restore the context. */ + ldr r1, [ r3 ] + ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */ + add r1, r1, #4 /* Move onto the second item in the TCB... */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ + bic r3, r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + str r3, [ r2 ] /* Disable MPU. */ + + ldr r2, =0xe000ed9c /* Region Base Address register. */ + ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ + stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ + #endif /* configTOTAL_MPU_REGIONS == 16. */ + + ldr r2, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ + orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + str r3, [ r2 ] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + ldmia r0 !, { r3 - r11, r14 } /* Pop the registers that are not automatically saved on exception entry. */ + msr control, r3 + + tst r14, #0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */ + it eq + vldmiaeq r0 !, { s16 - s31 } + + msr psp, r0 + bx r14 + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + uint32_t ulDummy; + + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vSetupTimerInterrupt( void ) +{ + /* Reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} +/*-----------------------------------------------------------*/ + +__asm void vPortSwitchToUserMode( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, control + orr r0, #1 + msr control, r0 + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void vPortEnableVFP( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */ + ldr r1, [ r0 ] + + orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */ + str r1, [ r0 ] + bx r14 + nop + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupMPU( void ) +{ + extern uint32_t __privileged_functions_start__; + extern uint32_t __privileged_functions_end__; + extern uint32_t __FLASH_segment_start__; + extern uint32_t __FLASH_segment_end__; + extern uint32_t __privileged_data_start__; + extern uint32_t __privileged_data_end__; + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check the expected MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* First setup the unprivileged flash for unprivileged read only access. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portUNPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) | + ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged flash for privileged only access. This is where + * the kernel code is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) | + ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged data RAM region. This is where the kernel data + * is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_RAM_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) | + ( portMPU_REGION_ENABLE ); + + /* By default allow everything to access the general peripherals. The + * system peripherals and registers are protected. */ + portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) | + ( portMPU_REGION_VALID ) | + ( portGENERAL_PERIPHERALS_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) | + ( portMPU_REGION_ENABLE ); + + /* Enable the memory fault exception. */ + portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE; + + /* Enable the MPU with the background region configured. */ + portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE ); + } +} +/*-----------------------------------------------------------*/ + +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) +{ + uint32_t ulRegionSize, ulReturnValue = 4; + + /* 32 is the smallest region size, 31 is the largest valid value for + * ulReturnValue. */ + for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) ) + { + if( ulActualSizeInBytes <= ulRegionSize ) + { + break; + } + else + { + ulReturnValue++; + } + } + + /* Shift the code by one before returning so it can be written directly + * into the the correct bit position of the attribute register. */ + return( ulReturnValue << 1UL ); +} +/*-----------------------------------------------------------*/ + +__asm BaseType_t xIsPrivileged( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void vResetPrivilege( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, control /* r0 = CONTROL. */ + orrs r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return. */ +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) +{ + extern uint32_t __SRAM_segment_start__; + extern uint32_t __SRAM_segment_end__; + extern uint32_t __privileged_data_start__; + extern uint32_t __privileged_data_end__; + + + int32_t lIndex; + uint32_t ul; + + if( xRegions == NULL ) + { + /* No MPU regions are specified so allow access to all RAM. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Invalidate user configurable regions. */ + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + } + } + else + { + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that the + * stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) pxBottomOfStack ) | + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( portMPU_REGION_ENABLE ); + } + + lIndex = 0; + + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) + { + /* Translate the generic region definition contained in + * xRegions into the CM4 specific MPU settings that are then + * stored in xMPUSettings. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = + ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | + ( portMPU_REGION_VALID ) | + ( ul - 1UL ); /* Region number. */ + + xMPUSettings->xRegion[ ul ].ulRegionAttribute = + ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | + ( xRegions[ lIndex ].ulParameters ) | + ( portMPU_REGION_ENABLE ); + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + } + + lIndex++; + } + } +} +/*-----------------------------------------------------------*/ + +__asm uint32_t prvPortGetIPSR( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, ipsr + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + ulCurrentInterrupt = prvPortGetIPSR(); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM4_MPU/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM4_MPU/portmacro.h new file mode 100644 index 0000000..066a1a2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM4_MPU/portmacro.h @@ -0,0 +1,427 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif + +/*-----------------------------------------------------------*/ + +/* MPU specific constants. */ +#define portUSING_MPU_WRAPPERS 1 +#define portPRIVILEGE_BIT ( 0x80000000UL ) + +#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) +#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) +#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) +#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) + +/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size + * Register (RASR). */ +#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) +#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) + +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* + * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the + * memory type, and where necessary the cacheable and shareable properties + * of the memory region. + * + * The TEX, C, and B bits together indicate the memory type of the region, + * and: + * - For Normal memory, the cacheable properties of the region. + * - For Device memory, whether the region is shareable. + * + * For Normal memory regions, the S bit indicates whether the region is + * shareable. For Strongly-ordered and Device memory, the S bit is ignored. + * + * See the following two tables for setting TEX, S, C and B bits for + * unprivileged flash, privileged flash and privileged RAM regions. + * + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 1 | Device | Shared device | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 0 | Device | Non-shared device | Not shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 1 | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 011 | X | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved | + | | | | | outer cacheability rules that must be exported on the | | + | | | | | bus. See the table below for the cacheability policy | | + | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | + +-----------------------------------------+----------------------------------------+ + | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy | + +-----------------------------------------+----------------------------------------+ + | 00 | Non-cacheable | + +-----------------------------------------+----------------------------------------+ + | 01 | Write-back, write and read allocate | + +-----------------------------------------+----------------------------------------+ + | 10 | Write-through, no write allocate | + +-----------------------------------------+----------------------------------------+ + | 11 | Write-back, no write allocate | + +-----------------------------------------+----------------------------------------+ + */ + +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for Flash + * region. */ +#ifndef configTEX_S_C_B_FLASH + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_FLASH ( 0x07UL ) +#endif + +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for SRAM + * region. */ +#ifndef configTEX_S_C_B_SRAM + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_SRAM ( 0x07UL ) +#endif + +#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL ) +#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL ) +#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL ) +#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL ) +#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portFIRST_CONFIGURABLE_REGION ( 0UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL ) +#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL ) +#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */ + +void vPortSwitchToUserMode( void ); +#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() + +typedef struct MPU_REGION_REGISTERS +{ + uint32_t ulRegionBaseAddress; + uint32_t ulRegionAttribute; +} xMPU_REGION_REGISTERS; + +typedef struct MPU_SETTINGS +{ + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ]; +} xMPU_SETTINGS; + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/* Constants used with memory barrier intrinsics. */ +#define portSY_FULL_READ_WRITE ( 15 ) + +/*-----------------------------------------------------------*/ + +/* SVC numbers for various services. */ +#define portSVC_START_SCHEDULER 0 +#define portSVC_YIELD 1 +#define portSVC_RAISE_PRIVILEGE 2 + +/* Scheduler utilities. */ + +#define portYIELD() __asm{ SVC portSVC_YIELD } +#define portYIELD_WITHIN_API() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __dsb( portSY_FULL_READ_WRITE ); \ + __isb( portSY_FULL_READ_WRITE ); \ + } +/*-----------------------------------------------------------*/ + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE __forceinline +#endif +/*-----------------------------------------------------------*/ + +extern BaseType_t xIsPrivileged( void ); +extern void vResetPrivilege( void ); + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +#define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + */ +#define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE } + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ +#define portRESET_PRIVILEGE() vResetPrivilege() +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) +{ + __asm + { + /* Barrier instructions are not used as this function is only used to + * lower the BASEPRI value. */ +/* *INDENT-OFF* */ + msr basepri, ulBASEPRI +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsid i + #endif + msr basepri, ulNewBASEPRI + dsb + isb + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsie i + #endif +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) +{ + __asm + { + /* Set BASEPRI to 0 so no interrupts are masked. This function is only + * used to lower the mask in an interrupt, so memory barriers are not + * used. */ +/* *INDENT-OFF* */ + msr basepri, # 0 +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + mrs ulReturn, basepri + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsid i + #endif + msr basepri, ulNewBASEPRI + dsb + isb + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsie i + #endif +/* *INDENT-ON* */ + } + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm + { + mrs ulCurrentInterrupt, ipsr + } + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html" + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 +#endif +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM7/ReadMe.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM7/ReadMe.txt new file mode 100644 index 0000000..b3950da --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM7/ReadMe.txt @@ -0,0 +1,18 @@ +There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers. +The best option depends on the revision of the ARM Cortex-M7 core in use. The +revision is specified by an 'r' number, and a 'p' number, so will look something +like 'r0p1'. Check the documentation for the microcontroller in use to find the +revision of the Cortex-M7 core used in that microcontroller. If in doubt, use +the FreeRTOS port provided specifically for r0p1 revisions, as that can be used +with all core revisions. + +The first option is to use the ARM Cortex-M4F port, and the second option is to +use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround. + +If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be +used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in +the /FreeRTOS/Source/portable/RVDS/ARM_CM4F directory. + +If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM +Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1 +directory. \ No newline at end of file diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM7/r0p1/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM7/r0p1/port.c new file mode 100644 index 0000000..da26a33 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM7/r0p1/port.c @@ -0,0 +1,796 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM7 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __TARGET_FPU_VFP + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* The __weak attribute does not work as you might expect with the Keil tools + * so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if + * the application writer wants to provide their own implementation of + * vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION + * is defined. */ +#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION + #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0 +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvStartFirstTask( void ); + +/* + * Functions defined in portasm.s to enable the VFP. + */ +static void prvEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +__asm void vPortSVCHandler( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r1, [ r3 ] + ldr r0, [ r1 ] + /* Pop the core registers. */ + ldmia r0!, { r4-r11, r14 } + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void prvStartFirstTask( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [ r0 ] + ldr r0, [ r0 ] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + + /* Clear the bit that indicates the FPU is in use in case the FPU was used + * before the scheduler was started - which would otherwise result in the + * unnecessary leaving of space in the SVC stack for lazy saving of FPU + * registers. */ + mov r0, #0 + msr control, r0 + /* Globally enable interrupts. */ + cpsie i + cpsie f + dsb + isb + /* Call SVC to start the first task. */ + svc 0 + nop + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void prvEnableVFP( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 + ldr r1, [ r0 ] + + /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [ r0 ] + bx r14 + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* The kernel interrupt priority should be set to the lowest + * priority. */ + configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + prvEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +__asm void xPortPendSVHandler( void ) +{ + extern uxCriticalNesting; + extern pxCurrentTCB; + extern vTaskSwitchContext; + +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, psp + isb + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r2, [ r3 ] + + /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + /* Save the core registers. */ + stmdb r0!, {r4-r11, r14 } + + /* Save the new top of stack into the first member of the TCB. */ + str r0, [ r2 ] + + stmdb sp!, { r0, r3 } + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + cpsid i + msr basepri, r0 + dsb + isb + cpsie i + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, { r0, r3 } + + /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [ r3 ] + ldr r0, [ r1 ] + + /* Pop the core registers. */ + ldmia r0!, { r4-r11, r14 } + + /* Is the task using the FPU context? If so, pop the high vfp registers + * too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, { s16-s31 } + + msr psp, r0 + isb + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */ + #if WORKAROUND_PMU_CM001 == 1 + push { r14 } + pop { pc } + nop + #endif + #endif + + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known - therefore the slightly faster vPortRaiseBASEPRI() function is used + * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */ + vPortRaiseBASEPRI(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + + vPortClearBASEPRIFromISR(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_irq() call + * above. */ + __enable_irq(); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __dsb( portSY_FULL_READ_WRITE ); + __wfi(); + __isb( portSY_FULL_READ_WRITE ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __enable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __enable_irq(); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +/* + * Setup the SysTick timer to generate the tick interrupts at the required + * frequency. + */ +#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) + + __weak void vPortSetupTimerInterrupt( void ) + { + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); + } + +#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */ +/*-----------------------------------------------------------*/ + +__asm uint32_t vPortGetIPSR( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, ipsr + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + ulCurrentInterrupt = vPortGetIPSR(); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM7/r0p1/portmacro.h new file mode 100644 index 0000000..abe79a9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/RVDS/ARM_CM7/r0p1/portmacro.h @@ -0,0 +1,269 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + +/* Constants used with memory barrier intrinsics. */ + #define portSY_FULL_READ_WRITE ( 15 ) + +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __dsb( portSY_FULL_READ_WRITE ); \ + __isb( portSY_FULL_READ_WRITE ); \ + } +/*-----------------------------------------------------------*/ + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + + #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() + #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Port specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) + + #endif /* taskRECORD_READY_PRIORITY */ +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + #define portINLINE __inline + + #ifndef portFORCE_INLINE + #define portFORCE_INLINE __forceinline + #endif + +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) + { + __asm + { + /* Barrier instructions are not used as this function is only used to + * lower the BASEPRI value. */ +/* *INDENT-OFF* */ + msr basepri, ulBASEPRI +/* *INDENT-ON* */ + } + } +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE void vPortRaiseBASEPRI( void ) + { + uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + cpsid i + msr basepri, ulNewBASEPRI + dsb + isb + cpsie i +/* *INDENT-ON* */ + } + } +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) + { + __asm + { + /* Set BASEPRI to 0 so no interrupts are masked. This function is only + * used to lower the mask in an interrupt, so memory barriers are not + * used. */ +/* *INDENT-OFF* */ + msr basepri, # 0 +/* *INDENT-ON* */ + } + } +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) + { + uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + mrs ulReturn, basepri + cpsid i + msr basepri, ulNewBASEPRI + dsb + isb + cpsie i +/* *INDENT-ON* */ + } + + return ulReturn; + } +/*-----------------------------------------------------------*/ + + static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) + { + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm + { +/* *INDENT-OFF* */ + mrs ulCurrentInterrupt, ipsr +/* *INDENT-ON* */ + } + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; + } + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX100/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX100/port.c new file mode 100644 index 0000000..7eaa9b1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX100/port.c @@ -0,0 +1,647 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the RX100 port. + *----------------------------------------------------------*/ + +/* Standard C includes. */ +#include "limits.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) + +/* The peripheral clock is divided by this value before being supplying the +CMT. */ +#if ( configUSE_TICKLESS_IDLE == 0 ) + /* If tickless idle is not used then the divisor can be fixed. */ + #define portCLOCK_DIVISOR 8UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 ) + #define portCLOCK_DIVISOR 512UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 ) + #define portCLOCK_DIVISOR 128UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 ) + #define portCLOCK_DIVISOR 32UL +#else + #define portCLOCK_DIVISOR 8UL +#endif + + +/* Keys required to lock and unlock access to certain system registers +respectively. */ +#define portUNLOCK_KEY 0xA50B +#define portLOCK_KEY 0xA500 + +/*-----------------------------------------------------------*/ + +/* The following lines are to ensure vSoftwareInterruptEntry can be referenced, + and therefore installed in the vector table, when the FreeRTOS code is built +as a library. */ +extern BaseType_t vSoftwareInterruptEntry; +const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry; + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +static void prvYieldHandler( void ); + +/* + * The entry point for the software interrupt handler. This is the function + * that calls the inline asm function prvYieldHandler(). It is installed in + * the vector table, but the code that installs it is in prvYieldHandler rather + * than using a #pragma. + */ +void vSoftwareInterruptISR( void ); + +/* + * Sets up the periodic ISR used for the RTOS tick using the CMT. + * The application writer can define configSETUP_TICK_INTERRUPT() (in + * FreeRTOSConfig.h) such that their own tick interrupt configuration is used + * in place of prvSetupTimerInterrupt(). + */ +static void prvSetupTimerInterrupt( void ); +#ifndef configSETUP_TICK_INTERRUPT + /* The user has not provided their own tick interrupt configuration so use + the definition in this file (which uses the interval timer). */ + #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt() +#endif /* configSETUP_TICK_INTERRUPT */ + +/* + * Called after the sleep mode registers have been configured, prvSleep() + * executes the pre and post sleep macros, and actually calls the wait + * instruction. + */ +#if configUSE_TICKLESS_IDLE == 1 + static void prvSleep( TickType_t xExpectedIdleTime ); +#endif /* configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +/* These is accessed by the inline assembler functions. */ +extern void *pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* Calculate how many clock increments make up a single tick period. */ +static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + +#if configUSE_TICKLESS_IDLE == 1 + + /* Holds the maximum number of ticks that can be suppressed - which is + basically how far into the future an interrupt can be generated. Set + during initialisation. This is the maximum possible value that the + compare match register can hold divided by ulMatchValueForOneTick. */ + static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + + /* Flag set from the tick interrupt to allow the sleep processing to know if + sleep mode was exited because of a tick interrupt, or an interrupt + generated by something else. */ + static volatile uint32_t ulTickFlag = pdFALSE; + + /* The CMT counter is stopped temporarily each time it is re-programmed. + The following constant offsets the CMT counter match value by the number of + CMT counts that would typically be missed while the counter was stopped to + compensate for the lost time. The large difference between the divided CMT + clock and the CPU clock means it is likely ulStoppedTimerCompensation will + equal zero - and be optimised away. */ + static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) ); + +#endif + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Offset to end up on 8 byte boundary. */ + pxTopOfStack--; + + /* R0 is not included as it is the stack pointer. */ + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xaaaabbbb; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + /* Leave space for the registers that will get popped from the stack + when the task first starts executing. */ + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate + the tick interrupt. This way the application can decide which + peripheral to use. If tickless mode is used then the default + implementation defined in this file (which uses CMT0) should not be + overridden. */ + configSETUP_TICK_INTERRUPT(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Execution should not reach here as the tasks are now running! + prvSetupTimerInterrupt() is called here to prevent the compiler outputting + a warning about a statically declared function not being referenced in the + case that the application writer has provided their own tick interrupt + configuration routine (and defined configSETUP_TICK_INTERRUPT() such that + their own routine will be called in place of prvSetupTimerInterrupt()). */ + prvSetupTimerInterrupt(); + + /* Just to make sure the function is not optimised away. */ + ( void ) vSoftwareInterruptISR(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvStartFirstTask +static void prvStartFirstTask( void ) +{ + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + MVTACLO R15 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15 /* Accumulator high 32 bits. */ + POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */ + RTE /* This pops the remaining registers. */ + NOP + NOP +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( prvTickISR( vect = _VECT( configTICK_VECTOR ), enable ) ) +void prvTickISR( void ) +{ + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + set_ipl( configKERNEL_INTERRUPT_PRIORITY ); + + #if configUSE_TICKLESS_IDLE == 1 + { + /* The CPU woke because of a tick. */ + ulTickFlag = pdTRUE; + + /* If this is the first tick since exiting tickless mode then the CMT + compare match value needs resetting. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + } + #endif +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + prvYieldHandler(); +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvYieldHandler +static void prvYieldHandler( void ) +{ + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack + when the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across. */ + MOV.L [ R0 ], [ R15 ] ; R15 + MOV.L 4[ R0 ], 4[ R15 ] ; PC + MOV.L 8[ R0 ], 8[ R15 ] ; PSW + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the accumulator. */ + MVFACHI R15 + PUSH.L R15 + MVFACMI R15 ; Middle order word. + SHLL #16, R15 ; Shifted left as it is restored to the low order word. + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the + kernel structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is + required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15 + POP R15 + MVTACHI R15 + POPM R1-R15 + RTE + NOP + NOP +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); + + /* The following line is just to prevent the symbol getting optimised away. */ + ( void ) vTaskSwitchContext(); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Unlock. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Enable CMT0. */ + MSTP( CMT0 ) = 0; + + /* Lock again. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + + /* Divide the PCLK. */ + #if portCLOCK_DIVISOR == 512 + { + CMT0.CMCR.BIT.CKS = 3; + } + #elif portCLOCK_DIVISOR == 128 + { + CMT0.CMCR.BIT.CKS = 2; + } + #elif portCLOCK_DIVISOR == 32 + { + CMT0.CMCR.BIT.CKS = 1; + } + #elif portCLOCK_DIVISOR == 8 + { + CMT0.CMCR.BIT.CKS = 0; + } + #else + { + #error Invalid portCLOCK_DIVISOR setting + } + #endif + + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + static void prvSleep( TickType_t xExpectedIdleTime ) + { + /* Allow the application to define some pre-sleep processing. */ + configPRE_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING() + means the application defined code has already executed the WAIT + instruction. */ + if( xExpectedIdleTime > 0 ) + { + wait(); + } + + /* Allow the application to define some post sleep processing. */ + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount; + eSleepModeStatus eSleepAction; + + /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* Make sure the CMT reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Calculate the reload value required to wait xExpectedIdleTime tick + periods. */ + ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime; + if( ulMatchValue > ulStoppedTimerCompensation ) + { + /* Compensate for the fact that the CMT is going to be stopped + momentarily. */ + ulMatchValue -= ulStoppedTimerCompensation; + } + + /* Stop the CMT momentarily. The time the CMT is stopped for is + accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + /* Critical section using the global interrupt bit as the i bit is + automatically reset by the WAIT instruction. */ + clrpsw_i(); + + /* The tick flag is set to false before sleeping. If it is true when + sleep mode is exited then sleep mode was probably exited because the + tick was suppressed for the entire xExpectedIdleTime period. */ + ulTickFlag = pdFALSE; + + /* If a context switch is pending then abandon the low power entry as + the context switch might have been pended by an external interrupt that + requires processing. */ + eSleepAction = eTaskConfirmSleepModeStatus(); + if( eSleepAction == eAbortSleep ) + { + /* Restart tick. */ + CMT.CMSTR0.BIT.STR0 = 1; + setpsw_i(); + } + else if( eSleepAction == eNoTasksWaitingTimeout ) + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for software standby with all clocks stopped. */ + SYSTEM.SBYCR.BIT.SSBY = 1; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Sleep until something happens. Calling prvSleep() will + automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Restart the CMT. */ + CMT.CMSTR0.BIT.STR0 = 1; + } + else + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for deep sleep mode. */ + SYSTEM.MSTPCRC.BIT.DSLPE = 1; + SYSTEM.MSTPCRA.BIT.MSTPA28 = 1; + SYSTEM.SBYCR.BIT.SSBY = 0; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Adjust the match value to take into account that the current + time slice is already partially complete. */ + ulMatchValue -= ( uint32_t ) CMT0.CMCNT; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* Restart the CMT to count up to the new match value. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Sleep until something happens. Calling prvSleep() will + automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Stop CMT. Again, the time the SysTick is stopped for is + accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + ulCurrentCount = ( uint32_t ) CMT0.CMCNT; + + if( ulTickFlag != pdFALSE ) + { + /* The tick interrupt has already executed, although because + this function is called with the scheduler suspended the actual + tick processing will not occur until after this function has + exited. Reset the match value with whatever remains of this + tick period. */ + ulMatchValue = ulMatchValueForOneTick - ulCurrentCount; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* The tick interrupt handler will already have pended the tick + processing in the kernel. As the pending tick will be + processed as soon as this function exits, the tick value + maintained by the tick is stepped forward by one less than the + time spent sleeping. The actual stepping of the tick appears + later in this function. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + How many complete tick periods passed while the processor was + sleeping? */ + ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick; + + /* The match value is set to whatever fraction of a single tick + period remains. */ + ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick ); + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + } + + /* Restart the CMT so it runs up to the match value. The match value + will get set to the value required to generate exactly one tick period + the next time the CMT interrupt executes. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Wind the tick forward by the number of tick periods that the CPU + remained in a low power state. */ + vTaskStepTick( ulCompleteTickPeriods ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX100/port_asm.src b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX100/port_asm.src new file mode 100644 index 0000000..bd2d5d2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX100/port_asm.src @@ -0,0 +1,42 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + .GLB _vSoftwareInterruptISR + .GLB _vSoftwareInterruptEntry + + .SECTION P,CODE + +_vSoftwareInterruptEntry: + + BRA _vSoftwareInterruptISR + + .RVECTOR 27, _vSoftwareInterruptEntry + + .END + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX100/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX100/portmacro.h new file mode 100644 index 0000000..be0dd7f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX100/portmacro.h @@ -0,0 +1,152 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Hardware specifics. */ +#include "machine.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other +than portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() nop() + +#pragma inline_asm vPortYield +static void vPortYield( void ) +{ + /* Save clobbered register - may not actually be necessary if inline asm + functions are considered to use the same rules as function calls by the + compiler. */ + PUSH.L R5 + /* Set ITU SWINTR. */ + MOV.L #872E0H, R5 + MOV.B #1, [R5] + /* Read back to ensure the value is taken before proceeding. */ + MOV.L [R5], R5 + /* Restore clobbered register to its previous value. */ + POP R5 +} +#define portYIELD() vPortYield() +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) { portYIELD(); } } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( signed long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( signed long ) uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#if configUSE_TICKLESS_IDLE == 1 + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX100/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX100/readme.txt new file mode 100644 index 0000000..9e89a09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX100/readme.txt @@ -0,0 +1,72 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX200/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX200/port.c new file mode 100644 index 0000000..dde18d1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX200/port.c @@ -0,0 +1,325 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the RX200 port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) + +/*-----------------------------------------------------------*/ + +/* The following lines are to ensure vSoftwareInterruptEntry can be referenced, + and therefore installed in the vector table, when the FreeRTOS code is built +as a library. */ +extern BaseType_t vSoftwareInterruptEntry; +const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry; + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +static void prvYieldHandler( void ); + +/* + * The entry point for the software interrupt handler. This is the function + * that calls the inline asm function prvYieldHandler(). It is installed in + * the vector table, but the code that installs it is in prvYieldHandler rather + * than using a #pragma. + */ +void vSoftwareInterruptISR( void ); + +/*-----------------------------------------------------------*/ + +/* This is accessed by the inline assembler functions so is file scope for +convenience. */ +extern void *pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Offset to end up on 8 byte boundary. */ + pxTopOfStack--; + + /* R0 is not included as it is the stack pointer. */ + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xaaaabbbb; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Just to make sure the function is not optimised away. */ + ( void ) vSoftwareInterruptISR(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvStartFirstTask +static void prvStartFirstTask( void ) +{ + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + MVTACLO R15 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15 /* Accumulator high 32 bits. */ + POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */ + RTE /* This pops the remaining registers. */ + NOP + NOP +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) ) +void vTickISR( void ) +{ + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + set_ipl( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + prvYieldHandler(); +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvYieldHandler +static void prvYieldHandler( void ) +{ + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across. */ + MOV.L [ R0 ], [ R15 ] ; R15 + MOV.L 4[ R0 ], 4[ R15 ] ; PC + MOV.L 8[ R0 ], 8[ R15 ] ; PSW + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the accumulator. */ + MVFACHI R15 + PUSH.L R15 + MVFACMI R15 ; Middle order word. + SHLL #16, R15 ; Shifted left as it is restored to the low order word. + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15 + POP R15 + MVTACHI R15 + POPM R1-R15 + RTE + NOP + NOP +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); + + /* The following line is just to prevent the symbol getting optimised away. */ + ( void ) vTaskSwitchContext(); +} +/*-----------------------------------------------------------*/ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX200/port_asm.src b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX200/port_asm.src new file mode 100644 index 0000000..bd2d5d2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX200/port_asm.src @@ -0,0 +1,42 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + .GLB _vSoftwareInterruptISR + .GLB _vSoftwareInterruptEntry + + .SECTION P,CODE + +_vSoftwareInterruptEntry: + + BRA _vSoftwareInterruptISR + + .RVECTOR 27, _vSoftwareInterruptEntry + + .END + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX200/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX200/portmacro.h new file mode 100644 index 0000000..29339e8 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX200/portmacro.h @@ -0,0 +1,142 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Hardware specifics. */ +#include "machine.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() nop() + +#pragma inline_asm vPortYield +static void vPortYield( void ) +{ + /* Save clobbered register - may not actually be necessary if inline asm + functions are considered to use the same rules as function calls by the + compiler. */ + PUSH.L R5 + /* Set ITU SWINTR. */ + MOV.L #553696, R5 + MOV.B #1, [R5] + /* Read back to ensure the value is taken before proceeding. */ + MOV.L [R5], R5 + /* Restore clobbered register to its previous value. */ + POP R5 +} +#define portYIELD() vPortYield() +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX200/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX200/readme.txt new file mode 100644 index 0000000..9e89a09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX200/readme.txt @@ -0,0 +1,72 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600/port.c new file mode 100644 index 0000000..0939c20 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600/port.c @@ -0,0 +1,330 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the RX600 port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/*-----------------------------------------------------------*/ + +/* The following lines are to ensure vSoftwareInterruptEntry can be referenced, + and therefore installed in the vector table, when the FreeRTOS code is built +as a library. */ +extern BaseType_t vSoftwareInterruptEntry; +const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry; + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +static void prvYieldHandler( void ); + +/* + * The entry point for the software interrupt handler. This is the function + * that calls the inline asm function prvYieldHandler(). It is installed in + * the vector table, but the code that installs it is in prvYieldHandler rather + * than using a #pragma. + */ +void vSoftwareInterruptISR( void ); + +/*-----------------------------------------------------------*/ + +/* This is accessed by the inline assembler functions so is file scope for +convenience. */ +extern void *pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Just to make sure the function is not optimised away. */ + ( void ) vSoftwareInterruptISR(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvStartFirstTask +static void prvStartFirstTask( void ) +{ + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + MVTACLO R15 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15 /* Accumulator high 32 bits. */ + POP R15 + MVTC R15,FPSW /* Floating point status word. */ + POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */ + RTE /* This pops the remaining registers. */ + NOP + NOP +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) ) +void vTickISR( void ) +{ + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + set_ipl( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + prvYieldHandler(); +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvYieldHandler +static void prvYieldHandler( void ) +{ + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across. */ + MOV.L [ R0 ], [ R15 ] ; R15 + MOV.L 4[ R0 ], 4[ R15 ] ; PC + MOV.L 8[ R0 ], 8[ R15 ] ; PSW + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulator. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACHI R15 + PUSH.L R15 + MVFACMI R15 ; Middle order word. + SHLL #16, R15 ; Shifted left as it is restored to the low order word. + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15 + POP R15 + MVTACHI R15 + POP R15 + MVTC R15,FPSW + POPM R1-R15 + RTE + NOP + NOP +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); + + /* The following line is just to prevent the symbol getting optimised away. */ + ( void ) vTaskSwitchContext(); +} +/*-----------------------------------------------------------*/ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600/port_asm.src b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600/port_asm.src new file mode 100644 index 0000000..bd2d5d2 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600/port_asm.src @@ -0,0 +1,42 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + .GLB _vSoftwareInterruptISR + .GLB _vSoftwareInterruptEntry + + .SECTION P,CODE + +_vSoftwareInterruptEntry: + + BRA _vSoftwareInterruptISR + + .RVECTOR 27, _vSoftwareInterruptEntry + + .END + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600/portmacro.h new file mode 100644 index 0000000..e17a834 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600/portmacro.h @@ -0,0 +1,143 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Hardware specifics. */ +#include "machine.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() nop() + + +#pragma inline_asm vPortYield +static void vPortYield( void ) +{ + /* Save clobbered register - may not actually be necessary if inline asm + functions are considered to use the same rules as function calls by the + compiler. */ + PUSH.L R5 + /* Set ITU SWINTR. */ + MOV.L #553696, R5 + MOV.B #1, [R5] + /* Read back to ensure the value is taken before proceeding. */ + MOV.L [R5], R5 + /* Restore clobbered register to its previous value. */ + POP R5 +} +#define portYIELD() vPortYield() +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600/readme.txt new file mode 100644 index 0000000..9e89a09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600/readme.txt @@ -0,0 +1,72 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600v2/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600v2/port.c new file mode 100644 index 0000000..dbb9b42 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600v2/port.c @@ -0,0 +1,365 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the RX600 port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if defined( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H ) && ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + #include "platform.h" +#else + #include "iodefine.h" +#endif + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/*-----------------------------------------------------------*/ + +/* The following lines are to ensure vSoftwareInterruptEntry can be referenced, + and therefore installed in the vector table, when the FreeRTOS code is built +as a library. */ +extern BaseType_t vSoftwareInterruptEntry; +const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry; + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +static void prvYieldHandler( void ); + +/* + * The entry point for the software interrupt handler. This is the function + * that calls the inline asm function prvYieldHandler(). It is installed in + * the vector table, but the code that installs it is in prvYieldHandler rather + * than using a #pragma. + */ +void vSoftwareInterruptISR( void ); + +/*-----------------------------------------------------------*/ + +/* This is accessed by the inline assembler functions so is file scope for +convenience. */ +extern void *pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 1. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Just to make sure the function is not optimised away. */ + ( void ) vSoftwareInterruptISR(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvStartFirstTask +static void prvStartFirstTask( void ) +{ + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + MVTACLO R15, A0 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15, A0 /* Accumulator high 32 bits. */ + POP R15 + MVTACGU R15, A0 /* Accumulator guard. */ + POP R15 + MVTACLO R15, A1 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15, A1 /* Accumulator high 32 bits. */ + POP R15 + MVTACGU R15, A1 /* Accumulator guard. */ + POP R15 + MVTC R15,FPSW /* Floating point status word. */ + POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */ + RTE /* This pops the remaining registers. */ + NOP + NOP +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) ) +void vTickISR( void ) +{ + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + set_ipl( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + prvYieldHandler(); +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvYieldHandler +static void prvYieldHandler( void ) +{ + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across. */ + MOV.L [ R0 ], [ R15 ] ; R15 + MOV.L 4[ R0 ], 4[ R15 ] ; PC + MOV.L 8[ R0 ], 8[ R15 ] ; PSW + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulators. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACGU #0, A1, R15 + PUSH.L R15 + MVFACHI #0, A1, R15 + PUSH.L R15 + MVFACLO #0, A1, R15 ; Low order word. + PUSH.L R15 + MVFACGU #0, A0, R15 + PUSH.L R15 + MVFACHI #0, A0, R15 + PUSH.L R15 + MVFACLO #0, A0, R15 ; Low order word. + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15, A0 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15, A0 /* Accumulator high 32 bits. */ + POP R15 + MVTACGU R15, A0 /* Accumulator guard. */ + POP R15 + MVTACLO R15, A1 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15, A1 /* Accumulator high 32 bits. */ + POP R15 + MVTACGU R15, A1 /* Accumulator guard. */ + POP R15 + MVTC R15,FPSW + POPM R1-R15 + RTE + NOP + NOP +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); + + /* The following line is just to prevent the symbol getting optimised away. */ + ( void ) vTaskSwitchContext(); +} +/*-----------------------------------------------------------*/ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600v2/port_asm.src b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600v2/port_asm.src new file mode 100644 index 0000000..5ed9b3f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600v2/port_asm.src @@ -0,0 +1,42 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + .GLB _vSoftwareInterruptISR + .GLB _vSoftwareInterruptEntry + + .SECTION P,CODE + +_vSoftwareInterruptEntry: + + BRA _vSoftwareInterruptISR + + .RVECTOR 27, _vSoftwareInterruptEntry + + .END + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600v2/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600v2/portmacro.h new file mode 100644 index 0000000..6636126 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600v2/portmacro.h @@ -0,0 +1,143 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Hardware specifics. */ +#include "machine.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() nop() + + +#pragma inline_asm vPortYield +static void vPortYield( void ) +{ + /* Save clobbered register - may not actually be necessary if inline asm + functions are considered to use the same rules as function calls by the + compiler. */ + PUSH.L R5 + /* Set ITU SWINTR. */ + MOV.L #553696, R5 + MOV.B #1, [R5] + /* Read back to ensure the value is taken before proceeding. */ + MOV.L [R5], R5 + /* Restore clobbered register to its previous value. */ + POP R5 +} +#define portYIELD() vPortYield() +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600v2/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600v2/readme.txt new file mode 100644 index 0000000..9e89a09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX600v2/readme.txt @@ -0,0 +1,72 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX700v3_DPFPU/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX700v3_DPFPU/port.c new file mode 100644 index 0000000..7ccea01 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX700v3_DPFPU/port.c @@ -0,0 +1,591 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the RXv3 DPFPU port. +*----------------------------------------------------------*/ + +#warning Testing for DFPU support in this port is not yet complete + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DCMR ( ( StackType_t ) 0x00000000 ) +#define portINITIAL_DECNT ( ( StackType_t ) 0x00000001 ) + +/* Tasks are not created with a DPFPU context, but can be given a DPFPU context + * after they have been created. A variable is stored as part of the tasks context + * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or + * any other value if the task does have a DPFPU context. */ +#define portNO_DPFPU_CONTEXT ( ( StackType_t ) 0 ) +#define portHAS_DPFPU_CONTEXT ( ( StackType_t ) 1 ) + +/* The space on the stack required to hold the DPFPU data registers. This is 16 + * 64-bit registers. */ +#define portDPFPU_DATA_REGISTER_WORDS ( 16 * 2 ) + +/*-----------------------------------------------------------*/ + +/* The following lines are to ensure vSoftwareInterruptEntry can be referenced, + * and therefore installed in the vector table, when the FreeRTOS code is built + * as a library. */ +extern BaseType_t vSoftwareInterruptEntry; +const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry; + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +static void prvYieldHandler( void ); + +/* + * The entry point for the software interrupt handler. This is the function + * that calls the inline asm function prvYieldHandler(). It is installed in + * the vector table, but the code that installs it is in prvYieldHandler rather + * than using a #pragma. + */ +void vSoftwareInterruptISR( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +void vTickISR( void ); + +/*-----------------------------------------------------------*/ + +/* Saved as part of the task context. If ulPortTaskHasDPFPUContext is non-zero + * then a DPFPU context must be saved and restored for the task. */ +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + StackType_t ulPortTaskHasDPFPUContext = portNO_DPFPU_CONTEXT; + +#endif /* configUSE_TASK_DPFPU_SUPPORT */ + +/* This is accessed by the inline assembler functions so is file scope for + * convenience. */ +extern void * pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= 15; + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 0. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + { + /* The task will start without a DPFPU context. A task that + * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before + * executing any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_DPFPU_CONTEXT; + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + { + /* The task will start with a DPFPU context. Leave enough + * space for the registers - and ensure they are initialised if desired. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1515.1515; /* DR15. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1414.1414; /* DR14. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1313.1313; /* DR13. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1212.1212; /* DR12. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1111.1111; /* DR11. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1010.1010; /* DR10. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 909.0909; /* DR9. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 808.0808; /* DR8. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 707.0707; /* DR7. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 606.0606; /* DR6. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 505.0505; /* DR5. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 404.0404; /* DR4. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 303.0303; /* DR3. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 202.0202; /* DR2. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 101.0101; /* DR1. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 9876.54321;/* DR0. */ + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) ); + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DCMR; /* DCMR. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DPSW; /* DPSW. */ + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 ) + { + /* Omit DPFPU support. */ + } + #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + { + #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined. + } + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + void vPortTaskUsesDPFPU( void ) + { + /* A task is registering the fact that it needs a DPFPU context. Set the + * DPFPU flag (which is saved as part of the task context). */ + ulPortTaskHasDPFPUContext = portHAS_DPFPU_CONTEXT; + } + +#endif /* configUSE_TASK_DPFPU_SUPPORT */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Just to make sure the function is not optimised away. */ + ( void ) vSoftwareInterruptISR(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); + + /* The following line is just to prevent the symbol getting optimised away. */ + ( void ) vTaskSwitchContext(); +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvStartFirstTask +static void prvStartFirstTask( void ) +{ +#ifndef __CDT_PARSER__ + + /* When starting the scheduler there is nothing that needs moving to the + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ + SETPSW U + + + /* Obtain the location of the stack associated with which ever task + * pxCurrentTCB is currently pointing to. */ + MOV.L # _pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + + /* Restore the registers from the stack of the task pointed to by + * pxCurrentTCB. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* The restored ulPortTaskHasDPFPUContext is to be zero here. + * So, it is never necessary to restore the DPFPU context here. */ + POP R15 + MOV.L # _ulPortTaskHasDPFPUContext, R14 + MOV.L R15, [ R14 ] + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + + /* Restore the DPFPU context. */ + DPOPM.L DPSW-DECNT + DPOPM.D DR0-DR15 + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + + /* Floating point status word. */ + MVTC R15, FPSW + + /* R1 to R15 - R0 is not included as it is the SP. */ + POPM R1-R15 + + /* This pops the remaining registers. */ + RTE + NOP + NOP + +#endif /* ifndef __CDT_PARSER__ */ +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + prvYieldHandler(); +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvYieldHandler +static void prvYieldHandler( void ) +{ +#ifndef __CDT_PARSER__ + + /* Re-enable interrupts. */ + SETPSW I + + + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB # 12, R15 + MVTC R15, USP + + /* Copy the data across, R15, then PC, then PSW. */ + MOV.L [ R0 ], [ R15 ] + MOV.L 4[ R0 ], 4[ R15 ] + MOV.L 8[ R0 ], 8[ R15 ] + + /* Move the interrupt stack pointer to its new correct position. */ + ADD # 12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulators. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACGU # 0, A1, R15 + PUSH.L R15 + MVFACHI # 0, A1, R15 + PUSH.L R15 + MVFACLO # 0, A1, R15 /* Low order word. */ + PUSH.L R15 + MVFACGU # 0, A0, R15 + PUSH.L R15 + MVFACHI # 0, A0, R15 + PUSH.L R15 + MVFACLO # 0, A0, R15 /* Low order word. */ + PUSH.L R15 + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* Does the task have a DPFPU context that needs saving? If + * ulPortTaskHasDPFPUContext is 0 then no. */ + MOV.L # _ulPortTaskHasDPFPUContext, R15 + MOV.L [ R15 ], R15 + CMP # 0, R15 + + /* Save the DPFPU context, if any. */ + BEQ.B ?+ + DPUSHM.D DR0-DR15 + DPUSHM.L DPSW-DECNT + ?: + + /* Save ulPortTaskHasDPFPUContext itself. */ + PUSH.L R15 + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + + /* Save the DPFPU context, always. */ + DPUSHM.D DR0-DR15 + DPUSHM.L DPSW-DECNT + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + + /* Save the stack pointer to the TCB. */ + MOV.L # _pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + * structures are being accessed. */ + MVTIPL # configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL # configKERNEL_INTERRUPT_PRIORITY + + + /* Load the stack pointer of the task that is now selected as the Running + * state task from its TCB. */ + MOV.L # _pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + + /* Restore the context of the new task. The PSW (Program Status Word) and + * PC will be popped by the RTE instruction. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* Is there a DPFPU context to restore? If the restored + * ulPortTaskHasDPFPUContext is zero then no. */ + POP R15 + MOV.L # _ulPortTaskHasDPFPUContext, R14 + MOV.L R15, [ R14 ] + CMP # 0, R15 + + /* Restore the DPFPU context, if any. */ + BEQ.B ?+ + DPOPM.L DPSW-DECNT + DPOPM.D DR0-DR15 + ?: + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + + /* Restore the DPFPU context, always. */ + DPOPM.L DPSW-DECNT + DPOPM.D DR0-DR15 + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + MVTC R15, FPSW + POPM R1-R15 + RTE + NOP + NOP + +#endif /* ifndef __CDT_PARSER__ */ +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) ) +void vTickISR( void ) +{ + /* Increment the tick, and perform any processing the new tick value + * necessitates. Ensure IPL is at the max syscall value first. */ + set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + set_ipl( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX700v3_DPFPU/port_asm.src b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX700v3_DPFPU/port_asm.src new file mode 100644 index 0000000..60f0dbc --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX700v3_DPFPU/port_asm.src @@ -0,0 +1,42 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + .GLB _vSoftwareInterruptISR + .GLB _vSoftwareInterruptEntry + + .SECTION P,CODE + +_vSoftwareInterruptEntry: + + BRA _vSoftwareInterruptISR + + .RVECTOR 27, _vSoftwareInterruptEntry + + .END + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX700v3_DPFPU/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX700v3_DPFPU/portmacro.h new file mode 100644 index 0000000..f70b74e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX700v3_DPFPU/portmacro.h @@ -0,0 +1,186 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/* Hardware specifics. */ + #include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ + #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 + #endif + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will + * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before + * making use of any DPFPU registers. If configUSE_TASK_DPFPU_SUPPORT is set to 2 then + * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has + * no effect. If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care + * of any DPFPU context (even if DPFPU registers are used). */ + #ifndef configUSE_TASK_DPFPU_SUPPORT + #define configUSE_TASK_DPFPU_SUPPORT 1 + #endif + +/*-----------------------------------------------------------*/ + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ + #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ + #define portSTACK_GROWTH -1 + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portNOP() nop() + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ + #pragma inline_asm vPortYield + static void vPortYield( void ) + { + #ifndef __CDT_PARSER__ + /* Save clobbered register - may not actually be necessary if inline asm + * functions are considered to use the same rules as function calls by the + * compiler. */ + PUSH.L R5 + /* Set ITU SWINTR. */ + MOV.L # 000872E0H, R5 + MOV.B # 1, [ R5 ] + /* Read back to ensure the value is taken before proceeding. */ + CMP [ R5 ].UB, R5 + /* Restore clobbered register to its previous value. */ + POP R5 + #endif + } + + #define portYIELD() vPortYield() + #define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 ) + +/* These macros should not be called directly, but through the + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ + #define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 ) + #ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #else + #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #endif + +/* Critical nesting counts are stored in the TCB. */ + #define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/*-----------------------------------------------------------*/ + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or left undefined) then tasks are + * created without a DPFPU context and must call vPortTaskUsesDPFPU() to give + * themselves a DPFPU context before using any DPFPU instructions. If + * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context + * by default. */ + #if( configUSE_TASK_DPFPU_SUPPORT == 1 ) + void vPortTaskUsesDPFPU( void ); + #else +/* Each task has a DPFPU context already, so define this function away to + * nothing to prevent it being called accidentally. */ + #define vPortTaskUsesDPFPU() + #endif + #define portTASK_USES_DPFPU() vPortTaskUsesDPFPU() + +/* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */ + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU() + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX700v3_DPFPU/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX700v3_DPFPU/readme.txt new file mode 100644 index 0000000..9e89a09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/RX700v3_DPFPU/readme.txt @@ -0,0 +1,72 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/SH2A_FPU/ISR_Support.inc b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/SH2A_FPU/ISR_Support.inc new file mode 100644 index 0000000..90451d9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/SH2A_FPU/ISR_Support.inc @@ -0,0 +1,75 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + .macro portSAVE_CONTEXT + + ; Save r0 to r14 and pr. + movml.l r15, @-r15 + + ; Save mac1, mach and gbr + sts.l macl, @-r15 + sts.l mach, @-r15 + stc.l gbr, @-r15 + + ; Get the address of pxCurrentTCB + mov.l #_pxCurrentTCB, r0 + + ; Get the address of pxTopOfStack from the TCB. + mov.l @r0, r0 + + ; Save the stack pointer in pxTopOfStack. + mov.l r15, @r0 + + .endm + +;----------------------------------------------------------- + + .macro portRESTORE_CONTEXT + + ; Get the address of the pxCurrentTCB variable. + mov.l #_pxCurrentTCB, r0 + + ; Get the address of the task stack from pxCurrentTCB. + mov.l @r0, r0 + + ; Get the task stack itself into the stack pointer. + mov.l @r0, r15 + + ; Restore system registers. + ldc.l @r15+, gbr + lds.l @r15+, mach + lds.l @r15+, macl + + ; Restore r0 to r14 and PR + movml.l @r15+, r15 + + ; Pop the SR and PC to jump to the start of the task. + rte + nop + + .endm +;----------------------------------------------------------- diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/SH2A_FPU/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/SH2A_FPU/port.c new file mode 100644 index 0000000..5297fd9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/SH2A_FPU/port.c @@ -0,0 +1,272 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the SH2A port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/*-----------------------------------------------------------*/ + +/* The SR assigned to a newly created task. The only important thing in this +value is for all interrupts to be enabled. */ +#define portINITIAL_SR ( 0UL ) + +/* Dimensions the array into which the floating point context is saved. +Allocate enough space for FPR0 to FPR15, FPUL and FPSCR, each of which is 4 +bytes big. If this number is changed then the 72 in portasm.src also needs +changing. */ +#define portFLOP_REGISTERS_TO_STORE ( 18 ) +#define portFLOP_STORAGE_SIZE ( portFLOP_REGISTERS_TO_STORE * 4 ) + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error configSUPPORT_DYNAMIC_ALLOCATION must be 1 to use this port. +#endif + +/*-----------------------------------------------------------*/ + +/* + * The TRAPA handler used to force a context switch. + */ +void vPortYield( void ); + +/* + * Function to start the first task executing - defined in portasm.src. + */ +extern void vPortStartFirstTask( void ); + +/* + * Obtains the current GBR value - defined in portasm.src. + */ +extern uint32_t ulPortGetGBR( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Mark the end of the stack - used for debugging only and can be removed. */ + *pxTopOfStack = 0x11111111UL; + pxTopOfStack--; + *pxTopOfStack = 0x22222222UL; + pxTopOfStack--; + *pxTopOfStack = 0x33333333UL; + pxTopOfStack--; + + /* SR. */ + *pxTopOfStack = portINITIAL_SR; + pxTopOfStack--; + + /* PC. */ + *pxTopOfStack = ( uint32_t ) pxCode; + pxTopOfStack--; + + /* PR. */ + *pxTopOfStack = 15; + pxTopOfStack--; + + /* 14. */ + *pxTopOfStack = 14; + pxTopOfStack--; + + /* R13. */ + *pxTopOfStack = 13; + pxTopOfStack--; + + /* R12. */ + *pxTopOfStack = 12; + pxTopOfStack--; + + /* R11. */ + *pxTopOfStack = 11; + pxTopOfStack--; + + /* R10. */ + *pxTopOfStack = 10; + pxTopOfStack--; + + /* R9. */ + *pxTopOfStack = 9; + pxTopOfStack--; + + /* R8. */ + *pxTopOfStack = 8; + pxTopOfStack--; + + /* R7. */ + *pxTopOfStack = 7; + pxTopOfStack--; + + /* R6. */ + *pxTopOfStack = 6; + pxTopOfStack--; + + /* R5. */ + *pxTopOfStack = 5; + pxTopOfStack--; + + /* R4. */ + *pxTopOfStack = ( uint32_t ) pvParameters; + pxTopOfStack--; + + /* R3. */ + *pxTopOfStack = 3; + pxTopOfStack--; + + /* R2. */ + *pxTopOfStack = 2; + pxTopOfStack--; + + /* R1. */ + *pxTopOfStack = 1; + pxTopOfStack--; + + /* R0 */ + *pxTopOfStack = 0; + pxTopOfStack--; + + /* MACL. */ + *pxTopOfStack = 16; + pxTopOfStack--; + + /* MACH. */ + *pxTopOfStack = 17; + pxTopOfStack--; + + /* GBR. */ + *pxTopOfStack = ulPortGetGBR(); + + /* GBR = global base register. + VBR = vector base register. + TBR = jump table base register. + R15 is the stack pointer. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Start the first task. This will only restore the standard registers and + not the flop registers. This does not really matter though because the only + flop register that is initialised to a particular value is fpscr, and it is + only initialised to the current value, which will still be the current value + when the first task starts executing. */ + trapa( portSTART_SCHEDULER_TRAP_NO ); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented as there is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ +int32_t lInterruptMask; + + /* Ensure the yield trap runs at the same priority as the other interrupts + that can cause a context switch. */ + lInterruptMask = get_imask(); + + /* taskYIELD() can only be called from a task, not an interrupt, so the + current interrupt mask can only be 0 or portKERNEL_INTERRUPT_PRIORITY and + the mask can be set without risk of accidentally lowering the mask value. */ + set_imask( portKERNEL_INTERRUPT_PRIORITY ); + + trapa( portYIELD_TRAP_NO ); + + /* Restore the interrupt mask to whatever it was previously (when the + function was entered). */ + set_imask( ( int ) lInterruptMask ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortUsesFloatingPoint( TaskHandle_t xTask ) +{ +uint32_t *pulFlopBuffer; +BaseType_t xReturn; +extern void * volatile pxCurrentTCB; + + /* This function tells the kernel that the task referenced by xTask is + going to use the floating point registers and therefore requires the + floating point registers saved as part of its context. */ + + /* Passing NULL as xTask is used to indicate that the calling task is the + subject task - so pxCurrentTCB is the task handle. */ + if( xTask == NULL ) + { + xTask = ( TaskHandle_t ) pxCurrentTCB; + } + + /* Allocate a buffer large enough to hold all the flop registers. */ + pulFlopBuffer = ( uint32_t * ) pvPortMalloc( portFLOP_STORAGE_SIZE ); + + if( pulFlopBuffer != NULL ) + { + /* Start with the registers in a benign state. */ + memset( ( void * ) pulFlopBuffer, 0x00, portFLOP_STORAGE_SIZE ); + + /* The first thing to get saved in the buffer is the FPSCR value - + initialise this to the current FPSCR value. */ + *pulFlopBuffer = get_fpscr(); + + /* Use the task tag to point to the flop buffer. Pass pointer to just + above the buffer because the flop save routine uses a pre-decrement. */ + vTaskSetApplicationTaskTag( xTask, ( void * ) ( pulFlopBuffer + portFLOP_REGISTERS_TO_STORE ) ); + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/SH2A_FPU/portasm.src b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/SH2A_FPU/portasm.src new file mode 100644 index 0000000..705f6f0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/SH2A_FPU/portasm.src @@ -0,0 +1,151 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + .import _pxCurrentTCB + .import _vTaskSwitchContext + .import _xTaskIncrementTick + + .export _vPortStartFirstTask + .export _ulPortGetGBR + .export _vPortYieldHandler + .export _vPortPreemptiveTick + .export _vPortCooperativeTick + .export _vPortSaveFlopRegisters + .export _vPortRestoreFlopRegisters + + .section P + + .INCLUDE "ISR_Support.inc" + +_vPortStartFirstTask: + + portRESTORE_CONTEXT + +;----------------------------------------------------------- + +_vPortYieldHandler: + + portSAVE_CONTEXT + + mov.l #_vTaskSwitchContext, r0 + jsr @r0 + nop + + portRESTORE_CONTEXT + +;----------------------------------------------------------- + +_vPortPreemptiveTick + + portSAVE_CONTEXT + + mov.l #_xTaskIncrementTick, r0 + jsr @r0 + nop + + mov.l #_vTaskSwitchContext, r0 + jsr @r0 + nop + + portRESTORE_CONTEXT + +;----------------------------------------------------------- + +_vPortCooperativeTick + + portSAVE_CONTEXT + + mov.l #_xTaskIncrementTick, r0 + jsr @r0 + nop + + portRESTORE_CONTEXT + +;----------------------------------------------------------- + +_ulPortGetGBR: + + stc.l gbr, r0 + rts + nop + +;----------------------------------------------------------- + +_vPortSaveFlopRegisters: + + fmov.s fr0, @-r4 + fmov.s fr1, @-r4 + fmov.s fr2, @-r4 + fmov.s fr3, @-r4 + fmov.s fr4, @-r4 + fmov.s fr5, @-r4 + fmov.s fr6, @-r4 + fmov.s fr7, @-r4 + fmov.s fr8, @-r4 + fmov.s fr9, @-r4 + fmov.s fr10, @-r4 + fmov.s fr11, @-r4 + fmov.s fr12, @-r4 + fmov.s fr13, @-r4 + fmov.s fr14, @-r4 + fmov.s fr15, @-r4 + sts.l fpul, @-r4 + sts.l fpscr, @-r4 + + rts + nop + +;----------------------------------------------------------- + +_vPortRestoreFlopRegisters: + + add.l #-72, r4 + lds.l @r4+, fpscr + lds.l @r4+, fpul + fmov.s @r4+, fr15 + fmov.s @r4+, fr14 + fmov.s @r4+, fr13 + fmov.s @r4+, fr12 + fmov.s @r4+, fr11 + fmov.s @r4+, fr10 + fmov.s @r4+, fr9 + fmov.s @r4+, fr8 + fmov.s @r4+, fr7 + fmov.s @r4+, fr6 + fmov.s @r4+, fr5 + fmov.s @r4+, fr4 + fmov.s @r4+, fr3 + fmov.s @r4+, fr2 + fmov.s @r4+, fr1 + fmov.s @r4+, fr0 + + rts + nop + + .end + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/SH2A_FPU/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/SH2A_FPU/portmacro.h new file mode 100644 index 0000000..ce248f4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Renesas/SH2A_FPU/portmacro.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() nop() +#define portSTART_SCHEDULER_TRAP_NO ( 32 ) +#define portYIELD_TRAP_NO ( 33 ) +#define portKERNEL_INTERRUPT_PRIORITY ( 1 ) + +void vPortYield( void ); +#define portYIELD() vPortYield() + +extern void vTaskSwitchContext( void ); +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) vTaskSwitchContext(); } while( 0 ) + +/* + * This function tells the kernel that the task referenced by xTask is going to + * use the floating point registers and therefore requires the floating point + * registers saved as part of its context. + */ +BaseType_t xPortUsesFloatingPoint( void* xTask ); + +/* + * The flop save and restore functions are defined in portasm.src and called by + * the trace "task switched in" and "trace task switched out" macros. + */ +void vPortSaveFlopRegisters( void *pulBuffer ); +void vPortRestoreFlopRegisters( void *pulBuffer ); + +/* + * pxTaskTag is used to point to the buffer into which the floating point + * context should be saved. If pxTaskTag is NULL then the task does not use + * a floating point context. + */ +#define traceTASK_SWITCHED_OUT() do { if( pxCurrentTCB->pxTaskTag != NULL ) vPortSaveFlopRegisters( pxCurrentTCB->pxTaskTag ); } while( 0 ) +#define traceTASK_SWITCHED_IN() do { if( pxCurrentTCB->pxTaskTag != NULL ) vPortRestoreFlopRegisters( pxCurrentTCB->pxTaskTag ); } while( 0 ) + +/* + * These macros should be called directly, but through the taskENTER_CRITICAL() + * and taskEXIT_CRITICAL() macros. + */ +#define portENABLE_INTERRUPTS() set_imask( 0x00 ) +#define portDISABLE_INTERRUPTS() set_imask( portKERNEL_INTERRUPT_PRIORITY ) + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical(); +#define portEXIT_CRITICAL() vTaskExitCritical(); + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/ARM7/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/ARM7/readme.txt new file mode 100644 index 0000000..8d3e87f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/ARM7/readme.txt @@ -0,0 +1 @@ +The Rowley ARM7 demo uses the GCC ARM7 port files. \ No newline at end of file diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/MSP430F449/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/MSP430F449/port.c new file mode 100644 index 0000000..36b117c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/MSP430F449/port.c @@ -0,0 +1,173 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430 port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x3333; + pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + executing an ISR. We want the stack to look just as if this has happened + so place a pointer to the start of the task on the stack first - followed + by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( StackType_t ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xcccc; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xeeee; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R15. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/MSP430F449/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/MSP430F449/portasm.h new file mode 100644 index 0000000..3c5dc08 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/MSP430F449/portasm.h @@ -0,0 +1,81 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORT_ASM_H +#define PORT_ASM_H + +portSAVE_CONTEXT macro + /* Save the remaining registers. */ + push r4 + push r5 + push r6 + push r7 + push r8 + push r9 + push r10 + push r11 + push r12 + push r13 + push r14 + push r15 + mov.w &_usCriticalNesting, r14 + push r14 + mov.w &_pxCurrentTCB, r12 + mov.w r1, @r12 + endm +/*-----------------------------------------------------------*/ + +portRESTORE_CONTEXT macro + mov.w &_pxCurrentTCB, r12 + mov.w @r12, r1 + pop r15 + mov.w r15, &_usCriticalNesting + pop r15 + pop r14 + pop r13 + pop r12 + pop r11 + pop r10 + pop r9 + pop r8 + pop r7 + pop r6 + pop r5 + pop r4 + + /* The last thing on the stack will be the status register. + Ensure the power down bits are clear ready for the next + time this power down register is popped from the stack. */ + bic.w #0xf0,0(SP) + + reti + endm +/*-----------------------------------------------------------*/ + +#endif + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/MSP430F449/portext.asm b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/MSP430F449/portext.asm new file mode 100644 index 0000000..f4d4388 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/MSP430F449/portext.asm @@ -0,0 +1,103 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" +#include "portasm.h" + + +.CODE + +/* + * The RTOS tick ISR. + * + * If the cooperative scheduler is in use this simply increments the tick + * count. + * + * If the preemptive scheduler is in use a context switch can also occur. + */ +_vTickISR: + portSAVE_CONTEXT + + call #_xTaskIncrementTick + cmp.w #0x00, r15 + jeq _SkipContextSwitch + call #_vTaskSwitchContext +_SkipContextSwitch: + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Manual context switch called by the portYIELD() macro. + */ +_vPortYield:: + + /* Mimic an interrupt by pushing the SR. */ + push SR + + /* Now the SR is stacked we can disable interrupts. */ + dint + + /* Save the context of the current task. */ + portSAVE_CONTEXT + + /* Switch to the highest priority task that is ready to run. */ + call #_vTaskSwitchContext + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Start off the scheduler by initialising the RTOS tick timer, then restoring + * the context of the first task. + */ +_xPortStartScheduler:: + + /* Setup the hardware to generate the tick. Interrupts are disabled + when this function is called. */ + call #_prvSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + + /* Place the tick ISR in the correct vector. */ + .VECTORS + + .KEEP + + ORG TIMERA0_VECTOR + DW _vTickISR + + + + END + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/MSP430F449/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/MSP430F449/portmacro.h new file mode 100644 index 0000000..78a4d87 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Rowley/MSP430F449/portmacro.h @@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _DINT(); _NOP() +#define portENABLE_INTERRUPTS() _EINT(); +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel + +#if configINTERRUPT_EXAMPLE_METHOD == 2 + +extern void vTaskSwitchContext( void ); +#define portYIELD_FROM_ISR( x ) do { if( x ) vTaskSwitchContext(); } while( 0 ) + +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/SDCC/Cygnal/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/SDCC/Cygnal/port.c new file mode 100644 index 0000000..66cf676 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/SDCC/Cygnal/port.c @@ -0,0 +1,425 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Cygnal port. + *----------------------------------------------------------*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup timer 2 to produce the RTOS tick. */ +#define portCLOCK_DIVISOR ( ( uint32_t ) 12 ) +#define portMAX_TIMER_VALUE ( ( uint32_t ) 0xffff ) +#define portENABLE_TIMER ( ( uint8_t ) 0x04 ) +#define portTIMER_2_INTERRUPT_ENABLE ( ( uint8_t ) 0x20 ) + +/* The value used in the IE register when a task first starts. */ +#define portGLOBAL_INTERRUPT_BIT ( ( StackType_t ) 0x80 ) + +/* The value used in the PSW register when a task first starts. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00 ) + +/* Macro to clear the timer 2 interrupt flag. */ +#define portCLEAR_INTERRUPT_FLAG() TMR2CN &= ~0x80; + +/* Used during a context switch to store the size of the stack being copied +to or from XRAM. */ +data static uint8_t ucStackBytes; + +/* Used during a context switch to point to the next byte in XRAM from/to which +a RAM byte is to be copied. */ +xdata static StackType_t * data pxXRAMStack; + +/* Used during a context switch to point to the next byte in RAM from/to which +an XRAM byte is to be copied. */ +data static StackType_t * data pxRAMStack; + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* + * Setup the hardware to generate an interrupt off timer 2 at the required + * frequency. + */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ +/* + * Macro that copies the current stack from internal RAM to XRAM. This is + * required as the 8051 only contains enough internal RAM for a single stack, + * but we have a stack for every task. + */ +#define portCOPY_STACK_TO_XRAM() \ +{ \ + /* pxCurrentTCB points to a TCB which itself points to the location into \ + which the first stack byte should be copied. Set pxXRAMStack to point \ + to the location into which the first stack byte is to be copied. */ \ + pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \ + \ + /* Set pxRAMStack to point to the first byte to be coped from the stack. */ \ + pxRAMStack = ( data StackType_t * data ) configSTACK_START; \ + \ + /* Calculate the size of the stack we are about to copy from the current \ + stack pointer value. */ \ + ucStackBytes = SP - ( configSTACK_START - 1 ); \ + \ + /* Before starting to copy the stack, store the calculated stack size so \ + the stack can be restored when the task is resumed. */ \ + *pxXRAMStack = ucStackBytes; \ + \ + /* Copy each stack byte in turn. pxXRAMStack is incremented first as we \ + have already stored the stack size into XRAM. */ \ + while( ucStackBytes ) \ + { \ + pxXRAMStack++; \ + *pxXRAMStack = *pxRAMStack; \ + pxRAMStack++; \ + ucStackBytes--; \ + } \ +} +/*-----------------------------------------------------------*/ + +/* + * Macro that copies the stack of the task being resumed from XRAM into + * internal RAM. + */ +#define portCOPY_XRAM_TO_STACK() \ +{ \ + /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to \ + copy the data back out of XRAM and into the stack. */ \ + pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \ + pxRAMStack = ( data StackType_t * data ) ( configSTACK_START - 1 ); \ + \ + /* The first value stored in XRAM was the size of the stack - i.e. the \ + number of bytes we need to copy back. */ \ + ucStackBytes = pxXRAMStack[ 0 ]; \ + \ + /* Copy the required number of bytes back into the stack. */ \ + do \ + { \ + pxXRAMStack++; \ + pxRAMStack++; \ + *pxRAMStack = *pxXRAMStack; \ + ucStackBytes--; \ + } while( ucStackBytes ); \ + \ + /* Restore the stack pointer ready to use the restored stack. */ \ + SP = ( uint8_t ) pxRAMStack; \ +} +/*-----------------------------------------------------------*/ + +/* + * Macro to push the current execution context onto the stack, before the stack + * is moved to XRAM. + */ +#define portSAVE_CONTEXT() \ +{ \ + _asm \ + /* Push ACC first, as when restoring the context it must be restored \ + last (it is used to set the IE register). */ \ + push ACC \ + /* Store the IE register then disable interrupts. */ \ + push IE \ + clr _EA \ + push DPL \ + push DPH \ + push b \ + push ar2 \ + push ar3 \ + push ar4 \ + push ar5 \ + push ar6 \ + push ar7 \ + push ar0 \ + push ar1 \ + push PSW \ + _endasm; \ + PSW = 0; \ + _asm \ + push _bp \ + _endasm; \ +} +/*-----------------------------------------------------------*/ + +/* + * Macro that restores the execution context from the stack. The execution + * context was saved into the stack before the stack was copied into XRAM. + */ +#define portRESTORE_CONTEXT() \ +{ \ + _asm \ + pop _bp \ + pop PSW \ + pop ar1 \ + pop ar0 \ + pop ar7 \ + pop ar6 \ + pop ar5 \ + pop ar4 \ + pop ar3 \ + pop ar2 \ + pop b \ + pop DPH \ + pop DPL \ + /* The next byte of the stack is the IE register. Only the global \ + enable bit forms part of the task context. Pop off the IE then set \ + the global enable bit to match that of the stored IE register. */ \ + pop ACC \ + JB ACC.7,0098$ \ + CLR IE.7 \ + LJMP 0099$ \ + 0098$: \ + SETB IE.7 \ + 0099$: \ + /* Finally pop off the ACC, which was the first register saved. */ \ + pop ACC \ + reti \ + _endasm; \ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint32_t ulAddress; +StackType_t *pxStartOfStack; + + /* Leave space to write the size of the stack as the first byte. */ + pxStartOfStack = pxTopOfStack; + pxTopOfStack++; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be uncommented if required. + *pxTopOfStack = 0x11; + pxTopOfStack++; + *pxTopOfStack = 0x22; + pxTopOfStack++; + *pxTopOfStack = 0x33; + pxTopOfStack++; + */ + + /* Simulate how the stack would look after a call to the scheduler tick + ISR. + + The return address that would have been pushed by the MCU. */ + ulAddress = ( uint32_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ulAddress; + ulAddress >>= 8; + pxTopOfStack++; + *pxTopOfStack = ( StackType_t ) ( ulAddress ); + pxTopOfStack++; + + /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */ + *pxTopOfStack = 0xaa; /* acc */ + pxTopOfStack++; + + /* We want tasks to start with interrupts enabled. */ + *pxTopOfStack = portGLOBAL_INTERRUPT_BIT; + pxTopOfStack++; + + /* The function parameters will be passed in the DPTR and B register as + a three byte generic pointer is used. */ + ulAddress = ( uint32_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ulAddress; /* DPL */ + ulAddress >>= 8; + *pxTopOfStack++; + *pxTopOfStack = ( StackType_t ) ulAddress; /* DPH */ + ulAddress >>= 8; + pxTopOfStack++; + *pxTopOfStack = ( StackType_t ) ulAddress; /* b */ + pxTopOfStack++; + + /* The remaining registers are straight forward. */ + *pxTopOfStack = 0x02; /* R2 */ + pxTopOfStack++; + *pxTopOfStack = 0x03; /* R3 */ + pxTopOfStack++; + *pxTopOfStack = 0x04; /* R4 */ + pxTopOfStack++; + *pxTopOfStack = 0x05; /* R5 */ + pxTopOfStack++; + *pxTopOfStack = 0x06; /* R6 */ + pxTopOfStack++; + *pxTopOfStack = 0x07; /* R7 */ + pxTopOfStack++; + *pxTopOfStack = 0x00; /* R0 */ + pxTopOfStack++; + *pxTopOfStack = 0x01; /* R1 */ + pxTopOfStack++; + *pxTopOfStack = 0x00; /* PSW */ + pxTopOfStack++; + *pxTopOfStack = 0xbb; /* BP */ + + /* Dont increment the stack size here as we don't want to include + the stack size byte as part of the stack size count. + + Finally we place the stack size at the beginning. */ + *pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack ); + + /* Unlike most ports, we return the start of the stack as this is where the + size of the stack is stored. */ + return pxStartOfStack; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* Setup timer 2 to generate the RTOS tick. */ + prvSetupTimerInterrupt(); + + /* Make sure we start with the expected SFR page. This line should not + really be required. */ + SFRPAGE = 0; + + /* Copy the stack for the first task to execute from XRAM into the stack, + restore the task context from the new stack, then start running the task. */ + portCOPY_XRAM_TO_STACK(); + portRESTORE_CONTEXT(); + + /* Should never get here! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented for this port. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. The first thing we do is save the registers so we + * can use a naked attribute. + */ +void vPortYield( void ) _naked +{ + /* Save the execution context onto the stack, then copy the entire stack + to XRAM. This is necessary as the internal RAM is only large enough to + hold one stack, and we want one per task. + + PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH + IS REQUIRED. */ + portSAVE_CONTEXT(); + portCOPY_STACK_TO_XRAM(); + + /* Call the standard scheduler context switch function. */ + vTaskSwitchContext(); + + /* Copy the stack of the task about to execute from XRAM into RAM and + restore it's context ready to run on exiting. */ + portCOPY_XRAM_TO_STACK(); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + void vTimer2ISR( void ) interrupt 5 _naked + { + /* Preemptive context switch function triggered by the timer 2 ISR. + This does the same as vPortYield() (see above) with the addition + of incrementing the RTOS tick count. */ + + portSAVE_CONTEXT(); + portCOPY_STACK_TO_XRAM(); + + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + portCLEAR_INTERRUPT_FLAG(); + portCOPY_XRAM_TO_STACK(); + portRESTORE_CONTEXT(); + } +#else + void vTimer2ISR( void ) interrupt 5 + { + /* When using the cooperative scheduler the timer 2 ISR is only + required to increment the RTOS tick count. */ + + xTaskIncrementTick(); + portCLEAR_INTERRUPT_FLAG(); + } +#endif +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +uint8_t ucOriginalSFRPage; + +/* Constants calculated to give the required timer capture values. */ +const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR; +const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ; +const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime; +const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff ); +const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 ); + + /* NOTE: This uses a timer only present on 8052 architecture. */ + + /* Remember the current SFR page so we can restore it at the end of the + function. */ + ucOriginalSFRPage = SFRPAGE; + SFRPAGE = 0; + + /* TMR2CF can be left in its default state. */ + TMR2CF = ( uint8_t ) 0; + + /* Setup the overflow reload value. */ + RCAP2L = ucLowCaptureByte; + RCAP2H = ucHighCaptureByte; + + /* The initial load is performed manually. */ + TMR2L = ucLowCaptureByte; + TMR2H = ucHighCaptureByte; + + /* Enable the timer 2 interrupts. */ + IE |= portTIMER_2_INTERRUPT_ENABLE; + + /* Interrupts are disabled when this is called so the timer can be started + here. */ + TMR2CN = portENABLE_TIMER; + + /* Restore the original SFR page. */ + SFRPAGE = ucOriginalSFRPage; +} + + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/SDCC/Cygnal/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/SDCC/Cygnal/portmacro.h new file mode 100644 index 0000000..e71f0fd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/SDCC/Cygnal/portmacro.h @@ -0,0 +1,116 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#if configUSE_PREEMPTION == 0 + void vTimer2ISR( void ) interrupt 5; +#else + void vTimer2ISR( void ) interrupt 5 _naked; +#endif + +void vSerialISR( void ) interrupt 4; + + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE float +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portENTER_CRITICAL() _asm \ + push ACC \ + push IE \ + _endasm; \ + EA = 0; + +#define portEXIT_CRITICAL() _asm \ + pop ACC \ + _endasm; \ + ACC &= 0x80; \ + IE |= ACC; \ + _asm \ + pop ACC \ + _endasm; + +#define portDISABLE_INTERRUPTS() EA = 0; +#define portENABLE_INTERRUPTS() EA = 1; +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portSTACK_GROWTH ( 1 ) +#define portTICK_PERIOD_MS ( ( uint32_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +void vPortYield( void ) _naked; +#define portYIELD() vPortYield(); +/*-----------------------------------------------------------*/ + +#define portNOP() _asm \ + nop \ + _endasm; + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB91460/__STD_LIB_sbrk.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB91460/__STD_LIB_sbrk.c new file mode 100644 index 0000000..235c544 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB91460/__STD_LIB_sbrk.c @@ -0,0 +1,55 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*--------------------------------------------------------------------------- + __STD_LIB_sbrk.C + - Used by heap_3.c for memory accocation and deletion. + +/*---------------------------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include + + static long brk_siz = 0; + typedef int _heep_t; + #define ROUNDUP(s) (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1)) + static _heep_t _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)]; + #define _heep_size ROUNDUP(configTOTAL_HEAP_SIZE) + + extern char *sbrk(int size) + { + if (brk_siz + size > _heep_size || brk_siz + size < 0) + + return((char*)-1); + brk_siz += size; + return( (char*)_heep + brk_siz - size); + } diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB91460/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB91460/port.c new file mode 100644 index 0000000..1f5b136 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB91460/port.c @@ -0,0 +1,322 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "mb91467d.h" + +/*-----------------------------------------------------------*/ + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +#pragma asm +#macro SaveContext + ORCCR #0x20 ;Switch to user stack + ST RP,@-R15 ;Store RP + STM0 (R7,R6,R5,R4,R3,R2,R1,R0) ;Store R7-R0 + STM1 (R14,R13,R12,R11,R10,R9,R8) ;Store R14-R8 + ST MDH, @-R15 ;Store MDH + ST MDL, @-R15 ;Store MDL + + ANDCCR #0xDF ;Switch back to system stack + LD @R15+,R0 ;Store PC to R0 + ORCCR #0x20 ;Switch to user stack + ST R0,@-R15 ;Store PC to User stack + + ANDCCR #0xDF ;Switch back to system stack + LD @R15+,R0 ;Store PS to R0 + ORCCR #0x20 ;Switch to user stack + ST R0,@-R15 ;Store PS to User stack + + LDI #_pxCurrentTCB, R0 ;Get pxCurrentTCB address + LD @R0, R0 ;Get the pxCurrentTCB->pxTopOfStack address + ST R15,@R0 ;Store USP to pxCurrentTCB->pxTopOfStack + + ANDCCR #0xDF ;Switch back to system stack for the rest of tick ISR +#endm + +#macro RestoreContext + LDI #_pxCurrentTCB, R0 ;Get pxCurrentTCB address + LD @R0, R0 ;Get the pxCurrentTCB->pxTopOfStack address + ORCCR #0x20 ;Switch to user stack + LD @R0, R15 ;Restore USP from pxCurrentTCB->pxTopOfStack + + LD @R15+,R0 ;Store PS to R0 + ANDCCR #0xDF ;Switch to system stack + ST R0,@-R15 ;Store PS to system stack + + ORCCR #0x20 ;Switch to user stack + LD @R15+,R0 ;Store PC to R0 + ANDCCR #0xDF ;Switch to system stack + ST R0,@-R15 ;Store PC to system stack + + ORCCR #0x20 ;Switch back to retrieve the remaining context + + LD @R15+, MDL ;Restore MDL + LD @R15+, MDH ;Restore MDH + LDM1 (R14,R13,R12,R11,R10,R9,R8) ;Restore R14-R8 + LDM0 (R7,R6,R5,R4,R3,R2,R1,R0) ;Restore R7-R0 + LD @R15+, RP ;Restore RP + + ANDCCR #0xDF ;Switch back to system stack for the rest of tick ISR +#endm +#pragma endasm + +/*-----------------------------------------------------------*/ + +/* + * Perform hardware setup to enable ticks from timer 1, + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11111111; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + + /* This is a redundant push to the stack, it may be required if + in some implementations of the compiler the parameter to the task + is passed on to the stack rather than in R4 register. */ + *pxTopOfStack = (StackType_t)(pvParameters); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x00000000; /* RP */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00007777; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00006666; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00005555; /* R5 */ + pxTopOfStack--; + + /* In the current implementation of the compiler the first + parameter to the task (or function) is passed via R4 parameter + to the task, hence the pvParameters pointer is copied into the R4 + register. See compiler manual section 4.6.2 for more information. */ + *pxTopOfStack = ( StackType_t ) (pvParameters); /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00003333; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00002222; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00001111; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00000001; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0000EEEE; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0000DDDD; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0000CCCC; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0000BBBB; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0000AAAA; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00009999; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00008888; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11110000; /* MDH */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22220000; /* MDL */ + pxTopOfStack--; + + /* The start of the task code. */ + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + + /* PS - User Mode, USP, ILM=31, Interrupts enabled */ + *pxTopOfStack = ( StackType_t ) 0x001F0030; /* PS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + #pragma asm + RestoreContext + #pragma endasm + + /* Simulate a function call end as generated by the compiler. We will now + jump to the start of the task the context of which we have just restored. */ + __asm(" reti "); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented - unlikely to ever be required as there is nothing to + return to. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +/* The peripheral clock divided by 32 is used by the timer. */ +const uint16_t usReloadValue = ( uint16_t ) ( ( ( configPER_CLOCK_HZ / configTICK_RATE_HZ ) / 32UL ) - 1UL ); + + /* Setup RLT0 to generate a tick interrupt. */ + + TMCSR0_CNTE = 0; /* Count Disable */ + TMCSR0_CSL = 0x2; /* CLKP/32 */ + TMCSR0_MOD = 0; /* Software trigger */ + TMCSR0_RELD = 1; /* Reload */ + + TMCSR0_UF = 0; /* Clear underflow flag */ + TMRLR0 = usReloadValue; + TMCSR0_INTE = 1; /* Interrupt Enable */ + TMCSR0_CNTE = 1; /* Count Enable */ + TMCSR0_TRG = 1; /* Trigger */ + + PORTEN = 0x3; /* Port Enable */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. The tick count is incremented + * after the context is saved. Then the context is switched if required, + * and last the context of the task which is to be resumed is restored. + */ + + #pragma asm + + .global _ReloadTimer0_IRQHandler + _ReloadTimer0_IRQHandler: + + ANDCCR #0xEF ;Disable Interrupts + SaveContext ;Save context + ORCCR #0x10 ;Re-enable Interrupts + + LDI #0xFFFB,R1 + LDI #_tmcsr0, R0 + AND R1,@R0 ;Clear RLT0 interrupt flag + + CALL32 _xTaskIncrementTick,R12 ;Increment Tick + CALL32 _vTaskSwitchContext,R12 ;Switch context if required + + ANDCCR #0xEF ;Disable Interrupts + RestoreContext ;Restore context + ORCCR #0x10 ;Re-enable Interrupts + + RETI + + #pragma endasm + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + __interrupt void ReloadTimer0_IRQHandler( void ) + { + /* Clear RLT0 interrupt flag */ + TMCSR0_UF = 0; + xTaskIncrementTick(); + } + +#endif + +/* + * Manual context switch. We can use a __nosavereg attribute as the context + * would be saved by PortSAVE_CONTEXT(). The context is switched and then + * the context of the new task is restored saved. + */ +#pragma asm + + .global _vPortYieldDelayed + _vPortYieldDelayed: + + ANDCCR #0xEF ;Disable Interrupts + SaveContext ;Save context + ORCCR #0x10 ;Re-enable Interrupts + + LDI #_dicr, R0 + BANDL #0x0E, @R0 ;Clear Delayed interrupt flag + + CALL32 _vTaskSwitchContext,R12 ;Switch context if required + + ANDCCR #0xEF ;Disable Interrupts + RestoreContext ;Restore context + ORCCR #0x10 ;Re-enable Interrupts + + RETI + +#pragma endasm +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. We can use a __nosavereg attribute as the context + * would be saved by PortSAVE_CONTEXT(). The context is switched and then + * the context of the new task is restored saved. + */ +#pragma asm + + .global _vPortYield + _vPortYield: + + SaveContext ;Save context + CALL32 _vTaskSwitchContext,R12 ;Switch context if required + RestoreContext ;Restore context + + RETI + +#pragma endasm +/*-----------------------------------------------------------*/ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB91460/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB91460/portmacro.h new file mode 100644 index 0000000..df7cb64 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB91460/portmacro.h @@ -0,0 +1,110 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* Hardware specific includes. */ +#include "mb91467d.h" + +/* Standard includes. */ +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#if configKERNEL_INTERRUPT_PRIORITY != 30 + #error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - 30 (1Eh) being the default. +#endif +#define portDISABLE_INTERRUPTS() __asm(" STILM #1Eh ") +#define portENABLE_INTERRUPTS() __asm(" STILM #1Fh ") + +#define portENTER_CRITICAL() \ + __asm(" ST PS,@-R15 "); \ + __asm(" ANDCCR #0xef "); \ + + +#define portEXIT_CRITICAL() \ + __asm(" LD @R15+,PS "); \ + +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() __asm( " nop " ); +/*-----------------------------------------------------------*/ + +/* portYIELD() uses a SW interrupt */ +#define portYIELD() __asm( " INT #40H " ); + +/* portYIELD_FROM_ISR() uses delayed interrupt */ +#define portYIELD_FROM_ISR() DICR_DLYI = 1 +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE + + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB96340/__STD_LIB_sbrk.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB96340/__STD_LIB_sbrk.c new file mode 100644 index 0000000..235c544 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB96340/__STD_LIB_sbrk.c @@ -0,0 +1,55 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*--------------------------------------------------------------------------- + __STD_LIB_sbrk.C + - Used by heap_3.c for memory accocation and deletion. + +/*---------------------------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include + + static long brk_siz = 0; + typedef int _heep_t; + #define ROUNDUP(s) (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1)) + static _heep_t _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)]; + #define _heep_size ROUNDUP(configTOTAL_HEAP_SIZE) + + extern char *sbrk(int size) + { + if (brk_siz + size > _heep_size || brk_siz + size < 0) + + return((char*)-1); + brk_siz += size; + return( (char*)_heep + brk_siz - size); + } diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB96340/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB96340/port.c new file mode 100644 index 0000000..4bfbb83 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB96340/port.c @@ -0,0 +1,510 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the 16FX port. + *----------------------------------------------------------*/ + +/* + * Get current value of DPR and ADB registers + */ +StackType_t xGet_DPR_ADB_bank( void ); + +/* + * Get current value of DTB and PCB registers + */ +StackType_t xGet_DTB_PCB_bank( void ); + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses RLT0, but + * can be done using any given RLT. + */ +static void prvSetupRLT0Interrupt( void ); + +/*-----------------------------------------------------------*/ + +/* + * We require the address of the pxCurrentTCB variable, but don't want to know + * any details of its type. + */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * Macro to save a task context to the task stack. This macro copies the + * saved context (AH:AL, DPR:ADB, DTB:PCB , PC and PS) from the system + * stack to task stack pointed by user stack pointer ( USP for SMALL and + * MEDIUM memory model amd USB:USP for COMPACT and LARGE memory model ), + * then it pushes the general purpose registers RW0-RW7 on to the task + * stack. Finally the resultant stack pointer value is saved into the + * task control block so it can be retrieved the next time the task + * executes. + */ +#if( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) ) + + #define portSAVE_CONTEXT() \ + { __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ + __asm(" MOVW A, _pxCurrentTCB "); \ + __asm(" MOVW A, SP "); \ + __asm(" SWAPW "); \ + __asm(" MOVW @AL, AH "); \ + __asm(" OR CCR,#H'20 "); \ + } + +/* + * Macro to restore a task context from the task stack. This is effecti- + * vely the reverse of SAVE_CONTEXT(). First the stack pointer value + * (USP for SMALL and MEDIUM memory model amd USB:USP for COMPACT and + * LARGE memory model ) is loaded from the task control block. Next the + * value of all the general purpose registers RW0-RW7 is retrieved. Fina- + * lly it copies of the context ( AH:AL, DPR:ADB, DTB:PCB, PC and PS) of + * the task to be executed upon RETI from user stack to system stack. + */ + + #define portRESTORE_CONTEXT() \ + { __asm(" MOVW A, _pxCurrentTCB "); \ + __asm(" MOVW A, @A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" MOVW SP, A "); \ + __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + } + +#elif( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) ) + + #define portSAVE_CONTEXT() \ + { __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ + __asm(" MOVL A, _pxCurrentTCB "); \ + __asm(" MOVL RL2, A "); \ + __asm(" MOVW A, SP "); \ + __asm(" MOVW @RL2+0, A "); \ + __asm(" MOV A, USB "); \ + __asm(" MOV @RL2+2, A "); \ + } + + #define portRESTORE_CONTEXT() \ + { __asm(" MOVL A, _pxCurrentTCB "); \ + __asm(" MOVL RL2, A "); \ + __asm(" MOVW A, @RL2+0 "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" MOVW SP, A "); \ + __asm(" MOV A, @RL2+2 "); \ + __asm(" MOV USB, A "); \ + __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + } +#endif + +/*-----------------------------------------------------------*/ + +/* + * Functions for obtaining the current value of DPR:ADB, DTB:PCB bank registers + */ + +#pragma asm + + .GLOBAL _xGet_DPR_ADB_bank + .GLOBAL _xGet_DTB_PCB_bank + .SECTION CODE, CODE, ALIGN=1 + +_xGet_DPR_ADB_bank: + + MOV A, DPR + SWAP + MOV A, ADB + ORW A + #if configMEMMODEL == portMEDIUM || configMEMMODEL == portLARGE + RETP + #elif configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT + RET + #endif + + +_xGet_DTB_PCB_bank: + + MOV A, DTB + SWAP + MOV A, PCB + ORW A + #if configMEMMODEL == portMEDIUM || configMEMMODEL == portLARGE + RETP + #elif configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT + RET + #endif + +#pragma endasm +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + + /* Once the task is called the task would push the pointer to the + parameter onto the stack. Hence here the pointer would be copied to the stack + first. When using the COMPACT or LARGE memory model the pointer would be 24 + bits, and when using the SMALL or MEDIUM memory model the pointer would be 16 + bits. */ + #if( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) ) + { + *pxTopOfStack = ( StackType_t ) ( ( uint32_t ) ( pvParameters ) >> 16 ); + pxTopOfStack--; + } + #endif + + *pxTopOfStack = ( StackType_t ) ( pvParameters ); + pxTopOfStack--; + + /* This is redundant push to the stack. This is required in order to introduce + an offset so that the task accesses a parameter correctly that is passed on to + the task stack. */ + #if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) ) + { + *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff ); + pxTopOfStack--; + } + #endif + + /* This is redundant push to the stack. This is required in order to introduce + an offset so the task correctly accesses the parameter passed on the task stack. */ + *pxTopOfStack = ( StackType_t ) ( pxCode ); + pxTopOfStack--; + + /* PS - User Mode, ILM=7, RB=0, Interrupts enabled,USP */ + *pxTopOfStack = 0xE0C0; + pxTopOfStack--; + + /* PC */ + *pxTopOfStack = ( StackType_t ) ( pxCode ); + pxTopOfStack--; + + /* DTB | PCB */ + #if configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT + { + *pxTopOfStack = xGet_DTB_PCB_bank(); + pxTopOfStack--; + } + #endif + + /* DTB | PCB, in case of MEDIUM and LARGE memory models, PCB would be used + along with PC to indicate the start address of the function. */ + #if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) ) + { + *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff ); + pxTopOfStack--; + } + #endif + + /* DPR | ADB */ + *pxTopOfStack = xGet_DPR_ADB_bank(); + pxTopOfStack--; + + /* AL */ + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + + /* AH */ + *pxTopOfStack = ( StackType_t ) 0xAAAA; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( StackType_t ) 0x7777; /* RW7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; /* RW6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; /* RW5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x4444; /* RW4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x3333; /* RW3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x2222; /* RW2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1111; /* RW1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; /* RW0 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvSetupRLT0Interrupt( void ) +{ +/* The peripheral clock divided by 16 is used by the timer. */ +const uint16_t usReloadValue = ( uint16_t ) ( ( ( configCLKP1_CLOCK_HZ / configTICK_RATE_HZ ) / 16UL ) - 1UL ); + + /* set reload value = 34999+1, TICK Interrupt after 10 ms @ 56MHz of CLKP1 */ + TMRLR0 = usReloadValue; + + /* prescaler 1:16, reload, interrupt enable, count enable, trigger */ + TMCSR0 = 0x041B; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupRLT0Interrupt(); + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT(); + + /* Simulate a function call end as generated by the compiler. We will now + jump to the start of the task the context of which we have just restored. */ + __asm(" reti "); + + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented - unlikely to ever be required as there is nothing to + return to. */ +} + +/*-----------------------------------------------------------*/ + +/* + * The interrupt service routine used depends on whether the pre-emptive + * scheduler is being used or not. + */ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a __nosavereg attribute + * as the context is to be saved by the portSAVE_CONTEXT() macro, not the + * compiler generated code. The tick count is incremented after the context + * is saved. + */ + __nosavereg __interrupt void prvRLT0_TICKISR( void ) + { + /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */ + __DI(); + + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Enable interrupts */ + __EI(); + + /* Clear RLT0 interrupt flag */ + TMCSR0_UF = 0; + + /* Increment the tick count then switch to the highest priority task + that is ready to run. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Disable interrupts so that portRESTORE_CONTEXT() is not interrupted */ + __DI(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + + /* Enable interrupts */ + __EI(); + } + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + __interrupt void prvRLT0_TICKISR( void ) + { + /* Clear RLT0 interrupt flag */ + TMCSR0_UF = 0; + + xTaskIncrementTick(); + } + +#endif + +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. We can use a __nosavereg attribute as the context + * is to be saved by the portSAVE_CONTEXT() macro, not the compiler generated + * code. + */ +__nosavereg __interrupt void vPortYield( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +__nosavereg __interrupt void vPortYieldDelayed( void ) +{ + /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */ + __DI(); + + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Enable interrupts */ + __EI(); + + /* Clear delayed interrupt flag */ + __asm (" CLRB 03A4H:0 "); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */ + __DI(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + + /* Enable interrupts */ + __EI(); +} +/*-----------------------------------------------------------*/ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB96340/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB96340/portmacro.h new file mode 100644 index 0000000..4ef510d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Softune/MB96340/portmacro.h @@ -0,0 +1,117 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* Standard includes. */ +#include + +/* Constants denoting the available memory models. These are used within +FreeRTOSConfig.h to set the configMEMMODEL value. */ +#define portSMALL 0 +#define portMEDIUM 1 +#define portCOMPACT 2 +#define portLARGE 3 + + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#if configKERNEL_INTERRUPT_PRIORITY != 6 + #error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - #06H being the default. +#endif +#define portDISABLE_INTERRUPTS() __asm(" MOV ILM, #06h ") +#define portENABLE_INTERRUPTS() __asm(" MOV ILM, #07h ") + +#define portENTER_CRITICAL() \ + { __asm(" PUSHW PS "); \ + portDISABLE_INTERRUPTS(); \ + } + +#define portEXIT_CRITICAL() \ + { __asm(" POPW PS "); \ + } + +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portNOP() __asm( " NOP " ); +/*-----------------------------------------------------------*/ + +/* portYIELD() uses SW interrupt */ +#define portYIELD() __asm( " INT #122 " ); + +/* portYIELD_FROM_ISR() uses delayed interrupt */ +#define portYIELD_FROM_ISR() __asm( " SETB 03A4H:0 " ); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE + + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Tasking/ARM_CM4F/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Tasking/ARM_CM4F/port.c new file mode 100644 index 0000000..35553cf --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Tasking/ARM_CM4F/port.c @@ -0,0 +1,269 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 ) +#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 ) +#define portNVIC_SHPR3_REG ( ( volatile uint32_t * ) 0xe000ed20 ) +#define portNVIC_SYSTICK_CLK 0x00000004 +#define portNVIC_SYSTICK_INT 0x00000002 +#define portNVIC_SYSTICK_ENABLE 0x00000001 +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16 ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24 ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* The priority used by the kernel is assigned to a variable to make access + * from inline assembler easier. */ +const uint32_t ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY; + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +/* + * Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void SysTick_Handler( void ); + +/* + * Functions defined in port_asm.asm. + */ +extern void vPortEnableVFP( void ); +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/* This exists purely to allow the const to be used from within the + * port_asm.asm assembly file. */ +const uint32_t ulMaxSyscallInterruptPriorityConst = configMAX_SYSCALL_INTERRUPT_PRIORITY; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ); + + /* Make PendSV and SysTick the lowest priority interrupts. */ + *( portNVIC_SHPR3_REG ) |= portNVIC_PENDSV_PRI; + *( portNVIC_SHPR3_REG ) |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + /* Set a PendSV to request a context switch. */ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; + + /* Barriers are normally not required but do ensure the code is completely + * within the specified behaviour for the architecture. */ + __DSB(); + __ISB(); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + __DSB(); + __ISB(); + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ( ( *( portNVIC_INT_CTRL ) ) & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) +{ + uint32_t ulDummy; + + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Configure SysTick to interrupt at the requested rate. */ + *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Tasking/ARM_CM4F/port_asm.asm b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Tasking/ARM_CM4F/port_asm.asm new file mode 100644 index 0000000..60d5af6 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Tasking/ARM_CM4F/port_asm.asm @@ -0,0 +1,237 @@ +;/* +; * FreeRTOS Kernel V10.5.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern ulMaxSyscallInterruptPriorityConst + + .global _vector_14 + .global _lc_ref__vector_pp_14 + .global SVC_Handler + .global vPortStartFirstTask + .global vPortEnableVFP + .global ulPortSetInterruptMask + .global vPortClearInterruptMask + +;----------------------------------------------------------- + + .section .text + .thumb + .align 4 +_vector_14: .type func + + mrs r0, psp + isb + + ;Get the location of the current TCB. + ldr.w r3, =pxCurrentTCB + ldr r2, [r3] + + ;Is the task using the FPU context? If so, push high vfp registers. + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + ;Save the core registers. + stmdb r0!, {r4-r11, r14} + + ;Save the new top of stack into the first member of the TCB. + str r0, [r2] + + stmdb sp!, {r0, r3} + ldr.w r0, =ulMaxSyscallInterruptPriorityConst + ldr r0, [r0] + msr basepri, r0 + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + ;The first item in pxCurrentTCB is the task top of stack. + ldr r1, [r3] + ldr r0, [r1] + + ;Pop the core registers. + ldmia r0!, {r4-r11, r14} + + ;Is the task using the FPU context? If so, pop the high vfp registers too. + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + bx r14 + + .size _vector_14, $-_vector_14 + .endsec + +;----------------------------------------------------------- + +; This function is an XMC4000 silicon errata workaround. It will get used when +; the SILICON_BUG_PMC_CM_001 linker macro is defined. + .section .text + .thumb + .align 4 +_lc_ref__vector_pp_14: .type func + + mrs r0, psp + isb + + ;Get the location of the current TCB. + ldr.w r3, =pxCurrentTCB + ldr r2, [r3] + + ;Is the task using the FPU context? If so, push high vfp registers. + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + ;Save the core registers. + stmdb r0!, {r4-r11, r14} + + ;Save the new top of stack into the first member of the TCB. + str r0, [r2] + + stmdb sp!, {r3} + ldr.w r0, =ulMaxSyscallInterruptPriorityConst + ldr r0, [r0] + msr basepri, r0 + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r3} + + ;The first item in pxCurrentTCB is the task top of stack. + ldr r1, [r3] + ldr r0, [r1] + + ;Pop the core registers. + ldmia r0!, {r4-r11, r14} + + ;Is the task using the FPU context? If so, pop the high vfp registers too. + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + push { lr } + pop { pc } ; XMC4000 specific errata workaround. Do not used "bx lr" here. + + .size _lc_ref__vector_pp_14, $-_lc_ref__vector_pp_14 + .endsec + +;----------------------------------------------------------- + + .section .text + .thumb + .align 4 +SVC_Handler: .type func + ;Get the location of the current TCB. + ldr.w r3, =pxCurrentTCB + ldr r1, [r3] + ldr r0, [r1] + ;Pop the core registers. + ldmia r0!, {r4-r11, r14} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 + .size SVC_Handler, $-SVC_Handler + .endsec + +;----------------------------------------------------------- + + .section .text + .thumb + .align 4 +vPortStartFirstTask .type func + ;Use the NVIC offset register to locate the stack. + ldr.w r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + ;Set the msp back to the start of the stack. + msr msp, r0 + ;Call SVC to start the first task. + cpsie i + cpsie f + dsb + isb + svc 0 + .size vPortStartFirstTask, $-vPortStartFirstTask + .endsec + +;----------------------------------------------------------- + + .section .text + .thumb + .align 4 +vPortEnableVFP .type func + ;The FPU enable bits are in the CPACR. + ldr.w r0, =0xE000ED88 + ldr r1, [r0] + + ;Enable CP10 and CP11 coprocessors, then save back. + orr r1, r1, #( 0xf << 20 ) + str r1, [r0] + bx r14 + .size vPortEnableVFP, $-vPortEnableVFP + .endsec + +;----------------------------------------------------------- + + .section .text + .thumb + .align 4 +ulPortSetInterruptMask: + mrs r0, basepri + ldr.w r1, =ulMaxSyscallInterruptPriorityConst + ldr r1, [r1] + msr basepri, r1 + bx r14 + .size ulPortSetInterruptMask, $-ulPortSetInterruptMask + .endsec + +;----------------------------------------------------------- + + .section .text + .thumb + .align 4 +vPortClearInterruptMask: + msr basepri, r0 + bx r14 + .size vPortClearInterruptMask, $-vPortClearInterruptMask + .endsec + +;----------------------------------------------------------- + + .end + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Tasking/ARM_CM4F/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Tasking/ARM_CM4F/portmacro.h new file mode 100644 index 0000000..ac4856a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/Tasking/ARM_CM4F/portmacro.h @@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + extern void vPortYield( void ); + #define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 ) + #define portNVIC_PENDSVSET 0x10000000 + #define portYIELD() vPortYield() + + #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +/* + * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other + * registers. r0 is clobbered. + */ + #define portSET_INTERRUPT_MASK() __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + +/* + * Set basepri back to 0 without effective other registers. + * r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. + */ + #define portCLEAR_INTERRUPT_MASK() __set_BASEPRI( 0 ) + + extern uint32_t ulPortSetInterruptMask( void ); + extern void vPortClearInterruptMask( uint32_t ulNewMask ); + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) + + + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + + #define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK() + #define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK() + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + + #define portNOP() + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/CDK/T-HEAD_CK802/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/CDK/T-HEAD_CK802/port.c new file mode 100644 index 0000000..964ddd9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/CDK/T-HEAD_CK802/port.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +extern void vPortStartTask(void); + +/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This +will be set to 0 prior to the first task being started. */ +portLONG ulCriticalNesting = 0x9999UL; + +/* Used to record one tack want to swtich task after enter critical area, we need know it + * and implement task switch after exit critical area */ +portLONG pendsvflag = 0; + +StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + StackType_t *stk = NULL; + + stk = pxTopOfStack; + + *(--stk) = (uint32_t)pxCode; /* Entry Point */ + *(--stk) = (uint32_t)0xE0000140L; /* PSR */ + *(--stk) = (uint32_t)0xFFFFFFFEL; /* R15 (LR) (init value will cause fault if ever used) */ + *(--stk) = (uint32_t)0x13131313L; /* R13 */ + *(--stk) = (uint32_t)0x12121212L; /* R12 */ + *(--stk) = (uint32_t)0x11111111L; /* R11 */ + *(--stk) = (uint32_t)0x10101010L; /* R10 */ + *(--stk) = (uint32_t)0x09090909L; /* R9 */ + *(--stk) = (uint32_t)0x08080808L; /* R8 */ + *(--stk) = (uint32_t)0x07070707L; /* R7 */ + *(--stk) = (uint32_t)0x06060606L; /* R6 */ + *(--stk) = (uint32_t)0x05050505L; /* R5 */ + *(--stk) = (uint32_t)0x04040404L; /* R4 */ + *(--stk) = (uint32_t)0x03030303L; /* R3 */ + *(--stk) = (uint32_t)0x02020202L; /* R2 */ + *(--stk) = (uint32_t)0x01010101L; /* R1 */ + *(--stk) = (uint32_t)pvParameters; /* R0 : argument */ + + return stk; +} + +BaseType_t xPortStartScheduler( void ) +{ + ulCriticalNesting = 0UL; + + vPortStartTask(); + + return pdFALSE; +} + + +void vPortEndScheduler( void ) +{ + /* Not implemented as there is nothing to return to. */ +} + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting ++; +} + +void vPortExitCritical( void ) +{ + if (ulCriticalNesting == 0) { + while(1); + } + + ulCriticalNesting --; + if (ulCriticalNesting == 0) + { + portENABLE_INTERRUPTS(); + + if (pendsvflag) + { + pendsvflag = 0; + portYIELD(); + } + } +} + +#if configUSE_PREEMPTION == 0 +void xPortSysTickHandler( void ) +{ + portLONG ulDummy; + + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + xTaskIncrementTick(); + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); +} + +#else +void xPortSysTickHandler( void ) +{ + portLONG ulDummy; + + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if (xTaskIncrementTick() != pdFALSE) + { + portYIELD_FROM_ISR(pdTRUE); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); +} +#endif + +void vPortYieldHandler( void ) +{ + uint32_t ulSavedInterruptMask; + + ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + + vTaskSwitchContext(); + + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); +} + +__attribute__((weak)) void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName ) +{ + for(;;); +} + +__attribute__((weak)) void vApplicationMallocFailedHook( void ) +{ + for(;;); +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/CDK/T-HEAD_CK802/portasm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/CDK/T-HEAD_CK802/portasm.S new file mode 100644 index 0000000..7396b50 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/CDK/T-HEAD_CK802/portasm.S @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +//#include + +/******************************************************************** + * Functions: vPortStartTask + * + ********************************************************************/ +.global vPortStartTask +.type vPortStartTask, %function +vPortStartTask: + psrclr ie + lrw r4, pxCurrentTCB + ld.w r4, (r4) // the current task stack pointer is the first member + ld.w sp, (r4) + + ldw r0, (sp, 64) + mtcr r0, epc + ldw r0, (sp, 60) + mtcr r0, epsr + ldw r15, (sp, 56) + ldm r0-r13, (sp) + addi sp, 68 + rte + +/******************************************************************** + * Functions: vPortYield + * + ********************************************************************/ +.global vPortYield +.type vPortYield, %function +vPortYield: + psrclr ee + subi sp, 68 + stm r0-r13, (sp) + stw r15, (sp, 56) + mfcr r0, psr + bseti r0, 8 + stw r0, (sp, 60) + stw r15, (sp, 64) + + lrw r2, pxCurrentTCB + ld.w r3, (r2) + st.w sp, (r3) + + jbsr vTaskSwitchContext + lrw r4, pxCurrentTCB + ld.w r4, (r4) + ld.w sp, (r4) + + ldw r0, (sp, 64) + mtcr r0, epc + ldw r0, (sp, 60) + mtcr r0, epsr + ldw r15, (sp, 56) + ldm r0-r13, (sp) + addi sp, 68 + + rte + +/******************************************************************** + * Functions: NOVIC_IRQ_Default_Handler + * + ********************************************************************/ +.global NOVIC_IRQ_Default_Handler +.type NOVIC_IRQ_Default_Handler, %function +NOVIC_IRQ_Default_Handler: + psrset ee + subi sp, 68 + stm r0-r13, (sp) + stw r15, (sp, 56) + mfcr r0, epsr + stw r0, (sp, 60) + mfcr r0, epc + stw r0, (sp, 64) + + lrw r7, pxCurrentTCB + ldw r7, (r7) + stw sp, (r7) + + lrw sp, g_top_irqstack + + lrw r1, g_irqvector + mfcr r0, psr + lsri r0, 16 + sextb r0 + subi r0, 32 + lsli r0, 2 + add r1, r0 + ldw r1, (r1) + lsri r0, 2 + jsr r1 + + lrw r7, pxCurrentTCB + ldw r7, (r7) + ldw sp, (r7) + + ldw r0, (sp, 64) + mtcr r0, epc + ldw r0, (sp, 60) + mtcr r0, epsr + ldm r0-r13, (sp) + ldw r15, (sp, 56) + addi sp, 68 + rte diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h new file mode 100644 index 0000000..61b652e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include +#include +#include + +extern void vPortYield(void); +#ifdef __cplusplus +class vPortYield; +extern "C" { +#endif + + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; +typedef void (*portvectorfunc)(void); + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif + + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH -1 +#define portMS_PERIOD_TICK 10 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + + +static inline void vPortEnableInterrupt( void ) +{ + __enable_irq(); +} + +static inline void vPortDisableInterrupt( void ) +{ + __disable_irq(); +} + +static inline portLONG GetCurrentPSR (void) +{ + return __get_PSR(); +} + +static inline portLONG SaveLocalPSR (void) +{ + portLONG flags = __get_PSR(); + __disable_irq(); + return flags; +} + +static inline void RestoreLocalPSR (portLONG newMask) +{ + __asm__ __volatile__( + "mtcr %0, psr \n" + : + :"r" (newMask) + :"memory" + ); +} + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern __attribute__((naked)) void cpu_yeild(void); + +#define portDISABLE_INTERRUPTS() vPortDisableInterrupt() +#define portENABLE_INTERRUPTS() vPortEnableInterrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() SaveLocalPSR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(a) RestoreLocalPSR(a) + +#define portNOP() asm("nop") + +extern portLONG ulCriticalNesting; +extern portLONG pendsvflag; + +#define portYIELD() if (ulCriticalNesting == 0) \ + { \ + vPortYield(); \ + } \ + else \ + { \ + pendsvflag = 1; \ + } \ + portNOP();portNOP() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( xSwitchRequired ) do { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + portYIELD(); \ + } \ + }while(0) + +#define portYIELD_FROM_ISR( a ) vTaskSwitchContext() + + + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c new file mode 100644 index 0000000..47f1e60 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c @@ -0,0 +1,52 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * \file + * \brief exception processing for freertos + */ + +/* #include "embARC.h" */ + +#include "arc_freertos_exceptions.h" + +#ifdef __GNU__ + extern void gnu_printf_setup( void ); +#endif + +/** + * \brief freertos related cpu exception initialization, all the interrupts handled by freertos must be not + * fast irqs. If fiq is needed, please install the default firq_exc_entry or your own fast irq entry into + * the specific interrupt exception. + */ +void freertos_exc_init( void ) +{ + #ifdef __GNU__ + gnu_printf_setup(); + #endif +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h new file mode 100644 index 0000000..dafd2c3 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h @@ -0,0 +1,46 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef ARC_FREERTOS_EXCEPTIONS_H +#define ARC_FREERTOS_EXCEPTIONS_H + +/* + * here, all arc cpu exceptions share the same entry, also for all interrupt + * exceptions + */ +extern void exc_entry_cpu( void ); /* cpu exception entry for freertos */ +extern void exc_entry_int( void ); /* int exception entry for freertos */ + +/* task dispatch functions in .s */ +extern void start_r( void ); +extern void start_dispatch(); +extern void dispatch(); + +extern void freertos_exc_init( void ); + +#endif /* ARC_FREERTOS_EXCEPTIONS_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s new file mode 100644 index 0000000..91e21ca --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s @@ -0,0 +1,522 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * \file + * \ingroup OS_FREERTOS + * \brief freertos support for arc processor + * like task dispatcher, interrupt handler + */ +/** @cond OS_FREERTOS_ASM_ARC_SUPPORT */ + +/* + * core-dependent part in assemble language (for arc) + */ +#define __ASSEMBLY__ +#include "arc/arc.h" +#include "arc/arc_asm_common.h" + +/* + * task dispatcher + * + */ + .text + .align 4 + .global dispatch +dispatch: +/* + * the pre-conditions of this routine are task context, CPU is + * locked, dispatch is enabled. + */ + SAVE_NONSCRATCH_REGS /* save callee save registers */ + mov r1, dispatch_r + PUSH r1 /* save return address */ + ld r0, [pxCurrentTCB] + bl dispatcher + +/* return routine when task dispatch happened in task context */ +dispatch_r: + RESTORE_NONSCRATCH_REGS /* recover registers */ + j [blink] + +/* + * start dispatch + */ + .global start_dispatch + .align 4 +start_dispatch: +/* + * this routine is called in the non-task context during the startup of the kernel + * , and all the interrupts are locked. + * + * when the dispatcher is called, the cpu is locked, no nest exception (CPU exception/interrupt). + * In target_initialize, all interrupt priority mask should be cleared, cpu should be + * locked, the interrupts outside the kernel such as fiq can be + * enabled. + */ + clri + mov r0, 0 + st r0, [exc_nest_count] + b dispatcher_0 +/* + * dispatcher + */ +dispatcher: + ld r1, [ulCriticalNesting] + PUSH r1 /* save critical nesting */ + st sp, [r0] /* save stack pointer of current task, r0->pxCurrentTCB */ + jl vTaskSwitchContext /* change the value of pxCurrentTCB */ +/* + * before dispatcher is called, task context | cpu locked | dispatch enabled + * should be satisfied. In this routine, the processor will jump + * into the entry of next to run task + * + * i.e. kernel mode, IRQ disabled, dispatch enabled + */ +dispatcher_0: + ld r1, [pxCurrentTCB] + ld sp, [r1] /* recover task stack */ +#if ARC_FEATURE_STACK_CHECK +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif + jl vPortSetStackCheck +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bset r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif + POP r0 /* get critical nesting */ + st r0, [ulCriticalNesting] + POP r0 /* get return address */ + j [r0] + +/* + * task startup routine + * + */ + .text + .global start_r + .align 4 +start_r: + seti /* unlock cpu */ + mov blink, vPortEndTask /* set return address */ + POP r1 /* get task function body */ + POP r0 /* get task parameters */ + j [r1] + +/****** exceptions and interrupts handing ******/ +/****** entry for exception handling ******/ + .global exc_entry_cpu + .align 4 +exc_entry_cpu: + + EXCEPTION_PROLOGUE + + mov blink, sp + mov r3, sp /* as exception handler's para(p_excinfo) */ + + ld r0, [exc_nest_count] + add r1, r0, 1 + st r1, [exc_nest_count] + brne r0, 0, exc_handler_1 +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +exc_handler_1: + PUSH blink + + lr r0, [AUX_ECR] + lsr r0, r0, 16 + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] + + mov r0, r3 + jl [r2] /* !!!!jump to exception handler where interrupts are not allowed! */ + +/* interrupts are not allowed */ +ret_exc: + POP sp + mov r1, exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] + brne r0, 0, ret_exc_1 /* nest exception case */ + lr r1, [AUX_IRQ_ACT] /* nest interrupt case */ + brne r1, 0, ret_exc_1 + + ld r0, [context_switch_reqflg] + brne r0, 0, ret_exc_2 +ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */ + + EXCEPTION_EPILOGUE + rtie + +/* there is a dispatch request */ +ret_exc_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [context_switch_reqflg] + + ld r0, [pxCurrentTCB] + breq r0, 0, ret_exc_1 + + SAVE_CALLEE_REGS /* save callee save registers */ + + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_AE /* clear exception bit */ + kflag r0 + + mov r1, ret_exc_r /* save return address */ + PUSH r1 + + bl dispatcher /* r0->pxCurrentTCB */ + +ret_exc_r: + /* recover exception status */ + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_AE + kflag r0 + + RESTORE_CALLEE_REGS /* recover registers */ + EXCEPTION_EPILOGUE + rtie + +/****** entry for normal interrupt exception handling ******/ + .global exc_entry_int /* entry for interrupt handling */ + .align 4 +exc_entry_int: +#if ARC_FEATURE_FIRQ == 1 +#if ARC_FEATURE_RGF_NUM_BANKS > 1 + lr r0, [AUX_IRQ_ACT] /* check whether it is P0 interrupt */ + btst r0, 0 + jnz exc_entry_firq +#else + PUSH r10 + lr r10, [AUX_IRQ_ACT] + btst r10, 0 + POP r10 + jnz exc_entry_firq +#endif +#endif + INTERRUPT_PROLOGUE + + mov blink, sp + + clri /* disable interrupt */ + ld r3, [exc_nest_count] + add r2, r3, 1 + st r2, [exc_nest_count] + seti /* enable higher priority interrupt */ + + brne r3, 0, irq_handler_1 +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +#if ARC_FEATURE_STACK_CHECK +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif +irq_handler_1: + PUSH blink + + lr r0, [AUX_IRQ_CAUSE] + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] /* r2 = exc_int_handler_table + irqno *4 */ +/* handle software triggered interrupt */ + lr r3, [AUX_IRQ_HINT] + cmp r3, r0 + bne.d irq_hint_handled + xor r3, r3, r3 + sr r3, [AUX_IRQ_HINT] +irq_hint_handled: + + jl [r2] /* jump to interrupt handler */ +/* no interrupts are allowed from here */ +ret_int: + clri /* disable interrupt */ + + POP sp + mov r1, exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] +/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */ + lr r0, [AUX_IRQ_CAUSE] + sr r0, [AUX_IRQ_SELECT] + lr r3, [AUX_IRQ_PRIORITY] + lr r1, [AUX_IRQ_ACT] + bclr r2, r1, r3 + brne r2, 0, ret_int_1 + + ld r0, [context_switch_reqflg] + brne r0, 0, ret_int_2 +ret_int_1: /* return from non-task context */ + INTERRUPT_EPILOGUE + rtie +/* there is a dispatch request */ +ret_int_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [context_switch_reqflg] + + ld r0, [pxCurrentTCB] + breq r0, 0, ret_int_1 + +/* r1 has old AUX_IRQ_ACT */ + PUSH r1 +/* clear related bits in IRQ_ACT manually to simulate a irq return */ + sr r2, [AUX_IRQ_ACT] + + SAVE_CALLEE_REGS /* save callee save registers */ + mov r1, ret_int_r /* save return address */ + PUSH r1 + + bl dispatcher /* r0->pxCurrentTCB */ + +ret_int_r: + RESTORE_CALLEE_REGS /* recover registers */ + POPAX AUX_IRQ_ACT + INTERRUPT_EPILOGUE + rtie + +#if ARC_FEATURE_FIRQ == 1 + .global exc_entry_firq + .align 4 +exc_entry_firq: +#if ARC_FEATURE_STACK_CHECK && ARC_FEATURE_RGF_NUM_BANKS > 1 +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif + SAVE_FIQ_EXC_REGS + + mov blink, sp + + ld r3, [exc_nest_count] + add r2, r3, 1 + st r2, [exc_nest_count] + + brne r3, 0, firq_handler_1 +#if ARC_FEATURE_STACK_CHECK && ARC_FEATURE_RGF_NUM_BANKS == 1 +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +firq_handler_1: + PUSH blink + + lr r0, [AUX_IRQ_CAUSE] + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] /* r2 = exc_int_handler_table + irqno *4 */ +/* handle software triggered interrupt */ + lr r3, [AUX_IRQ_HINT] + brne r3, r0, firq_hint_handled + xor r3, r3, r3 + sr r3, [AUX_IRQ_HINT] +firq_hint_handled: + + jl [r2] /* jump to interrupt handler */ +/* no interrupts are allowed from here */ +ret_firq: + clri + POP sp + + mov r1, exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] +/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */ + lr r1, [AUX_IRQ_ACT] + bclr r1, r1, 0 + brne r1, 0, ret_firq_1 + + ld r0, [context_switch_reqflg] + brne r0, 0, ret_firq_2 +ret_firq_1: /* return from non-task context */ + RESTORE_FIQ_EXC_REGS + rtie +/* there is a dispatch request */ +ret_firq_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [context_switch_reqflg] + + ld r0, [pxCurrentTCB] + breq r0, 0, ret_firq_1 + +/* reconstruct the interruptted context + * When ARC_FEATURE_RGF_BANKED_REGS >= 16 (16, 32), sp is banked + * so need to restore the fast irq stack. + */ +#if ARC_FEATURE_RGF_BANKED_REGS >= 16 + RESTORE_LP_REGS +#if ARC_FEATURE_CODE_DENSITY + RESTORE_CODE_DENSITY +#endif + RESTORE_R58_R59 +#endif + +/* when BANKED_REGS == 16, r4-r9 wiil be also saved in fast irq stack + * so pop them out + */ +#if ARC_FEATURE_RGF_BANKED_REGS == 16 && !defined(ARC_FEATURE_RF16) + POP r9 + POP r8 + POP r7 + POP r6 + POP r5 + POP r4 +#endif + +/* for other cases, unbanked regs are already in interrupted context's stack, + * so just need to save and pop the banked regs + */ + +/* save the interruptted context */ +#if ARC_FEATURE_RGF_BANKED_REGS > 0 +/* switch back to bank0 */ + lr r0, [AUX_STATUS32] + bic r0, r0, 0x70000 + kflag r0 +#endif + +#if ARC_FEATURE_RGF_BANKED_REGS == 4 +/* r4 - r12, gp, fp, r30, blink already saved */ + PUSH r0 + PUSH r1 + PUSH r2 + PUSH r3 +#elif ARC_FEATURE_RGF_BANKED_REGS == 8 +/* r4 - r9, r0, r11 gp, fp, r30, blink already saved */ + PUSH r0 + PUSH r1 + PUSH r2 + PUSH r3 + PUSH r12 +#elif ARC_FEATURE_RGF_BANKED_REGS >= 16 +/* nothing is saved, */ + SAVE_R0_TO_R12 + + SAVE_R58_R59 + PUSH gp + PUSH fp + PUSH r30 /* general purpose */ + PUSH blink + +#if ARC_FEATURE_CODE_DENSITY + SAVE_CODE_DENSITY +#endif + SAVE_LP_REGS +#endif + PUSH ilink + lr r0, [AUX_STATUS32_P0] + PUSH r0 + lr r0, [AUX_IRQ_ACT] + PUSH r0 + bclr r0, r0, 0 + sr r0, [AUX_IRQ_ACT] + + SAVE_CALLEE_REGS /* save callee save registers */ + + mov r1, ret_firq_r /* save return address */ + PUSH r1 + ld r0, [pxCurrentTCB] + bl dispatcher /* r0->pxCurrentTCB */ + +ret_firq_r: + RESTORE_CALLEE_REGS /* recover registers */ + POPAX AUX_IRQ_ACT + POPAX AUX_STATUS32_P0 + POP ilink + +#if ARC_FEATURE_RGF_NUM_BANKS > 1 +#if ARC_FEATURE_RGF_BANKED_REGS == 4 +/* r4 - r12, gp, fp, r30, blink already saved */ + POP r3 + POP r2 + POP r1 + POP r0 + RESTORE_FIQ_EXC_REGS +#elif ARC_FEATURE_RGF_BANKED_REGS == 8 +/* r4 - r9, gp, fp, r30, blink already saved */ + POP r12 + POP r3 + POP r2 + POP r1 + POP r0 + RESTORE_FIQ_EXC_REGS +#elif ARC_FEATURE_RGF_BANKED_REGS >= 16 + RESTORE_LP_REGS +#if ARC_FEATURE_CODE_DENSITY + RESTORE_CODE_DENSITY +#endif + POP blink + POP r30 + POP fp + POP gp + + RESTORE_R58_R59 + RESTORE_R0_TO_R12 +#endif /* ARC_FEATURE_RGF_BANKED_REGS */ +#else + RESTORE_FIQ_EXC_REGS +#endif /* ARC_FEATURE_RGF_NUM_BANKS */ + rtie +#endif +/** @endcond */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c new file mode 100644 index 0000000..c028b88 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c @@ -0,0 +1,240 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#if defined( __MW__ ) + + #include + #include + #include + + #include "FreeRTOS.h" + + #include "queue.h" + #include "semphr.h" + #include "task.h" + + #include "arc/arc_exception.h" + #include "embARC_toolchain.h" + #include "embARC_debug.h" + + #ifdef ENABLE_FREERTOS_TLS_DEBUG + #define TLS_DEBUG( fmt, ... ) EMBARC_PRINTF( fmt, ## __VA_ARGS__ ) + #else + #define TLS_DEBUG( fmt, ... ) + #endif + +/* + * Runtime routines to execute constructors and + * destructors for task local storage. + */ + extern void __mw_run_tls_dtor(); + extern void __mw_run_tls_ctor(); + + extern uint32_t exc_nest_count; + +/* + * Linker generated symbols to mark .tls section addresses + * first byte .. last byte + */ + extern char _ftls[], _etls[]; + #pragma weak _ftls + #pragma weak _etls + + void executable_requires_tls_section( void ) + { + #if _ARC + for( ; ; ) + { + _flag( 1 ); + _nop(); + _nop(); + _nop(); + _nop(); + _nop(); + } + #endif + } + #pragma off_inline(executable_requires_tls_section); + #pragma alias(executable_requires_tls_section, "executable_requires_.tls_section"); + + static void * init_task_tls( void ) + { + uint32_t len = ( uint32_t ) ( _etls - _ftls ); + void * tls = NULL; + + #if FREERTOS_HEAP_SEL == 3 + #warning "FreeRTOS TLS support is not compatible with heap 3 solution(FREERTOS_HEAP_SEL=3)!" + #warning "You can change FREERTOS_HEAP_SEL in freertos.mk to select other heap solution." + #else + tls = pvPortMalloc( len ); + #endif + + if( tls ) + { + TLS_DEBUG( "Malloc task tls:%dbytes\r\n", len ); + memcpy( tls, _ftls, len ); + __mw_run_tls_ctor(); /* Run constructors */ + } + + return tls; + } + + static void free_task_tls( void * pxTCB ) + { + TaskHandle_t task2free = ( TaskHandle_t ) pxTCB; + + if( task2free != NULL ) + { + void * tls = pvTaskGetThreadLocalStoragePointer( task2free, 0 ); + + if( tls ) + { + TLS_DEBUG( "Free task tls\r\n" ); + __mw_run_tls_dtor(); + vPortFree( tls ); + vTaskSetThreadLocalStoragePointer( task2free, 0, NULL ); + } + } + } + + void task_end_hook( void * pxTCB ) + { + free_task_tls( pxTCB ); + } + + static void * get_isr_tls( void ) + { + /* In an ISR */ + static int first = 1; + + if( _Rarely( first ) ) + { + first = 0; + __mw_run_tls_ctor(); /* Run constructors */ + } + + return ( void * ) _ftls; + } + #pragma off_inline(get_isr_tls) + + static void * get_task_tls( void ) + { + TaskHandle_t cur_task; + + cur_task = xTaskGetCurrentTaskHandle(); + + if( cur_task == NULL ) + { + return get_isr_tls(); + } + + void * tls = pvTaskGetThreadLocalStoragePointer( cur_task, 0 ); + + if( tls == NULL ) + { + tls = init_task_tls(); + + if( tls ) + { + vTaskSetThreadLocalStoragePointer( cur_task, 0, tls ); + } + else + { + tls = get_isr_tls(); + } + } + + return tls; + } + #pragma off_inline(get_task_tls) + + #if _ARC /* for ARC XCALLs need to preserve flags */ + extern void * _Preserve_flags _mwget_tls( void ); + #endif + +/* + * Back end gens calls to find local data for this task + */ + void * _mwget_tls( void ) + { + if( _ftls == ( char * ) 0 ) + { + executable_requires_tls_section(); + } + + if( exc_nest_count > 0 ) /* In ISR */ + { + return get_isr_tls(); + } + else /* In Task */ + { + return get_task_tls(); + } + } + + +/* simple interface of thread safe */ + typedef xSemaphoreHandle _lock_t; + #if configUSE_RECURSIVE_MUTEXES != 1 + #error "configUSE_RECURSIVE_MUTEXES in FreeRTOSConfig.h need to 1" + #endif + + void _mwmutex_create( _lock_t * mutex_ptr ) + { + *mutex_ptr = xSemaphoreCreateRecursiveMutex(); + } + + void _mwmutex_delete( _lock_t * mutex_ptr ) + { + if( ( *mutex_ptr ) != NULL ) + { + vSemaphoreDelete( *mutex_ptr ); + } + } + + void _mwmutex_lock( _lock_t mutex ) + { + if( ( mutex ) != NULL ) + { + while( xSemaphoreTakeRecursive( mutex, portMAX_DELAY ) != pdTRUE ) + { + } + } + } + + void _mwmutex_unlock( _lock_t mutex ) + { + if( ( mutex ) != NULL ) + { + xSemaphoreGiveRecursive( mutex ); + } + } + +#else /* if defined( __MW__ ) */ + +#endif /* __MW__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/port.c new file mode 100644 index 0000000..3dcd881 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/port.c @@ -0,0 +1,301 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Implementation of functions defined in portable.h + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "FreeRTOSConfig.h" + +#include "arc/arc_exception.h" +#include "arc/arc_timer.h" +#include "board.h" + +#include "arc_freertos_exceptions.h" + +volatile unsigned int ulCriticalNesting = 999UL; +volatile unsigned int context_switch_reqflg; /* task context switch request flag in exceptions and interrupts handling */ + +/** + * \var exc_nest_count + * \brief the counter for exc/int processing, =0 no int/exc + * >1 in int/exc processing + * @} + */ +uint32_t exc_nest_count; +/* --------------------------------------------------------------------------*/ + +/** + * @brief kernel tick interrupt handler of freertos + */ +/* ----------------------------------------------------------------------------*/ +static void vKernelTick( void * ptr ) +{ + /* clear timer interrupt */ + arc_timer_int_clear( BOARD_OS_TIMER_ID ); + board_timer_update( configTICK_RATE_HZ ); + + if( xTaskIncrementTick() ) + { + portYIELD_FROM_ISR(); /* need to make task switch */ + } +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief setup freertos kernel tick + */ +/* ----------------------------------------------------------------------------*/ +static void prvSetupTimerInterrupt( void ) +{ + unsigned int cyc = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + int_disable( BOARD_OS_TIMER_INTNO ); /* disable os timer interrupt */ + arc_timer_stop( BOARD_OS_TIMER_ID ); + arc_timer_start( BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc ); + + int_handler_install( BOARD_OS_TIMER_INTNO, ( INT_HANDLER_T ) vKernelTick ); + int_pri_set( BOARD_OS_TIMER_INTNO, INT_PRI_MIN ); + int_enable( BOARD_OS_TIMER_INTNO ); +} + +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in + * the order that the port expects to find them. + * + * For ARC, task context switch is implemented with the help of SWI exception + * It's not efficient but simple. + * + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* function body */ + + /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) start_r; /* dispatch return address */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; + return pxTopOfStack; +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief start the freertos scheduler, go to the first task + * + * @returns + */ +/* ----------------------------------------------------------------------------*/ +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. */ + prvSetupTimerInterrupt(); + start_dispatch(); + + /* Should not get here! */ + return 0; +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief + */ +/* ----------------------------------------------------------------------------*/ +void vPortEndScheduler( void ) +{ +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief generate a task switch request in ISR + */ +/* ----------------------------------------------------------------------------*/ +void vPortYieldFromIsr( void ) +{ + unsigned int status32; + + status32 = cpu_lock_save(); + context_switch_reqflg = true; + cpu_unlock_restore( status32 ); +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief + */ +/* ----------------------------------------------------------------------------*/ +void vPortYield( void ) +{ + unsigned int status32; + + status32 = cpu_lock_save(); + dispatch(); + cpu_unlock_restore( status32 ); +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief + */ +/* ----------------------------------------------------------------------------*/ +void vPortEndTask( void ) +{ + #if ( INCLUDE_vTaskDelete == 1 ) + vTaskDelete( NULL ); /* Delete task itself */ + #endif + + while( 1 ) /* Yield to other task */ + { + vPortYield(); + } +} + +#if ARC_FEATURE_STACK_CHECK + +/* + * !!! Note !!! + * This a trick!!! + * It's a copy from task.c. We need to konw the definition of TCB for the purpose of hardware + * stack check. Pls don't forget to update it when FreeRTOS is updated. + */ + typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */ + { + volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */ + + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ + #endif + + ListItem_t xStateListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */ + ListItem_t xEventListItem; /*< Used to reference a task from an event list. */ + UBaseType_t uxPriority; /*< The priority of the task. 0 is the lowest priority. */ + StackType_t * pxStack; /*< Points to the start of the stack. */ + char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */ + #endif + + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ + UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */ + #endif + + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ + UBaseType_t uxMutexesHeld; + #endif + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + TaskHookFunction_t pxTaskTag; + #endif + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */ + #endif + + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + + /* Allocate a Newlib reent structure that is specific to this task. + * Note Newlib support has been included by popular demand, but is not + * used by the FreeRTOS maintainers themselves. FreeRTOS is not + * responsible for resulting newlib operation. User must be familiar with + * newlib and must provide system-wide implementations of the necessary + * stubs. Be warned that (at the time of writing) the current newlib design + * implements a system-wide malloc() that must be provided with locks. */ + struct _reent xNewLib_reent; + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + volatile uint32_t ulNotifiedValue; + volatile uint8_t ucNotifyState; + #endif + + /* See the comments above the definition of + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */ + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */ + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDelayAborted; + #endif + + #if ( configUSE_POSIX_ERRNO == 1 ) + int iTaskErrno; + #endif + } tskTCB; + + + void vPortSetStackCheck( TaskHandle_t old, + TaskHandle_t new ) + { + if( new != NULL ) + { + #if ARC_FEATURE_SEC_PRESENT + arc_aux_write( AUX_S_KSTACK_BASE, ( uint32_t ) ( new->pxEndOfStack ) ); + arc_aux_write( AUX_S_KSTACK_TOP, ( uint32_t ) ( new->pxStack ) ); + #else + arc_aux_write( AUX_KSTACK_BASE, ( uint32_t ) ( new->pxEndOfStack ) ); + arc_aux_write( AUX_KSTACK_TOP, ( uint32_t ) ( new->pxStack ) ); + #endif + } + } +#endif /* if ARC_FEATURE_STACK_CHECK */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h new file mode 100644 index 0000000..0fd4cc5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h @@ -0,0 +1,158 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* record stack high address for stack check */ +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 1 +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned int +#define portBASE_TYPE portLONG + +#ifndef Asm + #define Asm __asm__ volatile +#endif + +/* + * normal constants + */ +#ifndef NULL + #define NULL 0 /* invalid pointer */ +#endif /* NULL */ + +#ifndef true + #define true 1 /* true */ +#endif /* true */ + +#ifndef false + #define false 0 /* false */ +#endif /* false */ + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef unsigned int TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif + +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() Asm( "nop_s" ); +#define IPM_ENABLE_ALL 1 + +#define portYIELD_FROM_ISR() vPortYieldFromIsr() +#define portYIELD() vPortYield() + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() \ + { \ + Asm( "clri" ); \ + Asm( "" ::: "memory" ); \ + } \ + +#define portENABLE_INTERRUPTS() \ + { \ + Asm( "" ::: "memory" ); \ + Asm( "seti" ); \ + } \ + +extern volatile unsigned int ulCriticalNesting; + +#define portENTER_CRITICAL() \ + { \ + portDISABLE_INTERRUPTS() \ + ulCriticalNesting++; \ + } + + +#define portEXIT_CRITICAL() \ + { \ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) \ + { \ + ulCriticalNesting--; \ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) \ + { \ + portENABLE_INTERRUPTS() \ + } \ + } \ + } + + +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() do {} while( 0 ) /* we use the timer */ +#define portALT_GET_RUN_TIME_COUNTER_VALUE( dest ) ( dest = xTickCount ) + +#if defined( __MW__ ) + extern void task_end_hook( void * pxTCB ); + #define portCLEAN_UP_TCB( pxTCB ) task_end_hook( ( void * ) pxTCB ) +#endif + +void vPortYield( void ); +void vPortYieldFromIsr( void ); + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c new file mode 100644 index 0000000..47f1e60 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c @@ -0,0 +1,52 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * \file + * \brief exception processing for freertos + */ + +/* #include "embARC.h" */ + +#include "arc_freertos_exceptions.h" + +#ifdef __GNU__ + extern void gnu_printf_setup( void ); +#endif + +/** + * \brief freertos related cpu exception initialization, all the interrupts handled by freertos must be not + * fast irqs. If fiq is needed, please install the default firq_exc_entry or your own fast irq entry into + * the specific interrupt exception. + */ +void freertos_exc_init( void ) +{ + #ifdef __GNU__ + gnu_printf_setup(); + #endif +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h new file mode 100644 index 0000000..dafd2c3 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h @@ -0,0 +1,46 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef ARC_FREERTOS_EXCEPTIONS_H +#define ARC_FREERTOS_EXCEPTIONS_H + +/* + * here, all arc cpu exceptions share the same entry, also for all interrupt + * exceptions + */ +extern void exc_entry_cpu( void ); /* cpu exception entry for freertos */ +extern void exc_entry_int( void ); /* int exception entry for freertos */ + +/* task dispatch functions in .s */ +extern void start_r( void ); +extern void start_dispatch(); +extern void dispatch(); + +extern void freertos_exc_init( void ); + +#endif /* ARC_FREERTOS_EXCEPTIONS_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/arc_support.s b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/arc_support.s new file mode 100644 index 0000000..35caae9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/arc_support.s @@ -0,0 +1,322 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * \file + * \ingroup OS_FREERTOS + * \brief freertos support for arc processor + * like task dispatcher, interrupt handler + */ +/** @cond OS_FREERTOS_ASM_ARC_SUPPORT */ + +/* + * core-dependent part in assemble language (for arc) + */ +#define __ASSEMBLY__ +#include "arc/arc.h" +#include "arc/arc_asm_common.h" + +/* + * task dispatcher + * + */ + .text + .align 4 + .global dispatch +dispatch: +/* + * the pre-conditions of this routine are task context, CPU is + * locked, dispatch is enabled. + */ + SAVE_NONSCRATCH_REGS /* save callee save registers */ + mov r1, dispatch_r + PUSH r1 /* save return address */ + ld r0, [pxCurrentTCB] + bl dispatcher + +/* return routine when task dispatch happened in task context */ +dispatch_r: + RESTORE_NONSCRATCH_REGS /* recover registers */ + j [blink] + +/* + * start dispatch + */ + .global start_dispatch + .align 4 +start_dispatch: +/* + * this routine is called in the non-task context during the startup of the kernel + * , and all the interrupts are locked. + * + * when the dispatcher is called, the cpu is locked, no nest exception (CPU exception/interrupt). + * In target_initialize, all interrupt priority mask should be cleared, cpu should be + * locked, the interrupts outside the kernel such as fiq can be + * enabled. + */ + clri + mov r0, 0 + st r0, [exc_nest_count] + b dispatcher_0 +/* + * dispatcher + */ +dispatcher: + ld r1, [ulCriticalNesting] + PUSH r1 /* save critical nesting */ + st sp, [r0] /* save stack pointer of current task, r0->pxCurrentTCB */ + jl vTaskSwitchContext /* change the value of pxCurrentTCB */ +/* + * before dispatcher is called, task context | cpu locked | dispatch enabled + * should be satisfied. In this routine, the processor will jump + * into the entry of next to run task + * + * i.e. kernel mode, IRQ disabled, dispatch enabled + */ +dispatcher_0: + ld r1, [pxCurrentTCB] + ld sp, [r1] /* recover task stack */ +#if ARC_FEATURE_STACK_CHECK + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + flag r0 + jl vPortSetStackCheck + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_SC + flag r0 +#endif + POP r0 /* get critical nesting */ + st r0, [ulCriticalNesting] + POP r0 /* get return address */ + j [r0] + +/* + * task startup routine + * + */ + .text + .global start_r + .align 4 +start_r: + seti /* unlock cpu */ + mov blink, vPortEndTask /* set return address */ + POP r1 /* get task function body */ + POP r0 /* get task parameters */ + j [r1] + +/****** exceptions and interrupts handing ******/ +/****** entry for exception handling ******/ + .global exc_entry_cpu + .align 4 +exc_entry_cpu: + + EXCEPTION_PROLOGUE + + + mov blink, sp + mov r3, sp /* as exception handler's para(p_excinfo) */ + + ld r1, [exc_nest_count] + add r1, r1, 1 + st r1, [exc_nest_count] + brne r1, 0, exc_handler_1 +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +exc_handler_1: + PUSH blink + +/* find the exception cause */ +#if ARC_FEATURE_CORE_700 + lr r0, [AUX_ECR] + lsr r0, r0, 16 + bmsk r0, r0, 7 +#endif + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] + + mov r0, r3 + jl [r2] /* !!!!jump to exception handler where interrupts are not allowed! */ + +/* interrupts are not allowed */ +ret_exc: + POP sp + mov r1, exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] + brne r0, 0, ret_exc_1 /* nested exception case */ + lr r1, [AUX_IRQ_LV12] + brne r1, 0, ret_exc_1 /* nested or pending interrupt case */ + + ld r0, [context_switch_reqflg] + brne r0, 0, ret_exc_2 +ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */ + + EXCEPTION_EPILOGUE +#if ARC_FEATURE_CORE_600 + rtie ilink2 +#else + rtie +#endif + +/* there is a dispatch request */ +ret_exc_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [context_switch_reqflg] + + ld r0, [pxCurrentTCB] + breq r0, 0, ret_exc_1 + + SAVE_CALLEE_REGS /* save callee save registers */ + + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_AE /* clear exception bit */ + flag r0 + + mov r1, ret_exc_r /* save return address */ + PUSH r1 + + bl dispatcher /* r0->pxCurrentTCB */ + +ret_exc_r: + /* recover exception status */ + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_AE + flag r0 + + RESTORE_CALLEE_REGS /* recover registers */ + EXCEPTION_EPILOGUE +#if ARC_FEATURE_CORE_600 + rtie ilink2 +#else + rtie +#endif + +/****** entry for normal interrupt exception handling ******/ + .global exc_entry_int /* entry for interrupt handling */ + .align 4 +exc_entry_int: + + INTERRUPT_PROLOGUE + + mov blink, sp + + /* disable interrupt */ + push r0 + lr r0, [AUX_STATUS32] + push r0 + bclr r0, r0, AUX_STATUS_BIT_E1 + bclr r0, r0, AUX_STATUS_BIT_E2 + flag r0 + ld r3, [exc_nest_count] + add r2, r3, 1 + st r2, [exc_nest_count] + /* enable interrupt */ + pop r0 + flag r0 + pop r0 + + brne r3, 0, irq_handler_1 +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +#if ARC_FEATURE_STACK_CHECK + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + flag r0 +#endif +irq_handler_1: + PUSH blink + +/* critical area */ +#if ARC_FEATURE_CORE_700 + lr r0, [AUX_IRQ_CAUSE1] +#endif + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] /* r2 = exc_int_handler_table + irqno *4 */ +/* handle software triggered interrupt */ + lr r3, [AUX_IRQ_HINT] + cmp r3, r0 + bne.d irq_hint_handled + xor r3, r3, r3 + sr r3, [AUX_IRQ_HINT] +irq_hint_handled: + + jl [r2] /* jump to interrupt handler */ +/* no interrupts are allowed from here */ +ret_int: + clri /* disable interrupt */ + + POP sp + mov r1, exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] +/* if there are multi-bits set in IRQ_LV12, it's still in nest interrupt */ + lr r1, [AUX_IRQ_LV12] + + ld r0, [context_switch_reqflg] + brne r0, 0, ret_int_2 +ret_int_1: /* return from non-task context */ + INTERRUPT_EPILOGUE +#if ARC_FEATURE_CORE_600 +/* TODO: series 600 IRQ6 and IRQ7 uses ilink2 */ + rtie ilink1 +#else + rtie +#endif +/* there is a dispatch request */ +ret_int_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [context_switch_reqflg] + + ld r0, [pxCurrentTCB] + breq r0, 0, ret_int_1 + +/* r1 has old AUX_IRQ_LV12 */ + PUSH r1 +/* clear related bits in IRQ_ACT manually to simulate a irq return */ + + SAVE_CALLEE_REGS /* save callee save registers */ + mov r1, ret_int_r /* save return address */ + PUSH r1 + + bl dispatcher /* r0->pxCurrentTCB */ + +ret_int_r: + RESTORE_CALLEE_REGS /* recover registers */ + POPAX AUX_IRQ_LV12 + INTERRUPT_EPILOGUE +#if ARC_FEATURE_CORE_600 + rtie ilink1 +#else + rtie +#endif + +/** @endcond */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/port.c new file mode 100644 index 0000000..9e952b7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/port.c @@ -0,0 +1,296 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Implementation of functions defined in portable.h + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "FreeRTOSConfig.h" + +#include "arc/arc_exception.h" +#include "arc/arc_timer.h" +#include "board.h" + +#include "arc_freertos_exceptions.h" + +volatile unsigned int ulCriticalNesting = 999UL; +volatile unsigned int context_switch_reqflg; /* task context switch request flag in exceptions and interrupts handling */ + +/** + * \var exc_nest_count + * \brief the counter for exc/int processing, =0 no int/exc + * >1 in int/exc processing + * @} + */ +uint32_t exc_nest_count; +/* --------------------------------------------------------------------------*/ + +/** + * @brief kernel tick interrupt handler of freertos + */ +/* ----------------------------------------------------------------------------*/ +static void vKernelTick( void * ptr ) +{ + /* clear timer interrupt */ + arc_timer_int_clear( BOARD_OS_TIMER_ID ); + board_timer_update( configTICK_RATE_HZ ); + + if( xTaskIncrementTick() ) + { + portYIELD_FROM_ISR(); /* need to make task switch */ + } +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief setup freertos kernel tick + */ +/* ----------------------------------------------------------------------------*/ +static void prvSetupTimerInterrupt( void ) +{ + unsigned int cyc = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + int_disable( BOARD_OS_TIMER_INTNO ); /* disable os timer interrupt */ + arc_timer_stop( BOARD_OS_TIMER_ID ); + arc_timer_start( BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc ); + + int_handler_install( BOARD_OS_TIMER_INTNO, ( INT_HANDLER_T ) vKernelTick ); + int_pri_set( BOARD_OS_TIMER_INTNO, INT_PRI_MIN ); + int_enable( BOARD_OS_TIMER_INTNO ); +} + +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in + * the order that the port expects to find them. + * + * For ARC, task context switch is implemented with the help of SWI exception + * It's not efficient but simple. + * + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* function body */ + + /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) start_r; /* dispatch return address */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; + return pxTopOfStack; +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief start the freertos scheduler, go to the first task + * + * @returns + */ +/* ----------------------------------------------------------------------------*/ +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. */ + prvSetupTimerInterrupt(); + start_dispatch(); + + /* Should not get here! */ + return 0; +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief + */ +/* ----------------------------------------------------------------------------*/ +void vPortEndScheduler( void ) +{ +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief generate a task switch request in ISR + */ +/* ----------------------------------------------------------------------------*/ +void vPortYieldFromIsr( void ) +{ + unsigned int status32; + + status32 = cpu_lock_save(); + context_switch_reqflg = true; + cpu_unlock_restore( status32 ); +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief + */ +/* ----------------------------------------------------------------------------*/ +void vPortYield( void ) +{ + unsigned int status32; + + status32 = cpu_lock_save(); + dispatch(); + cpu_unlock_restore( status32 ); +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief + */ +/* ----------------------------------------------------------------------------*/ +void vPortEndTask( void ) +{ + #if ( INCLUDE_vTaskDelete == 1 ) + vTaskDelete( NULL ); /* Delete task itself */ + #endif + + while( 1 ) /* Yield to other task */ + { + vPortYield(); + } +} + +#if ARC_FEATURE_STACK_CHECK + +/* + * !!! Note !!! + * This a trick!!! + * It's a copy from task.c. We need to konw the definition of TCB for the purpose of hardware + * stack check. Pls don't forget to update it when FreeRTOS is updated. + */ + typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */ + { + volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */ + + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ + #endif + + ListItem_t xStateListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */ + ListItem_t xEventListItem; /*< Used to reference a task from an event list. */ + UBaseType_t uxPriority; /*< The priority of the task. 0 is the lowest priority. */ + StackType_t * pxStack; /*< Points to the start of the stack. */ + char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */ + #endif + + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ + UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */ + #endif + + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ + UBaseType_t uxMutexesHeld; + #endif + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + TaskHookFunction_t pxTaskTag; + #endif + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */ + #endif + + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + + /* Allocate a Newlib reent structure that is specific to this task. + * Note Newlib support has been included by popular demand, but is not + * used by the FreeRTOS maintainers themselves. FreeRTOS is not + * responsible for resulting newlib operation. User must be familiar with + * newlib and must provide system-wide implementations of the necessary + * stubs. Be warned that (at the time of writing) the current newlib design + * implements a system-wide malloc() that must be provided with locks. */ + struct _reent xNewLib_reent; + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + volatile uint32_t ulNotifiedValue; + volatile uint8_t ucNotifyState; + #endif + + /* See the comments above the definition of + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */ + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */ + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDelayAborted; + #endif + + #if ( configUSE_POSIX_ERRNO == 1 ) + int iTaskErrno; + #endif + } tskTCB; + + + void vPortSetStackCheck( TaskHandle_t old, + TaskHandle_t new ) + { + if( new != NULL ) + { + arc_aux_write( AUX_USTACK_BASE, ( uint32_t ) ( new->pxEndOfStack ) ); + arc_aux_write( AUX_USTACK_TOP, ( uint32_t ) ( new->pxStack ) ); + } + } +#endif /* if ARC_FEATURE_STACK_CHECK */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/portmacro.h new file mode 100644 index 0000000..ea0f92c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARC_v1/portmacro.h @@ -0,0 +1,148 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H + #define PORTMACRO_H + #include "embARC.h" + + #ifdef __cplusplus + extern "C" { + #endif + +/* record stack high address for stack check */ + #ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 1 + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE unsigned int + #define portBASE_TYPE portLONG + + #ifndef Asm + #define Asm __asm__ volatile + #endif + +/* + * normal constants + */ + #ifndef NULL + #define NULL 0 /* invalid pointer */ + #endif /* NULL */ + + #ifndef true + #define true 1 /* true */ + #endif /* true */ + + #ifndef false + #define false 0 /* false */ + #endif /* false */ + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef unsigned int TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + #endif + + #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() Asm( "nop_s" ); + #define IPM_ENABLE_ALL 1 + + #define portYIELD_FROM_ISR() vPortYieldFromIsr() + #define portYIELD() vPortYield() + +/* Critical section management. */ + #define portDISABLE_INTERRUPTS() \ + { \ + arc_lock(); \ + } \ + + #define portENABLE_INTERRUPTS() \ + { \ + arc_unlock(); \ + } \ + + extern volatile unsigned int ulCriticalNesting; + + #define portENTER_CRITICAL() \ + { \ + portDISABLE_INTERRUPTS() \ + ulCriticalNesting++; \ + } + + + #define portEXIT_CRITICAL() \ + { \ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) \ + { \ + ulCriticalNesting--; \ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) \ + { \ + portENABLE_INTERRUPTS() \ + } \ + } \ + } + + + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() do {} while( 0 ) /* we use the timer */ + #define portALT_GET_RUN_TIME_COUNTER_VALUE( dest ) ( dest = xTickCount ) + + void vPortYield( void ); + void vPortYieldFromIsr( void ); + + #ifdef __cplusplus +} + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARM_TFM/README.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARM_TFM/README.md new file mode 100644 index 0000000..beb494b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARM_TFM/README.md @@ -0,0 +1,80 @@ +# Target of this port + +This port adds the support that FreeRTOS applications can call the secure +services in Trusted Firmware M(TF-M) through Platform Security Architecture +(PSA) API based on the ARM Cortex-M23, Cortex-M33, Cortex-M55 and Cortex-M85 +platform. + +The Platform Security Architecture (PSA) makes it quicker, easier and cheaper +to design security into a device from the ground up. PSA is made up of four key +stages: analyze, architect, implement, and certify. See [PSA Resource Page](https://developer.arm.com/architectures/security-architectures/platform-security-architecture). + +TF-M is an open source project. It provides a reference implementation of PSA +for Arm M-profile architecture. Please get the details from this [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/about/). + +# Derivation of the source code + +* ```os_wrapper_freertos.c``` + The implementation of APIs which are defined in ```\ns_interface\os_wrapper\mutex.h``` by tf-m-tests + (tag: TF-Mv1.5.0 & TF-Mv1.6.0). The implementation is based on FreeRTOS mutex type semaphore. + +# Usage notes + +To build a project based on this port: +* Step 1: build the secure image. Please follow the **Build the Secure Side** section for details. +* Step 2: build the nonsecure image. Please follow the **Build the Non-Secure Side** for details. + +## Build the Secure Side + +### Get the TF-M source code + +See the [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/) to get the source code. This port is supported by TF-M version **tag: TF-Mv1.5.0** & **tag: TF-Mv1.6.0**. + +### Build TF-M + +Please refer to this [link](https://tf-m-user-guide.trustedfirmware.org/docs/technical_references/instructions/tfm_build_instruction.html) to build the secure side. +_**Note:** ```TFM_NS_MANAGE_NSID``` must be configured as "OFF" when building TF-M_. + +## Build the Non-Secure Side + +Please copy all the files in ```freertos_kernel\portable\GCC\ARM_CM[23|33|55|85]_NTZ``` into the ```freertos_kernel\portable\ThirdParty\GCC\ARM_TFM``` folder before using this port. Note that TrustZone is enabled in this port. The TF-M runs in the Secure Side. + +Please call the API ```tfm_ns_interface_init()``` which is defined in ```\app\tfm_ns_interface.c``` by tf-m-tests +(tag: TF-Mv1.5.0 & TF-Mv1.6.0) at the very beginning of your application. Otherwise, it will always fail when calling a TF-M service in the Nonsecure Side. + +### Configuration in FreeRTOS kernel + +* ```configRUN_FREERTOS_SECURE_ONLY``` +This macro should be configured as 0. In this port, TF-M runs in the Secure Side while FreeRTOS +Kernel runs in the Non-Secure Side. + +* ```configENABLE_FPU``` +The setting of this macro is decided by the setting in Secure Side which is platform-specific. +If the Secure Side enables Non-Secure access to FPU, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0. +Please note that Cortex-M23 does not support FPU. +Please refer to [TF-M documentation](https://tf-m-user-guide.trustedfirmware.org/integration_guide/tfm_fpu_support.html) for FPU usage on the Non-Secure side. + +* ```configENABLE_MVE``` +The setting of this macro is decided by the setting in Secure Side which is platform-specific. +If the Secure Side enables Non-Secure access to MVE, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0. +Please note that only Cortex-M55 and Cortex-M85 support MVE. +Please refer to [TF-M documentation](https://tf-m-user-guide.trustedfirmware.org/integration_guide/tfm_fpu_support.html) for MVE usage on the Non-Secure side. + +* ```configENABLE_TRUSTZONE``` +This macro should be configured as 0 because TF-M doesn't use the secure context management function of FreeRTOS. New secure context management might be introduced when TF-M supports multiple secure context. + + +### Integrate TF-M Non-Secure interface with FreeRTOS project + +To enable calling TF-M services by the Non-Secure Side, the files below should be included in the FreeRTOS project and built together. +* files in ```trusted-firmware-m\build\install\interface\src``` + These files contain the implementation of PSA Functional Developer APIs which can be called by Non-Secure Side directly and PSA Firmware Framework APIs in the IPC model. These files should be taken as part of the Non-Secure source code. +* files in ```trusted-firmware-m\build\install\interface\include``` + These files are the necessary header files to call TF-M services. +* ```trusted-firmware-m\build\install\interface\lib\s_veneers.o``` + This object file contains all the Non-Secure callable functions exported by + TF-M and it should be linked when generating the Non-Secure image. + + + +*Copyright (c) 2020-2022, Arm Limited. All rights reserved.* diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c new file mode 100644 index 0000000..01183fb --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/* + * This file contains the implementation of APIs which are defined in + * os_wrapper/mutex.h by TF-M(tag: TF-Mv1.1). The implementation is based + * on FreeRTOS mutex type semaphore. + */ + +#include "os_wrapper/mutex.h" + +#include "FreeRTOS.h" +#include "semphr.h" +#include "mpu_wrappers.h" + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + /* + * In the static allocation, the RAM is required to hold the semaphore's + * state. + */ + StaticSemaphore_t xSecureMutexBuffer; +#endif + +void * os_wrapper_mutex_create( void ) +{ +SemaphoreHandle_t xMutexHandle = NULL; + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + xMutexHandle = xSemaphoreCreateMutex(); +#elif( configSUPPORT_STATIC_ALLOCATION == 1 ) + xMutexHandle = xSemaphoreCreateMutexStatic( &xSecureMutexBuffer ); +#endif + return ( void * ) xMutexHandle; +} +/*-----------------------------------------------------------*/ + +uint32_t os_wrapper_mutex_acquire( void * handle, uint32_t timeout ) +{ +BaseType_t xRet; + + if( ! handle ) + return OS_WRAPPER_ERROR; + + xRet = xSemaphoreTake( ( SemaphoreHandle_t ) handle, + ( timeout == OS_WRAPPER_WAIT_FOREVER ) ? + portMAX_DELAY : ( TickType_t ) timeout ); + + if( xRet != pdPASS ) + return OS_WRAPPER_ERROR; + else + return OS_WRAPPER_SUCCESS; +} +/*-----------------------------------------------------------*/ + +uint32_t os_wrapper_mutex_release( void * handle ) +{ +BaseType_t xRet; + + if( !handle ) + return OS_WRAPPER_ERROR; + + xRet = xSemaphoreGive( ( SemaphoreHandle_t ) handle ); + + if( xRet != pdPASS ) + return OS_WRAPPER_ERROR; + else + return OS_WRAPPER_SUCCESS; +} +/*-----------------------------------------------------------*/ + +uint32_t os_wrapper_mutex_delete( void * handle ) +{ + vSemaphoreDelete( ( SemaphoreHandle_t ) handle ); + + return OS_WRAPPER_SUCCESS; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ATmega/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ATmega/port.c new file mode 100644 index 0000000..18933e0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ATmega/port.c @@ -0,0 +1,768 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#include + +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the AVR port. + *----------------------------------------------------------*/ + +/* Start tasks with interrupts enabled. */ +#define portFLAGS_INT_ENABLED ( (StackType_t) 0x80 ) + +#if defined( portUSE_WDTO) + #warning "Watchdog Timer used for scheduler." + #define portSCHEDULER_ISR WDT_vect + +#elif defined( portUSE_TIMER0 ) +/* Hardware constants for Timer0. */ + #warning "Timer0 used for scheduler." + #define portSCHEDULER_ISR TIMER0_COMPA_vect + #define portCLEAR_COUNTER_ON_MATCH ( (uint8_t) _BV(WGM01) ) + #define portPRESCALE_1024 ( (uint8_t) (_BV(CS02)|_BV(CS00)) ) + #define portCLOCK_PRESCALER ( (uint32_t) 1024 ) + #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( (uint8_t) _BV(OCIE0A) ) + #define portOCRL OCR0A + #define portTCCRa TCCR0A + #define portTCCRb TCCR0B + #define portTIMSK TIMSK0 + #define portTIFR TIFR0 + +#else + #error "No Timer defined for scheduler" +#endif + +/*-----------------------------------------------------------*/ + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/** + Enable the watchdog timer, configuring it for expire after + (value) timeout (which is a combination of the WDP0 + through WDP3 bits). + + This function is derived from but enables only + the interrupt bit (WDIE), rather than the reset bit (WDE). + + Can't find it documented but the WDT, once enabled, + rolls over and fires a new interrupt each time. + + See also the symbolic constants WDTO_15MS et al. + + Updated to match avr-libc 2.0.0 +*/ + +#if defined( portUSE_WDTO) + +static __inline__ +__attribute__ ((__always_inline__)) +void wdt_interrupt_enable (const uint8_t value) +{ + if (_SFR_IO_REG_P (_WD_CONTROL_REG)) + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "out %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "out %0, %2" "\n\t" + : /* no outputs */ + : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), + "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), + "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | + _BV(WDIF) | _BV(WDIE) | (value & 0x07)) ) + : "r0" + ); + } + else + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "sts %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "sts %0, %2" "\n\t" + : /* no outputs */ + : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), + "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), + "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | + _BV(WDIF) | _BV(WDIE) | (value & 0x07)) ) + : "r0" + ); + } +} +#endif + +/*-----------------------------------------------------------*/ +/** + Enable the watchdog timer, configuring it for expire after + (value) timeout (which is a combination of the WDP0 + through WDP3 bits). + + This function is derived from but enables both + the reset bit (WDE), and the interrupt bit (WDIE). + + This will ensure that if the interrupt is not serviced + before the second timeout, the AVR will reset. + + Servicing the interrupt automatically clears it, + and ensures the AVR does not reset. + + Can't find it documented but the WDT, once enabled, + rolls over and fires a new interrupt each time. + + See also the symbolic constants WDTO_15MS et al. + + Updated to match avr-libc 2.0.0 +*/ + +#if defined( portUSE_WDTO) + +static __inline__ +__attribute__ ((__always_inline__)) +void wdt_interrupt_reset_enable (const uint8_t value) +{ + if (_SFR_IO_REG_P (_WD_CONTROL_REG)) + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "out %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "out %0, %2" "\n\t" + : /* no outputs */ + : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), + "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), + "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | + _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) ) + : "r0" + ); + } + else + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "sts %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "sts %0, %2" "\n\t" + : /* no outputs */ + : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), + "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), + "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | + _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) ) + : "r0" + ); + } +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * Macro to save all the general purpose registers, the save the stack pointer + * into the TCB. + * + * The first thing we do is save the flags then disable interrupts. This is to + * guard our stack against having a context switch interrupt after we have already + * pushed the registers onto the stack - causing the 32 registers to be on the + * stack twice. + * + * r1 is set to zero (__zero_reg__) as the compiler expects it to be thus, however + * some of the math routines make use of R1. + * + * r0 is set to __tmp_reg__ as the compiler expects it to be thus. + * + * #if defined(__AVR_HAVE_RAMPZ__) + * #define __RAMPZ__ 0x3B + * #endif + * + * #if defined(__AVR_3_BYTE_PC__) + * #define __EIND__ 0x3C + * #endif + * + * The interrupts will have been disabled during the call to portSAVE_CONTEXT() + * so we need not worry about reading/writing to the stack pointer. + */ +#if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__) +/* 3-Byte PC Save with RAMPZ */ +#define portSAVE_CONTEXT() \ + __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SREG__ \n\t" \ + "cli \n\t" \ + "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, 0x3B \n\t" \ + "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, 0x3C \n\t" \ + "push __tmp_reg__ \n\t" \ + "push __zero_reg__ \n\t" \ + "clr __zero_reg__ \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in __tmp_reg__, __SP_L__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SP_H__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + ); +#elif defined(__AVR_HAVE_RAMPZ__) +/* 2-Byte PC Save with RAMPZ */ +#define portSAVE_CONTEXT() \ + __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SREG__ \n\t" \ + "cli \n\t" \ + "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, 0x3B \n\t" \ + "push __tmp_reg__ \n\t" \ + "push __zero_reg__ \n\t" \ + "clr __zero_reg__ \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in __tmp_reg__, __SP_L__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SP_H__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + ); +#else +/* 2-Byte PC Save */ +#define portSAVE_CONTEXT() \ + __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SREG__ \n\t" \ + "cli \n\t" \ + "push __tmp_reg__ \n\t" \ + "push __zero_reg__ \n\t" \ + "clr __zero_reg__ \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in __tmp_reg__, __SP_L__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SP_H__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + ); +#endif + +/* + * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during + * the context save so we can write to the stack pointer. + */ +#if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__) +/* 3-Byte PC Restore with RAMPZ */ +#define portRESTORE_CONTEXT() \ + __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop __zero_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out 0x3C, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out 0x3B, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out __SREG__, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + ); +#elif defined(__AVR_HAVE_RAMPZ__) +/* 2-Byte PC Restore with RAMPZ */ +#define portRESTORE_CONTEXT() \ + __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop __zero_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out 0x3B, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out __SREG__, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + ); +#else +/* 2-Byte PC Restore */ +#define portRESTORE_CONTEXT() \ + __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop __zero_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out __SREG__, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + ); +#endif +/*-----------------------------------------------------------*/ + +/* + * Perform hardware setup to enable ticks from relevant Timer. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint16_t usAddress; + /* Simulate how the stack would look after a call to vPortYield() generated by + the compiler. */ + + /* The start of the task code will be popped off the stack last, so place + it on first. */ + usAddress = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + +#if defined(__AVR_3_BYTE_PC__) + /* The AVR ATmega2560/ATmega2561 have 256KBytes of program memory and a 17-bit + * program counter. When a code address is stored on the stack, it takes 3 bytes + * instead of 2 for the other ATmega* chips. + * + * Store 0 as the top byte since we force all task routines to the bottom 128K + * of flash. We do this by using the .lowtext label in the linker script. + * + * In order to do this properly, we would need to get a full 3-byte pointer to + * pxCode. That requires a change to GCC. Not likely to happen any time soon. + */ + *pxTopOfStack = 0; + pxTopOfStack--; +#endif + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + portSAVE_CONTEXT places the flags on the stack immediately after r0 + to ensure the interrupts get disabled as soon as possible, and so ensuring + the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + +#if defined(__AVR_3_BYTE_PC__) + /* If we have an ATmega256x, we are also saving the EIND register. + * We should default to 0. + */ + *pxTopOfStack = ( StackType_t ) 0x00; /* EIND */ + pxTopOfStack--; +#endif + +#if defined(__AVR_HAVE_RAMPZ__) + /* We are saving the RAMPZ register. + * We should default to 0. + */ + *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */ + pxTopOfStack--; +#endif + + /* Now the remaining registers. The compiler expects R1 to be 0. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */ + + /* Leave R2 - R23 untouched */ + pxTopOfStack -= 23; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + + /* Leave register R26 - R31 untouched */ + pxTopOfStack -= 7; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the relevant timer hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT(); + + /* Simulate a function call end as generated by the compiler. We will now + jump to the start of the task the context of which we have just restored. */ + __asm__ __volatile__ ( "ret" ); + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ATmega port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. The first thing we do is save the registers so we + * can use a naked attribute. + */ +void vPortYield( void ) __attribute__ ( ( hot, flatten, naked ) ); +void vPortYield( void ) +{ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); + + __asm__ __volatile__ ( "ret" ); +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch callable from ISRs. The first thing we do is save + * the registers so we can use a naked attribute. + */ +void vPortYieldFromISR(void) __attribute__ ( ( hot, flatten, naked ) ); +void vPortYieldFromISR(void) +{ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); + + __asm__ __volatile__ ( "reti" ); +} +/*-----------------------------------------------------------*/ + +/* + * Context switch function used by the tick. This must be identical to + * vPortYield() from the call to vTaskSwitchContext() onwards. The only + * difference from vPortYield() is the tick count is incremented as the + * call comes from the tick ISR. + */ +void vPortYieldFromTick( void ) __attribute__ ( ( hot, flatten, naked ) ); +void vPortYieldFromTick( void ) +{ + portSAVE_CONTEXT(); + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + portRESTORE_CONTEXT(); + + __asm__ __volatile__ ( "ret" ); +} +/*-----------------------------------------------------------*/ + +#if defined(portUSE_WDTO) +/* + * Setup WDT to generate a tick interrupt. + */ +void prvSetupTimerInterrupt( void ) +{ + /* reset watchdog */ + wdt_reset(); + + /* set up WDT Interrupt (rather than the WDT Reset). */ + wdt_interrupt_enable( portUSE_WDTO ); +} + +#elif defined (portUSE_TIMER0) +/* + * Setup Timer0 compare match A to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ +uint32_t ulCompareMatch; +uint8_t ucLowByte; + + /* Using 8bit Timer0 to generate the tick. Correct fuses must be + selected for the configCPU_CLOCK_HZ clock.*/ + + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* We only have 8 bits so have to scale 1024 to get our required tick rate. */ + ulCompareMatch /= portCLOCK_PRESCALER; + + /* Adjust for correct value. */ + ulCompareMatch -= ( uint32_t ) 1; + + /* Setup compare match value for compare match A. Interrupts are disabled + before this is called so we need not worry here. */ + ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); + portOCRL = ucLowByte; + + /* Setup clock source and compare match behaviour. */ + portTCCRa = portCLEAR_COUNTER_ON_MATCH; + portTCCRb = portPRESCALE_1024; + + + /* Enable the interrupt - this is okay as interrupt are currently globally disabled. */ + ucLowByte = portTIMSK; + ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; + portTIMSK = ucLowByte; +} + +#endif + +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + * + * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler. + * + */ + ISR(portSCHEDULER_ISR, ISR_NAKED) __attribute__ ((hot, flatten)); +/* ISR(portSCHEDULER_ISR, ISR_NAKED ISR_NOBLOCK) __attribute__ ((hot, flatten)); + */ + ISR(portSCHEDULER_ISR) + { + vPortYieldFromTick(); + __asm__ __volatile__ ( "reti" ); + } +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + * + * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler. + */ + ISR(portSCHEDULER_ISR) __attribute__ ((hot, flatten)); +/* ISR(portSCHEDULER_ISR, ISR_NOBLOCK) __attribute__ ((hot, flatten)); + */ + ISR(portSCHEDULER_ISR) + { + xTaskIncrementTick(); + } +#endif + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ATmega/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ATmega/portmacro.h new file mode 100644 index 0000000..7009c5a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ATmega/portmacro.h @@ -0,0 +1,157 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int + +typedef uint8_t StackType_t; +typedef int8_t BaseType_t; +typedef uint8_t UBaseType_t; + +#if configUSE_16_BIT_TICKS == 1 + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + +#define portENTER_CRITICAL() __asm__ __volatile__ ( \ + "in __tmp_reg__, __SREG__" "\n\t" \ + "cli" "\n\t" \ + "push __tmp_reg__" "\n\t" \ + ::: "memory" \ + ) + + +#define portEXIT_CRITICAL() __asm__ __volatile__ ( \ + "pop __tmp_reg__" "\n\t" \ + "out __SREG__, __tmp_reg__" "\n\t" \ + ::: "memory" \ + ) + + +#define portDISABLE_INTERRUPTS() __asm__ __volatile__ ( "cli" ::: "memory") +#define portENABLE_INTERRUPTS() __asm__ __volatile__ ( "sei" ::: "memory") +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + +/* System Tick - Scheduler timer + * Prefer to use the enhanced Watchdog Timer, but also Timer0 is ok. + */ + +#if defined(WDIE) && defined(WDIF) /* If Enhanced WDT with interrupt capability is available */ + +#define portUSE_WDTO WDTO_15MS /* use the Watchdog Timer for xTaskIncrementTick */ + +/* Watchdog period options: WDTO_15MS + WDTO_30MS + WDTO_60MS + WDTO_120MS + WDTO_250MS + WDTO_500MS + WDTO_1S + WDTO_2S +*/ + +#else + +#define portUSE_TIMER0 /* use the 8-bit Timer0 for xTaskIncrementTick */ + +#endif + +#define portSTACK_GROWTH ( -1 ) + +/* Timing for the scheduler. + * Watchdog Timer is 128kHz nominal, + * but 120 kHz at 5V DC and 25 degrees is actually more accurate, + * from data sheet. + */ +#if defined( portUSE_WDTO ) +#define portTICK_PERIOD_MS ( (TickType_t) _BV( portUSE_WDTO + 4 ) ) +#else +#define portTICK_PERIOD_MS ( (TickType_t) 1000 / configTICK_RATE_HZ ) +#endif + +#define portBYTE_ALIGNMENT 1 +#define portNOP() __asm__ __volatile__ ( "nop" ); +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +extern void vPortYield( void ) __attribute__ ( ( naked ) ); +#define portYIELD() vPortYield() + +extern void vPortYieldFromISR( void ) __attribute__ ( ( naked ) ); +#define portYIELD_FROM_ISR() vPortYieldFromISR() +/*-----------------------------------------------------------*/ + +#if defined(__AVR_3_BYTE_PC__) +/* Task function macros as described on the FreeRTOS.org WEB site. */ + +/* Add .lowtext tag from the avr linker script avr6.x for ATmega2560 and ATmega2561 + * to make sure functions are loaded in low memory. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__ ((section (".lowtext"))) +#else +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#endif + +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ATmega/readme.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ATmega/readme.md new file mode 100644 index 0000000..4afb4fe --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/ATmega/readme.md @@ -0,0 +1,86 @@ +

ATmegaxxxx

+ +__Port for generalised Microchip ATmega architecture__ + +

Description

+ +This port provides a basis for supporting all modern ATmega devices using either the Enhanced Watchdog Timer, or Timer0 (an 8-bit Timer generally available across the whole range). + +This initial commit contains the information required to build with System Tick being generated by either the: +- Watchdog Timer, or +- Timer0 - an 8-bit Timer, or +- TimerN - a 16-bit Timer which will be configured by the user. + +Further commits can add support for 16-bit Timers available on many relevant devices. The availability of these 16-bit Timers is somewhat device specific, and these complex and highly configurable Timers are often used to generate phase correct PWM timing (for example) and they would be wasted as a simple System Tick. + +The port also provides support for the 3 byte program counter devices __ATmega2560__ and __ATmega2561__. Specific to these two devices the `EIND` register need to be preserved during a context switch. Also, due to a limitation in GCC, the scheduler needs to reside in the lower 128kB of flash for both of these devices. This is achieved by adding the `.lowtext` section attribute to the function prototype. + +To build generic Microchip (AVR) ATmega support the similarities across the family must be considered, and differences respected. Some comments on the strategy follow. + +

System Tick

+ +The Microchip (AVR) ATmega family has limited Timer and Pin capabilities, and is designed to be used in physical applications, controlling hardware with PWM and recognising level and edge voltage changes. It does this mainly through the use of 16-bit Timers (for generating phase correct PWM by up/down counting), and Pins attached to Interrupts. The 8-bit Timers are also attached to Pins, and they can be used for more simple timing tasks, requiring only a single counting direction. + +The Timers not attached to Pins (and therefore not impacting the application of the device) are some 16-bit Timers (very device dependent, eg Timer3 on 1284p), The RTC Timer, and the Watch Dog Timer. + +The Watch Dog Timer is configured identically across most of the ATmega devices. It comes in two variants. 1. Old style (eg ATmega32) which does not have an Interrupt capability, and hence on these old devices cannot be used as the System Tick. and 2. New style enhanced WDT, which can generate an Interrupt, and is available on every relevant device. + +Using the Watch Dog Timer (WDT) to generate the System Tick does not impact its use as a watch dog. It can be configured to generate a System Tick interrupt, and then one period later to Reset the device if the interrupt is not serviced. + +Configuration and usage of the WDT is covered in `` which was revised in avr-libc 2.0.0. + +Two additional WDT functions are provided in `port.c`, which extend avr-libc functions to enable the WDT Interrupt without enabling Reset `wdt_interrupt_enable()`, and to enable both the Interrupt and the Reset `wdt_interrupt_reset_enable()`. + +

3 Byte PC Devices

+ +The ATtiny, ATmega, ATxmega families can optionally support both 3 byte PC and 3 byte RAM addresses. However, focusing on just the ATmega family only two devices have a large Flash requiring them to use 3 byte PC. These are the __ATmega2560__ and __ATmega2561__. This PR provides support for these two devices in two ways. + + - providing `portSAVE_CONTEXT()` and `portRESTORE_CONTEXT` saving both the __RAMPZ__ and __EIND__ registers. + - providing a `portTASK_FUNCTION_PROTO()` with the linker attribute `.lowtext` which is used to ensure that the scheduler and relevant functions remain in the lower 128kB of Flash. + +For devices which can support __XRAM__ and have the __RAMPZ__ register, this register is also preserved during the context switch. + +

Interrupt Nesting

+ +The ATmega family does not support interrupt nesting, having only one interrupt priority. This means that when the Scheduler is running, interrupts are normally disabled. + +When a very time critical process is running, based on microsecond timing generated by one of the Timers, it is important to re-enable interrupts as early as possible in processing a Yield. Fortunately, this is supported through the use of the `NO_BLOCK` decorator when defining the Interrupt Service Routine. + +The `NO_BLOCK` decorator will enable the global interrupt early in the handling of an ISR (in this case for the Scheduler), and enable interrupts to be nested. Using this method, I've been able to successfully implement an [Audio Synthesiser](https://feilipu.me/2015/06/02/goldilocks-analogue-synthesizer/) with less than 83 microseconds for each cycle, whilst still running the Scheduler to handle display and input. + +Using `NO_BLOCK` is optional, and should only be done if a critical Timer should interrupt the Scheduler. + +

Heap Management

+ +Most users of FreeRTOS will choose to manage their own heap using one of the pre-allocated heap management algorithms, but for those that choose to use `heap_3.c`, the wrappered `malloc()` method, there is an issue that needs to be addressed. + +The avr-libc library assumes that the stack will always be above the heap, and does a check for this when responding to a `malloc()` request. This is not the case when Tasks are running, as their stack is located in the early allocated heap address ranges which will be below free heap memory, and so the `malloc()` request will fail even though heap space is available. + +To avoid this issue causing `pvPort_Malloc()` to failing, the user needs to issue this tuning statement BEFORE they use the heap, or use the `xTaskCreate()` API. + +```c +if( __malloc_heap_end == 0 ) + __malloc_heap_end = (char *)(RAMEND - __malloc_margin); +``` +Unfortunately in the repository there is nowhere sensible to include this statement as it should be included early in the `main()` function. + +For devices which can support __XRAM__ the user will need to tune the location of stack and heap according to their own requirements. + +

Supported Devices

+ +ATmega devices with __ENHANCED WDT__ Interrupt capability - will use WDT. + + - ATmega8U2/16U2/32U2 -> 2kB RAM + - ATmega16U4/32U4 - Arduino Leonardo -> 2.5kB RAM + - ATmega48PB/88PB/168PB/328PB - Arduino Uno -> 2kB RAM + - ATmega164PA/324PA/644PA/1284P - Goldilocks -> __16kB RAM__ + - ATmega324PB -> 2kB RAM + - ATmega640/1280/2560/1281/2561 - Arduino Mega -> __8kB RAM + XRAM__ + +ATmega devices without enhanced __WDT__ Interrupt capability - will use a 8-bit or 16-bit Timer. + + - ATmega8A/16A/32A/64A/128A -> 4kB RAM + - ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P -> 4kB RAM + - ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P -> 4kB RAM + - ATmega808/809/1608/1609/3208/3209/4808/4809 - megaAVR 0-Series -> 6kB RAM + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/FreeRTOS-simulator-for-Linux.url b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/FreeRTOS-simulator-for-Linux.url new file mode 100644 index 0000000..60f7ee8 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/FreeRTOS-simulator-for-Linux.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,11 +[InternetShortcut] +IDList= +URL=https://www.freertos.org/FreeRTOS-simulator-for-Linux.html diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/port.c new file mode 100644 index 0000000..68a9663 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/port.c @@ -0,0 +1,578 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Cambridge Consultants Ltd. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the Posix port. +* +* Each task has a pthread which eases use of standard debuggers +* (allowing backtraces of tasks etc). Threads for tasks that are not +* running are blocked in sigwait(). +* +* Task switch is done by resuming the thread for the next task by +* signaling the condition variable and then waiting on a condition variable +* with the current thread. +* +* The timer interrupt uses SIGALRM and care is taken to ensure that +* the signal handler runs only on the thread for the current task. +* +* Use of part of the standard C library requires care as some +* functions can take pthread mutexes internally which can result in +* deadlocks as the FreeRTOS kernel can switch tasks while they're +* holding a pthread mutex. +* +* stdio (printf() and friends) should be called from a single task +* only or serialized with a FreeRTOS primitive such as a binary +* semaphore or mutex. +*----------------------------------------------------------*/ +#include "portmacro.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "utils/wait_for_event.h" +/*-----------------------------------------------------------*/ + +#define SIG_RESUME SIGUSR1 + +typedef struct THREAD +{ + pthread_t pthread; + pdTASK_CODE pxCode; + void * pvParams; + BaseType_t xDying; + struct event * ev; +} Thread_t; + +/* + * The additional per-thread data is stored at the beginning of the + * task's stack. + */ +static inline Thread_t * prvGetThreadFromTask( TaskHandle_t xTask ) +{ + StackType_t * pxTopOfStack = *( StackType_t ** ) xTask; + + return ( Thread_t * ) ( pxTopOfStack + 1 ); +} + +/*-----------------------------------------------------------*/ + +static pthread_once_t hSigSetupThread = PTHREAD_ONCE_INIT; +static sigset_t xAllSignals; +static sigset_t xSchedulerOriginalSignalMask; +static pthread_t hMainThread = ( pthread_t ) NULL; +static volatile portBASE_TYPE uxCriticalNesting; +/*-----------------------------------------------------------*/ + +static portBASE_TYPE xSchedulerEnd = pdFALSE; +/*-----------------------------------------------------------*/ + +static void prvSetupSignalsAndSchedulerPolicy( void ); +static void prvSetupTimerInterrupt( void ); +static void * prvWaitForStart( void * pvParams ); +static void prvSwitchThread( Thread_t * xThreadToResume, + Thread_t * xThreadToSuspend ); +static void prvSuspendSelf( Thread_t * thread ); +static void prvResumeThread( Thread_t * xThreadId ); +static void vPortSystemTickHandler( int sig ); +static void vPortStartFirstTask( void ); +static void prvPortYieldFromISR( void ); +/*-----------------------------------------------------------*/ + +static void prvFatalError( const char * pcCall, + int iErrno ) +{ + fprintf( stderr, "%s: %s\n", pcCall, strerror( iErrno ) ); + abort(); +} + +/* + * See header file for description. + */ +portSTACK_TYPE * pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, + portSTACK_TYPE * pxEndOfStack, + pdTASK_CODE pxCode, + void * pvParameters ) +{ + Thread_t * thread; + pthread_attr_t xThreadAttributes; + size_t ulStackSize; + int iRet; + + ( void ) pthread_once( &hSigSetupThread, prvSetupSignalsAndSchedulerPolicy ); + + /* + * Store the additional thread data at the start of the stack. + */ + thread = ( Thread_t * ) ( pxTopOfStack + 1 ) - 1; + pxTopOfStack = ( portSTACK_TYPE * ) thread - 1; + ulStackSize = ( pxTopOfStack + 1 - pxEndOfStack ) * sizeof( *pxTopOfStack ); + + thread->pxCode = pxCode; + thread->pvParams = pvParameters; + thread->xDying = pdFALSE; + + pthread_attr_init( &xThreadAttributes ); + pthread_attr_setstack( &xThreadAttributes, pxEndOfStack, ulStackSize ); + + thread->ev = event_create(); + + vPortEnterCritical(); + + iRet = pthread_create( &thread->pthread, &xThreadAttributes, + prvWaitForStart, thread ); + + if( iRet != 0 ) + { + prvFatalError( "pthread_create", iRet ); + } + + vPortExitCritical(); + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortStartFirstTask( void ) +{ + Thread_t * pxFirstThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + + /* Start the first task. */ + prvResumeThread( pxFirstThread ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portBASE_TYPE xPortStartScheduler( void ) +{ + int iSignal; + sigset_t xSignals; + + hMainThread = pthread_self(); + + /* Start the timer that generates the tick ISR(SIGALRM). + * Interrupts are disabled here already. */ + prvSetupTimerInterrupt(); + + /* + * Block SIG_RESUME before starting any tasks so the main thread can sigwait on it. + * To sigwait on an unblocked signal is undefined. + * https://pubs.opengroup.org/onlinepubs/009604499/functions/sigwait.html + */ + sigemptyset( &xSignals ); + sigaddset( &xSignals, SIG_RESUME ); + ( void ) pthread_sigmask( SIG_BLOCK, &xSignals, NULL ); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Wait until signaled by vPortEndScheduler(). */ + while( xSchedulerEnd != pdTRUE ) + { + sigwait( &xSignals, &iSignal ); + } + + /* Cancel the Idle task and free its resources */ + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + vPortCancelThread( xTaskGetIdleTaskHandle() ); + #endif + + #if ( configUSE_TIMERS == 1 ) + /* Cancel the Timer task and free its resources */ + vPortCancelThread( xTimerGetTimerDaemonTaskHandle() ); + #endif /* configUSE_TIMERS */ + + /* Restore original signal mask. */ + ( void ) pthread_sigmask( SIG_SETMASK, &xSchedulerOriginalSignalMask, NULL ); + + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + struct itimerval itimer; + struct sigaction sigtick; + Thread_t * xCurrentThread; + + /* Stop the timer and ignore any pending SIGALRMs that would end + * up running on the main thread when it is resumed. */ + itimer.it_value.tv_sec = 0; + itimer.it_value.tv_usec = 0; + + itimer.it_interval.tv_sec = 0; + itimer.it_interval.tv_usec = 0; + ( void ) setitimer( ITIMER_REAL, &itimer, NULL ); + + sigtick.sa_flags = 0; + sigtick.sa_handler = SIG_IGN; + sigemptyset( &sigtick.sa_mask ); + sigaction( SIGALRM, &sigtick, NULL ); + + /* Signal the scheduler to exit its loop. */ + xSchedulerEnd = pdTRUE; + ( void ) pthread_kill( hMainThread, SIG_RESUME ); + + xCurrentThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + prvSuspendSelf( xCurrentThread ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + if( uxCriticalNesting == 0 ) + { + vPortDisableInterrupts(); + } + + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + + /* If we have reached 0 then re-enable the interrupts. */ + if( uxCriticalNesting == 0 ) + { + vPortEnableInterrupts(); + } +} +/*-----------------------------------------------------------*/ + +static void prvPortYieldFromISR( void ) +{ + Thread_t * xThreadToSuspend; + Thread_t * xThreadToResume; + + xThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + + vTaskSwitchContext(); + + xThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + + prvSwitchThread( xThreadToResume, xThreadToSuspend ); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + vPortEnterCritical(); + + prvPortYieldFromISR(); + + vPortExitCritical(); +} +/*-----------------------------------------------------------*/ + +void vPortDisableInterrupts( void ) +{ + pthread_sigmask( SIG_BLOCK, &xAllSignals, NULL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnableInterrupts( void ) +{ + pthread_sigmask( SIG_UNBLOCK, &xAllSignals, NULL ); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortSetInterruptMask( void ) +{ + /* Interrupts are always disabled inside ISRs (signals + * handlers). */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( portBASE_TYPE xMask ) +{ + ( void ) xMask; +} +/*-----------------------------------------------------------*/ + +static uint64_t prvGetTimeNs( void ) +{ + struct timespec t; + + clock_gettime( CLOCK_MONOTONIC, &t ); + + return t.tv_sec * 1000000000ULL + t.tv_nsec; +} + +static uint64_t prvStartTimeNs; + +/* commented as part of the code below in vPortSystemTickHandler, + * to adjust timing according to full demo requirements */ +/* static uint64_t prvTickCount; */ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void prvSetupTimerInterrupt( void ) +{ + struct itimerval itimer; + int iRet; + + /* Initialise the structure with the current timer information. */ + iRet = getitimer( ITIMER_REAL, &itimer ); + + if( iRet == -1 ) + { + prvFatalError( "getitimer", errno ); + } + + /* Set the interval between timer events. */ + itimer.it_interval.tv_sec = 0; + itimer.it_interval.tv_usec = portTICK_RATE_MICROSECONDS; + + /* Set the current count-down. */ + itimer.it_value.tv_sec = 0; + itimer.it_value.tv_usec = portTICK_RATE_MICROSECONDS; + + /* Set-up the timer interrupt. */ + iRet = setitimer( ITIMER_REAL, &itimer, NULL ); + + if( iRet == -1 ) + { + prvFatalError( "setitimer", errno ); + } + + prvStartTimeNs = prvGetTimeNs(); +} +/*-----------------------------------------------------------*/ + +static void vPortSystemTickHandler( int sig ) +{ + Thread_t * pxThreadToSuspend; + Thread_t * pxThreadToResume; + + ( void ) sig; + +/* uint64_t xExpectedTicks; */ + + uxCriticalNesting++; /* Signals are blocked in this signal handler. */ + + #if ( configUSE_PREEMPTION == 1 ) + pxThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + #endif + + /* Tick Increment, accounting for any lost signals or drift in + * the timer. */ + +/* + * Comment code to adjust timing according to full demo requirements + * xExpectedTicks = (prvGetTimeNs() - prvStartTimeNs) + * / (portTICK_RATE_MICROSECONDS * 1000); + * do { */ + xTaskIncrementTick(); + +/* prvTickCount++; + * } while (prvTickCount < xExpectedTicks); + */ + + #if ( configUSE_PREEMPTION == 1 ) + /* Select Next Task. */ + vTaskSwitchContext(); + + pxThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + + prvSwitchThread( pxThreadToResume, pxThreadToSuspend ); + #endif + + uxCriticalNesting--; +} +/*-----------------------------------------------------------*/ + +void vPortThreadDying( void * pxTaskToDelete, + volatile BaseType_t * pxPendYield ) +{ + Thread_t * pxThread = prvGetThreadFromTask( pxTaskToDelete ); + + ( void ) pxPendYield; + + pxThread->xDying = pdTRUE; +} + +void vPortCancelThread( void * pxTaskToDelete ) +{ + Thread_t * pxThreadToCancel = prvGetThreadFromTask( pxTaskToDelete ); + + /* + * The thread has already been suspended so it can be safely cancelled. + */ + pthread_cancel( pxThreadToCancel->pthread ); + pthread_join( pxThreadToCancel->pthread, NULL ); + event_delete( pxThreadToCancel->ev ); +} +/*-----------------------------------------------------------*/ + +static void * prvWaitForStart( void * pvParams ) +{ + Thread_t * pxThread = pvParams; + + prvSuspendSelf( pxThread ); + + /* Resumed for the first time, unblocks all signals. */ + uxCriticalNesting = 0; + vPortEnableInterrupts(); + + /* Call the task's entry point. */ + pxThread->pxCode( pxThread->pvParams ); + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, so application writers can + * catch the error. */ + configASSERT( pdFALSE ); + + return NULL; +} +/*-----------------------------------------------------------*/ + +static void prvSwitchThread( Thread_t * pxThreadToResume, + Thread_t * pxThreadToSuspend ) +{ + BaseType_t uxSavedCriticalNesting; + + if( pxThreadToSuspend != pxThreadToResume ) + { + /* + * Switch tasks. + * + * The critical section nesting is per-task, so save it on the + * stack of the current (suspending thread), restoring it when + * we switch back to this task. + */ + uxSavedCriticalNesting = uxCriticalNesting; + + prvResumeThread( pxThreadToResume ); + + if( pxThreadToSuspend->xDying == pdTRUE ) + { + pthread_exit( NULL ); + } + + prvSuspendSelf( pxThreadToSuspend ); + + uxCriticalNesting = uxSavedCriticalNesting; + } +} +/*-----------------------------------------------------------*/ + +static void prvSuspendSelf( Thread_t * thread ) +{ + /* + * Suspend this thread by waiting for a pthread_cond_signal event. + * + * A suspended thread must not handle signals (interrupts) so + * all signals must be blocked by calling this from: + * + * - Inside a critical section (vPortEnterCritical() / + * vPortExitCritical()). + * + * - From a signal handler that has all signals masked. + * + * - A thread with all signals blocked with pthread_sigmask(). + */ + event_wait( thread->ev ); +} + +/*-----------------------------------------------------------*/ + +static void prvResumeThread( Thread_t * xThreadId ) +{ + if( pthread_self() != xThreadId->pthread ) + { + event_signal( xThreadId->ev ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupSignalsAndSchedulerPolicy( void ) +{ + struct sigaction sigtick; + int iRet; + + hMainThread = pthread_self(); + + /* Initialise common signal masks. */ + sigfillset( &xAllSignals ); + + /* Don't block SIGINT so this can be used to break into GDB while + * in a critical section. */ + sigdelset( &xAllSignals, SIGINT ); + + /* + * Block all signals in this thread so all new threads + * inherits this mask. + * + * When a thread is resumed for the first time, all signals + * will be unblocked. + */ + ( void ) pthread_sigmask( SIG_SETMASK, + &xAllSignals, + &xSchedulerOriginalSignalMask ); + + sigtick.sa_flags = 0; + sigtick.sa_handler = vPortSystemTickHandler; + sigfillset( &sigtick.sa_mask ); + + iRet = sigaction( SIGALRM, &sigtick, NULL ); + + if( iRet == -1 ) + { + prvFatalError( "sigaction", errno ); + } +} +/*-----------------------------------------------------------*/ + +unsigned long ulPortGetRunTime( void ) +{ + struct tms xTimes; + + times( &xTimes ); + + return ( unsigned long ) xTimes.tms_utime; +} +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/portmacro.h new file mode 100644 index 0000000..04d48f0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/portmacro.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright 2020 Cambridge Consultants Ltd. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned long +#define portBASE_TYPE long +#define portPOINTER_SIZE_TYPE intptr_t + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +typedef unsigned long TickType_t; +#define portMAX_DELAY ( TickType_t ) ULONG_MAX + +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portHAS_STACK_OVERFLOW_CHECKING ( 1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portTICK_RATE_MICROSECONDS ( ( portTickType ) 1000000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +extern void vPortYield( void ); + +#define portYIELD() vPortYield() + +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) vPortYield() +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortDisableInterrupts( void ); +extern void vPortEnableInterrupts( void ); +#define portSET_INTERRUPT_MASK() ( vPortDisableInterrupts() ) +#define portCLEAR_INTERRUPT_MASK() ( vPortEnableInterrupts() ) + +extern portBASE_TYPE xPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( portBASE_TYPE xMask ); + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) +#define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK() +#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +extern void vPortThreadDying( void *pxTaskToDelete, volatile BaseType_t *pxPendYield ); +extern void vPortCancelThread( void *pxTaskToDelete ); +#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortThreadDying( ( pvTaskToDelete ), ( pxPendYield ) ) +#define portCLEAN_UP_TCB( pxTCB ) vPortCancelThread( pxTCB ) +/*-----------------------------------------------------------*/ + +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +/* + * Tasks run in their own pthreads and context switches between them + * are always a full memory barrier. ISRs are emulated as signals + * which also imply a full memory barrier. + * + * Thus, only a compilier barrier is needed to prevent the compiler + * reordering. + */ +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) + +extern unsigned long ulPortGetRunTime( void ); +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() /* no-op */ +#define portGET_RUN_TIME_COUNTER_VALUE() ulPortGetRunTime() + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c new file mode 100644 index 0000000..faa9eff --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c @@ -0,0 +1,104 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include +#include + +#include "wait_for_event.h" + +struct event +{ + pthread_mutex_t mutex; + pthread_cond_t cond; + bool event_triggered; +}; + +struct event * event_create( void ) +{ + struct event * ev = malloc( sizeof( struct event ) ); + + ev->event_triggered = false; + pthread_mutex_init( &ev->mutex, NULL ); + pthread_cond_init( &ev->cond, NULL ); + return ev; +} + +void event_delete( struct event * ev ) +{ + pthread_mutex_destroy( &ev->mutex ); + pthread_cond_destroy( &ev->cond ); + free( ev ); +} + +bool event_wait( struct event * ev ) +{ + pthread_mutex_lock( &ev->mutex ); + + while( ev->event_triggered == false ) + { + pthread_cond_wait( &ev->cond, &ev->mutex ); + } + + ev->event_triggered = false; + pthread_mutex_unlock( &ev->mutex ); + return true; +} +bool event_wait_timed( struct event * ev, + time_t ms ) +{ + struct timespec ts; + int ret = 0; + + clock_gettime( CLOCK_REALTIME, &ts ); + ts.tv_sec += ms / 1000; + ts.tv_nsec += ((ms % 1000) * 1000000); + pthread_mutex_lock( &ev->mutex ); + + while( (ev->event_triggered == false) && (ret == 0) ) + { + ret = pthread_cond_timedwait( &ev->cond, &ev->mutex, &ts ); + + if( ( ret == -1 ) && ( errno == ETIMEDOUT ) ) + { + return false; + } + } + + ev->event_triggered = false; + pthread_mutex_unlock( &ev->mutex ); + return true; +} + +void event_signal( struct event * ev ) +{ + pthread_mutex_lock( &ev->mutex ); + ev->event_triggered = true; + pthread_cond_signal( &ev->cond ); + pthread_mutex_unlock( &ev->mutex ); +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h new file mode 100644 index 0000000..18a0c4a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h @@ -0,0 +1,46 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef _WAIT_FOR_EVENT_H_ +#define _WAIT_FOR_EVENT_H_ + +#include +#include + +struct event; + +struct event * event_create( void ); +void event_delete( struct event * ); +bool event_wait( struct event * ev ); +bool event_wait_timed( struct event * ev, + time_t ms ); +void event_signal( struct event * ev ); + + + +#endif /* ifndef _WAIT_FOR_EVENT_H_ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RISC-V/README-for-info-on-official-MIT-license-port.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RISC-V/README-for-info-on-official-MIT-license-port.txt new file mode 100644 index 0000000..bc15d12 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RISC-V/README-for-info-on-official-MIT-license-port.txt @@ -0,0 +1,6 @@ +The official and MIT licensed FreeRTOS ports for RISC-V are located in the following directories: +\FreeRTOS\Source\portable\GCC\RISC-V +\FreeRTOS\Source\portable\IAR\RISC-V + +Also so https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/.gitignore b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/.gitignore new file mode 100644 index 0000000..35eb919 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/.gitignore @@ -0,0 +1,2 @@ +**/cmake-* +.idea diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/CMakeLists.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/CMakeLists.txt new file mode 100644 index 0000000..c953f75 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/CMakeLists.txt @@ -0,0 +1,51 @@ +cmake_minimum_required(VERSION 3.13) + +if (NOT TARGET _FreeRTOS_kernel_inclusion_marker) + add_library(_FreeRTOS_kernel_inclusion_marker INTERFACE) + + # Pull in PICO SDK (must be before project) + include(pico_sdk_import.cmake) + if (PICO_SDK_VERSION_STRING VERSION_LESS "1.2.0") + message(FATAL_ERROR "Require at least Raspberry Pi Pico SDK version 1.2.0") + endif() + + if (NOT FREERTOS_KERNEL_PATH) + get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/../../../.. REALPATH) + endif () + + message(DEBUG "FREERTOS_KERNEL_PATH is ${FREERTOS_KERNEL_PATH}") + project(FreeRTOS-Kernel C CXX) + + set(CMAKE_C_STANDARD 11) + set(CMAKE_CXX_STANDARD 17) + + pico_is_top_level_project(FREERTOS_KERNEL_TOP_LEVEL_PROJECT) + + # if the SDK has already been initialized, then just add our libraries now - this allows + # this FreeRTOS port to just be added as a sub-directory or include within another project, rather than + # having to include it at the top level before pico_sdk_init() + if (TARGET _pico_sdk_inclusion_marker) + if (PICO_SDK_VERSION_STRING VERSION_LESS "1.3.2") + message(FATAL_ERROR "Require at least Raspberry Pi Pico SDK version 1.3.2 to include FreeRTOS after pico_sdk_init()") + endif() + include(${CMAKE_CURRENT_LIST_DIR}/library.cmake) + else() + # The real work gets done in library.cmake which is called at the end of pico_sdk_init + list(APPEND PICO_SDK_POST_LIST_FILES ${CMAKE_CURRENT_LIST_DIR}/library.cmake) + if (PICO_SDK_VERSION_STRING VERSION_LESS "1.3.2") + # We need to inject the following header file into ALL SDK files (which we do via the config header) + list(APPEND PICO_CONFIG_HEADER_FILES ${CMAKE_CURRENT_LIST_DIR}/include/freertos_sdk_config.h) + endif() + + if (FREERTOS_KERNEL_TOP_LEVEL_PROJECT) + message("FreeRTOS: initialize SDK since we're the top-level") + # Initialize the SDK + pico_sdk_init() + else() + set(FREERTOS_KERNEL_PATH ${FREERTOS_KERNEL_PATH} PARENT_SCOPE) + set(PICO_CONFIG_HEADER_FILES ${PICO_CONFIG_HEADER_FILES} PARENT_SCOPE) + set(PICO_SDK_POST_LIST_FILES ${PICO_SDK_POST_LIST_FILES} PARENT_SCOPE) + endif() + endif() +endif() + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/FreeRTOS_Kernel_import.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/FreeRTOS_Kernel_import.cmake new file mode 100644 index 0000000..1f0bf11 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/FreeRTOS_Kernel_import.cmake @@ -0,0 +1,61 @@ +# This is a copy of /portable/ThirdParty/GCC/RP2040/FREERTOS_KERNEL_import.cmake + +# This can be dropped into an external project to help locate the FreeRTOS kernel +# It should be include()ed prior to project(). Alternatively this file may +# or the CMakeLists.txt in this directory may be included or added via add_subdirectory +# respectively. + +if (DEFINED ENV{FREERTOS_KERNEL_PATH} AND (NOT FREERTOS_KERNEL_PATH)) + set(FREERTOS_KERNEL_PATH $ENV{FREERTOS_KERNEL_PATH}) + message("Using FREERTOS_KERNEL_PATH from environment ('${FREERTOS_KERNEL_PATH}')") +endif () + +set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "portable/ThirdParty/GCC/RP2040") +# undo the above +set(FREERTOS_KERNEL_RP2040_BACK_PATH "../../../..") + +if (NOT FREERTOS_KERNEL_PATH) + # check if we are inside the FreeRTOS kernel tree (i.e. this file has been included directly) + get_filename_component(_ACTUAL_PATH ${CMAKE_CURRENT_LIST_DIR} REALPATH) + get_filename_component(_POSSIBLE_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} REALPATH) + if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH) + get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH) + endif() + if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH) + get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH) + message("Setting FREERTOS_KERNEL_PATH to ${FREERTOS_KERNEL_PATH} based on location of FreeRTOS-Kernel-import.cmake") + elseif (PICO_SDK_PATH AND EXISTS "${PICO_SDK_PATH}/../FreeRTOS-Kernel") + set(FREERTOS_KERNEL_PATH ${PICO_SDK_PATH}/../FreeRTOS-Kernel) + message("Defaulting FREERTOS_KERNEL_PATH as sibling of PICO_SDK_PATH: ${FREERTOS_KERNEL_PATH}") + endif() +endif () + +if (NOT FREERTOS_KERNEL_PATH) + foreach(POSSIBLE_SUFFIX Source FreeRTOS-Kernel FreeRTOS/Source) + # check if FreeRTOS-Kernel exists under directory that included us + set(SEARCH_ROOT ${CMAKE_CURRENT_SOURCE_DIR}) + get_filename_component(_POSSIBLE_PATH ${SEARCH_ROOT}/${POSSIBLE_SUFFIX} REALPATH) + if (EXISTS ${_POSSIBLE_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt) + get_filename_component(FREERTOS_KERNEL_PATH ${_POSSIBLE_PATH} REALPATH) + message("Setting FREERTOS_KERNEL_PATH to '${FREERTOS_KERNEL_PATH}' found relative to enclosing project") + break() + endif() + endforeach() +endif() + +if (NOT FREERTOS_KERNEL_PATH) + message(FATAL_ERROR "FreeRTOS location was not specified. Please set FREERTOS_KERNEL_PATH.") +endif() + +set(FREERTOS_KERNEL_PATH "${FREERTOS_KERNEL_PATH}" CACHE PATH "Path to the FreeRTOS Kernel") + +get_filename_component(FREERTOS_KERNEL_PATH "${FREERTOS_KERNEL_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${FREERTOS_KERNEL_PATH}) + message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' not found") +endif() +if (NOT EXISTS ${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt) + message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' does not contain an RP2040 port here: ${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}") +endif() +set(FREERTOS_KERNEL_PATH ${FREERTOS_KERNEL_PATH} CACHE PATH "Path to the FreeRTOS_KERNEL" FORCE) + +add_subdirectory(${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} FREERTOS_KERNEL) \ No newline at end of file diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/LICENSE.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/LICENSE.md new file mode 100644 index 0000000..62cf255 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/LICENSE.md @@ -0,0 +1,23 @@ +BSD-3-Clause License + +Copyright (c) 2020-2021 Raspberry Pi (Trading) Ltd. + +Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/README.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/README.md new file mode 100644 index 0000000..c50cb4e --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/README.md @@ -0,0 +1,42 @@ +## Overview + +This directory provides a FreeRTOS-Kernel port that can be used with the Raspberry Pi Pico SDK. It supports: + + * Simple CMake INTERFACE libraries, to provide the FreeRTOS-Kernel and also the individual allocator types, without copying code into the user's project. + * Running the FreeRTOS-Kernel and tasks on either core 0 or core 1 + * Use of SDK synchronization primitives (such as mutexes, semaphores, queues from pico_sync) between FreeRTOS tasks and code executing on the other core, or in IRQ handlers. + +Note that a FreeRTOS SMP version of this port is also available in the FreeRTOS-Kernel smp branch, which additionally supports utilizing both RP2040 CPU cores for FreeRTOS tasks simultaneously. + +## Using this port + +You can copy [FreeRTOS-Kernel-import.cmake](FreeRTOS-Kernel-import.cmake) into your project, and +add the following in your `CMakeLists.txt`: + +```cmake +include(FreeRTOS_Kernel_import.cmake) +``` + +This will locate the FreeRTOS kernel if it is a direct sub-module of your project, or if you provide the +`FREERTOS_KERNEL_PATH` variable in your environment or via `-DFREERTOS_KERNEL_PATH=/path/to/FreeRTOS-Kernel` on the CMake command line. + +**NOTE:** If you are using version 1.3.1 or older of the Raspberry Pi Pico SDK then this line must appear before the +`pico_sdk_init()` and will cause FreeRTOS to be included/required in all RP2040 targets in your project. After this SDK +version, you can include the FreeRTOS-Kernel support later in your CMake build (possibly in a subdirectory) and the +FreeRTOS-Kernel support will only apply to those targets which explicitly include FreeRTOS support. + +As an alternative to the `import` statement above, you can just add this directory directly via thw following (with +the same placement restrictions related to the Raspberry Pi Pico SDK version above): + +```cmake +add_subdirectory(path/to/this/directory FreeRTOS-Kernel) +``` + + +## Advanced Configuration + +Some additional `config` options are defined [here](include/rp2040_config.h) which control some low level implementation details. + +## Known Limitations + +- Tickless idle has not currently been tested, and is likely non-functional diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c new file mode 100644 index 0000000..14ec09b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c @@ -0,0 +1,52 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + */ + +#include "FreeRTOS.h" + +void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, + StackType_t **ppxIdleTaskStackBuffer, + uint32_t *pulIdleTaskStackSize ) +{ + /* If the buffers to be provided to the Idle task are declared inside this + function then they must be declared static - otherwise they will be allocated on + the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h new file mode 100644 index 0000000..c1ff6e5 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h @@ -0,0 +1,73 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + */ + +#ifndef FREERTOS_SDK_CONFIG_H +#define FREERTOS_SDK_CONFIG_H + +#ifndef __ASSEMBLER__ + #include "FreeRTOSConfig.h" + #include "rp2040_config.h" + #ifndef PICO_USE_MALLOC_MUTEX + // malloc needs to be made thread safe + #define PICO_USE_MALLOC_MUTEX 1 + #endif /* PICO_USE_MALLOC_MUTEX */ + #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + // increase the amount of time it may reasonably take to wake us up + #ifndef PICO_TIME_SLEEP_OVERHEAD_ADJUST_US + #define PICO_TIME_SLEEP_OVERHEAD_ADJUST_US 150 + #endif + + #define lock_owner_id_t uint32_t + extern uint32_t ulPortLockGetCurrentOwnerId(void); + #define lock_get_caller_owner_id() ulPortLockGetCurrentOwnerId() + #define LOCK_INVALID_OWNER_ID ((uint32_t)-1) + + struct lock_core; + #ifndef lock_internal_spin_unlock_with_wait + extern void vPortLockInternalSpinUnlockWithWait( struct lock_core *pxLock, uint32_t ulSave); + #define lock_internal_spin_unlock_with_wait(lock, save) vPortLockInternalSpinUnlockWithWait(lock, save) + #endif + + #ifndef lock_internal_spin_unlock_with_notify + extern void vPortLockInternalSpinUnlockWithNotify( struct lock_core *pxLock, uint32_t save); + #define lock_internal_spin_unlock_with_notify(lock, save) vPortLockInternalSpinUnlockWithNotify(lock, save); + #endif + + #ifndef lock_internal_spin_unlock_with_best_effort_wait_or_timeout + extern bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core *pxLock, uint32_t ulSave, absolute_time_t uxUntil); + #define lock_internal_spin_unlock_with_best_effort_wait_or_timeout(lock, save, until) \ + xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout(lock, save, until) + #endif + #endif /* configSUPPORT_PICO_SYNC_INTEROP */ + + #if ( configSUPPORT_PICO_TIME_INTEROP == 1 ) + extern void xPortSyncInternalYieldUntilBefore(absolute_time_t t); + #define sync_internal_yield_until_before(t) xPortSyncInternalYieldUntilBefore(t) + #endif /* configSUPPORT_PICO_TIME_INTEROP */ +#endif /* __ASSEMBLER__ */ +#endif \ No newline at end of file diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/include/portmacro.h new file mode 100644 index 0000000..75f444a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/include/portmacro.h @@ -0,0 +1,151 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + + #include "pico.h" +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef int32_t BaseType_t; + typedef uint32_t UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portDONT_DISCARD __attribute__( ( used ) ) + /* We have to use PICO_DIVIDER_DISABLE_INTERRUPTS as the source of truth rathern than our config, + * as our FreeRTOSConfig.h header cannot be included by ASM code - which is what this affects in the SDK */ + #define portUSE_DIVIDER_SAVE_RESTORE !PICO_DIVIDER_DISABLE_INTERRUPTS + #if portUSE_DIVIDER_SAVE_RESTORE + #define portSTACK_LIMIT_PADDING 4 + #endif + +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + extern void vPortYield( void ); + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portYIELD() vPortYield() + #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Exception handlers */ + #if (configUSE_DYNAMIC_EXCEPTION_HANDLERS == 0) + /* We only need to override the SDK's weak functions if we want to replace them at compile time */ + #define vPortSVCHandler isr_svcall + #define xPortPendSVHandler isr_pendsv + #define xPortSysTickHandler isr_systick + #endif + + #define portCHECK_IF_IN_ISR() ({ \ + uint32_t ulIPSR; \ + __asm volatile ("mrs %0, IPSR" : "=r" (ulIPSR)::); \ + ((uint8_t)ulIPSR)>0;}) + +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) ); + extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__( ( naked ) ); + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x ) + + #define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) + + extern void vPortEnableInterrupts(); + #define portENABLE_INTERRUPTS() vPortEnableInterrupts() + + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + + #define portNOP() + + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h new file mode 100644 index 0000000..8c72018 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h @@ -0,0 +1,70 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + */ + +#ifndef RP2040_CONFIG_H +#define RP2040_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1 means set the exception handlers dynamically on cores + * that need them in case the user has set up distinct vector table offsets per core + */ +#ifndef configUSE_DYNAMIC_EXCEPTION_HANDLERS + #if defined( PICO_NO_RAM_VECTOR_TABLE ) && ( PICO_NO_RAM_VECTOR_TABLE == 1 ) + #define configUSE_DYNAMIC_EXCEPTION_HANDLERS 0 + #else + #define configUSE_DYNAMIC_EXCEPTION_HANDLERS 1 + #endif +#endif + +/* configSUPPORT_PICO_SYNC_INTEROP == 1 means that SDK pico_sync + * sem/mutex/queue etc. will work correctly when called from FreeRTOS tasks + */ +#ifndef configSUPPORT_PICO_SYNC_INTEROP + #if LIB_PICO_SYNC + #define configSUPPORT_PICO_SYNC_INTEROP 1 + #endif +#endif + +/* configSUPPORT_PICO_SYNC_INTEROP == 1 means that SDK pico_time + * sleep_ms/sleep_us/sleep_until will work correctly when called from FreeRTOS + * tasks, and will actually block at the FreeRTOS level + */ +#ifndef configSUPPORT_PICO_TIME_INTEROP + #if LIB_PICO_TIME + #define configSUPPORT_PICO_TIME_INTEROP 1 + #endif +#endif + +#ifdef __cplusplus +}; +#endif + +#endif diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/library.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/library.cmake new file mode 100644 index 0000000..902a217 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/library.cmake @@ -0,0 +1,69 @@ +# Copyright (c) 2020 Raspberry Pi (Trading) Ltd. +# +# SPDX-License-Identifier: BSD-3-Clause + +# Called after the Raspberry Pi Pico SDK has been initialized to add our libraries + +add_library(FreeRTOS-Kernel-Core INTERFACE) +target_sources(FreeRTOS-Kernel-Core INTERFACE + ${FREERTOS_KERNEL_PATH}/croutine.c + ${FREERTOS_KERNEL_PATH}/event_groups.c + ${FREERTOS_KERNEL_PATH}/list.c + ${FREERTOS_KERNEL_PATH}/queue.c + ${FREERTOS_KERNEL_PATH}/stream_buffer.c + ${FREERTOS_KERNEL_PATH}/tasks.c + ${FREERTOS_KERNEL_PATH}/timers.c + ) +target_include_directories(FreeRTOS-Kernel-Core INTERFACE ${FREERTOS_KERNEL_PATH}/include) + +if (PICO_SDK_VERSION_STRING VERSION_GREATER_EQUAL "1.3.2") + target_compile_definitions(FreeRTOS-Kernel-Core INTERFACE + PICO_CONFIG_RTOS_ADAPTER_HEADER=${CMAKE_CURRENT_LIST_DIR}/include/freertos_sdk_config.h) +endif() + +add_library(FreeRTOS-Kernel INTERFACE) +target_sources(FreeRTOS-Kernel INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/port.c +) + +target_include_directories(FreeRTOS-Kernel INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/include + ${FREERTOS_CONFIG_FILE_DIRECTORY}) + +target_link_libraries(FreeRTOS-Kernel INTERFACE + FreeRTOS-Kernel-Core + pico_base_headers + hardware_exception) + +target_compile_definitions(FreeRTOS-Kernel INTERFACE + LIB_FREERTOS_KERNEL=1 + FREERTOS_KERNEL_SMP=0 +) + +add_library(FreeRTOS-Kernel-Static INTERFACE) +target_compile_definitions(FreeRTOS-Kernel-Static INTERFACE + configSUPPORT_STATIC_ALLOCATION=1 + ) + +target_sources(FreeRTOS-Kernel-Static INTERFACE ${CMAKE_CURRENT_LIST_DIR}/idle_task_static_memory.c) +target_link_libraries(FreeRTOS-Kernel-Static INTERFACE FreeRTOS-Kernel) + +add_library(FreeRTOS-Kernel-Heap1 INTERFACE) +target_sources(FreeRTOS-Kernel-Heap1 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_1.c) +target_link_libraries(FreeRTOS-Kernel-Heap1 INTERFACE FreeRTOS-Kernel) + +add_library(FreeRTOS-Kernel-Heap2 INTERFACE) +target_sources(FreeRTOS-Kernel-Heap2 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_2.c) +target_link_libraries(FreeRTOS-Kernel-Heap2 INTERFACE FreeRTOS-Kernel) + +add_library(FreeRTOS-Kernel-Heap3 INTERFACE) +target_sources(FreeRTOS-Kernel-Heap3 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_3.c) +target_link_libraries(FreeRTOS-Kernel-Heap3 INTERFACE FreeRTOS-Kernel) + +add_library(FreeRTOS-Kernel-Heap4 INTERFACE) +target_sources(FreeRTOS-Kernel-Heap4 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_4.c) +target_link_libraries(FreeRTOS-Kernel-Heap4 INTERFACE FreeRTOS-Kernel) + +add_library(FreeRTOS-Kernel-Heap5 INTERFACE) +target_sources(FreeRTOS-Kernel-Heap5 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_5.c) +target_link_libraries(FreeRTOS-Kernel-Heap5 INTERFACE FreeRTOS-Kernel) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/pico_sdk_import.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/pico_sdk_import.cmake new file mode 100644 index 0000000..e6c7a66 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/pico_sdk_import.cmake @@ -0,0 +1,66 @@ +# Copyright (c) 2020 Raspberry Pi (Trading) Ltd. +# +# SPDX-License-Identifier: BSD-3-Clause + +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG master + ) + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + FetchContent_Populate(pico_sdk) + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/port.c new file mode 100644 index 0000000..86f2597 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/RP2040/port.c @@ -0,0 +1,876 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*---------------------------------------------------------------------- +* Implementation of functions defined in portable.h for the RP2040 port. +*----------------------------------------------------------------------*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "rp2040_config.h" +#include "hardware/clocks.h" +#include "hardware/exception.h" + +/* + * LIB_PICO_MULTICORE == 1, if we are linked with pico_multicore (note that + * the non SMP FreeRTOS_Kernel is not linked with pico_multicore itself). We + * use this flag to determine if we need multi-core functionality. + */ +#if ( LIB_PICO_MULTICORE == 1) + #include "pico/multicore.h" +#endif /* LIB_PICO_MULTICORE */ + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#ifndef portMISSED_COUNTS_FACTOR + #define portMISSED_COUNTS_FACTOR ( 45UL ) +#endif + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void vPortStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. This is initialized to 0 to allow vPortEnter/ExitCritical + * to be called before the scheduler is started */ +static UBaseType_t uxCriticalNesting; + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + #include "pico/lock_core.h" + #include "hardware/irq.h" + #include "event_groups.h" + #if configSUPPORT_STATIC_ALLOCATION + static StaticEventGroup_t xStaticEventGroup; + #define pEventGroup (&xStaticEventGroup) + #endif /* configSUPPORT_STATIC_ALLOCATION */ + static EventGroupHandle_t xEventGroup; + #if ( LIB_PICO_MULTICORE == 1 ) + static EventBits_t uxCrossCoreEventBits; + static spin_lock_t * pxCrossCoreSpinLock; + #endif /* LIB_PICO_MULTICORE */ + + static spin_lock_t * pxYieldSpinLock; + static uint32_t ulYieldSpinLockSaveValue; +#endif /* configSUPPORT_PICO_SYNC_INTEROP */ + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +#define INVALID_LAUNCH_CORE_NUM 0xffu +static uint8_t ucLaunchCoreNum = INVALID_LAUNCH_CORE_NUM; +#define portIS_FREE_RTOS_CORE() ( ucLaunchCoreNum == get_core_num() ) + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11..R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). */ + panic_unsupported(); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + /* This function is no longer used, but retained for backward + * compatibility. */ +} +/*-----------------------------------------------------------*/ + +void vPortStartFirstTask( void ) +{ + __asm volatile ( + " .syntax unified \n" + " ldr r2, pxCurrentTCBConst1 \n"/* Obtain location of pxCurrentTCB. */ + " ldr r3, [r2] \n" + " ldr r0, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " movs r0, #2 \n"/* Switch to the psp stack. */ + " msr CONTROL, r0 \n" + " isb \n" + " pop {r0-r5} \n"/* Pop the registers that are saved automatically. */ + " mov lr, r5 \n"/* lr is now in r5. */ + " pop {r3} \n"/* Return address is now in r3. */ + " pop {r2} \n"/* Pop and discard XPSR. */ + " cpsie i \n"/* The first task has its context and interrupts can be enabled. */ + " bx r3 \n"/* Finally, jump to the user defined task code. */ + " .align 4 \n" + "pxCurrentTCBConst1: .word pxCurrentTCB\n" + ); +} +/*-----------------------------------------------------------*/ + +#if ( LIB_PICO_MULTICORE == 1 ) && ( configSUPPORT_PICO_SYNC_INTEROP == 1) + static void prvFIFOInterruptHandler() + { + /* We must remove the contents (which we don't care about) + * to clear the IRQ */ + multicore_fifo_drain(); + multicore_fifo_clear_irq(); + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + uint32_t ulSave = spin_lock_blocking( pxCrossCoreSpinLock ); + EventBits_t ulBits = uxCrossCoreEventBits; + uxCrossCoreEventBits &= ~ulBits; + spin_unlock( pxCrossCoreSpinLock, ulSave ); + xEventGroupSetBitsFromISR( xEventGroup, ulBits, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } +#endif + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if (configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1) + exception_set_exclusive_handler( PENDSV_EXCEPTION, xPortPendSVHandler ); + exception_set_exclusive_handler( SYSTICK_EXCEPTION, xPortSysTickHandler ); + exception_set_exclusive_handler( SVCALL_EXCEPTION, vPortSVCHandler ); + #endif + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + ucLaunchCoreNum = get_core_num(); + #if (LIB_PICO_MULTICORE == 1) + #if ( configSUPPORT_PICO_SYNC_INTEROP == 1) + multicore_fifo_clear_irq(); + multicore_fifo_drain(); + uint32_t irq_num = 15 + get_core_num(); + irq_set_priority( irq_num, portMIN_INTERRUPT_PRIORITY ); + irq_set_exclusive_handler( irq_num, prvFIFOInterruptHandler ); + irq_set_enabled( irq_num, 1 ); + #endif + #endif + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimisation does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. */ + panic_unsupported(); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + /* We are not in an ISR, and pxYieldSpinLock is always dealt with and + * cleared interrupts are re-enabled, so should be NULL */ + configASSERT( pxYieldSpinLock == NULL ); + #endif /* configSUPPORT_PICO_SYNC_INTEROP */ + + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is completely + * within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} + +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} + +void vPortEnableInterrupts() { + #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + if( pxYieldSpinLock ) + { + spin_unlock(pxYieldSpinLock, ulYieldSpinLockSaveValue); + pxYieldSpinLock = NULL; + } + #endif + __asm volatile ( " cpsie i " ::: "memory" ); +} + +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMaskFromISR( void ) +{ + __asm volatile ( + " mrs r0, PRIMASK \n" + " cpsid i \n" + " bx lr " + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) +{ + __asm volatile ( + " msr PRIMASK, r0 \n" + " bx lr " + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " .syntax unified \n" + " mrs r0, psp \n" + " \n" + " ldr r3, pxCurrentTCBConst2 \n"/* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " subs r0, r0, #32 \n"/* Make space for the remaining low registers. */ + " str r0, [r2] \n"/* Save the new top of stack. */ + " stmia r0!, {r4-r7} \n"/* Store the low registers that are not saved automatically. */ + " mov r4, r8 \n"/* Store the high registers. */ + " mov r5, r9 \n" + " mov r6, r10 \n" + " mov r7, r11 \n" + " stmia r0!, {r4-r7} \n" + #if portUSE_DIVIDER_SAVE_RESTORE + " movs r2, #0xd \n"/* Store the divider state. */ + " lsls r2, #28 \n" + /* We expect that the divider is ready at this point (which is + * necessary to safely save/restore), because: + * a) if we have not been interrupted since we entered this method, + * then >8 cycles have clearly passed, so the divider is done + * b) if we were interrupted in the interim, then any "safe" - i.e. + * does the right thing in an IRQ - use of the divider should + * have waited for any in-process divide to complete, saved and + * then fully restored the result, thus the result is ready in + * that case too. */ + " ldr r4, [r2, #0x60] \n"/* SIO_DIV_UDIVIDEND_OFFSET */ + " ldr r5, [r2, #0x64] \n"/* SIO_DIV_UDIVISOR_OFFSET */ + " ldr r6, [r2, #0x74] \n"/* SIO_DIV_REMAINDER_OFFSET */ + " ldr r7, [r2, #0x70] \n"/* SIO_DIV_QUOTIENT_OFFSET */ + /* We actually save the divider state in the 4 words below + * our recorded stack pointer, so as not to disrupt the stack + * frame expected by debuggers - this is addressed by + * portEXTRA_STACK_SIZE */ + " subs r0, r0, #48 \n" + " stmia r0!, {r4-r7} \n" + #endif /* portUSE_DIVIDER_SAVE_RESTORE */ + " push {r3, r14} \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " pop {r2, r3} \n"/* lr goes in r3. r2 now holds tcb pointer. */ + " \n" + " ldr r1, [r2] \n" + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, r0, #16 \n"/* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n"/* Pop the high registers. */ + " mov r8, r4 \n" + " mov r9, r5 \n" + " mov r10, r6 \n" + " mov r11, r7 \n" + " \n" + " msr psp, r0 \n"/* Remember the new top of stack for the task. */ + " \n" + #if portUSE_DIVIDER_SAVE_RESTORE + " movs r2, #0xd \n"/* Pop the divider state. */ + " lsls r2, #28 \n" + " subs r0, r0, #48 \n"/* Go back for the divider state */ + " ldmia r0!, {r4-r7} \n"/* Pop the divider state. */ + /* Note always restore via SIO_DIV_UDIVI*, because we will overwrite the + * results stopping the calculation anyway, however the sign of results + * is adjusted by the h/w at read time based on whether the last started + * division was signed and the inputs' signs differed */ + " str r4, [r2, #0x60] \n"/* SIO_DIV_UDIVIDEND_OFFSET */ + " str r5, [r2, #0x64] \n"/* SIO_DIV_UDIVISOR_OFFSET */ + " str r6, [r2, #0x74] \n"/* SIO_DIV_REMAINDER_OFFSET */ + " str r7, [r2, #0x70] \n"/* SIO_DIV_QUOTIENT_OFFSET */ + #else + " subs r0, r0, #32 \n"/* Go back for the low registers that are not automatically restored. */ + #endif /* portUSE_DIVIDER_SAVE_RESTORE */ + " ldmia r0!, {r4-r7} \n"/* Pop low registers. */ + " \n" + " bx r3 \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( clock_get_hz(clk_sys) / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR; + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( clock_get_hz( clk_sys ) / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ + +#if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) || ( configSUPPORT_PICO_TIME_INTEROP == 1 ) + static TickType_t prvGetTicksToWaitBefore( absolute_time_t t ) + { + int64_t xDelay = absolute_time_diff_us(get_absolute_time(), t); + const uint32_t ulTickPeriod = 1000000 / configTICK_RATE_HZ; + xDelay -= ulTickPeriod; + if( xDelay >= ulTickPeriod ) + { + return xDelay / ulTickPeriod; + } + return 0; + } +#endif + +#if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + uint32_t ulPortLockGetCurrentOwnerId() + { + if( portIS_FREE_RTOS_CORE()) + { + uint32_t exception = __get_current_exception(); + if( !exception ) + { + return ( uintptr_t ) xTaskGetCurrentTaskHandle(); + } + /* Note: since ROM as at 0x00000000, these can't be confused with + * valid task handles (pointers) in RAM */ + /* We make all exception handler/core combinations distinct owners */ + return get_core_num() + exception * 2; + } + /* Note: since ROM as at 0x00000000, this can't be confused with + * valid task handles (pointers) in RAM */ + return get_core_num(); + } + + static inline EventBits_t prvGetEventGroupBit( spin_lock_t * spinLock ) + { + uint32_t ulBit; + #if ( configUSE_16_BIT_TICKS == 1 ) + ulBit = 1u << (spin_lock_get_num(spinLock) & 0x7u); + #else + ulBit = 1u << spin_lock_get_num(spinLock); + /* reduce to range 0-24 */ + ulBit |= ulBit << 8u; + ulBit >>= 8u; + #endif /* configUSE_16_BIT_TICKS */ + return ( EventBits_t ) ulBit; + } + + static inline EventBits_t prvGetAllEventGroupBits() + { + #if ( configUSE_16_BIT_TICKS == 1 ) + return (EventBits_t) 0xffu; + #else + return ( EventBits_t ) 0xffffffu; + #endif /* configUSE_16_BIT_TICKS */ + } + + void vPortLockInternalSpinUnlockWithWait( struct lock_core * pxLock, uint32_t ulSave ) + { + configASSERT( !portCHECK_IF_IN_ISR() ); + if( !portIS_FREE_RTOS_CORE() ) + { + spin_unlock(pxLock->spin_lock, ulSave ); + __wfe(); + } + else + { + configASSERT( pxYieldSpinLock == NULL ); + + // we want to hold the lock until the event bits have been set; since interrupts are currently disabled + // by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when + // the scheduler is unlocked during this call + configASSERT(pxLock->spin_lock); + pxYieldSpinLock = pxLock->spin_lock; + ulYieldSpinLockSaveValue = ulSave; + xEventGroupWaitBits( xEventGroup, prvGetEventGroupBit(pxLock->spin_lock), + pdTRUE, pdFALSE, portMAX_DELAY); + } + } + + void vPortLockInternalSpinUnlockWithNotify( struct lock_core *pxLock, uint32_t ulSave ) { + EventBits_t uxBits = prvGetEventGroupBit(pxLock->spin_lock ); + if (portIS_FREE_RTOS_CORE()) { + #if LIB_PICO_MULTICORE + /* signal an event in case a regular core is waiting */ + __sev(); + #endif + spin_unlock(pxLock->spin_lock, ulSave ); + if( !portCHECK_IF_IN_ISR() ) + { + xEventGroupSetBits( xEventGroup, uxBits ); + } + else + { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + xEventGroupSetBitsFromISR( xEventGroup, uxBits, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + } + else + { + __sev(); + #if ( LIB_PICO_MULTICORE == 1) + /* We could sent the bits across the FIFO which would have required us to block here if the FIFO was full, + * or we could have just set all bits on the other side, however it seems reasonable instead to take + * the hit of another spin lock to protect an accurate bit set. */ + if( pxCrossCoreSpinLock != pxLock->spin_lock ) + { + spin_lock_unsafe_blocking(pxCrossCoreSpinLock); + uxCrossCoreEventBits |= uxBits; + spin_unlock_unsafe(pxCrossCoreSpinLock); + } + else + { + uxCrossCoreEventBits |= uxBits; + } + /* This causes fifo irq on the other (FreeRTOS) core which will do the set the event bits */ + sio_hw->fifo_wr = 0; + #endif /* LIB_PICO_MULTICORE */ + spin_unlock(pxLock->spin_lock, ulSave); + } + } + + bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core * pxLock, uint32_t ulSave, absolute_time_t uxUntil ) + { + configASSERT( !portCHECK_IF_IN_ISR() ); + // note no need to check LIB_PICO_MULTICORE, as this is always returns true if that is not defined + if( !portIS_FREE_RTOS_CORE() ) + { + spin_unlock(pxLock->spin_lock, ulSave); + return best_effort_wfe_or_timeout(uxUntil); + } + else + { + configASSERT( pxYieldSpinLock == NULL ); + + TickType_t uxTicksToWait = prvGetTicksToWaitBefore( uxUntil ); + if( uxTicksToWait ) + { + /* We want to hold the lock until the event bits have been set; since interrupts are currently disabled + * by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when + * the scheduler is unlocked during this call */ + configASSERT(pxLock->spin_lock); + pxYieldSpinLock = pxLock->spin_lock; + ulYieldSpinLockSaveValue = ulSave; + xEventGroupWaitBits( xEventGroup, + prvGetEventGroupBit(pxLock->spin_lock), pdTRUE, + pdFALSE, uxTicksToWait ); + /* sanity check that interrupts were disabled, then re-enabled during the call, which will have + * taken care of the yield */ + configASSERT( pxYieldSpinLock == NULL ); + } + else + { + spin_unlock( pxLock->spin_lock, ulSave ); + } + if ( time_reached( uxUntil ) ) + { + return true; + } + else + { + /* We do not want to hog the core */ + portYIELD(); + /* We aren't sure if we've reached the timeout yet; the caller will check */ + return false; + } + } + } + + #if ( configSUPPORT_PICO_SYNC_INTEROP == 1) + /* runs before main */ + static void __attribute__((constructor)) prvRuntimeInitializer( void ) + { + /* This must be done even before the scheduler is started, as the spin lock + * is used by the overrides of the SDK wait/notify primitives */ + #if ( LIB_PICO_MULTICORE == 1 ) + pxCrossCoreSpinLock = spin_lock_instance( next_striped_spin_lock_num() ); + #endif /* portRUNNING_ON_BOTH_CORES */ + + /* The event group is not used prior to scheduler init, but is initialized + * here to since it logically belongs with the spin lock */ + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + xEventGroup = xEventGroupCreateStatic(&xStaticEventGroup); + #else + /* Note that it is slightly dubious calling this here before the scheduler is initialized, + * however the only thing it touches is the allocator which then calls vPortEnterCritical + * and vPortExitCritical, and allocating here saves us checking the one time initialized variable in + * some rather critical code paths */ + xEventGroup = xEventGroupCreate(); + #endif /* configSUPPORT_STATIC_ALLOCATION */ + } + #endif +#endif /* configSUPPORT_PICO_SYNC_INTEROP */ + +#if ( configSUPPORT_PICO_TIME_INTEROP == 1 ) + void xPortSyncInternalYieldUntilBefore( absolute_time_t t ) + { + TickType_t uxTicksToWait = prvGetTicksToWaitBefore(t); + if( uxTicksToWait ) + { + vTaskDelay(uxTicksToWait); + } + } +#endif /* configSUPPORT_PICO_TIME_INTEROP */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c new file mode 100644 index 0000000..671c2de --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c @@ -0,0 +1,27 @@ +/* + * Since at least FreeRTOS V7.5.3 uxTopUsedPriority is no longer + * present in the kernel, so it has to be supplied by other means for + * OpenOCD's threads awareness. + * + * Add this file to your project, and, if you're using --gc-sections, + * ``--undefined=uxTopUsedPriority'' (or + * ``-Wl,--undefined=uxTopUsedPriority'' when using gcc for final + * linking) to your LDFLAGS; same with all the other symbols you need. + */ + +#include "FreeRTOS.h" +#include "esp_attr.h" +#include "sdkconfig.h" + +#ifdef __GNUC__ + #define USED __attribute__( ( used ) ) +#else + #define USED +#endif + +/* + * This file is no longer needed as AFTER FreeRTOS V10.14.1 OpenOCD is fixed in the kernel. + * #ifdef CONFIG_ESP32_DEBUG_OCDAWARE + * const int USED DRAM_ATTR uxTopUsedPriority = configMAX_PRIORITIES - 1; + * #endif + */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h new file mode 100644 index 0000000..fee7dfd --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * This utility helps benchmarking interrupt latency and context switches. + * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h. + * You will also need to download the FreeRTOS_trace patch that contains + * portbenchmark.c and the complete version of portbenchmark.h + */ + +#ifndef PORTBENCHMARK_H +#define PORTBENCHMARK_H + +#if configBENCHMARK + #error "You need to download the FreeRTOS_trace patch that overwrites this file" +#endif + +#define portbenchmarkINTERRUPT_DISABLE() +#define portbenchmarkINTERRUPT_RESTORE( newstate ) +#define portbenchmarkIntLatency() +#define portbenchmarkIntWait() +#define portbenchmarkReset() +#define portbenchmarkPrint() + +#endif /* PORTBENCHMARK */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h new file mode 100644 index 0000000..5593cc0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h @@ -0,0 +1,561 @@ +/* + * SPDX-FileCopyrightText: 2017 Amazon.com, Inc. or its affiliates + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + */ + +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#ifndef __ASSEMBLER__ + + #include + + #include + #include + #include /* required for XSHAL_CLIB */ + #include + #include "esp_timer.h" /* required for FreeRTOS run time stats */ + #include "esp_system.h" + #include "esp_idf_version.h" + + + #include + #include "soc/soc_memory_layout.h" +#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #include "soc/compare_set.h" +#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + +/*#include "xtensa_context.h" */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + + #define portCHAR int8_t + #define portFLOAT float + #define portDOUBLE double + #define portLONG int32_t + #define portSHORT int16_t + #define portSTACK_TYPE uint8_t + #define portBASE_TYPE int + + typedef portSTACK_TYPE StackType_t; + typedef portBASE_TYPE BaseType_t; + typedef unsigned portBASE_TYPE UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + #endif +/*-----------------------------------------------------------*/ + +/* portbenchmark */ + #include "portbenchmark.h" + + #include "sdkconfig.h" + #include "esp_attr.h" + +/* "mux" data structure (spinlock) */ + typedef struct + { + /* owner field values: + * 0 - Uninitialized (invalid) + * portMUX_FREE_VAL - Mux is free, can be locked by either CPU + * CORE_ID_REGVAL_PRO / CORE_ID_REGVAL_APP - Mux is locked to the particular core + * + * Any value other than portMUX_FREE_VAL, CORE_ID_REGVAL_PRO, CORE_ID_REGVAL_APP indicates corruption + */ + uint32_t owner; + + /* count field: + * If mux is unlocked, count should be zero. + * If mux is locked, count is non-zero & represents the number of recursive locks on the mux. + */ + uint32_t count; + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + const char * lastLockedFn; + int lastLockedLine; + #endif + } portMUX_TYPE; + + #define portMUX_FREE_VAL 0xB33FFFFF + +/* Special constants for vPortCPUAcquireMutexTimeout() */ + #define portMUX_NO_TIMEOUT ( -1 ) /* When passed for 'timeout_cycles', spin forever if necessary */ + #define portMUX_TRY_LOCK 0 /* Try to acquire the spinlock a single time only */ + +/* Keep this in sync with the portMUX_TYPE struct definition please. */ + #ifndef CONFIG_FREERTOS_PORTMUX_DEBUG + #define portMUX_INITIALIZER_UNLOCKED \ + { \ + .owner = portMUX_FREE_VAL, \ + .count = 0, \ + } + #else + #define portMUX_INITIALIZER_UNLOCKED \ + { \ + .owner = portMUX_FREE_VAL, \ + .count = 0, \ + .lastLockedFn = "(never locked)", \ + .lastLockedLine = -1 \ + } + #endif /* ifndef CONFIG_FREERTOS_PORTMUX_DEBUG */ + + + #define portASSERT_IF_IN_ISR() vPortAssertIfInISR() + void vPortAssertIfInISR(); + + #define portCRITICAL_NESTING_IN_TCB 1 + +/* + * Modifications to portENTER_CRITICAL. + * + * For an introduction, see "Critical Sections & Disabling Interrupts" in docs/api-guides/freertos-smp.rst + * + * The original portENTER_CRITICAL only disabled the ISRs. This is enough for single-CPU operation: by + * disabling the interrupts, there is no task switch so no other tasks can meddle in the data, and because + * interrupts are disabled, ISRs can't corrupt data structures either. + * + * For multiprocessing, things get a bit more hairy. First of all, disabling the interrupts doesn't stop + * the tasks or ISRs on the other processors meddling with our CPU. For tasks, this is solved by adding + * a spinlock to the portENTER_CRITICAL macro. A task running on the other CPU accessing the same data will + * spinlock in the portENTER_CRITICAL code until the first CPU is done. + * + * For ISRs, we now also need muxes: while portENTER_CRITICAL disabling interrupts will stop ISRs on the same + * CPU from meddling with the data, it does not stop interrupts on the other cores from interfering with the + * data. For this, we also use a spinlock in the routines called by the ISR, but these spinlocks + * do not disable the interrupts (because they already are). + * + * This all assumes that interrupts are either entirely disabled or enabled. Interrupt priority levels + * will break this scheme. + * + * Remark: For the ESP32, portENTER_CRITICAL and portENTER_CRITICAL_ISR both alias vTaskEnterCritical, meaning + * that either function can be called both from ISR as well as task context. This is not standard FreeRTOS + * behaviour; please keep this in mind if you need any compatibility with other FreeRTOS implementations. + */ + void vPortCPUInitializeMutex( portMUX_TYPE * mux ); + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + #error CONFIG_FREERTOS_PORTMUX_DEBUG not supported in Amazon FreeRTOS + #endif + + void vTaskExitCritical(); + void vTaskEnterCritical(); + static inline void vPortConsumeSpinlockArg( int unused, + ... ) + { + } + +/** @brief Acquire a portmux spinlock with a timeout + * + * @param mux Pointer to portmux to acquire. + * @param timeout_cycles Timeout to spin, in CPU cycles. Pass portMUX_NO_TIMEOUT to wait forever, + * portMUX_TRY_LOCK to try a single time to acquire the lock. + * + * @return true if mutex is successfully acquired, false on timeout. + */ + bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux, + int timeout_cycles ); + void vPortCPUReleaseMutex( portMUX_TYPE * mux ); + + #define portENTER_CRITICAL( ... ) do { vTaskEnterCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 ) + #define portEXIT_CRITICAL( ... ) do { vTaskExitCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 ) + + + #define portENTER_CRITICAL_ISR( mux ) vPortCPUAcquireMutexTimeout( mux, portMUX_NO_TIMEOUT ) + #define portEXIT_CRITICAL_ISR( mux ) vPortCPUReleaseMutex( mux ) + + #define portENTER_CRITICAL_SAFE( mux ) \ + do { \ + if( xPortInIsrContext() ) { \ + portENTER_CRITICAL_ISR( mux ); \ + } \ + else { \ + portENTER_CRITICAL( mux ); \ + } \ + } while( 0 ) + + #define portEXIT_CRITICAL_SAFE( mux ) \ + do { \ + if( xPortInIsrContext() ) { \ + portEXIT_CRITICAL_ISR( mux ); \ + } \ + else { \ + portEXIT_CRITICAL( mux ); \ + } \ + } while( 0 ) + + +/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */ +/* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */ +/* */ +/* Only applies to one CPU. See notes above & below for reasons not to use these. */ + #define portDISABLE_INTERRUPTS() do { XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); portbenchmarkINTERRUPT_DISABLE(); } while( 0 ) + #define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 ) + +/* Cleaner solution allows nested interrupts disabling and restoring via local registers or stack. */ +/* They can be called from interrupts too. */ +/* WARNING: Only applies to current CPU. See notes above. */ + static inline unsigned portENTER_CRITICAL_NESTED() + { + unsigned state = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); + + portbenchmarkINTERRUPT_DISABLE(); + return state; + } + #define portEXIT_CRITICAL_NESTED( state ) do { portbenchmarkINTERRUPT_RESTORE( state ); XTOS_RESTORE_JUST_INTLEVEL( state ); } while( 0 ) + +/* These FreeRTOS versions are similar to the nested versions above */ + #define portSET_INTERRUPT_MASK_FROM_ISR() portENTER_CRITICAL_NESTED() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( state ) portEXIT_CRITICAL_NESTED( state ) + +/*Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force */ +/*the stack memory to always be internal. */ + #define portTcbMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT) + #define portStackMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT) + + #define pvPortMallocTcbMem(size) heap_caps_malloc(size, portTcbMemoryCaps) + #define pvPortMallocStackMem(size) heap_caps_malloc(size, portStackMemoryCaps) + +/*xTaskCreateStatic uses these functions to check incoming memory. */ + #define portVALID_TCB_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) ) + #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY + #define portVALID_STACK_MEM( ptr ) esp_ptr_byte_accessible( ptr ) + #else + #define portVALID_STACK_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) ) + #endif + +/* + * Wrapper for the Xtensa compare-and-set instruction. This subroutine will atomically compare + * *addr to 'compare'. If *addr == compare, *addr is set to *set. *set is updated with the previous + * value of *addr (either 'compare' or some other value.) + * + * Warning: From the ISA docs: in some (unspecified) cases, the s32c1i instruction may return the + * *bitwise inverse* of the old mem if the mem wasn't written. This doesn't seem to happen on the + * ESP32 (portMUX assertions would fail). + */ + static inline void uxPortCompareSet( volatile uint32_t * addr, + uint32_t compare, + uint32_t * set ) + { + #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) + __asm__ __volatile__ ( + "WSR %2,SCOMPARE1 \n" + "S32C1I %0, %1, 0 \n" + : "=r" ( *set ) + : "r" ( addr ), "r" ( compare ), "0" ( *set ) + ); + #else + #if ( XCHAL_HAVE_S32C1I > 0 ) + __asm__ __volatile__ ( + "WSR %2,SCOMPARE1 \n" + "S32C1I %0, %1, 0 \n" + : "=r" ( *set ) + : "r" ( addr ), "r" ( compare ), "0" ( *set ) + ); + #else + /* No S32C1I, so do this by disabling and re-enabling interrupts (slower) */ + uint32_t intlevel, old_value; + __asm__ __volatile__ ( "rsil %0, " XTSTR( XCHAL_EXCM_LEVEL ) "\n" + : "=r" ( intlevel ) ); + + old_value = *addr; + + if( old_value == compare ) + { + *addr = *set; + } + + __asm__ __volatile__ ( "memw \n" + "wsr %0, ps\n" + : : "r" ( intlevel ) ); + + *set = old_value; + #endif /* if ( XCHAL_HAVE_S32C1I > 0 ) */ + #endif /* #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) */ + } + + #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) + void uxPortCompareSetExtram( volatile uint32_t * addr, + uint32_t compare, + uint32_t * set ); + #else + static inline void uxPortCompareSetExtram(volatile uint32_t *addr, uint32_t compare, uint32_t *set) + { + #if defined(CONFIG_ESP32_SPIRAM_SUPPORT) + compare_and_set_extram(addr, compare, set); + #endif + } + #endif + +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 4 + #define portNOP() XT_NOP() +/*-----------------------------------------------------------*/ + +/* Fine resolution time */ + #define portGET_RUN_TIME_COUNTER_VALUE() xthal_get_ccount() +/*ccount or esp_timer are initialized elsewhere */ + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() + + #ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER +/* Coarse resolution time (us) */ + #define portALT_GET_RUN_TIME_COUNTER_VALUE( x ) x = ( uint32_t ) esp_timer_get_time() + #endif + + + +/* Kernel utilities. */ + void vPortYield( void ); + void _frxt_setup_switch( void ); + #define portYIELD() vPortYield() + #define portYIELD_FROM_ISR() { traceISR_EXIT_TO_SCHEDULER(); _frxt_setup_switch(); } + + static inline uint32_t xPortGetCoreID(); + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* When coprocessors are defined, we to maintain a pointer to coprocessors area. */ +/* We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: */ +/* MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. */ +/* The field is normally used for memory protection. FreeRTOS should create another general purpose field. */ + typedef struct + { + #if XCHAL_CP_NUM > 0 + volatile StackType_t * coproc_area; /* Pointer to coprocessor save area; MUST BE FIRST */ + #endif + + #if portUSING_MPU_WRAPPERS + /* Define here mpu_settings, which is port dependent */ + int mpu_setting; /* Just a dummy example here; MPU not ported to Xtensa yet */ + #endif + + #if configUSE_TRACE_FACILITY_2 + struct + { + /* Cf. porttraceStamp() */ + int taskstamp; /* Stamp from inside task to see where we are */ + int taskstampcount; /* A counter usually incremented when we restart the task's loop */ + } porttrace; + #endif + } xMPU_SETTINGS; + +/* Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) */ + #if ( XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2 ) && !portUSING_MPU_WRAPPERS /* If MPU wrappers not used, we still need to allocate coproc area */ + #undef portUSING_MPU_WRAPPERS + #define portUSING_MPU_WRAPPERS 1 /* Enable it to allocate coproc area */ + #define MPU_WRAPPERS_H /* Override mpu_wrapper.h to disable unwanted code */ + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA + #endif + + void vApplicationSleep( TickType_t xExpectedIdleTime ); + void vPortSetStackWatchpoint( void* pxStackStart ); + + #define portSUPPRESS_TICKS_AND_SLEEP( idleTime ) vApplicationSleep( idleTime ) + + /*-----------------------------------------------------------*/ + + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + /* Architecture specific optimisations. */ + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + /*-----------------------------------------------------------*/ + + + void _xt_coproc_release( volatile void * coproc_sa_base ); + + +/* + * Map to the memory management routines required for the port. + * + * Note that libc standard malloc/free are also available for + * non-FreeRTOS-specific code, and behave the same as + * pvPortMalloc()/vPortFree(). + */ + #define pvPortMalloc heap_caps_malloc_default + #define vPortFree heap_caps_free + #define xPortGetFreeHeapSize esp_get_free_heap_size + #define xPortGetMinimumEverFreeHeapSize esp_get_minimum_free_heap_size + +#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) +/* + * Send an interrupt to another core in order to make the task running + * on it yield for a higher-priority task. + */ + + void vPortYieldOtherCore( BaseType_t coreid ) PRIVILEGED_FUNCTION; + +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ + +/* + * Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack + * watchpoint around. + */ + void vPortSetStackWatchpoint( void * pxStackStart ); + +/* + * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs + * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway. + */ + BaseType_t xPortInIsrContext(); + + +/* + * This function will be called in High prio ISRs. Returns true if the current core was in ISR context + * before calling into high prio ISR context. + */ + BaseType_t xPortInterruptedFromISRContext(); + +/* + * The structures and methods of manipulating the MPU are contained within the + * port layer. + * + * Fills the xMPUSettings structure with the memory region information + * contained in xRegions. + */ + #if ( portUSING_MPU_WRAPPERS == 1 ) + struct xMEMORY_REGION; + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t usStackDepth ) PRIVILEGED_FUNCTION; + void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings ); + #endif + +/* Multi-core: get current core ID */ + static inline uint32_t IRAM_ATTR xPortGetCoreID() + { + int id; + + asm ( + "rsr.prid %0\n" + " extui %0,%0,13,1" + : "=r" ( id ) ); + return id; + } + +/* Get tick rate per second */ + uint32_t xPortGetTickRateHz( void ); + +/* porttrace */ + #if configUSE_TRACE_FACILITY_2 + #include "porttrace.h" + #endif + +/* configASSERT_2 if requested */ + #if configASSERT_2 + #include + void exit( int ); + #define configASSERT( x ) if( !( x ) ) { porttracePrint( -1 ); printf( "\nAssertion failed in %s:%d\n", __FILE__, __LINE__ ); exit( -1 ); } + #endif + +/* Barriers */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + + +#endif // __ASSEMBLER__ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h new file mode 100644 index 0000000..fce0d5a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: 2017, Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ + +/* File adapted to use on IDF FreeRTOS component, extracted + * originally from zephyr RTOS code base: + * https://github.com/zephyrproject-rtos/zephyr/blob/dafd348/arch/xtensa/include/xtensa-asm2-s.h + */ + +#ifndef __XT_ASM_UTILS_H +#define __XT_ASM_UTILS_H + +/* + * SPILL_ALL_WINDOWS + * + * Spills all windowed registers (i.e. registers not visible as + * A0-A15) to their ABI-defined spill regions on the stack. + * + * Unlike the Xtensa HAL implementation, this code requires that the + * EXCM and WOE bit be enabled in PS, and relies on repeated hardware + * exception handling to do the register spills. The trick is to do a + * noop write to the high registers, which the hardware will trap + * (into an overflow exception) in the case where those registers are + * already used by an existing call frame. Then it rotates the window + * and repeats until all but the A0-A3 registers of the original frame + * are guaranteed to be spilled, eventually rotating back around into + * the original frame. Advantages: + * + * - Vastly smaller code size + * + * - More easily maintained if changes are needed to window over/underflow + * exception handling. + * + * - Requires no scratch registers to do its work, so can be used safely in any + * context. + * + * - If the WOE bit is not enabled (for example, in code written for + * the CALL0 ABI), this becomes a silent noop and operates compatbily. + * + * - Hilariously it's ACTUALLY FASTER than the HAL routine. And not + * just a little bit, it's MUCH faster. With a mostly full register + * file on an LX6 core (ESP-32) I'm measuring 145 cycles to spill + * registers with this vs. 279 (!) to do it with + * xthal_spill_windows(). + */ + +.macro SPILL_ALL_WINDOWS +#if XCHAL_NUM_AREGS == 64 + and a12, a12, a12 + rotw 3 + and a12, a12, a12 + rotw 3 + and a12, a12, a12 + rotw 3 + and a12, a12, a12 + rotw 3 + and a12, a12, a12 + rotw 4 +#elif XCHAL_NUM_AREGS == 32 + and a12, a12, a12 + rotw 3 + and a12, a12, a12 + rotw 3 + and a4, a4, a4 + rotw 2 +#else +#error Unrecognized XCHAL_NUM_AREGS +#endif +.endm + +#endif \ No newline at end of file diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h new file mode 100644 index 0000000..aeade04 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h @@ -0,0 +1,139 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************** +* Xtensa-specific API for RTOS ports. +******************************************************************************/ + +#ifndef __XTENSA_API_H__ +#define __XTENSA_API_H__ + +#include + +#include "xtensa_context.h" + + +/* Typedef for C-callable interrupt handler function */ +typedef void (* xt_handler)( void * ); + +/* Typedef for C-callable exception handler function */ +typedef void (* xt_exc_handler)( XtExcFrame * ); + + +/* + * ------------------------------------------------------------------------------- + * Call this function to set a handler for the specified exception. The handler + * will be installed on the core that calls this function. + * + * n - Exception number (type) + * f - Handler function address, NULL to uninstall handler. + * + * The handler will be passed a pointer to the exception frame, which is created + * on the stack of the thread that caused the exception. + * + * If the handler returns, the thread context will be restored and the faulting + * instruction will be retried. Any values in the exception frame that are + * modified by the handler will be restored as part of the context. For details + * of the exception frame structure see xtensa_context.h. + * ------------------------------------------------------------------------------- + */ +extern xt_exc_handler xt_set_exception_handler( int n, + xt_exc_handler f ); + + +/* + * ------------------------------------------------------------------------------- + * Call this function to set a handler for the specified interrupt. The handler + * will be installed on the core that calls this function. + * + * n - Interrupt number. + * f - Handler function address, NULL to uninstall handler. + * arg - Argument to be passed to handler. + * ------------------------------------------------------------------------------- + */ +extern xt_handler xt_set_interrupt_handler( int n, + xt_handler f, + void * arg ); + + +/* + * ------------------------------------------------------------------------------- + * Call this function to enable the specified interrupts on the core that runs + * this code. + * + * mask - Bit mask of interrupts to be enabled. + * ------------------------------------------------------------------------------- + */ +extern void xt_ints_on( unsigned int mask ); + + +/* + * ------------------------------------------------------------------------------- + * Call this function to disable the specified interrupts on the core that runs + * this code. + * + * mask - Bit mask of interrupts to be disabled. + * ------------------------------------------------------------------------------- + */ +extern void xt_ints_off( unsigned int mask ); + + +/* + * ------------------------------------------------------------------------------- + * Call this function to set the specified (s/w) interrupt. + * ------------------------------------------------------------------------------- + */ +static inline void xt_set_intset( unsigned int arg ) +{ + xthal_set_intset( arg ); +} + + +/* + * ------------------------------------------------------------------------------- + * Call this function to clear the specified (s/w or edge-triggered) + * interrupt. + * ------------------------------------------------------------------------------- + */ +static inline void xt_set_intclear( unsigned int arg ) +{ + xthal_set_intclear( arg ); +} + +/* + * ------------------------------------------------------------------------------- + * Call this function to get handler's argument for the specified interrupt. + * + * n - Interrupt number. + * ------------------------------------------------------------------------------- + */ +extern void * xt_get_interrupt_handler_arg( int n ); + +#endif /* __XTENSA_API_H__ */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h new file mode 100644 index 0000000..c53987d --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h @@ -0,0 +1,154 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************* +* +* Configuration-specific information for Xtensa build. This file must be +* included in FreeRTOSConfig.h to properly set up the config-dependent +* parameters correctly. +* +* NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must +* be defined to be > 0 somewhere above or on the command line. +* +*******************************************************************************/ + +#ifndef XTENSA_CONFIG_H + #define XTENSA_CONFIG_H + + #ifdef __cplusplus + extern "C" { + #endif + + #include + #include + #include /* required for XSHAL_CLIB */ + + #include "xtensa_context.h" + + +/*----------------------------------------------------------------------------- + * STACK REQUIREMENTS + * + * This section defines the minimum stack size, and the extra space required to + * be allocated for saving coprocessor state and/or C library state information + * (if thread safety is enabled for the C library). The sizes are in bytes. + * + * Stack sizes for individual tasks should be derived from these minima based on + * the maximum call depth of the task and the maximum level of interrupt nesting. + * A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based + * on the requirement for a task that calls nothing else but can be interrupted. + * This assumes that interrupt handlers do not call more than a few levels deep. + * If this is not true, i.e. one or more interrupt handlers make deep calls then + * the minimum must be increased. + * + * If the Xtensa processor configuration includes coprocessors, then space is + * allocated to save the coprocessor state on the stack. + * + * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB + * is defined) then space is allocated to save the C library context in the TCB. + * + * Allocating insufficient stack space is a common source of hard-to-find errors. + * During development, it is best to enable the FreeRTOS stack checking features. + * + * Usage: + * + * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe + * use of the C library. This will require extra stack + * space to be allocated for tasks that use the C library + * reentrant functions. See below for more information. + * + * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them + * support thread safety. Check your core configuration to see which C library + * was chosen for your system. + * + * XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended + * that you do not use a stack smaller than this for any + * task. In case you want to use stacks smaller than this + * size, you must verify that the smaller size(s) will work + * under all operating conditions. + * + * XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task + * that does not make C library reentrant calls. Add this + * to the amount of stack space required by the task itself. + * + * XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state. + * + * -----------------------------------------------------------------------------*/ + +/* Extra space required for interrupt/exception hooks. */ + #ifdef XT_INTEXC_HOOKS + #ifdef __XTENSA_CALL0_ABI__ + #define STK_INTEXC_EXTRA 0x200 + #else + #define STK_INTEXC_EXTRA 0x180 + #endif + #else + #define STK_INTEXC_EXTRA 0 + #endif + + #define XT_CLIB_CONTEXT_AREA_SIZE 0 + +/*------------------------------------------------------------------------------ + * Extra size -- interrupt frame plus coprocessor save area plus hook space. + * NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks. + * ------------------------------------------------------------------------------*/ + #ifdef __XTENSA_CALL0_ABI__ + #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE ) + #else + #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE ) + #endif + +/*------------------------------------------------------------------------------ + * Space allocated for user code -- function calls and local variables. + * NOTE: This number can be adjusted to suit your needs. You must verify that the + * amount of space you reserve is adequate for the worst-case conditions in your + * application. + * NOTE: The windowed ABI requires more stack, since space has to be reserved + * for spilling register windows. + * ------------------------------------------------------------------------------*/ + #ifdef __XTENSA_CALL0_ABI__ + #define XT_USER_SIZE 0x200 + #else + #define XT_USER_SIZE 0x400 + #endif + +/* Minimum recommended stack size. */ + #define XT_STACK_MIN_SIZE ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) ) + +/* OS overhead with and without C library thread context. */ + #define XT_STACK_EXTRA ( XT_XTRA_SIZE ) + #define XT_STACK_EXTRA_CLIB ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE ) + + + #ifdef __cplusplus + } + #endif + +#endif /* XTENSA_CONFIG_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h new file mode 100644 index 0000000..1001650 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h @@ -0,0 +1,399 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************* + + XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES + +This header contains definitions and macros for use primarily by Xtensa +RTOS assembly coded source files. It includes and uses the Xtensa hardware +abstraction layer (HAL) to deal with config specifics. It may also be +included in C source files. + +!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !! + +NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes. + +*******************************************************************************/ + +#ifndef XTENSA_CONTEXT_H +#define XTENSA_CONTEXT_H + +#ifdef __ASSEMBLER__ +#include +#endif + +#include +#include +#include +#include +#include + + +/* Align a value up to nearest n-byte boundary, where n is a power of 2. */ +#define ALIGNUP(n, val) (((val) + (n)-1) & -(n)) + + +/* +------------------------------------------------------------------------------- + Macros that help define structures for both C and assembler. +------------------------------------------------------------------------------- +*/ + +#ifdef STRUCT_BEGIN +#undef STRUCT_BEGIN +#undef STRUCT_FIELD +#undef STRUCT_AFIELD +#undef STRUCT_END +#endif + +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) + +#define STRUCT_BEGIN .pushsection .text; .struct 0 +#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size +#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n) +#define STRUCT_END(sname) sname##Size:; .popsection + +#else + +#define STRUCT_BEGIN typedef struct { +#define STRUCT_FIELD(ctype,size,asname,name) ctype name; +#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n]; +#define STRUCT_END(sname) } sname; + +#endif //_ASMLANGUAGE || __ASSEMBLER__ + + +/* +------------------------------------------------------------------------------- + INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT + + A stack frame of this structure is allocated for any interrupt or exception. + It goes on the current stack. If the RTOS has a system stack for handling + interrupts, every thread stack must allow space for just one interrupt stack + frame, then nested interrupt stack frames go on the system stack. + + The frame includes basic registers (explicit) and "extra" registers introduced + by user TIE or the use of the MAC16 option in the user's Xtensa config. + The frame size is minimized by omitting regs not applicable to user's config. + + For Windowed ABI, this stack frame includes the interruptee's base save area, + another base save area to manage gcc nested functions, and a little temporary + space to help manage the spilling of the register windows. +------------------------------------------------------------------------------- +*/ + +STRUCT_BEGIN +STRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */ +STRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */ +STRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */ +STRUCT_FIELD (long, 4, XT_STK_A0, a0) +STRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */ +STRUCT_FIELD (long, 4, XT_STK_A2, a2) +STRUCT_FIELD (long, 4, XT_STK_A3, a3) +STRUCT_FIELD (long, 4, XT_STK_A4, a4) +STRUCT_FIELD (long, 4, XT_STK_A5, a5) +STRUCT_FIELD (long, 4, XT_STK_A6, a6) +STRUCT_FIELD (long, 4, XT_STK_A7, a7) +STRUCT_FIELD (long, 4, XT_STK_A8, a8) +STRUCT_FIELD (long, 4, XT_STK_A9, a9) +STRUCT_FIELD (long, 4, XT_STK_A10, a10) +STRUCT_FIELD (long, 4, XT_STK_A11, a11) +STRUCT_FIELD (long, 4, XT_STK_A12, a12) +STRUCT_FIELD (long, 4, XT_STK_A13, a13) +STRUCT_FIELD (long, 4, XT_STK_A14, a14) +STRUCT_FIELD (long, 4, XT_STK_A15, a15) +STRUCT_FIELD (long, 4, XT_STK_SAR, sar) +STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause) +STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr) +#if XCHAL_HAVE_LOOPS +STRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg) +STRUCT_FIELD (long, 4, XT_STK_LEND, lend) +STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount) +#endif +#ifndef __XTENSA_CALL0_ABI__ +/* Temporary space for saving stuff during window spill */ +STRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0) +STRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1) +STRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2) +#endif +#ifdef XT_USE_SWPRI +/* Storage for virtual priority mask */ +STRUCT_FIELD (long, 4, XT_STK_VPRI, vpri) +#endif +#ifdef XT_USE_OVLY +/* Storage for overlay state */ +STRUCT_FIELD (long, 4, XT_STK_OVLY, ovly) +#endif +STRUCT_END(XtExcFrame) + +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) +#define XT_STK_NEXT1 XtExcFrameSize +#else +#define XT_STK_NEXT1 sizeof(XtExcFrame) +#endif + +/* Allocate extra storage if needed */ +#if XCHAL_EXTRA_SA_SIZE != 0 + +#if XCHAL_EXTRA_SA_ALIGN <= 16 +#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) +#else +/* If need more alignment than stack, add space for dynamic alignment */ +#define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN) +#endif +#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE) + +#else + +#define XT_STK_NEXT2 XT_STK_NEXT1 + +#endif + +/* +------------------------------------------------------------------------------- + This is the frame size. Add space for 4 registers (interruptee's base save + area) and some space for gcc nested functions if any. +------------------------------------------------------------------------------- +*/ +#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20) + + +/* +------------------------------------------------------------------------------- + SOLICITED STACK FRAME FOR A THREAD + + A stack frame of this structure is allocated whenever a thread enters the + RTOS kernel intentionally (and synchronously) to submit to thread scheduling. + It goes on the current thread's stack. + + The solicited frame only includes registers that are required to be preserved + by the callee according to the compiler's ABI conventions, some space to save + the return address for returning to the caller, and the caller's PS register. + + For Windowed ABI, this stack frame includes the caller's base save area. + + Note on XT_SOL_EXIT field: + It is necessary to distinguish a solicited from an interrupt stack frame. + This field corresponds to XT_STK_EXIT in the interrupt stack frame and is + always at the same offset (0). It can be written with a code (usually 0) + to distinguish a solicted frame from an interrupt frame. An RTOS port may + opt to ignore this field if it has another way of distinguishing frames. +------------------------------------------------------------------------------- +*/ + +STRUCT_BEGIN +#ifdef __XTENSA_CALL0_ABI__ +STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) +STRUCT_FIELD (long, 4, XT_SOL_PC, pc) +STRUCT_FIELD (long, 4, XT_SOL_PS, ps) +STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) +STRUCT_FIELD (long, 4, XT_SOL_A12, a12) /* should be on 16-byte alignment */ +STRUCT_FIELD (long, 4, XT_SOL_A13, a13) +STRUCT_FIELD (long, 4, XT_SOL_A14, a14) +STRUCT_FIELD (long, 4, XT_SOL_A15, a15) +#else +STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) +STRUCT_FIELD (long, 4, XT_SOL_PC, pc) +STRUCT_FIELD (long, 4, XT_SOL_PS, ps) +STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) +STRUCT_FIELD (long, 4, XT_SOL_A0, a0) /* should be on 16-byte alignment */ +STRUCT_FIELD (long, 4, XT_SOL_A1, a1) +STRUCT_FIELD (long, 4, XT_SOL_A2, a2) +STRUCT_FIELD (long, 4, XT_SOL_A3, a3) +#endif +STRUCT_END(XtSolFrame) + +/* Size of solicited stack frame */ +#define XT_SOL_FRMSZ ALIGNUP(0x10, XtSolFrameSize) + + +/* +------------------------------------------------------------------------------- + CO-PROCESSOR STATE SAVE AREA FOR A THREAD + + The RTOS must provide an area per thread to save the state of co-processors + when that thread does not have control. Co-processors are context-switched + lazily (on demand) only when a new thread uses a co-processor instruction, + otherwise a thread retains ownership of the co-processor even when it loses + control of the processor. An Xtensa co-processor exception is triggered when + any co-processor instruction is executed by a thread that is not the owner, + and the context switch of that co-processor is then peformed by the handler. + Ownership represents which thread's state is currently in the co-processor. + + Co-processors may not be used by interrupt or exception handlers. If an + co-processor instruction is executed by an interrupt or exception handler, + the co-processor exception handler will trigger a kernel panic and freeze. + This restriction is introduced to reduce the overhead of saving and restoring + co-processor state (which can be quite large) and in particular remove that + overhead from interrupt handlers. + + The co-processor state save area may be in any convenient per-thread location + such as in the thread control block or above the thread stack area. It need + not be in the interrupt stack frame since interrupts don't use co-processors. + + Along with the save area for each co-processor, two bitmasks with flags per + co-processor (laid out as in the CPENABLE reg) help manage context-switching + co-processors as efficiently as possible: + + XT_CPENABLE + The contents of a non-running thread's CPENABLE register. + It represents the co-processors owned (and whose state is still needed) + by the thread. When a thread is preempted, its CPENABLE is saved here. + When a thread solicits a context-swtich, its CPENABLE is cleared - the + compiler has saved the (caller-saved) co-proc state if it needs to. + When a non-running thread loses ownership of a CP, its bit is cleared. + When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg. + Avoids co-processor exceptions when no change of ownership is needed. + + XT_CPSTORED + A bitmask with the same layout as CPENABLE, a bit per co-processor. + Indicates whether the state of each co-processor is saved in the state + save area. When a thread enters the kernel, only the state of co-procs + still enabled in CPENABLE is saved. When the co-processor exception + handler assigns ownership of a co-processor to a thread, it restores + the saved state only if this bit is set, and clears this bit. + + XT_CP_CS_ST + A bitmask with the same layout as CPENABLE, a bit per co-processor. + Indicates whether callee-saved state is saved in the state save area. + Callee-saved state is saved by itself on a solicited context switch, + and restored when needed by the coprocessor exception handler. + Unsolicited switches will cause the entire coprocessor to be saved + when necessary. + + XT_CP_ASA + Pointer to the aligned save area. Allows it to be aligned more than + the overall save area (which might only be stack-aligned or TCB-aligned). + Especially relevant for Xtensa cores configured with a very large data + path that requires alignment greater than 16 bytes (ABI stack alignment). +------------------------------------------------------------------------------- +*/ + +#if XCHAL_CP_NUM > 0 + +/* Offsets of each coprocessor save area within the 'aligned save area': */ +#define XT_CP0_SA 0 +#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE) +#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE) +#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE) +#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE) +#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE) +#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE) +#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE) +#define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE) + +/* Offsets within the overall save area: */ +#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */ +#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */ +#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */ +#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */ +/* Overall size allows for dynamic alignment: */ +#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN) +#else +#define XT_CP_SIZE 0 +#endif + + +/* + Macro to get the current core ID. Only uses the reg given as an argument. + Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0) + and 0xABAB on the APP CPU (1). We can distinguish between the two by checking + bit 13: it's 1 on the APP and 0 on the PRO processor. +*/ +#ifdef __ASSEMBLER__ + .macro getcoreid reg + rsr.prid \reg + extui \reg,\reg,13,1 + .endm +#endif + +#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) +#define CORE_ID_PRO 0xCDCD +#define CORE_ID_APP 0xABAB +#else +#define CORE_ID_REGVAL_PRO 0xCDCD +#define CORE_ID_REGVAL_APP 0xABAB + +/* Included for compatibility, recommend using CORE_ID_REGVAL_PRO instead */ +#define CORE_ID_PRO CORE_ID_REGVAL_PRO + +/* Included for compatibility, recommend using CORE_ID_REGVAL_APP instead */ +#define CORE_ID_APP CORE_ID_REGVAL_APP +#endif + +/* +------------------------------------------------------------------------------- + MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN + + Convenient where the frame size requirements are the same for both ABIs. + ENTRY(sz), RET(sz) are for framed functions (have locals or make calls). + ENTRY0, RET0 are for frameless functions (no locals, no calls). + + where size = size of stack frame in bytes (must be >0 and aligned to 16). + For framed functions the frame is created and the return address saved at + base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). + For frameless functions, there is no frame and return address remains in a0. + Note: Because CPP macros expand to a single line, macros requiring multi-line + expansions are implemented as assembler macros. +------------------------------------------------------------------------------- +*/ + +#ifdef __ASSEMBLER__ +#ifdef __XTENSA_CALL0_ABI__ + /* Call0 */ + #define ENTRY(sz) entry1 sz + .macro entry1 size=0x10 + addi sp, sp, -\size + s32i a0, sp, 0 + .endm + #define ENTRY0 + #define RET(sz) ret1 sz + .macro ret1 size=0x10 + l32i a0, sp, 0 + addi sp, sp, \size + ret + .endm + #define RET0 ret +#else + /* Windowed */ + #define ENTRY(sz) entry sp, sz + #define ENTRY0 entry sp, 0x10 + #define RET(sz) retw + #define RET0 retw +#endif +#endif + + + + + +#endif /* XTENSA_CONTEXT_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h new file mode 100644 index 0000000..fde7fcc --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h @@ -0,0 +1,240 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************* +* +* RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES +* (FreeRTOS Port) +* +* This header is the primary glue between generic Xtensa RTOS support +* sources and a specific RTOS port for Xtensa. It contains definitions +* and macros for use primarily by Xtensa assembly coded source files. +* +* Macros in this header map callouts from generic Xtensa files to specific +* RTOS functions. It may also be included in C source files. +* +* Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa +* architecture, using the Xtensa hardware abstraction layer (HAL) to deal +* with configuration specifics. +* +* Should be included by all Xtensa generic and RTOS port-specific sources. +* +*******************************************************************************/ + +#ifndef XTENSA_RTOS_H +#define XTENSA_RTOS_H + +#ifdef __ASSEMBLER__ + #include +#else + #include +#endif + +#include +#include + +/* + * Include any RTOS specific definitions that are needed by this header. + */ +#include "FreeRTOSConfig.h" + +/* + * Convert FreeRTOSConfig definitions to XTENSA definitions. + * However these can still be overridden from the command line. + */ + +#ifndef XT_SIMULATOR + #if configXT_SIMULATOR + #define XT_SIMULATOR 1 /* Simulator mode */ + #endif +#endif + +#ifndef XT_BOARD + #if configXT_BOARD + #define XT_BOARD 1 /* Board mode */ + #endif +#endif + +#ifndef XT_TIMER_INDEX + #if defined configXT_TIMER_INDEX + #define XT_TIMER_INDEX configXT_TIMER_INDEX /* Index of hardware timer to be used */ + #endif +#endif + +#ifndef XT_INTEXC_HOOKS + #if configXT_INTEXC_HOOKS + #define XT_INTEXC_HOOKS 1 /* Enables exception hooks */ + #endif +#endif + +#if !defined( XT_SIMULATOR ) && !defined( XT_BOARD ) + #error Either XT_SIMULATOR or XT_BOARD must be defined. +#endif + + +/* + * Name of RTOS (for messages). + */ +#define XT_RTOS_NAME FreeRTOS + +/* + * Check some Xtensa configuration requirements and report error if not met. + * Error messages can be customize to the RTOS port. + */ + +#if !XCHAL_HAVE_XEA2 + #error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)." +#endif + + +/******************************************************************************* +* +* RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS. +* +* Define callout macros used in generic Xtensa code to interact with the RTOS. +* The macros are simply the function names for use in calls from assembler code. +* Some of these functions may call back to generic functions in xtensa_context.h . +* +*******************************************************************************/ + +/* + * Inform RTOS of entry into an interrupt handler that will affect it. + * Allows RTOS to manage switch to any system stack and count nesting level. + * Called after minimal context has been saved, with interrupts disabled. + * RTOS port can call0 _xt_context_save to save the rest of the context. + * May only be called from assembly code by the 'call0' instruction. + */ +/* void XT_RTOS_INT_ENTER(void) */ +#define XT_RTOS_INT_ENTER _frxt_int_enter + +/* + * Inform RTOS of completion of an interrupt handler, and give control to + * RTOS to perform thread/task scheduling, switch back from any system stack + * and restore the context, and return to the exit dispatcher saved in the + * stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore + * to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save, + * leaving only a minimal part of the context to be restored by the exit + * dispatcher. This function does not return to the place it was called from. + * May only be called from assembly code by the 'call0' instruction. + */ +/* void XT_RTOS_INT_EXIT(void) */ +#define XT_RTOS_INT_EXIT _frxt_int_exit + +/* + * Inform RTOS of the occurrence of a tick timer interrupt. + * If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined. + * May be coded in or called from C or assembly, per ABI conventions. + * RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro). + */ +/* void XT_RTOS_TIMER_INT(void) */ +#define XT_RTOS_TIMER_INT _frxt_timer_int +#define XT_TICK_PER_SEC configTICK_RATE_HZ + +/* + * Return in a15 the base address of the co-processor state save area for the + * thread that triggered a co-processor exception, or 0 if no thread was running. + * The state save area is structured as defined in xtensa_context.h and has size + * XT_CP_SIZE. Co-processor instructions should only be used in thread code, never + * in interrupt handlers or the RTOS kernel. May only be called from assembly code + * and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. + * The implementation may use only a2-4, a15 (all other regs must be preserved). + */ +/* void* XT_RTOS_CP_STATE(void) */ +#define XT_RTOS_CP_STATE _frxt_task_coproc_state + + +/******************************************************************************* +* +* HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL. +* +* This Xtensa RTOS port provides hooks for dynamically installing exception +* and interrupt handlers to facilitate automated testing where each test +* case can install its own handler for user exceptions and each interrupt +* priority (level). This consists of an array of function pointers indexed +* by interrupt priority, with index 0 being the user exception handler hook. +* Each entry in the array is initially 0, and may be replaced by a function +* pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0. +* +* The handler for low and medium priority obeys ABI conventions so may be coded +* in C. For the exception handler, the cause is the contents of the EXCCAUSE +* reg, and the result is -1 if handled, else the cause (still needs handling). +* For interrupt handlers, the cause is a mask of pending enabled interrupts at +* that level, and the result is the same mask with the bits for the handled +* interrupts cleared (those not cleared still need handling). This allows a test +* case to either pre-handle or override the default handling for the exception +* or interrupt level (see xtensa_vectors.S). +* +* High priority handlers (including NMI) must be coded in assembly, are always +* called by 'call0' regardless of ABI, must preserve all registers except a0, +* and must not use or modify the interrupted stack. The hook argument 'cause' +* is not passed and the result is ignored, so as not to burden the caller with +* saving and restoring a2 (it assumes only one interrupt per level - see the +* discussion in high priority interrupts in xtensa_vectors.S). The handler +* therefore should be coded to prototype 'void h(void)' even though it plugs +* into an array of handlers of prototype 'unsigned h(unsigned)'. +* +* To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'. +* +*******************************************************************************/ + +#define XT_INTEXC_HOOK_NUM ( 1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI ) + +#ifndef __ASSEMBLER__ + typedef unsigned (* XT_INTEXC_HOOK)( unsigned cause ); + extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[ XT_INTEXC_HOOK_NUM ]; +#endif + + +/******************************************************************************* +* +* CONVENIENCE INCLUSIONS. +* +* Ensures RTOS specific files need only include this one Xtensa-generic header. +* These headers are included last so they can use the RTOS definitions above. +* +*******************************************************************************/ + +#include "xtensa_context.h" + +#ifdef XT_RTOS_TIMER_INT + #include "xtensa_timer.h" +#endif + + +/******************************************************************************* +* +* Xtensa Port Version. +* +*******************************************************************************/ + +#define XTENSA_PORT_VERSION 1.4 .2 +#define XTENSA_PORT_VERSION_STRING "1.4.2" + +#endif /* XTENSA_RTOS_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h new file mode 100644 index 0000000..185b141 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h @@ -0,0 +1,167 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************* +* +* XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY +* +* This header contains definitions and macros for use primarily by Xtensa +* RTOS assembly coded source files. It includes and uses the Xtensa hardware +* abstraction layer (HAL) to deal with config specifics. It may also be +* included in C source files. +* +* User may edit to modify timer selection and to specify clock frequency and +* tick duration to match timer interrupt to the real-time tick duration. +* +* If the RTOS has no timer interrupt, then there is no tick timer and the +* clock frequency is irrelevant, so all of these macros are left undefined +* and the Xtensa core configuration need not have a timer. +* +*******************************************************************************/ + +#ifndef XTENSA_TIMER_H +#define XTENSA_TIMER_H + +#ifdef __ASSEMBLER__ + #include +#endif + +#include +#include + +#include "xtensa_rtos.h" /* in case this wasn't included directly */ + +#include "FreeRTOSConfig.h" + +/* + * Select timer to use for periodic tick, and determine its interrupt number + * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, + * in which case its validity is checked (it must exist in this core and must + * not be on a high priority interrupt - an error will be reported in invalid). + * Otherwise select the first low or medium priority interrupt timer available. + */ +#if XCHAL_NUM_TIMERS == 0 + + #error "This Xtensa configuration is unsupported, it has no timers." + +#else + + #ifndef XT_TIMER_INDEX + #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL( XCHAL_TIMER3_INTERRUPT ) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 3 + #endif + #endif + #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL( XCHAL_TIMER2_INTERRUPT ) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 2 + #endif + #endif + #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL( XCHAL_TIMER1_INTERRUPT ) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 1 + #endif + #endif + #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL( XCHAL_TIMER0_INTERRUPT ) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 0 + #endif + #endif + #endif /* ifndef XT_TIMER_INDEX */ + #ifndef XT_TIMER_INDEX + #error "There is no suitable timer in this Xtensa configuration." + #endif + + #define XT_CCOMPARE ( CCOMPARE + XT_TIMER_INDEX ) + #define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT( XT_TIMER_INDEX ) + #define XT_TIMER_INTPRI XCHAL_INT_LEVEL( XT_TIMER_INTNUM ) + #define XT_TIMER_INTEN ( 1 << XT_TIMER_INTNUM ) + + #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED + #error "The timer selected by XT_TIMER_INDEX does not exist in this core." + #elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL + #error "The timer interrupt cannot be high priority (use medium or low)." + #endif + +#endif /* XCHAL_NUM_TIMERS */ + +/* + * Set processor clock frequency, used to determine clock divisor for timer tick. + * User should BE SURE TO ADJUST THIS for the Xtensa platform being used. + * If using a supported board via the board-independent API defined in xtbsp.h, + * this may be left undefined and frequency and tick divisor will be computed + * and cached during run-time initialization. + * + * NOTE ON SIMULATOR: + * Under the Xtensa instruction set simulator, the frequency can only be estimated + * because it depends on the speed of the host and the version of the simulator. + * Also because it runs much slower than hardware, it is not possible to achieve + * real-time performance for most applications under the simulator. A frequency + * too low does not allow enough time between timer interrupts, starving threads. + * To obtain a more convenient but non-real-time tick duration on the simulator, + * compile with xt-xcc option "-DXT_SIMULATOR". + * Adjust this frequency to taste (it's not real-time anyway!). + */ +#if defined( XT_SIMULATOR ) && !defined( XT_CLOCK_FREQ ) + #define XT_CLOCK_FREQ configCPU_CLOCK_HZ +#endif + +#if !defined( XT_CLOCK_FREQ ) && !defined( XT_BOARD ) + #error "XT_CLOCK_FREQ must be defined for the target platform." +#endif + +/* + * Default number of timer "ticks" per second (default 100 for 10ms tick). + * RTOS may define this in its own way (if applicable) in xtensa_rtos.h. + * User may redefine this to an optimal value for the application, either by + * editing this here or in xtensa_rtos.h, or compiling with xt-xcc option + * "-DXT_TICK_PER_SEC=" where is a suitable number. + */ +#ifndef XT_TICK_PER_SEC + #define XT_TICK_PER_SEC configTICK_RATE_HZ /* 10 ms tick = 100 ticks per second */ +#endif + +/* + * Derivation of clock divisor for timer tick and interrupt (one per tick). + */ +#ifdef XT_CLOCK_FREQ + #define XT_TICK_DIVISOR ( XT_CLOCK_FREQ / XT_TICK_PER_SEC ) +#endif + +#ifndef __ASSEMBLER__ + extern unsigned _xt_tick_divisor; + extern void _xt_tick_divisor_init( void ); +#endif + +#endif /* XTENSA_TIMER_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/port.c new file mode 100644 index 0000000..4b73eab --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/port.c @@ -0,0 +1,496 @@ +/* + * SPDX-FileCopyrightText: 2020 Amazon.com, Inc. or its affiliates + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + */ + +/******************************************************************************* + * // Copyright (c) 2003-2015 Cadence Design Systems, Inc. + * // + * // Permission is hereby granted, free of charge, to any person obtaining + * // a copy of this software and associated documentation files (the + * // "Software"), to deal in the Software without restriction, including + * // without limitation the rights to use, copy, modify, merge, publish, + * // distribute, sublicense, and/or sell copies of the Software, and to + * // permit persons to whom the Software is furnished to do so, subject to + * // the following conditions: + * // + * // The above copyright notice and this permission notice shall be included + * // in all copies or substantial portions of the Software. + * // + * // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ----------------------------------------------------------------------------- + */ + +#include +#include + +#include "xtensa_rtos.h" +#include "esp_idf_version.h" + +#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) +#include "rom/ets_sys.h" +#include "esp_panic.h" +#include "esp_crosscore_int.h" +#else +#if CONFIG_IDF_TARGET_ESP32S2 + #include "esp32s2/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32 + #include "esp32/rom/ets_sys.h" +#endif +#include "esp_private/panic_reason.h" +#include "esp_debug_helpers.h" +#include "esp_private/crosscore_int.h" +#include "esp_log.h" +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ +#include "soc/cpu.h" + +#include "FreeRTOS.h" +#include "task.h" + +#include "esp_heap_caps.h" + +#include "esp_intr_alloc.h" + +/* Defined in portasm.h */ +extern void _frxt_tick_timer_init( void ); + +/* Defined in xtensa_context.S */ +extern void _xt_coproc_init( void ); + + +#if CONFIG_FREERTOS_CORETIMER_0 + #define SYSTICK_INTR_ID ( ETS_INTERNAL_TIMER0_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF ) +#endif +#if CONFIG_FREERTOS_CORETIMER_1 + #define SYSTICK_INTR_ID ( ETS_INTERNAL_TIMER1_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF ) +#endif + +/*-----------------------------------------------------------*/ + +unsigned port_xSchedulerRunning[ portNUM_PROCESSORS ] = { 0 }; /* Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting */ +unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 }; /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */ + +/*-----------------------------------------------------------*/ + +/* User exception dispatcher when exiting */ +void _xt_user_exit( void ); + +#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER +/* Wrapper to allow task functions to return (increases stack overhead by 16 bytes) */ + static void vPortTaskWrapper( TaskFunction_t pxCode, + void * pvParameters ) + { + pxCode( pvParameters ); + /*FreeRTOS tasks should not return. Log the task name and abort. */ + char * pcTaskName = pcTaskGetTaskName( NULL ); + ESP_LOGE( "FreeRTOS", "FreeRTOS Task \"%s\" should not return, Aborting now!", pcTaskName ); + abort(); + } +#endif /* if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER */ + +/* + * Stack initialization + */ +/* *INDENT-OFF* */ +#if portUSING_MPU_WRAPPERS + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +#endif +/* *INDENT-ON* */ +{ + StackType_t * sp, * tp; + XtExcFrame * frame; + + #if XCHAL_CP_NUM > 0 + uint32_t * p; + #endif + + /* Create interrupt stack frame aligned to 16 byte boundary */ + sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - XT_STK_FRMSZ ) & ~0xf ); + + /* Clear the entire frame (do not use memset() because we don't depend on C library) */ + for( tp = sp; tp <= pxTopOfStack; ++tp ) + { + *tp = 0; + } + + frame = ( XtExcFrame * ) sp; + + /* Explicitly initialize certain saved registers */ + #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER + frame->pc = ( UBaseType_t ) vPortTaskWrapper; /* task wrapper */ + #else + frame->pc = ( UBaseType_t ) pxCode; /* task entrypoint */ + #endif + frame->a0 = 0; /* to terminate GDB backtrace */ + frame->a1 = ( UBaseType_t ) sp + XT_STK_FRMSZ; /* physical top of stack frame */ + frame->exit = ( UBaseType_t ) _xt_user_exit; /* user exception exit dispatcher */ + + /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */ + /* Also set entry point argument parameter. */ + #ifdef __XTENSA_CALL0_ABI__ + #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER + frame->a2 = ( UBaseType_t ) pxCode; + frame->a3 = ( UBaseType_t ) pvParameters; + #else + frame->a2 = ( UBaseType_t ) pvParameters; + #endif + frame->ps = PS_UM | PS_EXCM; + #else + /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */ + #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER + frame->a6 = ( UBaseType_t ) pxCode; + frame->a7 = ( UBaseType_t ) pvParameters; + #else + frame->a6 = ( UBaseType_t ) pvParameters; + #endif + frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC( 1 ); + #endif /* ifdef __XTENSA_CALL0_ABI__ */ + + #ifdef XT_USE_SWPRI + /* Set the initial virtual priority mask value to all 1's. */ + frame->vpri = 0xFFFFFFFF; + #endif + + #if XCHAL_CP_NUM > 0 + /* Init the coprocessor save area (see xtensa_context.h) */ + + /* No access to TCB here, so derive indirectly. Stack growth is top to bottom. + * //p = (uint32_t *) xMPUSettings->coproc_area; + */ + p = ( uint32_t * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE ) & ~0xf ); + configASSERT( ( uint32_t ) p >= frame->a1 ); + p[ 0 ] = 0; + p[ 1 ] = 0; + p[ 2 ] = ( ( ( uint32_t ) p ) + 12 + XCHAL_TOTAL_SA_ALIGN - 1 ) & -XCHAL_TOTAL_SA_ALIGN; + #endif + + return sp; +} + +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the Xtensa port will get stopped. If required simply + * disable the tick interrupt here. */ +} + +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored */ + + #if XCHAL_CP_NUM > 0 + /* Initialize co-processor management for tasks. Leave CPENABLE alone. */ + _xt_coproc_init(); + #endif + + /* Init the tick divisor value */ + _xt_tick_divisor_init(); + + /* Setup the hardware to generate the tick. */ + _frxt_tick_timer_init(); + + port_xSchedulerRunning[ xPortGetCoreID() ] = 1; + + /* Cannot be directly called from C; never returns */ + __asm__ volatile ( "call0 _frxt_dispatch\n" ); + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortSysTickHandler( void ) +{ + BaseType_t ret; + unsigned interruptMask; + + portbenchmarkIntLatency(); + traceISR_ENTER( SYSTICK_INTR_ID ); + + /* Interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY must be + * disabled before calling xTaskIncrementTick as it access the + * kernel lists. */ + interruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + ret = xTaskIncrementTick(); + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( interruptMask ); + + if( ret != pdFALSE ) + { + portYIELD_FROM_ISR(); + } + else + { + traceISR_EXIT(); + } + + return ret; +} + + +void vPortYieldOtherCore( BaseType_t coreid ) +{ + esp_crosscore_int_send_yield( coreid ); +} + +/*-----------------------------------------------------------*/ + +/* + * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area. + */ +#if portUSING_MPU_WRAPPERS + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t usStackDepth ) + { + #if XCHAL_CP_NUM > 0 + xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 )); + xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); + xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf ); + + + /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to + * clear the stack area after we return. This is done in pxPortInitialiseStack(). + */ + #endif + } + + void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings ) + { + /* If task has live floating point registers somewhere, release them */ + _xt_coproc_release( xMPUSettings->coproc_area ); + } + +#endif /* if portUSING_MPU_WRAPPERS */ + +/* + * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs + * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway. + */ +BaseType_t xPortInIsrContext() +{ + unsigned int irqStatus; + BaseType_t ret; + + irqStatus = portENTER_CRITICAL_NESTED(); + ret = ( port_interruptNesting[ xPortGetCoreID() ] != 0 ); + portEXIT_CRITICAL_NESTED( irqStatus ); + return ret; +} + +/* + * This function will be called in High prio ISRs. Returns true if the current core was in ISR context + * before calling into high prio ISR context. + */ +BaseType_t IRAM_ATTR xPortInterruptedFromISRContext() +{ + return( port_interruptNesting[ xPortGetCoreID() ] != 0 ); +} + +void vPortAssertIfInISR() +{ + if( xPortInIsrContext() ) + { + ets_printf( "core=%d port_interruptNesting=%d\n\n", xPortGetCoreID(), port_interruptNesting[ xPortGetCoreID() ] ); + } + + configASSERT( !xPortInIsrContext() ); +} + +/* + * For kernel use: Initialize a per-CPU mux. Mux will be initialized unlocked. + */ +void vPortCPUInitializeMutex( portMUX_TYPE * mux ) +{ + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + ets_printf( "Initializing mux %p\n", mux ); + mux->lastLockedFn = "(never locked)"; + mux->lastLockedLine = -1; + #endif + mux->owner = portMUX_FREE_VAL; + mux->count = 0; +} + +#include "portmux_impl.h" + +/* + * For kernel use: Acquire a per-CPU mux. Spinlocks, so don't hold on to these muxes for too long. + */ +#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + void vPortCPUAcquireMutex( portMUX_TYPE * mux, + const char * fnName, + int line ) + { + unsigned int irqStatus = portENTER_CRITICAL_NESTED(); + + vPortCPUAcquireMutexIntsDisabled( mux, portMUX_NO_TIMEOUT, fnName, line ); + portEXIT_CRITICAL_NESTED( irqStatus ); + } + + bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux, + int timeout_cycles, + const char * fnName, + int line ) + { + unsigned int irqStatus = portENTER_CRITICAL_NESTED(); + bool result = vPortCPUAcquireMutexIntsDisabled( mux, timeout_cycles, fnName, line ); + + portEXIT_CRITICAL_NESTED( irqStatus ); + return result; + } + +#else /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ + void vPortCPUAcquireMutex( portMUX_TYPE * mux ) + { + unsigned int irqStatus = portENTER_CRITICAL_NESTED(); + + vPortCPUAcquireMutexIntsDisabled( mux, portMUX_NO_TIMEOUT ); + portEXIT_CRITICAL_NESTED( irqStatus ); + } + + bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux, + int timeout_cycles ) + { + unsigned int irqStatus = portENTER_CRITICAL_NESTED(); + bool result = vPortCPUAcquireMutexIntsDisabled( mux, timeout_cycles ); + + portEXIT_CRITICAL_NESTED( irqStatus ); + return result; + } +#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ + + +/* + * For kernel use: Release a per-CPU mux + * + * Mux must be already locked by this core + */ +#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + void vPortCPUReleaseMutex( portMUX_TYPE * mux, + const char * fnName, + int line ) + { + unsigned int irqStatus = portENTER_CRITICAL_NESTED(); + + vPortCPUReleaseMutexIntsDisabled( mux, fnName, line ); + portEXIT_CRITICAL_NESTED( irqStatus ); + } +#else + void vPortCPUReleaseMutex( portMUX_TYPE * mux ) + { + unsigned int irqStatus = portENTER_CRITICAL_NESTED(); + + vPortCPUReleaseMutexIntsDisabled( mux ); + portEXIT_CRITICAL_NESTED( irqStatus ); + } +#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ + +void vPortSetStackWatchpoint( void * pxStackStart ) +{ + /*Set watchpoint 1 to watch the last 32 bytes of the stack. */ + /*Unfortunately, the Xtensa watchpoints can't set a watchpoint on a random [base - base+n] region because */ + /*the size works by masking off the lowest address bits. For that reason, we futz a bit and watch the lowest 32 */ + /*bytes of the stack we can actually watch. In general, this can cause the watchpoint to be triggered at most */ + /*28 bytes early. The value 32 is chosen because it's larger than the stack canary, which in FreeRTOS is 20 bytes. */ + /*This way, we make sure we trigger before/when the stack canary is corrupted, not after. */ + int addr = ( int ) pxStackStart; + + addr = ( addr + 31 ) & ( ~31 ); + esp_set_watchpoint( 1, ( char * ) addr, 32, ESP_WATCHPOINT_STORE ); +} + +#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) + +#if defined( CONFIG_SPIRAM_SUPPORT ) + +/* + * Compare & set (S32C1) does not work in external RAM. Instead, this routine uses a mux (in internal memory) to fake it. + */ + static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED; + + void uxPortCompareSetExtram( volatile uint32_t * addr, + uint32_t compare, + uint32_t * set ) + { + uint32_t prev; + + uint32_t oldlevel = portENTER_CRITICAL_NESTED(); + + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ ); + #else + vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT ); + #endif + prev = *addr; + + if( prev == compare ) + { + *addr = *set; + } + + *set = prev; + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ ); + #else + vPortCPUReleaseMutexIntsDisabled( &extram_mux ); + #endif + + portEXIT_CRITICAL_NESTED(oldlevel); + } +#endif //defined(CONFIG_SPIRAM_SUPPORT) + +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ + + +uint32_t xPortGetTickRateHz( void ) +{ + return ( uint32_t ) configTICK_RATE_HZ; +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S new file mode 100644 index 0000000..27c4ff1 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S @@ -0,0 +1,689 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "xtensa_rtos.h" +#include "sdkconfig.h" +#include "esp_idf_version.h" + +#define TOPOFSTACK_OFFS 0x00 /* StackType_t *pxTopOfStack */ +#define CP_TOPOFSTACK_OFFS 0x04 /* xMPU_SETTINGS.coproc_area */ + +.extern pxCurrentTCB + +/* +******************************************************************************* +* Interrupt stack. The size of the interrupt stack is determined by the config +* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h +******************************************************************************* +*/ + + .data + .align 16 + .global port_IntStack + .global port_IntStackTop + .global port_switch_flag +port_IntStack: + .space configISR_STACK_SIZE*portNUM_PROCESSORS /* This allocates stacks for each individual CPU. */ +port_IntStackTop: + .word 0 +port_switch_flag: + .space portNUM_PROCESSORS*4 /* One flag for each individual CPU. */ + + .text + +/* +******************************************************************************* +* _frxt_setup_switch +* void _frxt_setup_switch(void); +* +* Sets an internal flag indicating that a task switch is required on return +* from interrupt handling. +* +******************************************************************************* +*/ + .global _frxt_setup_switch + .type _frxt_setup_switch,@function + .align 4 +_frxt_setup_switch: + + ENTRY(16) + + getcoreid a3 + movi a2, port_switch_flag + addx4 a2, a3, a2 + + movi a3, 1 + s32i a3, a2, 0 + + RET(16) + + + + + + +/* +******************************************************************************* +* _frxt_int_enter +* void _frxt_int_enter(void) +* +* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for +* freeRTOS. Saves the rest of the interrupt context (not already saved). +* May only be called from assembly code by the 'call0' instruction, with +* interrupts disabled. +* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h. +* +******************************************************************************* +*/ + .globl _frxt_int_enter + .type _frxt_int_enter,@function + .align 4 +_frxt_int_enter: + + /* Save a12-13 in the stack frame as required by _xt_context_save. */ + s32i a12, a1, XT_STK_A12 + s32i a13, a1, XT_STK_A13 + + /* Save return address in a safe place (free a0). */ + mov a12, a0 + + /* Save the rest of the interrupted context (preserves A12-13). */ + call0 _xt_context_save + + /* + Save interrupted task's SP in TCB only if not nesting. + Manage nesting directly rather than call the generic IntEnter() + (in windowed ABI we can't call a C function here anyway because PS.EXCM is still set). + */ + getcoreid a4 + movi a2, port_xSchedulerRunning + addx4 a2, a4, a2 + movi a3, port_interruptNesting + addx4 a3, a4, a3 + l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */ + beqz a2, 1f /* scheduler not running, no tasks */ + l32i a2, a3, 0 /* a2 = port_interruptNesting */ + addi a2, a2, 1 /* increment nesting count */ + s32i a2, a3, 0 /* save nesting count */ + bnei a2, 1, .Lnested /* !=0 before incr, so nested */ + + movi a2, pxCurrentTCB + addx4 a2, a4, a2 + l32i a2, a2, 0 /* a2 = current TCB */ + beqz a2, 1f + s32i a1, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */ + movi a1, port_IntStack+configISR_STACK_SIZE /* a1 = top of intr stack for CPU 0 */ + movi a2, configISR_STACK_SIZE /* add configISR_STACK_SIZE * cpu_num to arrive at top of stack for cpu_num */ + mull a2, a4, a2 + add a1, a1, a2 /* for current proc */ + + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef CONFIG_FREERTOS_FPU_IN_ISR + #if XCHAL_CP_NUM > 0 + rsr a3, CPENABLE /* Restore thread scope CPENABLE */ + addi sp, sp,-4 /* ISR will manage FPU coprocessor by forcing */ + s32i a3, a1, 0 /* its trigger */ + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + +.Lnested: +1: + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef CONFIG_FREERTOS_FPU_IN_ISR + #if XCHAL_CP_NUM > 0 + movi a3, 0 /* whilst ISRs pending keep CPENABLE exception active */ + wsr a3, CPENABLE + rsync + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + mov a0, a12 /* restore return addr and return */ + ret + +/* +******************************************************************************* +* _frxt_int_exit +* void _frxt_int_exit(void) +* +* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for +* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context +* switching, restore the (possibly) new task's context, and return to the +* exit dispatcher saved in the task's stack frame at XT_STK_EXIT. +* May only be called from assembly code by the 'call0' instruction. Does not +* return to caller. +* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h. +* +******************************************************************************* +*/ + .globl _frxt_int_exit + .type _frxt_int_exit,@function + .align 4 +_frxt_int_exit: + + getcoreid a4 + movi a2, port_xSchedulerRunning + addx4 a2, a4, a2 + movi a3, port_interruptNesting + addx4 a3, a4, a3 + rsil a0, XCHAL_EXCM_LEVEL /* lock out interrupts */ + l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */ + beqz a2, .Lnoswitch /* scheduler not running, no tasks */ + l32i a2, a3, 0 /* a2 = port_interruptNesting */ + addi a2, a2, -1 /* decrement nesting count */ + s32i a2, a3, 0 /* save nesting count */ + bnez a2, .Lnesting /* !=0 after decr so still nested */ + + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef CONFIG_FREERTOS_FPU_IN_ISR + #if XCHAL_CP_NUM > 0 + l32i a3, sp, 0 /* Grab last CPENABLE before leave ISR */ + addi sp, sp, 4 + wsr a3, CPENABLE + rsync /* ensure CPENABLE was modified */ + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + movi a2, pxCurrentTCB + addx4 a2, a4, a2 + l32i a2, a2, 0 /* a2 = current TCB */ + beqz a2, 1f /* no task ? go to dispatcher */ + l32i a1, a2, TOPOFSTACK_OFFS /* SP = pxCurrentTCB->pxTopOfStack */ + + movi a2, port_switch_flag /* address of switch flag */ + addx4 a2, a4, a2 /* point to flag for this cpu */ + l32i a3, a2, 0 /* a3 = port_switch_flag */ + beqz a3, .Lnoswitch /* flag = 0 means no switch reqd */ + movi a3, 0 + s32i a3, a2, 0 /* zero out the flag for next time */ + +1: + /* + Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption. + However a12-13 were already saved by _frxt_int_enter(). + */ + #ifdef __XTENSA_CALL0_ABI__ + s32i a14, a1, XT_STK_A14 + s32i a15, a1, XT_STK_A15 + #endif + + #ifdef __XTENSA_CALL0_ABI__ + call0 vPortYieldFromInt /* call dispatch inside the function; never returns */ + #else + call4 vPortYieldFromInt /* this one returns */ + call0 _frxt_dispatch /* tail-call dispatcher */ + /* Never returns here. */ + #endif + +.Lnoswitch: + /* + If we came here then about to resume the interrupted task. + */ + +.Lnesting: + /* + We come here only if there was no context switch, that is if this + is a nested interrupt, or the interrupted task was not preempted. + In either case there's no need to load the SP. + */ + + /* Restore full context from interrupt stack frame */ + call0 _xt_context_restore + + /* + Must return via the exit dispatcher corresponding to the entrypoint from which + this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt + stack frame is deallocated in the exit dispatcher. + */ + l32i a0, a1, XT_STK_EXIT + ret + + +/* +********************************************************************************************************** +* _frxt_timer_int +* void _frxt_timer_int(void) +* +* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS. +* Called every timer interrupt. +* Manages the tick timer and calls xPortSysTickHandler() every tick. +* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h. +* +* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance. +* +********************************************************************************************************** +*/ + .globl _frxt_timer_int + .type _frxt_timer_int,@function + .align 4 +_frxt_timer_int: + + /* + Xtensa timers work by comparing a cycle counter with a preset value. Once the match occurs + an interrupt is generated, and the handler has to set a new cycle count into the comparator. + To avoid clock drift due to interrupt latency, the new cycle count is computed from the old, + not the time the interrupt was serviced. However if a timer interrupt is ever serviced more + than one tick late, it is necessary to process multiple ticks until the new cycle count is + in the future, otherwise the next timer interrupt would not occur until after the cycle + counter had wrapped (2^32 cycles later). + + do { + ticks++; + old_ccompare = read_ccompare_i(); + write_ccompare_i( old_ccompare + divisor ); + service one tick; + diff = read_ccount() - old_ccompare; + } while ( diff > divisor ); + */ + + ENTRY(16) + + #ifdef CONFIG_PM_TRACE + movi a6, 1 /* = ESP_PM_TRACE_TICK */ + getcoreid a7 + call4 esp_pm_trace_enter + #endif // CONFIG_PM_TRACE + +.L_xt_timer_int_catchup: + + /* Update the timer comparator for the next tick. */ + #ifdef XT_CLOCK_FREQ + movi a2, XT_TICK_DIVISOR /* a2 = comparator increment */ + #else + movi a3, _xt_tick_divisor + l32i a2, a3, 0 /* a2 = comparator increment */ + #endif + rsr a3, XT_CCOMPARE /* a3 = old comparator value */ + add a4, a3, a2 /* a4 = new comparator value */ + wsr a4, XT_CCOMPARE /* update comp. and clear interrupt */ + esync + + #ifdef __XTENSA_CALL0_ABI__ + /* Preserve a2 and a3 across C calls. */ + s32i a2, sp, 4 + s32i a3, sp, 8 + #endif + + /* Call the FreeRTOS tick handler (see port.c). */ + #ifdef __XTENSA_CALL0_ABI__ + call0 xPortSysTickHandler + #else + call4 xPortSysTickHandler + #endif + + #ifdef __XTENSA_CALL0_ABI__ + /* Restore a2 and a3. */ + l32i a2, sp, 4 + l32i a3, sp, 8 + #endif + + /* Check if we need to process more ticks to catch up. */ + esync /* ensure comparator update complete */ + rsr a4, CCOUNT /* a4 = cycle count */ + sub a4, a4, a3 /* diff = ccount - old comparator */ + blt a2, a4, .L_xt_timer_int_catchup /* repeat while diff > divisor */ + +#ifdef CONFIG_PM_TRACE + movi a6, 1 /* = ESP_PM_TRACE_TICK */ + getcoreid a7 + call4 esp_pm_trace_exit +#endif // CONFIG_PM_TRACE + + RET(16) + + /* +********************************************************************************************************** +* _frxt_tick_timer_init +* void _frxt_tick_timer_init(void) +* +* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called). +* Callable from C (obeys ABI conventions on entry). +* +********************************************************************************************************** +*/ + .globl _frxt_tick_timer_init + .type _frxt_tick_timer_init,@function + .align 4 +_frxt_tick_timer_init: + + ENTRY(16) + + + /* Set up the periodic tick timer (assume enough time to complete init). */ + #ifdef XT_CLOCK_FREQ + movi a3, XT_TICK_DIVISOR + #else + movi a2, _xt_tick_divisor + l32i a3, a2, 0 + #endif + rsr a2, CCOUNT /* current cycle count */ + add a2, a2, a3 /* time of first timer interrupt */ + wsr a2, XT_CCOMPARE /* set the comparator */ + + /* + Enable the timer interrupt at the device level. Don't write directly + to the INTENABLE register because it may be virtualized. + */ + #ifdef __XTENSA_CALL0_ABI__ + movi a2, XT_TIMER_INTEN + call0 xt_ints_on + #else + movi a6, XT_TIMER_INTEN + call4 xt_ints_on + #endif + + RET(16) + +/* +********************************************************************************************************** +* DISPATCH THE HIGH READY TASK +* void _frxt_dispatch(void) +* +* Switch context to the highest priority ready task, restore its state and dispatch control to it. +* +* This is a common dispatcher that acts as a shared exit path for all the context switch functions +* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher +* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ). +* +* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see +* comments on stack frames in xtensa_context.h). This function restores the state accordingly. +* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear. +* If restoring a task that was preempted, restores all state including the task's CPENABLE. +* +* Entry: +* pxCurrentTCB points to the TCB of the task to suspend, +* Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction. +* +* Exit: +* If incoming task called vPortYield() (solicited), this function returns as if from vPortYield(). +* If incoming task was preempted by an interrupt, this function jumps to exit dispatcher. +* +********************************************************************************************************** +*/ + .globl _frxt_dispatch + .type _frxt_dispatch,@function + .align 4 +_frxt_dispatch: + + #ifdef __XTENSA_CALL0_ABI__ + call0 vTaskSwitchContext // Get next TCB to resume + movi a2, pxCurrentTCB + getcoreid a3 + addx4 a2, a3, a2 + #else + call4 vTaskSwitchContext // Get next TCB to resume + movi a2, pxCurrentTCB + getcoreid a3 + addx4 a2, a3, a2 + #endif + l32i a3, a2, 0 + l32i sp, a3, TOPOFSTACK_OFFS /* SP = next_TCB->pxTopOfStack; */ + s32i a3, a2, 0 + + /* Determine the type of stack frame. */ + l32i a2, sp, XT_STK_EXIT /* exit dispatcher or solicited flag */ + bnez a2, .L_frxt_dispatch_stk + +.L_frxt_dispatch_sol: + + /* Solicited stack frame. Restore minimal context and return from vPortYield(). */ + l32i a3, sp, XT_SOL_PS + #ifdef __XTENSA_CALL0_ABI__ + l32i a12, sp, XT_SOL_A12 + l32i a13, sp, XT_SOL_A13 + l32i a14, sp, XT_SOL_A14 + l32i a15, sp, XT_SOL_A15 + #endif + l32i a0, sp, XT_SOL_PC + #if XCHAL_CP_NUM > 0 + /* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */ + rsync + #endif + /* As soons as PS is restored, interrupts can happen. No need to sync PS. */ + wsr a3, PS + #ifdef __XTENSA_CALL0_ABI__ + addi sp, sp, XT_SOL_FRMSZ + ret + #else + retw + #endif + +.L_frxt_dispatch_stk: + + #if XCHAL_CP_NUM > 0 + /* Restore CPENABLE from task's co-processor save area. */ + movi a3, pxCurrentTCB /* cp_state = */ + getcoreid a2 + addx4 a3, a2, a3 + l32i a3, a3, 0 + l32i a2, a3, CP_TOPOFSTACK_OFFS /* StackType_t *pxStack; */ + l16ui a3, a2, XT_CPENABLE /* CPENABLE = cp_state->cpenable; */ + wsr a3, CPENABLE + #endif + + /* Interrupt stack frame. Restore full context and return to exit dispatcher. */ + call0 _xt_context_restore + + /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */ + #ifdef __XTENSA_CALL0_ABI__ + l32i a14, sp, XT_STK_A14 + l32i a15, sp, XT_STK_A15 + #endif + + #if XCHAL_CP_NUM > 0 + /* Ensure wsr.CPENABLE has completed. */ + rsync + #endif + + /* + Must return via the exit dispatcher corresponding to the entrypoint from which + this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt + stack frame is deallocated in the exit dispatcher. + */ + l32i a0, sp, XT_STK_EXIT + ret + + +/* +********************************************************************************************************** +* PERFORM A SOLICTED CONTEXT SWITCH (from a task) +* void vPortYield(void) +* +* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE, +* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch +* +* At Entry: +* pxCurrentTCB points to the TCB of the task to suspend +* Callable from C (obeys ABI conventions on entry). +* +* Does not return to caller. +* +********************************************************************************************************** +*/ + .globl vPortYield + .type vPortYield,@function + .align 4 +vPortYield: + + #ifdef __XTENSA_CALL0_ABI__ + addi sp, sp, -XT_SOL_FRMSZ + #else + entry sp, XT_SOL_FRMSZ + #endif + + rsr a2, PS + s32i a0, sp, XT_SOL_PC + s32i a2, sp, XT_SOL_PS + #ifdef __XTENSA_CALL0_ABI__ + s32i a12, sp, XT_SOL_A12 /* save callee-saved registers */ + s32i a13, sp, XT_SOL_A13 + s32i a14, sp, XT_SOL_A14 + s32i a15, sp, XT_SOL_A15 + #else + /* Spill register windows. Calling xthal_window_spill() causes extra */ + /* spills and reloads, so we will set things up to call the _nw version */ + /* instead to save cycles. */ + movi a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK) /* spills a4-a7 if needed */ + and a2, a2, a6 /* clear WOE, INTLEVEL */ + addi a2, a2, XCHAL_EXCM_LEVEL /* set INTLEVEL */ + wsr a2, PS + rsync + call0 xthal_window_spill_nw + l32i a2, sp, XT_SOL_PS /* restore PS */ + wsr a2, PS + #endif + + rsil a2, XCHAL_EXCM_LEVEL /* disable low/med interrupts */ + + #if XCHAL_CP_NUM > 0 + /* Save coprocessor callee-saved state (if any). At this point CPENABLE */ + /* should still reflect which CPs were in use (enabled). */ + call0 _xt_coproc_savecs + #endif + + movi a2, pxCurrentTCB + getcoreid a3 + addx4 a2, a3, a2 + l32i a2, a2, 0 /* a2 = pxCurrentTCB */ + movi a3, 0 + s32i a3, sp, XT_SOL_EXIT /* 0 to flag as solicited frame */ + s32i sp, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */ + + #if XCHAL_CP_NUM > 0 + /* Clear CPENABLE, also in task's co-processor state save area. */ + l32i a2, a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state */ + movi a3, 0 + wsr a3, CPENABLE + beqz a2, 1f + s16i a3, a2, XT_CPENABLE /* clear saved cpenable */ +1: + #endif + + /* Tail-call dispatcher. */ + call0 _frxt_dispatch + /* Never reaches here. */ + + +/* +********************************************************************************************************** +* PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt) +* void vPortYieldFromInt(void) +* +* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher +* _frxt_dispatch() to perform the actual context switch. +* +* At Entry: +* Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack. +* pxCurrentTCB points to the TCB of the task to suspend, +* Callable from C (obeys ABI conventions on entry). +* +* At Exit: +* Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry. +* Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller. +* +********************************************************************************************************** +*/ + .globl vPortYieldFromInt + .type vPortYieldFromInt,@function + .align 4 +vPortYieldFromInt: + + ENTRY(16) + + #if XCHAL_CP_NUM > 0 + /* Save CPENABLE in task's co-processor save area, and clear CPENABLE. */ + movi a3, pxCurrentTCB /* cp_state = */ + getcoreid a2 + addx4 a3, a2, a3 + l32i a3, a3, 0 + + l32i a2, a3, CP_TOPOFSTACK_OFFS + + rsr a3, CPENABLE + s16i a3, a2, XT_CPENABLE /* cp_state->cpenable = CPENABLE; */ + movi a3, 0 + wsr a3, CPENABLE /* disable all co-processors */ + #endif + + #ifdef __XTENSA_CALL0_ABI__ + /* Tail-call dispatcher. */ + call0 _frxt_dispatch + /* Never reaches here. */ + #else + RET(16) + #endif + +/* +********************************************************************************************************** +* _frxt_task_coproc_state +* void _frxt_task_coproc_state(void) +* +* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS. +* +* May only be called when a task is running, not within an interrupt handler (returns 0 in that case). +* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions. +* Returns in A15 a pointer to the base of the co-processor state save area for the current task. +* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h. +* +********************************************************************************************************** +*/ +#if XCHAL_CP_NUM > 0 + + .globl _frxt_task_coproc_state + .type _frxt_task_coproc_state,@function + .align 4 +_frxt_task_coproc_state: + + + /* We can use a3 as a scratchpad, the instances of code calling XT_RTOS_CP_STATE don't seem to need it saved. */ + getcoreid a3 + movi a15, port_xSchedulerRunning /* if (port_xSchedulerRunning */ + addx4 a15, a3,a15 + l32i a15, a15, 0 + beqz a15, 1f + movi a15, port_interruptNesting /* && port_interruptNesting == 0 */ + addx4 a15, a3, a15 + l32i a15, a15, 0 + bnez a15, 1f + + movi a15, pxCurrentTCB + addx4 a15, a3, a15 + l32i a15, a15, 0 /* && pxCurrentTCB != 0) { */ + + beqz a15, 2f + l32i a15, a15, CP_TOPOFSTACK_OFFS + ret + +1: movi a15, 0 +2: ret + +#endif /* XCHAL_CP_NUM > 0 */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h new file mode 100644 index 0000000..98d924f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This header exists for performance reasons, in order to inline the + * implementation of vPortCPUAcquireMutexIntsDisabled and + * vPortCPUReleaseMutexIntsDisabled into the + * vTaskEnterCritical/vTaskExitCritical functions in task.c as well as the + * vPortCPUAcquireMutex/vPortCPUReleaseMutex implementations. + * + * Normally this kind of performance hack is over the top, but + * vTaskEnterCritical/vTaskExitCritical is called a great + * deal by FreeRTOS internals. + * + * It should be #included by freertos port.c or tasks.c, in esp-idf. + * + * The way it works is that it essentially uses portmux_impl.inc.h as a + * generator template of sorts. When no external memory is used, this + * template is only used to generate the vPortCPUAcquireMutexIntsDisabledInternal + * and vPortCPUReleaseMutexIntsDisabledInternal functions, which use S32C1 to + * do an atomic compare & swap. When external memory is used the functions + * vPortCPUAcquireMutexIntsDisabledExtram and vPortCPUReleaseMutexIntsDisabledExtram + * are also generated, which use uxPortCompareSetExtram to fake the S32C1 instruction. + * The wrapper functions vPortCPUAcquireMutexIntsDisabled and + * vPortCPUReleaseMutexIntsDisabled will then use the appropriate function to do the + * actual lock/unlock. + */ +#include "soc/cpu.h" +#include "portable.h" + +/* XOR one core ID with this value to get the other core ID */ +#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) +#define CORE_ID_XOR_SWAP ( CORE_ID_PRO ^ CORE_ID_APP ) +#else +#define CORE_ID_REGVAL_XOR_SWAP (CORE_ID_REGVAL_PRO ^ CORE_ID_REGVAL_APP) +#endif + + + +/*Define the mux routines for use with muxes in internal RAM */ +#define PORTMUX_AQUIRE_MUX_FN_NAME vPortCPUAcquireMutexIntsDisabledInternal +#define PORTMUX_RELEASE_MUX_FN_NAME vPortCPUReleaseMutexIntsDisabledInternal +#define PORTMUX_COMPARE_SET_FN_NAME uxPortCompareSet +#include "portmux_impl.inc.h" +#undef PORTMUX_AQUIRE_MUX_FN_NAME +#undef PORTMUX_RELEASE_MUX_FN_NAME +#undef PORTMUX_COMPARE_SET_FN_NAME + + +#if defined( CONFIG_SPIRAM_SUPPORT ) + + #define PORTMUX_AQUIRE_MUX_FN_NAME vPortCPUAcquireMutexIntsDisabledExtram + #define PORTMUX_RELEASE_MUX_FN_NAME vPortCPUReleaseMutexIntsDisabledExtram + #define PORTMUX_COMPARE_SET_FN_NAME uxPortCompareSetExtram + #include "portmux_impl.inc.h" + #undef PORTMUX_AQUIRE_MUX_FN_NAME + #undef PORTMUX_RELEASE_MUX_FN_NAME + #undef PORTMUX_COMPARE_SET_FN_NAME + +#endif + + +#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + #define PORTMUX_AQUIRE_MUX_FN_ARGS portMUX_TYPE * mux, int timeout_cycles, const char * fnName, int line + #define PORTMUX_RELEASE_MUX_FN_ARGS portMUX_TYPE * mux, const char * fnName, int line + #define PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( x ) x, timeout_cycles, fnName, line + #define PORTMUX_RELEASE_MUX_FN_CALL_ARGS( x ) x, fnName, line +#else + #define PORTMUX_AQUIRE_MUX_FN_ARGS portMUX_TYPE * mux, int timeout_cycles + #define PORTMUX_RELEASE_MUX_FN_ARGS portMUX_TYPE * mux + #define PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( x ) x, timeout_cycles + #define PORTMUX_RELEASE_MUX_FN_CALL_ARGS( x ) x +#endif + + +static inline bool __attribute__( ( always_inline ) ) vPortCPUAcquireMutexIntsDisabled( PORTMUX_AQUIRE_MUX_FN_ARGS ) +{ + #if defined( CONFIG_SPIRAM_SUPPORT ) + if( esp_ptr_external_ram( mux ) ) + { + return vPortCPUAcquireMutexIntsDisabledExtram( PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( mux ) ); + } + #endif + return vPortCPUAcquireMutexIntsDisabledInternal( PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( mux ) ); +} + + +static inline void vPortCPUReleaseMutexIntsDisabled( PORTMUX_RELEASE_MUX_FN_ARGS ) +{ + #if defined( CONFIG_SPIRAM_SUPPORT ) + if( esp_ptr_external_ram( mux ) ) + { + vPortCPUReleaseMutexIntsDisabledExtram( PORTMUX_RELEASE_MUX_FN_CALL_ARGS( mux ) ); + return; + } + #endif + vPortCPUReleaseMutexIntsDisabledInternal( PORTMUX_RELEASE_MUX_FN_CALL_ARGS( mux ) ); +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h new file mode 100644 index 0000000..9d7c826 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h @@ -0,0 +1,195 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +/* + * Warning: funky preprocessor hackery ahead. Including these headers will generate two + * functions, which names are defined by the preprocessor macros + * PORTMUX_AQUIRE_MUX_FN_NAME and PORTMUX_RELEASE_MUX_FN_NAME. In order to do the compare + * and exchange function, they will use whatever PORTMUX_COMPARE_SET_FN_NAME resolves to. + * + * In some scenarios, this header is included *twice* in portmux_impl.h: one time + * for the 'normal' mux code which uses a compare&exchange routine, another time + * to generate code for a second set of these routines that use a second mux + * (in internal ram) to fake a compare&exchange on a variable in external memory. + */ + + + +static inline bool __attribute__( ( always_inline ) ) +#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + PORTMUX_AQUIRE_MUX_FN_NAME( portMUX_TYPE * mux, + int timeout_cycles, + const char * fnName, + int line ) + { +#else + PORTMUX_AQUIRE_MUX_FN_NAME( portMUX_TYPE * mux, int timeout_cycles ) + { + #endif + + + #if !CONFIG_FREERTOS_UNICORE + uint32_t res; + portBASE_TYPE coreID, otherCoreID; + uint32_t ccount_start; + bool set_timeout = timeout_cycles > portMUX_NO_TIMEOUT; + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + if( !set_timeout ) + { + timeout_cycles = 10000; /* Always set a timeout in debug mode */ + set_timeout = true; + } + #endif + + if( set_timeout ) /* Timeout */ + { + RSR( CCOUNT, ccount_start ); + } + + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + uint32_t owner = mux->owner; + + #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) + if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) ) + #else + if (owner != portMUX_FREE_VAL && owner != CORE_ID_REGVAL_PRO && owner != CORE_ID_REGVAL_APP) + #endif + { + ets_printf( "ERROR: vPortCPUAcquireMutex: mux %p is uninitialized (0x%X)! Called from %s line %d.\n", mux, owner, fnName, line ); + mux->owner = portMUX_FREE_VAL; + } + #endif + + /* Spin until we own the core */ + + RSR( PRID, coreID ); + + /* Note: coreID is the full 32 bit core ID (CORE_ID_PRO/CORE_ID_APP), + * not the 0/1 value returned by xPortGetCoreID() + */ + #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) + otherCoreID = CORE_ID_XOR_SWAP ^ coreID; + #else + otherCoreID = CORE_ID_REGVAL_XOR_SWAP ^ coreID; + #endif + + do + { + /* mux->owner should be one of portMUX_FREE_VAL, CORE_ID_PRO, + * CORE_ID_APP: + * + * - If portMUX_FREE_VAL, we want to atomically set to 'coreID'. + * - If "our" coreID, we can drop through immediately. + * - If "otherCoreID", we spin here. + */ + res = coreID; + PORTMUX_COMPARE_SET_FN_NAME( &mux->owner, portMUX_FREE_VAL, &res ); + + if( res != otherCoreID ) + { + break; /* mux->owner is "our" coreID */ + } + + if( set_timeout ) + { + uint32_t ccount_now; + RSR( CCOUNT, ccount_now ); + + if( ccount_now - ccount_start > ( unsigned ) timeout_cycles ) + { + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + ets_printf( "Timeout on mux! last non-recursive lock %s line %d, curr %s line %d\n", mux->lastLockedFn, mux->lastLockedLine, fnName, line ); + ets_printf( "Owner 0x%x count %d\n", mux->owner, mux->count ); + #endif + return false; + } + } + } while( 1 ); + + assert( res == coreID || res == portMUX_FREE_VAL ); /* any other value implies memory corruption or uninitialized mux */ + assert( ( res == portMUX_FREE_VAL ) == ( mux->count == 0 ) ); /* we're first to lock iff count is zero */ + assert( mux->count < 0xFF ); /* Bad count value implies memory corruption */ + + /* now we own it, we can increment the refcount */ + mux->count++; + + + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + if( res == portMUX_FREE_VAL ) /*initial lock */ + { + mux->lastLockedFn = fnName; + mux->lastLockedLine = line; + } + else + { + ets_printf( "Recursive lock: count=%d last non-recursive lock %s line %d, curr %s line %d\n", mux->count - 1, + mux->lastLockedFn, mux->lastLockedLine, fnName, line ); + } + #endif /* CONFIG_FREERTOS_PORTMUX_DEBUG */ + #endif /* CONFIG_FREERTOS_UNICORE */ + return true; + } + +#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + static inline void PORTMUX_RELEASE_MUX_FN_NAME( portMUX_TYPE * mux, + const char * fnName, + int line ) + { +#else + static inline void PORTMUX_RELEASE_MUX_FN_NAME( portMUX_TYPE * mux ) + { + #endif + + + #if !CONFIG_FREERTOS_UNICORE + portBASE_TYPE coreID; + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + const char * lastLockedFn = mux->lastLockedFn; + int lastLockedLine = mux->lastLockedLine; + mux->lastLockedFn = fnName; + mux->lastLockedLine = line; + uint32_t owner = mux->owner; + + #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) + if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) ) + #else + if (owner != portMUX_FREE_VAL && owner != CORE_ID_REGVAL_PRO && owner != CORE_ID_REGVAL_APP) + #endif + { + ets_printf( "ERROR: vPortCPUReleaseMutex: mux %p is invalid (0x%x)!\n", mux, mux->owner ); + } + #endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ + + #if CONFIG_FREERTOS_PORTMUX_DEBUG || !defined( NDEBUG ) + RSR( PRID, coreID ); + #endif + + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + if( coreID != mux->owner ) + { + ets_printf( "ERROR: vPortCPUReleaseMutex: mux %p was already unlocked!\n", mux ); + ets_printf( "Last non-recursive unlock %s line %d, curr unlock %s line %d\n", lastLockedFn, lastLockedLine, fnName, line ); + } + #endif + + assert( coreID == mux->owner ); /* This is a mutex we didn't lock, or it's corrupt */ + + mux->count--; + + if( mux->count == 0 ) + { + mux->owner = portMUX_FREE_VAL; + } + else + { + assert( mux->count < 0x100 ); /* Indicates memory corruption */ + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG_RECURSIVE + ets_printf( "Recursive unlock: count=%d last locked %s line %d, curr %s line %d\n", mux->count, lastLockedFn, lastLockedLine, fnName, line ); + #endif + } + #endif //!CONFIG_FREERTOS_UNICORE + } diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S new file mode 100644 index 0000000..4450395 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S @@ -0,0 +1,712 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************* + + XTENSA CONTEXT SAVE AND RESTORE ROUTINES + +Low-level Call0 functions for handling generic context save and restore of +registers not specifically addressed by the interrupt vectors and handlers. +Those registers (not handled by these functions) are PC, PS, A0, A1 (SP). +Except for the calls to RTOS functions, this code is generic to Xtensa. + +Note that in Call0 ABI, interrupt handlers are expected to preserve the callee- +save regs (A12-A15), which is always the case if the handlers are coded in C. +However A12, A13 are made available as scratch registers for interrupt dispatch +code, so are presumed saved anyway, and are always restored even in Call0 ABI. +Only A14, A15 are truly handled as callee-save regs. + +Because Xtensa is a configurable architecture, this port supports all user +generated configurations (except restrictions stated in the release notes). +This is accomplished by conditional compilation using macros and functions +defined in the Xtensa HAL (hardware adaptation layer) for your configuration. +Only the processor state included in your configuration is saved and restored, +including any processor state added by user configuration options or TIE. + +*******************************************************************************/ + +/* Warn nicely if this file gets named with a lowercase .s instead of .S: */ +#define NOERROR # +NOERROR: .error "C preprocessor needed for this file: make sure its filename\ + ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option." + + +#include "xtensa_rtos.h" +#include "xtensa_context.h" +#include "esp_idf_version.h" +#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) +#include "xt_asm_utils.h" +#endif + +#ifdef XT_USE_OVLY +#include +#endif + + .text + +/******************************************************************************* + +_xt_context_save + + !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !! + +Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the +interrupt stack frame defined in xtensa_rtos.h. +Its counterpart is _xt_context_restore (which also restores A12, A13). + +Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame. +This function preserves A12 & A13 in order to provide the caller with 2 scratch +regs that need not be saved over the call to this function. The choice of which +2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw, +to avoid moving data more than necessary. Caller can assign regs accordingly. + +Entry Conditions: + A0 = Return address in caller. + A1 = Stack pointer of interrupted thread or handler ("interruptee"). + Original A12, A13 have already been saved in the interrupt stack frame. + Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the + point of interruption. + If windowed ABI, PS.EXCM = 1 (exceptions disabled). + +Exit conditions: + A0 = Return address in caller. + A1 = Stack pointer of interrupted thread or handler ("interruptee"). + A12, A13 as at entry (preserved). + If windowed ABI, PS.EXCM = 1 (exceptions disabled). + +*******************************************************************************/ + + .global _xt_context_save + .type _xt_context_save,@function + .align 4 + .literal_position + .align 4 + +_xt_context_save: + + s32i a2, sp, XT_STK_A2 + s32i a3, sp, XT_STK_A3 + s32i a4, sp, XT_STK_A4 + s32i a5, sp, XT_STK_A5 + s32i a6, sp, XT_STK_A6 + s32i a7, sp, XT_STK_A7 + s32i a8, sp, XT_STK_A8 + s32i a9, sp, XT_STK_A9 + s32i a10, sp, XT_STK_A10 + s32i a11, sp, XT_STK_A11 + + /* + Call0 ABI callee-saved regs a12-15 do not need to be saved here. + a12-13 are the caller's responsibility so it can use them as scratch. + So only need to save a14-a15 here for Windowed ABI (not Call0). + */ + #ifndef __XTENSA_CALL0_ABI__ + s32i a14, sp, XT_STK_A14 + s32i a15, sp, XT_STK_A15 + #endif + + rsr a3, SAR + s32i a3, sp, XT_STK_SAR + + #if XCHAL_HAVE_LOOPS + rsr a3, LBEG + s32i a3, sp, XT_STK_LBEG + rsr a3, LEND + s32i a3, sp, XT_STK_LEND + rsr a3, LCOUNT + s32i a3, sp, XT_STK_LCOUNT + #endif + + #ifdef XT_USE_SWPRI + /* Save virtual priority mask */ + movi a3, _xt_vpri_mask + l32i a3, a3, 0 + s32i a3, sp, XT_STK_VPRI + #endif + + #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__) + mov a9, a0 /* preserve ret addr */ + #endif + + #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifndef __XTENSA_CALL0_ABI__ + /* + To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15. + Need to save a9,12,13 temporarily (in frame temps) and recover originals. + Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow + and underflow exceptions disabled (assured by PS.EXCM == 1). + */ + s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */ + s32i a13, sp, XT_STK_TMP1 + s32i a9, sp, XT_STK_TMP2 + + /* + Save the overlay state if we are supporting overlays. Since we just saved + three registers, we can conveniently use them here. Note that as of now, + overlays only work for windowed calling ABI. + */ + #ifdef XT_USE_OVLY + l32i a9, sp, XT_STK_PC /* recover saved PC */ + _xt_overlay_get_state a9, a12, a13 + s32i a9, sp, XT_STK_OVLY /* save overlay state */ + #endif + + l32i a12, sp, XT_STK_A12 /* recover original a9,12,13 */ + l32i a13, sp, XT_STK_A13 + l32i a9, sp, XT_STK_A9 + addi sp, sp, XT_STK_FRMSZ /* restore the interruptee's SP */ + call0 xthal_window_spill_nw /* preserves only a4,5,8,9,12,13 */ + addi sp, sp, -XT_STK_FRMSZ + l32i a12, sp, XT_STK_TMP0 /* recover stuff from stack frame */ + l32i a13, sp, XT_STK_TMP1 + l32i a9, sp, XT_STK_TMP2 + #endif + #endif /* (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) */ + + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */ + s32i a13, sp, XT_STK_TMP1 + s32i a9, sp, XT_STK_TMP2 + + l32i a12, sp, XT_STK_A12 /* recover original a9,12,13 */ + l32i a13, sp, XT_STK_A13 + l32i a9, sp, XT_STK_A9 + #endif + + #if XCHAL_EXTRA_SA_SIZE > 0 + addi a2, sp, XT_STK_EXTRA /* where to save it */ + # if XCHAL_EXTRA_SA_ALIGN > 16 + movi a3, -XCHAL_EXTRA_SA_ALIGN + and a2, a2, a3 /* align dynamically >16 bytes */ + # endif + call0 xthal_save_extra_nw /* destroys a0,2,3 */ + #endif + + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifndef __XTENSA_CALL0_ABI__ + #ifdef XT_USE_OVLY + l32i a9, sp, XT_STK_PC /* recover saved PC */ + _xt_overlay_get_state a9, a12, a13 + s32i a9, sp, XT_STK_OVLY /* save overlay state */ + #endif + + /* SPILL_ALL_WINDOWS macro requires window overflow exceptions to be enabled, + * i.e. PS.EXCM cleared and PS.WOE set. + * Since we are going to clear PS.EXCM, we also need to increase INTLEVEL + * at least to XCHAL_EXCM_LEVEL. This matches that value of effective INTLEVEL + * at entry (CINTLEVEL=max(PS.INTLEVEL, XCHAL_EXCM_LEVEL) when PS.EXCM is set. + * Since WindowOverflow exceptions will trigger inside SPILL_ALL_WINDOWS, + * need to save/restore EPC1 as well. + * Note: even though a4-a15 are saved into the exception frame, we should not + * clobber them until after SPILL_ALL_WINDOWS. This is because these registers + * may contain live windows belonging to previous frames in the call stack. + * These frames will be spilled by SPILL_ALL_WINDOWS, and if the register was + * used as a temporary by this code, the temporary value would get stored + * onto the stack, instead of the real value. + */ + rsr a2, PS /* to be restored after SPILL_ALL_WINDOWS */ + movi a0, PS_INTLEVEL_MASK + and a3, a2, a0 /* get the current INTLEVEL */ + bgeui a3, XCHAL_EXCM_LEVEL, 1f /* calculate max(INTLEVEL, XCHAL_EXCM_LEVEL) */ + movi a3, XCHAL_EXCM_LEVEL +1: + movi a0, PS_UM | PS_WOE /* clear EXCM, enable window overflow, set new INTLEVEL */ + or a3, a3, a0 + wsr a3, ps + rsr a0, EPC1 /* to be restored after SPILL_ALL_WINDOWS */ + + addi sp, sp, XT_STK_FRMSZ /* restore the interruptee's SP */ + SPILL_ALL_WINDOWS + addi sp, sp, -XT_STK_FRMSZ /* return the current stack pointer and proceed with context save*/ + + + wsr a2, PS /* restore to the value at entry */ + rsync + wsr a0, EPC1 /* likewise */ + + #endif /* __XTENSA_CALL0_ABI__ */ + + l32i a12, sp, XT_STK_TMP0 /* restore the temp saved registers */ + l32i a13, sp, XT_STK_TMP1 /* our return address is there */ + l32i a9, sp, XT_STK_TMP2 + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__) + mov a0, a9 /* retrieve ret addr */ + #endif + + ret + +/******************************************************************************* + +_xt_context_restore + + !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !! + +Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0 +ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt +stack frame defined in xtensa_rtos.h . +Its counterpart is _xt_context_save (whose caller saved A12, A13). + +Caller is responsible to restore PC, PS, A0, A1 (SP). + +Entry Conditions: + A0 = Return address in caller. + A1 = Stack pointer of interrupted thread or handler ("interruptee"). + +Exit conditions: + A0 = Return address in caller. + A1 = Stack pointer of interrupted thread or handler ("interruptee"). + Other processor state except PC, PS, A0, A1 (SP), is as at the point + of interruption. + +*******************************************************************************/ + + .global _xt_context_restore + .type _xt_context_restore,@function + .align 4 + .literal_position + .align 4 +_xt_context_restore: + + #if XCHAL_EXTRA_SA_SIZE > 0 + /* + NOTE: Normally the xthal_restore_extra_nw macro only affects address + registers a2-a5. It is theoretically possible for Xtensa processor + designers to write TIE that causes more address registers to be + affected, but it is generally unlikely. If that ever happens, + more registers need to be saved/restored around this macro invocation. + Here we only assume a13 is preserved. + Future Xtensa tools releases might limit the regs that can be affected. + */ + mov a13, a0 /* preserve ret addr */ + addi a2, sp, XT_STK_EXTRA /* where to find it */ + # if XCHAL_EXTRA_SA_ALIGN > 16 + movi a3, -XCHAL_EXTRA_SA_ALIGN + and a2, a2, a3 /* align dynamically >16 bytes */ + # endif + call0 xthal_restore_extra_nw /* destroys a0,2,3,4,5 */ + mov a0, a13 /* retrieve ret addr */ + #endif + + #if XCHAL_HAVE_LOOPS + l32i a2, sp, XT_STK_LBEG + l32i a3, sp, XT_STK_LEND + wsr a2, LBEG + l32i a2, sp, XT_STK_LCOUNT + wsr a3, LEND + wsr a2, LCOUNT + #endif + + #ifdef XT_USE_OVLY + /* + If we are using overlays, this is a good spot to check if we need + to restore an overlay for the incoming task. Here we have a bunch + of registers to spare. Note that this step is going to use a few + bytes of storage below SP (SP-20 to SP-32) if an overlay is going + to be restored. + */ + l32i a2, sp, XT_STK_PC /* retrieve PC */ + l32i a3, sp, XT_STK_PS /* retrieve PS */ + l32i a4, sp, XT_STK_OVLY /* retrieve overlay state */ + l32i a5, sp, XT_STK_A1 /* retrieve stack ptr */ + _xt_overlay_check_map a2, a3, a4, a5, a6 + s32i a2, sp, XT_STK_PC /* save updated PC */ + s32i a3, sp, XT_STK_PS /* save updated PS */ + #endif + + #ifdef XT_USE_SWPRI + /* Restore virtual interrupt priority and interrupt enable */ + movi a3, _xt_intdata + l32i a4, a3, 0 /* a4 = _xt_intenable */ + l32i a5, sp, XT_STK_VPRI /* a5 = saved _xt_vpri_mask */ + and a4, a4, a5 + wsr a4, INTENABLE /* update INTENABLE */ + s32i a5, a3, 4 /* restore _xt_vpri_mask */ + #endif + + l32i a3, sp, XT_STK_SAR + l32i a2, sp, XT_STK_A2 + wsr a3, SAR + l32i a3, sp, XT_STK_A3 + l32i a4, sp, XT_STK_A4 + l32i a5, sp, XT_STK_A5 + l32i a6, sp, XT_STK_A6 + l32i a7, sp, XT_STK_A7 + l32i a8, sp, XT_STK_A8 + l32i a9, sp, XT_STK_A9 + l32i a10, sp, XT_STK_A10 + l32i a11, sp, XT_STK_A11 + + /* + Call0 ABI callee-saved regs a12-15 do not need to be restored here. + However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), + so need to be restored anyway, despite being callee-saved in Call0. + */ + l32i a12, sp, XT_STK_A12 + l32i a13, sp, XT_STK_A13 + #ifndef __XTENSA_CALL0_ABI__ + l32i a14, sp, XT_STK_A14 + l32i a15, sp, XT_STK_A15 + #endif + + ret + + +/******************************************************************************* + +_xt_coproc_init + +Initializes global co-processor management data, setting all co-processors +to "unowned". Leaves CPENABLE as it found it (does NOT clear it). + +Called during initialization of the RTOS, before any threads run. + +This may be called from normal Xtensa single-threaded application code which +might use co-processors. The Xtensa run-time initialization enables all +co-processors. They must remain enabled here, else a co-processor exception +might occur outside of a thread, which the exception handler doesn't expect. + +Entry Conditions: + Xtensa single-threaded run-time environment is in effect. + No thread is yet running. + +Exit conditions: + None. + +Obeys ABI conventions per prototype: + void _xt_coproc_init(void) + +*******************************************************************************/ + +#if XCHAL_CP_NUM > 0 + + .global _xt_coproc_init + .type _xt_coproc_init,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_init: + ENTRY0 + + /* Initialize thread co-processor ownerships to 0 (unowned). */ + movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */ + addi a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */ + movi a4, 0 /* a4 = 0 (unowned) */ +1: s32i a4, a2, 0 + addi a2, a2, 4 + bltu a2, a3, 1b + + RET0 + +#endif + + +/******************************************************************************* + +_xt_coproc_release + +Releases any and all co-processors owned by a given thread. The thread is +identified by it's co-processor state save area defined in xtensa_context.h . + +Must be called before a thread's co-proc save area is deleted to avoid +memory corruption when the exception handler tries to save the state. +May be called when a thread terminates or completes but does not delete +the co-proc save area, to avoid the exception handler having to save the +thread's co-proc state before another thread can use it (optimization). + +Needs to be called on the processor the thread was running on. Unpinned threads +won't have an entry here because they get pinned as soon they use a coprocessor. + +Entry Conditions: + A2 = Pointer to base of co-processor state save area. + +Exit conditions: + None. + +Obeys ABI conventions per prototype: + void _xt_coproc_release(void * coproc_sa_base) + +*******************************************************************************/ + +#if XCHAL_CP_NUM > 0 + + .global _xt_coproc_release + .type _xt_coproc_release,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_release: + ENTRY0 /* a2 = base of save area */ + + getcoreid a5 + movi a3, XCHAL_CP_MAX << 2 + mull a5, a5, a3 + movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */ + add a3, a3, a5 + + addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */ + movi a5, 0 /* a5 = 0 (unowned) */ + + rsil a6, XCHAL_EXCM_LEVEL /* lock interrupts */ + +1: l32i a7, a3, 0 /* a7 = owner at a3 */ + bne a2, a7, 2f /* if (coproc_sa_base == owner) */ + s32i a5, a3, 0 /* owner = unowned */ +2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */ + bltu a3, a4, 1b /* repeat until end of array */ + +3: wsr a6, PS /* restore interrupts */ + + RET0 + +#endif + + +/******************************************************************************* +_xt_coproc_savecs + +If there is a current thread and it has a coprocessor state save area, then +save all callee-saved state into this area. This function is called from the +solicited context switch handler. It calls a system-specific function to get +the coprocessor save area base address. + +Entry conditions: + - The thread being switched out is still the current thread. + - CPENABLE state reflects which coprocessors are active. + - Registers have been saved/spilled already. + +Exit conditions: + - All necessary CP callee-saved state has been saved. + - Registers a2-a7, a13-a15 have been trashed. + +Must be called from assembly code only, using CALL0. +*******************************************************************************/ +#if XCHAL_CP_NUM > 0 + + .extern _xt_coproc_sa_offset /* external reference */ + + .global _xt_coproc_savecs + .type _xt_coproc_savecs,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_savecs: + + /* At entry, CPENABLE should be showing which CPs are enabled. */ + + rsr a2, CPENABLE /* a2 = which CPs are enabled */ + beqz a2, .Ldone /* quick exit if none */ + mov a14, a0 /* save return address */ + call0 XT_RTOS_CP_STATE /* get address of CP save area */ + mov a0, a14 /* restore return address */ + beqz a15, .Ldone /* if none then nothing to do */ + s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */ + movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + +#if XCHAL_CP0_SA_SIZE + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ + xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP1_SA_SIZE + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ + xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP2_SA_SIZE + bbci.l a2, 2, 2f + l32i a14, a13, 8 + add a3, a14, a15 + xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP3_SA_SIZE + bbci.l a2, 3, 2f + l32i a14, a13, 12 + add a3, a14, a15 + xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP4_SA_SIZE + bbci.l a2, 4, 2f + l32i a14, a13, 16 + add a3, a14, a15 + xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP5_SA_SIZE + bbci.l a2, 5, 2f + l32i a14, a13, 20 + add a3, a14, a15 + xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP6_SA_SIZE + bbci.l a2, 6, 2f + l32i a14, a13, 24 + add a3, a14, a15 + xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP7_SA_SIZE + bbci.l a2, 7, 2f + l32i a14, a13, 28 + add a3, a14, a15 + xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +.Ldone: + ret +#endif + + +/******************************************************************************* +_xt_coproc_restorecs + +Restore any callee-saved coprocessor state for the incoming thread. +This function is called from coprocessor exception handling, when giving +ownership to a thread that solicited a context switch earlier. It calls a +system-specific function to get the coprocessor save area base address. + +Entry conditions: + - The incoming thread is set as the current thread. + - CPENABLE is set up correctly for all required coprocessors. + - a2 = mask of coprocessors to be restored. + +Exit conditions: + - All necessary CP callee-saved state has been restored. + - CPENABLE - unchanged. + - Registers a2-a7, a13-a15 have been trashed. + +Must be called from assembly code only, using CALL0. +*******************************************************************************/ +#if XCHAL_CP_NUM > 0 + + .global _xt_coproc_restorecs + .type _xt_coproc_restorecs,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_restorecs: + + mov a14, a0 /* save return address */ + call0 XT_RTOS_CP_STATE /* get address of CP save area */ + mov a0, a14 /* restore return address */ + beqz a15, .Ldone2 /* if none then nothing to do */ + l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */ + xor a3, a3, a2 /* clear the ones being restored */ + s32i a3, a15, XT_CP_CS_ST /* update saved CP mask */ + movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + +#if XCHAL_CP0_SA_SIZE + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ + xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP1_SA_SIZE + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ + xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP2_SA_SIZE + bbci.l a2, 2, 2f + l32i a14, a13, 8 + add a3, a14, a15 + xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP3_SA_SIZE + bbci.l a2, 3, 2f + l32i a14, a13, 12 + add a3, a14, a15 + xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP4_SA_SIZE + bbci.l a2, 4, 2f + l32i a14, a13, 16 + add a3, a14, a15 + xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP5_SA_SIZE + bbci.l a2, 5, 2f + l32i a14, a13, 20 + add a3, a14, a15 + xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP6_SA_SIZE + bbci.l a2, 6, 2f + l32i a14, a13, 24 + add a3, a14, a15 + xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP7_SA_SIZE + bbci.l a2, 7, 2f + l32i a14, a13, 28 + add a3, a14, a15 + xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +.Ldone2: + ret + +#endif + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c new file mode 100644 index 0000000..837dfbc --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c @@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************* +* +* XTENSA INITIALIZATION ROUTINES CODED IN C +* +* This file contains miscellaneous Xtensa RTOS-generic initialization functions +* that are implemented in C. +* +*******************************************************************************/ + + +#ifdef XT_BOARD + #include +#endif + +#include "xtensa_rtos.h" +#include "esp_idf_version.h" +#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) +#include "esp_clk.h" +#else +#if CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/clk.h" +#elif CONFIG_IDF_TARGET_ESP32 +#include "esp32/clk.h" +#endif +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ + +#ifdef XT_RTOS_TIMER_INT + + unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */ + + void _xt_tick_divisor_init( void ) + { + _xt_tick_divisor = esp_clk_cpu_freq() / XT_TICK_PER_SEC; + } + +/* Deprecated, to be removed */ + int xt_clock_freq( void ) + { + return esp_clk_cpu_freq(); + } + +#endif /* XT_RTOS_TIMER_INT */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c new file mode 100644 index 0000000..d1882e4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c @@ -0,0 +1,190 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************** +* Xtensa-specific interrupt and exception functions for RTOS ports. +* Also see xtensa_intr_asm.S. +******************************************************************************/ + +#include + +#include + +#include "freertos/FreeRTOS.h" +#include "freertos/xtensa_api.h" +#include "freertos/portable.h" +#include "esp_idf_version.h" + +#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) +#include "rom/ets_sys.h" +#else +#if CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32 +#include "esp32/rom/ets_sys.h" +#endif +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ + +#if XCHAL_HAVE_EXCEPTIONS + +/* Handler table is in xtensa_intr_asm.S */ + + extern xt_exc_handler _xt_exception_table[ XCHAL_EXCCAUSE_NUM * portNUM_PROCESSORS ]; + + +/* + * Default handler for unhandled exceptions. + * CHANGED: We do this in panic.c now + */ + +/*void xt_unhandled_exception(XtExcFrame *frame) */ +/*{ */ + /*exit(-1); */ +/*} */ + extern void xt_unhandled_exception( XtExcFrame * frame ); + + +/* + * This function registers a handler for the specified exception. + * The function returns the address of the previous handler. + * On error, it returns 0. + */ + xt_exc_handler xt_set_exception_handler( int n, + xt_exc_handler f ) + { + xt_exc_handler old; + + if( ( n < 0 ) || ( n >= XCHAL_EXCCAUSE_NUM ) ) + { + return 0; /* invalid exception number */ + } + + /* Convert exception number to _xt_exception_table name */ + n = n * portNUM_PROCESSORS + xPortGetCoreID(); + old = _xt_exception_table[ n ]; + + if( f ) + { + _xt_exception_table[ n ] = f; + } + else + { + _xt_exception_table[ n ] = &xt_unhandled_exception; + } + + return( ( old == &xt_unhandled_exception ) ? 0 : old ); + } + +#endif /* if XCHAL_HAVE_EXCEPTIONS */ + +#if XCHAL_HAVE_INTERRUPTS + +/* Handler table is in xtensa_intr_asm.S */ + + typedef struct xt_handler_table_entry + { + void * handler; + void * arg; + } xt_handler_table_entry; + + extern xt_handler_table_entry _xt_interrupt_table[ XCHAL_NUM_INTERRUPTS * portNUM_PROCESSORS ]; + + +/* + * Default handler for unhandled interrupts. + */ + void xt_unhandled_interrupt( void * arg ) + { + ets_printf( "Unhandled interrupt %d on cpu %d!\n", ( int ) arg, xPortGetCoreID() ); + } + + +/* + * This function registers a handler for the specified interrupt. The "arg" + * parameter specifies the argument to be passed to the handler when it is + * invoked. The function returns the address of the previous handler. + * On error, it returns 0. + */ + xt_handler xt_set_interrupt_handler( int n, + xt_handler f, + void * arg ) + { + xt_handler_table_entry * entry; + xt_handler old; + + if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) ) + { + return 0; /* invalid interrupt number */ + } + + if( Xthal_intlevel[ n ] > XCHAL_EXCM_LEVEL ) + { + return 0; /* priority level too high to safely handle in C */ + } + + /* Convert exception number to _xt_exception_table name */ + n = n * portNUM_PROCESSORS + xPortGetCoreID(); + + entry = _xt_interrupt_table + n; + old = entry->handler; + + if( f ) + { + entry->handler = f; + entry->arg = arg; + } + else + { + entry->handler = &xt_unhandled_interrupt; + entry->arg = ( void * ) n; + } + + return( ( old == &xt_unhandled_interrupt ) ? 0 : old ); + } + + #if CONFIG_SYSVIEW_ENABLE + void * xt_get_interrupt_handler_arg( int n ) + { + xt_handler_table_entry * entry; + + if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) ) + { + return 0; /* invalid interrupt number */ + } + + /* Convert exception number to _xt_exception_table name */ + n = n * portNUM_PROCESSORS + xPortGetCoreID(); + + entry = _xt_interrupt_table + n; + return entry->arg; + } + #endif /* if CONFIG_SYSVIEW_ENABLE */ + +#endif /* XCHAL_HAVE_INTERRUPTS */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr_asm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr_asm.S new file mode 100644 index 0000000..8797212 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr_asm.S @@ -0,0 +1,232 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************** + Xtensa interrupt handling data and assembly routines. + Also see xtensa_intr.c and xtensa_vectors.S. +******************************************************************************/ + +#include +#include + +#include "xtensa_context.h" +#include "FreeRTOSConfig.h" + +#if XCHAL_HAVE_INTERRUPTS + +/* +------------------------------------------------------------------------------- + INTENABLE virtualization information. +------------------------------------------------------------------------------- +*/ + + +#if XT_USE_SWPRI +/* Warning - this is not multicore-compatible. */ + .data + .global _xt_intdata + .align 8 +_xt_intdata: + .global _xt_intenable + .type _xt_intenable,@object + .size _xt_intenable,4 + .global _xt_vpri_mask + .type _xt_vpri_mask,@object + .size _xt_vpri_mask,4 + +_xt_intenable: .word 0 /* Virtual INTENABLE */ +_xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */ +#endif + +/* +------------------------------------------------------------------------------- + Table of C-callable interrupt handlers for each interrupt. Note that not all + slots can be filled, because interrupts at level > EXCM_LEVEL will not be + dispatched to a C handler by default. + + Stored as: + int 0 cpu 0 + int 0 cpu 1 + ... + int 0 cpu n + int 1 cpu 0 + int 1 cpu 1 + etc +------------------------------------------------------------------------------- +*/ + + .data + .global _xt_interrupt_table + .align 8 + +_xt_interrupt_table: + + .set i, 0 + .rept XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS + .word xt_unhandled_interrupt /* handler address */ + .word i /* handler arg (default: intnum) */ + .set i, i+1 + .endr + +#endif /* XCHAL_HAVE_INTERRUPTS */ + + +#if XCHAL_HAVE_EXCEPTIONS + +/* +------------------------------------------------------------------------------- + Table of C-callable exception handlers for each exception. Note that not all + slots will be active, because some exceptions (e.g. coprocessor exceptions) + are always handled by the OS and cannot be hooked by user handlers. + + Stored as: + exc 0 cpu 0 + exc 0 cpu 1 + ... + exc 0 cpu n + exc 1 cpu 0 + exc 1 cpu 1 + etc +------------------------------------------------------------------------------- +*/ + + .data + .global _xt_exception_table + .align 4 + +_xt_exception_table: + .rept XCHAL_EXCCAUSE_NUM * portNUM_PROCESSORS + .word xt_unhandled_exception /* handler address */ + .endr + +#endif + + +/* +------------------------------------------------------------------------------- + unsigned int xt_ints_on ( unsigned int mask ) + + Enables a set of interrupts. Does not simply set INTENABLE directly, but + computes it as a function of the current virtual priority if XT_USE_SWPRI is + enabled. + Can be called from interrupt handlers. +------------------------------------------------------------------------------- +*/ + + .text + .align 4 + .global xt_ints_on + .type xt_ints_on,@function + +xt_ints_on: + + ENTRY0 + +#if XCHAL_HAVE_INTERRUPTS +#if XT_USE_SWPRI + movi a3, 0 + movi a4, _xt_intdata + xsr a3, INTENABLE /* Disables all interrupts */ + rsync + l32i a3, a4, 0 /* a3 = _xt_intenable */ + l32i a6, a4, 4 /* a6 = _xt_vpri_mask */ + or a5, a3, a2 /* a5 = _xt_intenable | mask */ + s32i a5, a4, 0 /* _xt_intenable |= mask */ + and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */ + wsr a5, INTENABLE /* Reenable interrupts */ + mov a2, a3 /* Previous mask */ +#else + movi a3, 0 + xsr a3, INTENABLE /* Disables all interrupts */ + rsync + or a2, a3, a2 /* set bits in mask */ + wsr a2, INTENABLE /* Re-enable ints */ + rsync + mov a2, a3 /* return prev mask */ +#endif +#else + movi a2, 0 /* Return zero */ +#endif + RET0 + + .size xt_ints_on, . - xt_ints_on + + +/* +------------------------------------------------------------------------------- + unsigned int xt_ints_off ( unsigned int mask ) + + Disables a set of interrupts. Does not simply set INTENABLE directly, + but computes it as a function of the current virtual priority if XT_USE_SWPRI is + enabled. + Can be called from interrupt handlers. +------------------------------------------------------------------------------- +*/ + + .text + .align 4 + .global xt_ints_off + .type xt_ints_off,@function + +xt_ints_off: + + ENTRY0 +#if XCHAL_HAVE_INTERRUPTS +#if XT_USE_SWPRI + movi a3, 0 + movi a4, _xt_intdata + xsr a3, INTENABLE /* Disables all interrupts */ + rsync + l32i a3, a4, 0 /* a3 = _xt_intenable */ + l32i a6, a4, 4 /* a6 = _xt_vpri_mask */ + or a5, a3, a2 /* a5 = _xt_intenable | mask */ + xor a5, a5, a2 /* a5 = _xt_intenable & ~mask */ + s32i a5, a4, 0 /* _xt_intenable &= ~mask */ + and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */ + wsr a5, INTENABLE /* Reenable interrupts */ + mov a2, a3 /* Previous mask */ +#else + movi a4, 0 + xsr a4, INTENABLE /* Disables all interrupts */ + rsync + or a3, a4, a2 /* set bits in mask */ + xor a3, a3, a2 /* invert bits in mask set in mask, essentially clearing them */ + wsr a3, INTENABLE /* Re-enable ints */ + rsync + mov a2, a4 /* return prev mask */ +#endif +#else + movi a2, 0 /* return zero */ +#endif + RET0 + + .size xt_ints_off, . - xt_ints_off + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S new file mode 100644 index 0000000..4572eb6 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S @@ -0,0 +1,549 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * LoadStoreErrorCause: Occurs when trying to access 32 bit addressable memory region as 8 bit or 16 bit + * LoadStoreAlignmentCause: Occurs when trying to access in an unaligned manner + * + * xxxx xxxx = imm8 field + * yyyy = imm4 field + * ssss = s field + * tttt = t field + * + * 16 0 + * ------------------- + * L32I.N yyyy ssss tttt 1000 + * S32I.N yyyy ssss tttt 1001 + * + * 23 0 + * ----------------------------- + * L8UI xxxx xxxx 0000 ssss tttt 0010 <- LoadStoreError + * L16UI xxxx xxxx 0001 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignment + * L16SI xxxx xxxx 1001 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignment + * L32I xxxx xxxx 0010 ssss tttt 0010 <- LoadStoreAlignment + * + * S8I xxxx xxxx 0100 ssss tttt 0010 <- LoadStoreError + * S16I xxxx xxxx 0101 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignment + * S32I xxxx xxxx 0110 ssss tttt 0010 <- LoadStoreAlignment + * + * ******* UNSUPPORTED ******* + * + * L32E 0000 1001 rrrr ssss tttt 0000 + * S32E 0100 1001 rrrr ssss tttt 0000 + * ----------------------------- + */ + +#include "xtensa_rtos.h" +#include "sdkconfig.h" +#include "soc/soc.h" + +#define LOADSTORE_HANDLER_STACK_SZ 8 + .section .bss, "aw" + .balign 16 +LoadStoreHandlerStack: + .rept LOADSTORE_HANDLER_STACK_SZ + .word 0 + .endr + + +/* LoadStoreErrorCause handler: + * + * Completes 8-bit or 16-bit load/store instructions from 32-bit aligned memory region + * Called from UserExceptionVector if EXCCAUSE is LoadStoreErrorCause + */ + + .global LoadStoreErrorHandler + .section .iram1, "ax" + + .literal_position + + .balign 4 +LoadStoreErrorHandler: + .type LoadStoreErrorHandler, @function + + wsr a0, depc // Save return address in depc + mov a0, sp + movi sp, LoadStoreHandlerStack + s32i a0, sp, 0x04 // Since a0 contains value of a1 + s32i a2, sp, 0x08 + s32i a3, sp, 0x0c + s32i a4, sp, 0x10 + + rsr a0, sar // Save SAR in a0 to restore later + + /* Check whether the address lies in the valid range */ + rsr a3, excvaddr + movi a4, _iram_text_end // End of code section of IRAM + bge a3, a4, 1f + movi a4, SOC_CACHE_APP_LOW // Check if in APP cache region + blt a3, a4, .LS_wrong_opcode + movi a4, SOC_CACHE_APP_HIGH + bge a3, a4, .LS_wrong_opcode + j 2f + +1: + movi a4, SOC_IRAM_HIGH // End of IRAM address range + bge a3, a4, .LS_wrong_opcode + +2: + /* Examine the opcode which generated the exception */ + /* Note: Instructions are in this order to avoid pipeline stalls. */ + rsr a2, epc1 + movi a4, ~3 + ssa8l a2 // sar is now correct shift for aligned read + and a2, a2, a4 // a2 now 4-byte aligned address of instruction + l32i a4, a2, 0 + l32i a2, a2, 4 + + src a2, a2, a4 // a2 now instruction that failed + bbci a2, 1, .LS_wrong_opcode + bbsi a2, 14, .LSE_store_op // Store instruction + + /* l8/l16ui/l16si */ + movi a4, ~3 + and a4, a3, a4 // a4 now word aligned read address + + ssa8l a3 // sar is now shift to extract a3's byte + l32i a4, a4, 0 // perform the actual read + srl a4, a4 // shift right correct distance + extui a3, a2, 12, 4 + bnez a3, 1f // l16ui/l16si + extui a4, a4, 0, 8 // mask off bits needed for an l8 + j 2f + +1: + extui a4, a4, 0, 16 + bbci a2, 15, 2f // l16ui + + /* Sign adjustment */ + slli a4, a4, 16 + srai a4, a4, 16 // a4 contains the value + +2: + /* a4 contains the value */ + rsr a3, epc1 + addi a3, a3, 3 + wsr a3, epc1 + wsr a0, sar + rsr a0, excsave1 + + extui a2, a2, 3, 5 + blti a2, 10, .LSE_stack_reg + + movi a3, .LS_jumptable_base + addx8 a2, a2, a3 // a2 is now the address to jump to + l32i a3, sp, 0x0c + jx a2 + +.LSE_stack_reg: + addx2 a2, a2, sp + s32i a4, a2, 0 + + /* Restore all values */ + l32i a4, sp, 0x10 + l32i a3, sp, 0x0c + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + +.LSE_store_op: + s32i a5, a1, 0x14 + s32i a6, a1, 0x18 + + /* a2 -> instruction that caused the error */ + /* a3 -> unaligned address */ + extui a4, a2, 4, 4 + blti a4, 7, 1f + movi a5, .LSE_store_reg + addx8 a5, a4, a5 + jx a5 + +1: + addx4 a4, a4, sp + l32i a4, a4, 0 + +.LSE_store_data: + /* a4 contains the value */ + rsr a6, epc1 + addi a6, a6, 3 + wsr a6, epc1 + + ssa8b a3 + movi a5, -1 + bbsi a2, 12, 1f // s16 + extui a4, a4, 0, 8 + movi a6, 0xff + j 2f +1: + extui a4, a4, 0, 16 + movi a6, 0xffff +2: + sll a4, a4 // shift the value to proper offset + sll a6, a6 + xor a5, a5, a6 // a5 contains the mask + + movi a6, ~3 + and a3, a3, a6 // a3 has the aligned address + l32i a6, a3, 0 // a6 contains the data at the aligned address + and a6, a6, a5 + or a4, a6, a4 + s32i a4, a3, 0 + + /* Restore registers */ + wsr a0, sar + + l32i a6, sp, 0x18 + l32i a5, sp, 0x14 + l32i a4, sp, 0x10 + l32i a3, sp, 0x0c + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rsr a0, excsave1 + + rfe + +.LSE_store_reg: + .org .LSE_store_reg + (7 * 8) + mov a4, a7 + j .LSE_store_data + + .org .LSE_store_reg + (8 * 8) + mov a4, a8 + j .LSE_store_data + + .org .LSE_store_reg + (9 * 8) + mov a4, a9 + j .LSE_store_data + + .org .LSE_store_reg + (10 * 8) + mov a4, a10 + j .LSE_store_data + + .org .LSE_store_reg + (11 * 8) + mov a4, a11 + j .LSE_store_data + + .org .LSE_store_reg + (12 * 8) + mov a4, a12 + j .LSE_store_data + + .org .LSE_store_reg + (13 * 8) + mov a4, a13 + j .LSE_store_data + + .org .LSE_store_reg + (14 * 8) + mov a4, a14 + j .LSE_store_data + + .org .LSE_store_reg + (15 * 8) + mov a4, a15 + j .LSE_store_data + + +/* LoadStoreAlignmentCause handler: + * + * Completes unaligned 16-bit and 32-bit load/store instructions from 32-bit aligned memory region + * Called from UserExceptionVector if EXCCAUSE is LoadStoreAlignmentCause + */ + + .global AlignmentErrorHandler + .section .iram1, "ax" + + .literal_position + + .balign 4 +AlignmentErrorHandler: + .type AlignmentErrorHandler, @function + + wsr a0, depc // Save return address in depc + mov a0, sp + movi sp, LoadStoreHandlerStack + s32i a0, sp, 0x04 // Since a0 contains value of a1 + s32i a2, sp, 0x08 + s32i a3, sp, 0x0c + s32i a4, sp, 0x10 + + rsr a0, sar // Save SAR in a0 to restore later + + /* Check whether the address lies in the valid range */ + rsr a3, excvaddr + movi a4, _iram_text_end // End of code section of IRAM + bge a3, a4, 1f + movi a4, SOC_CACHE_APP_LOW // Check if in APP cache region + blt a3, a4, .LS_wrong_opcode + movi a4, SOC_CACHE_APP_HIGH + bge a3, a4, .LS_wrong_opcode + j 2f + +1: + movi a4, SOC_IRAM_HIGH // End of IRAM address range + bge a3, a4, .LS_wrong_opcode + +2: + /* Examine the opcode which generated the exception */ + /* Note: Instructions are in this order to avoid pipeline stalls. */ + rsr a2, epc1 + movi a4, ~3 + ssa8l a2 // sar is now correct shift for aligned read + and a2, a2, a4 // a2 now 4-byte aligned address of instruction + l32i a4, a2, 0 + l32i a2, a2, 4 + + /* a2 has the instruction that caused the error */ + src a2, a2, a4 + extui a4, a2, 0, 4 + addi a4, a4, -9 + beqz a4, .LSA_store_op + bbsi a2, 14, .LSA_store_op + + ssa8l a3 // a3 contains the unaligned address + movi a4, ~3 + and a4, a3, a4 // a4 has the aligned address + l32i a3, a4, 0 + l32i a4, a4, 4 + src a4, a4, a3 + + rsr a3, epc1 + addi a3, a3, 2 + bbsi a2, 3, 1f // l32i.n + bbci a2, 1, .LS_wrong_opcode + addi a3, a3, 1 + + bbsi a2, 13, 1f // l32 + extui a4, a4, 0, 16 + bbci a2, 15, 1f // l16ui + + /* Sign adjustment */ + slli a4, a4, 16 + srai a4, a4, 16 // a4 contains the value + +1: + wsr a3, epc1 + wsr a0, sar + rsr a0, excsave1 + + extui a2, a2, 4, 4 + blti a2, 5, .LSA_stack_reg // a3 contains the target register + + movi a3, .LS_jumptable_base + slli a2, a2, 4 + add a2, a2, a3 // a2 is now the address to jump to + l32i a3, sp, 0x0c + jx a2 + +.LSA_stack_reg: + addx4 a2, a2, sp + s32i a4, a2, 0 + + /* Restore all values */ + l32i a4, sp, 0x10 + l32i a3, sp, 0x0c + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + +/* Store instruction */ +.LSA_store_op: + s32i a5, sp, 0x14 + s32i a6, sp, 0x18 + s32i a7, sp, 0x1c + + /* a2 -> instruction that caused the error */ + /* a3 -> unaligned address */ + extui a4, a2, 4, 4 + blti a4, 8, 1f + movi a5, .LSA_store_reg + addx8 a5, a4, a5 + jx a5 + +1: + addx4 a4, a4, sp + l32i a4, a4, 0 // a4 contains the value + +.LSA_store_data: + movi a6, 0 + + rsr a7, epc1 + addi a7, a7 ,2 + bbsi a2, 3, 1f // s32i.n + bbci a2, 1, .LS_wrong_opcode + + addi a7, a7, 1 + bbsi a2, 13, 1f // s32i + + movi a5, -1 + extui a4, a4, 0, 16 + slli a6, a5, 16 // 0xffff0000 + +1: + wsr a7, epc1 + movi a5, ~3 + and a5, a3, a5 // a5 has the aligned address + + ssa8b a3 + movi a3, -1 + src a7, a6, a3 + src a3, a3, a6 + + /* Store data on lower address */ + l32i a6, a5, 0 + and a6, a6, a7 + sll a7, a4 + or a6, a6, a7 + s32i a6, a5, 0 + + /* Store data on higher address */ + l32i a7, a5, 4 + srl a6, a4 + and a3, a7, a3 + or a3, a3, a6 + s32i a3, a5, 4 + + /* Restore registers */ + wsr a0, sar + rsr a0, excsave1 + + l32i a7, sp, 0x1c + l32i a6, sp, 0x18 + l32i a5, sp, 0x14 + l32i a4, sp, 0x10 + l32i a3, sp, 0x0c + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + +.LSA_store_reg: + .org .LSA_store_reg + (8 * 8) + mov a4, a8 + j .LSA_store_data + + .org .LSA_store_reg + (9 * 8) + mov a4, a9 + j .LSA_store_data + + .org .LSA_store_reg + (10 * 8) + mov a4, a10 + j .LSA_store_data + + .org .LSA_store_reg + (11 * 8) + mov a4, a11 + j .LSA_store_data + + .org .LSA_store_reg + (12 * 8) + mov a4, a12 + j .LSA_store_data + + .org .LSA_store_reg + (13 * 8) + mov a4, a13 + j .LSA_store_data + + .org .LSA_store_reg + (14 * 8) + mov a4, a14 + j .LSA_store_data + + .org .LSA_store_reg + (15 * 8) + mov a4, a15 + j .LSA_store_data + +/* + * Common routines for both the exception handlers + */ + .balign 4 +.LS_jumptable: + /* The first 5 entries (80 bytes) of this table are unused (registers + a0..a4 are handled separately above). Rather than have a whole bunch + of wasted space, just pretend that the table starts 80 bytes + earlier in memory. */ + .set .LS_jumptable_base, .LS_jumptable - (16 * 5) + + .org .LS_jumptable_base + (16 * 5) + mov a5, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 6) + mov a6, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 7) + mov a7, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 8) + mov a8, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 9) + mov a9, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 10) + mov a10, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 11) + mov a11, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 12) + mov a12, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 13) + mov a13, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 14) + mov a14, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 15) + mov a15, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + +.LS_wrong_opcode: + /* Reaches here if the address is in invalid range or the opcode isn't supported. + * Restore registers and jump back to _xt_user_exc + */ + wsr a0, sar + l32i a4, sp, 0x10 + l32i a3, sp, 0x0c + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rsr a0, depc + ret // Equivalent to jx a0 diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c new file mode 100644 index 0000000..a622825 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* xtensa_overlay_os_hook.c -- Overlay manager OS hooks for FreeRTOS. */ + +#include "FreeRTOS.h" +#include "semphr.h" + +#if configUSE_MUTEX + +/* Mutex object that controls access to the overlay. Currently only one + * overlay region is supported so one mutex suffices. + */ + static SemaphoreHandle_t xt_overlay_mutex; + + +/* This function should be overridden to provide OS specific init such + * as the creation of a mutex lock that can be used for overlay locking. + * Typically this mutex would be set up with priority inheritance. See + * overlay manager documentation for more details. + */ + void xt_overlay_init_os( void ) + { + /* Create the mutex for overlay access. Priority inheritance is + * required. + */ + xt_overlay_mutex = xSemaphoreCreateMutex(); + } + + +/* This function locks access to shared overlay resources, typically + * by acquiring a mutex. + */ + void xt_overlay_lock( void ) + { + xSemaphoreTake( xt_overlay_mutex, 0 ); + } + + +/* This function releases access to shared overlay resources, typically + * by unlocking a mutex. + */ + void xt_overlay_unlock( void ) + { + xSemaphoreGive( xt_overlay_mutex ); + } + +#endif /* if configUSE_MUTEX */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S new file mode 100644 index 0000000..3932777 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S @@ -0,0 +1,161 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "xtensa_rtos.h" +#include "esp_idf_version.h" +#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) +#include "esp_panic.h" +#else +#include "esp_private/panic_reason.h" +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ +#include "sdkconfig.h" +#include "soc/soc.h" + +/* +This file contains the default handlers for the high interrupt levels as well as some specialized exceptions. +The default behaviour is to just exit the interrupt or call the panic handler on the exceptions +*/ + + +#if XCHAL_HAVE_DEBUG + .global xt_debugexception + .weak xt_debugexception + .set xt_debugexception, _xt_debugexception + .section .iram1,"ax" + .type _xt_debugexception,@function + .align 4 + +_xt_debugexception: + movi a0,PANIC_RSN_DEBUGEXCEPTION + wsr a0,EXCCAUSE + /* _xt_panic assumes a level 1 exception. As we're + crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL + to level 1. */ + rsr a0,(EPC + XCHAL_DEBUGLEVEL) + wsr a0,EPC_1 + rsr a0,(EXCSAVE + XCHAL_DEBUGLEVEL) + wsr a0,EXCSAVE_1 + call0 _xt_panic /* does not return */ + rfi XCHAL_DEBUGLEVEL + +#endif /* Debug exception */ + + +#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2 + .global xt_highint2 + .weak xt_highint2 + .set xt_highint2, _xt_highint2 + .section .iram1,"ax" + .type _xt_highint2,@function + .align 4 +_xt_highint2: + + /* Default handler does nothing; just returns */ + .align 4 +.L_xt_highint2_exit: + rsr a0, EXCSAVE_2 /* restore a0 */ + rfi 2 + +#endif /* Level 2 */ + +#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3 + + .global xt_highint3 + .weak xt_highint3 + .set xt_highint3, _xt_highint3 + .section .iram1,"ax" + .type _xt_highint3,@function + .align 4 +_xt_highint3: + + /* Default handler does nothing; just returns */ + + .align 4 +.L_xt_highint3_exit: + rsr a0, EXCSAVE_3 /* restore a0 */ + rfi 3 + +#endif /* Level 3 */ + +#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4 + + .global xt_highint4 + .weak xt_highint4 + .set xt_highint4, _xt_highint4 + .section .iram1,"ax" + .type _xt_highint4,@function + .align 4 +_xt_highint4: + + /* Default handler does nothing; just returns */ + + .align 4 +.L_xt_highint4_exit: + rsr a0, EXCSAVE_4 /* restore a0 */ + rfi 4 + +#endif /* Level 4 */ + +#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5 + + .global xt_highint5 + .weak xt_highint5 + .set xt_highint5, _xt_highint5 + .section .iram1,"ax" + .type _xt_highint5,@function + .align 4 +_xt_highint5: + + /* Default handler does nothing; just returns */ + + .align 4 +.L_xt_highint5_exit: + rsr a0, EXCSAVE_5 /* restore a0 */ + rfi 5 + + +#endif /* Level 5 */ + +#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6 + + .global _xt_highint6 + .global xt_highint6 + .weak xt_highint6 + .set xt_highint6, _xt_highint6 + .section .iram1,"ax" + .type _xt_highint6,@function + .align 4 +_xt_highint6: + + /* Default handler does nothing; just returns */ + + .align 4 +.L_xt_highint6_exit: + rsr a0, EXCSAVE_6 /* restore a0 */ + rfi 6 + +#endif /* Level 6 */ + +#if XCHAL_HAVE_NMI + + .global _xt_nmi + .global xt_nmi + .weak xt_nmi + .set xt_nmi, _xt_nmi + .section .iram1,"ax" + .type _xt_nmi,@function + .align 4 +_xt_nmi: + + /* Default handler does nothing; just returns */ + + .align 4 +.L_xt_nmi_exit: + rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */ + rfi XCHAL_NMILEVEL + +#endif /* NMI */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S new file mode 100644 index 0000000..a431758 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S @@ -0,0 +1,2067 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************* +-------------------------------------------------------------------------------- + + XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS + + Xtensa low level exception and interrupt vectors and handlers for an RTOS. + + Interrupt handlers and user exception handlers support interaction with + the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and + after user's specific interrupt handlers. These macros are defined in + xtensa_.h to call suitable functions in a specific RTOS. + + Users can install application-specific interrupt handlers for low and + medium level interrupts, by calling xt_set_interrupt_handler(). These + handlers can be written in C, and must obey C calling convention. The + handler table is indexed by the interrupt number. Each handler may be + provided with an argument. + + Note that the system timer interrupt is handled specially, and is + dispatched to the RTOS-specific handler. This timer cannot be hooked + by application code. + + Optional hooks are also provided to install a handler per level at + run-time, made available by compiling this source file with + '-DXT_INTEXC_HOOKS' (useful for automated testing). + +!! This file is a template that usually needs to be modified to handle !! +!! application specific interrupts. Search USER_EDIT for helpful comments !! +!! on where to insert handlers and how to write them. !! + + Users can also install application-specific exception handlers in the + same way, by calling xt_set_exception_handler(). One handler slot is + provided for each exception type. Note that some exceptions are handled + by the porting layer itself, and cannot be taken over by application + code in this manner. These are the alloca, syscall, and coprocessor + exceptions. + + The exception handlers can be written in C, and must follow C calling + convention. Each handler is passed a pointer to an exception frame as + its single argument. The exception frame is created on the stack, and + holds the saved context of the thread that took the exception. If the + handler returns, the context will be restored and the instruction that + caused the exception will be retried. If the handler makes any changes + to the saved state in the exception frame, the changes will be applied + when restoring the context. + + Because Xtensa is a configurable architecture, this port supports all user + generated configurations (except restrictions stated in the release notes). + This is accomplished by conditional compilation using macros and functions + defined in the Xtensa HAL (hardware adaptation layer) for your configuration. + Only the relevant parts of this file will be included in your RTOS build. + For example, this file provides interrupt vector templates for all types and + all priority levels, but only the ones in your configuration are built. + + NOTES on the use of 'call0' for long jumps instead of 'j': + 1. This file should be assembled with the -mlongcalls option to xt-xcc. + 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to + a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the + distance from the call to the destination. The linker then relaxes + it back to 'call0 dest' if it determines that dest is within range. + This allows more flexibility in locating code without the performance + overhead of the 'l32r' literal data load in cases where the destination + is in range of 'call0'. There is an additional benefit in that 'call0' + has a longer range than 'j' due to the target being word-aligned, so + the 'l32r' sequence is less likely needed. + 3. The use of 'call0' with -mlongcalls requires that register a0 not be + live at the time of the call, which is always the case for a function + call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'. + 4. This use of 'call0' is independent of the C function call ABI. + +*******************************************************************************/ + +#include "xtensa_rtos.h" +#include "esp_idf_version.h" +#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) +#include "esp_panic.h" +#else +#include "esp_private/panic_reason.h" +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ +#include "sdkconfig.h" +#include "soc/soc.h" + +/* + Define for workaround: pin no-cpu-affinity tasks to a cpu when fpu is used. + Please change this when the tcb structure is changed +*/ +#define TASKTCB_XCOREID_OFFSET (0x38+configMAX_TASK_NAME_LEN+3)&~3 +.extern pxCurrentTCB + +/* +-------------------------------------------------------------------------------- + In order for backtracing to be able to trace from the pre-exception stack + across to the exception stack (including nested interrupts), we need to create + a pseudo base-save area to make it appear like the exception dispatcher was + triggered by a CALL4 from the pre-exception code. In reality, the exception + dispatcher uses the same window as pre-exception code, and only CALL0s are + used within the exception dispatcher. + + To create the pseudo base-save area, we need to store a copy of the pre-exception's + base save area (a0 to a4) below the exception dispatcher's SP. EXCSAVE_x will + be used to store a copy of the SP that points to the interrupted code's exception + frame just in case the exception dispatcher's SP does not point to the exception + frame (which is the case when switching from task to interrupt stack). + + Clearing the pseudo base-save area is uncessary as the interrupt dispatcher + will restore the current SP to that of the pre-exception SP. +-------------------------------------------------------------------------------- +*/ +#ifdef CONFIG_FREERTOS_INTERRUPT_BACKTRACE +#define XT_DEBUG_BACKTRACE 1 +#endif + + +/* +-------------------------------------------------------------------------------- + Defines used to access _xtos_interrupt_table. +-------------------------------------------------------------------------------- +*/ +#define XIE_HANDLER 0 +#define XIE_ARG 4 +#define XIE_SIZE 8 + + +/* + Macro get_percpu_entry_for - convert a per-core ID into a multicore entry. + Basically does reg=reg*portNUM_PROCESSORS+current_core_id + Multiple versions here to optimize for specific portNUM_PROCESSORS values. +*/ + .macro get_percpu_entry_for reg scratch +#if (portNUM_PROCESSORS == 1) + /* No need to do anything */ +#elif (portNUM_PROCESSORS == 2) + /* Optimized 2-core code. */ + getcoreid \scratch + addx2 \reg,\reg,\scratch +#else + /* Generalized n-core code. Untested! */ + movi \scratch,portNUM_PROCESSORS + mull \scratch,\reg,\scratch + getcoreid \reg + add \reg,\scratch,\reg +#endif + .endm +/* +-------------------------------------------------------------------------------- + Macro extract_msb - return the input with only the highest bit set. + + Input : "ain" - Input value, clobbered. + Output : "aout" - Output value, has only one bit set, MSB of "ain". + The two arguments must be different AR registers. +-------------------------------------------------------------------------------- +*/ + + .macro extract_msb aout ain +1: + addi \aout, \ain, -1 /* aout = ain - 1 */ + and \ain, \ain, \aout /* ain = ain & aout */ + bnez \ain, 1b /* repeat until ain == 0 */ + addi \aout, \aout, 1 /* return aout + 1 */ + .endm + +/* +-------------------------------------------------------------------------------- + Macro dispatch_c_isr - dispatch interrupts to user ISRs. + This will dispatch to user handlers (if any) that are registered in the + XTOS dispatch table (_xtos_interrupt_table). These handlers would have + been registered by calling _xtos_set_interrupt_handler(). There is one + exception - the timer interrupt used by the OS will not be dispatched + to a user handler - this must be handled by the caller of this macro. + + Level triggered and software interrupts are automatically deasserted by + this code. + + ASSUMPTIONS: + -- PS.INTLEVEL is set to "level" at entry + -- PS.EXCM = 0, C calling enabled + + NOTE: For CALL0 ABI, a12-a15 have not yet been saved. + + NOTE: This macro will use registers a0 and a2-a7. The arguments are: + level -- interrupt level + mask -- interrupt bitmask for this level +-------------------------------------------------------------------------------- +*/ + + .macro dispatch_c_isr level mask + + #ifdef CONFIG_PM_TRACE + movi a6, 0 /* = ESP_PM_TRACE_IDLE */ + getcoreid a7 + call4 esp_pm_trace_exit + #endif // CONFIG_PM_TRACE + + /* Get mask of pending, enabled interrupts at this level into a2. */ + +.L_xt_user_int_&level&: + rsr a2, INTENABLE + rsr a3, INTERRUPT + movi a4, \mask + and a2, a2, a3 + and a2, a2, a4 + beqz a2, 9f /* nothing to do */ + + /* This bit of code provides a nice debug backtrace in the debugger. + It does take a few more instructions, so undef XT_DEBUG_BACKTRACE + if you want to save the cycles. + At this point, the exception frame should have been allocated and filled, + and current sp points to the interrupt stack (for non-nested interrupt) + or below the allocated exception frame (for nested interrupts). Copy the + pre-exception's base save area below the current SP. + */ + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + rsr a0, EXCSAVE_1 + \level - 1 /* Get exception frame pointer stored in EXCSAVE_x */ + l32i a3, a0, XT_STK_A0 /* Copy pre-exception a0 (return address) */ + s32e a3, a1, -16 + l32i a3, a0, XT_STK_A1 /* Copy pre-exception a1 (stack pointer) */ + s32e a3, a1, -12 + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + /* Backtracing only needs a0 and a1, no need to create full base save area. + Also need to change current frame's return address to point to pre-exception's + last run instruction. + */ + rsr a0, EPC_1 + \level - 1 /* return address */ + movi a4, 0xC0000000 /* constant with top 2 bits set (call size) */ + or a0, a0, a4 /* set top 2 bits */ + addx2 a0, a4, a0 /* clear top bit -- simulating call4 size */ + #endif + #endif + + #ifdef CONFIG_PM_ENABLE + call4 esp_pm_impl_isr_hook + #endif + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a4, _xt_intexc_hooks + l32i a4, a4, \level << 2 + beqz a4, 2f + #ifdef __XTENSA_CALL0_ABI__ + callx0 a4 + beqz a2, 9f + #else + mov a6, a2 + callx4 a4 + beqz a6, 9f + mov a2, a6 + #endif +2: + #endif + + /* Now look up in the dispatch table and call user ISR if any. */ + /* If multiple bits are set then MSB has highest priority. */ + + extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ + + #ifdef XT_USE_SWPRI + /* Enable all interrupts at this level that are numerically higher + than the one we just selected, since they are treated as higher + priority. + */ + movi a3, \mask /* a3 = all interrupts at this level */ + add a2, a4, a4 /* a2 = a4 << 1 */ + addi a2, a2, -1 /* a2 = mask of 1's <= a4 bit */ + and a2, a2, a3 /* a2 = mask of all bits <= a4 at this level */ + movi a3, _xt_intdata + l32i a6, a3, 4 /* a6 = _xt_vpri_mask */ + neg a2, a2 + addi a2, a2, -1 /* a2 = mask to apply */ + and a5, a6, a2 /* mask off all bits <= a4 bit */ + s32i a5, a3, 4 /* update _xt_vpri_mask */ + rsr a3, INTENABLE + and a3, a3, a2 /* mask off all bits <= a4 bit */ + wsr a3, INTENABLE + rsil a3, \level - 1 /* lower interrupt level by 1 */ + #endif + + movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */ + wsr a4, INTCLEAR /* clear sw or edge-triggered interrupt */ + beq a3, a4, 7f /* if timer interrupt then skip table */ + + find_ms_setbit a3, a4, a3, 0 /* a3 = interrupt number */ + + get_percpu_entry_for a3, a12 + movi a4, _xt_interrupt_table + addx8 a3, a3, a4 /* a3 = address of interrupt table entry */ + l32i a4, a3, XIE_HANDLER /* a4 = handler address */ + #ifdef __XTENSA_CALL0_ABI__ + mov a12, a6 /* save in callee-saved reg */ + l32i a2, a3, XIE_ARG /* a2 = handler arg */ + callx0 a4 /* call handler */ + mov a2, a12 + #else + mov a2, a6 /* save in windowed reg */ + l32i a6, a3, XIE_ARG /* a6 = handler arg */ + callx4 a4 /* call handler */ + #endif + + #ifdef XT_USE_SWPRI + j 8f + #else + j .L_xt_user_int_&level& /* check for more interrupts */ + #endif + +7: + + .ifeq XT_TIMER_INTPRI - \level +.L_xt_user_int_timer_&level&: + /* + Interrupt handler for the RTOS tick timer if at this level. + We'll be reading the interrupt state again after this call + so no need to preserve any registers except a6 (vpri_mask). + */ + + #ifdef __XTENSA_CALL0_ABI__ + mov a12, a6 + call0 XT_RTOS_TIMER_INT + mov a2, a12 + #else + mov a2, a6 + call4 XT_RTOS_TIMER_INT + #endif + .endif + + #ifdef XT_USE_SWPRI + j 8f + #else + j .L_xt_user_int_&level& /* check for more interrupts */ + #endif + + #ifdef XT_USE_SWPRI +8: + /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from + virtual _xt_intenable which _could_ have changed during interrupt + processing. */ + + movi a3, _xt_intdata + l32i a4, a3, 0 /* a4 = _xt_intenable */ + s32i a2, a3, 4 /* update _xt_vpri_mask */ + and a4, a4, a2 /* a4 = masked intenable */ + wsr a4, INTENABLE /* update INTENABLE */ + #endif + +9: + /* done */ + + .endm + + +/* +-------------------------------------------------------------------------------- + Panic handler. + Should be reached by call0 (preferable) or jump only. If call0, a0 says where + from. If on simulator, display panic message and abort, else loop indefinitely. +-------------------------------------------------------------------------------- +*/ + + .section .iram1,"ax" + .global panicHandler + + .global _xt_panic + .type _xt_panic,@function + .align 4 + .literal_position + .align 4 + +_xt_panic: + /* Allocate exception frame and save minimal context. */ + mov a0, sp + addi sp, sp, -XT_STK_FRMSZ + s32i a0, sp, XT_STK_A1 + #if XCHAL_HAVE_WINDOWED + s32e a0, sp, -12 /* for debug backtrace */ + #endif + rsr a0, PS /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_1 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + #if XCHAL_HAVE_WINDOWED + s32e a0, sp, -16 /* for debug backtrace */ + #endif + s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */ + s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */ + call0 _xt_context_save + + /* Save exc cause and vaddr into exception frame */ + rsr a0, EXCCAUSE + s32i a0, sp, XT_STK_EXCCAUSE + rsr a0, EXCVADDR + s32i a0, sp, XT_STK_EXCVADDR + + /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */ + rsr a0, EXCSAVE_1 /* save interruptee's a0 */ + + s32i a0, sp, XT_STK_A0 + + /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */ + movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE + wsr a0, PS + + //Call panic handler + mov a6,sp + call4 panicHandler + + + .align 4 +//Call using call0. Prints the hex char in a2. Kills a3, a4, a5 +panic_print_hex: + movi a3,0x60000000 + movi a4,8 +panic_print_hex_loop: + l32i a5, a3, 0x1c + extui a5, a5, 16, 8 + bgei a5,64,panic_print_hex_loop + + srli a5,a2,28 + bgei a5,10,panic_print_hex_a + addi a5,a5,'0' + j panic_print_hex_ok +panic_print_hex_a: + addi a5,a5,'A'-10 +panic_print_hex_ok: + s32i a5,a3,0 + slli a2,a2,4 + + addi a4,a4,-1 + bnei a4,0,panic_print_hex_loop + movi a5,' ' + s32i a5,a3,0 + + ret + + + + .section .rodata, "a" + .align 4 + + + +/* +-------------------------------------------------------------------------------- + Hooks to dynamically install handlers for exceptions and interrupts. + Allows automated regression frameworks to install handlers per test. + Consists of an array of function pointers indexed by interrupt level, + with index 0 containing the entry for user exceptions. + Initialized with all 0s, meaning no handler is installed at each level. + See comment in xtensa_rtos.h for more details. + + *WARNING* This array is for all CPUs, that is, installing a hook for + one CPU will install it for all others as well! +-------------------------------------------------------------------------------- +*/ + + #ifdef XT_INTEXC_HOOKS + .data + .global _xt_intexc_hooks + .type _xt_intexc_hooks,@object + .align 4 + +_xt_intexc_hooks: + .fill XT_INTEXC_HOOK_NUM, 4, 0 + #endif + + +/* +-------------------------------------------------------------------------------- + EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS + (except window exception vectors). + + Each vector goes at a predetermined location according to the Xtensa + hardware configuration, which is ensured by its placement in a special + section known to the Xtensa linker support package (LSP). It performs + the minimum necessary before jumping to the handler in the .text section. + + The corresponding handler goes in the normal .text section. It sets up + the appropriate stack frame, saves a few vector-specific registers and + calls XT_RTOS_INT_ENTER to save the rest of the interrupted context + and enter the RTOS, then sets up a C environment. It then calls the + user's interrupt handler code (which may be coded in C) and finally + calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling. + + While XT_RTOS_INT_EXIT does not return directly to the interruptee, + eventually the RTOS scheduler will want to dispatch the interrupted + task or handler. The scheduler will return to the exit point that was + saved in the interrupt stack frame at XT_STK_EXIT. +-------------------------------------------------------------------------------- +*/ + + +/* +-------------------------------------------------------------------------------- +Debug Exception. +-------------------------------------------------------------------------------- +*/ + +#if XCHAL_HAVE_DEBUG + + .begin literal_prefix .DebugExceptionVector + .section .DebugExceptionVector.text, "ax" + .global _DebugExceptionVector + .align 4 + .global xt_debugexception +_DebugExceptionVector: + wsr a0, EXCSAVE+XCHAL_DEBUGLEVEL /* preserve a0 */ + call0 xt_debugexception /* load exception handler */ + + .end literal_prefix + +#endif + +/* +-------------------------------------------------------------------------------- +Double Exception. +Double exceptions are not a normal occurrence. They indicate a bug of some kind. +-------------------------------------------------------------------------------- +*/ + +#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR + + .begin literal_prefix .DoubleExceptionVector + .section .DoubleExceptionVector.text, "ax" + .global _DoubleExceptionVector + .align 4 + +_DoubleExceptionVector: + + #if XCHAL_HAVE_DEBUG + break 1, 4 /* unhandled double exception */ + #endif + movi a0,PANIC_RSN_DOUBLEEXCEPTION + wsr a0,EXCCAUSE + call0 _xt_panic /* does not return */ + rfde /* make a0 point here not later */ + + .end literal_prefix + +#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */ + +/* +-------------------------------------------------------------------------------- +Kernel Exception (including Level 1 Interrupt from kernel mode). +-------------------------------------------------------------------------------- +*/ + + .begin literal_prefix .KernelExceptionVector + .section .KernelExceptionVector.text, "ax" + .global _KernelExceptionVector + .align 4 + +_KernelExceptionVector: + + wsr a0, EXCSAVE_1 /* preserve a0 */ + call0 _xt_kernel_exc /* kernel exception handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .section .iram1,"ax" + .align 4 + +_xt_kernel_exc: + #if XCHAL_HAVE_DEBUG + break 1, 0 /* unhandled kernel exception */ + #endif + movi a0,PANIC_RSN_KERNELEXCEPTION + wsr a0,EXCCAUSE + call0 _xt_panic /* does not return */ + rfe /* make a0 point here not there */ + + +/* +-------------------------------------------------------------------------------- +User Exception (including Level 1 Interrupt from user mode). +-------------------------------------------------------------------------------- +*/ + + .begin literal_prefix .UserExceptionVector + .section .UserExceptionVector.text, "ax" + .global _UserExceptionVector + .type _UserExceptionVector,@function + .align 4 + +_UserExceptionVector: + + wsr a0, EXCSAVE_1 /* preserve a0 */ + call0 _xt_user_exc /* user exception handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +/* +-------------------------------------------------------------------------------- + Insert some waypoints for jumping beyond the signed 8-bit range of + conditional branch instructions, so the conditional branchces to specific + exception handlers are not taken in the mainline. Saves some cycles in the + mainline. +-------------------------------------------------------------------------------- +*/ + +#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY + .global LoadStoreErrorHandler + .global AlignmentErrorHandler +#endif + + .section .iram1,"ax" + + #if XCHAL_HAVE_WINDOWED + .align 4 +_xt_to_alloca_exc: + call0 _xt_alloca_exc /* in window vectors section */ + /* never returns here - call0 is used as a jump (see note at top) */ + #endif + + .align 4 +_xt_to_syscall_exc: + call0 _xt_syscall_exc + /* never returns here - call0 is used as a jump (see note at top) */ + + #if XCHAL_CP_NUM > 0 + .align 4 +_xt_to_coproc_exc: + call0 _xt_coproc_exc + /* never returns here - call0 is used as a jump (see note at top) */ + #endif + +#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY + .align 4 +_call_loadstore_handler: + call0 LoadStoreErrorHandler + /* This will return only if wrong opcode or address out of range*/ + j .LS_exit + + .align 4 +_call_alignment_handler: + call0 AlignmentErrorHandler + /* This will return only if wrong opcode or address out of range*/ + addi a0, a0, 1 + j .LS_exit +#endif + +/* +-------------------------------------------------------------------------------- + User exception handler. +-------------------------------------------------------------------------------- +*/ + + .type _xt_user_exc,@function + .align 4 + +_xt_user_exc: + + /* If level 1 interrupt then jump to the dispatcher */ + rsr a0, EXCCAUSE + beqi a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1 + + /* Handle any coprocessor exceptions. Rely on the fact that exception + numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors. + */ + #if XCHAL_CP_NUM > 0 + bgeui a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc + #endif + + /* Handle alloca and syscall exceptions */ + #if XCHAL_HAVE_WINDOWED + beqi a0, EXCCAUSE_ALLOCA, _xt_to_alloca_exc + #endif + beqi a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc + +#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY + beqi a0, EXCCAUSE_LOAD_STORE_ERROR, _call_loadstore_handler + + addi a0, a0, -1 + beqi a0, 8, _call_alignment_handler + addi a0, a0, 1 +.LS_exit: +#endif + + /* Handle all other exceptions. All can have user-defined handlers. */ + /* NOTE: we'll stay on the user stack for exception handling. */ + + /* Allocate exception frame and save minimal context. */ + mov a0, sp + addi sp, sp, -XT_STK_FRMSZ + s32i a0, sp, XT_STK_A1 + #if XCHAL_HAVE_WINDOWED + s32e a0, sp, -12 /* for debug backtrace */ + #endif + rsr a0, PS /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_1 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + #if XCHAL_HAVE_WINDOWED + s32e a0, sp, -16 /* for debug backtrace */ + #endif + s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */ + s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */ + call0 _xt_context_save + + /* Save exc cause and vaddr into exception frame */ + rsr a0, EXCCAUSE + s32i a0, sp, XT_STK_EXCCAUSE + rsr a0, EXCVADDR + s32i a0, sp, XT_STK_EXCVADDR + + /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */ + rsr a0, EXCSAVE_1 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + + /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM + #else + movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE + #endif + wsr a0, PS + + /* + Create pseudo base save area. At this point, sp is still pointing to the + allocated and filled exception stack frame. + */ + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + l32i a3, sp, XT_STK_A0 /* Copy pre-exception a0 (return address) */ + s32e a3, sp, -16 + l32i a3, sp, XT_STK_A1 /* Copy pre-exception a1 (stack pointer) */ + s32e a3, sp, -12 + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + rsr a0, EPC_1 /* return address for debug backtrace */ + movi a5, 0xC0000000 /* constant with top 2 bits set (call size) */ + rsync /* wait for WSR.PS to complete */ + or a0, a0, a5 /* set top 2 bits */ + addx2 a0, a5, a0 /* clear top bit -- thus simulating call4 size */ + #else + rsync /* wait for WSR.PS to complete */ + #endif + #endif + + rsr a2, EXCCAUSE /* recover exc cause */ + + #ifdef XT_INTEXC_HOOKS + /* + Call exception hook to pre-handle exceptions (if installed). + Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling). + */ + movi a4, _xt_intexc_hooks + l32i a4, a4, 0 /* user exception hook index 0 */ + beqz a4, 1f +.Ln_xt_user_exc_call_hook: + #ifdef __XTENSA_CALL0_ABI__ + callx0 a4 + beqi a2, -1, .L_xt_user_done + #else + mov a6, a2 + callx4 a4 + beqi a6, -1, .L_xt_user_done + mov a2, a6 + #endif +1: + #endif + + rsr a2, EXCCAUSE /* recover exc cause */ + movi a3, _xt_exception_table + get_percpu_entry_for a2, a4 + addx4 a4, a2, a3 /* a4 = address of exception table entry */ + l32i a4, a4, 0 /* a4 = handler address */ + #ifdef __XTENSA_CALL0_ABI__ + mov a2, sp /* a2 = pointer to exc frame */ + callx0 a4 /* call handler */ + #else + mov a6, sp /* a6 = pointer to exc frame */ + callx4 a4 /* call handler */ + #endif + +.L_xt_user_done: + + /* Restore context and return */ + call0 _xt_context_restore + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, PS + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_1 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove exception frame */ + rsync /* ensure PS and EPC written */ + rfe /* PS.EXCM is cleared */ + + +/* +-------------------------------------------------------------------------------- + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. +-------------------------------------------------------------------------------- +*/ + + .global _xt_user_exit + .type _xt_user_exit,@function + .align 4 +_xt_user_exit: + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, PS + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_1 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure PS and EPC written */ + rfe /* PS.EXCM is cleared */ + + +/* + +-------------------------------------------------------------------------------- +Syscall Exception Handler (jumped to from User Exception Handler). +Syscall 0 is required to spill the register windows (no-op in Call 0 ABI). +Only syscall 0 is handled here. Other syscalls return -1 to caller in a2. +-------------------------------------------------------------------------------- +*/ + + .section .iram1,"ax" + .type _xt_syscall_exc,@function + .align 4 +_xt_syscall_exc: + + #ifdef __XTENSA_CALL0_ABI__ + /* + Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI. + Use a minimal stack frame (16B) to save A2 & A3 for scratch. + PS.EXCM could be cleared here, but unlikely to improve worst-case latency. + rsr a0, PS + addi a0, a0, -PS_EXCM_MASK + wsr a0, PS + */ + addi sp, sp, -16 + s32i a2, sp, 8 + s32i a3, sp, 12 + #else /* Windowed ABI */ + /* + Save necessary context and spill the register windows. + PS.EXCM is still set and must remain set until after the spill. + Reuse context save function though it saves more than necessary. + For this reason, a full interrupt stack frame is allocated. + */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */ + s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */ + call0 _xt_context_save + #endif + + /* + Grab the interruptee's PC and skip over the 'syscall' instruction. + If it's at the end of a zero-overhead loop and it's not on the last + iteration, decrement loop counter and skip to beginning of loop. + */ + rsr a2, EPC_1 /* a2 = PC of 'syscall' */ + addi a3, a2, 3 /* ++PC */ + #if XCHAL_HAVE_LOOPS + rsr a0, LEND /* if (PC == LEND */ + bne a3, a0, 1f + rsr a0, LCOUNT /* && LCOUNT != 0) */ + beqz a0, 1f /* { */ + addi a0, a0, -1 /* --LCOUNT */ + rsr a3, LBEG /* PC = LBEG */ + wsr a0, LCOUNT /* } */ + #endif +1: wsr a3, EPC_1 /* update PC */ + + /* Restore interruptee's context and return from exception. */ + #ifdef __XTENSA_CALL0_ABI__ + l32i a2, sp, 8 + l32i a3, sp, 12 + addi sp, sp, 16 + #else + call0 _xt_context_restore + addi sp, sp, XT_STK_FRMSZ + #endif + movi a0, -1 + movnez a2, a0, a2 /* return -1 if not syscall 0 */ + rsr a0, EXCSAVE_1 + rfe + +/* +-------------------------------------------------------------------------------- +Co-Processor Exception Handler (jumped to from User Exception Handler). +These exceptions are generated by co-processor instructions, which are only +allowed in thread code (not in interrupts or kernel code). This restriction is +deliberately imposed to reduce the burden of state-save/restore in interrupts. +-------------------------------------------------------------------------------- +*/ +#if XCHAL_CP_NUM > 0 + + .section .rodata, "a" + +/* Offset to CP n save area in thread's CP save area. */ + .global _xt_coproc_sa_offset + .type _xt_coproc_sa_offset,@object + .align 16 /* minimize crossing cache boundaries */ +_xt_coproc_sa_offset: + .word XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA + .word XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA + +/* Bitmask for CP n's CPENABLE bit. */ + .type _xt_coproc_mask,@object + .align 16,,8 /* try to keep it all in one cache line */ + .set i, 0 +_xt_coproc_mask: + .rept XCHAL_CP_MAX + .long (i<<16) | (1<= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifndef CONFIG_FREERTOS_FPU_IN_ISR + #endif + beq a15, a2, .L_goto_done /* new owner == old, we're done */ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #endif + #endif + + /* If no old owner then nothing to save. */ + beqz a2, .L_check_new + + /* If old owner not actively using CP then nothing to save. */ + l16ui a4, a2, XT_CPENABLE /* a4 = old owner's CPENABLE */ + bnone a4, a0, .L_check_new /* old owner not using CP */ + +.L_save_old: + /* Save old owner's coprocessor state. */ + + movi a5, _xt_coproc_sa_offset + + /* Mark old owner state as no longer active (CPENABLE bit n clear). */ + xor a4, a4, a0 /* clear CP bit in CPENABLE */ + s16i a4, a2, XT_CPENABLE /* update old owner's CPENABLE */ + + extui a4, a0, 16, 5 /* a4 = CP index = n */ + addx4 a5, a4, a5 /* a5 = &_xt_coproc_sa_offset[n] */ + + /* Mark old owner state as saved (CPSTORED bit n set). */ + l16ui a4, a2, XT_CPSTORED /* a4 = old owner's CPSTORED */ + l32i a5, a5, 0 /* a5 = XT_CP[n]_SA offset */ + or a4, a4, a0 /* set CP in old owner's CPSTORED */ + s16i a4, a2, XT_CPSTORED /* update old owner's CPSTORED */ + l32i a2, a2, XT_CP_ASA /* ptr to actual (aligned) save area */ + extui a3, a0, 16, 5 /* a3 = CP index = n */ + add a2, a2, a5 /* a2 = old owner's area for CP n */ + + /* + The config-specific HAL macro invoked below destroys a2-5, preserves a0-1. + It is theoretically possible for Xtensa processor designers to write TIE + that causes more address registers to be affected, but it is generally + unlikely. If that ever happens, more registers needs to be saved/restored + around this macro invocation, and the value in a15 needs to be recomputed. + */ + xchal_cpi_store_funcbody + +.L_check_new: + /* Check if any state has to be restored for new owner. */ + /* NOTE: a15 = new owner's save area, cannot be zero when we get here. */ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + beqz a15, .L_xt_coproc_done + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + l16ui a3, a15, XT_CPSTORED /* a3 = new owner's CPSTORED */ + movi a4, _xt_coproc_sa_offset + bnone a3, a0, .L_check_cs /* full CP not saved, check callee-saved */ + xor a3, a3, a0 /* CPSTORED bit is set, clear it */ + s16i a3, a15, XT_CPSTORED /* update new owner's CPSTORED */ + + /* Adjust new owner's save area pointers to area for CP n. */ + extui a3, a0, 16, 5 /* a3 = CP index = n */ + addx4 a4, a3, a4 /* a4 = &_xt_coproc_sa_offset[n] */ + l32i a4, a4, 0 /* a4 = XT_CP[n]_SA */ + l32i a5, a15, XT_CP_ASA /* ptr to actual (aligned) save area */ + add a2, a4, a5 /* a2 = new owner's area for CP */ + + /* + The config-specific HAL macro invoked below destroys a2-5, preserves a0-1. + It is theoretically possible for Xtensa processor designers to write TIE + that causes more address registers to be affected, but it is generally + unlikely. If that ever happens, more registers needs to be saved/restored + around this macro invocation. + */ + xchal_cpi_load_funcbody + + /* Restore interruptee's saved registers. */ + /* Can omit rsync for wsr.CPENABLE here because _xt_user_exit does it. */ +.L_xt_coproc_done: + l32i a15, sp, XT_STK_A15 + l32i a5, sp, XT_STK_A5 + l32i a4, sp, XT_STK_A4 + l32i a3, sp, XT_STK_A3 + l32i a2, sp, XT_STK_A2 + call0 _xt_user_exit /* return via exit dispatcher */ + /* Never returns here - call0 is used as a jump (see note at top) */ + +.L_check_cs: + /* a0 = CP mask in low bits, a15 = new owner's save area */ + l16ui a2, a15, XT_CP_CS_ST /* a2 = mask of CPs saved */ + bnone a2, a0, .L_xt_coproc_done /* if no match then done */ + and a2, a2, a0 /* a2 = which CPs to restore */ + extui a2, a2, 0, 8 /* extract low 8 bits */ + s32i a6, sp, XT_STK_A6 /* save extra needed regs */ + s32i a7, sp, XT_STK_A7 + s32i a13, sp, XT_STK_A13 + s32i a14, sp, XT_STK_A14 + call0 _xt_coproc_restorecs /* restore CP registers */ + l32i a6, sp, XT_STK_A6 /* restore saved registers */ + l32i a7, sp, XT_STK_A7 + l32i a13, sp, XT_STK_A13 + l32i a14, sp, XT_STK_A14 + j .L_xt_coproc_done + + /* Co-processor exception occurred outside a thread (not supported). */ +.L_xt_coproc_invalid: + movi a0,PANIC_RSN_COPROCEXCEPTION + wsr a0,EXCCAUSE + call0 _xt_panic /* not in a thread (invalid) */ + /* never returns */ + + +#endif /* XCHAL_CP_NUM */ + + +/* +------------------------------------------------------------------------------- + Level 1 interrupt dispatch. Assumes stack frame has not been allocated yet. +------------------------------------------------------------------------------- +*/ + + .section .iram1,"ax" + .type _xt_lowint1,@function + .align 4 + +_xt_lowint1: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, PS /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_1 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_1 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_user_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + /* EXCSAVE_1 should now be free to use. Use it to keep a copy of the + current stack pointer that points to the exception frame (XT_STK_FRAME).*/ + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + mov a0, sp + wsr a0, EXCSAVE_1 + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(1) | PS_UM + #else + movi a0, PS_INTLEVEL(1) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + +/* +------------------------------------------------------------------------------- + MEDIUM PRIORITY (LEVEL 2+) INTERRUPT VECTORS AND LOW LEVEL HANDLERS. + + Medium priority interrupts are by definition those with priority greater + than 1 and not greater than XCHAL_EXCM_LEVEL. These are disabled by + setting PS.EXCM and therefore can easily support a C environment for + handlers in C, and interact safely with an RTOS. + + Each vector goes at a predetermined location according to the Xtensa + hardware configuration, which is ensured by its placement in a special + section known to the Xtensa linker support package (LSP). It performs + the minimum necessary before jumping to the handler in the .text section. + + The corresponding handler goes in the normal .text section. It sets up + the appropriate stack frame, saves a few vector-specific registers and + calls XT_RTOS_INT_ENTER to save the rest of the interrupted context + and enter the RTOS, then sets up a C environment. It then calls the + user's interrupt handler code (which may be coded in C) and finally + calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling. + + While XT_RTOS_INT_EXIT does not return directly to the interruptee, + eventually the RTOS scheduler will want to dispatch the interrupted + task or handler. The scheduler will return to the exit point that was + saved in the interrupt stack frame at XT_STK_EXIT. +------------------------------------------------------------------------------- +*/ + +#if XCHAL_EXCM_LEVEL >= 2 + + .begin literal_prefix .Level2InterruptVector + .section .Level2InterruptVector.text, "ax" + .global _Level2Vector + .type _Level2Vector,@function + .align 4 +_Level2Vector: + wsr a0, EXCSAVE_2 /* preserve a0 */ + call0 _xt_medint2 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .section .iram1,"ax" + .type _xt_medint2,@function + .align 4 +_xt_medint2: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_2 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_2 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_2 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint2_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* EXCSAVE_2 should now be free to use. Use it to keep a copy of the + current stack pointer that points to the exception frame (XT_STK_FRAME).*/ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + mov a0, sp + wsr a0, EXCSAVE_2 + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(2) | PS_UM + #else + movi a0, PS_INTLEVEL(2) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint2_exit + .type _xt_medint2_exit,@function + .align 4 +_xt_medint2_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_2 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_2 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 2 + +#endif /* Level 2 */ + +#if XCHAL_EXCM_LEVEL >= 3 + + .begin literal_prefix .Level3InterruptVector + .section .Level3InterruptVector.text, "ax" + .global _Level3Vector + .type _Level3Vector,@function + .align 4 +_Level3Vector: + wsr a0, EXCSAVE_3 /* preserve a0 */ + call0 _xt_medint3 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .section .iram1,"ax" + .type _xt_medint3,@function + .align 4 +_xt_medint3: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_3 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_3 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_3 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint3_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* EXCSAVE_3 should now be free to use. Use it to keep a copy of the + current stack pointer that points to the exception frame (XT_STK_FRAME).*/ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + mov a0, sp + wsr a0, EXCSAVE_3 + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(3) | PS_UM + #else + movi a0, PS_INTLEVEL(3) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint3_exit + .type _xt_medint3_exit,@function + .align 4 +_xt_medint3_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_3 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_3 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 3 + +#endif /* Level 3 */ + +#if XCHAL_EXCM_LEVEL >= 4 + + .begin literal_prefix .Level4InterruptVector + .section .Level4InterruptVector.text, "ax" + .global _Level4Vector + .type _Level4Vector,@function + .align 4 +_Level4Vector: + wsr a0, EXCSAVE_4 /* preserve a0 */ + call0 _xt_medint4 /* load interrupt handler */ + + .end literal_prefix + + .section .iram1,"ax" + .type _xt_medint4,@function + .align 4 +_xt_medint4: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_4 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_4 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_4 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint4_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* EXCSAVE_4 should now be free to use. Use it to keep a copy of the + current stack pointer that points to the exception frame (XT_STK_FRAME).*/ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + mov a0, sp + wsr a0, EXCSAVE_4 + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(4) | PS_UM + #else + movi a0, PS_INTLEVEL(4) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint4_exit + .type _xt_medint4_exit,@function + .align 4 +_xt_medint4_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_4 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_4 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 4 + +#endif /* Level 4 */ + +#if XCHAL_EXCM_LEVEL >= 5 + + .begin literal_prefix .Level5InterruptVector + .section .Level5InterruptVector.text, "ax" + .global _Level5Vector + .type _Level5Vector,@function + .align 4 +_Level5Vector: + wsr a0, EXCSAVE_5 /* preserve a0 */ + call0 _xt_medint5 /* load interrupt handler */ + + .end literal_prefix + + .section .iram1,"ax" + .type _xt_medint5,@function + .align 4 +_xt_medint5: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_5 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_5 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_5 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint5_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* EXCSAVE_5 should now be free to use. Use it to keep a copy of the + current stack pointer that points to the exception frame (XT_STK_FRAME).*/ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + mov a0, sp + wsr a0, EXCSAVE_5 + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(5) | PS_UM + #else + movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint5_exit + .type _xt_medint5_exit,@function + .align 4 +_xt_medint5_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_5 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_5 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 5 + +#endif /* Level 5 */ + +#if XCHAL_EXCM_LEVEL >= 6 + + .begin literal_prefix .Level6InterruptVector + .section .Level6InterruptVector.text, "ax" + .global _Level6Vector + .type _Level6Vector,@function + .align 4 +_Level6Vector: + wsr a0, EXCSAVE_6 /* preserve a0 */ + call0 _xt_medint6 /* load interrupt handler */ + + .end literal_prefix + + .section .iram1,"ax" + .type _xt_medint6,@function + .align 4 +_xt_medint6: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_6 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_6 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_6 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint6_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* EXCSAVE_6 should now be free to use. Use it to keep a copy of the + current stack pointer that points to the exception frame (XT_STK_FRAME).*/ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + mov a0, sp + wsr a0, EXCSAVE_6 + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(6) | PS_UM + #else + movi a0, PS_INTLEVEL(6) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint6_exit + .type _xt_medint6_exit,@function + .align 4 +_xt_medint6_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_6 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_6 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 6 + +#endif /* Level 6 */ + + +/******************************************************************************* + +HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS + +High priority interrupts are by definition those with priorities greater +than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority +interrupts cannot interact with the RTOS, that is they must save all regs +they use and not call any RTOS function. + +A further restriction imposed by the Xtensa windowed architecture is that +high priority interrupts must not modify the stack area even logically +"above" the top of the interrupted stack (they need to provide their +own stack or static save area). + +Cadence Design Systems recommends high priority interrupt handlers be coded in assembly +and used for purposes requiring very short service times. + +Here are templates for high priority (level 2+) interrupt vectors. +They assume only one interrupt per level to avoid the burden of identifying +which interrupts at this level are pending and enabled. This allows for +minimum latency and avoids having to save/restore a2 in addition to a0. +If more than one interrupt per high priority level is configured, this burden +is on the handler which in any case must provide a way to save and restore +registers it uses without touching the interrupted stack. + +Each vector goes at a predetermined location according to the Xtensa +hardware configuration, which is ensured by its placement in a special +section known to the Xtensa linker support package (LSP). It performs +the minimum necessary before jumping to the handler in the .text section. + +*******************************************************************************/ + +/* +These stubs just call xt_highintX/xt_nmi to handle the real interrupt. Please define +these in an external assembly source file. If these symbols are not defined anywhere +else, the defaults in xtensa_vector_defaults.S are used. +*/ + +#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2 + + .begin literal_prefix .Level2InterruptVector + .section .Level2InterruptVector.text, "ax" + .global _Level2Vector + .type _Level2Vector,@function + .global xt_highint2 + .align 4 +_Level2Vector: + wsr a0, EXCSAVE_2 /* preserve a0 */ + call0 xt_highint2 /* load interrupt handler */ + + .end literal_prefix + +#endif /* Level 2 */ + +#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3 + + .begin literal_prefix .Level3InterruptVector + .section .Level3InterruptVector.text, "ax" + .global _Level3Vector + .type _Level3Vector,@function + .global xt_highint3 + .align 4 +_Level3Vector: + wsr a0, EXCSAVE_3 /* preserve a0 */ + call0 xt_highint3 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +#endif /* Level 3 */ + +#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4 + + .begin literal_prefix .Level4InterruptVector + .section .Level4InterruptVector.text, "ax" + .global _Level4Vector + .type _Level4Vector,@function + .global xt_highint4 + .align 4 +_Level4Vector: + wsr a0, EXCSAVE_4 /* preserve a0 */ + call0 xt_highint4 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +#endif /* Level 4 */ + +#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5 + + .begin literal_prefix .Level5InterruptVector + .section .Level5InterruptVector.text, "ax" + .global _Level5Vector + .type _Level5Vector,@function + .global xt_highint5 + .align 4 +_Level5Vector: + wsr a0, EXCSAVE_5 /* preserve a0 */ + call0 xt_highint5 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +#endif /* Level 5 */ + +#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6 + + .begin literal_prefix .Level6InterruptVector + .section .Level6InterruptVector.text, "ax" + .global _Level6Vector + .type _Level6Vector,@function + .global xt_highint6 + .align 4 +_Level6Vector: + wsr a0, EXCSAVE_6 /* preserve a0 */ + call0 xt_highint6 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +#endif /* Level 6 */ + +#if XCHAL_HAVE_NMI + + .begin literal_prefix .NMIExceptionVector + .section .NMIExceptionVector.text, "ax" + .global _NMIExceptionVector + .type _NMIExceptionVector,@function + .global xt_nmi + .align 4 +_NMIExceptionVector: + wsr a0, EXCSAVE + XCHAL_NMILEVEL _ /* preserve a0 */ + call0 xt_nmi /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +#endif /* NMI */ + + +/******************************************************************************* + +WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER + +Here is the code for each window overflow/underflow exception vector and +(interspersed) efficient code for handling the alloca exception cause. +Window exceptions are handled entirely in the vector area and are very +tight for performance. The alloca exception is also handled entirely in +the window vector area so comes at essentially no cost in code size. +Users should never need to modify them and Cadence Design Systems recommends +they do not. + +Window handlers go at predetermined vector locations according to the +Xtensa hardware configuration, which is ensured by their placement in a +special section known to the Xtensa linker support package (LSP). Since +their offsets in that section are always the same, the LSPs do not define +a section per vector. + +These things are coded for XEA2 only (XEA1 is not supported). + +Note on Underflow Handlers: +The underflow handler for returning from call[i+1] to call[i] +must preserve all the registers from call[i+1]'s window. +In particular, a0 and a1 must be preserved because the RETW instruction +will be reexecuted (and may even underflow if an intervening exception +has flushed call[i]'s registers). +Registers a2 and up may contain return values. + +*******************************************************************************/ + +#if XCHAL_HAVE_WINDOWED + + .section .WindowVectors.text, "ax" + +/* +-------------------------------------------------------------------------------- +Window Overflow Exception for Call4. + +Invoked if a call[i] referenced a register (a4-a15) +that contains data from ancestor call[j]; +call[j] had done a call4 to call[j+1]. +On entry here: + window rotated to call[j] start point; + a0-a3 are registers to be saved; + a4-a15 must be preserved; + a5 is call[j+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x0 + .global _WindowOverflow4 +_WindowOverflow4: + + s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */ + s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/* +-------------------------------------------------------------------------------- +Window Underflow Exception for Call4 + +Invoked by RETW returning from call[i+1] to call[i] +where call[i]'s registers must be reloaded (not live in ARs); +where call[i] had done a call4 to call[i+1]. +On entry here: + window rotated to call[i] start point; + a0-a3 are undefined, must be reloaded with call[i].reg[0..3]; + a4-a15 must be preserved (they are call[i+1].reg[0..11]); + a5 is call[i+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x40 + .global _WindowUnderflow4 +_WindowUnderflow4: + + l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */ + rfwu + +/* +-------------------------------------------------------------------------------- +Handle alloca exception generated by interruptee executing 'movsp'. +This uses space between the window vectors, so is essentially "free". +All interruptee's regs are intact except a0 which is saved in EXCSAVE_1, +and PS.EXCM has been set by the exception hardware (can't be interrupted). +The fact the alloca exception was taken means the registers associated with +the base-save area have been spilled and will be restored by the underflow +handler, so those 4 registers are available for scratch. +The code is optimized to avoid unaligned branches and minimize cache misses. +-------------------------------------------------------------------------------- +*/ + + .align 4 + .global _xt_alloca_exc +_xt_alloca_exc: + + rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */ + rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */ + rsr a2, PS + extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS + xor a3, a3, a4 /* bits changed from old to current windowbase */ + rsr a4, EXCSAVE_1 /* restore original a0 (now in a4) */ + slli a3, a3, XCHAL_PS_OWB_SHIFT + xor a2, a2, a3 /* flip changed bits in old window base */ + wsr a2, PS /* update PS.OWB to new window base */ + rsync + + _bbci.l a4, 31, _WindowUnderflow4 + rotw -1 /* original a0 goes to a8 */ + _bbci.l a8, 30, _WindowUnderflow8 + rotw -1 + j _WindowUnderflow12 + +/* +-------------------------------------------------------------------------------- +Window Overflow Exception for Call8 + +Invoked if a call[i] referenced a register (a4-a15) +that contains data from ancestor call[j]; +call[j] had done a call8 to call[j+1]. +On entry here: + window rotated to call[j] start point; + a0-a7 are registers to be saved; + a8-a15 must be preserved; + a9 is call[j+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x80 + .global _WindowOverflow8 +_WindowOverflow8: + + s32e a0, a9, -16 /* save a0 to call[j+1]'s stack frame */ + l32e a0, a1, -12 /* a0 <- call[j-1]'s sp + (used to find end of call[j]'s frame) */ + s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a9, -4 /* save a3 to call[j+1]'s stack frame */ + s32e a4, a0, -32 /* save a4 to call[j]'s stack frame */ + s32e a5, a0, -28 /* save a5 to call[j]'s stack frame */ + s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */ + s32e a7, a0, -20 /* save a7 to call[j]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/* +-------------------------------------------------------------------------------- +Window Underflow Exception for Call8 + +Invoked by RETW returning from call[i+1] to call[i] +where call[i]'s registers must be reloaded (not live in ARs); +where call[i] had done a call8 to call[i+1]. +On entry here: + window rotated to call[i] start point; + a0-a7 are undefined, must be reloaded with call[i].reg[0..7]; + a8-a15 must be preserved (they are call[i+1].reg[0..7]); + a9 is call[i+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0xC0 + .global _WindowUnderflow8 +_WindowUnderflow8: + + l32e a0, a9, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a7, a1, -12 /* a7 <- call[i-1]'s sp + (used to find end of call[i]'s frame) */ + l32e a3, a9, -4 /* restore a3 from call[i+1]'s stack frame */ + l32e a4, a7, -32 /* restore a4 from call[i]'s stack frame */ + l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */ + l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */ + l32e a7, a7, -20 /* restore a7 from call[i]'s stack frame */ + rfwu + +/* +-------------------------------------------------------------------------------- +Window Overflow Exception for Call12 + +Invoked if a call[i] referenced a register (a4-a15) +that contains data from ancestor call[j]; +call[j] had done a call12 to call[j+1]. +On entry here: + window rotated to call[j] start point; + a0-a11 are registers to be saved; + a12-a15 must be preserved; + a13 is call[j+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x100 + .global _WindowOverflow12 +_WindowOverflow12: + + s32e a0, a13, -16 /* save a0 to call[j+1]'s stack frame */ + l32e a0, a1, -12 /* a0 <- call[j-1]'s sp + (used to find end of call[j]'s frame) */ + s32e a1, a13, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a13, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a13, -4 /* save a3 to call[j+1]'s stack frame */ + s32e a4, a0, -48 /* save a4 to end of call[j]'s stack frame */ + s32e a5, a0, -44 /* save a5 to end of call[j]'s stack frame */ + s32e a6, a0, -40 /* save a6 to end of call[j]'s stack frame */ + s32e a7, a0, -36 /* save a7 to end of call[j]'s stack frame */ + s32e a8, a0, -32 /* save a8 to end of call[j]'s stack frame */ + s32e a9, a0, -28 /* save a9 to end of call[j]'s stack frame */ + s32e a10, a0, -24 /* save a10 to end of call[j]'s stack frame */ + s32e a11, a0, -20 /* save a11 to end of call[j]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/* +-------------------------------------------------------------------------------- +Window Underflow Exception for Call12 + +Invoked by RETW returning from call[i+1] to call[i] +where call[i]'s registers must be reloaded (not live in ARs); +where call[i] had done a call12 to call[i+1]. +On entry here: + window rotated to call[i] start point; + a0-a11 are undefined, must be reloaded with call[i].reg[0..11]; + a12-a15 must be preserved (they are call[i+1].reg[0..3]); + a13 is call[i+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x140 + .global _WindowUnderflow12 +_WindowUnderflow12: + + l32e a0, a13, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a13, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a13, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a11, a1, -12 /* a11 <- call[i-1]'s sp + (used to find end of call[i]'s frame) */ + l32e a3, a13, -4 /* restore a3 from call[i+1]'s stack frame */ + l32e a4, a11, -48 /* restore a4 from end of call[i]'s stack frame */ + l32e a5, a11, -44 /* restore a5 from end of call[i]'s stack frame */ + l32e a6, a11, -40 /* restore a6 from end of call[i]'s stack frame */ + l32e a7, a11, -36 /* restore a7 from end of call[i]'s stack frame */ + l32e a8, a11, -32 /* restore a8 from end of call[i]'s stack frame */ + l32e a9, a11, -28 /* restore a9 from end of call[i]'s stack frame */ + l32e a10, a11, -24 /* restore a10 from end of call[i]'s stack frame */ + l32e a11, a11, -20 /* restore a11 from end of call[i]'s stack frame */ + rfwu + +#endif /* XCHAL_HAVE_WINDOWED */ + + .section .UserEnter.text, "ax" + .global call_user_start + .type call_user_start,@function + .align 4 + .literal_position + + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/KnownIssues.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/KnownIssues.md new file mode 100644 index 0000000..593a411 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/KnownIssues.md @@ -0,0 +1,7 @@ +# Known Issues +This document lists the known issues in various FreeRTOS third +party ports. + +## ThirdParty/GCC/ARC_EM_HS +* [Memory Read Protection Violation from Secure MPU on exit from +interrupt](https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/331) diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/README.md b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/README.md new file mode 100644 index 0000000..93a4398 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/README.md @@ -0,0 +1,51 @@ +# FreeRTOS Third Party Ports + +FreeRTOS third party ports can be supported by the FreeRTOS team, a FreeRTOS +partner or FreeRTOS community members. Depending on who supports it, the support +provided will differ as follows: + +## FreeRTOS Team Supported Third Party FreeRTOS Ports + +Location: https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/main/portable/ThirdParty + +These third party FreeRTOS ports are supported by the FreeRTOS team. For a +FreeRTOS team supported third party FreeRTOS port: + +* The code has been reviewed by the FreeRTOS team. +* FreeRTOS team has access to the hardware and the test results have been + verified by the FreeRTOS team. +* Customer queries as well as bugs are addressed by the FreeRTOS team. +* The code can be included in Long Term Support (LTS) releases. + +A new FreeRTOS port cannot be directly contributed to this location. Instead, +the FreeRTOS team will decide to take ownership of a partner supported or a +community supported FreeRTOS port based on the community interest. + +## Partner Supported FreeRTOS Ports + +Location: https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports/tree/main + +These FreeRTOS ports are supported by a FreeRTOS partner. For a partner +supported FreeRTOS port: + +* The code has not been reviewed by the FreeRTOS team. +* FreeRTOS team has not verified the tests results but tests exist and are + reported to be successful by the partner. +* Customer queries as well as bugs are addressed by the partner. + +A new FreeRTOS port can be directly contributed by a partner. The process to +contribute a FreeRTOS port is documented [here](https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports/blob/main/README.md). + +## Community Supported FreeRTOS Ports + +Location: https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports/tree/main + +These FreeRTOS ports are supported by the FreeRTOS community members. For a +community supported FreeRTOS port: + +* The code has not been reviewed by the FreeRTOS team. +* Tests may or may not exist for the FreeRTOS port. +* Customer queries as well as bugs are addressed by the community. + +A new FreeRTOS port can be directly contributed by anyone. The process to +contribute a FreeRTOS port is documented [here](https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports/blob/main/README.md). diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/Makefile b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/Makefile new file mode 100644 index 0000000..6a0d3b0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/Makefile @@ -0,0 +1,98 @@ +### Makefile to build the FreeRTOS library ### + +# Build target (options: sim, board) + +TARGET = sim +SMALL = + +# Tools + +CC = xt-xcc +AS = xt-xcc +AR = xt-ar +XT_CORE = $(patsubst %-params,%,$(notdir $(shell xt-xcc --show-config=core))) +CONFIGDIR = $(shell xt-xcc --show-config=config) + +# For platform-specific commands + +include $(CONFIGDIR)/misc/hostenv.mk + +# Source code and build locations + +SRCROOT = $(subst /,$(S),$(CURDIR)) +TSTROOT = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..$(S)..$(S)..$(S)demos$(S)cadence$(S)sim$(SMALL)) +BLDROOT = $(TSTROOT)$(S)build +BLDDIR = $(BLDROOT)$(S)$(XT_CORE) + +FR_SRCDIR = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..) +FR_SRCDIR2 = $(FR_SRCDIR)$(S)portable$(S)MemMang +XT_SRCDIR = $(SRCROOT) + +vpath %.c $(FR_SRCDIR) $(FR_SRCDIR2) $(XT_SRCDIR) +vpath %.S $(XT_SRCDIR) + +# File lists + +FR_C_FILES = $(notdir $(wildcard $(FR_SRCDIR)/*.c)) $(notdir $(wildcard $(FR_SRCDIR2)/*.c)) +XT_C_FILES = $(notdir $(wildcard $(XT_SRCDIR)/*.c)) +XT_S_FILES = $(notdir $(wildcard $(XT_SRCDIR)/*.S)) + +# List of all .o files that will go into the library + +LIB_C_O = $(patsubst %.c,%.o,$(XT_C_FILES) $(FR_C_FILES)) +LIB_S_O = $(patsubst %.S,%.o,$(XT_S_FILES)) +LIB_O_LIST = $(addprefix $(BLDDIR)/,$(LIB_C_O) $(LIB_S_O)) + +# Output files + +OSLIB = $(BLDDIR)$(S)libfreertos.a + +# Build options + +ifeq ($(TARGET),sim) +DFLAGS = -DXT_SIMULATOR +endif +ifeq ($(TARGET),board) +DFLAGS = -DXT_BOARD +endif + +IFLAGS = \ + -I$(FR_SRCDIR)$(S)..$(S)include -I$(FR_SRCDIR)$(S)..$(S)include$(S)private \ + -I$(XT_SRCDIR) -I$(TSTROOT)$(S)common$(S)config_files -I$(BLDDIR) + +CFLAGS = -O2 -g +CCFLAGS = $(CFLAGS) -Wall -mno-coproc -mlongcalls -ffunction-sections -mno-l32r-flix $(DFLAGS) +ASFLAGS = $(CCFLAGS) + +# Include dependency rules (generated using -MD) + +-include $(wildcard $(BLDDIR)/*.d) + +# Targets + +all : mkdir $(OSLIB) + +mkdir : $(BLDDIR)/.mkdir + +$(BLDDIR)/.mkdir : + @$(MKPATH) $(BLDDIR) + @echo "" > $@ + -$(CP) $(CONFIGDIR)/xtensa-elf/include/sys/reent.h $(BLDDIR)/reent.h + +$(OSLIB) : $(LIB_O_LIST) + $(AR) -rs $@ $^ + +$(BLDDIR)/%.o : %.c + $(CC) $(CCFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $< + +$(BLDDIR)/%.o : %.S + $(CC) $(ASFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $< + +clean : + $(RM_R) $(BLDDIR) + +clean_all : + $(RM_R) $(BLDROOT) + +.PHONY : all mkdir clean clean_all + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/port.c new file mode 100644 index 0000000..7d27049 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/port.c @@ -0,0 +1,207 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include + +#include "xtensa_rtos.h" + +#include "FreeRTOS.h" +#include "task.h" + + +/* Defined in portasm.h */ +extern void _frxt_tick_timer_init(void); + +/* Defined in xtensa_context.S */ +extern void _xt_coproc_init(void); + + +/*-----------------------------------------------------------*/ + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +unsigned port_xSchedulerRunning = 0; // Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting +unsigned port_interruptNesting = 0; // Interrupt nesting level + +/*-----------------------------------------------------------*/ + +// User exception dispatcher when exiting +void _xt_user_exit(void); + +/* + * Stack initialization + */ +#if portUSING_MPU_WRAPPERS +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) +#else +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +#endif +{ + StackType_t * sp, * tp; + XtExcFrame * frame; + + #if XCHAL_CP_NUM > 0 + uint32_t * p; + #endif + + /* Create interrupt stack frame aligned to 16 byte boundary */ + sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - XT_STK_FRMSZ ) & ~0xf ); + + /* Clear the entire frame (do not use memset() because we don't depend on C library) */ + for( tp = sp; tp <= pxTopOfStack; ++tp ) + { + *tp = 0; + } + + frame = ( XtExcFrame * ) sp; + + /* Explicitly initialize certain saved registers */ + frame->pc = ( UBaseType_t ) pxCode; /* task entrypoint */ + frame->a0 = 0; /* to terminate GDB backtrace */ + frame->a1 = ( UBaseType_t ) sp + XT_STK_FRMSZ; /* physical top of stack frame */ + frame->exit = ( UBaseType_t ) _xt_user_exit; /* user exception exit dispatcher */ + + /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */ + /* Also set entry point argument parameter. */ + #ifdef __XTENSA_CALL0_ABI__ + frame->a2 = ( UBaseType_t ) pvParameters; + frame->ps = PS_UM | PS_EXCM; + #else + /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */ + frame->a6 = ( UBaseType_t ) pvParameters; + frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC( 1 ); + #endif + + #ifdef XT_USE_SWPRI + /* Set the initial virtual priority mask value to all 1's. */ + frame->vpri = 0xFFFFFFFF; + #endif + + #if XCHAL_CP_NUM > 0 + /* Init the coprocessor save area (see xtensa_context.h) */ + + /* No access to TCB here, so derive indirectly. Stack growth is top to bottom. + * //p = (uint32_t *) xMPUSettings->coproc_area; + */ + p = ( uint32_t * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE ) & ~0xf ); + configASSERT( ( uint32_t ) p >= frame->a1 ); + p[ 0 ] = 0; + p[ 1 ] = 0; + p[ 2 ] = ( ( ( uint32_t ) p ) + 12 + XCHAL_TOTAL_SA_ALIGN - 1 ) & -XCHAL_TOTAL_SA_ALIGN; + #endif + + return sp; +} + +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the Xtensa port will get stopped. If required simply + disable the tick interrupt here. */ +} + +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + // Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored + + #if XCHAL_CP_NUM > 0 + /* Initialize co-processor management for tasks. Leave CPENABLE alone. */ + _xt_coproc_init(); + #endif + + /* Init the tick divisor value */ + _xt_tick_divisor_init(); + + /* Setup the hardware to generate the tick. */ + _frxt_tick_timer_init(); + + #if XT_USE_THREAD_SAFE_CLIB + // Init C library + vPortClibInit(); + #endif + + port_xSchedulerRunning = 1; + + // Cannot be directly called from C; never returns + __asm__ volatile ("call0 _frxt_dispatch\n"); + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortSysTickHandler( void ) +{ + BaseType_t ret; + uint32_t interruptMask; + + portbenchmarkIntLatency(); + + /* Interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY must be + * disabled before calling xTaskIncrementTick as it access the + * kernel lists. */ + interruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + ret = xTaskIncrementTick(); + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( interruptMask ); + + portYIELD_FROM_ISR( ret ); + + return ret; +} +/*-----------------------------------------------------------*/ + +/* + * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area. + */ +#if portUSING_MPU_WRAPPERS +void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) +{ + #if XCHAL_CP_NUM > 0 + xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + ulStackDepth - 1 )); + xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); + xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf ); + + /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to + * clear the stack area after we return. This is done in pxPortInitialiseStack(). + */ + #endif +} +#endif /* if portUSING_MPU_WRAPPERS */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/portasm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/portasm.S new file mode 100644 index 0000000..39d68bb --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/portasm.S @@ -0,0 +1,601 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "xtensa_rtos.h" + +#define TOPOFSTACK_OFFS 0x00 /* StackType_t *pxTopOfStack */ +#define CP_TOPOFSTACK_OFFS 0x04 /* xMPU_SETTINGS.coproc_area */ + +.extern pxCurrentTCB + + +/* +******************************************************************************* +* Interrupt stack. The size of the interrupt stack is determined by the config +* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h +******************************************************************************* +*/ + .data + .align 16 + .global port_IntStack +port_IntStack: + .space configISR_STACK_SIZE +port_IntStackTop: + .word 0 +port_switch_flag: + .word 0 + + .text +/* +******************************************************************************* +* _frxt_setup_switch +* void _frxt_setup_switch(void); +* +* Sets an internal flag indicating that a task switch is required on return +* from interrupt handling. +* +******************************************************************************* +*/ + .global _frxt_setup_switch + .type _frxt_setup_switch,@function + .align 4 +_frxt_setup_switch: + + ENTRY(16) + + movi a2, port_switch_flag + movi a3, 1 + s32i a3, a2, 0 + + RET(16) + +/* +******************************************************************************* +* _frxt_int_enter +* void _frxt_int_enter(void) +* +* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for +* freeRTOS. Saves the rest of the interrupt context (not already saved). +* May only be called from assembly code by the 'call0' instruction, with +* interrupts disabled. +* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h. +* +******************************************************************************* +*/ + .globl _frxt_int_enter + .type _frxt_int_enter,@function + .align 4 +_frxt_int_enter: + + /* Save a12-13 in the stack frame as required by _xt_context_save. */ + s32i a12, a1, XT_STK_A12 + s32i a13, a1, XT_STK_A13 + + /* Save return address in a safe place (free a0). */ + mov a12, a0 + + /* Save the rest of the interrupted context (preserves A12-13). */ + call0 _xt_context_save + + /* + Save interrupted task's SP in TCB only if not nesting. + Manage nesting directly rather than call the generic IntEnter() + (in windowed ABI we can't call a C function here anyway because PS.EXCM is still set). + */ + movi a2, port_xSchedulerRunning + movi a3, port_interruptNesting + l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */ + beqz a2, 1f /* scheduler not running, no tasks */ + l32i a2, a3, 0 /* a2 = port_interruptNesting */ + addi a2, a2, 1 /* increment nesting count */ + s32i a2, a3, 0 /* save nesting count */ + bnei a2, 1, .Lnested /* !=0 before incr, so nested */ + + movi a2, pxCurrentTCB + l32i a2, a2, 0 /* a2 = current TCB */ + beqz a2, 1f + s32i a1, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */ + movi a1, port_IntStackTop /* a1 = top of intr stack */ + +.Lnested: +1: + mov a0, a12 /* restore return addr and return */ + ret + +/* +******************************************************************************* +* _frxt_int_exit +* void _frxt_int_exit(void) +* +* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for +* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context +* switching, restore the (possibly) new task's context, and return to the +* exit dispatcher saved in the task's stack frame at XT_STK_EXIT. +* May only be called from assembly code by the 'call0' instruction. Does not +* return to caller. +* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h. +* +******************************************************************************* +*/ + .globl _frxt_int_exit + .type _frxt_int_exit,@function + .align 4 +_frxt_int_exit: + + movi a2, port_xSchedulerRunning + movi a3, port_interruptNesting + rsil a0, XCHAL_EXCM_LEVEL /* lock out interrupts */ + l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */ + beqz a2, .Lnoswitch /* scheduler not running, no tasks */ + l32i a2, a3, 0 /* a2 = port_interruptNesting */ + addi a2, a2, -1 /* decrement nesting count */ + s32i a2, a3, 0 /* save nesting count */ + bnez a2, .Lnesting /* !=0 after decr so still nested */ + + movi a2, pxCurrentTCB + l32i a2, a2, 0 /* a2 = current TCB */ + beqz a2, 1f /* no task ? go to dispatcher */ + l32i a1, a2, TOPOFSTACK_OFFS /* SP = pxCurrentTCB->pxTopOfStack */ + + movi a2, port_switch_flag /* address of switch flag */ + l32i a3, a2, 0 /* a3 = port_switch_flag */ + beqz a3, .Lnoswitch /* flag = 0 means no switch reqd */ + movi a3, 0 + s32i a3, a2, 0 /* zero out the flag for next time */ + +1: + /* + Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption. + However a12-13 were already saved by _frxt_int_enter(). + */ + #ifdef __XTENSA_CALL0_ABI__ + s32i a14, a1, XT_STK_A14 + s32i a15, a1, XT_STK_A15 + #endif + + #ifdef __XTENSA_CALL0_ABI__ + call0 vPortYieldFromInt /* call dispatch inside the function; never returns */ + #else + call4 vPortYieldFromInt /* this one returns */ + call0 _frxt_dispatch /* tail-call dispatcher */ + /* Never returns here. */ + #endif + +.Lnoswitch: + /* + If we came here then about to resume the interrupted task. + */ + +.Lnesting: + /* + We come here only if there was no context switch, that is if this + is a nested interrupt, or the interrupted task was not preempted. + In either case there's no need to load the SP. + */ + + /* Restore full context from interrupt stack frame */ + call0 _xt_context_restore + + /* + Must return via the exit dispatcher corresponding to the entrypoint from which + this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt + stack frame is deallocated in the exit dispatcher. + */ + l32i a0, a1, XT_STK_EXIT + ret + + +/* +********************************************************************************************************** +* _frxt_timer_int +* void _frxt_timer_int(void) +* +* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS. +* Called every timer interrupt. +* Manages the tick timer and calls xPortSysTickHandler() every tick. +* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h. +* +* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance. +* +********************************************************************************************************** +*/ + .globl _frxt_timer_int + .type _frxt_timer_int,@function + .align 4 +_frxt_timer_int: + + /* + Xtensa timers work by comparing a cycle counter with a preset value. Once the match occurs + an interrupt is generated, and the handler has to set a new cycle count into the comparator. + To avoid clock drift due to interrupt latency, the new cycle count is computed from the old, + not the time the interrupt was serviced. However if a timer interrupt is ever serviced more + than one tick late, it is necessary to process multiple ticks until the new cycle count is + in the future, otherwise the next timer interrupt would not occur until after the cycle + counter had wrapped (2^32 cycles later). + + do { + ticks++; + old_ccompare = read_ccompare_i(); + write_ccompare_i( old_ccompare + divisor ); + service one tick; + diff = read_ccount() - old_ccompare; + } while ( diff > divisor ); + */ + + ENTRY(16) + +.L_xt_timer_int_catchup: + + /* Update the timer comparator for the next tick. */ + #ifdef XT_CLOCK_FREQ + movi a2, XT_TICK_DIVISOR /* a2 = comparator increment */ + #else + movi a3, _xt_tick_divisor + l32i a2, a3, 0 /* a2 = comparator increment */ + #endif + rsr a3, XT_CCOMPARE /* a3 = old comparator value */ + add a4, a3, a2 /* a4 = new comparator value */ + wsr a4, XT_CCOMPARE /* update comp. and clear interrupt */ + esync + + #ifdef __XTENSA_CALL0_ABI__ + /* Preserve a2 and a3 across C calls. */ + s32i a2, sp, 4 + s32i a3, sp, 8 + #endif + + /* Call the FreeRTOS tick handler (see port.c). */ + #ifdef __XTENSA_CALL0_ABI__ + call0 xPortSysTickHandler + #else + call4 xPortSysTickHandler + #endif + + #ifdef __XTENSA_CALL0_ABI__ + /* Restore a2 and a3. */ + l32i a2, sp, 4 + l32i a3, sp, 8 + #endif + + /* Check if we need to process more ticks to catch up. */ + esync /* ensure comparator update complete */ + rsr a4, CCOUNT /* a4 = cycle count */ + sub a4, a4, a3 /* diff = ccount - old comparator */ + blt a2, a4, .L_xt_timer_int_catchup /* repeat while diff > divisor */ + + RET(16) + + /* +********************************************************************************************************** +* _frxt_tick_timer_init +* void _frxt_tick_timer_init(void) +* +* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called). +* Callable from C (obeys ABI conventions on entry). +* +********************************************************************************************************** +*/ + .globl _frxt_tick_timer_init + .type _frxt_tick_timer_init,@function + .align 4 +_frxt_tick_timer_init: + + ENTRY(16) + + /* Set up the periodic tick timer (assume enough time to complete init). */ + #ifdef XT_CLOCK_FREQ + movi a3, XT_TICK_DIVISOR + #else + movi a2, _xt_tick_divisor + l32i a3, a2, 0 + #endif + rsr a2, CCOUNT /* current cycle count */ + add a2, a2, a3 /* time of first timer interrupt */ + wsr a2, XT_CCOMPARE /* set the comparator */ + + /* + Enable the timer interrupt at the device level. Don't write directly + to the INTENABLE register because it may be virtualized. + */ + #ifdef __XTENSA_CALL0_ABI__ + movi a2, XT_TIMER_INTEN + call0 xt_ints_on + #else + movi a6, XT_TIMER_INTEN + call4 xt_ints_on + #endif + + RET(16) + +/* +********************************************************************************************************** +* DISPATCH THE HIGH READY TASK +* void _frxt_dispatch(void) +* +* Switch context to the highest priority ready task, restore its state and dispatch control to it. +* +* This is a common dispatcher that acts as a shared exit path for all the context switch functions +* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher +* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ). +* +* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see +* comments on stack frames in xtensa_context.h). This function restores the state accordingly. +* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear. +* If restoring a task that was preempted, restores all state including the task's CPENABLE. +* +* Entry: +* pxCurrentTCB points to the TCB of the task to suspend, +* Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction. +* +* Exit: +* If incoming task called vPortYield() (solicited), this function returns as if from vPortYield(). +* If incoming task was preempted by an interrupt, this function jumps to exit dispatcher. +* +********************************************************************************************************** +*/ + .globl _frxt_dispatch + .type _frxt_dispatch,@function + .align 4 +_frxt_dispatch: + + #ifdef __XTENSA_CALL0_ABI__ + call0 vTaskSwitchContext // Get next TCB to resume + movi a2, pxCurrentTCB + #else + movi a2, pxCurrentTCB + call4 vTaskSwitchContext // Get next TCB to resume + #endif + l32i a3, a2, 0 + l32i sp, a3, TOPOFSTACK_OFFS /* SP = next_TCB->pxTopOfStack; */ + s32i a3, a2, 0 + + /* Determine the type of stack frame. */ + l32i a2, sp, XT_STK_EXIT /* exit dispatcher or solicited flag */ + bnez a2, .L_frxt_dispatch_stk + +.L_frxt_dispatch_sol: + + /* Solicited stack frame. Restore minimal context and return from vPortYield(). */ + l32i a3, sp, XT_SOL_PS + #ifdef __XTENSA_CALL0_ABI__ + l32i a12, sp, XT_SOL_A12 + l32i a13, sp, XT_SOL_A13 + l32i a14, sp, XT_SOL_A14 + l32i a15, sp, XT_SOL_A15 + #endif + l32i a0, sp, XT_SOL_PC + #if XCHAL_CP_NUM > 0 + /* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */ + rsync + #endif + /* As soons as PS is restored, interrupts can happen. No need to sync PS. */ + wsr a3, PS + #ifdef __XTENSA_CALL0_ABI__ + addi sp, sp, XT_SOL_FRMSZ + ret + #else + retw + #endif + +.L_frxt_dispatch_stk: + + #if XCHAL_CP_NUM > 0 + /* Restore CPENABLE from task's co-processor save area. */ + movi a3, pxCurrentTCB /* cp_state = */ + l32i a3, a3, 0 + l32i a2, a3, CP_TOPOFSTACK_OFFS /* StackType_t *pxStack; */ + l16ui a3, a2, XT_CPENABLE /* CPENABLE = cp_state->cpenable; */ + wsr a3, CPENABLE + #endif + + /* Interrupt stack frame. Restore full context and return to exit dispatcher. */ + call0 _xt_context_restore + + /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */ + #ifdef __XTENSA_CALL0_ABI__ + l32i a14, sp, XT_STK_A14 + l32i a15, sp, XT_STK_A15 + #endif + + #if XCHAL_CP_NUM > 0 + /* Ensure wsr.CPENABLE has completed. */ + rsync + #endif + + /* + Must return via the exit dispatcher corresponding to the entrypoint from which + this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt + stack frame is deallocated in the exit dispatcher. + */ + l32i a0, sp, XT_STK_EXIT + ret + + +/* +********************************************************************************************************** +* PERFORM A SOLICTED CONTEXT SWITCH (from a task) +* void vPortYield(void) +* +* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE, +* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch +* +* At Entry: +* pxCurrentTCB points to the TCB of the task to suspend +* Callable from C (obeys ABI conventions on entry). +* +* Does not return to caller. +* +********************************************************************************************************** +*/ + .globl vPortYield + .type vPortYield,@function + .align 4 +vPortYield: + + #ifdef __XTENSA_CALL0_ABI__ + addi sp, sp, -XT_SOL_FRMSZ + #else + entry sp, XT_SOL_FRMSZ + #endif + + rsr a2, PS + s32i a0, sp, XT_SOL_PC + s32i a2, sp, XT_SOL_PS + #ifdef __XTENSA_CALL0_ABI__ + s32i a12, sp, XT_SOL_A12 /* save callee-saved registers */ + s32i a13, sp, XT_SOL_A13 + s32i a14, sp, XT_SOL_A14 + s32i a15, sp, XT_SOL_A15 + #else + /* Spill register windows. Calling xthal_window_spill() causes extra */ + /* spills and reloads, so we will set things up to call the _nw version */ + /* instead to save cycles. */ + movi a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK) /* spills a4-a7 if needed */ + and a2, a2, a6 /* clear WOE, INTLEVEL */ + addi a2, a2, XCHAL_EXCM_LEVEL /* set INTLEVEL */ + wsr a2, PS + rsync + call0 xthal_window_spill_nw + l32i a2, sp, XT_SOL_PS /* restore PS */ + wsr a2, PS + #endif + + rsil a2, XCHAL_EXCM_LEVEL /* disable low/med interrupts */ + + #if XCHAL_CP_NUM > 0 + /* Save coprocessor callee-saved state (if any). At this point CPENABLE */ + /* should still reflect which CPs were in use (enabled). */ + call0 _xt_coproc_savecs + #endif + + movi a2, pxCurrentTCB + movi a3, 0 + l32i a2, a2, 0 /* a2 = pxCurrentTCB */ + s32i a3, sp, XT_SOL_EXIT /* 0 to flag as solicited frame */ + s32i sp, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */ + + #if XCHAL_CP_NUM > 0 + /* Clear CPENABLE, also in task's co-processor state save area. */ + l32i a2, a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state */ + movi a3, 0 + wsr a3, CPENABLE + beqz a2, 1f + s16i a3, a2, XT_CPENABLE /* clear saved cpenable */ +1: + #endif + + /* Tail-call dispatcher. */ + call0 _frxt_dispatch + /* Never reaches here. */ + + +/* +********************************************************************************************************** +* PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt) +* void vPortYieldFromInt(void) +* +* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher +* _frxt_dispatch() to perform the actual context switch. +* +* At Entry: +* Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack. +* pxCurrentTCB points to the TCB of the task to suspend, +* Callable from C (obeys ABI conventions on entry). +* +* At Exit: +* Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry. +* Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller. +* +********************************************************************************************************** +*/ + .globl vPortYieldFromInt + .type vPortYieldFromInt,@function + .align 4 +vPortYieldFromInt: + + ENTRY(16) + + #if XCHAL_CP_NUM > 0 + /* Save CPENABLE in task's co-processor save area, and clear CPENABLE. */ + movi a3, pxCurrentTCB /* cp_state = */ + l32i a3, a3, 0 + l32i a2, a3, CP_TOPOFSTACK_OFFS + + rsr a3, CPENABLE + s16i a3, a2, XT_CPENABLE /* cp_state->cpenable = CPENABLE; */ + movi a3, 0 + wsr a3, CPENABLE /* disable all co-processors */ + #endif + + #ifdef __XTENSA_CALL0_ABI__ + /* Tail-call dispatcher. */ + call0 _frxt_dispatch + /* Never reaches here. */ + #else + RET(16) + #endif + +/* +********************************************************************************************************** +* _frxt_task_coproc_state +* void _frxt_task_coproc_state(void) +* +* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS. +* +* May only be called when a task is running, not within an interrupt handler (returns 0 in that case). +* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions. +* Returns in A15 a pointer to the base of the co-processor state save area for the current task. +* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h. +* +********************************************************************************************************** +*/ +#if XCHAL_CP_NUM > 0 + + .globl _frxt_task_coproc_state + .type _frxt_task_coproc_state,@function + .align 4 +_frxt_task_coproc_state: + + movi a15, port_xSchedulerRunning /* if (port_xSchedulerRunning */ + l32i a15, a15, 0 + beqz a15, 1f + movi a15, port_interruptNesting /* && port_interruptNesting == 0 */ + l32i a15, a15, 0 + bnez a15, 1f + movi a15, pxCurrentTCB + l32i a15, a15, 0 /* && pxCurrentTCB != 0) { */ + beqz a15, 2f + l32i a15, a15, CP_TOPOFSTACK_OFFS + ret + +1: movi a15, 0 +2: ret + +#endif /* XCHAL_CP_NUM > 0 */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/portbenchmark.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/portbenchmark.h new file mode 100644 index 0000000..080aca8 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/portbenchmark.h @@ -0,0 +1,51 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This utility helps benchmarking interrupt latency and context switches. + * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h. + * You will also need to download the FreeRTOS_trace patch that contains + * portbenchmark.c and the complete version of portbenchmark.h + */ + +#ifndef PORTBENCHMARK_H +#define PORTBENCHMARK_H + +#if configBENCHMARK + #error "You need to download the FreeRTOS_trace patch that overwrites this file" +#endif + +#define portbenchmarkINTERRUPT_DISABLE() +#define portbenchmarkINTERRUPT_RESTORE(newstate) +#define portbenchmarkIntLatency() +#define portbenchmarkIntWait() +#define portbenchmarkReset() +#define portbenchmarkPrint() + +#endif /* PORTBENCHMARK */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/portclib.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/portclib.c new file mode 100644 index 0000000..f5572aa --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/portclib.c @@ -0,0 +1,230 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOS.h" + +#if XT_USE_THREAD_SAFE_CLIB + +#if XSHAL_CLIB == XTHAL_CLIB_XCLIB + +#include +#include + +#include "semphr.h" + +typedef SemaphoreHandle_t _Rmtx; + +//----------------------------------------------------------------------------- +// Override this and set to nonzero to enable locking. +//----------------------------------------------------------------------------- +int32_t _xclib_use_mt = 1; + + +//----------------------------------------------------------------------------- +// Init lock. +//----------------------------------------------------------------------------- +void +_Mtxinit(_Rmtx * mtx) +{ + *mtx = xSemaphoreCreateRecursiveMutex(); +} + +//----------------------------------------------------------------------------- +// Destroy lock. +//----------------------------------------------------------------------------- +void +_Mtxdst(_Rmtx * mtx) +{ + if ((mtx != NULL) && (*mtx != NULL)) { + vSemaphoreDelete(*mtx); + } +} + +//----------------------------------------------------------------------------- +// Lock. +//----------------------------------------------------------------------------- +void +_Mtxlock(_Rmtx * mtx) +{ + if ((mtx != NULL) && (*mtx != NULL)) { + xSemaphoreTakeRecursive(*mtx, portMAX_DELAY); + } +} + +//----------------------------------------------------------------------------- +// Unlock. +//----------------------------------------------------------------------------- +void +_Mtxunlock(_Rmtx * mtx) +{ + if ((mtx != NULL) && (*mtx != NULL)) { + xSemaphoreGiveRecursive(*mtx); + } +} + +//----------------------------------------------------------------------------- +// Called by malloc() to allocate blocks of memory from the heap. +//----------------------------------------------------------------------------- +void * +_sbrk_r (struct _reent * reent, int32_t incr) +{ + extern char _end; + extern char _heap_sentry; + static char * _heap_sentry_ptr = &_heap_sentry; + static char * heap_ptr; + char * base; + + if (!heap_ptr) + heap_ptr = (char *) &_end; + + base = heap_ptr; + if (heap_ptr + incr >= _heap_sentry_ptr) { + reent->_errno = ENOMEM; + return (char *) -1; + } + + heap_ptr += incr; + return base; +} + +//----------------------------------------------------------------------------- +// Global initialization for C library. +//----------------------------------------------------------------------------- +void +vPortClibInit(void) +{ +} + +//----------------------------------------------------------------------------- +// Per-thread cleanup stub provided for linking, does nothing. +//----------------------------------------------------------------------------- +void +_reclaim_reent(void * ptr) +{ +} + +#endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */ + +#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB + +#include +#include +#include +#include +#include + +#include "semphr.h" + +static SemaphoreHandle_t xClibMutex; +static uint32_t ulClibInitDone = 0; + +//----------------------------------------------------------------------------- +// Get C library lock. +//----------------------------------------------------------------------------- +void +__malloc_lock(struct _reent * ptr) +{ + if (!ulClibInitDone) + return; + + xSemaphoreTakeRecursive(xClibMutex, portMAX_DELAY); +} + +//----------------------------------------------------------------------------- +// Release C library lock. +//----------------------------------------------------------------------------- +void +__malloc_unlock(struct _reent * ptr) +{ + if (!ulClibInitDone) + return; + + xSemaphoreGiveRecursive(xClibMutex); +} + +//----------------------------------------------------------------------------- +// Lock for environment. Since we have only one global lock we can just call +// the malloc() lock function. +//----------------------------------------------------------------------------- +void +__env_lock(struct _reent * ptr) +{ + __malloc_lock(ptr); +} + + +//----------------------------------------------------------------------------- +// Unlock environment. +//----------------------------------------------------------------------------- +void +__env_unlock(struct _reent * ptr) +{ + __malloc_unlock(ptr); +} + +//----------------------------------------------------------------------------- +// Called by malloc() to allocate blocks of memory from the heap. +//----------------------------------------------------------------------------- +void * +_sbrk_r (struct _reent * reent, int32_t incr) +{ + extern char _end; + extern char _heap_sentry; + static char * _heap_sentry_ptr = &_heap_sentry; + static char * heap_ptr; + char * base; + + if (!heap_ptr) + heap_ptr = (char *) &_end; + + base = heap_ptr; + if (heap_ptr + incr >= _heap_sentry_ptr) { + reent->_errno = ENOMEM; + return (char *) -1; + } + + heap_ptr += incr; + return base; +} + +//----------------------------------------------------------------------------- +// Global initialization for C library. +//----------------------------------------------------------------------------- +void +vPortClibInit(void) +{ + configASSERT(!ulClibInitDone); + + xClibMutex = xSemaphoreCreateRecursiveMutex(); + ulClibInitDone = 1; +} + +#endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */ + +#endif /* XT_USE_THREAD_SAFE_CLIB */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/portmacro.h new file mode 100644 index 0000000..9ae6751 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/portmacro.h @@ -0,0 +1,210 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __ASSEMBLER__ + +#include + +#include +#include +#include +#include /* required for XSHAL_CLIB */ +#include + +//#include "xtensa_context.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + +#define portCHAR int8_t +#define portFLOAT float +#define portDOUBLE double +#define portLONG int32_t +#define portSHORT int16_t +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE int + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef unsigned portBASE_TYPE UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +// portbenchmark +#include "portbenchmark.h" + +/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */ +// These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. +#define portDISABLE_INTERRUPTS() do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0) +#define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0) + +// These can be nested +#define portCRITICAL_NESTING_IN_TCB 1 // For now, let FreeRTOS' (tasks.c) manage critical nesting +void vTaskEnterCritical(void); +void vTaskExitCritical(void); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +// Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack. +// They can be called from interrupts too. +static inline unsigned portENTER_CRITICAL_NESTED() { unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); return state; } +#define portEXIT_CRITICAL_NESTED(state) do { portbenchmarkINTERRUPT_RESTORE(state); XTOS_RESTORE_JUST_INTLEVEL(state); } while (0) + +// These FreeRTOS versions are similar to the nested versions above +#define portSET_INTERRUPT_MASK_FROM_ISR() portENTER_CRITICAL_NESTED() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(state) portEXIT_CRITICAL_NESTED(state) + +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() XT_NOP() +/*-----------------------------------------------------------*/ + +/* Fine resolution time */ +#define portGET_RUN_TIME_COUNTER_VALUE() xthal_get_ccount() + +/* Kernel utilities. */ +void vPortYield( void ); +void _frxt_setup_switch( void ); +#define portYIELD() vPortYield() +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) \ + if ( ( xHigherPriorityTaskWoken ) != 0 ) { \ + _frxt_setup_switch(); \ + } + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +// When coprocessors are defined, we to maintain a pointer to coprocessors area. +// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: +// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. +// The field is normally used for memory protection. FreeRTOS should create another general purpose field. +typedef struct { + #if XCHAL_CP_NUM > 0 + volatile StackType_t* coproc_area; // Pointer to coprocessor save area; MUST BE FIRST + #endif + + #if portUSING_MPU_WRAPPERS + // Define here mpu_settings, which is port dependent + int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet + #endif + + #if configUSE_TRACE_FACILITY_2 + struct { + // Cf. porttraceStamp() + int taskstamp; /* Stamp from inside task to see where we are */ + int taskstampcount; /* A counter usually incremented when we restart the task's loop */ + } porttrace; + #endif +} xMPU_SETTINGS; + +// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) +#if (XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2) && !portUSING_MPU_WRAPPERS // If MPU wrappers not used, we still need to allocate coproc area + #undef portUSING_MPU_WRAPPERS + #define portUSING_MPU_WRAPPERS 1 // Enable it to allocate coproc area + #define MPU_WRAPPERS_H // Override mpu_wrapper.h to disable unwanted code + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA +#endif + +// porttrace +#if configUSE_TRACE_FACILITY_2 +#include "porttrace.h" +#endif + +// configASSERT_2 if requested +#if configASSERT_2 +#include +void exit(int); +#define configASSERT( x ) if (!(x)) { porttracePrint(-1); printf("\nAssertion failed in %s:%d\n", __FILE__, __LINE__); exit(-1); } +#endif + + +/* C library support -- only XCLIB and NEWLIB are supported. */ + +/* To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must be + defined to be > 0 somewhere above or on the command line. */ + +#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_XCLIB) +extern void vPortClibInit(void); +#endif // XCLIB support + +#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_NEWLIB) +extern void vPortClibInit(void); + +// This C library cleanup is not currently done by FreeRTOS when deleting a task +#include +#define portCLEAN_UP_TCB(pxTCB) vPortCleanUpTcbClib(&((pxTCB)->xNewLib_reent)) +static inline void vPortCleanUpTcbClib(struct _reent *ptr) +{ + FILE * fp = &(ptr->__sf[0]); + int i; + for (i = 0; i < 3; ++i, ++fp) { + fp->_close = NULL; + } +} +#endif // NEWLIB support + +#endif // __ASSEMBLER__ + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/porttrace.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/porttrace.h new file mode 100644 index 0000000..a989f7c --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/porttrace.h @@ -0,0 +1,49 @@ + /* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This utility helps tracing the entering and exiting from tasks. + * It maintains a circular buffer of tasks in the order they execute, + * and their execution time. To enable it, set configUSE_TRACE_FACILITY_2 + * to 1 in FreeRTOSConfig.h. You will also need to download the + * FreeRTOS_trace patch that contains porttrace.c and the complete version + * of porttrace.h. + */ + +#ifndef PORTTRACE_H +#define PORTTRACE_H + +#if configUSE_TRACE_FACILITY_2 + #error "You need to download the FreeRTOS_trace patch that overwrites this file" +#endif + +#define porttracePrint(nelements) +#define porttraceStamp(stamp, count_incr) + +#endif /* PORTTRACE_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt new file mode 100644 index 0000000..247d731 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt @@ -0,0 +1,764 @@ + FreeRTOS Port for Xtensa Configurable and Diamond Processors + ============================================================ + + FreeRTOS Kernel Version 10.0.0 + + +Introduction +------------ + +This document describes the Xtensa port for FreeRTOS multitasking RTOS. +For an introduction to FreeRTOS itself, please refer to FreeRTOS +documentation. + +This port currently works with FreeRTOS kernel version 10.0.0. + + +Xtensa Configuration Requirements and Restrictions +-------------------------------------------------- + +The Xtensa configurable architecture supports a vast space of processor +features. This port supports all of them, including custom processor +extensions defined in the TIE language, with certain minimum +requirements. You must use Xtensa Tools to compile and link FreeRTOS and +your application for your Xtensa configuration. The port uses the Xtensa +Hardware Abstraction Layer (HAL) to adapt to your Xtensa configuration. +NOTE: It may be possible to build and run this with the open-source +xtensa-linux tools provided you have the correct overlay for your Xtensa +configuration. However, this has not been tested and is currently not +supported by Cadence. + +This port includes optional reentrancy support for the 'newlib' and +'xclib' C runtime libraries distributed with Xtensa Tools, providing +thread-safety on a per task basis (for use in tasks only, not interrupt +handlers). + +NOTE: At this time only 'newlib' and 'xclib' C libraries are supported +for thread safety. The 'uclibc' library is not reentrant and does not +provide thread safety at this time. However, if you are not concerned +with reentrancy then you can use any of these libraries. + +This port also includes a simple example application that may run on +a supported board or the Xtensa instruction set simulator (ISS). There +are also a couple of test programs used in maintaining the port, which +serve as additional examples. + +FreeRTOS for Xtensa configurable processors requires the following minimum +processor configuration options: +- Timer interrupt option with at least one interruptible timer. +- Interrupt option (implied by the timer interrupt option). +- Exception Architecture 2 (XEA2). Please note that XEA1 is NOT supported. + All 'Diamond', 'Xtensa 6', 'Xtensa LX' and 'Xtensa LX2' processors and + most 'Xtensa T1050' processors are configured with XEA2. +All Diamond processor cores meet these requirements and are supported. + +Minimal support for certain evaluation boards is provided via a board +independent XTBSP API implemented by a board specific library distributed +with the Xtensa Tools. This provides the board clock frequency and basic +polled drivers for the display and console device. Note that XTBSP +is not a tradtional RTOS "board support package" with RTOS specific +interrupt-driven drivers - it is not specific to any RTOS. Note that +FreeRTOS can run on any Xtensa or Diamond board without this board support +(a "raw" platform), but you will have to provide the clock frequency +and drivers for any on-board devices you want to use. + + +Installation +------------ + +The Xtensa port of FreeRTOS is available at this location: + + https://github.com/foss-xtensa/amazon-freertos + +This download includes the core FreeRTOS source and include files needed +to build the port. You can also download the official release of FreeRTOS +version 1.0.0 or later from this location: + + https://github.com/aws/amazon-freertos + +The Xtensa port files are currently not included in the official package. + +All source is provided along with a Makefile that works for any host +platform supported by Xtensa Tools (Windows, Linux). These instructions +are written for Windows users, but can easily be understood and adapted +to other host platforms. + +First install the FreeRTOS common package in a directory of your choosing. +The structure of that package will look like this: + + +|-- demos +| `-- cadence +| `-- sim +| |-- common +| | |-- application_code +| | | `-- cadence_code +| | `-- config_files +| `-- xplorer +`-- lib + |-- FreeRTOS + | `-- portable + | |-- Common + | |-- MemMang + | `-- XCC + | `-- Xtensa + `-- include + `-- private + +The Xtensa Tools are available from Cadence as part of a processor +license. Be sure you have installed the Xtensa Tools and your processor +configuration. + + +Building FreeRTOS for Xtensa +---------------------------- + +To build the FreeRTOS library and the example programs, go into the +directory 'demos/cadence/sim' and use the makefile in that directory. +"make all" will build all the examples. There is another makefile in +the 'lib/FreeRTOS/portable/XCC/Xtensa' directory that builds just the +FreeRTOS library. + +By default, you will build for the Xtensa instruction set simulator. If +you have a supported emulation board, you can build to run on that. You +can also build to run on a raw Xtensa core with no board support, a +good starting point for supporting your own target platform. Cadence +recommends doing functional development on the simulator because it +is easier to debug with, then move to a board if/when you need to test +hardware drivers or real-time performance. + +The provided makefile simplifies building FreeRTOS and the example +for your Xtensa configuration and platform (ISS, board, etc.). There +are detailed instructions in the comments at the top of the makefile. + +The makefiles work on Windows and Linux and support incremental builds. +The build for each Xtensa configuration and target platform is placed in +a subdirectory so several core and platform builds can co-exist even with +incremental rebuilds. You may specify the root of the build area (if tou +want it to be elsewhere than under the source tree) by defining BLDROOT +either in the make command or your shell environment. + + +Building the FreeRTOS Library +----------------------------- + +First, be sure you have installed Xtensa Tools and your processor +configuration, and be sure that Xtensa Tools are in your search path. +You can use xt-make, which comes with the Xtensa Tools, to run the +makefiles. + +Change directories to the Xtensa port directory: + +> cd lib/FreeRTOS/portable/XCC/Xtensa + +Now build the FreeRTOS RTOS as a library (libfreertos.a) as follows: + +> xt-make + +which by default builds for the simulator (TARGET=sim), or: + +> xt-make TARGET=board + +which builds for a supported board. Note that the board type does not +need to be specified when building the FreeRTOS library. + +If you are building for an Xtensa processor configuration that is not the +default you selected when you installed Xtensa Tools, you need to define the +environment variable XTENSA_CORE. If your configuration is not in the +default registry you selected when you installed Xtensa Tools, you also +need to define the environment variable XTENSA_SYSTEM. See tools manuals. +You can avoid defining these in your environment if you pass the variables +you need to redefine into xt-make as follows: + +> xt-make XTENSA_CORE= XTENSA_SYSTEM= ... + +There are more details about build options in the comment in the Makefile. + +After the library has been built, you must link your application with this +library in order to use FreeRTOS. + + +Building the FreeRTOS Examples +------------------------------ + +The provided examples are designed to run on the Xtensa instruction set +simulator (ISS) or a supported evaluation board programmed with your +Xtensa processor configuration. + +To build the examples for the default platform (simulator): + +> cd demos/cadence/sim + +> xt-make all + +which is the same as + +> xt-make all TARGET=sim + +The boards currently supported are the Xilinx ML605 and KC705 FPGA +development boards. To target these boards, type + +> xt-make all TARGET=ml605 + +or + +> xt-make all TARGET=kc705 + +To build in a location other than the default, specify the new location +using the BLDROOT variable. Note that this makefile will invoke the +FreeRTOS library build makefile automatically, passing on the relevant +parameters based on what you specified. + +You can override the default compilation options by specifying the new +options via CFLAGS. For example: + +> xt-make all TARGET=sim CFLAGS="-O2 -Os -g" + +This compiles the examples and links them with the FreeRTOS library +libfreertos.a and the appropriate linker-support package (LSP) for your +target platform (you can override the LSP by adding LSP= to the +xt-make command line). The resulting ELF files can be downloaded and +executed on the target. The example binaries appear in the platform +specific subdirectory described earlier. + +To build your application with thread-safe C library support, you +need to make certain modifications to the application to plug in and +invoke the reentrancy support. This allows each task to use the library +without interference with other tasks (it is not safe for interrupt +handlers to call the C library). + +First, you must define + + XT_USE_THREAD_SAFE_CLIB + +to a nonzero value either in xtensa_config.h or on the compiler's command +line. Note that the default xtensa_config.h provided with this port does +define this to 1 if either newlib or xclib is detected. + +Then, you must also make sure to allocate extra space on the stack for +each task that will use the C library reentrant functions. This extra +space is to be allocated over and above the actual stack space required +by the task itself. The define + + XT_STACK_EXTRA_CLIB + +specifies the amount of extra space to be added on to the stack to allow +saving the context for the C library as well as the coprocessors if any. +E.g. if your task requires 2000 bytes of stack space, you must allocate +(2000 + XT_STACK_EXTRA_CLIB) bytes for the stack. + + +IMPORTANT NOTE +-------------- + +The header file FreeRTOS.h, which is a part of the core FreeRTOS sources, +includes if thread safety for the C libraries is enabled. For +xclib, this file exists in and so is reported as missing. +To work around this, the makefiles supplied with this port will copy the +reent.h header into the build directory during the build process. If you +use a different build process, then you must make sure to copy this file +to a location that is included in the list of include paths. This can be +the build directory or the directory that contains the Xtensa port source +files. + + +Running or Debugging an Application +----------------------------------- + +To execute the example application on the simulator: + +> xt-run [--turbo] example.exe + +The option --turbo provides much faster, but non-cycle-accurate simulation +(the --turbo option is only available with Xtensa Tools version 7 or later). + + +To execute on the simulator using the Xplorer GUI based debugger: + +> xplorer --debug example.exe + + +To execute on a supported evaluation board, download example.exe per +instructions in the tools manuals. Be sure the board has been programmed +with the correct configuration and is set up to boot from RAM and debug +a downloaded program! Optionally you may connect a terminal or terminal +emulator to the serial port on the board with settings as described in +the board user manual, and see the output of printf on the terminal. + +To obtain I/O on a "raw" platform such as an unsupported board, you need +to provide low level I/O drivers (eg. inbyte() and outbyte() for character +I/O if you want to use printf etc.). You can run "raw" executables on +any Xtensa platform, including simulator and any board, but you will not +see any behavior specific to the platform (eg. display, printed output, +stopping simulation at end of program). You can, while debugging, use a +debugger mechanism called GDBIO to obtain basic I/O. To use GDBIO, link +with the gdbio LSP. Refer to Xtensa tools documentation for details. + + +Task Stack Sizes +---------------- + +The application must ensure that every task has enough space for its +stack. Each task needs enough space for its own use, its own interrupt +stack frame (defined in xtensa_context.h) and space to save coprocessor +state, if any. Several factors influence the size of the stack required, +including the compiler optimization level and the use of the C library. +Calls to standard output functions such as printf() can use up a lot of +stack space. The tool xt-stack-usage is helpful in determining safe stack +sizes for your application. + +Some macros are provided in xtensa_config.h to help determine the stack +size for tasks that do and do not use the C library. Use these as the +basis for each task's stack size. They are minimum requirements taking +into account your configuration and use of the C library. In particular, +the define + + XT_STACK_MIN_SIZE + +defines the minimum stack size for any task. Be very careful if you try +to use a stack size smaller than this minimum. Stack overruns can cause +all kinds of hard-to-debug errors. It is recommended that you enable the +FreeRTOS stack checking features during development. + +WARNING: The newlib printf() function uses a lot of stack space. Be very +careful in using it. Optionally you can use the 'libxtutil' library for +output - it implements a subset of printf() that has smaller code size +and uses far less stack space. More information about this library is in +the Xtensa Tools documentation. + + +Interrupt Stack +--------------- + +Beginning with port version 1.2, the port uses a separate interrupt stack +for handling interrupts. Thus, it is no longer necessary for each task to +reserve space on its stack to handle interrupts. The size of the interrupt +stack is controlled by the parameter "configISR_STACK_SIZE" defined in +FreeRTOSConfig.h. Define this carefully to match your system requirements. + + +Assembler / Compiler Switches +----------------------------- + +The following are compiler switches are used by the provided +Makefile in building the FreeRTOS library and example application. +These can be modified by editing the Makefile or by overriding the +CFLAGS variable in the make command line, for example: + +> xt-make CFLAGS="-O2 -DXT_USE_THREAD_SAFE_CLIB" + + -g Specifies debug information. + -c Specifies object code generation. + -On Sets compiler optimization level n (default -O0). + -mlongcalls Allows assembler and linker to convert call + instructions to longer indirect call sequences + when target is out of range. + -x assembler-with-cpp Passes .s and .S files through C preprocessor. + -Dmacro Define a preprocessor macro with no value. + -Dmacro=value Define a preprocessor macro with a value. + +See the compiler / linker documentation for a full list of switches and +their use. + +Many definitions can be provided at compile-time via the -D option +without editing the source code. Here are some of the more useful ones: + + XT_USE_THREAD_SAFE_CLIB Enable support for the reentrancy to provide + thread-safety for the newlib and xclib libraries + supplied with Xtensa Tools. Default ON. + + Note, the follwing defines are unique to the Xtensa port so have names + beginning with "XT_". + + XT_SIMULATOR Set this if building to run on the simulator. + Takes advantage of certain simulator control + and reporting facilities, and adjusts timing + of periodic tick to provide a more acceptable + performance in simulation (see XT_CLOCK_FREQ). + Set by default unless PLATFORM is overridden. + + XT_BOARD Set this if building for a supported board. + Be sure to specify the correct LSP for the + board. See the example makefile for usage. + + XT_CLOCK_FREQ=freq Specifies the target processor's clock + frequency in Hz. Used primarily to set the + timer that generates the periodic interrupt. + Defaults are provided and may be edited in + xtensa_timer.h (see comments there also). + Default for simulator provides more acceptable + performance, but cannot provide real-time + performance due to variation in simulation + speed per host platform and insufficient + cycles between interrupts to process them. + Supported board platforms by default leave + this undefined and compute the clock frequency + at initialization unless this is explicitly + defined. + + XT_TICK_PER_SEC=n Specifies the frequency of the periodic tick. + + XT_TIMER_INDEX=n Specifies which timer to use for periodic tick. + Set this if your Xtensa processor configuration + provides more than one suitable timer and you + want to override the default. See xtensa_timer.h . + + XT_INTEXC_HOOKS Enables hooks in interrupt vector handlers + to support dynamic installation of exception + and interrupt handlers. Disabled by default. + + XT_USE_OVLY Enable code overlay support. It uses a mutex, + hence configUSE_MUTEX must be enabled. This + option is currently unsupported. + + XT_USE_SWPRI Enable software prioritization of interrupts. + Enabling this will prioritize interrupts with + higher bit numbers over those with lower bit + numbers at the same level. This works only for + low and medium priority interrupts that can be + dispatched to C handlers. + + +Register Usage and Stack Frames +------------------------------- + +The Xtensa architecture specifies two ABIs that determine how the general +purpose registers a0-a15 are used: the standard windowed ABI use with +the Xtensa windowed register file architecture, and the optional and +more conventional Call0 ABI (required for Xtensa configurations without +a windowed register file). + +Xtensa processors may have other special registers (including co-processor +registers and other TIE "states") that are independent of this choice +of ABI. See Xtensa documentation for more details. + +In the windowed ABI the registers of the current window are used as follows: + a0 = return address + a1 = stack pointer (alias sp) + a2 = first argument and result of call (in simple cases) + a3-7 = second through sixth arguments of call (in simple cases). + Note that complex or large arguments are passed on the + stack. Details are in the Xtensa Tools manuals. + a8-a15 = available for use as temporaries. +There are no callee-save registers. The windowed hardware automatically +saves registers a0-a3 on a call4, a0-a8 on a call8, a0-a12 on a call12, +by rotating the register window. Hardware triggers window overflow and +underflow exceptions as necessary when registers outside the current +window need to be spilled to preallocated space in the stack frame, or +restored. Complete details are in the Xtensa manuals. The entire windowed +register file is saved and restored on interrupt or task context switch. + +The Call0 ABI does not make use of register windows, relying instead +on a fixed set of 16 registers without window rotation. +The Call0 ABI is more conventional and uses registers as follows: + a0 = return address + a1 = stack pointer (alias sp) + a2 = first argument and result of call (in simple cases) + a3-7 = second through sixth arguments of call (in simple cases). + Note that complex or large arguments are passed on the + stack. Details are in the Xtensa Tools manuals. + a8-a11 = scratch. + a12-a15 = callee-save (a function must preserve these for its caller). +On a FreeRTOS API call, callee-save registers are saved only when a task +context switch occurs, and other registers are not saved at all (the caller +does not expect them to be preserved). On an interrupt, callee-saved +registers might only be saved and restored when a task context-switch +occurs, but all other registers are always saved and restored. + +An Xtensa processor has other special registers independent of the ABI, +depending on the configuration (including co-processor registers and other +TIE state) that are part of the task context. FreeRTOS preserves all such +registers over an unsolicited context-switch triggered by an interrupt. +However it does NOT preserve these over a solicited context-switch during +a FreeRTOS API call. This bears some explanation. These special registers +are either ignored by the compiler or treated as caller-saved, meaning +that if kept "live" over a function call (ie. need to be preserved) +they must be saved and restored by the caller. Since solicited entry to +FreeRTOS is always made by a function call, FreeRTOS assumes the caller +has saved any of these registers that are "live". FreeRTOS avoids a lot +of overhead by not having to save and restore every special register +(there can be many) on every solicited context switch. + +As a consequence, the application developer should NOT assume that special +registers are preserved over a FreeRTOS API call such as vTaskDelay(). +If multiple tasks use a register, the caller must save and restore it. + +The saved context stack frames for context switches that occur as +a result of interrupt handling (interrupt frame) or from task-level +API calls (solicited frame) are described in human readable form in +xtensa_context.h . All suspended tasks have one of these two types +of stack frames. The top of the suspended task's stack is pointed to +by pxCurrentTCB->pxTopOfStack. A special location common to both stack +frames differentiates solicited and interrupt stack frames. + + +Improving Performance, Footprint, or Ease of Debugging +------------------------------------------------------ + +By default FreeRTOS for Xtensa is built with debug (-g) and without +compiler optimizations (-O0). This makes debugging easier. Of course, +-O0 costs performance and usually also increases stack usage. To make +FreeRTOS run faster you can change the Makefile to enable the desired +optimizations or set a predefined optimization level (-O) . + +Maximum performance is achieved with -O3 -ipa, but that might increase +the footprint substantially. A good compromise is -O2. See the compiler +manual for details. + +Minimal footprint is achieved by optimizing for space with -Os, at the +cost of some performance. See the compiler manual for details. + +The Xtensa architecture port-specific assembly files are coded with no +file-scope labels inside functions (all labels inside functions begin with +".L"). This allows a profiler to accurately associate an address with a +function, and also allows the debugger's stack trace to show the correct +function wherever the program counter is within that function. However +there are some tradeoffs in debugging. Local (".L") labels are not +visible to the debugger, so the following limitations may be observed +during debugging: +- You cannot set a breakpoint on a local label inside a function. +- Disassembly will show the entire function, but will get out of sync and + show incorrect opcodes if it crosses any padding before an aligned local + branch target (".L" label, not ".Ln"). Restart disassembly specifying an + address range explicitly between points where there is padding. +Since FreeRTOS is provided in source form, it is not difficult to remove +the ".L" and ".Ln" prefixes from local labels if you want them visible. +They can also be made visible by passing the '-L' option to the assembler +and linker (see the assembler and linker manuals for details). + + +Interrupt and Exception Handling +-------------------------------- + +FreeRTOS provides a complete set of efficient exception and first-level +interrupt handlers installed at the appropriate exception and interrupt +vector locations. The Xtensa architecture supports several different +classes of exceptions and interrupts. Being a configurable architecture, +many of these are optional, and the vector locations are determined by +your processor configuration. (Note that Diamond cores are pre-configured +with specific vector locations.) The handlers provided use conditional +compilation to adapt to your processor configuration and include only +the code that is needed. + +Xtensa vector locations may reside almost anywhere, including in ROM. +The amount of code space available at each of these locations is +often very small (e.g. due to following vectors). A small stub of +code installed at the vector jumps to the corresponding handler, +usually in RAM. The exception and interrupt handlers are defined in +xtensa_vectors.S. They are not specific to FreeRTOS, but call into +FreeRTOS where appropriate via macros defined in xtensa_rtos.h . + +The handlers provided for low and medium priority interrupts are just +dispatchers that save relevant state and call user-definable handlers. +See the files xtensa_vectors.S and xtensa_api.h for more details of how +to create and install application-specific user interrupt handlers. +Similarly, user-defined handlers can be installed for exceptions (other +than a few which are always handled by the OS). + +The high priority interrupt handlers provided may be considered templates +into which the application adds code to service specific interrupts. +The places where application handlers should be inserted are tagged with +the comment "USER_EDIT" in xtensa_vectors.S. + +This FreeRTOS port supports strict priority-based nesting of interrupts. +An interrupt may only nest on top of one of strictly lower priority. +Equal priority interrupts concurrently pending are handled in an +application-defined sequence before any lower priority interrupts +are handled. During interrupt and exception handling, the processor's +interrupt level (PS.INTLEVEL) is used to control the interrupt priority +level that can be accepted; interrupt sources are not controlled +individually by FreeRTOS (the application is free to access the INTENABLE +register directly to enable/disable individual interrupts, eg. using +Xtensa HAL services). This approach provides the most deterministic +bounds on interrupt latency (for a given priority) and stack depth. + +Software prioritization of interrupts at the same priority is controlled +by the definition of XT_USE_SWPRI. See above for a description of this +parameter. + +The following subsections describe the handling of each class of exception +and interrupt in more detail. Many have nothing to do with FreeRTOS but +are mentioned because there is code to handle them in xtensa_vectors.S. + +User Exception and Interrupt Handler (Low/Medium Priority): + + All Xtensa 'general exceptions' come to the user, kernel, or double + exception vector. The exception type is identified by the EXCCAUSE + special register (level 1 interrupts are one particular cause of a + general exception). This port sets up PS to direct all such exceptions + to the user vector. Exceptions taken at the other two vectors usually + indicate a kernel or application bug. + + Level 1 interrupts are identified at the beginning of the handler + and are dispatched to a dedicated handler. Then, syscall and alloca + exceptions are identified and dispatched to special handlers described + below. After this, coprocessor exceptions are identified and dispatched + to the coprocessor handler. + + Any remaining exceptions are processed as follows: + + Having allocated the exception stack frame, the user exception handler + saves the current task state and sets up a C environment and enables + the high-priority class of interrupts (which do not interact with + FreeRTOS), then reads EXCCAUSE and uses the cause (number) to index + into a table of user-specified handlers. The correct handler is then + called. If the handler returns, the context is restored and control is + returned to the code that caused the exception. The user-defined handler + may alter the saved context, or any other system state, that allows the + faulting instruction to be retried. + + If the cause is a level 1 (low-priority) or medium-priority interrupt, + the handler enables all interrupts above that priority level after + saving the task context. It then sets up the environment for C code + and then calls the handler (found in the handler table) for the + interrupt number. If the user has not specified a handler, then the + default handler will be called, which will terminate the program. + + If the interrupt is for the system timer, it calls a special interrupt + handler for the system timer tick, which calls _frxt_timer_int then + clears its bit from the mask. This interrupt cannot be hooked by the + user-defined handler. + + Finally, the handler calls _frxt_int_exit to allow FreeRTOS to perform + any scheduling necessary and return either to the interrupted task + or another. + + If software prioritization is enabled, the handler will re-enable all + interrupts at the same level that are numerically higher than the current + one, before calling the user handler. This allows a higher priority + interrupt to pre-empt the lower priority handler. + +Medium Priority Interrupt Handlers: + + Medium priority interrupts are those at levels 2 up to XCHAL_EXCM_LEVEL, + a configuration-specific maximum interrupt level affected by the global + 'exception mode' bit in the processor status word (PS.EXCM). + Interrupt levels above XCHAL_EXCM_LEVEL are of the high-priority class. + The Xtensa hardware documentation considers medium priority interrupts + to be a special case of high-priority interrupts, but from a software + perspective they are very different. + + Dispatch of medium-priority interrupts is discussed in the section + above. + +High Priority Interrupt Handlers: + + High priority interrupts are those strictly above XCHAL_EXCM_LEVEL, + a configuration-specific maximum interrupt level affected by the + global 'exception mode' bit in the processor status word (PS.EXCM). + High priority handlers may not directly interact with FreeRTOS at all, + and are described here only for the sake of completeness. They must + be coded in assembler (may not be coded in C) and are intended to be + used for handling extremely high frequency hardware events that need + to be handled in only a few cycles. A high priority interrupt handler + may trigger a software interrupt at a medium or low priority level to + occasionally signal FreeRTOS. Please see Xtensa documentation. + + There is a separate vector and a few special registers for each high + priority interrupt, providing for fast dispatch and efficient nesting + on top of lower priority interrupts. Handlers are templates included + only for the vectors that exist in your Xtensa processor configuration. + These templates are written for only one interrupt per high priority + level to minimize latency servicing very fast time-critical interrupts. + The vector code jumps to the corresponding first-level interrupt handler, + which then executes application-provided assembler code before returning + quickly to the interrupted task or lower priority handler. + +Kernel Exception Handler: + + Kernel mode is not used in this port of FreeRTOS, and therefore kernel + exceptions should not happen. A stub is provided for the vector that + triggers the debugger (if connected) or calls _xt_panic to freeze the + processor should a kernel exception occur. + +Alloca Exception Handler: + + Alloca exceptions are generated by the 'movsp' instruction, which + is used only in the windowed ABI. Its purpose is to allocate some + space on top of the stack. Because the window hardware may have + spilled some registers to the 16 byte "base save" area below the + stack pointer, it is necessary to protect those values. The alloca + handler accomplishes this quickly without setting up an interrupt + frame or entering FreeRTOS, by emulating a register underflow and + re-executing 'movsp'. + +Syscall Exception Handler: + + Syscall exceptions are generated by a 'syscall' instruction. + The windowed ABI specifies that executing this instruction with + a value of zero in register a2 must spill any unsaved registers + in the windowed register file to their pre-determined locations + on the caller's stack. The handler does exactly that, and skips + over the 'syscall' instruction before returning to the caller. + If a2 is non-zero, the handler returns a2 == -1 to the caller. + +Co-Processor Exception Handler: + + A co-processor exception is generated when a task accesses a + co-processor that it does not "own". Ownership represents which + task's state is currently in the co-processor. Co-processors are + context-switched "lazily" (on demand) only when a non-owning task + uses a co-processor instruction, otherwise a task retains ownership + even when it is preempted from the main processor. The co-processor + exception handler performs the context-switch and manages ownership. + + Co-processors may not be used by any code outside the context of a + task. A co-processor exception triggered by code that is not part + of a running task is a fatal error and FreeRTOS for Xtensa will panic. + This restriction is intended to reduce the overhead of saving and + restoring co-processor state (which can be quite large) and in + particular remove that overhead from interrupt handlers. + +Debug Exception Handler: + + A debug exception is caused as a result of running code, such as by + a 'break' instruction or hardware breakpoints and watchpoints, or + as a result of an external debug interrupt, such as from an OCD based + debugger or multiprocessor debug events ("breakin/breakout"). If the + processor is running in OCD mode under control of an OCD-based debugger, + the trigger event immediately halts the processor and gives control to + the OCD debugger. Otherwise control is transferred to the debug vector. + The debug vector handler calls the simulator if running on the ISS, + which then takes control and interacts with any attached debugger. + If running on hardware and not in OCD mode, debug exceptions are not + expected, so the debug handler calls _xt_panic to freeze the processor. + +Double Exception Handler: + + A double exception is a general exception that happens while the + processor is in exception mode (PS.EXCM set), and thus indicates a + bug in kernel code. The double exception vector handler triggers + the debugger (if connected) or calls _xt_panic to freeze the + processor. + +Window Overflow and Underflow Exception Handlers: + + Window overflow and underflow handlers are required for use of the + windowed ABI. Each has its own dedicated vector and highly optimized + code that is independent of OS. See Xtensa documentation for details. + +Hooks for Dynamic Installation of Handlers: + + Optional hooks are provided in the user exception and low level + interrupt handler and all medium and high priority interrupt handlers, + to dynamically install a handler function (which may be coded in C, + unless in a high-priority interrupt handler). These hooks are enabled + and used by automatic regression tests, they are not part of a normal + FreeRTOS build. However an application is free to take advantage of + them. The interrupt/exception hooks are described in xtensa_rtos.h . + + It is recommended that the application not make use of these hooks, but + rather use xt_set_interrupt_handler() and xt_set_exception_handler() + to install application-specific handlers. This method is more convenient + and allows arguments to be passed to the handlers. Software prioritization + of interrupts works only with this method. See xtensa_api.h for details. + +Overlay Support + + Code overlays are currently not supported for FreeRTOS. This will be + supported in a future release. Make sure that the option XT_USE_OVLY is + never defined when building. + + +-End- + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_api.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_api.h new file mode 100644 index 0000000..62f52aa --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_api.h @@ -0,0 +1,128 @@ + /* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Xtensa-specific API for RTOS ports. + */ + +#ifndef __XTENSA_API_H__ +#define __XTENSA_API_H__ + +#include + +#include "xtensa_context.h" + + +/* Typedef for C-callable interrupt handler function */ +typedef void (*xt_handler)(void *); + +/* Typedef for C-callable exception handler function */ +typedef void (*xt_exc_handler)(XtExcFrame *); + + +/* +------------------------------------------------------------------------------- + Call this function to set a handler for the specified exception. + + n - Exception number (type) + f - Handler function address, NULL to uninstall handler. + + The handler will be passed a pointer to the exception frame, which is created + on the stack of the thread that caused the exception. + + If the handler returns, the thread context will be restored and the faulting + instruction will be retried. Any values in the exception frame that are + modified by the handler will be restored as part of the context. For details + of the exception frame structure see xtensa_context.h. +------------------------------------------------------------------------------- +*/ +extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f); + + +/* +------------------------------------------------------------------------------- + Call this function to set a handler for the specified interrupt. + + n - Interrupt number. + f - Handler function address, NULL to uninstall handler. + arg - Argument to be passed to handler. +------------------------------------------------------------------------------- +*/ +extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg); + + +/* +------------------------------------------------------------------------------- + Call this function to enable the specified interrupts. + + mask - Bit mask of interrupts to be enabled. + + Returns the previous state of the interrupt enables. +------------------------------------------------------------------------------- +*/ +extern unsigned int xt_ints_on(unsigned int mask); + + +/* +------------------------------------------------------------------------------- + Call this function to disable the specified interrupts. + + mask - Bit mask of interrupts to be disabled. + + Returns the previous state of the interrupt enables. +------------------------------------------------------------------------------- +*/ +extern unsigned int xt_ints_off(unsigned int mask); + + +/* +------------------------------------------------------------------------------- + Call this function to set the specified (s/w) interrupt. +------------------------------------------------------------------------------- +*/ +static inline void xt_set_intset(unsigned int arg) +{ + xthal_set_intset(arg); +} + + +/* +------------------------------------------------------------------------------- + Call this function to clear the specified (s/w or edge-triggered) + interrupt. +------------------------------------------------------------------------------- +*/ +static inline void xt_set_intclear(unsigned int arg) +{ + xthal_set_intclear(arg); +} + + +#endif /* __XTENSA_API_H__ */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_config.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_config.h new file mode 100644 index 0000000..201a0c9 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_config.h @@ -0,0 +1,188 @@ + /* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Configuration-specific information for Xtensa build. This file must be + * included in FreeRTOSConfig.h to properly set up the config-dependent + * parameters correctly. + * + * NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must + * be defined to be > 0 somewhere above or on the command line. + */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include /* required for XSHAL_CLIB */ + +#include "xtensa_context.h" + + +/*----------------------------------------------------------------------------- +* STACK REQUIREMENTS +* +* This section defines the minimum stack size, and the extra space required to +* be allocated for saving coprocessor state and/or C library state information +* (if thread safety is enabled for the C library). The sizes are in bytes. +* +* Stack sizes for individual tasks should be derived from these minima based on +* the maximum call depth of the task and the maximum level of interrupt nesting. +* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based +* on the requirement for a task that calls nothing else but can be interrupted. +* This assumes that interrupt handlers do not call more than a few levels deep. +* If this is not true, i.e. one or more interrupt handlers make deep calls then +* the minimum must be increased. +* +* If the Xtensa processor configuration includes coprocessors, then space is +* allocated to save the coprocessor state on the stack. +* +* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB +* is defined) then space is allocated to save the C library context in the TCB. +* +* Allocating insufficient stack space is a common source of hard-to-find errors. +* During development, it is best to enable the FreeRTOS stack checking features. +* +* Usage: +* +* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe +* use of the C library. This will require extra stack +* space to be allocated for tasks that use the C library +* reentrant functions. See below for more information. +* +* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them +* support thread safety. Check your core configuration to see which C library +* was chosen for your system. +* +* XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended +* that you do not use a stack smaller than this for any +* task. In case you want to use stacks smaller than this +* size, you must verify that the smaller size(s) will work +* under all operating conditions. +* +* XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task +* that does not make C library reentrant calls. Add this +* to the amount of stack space required by the task itself. +* +* XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state. +* +-----------------------------------------------------------------------------*/ + +/* Extra space required for interrupt/exception hooks. */ +#ifdef XT_INTEXC_HOOKS + #ifdef __XTENSA_CALL0_ABI__ + #define STK_INTEXC_EXTRA 0x200 + #else + #define STK_INTEXC_EXTRA 0x180 + #endif +#else + #define STK_INTEXC_EXTRA 0 +#endif + +/* Check C library thread safety support and compute size of C library save area. + For the supported libraries, we enable thread safety by default, and this can + be overridden from the compiler/make command line. */ +#if (XSHAL_CLIB == XTHAL_CLIB_NEWLIB) || (XSHAL_CLIB == XTHAL_CLIB_XCLIB) + #ifndef XT_USE_THREAD_SAFE_CLIB + #define XT_USE_THREAD_SAFE_CLIB 1 + #endif +#else + #define XT_USE_THREAD_SAFE_CLIB 0 +#endif + +#if XT_USE_THREAD_SAFE_CLIB > 0u + #if XSHAL_CLIB == XTHAL_CLIB_XCLIB + #define XT_HAVE_THREAD_SAFE_CLIB 1 + #if !defined __ASSEMBLER__ + #include + #define XT_CLIB_CONTEXT_AREA_SIZE ((sizeof(struct _reent) + 15) + (-16)) + #define XT_CLIB_GLOBAL_PTR _reent_ptr + #define _REENT_INIT_PTR _init_reent + #define _impure_ptr _reent_ptr + + void _reclaim_reent(void * ptr); + #endif + #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB + #define XT_HAVE_THREAD_SAFE_CLIB 1 + #if !defined __ASSEMBLER__ + #include + #define XT_CLIB_CONTEXT_AREA_SIZE ((sizeof(struct _reent) + 15) + (-16)) + #define XT_CLIB_GLOBAL_PTR _impure_ptr + #endif + #else + #define XT_HAVE_THREAD_SAFE_CLIB 0 + #error The selected C runtime library is not thread safe. + #endif +#else + #define XT_CLIB_CONTEXT_AREA_SIZE 0 +#endif + +/*------------------------------------------------------------------------------ + Extra size -- interrupt frame plus coprocessor save area plus hook space. + NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks. +------------------------------------------------------------------------------*/ +#ifdef __XTENSA_CALL0_ABI__ + #define XT_XTRA_SIZE (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE) +#else + #define XT_XTRA_SIZE (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE) +#endif + +/*------------------------------------------------------------------------------ + Space allocated for user code -- function calls and local variables. + NOTE: This number can be adjusted to suit your needs. You must verify that the + amount of space you reserve is adequate for the worst-case conditions in your + application. + NOTE: The windowed ABI requires more stack, since space has to be reserved + for spilling register windows. +------------------------------------------------------------------------------*/ +#ifdef __XTENSA_CALL0_ABI__ + #define XT_USER_SIZE 0x200 +#else + #define XT_USER_SIZE 0x400 +#endif + +/* Minimum recommended stack size. */ +#define XT_STACK_MIN_SIZE ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char)) + +/* OS overhead with and without C library thread context. */ +#define XT_STACK_EXTRA (XT_XTRA_SIZE) +#define XT_STACK_EXTRA_CLIB (XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE) + + +#ifdef __cplusplus +} +#endif + +#endif /* XTENSA_CONFIG_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_context.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_context.S new file mode 100644 index 0000000..8553e8a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_context.S @@ -0,0 +1,631 @@ + /* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * XTENSA CONTEXT SAVE AND RESTORE ROUTINES + * + * Low-level Call0 functions for handling generic context save and restore of + * registers not specifically addressed by the interrupt vectors and handlers. + * Those registers (not handled by these functions) are PC, PS, A0, A1 (SP). + * Except for the calls to RTOS functions, this code is generic to Xtensa. + * + * Note that in Call0 ABI, interrupt handlers are expected to preserve the callee- + * save regs (A12-A15), which is always the case if the handlers are coded in C. + * However A12, A13 are made available as scratch registers for interrupt dispatch + * code, so are presumed saved anyway, and are always restored even in Call0 ABI. + * Only A14, A15 are truly handled as callee-save regs. + * + * Because Xtensa is a configurable architecture, this port supports all user + * generated configurations (except restrictions stated in the release notes). + * This is accomplished by conditional compilation using macros and functions + * defined in the Xtensa HAL (hardware adaptation layer) for your configuration. + * Only the processor state included in your configuration is saved and restored, + * including any processor state added by user configuration options or TIE. + */ + +/* Warn nicely if this file gets named with a lowercase .s instead of .S: */ +#define NOERROR # +NOERROR: .error "C preprocessor needed for this file: make sure its filename\ + ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option." + + +#include "xtensa_rtos.h" + +#ifdef XT_USE_OVLY +#include +#endif + + .text + .literal_position + +/******************************************************************************* + +_xt_context_save + + !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !! + +Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the +interrupt stack frame defined in xtensa_rtos.h. +Its counterpart is _xt_context_restore (which also restores A12, A13). + +Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame. +This function preserves A12 & A13 in order to provide the caller with 2 scratch +regs that need not be saved over the call to this function. The choice of which +2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw, +to avoid moving data more than necessary. Caller can assign regs accordingly. + +Entry Conditions: + A0 = Return address in caller. + A1 = Stack pointer of interrupted thread or handler ("interruptee"). + Original A12, A13 have already been saved in the interrupt stack frame. + Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the + point of interruption. + If windowed ABI, PS.EXCM = 1 (exceptions disabled). + +Exit conditions: + A0 = Return address in caller. + A1 = Stack pointer of interrupted thread or handler ("interruptee"). + A12, A13 as at entry (preserved). + If windowed ABI, PS.EXCM = 1 (exceptions disabled). + +*******************************************************************************/ + + .global _xt_context_save + .type _xt_context_save,@function + .align 4 +_xt_context_save: + + s32i a2, sp, XT_STK_A2 + s32i a3, sp, XT_STK_A3 + s32i a4, sp, XT_STK_A4 + s32i a5, sp, XT_STK_A5 + s32i a6, sp, XT_STK_A6 + s32i a7, sp, XT_STK_A7 + s32i a8, sp, XT_STK_A8 + s32i a9, sp, XT_STK_A9 + s32i a10, sp, XT_STK_A10 + s32i a11, sp, XT_STK_A11 + + /* + Call0 ABI callee-saved regs a12-15 do not need to be saved here. + a12-13 are the caller's responsibility so it can use them as scratch. + So only need to save a14-a15 here for Windowed ABI (not Call0). + */ + #ifndef __XTENSA_CALL0_ABI__ + s32i a14, sp, XT_STK_A14 + s32i a15, sp, XT_STK_A15 + #endif + + rsr a3, SAR + s32i a3, sp, XT_STK_SAR + + #if XCHAL_HAVE_LOOPS + rsr a3, LBEG + s32i a3, sp, XT_STK_LBEG + rsr a3, LEND + s32i a3, sp, XT_STK_LEND + rsr a3, LCOUNT + s32i a3, sp, XT_STK_LCOUNT + #endif + + #if XT_USE_SWPRI + /* Save virtual priority mask */ + movi a3, _xt_vpri_mask + l32i a3, a3, 0 + s32i a3, sp, XT_STK_VPRI + #endif + + #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__) + mov a9, a0 /* preserve ret addr */ + #endif + + #ifndef __XTENSA_CALL0_ABI__ + /* + To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15. + Need to save a9,12,13 temporarily (in frame temps) and recover originals. + Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow + and underflow exceptions disabled (assured by PS.EXCM == 1). + */ + s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */ + s32i a13, sp, XT_STK_TMP1 + s32i a9, sp, XT_STK_TMP2 + + /* + Save the overlay state if we are supporting overlays. Since we just saved + three registers, we can conveniently use them here. Note that as of now, + overlays only work for windowed calling ABI. + */ + #ifdef XT_USE_OVLY + l32i a9, sp, XT_STK_PC /* recover saved PC */ + _xt_overlay_get_state a9, a12, a13 + s32i a9, sp, XT_STK_OVLY /* save overlay state */ + #endif + + l32i a12, sp, XT_STK_A12 /* recover original a9,12,13 */ + l32i a13, sp, XT_STK_A13 + l32i a9, sp, XT_STK_A9 + addi sp, sp, XT_STK_FRMSZ /* restore the interruptee's SP */ + call0 xthal_window_spill_nw /* preserves only a4,5,8,9,12,13 */ + addi sp, sp, -XT_STK_FRMSZ + l32i a12, sp, XT_STK_TMP0 /* recover stuff from stack frame */ + l32i a13, sp, XT_STK_TMP1 + l32i a9, sp, XT_STK_TMP2 + #endif + + #if XCHAL_EXTRA_SA_SIZE > 0 + /* + NOTE: Normally the xthal_save_extra_nw macro only affects address + registers a2-a5. It is theoretically possible for Xtensa processor + designers to write TIE that causes more address registers to be + affected, but it is generally unlikely. If that ever happens, + more registers need to be saved/restored around this macro invocation. + Here we assume a9,12,13 are preserved. + Future Xtensa tools releases might limit the regs that can be affected. + */ + addi a2, sp, XT_STK_EXTRA /* where to save it */ + # if XCHAL_EXTRA_SA_ALIGN > 16 + movi a3, -XCHAL_EXTRA_SA_ALIGN + and a2, a2, a3 /* align dynamically >16 bytes */ + # endif + call0 xthal_save_extra_nw /* destroys a0,2,3,4,5 */ + #endif + + #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__) + mov a0, a9 /* retrieve ret addr */ + #endif + + ret + +/******************************************************************************* + +_xt_context_restore + + !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !! + +Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0 +ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt +stack frame defined in xtensa_rtos.h . +Its counterpart is _xt_context_save (whose caller saved A12, A13). + +Caller is responsible to restore PC, PS, A0, A1 (SP). + +Entry Conditions: + A0 = Return address in caller. + A1 = Stack pointer of interrupted thread or handler ("interruptee"). + +Exit conditions: + A0 = Return address in caller. + A1 = Stack pointer of interrupted thread or handler ("interruptee"). + Other processor state except PC, PS, A0, A1 (SP), is as at the point + of interruption. + +*******************************************************************************/ + + .global _xt_context_restore + .type _xt_context_restore,@function + .align 4 +_xt_context_restore: + + #if XCHAL_EXTRA_SA_SIZE > 0 + /* + NOTE: Normally the xthal_restore_extra_nw macro only affects address + registers a2-a5. It is theoretically possible for Xtensa processor + designers to write TIE that causes more address registers to be + affected, but it is generally unlikely. If that ever happens, + more registers need to be saved/restored around this macro invocation. + Here we only assume a13 is preserved. + Future Xtensa tools releases might limit the regs that can be affected. + */ + mov a13, a0 /* preserve ret addr */ + addi a2, sp, XT_STK_EXTRA /* where to find it */ + # if XCHAL_EXTRA_SA_ALIGN > 16 + movi a3, -XCHAL_EXTRA_SA_ALIGN + and a2, a2, a3 /* align dynamically >16 bytes */ + # endif + call0 xthal_restore_extra_nw /* destroys a0,2,3,4,5 */ + mov a0, a13 /* retrieve ret addr */ + #endif + + #if XCHAL_HAVE_LOOPS + l32i a2, sp, XT_STK_LBEG + l32i a3, sp, XT_STK_LEND + wsr a2, LBEG + l32i a2, sp, XT_STK_LCOUNT + wsr a3, LEND + wsr a2, LCOUNT + #endif + + #ifdef XT_USE_OVLY + /* + If we are using overlays, this is a good spot to check if we need + to restore an overlay for the incoming task. Here we have a bunch + of registers to spare. Note that this step is going to use a few + bytes of storage below SP (SP-20 to SP-32) if an overlay is going + to be restored. + */ + l32i a2, sp, XT_STK_PC /* retrieve PC */ + l32i a3, sp, XT_STK_PS /* retrieve PS */ + l32i a4, sp, XT_STK_OVLY /* retrieve overlay state */ + l32i a5, sp, XT_STK_A1 /* retrieve stack ptr */ + _xt_overlay_check_map a2, a3, a4, a5, a6 + s32i a2, sp, XT_STK_PC /* save updated PC */ + s32i a3, sp, XT_STK_PS /* save updated PS */ + #endif + + #ifdef XT_USE_SWPRI + /* Restore virtual interrupt priority and interrupt enable */ + movi a3, _xt_intdata + l32i a4, a3, 0 /* a4 = _xt_intenable */ + l32i a5, sp, XT_STK_VPRI /* a5 = saved _xt_vpri_mask */ + and a4, a4, a5 + wsr a4, INTENABLE /* update INTENABLE */ + s32i a5, a3, 4 /* restore _xt_vpri_mask */ + #endif + + l32i a3, sp, XT_STK_SAR + l32i a2, sp, XT_STK_A2 + wsr a3, SAR + l32i a3, sp, XT_STK_A3 + l32i a4, sp, XT_STK_A4 + l32i a5, sp, XT_STK_A5 + l32i a6, sp, XT_STK_A6 + l32i a7, sp, XT_STK_A7 + l32i a8, sp, XT_STK_A8 + l32i a9, sp, XT_STK_A9 + l32i a10, sp, XT_STK_A10 + l32i a11, sp, XT_STK_A11 + + /* + Call0 ABI callee-saved regs a12-15 do not need to be restored here. + However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), + so need to be restored anyway, despite being callee-saved in Call0. + */ + l32i a12, sp, XT_STK_A12 + l32i a13, sp, XT_STK_A13 + #ifndef __XTENSA_CALL0_ABI__ + l32i a14, sp, XT_STK_A14 + l32i a15, sp, XT_STK_A15 + #endif + + ret + + +/******************************************************************************* + +_xt_coproc_init + +Initializes global co-processor management data, setting all co-processors +to "unowned". Leaves CPENABLE as it found it (does NOT clear it). + +Called during initialization of the RTOS, before any threads run. + +This may be called from normal Xtensa single-threaded application code which +might use co-processors. The Xtensa run-time initialization enables all +co-processors. They must remain enabled here, else a co-processor exception +might occur outside of a thread, which the exception handler doesn't expect. + +Entry Conditions: + Xtensa single-threaded run-time environment is in effect. + No thread is yet running. + +Exit conditions: + None. + +Obeys ABI conventions per prototype: + void _xt_coproc_init(void) + +*******************************************************************************/ + +#if XCHAL_CP_NUM > 0 + + .global _xt_coproc_init + .type _xt_coproc_init,@function + .align 4 +_xt_coproc_init: + ENTRY0 + + /* Initialize thread co-processor ownerships to 0 (unowned). */ + movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */ + addi a3, a2, XCHAL_CP_MAX << 2 /* a3 = top+1 of owner array */ + movi a4, 0 /* a4 = 0 (unowned) */ +1: s32i a4, a2, 0 + addi a2, a2, 4 + bltu a2, a3, 1b + + RET0 + +#endif + + +/******************************************************************************* + +_xt_coproc_release + +Releases any and all co-processors owned by a given thread. The thread is +identified by it's co-processor state save area defined in xtensa_context.h . + +Must be called before a thread's co-proc save area is deleted to avoid +memory corruption when the exception handler tries to save the state. +May be called when a thread terminates or completes but does not delete +the co-proc save area, to avoid the exception handler having to save the +thread's co-proc state before another thread can use it (optimization). + +Entry Conditions: + A2 = Pointer to base of co-processor state save area. + +Exit conditions: + None. + +Obeys ABI conventions per prototype: + void _xt_coproc_release(void * coproc_sa_base) + +*******************************************************************************/ + +#if XCHAL_CP_NUM > 0 + + .global _xt_coproc_release + .type _xt_coproc_release,@function + .align 4 +_xt_coproc_release: + ENTRY0 /* a2 = base of save area */ + + movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */ + addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */ + movi a5, 0 /* a5 = 0 (unowned) */ + + rsil a6, XCHAL_EXCM_LEVEL /* lock interrupts */ + +1: l32i a7, a3, 0 /* a7 = owner at a3 */ + bne a2, a7, 2f /* if (coproc_sa_base == owner) */ + s32i a5, a3, 0 /* owner = unowned */ +2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */ + bltu a3, a4, 1b /* repeat until end of array */ + +3: wsr a6, PS /* restore interrupts */ + + RET0 + +#endif + + +/******************************************************************************* +_xt_coproc_savecs + +If there is a current thread and it has a coprocessor state save area, then +save all callee-saved state into this area. This function is called from the +solicited context switch handler. It calls a system-specific function to get +the coprocessor save area base address. + +Entry conditions: + - The thread being switched out is still the current thread. + - CPENABLE state reflects which coprocessors are active. + - Registers have been saved/spilled already. + +Exit conditions: + - All necessary CP callee-saved state has been saved. + - Registers a2-a7, a13-a15 have been trashed. + +Must be called from assembly code only, using CALL0. +*******************************************************************************/ +#if XCHAL_CP_NUM > 0 + + .extern _xt_coproc_sa_offset /* external reference */ + + .global _xt_coproc_savecs + .type _xt_coproc_savecs,@function + .align 4 +_xt_coproc_savecs: + + /* At entry, CPENABLE should be showing which CPs are enabled. */ + + rsr a2, CPENABLE /* a2 = which CPs are enabled */ + beqz a2, .Ldone /* quick exit if none */ + mov a14, a0 /* save return address */ + call0 XT_RTOS_CP_STATE /* get address of CP save area */ + mov a0, a14 /* restore return address */ + beqz a15, .Ldone /* if none then nothing to do */ + s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */ + movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + +#if XCHAL_CP0_SA_SIZE + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ + xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP1_SA_SIZE + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ + xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP2_SA_SIZE + bbci.l a2, 2, 2f + l32i a14, a13, 8 + add a3, a14, a15 + xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP3_SA_SIZE + bbci.l a2, 3, 2f + l32i a14, a13, 12 + add a3, a14, a15 + xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP4_SA_SIZE + bbci.l a2, 4, 2f + l32i a14, a13, 16 + add a3, a14, a15 + xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP5_SA_SIZE + bbci.l a2, 5, 2f + l32i a14, a13, 20 + add a3, a14, a15 + xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP6_SA_SIZE + bbci.l a2, 6, 2f + l32i a14, a13, 24 + add a3, a14, a15 + xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP7_SA_SIZE + bbci.l a2, 7, 2f + l32i a14, a13, 28 + add a3, a14, a15 + xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +.Ldone: + ret +#endif + + +/******************************************************************************* +_xt_coproc_restorecs + +Restore any callee-saved coprocessor state for the incoming thread. +This function is called from coprocessor exception handling, when giving +ownership to a thread that solicited a context switch earlier. It calls a +system-specific function to get the coprocessor save area base address. + +Entry conditions: + - The incoming thread is set as the current thread. + - CPENABLE is set up correctly for all required coprocessors. + - a2 = mask of coprocessors to be restored. + +Exit conditions: + - All necessary CP callee-saved state has been restored. + - CPENABLE - unchanged. + - Registers a2-a7, a13-a15 have been trashed. + +Must be called from assembly code only, using CALL0. +*******************************************************************************/ +#if XCHAL_CP_NUM > 0 + + .global _xt_coproc_restorecs + .type _xt_coproc_restorecs,@function + .align 4 +_xt_coproc_restorecs: + + mov a14, a0 /* save return address */ + call0 XT_RTOS_CP_STATE /* get address of CP save area */ + mov a0, a14 /* restore return address */ + beqz a15, .Ldone2 /* if none then nothing to do */ + l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */ + xor a3, a3, a2 /* clear the ones being restored */ + s32i a3, a15, XT_CP_CS_ST /* update saved CP mask */ + movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + +#if XCHAL_CP0_SA_SIZE + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ + xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP1_SA_SIZE + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ + xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP2_SA_SIZE + bbci.l a2, 2, 2f + l32i a14, a13, 8 + add a3, a14, a15 + xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP3_SA_SIZE + bbci.l a2, 3, 2f + l32i a14, a13, 12 + add a3, a14, a15 + xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP4_SA_SIZE + bbci.l a2, 4, 2f + l32i a14, a13, 16 + add a3, a14, a15 + xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP5_SA_SIZE + bbci.l a2, 5, 2f + l32i a14, a13, 20 + add a3, a14, a15 + xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP6_SA_SIZE + bbci.l a2, 6, 2f + l32i a14, a13, 24 + add a3, a14, a15 + xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP7_SA_SIZE + bbci.l a2, 7, 2f + l32i a14, a13, 28 + add a3, a14, a15 + xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +.Ldone2: + ret + +#endif + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_context.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_context.h new file mode 100644 index 0000000..d8048ed --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_context.h @@ -0,0 +1,356 @@ + /* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES + * + * This header contains definitions and macros for use primarily by Xtensa + * RTOS assembly coded source files. It includes and uses the Xtensa hardware + * abstraction layer (HAL) to deal with config specifics. It may also be + * included in C source files. + * + * !! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !! + * + * NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes. + */ + +#ifndef XTENSA_CONTEXT_H +#define XTENSA_CONTEXT_H + +#ifdef __ASSEMBLER__ +#include +#endif + +#include +#include +#include + + +/* Align a value up to nearest n-byte boundary, where n is a power of 2. */ +#define ALIGNUP(n, val) (((val) + (n)-1) & -(n)) + + +/* +------------------------------------------------------------------------------- + Macros that help define structures for both C and assembler. +------------------------------------------------------------------------------- +*/ +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) + +#define STRUCT_BEGIN .pushsection .text; .struct 0 +#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size +#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n) +#define STRUCT_END(sname) sname##Size:; .popsection + +#else + +#define STRUCT_BEGIN typedef struct { +#define STRUCT_FIELD(ctype,size,asname,name) ctype name; +#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n]; +#define STRUCT_END(sname) } sname; + +#endif //_ASMLANGUAGE || __ASSEMBLER__ + + +/* +------------------------------------------------------------------------------- + INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT + + A stack frame of this structure is allocated for any interrupt or exception. + It goes on the current stack. If the RTOS has a system stack for handling + interrupts, every thread stack must allow space for just one interrupt stack + frame, then nested interrupt stack frames go on the system stack. + + The frame includes basic registers (explicit) and "extra" registers introduced + by user TIE or the use of the MAC16 option in the user's Xtensa config. + The frame size is minimized by omitting regs not applicable to user's config. + + For Windowed ABI, this stack frame includes the interruptee's base save area, + another base save area to manage gcc nested functions, and a little temporary + space to help manage the spilling of the register windows. +------------------------------------------------------------------------------- +*/ + +STRUCT_BEGIN +STRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */ +STRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */ +STRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */ +STRUCT_FIELD (long, 4, XT_STK_A0, a0) +STRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */ +STRUCT_FIELD (long, 4, XT_STK_A2, a2) +STRUCT_FIELD (long, 4, XT_STK_A3, a3) +STRUCT_FIELD (long, 4, XT_STK_A4, a4) +STRUCT_FIELD (long, 4, XT_STK_A5, a5) +STRUCT_FIELD (long, 4, XT_STK_A6, a6) +STRUCT_FIELD (long, 4, XT_STK_A7, a7) +STRUCT_FIELD (long, 4, XT_STK_A8, a8) +STRUCT_FIELD (long, 4, XT_STK_A9, a9) +STRUCT_FIELD (long, 4, XT_STK_A10, a10) +STRUCT_FIELD (long, 4, XT_STK_A11, a11) +STRUCT_FIELD (long, 4, XT_STK_A12, a12) +STRUCT_FIELD (long, 4, XT_STK_A13, a13) +STRUCT_FIELD (long, 4, XT_STK_A14, a14) +STRUCT_FIELD (long, 4, XT_STK_A15, a15) +STRUCT_FIELD (long, 4, XT_STK_SAR, sar) +STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause) +STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr) +#if XCHAL_HAVE_LOOPS +STRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg) +STRUCT_FIELD (long, 4, XT_STK_LEND, lend) +STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount) +#endif +#ifndef __XTENSA_CALL0_ABI__ +/* Temporary space for saving stuff during window spill */ +STRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0) +STRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1) +STRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2) +#endif +#ifdef XT_USE_SWPRI +/* Storage for virtual priority mask */ +STRUCT_FIELD (long, 4, XT_STK_VPRI, vpri) +#endif +#ifdef XT_USE_OVLY +/* Storage for overlay state */ +STRUCT_FIELD (long, 4, XT_STK_OVLY, ovly) +#endif +STRUCT_END(XtExcFrame) + +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) +#define XT_STK_NEXT1 XtExcFrameSize +#else +#define XT_STK_NEXT1 sizeof(XtExcFrame) +#endif + +/* Allocate extra storage if needed */ +#if XCHAL_EXTRA_SA_SIZE != 0 + +#if XCHAL_EXTRA_SA_ALIGN <= 16 +#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) +#else +/* If need more alignment than stack, add space for dynamic alignment */ +#define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN) +#endif +#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE) + +#else + +#define XT_STK_NEXT2 XT_STK_NEXT1 + +#endif + +/* +------------------------------------------------------------------------------- + This is the frame size. Add space for 4 registers (interruptee's base save + area) and some space for gcc nested functions if any. +------------------------------------------------------------------------------- +*/ +#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20) + + +/* +------------------------------------------------------------------------------- + SOLICITED STACK FRAME FOR A THREAD + + A stack frame of this structure is allocated whenever a thread enters the + RTOS kernel intentionally (and synchronously) to submit to thread scheduling. + It goes on the current thread's stack. + + The solicited frame only includes registers that are required to be preserved + by the callee according to the compiler's ABI conventions, some space to save + the return address for returning to the caller, and the caller's PS register. + + For Windowed ABI, this stack frame includes the caller's base save area. + + Note on XT_SOL_EXIT field: + It is necessary to distinguish a solicited from an interrupt stack frame. + This field corresponds to XT_STK_EXIT in the interrupt stack frame and is + always at the same offset (0). It can be written with a code (usually 0) + to distinguish a solicted frame from an interrupt frame. An RTOS port may + opt to ignore this field if it has another way of distinguishing frames. +------------------------------------------------------------------------------- +*/ + +STRUCT_BEGIN +#ifdef __XTENSA_CALL0_ABI__ +STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) +STRUCT_FIELD (long, 4, XT_SOL_PC, pc) +STRUCT_FIELD (long, 4, XT_SOL_PS, ps) +STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) +STRUCT_FIELD (long, 4, XT_SOL_A12, a12) /* should be on 16-byte alignment */ +STRUCT_FIELD (long, 4, XT_SOL_A13, a13) +STRUCT_FIELD (long, 4, XT_SOL_A14, a14) +STRUCT_FIELD (long, 4, XT_SOL_A15, a15) +#else +STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) +STRUCT_FIELD (long, 4, XT_SOL_PC, pc) +STRUCT_FIELD (long, 4, XT_SOL_PS, ps) +STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) +STRUCT_FIELD (long, 4, XT_SOL_A0, a0) /* should be on 16-byte alignment */ +STRUCT_FIELD (long, 4, XT_SOL_A1, a1) +STRUCT_FIELD (long, 4, XT_SOL_A2, a2) +STRUCT_FIELD (long, 4, XT_SOL_A3, a3) +#endif +STRUCT_END(XtSolFrame) + +/* Size of solicited stack frame */ +#define XT_SOL_FRMSZ ALIGNUP(0x10, XtSolFrameSize) + + +/* +------------------------------------------------------------------------------- + CO-PROCESSOR STATE SAVE AREA FOR A THREAD + + The RTOS must provide an area per thread to save the state of co-processors + when that thread does not have control. Co-processors are context-switched + lazily (on demand) only when a new thread uses a co-processor instruction, + otherwise a thread retains ownership of the co-processor even when it loses + control of the processor. An Xtensa co-processor exception is triggered when + any co-processor instruction is executed by a thread that is not the owner, + and the context switch of that co-processor is then peformed by the handler. + Ownership represents which thread's state is currently in the co-processor. + + Co-processors may not be used by interrupt or exception handlers. If an + co-processor instruction is executed by an interrupt or exception handler, + the co-processor exception handler will trigger a kernel panic and freeze. + This restriction is introduced to reduce the overhead of saving and restoring + co-processor state (which can be quite large) and in particular remove that + overhead from interrupt handlers. + + The co-processor state save area may be in any convenient per-thread location + such as in the thread control block or above the thread stack area. It need + not be in the interrupt stack frame since interrupts don't use co-processors. + + Along with the save area for each co-processor, two bitmasks with flags per + co-processor (laid out as in the CPENABLE reg) help manage context-switching + co-processors as efficiently as possible: + + XT_CPENABLE + The contents of a non-running thread's CPENABLE register. + It represents the co-processors owned (and whose state is still needed) + by the thread. When a thread is preempted, its CPENABLE is saved here. + When a thread solicits a context-swtich, its CPENABLE is cleared - the + compiler has saved the (caller-saved) co-proc state if it needs to. + When a non-running thread loses ownership of a CP, its bit is cleared. + When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg. + Avoids co-processor exceptions when no change of ownership is needed. + + XT_CPSTORED + A bitmask with the same layout as CPENABLE, a bit per co-processor. + Indicates whether the state of each co-processor is saved in the state + save area. When a thread enters the kernel, only the state of co-procs + still enabled in CPENABLE is saved. When the co-processor exception + handler assigns ownership of a co-processor to a thread, it restores + the saved state only if this bit is set, and clears this bit. + + XT_CP_CS_ST + A bitmask with the same layout as CPENABLE, a bit per co-processor. + Indicates whether callee-saved state is saved in the state save area. + Callee-saved state is saved by itself on a solicited context switch, + and restored when needed by the coprocessor exception handler. + Unsolicited switches will cause the entire coprocessor to be saved + when necessary. + + XT_CP_ASA + Pointer to the aligned save area. Allows it to be aligned more than + the overall save area (which might only be stack-aligned or TCB-aligned). + Especially relevant for Xtensa cores configured with a very large data + path that requires alignment greater than 16 bytes (ABI stack alignment). +------------------------------------------------------------------------------- +*/ + +#if XCHAL_CP_NUM > 0 + +/* Offsets of each coprocessor save area within the 'aligned save area': */ +#define XT_CP0_SA 0 +#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE) +#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE) +#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE) +#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE) +#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE) +#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE) +#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE) +#define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE) + +/* Offsets within the overall save area: */ +#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */ +#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */ +#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */ +#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */ +/* Overall size allows for dynamic alignment: */ +#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN) +#else +#define XT_CP_SIZE 0 +#endif + + +/* +------------------------------------------------------------------------------- + MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN + + Convenient where the frame size requirements are the same for both ABIs. + ENTRY(sz), RET(sz) are for framed functions (have locals or make calls). + ENTRY0, RET0 are for frameless functions (no locals, no calls). + + where size = size of stack frame in bytes (must be >0 and aligned to 16). + For framed functions the frame is created and the return address saved at + base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). + For frameless functions, there is no frame and return address remains in a0. + Note: Because CPP macros expand to a single line, macros requiring multi-line + expansions are implemented as assembler macros. +------------------------------------------------------------------------------- +*/ + +#ifdef __ASSEMBLER__ +#ifdef __XTENSA_CALL0_ABI__ + /* Call0 */ + #define ENTRY(sz) entry1 sz + .macro entry1 size=0x10 + addi sp, sp, -\size + s32i a0, sp, 0 + .endm + #define ENTRY0 + #define RET(sz) ret1 sz + .macro ret1 size=0x10 + l32i a0, sp, 0 + addi sp, sp, \size + ret + .endm + #define RET0 ret +#else + /* Windowed */ + #define ENTRY(sz) entry sp, sz + #define ENTRY0 entry sp, 0x10 + #define RET(sz) retw + #define RET0 retw +#endif +#endif + + +#endif /* XTENSA_CONTEXT_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_init.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_init.c new file mode 100644 index 0000000..9284a02 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_init.c @@ -0,0 +1,71 @@ + /* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * XTENSA INITIALIZATION ROUTINES CODED IN C + * + * This file contains miscellaneous Xtensa RTOS-generic initialization functions + * that are implemented in C. + */ + + +#ifdef XT_BOARD +#include +#endif + +#include "xtensa_rtos.h" + +#ifdef XT_RTOS_TIMER_INT + +unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */ + +/* +Compute and initialize at run-time the tick divisor (the number of +processor clock cycles in an RTOS tick, used to set the tick timer). +Called when the processor clock frequency is not known at compile-time. +*/ +void _xt_tick_divisor_init(void) +{ +#ifdef XT_CLOCK_FREQ + + _xt_tick_divisor = (XT_CLOCK_FREQ / XT_TICK_PER_SEC); + +#else + + #ifdef XT_BOARD + _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC; + #else + #error "No way to obtain processor clock frequency" + #endif /* XT_BOARD */ + +#endif /* XT_CLOCK_FREQ */ +} + +#endif /* XT_RTOS_TIMER_INT */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c new file mode 100644 index 0000000..caf473f --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c @@ -0,0 +1,138 @@ + /* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Xtensa-specific interrupt and exception functions for RTOS ports. + * Also see xtensa_intr_asm.S. + */ + +#include + +#include + +#include "xtensa_api.h" + + +#if XCHAL_HAVE_EXCEPTIONS + +/* Handler table is in xtensa_intr_asm.S */ + +extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM]; + + +/* + Default handler for unhandled exceptions. +*/ +void xt_unhandled_exception(XtExcFrame *frame) +{ + exit(-1); +} + + +/* + This function registers a handler for the specified exception. + The function returns the address of the previous handler. + On error, it returns 0. +*/ +xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f) +{ + xt_exc_handler old; + + if( n < 0 || n >= XCHAL_EXCCAUSE_NUM ) + return 0; /* invalid exception number */ + + old = _xt_exception_table[n]; + + if (f) { + _xt_exception_table[n] = f; + } + else { + _xt_exception_table[n] = &xt_unhandled_exception; + } + + return ((old == &xt_unhandled_exception) ? 0 : old); +} + +#endif + +#if XCHAL_HAVE_INTERRUPTS + +/* Handler table is in xtensa_intr_asm.S */ + +typedef struct xt_handler_table_entry { + void * handler; + void * arg; +} xt_handler_table_entry; + +extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS]; + + +/* + Default handler for unhandled interrupts. +*/ +void xt_unhandled_interrupt(void * arg) +{ + exit(-1); +} + + +/* + This function registers a handler for the specified interrupt. The "arg" + parameter specifies the argument to be passed to the handler when it is + invoked. The function returns the address of the previous handler. + On error, it returns 0. +*/ +xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg) +{ + xt_handler_table_entry * entry; + xt_handler old; + + if( n < 0 || n >= XCHAL_NUM_INTERRUPTS ) + return 0; /* invalid interrupt number */ + if( Xthal_intlevel[n] > XCHAL_EXCM_LEVEL ) + return 0; /* priority level too high to safely handle in C */ + + entry = _xt_interrupt_table + n; + old = entry->handler; + + if (f) { + entry->handler = f; + entry->arg = arg; + } + else { + entry->handler = &xt_unhandled_interrupt; + entry->arg = (void*)n; + } + + return ((old == &xt_unhandled_interrupt) ? 0 : old); +} + + +#endif /* XCHAL_HAVE_INTERRUPTS */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S new file mode 100644 index 0000000..52f4721 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S @@ -0,0 +1,185 @@ + /* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Xtensa interrupt handling data and assembly routines. + * Also see xtensa_intr.c and xtensa_vectors.S. + */ + +#include +#include + +#include "xtensa_context.h" + +#if XCHAL_HAVE_INTERRUPTS + +/* +------------------------------------------------------------------------------- + INTENABLE virtualization information. +------------------------------------------------------------------------------- +*/ + + .data + .global _xt_intdata + .align 8 +_xt_intdata: + .global _xt_intenable + .type _xt_intenable,@object + .size _xt_intenable,4 + .global _xt_vpri_mask + .type _xt_vpri_mask,@object + .size _xt_vpri_mask,4 + +_xt_intenable: .word 0 /* Virtual INTENABLE */ +_xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */ + + +/* +------------------------------------------------------------------------------- + Table of C-callable interrupt handlers for each interrupt. Note that not all + slots can be filled, because interrupts at level > EXCM_LEVEL will not be + dispatched to a C handler by default. +------------------------------------------------------------------------------- +*/ + + .data + .global _xt_interrupt_table + .align 8 + +_xt_interrupt_table: + + .set i, 0 + .rept XCHAL_NUM_INTERRUPTS + .word xt_unhandled_interrupt /* handler address */ + .word i /* handler arg (default: intnum) */ + .set i, i+1 + .endr + +#endif /* XCHAL_HAVE_INTERRUPTS */ + + +#if XCHAL_HAVE_EXCEPTIONS + +/* +------------------------------------------------------------------------------- + Table of C-callable exception handlers for each exception. Note that not all + slots will be active, because some exceptions (e.g. coprocessor exceptions) + are always handled by the OS and cannot be hooked by user handlers. +------------------------------------------------------------------------------- +*/ + + .data + .global _xt_exception_table + .align 4 + +_xt_exception_table: + .rept XCHAL_EXCCAUSE_NUM + .word xt_unhandled_exception /* handler address */ + .endr + +#endif + + +/* +------------------------------------------------------------------------------- + unsigned int xt_ints_on ( unsigned int mask ) + + Enables a set of interrupts. Does not simply set INTENABLE directly, but + computes it as a function of the current virtual priority. + Can be called from interrupt handlers. +------------------------------------------------------------------------------- +*/ + + .text + .align 4 + .global xt_ints_on + .type xt_ints_on,@function + +xt_ints_on: + + ENTRY0 +#if XCHAL_HAVE_INTERRUPTS + movi a3, 0 + movi a4, _xt_intdata + xsr a3, INTENABLE /* Disables all interrupts */ + rsync + l32i a3, a4, 0 /* a3 = _xt_intenable */ + l32i a6, a4, 4 /* a6 = _xt_vpri_mask */ + or a5, a3, a2 /* a5 = _xt_intenable | mask */ + s32i a5, a4, 0 /* _xt_intenable |= mask */ + and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */ + wsr a5, INTENABLE /* Reenable interrupts */ + mov a2, a3 /* Previous mask */ +#else + movi a2, 0 /* Return zero */ +#endif + RET0 + + .size xt_ints_on, . - xt_ints_on + + +/* +------------------------------------------------------------------------------- + unsigned int xt_ints_off ( unsigned int mask ) + + Disables a set of interrupts. Does not simply set INTENABLE directly, + but computes it as a function of the current virtual priority. + Can be called from interrupt handlers. +------------------------------------------------------------------------------- +*/ + + .text + .align 4 + .global xt_ints_off + .type xt_ints_off,@function + +xt_ints_off: + + ENTRY0 +#if XCHAL_HAVE_INTERRUPTS + movi a3, 0 + movi a4, _xt_intdata + xsr a3, INTENABLE /* Disables all interrupts */ + rsync + l32i a3, a4, 0 /* a3 = _xt_intenable */ + l32i a6, a4, 4 /* a6 = _xt_vpri_mask */ + or a5, a3, a2 /* a5 = _xt_intenable | mask */ + xor a5, a5, a2 /* a5 = _xt_intenable & ~mask */ + s32i a5, a4, 0 /* _xt_intenable &= ~mask */ + and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */ + wsr a5, INTENABLE /* Reenable interrupts */ + mov a2, a3 /* Previous mask */ +#else + movi a2, 0 /* return zero */ +#endif + RET0 + + .size xt_ints_off, . - xt_ints_off + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c new file mode 100644 index 0000000..7145ad4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c @@ -0,0 +1,76 @@ + /* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * xtensa_overlay_os_hook.c -- Overlay manager OS hooks for FreeRTOS. + */ + +#include "FreeRTOS.h" +#include "semphr.h" + +#if configUSE_MUTEX + +/* Mutex object that controls access to the overlay. Currently only one + * overlay region is supported so one mutex suffices. + */ +static SemaphoreHandle_t xt_overlay_mutex; + + +/* This function should be overridden to provide OS specific init such + * as the creation of a mutex lock that can be used for overlay locking. + * Typically this mutex would be set up with priority inheritance. See + * overlay manager documentation for more details. + */ +void xt_overlay_init_os(void) +{ + /* Create the mutex for overlay access. Priority inheritance is + * required. + */ + xt_overlay_mutex = xSemaphoreCreateMutex(); +} + + +/* This function locks access to shared overlay resources, typically + * by acquiring a mutex. + */ +void xt_overlay_lock(void) +{ + xSemaphoreTake(xt_overlay_mutex, 0); +} + + +/* This function releases access to shared overlay resources, typically + * by unlocking a mutex. + */ +void xt_overlay_unlock(void) +{ + xSemaphoreGive(xt_overlay_mutex); +} + +#endif diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h new file mode 100644 index 0000000..c1b95c7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h @@ -0,0 +1,239 @@ + /* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES + * (FreeRTOS Port) + * + * This header is the primary glue between generic Xtensa RTOS support + * sources and a specific RTOS port for Xtensa. It contains definitions + * and macros for use primarily by Xtensa assembly coded source files. + * + * Macros in this header map callouts from generic Xtensa files to specific + * RTOS functions. It may also be included in C source files. + * + * Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa + * architecture, using the Xtensa hardware abstraction layer (HAL) to deal + * with configuration specifics. + * + * Should be included by all Xtensa generic and RTOS port-specific sources. + */ + +#ifndef XTENSA_RTOS_H +#define XTENSA_RTOS_H + +#ifdef __ASSEMBLER__ +#include +#else +#include +#endif + +#include +#include +#include + +/* +Include any RTOS specific definitions that are needed by this header. +*/ +#include + +/* +Convert FreeRTOSConfig definitions to XTENSA definitions. +However these can still be overridden from the command line. +*/ + +#ifndef XT_SIMULATOR + #if configXT_SIMULATOR + #define XT_SIMULATOR 1 /* Simulator mode */ + #endif +#endif + +#ifndef XT_BOARD + #if configXT_BOARD + #define XT_BOARD 1 /* Board mode */ + #endif +#endif + +#ifndef XT_TIMER_INDEX + #if defined configXT_TIMER_INDEX + #define XT_TIMER_INDEX configXT_TIMER_INDEX /* Index of hardware timer to be used */ + #endif +#endif + +#ifndef XT_INTEXC_HOOKS + #if configXT_INTEXC_HOOKS + #define XT_INTEXC_HOOKS 1 /* Enables exception hooks */ + #endif +#endif + +#if (!XT_SIMULATOR) && (!XT_BOARD) + #error Either XT_SIMULATOR or XT_BOARD must be defined. +#endif + + +/* +Name of RTOS (for messages). +*/ +#define XT_RTOS_NAME FreeRTOS + +/* +Check some Xtensa configuration requirements and report error if not met. +Error messages can be customize to the RTOS port. +*/ + +#if !XCHAL_HAVE_XEA2 +#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)." +#endif + + +/******************************************************************************* + +RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS. + +Define callout macros used in generic Xtensa code to interact with the RTOS. +The macros are simply the function names for use in calls from assembler code. +Some of these functions may call back to generic functions in xtensa_context.h . + +*******************************************************************************/ + +/* +Inform RTOS of entry into an interrupt handler that will affect it. +Allows RTOS to manage switch to any system stack and count nesting level. +Called after minimal context has been saved, with interrupts disabled. +RTOS port can call0 _xt_context_save to save the rest of the context. +May only be called from assembly code by the 'call0' instruction. +*/ +// void XT_RTOS_INT_ENTER(void) +#define XT_RTOS_INT_ENTER _frxt_int_enter + +/* +Inform RTOS of completion of an interrupt handler, and give control to +RTOS to perform thread/task scheduling, switch back from any system stack +and restore the context, and return to the exit dispatcher saved in the +stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore +to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save, +leaving only a minimal part of the context to be restored by the exit +dispatcher. This function does not return to the place it was called from. +May only be called from assembly code by the 'call0' instruction. +*/ +// void XT_RTOS_INT_EXIT(void) +#define XT_RTOS_INT_EXIT _frxt_int_exit + +/* +Inform RTOS of the occurrence of a tick timer interrupt. +If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined. +May be coded in or called from C or assembly, per ABI conventions. +RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro). +*/ +// void XT_RTOS_TIMER_INT(void) +#define XT_RTOS_TIMER_INT _frxt_timer_int +#define XT_TICK_PER_SEC configTICK_RATE_HZ + +/* +Return in a15 the base address of the co-processor state save area for the +thread that triggered a co-processor exception, or 0 if no thread was running. +The state save area is structured as defined in xtensa_context.h and has size +XT_CP_SIZE. Co-processor instructions should only be used in thread code, never +in interrupt handlers or the RTOS kernel. May only be called from assembly code +and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. +The implementation may use only a2-4, a15 (all other regs must be preserved). +*/ +// void* XT_RTOS_CP_STATE(void) +#define XT_RTOS_CP_STATE _frxt_task_coproc_state + + +/******************************************************************************* + +HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL. + +This Xtensa RTOS port provides hooks for dynamically installing exception +and interrupt handlers to facilitate automated testing where each test +case can install its own handler for user exceptions and each interrupt +priority (level). This consists of an array of function pointers indexed +by interrupt priority, with index 0 being the user exception handler hook. +Each entry in the array is initially 0, and may be replaced by a function +pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0. + +The handler for low and medium priority obeys ABI conventions so may be coded +in C. For the exception handler, the cause is the contents of the EXCCAUSE +reg, and the result is -1 if handled, else the cause (still needs handling). +For interrupt handlers, the cause is a mask of pending enabled interrupts at +that level, and the result is the same mask with the bits for the handled +interrupts cleared (those not cleared still need handling). This allows a test +case to either pre-handle or override the default handling for the exception +or interrupt level (see xtensa_vectors.S). + +High priority handlers (including NMI) must be coded in assembly, are always +called by 'call0' regardless of ABI, must preserve all registers except a0, +and must not use or modify the interrupted stack. The hook argument 'cause' +is not passed and the result is ignored, so as not to burden the caller with +saving and restoring a2 (it assumes only one interrupt per level - see the +discussion in high priority interrupts in xtensa_vectors.S). The handler +therefore should be coded to prototype 'void h(void)' even though it plugs +into an array of handlers of prototype 'unsigned h(unsigned)'. + +To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'. + +*******************************************************************************/ + +#define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI) + +#ifndef __ASSEMBLER__ +typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause); +extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM]; +#endif + + +/******************************************************************************* + +CONVENIENCE INCLUSIONS. + +Ensures RTOS specific files need only include this one Xtensa-generic header. +These headers are included last so they can use the RTOS definitions above. + +*******************************************************************************/ + +#include "xtensa_context.h" + +#ifdef XT_RTOS_TIMER_INT +#include "xtensa_timer.h" +#endif + + +/******************************************************************************* + +Xtensa Port Version. + +*******************************************************************************/ + +#define XTENSA_PORT_VERSION 1.7 +#define XTENSA_PORT_VERSION_STRING "1.7" + +#endif /* XTENSA_RTOS_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h new file mode 100644 index 0000000..07d974a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h @@ -0,0 +1,165 @@ + /* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY + * + * This header contains definitions and macros for use primarily by Xtensa + * RTOS assembly coded source files. It includes and uses the Xtensa hardware + * abstraction layer (HAL) to deal with config specifics. It may also be + * included in C source files. + * + * Edit this file to modify timer selection and to specify clock frequency and + * tick duration to match timer interrupt to the real-time tick duration. + * + * If the RTOS has no timer interrupt, then there is no tick timer and the + * clock frequency is irrelevant, so all of these macros are left undefined + * and the Xtensa core configuration need not have a timer. + */ + +#ifndef XTENSA_TIMER_H +#define XTENSA_TIMER_H + +#ifdef __ASSEMBLER__ +#include +#endif + +#include +#include + +#include "xtensa_rtos.h" /* in case this wasn't included directly */ + +#include + +/* +Select timer to use for periodic tick, and determine its interrupt number +and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, +in which case its validity is checked (it must exist in this core and must +not be on a high priority interrupt - an error will be reported in invalid). +Otherwise select the first low or medium priority interrupt timer available. +*/ +#if XCHAL_NUM_TIMERS == 0 + + #error "This Xtensa configuration is unsupported, it has no timers." + +#else + +#ifndef XT_TIMER_INDEX + #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 3 + #endif + #endif + #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 2 + #endif + #endif + #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 1 + #endif + #endif + #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 0 + #endif + #endif +#endif +#ifndef XT_TIMER_INDEX + #error "There is no suitable timer in this Xtensa configuration." +#endif + +#define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX) +#define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX) +#define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM) +#define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM) + +#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED + #error "The timer selected by XT_TIMER_INDEX does not exist in this core." +#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL + #error "The timer interrupt cannot be high priority (use medium or low)." +#endif + +#endif /* XCHAL_NUM_TIMERS */ + +/* +Set processor clock frequency, used to determine clock divisor for timer tick. +User should BE SURE TO ADJUST THIS for the Xtensa platform being used. +If using a supported board via the board-independent API defined in xtbsp.h, +this may be left undefined and frequency and tick divisor will be computed +and cached during run-time initialization. + +NOTE ON SIMULATOR: +Under the Xtensa instruction set simulator, the frequency can only be estimated +because it depends on the speed of the host and the version of the simulator. +Also because it runs much slower than hardware, it is not possible to achieve +real-time performance for most applications under the simulator. A frequency +too low does not allow enough time between timer interrupts, starving threads. +To obtain a more convenient but non-real-time tick duration on the simulator, +compile with xt-xcc option "-DXT_SIMULATOR". +Adjust this frequency to taste (it's not real-time anyway!). +*/ +#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ) +#define XT_CLOCK_FREQ configCPU_CLOCK_HZ +#endif + +#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD) + #error "XT_CLOCK_FREQ must be defined for the target platform." +#endif + +/* +Default number of timer "ticks" per second (default 100 for 10ms tick). +RTOS may define this in its own way (if applicable) in xtensa_rtos.h. +User may redefine this to an optimal value for the application, either by +editing this here or in xtensa_rtos.h, or compiling with xt-xcc option +"-DXT_TICK_PER_SEC=" where is a suitable number. +*/ +#ifndef XT_TICK_PER_SEC +#define XT_TICK_PER_SEC configTICK_RATE_HZ /* 10 ms tick = 100 ticks per second */ +#endif + +/* +Derivation of clock divisor for timer tick and interrupt (one per tick). +*/ +#ifdef XT_CLOCK_FREQ +#define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC) +#endif + +#ifndef __ASSEMBLER__ +extern unsigned _xt_tick_divisor; +extern void _xt_tick_divisor_init(void); +#endif + +#endif /* XTENSA_TIMER_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S new file mode 100644 index 0000000..036ad40 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S @@ -0,0 +1,1925 @@ + /* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2015-2019 Cadence Design Systems, Inc. + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS + + Xtensa low level exception and interrupt vectors and handlers for an RTOS. + + Interrupt handlers and user exception handlers support interaction with + the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and + after user's specific interrupt handlers. These macros are defined in + xtensa_.h to call suitable functions in a specific RTOS. + + Users can install application-specific interrupt handlers for low and + medium level interrupts, by calling xt_set_interrupt_handler(). These + handlers can be written in C, and must obey C calling convention. The + handler table is indexed by the interrupt number. Each handler may be + provided with an argument. + + Note that the system timer interrupt is handled specially, and is + dispatched to the RTOS-specific handler. This timer cannot be hooked + by application code. + + Optional hooks are also provided to install a handler per level at + run-time, made available by compiling this source file with + '-DXT_INTEXC_HOOKS' (useful for automated testing). + +!! This file is a template that usually needs to be modified to handle !! +!! application specific interrupts. Search USER_EDIT for helpful comments !! +!! on where to insert handlers and how to write them. !! + + Users can also install application-specific exception handlers in the + same way, by calling xt_set_exception_handler(). One handler slot is + provided for each exception type. Note that some exceptions are handled + by the porting layer itself, and cannot be taken over by application + code in this manner. These are the alloca, syscall, and coprocessor + exceptions. + + The exception handlers can be written in C, and must follow C calling + convention. Each handler is passed a pointer to an exception frame as + its single argument. The exception frame is created on the stack, and + holds the saved context of the thread that took the exception. If the + handler returns, the context will be restored and the instruction that + caused the exception will be retried. If the handler makes any changes + to the saved state in the exception frame, the changes will be applied + when restoring the context. + + Because Xtensa is a configurable architecture, this port supports all user + generated configurations (except restrictions stated in the release notes). + This is accomplished by conditional compilation using macros and functions + defined in the Xtensa HAL (hardware adaptation layer) for your configuration. + Only the relevant parts of this file will be included in your RTOS build. + For example, this file provides interrupt vector templates for all types and + all priority levels, but only the ones in your configuration are built. + + NOTES on the use of 'call0' for long jumps instead of 'j': + 1. This file should be assembled with the -mlongcalls option to xt-xcc. + 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to + a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the + distance from the call to the destination. The linker then relaxes + it back to 'call0 dest' if it determines that dest is within range. + This allows more flexibility in locating code without the performance + overhead of the 'l32r' literal data load in cases where the destination + is in range of 'call0'. There is an additional benefit in that 'call0' + has a longer range than 'j' due to the target being word-aligned, so + the 'l32r' sequence is less likely needed. + 3. The use of 'call0' with -mlongcalls requires that register a0 not be + live at the time of the call, which is always the case for a function + call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'. + 4. This use of 'call0' is independent of the C function call ABI. + + */ + +#include "xtensa_rtos.h" + + +/* Enable stack backtrace across exception/interrupt - see below */ +#define XT_DEBUG_BACKTRACE 1 + + +/* +-------------------------------------------------------------------------------- + Defines used to access _xtos_interrupt_table. +-------------------------------------------------------------------------------- +*/ +#define XIE_HANDLER 0 +#define XIE_ARG 4 +#define XIE_SIZE 8 + +/* +-------------------------------------------------------------------------------- + Macro extract_msb - return the input with only the highest bit set. + + Input : "ain" - Input value, clobbered. + Output : "aout" - Output value, has only one bit set, MSB of "ain". + The two arguments must be different AR registers. +-------------------------------------------------------------------------------- +*/ + + .macro extract_msb aout ain +1: + addi \aout, \ain, -1 /* aout = ain - 1 */ + and \ain, \ain, \aout /* ain = ain & aout */ + bnez \ain, 1b /* repeat until ain == 0 */ + addi \aout, \aout, 1 /* return aout + 1 */ + .endm + +/* +-------------------------------------------------------------------------------- + Macro dispatch_c_isr - dispatch interrupts to user ISRs. + This will dispatch to user handlers (if any) that are registered in the + XTOS dispatch table (_xtos_interrupt_table). These handlers would have + been registered by calling _xtos_set_interrupt_handler(). There is one + exception - the timer interrupt used by the OS will not be dispatched + to a user handler - this must be handled by the caller of this macro. + + Level triggered and software interrupts are automatically deasserted by + this code. + + ASSUMPTIONS: + -- PS.INTLEVEL is set to "level" at entry + -- PS.EXCM = 0, C calling enabled + + NOTE: For CALL0 ABI, a12-a15 have not yet been saved. + + NOTE: This macro will use registers a0 and a2-a6. The arguments are: + level -- interrupt level + mask -- interrupt bitmask for this level +-------------------------------------------------------------------------------- +*/ + + .macro dispatch_c_isr level mask + + /* Get mask of pending, enabled interrupts at this level into a2. */ + +.L_xt_user_int_&level&: + rsr a2, INTENABLE + rsr a3, INTERRUPT + movi a4, \mask + and a2, a2, a3 + and a2, a2, a4 + beqz a2, 9f /* nothing to do */ + + /* This bit of code provides a nice debug backtrace in the debugger. + It does take a few more instructions, so undef XT_DEBUG_BACKTRACE + if you want to save the cycles. + */ + #if XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + rsr a0, EPC_1 + \level - 1 /* return address */ + movi a4, 0xC0000000 /* constant with top 2 bits set (call size) */ + or a0, a0, a4 /* set top 2 bits */ + addx2 a0, a4, a0 /* clear top bit -- simulating call4 size */ + #endif + #endif + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a4, _xt_intexc_hooks + l32i a4, a4, \level << 2 + beqz a4, 2f + #ifdef __XTENSA_CALL0_ABI__ + callx0 a4 + beqz a2, 9f + #else + mov a6, a2 + callx4 a4 + beqz a6, 9f + mov a2, a6 + #endif +2: + #endif + + /* Now look up in the dispatch table and call user ISR if any. */ + /* If multiple bits are set then MSB has highest priority. */ + + extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ + + #ifdef XT_USE_SWPRI + /* Enable all interrupts at this level that are numerically higher + than the one we just selected, since they are treated as higher + priority. + */ + movi a3, \mask /* a3 = all interrupts at this level */ + add a2, a4, a4 /* a2 = a4 << 1 */ + addi a2, a2, -1 /* a2 = mask of 1's <= a4 bit */ + and a2, a2, a3 /* a2 = mask of all bits <= a4 at this level */ + movi a3, _xt_intdata + l32i a6, a3, 4 /* a6 = _xt_vpri_mask */ + neg a2, a2 + addi a2, a2, -1 /* a2 = mask to apply */ + and a5, a6, a2 /* mask off all bits <= a4 bit */ + s32i a5, a3, 4 /* update _xt_vpri_mask */ + rsr a3, INTENABLE + and a3, a3, a2 /* mask off all bits <= a4 bit */ + wsr a3, INTENABLE + rsil a3, \level - 1 /* lower interrupt level by 1 */ + #endif + + movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */ + wsr a4, INTCLEAR /* clear sw or edge-triggered interrupt */ + beq a3, a4, 7f /* if timer interrupt then skip table */ + + find_ms_setbit a3, a4, a3, 0 /* a3 = interrupt number */ + + movi a4, _xt_interrupt_table + addx8 a3, a3, a4 /* a3 = address of interrupt table entry */ + l32i a4, a3, XIE_HANDLER /* a4 = handler address */ + #ifdef __XTENSA_CALL0_ABI__ + mov a12, a6 /* save in callee-saved reg */ + l32i a2, a3, XIE_ARG /* a2 = handler arg */ + callx0 a4 /* call handler */ + mov a2, a12 + #else + mov a2, a6 /* save in windowed reg */ + l32i a6, a3, XIE_ARG /* a6 = handler arg */ + callx4 a4 /* call handler */ + #endif + + #ifdef XT_USE_SWPRI + j 8f + #else + j .L_xt_user_int_&level& /* check for more interrupts */ + #endif + +7: + + .ifeq XT_TIMER_INTPRI - \level +.L_xt_user_int_timer_&level&: + /* + Interrupt handler for the RTOS tick timer if at this level. + We'll be reading the interrupt state again after this call + so no need to preserve any registers except a6 (vpri_mask). + */ + + #ifdef __XTENSA_CALL0_ABI__ + mov a12, a6 + call0 XT_RTOS_TIMER_INT + mov a2, a12 + #else + mov a2, a6 + call4 XT_RTOS_TIMER_INT + #endif + .endif + + #ifdef XT_USE_SWPRI + j 8f + #else + j .L_xt_user_int_&level& /* check for more interrupts */ + #endif + + #ifdef XT_USE_SWPRI +8: + /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from + virtual _xt_intenable which _could_ have changed during interrupt + processing. */ + + movi a3, _xt_intdata + l32i a4, a3, 0 /* a4 = _xt_intenable */ + s32i a2, a3, 4 /* update _xt_vpri_mask */ + and a4, a4, a2 /* a4 = masked intenable */ + wsr a4, INTENABLE /* update INTENABLE */ + #endif + +9: + /* done */ + + .endm + + +/* +-------------------------------------------------------------------------------- + Panic handler. + Should be reached by call0 (preferable) or jump only. If call0, a0 says where + from. If on simulator, display panic message and abort, else loop indefinitely. +-------------------------------------------------------------------------------- +*/ + + .text + .global _xt_panic + .type _xt_panic,@function + .align 4 + .literal_position + +_xt_panic: + #ifdef XT_SIMULATOR + addi a4, a0, -3 /* point to call0 */ + movi a3, _xt_panic_message + movi a2, SYS_log_msg + simcall + movi a2, SYS_gdb_abort + simcall + #else + rsil a2, XCHAL_EXCM_LEVEL /* disable all low & med ints */ +1: j 1b /* loop infinitely */ + #endif + + .section .rodata, "a" + .align 4 + +_xt_panic_message: + .string "\n*** _xt_panic() was called from 0x%08x or jumped to. ***\n" + + +/* +-------------------------------------------------------------------------------- + Hooks to dynamically install handlers for exceptions and interrupts. + Allows automated regression frameworks to install handlers per test. + Consists of an array of function pointers indexed by interrupt level, + with index 0 containing the entry for user exceptions. + Initialized with all 0s, meaning no handler is installed at each level. + See comment in xtensa_rtos.h for more details. +-------------------------------------------------------------------------------- +*/ + + #ifdef XT_INTEXC_HOOKS + .data + .global _xt_intexc_hooks + .type _xt_intexc_hooks,@object + .align 4 + +_xt_intexc_hooks: + .fill XT_INTEXC_HOOK_NUM, 4, 0 + #endif + + +/* +-------------------------------------------------------------------------------- + EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS + (except window exception vectors). + + Each vector goes at a predetermined location according to the Xtensa + hardware configuration, which is ensured by its placement in a special + section known to the Xtensa linker support package (LSP). It performs + the minimum necessary before jumping to the handler in the .text section. + + The corresponding handler goes in the normal .text section. It sets up + the appropriate stack frame, saves a few vector-specific registers and + calls XT_RTOS_INT_ENTER to save the rest of the interrupted context + and enter the RTOS, then sets up a C environment. It then calls the + user's interrupt handler code (which may be coded in C) and finally + calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling. + + While XT_RTOS_INT_EXIT does not return directly to the interruptee, + eventually the RTOS scheduler will want to dispatch the interrupted + task or handler. The scheduler will return to the exit point that was + saved in the interrupt stack frame at XT_STK_EXIT. +-------------------------------------------------------------------------------- +*/ + + +/* +-------------------------------------------------------------------------------- +Debug Exception. +-------------------------------------------------------------------------------- +*/ + +#if XCHAL_HAVE_DEBUG + + .begin literal_prefix .DebugExceptionVector + .section .DebugExceptionVector.text, "ax" + .global _DebugExceptionVector + .align 4 + .literal_position + +_DebugExceptionVector: + + #ifdef XT_SIMULATOR + /* + In the simulator, let the debugger (if any) handle the debug exception, + or simply stop the simulation: + */ + wsr a2, EXCSAVE+XCHAL_DEBUGLEVEL /* save a2 where sim expects it */ + movi a2, SYS_gdb_enter_sktloop + simcall /* have ISS handle debug exc. */ + #elif 0 /* change condition to 1 to use the HAL minimal debug handler */ + wsr a3, EXCSAVE+XCHAL_DEBUGLEVEL + movi a3, xthal_debugexc_defhndlr_nw /* use default debug handler */ + jx a3 + #else + wsr a0, EXCSAVE+XCHAL_DEBUGLEVEL /* save original a0 somewhere */ + call0 _xt_panic /* does not return */ + rfi XCHAL_DEBUGLEVEL /* make a0 point here not later */ + #endif + + .end literal_prefix + +#endif + +/* +-------------------------------------------------------------------------------- +Double Exception. +Double exceptions are not a normal occurrence. They indicate a bug of some kind. +-------------------------------------------------------------------------------- +*/ + +#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR + + .begin literal_prefix .DoubleExceptionVector + .section .DoubleExceptionVector.text, "ax" + .global _DoubleExceptionVector + .align 4 + .literal_position + +_DoubleExceptionVector: + + #if XCHAL_HAVE_DEBUG + break 1, 4 /* unhandled double exception */ + #endif + call0 _xt_panic /* does not return */ + rfde /* make a0 point here not later */ + + .end literal_prefix + +#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */ + +/* +-------------------------------------------------------------------------------- +Kernel Exception (including Level 1 Interrupt from kernel mode). +-------------------------------------------------------------------------------- +*/ + + .begin literal_prefix .KernelExceptionVector + .section .KernelExceptionVector.text, "ax" + .global _KernelExceptionVector + .align 4 + .literal_position + +_KernelExceptionVector: + + wsr a0, EXCSAVE_1 /* preserve a0 */ + call0 _xt_kernel_exc /* kernel exception handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .text + .align 4 + +_xt_kernel_exc: + #if XCHAL_HAVE_DEBUG + break 1, 0 /* unhandled kernel exception */ + #endif + call0 _xt_panic /* does not return */ + rfe /* make a0 point here not there */ + + +/* +-------------------------------------------------------------------------------- +User Exception (including Level 1 Interrupt from user mode). +-------------------------------------------------------------------------------- +*/ + + .begin literal_prefix .UserExceptionVector + .section .UserExceptionVector.text, "ax" + .global _UserExceptionVector + .type _UserExceptionVector,@function + .align 4 + .literal_position + +_UserExceptionVector: + + wsr a0, EXCSAVE_1 /* preserve a0 */ + call0 _xt_user_exc /* user exception handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +/* +-------------------------------------------------------------------------------- + Insert some waypoints for jumping beyond the signed 8-bit range of + conditional branch instructions, so the conditional branchces to specific + exception handlers are not taken in the mainline. Saves some cycles in the + mainline. +-------------------------------------------------------------------------------- +*/ + + .text + + #if XCHAL_HAVE_WINDOWED + .align 4 +_xt_to_alloca_exc: + call0 _xt_alloca_exc /* in window vectors section */ + /* never returns here - call0 is used as a jump (see note at top) */ + #endif + + .align 4 +_xt_to_syscall_exc: + call0 _xt_syscall_exc + /* never returns here - call0 is used as a jump (see note at top) */ + + #if XCHAL_CP_NUM > 0 + .align 4 +_xt_to_coproc_exc: + call0 _xt_coproc_exc + /* never returns here - call0 is used as a jump (see note at top) */ + #endif + + +/* +-------------------------------------------------------------------------------- + User exception handler. +-------------------------------------------------------------------------------- +*/ + + .type _xt_user_exc,@function + .align 4 + +_xt_user_exc: + + /* If level 1 interrupt then jump to the dispatcher */ + rsr a0, EXCCAUSE + beqi a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1 + + /* Handle any coprocessor exceptions. Rely on the fact that exception + numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors. + */ + #if XCHAL_CP_NUM > 0 + bgeui a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc + #endif + + /* Handle alloca and syscall exceptions */ + #if XCHAL_HAVE_WINDOWED + beqi a0, EXCCAUSE_ALLOCA, _xt_to_alloca_exc + #endif + beqi a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc + + /* Handle all other exceptions. All can have user-defined handlers. */ + /* NOTE: we'll stay on the user stack for exception handling. */ + + /* Allocate exception frame and save minimal context. */ + mov a0, sp + addi sp, sp, -XT_STK_FRMSZ + s32i a0, sp, XT_STK_A1 + #if XCHAL_HAVE_WINDOWED + s32e a0, sp, -12 /* for debug backtrace */ + #endif + rsr a0, PS /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_1 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_1 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + #if XCHAL_HAVE_WINDOWED + s32e a0, sp, -16 /* for debug backtrace */ + #endif + s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */ + s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */ + call0 _xt_context_save + + /* Save exc cause and vaddr into exception frame */ + rsr a0, EXCCAUSE + s32i a0, sp, XT_STK_EXCCAUSE + rsr a0, EXCVADDR + s32i a0, sp, XT_STK_EXCVADDR + + /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM + #else + movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE + #endif + wsr a0, PS + + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + rsr a0, EPC_1 /* return address for debug backtrace */ + movi a5, 0xC0000000 /* constant with top 2 bits set (call size) */ + rsync /* wait for WSR.PS to complete */ + or a0, a0, a5 /* set top 2 bits */ + addx2 a0, a5, a0 /* clear top bit -- thus simulating call4 size */ + #else + rsync /* wait for WSR.PS to complete */ + #endif + #endif + + rsr a2, EXCCAUSE /* recover exc cause */ + + #ifdef XT_INTEXC_HOOKS + /* + Call exception hook to pre-handle exceptions (if installed). + Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling). + */ + movi a4, _xt_intexc_hooks + l32i a4, a4, 0 /* user exception hook index 0 */ + beqz a4, 1f +.Ln_xt_user_exc_call_hook: + #ifdef __XTENSA_CALL0_ABI__ + callx0 a4 + beqi a2, -1, .L_xt_user_done + #else + mov a6, a2 + callx4 a4 + beqi a6, -1, .L_xt_user_done + mov a2, a6 + #endif +1: + #endif + + rsr a2, EXCCAUSE /* recover exc cause */ + movi a3, _xt_exception_table + addx4 a4, a2, a3 /* a4 = address of exception table entry */ + l32i a4, a4, 0 /* a4 = handler address */ + #ifdef __XTENSA_CALL0_ABI__ + mov a2, sp /* a2 = pointer to exc frame */ + callx0 a4 /* call handler */ + #else + mov a6, sp /* a6 = pointer to exc frame */ + callx4 a4 /* call handler */ + #endif + +.L_xt_user_done: + + /* Restore context and return */ + call0 _xt_context_restore + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, PS + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_1 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove exception frame */ + rsync /* ensure PS and EPC written */ + rfe /* PS.EXCM is cleared */ + + +/* +-------------------------------------------------------------------------------- + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. +-------------------------------------------------------------------------------- +*/ + + .global _xt_user_exit + .type _xt_user_exit,@function + .align 4 +_xt_user_exit: + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, PS + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_1 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure PS and EPC written */ + rfe /* PS.EXCM is cleared */ + + +/* +-------------------------------------------------------------------------------- +Syscall Exception Handler (jumped to from User Exception Handler). +Syscall 0 is required to spill the register windows (no-op in Call 0 ABI). +Only syscall 0 is handled here. Other syscalls return -1 to caller in a2. +-------------------------------------------------------------------------------- +*/ + + .text + .type _xt_syscall_exc,@function + .align 4 +_xt_syscall_exc: + + #ifdef __XTENSA_CALL0_ABI__ + /* + Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI. + Use a minimal stack frame (16B) to save A2 & A3 for scratch. + PS.EXCM could be cleared here, but unlikely to improve worst-case latency. + rsr a0, PS + addi a0, a0, -PS_EXCM_MASK + wsr a0, PS + */ + addi sp, sp, -16 + s32i a2, sp, 8 + s32i a3, sp, 12 + #else /* Windowed ABI */ + /* + Save necessary context and spill the register windows. + PS.EXCM is still set and must remain set until after the spill. + Reuse context save function though it saves more than necessary. + For this reason, a full interrupt stack frame is allocated. + */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */ + s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */ + call0 _xt_context_save + #endif + + /* + Grab the interruptee's PC and skip over the 'syscall' instruction. + If it's at the end of a zero-overhead loop and it's not on the last + iteration, decrement loop counter and skip to beginning of loop. + */ + rsr a2, EPC_1 /* a2 = PC of 'syscall' */ + addi a3, a2, 3 /* ++PC */ + #if XCHAL_HAVE_LOOPS + rsr a0, LEND /* if (PC == LEND */ + bne a3, a0, 1f + rsr a0, LCOUNT /* && LCOUNT != 0) */ + beqz a0, 1f /* { */ + addi a0, a0, -1 /* --LCOUNT */ + rsr a3, LBEG /* PC = LBEG */ + wsr a0, LCOUNT /* } */ + #endif +1: wsr a3, EPC_1 /* update PC */ + + /* Restore interruptee's context and return from exception. */ + #ifdef __XTENSA_CALL0_ABI__ + l32i a2, sp, 8 + l32i a3, sp, 12 + addi sp, sp, 16 + #else + call0 _xt_context_restore + addi sp, sp, XT_STK_FRMSZ + #endif + movi a0, -1 + movnez a2, a0, a2 /* return -1 if not syscall 0 */ + rsr a0, EXCSAVE_1 + rfe + +/* +-------------------------------------------------------------------------------- +Co-Processor Exception Handler (jumped to from User Exception Handler). +These exceptions are generated by co-processor instructions, which are only +allowed in thread code (not in interrupts or kernel code). This restriction is +deliberately imposed to reduce the burden of state-save/restore in interrupts. +-------------------------------------------------------------------------------- +*/ +#if XCHAL_CP_NUM > 0 + + .section .rodata, "a" + +/* Offset to CP n save area in thread's CP save area. */ + .global _xt_coproc_sa_offset + .type _xt_coproc_sa_offset,@object + .align 16 /* minimize crossing cache boundaries */ +_xt_coproc_sa_offset: + .word XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA + .word XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA + +/* Bitmask for CP n's CPENABLE bit. */ + .type _xt_coproc_mask,@object + .align 16,,8 /* try to keep it all in one cache line */ + .set i, 0 +_xt_coproc_mask: + .rept XCHAL_CP_MAX + .long (i<<16) | (1<= 2 + + .begin literal_prefix .Level2InterruptVector + .section .Level2InterruptVector.text, "ax" + .global _Level2Vector + .type _Level2Vector,@function + .align 4 + .literal_position + +_Level2Vector: + wsr a0, EXCSAVE_2 /* preserve a0 */ + call0 _xt_medint2 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .text + .type _xt_medint2,@function + .align 4 +_xt_medint2: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_2 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_2 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_2 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint2_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(2) | PS_UM + #else + movi a0, PS_INTLEVEL(2) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint2_exit + .type _xt_medint2_exit,@function + .align 4 +_xt_medint2_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_2 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_2 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 2 + +#endif /* Level 2 */ + +#if XCHAL_EXCM_LEVEL >= 3 + + .begin literal_prefix .Level3InterruptVector + .section .Level3InterruptVector.text, "ax" + .global _Level3Vector + .type _Level3Vector,@function + .align 4 + .literal_position + +_Level3Vector: + wsr a0, EXCSAVE_3 /* preserve a0 */ + call0 _xt_medint3 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .text + .type _xt_medint3,@function + .align 4 +_xt_medint3: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_3 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_3 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_3 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint3_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(3) | PS_UM + #else + movi a0, PS_INTLEVEL(3) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint3_exit + .type _xt_medint3_exit,@function + .align 4 +_xt_medint3_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_3 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_3 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 3 + +#endif /* Level 3 */ + +#if XCHAL_EXCM_LEVEL >= 4 + + .begin literal_prefix .Level4InterruptVector + .section .Level4InterruptVector.text, "ax" + .global _Level4Vector + .type _Level4Vector,@function + .align 4 + .literal_position + +_Level4Vector: + wsr a0, EXCSAVE_4 /* preserve a0 */ + call0 _xt_medint4 /* load interrupt handler */ + + .end literal_prefix + + .text + .type _xt_medint4,@function + .align 4 +_xt_medint4: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_4 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_4 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_4 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint4_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(4) | PS_UM + #else + movi a0, PS_INTLEVEL(4) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint4_exit + .type _xt_medint4_exit,@function + .align 4 +_xt_medint4_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_4 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_4 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 4 + +#endif /* Level 4 */ + +#if XCHAL_EXCM_LEVEL >= 5 + + .begin literal_prefix .Level5InterruptVector + .section .Level5InterruptVector.text, "ax" + .global _Level5Vector + .type _Level5Vector,@function + .align 4 + .literal_position + +_Level5Vector: + wsr a0, EXCSAVE_5 /* preserve a0 */ + call0 _xt_medint5 /* load interrupt handler */ + + .end literal_prefix + + .text + .type _xt_medint5,@function + .align 4 +_xt_medint5: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_5 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_5 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_5 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint5_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(5) | PS_UM + #else + movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint5_exit + .type _xt_medint5_exit,@function + .align 4 +_xt_medint5_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_5 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_5 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 5 + +#endif /* Level 5 */ + +#if XCHAL_EXCM_LEVEL >= 6 + + .begin literal_prefix .Level6InterruptVector + .section .Level6InterruptVector.text, "ax" + .global _Level6Vector + .type _Level6Vector,@function + .align 4 + .literal_position + +_Level6Vector: + wsr a0, EXCSAVE_6 /* preserve a0 */ + call0 _xt_medint6 /* load interrupt handler */ + + .end literal_prefix + + .text + .type _xt_medint6,@function + .align 4 +_xt_medint6: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_6 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_6 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_6 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint6_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(6) | PS_UM + #else + movi a0, PS_INTLEVEL(6) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint6_exit + .type _xt_medint6_exit,@function + .align 4 +_xt_medint6_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_6 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_6 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 6 + +#endif /* Level 6 */ + + +/******************************************************************************* + +HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS + +High priority interrupts are by definition those with priorities greater +than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority +interrupts cannot interact with the RTOS, that is they must save all regs +they use and not call any RTOS function. + +A further restriction imposed by the Xtensa windowed architecture is that +high priority interrupts must not modify the stack area even logically +"above" the top of the interrupted stack (they need to provide their +own stack or static save area). + +Cadence Design Systems recommends high priority interrupt handlers be coded in assembly +and used for purposes requiring very short service times. + +Here are templates for high priority (level 2+) interrupt vectors. +They assume only one interrupt per level to avoid the burden of identifying +which interrupts at this level are pending and enabled. This allows for +minimum latency and avoids having to save/restore a2 in addition to a0. +If more than one interrupt per high priority level is configured, this burden +is on the handler which in any case must provide a way to save and restore +registers it uses without touching the interrupted stack. + +Each vector goes at a predetermined location according to the Xtensa +hardware configuration, which is ensured by its placement in a special +section known to the Xtensa linker support package (LSP). It performs +the minimum necessary before jumping to the handler in the .text section. + +*******************************************************************************/ + +/* +Currently only shells for high priority interrupt handlers are provided +here. However a template and example can be found in the Cadence Design Systems tools +documentation: "Microprocessor Programmer's Guide". +*/ + +#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2 + + .begin literal_prefix .Level2InterruptVector + .section .Level2InterruptVector.text, "ax" + .global _Level2Vector + .type _Level2Vector,@function + .align 4 +_Level2Vector: + wsr a0, EXCSAVE_2 /* preserve a0 */ + call0 _xt_highint2 /* load interrupt handler */ + + .end literal_prefix + + .text + .type _xt_highint2,@function + .align 4 +_xt_highint2: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 2<<2 + beqz a0, 1f +.Ln_xt_highint2_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint2_exit: + rsr a0, EXCSAVE_2 /* restore a0 */ + rfi 2 + +#endif /* Level 2 */ + +#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3 + + .begin literal_prefix .Level3InterruptVector + .section .Level3InterruptVector.text, "ax" + .global _Level3Vector + .type _Level3Vector,@function + .align 4 +_Level3Vector: + wsr a0, EXCSAVE_3 /* preserve a0 */ + call0 _xt_highint3 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .text + .type _xt_highint3,@function + .align 4 +_xt_highint3: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 3<<2 + beqz a0, 1f +.Ln_xt_highint3_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint3_exit: + rsr a0, EXCSAVE_3 /* restore a0 */ + rfi 3 + +#endif /* Level 3 */ + +#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4 + + .begin literal_prefix .Level4InterruptVector + .section .Level4InterruptVector.text, "ax" + .global _Level4Vector + .type _Level4Vector,@function + .align 4 +_Level4Vector: + wsr a0, EXCSAVE_4 /* preserve a0 */ + call0 _xt_highint4 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .text + .type _xt_highint4,@function + .align 4 +_xt_highint4: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 4<<2 + beqz a0, 1f +.Ln_xt_highint4_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint4_exit: + rsr a0, EXCSAVE_4 /* restore a0 */ + rfi 4 + +#endif /* Level 4 */ + +#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5 + + .begin literal_prefix .Level5InterruptVector + .section .Level5InterruptVector.text, "ax" + .global _Level5Vector + .type _Level5Vector,@function + .align 4 +_Level5Vector: + wsr a0, EXCSAVE_5 /* preserve a0 */ + call0 _xt_highint5 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .text + .type _xt_highint5,@function + .align 4 +_xt_highint5: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 5<<2 + beqz a0, 1f +.Ln_xt_highint5_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint5_exit: + rsr a0, EXCSAVE_5 /* restore a0 */ + rfi 5 + +#endif /* Level 5 */ + +#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6 + + .begin literal_prefix .Level6InterruptVector + .section .Level6InterruptVector.text, "ax" + .global _Level6Vector + .type _Level6Vector,@function + .align 4 +_Level6Vector: + wsr a0, EXCSAVE_6 /* preserve a0 */ + call0 _xt_highint6 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .text + .type _xt_highint6,@function + .align 4 +_xt_highint6: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, 6<<2 + beqz a0, 1f +.Ln_xt_highint6_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xt_highint6_exit: + rsr a0, EXCSAVE_6 /* restore a0 */ + rfi 6 + +#endif /* Level 6 */ + +#if XCHAL_HAVE_NMI + + .begin literal_prefix .NMIExceptionVector + .section .NMIExceptionVector.text, "ax" + .global _NMIExceptionVector + .type _NMIExceptionVector,@function + .align 4 +_NMIExceptionVector: + wsr a0, EXCSAVE + XCHAL_NMILEVEL _ /* preserve a0 */ + call0 _xt_nmi /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .text + .type _xt_nmi,@function + .align 4 +_xt_nmi: + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a0, _xt_intexc_hooks + l32i a0, a0, XCHAL_NMILEVEL<<2 + beqz a0, 1f +.Ln_xt_nmi_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: + #endif + + /* USER_EDIT: + ADD HIGH PRIORITY NON-MASKABLE INTERRUPT (NMI) HANDLER CODE HERE. + */ + + .align 4 +.L_xt_nmi_exit: + rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */ + rfi XCHAL_NMILEVEL + +#endif /* NMI */ + + +/******************************************************************************* + +WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER + +Here is the code for each window overflow/underflow exception vector and +(interspersed) efficient code for handling the alloca exception cause. +Window exceptions are handled entirely in the vector area and are very +tight for performance. The alloca exception is also handled entirely in +the window vector area so comes at essentially no cost in code size. +Users should never need to modify them and Cadence Design Systems recommends +they do not. + +Window handlers go at predetermined vector locations according to the +Xtensa hardware configuration, which is ensured by their placement in a +special section known to the Xtensa linker support package (LSP). Since +their offsets in that section are always the same, the LSPs do not define +a section per vector. + +These things are coded for XEA2 only (XEA1 is not supported). + +Note on Underflow Handlers: +The underflow handler for returning from call[i+1] to call[i] +must preserve all the registers from call[i+1]'s window. +In particular, a0 and a1 must be preserved because the RETW instruction +will be reexecuted (and may even underflow if an intervening exception +has flushed call[i]'s registers). +Registers a2 and up may contain return values. + +*******************************************************************************/ + +#if XCHAL_HAVE_WINDOWED + + .section .WindowVectors.text, "ax" + +/* +-------------------------------------------------------------------------------- +Window Overflow Exception for Call4. + +Invoked if a call[i] referenced a register (a4-a15) +that contains data from ancestor call[j]; +call[j] had done a call4 to call[j+1]. +On entry here: + window rotated to call[j] start point; + a0-a3 are registers to be saved; + a4-a15 must be preserved; + a5 is call[j+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x0 + .global _WindowOverflow4 +_WindowOverflow4: + + s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */ + s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/* +-------------------------------------------------------------------------------- +Window Underflow Exception for Call4 + +Invoked by RETW returning from call[i+1] to call[i] +where call[i]'s registers must be reloaded (not live in ARs); +where call[i] had done a call4 to call[i+1]. +On entry here: + window rotated to call[i] start point; + a0-a3 are undefined, must be reloaded with call[i].reg[0..3]; + a4-a15 must be preserved (they are call[i+1].reg[0..11]); + a5 is call[i+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x40 + .global _WindowUnderflow4 +_WindowUnderflow4: + + l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */ + rfwu + +/* +-------------------------------------------------------------------------------- +Handle alloca exception generated by interruptee executing 'movsp'. +This uses space between the window vectors, so is essentially "free". +All interruptee's regs are intact except a0 which is saved in EXCSAVE_1, +and PS.EXCM has been set by the exception hardware (can't be interrupted). +The fact the alloca exception was taken means the registers associated with +the base-save area have been spilled and will be restored by the underflow +handler, so those 4 registers are available for scratch. +The code is optimized to avoid unaligned branches and minimize cache misses. +-------------------------------------------------------------------------------- +*/ + + .align 4 + .global _xt_alloca_exc +_xt_alloca_exc: + + rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */ + rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */ + rsr a2, PS + extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS + xor a3, a3, a4 /* bits changed from old to current windowbase */ + rsr a4, EXCSAVE_1 /* restore original a0 (now in a4) */ + slli a3, a3, XCHAL_PS_OWB_SHIFT + xor a2, a2, a3 /* flip changed bits in old window base */ + wsr a2, PS /* update PS.OWB to new window base */ + rsync + + _bbci.l a4, 31, _WindowUnderflow4 + rotw -1 /* original a0 goes to a8 */ + _bbci.l a8, 30, _WindowUnderflow8 + rotw -1 + j _WindowUnderflow12 + +/* +-------------------------------------------------------------------------------- +Window Overflow Exception for Call8 + +Invoked if a call[i] referenced a register (a4-a15) +that contains data from ancestor call[j]; +call[j] had done a call8 to call[j+1]. +On entry here: + window rotated to call[j] start point; + a0-a7 are registers to be saved; + a8-a15 must be preserved; + a9 is call[j+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x80 + .global _WindowOverflow8 +_WindowOverflow8: + + s32e a0, a9, -16 /* save a0 to call[j+1]'s stack frame */ + l32e a0, a1, -12 /* a0 <- call[j-1]'s sp + (used to find end of call[j]'s frame) */ + s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a9, -4 /* save a3 to call[j+1]'s stack frame */ + s32e a4, a0, -32 /* save a4 to call[j]'s stack frame */ + s32e a5, a0, -28 /* save a5 to call[j]'s stack frame */ + s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */ + s32e a7, a0, -20 /* save a7 to call[j]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/* +-------------------------------------------------------------------------------- +Window Underflow Exception for Call8 + +Invoked by RETW returning from call[i+1] to call[i] +where call[i]'s registers must be reloaded (not live in ARs); +where call[i] had done a call8 to call[i+1]. +On entry here: + window rotated to call[i] start point; + a0-a7 are undefined, must be reloaded with call[i].reg[0..7]; + a8-a15 must be preserved (they are call[i+1].reg[0..7]); + a9 is call[i+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0xC0 + .global _WindowUnderflow8 +_WindowUnderflow8: + + l32e a0, a9, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a7, a1, -12 /* a7 <- call[i-1]'s sp + (used to find end of call[i]'s frame) */ + l32e a3, a9, -4 /* restore a3 from call[i+1]'s stack frame */ + l32e a4, a7, -32 /* restore a4 from call[i]'s stack frame */ + l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */ + l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */ + l32e a7, a7, -20 /* restore a7 from call[i]'s stack frame */ + rfwu + +/* +-------------------------------------------------------------------------------- +Window Overflow Exception for Call12 + +Invoked if a call[i] referenced a register (a4-a15) +that contains data from ancestor call[j]; +call[j] had done a call12 to call[j+1]. +On entry here: + window rotated to call[j] start point; + a0-a11 are registers to be saved; + a12-a15 must be preserved; + a13 is call[j+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x100 + .global _WindowOverflow12 +_WindowOverflow12: + + s32e a0, a13, -16 /* save a0 to call[j+1]'s stack frame */ + l32e a0, a1, -12 /* a0 <- call[j-1]'s sp + (used to find end of call[j]'s frame) */ + s32e a1, a13, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a13, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a13, -4 /* save a3 to call[j+1]'s stack frame */ + s32e a4, a0, -48 /* save a4 to end of call[j]'s stack frame */ + s32e a5, a0, -44 /* save a5 to end of call[j]'s stack frame */ + s32e a6, a0, -40 /* save a6 to end of call[j]'s stack frame */ + s32e a7, a0, -36 /* save a7 to end of call[j]'s stack frame */ + s32e a8, a0, -32 /* save a8 to end of call[j]'s stack frame */ + s32e a9, a0, -28 /* save a9 to end of call[j]'s stack frame */ + s32e a10, a0, -24 /* save a10 to end of call[j]'s stack frame */ + s32e a11, a0, -20 /* save a11 to end of call[j]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/* +-------------------------------------------------------------------------------- +Window Underflow Exception for Call12 + +Invoked by RETW returning from call[i+1] to call[i] +where call[i]'s registers must be reloaded (not live in ARs); +where call[i] had done a call12 to call[i+1]. +On entry here: + window rotated to call[i] start point; + a0-a11 are undefined, must be reloaded with call[i].reg[0..11]; + a12-a15 must be preserved (they are call[i+1].reg[0..3]); + a13 is call[i+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x140 + .global _WindowUnderflow12 +_WindowUnderflow12: + + l32e a0, a13, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a13, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a13, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a11, a1, -12 /* a11 <- call[i-1]'s sp + (used to find end of call[i]'s frame) */ + l32e a3, a13, -4 /* restore a3 from call[i+1]'s stack frame */ + l32e a4, a11, -48 /* restore a4 from end of call[i]'s stack frame */ + l32e a5, a11, -44 /* restore a5 from end of call[i]'s stack frame */ + l32e a6, a11, -40 /* restore a6 from end of call[i]'s stack frame */ + l32e a7, a11, -36 /* restore a7 from end of call[i]'s stack frame */ + l32e a8, a11, -32 /* restore a8 from end of call[i]'s stack frame */ + l32e a9, a11, -28 /* restore a9 from end of call[i]'s stack frame */ + l32e a10, a11, -24 /* restore a10 from end of call[i]'s stack frame */ + l32e a11, a11, -20 /* restore a11 from end of call[i]'s stack frame */ + rfwu + +#endif /* XCHAL_HAVE_WINDOWED */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/Drivers/Tick/Tick.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/Drivers/Tick/Tick.c new file mode 100644 index 0000000..cd5da91 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/Drivers/Tick/Tick.c @@ -0,0 +1,139 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V3.0.0 + + ISRcode is pulled inline and portTICKisr() is therefore + deleted from this file. + + + Prescaler logic for Timer1 added to allow for a wider + range of TickRates. + +Changes from V3.0.1 +*/ + +#include +#include + +/* IO port constants. */ +#define portBIT_SET (1) +#define portBIT_CLEAR (0) + +/* + * Hardware setup for the tick. + * We use a compare match on timer1. Depending on MPU-frequency + * and requested tickrate, a prescaled value with a matching + * prescaler are determined. + */ +#define portTIMER_COMPARE_BASE ((APROCFREQ/4)/configTICK_RATE_HZ) + +#if portTIMER_COMPARE_BASE < 0x10000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE) + #define portTIMER_COMPARE_PS1 (portBIT_CLEAR) + #define portTIMER_COMPARE_PS0 (portBIT_CLEAR) +#elif portTIMER_COMPARE_BASE < 0x20000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 2) + #define portTIMER_COMPARE_PS1 (portBIT_CLEAR) + #define portTIMER_COMPARE_PS0 (portBIT_SET) +#elif portTIMER_COMPARE_BASE < 0x40000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 4) + #define portTIMER_COMPARE_PS1 (portBIT_SET) + #define portTIMER_COMPARE_PS0 (portBIT_CLEAR) +#elif portTIMER_COMPARE_BASE < 0x80000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 8) + #define portTIMER_COMPARE_PS1 (portBIT_SET) + #define portTIMER_COMPARE_PS0 (portBIT_SET) +#else + #error "TickRate out of range" +#endif + +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. + */ +void portSetupTick( void ) +{ + /* + * Interrupts are disabled when this function is called. + */ + + /* + * Setup CCP1 + * Provide the tick interrupt using a compare match on timer1. + */ + + /* + * Set the compare match value. + */ + CCPR1H = ( uint8_t ) ( ( portTIMER_COMPARE_VALUE >> 8 ) & 0xff ); + CCPR1L = ( uint8_t ) ( portTIMER_COMPARE_VALUE & 0xff ); + + /* + * Set Compare Special Event Trigger Mode + */ + bCCP1M3 = portBIT_SET; + bCCP1M2 = portBIT_CLEAR; + bCCP1M1 = portBIT_SET; + bCCP1M0 = portBIT_SET; + + /* + * Enable CCP1 interrupt + */ + bCCP1IE = portBIT_SET; + + /* + * We are only going to use the global interrupt bit, so disable + * interruptpriorities and enable peripheral interrupts. + */ + bIPEN = portBIT_CLEAR; + bPEIE = portBIT_SET; + + /* + * Set up timer1 + * It will produce the system tick. + */ + + /* + * Clear the time count + */ + TMR1H = ( uint8_t ) 0x00; + TMR1L = ( uint8_t ) 0x00; + + /* + * Setup the timer + */ + bRD16 = portBIT_SET; // 16-bit + bT1CKPS1 = portTIMER_COMPARE_PS1; // prescaler + bT1CKPS0 = portTIMER_COMPARE_PS0; // prescaler + bT1OSCEN = portBIT_SET; // Oscillator enable + bT1SYNC = portBIT_SET; // No external clock sync + bTMR1CS = portBIT_CLEAR; // Internal clock + + bTMR1ON = portBIT_SET; // Start timer1 +} diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/Drivers/Tick/isrTick.c new file mode 100644 index 0000000..90b5044 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/Drivers/Tick/isrTick.c @@ -0,0 +1,79 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V3.0.0 + + ISRcode pulled inline to reduce stack-usage. + + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Filename changed to a .c extension to allow stepping through code + using F7. + +Changes from V3.0.1 +*/ + +/* + * ISR for the tick. + * This increments the tick count and, if using the preemptive scheduler, + * performs a context switch. This must be identical to the manual + * context switch in how it stores the context of a task. + */ + +#ifndef _FREERTOS_DRIVERS_TICK_ISRTICK_C +#define _FREERTOS_DRIVERS_TICK_ISRTICK_C + +{ + /* + * Was the interrupt the SystemClock? + */ + if( bCCP1IF && bCCP1IE ) + { + /* + * Reset the interrupt flag + */ + bCCP1IF = 0; + + /* + * Maintain the tick count. + */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* + * Ask for a switch to the highest priority task + * that is ready to run. + */ + uxSwitchRequested = pdTRUE; + } + } +} + +#pragma wizcpp uselib "$__PATHNAME__/Tick.c" + +#endif /* _FREERTOS_DRIVERS_TICK_ISRTICK_C */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/Install.bat b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/Install.bat new file mode 100644 index 0000000..780ec21 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/Install.bat @@ -0,0 +1,172 @@ + +@echo off +cls + +SET PACKAGENAME=the FreeRTOS port for fedC and wizC + +echo. +echo Hello, I'm the installationscript for %PACKAGENAME%. +echo. + +:CHECKFEDC + set FED=C:\Program Files\FED\PIC_C + echo. + echo I'm checking your system for fedC + if not exist "%FED%" goto NOFEDC + echo YES, I found a fedC-installation! + goto FOUNDFED +:NOFEDC + echo I could not find a fedC-installation. + + +:CHECKWIZC + set FED=C:\Program Files\FED\PIXIE + echo. + echo I'm checking your system for wizC + if not exist "%FED%" goto NOWIZC + echo YES, I found a wizC-installation! + goto FOUNDFED +:noWIZC + echo I could not find a wizC-installation. + + +:ERROR + echo. + echo. + echo I could not find a FED C-compiler installation on your system. + echo. + echo Perhaps I got confused because you installed fedC or wizC in a non-default directory. + echo If this is the case, please change the path at the top of this install-script. + echo After that rerun the script and I will be happy to try again. + echo. + goto ENDIT + + +:FOUNDFED + echo. + echo. + + set FEDLIBS=%FED%\Libs + set FEDLIBSUSER=%FEDLIBS%\LibsUser + + if exist "%FEDLIBS%" goto INSTALL + echo The FED installationdirectory "%FED%" + echo contains no Libs subdirectory. This is weird! + echo. + echo Installation is aborted, sorry... + goto ENDIT + + +:INSTALL + echo I am about to install %PACKAGENAME% + echo into directory %FEDLIBSUSER% + echo. + echo Press 'enter' to let me do my thing + echo Press 'ctrl-c' to stop me + pause >nul + echo. + echo Installing... + + +:RESET_READONLY + echo. + echo Removing ReadOnly attributes + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul + attrib -R "%FEDLIBSUSER%\FreeRTOS.h" >nul + echo Done + +:CREATE_DIRECTORIES + echo. + echo Creating directories (if necessary)... + if not exist "%FEDLIBSUSER%" mkdir "%FEDLIBSUSER%" + if not exist "%FEDLIBSUSER%\libFreeRTOS" mkdir "%FEDLIBSUSER%\libFreeRTOS" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Include" mkdir "%FEDLIBSUSER%\libFreeRTOS\Include" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Modules" mkdir "%FEDLIBSUSER%\libFreeRTOS\Modules" + echo Done + + + echo. + echo Copying Files... +:COPY_MODULES + echo Modules... + copy /V /Y "Port.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul + copy /V /Y "..\..\..\Croutine.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c" >nul + copy /V /Y "..\..\..\List.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul + copy /V /Y "..\..\..\Queue.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul + copy /V /Y "..\..\..\Tasks.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul + +:COPY_DRIVERS + echo Drivers... + copy /V /Y "Drivers\Tick\Tick.c" "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul + copy /V /Y "Drivers\Tick\isrTick.c" "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul + +:COPY_HEADERS + echo Headers... + copy /V /Y "portmacro.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul + copy /V /Y "..\..\..\include\Croutine.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h" >nul + copy /V /Y "..\..\..\include\List.h" "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul + copy /V /Y "..\..\..\include\Portable.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul + copy /V /Y "..\..\..\include\Projdefs.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul + copy /V /Y "..\..\..\include\Queue.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul + copy /V /Y "..\..\..\include\Semphr.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul + copy /V /Y "..\..\..\include\Task.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul + copy /V /Y "addFreeRTOS.h" + "..\..\..\include\FreeRTOS.h" "%FEDLIBSUSER%\FreeRTOS.h" >nul + + + echo Done + + +:SET_READONLY + echo. + echo Setting files to ReadOnly + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul + attrib +R "%FEDLIBSUSER%\FreeRTOS.h" >nul + echo Done + + +:FINISHED + echo. + echo The installation of %PACKAGENAME% is completed. + echo. + echo Please review the installation instructions as additional libraries + echo and fedC/wizC configuration settings may be needed for FreeRTOS + echo to function correctly. + + goto ENDIT + + +:ENDIT + echo. + echo. + echo Press 'enter' to close this window + pause >nul diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/addFreeRTOS.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/addFreeRTOS.h new file mode 100644 index 0000000..71e655b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/addFreeRTOS.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 + +Changes from V4.0.1 + Uselib pragma added for Croutine.c +*/ + +/* + * The installation script will automatically prepend this file to the default FreeRTOS.h. + */ + +#ifndef WIZC_FREERTOS_H +#define WIZC_FREERTOS_H + +#pragma noheap +#pragma wizcpp expandnl on +#pragma wizcpp searchpath "$__PATHNAME__/libFreeRTOS/Include/" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Croutine.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Tasks.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Queue.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/List.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Port.c" + +#endif /* WIZC_FREERTOS_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/port.c new file mode 100644 index 0000000..07aa4c7 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/port.c @@ -0,0 +1,318 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V3.2.1 + + CallReturn Depth increased from 8 to 10 levels to accomodate wizC/fedC V12. + +Changes from V3.2.0 + + TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves + an error on devices with more than 64kB ROM. + +Changes from V3.0.0 + + ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being + handled before the scheduler is started. + +Changes from V3.0.1 +*/ + +/* Scheduler include files. */ +#include +#include + +#include + +/*--------------------------------------------------------------------------- + * Implementation of functions defined in portable.h for the WizC PIC18 port. + *---------------------------------------------------------------------------*/ + +/* + * We require the address of the pxCurrentTCB variable, but don't want to + * know any details of its type. + */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* + * Define minimal-stack constants + * ----- + * FSR's: + * STATUS, WREG, BSR, PRODH, PRODL, FSR0H, FSR0L, + * FSR1H, FSR1L,TABLAT, (TBLPTRU), TBLPTRH, TBLPTRL, + * (PCLATU), PCLATH + * sfr's within parenthesis only on devices > 64kB + * ----- + * Call/Return stack: + * 2 bytes per entry on devices <= 64kB + * 3 bytes per entry on devices > 64kB + * ----- + * Other bytes: + * 2 bytes: FunctionParameter for initial taskcode + * 1 byte : Number of entries on call/return stack + * 1 byte : ucCriticalNesting + * 16 bytes: Free space on stack + */ +#if _ROMSIZE > 0x8000 + #define portSTACK_FSR_BYTES ( 15 ) + #define portSTACK_CALLRETURN_ENTRY_SIZE ( 3 ) +#else + #define portSTACK_FSR_BYTES ( 13 ) + #define portSTACK_CALLRETURN_ENTRY_SIZE ( 2 ) +#endif + +#define portSTACK_MINIMAL_CALLRETURN_DEPTH ( 10 ) +#define portSTACK_OTHER_BYTES ( 20 ) + +uint16_t usCalcMinStackSize = 0; + +/*-----------------------------------------------------------*/ + +/* + * We initialise ucCriticalNesting to the middle value an + * uint8_t can contain. This way portENTER_CRITICAL() + * and portEXIT_CRITICAL() can be called without interrupts + * being enabled before the scheduler starts. + */ +register uint8_t ucCriticalNesting = 0x7F; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a new task. + * See portSAVE_CONTEXT macro for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint8_t ucScratch; + /* + * Get the size of the RAMarea in page 0 used by the compiler + * We do this here already to avoid W-register conflicts. + */ + _Pragma("asm") + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE + movwf PRODL,ACCESS ; PRODL is used as temp register + _Pragma("asmend") + ucScratch = PRODL; + + /* + * Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging. + */ +// *pxTopOfStack-- = 0x11; +// *pxTopOfStack-- = 0x22; +// *pxTopOfStack-- = 0x33; + + /* + * Simulate how the stack would look after a call to vPortYield() + * generated by the compiler. + */ + + /* + * First store the function parameters. This is where the task expects + * to find them when it starts running. + */ + *pxTopOfStack-- = ( StackType_t ) ( (( uint16_t ) pvParameters >> 8) & 0x00ff ); + *pxTopOfStack-- = ( StackType_t ) ( ( uint16_t ) pvParameters & 0x00ff ); + + /* + * Next are all the registers that form part of the task context. + */ + *pxTopOfStack-- = ( StackType_t ) 0x11; /* STATUS. */ + *pxTopOfStack-- = ( StackType_t ) 0x22; /* WREG. */ + *pxTopOfStack-- = ( StackType_t ) 0x33; /* BSR. */ + *pxTopOfStack-- = ( StackType_t ) 0x44; /* PRODH. */ + *pxTopOfStack-- = ( StackType_t ) 0x55; /* PRODL. */ + *pxTopOfStack-- = ( StackType_t ) 0x66; /* FSR0H. */ + *pxTopOfStack-- = ( StackType_t ) 0x77; /* FSR0L. */ + *pxTopOfStack-- = ( StackType_t ) 0x88; /* FSR1H. */ + *pxTopOfStack-- = ( StackType_t ) 0x99; /* FSR1L. */ + *pxTopOfStack-- = ( StackType_t ) 0xAA; /* TABLAT. */ +#if _ROMSIZE > 0x8000 + *pxTopOfStack-- = ( StackType_t ) 0x00; /* TBLPTRU. */ +#endif + *pxTopOfStack-- = ( StackType_t ) 0xCC; /* TBLPTRH. */ + *pxTopOfStack-- = ( StackType_t ) 0xDD; /* TBLPTRL. */ +#if _ROMSIZE > 0x8000 + *pxTopOfStack-- = ( StackType_t ) 0xEE; /* PCLATU. */ +#endif + *pxTopOfStack-- = ( StackType_t ) 0xFF; /* PCLATH. */ + + /* + * Next the compiler's scratchspace. + */ + while(ucScratch-- > 0) + { + *pxTopOfStack-- = ( StackType_t ) 0; + } + + /* + * The only function return address so far is the address of the task entry. + * The order is TOSU/TOSH/TOSL. For devices > 64kB, TOSU is put on the + * stack, too. TOSU is always written as zero here because wizC does not allow + * functionpointers to point above 64kB in ROM. + */ +#if _ROMSIZE > 0x8000 + *pxTopOfStack-- = ( StackType_t ) 0; +#endif + *pxTopOfStack-- = ( StackType_t ) ( ( ( uint16_t ) pxCode >> 8 ) & 0x00ff ); + *pxTopOfStack-- = ( StackType_t ) ( ( uint16_t ) pxCode & 0x00ff ); + + /* + * Store the number of return addresses on the hardware stack. + * So far only the address of the task entry point. + */ + *pxTopOfStack-- = ( StackType_t ) 1; + + /* + * The code generated by wizC does not maintain separate + * stack and frame pointers. Therefore the portENTER_CRITICAL macro cannot + * use the stack as per other ports. Instead a variable is used to keep + * track of the critical section nesting. This variable has to be stored + * as part of the task context and is initially set to zero. + */ + *pxTopOfStack-- = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void ) +{ + /* + * Fetch the size of compiler's scratchspace. + */ + _Pragma("asm") + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE + movlb usCalcMinStackSize>>8 + movwf usCalcMinStackSize,BANKED + _Pragma("asmend") + + /* + * Add minimum needed stackspace + */ + usCalcMinStackSize += ( portSTACK_FSR_BYTES ) + + ( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE ) + + ( portSTACK_OTHER_BYTES ); + + return(usCalcMinStackSize); +} + +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void portSetupTick( void ); + + /* + * Setup a timer for the tick ISR for the preemptive scheduler. + */ + portSetupTick(); + + /* + * Restore the context of the first task to run. + */ + portRESTORE_CONTEXT(); + + /* + * This point should never be reached during execution. + */ + return pdTRUE; +} + +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* + * It is unlikely that the scheduler for the PIC port will get stopped + * once running. When called a reset is done which is probably the + * most valid action. + */ + _Pragma(asmline reset); +} + +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. This is similar to the tick context switch, + * but does not increment the tick count. It must be identical to the + * tick context switch in how it stores the stack of a task. + */ +void vPortYield( void ) +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED ); + + /* + * Switch to the highest priority task that is ready to run. + */ + vTaskSwitchContext(); + + /* + * Start executing the task we have just switched to. + */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + void *pvPortMalloc( uint16_t usWantedSize ) + { + void *pvReturn; + + vTaskSuspendAll(); + { + pvReturn = malloc( ( malloc_t ) usWantedSize ); + } + xTaskResumeAll(); + + return pvReturn; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + void vPortFree( void *pv ) + { + if( pv ) + { + vTaskSuspendAll(); + { + free( pv ); + } + xTaskResumeAll(); + } + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/portmacro.h new file mode 100644 index 0000000..94223c4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/WizC/PIC18/portmacro.h @@ -0,0 +1,424 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#if !defined(_SERIES) || _SERIES != 18 + #error "WizC supports FreeRTOS on the Microchip PIC18-series only" +#endif + +#if !defined(QUICKCALL) || QUICKCALL != 1 + #error "QuickCall must be enabled (see ProjectOptions/Optimisations)" +#endif + +#include +#include + +#define portCHAR char +#define portFLOAT float +#define portDOUBLE portFLOAT +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFF ) +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFF ) +#endif + +#define portBYTE_ALIGNMENT 1 + +/*-----------------------------------------------------------*/ + +/* + * Constant used for context switch macro when we require the interrupt + * enable state to be forced when the interrupted task is switched back in. + */ +#define portINTERRUPTS_FORCED (0x01) + +/* + * Constant used for context switch macro when we require the interrupt + * enable state to be unchanged when the interrupted task is switched back in. + */ +#define portINTERRUPTS_UNCHANGED (0x00) + +/* Initial interrupt enable state for newly created tasks. This value is + * used when a task switches in for the first time. + */ +#define portINTERRUPTS_INITIAL_STATE (portINTERRUPTS_FORCED) + +/* + * Macros to modify the global interrupt enable bit in INTCON. + */ +#define portDISABLE_INTERRUPTS() \ + do \ + { \ + bGIE=0; \ + } while(bGIE) // MicroChip recommends this check! + +#define portENABLE_INTERRUPTS() \ + do \ + { \ + bGIE=1; \ + } while(0) + +/*-----------------------------------------------------------*/ + +/* + * Critical section macros. + */ +extern uint8_t ucCriticalNesting; + +#define portNO_CRITICAL_SECTION_NESTING ( ( uint8_t ) 0 ) + +#define portENTER_CRITICAL() \ + do \ + { \ + portDISABLE_INTERRUPTS(); \ + \ + /* \ + * Now interrupts are disabled ucCriticalNesting \ + * can be accessed directly. Increment \ + * ucCriticalNesting to keep a count of how \ + * many times portENTER_CRITICAL() has been called. \ + */ \ + ucCriticalNesting++; \ + } while(0) + +#define portEXIT_CRITICAL() \ + do \ + { \ + if(ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING) \ + { \ + /* \ + * Decrement the nesting count as we are leaving a \ + * critical section. \ + */ \ + ucCriticalNesting--; \ + } \ + \ + /* \ + * If the nesting level has reached zero then \ + * interrupts should be re-enabled. \ + */ \ + if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } while(0) + +/*-----------------------------------------------------------*/ + +/* + * The minimal stacksize is calculated on the first reference of + * portMINIMAL_STACK_SIZE. Some input to this calculation is + * compiletime determined, other input is port-defined (see port.c) + */ +extern uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void ); +extern uint16_t usCalcMinStackSize; + +#define portMINIMAL_STACK_SIZE \ + ((usCalcMinStackSize == 0) \ + ? usPortCALCULATE_MINIMAL_STACK_SIZE() \ + : usCalcMinStackSize ) + +/* + * WizC uses a downgrowing stack + */ +#define portSTACK_GROWTH ( -1 ) + +/*-----------------------------------------------------------*/ + +/* + * Macro's that pushes all the registers that make up the context of a task onto + * the stack, then saves the new top of stack into the TCB. TOSU and TBLPTRU + * are only saved/restored on devices with more than 64kB (32k Words) ROM. + * + * The stackpointer is helt by WizC in FSR2 and points to the first free byte. + * WizC uses a "downgrowing" stack. There is no framepointer. + * + * We keep track of the interruptstatus using ucCriticalNesting. When this + * value equals zero, interrupts have to be enabled upon exit from the + * portRESTORE_CONTEXT macro. + * + * If this is called from an ISR then the interrupt enable bits must have been + * set for the ISR to ever get called. Therefore we want to save + * ucCriticalNesting with value zero. This means the interrupts will again be + * re-enabled when the interrupted task is switched back in. + * + * If this is called from a manual context switch (i.e. from a call to yield), + * then we want to keep the current value of ucCritialNesting so it is restored + * with its current value. This allows a yield from within a critical section. + * + * The compiler uses some locations at the bottom of RAM for temporary + * storage. The compiler may also have been instructed to optimize + * function-parameters and local variables to global storage. The compiler + * uses an area called LocOpt for this wizC feature. + * The total overheadstorage has to be saved in it's entirety as part of + * a task context. These macro's store/restore from data address 0x0000 to + * (OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE - 1). + * OVERHEADPAGE0, LOCOPTSIZE and MAXLOCOPTSIZE are compiler-generated + * assembler definitions. + */ + +#define portSAVE_CONTEXT( ucInterruptForced ) \ + do \ + { \ + portDISABLE_INTERRUPTS(); \ + \ + _Pragma("asm") \ + ; \ + ; Push the relevant SFR's onto the task's stack \ + ; \ + movff STATUS,POSTDEC2 \ + movff WREG,POSTDEC2 \ + movff BSR,POSTDEC2 \ + movff PRODH,POSTDEC2 \ + movff PRODL,POSTDEC2 \ + movff FSR0H,POSTDEC2 \ + movff FSR0L,POSTDEC2 \ + movff FSR1H,POSTDEC2 \ + movff FSR1L,POSTDEC2 \ + movff TABLAT,POSTDEC2 \ + if __ROMSIZE > 0x8000 \ + movff TBLPTRU,POSTDEC2 \ + endif \ + movff TBLPTRH,POSTDEC2 \ + movff TBLPTRL,POSTDEC2 \ + if __ROMSIZE > 0x8000 \ + movff PCLATU,POSTDEC2 \ + endif \ + movff PCLATH,POSTDEC2 \ + ; \ + ; Store the compiler-scratch-area as described above. \ + ; \ + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \ + clrf FSR0L,ACCESS \ + clrf FSR0H,ACCESS \ + _rtos_S1: \ + movff POSTINC0,POSTDEC2 \ + decfsz WREG,W,ACCESS \ + SMARTJUMP _rtos_S1 \ + ; \ + ; Save the pic call/return-stack belonging to the \ + ; current task by copying it to the task's software- \ + ; stack. We save the hardware stack pointer (which \ + ; is the number of addresses on the stack) in the \ + ; W-register first because we need it later and it \ + ; is modified in the save-loop by executing pop's. \ + ; After the loop the W-register is stored on the \ + ; stack, too. \ + ; \ + movf STKPTR,W,ACCESS \ + bz _rtos_s3 \ + _rtos_S2: \ + if __ROMSIZE > 0x8000 \ + movff TOSU,POSTDEC2 \ + endif \ + movff TOSH,POSTDEC2 \ + movff TOSL,POSTDEC2 \ + pop \ + tstfsz STKPTR,ACCESS \ + SMARTJUMP _rtos_S2 \ + _rtos_s3: \ + movwf POSTDEC2,ACCESS \ + ; \ + ; Next the value for ucCriticalNesting used by the \ + ; task is stored on the stack. When \ + ; (ucInterruptForced == portINTERRUPTS_FORCED), we save \ + ; it as 0 (portNO_CRITICAL_SECTION_NESTING). \ + ; \ + if ucInterruptForced == portINTERRUPTS_FORCED \ + clrf POSTDEC2,ACCESS \ + else \ + movff ucCriticalNesting,POSTDEC2 \ + endif \ + ; \ + ; Save the new top of the software stack in the TCB. \ + ; \ + movff pxCurrentTCB,FSR0L \ + movff pxCurrentTCB+1,FSR0H \ + movff FSR2L,POSTINC0 \ + movff FSR2H,POSTINC0 \ + _Pragma("asmend") \ + } while(0) + +/************************************************************/ + +/* + * This is the reverse of portSAVE_CONTEXT. + */ +#define portRESTORE_CONTEXT() \ + do \ + { \ + _Pragma("asm") \ + ; \ + ; Set FSR0 to point to pxCurrentTCB->pxTopOfStack. \ + ; \ + movff pxCurrentTCB,FSR0L \ + movff pxCurrentTCB+1,FSR0H \ + ; \ + ; De-reference FSR0 to set the address it holds into \ + ; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2 \ + ; is used by wizC as stackpointer. \ + ; \ + movff POSTINC0,FSR2L \ + movff POSTINC0,FSR2H \ + ; \ + ; Next, the value for ucCriticalNesting used by the \ + ; task is retrieved from the stack. \ + ; \ + movff PREINC2,ucCriticalNesting \ + ; \ + ; Rebuild the pic call/return-stack. The number of \ + ; return addresses is the next item on the task stack. \ + ; Save this number in PRODL. Then fetch the addresses \ + ; and store them on the hardwarestack. \ + ; The datasheets say we can't use movff here... \ + ; \ + movff PREINC2,PRODL // Use PRODL as tempregister \ + clrf STKPTR,ACCESS \ + _rtos_R1: \ + push \ + movf PREINC2,W,ACCESS \ + movwf TOSL,ACCESS \ + movf PREINC2,W,ACCESS \ + movwf TOSH,ACCESS \ + if __ROMSIZE > 0x8000 \ + movf PREINC2,W,ACCESS \ + movwf TOSU,ACCESS \ + else \ + clrf TOSU,ACCESS \ + endif \ + decfsz PRODL,F,ACCESS \ + SMARTJUMP _rtos_R1 \ + ; \ + ; Restore the compiler's working storage area to page 0 \ + ; \ + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \ + movwf FSR0L,ACCESS \ + clrf FSR0H,ACCESS \ + _rtos_R2: \ + decf FSR0L,F,ACCESS \ + movff PREINC2,INDF0 \ + tstfsz FSR0L,ACCESS \ + SMARTJUMP _rtos_R2 \ + ; \ + ; Restore the sfr's forming the tasks context. \ + ; We cannot yet restore bsr, w and status because \ + ; we need these registers for a final test. \ + ; \ + movff PREINC2,PCLATH \ + if __ROMSIZE > 0x8000 \ + movff PREINC2,PCLATU \ + else \ + clrf PCLATU,ACCESS \ + endif \ + movff PREINC2,TBLPTRL \ + movff PREINC2,TBLPTRH \ + if __ROMSIZE > 0x8000 \ + movff PREINC2,TBLPTRU \ + else \ + clrf TBLPTRU,ACCESS \ + endif \ + movff PREINC2,TABLAT \ + movff PREINC2,FSR1L \ + movff PREINC2,FSR1H \ + movff PREINC2,FSR0L \ + movff PREINC2,FSR0H \ + movff PREINC2,PRODL \ + movff PREINC2,PRODH \ + ; \ + ; The return from portRESTORE_CONTEXT() depends on \ + ; the value of ucCriticalNesting. When it is zero, \ + ; interrupts need to be enabled. This is done via a \ + ; retfie instruction because we need the \ + ; interrupt-enabling and the return to the restored \ + ; task to be uninterruptable. \ + ; Because bsr, status and W are affected by the test \ + ; they are restored after the test. \ + ; \ + movlb ucCriticalNesting>>8 \ + tstfsz ucCriticalNesting,BANKED \ + SMARTJUMP _rtos_R4 \ + _rtos_R3: \ + movff PREINC2,BSR \ + movff PREINC2,WREG \ + movff PREINC2,STATUS \ + retfie 0 ; Return enabling interrupts \ + _rtos_R4: \ + movff PREINC2,BSR \ + movff PREINC2,WREG \ + movff PREINC2,STATUS \ + return 0 ; Return without affecting interrupts \ + _Pragma("asmend") \ + } while(0) + +/*-----------------------------------------------------------*/ + +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + +/*-----------------------------------------------------------*/ + +extern void vPortYield( void ); +#define portYIELD() vPortYield() + +#define portNOP() _Pragma("asm") \ + nop \ + _Pragma("asmend") + +/*-----------------------------------------------------------*/ + +#define portTASK_FUNCTION( xFunction, pvParameters ) \ + void pointed xFunction( void *pvParameters ) \ + _Pragma(asmfunc xFunction) + +#define portTASK_FUNCTION_PROTO portTASK_FUNCTION +/*-----------------------------------------------------------*/ + + +#define volatile +#define register + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/Flsh186/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/Flsh186/port.c new file mode 100644 index 0000000..e997f65 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/Flsh186/port.c @@ -0,0 +1,247 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V1.00: + + + Call to taskYIELD() from within tick ISR has been replaced by the more + efficient portSWITCH_CONTEXT(). + + ISR function definitions renamed to include the prv prefix. + +Changes from V1.2.0: + + + portRESET_PIC() is now called last thing before the end of the preemptive + tick routine. + +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Flashlite 186 + * port. + *----------------------------------------------------------*/ + +#include +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_EOI_TYPE ( 8 ) +#define portRESET_PIC() portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE ) +#define portTIMER_INT_NUMBER 0x12 + +#define portTIMER_1_CONTROL_REGISTER ( ( uint16_t ) 0xff5e ) +#define portTIMER_0_CONTROL_REGISTER ( ( uint16_t ) 0xff56 ) +#define portTIMER_INTERRUPT_ENABLE ( ( uint16_t ) 0x2000 ) + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetTickFrequency( uint32_t ulTickRateHz ); + +/* Set the hardware back to the state as per before the scheduler started. */ +static void prvExitFunction( void ); + +#if configUSE_PREEMPTION == 1 + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static int16_t sSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +BaseType_t xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + #if configUSE_PREEMPTION == 1 + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + sSchedulerRunning = pdFALSE; + } + else + { + sSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return sSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The tick ISR used depend on whether or not the preemptive or cooperative +kernel is being used. */ +#if configUSE_PREEMPTION == 1 + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + } + + /* Reset the PIC ready for the next time. */ + portRESET_PIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + xTaskIncrementTick(); + portRESET_PIC(); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +const uint16_t usTimerDisable = 0x0000; +uint16_t usTimer0Control; + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( sSchedulerRunning == pdTRUE ) + { + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + } + + /* Disable the timer used for the tick to ensure the scheduler is + not called before restoring interrupts. There was previously nothing + on this timer so there is no old ISR to restore. */ + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable ); + + /* Restart the DOS tick. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control |= portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); + + + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( uint32_t ulTickRateHz ) +{ +const uint16_t usMaxCountRegister = 0xff5a; +const uint16_t usTimerPriorityRegister = 0xff32; +const uint16_t usTimerEnable = 0xC000; +const uint16_t usRetrigger = 0x0001; +const uint16_t usTimerHighPriority = 0x0000; +uint16_t usTimer0Control; + +/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */ + +const uint32_t ulClockFrequency = 0x7f31a0; + +uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz; + + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger ); + portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount ); + portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority ); + + /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); +} + + +/*lint +e950 */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/Flsh186/portmacro.h new file mode 100644 index 0000000..0a117b4 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/Flsh186/portmacro.h @@ -0,0 +1,111 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +void portENTER_CRITICAL( void ); +#pragma aux portENTER_CRITICAL = "pushf" \ + "cli"; + +void portEXIT_CRITICAL( void ); +#pragma aux portEXIT_CRITICAL = "popf"; + +void portDISABLE_INTERRUPTS( void ); +#pragma aux portDISABLE_INTERRUPTS = "cli"; + +void portENABLE_INTERRUPTS( void ); +#pragma aux portENABLE_INTERRUPTS = "sti"; +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +#define portNOP() __asm{ nop } +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/PC/port.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/PC/port.c new file mode 100644 index 0000000..d369787 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/PC/port.c @@ -0,0 +1,303 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V1.00: + + + Call to taskYIELD() from within tick ISR has been replaced by the more + efficient portSWITCH_CONTEXT(). + + ISR function definitions renamed to include the prv prefix. + +Changes from V1.2.0: + + + prvPortResetPIC() is now called last thing before the end of the + preemptive tick routine. + +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. + +Changes from V4.0.1 + + + Add function prvSetTickFrequencyDefault() to set the DOS tick back to + its proper value when the scheduler exits. +*/ + +#include +#include +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the industrial + * PC port. + *----------------------------------------------------------*/ + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_INT_NUMBER 0x08 + +/* Setup hardware for required tick interrupt rate. */ +static void prvSetTickFrequency( uint32_t ulTickRateHz ); + +/* Restore hardware to as it was prior to starting the scheduler. */ +static void prvExitFunction( void ); + +/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC +directly. We chain to the DOS tick as close as possible to the standard DOS +tick rate. */ +static void prvPortResetPIC( void ); + +/* The tick ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if configUSE_PREEMPTION == 1 + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/* Set the tick frequency back so the floppy drive works correctly when the +scheduler exits. */ +static void prvSetTickFrequencyDefault( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */ +static int16_t sDOSTickCounter; + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static int16_t sSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISRPlus1 )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +BaseType_t xPortStartScheduler( void ) +{ +pxISR pxOriginalTickISR; + + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER ); + pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Put the old tick on a different interrupt number so we can + call it when we want. */ + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR ); + + #if configUSE_PREEMPTION == 1 + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + /* Setup a counter that is used to call the DOS interrupt as close + to it's original frequency as can be achieved given our chosen tick + frequency. */ + sDOSTickCounter = portTICKS_PER_DOS_TICK; + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + sSchedulerRunning = pdFALSE; + } + else + { + sSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return sSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The tick ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if configUSE_PREEMPTION == 1 + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + } + + /* Reset the PIC ready for the next time. */ + prvPortResetPIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + xTaskIncrementTick(); + prvPortResetPIC(); + } +#endif +/*-----------------------------------------------------------*/ + + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +static void prvPortResetPIC( void ) +{ + /* We are going to call the DOS tick interrupt at as close a + frequency to the normal DOS tick as possible. */ + + /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */ + --sDOSTickCounter; + if( sDOSTickCounter <= 0 ) + { + sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK; + __asm{ int portSWITCH_INT_NUMBER + 1 }; + } + else + { + /* Reset the PIC as the DOS tick is not being called to + do it. */ + __asm + { + mov al, 20H + out 20H, al + }; + } +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +void ( __interrupt __far *pxOriginalTickISR )(); + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( sSchedulerRunning == pdTRUE ) + { + /* Set the DOS tick back onto the timer ticker. */ + pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR ); + prvSetTickFrequencyDefault(); + + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 ); + } + /* The tick timer is back how DOS wants it. We can re-enable + interrupts without the scheduler being called. */ + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( uint32_t ulTickRateHz ) +{ +const uint16_t usPIT_MODE = ( uint16_t ) 0x43; +const uint16_t usPIT0 = ( uint16_t ) 0x40; +const uint32_t ulPIT_CONST = ( uint32_t ) 1193180; +const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36; +uint32_t ulOutput; + + /* Setup the 8245 to tick at the wanted frequency. */ + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + ulOutput = ulPIT_CONST / ulTickRateHz; + + portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) ); + ulOutput >>= 8; + portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) ); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequencyDefault( void ) +{ +const uint16_t usPIT_MODE = ( uint16_t ) 0x43; +const uint16_t usPIT0 = ( uint16_t ) 0x40; +const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36; + + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + portOUTPUT_BYTE( usPIT0,0 ); + portOUTPUT_BYTE( usPIT0,0 ); +} + + +/*lint +e950 */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/PC/portmacro.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/PC/portmacro.h new file mode 100644 index 0000000..6d45771 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/PC/portmacro.h @@ -0,0 +1,113 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Critical section definitions. portENTER_CRITICAL() must be defined as a +macro for portable.h to work properly. */ +void portLOCAL_ENTER_CRITICAL( void ); +#pragma aux portLOCAL_ENTER_CRITICAL = "pushf" \ + "cli"; +#define portENTER_CRITICAL() portLOCAL_ENTER_CRITICAL() + +void portEXIT_CRITICAL( void ); +#pragma aux portEXIT_CRITICAL = "popf"; + +void portDISABLE_INTERRUPTS( void ); +#pragma aux portDISABLE_INTERRUPTS = "cli"; + +void portENABLE_INTERRUPTS( void ); +#pragma aux portENABLE_INTERRUPTS = "sti"; +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portDOS_TICK_RATE ( 18.20648 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portTICKS_PER_DOS_TICK ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) ) +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +#define portBYTE_ALIGNMENT ( 2 ) +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portNOP() __asm{ nop } +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + + +#endif /* PORTMACRO_H */ + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/common/portasm.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/common/portasm.h new file mode 100644 index 0000000..a834e3b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/common/portasm.h @@ -0,0 +1,111 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portSWITCH_CONTEXT( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +/* There are slightly different versions depending on whether you are building +to include debugger information. If debugger information is used then there +are a couple of extra bytes left of the ISR stack (presumably for use by the +debugger). The true stack pointer is then stored in the bp register. We add +2 to the stack pointer to remove the extra bytes before we restore our context. */ + +#ifdef DEBUG_BUILD + + #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \ + "mov es:0x2[ bx ], ss" \ + "mov es:[ bx ], sp" \ + "call vTaskSwitchContext" /* Perform the switch. */ \ + "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" \ + "mov bp, sp" /* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */ \ + "add bp, 0x0002" + + + + #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" \ + "add sp, 0x0002" /* Remove the extra bytes that exist in debug builds before restoring the context. */ \ + "pop ax" \ + "pop ax" \ + "pop es" \ + "pop ds" \ + "popa" \ + "iret" +#else + + #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \ + "mov es:0x2[ bx ], ss" \ + "mov es:[ bx ], sp" \ + "call vTaskSwitchContext" /* Perform the switch. */ \ + "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" + + + #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" \ + "pop ax" \ + "pop ax" \ + "pop es" \ + "pop ds" \ + "popa" \ + "iret" +#endif + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/common/portcomn.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/common/portcomn.c new file mode 100644 index 0000000..364fd5a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/oWatcom/16BitDOS/common/portcomn.c @@ -0,0 +1,142 @@ +/* + * FreeRTOS Kernel V10.5.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V1.00: + + + pxPortInitialiseStack() now initialises the stack of new tasks to the + same format used by the compiler. This allows the compiler generated + interrupt mechanism to be used for context switches. + +Changes from V2.4.2: + + + pvPortMalloc and vPortFree have been removed. The projects now use + the definitions from the source/portable/MemMang directory. + +Changes from V2.6.1: + + + usPortCheckFreeStackSpace() has been moved to tasks.c. +*/ + + + +#include +#include "FreeRTOS.h" + +/*-----------------------------------------------------------*/ + +/* See header file for description. */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t DS_Reg = 0, *pxOriginalSP; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + *pxTopOfStack = 0x4444; + pxTopOfStack--; + *pxTopOfStack = 0x5555; + pxTopOfStack--; + + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + status register and interrupt return address. We make this the start + of the task. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* We are going to setup the stack for the new task to look like + the stack frame was setup by a compiler generated ISR. We need to know + the address of the existing stack top to place in the SP register within + the stack frame. pxOriginalSP holds SP before (simulated) pusha was + called. */ + pxOriginalSP = pxTopOfStack; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pvParameters ); /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxOriginalSP ); /* SP */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */ + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + pxTopOfStack--; + *pxTopOfStack = DS_Reg; /* DS */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */ + + /* The AX register is pushed again twice - don't know why. */ + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ + + + #ifdef DEBUG_BUILD + /* The compiler adds space to each ISR stack if building to + include debug information. Presumably this is used by the + debugger - we don't need to initialise it to anything just + make sure it is there. */ + pxTopOfStack--; + #endif + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/readme.txt b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/readme.txt new file mode 100644 index 0000000..af93a4b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/portable/readme.txt @@ -0,0 +1,20 @@ +Each real time kernel port consists of three files that contain the core kernel +components and are common to every port, and one or more files that are +specific to a particular microcontroller and/or compiler. + + ++ The FreeRTOS/Source/Portable/MemMang directory contains the five sample +memory allocators as described on the https://www.FreeRTOS.org WEB site. + ++ The other directories each contain files specific to a particular +microcontroller or compiler, where the directory name denotes the compiler +specific files the directory contains. + + + +For example, if you are interested in the [compiler] port for the [architecture] +microcontroller, then the port specific files are contained in +FreeRTOS/Source/Portable/[compiler]/[architecture] directory. If this is the +only port you are interested in then all the other directories can be +ignored. + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/queue.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/queue.c new file mode 100644 index 0000000..03bf21a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/queue.c @@ -0,0 +1,3089 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +#if ( configUSE_CO_ROUTINES == 1 ) + #include "croutine.h" +#endif + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + + +/* Constants used with the cRxLock and cTxLock structure members. */ +#define queueUNLOCKED ( ( int8_t ) -1 ) +#define queueLOCKED_UNMODIFIED ( ( int8_t ) 0 ) +#define queueINT8_MAX ( ( int8_t ) 127 ) + +/* When the Queue_t structure is used to represent a base queue its pcHead and + * pcTail members are used as pointers into the queue storage area. When the + * Queue_t structure is used to represent a mutex pcHead and pcTail pointers are + * not necessary, and the pcHead pointer is set to NULL to indicate that the + * structure instead holds a pointer to the mutex holder (if any). Map alternative + * names to the pcHead and structure member to ensure the readability of the code + * is maintained. The QueuePointers_t and SemaphoreData_t types are used to form + * a union as their usage is mutually exclusive dependent on what the queue is + * being used for. */ +#define uxQueueType pcHead +#define queueQUEUE_IS_MUTEX NULL + +typedef struct QueuePointers +{ + int8_t * pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ + int8_t * pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */ +} QueuePointers_t; + +typedef struct SemaphoreData +{ + TaskHandle_t xMutexHolder; /*< The handle of the task that holds the mutex. */ + UBaseType_t uxRecursiveCallCount; /*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */ +} SemaphoreData_t; + +/* Semaphores do not actually store or copy data, so have an item size of + * zero. */ +#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 ) +#define queueMUTEX_GIVE_BLOCK_TIME ( ( TickType_t ) 0U ) + +#if ( configUSE_PREEMPTION == 0 ) + +/* If the cooperative scheduler is being used then a yield should not be + * performed just because a higher priority task has been woken. */ + #define queueYIELD_IF_USING_PREEMPTION() +#else + #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API() +#endif + +/* + * Definition of the queue used by the scheduler. + * Items are queued by copy, not reference. See the following link for the + * rationale: https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + */ +typedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +{ + int8_t * pcHead; /*< Points to the beginning of the queue storage area. */ + int8_t * pcWriteTo; /*< Points to the free next place in the storage area. */ + + union + { + QueuePointers_t xQueue; /*< Data required exclusively when this structure is used as a queue. */ + SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */ + } u; + + List_t xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ + List_t xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ + + volatile UBaseType_t uxMessagesWaiting; /*< The number of items currently in the queue. */ + UBaseType_t uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ + UBaseType_t uxItemSize; /*< The size of each items that the queue will hold. */ + + volatile int8_t cRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ + volatile int8_t cTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */ + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + struct QueueDefinition * pxQueueSetContainer; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxQueueNumber; + uint8_t ucQueueType; + #endif +} xQUEUE; + +/* The old xQUEUE name is maintained above then typedefed to the new Queue_t + * name below to enable the use of older kernel aware debuggers. */ +typedef xQUEUE Queue_t; + +/*-----------------------------------------------------------*/ + +/* + * The queue registry is just a means for kernel aware debuggers to locate + * queue structures. It has no other purpose so is an optional component. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + +/* The type stored within the queue registry array. This allows a name + * to be assigned to each queue making kernel aware debugging a little + * more user friendly. */ + typedef struct QUEUE_REGISTRY_ITEM + { + const char * pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + QueueHandle_t xHandle; + } xQueueRegistryItem; + +/* The old xQueueRegistryItem name is maintained above then typedefed to the + * new xQueueRegistryItem name below to enable the use of older kernel aware + * debuggers. */ + typedef xQueueRegistryItem QueueRegistryItem_t; + +/* The queue registry is simply an array of QueueRegistryItem_t structures. + * The pcQueueName member of a structure being NULL is indicative of the + * array position being vacant. */ + PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ]; + +#endif /* configQUEUE_REGISTRY_SIZE */ + +/* + * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not + * prevent an ISR from adding or removing items to the queue, but does prevent + * an ISR from removing tasks from the queue event lists. If an ISR finds a + * queue is locked it will instead increment the appropriate queue lock count + * to indicate that a task may require unblocking. When the queue in unlocked + * these lock counts are inspected, and the appropriate action taken. + */ +static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Uses a critical section to determine if there is any data in a queue. + * + * @return pdTRUE if the queue contains no items, otherwise pdFALSE. + */ +static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Uses a critical section to determine if there is any space in a queue. + * + * @return pdTRUE if there is no space, otherwise pdFALSE; + */ +static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Copies an item into the queue, either at the front of the queue or the + * back of the queue. + */ +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, + const void * pvItemToQueue, + const BaseType_t xPosition ) PRIVILEGED_FUNCTION; + +/* + * Copies an item out of a queue. + */ +static void prvCopyDataFromQueue( Queue_t * const pxQueue, + void * const pvBuffer ) PRIVILEGED_FUNCTION; + +#if ( configUSE_QUEUE_SETS == 1 ) + +/* + * Checks to see if a queue is a member of a queue set, and if so, notifies + * the queue set that the queue contains data. + */ + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * Called after a Queue_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ +static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + const uint8_t ucQueueType, + Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION; + +/* + * Mutexes are a special type of queue. When a mutex is created, first the + * queue is created, then prvInitialiseMutex() is called to configure the queue + * as a mutex. + */ +#if ( configUSE_MUTEXES == 1 ) + static void prvInitialiseMutex( Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_MUTEXES == 1 ) + +/* + * If a task waiting for a mutex causes the mutex holder to inherit a + * priority, but the waiting task times out, then the holder should + * disinherit the priority - but only down to the highest priority of any + * other tasks that are waiting for the same mutex. This function returns + * that priority. + */ + static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; +#endif +/*-----------------------------------------------------------*/ + +/* + * Macro to mark a queue as locked. Locking a queue prevents an ISR from + * accessing the queue event lists. + */ +#define prvLockQueue( pxQueue ) \ + taskENTER_CRITICAL(); \ + { \ + if( ( pxQueue )->cRxLock == queueUNLOCKED ) \ + { \ + ( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED; \ + } \ + if( ( pxQueue )->cTxLock == queueUNLOCKED ) \ + { \ + ( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED; \ + } \ + } \ + taskEXIT_CRITICAL() + +/* + * Macro to increment cTxLock member of the queue data structure. It is + * capped at the number of tasks in the system as we cannot unblock more + * tasks than the number of tasks in the system. + */ +#define prvIncrementQueueTxLock( pxQueue, cTxLock ) \ + { \ + const UBaseType_t uxNumberOfTasks = uxTaskGetNumberOfTasks(); \ + if( ( UBaseType_t ) ( cTxLock ) < uxNumberOfTasks ) \ + { \ + configASSERT( ( cTxLock ) != queueINT8_MAX ); \ + ( pxQueue )->cTxLock = ( int8_t ) ( ( cTxLock ) + ( int8_t ) 1 ); \ + } \ + } + +/* + * Macro to increment cRxLock member of the queue data structure. It is + * capped at the number of tasks in the system as we cannot unblock more + * tasks than the number of tasks in the system. + */ +#define prvIncrementQueueRxLock( pxQueue, cRxLock ) \ + { \ + const UBaseType_t uxNumberOfTasks = uxTaskGetNumberOfTasks(); \ + if( ( UBaseType_t ) ( cRxLock ) < uxNumberOfTasks ) \ + { \ + configASSERT( ( cRxLock ) != queueINT8_MAX ); \ + ( pxQueue )->cRxLock = ( int8_t ) ( ( cRxLock ) + ( int8_t ) 1 ); \ + } \ + } +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) +{ + BaseType_t xReturn = pdPASS; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + if( ( pxQueue != NULL ) && + ( pxQueue->uxLength >= 1U ) && + /* Check for multiplication overflow. */ + ( ( SIZE_MAX / pxQueue->uxLength ) >= pxQueue->uxItemSize ) ) + { + taskENTER_CRITICAL(); + { + pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; + pxQueue->pcWriteTo = pxQueue->pcHead; + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + pxQueue->cRxLock = queueUNLOCKED; + pxQueue->cTxLock = queueUNLOCKED; + + if( xNewQueue == pdFALSE ) + { + /* If there are tasks blocked waiting to read from the queue, then + * the tasks will remain blocked as after this function exits the queue + * will still be empty. If there are tasks blocked waiting to write to + * the queue, then one should be unblocked as after this function exits + * it will be possible to write to it. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Ensure the event queues start in the correct state. */ + vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); + vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); + } + } + taskEXIT_CRITICAL(); + } + else + { + xReturn = pdFAIL; + } + + configASSERT( xReturn != pdFAIL ); + + /* A value is returned for calling semantic consistency with previous + * versions. */ + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) + { + Queue_t * pxNewQueue = NULL; + + /* The StaticQueue_t structure and the queue storage area must be + * supplied. */ + configASSERT( pxStaticQueue ); + + if( ( uxQueueLength > ( UBaseType_t ) 0 ) && + ( pxStaticQueue != NULL ) && + + /* A queue storage area should be provided if the item size is not 0, and + * should not be provided if the item size is 0. */ + ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ) && + ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ) ) + { + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticQueue_t or StaticSemaphore_t equals the size of + * the real queue and semaphore structures. */ + volatile size_t xSize = sizeof( StaticQueue_t ); + + /* This assertion cannot be branch covered in unit tests */ + configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */ + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + } + #endif /* configASSERT_DEFINED */ + + /* The address of a statically allocated queue was passed in, use it. + * The address of a statically allocated storage area was also passed in + * but is already set. */ + pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Queues can be allocated wither statically or dynamically, so + * note this queue was allocated statically in case the queue is + * later deleted. */ + pxNewQueue->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + } + else + { + configASSERT( pxNewQueue ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) + { + Queue_t * pxNewQueue = NULL; + size_t xQueueSizeInBytes; + uint8_t * pucQueueStorage; + + if( ( uxQueueLength > ( UBaseType_t ) 0 ) && + /* Check for multiplication overflow. */ + ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) && + /* Check for addition overflow. */ + ( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) ) + { + /* Allocate enough space to hold the maximum number of items that + * can be in the queue at any time. It is valid for uxItemSize to be + * zero in the case the queue is used as a semaphore. */ + xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + /* Allocate the queue and storage area. Justification for MISRA + * deviation as follows: pvPortMalloc() always ensures returned memory + * blocks are aligned per the requirements of the MCU stack. In this case + * pvPortMalloc() must return a pointer that is guaranteed to meet the + * alignment requirements of the Queue_t structure - which in this case + * is an int8_t *. Therefore, whenever the stack alignment requirements + * are greater than or equal to the pointer to char requirements the cast + * is safe. In other cases alignment requirements are not strict (one or + * two bytes). */ + pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ + + if( pxNewQueue != NULL ) + { + /* Jump past the queue structure to find the location of the queue + * storage area. */ + pucQueueStorage = ( uint8_t * ) pxNewQueue; + pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Queues can be created either statically or dynamically, so + * note this task was created dynamically in case it is later + * deleted. */ + pxNewQueue->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + } + else + { + traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + configASSERT( pxNewQueue ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + const uint8_t ucQueueType, + Queue_t * pxNewQueue ) +{ + /* Remove compiler warnings about unused parameters should + * configUSE_TRACE_FACILITY not be set to 1. */ + ( void ) ucQueueType; + + if( uxItemSize == ( UBaseType_t ) 0 ) + { + /* No RAM was allocated for the queue storage area, but PC head cannot + * be set to NULL because NULL is used as a key to say the queue is used as + * a mutex. Therefore just set pcHead to point to the queue as a benign + * value that is known to be within the memory map. */ + pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; + } + else + { + /* Set the head to the start of the queue storage area. */ + pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; + } + + /* Initialise the queue members as described where the queue type is + * defined. */ + pxNewQueue->uxLength = uxQueueLength; + pxNewQueue->uxItemSize = uxItemSize; + ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + pxNewQueue->ucQueueType = ucQueueType; + } + #endif /* configUSE_TRACE_FACILITY */ + + #if ( configUSE_QUEUE_SETS == 1 ) + { + pxNewQueue->pxQueueSetContainer = NULL; + } + #endif /* configUSE_QUEUE_SETS */ + + traceQUEUE_CREATE( pxNewQueue ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + static void prvInitialiseMutex( Queue_t * pxNewQueue ) + { + if( pxNewQueue != NULL ) + { + /* The queue create function will set all the queue structure members + * correctly for a generic queue, but this function is creating a + * mutex. Overwrite those members that need to be set differently - + * in particular the information required for priority inheritance. */ + pxNewQueue->u.xSemaphore.xMutexHolder = NULL; + pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; + + /* In case this is a recursive mutex. */ + pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; + + traceCREATE_MUTEX( pxNewQueue ); + + /* Start with the semaphore in the expected state. */ + ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); + } + else + { + traceCREATE_MUTEX_FAILED(); + } + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) + { + QueueHandle_t xNewQueue; + const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + + xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + + return xNewQueue; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) + { + QueueHandle_t xNewQueue; + const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + + /* Prevent compiler warnings about unused parameters if + * configUSE_TRACE_FACILITY does not equal 1. */ + ( void ) ucQueueType; + + xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + + return xNewQueue; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) + { + TaskHandle_t pxReturn; + Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore; + + configASSERT( xSemaphore ); + + /* This function is called by xSemaphoreGetMutexHolder(), and should not + * be called directly. Note: This is a good way of determining if the + * calling task is the mutex holder, but not a good way of determining the + * identity of the mutex holder, as the holder may change between the + * following critical section exiting and the function returning. */ + taskENTER_CRITICAL(); + { + if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX ) + { + pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder; + } + else + { + pxReturn = NULL; + } + } + taskEXIT_CRITICAL(); + + return pxReturn; + } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */ + +#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) + { + TaskHandle_t pxReturn; + + configASSERT( xSemaphore ); + + /* Mutexes cannot be used in interrupt service routines, so the mutex + * holder should not change in an ISR, and therefore a critical section is + * not required here. */ + if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX ) + { + pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder; + } + else + { + pxReturn = NULL; + } + + return pxReturn; + } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */ + +#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) + { + BaseType_t xReturn; + Queue_t * const pxMutex = ( Queue_t * ) xMutex; + + configASSERT( pxMutex ); + + /* If this is the task that holds the mutex then xMutexHolder will not + * change outside of this task. If this task does not hold the mutex then + * pxMutexHolder can never coincidentally equal the tasks handle, and as + * this is the only condition we are interested in it does not matter if + * pxMutexHolder is accessed simultaneously by another task. Therefore no + * mutual exclusion is required to test the pxMutexHolder variable. */ + if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) + { + traceGIVE_MUTEX_RECURSIVE( pxMutex ); + + /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to + * the task handle, therefore no underflow check is required. Also, + * uxRecursiveCallCount is only modified by the mutex holder, and as + * there can only be one, no mutual exclusion is required to modify the + * uxRecursiveCallCount member. */ + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; + + /* Has the recursive call count unwound to 0? */ + if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) + { + /* Return the mutex. This will automatically unblock any other + * task that might be waiting to access the mutex. */ + ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = pdPASS; + } + else + { + /* The mutex cannot be given because the calling task is not the + * holder. */ + xReturn = pdFAIL; + + traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); + } + + return xReturn; + } + +#endif /* configUSE_RECURSIVE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxMutex = ( Queue_t * ) xMutex; + + configASSERT( pxMutex ); + + /* Comments regarding mutual exclusion as per those within + * xQueueGiveMutexRecursive(). */ + + traceTAKE_MUTEX_RECURSIVE( pxMutex ); + + if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) + { + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; + xReturn = pdPASS; + } + else + { + xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); + + /* pdPASS will only be returned if the mutex was successfully + * obtained. The calling task may have entered the Blocked state + * before reaching here. */ + if( xReturn != pdFAIL ) + { + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; + } + else + { + traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); + } + } + + return xReturn; + } + +#endif /* configUSE_RECURSIVE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) + { + QueueHandle_t xHandle = NULL; + + if( ( uxMaxCount != 0 ) && + ( uxInitialCount <= uxMaxCount ) ) + { + xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); + + if( xHandle != NULL ) + { + ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; + + traceCREATE_COUNTING_SEMAPHORE(); + } + else + { + traceCREATE_COUNTING_SEMAPHORE_FAILED(); + } + } + else + { + configASSERT( xHandle ); + mtCOVERAGE_TEST_MARKER(); + } + + return xHandle; + } + +#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) + { + QueueHandle_t xHandle = NULL; + + if( ( uxMaxCount != 0 ) && + ( uxInitialCount <= uxMaxCount ) ) + { + xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); + + if( xHandle != NULL ) + { + ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; + + traceCREATE_COUNTING_SEMAPHORE(); + } + else + { + traceCREATE_COUNTING_SEMAPHORE_FAILED(); + } + } + else + { + configASSERT( xHandle ); + mtCOVERAGE_TEST_MARKER(); + } + + return xHandle; + } + +#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) +{ + BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to + * allow return statements within the function itself. This is done in the + * interest of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + /* Is there room on the queue now? The running task must be the + * highest priority task wanting to access the queue. If the head item + * in the queue is to be overwritten then it does not matter if the + * queue is full. */ + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + { + traceQUEUE_SEND( pxQueue ); + + #if ( configUSE_QUEUE_SETS == 1 ) + { + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; + + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) ) + { + /* Do not notify the queue set as an existing item + * was overwritten in the queue so the number of items + * in the queue has not changed. */ + mtCOVERAGE_TEST_MARKER(); + } + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting + * to the queue set caused a higher priority task to + * unblock. A context switch is required. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If there was a task waiting for data to arrive on the + * queue then unblock it now. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The unblocked task has a priority higher than + * our own so yield immediately. Yes it is ok to + * do this from within the critical section - the + * kernel takes care of that. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xYieldRequired != pdFALSE ) + { + /* This path is a special case that will only get + * executed if the task was holding multiple mutexes + * and the mutexes were given back in an order that is + * different to that in which they were taken. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + /* If there was a task waiting for data to arrive on the + * queue then unblock it now. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The unblocked task has a priority higher than + * our own so yield immediately. Yes it is ok to do + * this from within the critical section - the kernel + * takes care of that. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xYieldRequired != pdFALSE ) + { + /* This path is a special case that will only get + * executed if the task was holding multiple mutexes and + * the mutexes were given back in an order that is + * different to that in which they were taken. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_QUEUE_SETS */ + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was full and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + + /* Return to the original privilege level before exiting + * the function. */ + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was full and a block time was specified so + * configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_SEND( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); + + /* Unlocking the queue means queue events can effect the + * event list. It is possible that interrupts occurring now + * remove this task from the event list again - but as the + * scheduler is suspended the task will go onto the pending + * ready list instead of the actual ready list. */ + prvUnlockQueue( pxQueue ); + + /* Resuming the scheduler will move tasks from the pending + * ready list into the ready list - so it is feasible that this + * task is already in the ready list before it yields - in which + * case the yield will not cause a context switch unless there + * is also a higher priority task in the pending ready list. */ + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + } + else + { + /* Try again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* The timeout has expired. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, + const void * const pvItemToQueue, + BaseType_t * const pxHigherPriorityTaskWoken, + const BaseType_t xCopyPosition ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + /* Similar to xQueueGenericSend, except without blocking if there is no room + * in the queue. Also don't directly wake a task that was blocked on a queue + * read, instead return a flag to say whether a context switch is required or + * not (i.e. has a task with a higher priority than us been woken by this + * post). */ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + { + const int8_t cTxLock = pxQueue->cTxLock; + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; + + traceQUEUE_SEND_FROM_ISR( pxQueue ); + + /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a + * semaphore or mutex. That means prvCopyDataToQueue() cannot result + * in a task disinheriting a priority and prvCopyDataToQueue() can be + * called here even though the disinherit function does not check if + * the scheduler is suspended before accessing the ready lists. */ + ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + /* The event list is not altered if the queue is locked. This will + * be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + { + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) ) + { + /* Do not notify the queue set as an existing item + * was overwritten in the queue so the number of items + * in the queue has not changed. */ + mtCOVERAGE_TEST_MARKER(); + } + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting + * to the queue set caused a higher priority task to + * unblock. A context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so + * record that a context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Not used in this path. */ + ( void ) uxPreviousMessagesWaiting; + } + #endif /* configUSE_QUEUE_SETS */ + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was posted while it was locked. */ + prvIncrementQueueTxLock( pxQueue, cTxLock ); + } + + xReturn = pdPASS; + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + /* Similar to xQueueGenericSendFromISR() but used with semaphores where the + * item size is 0. Don't directly wake a task that was blocked on a queue + * read, instead return a flag to say whether a context switch is required or + * not (i.e. has a task with a higher priority than us been woken by this + * post). */ + + configASSERT( pxQueue ); + + /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR() + * if the item size is not 0. */ + configASSERT( pxQueue->uxItemSize == 0 ); + + /* Normally a mutex would not be given from an interrupt, especially if + * there is a mutex holder, as priority inheritance makes no sense for an + * interrupts, only tasks. */ + configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* When the queue is used to implement a semaphore no data is ever + * moved through the queue but it is still valid to see if the queue 'has + * space'. */ + if( uxMessagesWaiting < pxQueue->uxLength ) + { + const int8_t cTxLock = pxQueue->cTxLock; + + traceQUEUE_SEND_FROM_ISR( pxQueue ); + + /* A task can only have an inherited priority if it is a mutex + * holder - and if there is a mutex holder then the mutex cannot be + * given from an ISR. As this is the ISR version of the function it + * can be assumed there is no mutex holder and no need to determine if + * priority disinheritance is needed. Simply increase the count of + * messages (semaphores) available. */ + pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + + /* The event list is not altered if the queue is locked. This will + * be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + { + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The semaphore is a member of a queue set, and + * posting to the queue set caused a higher priority + * task to unblock. A context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so + * record that a context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_QUEUE_SETS */ + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was posted while it was locked. */ + prvIncrementQueueTxLock( pxQueue, cTxLock ); + } + + xReturn = pdPASS; + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + /* Check the pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* The buffer into which data is received can only be NULL if the data size + * is zero (so no data is copied into the buffer). */ + configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to + * allow return statements within the function itself. This is done in the + * interest of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Data available, remove one item. */ + prvCopyDataFromQueue( pxQueue, pvBuffer ); + traceQUEUE_RECEIVE( pxQueue ); + pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + + /* There is now space in the queue, were any tasks waiting to + * post to the queue? If so, unblock the highest priority waiting + * task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was empty and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was empty and a block time was specified so + * configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* The timeout has not expired. If the queue is still empty place + * the task on the list of tasks waiting to receive from the queue. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* The queue contains data again. Loop back to try and read the + * data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* Timed out. If there is no data in the queue exit, otherwise loop + * back and attempt to read the data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + void *pvBuffer = NULL; + (void)pvBuffer; + + #if ( configUSE_MUTEXES == 1 ) + BaseType_t xInheritanceOccurred = pdFALSE; + #endif + + /* Check the queue pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* Check this really is a semaphore, in which case the item size will be + * 0. */ + configASSERT( pxQueue->uxItemSize == 0 ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to allow return + * statements within the function itself. This is done in the interest + * of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + /* Semaphores are queues with an item size of 0, and where the + * number of messages in the queue is the semaphore's count value. */ + const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxSemaphoreCount > ( UBaseType_t ) 0 ) + { + traceQUEUE_RECEIVE( pxQueue ); + + /* Semaphores are queues with a data size of zero and where the + * messages waiting is the semaphore's count. Reduce the count. */ + pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + /* Record the information required to implement + * priority inheritance should it become necessary. */ + pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_MUTEXES */ + + /* Check to see if other tasks are blocked waiting to give the + * semaphore, and if so, unblock the highest priority such task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The semaphore count was 0 and no block time is specified + * (or the block time has expired) so exit now. */ + taskEXIT_CRITICAL(); + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The semaphore count was 0 and a block time was specified + * so configure the timeout structure ready to block. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can give to and take from the semaphore + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* A block time is specified and not expired. If the semaphore + * count is 0 then enter the Blocked state to wait for a semaphore to + * become available. As semaphores are implemented with queues the + * queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + taskENTER_CRITICAL(); + { + xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); + } + taskEXIT_CRITICAL(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( configUSE_MUTEXES == 1 ) */ + + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* There was no timeout and the semaphore count was not 0, so + * attempt to take the semaphore again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* Timed out. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + /* If the semaphore count is 0 exit now as the timeout has + * expired. Otherwise return to attempt to take the semaphore that is + * known to be available. As semaphores are implemented by queues the + * queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + #if ( configUSE_MUTEXES == 1 ) + { + /* xInheritanceOccurred could only have be set if + * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to + * test the mutex type again to check it is actually a mutex. */ + if( xInheritanceOccurred != pdFALSE ) + { + taskENTER_CRITICAL(); + { + UBaseType_t uxHighestWaitingPriority; + + /* This task blocking on the mutex caused another + * task to inherit this task's priority. Now this task + * has timed out the priority should be disinherited + * again, but only as low as the next highest priority + * task that is waiting for the same mutex. */ + uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); + vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); + } + taskEXIT_CRITICAL(); + } + } + #endif /* configUSE_MUTEXES */ + + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + int8_t * pcOriginalReadPosition; + Queue_t * const pxQueue = xQueue; + + /* Check the pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* The buffer into which data is received can only be NULL if the data size + * is zero (so no data is copied into the buffer. */ + configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to + * allow return statements within the function itself. This is done in the + * interest of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Remember the read position so it can be reset after the data + * is read from the queue as this function is only peeking the + * data, not removing it. */ + pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom; + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + traceQUEUE_PEEK( pxQueue ); + + /* The data is not being removed, so reset the read pointer. */ + pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition; + + /* The data is being left in the queue, so see if there are + * any other tasks waiting for the data. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority than this task. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was empty and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + traceQUEUE_PEEK_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was empty and a block time was specified so + * configure the timeout structure ready to enter the blocked + * state. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now that the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* Timeout has not expired yet, check to see if there is data in the + * queue now, and if not enter the Blocked state to wait for data. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_PEEK( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* There is data in the queue now, so don't enter the blocked + * state, instead return to try and obtain the data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* The timeout has expired. If there is still no data in the queue + * exit, otherwise go back and try to read the data again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceQUEUE_PEEK_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, + void * const pvBuffer, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Cannot block in an ISR, so check there is data available. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + const int8_t cRxLock = pxQueue->cRxLock; + + traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + + /* If the queue is locked the event list will not be modified. + * Instead update the lock count so the task that unlocks the queue + * will know that an ISR has removed data while the queue was + * locked. */ + if( cRxLock == queueUNLOCKED ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + /* The task waiting has a higher priority than us so + * force a context switch. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was removed while it was locked. */ + prvIncrementQueueRxLock( pxQueue, cRxLock ); + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, + void * const pvBuffer ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + int8_t * pcOriginalReadPosition; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */ + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Cannot block in an ISR, so check there is data available. */ + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + traceQUEUE_PEEK_FROM_ISR( pxQueue ); + + /* Remember the read position so it can be reset as nothing is + * actually being removed from the queue. */ + pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom; + prvCopyDataFromQueue( pxQueue, pvBuffer ); + pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition; + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + + configASSERT( xQueue ); + + taskENTER_CRITICAL(); + { + uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + taskENTER_CRITICAL(); + { + uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + uxReturn = pxQueue->uxMessagesWaiting; + + return uxReturn; +} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +/*-----------------------------------------------------------*/ + +void vQueueDelete( QueueHandle_t xQueue ) +{ + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + traceQUEUE_DELETE( pxQueue ); + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + vQueueUnregisterQueue( pxQueue ); + } + #endif + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The queue can only have been allocated dynamically - free it + * again. */ + vPortFree( pxQueue ); + } + #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The queue could have been allocated statically or dynamically, so + * check before attempting to free the memory. */ + if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxQueue ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #else /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) */ + { + /* The queue must have been statically allocated, so is not going to be + * deleted. Avoid compiler warnings about the unused parameter. */ + ( void ) pxQueue; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) + { + return ( ( Queue_t * ) xQueue )->uxQueueNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) + { + ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) + { + return ( ( Queue_t * ) xQueue )->ucQueueType; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) + { + UBaseType_t uxHighestPriorityOfWaitingTasks; + + /* If a task waiting for a mutex causes the mutex holder to inherit a + * priority, but the waiting task times out, then the holder should + * disinherit the priority - but only down to the highest priority of any + * other tasks that are waiting for the same mutex. For this purpose, + * return the priority of the highest priority task that is waiting for the + * mutex. */ + if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) + { + uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); + } + else + { + uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; + } + + return uxHighestPriorityOfWaitingTasks; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, + const void * pvItemToQueue, + const BaseType_t xPosition ) +{ + BaseType_t xReturn = pdFALSE; + UBaseType_t uxMessagesWaiting; + + /* This function is called from a critical section. */ + + uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) + { + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + /* The mutex is no longer being held. */ + xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); + pxQueue->u.xSemaphore.xMutexHolder = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_MUTEXES */ + } + else if( xPosition == queueSEND_TO_BACK ) + { + ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + + if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + { + pxQueue->pcWriteTo = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ + pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + { + pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xPosition == queueOVERWRITE ) + { + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* An item is not being added but overwritten, so subtract + * one from the recorded number of items in the queue so when + * one is added again below the number of recorded items remains + * correct. */ + --uxMessagesWaiting; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvCopyDataFromQueue( Queue_t * const pxQueue, + void * const pvBuffer ) +{ + if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) + { + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvUnlockQueue( Queue_t * const pxQueue ) +{ + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* The lock counts contains the number of extra data items placed or + * removed from the queue while the queue was locked. When a queue is + * locked items can be added or removed, but the event lists cannot be + * updated. */ + taskENTER_CRITICAL(); + { + int8_t cTxLock = pxQueue->cTxLock; + + /* See if data was added to the queue while it was locked. */ + while( cTxLock > queueLOCKED_UNMODIFIED ) + { + /* Data was posted while the queue was locked. Are any tasks + * blocked waiting for data to become available? */ + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting to + * the queue set caused a higher priority task to unblock. + * A context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Tasks that are removed from the event list will get + * added to the pending ready list as the scheduler is still + * suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + break; + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + /* Tasks that are removed from the event list will get added to + * the pending ready list as the scheduler is still suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that + * a context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + break; + } + } + #endif /* configUSE_QUEUE_SETS */ + + --cTxLock; + } + + pxQueue->cTxLock = queueUNLOCKED; + } + taskEXIT_CRITICAL(); + + /* Do the same for the Rx lock. */ + taskENTER_CRITICAL(); + { + int8_t cRxLock = pxQueue->cRxLock; + + while( cRxLock > queueLOCKED_UNMODIFIED ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --cRxLock; + } + else + { + break; + } + } + + pxQueue->cRxLock = queueUNLOCKED; + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) +{ + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) +{ + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) +{ + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) +{ + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRSend( QueueHandle_t xQueue, + const void * pvItemToQueue, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + /* If the queue is already full we may have to block. A critical section + * is required to prevent an interrupt removing something from the queue + * between the check to see if the queue is full and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + { + /* The queue is full - do we want to block or just leave without + * posting? */ + if( xTicksToWait > ( TickType_t ) 0 ) + { + /* As this is called from a coroutine we cannot block directly, but + * return indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + } + portENABLE_INTERRUPTS(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + /* There is room in the queue, copy the data into the queue. */ + prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); + xReturn = pdPASS; + + /* Were any co-routines waiting for data to become available? */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + /* In this instance the co-routine could be placed directly + * into the ready list as we are within a critical section. + * Instead the same pending ready list mechanism is used as if + * the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The co-routine waiting has a higher priority so record + * that a yield might be appropriate. */ + xReturn = errQUEUE_YIELD; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xReturn = errQUEUE_FULL; + } + } + portENABLE_INTERRUPTS(); + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRReceive( QueueHandle_t xQueue, + void * pvBuffer, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + /* If the queue is already empty we may have to block. A critical section + * is required to prevent an interrupt adding something to the queue + * between the check to see if the queue is empty and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + /* There are no messages in the queue, do we want to block or just + * leave with nothing? */ + if( xTicksToWait > ( TickType_t ) 0 ) + { + /* As this is a co-routine we cannot block directly, but return + * indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + portENABLE_INTERRUPTS(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Data is available from the queue. */ + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --( pxQueue->uxMessagesWaiting ); + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + xReturn = pdPASS; + + /* Were any co-routines waiting for space to become available? */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + /* In this instance the co-routine could be placed directly + * into the ready list as we are within a critical section. + * Instead the same pending ready list mechanism is used as if + * the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + xReturn = errQUEUE_YIELD; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xReturn = pdFAIL; + } + } + portENABLE_INTERRUPTS(); + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, + const void * pvItemToQueue, + BaseType_t xCoRoutinePreviouslyWoken ) + { + Queue_t * const pxQueue = xQueue; + + /* Cannot block within an ISR so if there is no space on the queue then + * exit without doing anything. */ + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); + + /* We only want to wake one co-routine per ISR, so check that a + * co-routine has not already been woken. */ + if( xCoRoutinePreviouslyWoken == pdFALSE ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + return pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xCoRoutinePreviouslyWoken; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, + void * pvBuffer, + BaseType_t * pxCoRoutineWoken ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + /* We cannot block from an ISR, so check there is data available. If + * not then just leave without doing anything. */ + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Copy the data from the queue. */ + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --( pxQueue->uxMessagesWaiting ); + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + if( ( *pxCoRoutineWoken ) == pdFALSE ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + *pxCoRoutineWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + UBaseType_t ux; + QueueRegistryItem_t * pxEntryToWrite = NULL; + + configASSERT( xQueue ); + + if( pcQueueName != NULL ) + { + /* See if there is an empty space in the registry. A NULL name denotes + * a free slot. */ + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + /* Replace an existing entry if the queue is already in the registry. */ + if( xQueue == xQueueRegistry[ ux ].xHandle ) + { + pxEntryToWrite = &( xQueueRegistry[ ux ] ); + break; + } + /* Otherwise, store in the next empty location */ + else if( ( pxEntryToWrite == NULL ) && ( xQueueRegistry[ ux ].pcQueueName == NULL ) ) + { + pxEntryToWrite = &( xQueueRegistry[ ux ] ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + + if( pxEntryToWrite != NULL ) + { + /* Store the information on this queue. */ + pxEntryToWrite->pcQueueName = pcQueueName; + pxEntryToWrite->xHandle = xQueue; + + traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); + } + } + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + UBaseType_t ux; + const char * pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + + configASSERT( xQueue ); + + /* Note there is nothing here to protect against another task adding or + * removing entries from the registry while it is being searched. */ + + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + if( xQueueRegistry[ ux ].xHandle == xQueue ) + { + pcReturn = xQueueRegistry[ ux ].pcQueueName; + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return pcReturn; + } /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */ + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void vQueueUnregisterQueue( QueueHandle_t xQueue ) + { + UBaseType_t ux; + + configASSERT( xQueue ); + + /* See if the handle of the queue being unregistered in actually in the + * registry. */ + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + if( xQueueRegistry[ ux ].xHandle == xQueue ) + { + /* Set the name to NULL to show that this slot if free again. */ + xQueueRegistry[ ux ].pcQueueName = NULL; + + /* Set the handle to NULL to ensure the same queue handle cannot + * appear in the registry twice if it is added, removed, then + * added again. */ + xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0; + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + + void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) + { + Queue_t * const pxQueue = xQueue; + + /* This function should not be called by application code hence the + * 'Restricted' in its name. It is not part of the public API. It is + * designed for use by kernel code, and has special calling requirements. + * It can result in vListInsert() being called on a list that can only + * possibly ever have one item in it, so the list will be fast, but even + * so it should be called with the scheduler locked and not from a critical + * section. */ + + /* Only do anything if there are no messages in the queue. This function + * will not actually cause the task to block, just place it on a blocked + * list. It will not block until the scheduler is unlocked - at which + * time a yield will be performed. If an item is added to the queue while + * the queue is locked, and the calling task blocks on the queue, then the + * calling task will be immediately unblocked when the queue is unlocked. */ + prvLockQueue( pxQueue ); + + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) + { + /* There is nothing in the queue, block for the specified period. */ + vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvUnlockQueue( pxQueue ); + } + +#endif /* configUSE_TIMERS */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) + { + QueueSetHandle_t pxQueue; + + pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET ); + + return pxQueue; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) + { + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL ) + { + /* Cannot add a queue/semaphore to more than one queue set. */ + xReturn = pdFAIL; + } + else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 ) + { + /* Cannot add a queue/semaphore to a queue set if there are already + * items in the queue/semaphore. */ + xReturn = pdFAIL; + } + else + { + ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet; + xReturn = pdPASS; + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) + { + BaseType_t xReturn; + Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore; + + if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet ) + { + /* The queue was not a member of the set. */ + xReturn = pdFAIL; + } + else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 ) + { + /* It is dangerous to remove a queue from a set when the queue is + * not empty because the queue set will still hold pending events for + * the queue. */ + xReturn = pdFAIL; + } + else + { + taskENTER_CRITICAL(); + { + /* The queue is no longer contained in the set. */ + pxQueueOrSemaphore->pxQueueSetContainer = NULL; + } + taskEXIT_CRITICAL(); + xReturn = pdPASS; + } + + return xReturn; + } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */ + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + TickType_t const xTicksToWait ) + { + QueueSetMemberHandle_t xReturn = NULL; + + ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */ + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) + { + QueueSetMemberHandle_t xReturn = NULL; + + ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */ + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) + { + Queue_t * pxQueueSetContainer = pxQueue->pxQueueSetContainer; + BaseType_t xReturn = pdFALSE; + + /* This function must be called form a critical section. */ + + /* The following line is not reachable in unit tests because every call + * to prvNotifyQueueSetContainer is preceded by a check that + * pxQueueSetContainer != NULL */ + configASSERT( pxQueueSetContainer ); /* LCOV_EXCL_BR_LINE */ + configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength ); + + if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength ) + { + const int8_t cTxLock = pxQueueSetContainer->cTxLock; + + traceQUEUE_SET_SEND( pxQueueSetContainer ); + + /* The data copied is the handle of the queue that contains data. */ + xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK ); + + if( cTxLock == queueUNLOCKED ) + { + if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority. */ + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + prvIncrementQueueTxLock( pxQueueSetContainer, cTxLock ); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/sbom.spdx b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/sbom.spdx new file mode 100644 index 0000000..dd23423 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/sbom.spdx @@ -0,0 +1,1561 @@ +SPDXVersion: SPDX-2.2 +DataLicense: CC0-1.0 +SPDXID: SPDXRef-DOCUMENT +DocumentName: FreeRTOS-Kernel +DocumentNamespace: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/v10.5.1/sbom.spdx +Creator: Amazon Web Services +Created: 2022-11-15T20:10:07Z +CreatorComment: NOASSERTION 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b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/set.middleware.freertos-kernel.yml new file mode 100644 index 0000000..b0b2af0 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/set.middleware.freertos-kernel.yml @@ -0,0 +1,1032 @@ +--- +container.freertos-kernel.armv8m: + section-type: container + contents: + repo_base_path: rtos/freertos/freertos-kernel + files: + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/copy_files.py + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/port.c + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portasm.h + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/portmacrocommon.h + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/non_secure/ReadMe.txt + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/ReadMe.txt + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/secure_context.c + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/secure/context/secure_context.h + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/secure/heap/secure_heap.c + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/secure/heap/secure_heap.h + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/secure/init/secure_init.c + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/secure/init/secure_init.h + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/secure/macros/secure_port_macros.h + - source: rtos/freertos/freertos-kernel/portable/ARMv8M/secure/ReadMe.txt + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel +container.freertos-kernel.doc: + section-type: container + contents: + repo_base_path: rtos/freertos/freertos-kernel + files: + - source: rtos/freertos/freertos-kernel/ChangeLogKSDK.txt + - source: rtos/freertos/freertos-kernel/CMakeLists.txt + - source: rtos/freertos/freertos-kernel/GitHub-FreeRTOS-Kernel-Home.url + - source: rtos/freertos/freertos-kernel/History.txt + - source: rtos/freertos/freertos-kernel/LICENSE.md + - source: rtos/freertos/freertos-kernel/manifest.yml + - source: rtos/freertos/freertos-kernel/portable/CMakeLists.txt + - source: rtos/freertos/freertos-kernel/portable/ARMClang/Use-the-GCC-ports.txt + - source: rtos/freertos/freertos-kernel/Quick_Start_Guide.url + - source: rtos/freertos/freertos-kernel/README.md + - source: rtos/freertos/freertos-kernel/sbom.spdx + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel +middleware.freertos-kernel.extension: + section-type: component + contents: + repo_base_path: rtos/freertos/freertos-kernel + project_base_path: freertos/freertos-kernel + cc-include: + - repo_relative_path: include + project_relative_path: include + package_relative_path: include + files: + - source: rtos/freertos/freertos-kernel/include/freertos_tasks_c_additions.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/middleware_freertos-kernel_extension.cmake + type: workspace + toolchains: armgcc + hidden: true + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel + section_info: + type: other + full_name: FreeRTOS NXP extension + description: FreeRTOS NXP extension + version: 10.5.1 + vendor: NXP + user_visible: never + taxonomy: + cclass: RTOS + cgroup: TAD extension + cbundle: FreeRTOS NXP + cbundle_version: 1.0.0 + display_name: FreeRTOS NXP extension + meta-name: middleware.freertos-kernel.extension + cmake_module_name: middleware_freertos-kernel_extension +middleware.freertos-kernel.template: + section-type: component + contents: + repo_base_path: rtos/freertos/freertos-kernel + project_base_path: freertos/freertos-kernel + cc-include: + - repo_relative_path: template/ARM_CM0 + cores: cm0p + project_relative_path: "../../source" + target_file: + - FreeRTOSConfig.h + package_relative_path: template/ARM_CM0 + - repo_relative_path: template/ARM_CM33_3_priority_bits + cores: cm33 + fpu: NO_FPU SP_FPU + device_ids: LPC5502 LPC5504 LPC5506 LPC5512 LPC5514 LPC5516 LPC5526 LPC5528 + LPC5534 LPC5536 LPC55S04 LPC55S06 LPC55S14 LPC55S16 LPC55S26 LPC55S28 LPC55S36 + LPC55S66 LPC55S69 MIMX8UD3xxx08 MIMX8UD5xxx08 MIMX8US3xxx08 MIMX8US5xxx08 + MIMXRT533S MIMXRT555S MIMXRT595S MIMXRT633S MIMXRT685S + project_relative_path: "../../source" + target_file: + - FreeRTOSConfig.h + package_relative_path: template/ARM_CM33_3_priority_bits + - repo_relative_path: template/ARM_CM4F_3_priority_bits + cores: cm4f + device_ids: LPC54005 LPC54016 LPC54018 LPC54018J2M LPC54018J4M LPC54605J512 + LPC54605J256 LPC54606J512 LPC54606J256 LPC54607J256 LPC54607J512 LPC54608J512 + LPC54616J512 LPC54616J256 LPC54618J512 LPC54628J512 LPC54S005 LPC54S016 LPC54S018 + LPC54S018J2M LPC54S018J4M + project_relative_path: "../../source" + target_file: + - FreeRTOSConfig.h + package_relative_path: template/ARM_CM4F_3_priority_bits + - repo_relative_path: template/ARM_CM4F_4_priority_bits + cores: cm4f cm7f + device_ids: K32L3A60xxx MCIMX7U3xxxxx MCIMX7U5xxxxx MIMX8MD6xxxJZ MIMX8MD6xxxHZ + MIMX8MD7xxxJZ MIMX8MD7xxxHZ MIMX8MM1xxxLZ MIMX8MM1xxxKZ MIMX8MM2xxxLZ MIMX8MM2xxxKZ + MIMX8MM3xxxLZ MIMX8MM3xxxKZ MIMX8MM4xxxLZ MIMX8MM4xxxKZ MIMX8MM5xxxLZ MIMX8MM5xxxKZ + MIMX8MM6xxxLZ MIMX8MM6xxxKZ MIMX8MQ5xxxJZ MIMX8MQ5xxxHZ MIMX8MQ6xxxJZ MIMX8MQ6xxxHZ + MIMX8MQ7xxxJZ MIMX8MQ7xxxHZ MIMXRT1165xxxxx MIMXRT1166xxxxx MIMXRT1173xxxxx + MIMXRT1175xxxxx MIMXRT1176xxxxx MK02FN128xxx10 MK02FN64xxx10 MK22FN128xxx12 + MK22FN256xxx12 MK22FN512xxx12 MIMX8ML3xxxLZ MIMX8ML3xxxKZ MIMX8ML4xxxLZ MIMX8ML4xxxKZ + MIMX8ML6xxxLZ MIMX8ML6xxxKZ MIMX8ML8xxxLZ MIMX8ML8xxxKZ MIMX8MN1xxxJZ MIMX8MN1xxxIZ + MIMX8MN2xxxJZ MIMX8MN2xxxIZ MIMX8MN3xxxJZ MIMX8MN3xxxIZ MIMX8MN4xxxJZ MIMX8MN4xxxIZ + MIMX8MN5xxxJZ MIMX8MN5xxxIZ MIMX8MN6xxxJZ MIMX8MN6xxxIZ MIMXRT1011xxxxx MIMXRT1015xxxxx + MIMXRT1021xxxxx MIMXRT1024xxxxx MIMXRT1041xxxxB MIMXRT1042xxxxB MIMXRT1051xxxxB + MIMXRT1052xxxxB MIMXRT1061xxxxA MIMXRT1061xxxxB MIMXRT1062xxxxA MIMXRT1062xxxxB + MIMXRT1064xxxxA MIMXRT1171xxxxx MIMXRT1172xxxxx + project_relative_path: "../../source" + target_file: + - FreeRTOSConfig.h + package_relative_path: template/ARM_CM4F_4_priority_bits + files: + - source: rtos/freertos/freertos-kernel/template/ARM_CM0/FreeRTOSConfig.h + cores: cm0p + project_relative_path: "../../source" + repo_relative_path: template/ARM_CM0 + package_relative_path: template/ARM_CM0 + type: c_include + config: true + - source: rtos/freertos/freertos-kernel/template/ARM_CM33_3_priority_bits/FreeRTOSConfig.h + cores: cm33 + fpu: NO_FPU SP_FPU + device_ids: LPC5502 LPC5504 LPC5506 LPC5512 LPC5514 LPC5516 LPC5526 LPC5528 + LPC5534 LPC5536 LPC55S04 LPC55S06 LPC55S14 LPC55S16 LPC55S26 LPC55S28 LPC55S36 + LPC55S66 LPC55S69 MIMX8UD3xxx08 MIMX8UD5xxx08 MIMX8US3xxx08 MIMX8US5xxx08 + MIMXRT533S MIMXRT555S MIMXRT595S MIMXRT633S MIMXRT685S + project_relative_path: "../../source" + repo_relative_path: template/ARM_CM33_3_priority_bits + package_relative_path: template/ARM_CM33_3_priority_bits + type: c_include + config: true + - source: rtos/freertos/freertos-kernel/template/ARM_CM4F_3_priority_bits/FreeRTOSConfig.h + cores: cm4f + device_ids: LPC54005 LPC54016 LPC54018 LPC54018J2M LPC54018J4M LPC54605J512 + LPC54605J256 LPC54606J512 LPC54606J256 LPC54607J256 LPC54607J512 LPC54608J512 + LPC54616J512 LPC54616J256 LPC54618J512 LPC54628J512 LPC54S005 LPC54S016 LPC54S018 + LPC54S018J2M LPC54S018J4M + project_relative_path: "../../source" + repo_relative_path: template/ARM_CM4F_3_priority_bits + package_relative_path: template/ARM_CM4F_3_priority_bits + type: c_include + config: true + - source: rtos/freertos/freertos-kernel/template/ARM_CM4F_4_priority_bits/FreeRTOSConfig.h + cores: cm4f cm7f + device_ids: K32L3A60xxx MCIMX7U3xxxxx MCIMX7U5xxxxx MIMX8MD6xxxJZ MIMX8MD6xxxHZ + MIMX8MD7xxxJZ MIMX8MD7xxxHZ MIMX8MM1xxxLZ MIMX8MM1xxxKZ MIMX8MM2xxxLZ MIMX8MM2xxxKZ + MIMX8MM3xxxLZ MIMX8MM3xxxKZ MIMX8MM4xxxLZ MIMX8MM4xxxKZ MIMX8MM5xxxLZ MIMX8MM5xxxKZ + MIMX8MM6xxxLZ MIMX8MM6xxxKZ MIMX8MQ5xxxJZ MIMX8MQ5xxxHZ MIMX8MQ6xxxJZ MIMX8MQ6xxxHZ + MIMX8MQ7xxxJZ MIMX8MQ7xxxHZ MIMXRT1165xxxxx MIMXRT1166xxxxx MIMXRT1173xxxxx + MIMXRT1175xxxxx MIMXRT1176xxxxx MK02FN128xxx10 MK02FN64xxx10 MK22FN128xxx12 + MK22FN256xxx12 MK22FN512xxx12 MIMX8ML3xxxLZ MIMX8ML3xxxKZ MIMX8ML4xxxLZ MIMX8ML4xxxKZ + MIMX8ML6xxxLZ MIMX8ML6xxxKZ MIMX8ML8xxxLZ MIMX8ML8xxxKZ MIMX8MN1xxxJZ MIMX8MN1xxxIZ + MIMX8MN2xxxJZ MIMX8MN2xxxIZ MIMX8MN3xxxJZ MIMX8MN3xxxIZ MIMX8MN4xxxJZ MIMX8MN4xxxIZ + MIMX8MN5xxxJZ MIMX8MN5xxxIZ MIMX8MN6xxxJZ MIMX8MN6xxxIZ MIMXRT1011xxxxx MIMXRT1015xxxxx + MIMXRT1021xxxxx MIMXRT1024xxxxx MIMXRT1041xxxxB MIMXRT1042xxxxB MIMXRT1051xxxxB + MIMXRT1052xxxxB MIMXRT1061xxxxA MIMXRT1061xxxxB MIMXRT1062xxxxA MIMXRT1062xxxxB + MIMXRT1064xxxxA MIMXRT1171xxxxx MIMXRT1172xxxxx + project_relative_path: "../../source" + repo_relative_path: template/ARM_CM4F_4_priority_bits + package_relative_path: template/ARM_CM4F_4_priority_bits + type: c_include + config: true + - source: rtos/freertos/freertos-kernel/middleware_freertos-kernel_template.cmake + type: workspace + toolchains: armgcc + hidden: true + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel + section_info: + type: project_template + full_name: FreeRTOS configuration template + description: Template configuration file to be edited by user. Provides also memory + allocator (heap_x), change variant if needed. + version: 10.5.1 + vendor: NXP + user_visible: never + taxonomy: + cclass: RTOS + cgroup: freertos template + cbundle: FreeRTOS NXP + cbundle_version: 1.0.0 + display_name: FreeRTOS configuration template + meta-name: middleware.freertos-kernel.template + cmake_module_name: middleware_freertos-kernel_template +set.middleware.freertos-kernel: + section-type: set + belong_to: set.middleware.freertos-kernel + section_info: + fixed_id: amazon_freertos_kernel + version: 10.5.1 + display_name: FreeRTOS + description: Real-time operating system for microcontrollers from Amazon + set_location: + repo_base_path: rtos/freertos/freertos-kernel + type: middleware + vendor: NXP + product: + kex_package: + scr: + - scr.freertos-kernel + kex_web_ui: + ui_control: true + ui_release_specific: true + ui_control_default: false + ui_category: Operating System + cmsis_pack: + scr: + - scr.freertos-kernel + vendor: NXP + supported: true + pack_root: + pack_type: SWP + pack_name: FREERTOS-KERNEL + pack_version: 1.0.0 +scr.freertos-kernel: + section-type: scr + belong_to: set.middleware.freertos-kernel + contents: + Name: FreeRTOS kernel + Version: 10.5.1 + license: + - license.amazon_mit + Format: source code + Description: Open source RTOS kernel for small devices + Location: rtos/freertos/freertos-kernel + Origin: Amazon (MIT) + Url: https://github.com/FreeRTOS/FreeRTOS-Kernel +license.segger_sysview: + section-type: license + contents: + repo_base_path: boards//freertos_examples/visualization/freertos_segger_sysview + files: + - source: boards//freertos_examples/visualization/freertos_segger_sysview/LICENSE + package_base_path: boards//freertos_examples/visualization/freertos_segger_sysview + belong_to: set.middleware.freertos-kernel + section_info: + click_through: false + Outgoing License: BSD-1-Clause +scr.segger_sysview: + section-type: scr + belong_to: set.middleware.freertos-kernel + contents: + Name: Segger SystemView Demo + Version: '3.30' + license: + - license.segger_sysview + Format: source code + Description: Segger SystemView demo + Location: boards//freertos_examples/visualization/freertos_segger_sysview + Origin: Segger (BSD-1-Clause) + Url: https://www.segger.com/products/development-tools/systemview/ +middleware.freertos-kernel: + section-type: component + contents: + repo_base_path: rtos/freertos/freertos-kernel + project_base_path: freertos/freertos-kernel + cc-include: + - repo_relative_path: include + project_relative_path: include + package_relative_path: include + - compilers: gcc + cores: cm0p + repo_relative_path: portable/GCC/ARM_CM0 + toolchains: armgcc mcux + project_relative_path: portable/GCC/ARM_CM0 + package_relative_path: portable/GCC/ARM_CM0 + - compilers: gcc + cores: cm4f cm7f + repo_relative_path: portable/GCC/ARM_CM4F + toolchains: armgcc mcux + project_relative_path: portable/GCC/ARM_CM4F + package_relative_path: portable/GCC/ARM_CM4F + files: + - source: rtos/freertos/freertos-kernel/croutine.c + repo_relative_path: "./" + project_relative_path: "./" + package_relative_path: "./" + type: src + - source: rtos/freertos/freertos-kernel/event_groups.c + repo_relative_path: "./" + project_relative_path: "./" + package_relative_path: "./" + type: src + - source: rtos/freertos/freertos-kernel/include/atomic.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/croutine.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/deprecated_definitions.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/event_groups.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/FreeRTOS.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/list.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/message_buffer.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/mpu_prototypes.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/mpu_wrappers.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/portable.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/projdefs.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/queue.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/semphr.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/stack_macros.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/StackMacros.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/stdint.readme + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: doc + - source: rtos/freertos/freertos-kernel/include/stream_buffer.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/task.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/include/timers.h + repo_relative_path: include + project_relative_path: include + package_relative_path: include + type: c_include + - source: rtos/freertos/freertos-kernel/list.c + repo_relative_path: "./" + project_relative_path: "./" + package_relative_path: "./" + type: src + - compilers: gcc + cores: cm0p + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM0/port.c + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM0 + project_relative_path: portable/GCC/ARM_CM0 + package_relative_path: portable/GCC/ARM_CM0 + type: src + - compilers: gcc + cores: cm0p + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM0/portmacro.h + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM0 + project_relative_path: portable/GCC/ARM_CM0 + package_relative_path: portable/GCC/ARM_CM0 + type: c_include + - compilers: gcc + cores: cm4f cm7f + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4F/port.c + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM4F + project_relative_path: portable/GCC/ARM_CM4F + package_relative_path: portable/GCC/ARM_CM4F + type: src + - compilers: gcc + cores: cm4f cm7f + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM4F/portmacro.h + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM4F + project_relative_path: portable/GCC/ARM_CM4F + package_relative_path: portable/GCC/ARM_CM4F + type: c_include + - source: rtos/freertos/freertos-kernel/portable/MemMang/ReadMe.url + repo_relative_path: portable/MemMang + project_relative_path: portable/MemMang + package_relative_path: portable/MemMang + type: other + - source: rtos/freertos/freertos-kernel/portable/readme.txt + repo_relative_path: portable + project_relative_path: portable + package_relative_path: portable + type: doc + - source: rtos/freertos/freertos-kernel/queue.c + repo_relative_path: "./" + project_relative_path: "./" + package_relative_path: "./" + type: src + - source: rtos/freertos/freertos-kernel/stream_buffer.c + repo_relative_path: "./" + project_relative_path: "./" + package_relative_path: "./" + type: src + - source: rtos/freertos/freertos-kernel/tasks.c + repo_relative_path: "./" + project_relative_path: "./" + package_relative_path: "./" + type: src + - source: rtos/freertos/freertos-kernel/timers.c + repo_relative_path: "./" + project_relative_path: "./" + package_relative_path: "./" + type: src + - source: rtos/freertos/freertos-kernel/middleware_freertos-kernel.cmake + type: workspace + toolchains: armgcc + hidden: true + configuration: + cc-define: + SDK_OS_FREE_RTOS: + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel + section_info: + type: OS + full_name: FreeRTOS kernel + description: FreeRTOS kernel + version: 10.5.1 + vendor: NXP + user_visible: always + taxonomy: + cclass: RTOS + cgroup: Core + cbundle: FreeRTOS NXP + cbundle_version: 1.0.0 + display_name: FreeRTOS kernel + dependency: + allOf: + - middleware.freertos-kernel.template + - middleware.freertos-kernel.extension + meta-name: middleware.freertos-kernel + cmake_module_name: middleware_freertos-kernel +middleware.freertos-kernel.cm33_non_trustzone: + section-type: component + contents: + repo_base_path: rtos/freertos/freertos-kernel + project_base_path: freertos/freertos-kernel + cc-include: + - cores: cm33 + fpu: NO_FPU SP_FPU + repo_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + toolchains: armgcc mcux + project_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + package_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + files: + - cores: cm33 + fpu: NO_FPU SP_FPU + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + project_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + package_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + type: src + - cores: cm33 + fpu: NO_FPU SP_FPU + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + project_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + package_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + type: src + - cores: cm33 + fpu: NO_FPU SP_FPU + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + project_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + package_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + type: c_include + - cores: cm33 + fpu: NO_FPU SP_FPU + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + project_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + package_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + type: c_include + - cores: cm33 + fpu: NO_FPU SP_FPU + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + project_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + package_relative_path: portable/GCC/ARM_CM33_NTZ/non_secure + type: c_include + - source: rtos/freertos/freertos-kernel/middleware_freertos-kernel_cm33_non_trustzone.cmake + type: workspace + toolchains: armgcc + hidden: true + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel + section_info: + type: middleware + full_name: FreeRTOS cm33 non trustzone port + description: FreeRTOS cm33 non trustzone port + version: 10.5.1 + vendor: NXP + user_visible: always + taxonomy: + cclass: RTOS + cgroup: cm33_non_trustzone_port + cbundle: FreeRTOS NXP + cbundle_version: 1.0.0 + display_name: cm33 nontrustzone port + dependency: + allOf: + - middleware.freertos-kernel + - anyOf: + - middleware.freertos-kernel.template + - not: middleware.freertos-kernel.template + - core: + - cm33 + - not: middleware.freertos-kernel.cm33_trustzone.non_secure + - not: middleware.freertos-kernel.cm33_trustzone.secure + meta-name: middleware.freertos-kernel.cm33_non_trustzone + cmake_module_name: middleware_freertos-kernel_cm33_non_trustzone +middleware.freertos-kernel.cm33_trustzone.non_secure: + section-type: component + contents: + repo_base_path: rtos/freertos/freertos-kernel + project_base_path: freertos/freertos-kernel + cc-include: + - cores: cm33 + fpu: NO_FPU SP_FPU + repo_relative_path: portable/GCC/ARM_CM33/non_secure + toolchains: armgcc mcux + project_relative_path: portable/GCC/ARM_CM33/non_secure + package_relative_path: portable/GCC/ARM_CM33/non_secure + files: + - cores: cm33 + fpu: NO_FPU SP_FPU + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/port.c + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33/non_secure + project_relative_path: portable/GCC/ARM_CM33/non_secure + package_relative_path: portable/GCC/ARM_CM33/non_secure + type: src + - cores: cm33 + fpu: NO_FPU SP_FPU + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portasm.c + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33/non_secure + project_relative_path: portable/GCC/ARM_CM33/non_secure + package_relative_path: portable/GCC/ARM_CM33/non_secure + type: src + - cores: cm33 + fpu: NO_FPU SP_FPU + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portasm.h + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33/non_secure + project_relative_path: portable/GCC/ARM_CM33/non_secure + package_relative_path: portable/GCC/ARM_CM33/non_secure + type: c_include + - cores: cm33 + fpu: NO_FPU SP_FPU + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portmacro.h + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33/non_secure + project_relative_path: portable/GCC/ARM_CM33/non_secure + package_relative_path: portable/GCC/ARM_CM33/non_secure + type: c_include + - cores: cm33 + fpu: NO_FPU SP_FPU + source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33/non_secure + project_relative_path: portable/GCC/ARM_CM33/non_secure + package_relative_path: portable/GCC/ARM_CM33/non_secure + type: c_include + - source: rtos/freertos/freertos-kernel/middleware_freertos-kernel_cm33_trustzone_non_secure.cmake + type: workspace + toolchains: armgcc + hidden: true + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel + section_info: + type: middleware + full_name: FreeRTOS cm33 secure port + description: FreeRTOS cm33 secure port + version: 10.5.1 + vendor: NXP + user_visible: never + taxonomy: + cclass: RTOS + cgroup: cm33_secure_port + cbundle: FreeRTOS NXP + cbundle_version: 1.0.0 + display_name: cm33 secure port + dependency: + allOf: + - middleware.freertos-kernel + - middleware.freertos-kernel.mpu_wrappers + - middleware.freertos-kernel.cm33_trustzone.secure.context + - core: + - cm33 + - not: middleware.freertos-kernel.cm33_non_trustzone + meta-name: middleware.freertos-kernel.cm33_trustzone.non_secure + cmake_module_name: middleware_freertos-kernel_cm33_trustzone_non_secure +middleware.freertos-kernel.heap_1: + section-type: component + contents: + repo_base_path: rtos/freertos/freertos-kernel + project_base_path: freertos/freertos-kernel + files: + - source: rtos/freertos/freertos-kernel/portable/MemMang/heap_1.c + repo_relative_path: portable/MemMang + project_relative_path: portable/MemMang + package_relative_path: portable/MemMang + type: src + - source: rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_1.cmake + type: workspace + toolchains: armgcc + hidden: true + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel + section_info: + type: other + full_name: FreeRTOS heap 1 + description: FreeRTOS heap 1 + version: 10.5.1 + vendor: NXP + user_visible: never + taxonomy: + cclass: RTOS + cgroup: Heap + cvariant: Heap_1 + cbundle: FreeRTOS NXP + cbundle_version: 1.0.0 + display_name: FreeRTOS heap 1 + dependency: + allOf: + - middleware.freertos-kernel + - not: middleware.freertos-kernel.heap_2 + - not: middleware.freertos-kernel.heap_3 + - not: middleware.freertos-kernel.heap_4 + - not: middleware.freertos-kernel.heap_5 + meta-name: middleware.freertos-kernel.heap_1 + cmake_module_name: middleware_freertos-kernel_heap_1 +middleware.freertos-kernel.heap_2: + section-type: component + contents: + repo_base_path: rtos/freertos/freertos-kernel + project_base_path: freertos/freertos-kernel + files: + - source: rtos/freertos/freertos-kernel/portable/MemMang/heap_2.c + repo_relative_path: portable/MemMang + project_relative_path: portable/MemMang + package_relative_path: portable/MemMang + type: src + - source: rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_2.cmake + type: workspace + toolchains: armgcc + hidden: true + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel + section_info: + type: other + full_name: FreeRTOS heap 2 + description: FreeRTOS heap 2 + version: 10.5.1 + vendor: NXP + user_visible: never + taxonomy: + cclass: RTOS + cgroup: Heap + cvariant: Heap_2 + cbundle: FreeRTOS NXP + cbundle_version: 1.0.0 + display_name: FreeRTOS heap 2 + dependency: + allOf: + - middleware.freertos-kernel + - not: middleware.freertos-kernel.heap_1 + - not: middleware.freertos-kernel.heap_3 + - not: middleware.freertos-kernel.heap_4 + - not: middleware.freertos-kernel.heap_5 + meta-name: middleware.freertos-kernel.heap_2 + cmake_module_name: middleware_freertos-kernel_heap_2 +middleware.freertos-kernel.heap_3: + section-type: component + contents: + repo_base_path: rtos/freertos/freertos-kernel + project_base_path: freertos/freertos-kernel + files: + - source: rtos/freertos/freertos-kernel/portable/MemMang/heap_3.c + repo_relative_path: portable/MemMang + project_relative_path: portable/MemMang + package_relative_path: portable/MemMang + type: src + - source: rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_3.cmake + type: workspace + toolchains: armgcc + hidden: true + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel + section_info: + type: other + full_name: FreeRTOS heap_3 + description: FreeRTOS heap 3 + version: 10.5.1 + vendor: NXP + user_visible: never + taxonomy: + cclass: RTOS + cgroup: Heap + cvariant: Heap_3 + cbundle: FreeRTOS NXP + cbundle_version: 1.0.0 + display_name: FreeRTOS heap 3 + dependency: + allOf: + - middleware.freertos-kernel + - not: middleware.freertos-kernel.heap_1 + - not: middleware.freertos-kernel.heap_2 + - not: middleware.freertos-kernel.heap_4 + - not: middleware.freertos-kernel.heap_5 + meta-name: middleware.freertos-kernel.heap_3 + cmake_module_name: middleware_freertos-kernel_heap_3 +middleware.freertos-kernel.heap_4: + section-type: component + contents: + repo_base_path: rtos/freertos/freertos-kernel + project_base_path: freertos/freertos-kernel + files: + - source: rtos/freertos/freertos-kernel/portable/MemMang/heap_4.c + repo_relative_path: portable/MemMang + project_relative_path: portable/MemMang + package_relative_path: portable/MemMang + type: src + - source: rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_4.cmake + type: workspace + toolchains: armgcc + hidden: true + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel + section_info: + type: other + full_name: FreeRTOS heap 4 + description: FreeRTOS heap 4 + version: 10.5.1 + vendor: NXP + user_visible: never + taxonomy: + cclass: RTOS + cgroup: Heap + cvariant: Heap_4 + cbundle: FreeRTOS NXP + cbundle_version: 1.0.0 + default_variant: true + display_name: FreeRTOS heap 4 + dependency: + allOf: + - middleware.freertos-kernel + - not: middleware.freertos-kernel.heap_1 + - not: middleware.freertos-kernel.heap_2 + - not: middleware.freertos-kernel.heap_3 + - not: middleware.freertos-kernel.heap_5 + meta-name: middleware.freertos-kernel.heap_4 + cmake_module_name: middleware_freertos-kernel_heap_4 +middleware.freertos-kernel.heap_5: + section-type: component + contents: + repo_base_path: rtos/freertos/freertos-kernel + project_base_path: freertos/freertos-kernel + files: + - source: rtos/freertos/freertos-kernel/portable/MemMang/heap_5.c + repo_relative_path: portable/MemMang + project_relative_path: portable/MemMang + package_relative_path: portable/MemMang + type: src + - source: rtos/freertos/freertos-kernel/middleware_freertos-kernel_heap_5.cmake + type: workspace + toolchains: armgcc + hidden: true + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel + section_info: + type: other + full_name: FreeRTOS heap 5 + description: FreeRTOS heap 5 + version: 10.5.1 + vendor: NXP + user_visible: never + taxonomy: + cclass: RTOS + cgroup: Heap + cvariant: Heap_5 + cbundle: FreeRTOS NXP + cbundle_version: 1.0.0 + display_name: FreeRTOS heap 5 + dependency: + allOf: + - middleware.freertos-kernel + - not: middleware.freertos-kernel.heap_1 + - not: middleware.freertos-kernel.heap_2 + - not: middleware.freertos-kernel.heap_3 + - not: middleware.freertos-kernel.heap_4 + meta-name: middleware.freertos-kernel.heap_5 + cmake_module_name: middleware_freertos-kernel_heap_5 +middleware.freertos-kernel.mpu_wrappers: + section-type: component + contents: + repo_base_path: rtos/freertos/freertos-kernel + project_base_path: freertos/freertos-kernel + files: + - source: rtos/freertos/freertos-kernel/portable/Common/mpu_wrappers.c + repo_relative_path: portable/Common + project_relative_path: portable/Common + package_relative_path: portable/Common + type: src + - source: rtos/freertos/freertos-kernel/middleware_freertos-kernel_mpu_wrappers.cmake + type: workspace + toolchains: armgcc + hidden: true + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel + section_info: + type: other + full_name: FreeRTOS MPU wrappers + description: FreeRTOS MPU wrappers + version: 10.5.1 + vendor: NXP + user_visible: never + taxonomy: + cclass: RTOS + cgroup: MPU wrappers + cbundle: FreeRTOS NXP + cbundle_version: 1.0.0 + display_name: FreeRTOS MPU wrappers + dependency: + allOf: + - middleware.freertos-kernel + meta-name: middleware.freertos-kernel.mpu_wrappers + cmake_module_name: middleware_freertos-kernel_mpu_wrappers +middleware.freertos-kernel.cm33_trustzone.secure.context: + section-type: component + contents: + repo_base_path: rtos/freertos/freertos-kernel + project_base_path: freertos/freertos-kernel + cc-include: + - cores: cm33 + toolchains: armgcc mcux + fpu: NO_FPU SP_FPU + repo_relative_path: portable/GCC/ARM_CM33/secure + project_relative_path: portable/GCC/ARM_CM33/secure + package_relative_path: portable/GCC/ARM_CM33/secure + files: + - source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_context.h + toolchains: armgcc mcux + cores: cm33 + fpu: NO_FPU SP_FPU + repo_relative_path: portable/GCC/ARM_CM33/secure + project_relative_path: portable/GCC/ARM_CM33/secure + package_relative_path: portable/GCC/ARM_CM33/secure + type: c_include + - source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_init.h + toolchains: armgcc mcux + cores: cm33 + fpu: NO_FPU SP_FPU + repo_relative_path: portable/GCC/ARM_CM33/secure + project_relative_path: portable/GCC/ARM_CM33/secure + package_relative_path: portable/GCC/ARM_CM33/secure + type: c_include + - source: rtos/freertos/freertos-kernel/middleware_freertos-kernel_cm33_trustzone_secure_context.cmake + type: workspace + toolchains: armgcc + hidden: true + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel + section_info: + type: middleware + full_name: FreeRTOS cm33 TrustZone secure port + description: FreeRTOS cm33 TrustZone secure port + version: 10.5.1 + vendor: NXP + user_visible: never + taxonomy: + cclass: RTOS + cgroup: cm33 trustzone secure context + cbundle: FreeRTOS NXP + cbundle_version: 1.0.0 + display_name: cm33 trustzone secure context + dependency: + allOf: + - core: + - cm33 + meta-name: middleware.freertos-kernel.cm33_trustzone.secure.context + cmake_module_name: middleware_freertos-kernel_cm33_trustzone_secure_context +middleware.freertos-kernel.cm33_trustzone.secure: + section-type: component + contents: + repo_base_path: rtos/freertos/freertos-kernel + project_base_path: freertos/freertos-kernel + cc-include: + - repo_relative_path: portable/GCC/ARM_CM33/secure + toolchains: armgcc mcux + project_relative_path: portable/GCC/ARM_CM33/secure + package_relative_path: portable/GCC/ARM_CM33/secure + files: + - source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_context.c + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33/secure + project_relative_path: portable/GCC/ARM_CM33/secure + package_relative_path: portable/GCC/ARM_CM33/secure + type: src + - source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_context_port.c + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33/secure + project_relative_path: portable/GCC/ARM_CM33/secure + package_relative_path: portable/GCC/ARM_CM33/secure + type: src + - source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_heap.c + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33/secure + project_relative_path: portable/GCC/ARM_CM33/secure + package_relative_path: portable/GCC/ARM_CM33/secure + type: src + - source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_heap.h + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33/secure + project_relative_path: portable/GCC/ARM_CM33/secure + package_relative_path: portable/GCC/ARM_CM33/secure + type: c_include + - source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_init.c + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33/secure + project_relative_path: portable/GCC/ARM_CM33/secure + package_relative_path: portable/GCC/ARM_CM33/secure + type: src + - source: rtos/freertos/freertos-kernel/portable/GCC/ARM_CM33/secure/secure_port_macros.h + toolchains: armgcc mcux + repo_relative_path: portable/GCC/ARM_CM33/secure + project_relative_path: portable/GCC/ARM_CM33/secure + package_relative_path: portable/GCC/ARM_CM33/secure + type: c_include + - source: rtos/freertos/freertos-kernel/middleware_freertos-kernel_cm33_trustzone_secure.cmake + type: workspace + toolchains: armgcc + hidden: true + package_base_path: rtos/freertos/freertos-kernel + belong_to: set.middleware.freertos-kernel + section_info: + type: middleware + full_name: FreeRTOS Secure Context + description: FreeRTOS Secure Context + version: 10.5.1 + vendor: NXP + user_visible: always + taxonomy: + cclass: RTOS + cgroup: cm33 secure port + cbundle: FreeRTOS NXP + cbundle_version: 1.0.0 + display_name: cm33 secure port + dependency: + allOf: + - middleware.freertos-kernel.cm33_trustzone.secure.context + - anyOf: + - middleware.freertos-kernel.template + - not: middleware.freertos-kernel.template + - core: + - cm33 + meta-name: middleware.freertos-kernel.cm33_trustzone.secure + cmake_module_name: middleware_freertos-kernel_cm33_trustzone_secure diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/set_middleware_freertos-kernel.cmake b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/set_middleware_freertos-kernel.cmake new file mode 100644 index 0000000..c5151e3 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/set_middleware_freertos-kernel.cmake @@ -0,0 +1,314 @@ +include_guard(GLOBAL) + + +if (CONFIG_USE_middleware_freertos-kernel_extension) +# Add set(CONFIG_USE_middleware_freertos-kernel_extension true) in config.cmake to use this component + +message("middleware_freertos-kernel_extension component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./include +) + + +endif() + + +if (CONFIG_USE_middleware_freertos-kernel_template) +# Add set(CONFIG_USE_middleware_freertos-kernel_template true) in config.cmake to use this component + +message("middleware_freertos-kernel_template component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_CORE STREQUAL cm33 AND (CONFIG_FPU STREQUAL NO_FPU OR CONFIG_FPU STREQUAL SP_FPU) AND (CONFIG_DEVICE_ID STREQUAL LPC5502 OR CONFIG_DEVICE_ID STREQUAL LPC5504 OR CONFIG_DEVICE_ID STREQUAL LPC5506 OR CONFIG_DEVICE_ID STREQUAL LPC5512 OR CONFIG_DEVICE_ID STREQUAL LPC5514 OR CONFIG_DEVICE_ID STREQUAL LPC5516 OR CONFIG_DEVICE_ID STREQUAL LPC5526 OR CONFIG_DEVICE_ID STREQUAL LPC5528 OR CONFIG_DEVICE_ID STREQUAL LPC5534 OR CONFIG_DEVICE_ID STREQUAL LPC5536 OR CONFIG_DEVICE_ID STREQUAL LPC55S04 OR CONFIG_DEVICE_ID STREQUAL LPC55S06 OR CONFIG_DEVICE_ID STREQUAL LPC55S14 OR CONFIG_DEVICE_ID STREQUAL LPC55S16 OR CONFIG_DEVICE_ID STREQUAL LPC55S26 OR CONFIG_DEVICE_ID STREQUAL LPC55S28 OR CONFIG_DEVICE_ID STREQUAL LPC55S36 OR CONFIG_DEVICE_ID STREQUAL LPC55S66 OR CONFIG_DEVICE_ID STREQUAL LPC55S69)) + add_config_file(${CMAKE_CURRENT_LIST_DIR}/./template/ARM_CM33_3_priority_bits/FreeRTOSConfig.h ${CMAKE_CURRENT_LIST_DIR}/./template/ARM_CM4F_4_priority_bits middleware_freertos-kernel_template) +endif() + +if((CONFIG_CORE STREQUAL cm4f OR CONFIG_CORE STREQUAL cm7f) AND (CONFIG_DEVICE_ID STREQUAL MIMXRT1165xxxxx OR CONFIG_DEVICE_ID STREQUAL MIMXRT1166xxxxx OR CONFIG_DEVICE_ID STREQUAL MIMXRT1173xxxxx OR CONFIG_DEVICE_ID STREQUAL MIMXRT1175xxxxx OR CONFIG_DEVICE_ID STREQUAL MIMXRT1176xxxxx OR CONFIG_DEVICE_ID STREQUAL MIMXRT1021xxxxx OR CONFIG_DEVICE_ID STREQUAL MIMXRT1041xxxxB OR CONFIG_DEVICE_ID STREQUAL MIMXRT1042xxxxB OR CONFIG_DEVICE_ID STREQUAL MIMXRT1051xxxxB OR CONFIG_DEVICE_ID STREQUAL MIMXRT1052xxxxB OR CONFIG_DEVICE_ID STREQUAL MIMXRT1061xxxxA OR CONFIG_DEVICE_ID STREQUAL MIMXRT1061xxxxB OR CONFIG_DEVICE_ID STREQUAL MIMXRT1062xxxxA OR CONFIG_DEVICE_ID STREQUAL MIMXRT1062xxxxB OR CONFIG_DEVICE_ID STREQUAL MIMXRT1064xxxxA OR CONFIG_DEVICE_ID STREQUAL MIMXRT1171xxxxx OR CONFIG_DEVICE_ID STREQUAL MIMXRT1172xxxxx)) + add_config_file(${CMAKE_CURRENT_LIST_DIR}/./template/ARM_CM4F_4_priority_bits/FreeRTOSConfig.h ${CMAKE_CURRENT_LIST_DIR}/./template/ARM_CM4F_4_priority_bits middleware_freertos-kernel_template) +endif() + + +endif() + + +if (CONFIG_USE_middleware_freertos-kernel) +# Add set(CONFIG_USE_middleware_freertos-kernel true) in config.cmake to use this component + +message("middleware_freertos-kernel component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_middleware_freertos-kernel_template AND CONFIG_USE_middleware_freertos-kernel_extension) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./croutine.c + ${CMAKE_CURRENT_LIST_DIR}/./event_groups.c + ${CMAKE_CURRENT_LIST_DIR}/./list.c + ${CMAKE_CURRENT_LIST_DIR}/./queue.c + ${CMAKE_CURRENT_LIST_DIR}/./stream_buffer.c + ${CMAKE_CURRENT_LIST_DIR}/./tasks.c + ${CMAKE_CURRENT_LIST_DIR}/./timers.c +) + +if(CONFIG_COMPILER STREQUAL gcc AND (CONFIG_CORE STREQUAL cm4f OR CONFIG_CORE STREQUAL cm7f) AND (CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux)) + target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM4F/port.c + ) +endif() + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./include +) + +if(CONFIG_COMPILER STREQUAL gcc AND (CONFIG_CORE STREQUAL cm4f OR CONFIG_CORE STREQUAL cm7f) AND (CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux)) +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM4F +) +endif() + +if(CONFIG_USE_COMPONENT_CONFIGURATION) + message("===>Import configuration from ${CMAKE_CURRENT_LIST_FILE}") + + target_compile_definitions(${MCUX_SDK_PROJECT_NAME} PUBLIC + -DSDK_OS_FREE_RTOS + ) + +endif() + +else() + +message(SEND_ERROR "middleware_freertos-kernel dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_middleware_freertos-kernel_cm33_non_trustzone) +# Add set(CONFIG_USE_middleware_freertos-kernel_cm33_non_trustzone true) in config.cmake to use this component + +message("middleware_freertos-kernel_cm33_non_trustzone component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_middleware_freertos-kernel AND (CONFIG_USE_middleware_freertos-kernel_template OR (NOT CONFIG_USE_middleware_freertos-kernel_template)) AND (CONFIG_CORE STREQUAL cm33) AND (NOT CONFIG_USE_middleware_freertos-kernel_cm33_trustzone_non_secure) AND (NOT CONFIG_USE_middleware_freertos-kernel_cm33_trustzone_secure)) + +if(CONFIG_CORE STREQUAL cm33 AND (CONFIG_FPU STREQUAL NO_FPU OR CONFIG_FPU STREQUAL SP_FPU) AND (CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux)) + target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM33_NTZ/non_secure/port.c + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c + ) +endif() + +if(CONFIG_CORE STREQUAL cm33 AND (CONFIG_FPU STREQUAL NO_FPU OR CONFIG_FPU STREQUAL SP_FPU) AND (CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux)) +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM33_NTZ/non_secure +) +endif() + +else() + +message(SEND_ERROR "middleware_freertos-kernel_cm33_non_trustzone dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_middleware_freertos-kernel_cm33_trustzone_non_secure) +# Add set(CONFIG_USE_middleware_freertos-kernel_cm33_trustzone_non_secure true) in config.cmake to use this component + +message("middleware_freertos-kernel_cm33_trustzone_non_secure component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_middleware_freertos-kernel AND CONFIG_USE_middleware_freertos-kernel_mpu_wrappers AND CONFIG_USE_middleware_freertos-kernel_cm33_trustzone_secure_context AND (CONFIG_CORE STREQUAL cm33) AND (NOT CONFIG_USE_middleware_freertos-kernel_cm33_non_trustzone)) + +if(CONFIG_CORE STREQUAL cm33 AND (CONFIG_FPU STREQUAL NO_FPU OR CONFIG_FPU STREQUAL SP_FPU) AND (CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux)) + target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM33/non_secure/port.c + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM33/non_secure/portasm.c + ) +endif() + +if(CONFIG_CORE STREQUAL cm33 AND (CONFIG_FPU STREQUAL NO_FPU OR CONFIG_FPU STREQUAL SP_FPU) AND (CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux)) +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM33/non_secure +) +endif() + +else() + +message(SEND_ERROR "middleware_freertos-kernel_cm33_trustzone_non_secure dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_middleware_freertos-kernel_heap_1) +# Add set(CONFIG_USE_middleware_freertos-kernel_heap_1 true) in config.cmake to use this component + +message("middleware_freertos-kernel_heap_1 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_middleware_freertos-kernel AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_2) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_3) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_4) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_5)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./portable/MemMang/heap_1.c +) + +else() + +message(SEND_ERROR "middleware_freertos-kernel_heap_1 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_middleware_freertos-kernel_heap_2) +# Add set(CONFIG_USE_middleware_freertos-kernel_heap_2 true) in config.cmake to use this component + +message("middleware_freertos-kernel_heap_2 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_middleware_freertos-kernel AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_1) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_3) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_4) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_5)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./portable/MemMang/heap_2.c +) + +else() + +message(SEND_ERROR "middleware_freertos-kernel_heap_2 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_middleware_freertos-kernel_heap_3) +# Add set(CONFIG_USE_middleware_freertos-kernel_heap_3 true) in config.cmake to use this component + +message("middleware_freertos-kernel_heap_3 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_middleware_freertos-kernel AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_1) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_2) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_4) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_5)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./portable/MemMang/heap_3.c +) + +else() + +message(SEND_ERROR "middleware_freertos-kernel_heap_3 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_middleware_freertos-kernel_heap_4) +# Add set(CONFIG_USE_middleware_freertos-kernel_heap_4 true) in config.cmake to use this component + +message("middleware_freertos-kernel_heap_4 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_middleware_freertos-kernel AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_1) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_2) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_3) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_5)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./portable/MemMang/heap_4.c +) + +else() + +message(SEND_ERROR "middleware_freertos-kernel_heap_4 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_middleware_freertos-kernel_heap_5) +# Add set(CONFIG_USE_middleware_freertos-kernel_heap_5 true) in config.cmake to use this component + +message("middleware_freertos-kernel_heap_5 component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_middleware_freertos-kernel AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_1) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_2) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_3) AND (NOT CONFIG_USE_middleware_freertos-kernel_heap_4)) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./portable/MemMang/heap_5.c +) + +else() + +message(SEND_ERROR "middleware_freertos-kernel_heap_5 dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_middleware_freertos-kernel_mpu_wrappers) +# Add set(CONFIG_USE_middleware_freertos-kernel_mpu_wrappers true) in config.cmake to use this component + +message("middleware_freertos-kernel_mpu_wrappers component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_middleware_freertos-kernel) + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./portable/Common/mpu_wrappers.c +) + +else() + +message(SEND_ERROR "middleware_freertos-kernel_mpu_wrappers dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_middleware_freertos-kernel_cm33_trustzone_secure_context) +# Add set(CONFIG_USE_middleware_freertos-kernel_cm33_trustzone_secure_context true) in config.cmake to use this component + +message("middleware_freertos-kernel_cm33_trustzone_secure_context component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if((CONFIG_CORE STREQUAL cm33)) + +if(CONFIG_CORE STREQUAL cm33 AND (CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux) AND (CONFIG_FPU STREQUAL NO_FPU OR CONFIG_FPU STREQUAL SP_FPU)) +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM33/secure +) +endif() + +else() + +message(SEND_ERROR "middleware_freertos-kernel_cm33_trustzone_secure_context dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + + +if (CONFIG_USE_middleware_freertos-kernel_cm33_trustzone_secure) +# Add set(CONFIG_USE_middleware_freertos-kernel_cm33_trustzone_secure true) in config.cmake to use this component + +message("middleware_freertos-kernel_cm33_trustzone_secure component is included from ${CMAKE_CURRENT_LIST_FILE}.") + +if(CONFIG_USE_middleware_freertos-kernel_cm33_trustzone_secure_context AND (CONFIG_USE_middleware_freertos-kernel_template OR (NOT CONFIG_USE_middleware_freertos-kernel_template)) AND (CONFIG_CORE STREQUAL cm33)) + +if((CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux)) + target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM33/secure/secure_context.c + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM33/secure/secure_context_port.c + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM33/secure/secure_heap.c + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM33/secure/secure_init.c + ) +endif() + +if((CONFIG_TOOLCHAIN STREQUAL armgcc OR CONFIG_TOOLCHAIN STREQUAL mcux)) +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/./portable/GCC/ARM_CM33/secure +) +endif() + +else() + +message(SEND_ERROR "middleware_freertos-kernel_cm33_trustzone_secure dependency does not meet, please check ${CMAKE_CURRENT_LIST_FILE}.") + +endif() + +endif() + diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/stream_buffer.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/stream_buffer.c new file mode 100644 index 0000000..fed7eb8 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/stream_buffer.c @@ -0,0 +1,1427 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "stream_buffer.h" + +#if ( configUSE_TASK_NOTIFICATIONS != 1 ) + #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c +#endif + +#if ( INCLUDE_xTaskGetCurrentTaskHandle != 1 ) + #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 to build stream_buffer.c +#endif + +/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + +/* If the user has not provided application specific Rx notification macros, + * or #defined the notification macros away, then provide default implementations + * that uses task notifications. */ +/*lint -save -e9026 Function like macros allowed and needed here so they can be overridden. */ +#ifndef sbRECEIVE_COMPLETED + #define sbRECEIVE_COMPLETED( pxStreamBuffer ) \ + vTaskSuspendAll(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ + { \ + ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \ + ( uint32_t ) 0, \ + eNoAction ); \ + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ + } \ + } \ + ( void ) xTaskResumeAll(); +#endif /* sbRECEIVE_COMPLETED */ + +/* If user has provided a per-instance receive complete callback, then + * invoke the callback else use the receive complete macro which is provided by default for all instances. + */ +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define prvRECEIVE_COMPLETED( pxStreamBuffer ) \ + { \ + if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL ) \ + { \ + ( pxStreamBuffer )->pxReceiveCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \ + } \ + else \ + { \ + sbRECEIVE_COMPLETED( ( pxStreamBuffer ) ); \ + } \ + } +#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + #define prvRECEIVE_COMPLETED( pxStreamBuffer ) sbRECEIVE_COMPLETED( ( pxStreamBuffer ) ) +#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + +#ifndef sbRECEIVE_COMPLETED_FROM_ISR + #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \ + pxHigherPriorityTaskWoken ) \ + { \ + UBaseType_t uxSavedInterruptStatus; \ + \ + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ + { \ + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \ + ( uint32_t ) 0, \ + eNoAction, \ + ( pxHigherPriorityTaskWoken ) ); \ + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ + } \ + } \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \ + } +#endif /* sbRECEIVE_COMPLETED_FROM_ISR */ + +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \ + pxHigherPriorityTaskWoken ) \ + { \ + if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL ) \ + { \ + ( pxStreamBuffer )->pxReceiveCompletedCallback( ( pxStreamBuffer ), pdTRUE, ( pxHigherPriorityTaskWoken ) ); \ + } \ + else \ + { \ + sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) ); \ + } \ + } +#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \ + sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) ) +#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + +/* If the user has not provided an application specific Tx notification macro, + * or #defined the notification macro away, then provide a default + * implementation that uses task notifications. + */ +#ifndef sbSEND_COMPLETED + #define sbSEND_COMPLETED( pxStreamBuffer ) \ + vTaskSuspendAll(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \ + { \ + ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive, \ + ( uint32_t ) 0, \ + eNoAction ); \ + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \ + } \ + } \ + ( void ) xTaskResumeAll(); +#endif /* sbSEND_COMPLETED */ + +/* If user has provided a per-instance send completed callback, then + * invoke the callback else use the send complete macro which is provided by default for all instances. + */ +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define prvSEND_COMPLETED( pxStreamBuffer ) \ + { \ + if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL ) \ + { \ + pxStreamBuffer->pxSendCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \ + } \ + else \ + { \ + sbSEND_COMPLETED( ( pxStreamBuffer ) ); \ + } \ + } +#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + #define prvSEND_COMPLETED( pxStreamBuffer ) sbSEND_COMPLETED( ( pxStreamBuffer ) ) +#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + + +#ifndef sbSEND_COMPLETE_FROM_ISR + #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \ + { \ + UBaseType_t uxSavedInterruptStatus; \ + \ + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \ + { \ + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \ + ( uint32_t ) 0, \ + eNoAction, \ + ( pxHigherPriorityTaskWoken ) ); \ + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \ + } \ + } \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \ + } +#endif /* sbSEND_COMPLETE_FROM_ISR */ + + +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \ + { \ + if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL ) \ + { \ + ( pxStreamBuffer )->pxSendCompletedCallback( ( pxStreamBuffer ), pdTRUE, ( pxHigherPriorityTaskWoken ) ); \ + } \ + else \ + { \ + sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) ); \ + } \ + } +#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \ + sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) ) +#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + +/*lint -restore (9026) */ + +/* The number of bytes used to hold the length of a message in the buffer. */ +#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) ) + +/* Bits stored in the ucFlags field of the stream buffer. */ +#define sbFLAGS_IS_MESSAGE_BUFFER ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */ +#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */ + +/*-----------------------------------------------------------*/ + +/* Structure that hold state information on the buffer. */ +typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */ +{ + volatile size_t xTail; /* Index to the next item to read within the buffer. */ + volatile size_t xHead; /* Index to the next item to write within the buffer. */ + size_t xLength; /* The length of the buffer pointed to by pucBuffer. */ + size_t xTriggerLevelBytes; /* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */ + volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */ + volatile TaskHandle_t xTaskWaitingToSend; /* Holds the handle of a task waiting to send data to a message buffer that is full. */ + uint8_t * pucBuffer; /* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */ + uint8_t ucFlags; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */ + #endif + + #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + StreamBufferCallbackFunction_t pxSendCompletedCallback; /* Optional callback called on send complete. sbSEND_COMPLETED is called if this is NULL. */ + StreamBufferCallbackFunction_t pxReceiveCompletedCallback; /* Optional callback called on receive complete. sbRECEIVE_COMPLETED is called if this is NULL. */ + #endif +} StreamBuffer_t; + +/* + * The number of bytes available to be read from the buffer. + */ +static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION; + +/* + * Add xCount bytes from pucData into the pxStreamBuffer's data storage area. + * This function does not update the buffer's xHead pointer, so multiple writes + * may be chained together "atomically". This is useful for Message Buffers where + * the length and data bytes are written in two separate chunks, and we don't want + * the reader to see the buffer as having grown until after all data is copied over. + * This function takes a custom xHead value to indicate where to write to (necessary + * for chaining) and returns the the resulting xHead position. + * To mark the write as complete, manually set the buffer's xHead field with the + * returned xHead from this function. + */ +static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, + const uint8_t * pucData, + size_t xCount, + size_t xHead ) PRIVILEGED_FUNCTION; + +/* + * If the stream buffer is being used as a message buffer, then reads an entire + * message out of the buffer. If the stream buffer is being used as a stream + * buffer then read as many bytes as possible from the buffer. + * prvReadBytesFromBuffer() is called to actually extract the bytes from the + * buffer's data storage area. + */ +static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + size_t xBytesAvailable ) PRIVILEGED_FUNCTION; + +/* + * If the stream buffer is being used as a message buffer, then writes an entire + * message to the buffer. If the stream buffer is being used as a stream + * buffer then write as many bytes as possible to the buffer. + * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's + * data storage area. + */ +static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + size_t xSpace, + size_t xRequiredSpace ) PRIVILEGED_FUNCTION; + +/* + * Copies xCount bytes from the pxStreamBuffer's data storage area to pucData. + * This function does not update the buffer's xTail pointer, so multiple reads + * may be chained together "atomically". This is useful for Message Buffers where + * the length and data bytes are read in two separate chunks, and we don't want + * the writer to see the buffer as having more free space until after all data is + * copied over, especially if we have to abort the read due to insufficient receiving space. + * This function takes a custom xTail value to indicate where to read from (necessary + * for chaining) and returns the the resulting xTail position. + * To mark the read as complete, manually set the buffer's xTail field with the + * returned xTail from this function. + */ +static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer, + uint8_t * pucData, + size_t xCount, + size_t xTail ) PRIVILEGED_FUNCTION; + +/* + * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to + * initialise the members of the newly created stream buffer structure. + */ +static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, + uint8_t * const pucBuffer, + size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + uint8_t ucFlags, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) + { + uint8_t * pucAllocatedMemory; + uint8_t ucFlags; + + /* In case the stream buffer is going to be used as a message buffer + * (that is, it will hold discrete messages with a little meta data that + * says how big the next message is) check the buffer will be large enough + * to hold at least one message. */ + if( xIsMessageBuffer == pdTRUE ) + { + /* Is a message buffer but not statically allocated. */ + ucFlags = sbFLAGS_IS_MESSAGE_BUFFER; + configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); + } + else + { + /* Not a message buffer and not statically allocated. */ + ucFlags = 0; + configASSERT( xBufferSizeBytes > 0 ); + } + + configASSERT( xTriggerLevelBytes <= xBufferSizeBytes ); + + /* A trigger level of 0 would cause a waiting task to unblock even when + * the buffer was empty. */ + if( xTriggerLevelBytes == ( size_t ) 0 ) + { + xTriggerLevelBytes = ( size_t ) 1; + } + + /* A stream buffer requires a StreamBuffer_t structure and a buffer. + * Both are allocated in a single call to pvPortMalloc(). The + * StreamBuffer_t structure is placed at the start of the allocated memory + * and the buffer follows immediately after. The requested size is + * incremented so the free space is returned as the user would expect - + * this is a quirk of the implementation that means otherwise the free + * space would be reported as one byte smaller than would be logically + * expected. */ + if( xBufferSizeBytes < ( xBufferSizeBytes + 1 + sizeof( StreamBuffer_t ) ) ) + { + xBufferSizeBytes++; + pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */ + } + else + { + pucAllocatedMemory = NULL; + } + + if( pucAllocatedMemory != NULL ) + { + prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */ + pucAllocatedMemory + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */ + xBufferSizeBytes, + xTriggerLevelBytes, + ucFlags, + pxSendCompletedCallback, + pxReceiveCompletedCallback ); + + traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer ); + } + else + { + traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ); + } + + return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */ + } +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) + { + StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */ + StreamBufferHandle_t xReturn; + uint8_t ucFlags; + + configASSERT( pucStreamBufferStorageArea ); + configASSERT( pxStaticStreamBuffer ); + configASSERT( xTriggerLevelBytes <= xBufferSizeBytes ); + + /* A trigger level of 0 would cause a waiting task to unblock even when + * the buffer was empty. */ + if( xTriggerLevelBytes == ( size_t ) 0 ) + { + xTriggerLevelBytes = ( size_t ) 1; + } + + if( xIsMessageBuffer != pdFALSE ) + { + /* Statically allocated message buffer. */ + ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED; + } + else + { + /* Statically allocated stream buffer. */ + ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED; + } + + /* In case the stream buffer is going to be used as a message buffer + * (that is, it will hold discrete messages with a little meta data that + * says how big the next message is) check the buffer will be large enough + * to hold at least one message. */ + configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticStreamBuffer_t equals the size of the real + * message buffer structure. */ + volatile size_t xSize = sizeof( StaticStreamBuffer_t ); + configASSERT( xSize == sizeof( StreamBuffer_t ) ); + } /*lint !e529 xSize is referenced is configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + + if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) ) + { + prvInitialiseNewStreamBuffer( pxStreamBuffer, + pucStreamBufferStorageArea, + xBufferSizeBytes, + xTriggerLevelBytes, + ucFlags, + pxSendCompletedCallback, + pxReceiveCompletedCallback ); + + /* Remember this was statically allocated in case it is ever deleted + * again. */ + pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED; + + traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ); + + xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */ + } + else + { + xReturn = NULL; + traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ); + } + + return xReturn; + } +#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + +void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * pxStreamBuffer = xStreamBuffer; + + configASSERT( pxStreamBuffer ); + + traceSTREAM_BUFFER_DELETE( xStreamBuffer ); + + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE ) + { + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both the structure and the buffer were allocated using a single call + * to pvPortMalloc(), hence only one call to vPortFree() is required. */ + vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */ + } + #else + { + /* Should not be possible to get here, ucFlags must be corrupt. + * Force an assert. */ + configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 ); + } + #endif + } + else + { + /* The structure and buffer were not allocated dynamically and cannot be + * freed - just scrub the structure so future use will assert. */ + ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn = pdFAIL; + StreamBufferCallbackFunction_t pxSendCallback = NULL, pxReceiveCallback = NULL; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxStreamBufferNumber; + #endif + + configASSERT( pxStreamBuffer ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Store the stream buffer number so it can be restored after the + * reset. */ + uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber; + } + #endif + + /* Can only reset a message buffer if there are no tasks blocked on it. */ + taskENTER_CRITICAL(); + { + if( ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) ) + { + #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + { + pxSendCallback = pxStreamBuffer->pxSendCompletedCallback; + pxReceiveCallback = pxStreamBuffer->pxReceiveCompletedCallback; + } + #endif + + prvInitialiseNewStreamBuffer( pxStreamBuffer, + pxStreamBuffer->pucBuffer, + pxStreamBuffer->xLength, + pxStreamBuffer->xTriggerLevelBytes, + pxStreamBuffer->ucFlags, + pxSendCallback, + pxReceiveCallback ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + } + #endif + + traceSTREAM_BUFFER_RESET( xStreamBuffer ); + + xReturn = pdPASS; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + + configASSERT( pxStreamBuffer ); + + /* It is not valid for the trigger level to be 0. */ + if( xTriggerLevel == ( size_t ) 0 ) + { + xTriggerLevel = ( size_t ) 1; + } + + /* The trigger level is the number of bytes that must be in the stream + * buffer before a task that is waiting for data is unblocked. */ + if( xTriggerLevel < pxStreamBuffer->xLength ) + { + pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel; + xReturn = pdPASS; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xSpace; + size_t xOriginalTail; + + configASSERT( pxStreamBuffer ); + + /* The code below reads xTail and then xHead. This is safe if the stream + * buffer is updated once between the two reads - but not if the stream buffer + * is updated more than once between the two reads - hence the loop. */ + do + { + xOriginalTail = pxStreamBuffer->xTail; + xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; + xSpace -= pxStreamBuffer->xHead; + } while( xOriginalTail != pxStreamBuffer->xTail ); + + xSpace -= ( size_t ) 1; + + if( xSpace >= pxStreamBuffer->xLength ) + { + xSpace -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xSpace; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn; + + configASSERT( pxStreamBuffer ); + + xReturn = prvBytesInBuffer( pxStreamBuffer ); + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xSpace = 0; + size_t xRequiredSpace = xDataLengthBytes; + TimeOut_t xTimeOut; + size_t xMaxReportedSpace = 0; + + configASSERT( pvTxData ); + configASSERT( pxStreamBuffer ); + + /* The maximum amount of space a stream buffer will ever report is its length + * minus 1. */ + xMaxReportedSpace = pxStreamBuffer->xLength - ( size_t ) 1; + + /* This send function is used to write to both message buffers and stream + * buffers. If this is a message buffer then the space needed must be + * increased by the amount of bytes needed to store the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; + + /* Overflow? */ + configASSERT( xRequiredSpace > xDataLengthBytes ); + + /* If this is a message buffer then it must be possible to write the + * whole message. */ + if( xRequiredSpace > xMaxReportedSpace ) + { + /* The message would not fit even if the entire buffer was empty, + * so don't wait for space. */ + xTicksToWait = ( TickType_t ) 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If this is a stream buffer then it is acceptable to write only part + * of the message to the buffer. Cap the length to the total length of + * the buffer. */ + if( xRequiredSpace > xMaxReportedSpace ) + { + xRequiredSpace = xMaxReportedSpace; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xTicksToWait != ( TickType_t ) 0 ) + { + vTaskSetTimeOutState( &xTimeOut ); + + do + { + /* Wait until the required number of bytes are free in the message + * buffer. */ + taskENTER_CRITICAL(); + { + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + + if( xSpace < xRequiredSpace ) + { + /* Clear notification state as going to wait for space. */ + ( void ) xTaskNotifyStateClear( NULL ); + + /* Should only be one writer. */ + configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); + pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); + } + else + { + taskEXIT_CRITICAL(); + break; + } + } + taskEXIT_CRITICAL(); + + traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); + ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); + pxStreamBuffer->xTaskWaitingToSend = NULL; + } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xSpace == ( size_t ) 0 ) + { + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); + + if( xReturn > ( size_t ) 0 ) + { + traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); + + /* Was a task waiting for the data? */ + if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) + { + prvSEND_COMPLETED( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xSpace; + size_t xRequiredSpace = xDataLengthBytes; + + configASSERT( pvTxData ); + configASSERT( pxStreamBuffer ); + + /* This send function is used to write to both message buffers and stream + * buffers. If this is a message buffer then the space needed must be + * increased by the amount of bytes needed to store the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); + + if( xReturn > ( size_t ) 0 ) + { + /* Was a task waiting for the data? */ + if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) + { + prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + size_t xSpace, + size_t xRequiredSpace ) +{ + size_t xNextHead = pxStreamBuffer->xHead; + configMESSAGE_BUFFER_LENGTH_TYPE xMessageLength; + + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + /* This is a message buffer, as opposed to a stream buffer. */ + + /* Convert xDataLengthBytes to the message length type. */ + xMessageLength = ( configMESSAGE_BUFFER_LENGTH_TYPE ) xDataLengthBytes; + + /* Ensure the data length given fits within configMESSAGE_BUFFER_LENGTH_TYPE. */ + configASSERT( ( size_t ) xMessageLength == xDataLengthBytes ); + + if( xSpace >= xRequiredSpace ) + { + /* There is enough space to write both the message length and the message + * itself into the buffer. Start by writing the length of the data, the data + * itself will be written later in this function. */ + xNextHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xMessageLength ), sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextHead ); + } + else + { + /* Not enough space, so do not write data to the buffer. */ + xDataLengthBytes = 0; + } + } + else + { + /* This is a stream buffer, as opposed to a message buffer, so writing a + * stream of bytes rather than discrete messages. Plan to write as many + * bytes as possible. */ + xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); + } + + if( xDataLengthBytes != ( size_t ) 0 ) + { + /* Write the data to the buffer. */ + pxStreamBuffer->xHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes, xNextHead ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alignment and access. */ + } + + return xDataLengthBytes; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; + + configASSERT( pvRxData ); + configASSERT( pxStreamBuffer ); + + /* This receive function is used by both message buffers, which store + * discrete messages, and stream buffers, which store a continuous stream of + * bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + if( xTicksToWait != ( TickType_t ) 0 ) + { + /* Checking if there is data and clearing the notification state must be + * performed atomically. */ + taskENTER_CRITICAL(); + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + /* If this function was invoked by a message buffer read then + * xBytesToStoreMessageLength holds the number of bytes used to hold + * the length of the next discrete message. If this function was + * invoked by a stream buffer read then xBytesToStoreMessageLength will + * be 0. */ + if( xBytesAvailable <= xBytesToStoreMessageLength ) + { + /* Clear notification state as going to wait for data. */ + ( void ) xTaskNotifyStateClear( NULL ); + + /* Should only be one reader. */ + configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL ); + pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + if( xBytesAvailable <= xBytesToStoreMessageLength ) + { + /* Wait for data to be available. */ + traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ); + ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); + pxStreamBuffer->xTaskWaitingToReceive = NULL; + + /* Recheck the data available after blocking. */ + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + } + + /* Whether receiving a discrete message (where xBytesToStoreMessageLength + * holds the number of bytes used to store the message length) or a stream of + * bytes (where xBytesToStoreMessageLength is zero), the number of bytes + * available must be greater than xBytesToStoreMessageLength to be able to + * read bytes from the buffer. */ + if( xBytesAvailable > xBytesToStoreMessageLength ) + { + xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable ); + + /* Was a task waiting for space in the buffer? */ + if( xReceivedLength != ( size_t ) 0 ) + { + traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ); + prvRECEIVE_COMPLETED( xStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ); + mtCOVERAGE_TEST_MARKER(); + } + + return xReceivedLength; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xBytesAvailable; + configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn; + + configASSERT( pxStreamBuffer ); + + /* Ensure the stream buffer is being used as a message buffer. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH ) + { + /* The number of bytes available is greater than the number of bytes + * required to hold the length of the next message, so another message + * is available. */ + ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, pxStreamBuffer->xTail ); + xReturn = ( size_t ) xTempReturn; + } + else + { + /* The minimum amount of bytes in a message buffer is + * ( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is + * less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid + * value is 0. */ + configASSERT( xBytesAvailable == 0 ); + xReturn = 0; + } + } + else + { + xReturn = 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; + + configASSERT( pvRxData ); + configASSERT( pxStreamBuffer ); + + /* This receive function is used by both message buffers, which store + * discrete messages, and stream buffers, which store a continuous stream of + * bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + /* Whether receiving a discrete message (where xBytesToStoreMessageLength + * holds the number of bytes used to store the message length) or a stream of + * bytes (where xBytesToStoreMessageLength is zero), the number of bytes + * available must be greater than xBytesToStoreMessageLength to be able to + * read bytes from the buffer. */ + if( xBytesAvailable > xBytesToStoreMessageLength ) + { + xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable ); + + /* Was a task waiting for space in the buffer? */ + if( xReceivedLength != ( size_t ) 0 ) + { + prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ); + + return xReceivedLength; +} +/*-----------------------------------------------------------*/ + +static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + size_t xBytesAvailable ) +{ + size_t xCount, xNextMessageLength; + configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength; + size_t xNextTail = pxStreamBuffer->xTail; + + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + /* A discrete message is being received. First receive the length + * of the message. */ + xNextTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextTail ); + xNextMessageLength = ( size_t ) xTempNextMessageLength; + + /* Reduce the number of bytes available by the number of bytes just + * read out. */ + xBytesAvailable -= sbBYTES_TO_STORE_MESSAGE_LENGTH; + + /* Check there is enough space in the buffer provided by the + * user. */ + if( xNextMessageLength > xBufferLengthBytes ) + { + /* The user has provided insufficient space to read the message. */ + xNextMessageLength = 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* A stream of bytes is being received (as opposed to a discrete + * message), so read as many bytes as possible. */ + xNextMessageLength = xBufferLengthBytes; + } + + /* Use the minimum of the wanted bytes and the available bytes. */ + xCount = configMIN( xNextMessageLength, xBytesAvailable ); + + if( xCount != ( size_t ) 0 ) + { + /* Read the actual data and update the tail to mark the data as officially consumed. */ + pxStreamBuffer->xTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xCount, xNextTail ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */ + } + + return xCount; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + size_t xTail; + + configASSERT( pxStreamBuffer ); + + /* True if no bytes are available. */ + xTail = pxStreamBuffer->xTail; + + if( pxStreamBuffer->xHead == xTail ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) +{ + BaseType_t xReturn; + size_t xBytesToStoreMessageLength; + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + + configASSERT( pxStreamBuffer ); + + /* This generic version of the receive function is used by both message + * buffers, which store discrete messages, and stream buffers, which store a + * continuous stream of bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + /* True if the available space equals zero. */ + if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( pxStreamBuffer ); + + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) + { + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, + ( uint32_t ) 0, + eNoAction, + pxHigherPriorityTaskWoken ); + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( pxStreamBuffer ); + + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) + { + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, + ( uint32_t ) 0, + eNoAction, + pxHigherPriorityTaskWoken ); + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, + const uint8_t * pucData, + size_t xCount, + size_t xHead ) +{ + size_t xFirstLength; + + configASSERT( xCount > ( size_t ) 0 ); + + /* Calculate the number of bytes that can be added in the first write - + * which may be less than the total number of bytes that need to be added if + * the buffer will wrap back to the beginning. */ + xFirstLength = configMIN( pxStreamBuffer->xLength - xHead, xCount ); + + /* Write as many bytes as can be written in the first write. */ + configASSERT( ( xHead + xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + + /* If the number of bytes written was less than the number that could be + * written in the first write... */ + if( xCount > xFirstLength ) + { + /* ...then write the remaining bytes to the start of the buffer. */ + configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xHead += xCount; + + if( xHead >= pxStreamBuffer->xLength ) + { + xHead -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xHead; +} +/*-----------------------------------------------------------*/ + +static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer, + uint8_t * pucData, + size_t xCount, + size_t xTail ) +{ + size_t xFirstLength; + + configASSERT( xCount != ( size_t ) 0 ); + + /* Calculate the number of bytes that can be read - which may be + * less than the number wanted if the data wraps around to the start of + * the buffer. */ + xFirstLength = configMIN( pxStreamBuffer->xLength - xTail, xCount ); + + /* Obtain the number of bytes it is possible to obtain in the first + * read. Asserts check bounds of read and write. */ + configASSERT( xFirstLength <= xCount ); + configASSERT( ( xTail + xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + + /* If the total number of wanted bytes is greater than the number + * that could be read in the first read... */ + if( xCount > xFirstLength ) + { + /* ...then read the remaining bytes from the start of the buffer. */ + ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Move the tail pointer to effectively remove the data read from the buffer. */ + xTail += xCount; + + if( xTail >= pxStreamBuffer->xLength ) + { + xTail -= pxStreamBuffer->xLength; + } + + return xTail; +} +/*-----------------------------------------------------------*/ + +static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) +{ +/* Returns the distance between xTail and xHead. */ + size_t xCount; + + xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; + xCount -= pxStreamBuffer->xTail; + + if( xCount >= pxStreamBuffer->xLength ) + { + xCount -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xCount; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, + uint8_t * const pucBuffer, + size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + uint8_t ucFlags, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) +{ + /* Assert here is deliberately writing to the entire buffer to ensure it can + * be written to without generating exceptions, and is setting the buffer to a + * known value to assist in development/debugging. */ + #if ( configASSERT_DEFINED == 1 ) + { + /* The value written just has to be identifiable when looking at the + * memory. Don't use 0xA5 as that is the stack fill value and could + * result in confusion as to what is actually being observed. */ + const BaseType_t xWriteValue = 0x55; + configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer ); + } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */ + #endif + + ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */ + pxStreamBuffer->pucBuffer = pucBuffer; + pxStreamBuffer->xLength = xBufferSizeBytes; + pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes; + pxStreamBuffer->ucFlags = ucFlags; + #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + { + pxStreamBuffer->pxSendCompletedCallback = pxSendCompletedCallback; + pxStreamBuffer->pxReceiveCompletedCallback = pxReceiveCompletedCallback; + } + #else + { + ( void ) pxSendCompletedCallback; + ( void ) pxReceiveCompletedCallback; + } + #endif +} + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) + { + return xStreamBuffer->uxStreamBufferNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, + UBaseType_t uxStreamBufferNumber ) + { + xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) + { + return( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ); + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/tasks.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/tasks.c new file mode 100644 index 0000000..f965938 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/tasks.c @@ -0,0 +1,5464 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + * + * Copyright 2019 MicroEJ Corp. This file has been modified by MicroEJ Corp. + * 1. Patch for SystemView support + */ + +/* Standard includes. */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "stack_macros.h" + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + +/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting + * functions but without including stdio.h here. */ +#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) + +/* At the bottom of this file are two optional functions that can be used + * to generate human readable text from the raw data generated by the + * uxTaskGetSystemState() function. Note the formatting functions are provided + * for convenience only, and are NOT considered part of the kernel. */ + #include +#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */ + +#if ( configUSE_PREEMPTION == 0 ) + +/* If the cooperative scheduler is being used then a yield should not be + * performed just because a higher priority task has been woken. */ + #define taskYIELD_IF_USING_PREEMPTION() +#else + #define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API() +#endif + +/* Values that can be assigned to the ucNotifyState member of the TCB. */ +#define taskNOT_WAITING_NOTIFICATION ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */ +#define taskWAITING_NOTIFICATION ( ( uint8_t ) 1 ) +#define taskNOTIFICATION_RECEIVED ( ( uint8_t ) 2 ) + +/* + * The value used to fill the stack of a task when the task is created. This + * is used purely for checking the high water mark for tasks. + */ +#define tskSTACK_FILL_BYTE ( 0xa5U ) + +/* Bits used to record how a task's stack and TCB were allocated. */ +#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 0 ) +#define tskSTATICALLY_ALLOCATED_STACK_ONLY ( ( uint8_t ) 1 ) +#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 2 ) + +/* If any of the following are set then task stacks are filled with a known + * value so the high water mark can be determined. If none of the following are + * set then don't fill the stack so there is no unnecessary dependency on memset. */ +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) + #define tskSET_NEW_STACKS_TO_KNOWN_VALUE 1 +#else + #define tskSET_NEW_STACKS_TO_KNOWN_VALUE 0 +#endif + +/* + * Macros used by vListTask to indicate which state a task is in. + */ +#define tskRUNNING_CHAR ( 'X' ) +#define tskBLOCKED_CHAR ( 'B' ) +#define tskREADY_CHAR ( 'R' ) +#define tskDELETED_CHAR ( 'D' ) +#define tskSUSPENDED_CHAR ( 'S' ) + +/* + * Some kernel aware debuggers require the data the debugger needs access to to + * be global, rather than file scope. + */ +#ifdef portREMOVE_STATIC_QUALIFIER + #define static +#endif + +/* The name allocated to the Idle task. This can be overridden by defining + * configIDLE_TASK_NAME in FreeRTOSConfig.h. */ +#ifndef configIDLE_TASK_NAME + #define configIDLE_TASK_NAME "IDLE" +#endif + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) + +/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is + * performed in a generic way that is not optimised to any particular + * microcontroller architecture. */ + +/* uxTopReadyPriority holds the priority of the highest priority ready + * state task. */ + #define taskRECORD_READY_PRIORITY( uxPriority ) \ + { \ + if( ( uxPriority ) > uxTopReadyPriority ) \ + { \ + uxTopReadyPriority = ( uxPriority ); \ + } \ + } /* taskRECORD_READY_PRIORITY */ + +/*-----------------------------------------------------------*/ + + #define taskSELECT_HIGHEST_PRIORITY_TASK() \ + { \ + UBaseType_t uxTopPriority = uxTopReadyPriority; \ + \ + /* Find the highest priority queue that contains ready tasks. */ \ + while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) ) \ + { \ + configASSERT( uxTopPriority ); \ + --uxTopPriority; \ + } \ + \ + /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \ + * the same priority get an equal share of the processor time. */ \ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \ + uxTopReadyPriority = uxTopPriority; \ + } /* taskSELECT_HIGHEST_PRIORITY_TASK */ + +/*-----------------------------------------------------------*/ + +/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as + * they are only required when a port optimised method of task selection is + * being used. */ + #define taskRESET_READY_PRIORITY( uxPriority ) + #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority ) + +#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is + * performed in a way that is tailored to the particular microcontroller + * architecture being used. */ + +/* A port optimised version is provided. Call the port defined macros. */ + #define taskRECORD_READY_PRIORITY( uxPriority ) portRECORD_READY_PRIORITY( ( uxPriority ), uxTopReadyPriority ) + +/*-----------------------------------------------------------*/ + + #define taskSELECT_HIGHEST_PRIORITY_TASK() \ + { \ + UBaseType_t uxTopPriority; \ + \ + /* Find the highest priority list that contains ready tasks. */ \ + portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority ); \ + configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \ + } /* taskSELECT_HIGHEST_PRIORITY_TASK() */ + +/*-----------------------------------------------------------*/ + +/* A port optimised version is provided, call it only if the TCB being reset + * is being referenced from a ready list. If it is referenced from a delayed + * or suspended list then it won't be in a ready list. */ + #define taskRESET_READY_PRIORITY( uxPriority ) \ + { \ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \ + { \ + portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) ); \ + } \ + } + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick + * count overflows. */ +#define taskSWITCH_DELAYED_LISTS() \ + { \ + List_t * pxTemp; \ + \ + /* The delayed tasks list should be empty when the lists are switched. */ \ + configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) ); \ + \ + pxTemp = pxDelayedTaskList; \ + pxDelayedTaskList = pxOverflowDelayedTaskList; \ + pxOverflowDelayedTaskList = pxTemp; \ + xNumOfOverflows++; \ + prvResetNextTaskUnblockTime(); \ + } + +/*-----------------------------------------------------------*/ + +/* + * Place the task represented by pxTCB into the appropriate ready list for + * the task. It is inserted at the end of the list. + */ +#define prvAddTaskToReadyList( pxTCB ) \ + traceMOVED_TASK_TO_READY_STATE( pxTCB ); \ + taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority ); \ + listINSERT_END( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \ + tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +/*-----------------------------------------------------------*/ +/* + * Place the task represented by pxTCB which has been in a ready list before + * into the appropriate ready list for the task. + * It is inserted at the end of the list. + */ +#define prvReaddTaskToReadyList( pxTCB ) \ + traceREADDED_TASK_TO_READY_STATE( pxTCB ); \ + taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority ); \ + vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \ + tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +/*-----------------------------------------------------------*/ + +/* + * Several functions take a TaskHandle_t parameter that can optionally be NULL, + * where NULL is used to indicate that the handle of the currently executing + * task should be used in place of the parameter. This macro simply checks to + * see if the parameter is NULL and returns a pointer to the appropriate TCB. + */ +#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) ) + +/* The item value of the event list item is normally used to hold the priority + * of the task to which it belongs (coded to allow it to be held in reverse + * priority order). However, it is occasionally borrowed for other purposes. It + * is important its value is not updated due to a task priority change while it is + * being used for another purpose. The following bit definition is used to inform + * the scheduler that the value should not be changed - in which case it is the + * responsibility of whichever module is using the value to ensure it gets set back + * to its original value when it is released. */ +#if ( configUSE_16_BIT_TICKS == 1 ) + #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x8000U +#else + #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x80000000UL +#endif + +/* + * Task control block. A task control block (TCB) is allocated for each task, + * and stores task state information, including a pointer to the task's context + * (the task's run time environment, including register values) + */ +typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +{ + volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */ + + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ + #endif + + ListItem_t xStateListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */ + ListItem_t xEventListItem; /*< Used to reference a task from an event list. */ + UBaseType_t uxPriority; /*< The priority of the task. 0 is the lowest priority. */ + StackType_t * pxStack; /*< Points to the start of the stack. */ + char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */ + #endif + + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ + UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */ + #endif + + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ + UBaseType_t uxMutexesHeld; + #endif + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + TaskHookFunction_t pxTaskTag; + #endif + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */ + #endif + + #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) ) + configTLS_BLOCK_TYPE xTLSBlock; /*< Memory block used as Thread Local Storage (TLS) Block for the task. */ + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + volatile uint32_t ulNotifiedValue[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + volatile uint8_t ucNotifyState[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + #endif + + /* See the comments in FreeRTOS.h with the definition of + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */ + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */ + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDelayAborted; + #endif + + #if ( configUSE_POSIX_ERRNO == 1 ) + int iTaskErrno; + #endif +} tskTCB; + +/* The old tskTCB name is maintained above then typedefed to the new TCB_t name + * below to enable the use of older kernel aware debuggers. */ +typedef tskTCB TCB_t; + +/*lint -save -e956 A manual analysis and inspection has been used to determine + * which static variables must be declared volatile. */ +portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL; + +/* Lists for ready and blocked tasks. -------------------- + * xDelayedTaskList1 and xDelayedTaskList2 could be moved to function scope but + * doing so breaks some kernel aware debuggers and debuggers that rely on removing + * the static qualifier. */ +PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */ +PRIVILEGED_DATA static List_t xDelayedTaskList1; /*< Delayed tasks. */ +PRIVILEGED_DATA static List_t xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ +PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ +PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ +PRIVILEGED_DATA static List_t xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */ + +#if ( INCLUDE_vTaskDelete == 1 ) + + PRIVILEGED_DATA static List_t xTasksWaitingTermination; /*< Tasks that have been deleted - but their memory not yet freed. */ + PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U; + +#endif + +#if ( INCLUDE_vTaskSuspend == 1 ) + + PRIVILEGED_DATA static List_t xSuspendedTaskList; /*< Tasks that are currently suspended. */ + +#endif + +/* Global POSIX errno. Its value is changed upon context switching to match + * the errno of the currently running task. */ +#if ( configUSE_POSIX_ERRNO == 1 ) + int FreeRTOS_errno = 0; +#endif + +/* Other file private variables. --------------------------------*/ +PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U; +PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; +PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY; +PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE; +PRIVILEGED_DATA static volatile TickType_t xPendedTicks = ( TickType_t ) 0U; +PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE; +PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0; +PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U; +PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */ +PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL; /*< Holds the handle of the idle task. The idle task is created automatically when the scheduler is started. */ + +/* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists. + * For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority + * to determine the number of priority lists to read back from the remote target. */ +const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U; + +/* Context switches are held pending while the scheduler is suspended. Also, + * interrupts must not manipulate the xStateListItem of a TCB, or any of the + * lists the xStateListItem can be referenced from, if the scheduler is suspended. + * If an interrupt needs to unblock a task while the scheduler is suspended then it + * moves the task's event list item into the xPendingReadyList, ready for the + * kernel to move the task from the pending ready list into the real ready list + * when the scheduler is unsuspended. The pending ready list itself can only be + * accessed from a critical section. */ +PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) pdFALSE; + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + +/* Do not move these variables to function scope as doing so prevents the + * code working with debuggers that need to remove the static qualifier. */ + PRIVILEGED_DATA static configRUN_TIME_COUNTER_TYPE ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */ + PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */ + +#endif + +/*lint -restore */ + +/*-----------------------------------------------------------*/ + +/* File private functions. --------------------------------*/ + +/** + * Utility task that simply returns pdTRUE if the task referenced by xTask is + * currently in the Suspended state, or pdFALSE if the task referenced by xTask + * is in any other state. + */ +#if ( INCLUDE_vTaskSuspend == 1 ) + + static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +#endif /* INCLUDE_vTaskSuspend */ + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first task. + */ +static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION; + +/* + * The idle task, which as all tasks is implemented as a never ending loop. + * The idle task is automatically created and added to the ready lists upon + * creation of the first user task. + * + * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ) PRIVILEGED_FUNCTION; + +/* + * Utility to free all memory allocated by the scheduler to hold a TCB, + * including the stack pointed to by the TCB. + * + * This does not free memory allocated by the task itself (i.e. memory + * allocated by calls to pvPortMalloc from within the tasks application code). + */ +#if ( INCLUDE_vTaskDelete == 1 ) + + static void prvDeleteTCB( TCB_t * pxTCB ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Used only by the idle task. This checks to see if anything has been placed + * in the list of tasks waiting to be deleted. If so the task is cleaned up + * and its TCB deleted. + */ +static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION; + +/* + * The currently executing task is entering the Blocked state. Add the task to + * either the current or the overflow delayed task list. + */ +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, + const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION; + +/* + * Fills an TaskStatus_t structure with information on each task that is + * referenced from the pxList list (which may be a ready list, a delayed list, + * a suspended list, etc.). + * + * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM + * NORMAL APPLICATION CODE. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + + static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray, + List_t * pxList, + eTaskState eState ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Searches pxList for a task with name pcNameToQuery - returning a handle to + * the task if it is found, or NULL if the task is not found. + */ +#if ( INCLUDE_xTaskGetHandle == 1 ) + + static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList, + const char pcNameToQuery[] ) PRIVILEGED_FUNCTION; + +#endif + +/* + * When a task is created, the stack of the task is filled with a known value. + * This function determines the 'high water mark' of the task stack by + * determining how much of the stack remains at the original preset value. + */ +#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) + + static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Return the amount of time, in ticks, that will pass before the kernel will + * next move a task from the Blocked state to the Running state. + * + * This conditional compilation should use inequality to 0, not equality to 1. + * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user + * defined low power mode implementations require configUSE_TICKLESS_IDLE to be + * set to a value other than 1. + */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + + static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Set xNextTaskUnblockTime to the time at which the next Blocked state task + * will exit the Blocked state. + */ +static void prvResetNextTaskUnblockTime( void ) PRIVILEGED_FUNCTION; + +#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) + +/* + * Helper function used to pad task names with spaces when printing out + * human readable tables of task information. + */ + static char * prvWriteNameToBuffer( char * pcBuffer, + const char * pcTaskName ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Called after a Task_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ +static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + TCB_t * pxNewTCB, + const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION; + +/* + * Called after a new task has been created and initialised to place the task + * under the control of the scheduler. + */ +static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; + +/* + * freertos_tasks_c_additions_init() should only be called if the user definable + * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro + * called by the function. + */ +#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + + static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION; + +#endif + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) + { + TCB_t * pxNewTCB; + TaskHandle_t xReturn; + + configASSERT( puxStackBuffer != NULL ); + configASSERT( pxTaskBuffer != NULL ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticTask_t equals the size of the real task + * structure. */ + volatile size_t xSize = sizeof( StaticTask_t ); + configASSERT( xSize == sizeof( TCB_t ) ); + ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ + } + #endif /* configASSERT_DEFINED */ + + if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) + { + /* The memory used for the task's TCB and stack are passed into this + * function - use them. */ + pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + * task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); + prvAddNewTaskToReadyList( pxNewTCB ); + } + else + { + xReturn = NULL; + } + + return xReturn; + } + +#endif /* SUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + + configASSERT( pxTaskDefinition->puxStackBuffer != NULL ); + configASSERT( pxTaskDefinition->pxTaskBuffer != NULL ); + + if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) ) + { + /* Allocate space for the TCB. Where the memory comes from depends + * on the implementation of the port malloc function and whether or + * not static allocation is being used. */ + pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer; + memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note this + * task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, + pxTaskDefinition->pcName, + ( uint32_t ) pxTaskDefinition->usStackDepth, + pxTaskDefinition->pvParameters, + pxTaskDefinition->uxPriority, + pxCreatedTask, pxNewTCB, + pxTaskDefinition->xRegions ); + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + + return xReturn; + } + +#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + + configASSERT( pxTaskDefinition->puxStackBuffer ); + + if( pxTaskDefinition->puxStackBuffer != NULL ) + { + /* Allocate space for the TCB. Where the memory comes from depends + * on the implementation of the port malloc function and whether or + * not static allocation is being used. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + + if( pxNewTCB != NULL ) + { + memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note + * this task had a statically allocated stack in case it is + * later deleted. The TCB was allocated dynamically. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, + pxTaskDefinition->pcName, + ( uint32_t ) pxTaskDefinition->usStackDepth, + pxTaskDefinition->pvParameters, + pxTaskDefinition->uxPriority, + pxCreatedTask, pxNewTCB, + pxTaskDefinition->xRegions ); + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + } + + return xReturn; + } + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + /* If the stack grows down then allocate the stack then the TCB so the stack + * does not grow into the TCB. Likewise if the stack grows up then allocate + * the TCB then the stack. */ + #if ( portSTACK_GROWTH > 0 ) + { + /* Allocate space for the TCB. Where the memory comes from depends on + * the implementation of the port malloc function and whether or not static + * allocation is being used. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + + if( pxNewTCB != NULL ) + { + memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + + /* Allocate space for the stack used by the task being created. + * The base of the stack memory stored in the TCB so the task can + * be deleted later if required. */ + pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + if( pxNewTCB->pxStack == NULL ) + { + /* Could not allocate the stack. Delete the allocated TCB. */ + vPortFree( pxNewTCB ); + pxNewTCB = NULL; + } + } + } + #else /* portSTACK_GROWTH */ + { + StackType_t * pxStack; + + /* Allocate space for the stack used by the task being created. */ + pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ + + if( pxStack != NULL ) + { + /* Allocate space for the TCB. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ + + if( pxNewTCB != NULL ) + { + memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxStack; + } + else + { + /* The stack cannot be used as the TCB was not created. Free + * it again. */ + vPortFreeStack( pxStack ); + } + } + else + { + pxNewTCB = NULL; + } + } + #endif /* portSTACK_GROWTH */ + + if( pxNewTCB != NULL ) + { + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + * task was created dynamically in case it is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + TCB_t * pxNewTCB, + const MemoryRegion_t * const xRegions ) +{ + StackType_t * pxTopOfStack; + UBaseType_t x; + + #if ( portUSING_MPU_WRAPPERS == 1 ) + /* Should the task be created in privileged mode? */ + BaseType_t xRunPrivileged; + + if( ( uxPriority & portPRIVILEGE_BIT ) != 0U ) + { + xRunPrivileged = pdTRUE; + } + else + { + xRunPrivileged = pdFALSE; + } + uxPriority &= ~portPRIVILEGE_BIT; + #endif /* portUSING_MPU_WRAPPERS == 1 */ + + /* Avoid dependency on memset() if it is not required. */ + #if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) + { + /* Fill the stack with a known value to assist debugging. */ + ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); + } + #endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */ + + /* Calculate the top of stack address. This depends on whether the stack + * grows from high memory to low (as per the 80x86) or vice versa. + * portSTACK_GROWTH is used to make the result positive or negative as required + * by the port. */ + #if ( portSTACK_GROWTH < 0 ) + { + pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); + pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ + + /* Check the alignment of the calculated top of stack is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); + + #if ( configRECORD_STACK_HIGH_ADDRESS == 1 ) + { + /* Also record the stack's high address, which may assist + * debugging. */ + pxNewTCB->pxEndOfStack = pxTopOfStack; + } + #endif /* configRECORD_STACK_HIGH_ADDRESS */ + } + #else /* portSTACK_GROWTH */ + { + pxTopOfStack = pxNewTCB->pxStack; + + /* Check the alignment of the stack buffer is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); + + /* The other extreme of the stack space is required if stack checking is + * performed. */ + pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); + } + #endif /* portSTACK_GROWTH */ + + /* Store the task name in the TCB. */ + if( pcName != NULL ) + { + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + { + pxNewTCB->pcTaskName[ x ] = pcName[ x ]; + + /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than + * configMAX_TASK_NAME_LEN characters just in case the memory after the + * string is not accessible (extremely unlikely). */ + if( pcName[ x ] == ( char ) 0x00 ) + { + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Ensure the name string is terminated in the case that the string length + * was greater or equal to configMAX_TASK_NAME_LEN. */ + pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* This is used as an array index so must ensure it's not too large. */ + configASSERT( uxPriority < configMAX_PRIORITIES ); + + if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + { + uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxNewTCB->uxPriority = uxPriority; + #if ( configUSE_MUTEXES == 1 ) + { + pxNewTCB->uxBasePriority = uxPriority; + } + #endif /* configUSE_MUTEXES */ + + vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); + vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); + + /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get + * back to the containing TCB from a generic item in a list. */ + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); + + #if ( portUSING_MPU_WRAPPERS == 1 ) + { + vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth ); + } + #else + { + /* Avoid compiler warning about unreferenced parameter. */ + ( void ) xRegions; + } + #endif + + #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) ) + { + /* Allocate and initialize memory for the task's TLS Block. */ + configINIT_TLS_BLOCK( pxNewTCB->xTLSBlock ); + } + #endif + + /* Initialize the TCB stack to look as if the task was already running, + * but had been interrupted by the scheduler. The return address is set + * to the start of the task function. Once the stack has been initialised + * the top of stack variable is updated. */ + #if ( portUSING_MPU_WRAPPERS == 1 ) + { + /* If the port has capability to detect stack overflow, + * pass the stack end address to the stack initialization + * function as well. */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + { + #if ( portSTACK_GROWTH < 0 ) + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #else /* portSTACK_GROWTH */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ + } + #else /* portUSING_MPU_WRAPPERS */ + { + /* If the port has capability to detect stack overflow, + * pass the stack end address to the stack initialization + * function as well. */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + { + #if ( portSTACK_GROWTH < 0 ) + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters ); + } + #else /* portSTACK_GROWTH */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters ); + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ + } + #endif /* portUSING_MPU_WRAPPERS */ + + if( pxCreatedTask != NULL ) + { + /* Pass the handle out in an anonymous way. The handle can be used to + * change the created task's priority, delete the created task, etc.*/ + *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) +{ + /* Ensure interrupts don't access the task lists while the lists are being + * updated. */ + taskENTER_CRITICAL(); + { + uxCurrentNumberOfTasks++; + + if( pxCurrentTCB == NULL ) + { + /* There are no other tasks, or all the other tasks are in + * the suspended state - make this the current task. */ + pxCurrentTCB = pxNewTCB; + + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + { + /* This is the first task to be created so do the preliminary + * initialisation required. We will not recover if this call + * fails, but we will report the failure. */ + prvInitialiseTaskLists(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If the scheduler is not already running, make this task the + * current task if it is the highest priority task to be created + * so far. */ + if( xSchedulerRunning == pdFALSE ) + { + if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) + { + pxCurrentTCB = pxNewTCB; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + uxTaskNumber++; + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Add a counter into the TCB for tracing only. */ + pxNewTCB->uxTCBNumber = uxTaskNumber; + } + #endif /* configUSE_TRACE_FACILITY */ + traceTASK_CREATE( pxNewTCB ); + + prvAddTaskToReadyList( pxNewTCB ); + + portSETUP_TCB( pxNewTCB ); + } + taskEXIT_CRITICAL(); + + if( xSchedulerRunning != pdFALSE ) + { + /* If the created task is of a higher priority than the current task + * then it should run now. */ + if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) + { + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + void vTaskDelete( TaskHandle_t xTaskToDelete ) + { + TCB_t * pxTCB; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the calling task that is + * being deleted. */ + pxTCB = prvGetTCBFromHandle( xTaskToDelete ); + + /* Remove task from the ready/delayed list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + taskRESET_READY_PRIORITY( pxTCB->uxPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Is the task waiting on an event also? */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Increment the uxTaskNumber also so kernel aware debuggers can + * detect that the task lists need re-generating. This is done before + * portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will + * not return. */ + uxTaskNumber++; + + if( pxTCB == pxCurrentTCB ) + { + /* A task is deleting itself. This cannot complete within the + * task itself, as a context switch to another task is required. + * Place the task in the termination list. The idle task will + * check the termination list and free up any memory allocated by + * the scheduler for the TCB and stack of the deleted task. */ + vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) ); + + /* Increment the ucTasksDeleted variable so the idle task knows + * there is a task that has been deleted and that it should therefore + * check the xTasksWaitingTermination list. */ + ++uxDeletedTasksWaitingCleanUp; + + /* Call the delete hook before portPRE_TASK_DELETE_HOOK() as + * portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */ + traceTASK_DELETE( pxTCB ); + + /* The pre-delete hook is primarily for the Windows simulator, + * in which Windows specific clean up operations are performed, + * after which it is not possible to yield away from this task - + * hence xYieldPending is used to latch that a context switch is + * required. */ + portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending ); + } + else + { + --uxCurrentNumberOfTasks; + traceTASK_DELETE( pxTCB ); + + /* Reset the next expected unblock time in case it referred to + * the task that has just been deleted. */ + prvResetNextTaskUnblockTime(); + } + } + taskEXIT_CRITICAL(); + + /* If the task is not deleting itself, call prvDeleteTCB from outside of + * critical section. If a task deletes itself, prvDeleteTCB is called + * from prvCheckTasksWaitingTermination which is called from Idle task. */ + if( pxTCB != pxCurrentTCB ) + { + prvDeleteTCB( pxTCB ); + } + + /* Force a reschedule if it is the currently running task that has just + * been deleted. */ + if( xSchedulerRunning != pdFALSE ) + { + if( pxTCB == pxCurrentTCB ) + { + configASSERT( uxSchedulerSuspended == 0 ); + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) + { + TickType_t xTimeToWake; + BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE; + + configASSERT( pxPreviousWakeTime ); + configASSERT( ( xTimeIncrement > 0U ) ); + configASSERT( uxSchedulerSuspended == 0 ); + + vTaskSuspendAll(); + { + /* Minor optimisation. The tick count cannot change in this + * block. */ + const TickType_t xConstTickCount = xTickCount; + + /* Generate the tick time at which the task wants to wake. */ + xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; + + if( xConstTickCount < *pxPreviousWakeTime ) + { + /* The tick count has overflowed since this function was + * lasted called. In this case the only time we should ever + * actually delay is if the wake time has also overflowed, + * and the wake time is greater than the tick time. When this + * is the case it is as if neither time had overflowed. */ + if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) ) + { + xShouldDelay = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* The tick time has not overflowed. In this case we will + * delay if either the wake time has overflowed, and/or the + * tick time is less than the wake time. */ + if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) ) + { + xShouldDelay = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Update the wake time ready for the next call. */ + *pxPreviousWakeTime = xTimeToWake; + + if( xShouldDelay != pdFALSE ) + { + traceTASK_DELAY_UNTIL( xTimeToWake ); + + /* prvAddCurrentTaskToDelayedList() needs the block time, not + * the time to wake, so subtract the current tick count. */ + prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + xAlreadyYielded = xTaskResumeAll(); + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + * have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xShouldDelay; + } + +#endif /* INCLUDE_xTaskDelayUntil */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelay == 1 ) + + void vTaskDelay( const TickType_t xTicksToDelay ) + { + BaseType_t xAlreadyYielded = pdFALSE; + + /* A delay time of zero just forces a reschedule. */ + if( xTicksToDelay > ( TickType_t ) 0U ) + { + configASSERT( uxSchedulerSuspended == 0 ); + vTaskSuspendAll(); + { + traceTASK_DELAY(); + + /* A task that is removed from the event list while the + * scheduler is suspended will not get placed in the ready + * list or removed from the blocked list until the scheduler + * is resumed. + * + * This task cannot be in an event list as it is the currently + * executing task. */ + prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); + } + xAlreadyYielded = xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + * have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* INCLUDE_vTaskDelay */ +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) ) + + eTaskState eTaskGetState( TaskHandle_t xTask ) + { + eTaskState eReturn; + List_t const * pxStateList; + List_t const * pxDelayedList; + List_t const * pxOverflowedDelayedList; + const TCB_t * const pxTCB = xTask; + + configASSERT( pxTCB ); + + if( pxTCB == pxCurrentTCB ) + { + /* The task calling this function is querying its own state. */ + eReturn = eRunning; + } + else + { + taskENTER_CRITICAL(); + { + pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) ); + pxDelayedList = pxDelayedTaskList; + pxOverflowedDelayedList = pxOverflowDelayedTaskList; + } + taskEXIT_CRITICAL(); + + if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) ) + { + /* The task being queried is referenced from one of the Blocked + * lists. */ + eReturn = eBlocked; + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + else if( pxStateList == &xSuspendedTaskList ) + { + /* The task being queried is referenced from the suspended + * list. Is it genuinely suspended or is it blocked + * indefinitely? */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ) + { + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + BaseType_t x; + + /* The task does not appear on the event list item of + * and of the RTOS objects, but could still be in the + * blocked state if it is waiting on its notification + * rather than waiting on an object. If not, is + * suspended. */ + eReturn = eSuspended; + + for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + { + if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) + { + eReturn = eBlocked; + break; + } + } + } + #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + { + eReturn = eSuspended; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + } + else + { + eReturn = eBlocked; + } + } + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ + + #if ( INCLUDE_vTaskDelete == 1 ) + else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) ) + { + /* The task being queried is referenced from the deleted + * tasks list, or it is not referenced from any lists at + * all. */ + eReturn = eDeleted; + } + #endif + + else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */ + { + /* If the task is not in any other state, it must be in the + * Ready (including pending ready) state. */ + eReturn = eReady; + } + } + + return eReturn; + } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */ + +#endif /* INCLUDE_eTaskGetState */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) + { + TCB_t const * pxTCB; + UBaseType_t uxReturn; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the priority of the task + * that called uxTaskPriorityGet() that is being queried. */ + pxTCB = prvGetTCBFromHandle( xTask ); + uxReturn = pxTCB->uxPriority; + } + taskEXIT_CRITICAL(); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskPriorityGet */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) + { + TCB_t const * pxTCB; + UBaseType_t uxReturn, uxSavedInterruptState; + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* If null is passed in here then it is the priority of the calling + * task that is being queried. */ + pxTCB = prvGetTCBFromHandle( xTask ); + uxReturn = pxTCB->uxPriority; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskPriorityGet */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskPrioritySet == 1 ) + + void vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) + { + TCB_t * pxTCB; + UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry; + BaseType_t xYieldRequired = pdFALSE; + + configASSERT( uxNewPriority < configMAX_PRIORITIES ); + + /* Ensure the new priority is valid. */ + if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + { + uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the priority of the calling + * task that is being changed. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + traceTASK_PRIORITY_SET( pxTCB, uxNewPriority ); + + #if ( configUSE_MUTEXES == 1 ) + { + uxCurrentBasePriority = pxTCB->uxBasePriority; + } + #else + { + uxCurrentBasePriority = pxTCB->uxPriority; + } + #endif + + if( uxCurrentBasePriority != uxNewPriority ) + { + /* The priority change may have readied a task of higher + * priority than the calling task. */ + if( uxNewPriority > uxCurrentBasePriority ) + { + if( pxTCB != pxCurrentTCB ) + { + /* The priority of a task other than the currently + * running task is being raised. Is the priority being + * raised above that of the running task? */ + if( uxNewPriority >= pxCurrentTCB->uxPriority ) + { + xYieldRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* The priority of the running task is being raised, + * but the running task must already be the highest + * priority task able to run so no yield is required. */ + } + } + else if( pxTCB == pxCurrentTCB ) + { + /* Setting the priority of the running task down means + * there may now be another task of higher priority that + * is ready to execute. */ + xYieldRequired = pdTRUE; + } + else + { + /* Setting the priority of any other task down does not + * require a yield as the running task must be above the + * new priority of the task being modified. */ + } + + /* Remember the ready list the task might be referenced from + * before its uxPriority member is changed so the + * taskRESET_READY_PRIORITY() macro can function correctly. */ + uxPriorityUsedOnEntry = pxTCB->uxPriority; + + #if ( configUSE_MUTEXES == 1 ) + { + /* Only change the priority being used if the task is not + * currently using an inherited priority. */ + if( pxTCB->uxBasePriority == pxTCB->uxPriority ) + { + pxTCB->uxPriority = uxNewPriority; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The base priority gets set whatever. */ + pxTCB->uxBasePriority = uxNewPriority; + } + #else /* if ( configUSE_MUTEXES == 1 ) */ + { + pxTCB->uxPriority = uxNewPriority; + } + #endif /* if ( configUSE_MUTEXES == 1 ) */ + + /* Only reset the event list item value if the value is not + * being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + { + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the task is in the blocked or suspended list we need do + * nothing more than change its priority variable. However, if + * the task is in a ready list it needs to be removed and placed + * in the list appropriate to its new priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + /* The task is currently in its ready list - remove before + * adding it to its new ready list. As we are in a critical + * section we can do this even if the scheduler is suspended. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvReaddTaskToReadyList( pxTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xYieldRequired != pdFALSE ) + { + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Remove compiler warning about unused variables when the port + * optimised task selection is not being used. */ + ( void ) uxPriorityUsedOnEntry; + } + } + taskEXIT_CRITICAL(); + } + +#endif /* INCLUDE_vTaskPrioritySet */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + void vTaskSuspend( TaskHandle_t xTaskToSuspend ) + { + TCB_t * pxTCB; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the running task that is + * being suspended. */ + pxTCB = prvGetTCBFromHandle( xTaskToSuspend ); + + traceTASK_SUSPEND( pxTCB ); + + /* Remove task from the ready/delayed list and place in the + * suspended list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + taskRESET_READY_PRIORITY( pxTCB->uxPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Is the task waiting on an event also? */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMOVED_TASK_TO_SUSPENDED_LIST(pxTCB); + vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ); + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + BaseType_t x; + + for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + { + if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) + { + /* The task was blocked to wait for a notification, but is + * now suspended, so no notification was received. */ + pxTCB->ucNotifyState[ x ] = taskNOT_WAITING_NOTIFICATION; + } + } + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + } + taskEXIT_CRITICAL(); + + if( xSchedulerRunning != pdFALSE ) + { + /* Reset the next expected unblock time in case it referred to the + * task that is now in the Suspended state. */ + taskENTER_CRITICAL(); + { + prvResetNextTaskUnblockTime(); + } + taskEXIT_CRITICAL(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( pxTCB == pxCurrentTCB ) + { + if( xSchedulerRunning != pdFALSE ) + { + /* The current task has just been suspended. */ + configASSERT( uxSchedulerSuspended == 0 ); + portYIELD_WITHIN_API(); + } + else + { + /* The scheduler is not running, but the task that was pointed + * to by pxCurrentTCB has just been suspended and pxCurrentTCB + * must be adjusted to point to a different task. */ + if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */ + { + /* No other tasks are ready, so set pxCurrentTCB back to + * NULL so when the next task is created pxCurrentTCB will + * be set to point to it no matter what its relative priority + * is. */ + pxCurrentTCB = NULL; + } + else + { + vTaskSwitchContext(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* INCLUDE_vTaskSuspend */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) + { + BaseType_t xReturn = pdFALSE; + const TCB_t * const pxTCB = xTask; + + /* Accesses xPendingReadyList so must be called from a critical + * section. */ + + /* It does not make sense to check if the calling task is suspended. */ + configASSERT( xTask ); + + /* Is the task being resumed actually in the suspended list? */ + if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + /* Has the task already been resumed from within an ISR? */ + if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE ) + { + /* Is it in the suspended list because it is in the Suspended + * state, or because is is blocked with no timeout? */ + if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961. The cast is only redundant when NULL is used. */ + { + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */ + +#endif /* INCLUDE_vTaskSuspend */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + void vTaskResume( TaskHandle_t xTaskToResume ) + { + TCB_t * const pxTCB = xTaskToResume; + + /* It does not make sense to resume the calling task. */ + configASSERT( xTaskToResume ); + + /* The parameter cannot be NULL as it is impossible to resume the + * currently executing task. */ + if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) ) + { + taskENTER_CRITICAL(); + { + if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE ) + { + traceTASK_RESUME( pxTCB ); + + /* The ready list can be accessed even if the scheduler is + * suspended because this is inside a critical section. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + /* A higher priority task may have just been resumed. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + /* This yield may not cause the task just resumed to run, + * but will leave the lists in the correct state for the + * next yield. */ + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* INCLUDE_vTaskSuspend */ + +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) + + BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) + { + BaseType_t xYieldRequired = pdFALSE; + TCB_t * const pxTCB = xTaskToResume; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( xTaskToResume ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE ) + { + traceTASK_RESUME_FROM_ISR( pxTCB ); + + /* Check the ready lists can be accessed. */ + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + /* Ready lists can be accessed so move the task from the + * suspended list to the ready list directly. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + xYieldRequired = pdTRUE; + + /* Mark that a yield is pending in case the user is not + * using the return value to initiate a context switch + * from the ISR using portYIELD_FROM_ISR. */ + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + } + else + { + /* The delayed or ready lists cannot be accessed so the task + * is held in the pending ready list until the scheduler is + * unsuspended. */ + vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xYieldRequired; + } + +#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ +/*-----------------------------------------------------------*/ + +void vTaskStartScheduler( void ) +{ + BaseType_t xReturn; + + /* Add the idle task at the lowest priority. */ + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxIdleTaskTCBBuffer = NULL; + StackType_t * pxIdleTaskStackBuffer = NULL; + uint32_t ulIdleTaskStackSize; + + /* The Idle task is created using user provided RAM - obtain the + * address of the RAM then create the idle task. */ + vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); + xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, + configIDLE_TASK_NAME, + ulIdleTaskStackSize, + ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + pxIdleTaskStackBuffer, + pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ + + if( xIdleTaskHandle != NULL ) + { + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + /* The Idle task is being created using dynamically allocated RAM. */ + xReturn = xTaskCreate( prvIdleTask, + configIDLE_TASK_NAME, + configMINIMAL_STACK_SIZE, + ( void * ) NULL, + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + #if ( configUSE_TIMERS == 1 ) + { + if( xReturn == pdPASS ) + { + xReturn = xTimerCreateTimerTask(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TIMERS */ + + if( xReturn == pdPASS ) + { + /* freertos_tasks_c_additions_init() should only be called if the user + * definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is + * the only macro called by the function. */ + #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + { + freertos_tasks_c_additions_init(); + } + #endif + + /* Interrupts are turned off here, to ensure a tick does not occur + * before or during the call to xPortStartScheduler(). The stacks of + * the created tasks contain a status word with interrupts switched on + * so interrupts will automatically get re-enabled when the first task + * starts to run. */ + portDISABLE_INTERRUPTS(); + + #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) ) + { + /* Switch C-Runtime's TLS Block to point to the TLS + * block specific to the task that will run first. */ + configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); + } + #endif + + xNextTaskUnblockTime = portMAX_DELAY; + xSchedulerRunning = pdTRUE; + xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; + + /* If configGENERATE_RUN_TIME_STATS is defined then the following + * macro must be defined to configure the timer/counter used to generate + * the run time counter time base. NOTE: If configGENERATE_RUN_TIME_STATS + * is set to 0 and the following line fails to build then ensure you do not + * have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your + * FreeRTOSConfig.h file. */ + portCONFIGURE_TIMER_FOR_RUN_TIME_STATS(); + + traceTASK_SWITCHED_IN(); + + /* Setting up the timer tick is hardware specific and thus in the + * portable interface. */ + xPortStartScheduler(); + + /* In most cases, xPortStartScheduler() will not return. If it + * returns pdTRUE then there was not enough heap memory available + * to create either the Idle or the Timer task. If it returned + * pdFALSE, then the application called xTaskEndScheduler(). + * Most ports don't implement xTaskEndScheduler() as there is + * nothing to return to. */ + } + else + { + /* This line will only be reached if the kernel could not be started, + * because there was not enough FreeRTOS heap to create the idle task + * or the timer task. */ + configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); + } + + /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, + * meaning xIdleTaskHandle is not used anywhere else. */ + ( void ) xIdleTaskHandle; + + /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority + * from getting optimized out as it is no longer used by the kernel. */ + ( void ) uxTopUsedPriority; +} +/*-----------------------------------------------------------*/ + +void vTaskEndScheduler( void ) +{ + /* Stop the scheduler interrupts and call the portable scheduler end + * routine so the original ISRs can be restored if necessary. The port + * layer must ensure interrupts enable bit is left in the correct state. */ + portDISABLE_INTERRUPTS(); + xSchedulerRunning = pdFALSE; + vPortEndScheduler(); +} +/*----------------------------------------------------------*/ + +void vTaskSuspendAll( void ) +{ + /* A critical section is not required as the variable is of type + * BaseType_t. Please read Richard Barry's reply in the following link to a + * post in the FreeRTOS support forum before reporting this as a bug! - + * https://goo.gl/wu4acr */ + + /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that + * do not otherwise exhibit real time behaviour. */ + portSOFTWARE_BARRIER(); + + /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment + * is used to allow calls to vTaskSuspendAll() to nest. */ + ++uxSchedulerSuspended; + + /* Enforces ordering for ports and optimised compilers that may otherwise place + * the above increment elsewhere. */ + portMEMORY_BARRIER(); +} +/*----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE != 0 ) + + static TickType_t prvGetExpectedIdleTime( void ) + { + TickType_t xReturn; + UBaseType_t uxHigherPriorityReadyTasks = pdFALSE; + + /* uxHigherPriorityReadyTasks takes care of the case where + * configUSE_PREEMPTION is 0, so there may be tasks above the idle priority + * task that are in the Ready state, even though the idle task is + * running. */ + #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) + { + if( uxTopReadyPriority > tskIDLE_PRIORITY ) + { + uxHigherPriorityReadyTasks = pdTRUE; + } + } + #else + { + const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01; + + /* When port optimised task selection is used the uxTopReadyPriority + * variable is used as a bit map. If bits other than the least + * significant bit are set then there are tasks that have a priority + * above the idle priority that are in the Ready state. This takes + * care of the case where the co-operative scheduler is in use. */ + if( uxTopReadyPriority > uxLeastSignificantBit ) + { + uxHigherPriorityReadyTasks = pdTRUE; + } + } + #endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */ + + if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY ) + { + xReturn = 0; + } + else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 ) + { + /* There are other idle priority tasks in the ready state. If + * time slicing is used then the very next tick interrupt must be + * processed. */ + xReturn = 0; + } + else if( uxHigherPriorityReadyTasks != pdFALSE ) + { + /* There are tasks in the Ready state that have a priority above the + * idle priority. This path can only be reached if + * configUSE_PREEMPTION is 0. */ + xReturn = 0; + } + else + { + xReturn = xNextTaskUnblockTime - xTickCount; + } + + return xReturn; + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskResumeAll( void ) +{ + TCB_t * pxTCB = NULL; + BaseType_t xAlreadyYielded = pdFALSE; + + /* If uxSchedulerSuspended is zero then this function does not match a + * previous call to vTaskSuspendAll(). */ + configASSERT( uxSchedulerSuspended ); + + /* It is possible that an ISR caused a task to be removed from an event + * list while the scheduler was suspended. If this was the case then the + * removed task will have been added to the xPendingReadyList. Once the + * scheduler has been resumed it is safe to move all the pending ready + * tasks from this list into their appropriate ready list. */ + taskENTER_CRITICAL(); + { + --uxSchedulerSuspended; + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) + { + /* Move any readied tasks from the pending list into the + * appropriate ready list. */ + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + listREMOVE_ITEM( &( pxTCB->xEventListItem ) ); + portMEMORY_BARRIER(); + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + /* If the moved task has a priority higher than or equal to + * the current task then a yield must be performed. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( pxTCB != NULL ) + { + /* A task was unblocked while the scheduler was suspended, + * which may have prevented the next unblock time from being + * re-calculated, in which case re-calculate it now. Mainly + * important for low power tickless implementations, where + * this can prevent an unnecessary exit from low power + * state. */ + prvResetNextTaskUnblockTime(); + } + + /* If any ticks occurred while the scheduler was suspended then + * they should be processed now. This ensures the tick count does + * not slip, and that any delayed tasks are resumed at the correct + * time. */ + { + TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ + + if( xPendedCounts > ( TickType_t ) 0U ) + { + do + { + if( xTaskIncrementTick() != pdFALSE ) + { + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --xPendedCounts; + } while( xPendedCounts > ( TickType_t ) 0U ); + + xPendedTicks = 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xYieldPending != pdFALSE ) + { + #if ( configUSE_PREEMPTION != 0 ) + { + xAlreadyYielded = pdTRUE; + } + #endif + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + return xAlreadyYielded; +} +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCount( void ) +{ + TickType_t xTicks; + + /* Critical section required if running on a 16 bit processor. */ + portTICK_TYPE_ENTER_CRITICAL(); + { + xTicks = xTickCount; + } + portTICK_TYPE_EXIT_CRITICAL(); + + return xTicks; +} +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCountFromISR( void ) +{ + TickType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR(); + { + xReturn = xTickCount; + } + portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxTaskGetNumberOfTasks( void ) +{ + /* A critical section is not required because the variables are of type + * BaseType_t. */ + return uxCurrentNumberOfTasks; +} +/*-----------------------------------------------------------*/ + +char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +{ + TCB_t * pxTCB; + + /* If null is passed in here then the name of the calling task is being + * queried. */ + pxTCB = prvGetTCBFromHandle( xTaskToQuery ); + configASSERT( pxTCB ); + return &( pxTCB->pcTaskName[ 0 ] ); +} +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetHandle == 1 ) + + static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList, + const char pcNameToQuery[] ) + { + TCB_t * pxNextTCB; + TCB_t * pxFirstTCB; + TCB_t * pxReturn = NULL; + UBaseType_t x; + char cNextChar; + BaseType_t xBreakLoop; + + /* This function is called with the scheduler suspended. */ + + if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + do + { + listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + /* Check each character in the name looking for a match or + * mismatch. */ + xBreakLoop = pdFALSE; + + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + { + cNextChar = pxNextTCB->pcTaskName[ x ]; + + if( cNextChar != pcNameToQuery[ x ] ) + { + /* Characters didn't match. */ + xBreakLoop = pdTRUE; + } + else if( cNextChar == ( char ) 0x00 ) + { + /* Both strings terminated, a match must have been + * found. */ + pxReturn = pxNextTCB; + xBreakLoop = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xBreakLoop != pdFALSE ) + { + break; + } + } + + if( pxReturn != NULL ) + { + /* The handle has been found. */ + break; + } + } while( pxNextTCB != pxFirstTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return pxReturn; + } + +#endif /* INCLUDE_xTaskGetHandle */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetHandle == 1 ) + + TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + UBaseType_t uxQueue = configMAX_PRIORITIES; + TCB_t * pxTCB; + + /* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */ + configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN ); + + vTaskSuspendAll(); + { + /* Search the ready lists. */ + do + { + uxQueue--; + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery ); + + if( pxTCB != NULL ) + { + /* Found the handle. */ + break; + } + } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + /* Search the delayed lists. */ + if( pxTCB == NULL ) + { + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery ); + } + + if( pxTCB == NULL ) + { + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery ); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( pxTCB == NULL ) + { + /* Search the suspended list. */ + pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery ); + } + } + #endif + + #if ( INCLUDE_vTaskDelete == 1 ) + { + if( pxTCB == NULL ) + { + /* Search the deleted list. */ + pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery ); + } + } + #endif + } + ( void ) xTaskResumeAll(); + + return pxTCB; + } + +#endif /* INCLUDE_xTaskGetHandle */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) + { + UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES; + + vTaskSuspendAll(); + { + /* Is there a space in the array for each task in the system? */ + if( uxArraySize >= uxCurrentNumberOfTasks ) + { + /* Fill in an TaskStatus_t structure with information on each + * task in the Ready state. */ + do + { + uxQueue--; + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady ); + } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + /* Fill in an TaskStatus_t structure with information on each + * task in the Blocked state. */ + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked ); + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked ); + + #if ( INCLUDE_vTaskDelete == 1 ) + { + /* Fill in an TaskStatus_t structure with information on + * each task that has been deleted but not yet cleaned up. */ + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted ); + } + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + /* Fill in an TaskStatus_t structure with information on + * each task in the Suspended state. */ + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended ); + } + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + if( pulTotalRunTime != NULL ) + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) ); + #else + *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + } + } + #else /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ + { + if( pulTotalRunTime != NULL ) + { + *pulTotalRunTime = 0; + } + } + #endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + ( void ) xTaskResumeAll(); + + return uxTask; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t xTaskGetIdleTaskHandle( void ) + { + /* If xTaskGetIdleTaskHandle() is called before the scheduler has been + * started, then xIdleTaskHandle will be NULL. */ + configASSERT( ( xIdleTaskHandle != NULL ) ); + return xIdleTaskHandle; + } + +#endif /* INCLUDE_xTaskGetIdleTaskHandle */ +/*----------------------------------------------------------*/ + +/* This conditional compilation should use inequality to 0, not equality to 1. + * This is to ensure vTaskStepTick() is available when user defined low power mode + * implementations require configUSE_TICKLESS_IDLE to be set to a value other than + * 1. */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + + void vTaskStepTick( TickType_t xTicksToJump ) + { + /* Correct the tick count value after a period during which the tick + * was suppressed. Note this does *not* call the tick hook function for + * each stepped tick. */ + configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime ); + + if( ( xTickCount + xTicksToJump ) == xNextTaskUnblockTime ) + { + /* Arrange for xTickCount to reach xNextTaskUnblockTime in + * xTaskIncrementTick() when the scheduler resumes. This ensures + * that any delayed tasks are resumed at the correct time. */ + configASSERT( uxSchedulerSuspended ); + configASSERT( xTicksToJump != ( TickType_t ) 0 ); + + /* Prevent the tick interrupt modifying xPendedTicks simultaneously. */ + taskENTER_CRITICAL(); + { + xPendedTicks++; + } + taskEXIT_CRITICAL(); + xTicksToJump--; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xTickCount += xTicksToJump; + traceINCREASE_TICK_COUNT( xTicksToJump ); + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) +{ + BaseType_t xYieldOccurred; + + /* Must not be called with the scheduler suspended as the implementation + * relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */ + configASSERT( uxSchedulerSuspended == 0 ); + + /* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when + * the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */ + vTaskSuspendAll(); + + /* Prevent the tick interrupt modifying xPendedTicks simultaneously. */ + taskENTER_CRITICAL(); + { + xPendedTicks += xTicksToCatchUp; + } + taskEXIT_CRITICAL(); + xYieldOccurred = xTaskResumeAll(); + + return xYieldOccurred; +} +/*----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) + { + TCB_t * pxTCB = xTask; + BaseType_t xReturn; + + configASSERT( pxTCB ); + + vTaskSuspendAll(); + { + /* A task can only be prematurely removed from the Blocked state if + * it is actually in the Blocked state. */ + if( eTaskGetState( xTask ) == eBlocked ) + { + xReturn = pdPASS; + + /* Remove the reference to the task from the blocked list. An + * interrupt won't touch the xStateListItem because the + * scheduler is suspended. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + + /* Is the task waiting on an event also? If so remove it from + * the event list too. Interrupts can touch the event list item, + * even though the scheduler is suspended, so a critical section + * is used. */ + taskENTER_CRITICAL(); + { + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + + /* This lets the task know it was forcibly removed from the + * blocked state so it should not re-evaluate its block time and + * then block again. */ + pxTCB->ucDelayAborted = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + /* Place the unblocked task into the appropriate ready list. */ + prvAddTaskToReadyList( pxTCB ); + + /* A task being unblocked cannot cause an immediate context + * switch if preemption is turned off. */ + #if ( configUSE_PREEMPTION == 1 ) + { + /* Preemption is on, but a context switch should only be + * performed if the unblocked task has a priority that is + * higher than the currently executing task. */ + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* Pend the yield to be performed when the scheduler + * is unsuspended. */ + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + } + else + { + xReturn = pdFAIL; + } + } + ( void ) xTaskResumeAll(); + + return xReturn; + } + +#endif /* INCLUDE_xTaskAbortDelay */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskIncrementTick( void ) +{ + TCB_t * pxTCB; + TickType_t xItemValue; + BaseType_t xSwitchRequired = pdFALSE; + + /* Called by the portable layer each time a tick interrupt occurs. + * Increments the tick then checks to see if the new tick value will cause any + * tasks to be unblocked. */ + traceTASK_INCREMENT_TICK( xTickCount ); + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + /* Minor optimisation. The tick count cannot change in this + * block. */ + const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; + + /* Increment the RTOS tick, switching the delayed and overflowed + * delayed lists if it wraps to 0. */ + xTickCount = xConstTickCount; + + if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ + { + taskSWITCH_DELAYED_LISTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* See if this tick has made a timeout expire. Tasks are stored in + * the queue in the order of their wake time - meaning once one task + * has been found whose block time has not expired there is no need to + * look any further down the list. */ + if( xConstTickCount >= xNextTaskUnblockTime ) + { + for( ; ; ) + { + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + { + /* The delayed list is empty. Set xNextTaskUnblockTime + * to the maximum possible value so it is extremely + * unlikely that the + * if( xTickCount >= xNextTaskUnblockTime ) test will pass + * next time through. */ + xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + break; + } + else + { + /* The delayed list is not empty, get the value of the + * item at the head of the delayed list. This is the time + * at which the task at the head of the delayed list must + * be removed from the Blocked state. */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); + + if( xConstTickCount < xItemValue ) + { + /* It is not time to unblock this item yet, but the + * item value is the time at which the task at the head + * of the blocked list must be removed from the Blocked + * state - so record the item value in + * xNextTaskUnblockTime. */ + xNextTaskUnblockTime = xItemValue; + break; /*lint !e9011 Code structure here is deemed easier to understand with multiple breaks. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* It is time to remove the item from the Blocked state. */ + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + + /* Is the task waiting on an event also? If so remove + * it from the event list. */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + listREMOVE_ITEM( &( pxTCB->xEventListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Place the unblocked task into the appropriate ready + * list. */ + prvAddTaskToReadyList( pxTCB ); + + /* A task being unblocked cannot cause an immediate + * context switch if preemption is turned off. */ + #if ( configUSE_PREEMPTION == 1 ) + { + /* Preemption is on, but a context switch should + * only be performed if the unblocked task's + * priority is higher than the currently executing + * task. + * The case of equal priority tasks sharing + * processing time (which happens when both + * preemption and time slicing are on) is + * handled below.*/ + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + } + } + } + + /* Tasks of equal priority to the currently running task will share + * processing time (time slice) if preemption is on, and the application + * writer has not explicitly turned time slicing off. */ + #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) + { + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */ + + #if ( configUSE_TICK_HOOK == 1 ) + { + /* Guard against the tick hook being called when the pended tick + * count is being unwound (when the scheduler is being unlocked). */ + if( xPendedTicks == ( TickType_t ) 0 ) + { + vApplicationTickHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TICK_HOOK */ + + #if ( configUSE_PREEMPTION == 1 ) + { + if( xYieldPending != pdFALSE ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + } + else + { + ++xPendedTicks; + + /* The tick hook gets called at regular intervals, even if the + * scheduler is locked. */ + #if ( configUSE_TICK_HOOK == 1 ) + { + vApplicationTickHook(); + } + #endif + } + + return xSwitchRequired; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) + { + TCB_t * xTCB; + + /* If xTask is NULL then it is the task hook of the calling task that is + * getting set. */ + if( xTask == NULL ) + { + xTCB = ( TCB_t * ) pxCurrentTCB; + } + else + { + xTCB = xTask; + } + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + taskENTER_CRITICAL(); + { + xTCB->pxTaskTag = pxHookFunction; + } + taskEXIT_CRITICAL(); + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + TaskHookFunction_t xReturn; + + /* If xTask is NULL then set the calling task's hook. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + taskENTER_CRITICAL(); + { + xReturn = pxTCB->pxTaskTag; + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + TaskHookFunction_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + /* If xTask is NULL then set the calling task's hook. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + xReturn = pxTCB->pxTaskTag; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) + { + TCB_t * xTCB; + BaseType_t xReturn; + + /* If xTask is NULL then we are calling our own task hook. */ + if( xTask == NULL ) + { + xTCB = pxCurrentTCB; + } + else + { + xTCB = xTask; + } + + if( xTCB->pxTaskTag != NULL ) + { + xReturn = xTCB->pxTaskTag( pvParameter ); + } + else + { + xReturn = pdFAIL; + } + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +void vTaskSwitchContext( void ) +{ + if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) + { + /* The scheduler is currently suspended - do not allow a context + * switch. */ + xYieldPending = pdTRUE; + } + else + { + xYieldPending = pdFALSE; + traceTASK_SWITCHED_OUT(); + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime ); + #else + ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + + /* Add the amount of time the task has been running to the + * accumulated time so far. The time the task started running was + * stored in ulTaskSwitchedInTime. Note that there is no overflow + * protection here so count values are only valid until the timer + * overflows. The guard against negative values is to protect + * against suspect run time stat counter implementations - which + * are provided by the application, not the kernel. */ + if( ulTotalRunTime > ulTaskSwitchedInTime ) + { + pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ulTaskSwitchedInTime = ulTotalRunTime; + } + #endif /* configGENERATE_RUN_TIME_STATS */ + + /* Check for stack overflow, if configured. */ + taskCHECK_FOR_STACK_OVERFLOW(); + + /* Before the currently running task is switched out, save its errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) + { + pxCurrentTCB->iTaskErrno = FreeRTOS_errno; + } + #endif + + /* Select a new task to run using either the generic C or port + * optimised asm code. */ + taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + traceTASK_SWITCHED_IN(); + + /* After the new task is switched in, update the global errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) + { + FreeRTOS_errno = pxCurrentTCB->iTaskErrno; + } + #endif + + #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) ) + { + /* Switch C-Runtime's TLS Block to point to the TLS + * Block specific to this task. */ + configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); + } + #endif + } +} +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnEventList( List_t * const pxEventList, + const TickType_t xTicksToWait ) +{ + configASSERT( pxEventList ); + + /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE + * SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */ + + /* Place the event list item of the TCB in the appropriate event list. + * This is placed in the list in priority order so the highest priority task + * is the first to be woken by the event. + * + * Note: Lists are sorted in ascending order by ListItem_t.xItemValue. + * Normally, the xItemValue of a TCB's ListItem_t members is: + * xItemValue = ( configMAX_PRIORITIES - uxPriority ) + * Therefore, the event list is sorted in descending priority order. + * + * The queue that contains the event list is locked, preventing + * simultaneous access from interrupts. */ + vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, + const TickType_t xItemValue, + const TickType_t xTicksToWait ) +{ + configASSERT( pxEventList ); + + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by + * the event groups implementation. */ + configASSERT( uxSchedulerSuspended != 0 ); + + /* Store the item value in the event list item. It is safe to access the + * event list item here as interrupts won't access the event list item of a + * task that is not in the Blocked state. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE ); + + /* Place the event list item of the TCB at the end of the appropriate event + * list. It is safe to access the event list here because it is part of an + * event group implementation - and interrupts don't access event groups + * directly (instead they access them indirectly by pending function calls to + * the task level). */ + listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + + void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) + { + configASSERT( pxEventList ); + + /* This function should not be called by application code hence the + * 'Restricted' in its name. It is not part of the public API. It is + * designed for use by kernel code, and has special calling requirements - + * it should be called with the scheduler suspended. */ + + + /* Place the event list item of the TCB in the appropriate event list. + * In this case it is assume that this is the only task that is going to + * be waiting on this event list, so the faster vListInsertEnd() function + * can be used in place of vListInsert. */ + listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + + /* If the task should block indefinitely then set the block time to a + * value that will be recognised as an indefinite delay inside the + * prvAddCurrentTaskToDelayedList() function. */ + if( xWaitIndefinitely != pdFALSE ) + { + xTicksToWait = portMAX_DELAY; + } + + traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); + prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); + } + +#endif /* configUSE_TIMERS */ +/*-----------------------------------------------------------*/ + +BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) +{ + TCB_t * pxUnblockedTCB; + BaseType_t xReturn; + + /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION. It can also be + * called from a critical section within an ISR. */ + + /* The event list is sorted in priority order, so the first in the list can + * be removed as it is known to be the highest priority. Remove the TCB from + * the delayed list, and add it to the ready list. + * + * If an event is for a queue that is locked then this function will never + * get called - the lock count on the queue will get modified instead. This + * means exclusive access to the event list is guaranteed here. + * + * This function assumes that a check has already been made to ensure that + * pxEventList is not empty. */ + pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + configASSERT( pxUnblockedTCB ); + listREMOVE_ITEM( &( pxUnblockedTCB->xEventListItem ) ); + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxUnblockedTCB ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + * might be set to the blocked task's time out time. If the task is + * unblocked for a reason other than a timeout xNextTaskUnblockTime is + * normally left unchanged, because it is automatically reset to a new + * value when the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter sleep mode + * at the earliest possible time - so reset xNextTaskUnblockTime here to + * ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + } + else + { + /* The delayed and ready lists cannot be accessed, so hold this task + * pending until the scheduler is resumed. */ + listINSERT_END( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); + } + + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* Return true if the task removed from the event list has a higher + * priority than the calling task. This allows the calling task to know if + * it should force a context switch now. */ + xReturn = pdTRUE; + + /* Mark that a yield is pending in case the user is not using the + * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ + xYieldPending = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, + const TickType_t xItemValue ) +{ + TCB_t * pxUnblockedTCB; + + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by + * the event flags implementation. */ + configASSERT( uxSchedulerSuspended != pdFALSE ); + + /* Store the new item value in the event list. */ + listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE ); + + /* Remove the event list form the event flag. Interrupts do not access + * event flags. */ + pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + configASSERT( pxUnblockedTCB ); + listREMOVE_ITEM( pxEventListItem ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + * might be set to the blocked task's time out time. If the task is + * unblocked for a reason other than a timeout xNextTaskUnblockTime is + * normally left unchanged, because it is automatically reset to a new + * value when the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter sleep mode + * at the earliest possible time - so reset xNextTaskUnblockTime here to + * ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + + /* Remove the task from the delayed list and add it to the ready list. The + * scheduler is suspended so interrupts will not be accessing the ready + * lists. */ + listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxUnblockedTCB ); + + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The unblocked task has a priority above that of the calling task, so + * a context switch is required. This function is called with the + * scheduler suspended so xYieldPending is set so the context switch + * occurs immediately that the scheduler is resumed (unsuspended). */ + xYieldPending = pdTRUE; + } +} +/*-----------------------------------------------------------*/ + +void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) +{ + configASSERT( pxTimeOut ); + taskENTER_CRITICAL(); + { + pxTimeOut->xOverflowCount = xNumOfOverflows; + pxTimeOut->xTimeOnEntering = xTickCount; + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) +{ + /* For internal use only as it does not use a critical section. */ + pxTimeOut->xOverflowCount = xNumOfOverflows; + pxTimeOut->xTimeOnEntering = xTickCount; +} +/*-----------------------------------------------------------*/ + +BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) +{ + BaseType_t xReturn; + + configASSERT( pxTimeOut ); + configASSERT( pxTicksToWait ); + + taskENTER_CRITICAL(); + { + /* Minor optimisation. The tick count cannot change in this block. */ + const TickType_t xConstTickCount = xTickCount; + const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE ) + { + /* The delay was aborted, which is not the same as a time out, + * but has the same result. */ + pxCurrentTCB->ucDelayAborted = pdFALSE; + xReturn = pdTRUE; + } + else + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + if( *pxTicksToWait == portMAX_DELAY ) + { + /* If INCLUDE_vTaskSuspend is set to 1 and the block time + * specified is the maximum block time then the task should block + * indefinitely, and therefore never time out. */ + xReturn = pdFALSE; + } + else + #endif + + if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ + { + /* The tick count is greater than the time at which + * vTaskSetTimeout() was called, but has also overflowed since + * vTaskSetTimeOut() was called. It must have wrapped all the way + * around and gone past again. This passed since vTaskSetTimeout() + * was called. */ + xReturn = pdTRUE; + *pxTicksToWait = ( TickType_t ) 0; + } + else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ + { + /* Not a genuine timeout. Adjust parameters for time remaining. */ + *pxTicksToWait -= xElapsedTime; + vTaskInternalSetTimeOutState( pxTimeOut ); + xReturn = pdFALSE; + } + else + { + *pxTicksToWait = ( TickType_t ) 0; + xReturn = pdTRUE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vTaskMissedYield( void ) +{ + xYieldPending = pdTRUE; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) + { + UBaseType_t uxReturn; + TCB_t const * pxTCB; + + if( xTask != NULL ) + { + pxTCB = xTask; + uxReturn = pxTCB->uxTaskNumber; + } + else + { + uxReturn = 0U; + } + + return uxReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vTaskSetTaskNumber( TaskHandle_t xTask, + const UBaseType_t uxHandle ) + { + TCB_t * pxTCB; + + if( xTask != NULL ) + { + pxTCB = xTask; + pxTCB->uxTaskNumber = uxHandle; + } + } + +#endif /* configUSE_TRACE_FACILITY */ + +/* + * ----------------------------------------------------------- + * The Idle task. + * ---------------------------------------------------------- + * + * The portTASK_FUNCTION() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION( prvIdleTask, pvParameters ) +{ + /* Stop warnings. */ + ( void ) pvParameters; + + /** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE + * SCHEDULER IS STARTED. **/ + + /* In case a task that has a secure context deletes itself, in which case + * the idle task is responsible for deleting the task's secure context, if + * any. */ + portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE ); + + for( ; ; ) + { + /* See if any tasks have deleted themselves - if so then the idle task + * is responsible for freeing the deleted task's TCB and stack. */ + prvCheckTasksWaitingTermination(); + + #if ( configUSE_PREEMPTION == 0 ) + { + /* If we are not using preemption we keep forcing a task switch to + * see if any other task has become available. If we are using + * preemption we don't need to do this as any task becoming available + * will automatically get the processor anyway. */ + taskYIELD(); + } + #endif /* configUSE_PREEMPTION */ + + #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) + { + /* When using preemption tasks of equal priority will be + * timesliced. If a task that is sharing the idle priority is ready + * to run then the idle task should yield before the end of the + * timeslice. + * + * A critical region is not required here as we are just reading from + * the list, and an occasional incorrect value will not matter. If + * the ready list at the idle priority contains more than one task + * then a task other than the idle task is ready to execute. */ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) + { + taskYIELD(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */ + + #if ( configUSE_IDLE_HOOK == 1 ) + { + extern void vApplicationIdleHook( void ); + + /* Call the user defined function from within the idle task. This + * allows the application designer to add background functionality + * without the overhead of a separate task. + * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, + * CALL A FUNCTION THAT MIGHT BLOCK. */ + vApplicationIdleHook(); + } + #endif /* configUSE_IDLE_HOOK */ + + /* This conditional compilation should use inequality to 0, not equality + * to 1. This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when + * user defined low power mode implementations require + * configUSE_TICKLESS_IDLE to be set to a value other than 1. */ + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + TickType_t xExpectedIdleTime; + + /* It is not desirable to suspend then resume the scheduler on + * each iteration of the idle task. Therefore, a preliminary + * test of the expected idle time is performed without the + * scheduler suspended. The result here is not necessarily + * valid. */ + xExpectedIdleTime = prvGetExpectedIdleTime(); + + if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + { + vTaskSuspendAll(); + { + /* Now the scheduler is suspended, the expected idle + * time can be sampled again, and this time its value can + * be used. */ + configASSERT( xNextTaskUnblockTime >= xTickCount ); + xExpectedIdleTime = prvGetExpectedIdleTime(); + + /* Define the following macro to set xExpectedIdleTime to 0 + * if the application does not want + * portSUPPRESS_TICKS_AND_SLEEP() to be called. */ + configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime ); + + if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + { + traceLOW_POWER_IDLE_BEGIN(); + portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ); + traceLOW_POWER_IDLE_END(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + ( void ) xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TICKLESS_IDLE */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE != 0 ) + + eSleepModeStatus eTaskConfirmSleepModeStatus( void ) + { + #if ( INCLUDE_vTaskSuspend == 1 ) + /* The idle task exists in addition to the application tasks. */ + const UBaseType_t uxNonApplicationTasks = 1; + #endif /* INCLUDE_vTaskSuspend */ + + eSleepModeStatus eReturn = eStandardSleep; + + /* This function must be called from a critical section. */ + + if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 ) + { + /* A task was made ready while the scheduler was suspended. */ + eReturn = eAbortSleep; + } + else if( xYieldPending != pdFALSE ) + { + /* A yield was pended while the scheduler was suspended. */ + eReturn = eAbortSleep; + } + else if( xPendedTicks != 0 ) + { + /* A tick interrupt has already occurred but was held pending + * because the scheduler is suspended. */ + eReturn = eAbortSleep; + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + else if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) ) + { + /* If all the tasks are in the suspended list (which might mean they + * have an infinite block time rather than actually being suspended) + * then it is safe to turn all clocks off and just wait for external + * interrupts. */ + eReturn = eNoTasksWaitingTimeout; + } + #endif /* INCLUDE_vTaskSuspend */ + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return eReturn; + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) + { + TCB_t * pxTCB; + + if( ( xIndex >= 0 ) && + ( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) ) + { + pxTCB = prvGetTCBFromHandle( xTaskToSet ); + configASSERT( pxTCB != NULL ); + pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue; + } + } + +#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */ +/*-----------------------------------------------------------*/ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) + { + void * pvReturn = NULL; + TCB_t * pxTCB; + + if( ( xIndex >= 0 ) && + ( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) ) + { + pxTCB = prvGetTCBFromHandle( xTaskToQuery ); + pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ]; + } + else + { + pvReturn = NULL; + } + + return pvReturn; + } + +#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */ +/*-----------------------------------------------------------*/ + +#if ( portUSING_MPU_WRAPPERS == 1 ) + + void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, + const MemoryRegion_t * const xRegions ) + { + TCB_t * pxTCB; + + /* If null is passed in here then we are modifying the MPU settings of + * the calling task. */ + pxTCB = prvGetTCBFromHandle( xTaskToModify ); + + vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 ); + } + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseTaskLists( void ) +{ + UBaseType_t uxPriority; + + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + { + vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); + } + + vListInitialise( &xDelayedTaskList1 ); + vListInitialise( &xDelayedTaskList2 ); + vListInitialise( &xPendingReadyList ); + + #if ( INCLUDE_vTaskDelete == 1 ) + { + vListInitialise( &xTasksWaitingTermination ); + } + #endif /* INCLUDE_vTaskDelete */ + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + vListInitialise( &xSuspendedTaskList ); + } + #endif /* INCLUDE_vTaskSuspend */ + + /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList + * using list2. */ + pxDelayedTaskList = &xDelayedTaskList1; + pxOverflowDelayedTaskList = &xDelayedTaskList2; +} +/*-----------------------------------------------------------*/ + +static void prvCheckTasksWaitingTermination( void ) +{ + /** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/ + + #if ( INCLUDE_vTaskDelete == 1 ) + { + TCB_t * pxTCB; + + /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() + * being called too often in the idle task. */ + while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + { + taskENTER_CRITICAL(); + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + --uxCurrentNumberOfTasks; + --uxDeletedTasksWaitingCleanUp; + } + taskEXIT_CRITICAL(); + + prvDeleteTCB( pxTCB ); + } + } + #endif /* INCLUDE_vTaskDelete */ +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) + { + TCB_t * pxTCB; + + /* xTask is NULL then get the state of the calling task. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB; + pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] ); + pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority; + pxTaskStatus->pxStackBase = pxTCB->pxStack; + #if ( ( portSTACK_GROWTH > 0 ) && ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + pxTaskStatus->pxTopOfStack = pxTCB->pxTopOfStack; + pxTaskStatus->pxEndOfStack = pxTCB->pxEndOfStack; + #endif + pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber; + + #if ( configUSE_MUTEXES == 1 ) + { + pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority; + } + #else + { + pxTaskStatus->uxBasePriority = 0; + } + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter; + } + #else + { + pxTaskStatus->ulRunTimeCounter = ( configRUN_TIME_COUNTER_TYPE ) 0; + } + #endif + + /* Obtaining the task state is a little fiddly, so is only done if the + * value of eState passed into this function is eInvalid - otherwise the + * state is just set to whatever is passed in. */ + if( eState != eInvalid ) + { + if( pxTCB == pxCurrentTCB ) + { + pxTaskStatus->eCurrentState = eRunning; + } + else + { + pxTaskStatus->eCurrentState = eState; + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + /* If the task is in the suspended list then there is a + * chance it is actually just blocked indefinitely - so really + * it should be reported as being in the Blocked state. */ + if( eState == eSuspended ) + { + vTaskSuspendAll(); + { + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + pxTaskStatus->eCurrentState = eBlocked; + } + } + ( void ) xTaskResumeAll(); + } + } + #endif /* INCLUDE_vTaskSuspend */ + } + } + else + { + pxTaskStatus->eCurrentState = eTaskGetState( pxTCB ); + } + + /* Obtaining the stack space takes some time, so the xGetFreeStackSpace + * parameter is provided to allow it to be skipped. */ + if( xGetFreeStackSpace != pdFALSE ) + { + #if ( portSTACK_GROWTH > 0 ) + { + pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack ); + } + #else + { + pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack ); + } + #endif + } + else + { + pxTaskStatus->usStackHighWaterMark = 0; + } + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray, + List_t * pxList, + eTaskState eState ) + { + configLIST_VOLATILE TCB_t * pxNextTCB; + configLIST_VOLATILE TCB_t * pxFirstTCB; + UBaseType_t uxTask = 0; + + if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + /* Populate an TaskStatus_t structure within the + * pxTaskStatusArray array for each task that is referenced from + * pxList. See the definition of TaskStatus_t in task.h for the + * meaning of each TaskStatus_t structure member. */ + do + { + listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState ); + uxTask++; + } while( pxNextTCB != pxFirstTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return uxTask; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) + + static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) + { + uint32_t ulCount = 0U; + + while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE ) + { + pucStackByte -= portSTACK_GROWTH; + ulCount++; + } + + ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */ + + return ( configSTACK_DEPTH_TYPE ) ulCount; + } + +#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + +/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. */ + configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + uint8_t * pucEndOfStack; + configSTACK_DEPTH_TYPE uxReturn; + + /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are + * the same except for their return type. Using configSTACK_DEPTH_TYPE + * allows the user to determine the return type. It gets around the + * problem of the value overflowing on 8-bit types without breaking + * backward compatibility for applications that expect an 8-bit return + * type. */ + + pxTCB = prvGetTCBFromHandle( xTask ); + + #if portSTACK_GROWTH < 0 + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxStack; + } + #else + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack; + } + #endif + + uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + uint8_t * pucEndOfStack; + UBaseType_t uxReturn; + + pxTCB = prvGetTCBFromHandle( xTask ); + + #if portSTACK_GROWTH < 0 + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxStack; + } + #else + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack; + } + #endif + + uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskGetStackHighWaterMark */ +/*-----------------------------------------------------------*/ + +#if (INCLUDE_pxTaskGetStackStart == 1) + uint8_t* pxTaskGetStackStart( TaskHandle_t xTask) + { + TCB_t *pxTCB; + UBaseType_t uxReturn; + (void)uxReturn; + + pxTCB = prvGetTCBFromHandle( xTask ); + return ( uint8_t * ) pxTCB->pxStack; + } + +#endif /* INCLUDE_pxTaskGetStackStart */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + static void prvDeleteTCB( TCB_t * pxTCB ) + { + /* This call is required specifically for the TriCore port. It must be + * above the vPortFree() calls. The call is also used by ports/demos that + * want to allocate and clean RAM statically. */ + portCLEAN_UP_TCB( pxTCB ); + + #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) ) + { + /* Free up the memory allocated for the task's TLS Block. */ + configDEINIT_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); + } + #endif + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) + { + /* The task can only have been allocated dynamically - free both + * the stack and TCB. */ + vPortFreeStack( pxTCB->pxStack ); + vPortFree( pxTCB ); + } + #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* The task could have been allocated statically or dynamically, so + * check what was statically allocated before trying to free the + * memory. */ + if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) + { + /* Both the stack and TCB were allocated dynamically, so both + * must be freed. */ + vPortFreeStack( pxTCB->pxStack ); + vPortFree( pxTCB ); + } + else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) + { + /* Only the stack was statically allocated, so the TCB is the + * only memory that must be freed. */ + vPortFree( pxTCB ); + } + else + { + /* Neither the stack nor the TCB were allocated dynamically, so + * nothing needs to be freed. */ + configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +static void prvResetNextTaskUnblockTime( void ) +{ + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + { + /* The new current delayed list is empty. Set xNextTaskUnblockTime to + * the maximum possible value so it is extremely unlikely that the + * if( xTickCount >= xNextTaskUnblockTime ) test will pass until + * there is an item in the delayed list. */ + xNextTaskUnblockTime = portMAX_DELAY; + } + else + { + /* The new current delayed list is not empty, get the value of + * the item at the head of the delayed list. This is the time at + * which the task at the head of the delayed list should be removed + * from the Blocked state. */ + xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t xTaskGetCurrentTaskHandle( void ) + { + TaskHandle_t xReturn; + + /* A critical section is not required as this is not called from + * an interrupt and the current TCB will always be the same for any + * individual execution thread. */ + xReturn = pxCurrentTCB; + + return xReturn; + } + +#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + + BaseType_t xTaskGetSchedulerState( void ) + { + BaseType_t xReturn; + + if( xSchedulerRunning == pdFALSE ) + { + xReturn = taskSCHEDULER_NOT_STARTED; + } + else + { + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + xReturn = taskSCHEDULER_RUNNING; + } + else + { + xReturn = taskSCHEDULER_SUSPENDED; + } + } + + return xReturn; + } + +#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) + { + TCB_t * const pxMutexHolderTCB = pxMutexHolder; + BaseType_t xReturn = pdFALSE; + + /* If the mutex was given back by an interrupt while the queue was + * locked then the mutex holder might now be NULL. _RB_ Is this still + * needed as interrupts can no longer use mutexes? */ + if( pxMutexHolder != NULL ) + { + /* If the holder of the mutex has a priority below the priority of + * the task attempting to obtain the mutex then it will temporarily + * inherit the priority of the task attempting to obtain the mutex. */ + if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) + { + /* Adjust the mutex holder state to account for its new + * priority. Only reset the event list item value if the value is + * not being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + { + listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the task being modified is in the ready state it will need + * to be moved into a new list. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) + { + if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Inherit the priority before being moved into the new list. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; + prvReaddTaskToReadyList( pxMutexHolderTCB ); + } + else + { + /* Just inherit the priority. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; + } + + traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); + + /* Inheritance occurred. */ + xReturn = pdTRUE; + } + else + { + if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) + { + /* The base priority of the mutex holder is lower than the + * priority of the task attempting to take the mutex, but the + * current priority of the mutex holder is not lower than the + * priority of the task attempting to take the mutex. + * Therefore the mutex holder must have already inherited a + * priority, but inheritance would have occurred if that had + * not been the case. */ + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) + { + TCB_t * const pxTCB = pxMutexHolder; + BaseType_t xReturn = pdFALSE; + + if( pxMutexHolder != NULL ) + { + /* A task can only have an inherited priority if it holds the mutex. + * If the mutex is held by a task then it cannot be given from an + * interrupt, and if a mutex is given by the holding task then it must + * be the running state task. */ + configASSERT( pxTCB == pxCurrentTCB ); + configASSERT( pxTCB->uxMutexesHeld ); + ( pxTCB->uxMutexesHeld )--; + + /* Has the holder of the mutex inherited the priority of another + * task? */ + if( pxTCB->uxPriority != pxTCB->uxBasePriority ) + { + /* Only disinherit if no other mutexes are held. */ + if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) + { + /* A task can only have an inherited priority if it holds + * the mutex. If the mutex is held by a task then it cannot be + * given from an interrupt, and if a mutex is given by the + * holding task then it must be the running state task. Remove + * the holding task from the ready list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Disinherit the priority before adding the task into the + * new ready list. */ + traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); + pxTCB->uxPriority = pxTCB->uxBasePriority; + + /* Reset the event list item value. It cannot be in use for + * any other purpose if this task is running, and it must be + * running to give back the mutex. */ + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + prvReaddTaskToReadyList( pxTCB ); + + /* Return true to indicate that a context switch is required. + * This is only actually required in the corner case whereby + * multiple mutexes were held and the mutexes were given back + * in an order different to that in which they were taken. + * If a context switch did not occur when the first mutex was + * returned, even if a task was waiting on it, then a context + * switch should occur when the last mutex is returned whether + * a task is waiting on it or not. */ + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, + UBaseType_t uxHighestPriorityWaitingTask ) + { + TCB_t * const pxTCB = pxMutexHolder; + UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; + const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; + + if( pxMutexHolder != NULL ) + { + /* If pxMutexHolder is not NULL then the holder must hold at least + * one mutex. */ + configASSERT( pxTCB->uxMutexesHeld ); + + /* Determine the priority to which the priority of the task that + * holds the mutex should be set. This will be the greater of the + * holding task's base priority and the priority of the highest + * priority task that is waiting to obtain the mutex. */ + if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) + { + uxPriorityToUse = uxHighestPriorityWaitingTask; + } + else + { + uxPriorityToUse = pxTCB->uxBasePriority; + } + + /* Does the priority need to change? */ + if( pxTCB->uxPriority != uxPriorityToUse ) + { + /* Only disinherit if no other mutexes are held. This is a + * simplification in the priority inheritance implementation. If + * the task that holds the mutex is also holding other mutexes then + * the other mutexes may have caused the priority inheritance. */ + if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) + { + /* If a task has timed out because it already holds the + * mutex it was trying to obtain then it cannot of inherited + * its own priority. */ + configASSERT( pxTCB != pxCurrentTCB ); + + /* Disinherit the priority, remembering the previous + * priority to facilitate determining the subject task's + * state. */ + traceTASK_PRIORITY_DISINHERIT( pxTCB, uxPriorityToUse ); + uxPriorityUsedOnEntry = pxTCB->uxPriority; + pxTCB->uxPriority = uxPriorityToUse; + + /* Only reset the event list item value if the value is not + * being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + { + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the running task is not the task that holds the mutex + * then the task that holds the mutex could be in either the + * Ready, Blocked or Suspended states. Only remove the task + * from its current state list if it is in the Ready state as + * the task's priority is going to change and there is one + * Ready list per priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvAddTaskToReadyList( pxTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( portCRITICAL_NESTING_IN_TCB == 1 ) + + void vTaskEnterCritical( void ) + { + portDISABLE_INTERRUPTS(); + + if( xSchedulerRunning != pdFALSE ) + { + ( pxCurrentTCB->uxCriticalNesting )++; + + /* This is not the interrupt safe version of the enter critical + * function so assert() if it is being called from an interrupt + * context. Only API functions that end in "FromISR" can be used in an + * interrupt. Only assert if the critical nesting count is 1 to + * protect against recursive calls if the assert function also uses a + * critical section. */ + if( pxCurrentTCB->uxCriticalNesting == 1 ) + { + portASSERT_IF_IN_ISR(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* portCRITICAL_NESTING_IN_TCB */ +/*-----------------------------------------------------------*/ + +#if ( portCRITICAL_NESTING_IN_TCB == 1 ) + + void vTaskExitCritical( void ) + { + if( xSchedulerRunning != pdFALSE ) + { + if( pxCurrentTCB->uxCriticalNesting > 0U ) + { + ( pxCurrentTCB->uxCriticalNesting )--; + + if( pxCurrentTCB->uxCriticalNesting == 0U ) + { + portENABLE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* portCRITICAL_NESTING_IN_TCB */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) + + static char * prvWriteNameToBuffer( char * pcBuffer, + const char * pcTaskName ) + { + size_t x; + + /* Start by copying the entire string. */ + strcpy( pcBuffer, pcTaskName ); + + /* Pad the end of the string with spaces to ensure columns line up when + * printed out. */ + for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ ) + { + pcBuffer[ x ] = ' '; + } + + /* Terminate. */ + pcBuffer[ x ] = ( char ) 0x00; + + /* Return the new end of string. */ + return &( pcBuffer[ x ] ); + } + +#endif /* ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) + + void vTaskList( char * pcWriteBuffer ) + { + TaskStatus_t * pxTaskStatusArray; + UBaseType_t uxArraySize, x; + char cStatus; + + /* + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many + * of the demo applications. Do not consider it to be part of the + * scheduler. + * + * vTaskList() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that + * displays task: names, states, priority, stack usage and task number. + * Stack usage specified as the number of unused StackType_t words stack can hold + * on top of stack - not the number of bytes. + * + * vTaskList() has a dependency on the sprintf() C library function that + * might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, + * and limited functionality implementation of sprintf() is provided in + * many of the FreeRTOS/Demo sub-directories in a file called + * printf-stdarg.c (note printf-stdarg.c does not provide a full + * snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly + * through a call to vTaskList(). + */ + + + /* Make sure the write buffer does not contain a string. */ + *pcWriteBuffer = ( char ) 0x00; + + /* Take a snapshot of the number of tasks in case it changes while this + * function is executing. */ + uxArraySize = uxCurrentNumberOfTasks; + + /* Allocate an array index for each task. NOTE! if + * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will + * equate to NULL. */ + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */ + + if( pxTaskStatusArray != NULL ) + { + /* Generate the (binary) data. */ + uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL ); + + /* Create a human readable table from the binary data. */ + for( x = 0; x < uxArraySize; x++ ) + { + switch( pxTaskStatusArray[ x ].eCurrentState ) + { + case eRunning: + cStatus = tskRUNNING_CHAR; + break; + + case eReady: + cStatus = tskREADY_CHAR; + break; + + case eBlocked: + cStatus = tskBLOCKED_CHAR; + break; + + case eSuspended: + cStatus = tskSUSPENDED_CHAR; + break; + + case eDeleted: + cStatus = tskDELETED_CHAR; + break; + + case eInvalid: /* Fall through. */ + default: /* Should not get here, but it is included + * to prevent static checking errors. */ + cStatus = ( char ) 0x00; + break; + } + + /* Write the task name to the string, padding with spaces so it + * can be printed in tabular form more easily. */ + pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); + + /* Write the rest of the string. */ + sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ + } + + /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION + * is 0 then vPortFree() will be #defined to nothing. */ + vPortFree( pxTaskStatusArray ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */ +/*----------------------------------------------------------*/ + +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void vTaskGetRunTimeStats( char * pcWriteBuffer ) + { + TaskStatus_t * pxTaskStatusArray; + UBaseType_t uxArraySize, x; + configRUN_TIME_COUNTER_TYPE ulTotalTime, ulStatsAsPercentage; + + /* + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many + * of the demo applications. Do not consider it to be part of the + * scheduler. + * + * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part + * of the uxTaskGetSystemState() output into a human readable table that + * displays the amount of time each task has spent in the Running state + * in both absolute and percentage terms. + * + * vTaskGetRunTimeStats() has a dependency on the sprintf() C library + * function that might bloat the code size, use a lot of stack, and + * provide different results on different platforms. An alternative, + * tiny, third party, and limited functionality implementation of + * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in + * a file called printf-stdarg.c (note printf-stdarg.c does not provide + * a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly + * through a call to vTaskGetRunTimeStats(). + */ + + /* Make sure the write buffer does not contain a string. */ + *pcWriteBuffer = ( char ) 0x00; + + /* Take a snapshot of the number of tasks in case it changes while this + * function is executing. */ + uxArraySize = uxCurrentNumberOfTasks; + + /* Allocate an array index for each task. NOTE! If + * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will + * equate to NULL. */ + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */ + + if( pxTaskStatusArray != NULL ) + { + /* Generate the (binary) data. */ + uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime ); + + /* For percentage calculations. */ + ulTotalTime /= 100UL; + + /* Avoid divide by zero errors. */ + if( ulTotalTime > 0UL ) + { + /* Create a human readable table from the binary data. */ + for( x = 0; x < uxArraySize; x++ ) + { + /* What percentage of the total run time has the task used? + * This will always be rounded down to the nearest integer. + * ulTotalRunTime has already been divided by 100. */ + ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime; + + /* Write the task name to the string, padding with + * spaces so it can be printed in tabular form more + * easily. */ + pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); + + if( ulStatsAsPercentage > 0UL ) + { + #ifdef portLU_PRINTF_SPECIFIER_REQUIRED + { + sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage ); + } + #else + { + /* sizeof( int ) == sizeof( long ) so a smaller + * printf() library can be used. */ + sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + } + #endif + } + else + { + /* If the percentage is zero here then the task has + * consumed less than 1% of the total run time. */ + #ifdef portLU_PRINTF_SPECIFIER_REQUIRED + { + sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter ); + } + #else + { + /* sizeof( int ) == sizeof( long ) so a smaller + * printf() library can be used. */ + sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + } + #endif + } + + pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION + * is 0 then vPortFree() will be #defined to nothing. */ + vPortFree( pxTaskStatusArray ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */ +/*-----------------------------------------------------------*/ + +TickType_t uxTaskResetEventItemValue( void ) +{ + TickType_t uxReturn; + + uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) ); + + /* Reset the event list item to its normal value - so it can be used with + * queues and semaphores. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + TaskHandle_t pvTaskIncrementMutexHeldCount( void ) + { + /* If xSemaphoreCreateMutex() is called before any tasks have been created + * then pxCurrentTCB will be NULL. */ + if( pxCurrentTCB != NULL ) + { + ( pxCurrentTCB->uxMutexesHeld )++; + } + + return pxCurrentTCB; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWait, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) + { + uint32_t ulReturn; + + configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + taskENTER_CRITICAL(); + { + /* Only block if the notification count is not already non-zero. */ + if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] == 0UL ) + { + /* Mark this task as waiting for a notification. */ + pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION; + + if( xTicksToWait > ( TickType_t ) 0 ) + { + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait ); + + /* All ports are written to allow a yield in a critical + * section (some will yield immediately, others wait until the + * critical section exits) - but it is not something that + * application code should ever do. */ + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + taskENTER_CRITICAL(); + { + traceTASK_NOTIFY_TAKE( uxIndexToWait ); + ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ]; + + if( ulReturn != 0UL ) + { + if( xClearCountOnExit != pdFALSE ) + { + pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = 0UL; + } + else + { + pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = ulReturn - ( uint32_t ) 1; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; + } + taskEXIT_CRITICAL(); + + return ulReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWait, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + + configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + taskENTER_CRITICAL(); + { + /* Only block if a notification is not already pending. */ + if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED ) + { + /* Clear bits in the task's notification value as bits may get + * set by the notifying task or interrupt. This can be used to + * clear the value to zero. */ + pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnEntry; + + /* Mark this task as waiting for a notification. */ + pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION; + + if( xTicksToWait > ( TickType_t ) 0 ) + { + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait ); + + /* All ports are written to allow a yield in a critical + * section (some will yield immediately, others wait until the + * critical section exits) - but it is not something that + * application code should ever do. */ + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + taskENTER_CRITICAL(); + { + traceTASK_NOTIFY_WAIT( uxIndexToWait ); + + if( pulNotificationValue != NULL ) + { + /* Output the current notification value, which may or may not + * have changed. */ + *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ]; + } + + /* If ucNotifyValue is set then either the task never entered the + * blocked state (because a notification was already pending) or the + * task unblocked because of a notification. Otherwise the task + * unblocked because of a timeout. */ + if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED ) + { + /* A notification was not received. */ + xReturn = pdFALSE; + } + else + { + /* A notification was already pending or a notification was + * received while the task was waiting. */ + pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnExit; + xReturn = pdTRUE; + } + + pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) + { + TCB_t * pxTCB; + BaseType_t xReturn = pdPASS; + uint8_t ucOriginalNotifyState; + + configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + configASSERT( xTaskToNotify ); + pxTCB = xTaskToNotify; + + taskENTER_CRITICAL(); + { + if( pulPreviousNotificationValue != NULL ) + { + *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ]; + } + + ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; + + pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; + + switch( eAction ) + { + case eSetBits: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue; + break; + + case eIncrement: + ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; + break; + + case eSetValueWithOverwrite: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + break; + + case eSetValueWithoutOverwrite: + + if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) + { + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + } + else + { + /* The value could not be written to the task. */ + xReturn = pdFAIL; + } + + break; + + case eNoAction: + + /* The task is being notified without its notify value being + * updated. */ + break; + + default: + + /* Should not get here if all enums are handled. + * Artificially force an assert by testing a value the + * compiler can't assume is const. */ + configASSERT( xTickCount == ( TickType_t ) 0 ); + + break; + } + + traceTASK_NOTIFY( uxIndexToNotify ); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + { + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + /* The task should not have been on an event list. */ + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked waiting for a notification then + * xNextTaskUnblockTime might be set to the blocked task's time + * out time. If the task is unblocked for a reason other than + * a timeout xNextTaskUnblockTime is normally left unchanged, + * because it will automatically get reset to a new value when + * the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter + * sleep mode at the earliest possible time - so reset + * xNextTaskUnblockTime here to ensure it is updated at the + * earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue, + BaseType_t * pxHigherPriorityTaskWoken ) + { + TCB_t * pxTCB; + uint8_t ucOriginalNotifyState; + BaseType_t xReturn = pdPASS; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( xTaskToNotify ); + configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + pxTCB = xTaskToNotify; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( pulPreviousNotificationValue != NULL ) + { + *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ]; + } + + ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; + pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; + + switch( eAction ) + { + case eSetBits: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue; + break; + + case eIncrement: + ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; + break; + + case eSetValueWithOverwrite: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + break; + + case eSetValueWithoutOverwrite: + + if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) + { + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + } + else + { + /* The value could not be written to the task. */ + xReturn = pdFAIL; + } + + break; + + case eNoAction: + + /* The task is being notified without its notify value being + * updated. */ + break; + + default: + + /* Should not get here if all enums are handled. + * Artificially force an assert by testing a value the + * compiler can't assume is const. */ + configASSERT( xTickCount == ( TickType_t ) 0 ); + break; + } + + traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify ); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + { + /* The task should not have been on an event list. */ + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + } + else + { + /* The delayed and ready lists cannot be accessed, so hold + * this task pending until the scheduler is resumed. */ + listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter to an ISR + * safe FreeRTOS function. */ + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + BaseType_t * pxHigherPriorityTaskWoken ) + { + TCB_t * pxTCB; + uint8_t ucOriginalNotifyState; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( xTaskToNotify ); + configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + pxTCB = xTaskToNotify; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; + pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; + + /* 'Giving' is equivalent to incrementing a count in a counting + * semaphore. */ + ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; + + traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + { + /* The task should not have been on an event list. */ + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + } + else + { + /* The delayed and ready lists cannot be accessed, so hold + * this task pending until the scheduler is resumed. */ + listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter in an ISR + * safe FreeRTOS function. */ + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) + { + TCB_t * pxTCB; + BaseType_t xReturn; + + configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* If null is passed in here then it is the calling task that is having + * its notification state cleared. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + taskENTER_CRITICAL(); + { + if( pxTCB->ucNotifyState[ uxIndexToClear ] == taskNOTIFICATION_RECEIVED ) + { + pxTCB->ucNotifyState[ uxIndexToClear ] = taskNOT_WAITING_NOTIFICATION; + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) + { + TCB_t * pxTCB; + uint32_t ulReturn; + + /* If null is passed in here then it is the calling task that is having + * its notification state cleared. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + taskENTER_CRITICAL(); + { + /* Return the notification as it was before the bits were cleared, + * then clear the bit mask. */ + ulReturn = pxTCB->ulNotifiedValue[ uxIndexToClear ]; + pxTCB->ulNotifiedValue[ uxIndexToClear ] &= ~ulBitsToClear; + } + taskEXIT_CRITICAL(); + + return ulReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) + { + return xIdleTaskHandle->ulRunTimeCounter; + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) + { + configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn; + + ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE(); + + /* For percentage calculations. */ + ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100; + + /* Avoid divide by zero errors. */ + if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 ) + { + ulReturn = xIdleTaskHandle->ulRunTimeCounter / ulTotalTime; + } + else + { + ulReturn = 0; + } + + return ulReturn; + } + +#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, + const BaseType_t xCanBlockIndefinitely ) +{ + TickType_t xTimeToWake; + const TickType_t xConstTickCount = xTickCount; + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + { + /* About to enter a delayed list, so ensure the ucDelayAborted flag is + * reset to pdFALSE so it can be detected as having been set to pdTRUE + * when the task leaves the Blocked state. */ + pxCurrentTCB->ucDelayAborted = pdFALSE; + } + #endif + + /* Remove the task from the ready list before adding it to the blocked list + * as the same list item is used for both lists. */ + if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* The current task must be in a ready list, so there is no need to + * check, and the port reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) + { + /* Add the task to the suspended task list instead of a delayed task + * list to ensure it is not woken by a timing event. It will block + * indefinitely. */ + traceMOVED_TASK_TO_SUSPENDED_LIST(pxCurrentTCB); + listINSERT_END( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); + } + else + { + /* Calculate the time at which the task should be woken if the event + * does not occur. This may overflow but this doesn't matter, the + * kernel will manage it correctly. */ + xTimeToWake = xConstTickCount + xTicksToWait; + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + + if( xTimeToWake < xConstTickCount ) + { + /* Wake time has overflowed. Place this item in the overflow + * list. */ + traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST(); + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + } + else + { + /* The wake time has not overflowed, so the current block list + * is used. */ + traceMOVED_TASK_TO_DELAYED_LIST(); + vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + + /* If the task entering the blocked state was placed at the + * head of the list of blocked tasks then xNextTaskUnblockTime + * needs to be updated too. */ + if( xTimeToWake < xNextTaskUnblockTime ) + { + xNextTaskUnblockTime = xTimeToWake; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + } + #else /* INCLUDE_vTaskSuspend */ + { + /* Calculate the time at which the task should be woken if the event + * does not occur. This may overflow but this doesn't matter, the kernel + * will manage it correctly. */ + xTimeToWake = xConstTickCount + xTicksToWait; + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + + if( xTimeToWake < xConstTickCount ) + { + /* Wake time has overflowed. Place this item in the overflow list. */ + traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST(); + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + } + else + { + /* The wake time has not overflowed, so the current block list is used. */ + traceMOVED_TASK_TO_DELAYED_LIST(); + vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + + /* If the task entering the blocked state was placed at the head of the + * list of blocked tasks then xNextTaskUnblockTime needs to be updated + * too. */ + if( xTimeToWake < xNextTaskUnblockTime ) + { + xNextTaskUnblockTime = xTimeToWake; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ + ( void ) xCanBlockIndefinitely; + } + #endif /* INCLUDE_vTaskSuspend */ +} + +/* Code below here allows additional code to be inserted into this source file, + * especially where access to file scope functions and data is needed (for example + * when performing module tests). */ + +#ifdef FREERTOS_MODULE_TEST + #include "tasks_test_access_functions.h" +#endif + + +#if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) + + #include "freertos_tasks_c_additions.h" + + #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + static void freertos_tasks_c_additions_init( void ) + { + FREERTOS_TASKS_C_ADDITIONS_INIT(); + } + #endif + +#endif /* if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CA9/FreeRTOSConfig.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CA9/FreeRTOSConfig.h new file mode 100644 index 0000000..f9fba40 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CA9/FreeRTOSConfig.h @@ -0,0 +1,159 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 +#define configUSE_APPLICATION_TASK_TAG 0 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10240)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if((x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + +/* Cortex-A specific definitions. */ +#define configMAX_API_CALL_INTERRUPT_PRIORITY 24 + +/* Systick definitions */ +#define configSETUP_TICK_INTERRUPT() \ + do { \ + void SystemSetupSystick(uint32_t tickRateHz, void *tickHandler); \ + SystemSetupSystick(configTICK_RATE_HZ, (void *)FreeRTOS_Tick_Handler); \ + } while (0) +#define configCLEAR_TICK_INTERRUPT() \ + do { \ + void SystemClearSystickFlag(void); \ + SystemClearSystickFlag(); \ + } while (0) + +/* Definitions that map the FreeRTOS port exception handlers to startup handler names. */ +#define FreeRTOS_IRQ_Handler IRQ_Handler +#define FreeRTOS_SWI_Handler SVC_Handler + +/* Definitions that map the FreeRTOS application handler to device SystemIrqHandler */ +#define vApplicationIRQHandler SystemIrqHandler + +/* GIC information defintions. */ +#define configINTERRUPT_CONTROLLER_BASE_ADDRESS 0x00a01000UL +#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET 0x1000UL +#define configUNIQUE_INTERRUPT_PRIORITIES 32 + +/* Map the FreeRTOS printf() to the logging task printf. */ +#define configPRINTF( x ) vLoggingPrintf x + +/* Map the logging task's printf to the board specific output function. */ +#define configPRINT_STRING + +/* Sets the length of the buffers into which logging messages are written - so + * also defines the maximum length of each log message. */ +#define configLOGGING_MAX_MESSAGE_LENGTH 256 + +/* Set to 1 to prepend each log message with a message number, the task name, + * and a time stamp. */ +#define configLOGGING_INCLUDE_TIME_AND_TASK_NAME 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM0/FreeRTOSConfig.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM0/FreeRTOSConfig.h new file mode 100644 index 0000000..da51803 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM0/FreeRTOSConfig.h @@ -0,0 +1,141 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 +#define configUSE_APPLICATION_TASK_TAG 0 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10240)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if((x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + + +/* Map the FreeRTOS printf() to the logging task printf. */ +#define configPRINTF( x ) vLoggingPrintf x + +/* Map the logging task's printf to the board specific output function. */ +#define configPRINT_STRING + +/* Sets the length of the buffers into which logging messages are written - so + * also defines the maximum length of each log message. */ +#define configLOGGING_MAX_MESSAGE_LENGTH 256 + +/* Set to 1 to prepend each log message with a message number, the task name, + * and a time stamp. */ +#define configLOGGING_INCLUDE_TIME_AND_TASK_NAME 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/template/ARM_CM4F/FreeRTOSConfig.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM3/FreeRTOSConfig.h similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/template/ARM_CM4F/FreeRTOSConfig.h rename to bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM3/FreeRTOSConfig.h diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM33/FreeRTOSConfig.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM33/FreeRTOSConfig.h new file mode 100644 index 0000000..3a6a1cc --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM33/FreeRTOSConfig.h @@ -0,0 +1,175 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ +#ifndef configENABLE_FPU + #define configENABLE_FPU 0 +#endif +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 0 +#endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 1 +#endif + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 +#define configUSE_APPLICATION_TASK_TAG 0 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10240)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if((x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 3 /* 8 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + + +/* Map the FreeRTOS printf() to the logging task printf. */ +#define configPRINTF( x ) vLoggingPrintf x + +/* Map the logging task's printf to the board specific output function. */ +#define configPRINT_STRING + +/* Sets the length of the buffers into which logging messages are written - so + * also defines the maximum length of each log message. */ +#define configLOGGING_MAX_MESSAGE_LENGTH 256 + +/* Set to 1 to prepend each log message with a message number, the task name, + * and a time stamp. */ +#define configLOGGING_INCLUDE_TIME_AND_TASK_NAME 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM33_3_priority_bits/FreeRTOSConfig.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM33_3_priority_bits/FreeRTOSConfig.h new file mode 100644 index 0000000..db3c65b --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM33_3_priority_bits/FreeRTOSConfig.h @@ -0,0 +1,174 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ +#ifndef configENABLE_FPU + #define configENABLE_FPU 0 +#endif +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 0 +#endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 1 +#endif + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 +#define configUSE_APPLICATION_TASK_TAG 0 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10240)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if((x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + +/* This value is defined also by CMSIS macro __NVIC_PRIO_BITS, but it cannot +be used here because of conflict in *.h inclussion into assembler. */ +#define configPRIO_BITS 3 /* 8 priority levels */ + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + + +/* Map the FreeRTOS printf() to the logging task printf. */ +#define configPRINTF( x ) vLoggingPrintf x + +/* Map the logging task's printf to the board specific output function. */ +#define configPRINT_STRING + +/* Sets the length of the buffers into which logging messages are written - so + * also defines the maximum length of each log message. */ +#define configLOGGING_MAX_MESSAGE_LENGTH 256 + +/* Set to 1 to prepend each log message with a message number, the task name, + * and a time stamp. */ +#define configLOGGING_INCLUDE_TIME_AND_TASK_NAME 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM4F/FreeRTOSConfig.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM4F/FreeRTOSConfig.h new file mode 100644 index 0000000..1d7df54 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM4F/FreeRTOSConfig.h @@ -0,0 +1,163 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 +#define configUSE_APPLICATION_TASK_TAG 0 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10240)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if((x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + + +/* Map the FreeRTOS printf() to the logging task printf. */ +#define configPRINTF( x ) vLoggingPrintf x + +/* Map the logging task's printf to the board specific output function. */ +#define configPRINT_STRING + +/* Sets the length of the buffers into which logging messages are written - so + * also defines the maximum length of each log message. */ +#define configLOGGING_MAX_MESSAGE_LENGTH 256 + +/* Set to 1 to prepend each log message with a message number, the task name, + * and a time stamp. */ +#define configLOGGING_INCLUDE_TIME_AND_TASK_NAME 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM4F_3_priority_bits/FreeRTOSConfig.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM4F_3_priority_bits/FreeRTOSConfig.h new file mode 100644 index 0000000..8700e09 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM4F_3_priority_bits/FreeRTOSConfig.h @@ -0,0 +1,162 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 +#define configUSE_APPLICATION_TASK_TAG 0 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10240)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if((x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + +/* This value is defined also by CMSIS macro __NVIC_PRIO_BITS, but it cannot +be used here because of conflict in *.h inclussion into assembler. */ +#define configPRIO_BITS 3 /* 8 priority levels */ + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + + +/* Map the FreeRTOS printf() to the logging task printf. */ +#define configPRINTF( x ) vLoggingPrintf x + +/* Map the logging task's printf to the board specific output function. */ +#define configPRINT_STRING + +/* Sets the length of the buffers into which logging messages are written - so + * also defines the maximum length of each log message. */ +#define configLOGGING_MAX_MESSAGE_LENGTH 256 + +/* Set to 1 to prepend each log message with a message number, the task name, + * and a time stamp. */ +#define configLOGGING_INCLUDE_TIME_AND_TASK_NAME 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM4F_4_priority_bits/FreeRTOSConfig.h b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM4F_4_priority_bits/FreeRTOSConfig.h new file mode 100644 index 0000000..ae96d9a --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/template/ARM_CM4F_4_priority_bits/FreeRTOSConfig.h @@ -0,0 +1,162 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 +#define configUSE_APPLICATION_TASK_TAG 0 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10240)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if((x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + +/* This value is defined also by CMSIS macro __NVIC_PRIO_BITS, but it cannot +be used here because of conflict in *.h inclussion into assembler. */ +#define configPRIO_BITS 4 /* 15 priority levels */ + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + + +/* Map the FreeRTOS printf() to the logging task printf. */ +#define configPRINTF( x ) vLoggingPrintf x + +/* Map the logging task's printf to the board specific output function. */ +#define configPRINT_STRING + +/* Sets the length of the buffers into which logging messages are written - so + * also defines the maximum length of each log message. */ +#define configLOGGING_MAX_MESSAGE_LENGTH 256 + +/* Set to 1 to prepend each log message with a message number, the task name, + * and a time stamp. */ +#define configLOGGING_INCLUDE_TIME_AND_TASK_NAME 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/bsp/sdk_overlay/rtos/freertos/freertos-kernel/timers.c b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/timers.c new file mode 100644 index 0000000..6b7be77 --- /dev/null +++ b/bsp/sdk_overlay/rtos/freertos/freertos-kernel/timers.c @@ -0,0 +1,1124 @@ +/* + * FreeRTOS Kernel V10.5.1 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" + +#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 ) + #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available. +#endif + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */ + + +/* This entire source file will be skipped if the application is not configured + * to include software timer functionality. This #if is closed at the very bottom + * of this file. If you want to include software timer functionality then ensure + * configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */ +#if ( configUSE_TIMERS == 1 ) + +/* Misc definitions. */ + #define tmrNO_DELAY ( ( TickType_t ) 0U ) + #define tmrMAX_TIME_BEFORE_OVERFLOW ( ( TickType_t ) -1 ) + +/* The name assigned to the timer service task. This can be overridden by + * defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */ + #ifndef configTIMER_SERVICE_TASK_NAME + #define configTIMER_SERVICE_TASK_NAME "Tmr Svc" + #endif + +/* Bit definitions used in the ucStatus member of a timer structure. */ + #define tmrSTATUS_IS_ACTIVE ( ( uint8_t ) 0x01 ) + #define tmrSTATUS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 0x02 ) + #define tmrSTATUS_IS_AUTORELOAD ( ( uint8_t ) 0x04 ) + +/* The definition of the timers themselves. */ + typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */ + { + const char * pcTimerName; /*<< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + ListItem_t xTimerListItem; /*<< Standard linked list item as used by all kernel features for event management. */ + TickType_t xTimerPeriodInTicks; /*<< How quickly and often the timer expires. */ + void * pvTimerID; /*<< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */ + TimerCallbackFunction_t pxCallbackFunction; /*<< The function that will be called when the timer expires. */ + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTimerNumber; /*<< An ID assigned by trace tools such as FreeRTOS+Trace */ + #endif + uint8_t ucStatus; /*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */ + } xTIMER; + +/* The old xTIMER name is maintained above then typedefed to the new Timer_t + * name below to enable the use of older kernel aware debuggers. */ + typedef xTIMER Timer_t; + +/* The definition of messages that can be sent and received on the timer queue. + * Two types of message can be queued - messages that manipulate a software timer, + * and messages that request the execution of a non-timer related callback. The + * two message types are defined in two separate structures, xTimerParametersType + * and xCallbackParametersType respectively. */ + typedef struct tmrTimerParameters + { + TickType_t xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */ + Timer_t * pxTimer; /*<< The timer to which the command will be applied. */ + } TimerParameter_t; + + + typedef struct tmrCallbackParameters + { + PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */ + void * pvParameter1; /* << The value that will be used as the callback functions first parameter. */ + uint32_t ulParameter2; /* << The value that will be used as the callback functions second parameter. */ + } CallbackParameters_t; + +/* The structure that contains the two message types, along with an identifier + * that is used to determine which message type is valid. */ + typedef struct tmrTimerQueueMessage + { + BaseType_t xMessageID; /*<< The command being sent to the timer service task. */ + union + { + TimerParameter_t xTimerParameters; + + /* Don't include xCallbackParameters if it is not going to be used as + * it makes the structure (and therefore the timer queue) larger. */ + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + CallbackParameters_t xCallbackParameters; + #endif /* INCLUDE_xTimerPendFunctionCall */ + } u; + } DaemonTaskMessage_t; + +/*lint -save -e956 A manual analysis and inspection has been used to determine + * which static variables must be declared volatile. */ + +/* The list in which active timers are stored. Timers are referenced in expire + * time order, with the nearest expiry time at the front of the list. Only the + * timer service task is allowed to access these lists. + * xActiveTimerList1 and xActiveTimerList2 could be at function scope but that + * breaks some kernel aware debuggers, and debuggers that reply on removing the + * static qualifier. */ + PRIVILEGED_DATA static List_t xActiveTimerList1; + PRIVILEGED_DATA static List_t xActiveTimerList2; + PRIVILEGED_DATA static List_t * pxCurrentTimerList; + PRIVILEGED_DATA static List_t * pxOverflowTimerList; + +/* A queue that is used to send commands to the timer service task. */ + PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL; + PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL; + +/*lint -restore */ + +/*-----------------------------------------------------------*/ + +/* + * Initialise the infrastructure used by the timer service task if it has not + * been initialised already. + */ + static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION; + +/* + * The timer service task (daemon). Timer functionality is controlled by this + * task. Other tasks communicate with the timer service task using the + * xTimerQueue queue. + */ + static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION; + +/* + * Called by the timer service task to interpret and process a command it + * received on the timer queue. + */ + static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION; + +/* + * Insert the timer into either xActiveTimerList1, or xActiveTimerList2, + * depending on if the expire time causes a timer counter overflow. + */ + static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, + const TickType_t xNextExpiryTime, + const TickType_t xTimeNow, + const TickType_t xCommandTime ) PRIVILEGED_FUNCTION; + +/* + * Reload the specified auto-reload timer. If the reloading is backlogged, + * clear the backlog, calling the callback for each additional reload. When + * this function returns, the next expiry time is after xTimeNow. + */ + static void prvReloadTimer( Timer_t * const pxTimer, + TickType_t xExpiredTime, + const TickType_t xTimeNow ) PRIVILEGED_FUNCTION; + +/* + * An active timer has reached its expire time. Reload the timer if it is an + * auto-reload timer, then call its callback. + */ + static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, + const TickType_t xTimeNow ) PRIVILEGED_FUNCTION; + +/* + * The tick count has overflowed. Switch the timer lists after ensuring the + * current timer list does not still reference some timers. + */ + static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION; + +/* + * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE + * if a tick count overflow occurred since prvSampleTimeNow() was last called. + */ + static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION; + +/* + * If the timer list contains any active timers then return the expire time of + * the timer that will expire first and set *pxListWasEmpty to false. If the + * timer list does not contain any timers then return 0 and set *pxListWasEmpty + * to pdTRUE. + */ + static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION; + +/* + * If a timer has expired, process it. Otherwise, block the timer service task + * until either a timer does expire or a command is received. + */ + static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, + BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION; + +/* + * Called after a Timer_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ + static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + + BaseType_t xTimerCreateTimerTask( void ) + { + BaseType_t xReturn = pdFAIL; + + /* This function is called when the scheduler is started if + * configUSE_TIMERS is set to 1. Check that the infrastructure used by the + * timer service task has been created/initialised. If timers have already + * been created then the initialisation will already have been performed. */ + prvCheckForValidListAndQueue(); + + if( xTimerQueue != NULL ) + { + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxTimerTaskTCBBuffer = NULL; + StackType_t * pxTimerTaskStackBuffer = NULL; + uint32_t ulTimerTaskStackSize; + + vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); + xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + ulTimerTaskStackSize, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + pxTimerTaskStackBuffer, + pxTimerTaskTCBBuffer ); + + if( xTimerTaskHandle != NULL ) + { + xReturn = pdPASS; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + xReturn = xTaskCreate( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + configTIMER_TASK_STACK_DEPTH, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + &xTimerTaskHandle ); + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + configASSERT( xReturn ); + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) + { + Timer_t * pxNewTimer; + + pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ + + if( pxNewTimer != NULL ) + { + /* Status is thus far zero as the timer is not created statically + * and has not been started. The auto-reload bit may get set in + * prvInitialiseNewTimer. */ + pxNewTimer->ucStatus = 0x00; + prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); + } + + return pxNewTimer; + } + + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) + { + Timer_t * pxNewTimer; + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticTimer_t equals the size of the real timer + * structure. */ + volatile size_t xSize = sizeof( StaticTimer_t ); + configASSERT( xSize == sizeof( Timer_t ) ); + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + } + #endif /* configASSERT_DEFINED */ + + /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ + configASSERT( pxTimerBuffer ); + pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ + + if( pxNewTimer != NULL ) + { + /* Timers can be created statically or dynamically so note this + * timer was created statically in case it is later deleted. The + * auto-reload bit may get set in prvInitialiseNewTimer(). */ + pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; + + prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); + } + + return pxNewTimer; + } + + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + Timer_t * pxNewTimer ) + { + /* 0 is not a valid value for xTimerPeriodInTicks. */ + configASSERT( ( xTimerPeriodInTicks > 0 ) ); + + /* Ensure the infrastructure used by the timer service task has been + * created/initialised. */ + prvCheckForValidListAndQueue(); + + /* Initialise the timer structure members using the function + * parameters. */ + pxNewTimer->pcTimerName = pcTimerName; + pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; + pxNewTimer->pvTimerID = pvTimerID; + pxNewTimer->pxCallbackFunction = pxCallbackFunction; + vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); + + if( xAutoReload != pdFALSE ) + { + pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; + } + + traceTIMER_CREATE( pxNewTimer ); + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) + { + BaseType_t xReturn = pdFAIL; + DaemonTaskMessage_t xMessage; + + configASSERT( xTimer ); + + /* Send a message to the timer service task to perform a particular action + * on a particular timer definition. */ + if( xTimerQueue != NULL ) + { + /* Send a command to the timer service task to start the xTimer timer. */ + xMessage.xMessageID = xCommandID; + xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; + xMessage.u.xTimerParameters.pxTimer = xTimer; + + if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) + { + if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); + } + else + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); + } + } + else + { + xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); + } + + traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) + { + /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been + * started, then xTimerTaskHandle will be NULL. */ + configASSERT( ( xTimerTaskHandle != NULL ) ); + return xTimerTaskHandle; + } +/*-----------------------------------------------------------*/ + + TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + return pxTimer->xTimerPeriodInTicks; + } +/*-----------------------------------------------------------*/ + + void vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) + { + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + taskENTER_CRITICAL(); + { + if( xAutoReload != pdFALSE ) + { + pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; + } + else + { + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_AUTORELOAD ); + } + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + BaseType_t xReturn; + + configASSERT( xTimer ); + taskENTER_CRITICAL(); + { + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 ) + { + /* Not an auto-reload timer. */ + xReturn = pdFALSE; + } + else + { + /* Is an auto-reload timer. */ + xReturn = pdTRUE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } + + UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) + { + return ( UBaseType_t ) xTimerGetReloadMode( xTimer ); + } +/*-----------------------------------------------------------*/ + + TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + TickType_t xReturn; + + configASSERT( xTimer ); + xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) ); + return xReturn; + } +/*-----------------------------------------------------------*/ + + const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + return pxTimer->pcTimerName; + } +/*-----------------------------------------------------------*/ + + static void prvReloadTimer( Timer_t * const pxTimer, + TickType_t xExpiredTime, + const TickType_t xTimeNow ) + { + /* Insert the timer into the appropriate list for the next expiry time. + * If the next expiry time has already passed, advance the expiry time, + * call the callback function, and try again. */ + while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE ) + { + /* Advance the expiry time. */ + xExpiredTime += pxTimer->xTimerPeriodInTicks; + + /* Call the timer callback. */ + traceTIMER_EXPIRED( pxTimer ); + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + } + } +/*-----------------------------------------------------------*/ + + static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, + const TickType_t xTimeNow ) + { + Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + /* Remove the timer from the list of active timers. A check has already + * been performed to ensure the list is not empty. */ + + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + + /* If the timer is an auto-reload timer then calculate the next + * expiry time and re-insert the timer in the list of active timers. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + { + prvReloadTimer( pxTimer, xNextExpireTime, xTimeNow ); + } + else + { + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + } + + /* Call the timer callback. */ + traceTIMER_EXPIRED( pxTimer ); + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + } +/*-----------------------------------------------------------*/ + + static portTASK_FUNCTION( prvTimerTask, pvParameters ) + { + TickType_t xNextExpireTime; + BaseType_t xListWasEmpty; + + /* Just to avoid compiler warnings. */ + ( void ) pvParameters; + + #if ( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 ) + { + extern void vApplicationDaemonTaskStartupHook( void ); + + /* Allow the application writer to execute some code in the context of + * this task at the point the task starts executing. This is useful if the + * application includes initialisation code that would benefit from + * executing after the scheduler has been started. */ + vApplicationDaemonTaskStartupHook(); + } + #endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */ + + for( ; ; ) + { + /* Query the timers list to see if it contains any timers, and if so, + * obtain the time at which the next timer will expire. */ + xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); + + /* If a timer has expired, process it. Otherwise, block this task + * until either a timer does expire, or a command is received. */ + prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); + + /* Empty the command queue. */ + prvProcessReceivedCommands(); + } + } +/*-----------------------------------------------------------*/ + + static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, + BaseType_t xListWasEmpty ) + { + TickType_t xTimeNow; + BaseType_t xTimerListsWereSwitched; + + vTaskSuspendAll(); + { + /* Obtain the time now to make an assessment as to whether the timer + * has expired or not. If obtaining the time causes the lists to switch + * then don't process this timer as any timers that remained in the list + * when the lists were switched will have been processed within the + * prvSampleTimeNow() function. */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + + if( xTimerListsWereSwitched == pdFALSE ) + { + /* The tick count has not overflowed, has the timer expired? */ + if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) + { + ( void ) xTaskResumeAll(); + prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); + } + else + { + /* The tick count has not overflowed, and the next expire + * time has not been reached yet. This task should therefore + * block to wait for the next expire time or a command to be + * received - whichever comes first. The following line cannot + * be reached unless xNextExpireTime > xTimeNow, except in the + * case when the current timer list is empty. */ + if( xListWasEmpty != pdFALSE ) + { + /* The current timer list is empty - is the overflow list + * also empty? */ + xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); + } + + vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); + + if( xTaskResumeAll() == pdFALSE ) + { + /* Yield to wait for either a command to arrive, or the + * block time to expire. If a command arrived between the + * critical section being exited and this yield then the yield + * will not cause the task to block. */ + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + else + { + ( void ) xTaskResumeAll(); + } + } + } +/*-----------------------------------------------------------*/ + + static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) + { + TickType_t xNextExpireTime; + + /* Timers are listed in expiry time order, with the head of the list + * referencing the task that will expire first. Obtain the time at which + * the timer with the nearest expiry time will expire. If there are no + * active timers then just set the next expire time to 0. That will cause + * this task to unblock when the tick count overflows, at which point the + * timer lists will be switched and the next expiry time can be + * re-assessed. */ + *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); + + if( *pxListWasEmpty == pdFALSE ) + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + } + else + { + /* Ensure the task unblocks when the tick count rolls over. */ + xNextExpireTime = ( TickType_t ) 0U; + } + + return xNextExpireTime; + } +/*-----------------------------------------------------------*/ + + static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) + { + TickType_t xTimeNow; + PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ + + xTimeNow = xTaskGetTickCount(); + + if( xTimeNow < xLastTime ) + { + prvSwitchTimerLists(); + *pxTimerListsWereSwitched = pdTRUE; + } + else + { + *pxTimerListsWereSwitched = pdFALSE; + } + + xLastTime = xTimeNow; + + return xTimeNow; + } +/*-----------------------------------------------------------*/ + + static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, + const TickType_t xNextExpiryTime, + const TickType_t xTimeNow, + const TickType_t xCommandTime ) + { + BaseType_t xProcessTimerNow = pdFALSE; + + listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); + listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); + + if( xNextExpiryTime <= xTimeNow ) + { + /* Has the expiry time elapsed between the command to start/reset a + * timer was issued, and the time the command was processed? */ + if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + { + /* The time between a command being issued and the command being + * processed actually exceeds the timers period. */ + xProcessTimerNow = pdTRUE; + } + else + { + vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); + } + } + else + { + if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) + { + /* If, since the command was issued, the tick count has overflowed + * but the expiry time has not, then the timer must have already passed + * its expiry time and should be processed immediately. */ + xProcessTimerNow = pdTRUE; + } + else + { + vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); + } + } + + return xProcessTimerNow; + } +/*-----------------------------------------------------------*/ + + static void prvProcessReceivedCommands( void ) + { + DaemonTaskMessage_t xMessage; + Timer_t * pxTimer; + BaseType_t xTimerListsWereSwitched; + TickType_t xTimeNow; + + while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ + { + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + { + /* Negative commands are pended function calls rather than timer + * commands. */ + if( xMessage.xMessageID < ( BaseType_t ) 0 ) + { + const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); + + /* The timer uses the xCallbackParameters member to request a + * callback be executed. Check the callback is not NULL. */ + configASSERT( pxCallback ); + + /* Call the function. */ + pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* INCLUDE_xTimerPendFunctionCall */ + + /* Commands that are positive are timer commands rather than pended + * function calls. */ + if( xMessage.xMessageID >= ( BaseType_t ) 0 ) + { + /* The messages uses the xTimerParameters member to work on a + * software timer. */ + pxTimer = xMessage.u.xTimerParameters.pxTimer; + + if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ + { + /* The timer is in a list, remove it. */ + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue ); + + /* In this case the xTimerListsWereSwitched parameter is not used, but + * it must be present in the function call. prvSampleTimeNow() must be + * called after the message is received from xTimerQueue so there is no + * possibility of a higher priority task adding a message to the message + * queue with a time that is ahead of the timer daemon task (because it + * pre-empted the timer daemon task after the xTimeNow value was set). */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + + switch( xMessage.xMessageID ) + { + case tmrCOMMAND_START: + case tmrCOMMAND_START_FROM_ISR: + case tmrCOMMAND_RESET: + case tmrCOMMAND_RESET_FROM_ISR: + /* Start or restart a timer. */ + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + + if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) + { + /* The timer expired before it was added to the active + * timer list. Process it now. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + { + prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow ); + } + else + { + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + } + + /* Call the timer callback. */ + traceTIMER_EXPIRED( pxTimer ); + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + break; + + case tmrCOMMAND_STOP: + case tmrCOMMAND_STOP_FROM_ISR: + /* The timer has already been removed from the active list. */ + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + break; + + case tmrCOMMAND_CHANGE_PERIOD: + case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR: + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; + configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); + + /* The new period does not really have a reference, and can + * be longer or shorter than the old one. The command time is + * therefore set to the current time, and as the period cannot + * be zero the next expiry time can only be in the future, + * meaning (unlike for the xTimerStart() case above) there is + * no fail case that needs to be handled here. */ + ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); + break; + + case tmrCOMMAND_DELETE: + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* The timer has already been removed from the active list, + * just free up the memory if the memory was dynamically + * allocated. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) + { + vPortFree( pxTimer ); + } + else + { + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + } + } + #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ + { + /* If dynamic allocation is not enabled, the memory + * could not have been dynamically allocated. So there is + * no need to free the memory - just mark the timer as + * "not active". */ + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + break; + + default: + /* Don't expect to get here. */ + break; + } + } + } + } +/*-----------------------------------------------------------*/ + + static void prvSwitchTimerLists( void ) + { + TickType_t xNextExpireTime; + List_t * pxTemp; + + /* The tick count has overflowed. The timer lists must be switched. + * If there are any timers still referenced from the current timer list + * then they must have expired and should be processed before the lists + * are switched. */ + while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + + /* Process the expired timer. For auto-reload timers, be careful to + * process only expirations that occur on the current list. Further + * expirations must wait until after the lists are switched. */ + prvProcessExpiredTimer( xNextExpireTime, tmrMAX_TIME_BEFORE_OVERFLOW ); + } + + pxTemp = pxCurrentTimerList; + pxCurrentTimerList = pxOverflowTimerList; + pxOverflowTimerList = pxTemp; + } +/*-----------------------------------------------------------*/ + + static void prvCheckForValidListAndQueue( void ) + { + /* Check that the list from which active timers are referenced, and the + * queue used to communicate with the timer service, have been + * initialised. */ + taskENTER_CRITICAL(); + { + if( xTimerQueue == NULL ) + { + vListInitialise( &xActiveTimerList1 ); + vListInitialise( &xActiveTimerList2 ); + pxCurrentTimerList = &xActiveTimerList1; + pxOverflowTimerList = &xActiveTimerList2; + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* The timer queue is allocated statically in case + * configSUPPORT_DYNAMIC_ALLOCATION is 0. */ + PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ + PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ + + xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); + } + #else + { + xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) ); + } + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + if( xTimerQueue != NULL ) + { + vQueueAddToRegistry( xTimerQueue, "TmrQ" ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configQUEUE_REGISTRY_SIZE */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) + { + BaseType_t xReturn; + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + + /* Is the timer in the list of active timers? */ + taskENTER_CRITICAL(); + { + if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } /*lint !e818 Can't be pointer to const due to the typedef. */ +/*-----------------------------------------------------------*/ + + void * pvTimerGetTimerID( const TimerHandle_t xTimer ) + { + Timer_t * const pxTimer = xTimer; + void * pvReturn; + + configASSERT( xTimer ); + + taskENTER_CRITICAL(); + { + pvReturn = pxTimer->pvTimerID; + } + taskEXIT_CRITICAL(); + + return pvReturn; + } +/*-----------------------------------------------------------*/ + + void vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) + { + Timer_t * const pxTimer = xTimer; + + configASSERT( xTimer ); + + taskENTER_CRITICAL(); + { + pxTimer->pvTimerID = pvNewID; + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + + BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + BaseType_t * pxHigherPriorityTaskWoken ) + { + DaemonTaskMessage_t xMessage; + BaseType_t xReturn; + + /* Complete the message with the function parameters and post it to the + * daemon task. */ + xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR; + xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend; + xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1; + xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2; + + xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); + + tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn ); + + return xReturn; + } + + #endif /* INCLUDE_xTimerPendFunctionCall */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + + BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) + { + DaemonTaskMessage_t xMessage; + BaseType_t xReturn; + + /* This function can only be called after a timer has been created or + * after the scheduler has been started because, until then, the timer + * queue does not exist. */ + configASSERT( xTimerQueue ); + + /* Complete the message with the function parameters and post it to the + * daemon task. */ + xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK; + xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend; + xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1; + xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2; + + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); + + tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn ); + + return xReturn; + } + + #endif /* INCLUDE_xTimerPendFunctionCall */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) + { + return ( ( Timer_t * ) xTimer )->uxTimerNumber; + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void vTimerSetTimerNumber( TimerHandle_t xTimer, + UBaseType_t uxTimerNumber ) + { + ( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber; + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +/* This entire source file will be skipped if the application is not configured + * to include software timer functionality. If you want to include software timer + * functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */ +#endif /* configUSE_TIMERS == 1 */ diff --git a/microej/MIMXRT595-evk_platform-CM4hardfp_GCC48-2.0.0/.project b/microej/MIMXRT595-evk_platform-CM4hardfp_GCC48-2.0.0/.project new file mode 100644 index 0000000..89a1c9b --- /dev/null +++ b/microej/MIMXRT595-evk_platform-CM4hardfp_GCC48-2.0.0/.project @@ -0,0 +1,17 @@ + + + MIMXRT595-evk_platform-CM4hardfp_GCC48-2.0.0 + + + + + + com.is2t.microej.pro.workbench.jpfBuilder + + + + + + com.is2t.microej.pro.workbench.jpfNature + + diff --git a/nxpvee-mimxrt595-evk-round-apps/.classpath b/microej/apps/.classpath similarity index 100% rename from nxpvee-mimxrt595-evk-round-apps/.classpath rename to microej/apps/.classpath diff --git a/nxpvee-mimxrt595-evk-round-apps/.gitignore b/microej/apps/.gitignore similarity index 100% rename from nxpvee-mimxrt595-evk-round-apps/.gitignore rename to microej/apps/.gitignore diff --git a/nxpvee-mimxrt595-evk-round-apps/.project b/microej/apps/.project similarity index 100% rename from nxpvee-mimxrt595-evk-round-apps/.project rename to microej/apps/.project diff --git a/nxpvee-mimxrt595-evk-round-apps/.settings/org.eclipse.jdt.core.prefs b/microej/apps/.settings/org.eclipse.jdt.core.prefs similarity index 100% rename from nxpvee-mimxrt595-evk-round-apps/.settings/org.eclipse.jdt.core.prefs rename to microej/apps/.settings/org.eclipse.jdt.core.prefs diff --git a/nxpvee-mimxrt595-evk-round-apps/.settings/org.eclipse.jdt.ui.prefs b/microej/apps/.settings/org.eclipse.jdt.ui.prefs similarity index 100% rename from nxpvee-mimxrt595-evk-round-apps/.settings/org.eclipse.jdt.ui.prefs rename to microej/apps/.settings/org.eclipse.jdt.ui.prefs diff --git a/nxpvee-mimxrt595-evk-round-apps/LICENSE.txt b/microej/apps/LICENSE.txt similarity index 100% rename from nxpvee-mimxrt595-evk-round-apps/LICENSE.txt rename to microej/apps/LICENSE.txt diff --git a/nxpvee-mimxrt595-evk-round-apps/build/common.properties b/microej/apps/build/common.properties similarity index 100% rename from nxpvee-mimxrt595-evk-round-apps/build/common.properties rename to microej/apps/build/common.properties diff --git a/nxpvee-mimxrt595-evk-round-apps/launchers/AnimatedMascot (EMB).launch b/microej/apps/launchers/AnimatedMascot (EMB).launch similarity index 92% rename from nxpvee-mimxrt595-evk-round-apps/launchers/AnimatedMascot (EMB).launch rename to microej/apps/launchers/AnimatedMascot (EMB).launch index b697a1e..eb4aba9 100644 --- a/nxpvee-mimxrt595-evk-round-apps/launchers/AnimatedMascot (EMB).launch +++ b/microej/apps/launchers/AnimatedMascot (EMB).launch @@ -14,10 +14,10 @@ - + @@ -39,11 +39,12 @@ - + + @@ -55,7 +56,9 @@ + + @@ -73,6 +76,8 @@ + + @@ -82,12 +87,12 @@ - + - + diff --git a/microej/apps/launchers/AnimatedMascot (SIM).launch b/microej/apps/launchers/AnimatedMascot (SIM).launch new file mode 100644 index 0000000..ef07c17 --- /dev/null +++ b/microej/apps/launchers/AnimatedMascot (SIM).launch @@ -0,0 +1,116 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/nxpvee-mimxrt595-evk-round-apps/launchers/SimpleGFX (EMB).launch b/microej/apps/launchers/SimpleGFX (EMB).launch similarity index 92% rename from nxpvee-mimxrt595-evk-round-apps/launchers/SimpleGFX (EMB).launch rename to microej/apps/launchers/SimpleGFX (EMB).launch index 7033c05..c60cd99 100644 --- a/nxpvee-mimxrt595-evk-round-apps/launchers/SimpleGFX (EMB).launch +++ b/microej/apps/launchers/SimpleGFX (EMB).launch @@ -14,10 +14,10 @@ - + @@ -39,11 +39,12 @@ - + + @@ -55,7 +56,9 @@ + + @@ -73,6 +76,8 @@ + + @@ -82,12 +87,12 @@ - + - + diff --git a/nxpvee-mimxrt595-evk-round-apps/launchers/SimpleGFX (SIM).launch b/microej/apps/launchers/SimpleGFX (SIM).launch similarity index 77% rename from nxpvee-mimxrt595-evk-round-apps/launchers/SimpleGFX (SIM).launch rename to microej/apps/launchers/SimpleGFX (SIM).launch index 4e2593f..2b0b007 100644 --- a/nxpvee-mimxrt595-evk-round-apps/launchers/SimpleGFX (SIM).launch +++ b/microej/apps/launchers/SimpleGFX (SIM).launch @@ -4,14 +4,20 @@ + + + + + - + + @@ -23,17 +29,23 @@ + + + + - + + + @@ -41,13 +53,19 @@ + + + + + + @@ -58,6 +76,8 @@ + + @@ -72,7 +92,7 @@ - + diff --git a/microej/apps/module.ant b/microej/apps/module.ant new file mode 100644 index 0000000..cc60e10 --- /dev/null +++ b/microej/apps/module.ant @@ -0,0 +1,8 @@ + + + + + + + diff --git a/microej/apps/module.ivy b/microej/apps/module.ivy new file mode 100644 index 0000000..db2438a --- /dev/null +++ b/microej/apps/module.ivy @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/nxpvee-mimxrt595-evk-round-apps/src/test/java/.gitkeep b/microej/apps/src/main/java/.gitkeep similarity index 100% rename from nxpvee-mimxrt595-evk-round-apps/src/test/java/.gitkeep rename to microej/apps/src/main/java/.gitkeep diff --git a/nxpvee-mimxrt595-evk-round-apps/src/main/java/com/nxp/animatedMascot/AnimatedMascot.java b/microej/apps/src/main/java/com/nxp/animatedMascot/AnimatedMascot.java similarity index 95% rename from nxpvee-mimxrt595-evk-round-apps/src/main/java/com/nxp/animatedMascot/AnimatedMascot.java rename to microej/apps/src/main/java/com/nxp/animatedMascot/AnimatedMascot.java index 53cc1b0..361b82c 100644 --- a/nxpvee-mimxrt595-evk-round-apps/src/main/java/com/nxp/animatedMascot/AnimatedMascot.java +++ b/microej/apps/src/main/java/com/nxp/animatedMascot/AnimatedMascot.java @@ -42,7 +42,7 @@ private void start() { final Matrix matrix = new Matrix(); - final VectorImage mascot = VectorImage.getImage("/images/mascot.xml"); //$NON-NLS-1$ + final VectorImage mascot = VectorImage.getImage("/vectorimages/mascot.xml"); //$NON-NLS-1$ // Prepare matrix to scale the image to the display size matrix.setScale(display.getWidth() / mascot.getWidth(), display.getHeight() / mascot.getHeight()); diff --git a/nxpvee-mimxrt595-evk-round-apps/src/main/java/com/nxp/simpleGFX/SimpleGFX.java b/microej/apps/src/main/java/com/nxp/simpleGFX/SimpleGFX.java similarity index 94% rename from nxpvee-mimxrt595-evk-round-apps/src/main/java/com/nxp/simpleGFX/SimpleGFX.java rename to microej/apps/src/main/java/com/nxp/simpleGFX/SimpleGFX.java index 8d034da..5abb26d 100644 --- a/nxpvee-mimxrt595-evk-round-apps/src/main/java/com/nxp/simpleGFX/SimpleGFX.java +++ b/microej/apps/src/main/java/com/nxp/simpleGFX/SimpleGFX.java @@ -1,5 +1,5 @@ /** - * Copyright 2022 NXP + * Copyright 2022-2023 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,8 +16,8 @@ public class SimpleGFX extends Thread { final static int NXP_ORANGE = 0xF9B500; - final static int NXP_BLUE = 0x7BB1DB; - final static int NXP_GREEN = 0xC9D200; + final static int NXP_BLUE = 0x0EAFE0; + final static int NXP_GREEN = 0x69CA00; final static int DISPLAY_SIZE = 390; private static int grey = 0xFFFFFF; @@ -74,7 +74,7 @@ private static void draw_all(GraphicsContext g, int t) { decrease_grey = true; } } - Painter.fillCircle(g, 0, 0, 390); + Painter.fillCircle(g, 0, 0, DISPLAY_SIZE); // int centre = this.DISPLAY_SIZE / 2; // double sine_orange = 30.0 * Math.cos(t * Math.PI / 45.0); // double sine_blue = 75.0 * Math.sin(t * Math.PI / 45.0); diff --git a/nxpvee-mimxrt595-evk-round-apps/src/main/java/com/nxp/simpleGFX/SimpleGFXNatives.java b/microej/apps/src/main/java/com/nxp/simpleGFX/SimpleGFXNatives.java similarity index 100% rename from nxpvee-mimxrt595-evk-round-apps/src/main/java/com/nxp/simpleGFX/SimpleGFXNatives.java rename to microej/apps/src/main/java/com/nxp/simpleGFX/SimpleGFXNatives.java diff --git a/nxpvee-mimxrt595-evk-round-apps/src/test/resources/.gitkeep b/microej/apps/src/main/resources/.gitkeep similarity index 100% rename from nxpvee-mimxrt595-evk-round-apps/src/test/resources/.gitkeep rename to microej/apps/src/main/resources/.gitkeep diff --git a/microej/apps/src/main/resources/com/nxp/animatedMascot/AnimatedMascot.vectorimages.list b/microej/apps/src/main/resources/com/nxp/animatedMascot/AnimatedMascot.vectorimages.list new file mode 100644 index 0000000..9d456dc --- /dev/null +++ b/microej/apps/src/main/resources/com/nxp/animatedMascot/AnimatedMascot.vectorimages.list @@ -0,0 +1,7 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# + +/vectorimages/mascot.xml:VGF diff --git a/nxpvee-mimxrt595-evk-round-apps/src/main/resources/images/mascot.xml b/microej/apps/src/main/resources/vectorimages/mascot.xml similarity index 100% rename from nxpvee-mimxrt595-evk-round-apps/src/main/resources/images/mascot.xml rename to microej/apps/src/main/resources/vectorimages/mascot.xml diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/obj/.gitkeep b/microej/apps/src/test/java/.gitkeep similarity index 100% rename from nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/obj/.gitkeep rename to microej/apps/src/test/java/.gitkeep diff --git a/nxpvee-mimxrt595-evk-round-mock/src/main/java/.gitkeep b/microej/apps/src/test/resources/.gitkeep similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/src/main/java/.gitkeep rename to microej/apps/src/test/resources/.gitkeep diff --git a/nxpvee-mimxrt595-evk-round-fp/.classpath b/microej/front-panel/.classpath similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/.classpath rename to microej/front-panel/.classpath diff --git a/nxpvee-mimxrt595-evk-round-fp/.gitignore b/microej/front-panel/.gitignore similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/.gitignore rename to microej/front-panel/.gitignore diff --git a/nxpvee-mimxrt595-evk-round-fp/.project b/microej/front-panel/.project similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/.project rename to microej/front-panel/.project diff --git a/microej/front-panel/module.ivy b/microej/front-panel/module.ivy new file mode 100644 index 0000000..0944a6a --- /dev/null +++ b/microej/front-panel/module.ivy @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + diff --git a/nxpvee-mimxrt595-evk-round-fp/src/main/java/ej/fp/widget/ButtonListener.java b/microej/front-panel/src/main/java/ej/fp/widget/ButtonListener.java similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/src/main/java/ej/fp/widget/ButtonListener.java rename to microej/front-panel/src/main/java/ej/fp/widget/ButtonListener.java diff --git a/nxpvee-mimxrt595-evk-round-fp/src/main/resources/.gitignore b/microej/front-panel/src/main/resources/.gitignore similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/src/main/resources/.gitignore rename to microej/front-panel/src/main/resources/.gitignore diff --git a/nxpvee-mimxrt595-evk-round-fp/src/main/resources/Board.png b/microej/front-panel/src/main/resources/Board.png similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/src/main/resources/Board.png rename to microej/front-panel/src/main/resources/Board.png diff --git a/nxpvee-mimxrt595-evk-round-fp/src/main/resources/Button.png b/microej/front-panel/src/main/resources/Button.png similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/src/main/resources/Button.png rename to microej/front-panel/src/main/resources/Button.png diff --git a/nxpvee-mimxrt595-evk-round-fp/src/main/resources/LedOff.png b/microej/front-panel/src/main/resources/LedOff.png similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/src/main/resources/LedOff.png rename to microej/front-panel/src/main/resources/LedOff.png diff --git a/nxpvee-mimxrt595-evk-round-fp/src/main/resources/LedRed.png b/microej/front-panel/src/main/resources/LedRed.png similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/src/main/resources/LedRed.png rename to microej/front-panel/src/main/resources/LedRed.png diff --git a/nxpvee-mimxrt595-evk-round-fp/src/main/resources/PushedButton.png b/microej/front-panel/src/main/resources/PushedButton.png similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/src/main/resources/PushedButton.png rename to microej/front-panel/src/main/resources/PushedButton.png diff --git a/nxpvee-mimxrt595-evk-round-fp/src/main/resources/button1.png b/microej/front-panel/src/main/resources/button1.png similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/src/main/resources/button1.png rename to microej/front-panel/src/main/resources/button1.png diff --git a/nxpvee-mimxrt595-evk-round-fp/src/main/resources/button1_pushed.png b/microej/front-panel/src/main/resources/button1_pushed.png similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/src/main/resources/button1_pushed.png rename to microej/front-panel/src/main/resources/button1_pushed.png diff --git a/nxpvee-mimxrt595-evk-round-fp/src/main/resources/button2.png b/microej/front-panel/src/main/resources/button2.png similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/src/main/resources/button2.png rename to microej/front-panel/src/main/resources/button2.png diff --git a/nxpvee-mimxrt595-evk-round-fp/src/main/resources/button2_pushed.png b/microej/front-panel/src/main/resources/button2_pushed.png similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/src/main/resources/button2_pushed.png rename to microej/front-panel/src/main/resources/button2_pushed.png diff --git a/nxpvee-mimxrt595-evk-round-fp/src/main/resources/frontpanel.fp b/microej/front-panel/src/main/resources/frontpanel.fp similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/src/main/resources/frontpanel.fp rename to microej/front-panel/src/main/resources/frontpanel.fp diff --git a/nxpvee-mimxrt595-evk-round-fp/src/main/resources/mask_392.png b/microej/front-panel/src/main/resources/mask_392.png similarity index 100% rename from nxpvee-mimxrt595-evk-round-fp/src/main/resources/mask_392.png rename to microej/front-panel/src/main/resources/mask_392.png diff --git a/nxpvee-mimxrt595-evk-round-imageGenerator/.classpath b/microej/imageGenerator/.classpath similarity index 100% rename from nxpvee-mimxrt595-evk-round-imageGenerator/.classpath rename to microej/imageGenerator/.classpath diff --git a/nxpvee-mimxrt595-evk-round-imageGenerator/.project b/microej/imageGenerator/.project similarity index 100% rename from nxpvee-mimxrt595-evk-round-imageGenerator/.project rename to microej/imageGenerator/.project diff --git a/nxpvee-mimxrt595-evk-round-imageGenerator/.settings/org.eclipse.jdt.core.prefs b/microej/imageGenerator/.settings/org.eclipse.jdt.core.prefs similarity index 100% rename from nxpvee-mimxrt595-evk-round-imageGenerator/.settings/org.eclipse.jdt.core.prefs rename to microej/imageGenerator/.settings/org.eclipse.jdt.core.prefs diff --git a/microej/imageGenerator/module.ivy b/microej/imageGenerator/module.ivy new file mode 100644 index 0000000..f7a18e1 --- /dev/null +++ b/microej/imageGenerator/module.ivy @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/nxpvee-mimxrt595-evk-round-imageGenerator/src/main/java/com/microej/graphicalengine/generator/MicroUIGeneratorExtension.java b/microej/imageGenerator/src/main/java/com/microej/graphicalengine/generator/MicroUIGeneratorExtension.java similarity index 100% rename from nxpvee-mimxrt595-evk-round-imageGenerator/src/main/java/com/microej/graphicalengine/generator/MicroUIGeneratorExtension.java rename to microej/imageGenerator/src/main/java/com/microej/graphicalengine/generator/MicroUIGeneratorExtension.java diff --git a/nxpvee-mimxrt595-evk-round-imageGenerator/src/main/resources/META-INF/services/com.microej.tool.ui.generator.MicroUIRawImageGeneratorExtension b/microej/imageGenerator/src/main/resources/META-INF/services/com.microej.tool.ui.generator.MicroUIRawImageGeneratorExtension similarity index 100% rename from nxpvee-mimxrt595-evk-round-imageGenerator/src/main/resources/META-INF/services/com.microej.tool.ui.generator.MicroUIRawImageGeneratorExtension rename to microej/imageGenerator/src/main/resources/META-INF/services/com.microej.tool.ui.generator.MicroUIRawImageGeneratorExtension diff --git a/nxpvee-mimxrt595-evk-round-mock/.classpath b/microej/mock/.classpath similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/.classpath rename to microej/mock/.classpath diff --git a/nxpvee-mimxrt595-evk-round-mock/.gitignore b/microej/mock/.gitignore similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/.gitignore rename to microej/mock/.gitignore diff --git a/nxpvee-mimxrt595-evk-round-mock/.project b/microej/mock/.project similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/.project rename to microej/mock/.project diff --git a/nxpvee-mimxrt595-evk-round-mock/HILEngine.jar b/microej/mock/HILEngine.jar similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/HILEngine.jar rename to microej/mock/HILEngine.jar diff --git a/nxpvee-mimxrt595-evk-round-mock/LICENSE.txt b/microej/mock/LICENSE.txt similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/LICENSE.txt rename to microej/mock/LICENSE.txt diff --git a/nxpvee-mimxrt595-evk-round-mock/README.md b/microej/mock/README.md similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/README.md rename to microej/mock/README.md diff --git a/nxpvee-mimxrt595-evk-round-mock/content/scripts/init-evk-platform-mock-s3/evk_platform_mock_init.xml b/microej/mock/content/scripts/init-evk-platform-mock-s3/evk_platform_mock_init.xml similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/content/scripts/init-evk-platform-mock-s3/evk_platform_mock_init.xml rename to microej/mock/content/scripts/init-evk-platform-mock-s3/evk_platform_mock_init.xml diff --git a/nxpvee-mimxrt595-evk-round-mock/lib/HILEngine.jar b/microej/mock/lib/HILEngine.jar similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/lib/HILEngine.jar rename to microej/mock/lib/HILEngine.jar diff --git a/nxpvee-mimxrt595-evk-round-mock/module.ant b/microej/mock/module.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/module.ant rename to microej/mock/module.ant diff --git a/nxpvee-mimxrt595-evk-round-mock/module.ivy b/microej/mock/module.ivy similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/module.ivy rename to microej/mock/module.ivy diff --git a/nxpvee-mimxrt595-evk-round-mock/module.pro b/microej/mock/module.pro similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/module.pro rename to microej/mock/module.pro diff --git a/nxpvee-mimxrt595-evk-round-mock/src/main/resources/.gitkeep b/microej/mock/src/main/java/.gitkeep similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/src/main/resources/.gitkeep rename to microej/mock/src/main/java/.gitkeep diff --git a/nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/mock/Dashboard.java b/microej/mock/src/main/java/com/microej/mock/Dashboard.java similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/mock/Dashboard.java rename to microej/mock/src/main/java/com/microej/mock/Dashboard.java diff --git a/nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/mock/MockupApplication.java b/microej/mock/src/main/java/com/microej/mock/MockupApplication.java similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/mock/MockupApplication.java rename to microej/mock/src/main/java/com/microej/mock/MockupApplication.java diff --git a/nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/mock/MockupLauncher.java b/microej/mock/src/main/java/com/microej/mock/MockupLauncher.java similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/mock/MockupLauncher.java rename to microej/mock/src/main/java/com/microej/mock/MockupLauncher.java diff --git a/nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/service/HeartRateService.java b/microej/mock/src/main/java/com/microej/service/HeartRateService.java similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/service/HeartRateService.java rename to microej/mock/src/main/java/com/microej/service/HeartRateService.java diff --git a/nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/service/HeartRateServiceNative.java b/microej/mock/src/main/java/com/microej/service/HeartRateServiceNative.java similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/service/HeartRateServiceNative.java rename to microej/mock/src/main/java/com/microej/service/HeartRateServiceNative.java diff --git a/nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/service/PowerService.java b/microej/mock/src/main/java/com/microej/service/PowerService.java similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/service/PowerService.java rename to microej/mock/src/main/java/com/microej/service/PowerService.java diff --git a/nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/service/PowerServiceNative.java b/microej/mock/src/main/java/com/microej/service/PowerServiceNative.java similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/src/main/java/com/microej/service/PowerServiceNative.java rename to microej/mock/src/main/java/com/microej/service/PowerServiceNative.java diff --git a/nxpvee-mimxrt595-evk-round-mock/src/main/java/com/nxp/simpleGFX/SimpleGFXNatives.java b/microej/mock/src/main/java/com/nxp/simpleGFX/SimpleGFXNatives.java similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/src/main/java/com/nxp/simpleGFX/SimpleGFXNatives.java rename to microej/mock/src/main/java/com/nxp/simpleGFX/SimpleGFXNatives.java diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/src/main/java/.gitkeep b/microej/mock/src/main/resources/.gitkeep similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/src/main/java/.gitkeep rename to microej/mock/src/main/resources/.gitkeep diff --git a/nxpvee-mimxrt595-evk-round-mock/src/main/resources/images/logo_microej_1500px.png b/microej/mock/src/main/resources/images/logo_microej_1500px.png similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/src/main/resources/images/logo_microej_1500px.png rename to microej/mock/src/main/resources/images/logo_microej_1500px.png diff --git a/nxpvee-mimxrt595-evk-round-mock/src/main/resources/images/watchface.png b/microej/mock/src/main/resources/images/watchface.png similarity index 100% rename from nxpvee-mimxrt595-evk-round-mock/src/main/resources/images/watchface.png rename to microej/mock/src/main/resources/images/watchface.png diff --git a/microej/validation/core/README.rst b/microej/validation/core/README.rst new file mode 100644 index 0000000..7ec1bf0 --- /dev/null +++ b/microej/validation/core/README.rst @@ -0,0 +1,897 @@ +.. ReStructuredText + +.. Copyright 2019-2023 MicroEJ Corp. MicroEJ Corp. All rights reserved. + +.. Use of this source code is governed by a BSD-style license that can be found with this software. + + + +********************** + +Core Engine Test Suite + +********************** + + + +Overview + +======== + + + +This folder contains sources and projects to test drivers and implementation of print, time base, RAM, Core (see `Tests Description`_), and MicroEJ Core (see `MicroEJ Core Validation`_). + + + +All tests can be run in one step: all tests will be executed one by one + +and are run in a specific order, *next one* expects *previous one* is + +passed. + + + +For each test, the configuration and results are described in a + +dedicated section. See `Quick Start`_ section which summarize how to configure the + +tests, how to launch them and how to analyze the report. + + + +Requirements + +============ + + + +- Follow the `main Readme <../../README.rst>`_. + +- EEMBC Coremark + + + +Quick Start + +=========== + + + +Configuration + +------------- + + + +#. In your BSP project, add all files of these folders as source files: + + + + * ``tests/core/c/src/`` + + * ``framework/c/utils/src/`` + + * ``framework/c/embunit/embUnit/`` + + * ``framework/c/CoreMark/`` + + + +#. In your BSP project, add these folders as include paths: + + + + * ``tests/core/c/inc/`` + + * ``framework/c/utils/inc/`` + + * ``framework/c/embunit/embUnit/`` + + * ``framework/c/CoreMark/`` + + + +#. Port EEMBC CoreMark (http://www.eembc.org/coremark/index.php) to your platform: + + + + * Pick one of the provided skeleton configuration folders located in ``framework/c/CoreMark/`` (*barebones* is a good choice, but one of the other folders may match your project better). Copy its source files into your BSP project and make sure they will be compiled/included. + + * Define the constants and functions required by CoreMark. What needs to be defined will depend on the configuration skeleton you picked, but CoreMark will at least require a clock and a text output. If you chose the *barebones* skeleton configuration, you will need to define the following: + + + + * In ``core_portme.h``: + + + + * Define the ``ITERATIONS`` constant as a number of iterations high enough to keep the benchmark running for at least 10 seconds. You will have to adjust its value depending on the hardware and according to the benchmark report, but ``1000`` is a good starting point. + + * Define the ``CLOCKS_PER_SEC`` as the frequency of your platform's clock ticks. CoreMark needs to be provided a clock to measure the time taken by the benchmarked operations. This constant will be used to convert the clock tick count to a value in seconds. + + * Define the ``TIMER_RES_DIVIDER`` constant. Its value will be used to prevent overflows of the clock tick count, but will reduce the time measurement resolution in return. Unless the resolution of your clock is too high and you experience integer overflows, you can set this constant to ``1``. + + * Go over the whole file and edit constants as needed for your platform. Specifically, you may want to edit the compiler version and flags, as well as some type definitions. + + + + * In ``core_portme.c``: + + + + * Implement ``barebones_clock`` to return the current time, measured in clock ticks. A clock frequency of 1 kHz is sufficient for CoreMark's measurements. You may use ``microej_time_get_current_time``, which should already be defined as it is required for the platform to run. + + * Add any needed initialization step to ``portable_init``. Namely, you might need to initialize the UART output there (if it is not yet initialized when reaching this point). + + + + * In ``ee_printf.c``: + + + + * Implement ``uart_send_char`` to send a single character through the UART output. + + + + * Finally, insert the directive line :code:`#define main core_main` in ``core_portme.h`` so that the BSP's main function does not conflict with CoreMark's main function. + + + +#. Define all functions declared in ``x_ram_checks.h`` and ``x_core_benchmark.h``. + + + + * **RAM tests**: The RAM benchmark will perform several read, write and copy operations on different memory areas. You must allocate appropriate memory areas for these operations, and define all the ``X_RAM_CHECK`` functions that will give the benchmark access to these areas. See `RAM Tests: t_core_ram.c`_ and `RAM Benchs: t_core_ram.c`_ for more information. + + * **Run CoreMark**: Call CoreMark's main function in ``X_CORE_BENCHMARK_run``. This function should only call ``core_main``, and return ``true`` if CoreMark was run properly. + + + +#. Implement other functions required by the benchmark: + + + + * :code:`int printf(const char* format, ...)` is required to output the benchmark results. If this function is not already defined, or if its ouptut is not visible, you will need to define your own version of it. + + * :code:`int64_t UTIL_TIME_BASE_getTime()` (declared in ``u_time_base.h``) must return the current time, in microseconds. You can call ``microej_time_get_time_nanos``, which should already be defined in your BSP project, as it is required for the platform to run. + + * :code:`void UTIL_TIME_BASE_initialize()` (declared in ``u_time_base.h``) should contain any necessary initialization step required for ``UTIL_TIME_BASE_getTime`` to perform its task. + + + +#. Locate the call to ``microej_main`` in the BSP project. Include the ``t_core_main.h`` header file in this file, and add a call to the function ``T_CORE_main`` just before the call to ``microej_main``. + +#. In the MicroEJ SDK, import the MicroEJ project ``java-testsuite-runner-core`` from the folder ``tests/core``. + +#. Follow `MicroEJ Core Validation Readme `_ and build this MicroEJ Application against the MicroEJ Platform to qualify. + +#. Build the BSP and link it with the MicroEJ Platform runtime library and MicroEJ Application. + + + +Expected Results + +---------------- + + + +:: + + + + start + + . + + **************************************************************************** + + ** Platform Qualification Core ** + + ** version 1.0 ** + + **************************************************************************** + + * Copyright 2013-2020 MicroEJ Corp. All rights reserved. * + + * Use of this source code is governed by a BSD-style license * + + * that can be found with this software. * + + **************************************************************************** + + + + Print test: + + if this message is displayed, the test is passed! + + + + Time base check: + + . + + RAM tests: + + ..................... + + RAM speed benchmark: + + .RAM speed average read access (according to your configuration file 8/16/32 bits) : 51.180522MBytes/s + + .RAM speed average write access (according to your configuration file 8/16/32 bits) : 131.289164 MBytes/s + + .RAM speed average transfert access (according to your configuration file 8/16/32 bits) : 86.466471MBytes/s + + + + Core/Flash benchmark: + + .2K performance run parameters for coremark. + + CoreMark Size : 666 + + Total ticks : 12052657 + + Total time (secs): 12.052657 + + Iterations/Sec : 497.815544 + + Iterations : 6000 + + Compiler version : ARMCC V5.06 update 4 (build 422) + + Compiler flags : -c --cpu Cortex-M4.fp -D__MICROLIB -g -O3 -Otime --apcs=interwork --split_sections -D__UVISION_VERSION="523" -D_RTE_ -DSTM32L496xx -DUSE_HAL_DRIVER -DSTM32L496xx + + Memory location : STATIC + + seedcrc : 0xe9f5 + + [0]crclist : 0xe714 + + [0]crcmatrix : 0x1fd7 + + [0]crcstate : 0x8e3a + + [0]crcfinal : 0xa14c + + Correct operation validated. See readme.txt for run and reporting rules. + + CoreMark 1.0 : 497.815544 / ARMCC V5.06 update 4 (build 422) -c --cpu Cortex-M4.fp -D__MICROLIB -g -O3 -Otime --apcs=interwork --split_sections -D__UVISION_VERSION="523" -D_RTE_ -DSTM32L496xx -DUSE_HAL_DRIVER -DSTM32L496xx / STATIC + + + + OK (27 tests) + + MicroEJ START + + ***************************************************************************************************** + + * MicroEJ Core Validation - 3.2.0 * + + ***************************************************************************************************** + + * Copyright 2013-2023 MicroEJ Corp. All rights reserved. * + + * Use of this source code is governed by a BSD-style license that can be found with this software. * + + ***************************************************************************************************** + + + + -> Check visible clock (LLMJVM_IMPL_getCurrentTime validation)... + + Property 'com.microej.core.tests.max.allowed.clock.tick.duration.milliseconds' is not set (default to '20' millisecondss) + + Property 'com.microej.core.tests.clock.seconds' is not set (default to '10' seconds) + + 1 + + 2 + + 3 + + 4 + + 5 + + 6 + + 7 + + 8 + + 9 + + 10 + + OK: testVisibleClock + + -> Check schedule request and wakeup (LLMJVM_IMPL_scheduleRequest and LLMJVM_IMPL_wakeupVM validation)... + + Property 'com.microej.core.tests.max.allowed.clock.tick.duration.milliseconds' is not set (default to '20' millisecondss) + + Waiting for 5s... + + ...done + + OK: testTime + + -> Check monotonic time (LLMJVM_IMPL_getCurrentTime, LLMJVM_IMPL_setApplicationTime validation)... + + Waiting for 5s... + + ...done + + OK: testMonotonicTime + + -> Check Java round robin (LLMJVM_IMPL_scheduleRequest validation)... + + For a best result, please disable all the C native tasks except the MicroEJ task. + + Task 3 is waiting for start... + + Task 2 is waiting for start... + + Task 1 is waiting for start... + + Task 0 is waiting for start... + + Starting tasks and wait for 10 seconds... + + Task 2 ends. + + Task 3 ends. + + Task 0 ends. + + Task 1 ends. + + ...done. + + OK: testJavaRoundRobin + + Main thread starts sleeping for 1s.. + + WaitMaxTimeThread starts sleeping for `Long.MAX_VALUE` milliseconds + + Main thread woke up! + + OK: testScheduleMaxTime + + -> Check isInReadOnlyMemory (LLBSP_IMPL_isInReadOnlyMemory validation)... + + Test synchronize on literal string + + Test synchronize on class + + Test multiple synchronize + + OK: testIsInReadOnlyMemory + + -> Check FPU (soft/hard FP option)... + + OK: testFPU + + -> Check floating-point arithmetic with NaN... + + -> Check floating-point arithmetic with 0.0 and -0.0... + + -> Check floating-point arithmetic with infinity... + + -> Check floating-point arithmetic with min values... + + -> Check floating-point division by 0.0... + + -> Check floating-point Math functions... + + -> Check integer arithmetic... + + OK: testFloatingPointArithmetic + + -> Check floating-point parser... + + OK: testParseFloatingPoint + + -> Check floating-point formatter... + + OK: testFormatFloatingPoint + + -> Check parsing a string as a double ; in some systems such operations may allocate memory in the C heap (strtod, strtof, malloc implementation)... + + OK: testParseDoubleStringHeap + + Property 'com.microej.core.tests.monotonic.time.check.seconds' is not set (default to '60' seconds) + + -> Check monotonic time consistency for 60 seconds (LLMJVM_IMPL_getCurrentTime)... + + ............................. + + OK: testMonotonicTimeIncreases + + -> Check current time clock tick duration (LLMJVM_IMPL_getCurrentTime, LLMJVM_IMPL_getTimeNanos)... + + Property 'com.microej.core.tests.max.allowed.clock.tick.duration.milliseconds' is not set (default to '20' millisecondss) + + Estimated LLMJVM_IMPL_getCurrentTime clock tick is 1 ms. + + Estimated LLMJVM_IMPL_getTimeNanos clock tick is lower than 4000 ns. + + OK: testSystemCurrentTimeClockTick + + -> Check schedule request clock tick duration (LLMJVM_IMPL_scheduleRequest)... + + Property 'com.microej.core.tests.max.allowed.clock.tick.duration.milliseconds' is not set (default to '20' millisecondss) + + Estimated LLMJVM_IMPL_scheduleRequest clock tick is 1 ms. + + OK: testScheduleRequestClockTick + + -> Check SNI native calling convention (ABI)... + + OK: testSniAbi + + PASSED: 15 + + MicroEJ END (exit code = 0) + + + +-------------- + + + +Tests Description + +================= + + + +Print: t_core_print.c + +--------------------- + + + +An implementation of ``print`` is required by MicroEJ Platform to debug + +the Java exceptions. Furthermore this implementation is also required to + +check this qualification bundle. + + + +**Configuration** + + + +The default implementation (the one implemented in the ``weak`` + +functions, see ``u_print.c``) calls ``stdio``\ s ``printf`` functions. + +Write your own functions if necessary. + + + +**Expected results** + + + +A message is just printed: + + + +:: + + + + **************************************************************************** + + ** Platform Qualification Core ** + + ** version 1.0 ** + + **************************************************************************** + + * Copyright 2013-2020 MicroEJ Corp. All rights reserved. * + + * Use of this source code is governed by a BSD-style license * + + * that can be found with this software. * + + **************************************************************************** + + + + Print test: + + if this message is displayed, the test is passed! + + + +Timer: t_core_time_base.c + +------------------------- + + + +A time counter is required by MicroEJ Platform. This timer must respect + +the following rules: + + + +* during MicroEJ Application, this counter must not return to zero + + (return in the past), + +* its precision must be around one or ten microseconds (often running + + at 1MHz). + + + +This timer can be the OS timer but most of time the OS timer does not + +respect the expected conditions. A hardware timer is often used instead. + +Its interrupt should be programmed to occur when the timer exceeds the + +half of the counter. Under interrupt, a software counter is updated. + +When application asks the time, an addition between this software + +counter and the current hardware timer is performed. + + + +This timer is used by the next qualification tests and by the LLMJVM + +implementation (see ``LLMJVM_impl.h``, functions + +``LLMJVM_IMPL_getCurrentTime`` and ``LLMJVM_IMPL_getTimeNanos``). + + + +This test ensures a timer is implemented but it does not check its + +accuracy (tested later). + + + +**Configuration** + + + +The default implementation (the one implemented in the ``weak`` + +functions, see ``u_time_base.c``) returns always ``0``. Write your own + +functions to implement the timer counter. + + + +**Expected results** + + + +No error must be thrown when executing this test: + + + +:: + + + + Time base check: + + . + + + +**Code Review** + + + +In addition to this automatic test, a code review must be done to spot potential + +race conditions that are diffcult to check automatically. + + + +In some implementations, the current time is calculated by adding 2 values: + + + +* a high-precision time with a quick overflow: ``hp_time`` + +* a low-precision time without any overflow risk: ``lp_time`` + + + +Low-precision time is incremented when high-precision time overflows. + +It is done usually in an interrupt or directly by the hardware. + +Computing time with an expression similar to ``time = lp_time + hp_time`` can lead + +to a wrong result because this operation is not done atomically. + +Moreover, the compiler may reorder the accesses to ``hp_time`` and ``lp_time``. + + + +The right pattern to use is the following one, where ``hp_time`` and ``lp_time`` + +are both declared **volatile**: + + + +:: + + + + // An interrupt may occur between read of lp_time and hp_time, + + // this interrupt may modify lp_time, + + // so, after accessing hp_time, we must check if lp_time has not been modified. + + do { + + lp_time_local = lp_time; + + hp_time_local = hp_time; + + } while (lp_time_local != lp_time); + + + + time = lp_time_local + hp_time_local; + + + +The code review consists in verifying the implementations of ``LLMJVM_IMPL_getCurrentTime`` + +and ``LLMJVM_IMPL_getTimeNanos`` to see if they follow the above recommendation. + + + +RAM Tests: t_core_ram.c + +----------------------- + + + +This test is useful to check external RAM when it is available on the + +hardware. The test performs several read and write actions, with + +different patterns. All accesses are aligned on value to write: 8, 16 or + +32 bits, like the MicroEJ Platform will use the RAM. + + + +To run, several functions must be implemented. See ``x_ram_checks.h``: + + + +* ``X_RAM_CHECKS_zone_t* X_RAM_CHECKS_get32bitZones(void)`` + +* ``X_RAM_CHECKS_zone_t* X_RAM_CHECKS_get16bitZones(void)`` + +* ``X_RAM_CHECKS_zone_t* X_RAM_CHECKS_get8bitZones(void)`` + +* ``uint8_t X_RAM_CHECKS_get32bitZoneNumber(void)`` + +* ``uint8_t X_RAM_CHECKS_get16bitZoneNumber(void)`` + +* ``uint8_t X_RAM_CHECKS_get8bitZoneNumber(void)`` + + + +**Configuration** + + + +Some default weak functions are already implemented and return ``NULL`` + +or ``0``; that means the test will not been performed. + + + +**Expected results** + + + +No error must be thrown when executing this test: + + + +:: + + + + RAM tests: + + ..................... + + + +RAM Benchs: t_core_ram.c + +------------------------ + + + +This test is useful to bench external RAM accesses when it is available + +on the hardware. This test only performs some benches. In addition with + +previous test, the external RAM timings can be adjusted to obtain the + +faster RAM accesses (and without any error!). + + + +**Configuration** + + + +To run, several functions must be implemented. See ``x_ram_checks.h``: + + + +* ``X_RAM_CHECKS_zone_t* X_RAM_CHECKS_get32bitSourceZone(void)`` + +* ``X_RAM_CHECKS_zone_t* X_RAM_CHECKS_get16bitSourceZone(void)`` + +* ``X_RAM_CHECKS_zone_t* X_RAM_CHECKS_get8bitSourceZone(void)`` + + + +These *sources* can target a region in internal flash, internal RAM or + +any other regions. + + + +**Expected results** + + + +:: + + + + RAM speed benchmark: + + .RAM speed average read access (according to your configuration file 8/16/32 bits) : 51.180522MBytes/s + + .RAM speed average write access (according to your configuration file 8/16/32 bits) : 131.289164 MBytes/s + + .RAM speed average transfert access (according to your configuration file 8/16/32 bits) : 86.466471MBytes/s + + + +**Notes** + + + +These results can be sent to MicroEJ in order to compare the BSP + +implementation with all others MicroEJ Platforms. + + + +Coremark: t_core_core_benchmark.c + +--------------------------------- + + + +EEMBC Coremark allows to compare CPU and BSP configurations. Refer to + +EEMBC Coremark website (http://www.eembc.org/coremark/index.php) to have + +more information about results. The Github repository containing the sources of Coremark (https://github.com/eembc/coremark.git) is linked as a submodule of this repository. + + + + + + + +**Configuration** + + + +To run this test: + + + +* Create ``core_portme.h`` and ``core_portme.h`` files to port EEMBC CoreMark. + +* Insert the directive line :code:`#define main core_main` into the ``core_portme.h``. + +* Implement ``X_CORE_BENCHMARK_run(void)`` from ``x_core_benchmark.h``. + + + +**Expected results** + + + +:: + + + + Core/Flash benchmark: + + .2K performance run parameters for coremark. + + CoreMark Size : 666 + + Total ticks : 12052657 + + Total time (secs): 12.052657 + + Iterations/Sec : 497.815544 + + Iterations : 6000 + + Compiler version : ARMCC V5.06 update 4 (build 422) + + Compiler flags : -c --cpu Cortex-M4.fp -D__MICROLIB -g -O3 -Otime --apcs=interwork --split_sections -D__UVISION_VERSION="523" -D_RTE_ -DSTM32L496xx -DUSE_HAL_DRIVER -DSTM32L496xx + + Memory location : STATIC + + seedcrc : 0xe9f5 + + [0]crclist : 0xe714 + + [0]crcmatrix : 0x1fd7 + + [0]crcstate : 0x8e3a + + [0]crcfinal : 0xa14c + + Correct operation validated. See readme.txt for run and reporting rules. + + CoreMark 1.0 : 497.815544 / ARMCC V5.06 update 4 (build 422) -c --cpu Cortex-M4.fp -D__MICROLIB -g -O3 -Otime --apcs=interwork --split_sections -D__UVISION_VERSION="523" -D_RTE_ -DSTM32L496xx -DUSE_HAL_DRIVER -DSTM32L496xx / STATIC + + + +MicroEJ Core Validation + +----------------------- + + + +This MicroEJ Application validates the LLAPI ``LLMJVM_impl.h`` + +implementation executing several tests. Two first tests check the time, + +and require an human check to be sure the time is correct. + + + +**Configuration** + + + +In the MicroEJ SDK, import the MicroEJ project `java-testsuite-runner-core <./java-testsuite-runner-core/>`_ from the folder ``tests/core``. + +Follow the MicroEJ Core Validation `README <./java-testsuite-runner-core/README.rst>`_ to build and link this MicroEJ Application against the MicroEJ Platform to qualify. + + + +**Expected results** + + + +No error must be thrown when executing this test. A typical execution trace is described in the MicroEJ Core Validation `README <./java-testsuite-runner-core/README.rst>`_ + +(the visible clock accuracy must be compared manually with an external clock). diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/.classpath b/microej/validation/core/java-testsuite-runner-core/.classpath similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/.classpath rename to microej/validation/core/java-testsuite-runner-core/.classpath diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/.gitignore b/microej/validation/core/java-testsuite-runner-core/.gitignore similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/.gitignore rename to microej/validation/core/java-testsuite-runner-core/.gitignore diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/.project b/microej/validation/core/java-testsuite-runner-core/.project similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/.project rename to microej/validation/core/java-testsuite-runner-core/.project diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/.settings/org.eclipse.jdt.core.prefs b/microej/validation/core/java-testsuite-runner-core/.settings/org.eclipse.jdt.core.prefs similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/.settings/org.eclipse.jdt.core.prefs rename to microej/validation/core/java-testsuite-runner-core/.settings/org.eclipse.jdt.core.prefs diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/.settings/org.eclipse.jdt.ui.prefs b/microej/validation/core/java-testsuite-runner-core/.settings/org.eclipse.jdt.ui.prefs similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/.settings/org.eclipse.jdt.ui.prefs rename to microej/validation/core/java-testsuite-runner-core/.settings/org.eclipse.jdt.ui.prefs diff --git a/microej/validation/core/java-testsuite-runner-core/CHANGELOG.rst b/microej/validation/core/java-testsuite-runner-core/CHANGELOG.rst new file mode 100644 index 0000000..1fceea1 --- /dev/null +++ b/microej/validation/core/java-testsuite-runner-core/CHANGELOG.rst @@ -0,0 +1,122 @@ +CHANGELOG +========= + +The format is based on `Keep a +Changelog `__, and this project +adheres to `Semantic +Versioning `__. + +.. _320--2023-06-14: + +[3.2.0] - 2023-06-14 +-------------------- + +Added +~~~~~ + +- Add check for floating-point arithmetic. +- Add check for floating-point parse and toString with scientific notation. +- Add check for SNI native calling convention (ABI). + +.. _310--2022-07-23: + +[3.1.0] - 2022-07-23 +-------------------- + +Added +~~~~~ + +- Add check for ``LLMJVM_IMPL_setApplicationTime``. +- Test Thread.sleep() with max number of milliseconds (Long.MAX_VALUE) does not cause an infinite loop in the MicroEJ Core due to time conversion overflow. +- Add check for ``LLMJVM_IMPL_getCurrentTime``, which should not go back in time. +- Add check for C malloc heap configuration which can be used when parsing float. +- Add check of ``LLMJVM_IMPL_scheduleRequest``, ``LLMJVM_IMPL_getCurrentTime``, and ``LLMJVM_IMPL_getTimeNanos`` precision + +Changed +~~~~~~~ + +- Split floating-point tests into 3 JUnit tests (FPU, parser, formatter) + to allow for fine-grained ignored tests list. +- Reformat to use standard MicroEJ Test Suite flow. +- Add tolerance on floating-point parsing. + +Fixed +~~~~~ + +- Fix assertions to conform with JUnit semantic of expected/actual. + +.. _302--2021-04-14: + +[3.0.2] - 2021-04-14 +-------------------- + +Fixed +~~~~~ + +- Ensure an error message is shown when the Round Robin test fails. + +.. _301--2021-02-12: + +[3.0.1] - 2021-02-12 +-------------------- + +Fixed +~~~~~ + +- Removed a comment about ``testFloat`` and ``testDouble`` functions + in ``MicroEJCoreValidation.java``. This is documented in the README + of the project. + +.. _300---2020-06-02: + +[3.0.0] - 2020-06-02 +-------------------- + +Changed +~~~~~~~ + +- Previous test functions are now JUnit test cases + +.. _240---2019-12-18: + +[2.4.0] - 2019-12-18 +-------------------- + +Added +~~~~~ + +- New floating-point related tests: parse/toString for float/double + +.. _changed-1: + +Changed +~~~~~~~ + +- Review round robin check test +- Update license + +.. _230---2019-10-01: + +[2.3.0] - 2019-10-01 +-------------------- + +Initial revision with Changelog. + +.. _added-1: + +Added +~~~~~ + +- Property ``MJVMPortValidation.clock.seconds`` to configure the time + in seconds of the visible clock test (default to 10s). + +.. _100---2017-09-29: + +[1.0.0] - 2017-09-29 +-------------------- + +Features : - Initial revision + +.. + Copyright 2020-2023 MicroEJ Corp. All rights reserved. + Use of this source code is governed by a BSD-style license that can be found with this software. diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/LICENSE.txt b/microej/validation/core/java-testsuite-runner-core/LICENSE.txt similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/LICENSE.txt rename to microej/validation/core/java-testsuite-runner-core/LICENSE.txt diff --git a/microej/validation/core/java-testsuite-runner-core/README.rst b/microej/validation/core/java-testsuite-runner-core/README.rst new file mode 100644 index 0000000..0b3cb1b --- /dev/null +++ b/microej/validation/core/java-testsuite-runner-core/README.rst @@ -0,0 +1,308 @@ +MicroEJ Core Validation +======================= + +Overview +-------- + +This project contains test cases aimed at validating the correct runtime execution +of a MicroEJ Platform connected to a Board Support Package (BSP). + +Tests are written as JUnit test cases, thus the main entry point is automatically generated by MicroEJ SDK. + +Tests can be launched: + +- as a standard Application by using a local launcher. +- as a Platform Test Suite by building the module. + +Requirements +------------ + +- MicroEJ SDK version ``5.1.0`` (included in MicroEJ SDK dist. ``19.05``). +- MicroEJ Platform built from a MicroEJ Architecture version ``7.0.0`` or higher. +- See Platform Test Suites `documentation <../../README.rst>`_. + +Usage +----- + +Launcher Mode +~~~~~~~~~~~~~ + +In MicroEJ SDK, + +- Select ``Run > Run Configurations...``. A launcher named + ``java-testsuite-runner-core`` should be available under + ``MicroEJ Application``. + +- In ``Execution`` tab, select the target MicroEJ Platform. + +- Click on ``Run`` button to compile the MicroEJ Application. + +- Before linking the application against the MicroEJ Platform, add the + following code in your BSP to test the FPU configuration and SNI native + calling convention: + +.. code:: c + + #include "sni.h" + + jfloat Java_com_microej_core_tests_MicroejCoreValidation_testFloat(jfloat a, jfloat b){ + return a * b; + } + + jdouble Java_com_microej_core_tests_MicroejCoreValidation_testDouble(jdouble a, jdouble b){ + return a * b; + } + + jint Java_com_microej_core_tests_MicroejCoreValidation_testNativeArguments01(jint i1, jint i2, jint i3, jint i4, jint i5, jint i6, jint i7, jint i8, jint i9, jint i10){ + if(i1==0x01020304 && + i2==0x05060708 && + i3==0x090A0B0C && + i4==0x0D0E0F10 && + i5==0x11121314 && + i6==0x15161718 && + i7==0x191A1B1C && + i8==0x1D1E1F20 && + i9==0x21222324 && + i10==0x25262728){ + return 0x292A2B2C; + } + else { + return 0; + } + } + + jlong Java_com_microej_core_tests_MicroejCoreValidation_testNativeArguments02(jlong l1, jlong l2, jlong l3, jlong l4, jlong l5, jlong l6, jlong l7, jlong l8, jlong l9, jlong l10){ + if(l1==0x2D2E2F3031323334ll && + l2==0x35363738393A3B3Cll && + l3==0x3D3E3F4041424344ll && + l4==0x45464748494A4B4Cll && + l5==0x4D4E4F5051525354ll && + l6==0x55565758595A5B5Cll && + l7==0x5D5E5F6061626364ll && + l8==0x65666768696A6B6Cll && + l9==0x6D6E6F7071727374ll && + l10==0x75767778797A7B7Cll){ + return 0x7D7E7F8081828384ll; + } + else { + return 0ll; + } + } + + jlong Java_com_microej_core_tests_MicroejCoreValidation_testNativeArguments03(jint i1, jlong l2, jint i3, jlong l4, jint i5, jlong l6, jint i7, jlong l8, jint i9, jlong l10){ + if(i1==0x85868788 && + l2==0x898A8B8C8D8E8F90ll && + i3==0x91929394 && + l4==0x95969798999A9B9Cll && + i5==0x9D9E9FA0 && + l6==0xA1A2A3A4A5A6A7A8ll && + i7==0xA9AAABAC && + l8==0xADAEAFB0B1B2B3B4ll && + i9==0xB5B6B7B8 && + l10==0xB9BABBBCBDBEBFC0ll){ + return 0xC1C2C3C4C5C6C7C8ll; + } + else { + return 0ll; + } + } + + jfloat Java_com_microej_core_tests_MicroejCoreValidation_testNativeArguments04(jfloat f1, jfloat f2, jfloat f3, jfloat f4, jfloat f5, jfloat f6, jfloat f7, jfloat f8, jfloat f9, jfloat f10){ + if(f1==1.0f && + f2==1.1f && + f3==1.2f && + f4==1.3f && + f5==1.4f && + f6==1.5f && + f7==1.6f && + f8==1.7f && + f9==1.8f && + f10==1.9f){ + return 2.0f; + } + else { + return 0.0f; + } + } + + jdouble Java_com_microej_core_tests_MicroejCoreValidation_testNativeArguments05(jdouble d1, jdouble d2, jdouble d3, jdouble d4, jdouble d5, jdouble d6, jdouble d7, jdouble d8, jdouble d9, jdouble d10){ + if(d1==2.0 && + d2==2.1 && + d3==2.2 && + d4==2.3 && + d5==2.4 && + d6==2.5 && + d7==2.6 && + d8==2.7 && + d9==2.8 && + d10==2.9){ + return 3.0; + } + else { + return 0.0; + } + } + + jdouble Java_com_microej_core_tests_MicroejCoreValidation_testNativeArguments06(jfloat f1, jdouble d2, jfloat f3, jdouble d4, jfloat f5, jdouble d6, jfloat f7, jdouble d8, jfloat f9, jdouble d10){ + if(f1==3.0f && + d2==3.1 && + f3==3.2f && + d4==3.3 && + f5==3.4f && + d6==3.5 && + f7==3.6f && + d8==3.7 && + f9==3.8f && + d10==3.9){ + return 4.0; + } + else { + return 0.0; + } + } + +- For a best result in the Java Round Robin test, disable all the C + native tasks except the MicroEJ task. + +- Link the BSP project with the MicroEJ Application (``microejapp.o``), + the MicroEJ Platform runtime (``microejruntime.a``) and the MicroEJ Platform header files (``*.h``). + +- Once all the tests have passed successfully, MicroEJ Core is validated. + +- See below for an output example of a successful validation. + +:: + + MicroEJ START + ***************************************************************************************************** + * MicroEJ Core Validation - 3.2.0 * + ***************************************************************************************************** + * Copyright 2013-2023 MicroEJ Corp. All rights reserved. * + * Use of this source code is governed by a BSD-style license that can be found with this software. * + ***************************************************************************************************** + + -> Check visible clock (LLMJVM_IMPL_getCurrentTime validation)... + Property 'com.microej.core.tests.max.allowed.clock.tick.duration.milliseconds' is not set (default to '20' millisecondss) + Property 'com.microej.core.tests.clock.seconds' is not set (default to '10' seconds) + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + OK: testVisibleClock + -> Check schedule request and wakeup (LLMJVM_IMPL_scheduleRequest and LLMJVM_IMPL_wakeupVM validation)... + Property 'com.microej.core.tests.max.allowed.clock.tick.duration.milliseconds' is not set (default to '20' millisecondss) + Waiting for 5s... + ...done + OK: testTime + -> Check monotonic time (LLMJVM_IMPL_getCurrentTime, LLMJVM_IMPL_setApplicationTime validation)... + Waiting for 5s... + ...done + OK: testMonotonicTime + -> Check Java round robin (LLMJVM_IMPL_scheduleRequest validation)... + For a best result, please disable all the C native tasks except the MicroEJ task. + Task 3 is waiting for start... + Task 2 is waiting for start... + Task 1 is waiting for start... + Task 0 is waiting for start... + Starting tasks and wait for 10 seconds... + Task 2 ends. + Task 3 ends. + Task 0 ends. + Task 1 ends. + ...done. + OK: testJavaRoundRobin + Main thread starts sleeping for 1s.. + WaitMaxTimeThread starts sleeping for `Long.MAX_VALUE` milliseconds + Main thread woke up! + OK: testScheduleMaxTime + Test synchronize on literal string + Test synchronize on class + Test multiple synchronize + OK: testIsInReadOnlyMemory + -> Check FPU (soft/hard FP option)... + OK: testFPU + -> Check floating-point arithmetic with NaN... + -> Check floating-point arithmetic with 0.0 and -0.0... + -> Check floating-point arithmetic with infinity... + -> Check floating-point arithmetic with min values... + -> Check floating-point division by 0.0... + -> Check floating-point Math functions... + -> Check integer arithmetic... + OK: testFloatingPointArithmetic + -> Check floating-point parser... + OK: testParseFloatingPoint + -> Check floating-point formatter... + OK: testFormatFloatingPoint + -> Check parsing a string as a double ; in some systems such operations may allocate memory in the C heap (strtod, strtof, malloc implementation)... + OK: testParseDoubleStringHeap + Property 'com.microej.core.tests.monotonic.time.check.seconds' is not set (default to '60' seconds) + -> Check monotonic time consistency for 60 seconds (LLMJVM_IMPL_getCurrentTime)... + ............................. + OK: testMonotonicTimeIncreases + -> Check current time clock tick duration (LLMJVM_IMPL_getCurrentTime, LLMJVM_IMPL_getTimeNanos)... + Property 'com.microej.core.tests.max.allowed.clock.tick.duration.milliseconds' is not set (default to '20' millisecondss) + Estimated LLMJVM_IMPL_getCurrentTime clock tick is 1 ms. + Estimated LLMJVM_IMPL_getTimeNanos clock tick is lower than 4000 ns. + OK: testSystemCurrentTimeClockTick + -> Check schedule request clock tick duration (LLMJVM_IMPL_scheduleRequest)... + Property 'com.microej.core.tests.max.allowed.clock.tick.duration.milliseconds' is not set (default to '20' millisecondss) + Estimated LLMJVM_IMPL_scheduleRequest clock tick is 1 ms. + OK: testScheduleRequestClockTick + -> Check SNI native calling convention (ABI)... + OK: testSniAbi + PASSED: 15 + MicroEJ END (exit code = 0) + + +Platform Test Suite Mode +~~~~~~~~~~~~~~~~~~~~~~~~ + +- In MicroEJ SDK, import the ``java-testsuite-runner-core`` project in your workspace. + +- Follow the configuration and execution steps described in Platform Test Suites `documentation <../../README.rst>`_. + +Dependencies +------------ + +*All dependencies are retrieved transitively by MicroEJ Module Manager*. + +Troubleshooting +--------------- + +The test blocks during the Java round robin test under FreeRTOS +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Issue: + +- The test of ``LLMJVM_IMPL_scheduleRequest`` blocks at the following + step: ``Starting tasks and wait for 10 seconds...``. + +Solution: + +- Ensure the JVM native C task has a priority lower than the FreeRTOS + timer task defined in ``FreeRTOSConfig.h`` (``configTIMER_TASK_PRIORITY``). + +Platform Test Suite issues +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +See Platform Test Suites `documentation <../../README.rst>`_. + +Source +------ + +N/A + +Restrictions +------------ + +None. + +.. + Copyright 2020-2023 MicroEJ Corp. All rights reserved. + Use of this source code is governed by a BSD-style license that can be found with this software. diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/build/common.properties b/microej/validation/core/java-testsuite-runner-core/build/common.properties similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/build/common.properties rename to microej/validation/core/java-testsuite-runner-core/build/common.properties diff --git a/microej/validation/core/java-testsuite-runner-core/config.properties b/microej/validation/core/java-testsuite-runner-core/config.properties new file mode 100644 index 0000000..b630bc2 --- /dev/null +++ b/microej/validation/core/java-testsuite-runner-core/config.properties @@ -0,0 +1,100 @@ +# Properties +# +# Copyright 2021-2023 MicroEJ Corp. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be found with this software. + +############################################################################### +# Testsuite Configuration Options +# +# Usage: +# Uncomment and set options marked '[required]'. +# Other options are set with a value that shall not be changed by default. +# +# Each option can be declared outside this file as a system property: +# In MicroEJ SDK, select 'Window' > 'Preferences' > 'Ant' > 'Runtime' > 'Properties' +# This can be useful to avoid to share absolute file-system locations in this file. +# In this case, it overrides the option defined in this file if any. +# Moreover, options related to local setup (absolute file-system locations, trace ip & port) +# can be extracted to the file 'local.properties' which is ignored for source control. +# +# This file respects the Java properties file convention: the OS path +# must use the UNIX path convention (path separator is '/'). The WINDOWS +# paths must have been converted manually replacing '\' by '/' or by '\\'. +############################################################################### + +############################################################################### +# Target Platform +############################################################################### + +# defined in module.ant +#target.platform.dir= + +############################################################################### +# BSP Connection [required] +# Uncomment one and only one option block depending on how the target Platform is connected to BSP. +# See https://docs.microej.com/en/latest/PlatformDeveloperGuide/platformCreation.html +############################################################################### + +# No BSP Connection +#microej.testsuite.properties.deploy.dir.microejapp=[absolute_path] +#microej.testsuite.properties.deploy.dir.microejlib=[absolute_path] +#microej.testsuite.properties.deploy.dir.microejinc=[absolute_path] +#microej.testsuite.properties.deploy.dir.microejscript=[absolute_path] + +# Partial BSP Connection +#microej.testsuite.properties.deploy.bsp.root.dir=[absolute_path] +#microej.testsuite.properties.deploy.bsp.microejscript=true + +# Full BSP Connection +microej.testsuite.properties.deploy.bsp.microejscript=true + +############################################################################### +# Trace Redirection (System.out) +# [required] when trace is redirected by 'Serial to Socket Transmitter' tool, +# otherwise the trace is assumed to be redirected by 'run.bat' or 'run.sh' script. +############################################################################### + +microej.testsuite.properties.testsuite.trace.ip=localhost +microej.testsuite.properties.testsuite.trace.port=5555 + +# Platform specific option to redirect trace on dedicated UART +#microej.testsuite.properties.debug.traces.uart=SET + +############################################################################### +# Tests to run +############################################################################### + +# Comma separated list of patterns of files that must be included +test.run.includes.pattern=**/_AllTests_*.class +# Comma separated list of patterns of files that must be excluded (defaults to inner classes) +test.run.excludes.pattern=**/*$*.class + +####################################################################### +# Advanced Options +# These options shall not be changed by default. +############################################################################### + +# The execution target (`MICROJVM` to execute on Device, `S3` to execute on Simulator) +target.vm.name=MICROJVM + +# The deploy tool to run after the build of the microejapp.o (defaults to 'Platform Configuration Additions') +microej.testsuite.properties.microejtool.deploy.name=deployToolBSPRun + +# Set the verbose or not. Possible values: `true` or `false` +# When this option is set to `true`, the harness will output the execution trace. +microej.testsuite.verbose=true + +# The testsuite timeout (in seconds) +microej.testsuite.timeout=600 + +# The number of times we'll retry a test if it fails +microej.testsuite.retry.count=1 + +# Retry a test unless this pattern is shown +microej.testsuite.retry.unless=VM START + +# A jvm args to pass to the testsuite harness +microej.testsuite.jvmArgs=-Xmx768m + +# A jvm args to pass to launch scripts forked vm +microej.testsuite.properties.launch.properties.jvm=-Xmx2048M diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/content/scripts/init-core-testsuite/core-testsuite-init.xml b/microej/validation/core/java-testsuite-runner-core/content/scripts/init-core-testsuite/core-testsuite-init.xml similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/content/scripts/init-core-testsuite/core-testsuite-init.xml rename to microej/validation/core/java-testsuite-runner-core/content/scripts/init-core-testsuite/core-testsuite-init.xml diff --git a/microej/validation/core/java-testsuite-runner-core/module.ant b/microej/validation/core/java-testsuite-runner-core/module.ant new file mode 100644 index 0000000..19156d3 --- /dev/null +++ b/microej/validation/core/java-testsuite-runner-core/module.ant @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/microej/validation/core/java-testsuite-runner-core/module.ivy b/microej/validation/core/java-testsuite-runner-core/module.ivy new file mode 100644 index 0000000..d7c066d --- /dev/null +++ b/microej/validation/core/java-testsuite-runner-core/module.ivy @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/override.module.ant b/microej/validation/core/java-testsuite-runner-core/override.module.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/override.module.ant rename to microej/validation/core/java-testsuite-runner-core/override.module.ant diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/src/main/resources/.gitkeep b/microej/validation/core/java-testsuite-runner-core/src/main/java/.gitkeep similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/src/main/resources/.gitkeep rename to microej/validation/core/java-testsuite-runner-core/src/main/java/.gitkeep diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/src/main/java/.gitkeep b/microej/validation/core/java-testsuite-runner-core/src/main/resources/.gitkeep similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/src/main/java/.gitkeep rename to microej/validation/core/java-testsuite-runner-core/src/main/resources/.gitkeep diff --git a/microej/validation/core/java-testsuite-runner-core/src/test/java/com/microej/core/tests/MicroejCoreValidation.java b/microej/validation/core/java-testsuite-runner-core/src/test/java/com/microej/core/tests/MicroejCoreValidation.java new file mode 100644 index 0000000..36f0878 --- /dev/null +++ b/microej/validation/core/java-testsuite-runner-core/src/test/java/com/microej/core/tests/MicroejCoreValidation.java @@ -0,0 +1,1048 @@ +/* + * Java + * + * Copyright 2013-2023 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ +package com.microej.core.tests; + +import static org.junit.Assert.assertEquals; +import static org.junit.Assert.assertTrue; +import static org.junit.Assert.fail; + +import java.io.InputStream; +import java.io.OutputStream; +import java.io.Reader; +import java.io.Writer; +import java.util.ArrayList; +import java.util.Calendar; +import java.util.HashMap; +import java.util.Hashtable; +import java.util.Iterator; +import java.util.List; +import java.util.Map; +import java.util.NoSuchElementException; + +import org.junit.BeforeClass; +import org.junit.Test; + +import ej.bon.Immortals; +import ej.bon.Immutables; +import ej.bon.Util; + +/** + * MicroEJ Core Validation tests. + */ +public class MicroejCoreValidation { + + private static final String VERSION = "3.2.0"; + + private static final String PROPERTY_SUFFIX = "com.microej.core.tests."; + private static final String OPTION_CLOCK_NB_SECONDS = "clock.seconds"; + private static final String OPTION_MONOTONIC_CHECK_NB_SECONDS = "monotonic.time.check.seconds"; + /** + * Option that specifies the maximum allowed value for the duration of a clock tick. The higher this value is the + * lower the allowed clock resolution will be. + */ + private static final String OPTION_MAX_ALLOWED_CLOCK_TICK_DURATION_MS = "max.allowed.clock.tick.duration.milliseconds"; + private static final int DEFAULT_MAX_ALLOWED_CLOCK_TICK_DURATION_MS = 20; + + private static final String INVALID_C_FUNCTION_MESSAGE = "C function not correctly implemented (check your libc configuration)"; + private static final String INCOHERENT_FPU_MESSAGE = "FPU option is not coherent between MicroEJ Core and BSP"; + + private static Class THIS_CLASS = MicroejCoreValidation.class; + + // Round Robin constants + private static final int NB_THREADS = 4; + private static final int ROUND_ROBIN_TEST_DURATION = 10000; + private static final int ROUND_ROBIN_MIN_COUNTER_REQUIRED = 500; + private static final int ROUND_ROBIN_MAX_DELTA_PERCENTAGE_ALLOWED = 5; + + private static volatile boolean ROUND_ROBIN_IS_RUNNING; + private static Object ROUND_ROBIN_LOCK = new Object(); + private static long[] ROUND_ROBIN_TASK_COUNTERS; + + // Set this fields volatile so we are sure accesses are not optimized + volatile private static double double3 = 3d; + volatile private static double double4 = 4d; + volatile private static double doubleNaN = Double.NaN; + volatile private static double doubleZero = 0.0; + volatile private static double doubleNegativeZero = -0.0; + volatile private static double doublePositiveInfinity = Double.POSITIVE_INFINITY; + volatile private static double doubleNegativeInfinity = Double.NEGATIVE_INFINITY; + volatile private static float float3 = 3f; + volatile private static float float4 = 4f; + volatile private static float floatNaN = Float.NaN; + volatile private static float floatZero = 0.0f; + volatile private static float floatNegativeZero = -0.0f; + volatile private static float floatPositiveInfinity = Float.POSITIVE_INFINITY; + volatile private static float floatNegativeInfinity = Float.NEGATIVE_INFINITY; + volatile private static int intMin = Integer.MIN_VALUE; + volatile private static int intNegativeOne = -1; + volatile private static long longMin = Long.MIN_VALUE; + volatile private static long longNegativeOne = -1l; + + // testParseDoubleStringHeap: tolerance value for float comparison + private static final float FLOAT_COMPARISON_TOLERANCE_PERCENT = 0.01f; + + private static void printProduct() { + final String sep = "*****************************************************************************************************"; + System.out.println(sep); + System.out.println("* MicroEJ Core Validation - " + VERSION + + " *"); + System.out.println(sep); + System.out.println( + "* Copyright 2013-2023 MicroEJ Corp. All rights reserved. *"); + System.out.println( + "* Use of this source code is governed by a BSD-style license that can be found with this software. *"); + System.out.println(sep); + System.out.println(); + } + + private static int getOptionAsInt(String optionName, int defaultValue, String unit) { + String propertyName = PROPERTY_SUFFIX + optionName; + String valueStr = System.getProperty(propertyName); + int value; + if (valueStr == null) { + value = defaultValue; + System.out.println("Property '" + propertyName + "' is not set (default to '" + value + "' " + unit + + (value > 1 ? "s" : "") + ")"); + } else { + try { + value = Integer.parseInt(valueStr); + System.out.println( + "Property '" + propertyName + "' is set to '" + value + "' " + unit + (value > 1 ? "s" : "")); + } catch (NumberFormatException e) { + value = defaultValue; + System.out.println("Property '" + propertyName + "' is invalid (set to '" + valueStr + "', default to '" + + value + "' " + unit + (value > 1 ? "s" : "") + ")"); + } + } + return value; + } + + private static void tryToSynchronizeOn(List objects, boolean mustFail) { + MonitorKeeper.errorCount = 0; + Thread[] threads = new Thread[MonitorKeeper.THREAD_COUNT]; + + try { + for (int i = 0; i < threads.length; i++) { + threads[i] = new Thread(new MonitorKeeper(objects.get(i))); + } + + for (Thread thread : threads) { + thread.start(); + } + + for (Thread thread : threads) { + try { + thread.join(); + } catch (InterruptedException e) { + // Nothing to do here. + } + } + + boolean success; + if (mustFail) { + success = MonitorKeeper.errorCount > 0; + } else { + success = MonitorKeeper.errorCount == 0; + } + assertTrue("Too many synchronized monitors.", success); + } catch (IndexOutOfBoundsException ioobe) { + fail("No objects to synchronize on, aborting."); + } + } + + private static List objectsFromRam() { + List objects = new ArrayList<>(); + + for (int i = 0; i < MonitorKeeper.THREAD_COUNT; i++) { + Object[] objects2 = new Object[MonitorKeeper.MONITOR_PER_THREAD_COUNT]; + for (int j = 0; j < objects2.length; j++) { + objects2[j] = new Object(); + } + objects.add(objects2); + } + + return objects; + } + + private static List objectsFromImmortals() { + List objects = new ArrayList<>(); + + for (int i = 0; i < MonitorKeeper.THREAD_COUNT; i++) { + Object[] objects2 = new Object[MonitorKeeper.MONITOR_PER_THREAD_COUNT]; + for (int j = 0; j < objects2.length; j++) { + Object object = new Object(); + Immortals.setImmortal(object); + objects2[j] = object; + } + objects.add(objects2); + } + + return objects; + } + + private static List objectsFromImmutables() { + List objects = new ArrayList<>(); + int objectID = 0; + + try { + for (int i = 0; i < MonitorKeeper.THREAD_COUNT; i++) { + Object[] objects2 = new Object[MonitorKeeper.MONITOR_PER_THREAD_COUNT]; + for (int j = 0; j < objects2.length; j++) { + Object object = Immutables.get("array" + objectID++); + objects2[j] = object; + } + objects.add(objects2); + } + } catch (NoSuchElementException nsee) { + System.out.println("Can't find the requested object in the immutables, check your launch configuration."); + } + + return objects; + } + + private static List stringsFromImmutables() { + List objects = new ArrayList<>(); + + objects.add(new String[] { "0", "1", "2", "3", "4", "5", "6" }); + objects.add(new String[] { "7", "8", "9", "10", "11", "12", "13" }); + objects.add(new String[] { "14", "15", "16", "17", "18", "19", "20" }); + objects.add(new String[] { "21", "22", "23", "24", "25", "26", "27" }); + objects.add(new String[] { "28", "29", "30", "31", "32", "33", "34" }); + + return objects; + } + + private static List classes() { + List objects = new ArrayList<>(); + + objects.add(new Class[] { Integer.class, Boolean.class, Long.class, Float.class, Double.class, Thread.class, + Object.class }); + objects.add(new Class[] { Byte.class, Character.class, Calendar.class, ArrayList.class, List.class, Class.class, + Exception.class }); + objects.add(new Class[] { InputStream.class, OutputStream.class, Map.class, HashMap.class, Hashtable.class, + Reader.class, Writer.class }); + objects.add(new Class[] { Number.class, Throwable.class, String.class, Short.class, Enum.class, Runtime.class, + Package.class }); + objects.add(new Class[] { System.class, Math.class, StringBuilder.class, StringBuffer.class, Runnable.class, + Iterable.class, Iterator.class }); + + return objects; + } + + private static float testFPUJava(float a, float b) { + return a * b; + } + + private static double testFPUJava(double a, double b) { + return a * b; + } + + /** + * @throws java.lang.Exception + * If an error occurred. + */ + @BeforeClass + public static void setUpBeforeClass() throws Exception { + printProduct(); + } + + /** + * Tests the LLMJVM_IMPL_getCurrentTime implementation. + */ + @Test + public void testVisibleClock() { + System.out.println("-> Check visible clock (LLMJVM_IMPL_getCurrentTime validation)..."); + final long precisionLimit = getOptionAsInt(OPTION_MAX_ALLOWED_CLOCK_TICK_DURATION_MS, + DEFAULT_MAX_ALLOWED_CLOCK_TICK_DURATION_MS, "milliseconds"); + int defaultNbSeconds = 10; + int nbSeconds = getOptionAsInt(OPTION_CLOCK_NB_SECONDS, defaultNbSeconds, "second"); + + // Check if a message is printed every seconds in terminal: + long timeStart = System.currentTimeMillis(); + int seconds = 0; + long nbMilliSeconds = nbSeconds * 1000; + while (true) { + long time = System.currentTimeMillis(); + long delta = time - timeStart; + int newSecond = (int) (delta / 1000); + if (newSecond > seconds) { + System.out.println(newSecond); + seconds = newSecond; + } + + if (delta > nbMilliSeconds) { + break; // end of test + } + } + + // ensure both API returns same value + long timeEnd1 = System.currentTimeMillis(); + long timeEnd2 = Util.platformTimeMillis(); + long delta = timeEnd2 - timeEnd1; + assertTrue("Util.platformTimeMillis() != System.currentTimeMillis()", delta <= precisionLimit); + + // ensure nano time is valid + delta = (Util.platformTimeNanos() / 1000000) - Util.platformTimeMillis(); + assertTrue("Util.platformTimeNanos()/1000000 != Util.platformTimeMillis()", delta <= precisionLimit); + } + + /** + * Tests LLMJVM_IMPL_scheduleRequest and LLMJVM_IMPL_wakeupVM implementations. + */ + @Test + public void testTime() { + System.out.println( + "-> Check schedule request and wakeup (LLMJVM_IMPL_scheduleRequest and LLMJVM_IMPL_wakeupVM validation)..."); + final long precisionLimit = getOptionAsInt(OPTION_MAX_ALLOWED_CLOCK_TICK_DURATION_MS, + DEFAULT_MAX_ALLOWED_CLOCK_TICK_DURATION_MS, "milliseconds"); + long delay = 5 * 1000; + System.out.println("Waiting for " + delay / 1000 + "s..."); + long timeBefore = System.currentTimeMillis(); + try { + Thread.sleep(delay); + } catch (InterruptedException e) { + throw new Error(); + } + long timeAfter = System.currentTimeMillis(); + System.out.println("...done"); + long realDelay = timeAfter - timeBefore; + assertTrue("realDelay>=delay", realDelay >= delay); + long delta = realDelay - delay; + assertTrue("delta(=" + delta + ")<=" + precisionLimit, delta <= precisionLimit); + } + + /** + * Tests the LLMJVM_IMPL_setApplicationTime implementation. + */ + @Test + public void testMonotonicTime() { + System.out.println( + "-> Check monotonic time (LLMJVM_IMPL_getCurrentTime, LLMJVM_IMPL_setApplicationTime validation)..."); + long delay = 5 * 1000; + long elapsedTime = 100; + long timeOffset = 50_000; + System.out.println("Waiting for " + delay / 1000 + "s..."); + long monotonicTimeBefore = Util.platformTimeMillis(); + long applicationTimeBefore = System.currentTimeMillis(); + + Util.setCurrentTimeMillis(applicationTimeBefore + timeOffset); + long applicationTimeAfter = System.currentTimeMillis(); + + try { + Thread.sleep(delay); + } catch (InterruptedException e) { + throw new Error(); + } + long montonicTimeAfter = Util.platformTimeMillis(); + System.out.println("...done"); + assertTrue("application time not set", applicationTimeAfter >= applicationTimeBefore + timeOffset + && applicationTimeAfter <= applicationTimeBefore + timeOffset + elapsedTime); + assertTrue("monotonic time not set", montonicTimeAfter >= monotonicTimeBefore + delay + && montonicTimeAfter <= monotonicTimeBefore + delay + elapsedTime); + } + + /** + * Tests the LLMJVM_IMPL_scheduleRequest implementation. + */ + @Test + public void testJavaRoundRobin() { + System.out.println("-> Check Java round robin (LLMJVM_IMPL_scheduleRequest validation)..."); + System.out.println("For a best result, please disable all the C native tasks except the MicroEJ task."); + int nbThreads = NB_THREADS; + assertTrue("nbThreads >= 2", nbThreads >= 2); + + ROUND_ROBIN_TASK_COUNTERS = new long[nbThreads]; + int priority = Thread.currentThread().getPriority() - 1; + Thread[] threads = new Thread[nbThreads]; + for (int i = threads.length; --i >= 0;) { + Thread t = new Thread(new RoundRobinTestTask(i)); + threads[i] = t; + t.setPriority(priority); + t.start(); + } + + // Poll until all threads are waiting on the monitor + while (RoundRobinTestTask.COUNTER < NB_THREADS) { + try { + Thread.sleep(500); + } catch (InterruptedException e) { + e.printStackTrace(); + } + } + + System.out.println("Starting tasks and wait for " + (ROUND_ROBIN_TEST_DURATION / 1000) + " seconds..."); + synchronized (ROUND_ROBIN_LOCK) { + ROUND_ROBIN_IS_RUNNING = true; + ROUND_ROBIN_LOCK.notifyAll(); // start ! + } + + try { + Thread.sleep(ROUND_ROBIN_TEST_DURATION); + } catch (InterruptedException e1) { + assertTrue("Unexpected InterruptedException", false); + } + + // stop threads + ROUND_ROBIN_IS_RUNNING = false; + for (int i = threads.length; --i >= 0;) { + try { + threads[i].join(); + } catch (InterruptedException e) { + throw new Error(); + } + } + System.out.println("...done."); + + long totalCounter = 0; + long minCounter = Long.MAX_VALUE; + long maxCounter = 0; + for (int i = threads.length; --i >= 0;) { + long counter = ROUND_ROBIN_TASK_COUNTERS[i]; + totalCounter += counter; + maxCounter = Math.max(maxCounter, counter); + minCounter = Math.min(minCounter, counter); + } + + long deltaCounter = maxCounter - minCounter; + long averageCounter = totalCounter / threads.length; + long deltaPercentage; + if (minCounter > 0) { + deltaPercentage = (deltaCounter * 100) / minCounter; + } else { + deltaPercentage = 100; + } + + if (deltaPercentage > ROUND_ROBIN_MAX_DELTA_PERCENTAGE_ALLOWED) { + // Print some information when the test fails + System.out.println("Min counter = " + minCounter); + System.out.println("Max counter = " + maxCounter); + System.out.println("Average = " + averageCounter); + System.out.println("Delta = " + deltaCounter); + System.out.println("Delta Percentage = " + deltaPercentage); + } + + assertTrue("counter increments < " + ROUND_ROBIN_MIN_COUNTER_REQUIRED + " (actually " + minCounter + ")", + minCounter >= ROUND_ROBIN_MIN_COUNTER_REQUIRED); + + assertTrue("delta percentage > " + ROUND_ROBIN_MAX_DELTA_PERCENTAGE_ALLOWED + " (actually " + deltaPercentage + + ")", deltaPercentage <= ROUND_ROBIN_MAX_DELTA_PERCENTAGE_ALLOWED); + } + + /** + * Tests the LLMJVM_IMPL_scheduleRequest implementation with a max schedule request time + * (Long.MAX_VALUE milliseconds). + * + * Tests Thread.sleep() with max number of milliseconds (Long.MAX_VALUE) does not cause an infinite loop in the + * MicroEJ Core. + * + * This test will check if the time conversion overflow is correctly handled in the LLMJVM_scheduleRequest() + * implementation. A correct implementation should saturate the time to the max value of microseconds or ticks in + * case of overflow. + */ + @Test + public void testScheduleMaxTime() { + Thread waitMaxTimeThread = new Thread(new Runnable() { + @Override + public void run() { + try { + System.out.println("WaitMaxTimeThread starts sleeping for `Long.MAX_VALUE` milliseconds"); + Thread.sleep(Long.MAX_VALUE); + assertTrue("Max sleep time reached!", false); + } catch (InterruptedException e) { + // interrupted + } + } + }); + + waitMaxTimeThread.start(); + + System.out.println("Main thread starts sleeping for 1s.."); + try { + Thread.sleep(1000); + System.out.println("Main thread woke up!"); + waitMaxTimeThread.interrupt(); + waitMaxTimeThread.join(); + assertTrue("Main thread woke up and continued its execution: MicroEJ Core does not loop indefinitely", + true); + } catch (InterruptedException e) { + throw new Error(); + } + + } + + /** + * Tests the LLBSP_IMPL_isInReadOnlyMemory implementation. + */ + @Test + public void testIsInReadOnlyMemory() { + System.out.println("-> Check isInReadOnlyMemory (LLBSP_IMPL_isInReadOnlyMemory validation)..."); + + try { + String s = "literal string"; + synchronized (s) { + System.out.println("Test synchronize on literal string"); + } + } catch (IllegalMonitorStateException e) { + fail("IllegalMonitorStateException during synchronization on immutable object (literal string)"); + } + + try { + synchronized (MicroejCoreValidation.class) { + System.out.println("Test synchronize on class"); + } + } catch (IllegalMonitorStateException e) { + fail("IllegalMonitorStateException during synchronization on immutable object (class)"); + } + + /* + * There is a limit of the number of the synchronized monitors in flash but not in ram. We test this limit is + * reached for the objects in flash but not for the objects in ram. If the LLBSP_IMPL_isInReadOnlyMemory + * function is not correctly implemented this test can highlight it. + */ + System.out.println("Test multiple synchronize"); + tryToSynchronizeOn(objectsFromRam(), false); + tryToSynchronizeOn(stringsFromImmutables(), true); + tryToSynchronizeOn(classes(), true); + tryToSynchronizeOn(objectsFromImmortals(), false); + tryToSynchronizeOn(objectsFromImmutables(), true); + } + + /** + * Tests the VEE Port FPU configuration. + */ + @Test + public void testFPU() { + System.out.println("-> Check FPU (soft/hard FP option)..."); + + assertEquals("test 'float * float' in Java: " + INCOHERENT_FPU_MESSAGE, new Float(12f), + new Float(testFPUJava(float3, float4))); + assertEquals("test 'double * double' in Java: " + INCOHERENT_FPU_MESSAGE, new Double(12), + new Double(testFPUJava(double3, double4))); + assertEquals("test 'float * float' in C: " + INCOHERENT_FPU_MESSAGE, new Float(12f), + new Float(testFloat(float3, float4))); + assertEquals("test 'double * double' in C: " + INCOHERENT_FPU_MESSAGE, new Double(12), + new Double(testDouble(double3, double4))); + } + + /** + * Tests the VEE Port floating-point arithmetic. + */ + @Test + public void testFloatingPointArithmetic() { + System.out.println("-> Check floating-point arithmetic with NaN..."); + + boolean allOk = true; + + allOk &= checkTrue("test 'NaN + float' returns NaN", Float.isNaN(floatNaN + float3)); + allOk &= checkTrue("test 'NaN - float' returns NaN", Float.isNaN(floatNaN - float3)); + allOk &= checkTrue("test 'NaN / float' returns NaN", Float.isNaN(floatNaN / float3)); + allOk &= checkTrue("test 'NaN * float' returns NaN", Float.isNaN(floatNaN * float3)); + allOk &= checkTrue("test 'NaN % float' returns NaN", Float.isNaN(floatNaN % float3)); + allOk &= checkTrue("test '(double)Float.NaN' returns NaN", Double.isNaN(floatNaN)); + allOk &= checkEquals("test '(int)Float.NaN' returns 0", 0, (int) floatNaN); + allOk &= checkEquals("test '(long)Float.NaN' returns 0", 0, (long) floatNaN); + + allOk &= checkTrue("test 'NaN + double' returns NaN", Double.isNaN(doubleNaN + double3)); + allOk &= checkTrue("test 'NaN - double' returns NaN", Double.isNaN(doubleNaN - double3)); + allOk &= checkTrue("test 'NaN / double' returns NaN", Double.isNaN(doubleNaN / double3)); + allOk &= checkTrue("test 'NaN * double' returns NaN", Double.isNaN(doubleNaN * double3)); + allOk &= checkTrue("test 'NaN % double' returns NaN", Double.isNaN(doubleNaN % double3)); + allOk &= checkTrue("test '(float)Double.NaN' returns NaN", Float.isNaN((float) doubleNaN)); + allOk &= checkEquals("test '(int)Double.NaN' returns 0", 0, (int) doubleNaN); + allOk &= checkEquals("test '(long)Double.NaN' returns 0", 0, (long) doubleNaN); + + System.out.println("-> Check floating-point arithmetic with 0.0 and -0.0..."); + allOk &= checkTrue("test 'float % 0.0' returns NaN", Float.isNaN(float3 % floatZero)); + allOk &= checkTrue("test 'float % -0.0' returns NaN", Float.isNaN(float3 % floatNegativeZero)); + allOk &= checkTrue("test 'double % 0.0' returns NaN", Double.isNaN(double3 % doubleZero)); + allOk &= checkTrue("test 'double % -0.0' returns NaN", Double.isNaN(double3 % doubleNegativeZero)); + + allOk &= checkTrue("test 'inf * 0.0f' returns NaN", Float.isNaN(floatPositiveInfinity * floatZero)); + allOk &= checkEquals("test 'float * -0.0' returns -0.0", 0, Float.compare(-0.0f, (float3 * floatNegativeZero))); + allOk &= checkEquals("test 'float * 0.0' returns 0.0", 0, Float.compare(0.0f, (float3 * floatZero))); + allOk &= checkEquals("test '-float * -0.0' returns 0.0", 0, Float.compare(0.0f, (-float3 * floatNegativeZero))); + allOk &= checkEquals("test '-float * 0.0' returns -0.0", 0, Float.compare(-0.0f, (-float3 * floatZero))); + allOk &= checkTrue("test 'inf * 0.0d' returns NaN", Double.isNaN(doublePositiveInfinity * doubleZero)); + allOk &= checkEquals("test 'double * -0.0' returns -0.0", 0, + Double.compare(-0.0, (double3 * doubleNegativeZero))); + allOk &= checkEquals("test 'double * 0.0' returns 0.0", 0, Double.compare(0.0, (double3 * doubleZero))); + allOk &= checkEquals("test '-double * -0.0' returns 0.0", 0, + Double.compare(0.0, (-double3 * doubleNegativeZero))); + allOk &= checkEquals("test '-double * 0.0' returns -0.0", 0, Double.compare(-0.0, (-double3 * doubleZero))); + + allOk &= checkEquals("test '-0.0f + 0.0f' returns 0.0f", 0, Float.compare(0.0f, floatNegativeZero + floatZero)); + allOk &= checkEquals("test '-0.0f - -0.0f' returns 0.0f", 0, + Float.compare(0.0f, floatNegativeZero - floatNegativeZero)); + allOk &= checkEquals("test '-0.0d + 0.0d' returns 0.0d", 0, + Double.compare(0.0d, doubleNegativeZero + doubleZero)); + allOk &= checkEquals("test '-0.0d - -0.0d' returns 0.0d", 0, + Double.compare(0.0d, doubleNegativeZero - doubleNegativeZero)); + + allOk &= checkEquals("test '(float)-0.0d' returns -0.0f", 0, Float.compare(-0.0f, (float) doubleNegativeZero)); + allOk &= checkEquals("test '(double)-0.0f' returns -0.0d", 0, Double.compare(-0.0, floatNegativeZero)); + + System.out.println("-> Check floating-point arithmetic with infinity..."); + allOk &= checkTrue("test '+inf % float' returns NaN", Float.isNaN(floatPositiveInfinity % float3)); + allOk &= checkTrue("test '-inf % float' returns NaN", Float.isNaN(floatNegativeInfinity % float3)); + allOk &= checkTrue("test '-inf + float' returns -inf", + (floatNegativeInfinity + float3) == Float.NEGATIVE_INFINITY); + allOk &= checkTrue("test '+inf + -float' returns +inf", + (floatPositiveInfinity + -float3) == Float.POSITIVE_INFINITY); + allOk &= checkTrue("test '(double)+inf' returns +inf", floatPositiveInfinity == Double.POSITIVE_INFINITY); + allOk &= checkTrue("test '(double)-inf' returns -inf", floatNegativeInfinity == Double.NEGATIVE_INFINITY); + + allOk &= checkTrue("test '+inf % double' returns NaN", Double.isNaN(doublePositiveInfinity % double3)); + allOk &= checkTrue("test '-inf % double' returns NaN", Double.isNaN(doubleNegativeInfinity % double3)); + allOk &= checkTrue("test '-inf + double' returns -inf", + (doubleNegativeInfinity + double3) == Double.NEGATIVE_INFINITY); + allOk &= checkTrue("test '+inf + -double' returns +inf", + (doublePositiveInfinity + -double3) == Double.POSITIVE_INFINITY); + allOk &= checkTrue("test '(float)+inf' returns +inf", + (float) doublePositiveInfinity == Float.POSITIVE_INFINITY); + allOk &= checkTrue("test '(float)-inf' returns -inf", + (float) doubleNegativeInfinity == Float.NEGATIVE_INFINITY); + + System.out.println("-> Check floating-point arithmetic with min values..."); + allOk &= checkTrue("test 'min % float' returns min", (Float.MIN_VALUE % float3) == Float.MIN_VALUE); + allOk &= checkTrue("test 'min % double' returns min", (Double.MIN_VALUE % float3) == Double.MIN_VALUE); + + System.out.println("-> Check floating-point division by 0.0..."); + allOk &= checkTrue("test '0.0f / 0.0f' returns NaN", Float.isNaN(floatZero / floatZero)); + allOk &= checkTrue("test 'float / 0.0' returns +inf", (float3 / floatZero) == Float.POSITIVE_INFINITY); + allOk &= checkTrue("test 'float / -0.0' returns -inf", (float3 / floatNegativeZero) == Float.NEGATIVE_INFINITY); + allOk &= checkTrue("test '-float / 0.0' returns -inf", (-float3 / floatZero) == Float.NEGATIVE_INFINITY); + allOk &= checkTrue("test '-float / -0.0' returns +inf", + (-float3 / floatNegativeZero) == Float.POSITIVE_INFINITY); + + allOk &= checkTrue("test '0.0d / 0.0d' returns NaN", Double.isNaN(doubleZero / doubleZero)); + allOk &= checkTrue("test 'double / 0.0' returns +inf", (double3 / doubleZero) == Double.POSITIVE_INFINITY); + allOk &= checkTrue("test 'double / -0.0' returns -inf", + (double3 / doubleNegativeZero) == Double.NEGATIVE_INFINITY); + allOk &= checkTrue("test '-double / 0.0' returns -inf", (-double3 / doubleZero) == Double.NEGATIVE_INFINITY); + allOk &= checkTrue("test '-double / -0.0' returns +inf", + (-double3 / doubleNegativeZero) == Double.POSITIVE_INFINITY); + + System.out.println("-> Check floating-point Math functions..."); + allOk &= checkTrue("test 'log1p(-3)' returns NaN", Double.isNaN(Math.log1p(-double3))); + allOk &= checkTrue("test 'sqrt(neg)' returns NaN", Double.isNaN(Math.sqrt(-double3))); + allOk &= checkTrue("test 'IEEEremainder(double, 0.0)' returns NaN", + Double.isNaN(Math.IEEEremainder(double3, doubleZero))); + allOk &= checkTrue("test 'IEEEremainder(double, -0.0)' returns NaN", + Double.isNaN(Math.IEEEremainder(double3, doubleNegativeZero))); + allOk &= checkTrue("test 'cos(NaN)' returns NaN", Double.isNaN(Math.cos(doubleNaN))); + allOk &= checkTrue("test 'cos(+inf)' returns NaN", Double.isNaN(Math.cos(doublePositiveInfinity))); + allOk &= checkTrue("test 'cos(-inf)' returns NaN", Double.isNaN(Math.cos(doubleNegativeInfinity))); + allOk &= checkTrue("test 'sin(NaN)' returns NaN", Double.isNaN(Math.sin(doubleNaN))); + allOk &= checkTrue("test 'sin(+inf)' returns NaN", Double.isNaN(Math.sin(doublePositiveInfinity))); + allOk &= checkTrue("test 'sin(-inf)' returns NaN", Double.isNaN(Math.sin(doubleNegativeInfinity))); + allOk &= checkTrue("test 'tan(NaN)' returns NaN", Double.isNaN(Math.tan(doubleNaN))); + allOk &= checkTrue("test 'tan(+inf)' returns NaN", Double.isNaN(Math.tan(doublePositiveInfinity))); + allOk &= checkTrue("test 'tan(-inf)' returns NaN", Double.isNaN(Math.tan(doubleNegativeInfinity))); + allOk &= checkTrue("test 'acos(NaN)' returns NaN", Double.isNaN(Math.acos(doubleNaN))); + allOk &= checkTrue("test 'asin(NaN)' returns NaN", Double.isNaN(Math.asin(doubleNaN))); + allOk &= checkTrue("test 'atan(NaN)' returns NaN", Double.isNaN(Math.atan(doubleNaN))); + + System.out.println("-> Check integer arithmetic..."); + allOk &= checkEquals("test 'INT_MIN / -1' returns INT_MIN", Integer.MIN_VALUE, intMin / intNegativeOne); + allOk &= checkEquals("test 'INT_MIN % -1' returns INT_MIN", 0, intMin % intNegativeOne); + allOk &= checkEquals("test 'LONG_MIN / -1' returns LONG_MIN", Long.MIN_VALUE, longMin / longNegativeOne); + allOk &= checkEquals("test 'LONG_MIN % -1' returns LONG_MIN", 0, longMin % longNegativeOne); + + assertTrue(allOk); + } + + private static boolean checkTrue(String message, boolean condition) { + try { + assertTrue(message, condition); + return true; + } catch (AssertionError error) { + System.out.println("Assertion failed: " + error.getMessage()); + return false; + } + } + + private static boolean checkEquals(String message, long expected, long actual) { + try { + assertEquals(message, expected, actual); + return true; + } catch (AssertionError error) { + System.out.println("Assertion failed: " + error.getMessage()); + return false; + } + } + + /** + * Tests the VEE Port floating-point parser. + */ + @Test + public void testParseFloatingPoint() { + System.out.println("-> Check floating-point parser..."); + + float parsedFloat = Float.parseFloat("1234.5"); + float expectedFloat = 1234.5f; + assertEquals("test 'parse float string': strtof " + INVALID_C_FUNCTION_MESSAGE, expectedFloat, parsedFloat, + getAssertFloatDelta(expectedFloat)); + + double parsedDouble = Double.parseDouble("1234.5"); + double expectedDouble = 1234.5; + assertEquals("test 'parse double string': strtod " + INVALID_C_FUNCTION_MESSAGE, expectedDouble, parsedDouble, + getAssertDoubleDelta(expectedDouble)); + + float parsedFloatScientific = Float.parseFloat("9.82E-22"); + float expectedFloatScientific = 9.82E-22f; + assertEquals("test 'parse float string scientific notation': strtof " + INVALID_C_FUNCTION_MESSAGE, + expectedFloatScientific, parsedFloatScientific, getAssertFloatDelta(expectedFloatScientific)); + + double parsedDoubleScientific = Double.parseDouble("1.25E128"); + double expectedDoubleScientific = 1.25E128; + assertEquals("test 'parse double string scientific notation': strtod " + INVALID_C_FUNCTION_MESSAGE, + expectedDoubleScientific, parsedDoubleScientific, getAssertDoubleDelta(expectedDoubleScientific)); + } + + /** + * Tests the VEE Port floating-point formatter. + */ + @Test + public void testFormatFloatingPoint() { + System.out.println("-> Check floating-point formatter..."); + + String floatToString = Float.toString(1234.5f); + assertEquals("test 'float to string': snprintf " + INVALID_C_FUNCTION_MESSAGE, "1234.5", floatToString); + + String doubleToString = Double.toString(1234.5d); + assertEquals("test 'double to string': snprintf " + INVALID_C_FUNCTION_MESSAGE, "1234.5", doubleToString); + + String floatScientificToString = Float.toString(1.11E-22f); + assertTrue( + "test 'float to string scientific notation (toString(1.11E-22f) is '" + floatScientificToString + + "')': snprintf " + INVALID_C_FUNCTION_MESSAGE, + floatScientificToString.startsWith("1.1") && floatScientificToString.endsWith("E-22")); + + String doubleScientificToString = Double.toString(1.11E128d); + assertTrue( + "test 'double to string scientific notation (toString(1.11E128d) is '" + doubleScientificToString + + "')': snprintf " + INVALID_C_FUNCTION_MESSAGE, + doubleScientificToString.startsWith("1.1") && doubleScientificToString.endsWith("E128")); + } + + /** + * Tests parse double/float with potential dynamic allocation. + */ + @Test + public void testParseDoubleStringHeap() { + System.out.println( + "-> Check parsing a string as a double ; in some systems such operations may allocate memory in the C heap (strtod, strtof, malloc implementation)..."); + + double parsedDouble; + double expectedDouble; + float parsedFloat; + float expectedFloat; + parsedDouble = Double.parseDouble("1.7976931348623157E308"); + expectedDouble = 1.7976931348623157E308; + assertEquals("test 'parse float/double string (1/10)': strtod " + INVALID_C_FUNCTION_MESSAGE, expectedDouble, + parsedDouble, getAssertDoubleDelta(expectedDouble)); + + parsedDouble = Double.parseDouble("4.9E-324"); + expectedDouble = 4.9E-324; + assertEquals("test 'parse float/double string (2/10)': strtod " + INVALID_C_FUNCTION_MESSAGE, expectedDouble, + parsedDouble, getAssertDoubleDelta(expectedDouble)); + + parsedDouble = Double.parseDouble( + "8456452315484210000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009999999999999999999999999999999999999999999999999999999999999999040.005460000000000E-512"); + expectedDouble = 8.4E-323d; + assertEquals("test 'parse float/double string (3/10)': strtod " + INVALID_C_FUNCTION_MESSAGE, expectedDouble, + parsedDouble, getAssertDoubleDelta(expectedDouble)); + + parsedFloat = Float.parseFloat("7.56042114E-33"); + expectedFloat = 7.56042114E-33f; + assertEquals("test 'parse float/double string (4/10)': strtof " + INVALID_C_FUNCTION_MESSAGE, expectedFloat, + parsedFloat, getAssertFloatDelta(expectedFloat)); + + parsedFloat = Float.parseFloat("3.71806751E-19"); + expectedFloat = 3.71806751E-19f; + assertEquals("test 'parse float/double string (5/10)': strtof " + INVALID_C_FUNCTION_MESSAGE, expectedFloat, + parsedFloat, getAssertFloatDelta(expectedFloat)); + + parsedFloat = Float.parseFloat("7.99279006E37"); + expectedFloat = 7.99279006E37f; + assertEquals("test 'parse float/double string (6/10)': strtof " + INVALID_C_FUNCTION_MESSAGE, expectedFloat, + parsedFloat, getAssertFloatDelta(expectedFloat)); + + parsedFloat = Float.parseFloat("2.27187279E-38"); + expectedFloat = 2.27187279E-38f; + assertEquals("test 'parse float/double string (7/10)': strtof " + INVALID_C_FUNCTION_MESSAGE, expectedFloat, + parsedFloat, getAssertFloatDelta(expectedFloat)); + + parsedDouble = Double.parseDouble("1.7976931348623157E308"); + expectedDouble = 1.7976931348623157E308; + assertEquals("test 'parse float/double string (8/10)': strtod " + INVALID_C_FUNCTION_MESSAGE, expectedDouble, + parsedDouble, getAssertDoubleDelta(expectedDouble)); + + String strDouble = Double.toString(2.4375d); + assertEquals("test 'double to string (9/10)': sprintf " + INVALID_C_FUNCTION_MESSAGE, "2.4375", strDouble); + + parsedDouble = Double.parseDouble("4.9E-324"); + expectedDouble = 4.9E-324; + assertEquals("test 'parse float/double string (10/10)': strtod " + INVALID_C_FUNCTION_MESSAGE, expectedDouble, + parsedDouble, getAssertDoubleDelta(expectedDouble)); + + } + + /** + * From expected double value, returns the delta value to use when comparing two doubles. + */ + private static double getAssertDoubleDelta(double expectedResult) { + return expectedResult * FLOAT_COMPARISON_TOLERANCE_PERCENT; + } + + /** + * From expected float value, returns the delta value to use when comparing two floats. + */ + private static float getAssertFloatDelta(float expectedResult) { + return expectedResult * FLOAT_COMPARISON_TOLERANCE_PERCENT; + } + + /** + * Tests that the LLMJVM_IMPL_getCurrentTime implementation always increases. + */ + @Test + public void testMonotonicTimeIncreases() { + final long testDurationS = getOptionAsInt(OPTION_MONOTONIC_CHECK_NB_SECONDS, 60, "second"); + System.out.println("-> Check monotonic time consistency for " + testDurationS + + " seconds (LLMJVM_IMPL_getCurrentTime)..."); + + final long printDotPeriodMs = 2000; + long startTime = Util.platformTimeMillis(); + long endTime = startTime + (testDurationS * 1000); + long printDotTime = startTime + printDotPeriodMs; + long previousTime = startTime; + long currentTime; + while (endTime > (currentTime = Util.platformTimeMillis())) { + if (printDotTime < currentTime) { + System.out.print('.'); + printDotTime = currentTime + printDotPeriodMs; + } + if (currentTime < previousTime) { + System.out.println(); + assertTrue("Monotonic time goes back in time (currentTime = " + currentTime + " previousTime=" + + previousTime + ").\nThis issue is usually caused by a non-atomic calculation of the time.", + false); + return; + } + previousTime = currentTime; + } + System.out.println(); + + } + + /** + * Checks {@code LLMJVM_IMPL_getCurrentTime()} and {@code LLMJVM_IMPL_getTimeNanos()} clock tick duration. + */ + @Test + public void testSystemCurrentTimeClockTick() { + System.out.println( + "-> Check current time clock tick duration (LLMJVM_IMPL_getCurrentTime, LLMJVM_IMPL_getTimeNanos)..."); + final long precisionLimitMs = getOptionAsInt(OPTION_MAX_ALLOWED_CLOCK_TICK_DURATION_MS, + DEFAULT_MAX_ALLOWED_CLOCK_TICK_DURATION_MS, "milliseconds"); + + long t0; + long t1; + long precision; + + // Check LLMJVM_IMPL_getCurrentTime + t0 = System.currentTimeMillis(); + while ((t1 = System.currentTimeMillis()) == t0) { + // Nothing to do + } + precision = t1 - t0; + System.out.println("Estimated LLMJVM_IMPL_getCurrentTime clock tick is " + precision + " ms."); + assertTrue("LLMJVM_IMPL_getCurrentTime timer precision (" + precision + + " ms) is lower than the expected limit (" + precisionLimitMs + " ms)", precision <= precisionLimitMs); + + // Check LLMJVM_IMPL_getTimeNanos + t0 = System.nanoTime(); + t1 = System.nanoTime(); + if (t0 != t1) { + // Time to call nanoTime is longer than the clock tick. + // Cannot compute exact precision, just print this result + System.out.println("Estimated LLMJVM_IMPL_getTimeNanos clock tick is lower than " + (t1 - t0) + " ns."); + } else { + t0 = System.nanoTime(); + while ((t1 = System.nanoTime()) == t0) { + // Nothing to do + } + precision = t1 - t0; + long precisionLimitNs = precisionLimitMs * 1000000l; + System.out.println("Estimated LLMJVM_IMPL_getTimeNanos clock tick is " + precision + " ns."); + assertTrue("LLMJVM_IMPL_getTimeNanos timer precision (" + precision + + " ns) is lower than the expected limit (" + precisionLimitMs + " ns)", + precision <= precisionLimitNs); + } + + } + + /** + * Checks {@code LLMJVM_IMPL_scheduleRequest()} clock tick duration. + */ + @Test + public void testScheduleRequestClockTick() { + System.out.println("-> Check schedule request clock tick duration (LLMJVM_IMPL_scheduleRequest)..."); + final long precisionLimit = getOptionAsInt(OPTION_MAX_ALLOWED_CLOCK_TICK_DURATION_MS, + DEFAULT_MAX_ALLOWED_CLOCK_TICK_DURATION_MS, "milliseconds"); + try { + // Execute a first sleep just to end the current clock cycle. + // Following operations will start at the beginning of the next clock cycle. + Thread.sleep(1); + long t0 = System.currentTimeMillis(); + Thread.sleep(1); + long t1 = System.currentTimeMillis(); + + long precision = t1 - t0; + System.out.println("Estimated LLMJVM_IMPL_scheduleRequest clock tick is " + precision + " ms."); + assertTrue( + "LLMJVM_IMPL_scheduleRequest timer precision (" + precision + + " ms) is lower than the expected limit (" + precisionLimit + " ms)", + precision <= precisionLimit); + + } catch (InterruptedException e) { + throw new Error(); + } + } + + /** + * Checks SNI calling convention ABI. + */ + @Test + public void testSniAbi() { + System.out.println("-> Check SNI native calling convention (ABI)..."); + + boolean allOk = true; + + int res01 = testNativeArguments01(0x01020304, 0x05060708, 0x090A0B0C, 0x0D0E0F10, 0x11121314, 0x15161718, + 0x191A1B1C, 0x1D1E1F20, 0x21222324, 0x25262728); + allOk &= checkTrue("test int32_t SNI arguments", res01 == 0x292A2B2C); + + long res02 = testNativeArguments02(0x2D2E2F3031323334l, 0x35363738393A3B3Cl, 0x3D3E3F4041424344l, + 0x45464748494A4B4Cl, 0x4D4E4F5051525354l, 0x55565758595A5B5Cl, 0x5D5E5F6061626364l, 0x65666768696A6B6Cl, + 0x6D6E6F7071727374l, 0x75767778797A7B7Cl); + allOk &= checkTrue("test int64_t SNI arguments", res02 == 0x7D7E7F8081828384l); + + long res03 = testNativeArguments03(0x85868788, 0x898A8B8C8D8E8F90l, 0x91929394, 0x95969798999A9B9Cl, 0x9D9E9FA0, + 0xA1A2A3A4A5A6A7A8l, 0xA9AAABAC, 0xADAEAFB0B1B2B3B4l, 0xB5B6B7B8, 0xB9BABBBCBDBEBFC0l); + allOk &= checkTrue("test int32_t/int64_t SNI arguments", res03 == 0xC1C2C3C4C5C6C7C8l); + + float res04 = testNativeArguments04(1.0f, 1.1f, 1.2f, 1.3f, 1.4f, 1.5f, 1.6f, 1.7f, 1.8f, 1.9f); + allOk &= checkTrue("test float SNI arguments", res04 == 2.0f); + + double res05 = testNativeArguments05(2.0d, 2.1d, 2.2d, 2.3d, 2.4d, 2.5d, 2.6d, 2.7d, 2.8d, 2.9d); + allOk &= checkTrue("test double SNI arguments", res05 == 3.0d); + + double res06 = testNativeArguments06(3.0f, 3.1d, 3.2f, 3.3d, 3.4f, 3.5d, 3.6f, 3.7d, 3.8f, 3.9d); + allOk &= checkTrue("test float/double SNI arguments", res06 == 4.0d); + + assertTrue(allOk); + } + + /** + * Task class for the round robin test. + */ + private static class RoundRobinTestTask implements Runnable { + + public static int COUNTER = 0; + + private final int id; + + public RoundRobinTestTask(int id) { + this.id = id; + } + + @Override + public void run() { + synchronized (MicroejCoreValidation.ROUND_ROBIN_LOCK) { + if (!MicroejCoreValidation.ROUND_ROBIN_IS_RUNNING) { + ++COUNTER; + System.out.println("Task " + this.id + " is waiting for start..."); + try { + MicroejCoreValidation.ROUND_ROBIN_LOCK.wait(); + } catch (InterruptedException e) { + throw new Error(); + } + } + } + while (MicroejCoreValidation.ROUND_ROBIN_IS_RUNNING) { + ++MicroejCoreValidation.ROUND_ROBIN_TASK_COUNTERS[this.id]; + } + System.out.println("Task " + this.id + " ends."); + } + + } + + /** + * Synchronizes on a list of monitors and sleeps for a while. + */ + private static class MonitorKeeper implements Runnable { + static final int THREAD_COUNT = 5; + static final int MONITOR_PER_THREAD_COUNT = 7; + static final int SLEEP_TIME = 5_000; + public static int errorCount; + + private final Object[] monitors; + + public MonitorKeeper(Object[] monitors) { + this.monitors = monitors; + } + + @Override + public void run() { + try { + synchronizeAll(0); + } catch (Error e) { + errorCount++; + } + } + + private void synchronizeAll(int monitorIndex) { + if (monitorIndex < this.monitors.length) { + synchronized (this.monitors[monitorIndex]) { + synchronizeAll(monitorIndex + 1); + } + } else { + try { + Thread.sleep(SLEEP_TIME); + } catch (InterruptedException e) { + // Nothing to do here. + } + } + } + + } + + // See instructions in README.rst for the implementation of the following native methods. + + private static native float testFloat(float a, float b); + + private static native double testDouble(double a, double b); + + private static native int testNativeArguments01(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, + int i9, int i10); + + private static native long testNativeArguments02(long l1, long l2, long l3, long l4, long l5, long l6, long l7, + long l8, long l9, long l10); + + private static native long testNativeArguments03(int i1, long l2, int i3, long l4, int i5, long l6, int i7, long l8, + int i9, long l10); + + private static native float testNativeArguments04(float f1, float f2, float f3, float f4, float f5, float f6, + float f7, float f8, float f9, float f10); + + private static native double testNativeArguments05(double d1, double d2, double d3, double d4, double d5, double d6, + double d7, double d8, double d9, double d10); + + private static native double testNativeArguments06(float f1, double d2, float f3, double d4, float f5, double d6, + float f7, double d8, float f9, double d10); + +} diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/src/test/java/com/microej/core/tests/package-info.java b/microej/validation/core/java-testsuite-runner-core/src/test/java/com/microej/core/tests/package-info.java similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/src/test/java/com/microej/core/tests/package-info.java rename to microej/validation/core/java-testsuite-runner-core/src/test/java/com/microej/core/tests/package-info.java diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/src/test/resources/com/microej/core/tests/immutables.xml b/microej/validation/core/java-testsuite-runner-core/src/test/resources/com/microej/core/tests/immutables.xml similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/src/test/resources/com/microej/core/tests/immutables.xml rename to microej/validation/core/java-testsuite-runner-core/src/test/resources/com/microej/core/tests/immutables.xml diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/src/test/resources/com/microej/core/tests/microej-core-validation.immutables.list b/microej/validation/core/java-testsuite-runner-core/src/test/resources/com/microej/core/tests/microej-core-validation.immutables.list similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/src/test/resources/com/microej/core/tests/microej-core-validation.immutables.list rename to microej/validation/core/java-testsuite-runner-core/src/test/resources/com/microej/core/tests/microej-core-validation.immutables.list diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/validation/microej-testsuite-common.properties b/microej/validation/core/java-testsuite-runner-core/validation/microej-testsuite-common.properties similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/validation/microej-testsuite-common.properties rename to microej/validation/core/java-testsuite-runner-core/validation/microej-testsuite-common.properties diff --git a/microej/validation/gpio/gpio-testsuite-runner/.gitignore b/microej/validation/gpio/gpio-testsuite-runner/.gitignore new file mode 100644 index 0000000..49dd0f3 --- /dev/null +++ b/microej/validation/gpio/gpio-testsuite-runner/.gitignore @@ -0,0 +1,2 @@ +target~ +src-adpgenerated \ No newline at end of file diff --git a/microej/validation/gpio/gpio-testsuite-runner/.project b/microej/validation/gpio/gpio-testsuite-runner/.project new file mode 100644 index 0000000..315a25d --- /dev/null +++ b/microej/validation/gpio/gpio-testsuite-runner/.project @@ -0,0 +1,11 @@ + + + gpio-testsuite-runner + + + + + + + + diff --git a/microej/validation/gpio/gpio-testsuite-runner/CHANGELOG.md b/microej/validation/gpio/gpio-testsuite-runner/CHANGELOG.md new file mode 100644 index 0000000..de48c11 --- /dev/null +++ b/microej/validation/gpio/gpio-testsuite-runner/CHANGELOG.md @@ -0,0 +1,12 @@ +# Changelog + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/), +and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). + +## 1.0.0 - 2023-07-24 + +### Added + + - Initial revision. diff --git a/microej/validation/gpio/gpio-testsuite-runner/LICENSE.txt b/microej/validation/gpio/gpio-testsuite-runner/LICENSE.txt new file mode 100644 index 0000000..8ed0ac3 --- /dev/null +++ b/microej/validation/gpio/gpio-testsuite-runner/LICENSE.txt @@ -0,0 +1 @@ +[Put your license here] \ No newline at end of file diff --git a/microej/validation/gpio/gpio-testsuite-runner/README.md b/microej/validation/gpio/gpio-testsuite-runner/README.md new file mode 100644 index 0000000..7257925 --- /dev/null +++ b/microej/validation/gpio/gpio-testsuite-runner/README.md @@ -0,0 +1,25 @@ +# Overview + +MicroEJ Testsuite Report: `@MMM_MODULE_NAME@`. + +# Usage + +Add the following line to your `module.ivy`: + + @MMM_DEPENDENCY_DECLARATION@ + +# Requirements + +N/A. + +# Dependencies + +_All dependencies are retrieved transitively by MicroEJ Module Manager_. + +# Source + +N/A. + +# Restrictions + +None. diff --git a/microej/validation/gpio/gpio-testsuite-runner/config.properties b/microej/validation/gpio/gpio-testsuite-runner/config.properties new file mode 100644 index 0000000..5514952 --- /dev/null +++ b/microej/validation/gpio/gpio-testsuite-runner/config.properties @@ -0,0 +1,100 @@ +# Properties +# +# Copyright 2023 NXP Semiconductors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be found with this software. + +############################################################################### +# Testsuite Configuration Options +# +# Usage: +# Uncomment and set options marked '[required]'. +# Other options are set with a value that shall not be changed by default. +# +# Each option can be declared outside this file as a system property: +# In MicroEJ SDK, select 'Window' > 'Preferences' > 'Ant' > 'Runtime' > 'Properties' +# This can be useful to avoid to share absolute file-system locations in this file. +# In this case, it overrides the option defined in this file if any. +# Moreover, options related to local setup (absolute file-system locations, trace ip & port) +# can be extracted to the file 'local.properties' which is ignored for source control. +# +# This file respects the Java properties file convention: the OS path +# must use the UNIX path convention (path separator is '/'). The WINDOWS +# paths must have been converted manually replacing '\' by '/' or by '\\'. +############################################################################### + +############################################################################### +# Target Platform [required] +############################################################################### + +# target.platform.dir=[absolute_path] + +############################################################################### +# BSP Connection [required] +# Uncomment one and only one option block depending on how the target Platform is connected to BSP. +# See https://docs.microej.com/en/latest/PlatformDeveloperGuide/platformCreation.html +############################################################################### + +# No BSP Connection +#microej.testsuite.properties.deploy.dir.microejapp=[absolute_path] +#microej.testsuite.properties.deploy.dir.microejlib=[absolute_path] +#microej.testsuite.properties.deploy.dir.microejinc=[absolute_path] +#microej.testsuite.properties.deploy.bsp.microejscript=[absolute_path] + +# Partial BSP Connection +#microej.testsuite.properties.deploy.bsp.root.dir=[absolute_path] +#microej.testsuite.properties.deploy.bsp.microejscript=true + +# Full BSP Connection +microej.testsuite.properties.deploy.bsp.microejscript=true + +############################################################################### +# Trace Redirection (System.out) +# [required] when trace is redirected by 'Serial to Socket Transmitter' tool, +# otherwise the trace is assumed to be redirected by 'run.bat' or 'run.sh' script. +############################################################################### + +microej.testsuite.properties.testsuite.trace.ip=localhost +microej.testsuite.properties.testsuite.trace.port=5555 + +# Platform specific option to redirect trace on dedicated UART +#microej.testsuite.properties.debug.traces.uart=SET + +############################################################################### +# Tests to run +############################################################################### + +# Comma separated list of patterns of files that must be included +test.run.includes.pattern=**/_AllTests_*.class +# Comma separated list of patterns of files that must be excluded (defaults to inner classes) +test.run.excludes.pattern=**/*$*.class + +####################################################################### +# Advanced Options +# These options shall not be changed by default. +############################################################################### + +# The execution target (`MICROJVM` to execute on Device, `S3` to execute on Simulator) +#target.vm.name=S3 +target.vm.name=MICROJVM + +# The deploy tool to run after the build of the microejapp.o (defaults to 'Platform Configuration Additions') +microej.testsuite.properties.microejtool.deploy.name=deployToolBSPRun + +# Set the verbose or not. Possible values: `true` or `false` +# When this option is set to `true`, the harness will output the execution trace. +microej.testsuite.verbose=true + +# The testsuite timeout (in seconds) +microej.testsuite.timeout=600 + +# The number of times we'll retry a test if it fails +microej.testsuite.retry.count=1 + +# Retry a test unless this pattern is shown +microej.testsuite.retry.unless=VM START + +# A jvm args to pass to the testsuite harness +microej.testsuite.jvmArgs=-Xmx768m + +# A jvm args to pass to launch scripts forked vm +microej.testsuite.properties.launch.properties.jvm=-Xmx2048M \ No newline at end of file diff --git a/microej/validation/gpio/gpio-testsuite-runner/module.ant b/microej/validation/gpio/gpio-testsuite-runner/module.ant new file mode 100644 index 0000000..db5d1d6 --- /dev/null +++ b/microej/validation/gpio/gpio-testsuite-runner/module.ant @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/microej/validation/gpio/gpio-testsuite-runner/module.ivy b/microej/validation/gpio/gpio-testsuite-runner/module.ivy new file mode 100644 index 0000000..bcf7b06 --- /dev/null +++ b/microej/validation/gpio/gpio-testsuite-runner/module.ivy @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/microej/validation/gpio/gpio-testsuite-runner/override.module.ant b/microej/validation/gpio/gpio-testsuite-runner/override.module.ant new file mode 100644 index 0000000..3869e20 --- /dev/null +++ b/microej/validation/gpio/gpio-testsuite-runner/override.module.ant @@ -0,0 +1,16 @@ + + + + + + + + + + + + \ No newline at end of file diff --git a/microej/validation/gpio/gpio-testsuite-runner/validation/microej-testsuite-common.properties b/microej/validation/gpio/gpio-testsuite-runner/validation/microej-testsuite-common.properties new file mode 100644 index 0000000..ef80397 --- /dev/null +++ b/microej/validation/gpio/gpio-testsuite-runner/validation/microej-testsuite-common.properties @@ -0,0 +1,23 @@ +# Testsuite Application Options +# +# Copyright 2023 NXP Semiconductors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be found with this software. + +# Java memory settings +core.memory.immortal.memory=RAM +core.memory.immortal.size=4096 +core.memory.javaheap.memory=RAM +core.memory.javaheap.size=32768 +core.memory.javaheapsum.size=32768 +core.memory.thread.block.size=512 +core.memory.thread.max.size=4 +core.memory.threads.memory=RAM +core.memory.threads.pool.memory=RAM +core.memory.threads.pool.size=15 +core.memory.threads.size=10 + +# Configuration of GPIO01 and unreachable GPIO used by the testsuite. +# Here NXP RT595 board blue LED GPIO used for GPIO01. +microej.java.property.com.nxp.api.gpio.testsuite.gpio01.number=113 +microej.java.property.com.nxp.api.gpio.testsuite.unreachableGpio01.number=220 +microej.java.property.com.nxp.api.gpio.testsuite.unreachableGpio02.number=224 \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/README.rst b/microej/validation/ui/ui3/README.rst similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/ui/ui3/README.rst rename to microej/validation/ui/ui3/README.rst diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/.classpath b/microej/validation/ui/ui3/java-testsuite-runner-ui3/.classpath similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/.classpath rename to microej/validation/ui/ui3/java-testsuite-runner-ui3/.classpath diff --git a/microej/validation/ui/ui3/java-testsuite-runner-ui3/.gitignore b/microej/validation/ui/ui3/java-testsuite-runner-ui3/.gitignore new file mode 100644 index 0000000..bed3d0e --- /dev/null +++ b/microej/validation/ui/ui3/java-testsuite-runner-ui3/.gitignore @@ -0,0 +1,5 @@ +target~/ +bin/ +src-adpgenerated/ +com.microej.ui.tests.*/ +local.properties \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/.project b/microej/validation/ui/ui3/java-testsuite-runner-ui3/.project similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/.project rename to microej/validation/ui/ui3/java-testsuite-runner-ui3/.project diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/.settings/org.eclipse.jdt.core.prefs b/microej/validation/ui/ui3/java-testsuite-runner-ui3/.settings/org.eclipse.jdt.core.prefs similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/.settings/org.eclipse.jdt.core.prefs rename to microej/validation/ui/ui3/java-testsuite-runner-ui3/.settings/org.eclipse.jdt.core.prefs diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/.settings/org.eclipse.jdt.ui.prefs b/microej/validation/ui/ui3/java-testsuite-runner-ui3/.settings/org.eclipse.jdt.ui.prefs similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/.settings/org.eclipse.jdt.ui.prefs rename to microej/validation/ui/ui3/java-testsuite-runner-ui3/.settings/org.eclipse.jdt.ui.prefs diff --git a/microej/validation/ui/ui3/java-testsuite-runner-ui3/CHANGELOG.rst b/microej/validation/ui/ui3/java-testsuite-runner-ui3/CHANGELOG.rst new file mode 100644 index 0000000..6828e3a --- /dev/null +++ b/microej/validation/ui/ui3/java-testsuite-runner-ui3/CHANGELOG.rst @@ -0,0 +1,84 @@ +CHANGELOG +========= + +The format is based on `Keep a +Changelog `__, and this project +adheres to `Semantic +Versioning `__. + +Relationship +------------ + +See `UI Readme `_ to have more information about the relationship between the version of the test suite and the UI Pack. + +.. _170---2024-02-14: + +[1.7.0] - 2023-02-14 +-------------------- + +Changed +~~~~~~~ + +- UI Test Suite 1.7.0 (compatibility with UI Pack 14.0.0). + +Removed +~~~~~~~ + +- Remove ``testBackBufferRestore``: no meaning since UI Pack 14.0.0. + +.. _140---2023-12-05: + +[1.4.0] - 2023-12-05 +-------------------- + +Added +~~~~~ + +- Relationship table between the version of the test suite and the UI Pack in `UI Readme `_. + +Changed +~~~~~~~ + +- UI Test Suite 1.4.0. + +.. _120---2023-02-08: + +[1.2.0] - 2023-02-08 +-------------------- + +Changed +~~~~~~~ + +- UI Test Suite 1.2.0. + +.. _110---2022-07-23: + +[1.1.0] - 2022-07-23 +-------------------- + +Added +~~~~~ + +- Add test `testFlushTime`. +- Add UI Test Suite dependency. + +Changed +~~~~~~~ + +- Reformat to use standard MicroEJ Test Suite flow. +- Update the test ``testBackBufferRestore`` to be compliant with round displays and displays with specific pixels on corners. + +.. _100---2021-04-20: + +[1.0.0] - 2021-04-20 +-------------------- + +Added +~~~~~ + +- Tearing tests: show LCD tearing effect with full screen and black band. +- Drawing time: retrieve the maximum drawing time to have the better framerate. + +.. + Copyright 2021-2024 MicroEJ Corp. All rights reserved. + Use of this source code is governed by a BSD-style license that can be found with this software. diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/LICENSE.txt b/microej/validation/ui/ui3/java-testsuite-runner-ui3/LICENSE.txt similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/LICENSE.txt rename to microej/validation/ui/ui3/java-testsuite-runner-ui3/LICENSE.txt diff --git a/microej/validation/ui/ui3/java-testsuite-runner-ui3/README.rst b/microej/validation/ui/ui3/java-testsuite-runner-ui3/README.rst new file mode 100644 index 0000000..9f6237c --- /dev/null +++ b/microej/validation/ui/ui3/java-testsuite-runner-ui3/README.rst @@ -0,0 +1,164 @@ +.. + Copyright 2021-2024 MicroEJ Corp. All rights reserved. + Use of this source code is governed by a BSD-style license that can be found with this software. + +MicroEJ UI Validation +===================== + +Overview +-------- + +This project contains test cases aimed at validating the correct runtime execution +of UI Pack on a VEE Port connected to a Board Support Package (BSP). + +Tests are written as JUnit test cases, thus the main entry point is automatically generated by MicroEJ SDK. + +Tests can be launched: + +- as a standard Application by using a local launcher, see `Launcher Mode`_. +- as a VEE Port Test Suite by building the module, see `VEE Port Test Suite Mode`_. + +Requirements +------------ + +- MicroEJ SDK version ``5.1.0`` (included in MicroEJ SDK dist. ``19.05``). +- VEE Port built from a MicroEJ UI Pack version ``14.0.0`` or higher. +- See VEE Port Test Suites `documentation <../../../README.rst>`_. + +Relationship +------------ + +The test suite evolves as the UI Pack evolves: bug fixes, new features, etc. +A test suite is, therefore, compatible with a given range of UI Packs (cf UI Pack changelog: https://docs.microej.com/en/latest/VEEPortingGuide/uiChangeLog.html). +The following table shows the relationship between the different versions of the test suite and the associated UI Packs. +(note: Each UI Pack implements a version of MicroUI; cf UI Pack release notes: https://docs.microej.com/en/latest/VEEPortingGuide/uiReleaseNotes.html). + +The table indicates: + +* the version of the project ``java-testsuite-runner-ui3``, +* the version of the test suite library fetched by the project ``java-testsuite-runner-ui3``, +* the compatible UI Packs to run the tests of the test suite, +* the minimum version of the MicroUI API required by the test suite. + ++-----------------+-------------------+-----------------+-------------------+------------------------------------------------------------------------+ +| Project version | TestSuite version | UI Pack Range | MicroUI API Range | Testsuite changes | ++=================+===================+=================+===================+========================================================================+ +| 1.7.0 | 1.7.0 | [14.0.0-15.0.0[ | [3.5.0-4.0.0[ | Add Buffer Refresh Strategies tests | ++-----------------+-------------------+-----------------+-------------------+------------------------------------------------------------------------+ +| 1.4.0 | 1.4.0 | [13.7.0-14.0.0[ | [3.0.3-4.0.0[ | Add image formats with premultiplied alpha values | ++-----------------+-------------------+-----------------+-------------------+------------------------------------------------------------------------+ +| [1.3.0-1.3.1] | 1.3.0 | [13.4.1-14.0.0[ | [3.0.3-4.0.0[ | Allow setting the image heap size according to the display buffer size | ++-----------------+-------------------+-----------------+-------------------+------------------------------------------------------------------------+ +| 1.2.0 | 1.2.0 | [13.4.1-14.0.0[ | [3.0.3-4.0.0[ | Add tests for circles and ellipses | ++-----------------+-------------------+-----------------+-------------------+------------------------------------------------------------------------+ +| 1.1.0 | 1.1.0 | [13.0.0-14.0.0[ | [3.0.3-4.0.0[ | Add tests for GPU ports | ++-----------------+-------------------+-----------------+-------------------+------------------------------------------------------------------------+ +| 1.0.0 | 1.0.0 | [13.0.0-14.0.0[ | [3.0.3-4.0.0[ | Initial version | ++-----------------+-------------------+-----------------+-------------------+------------------------------------------------------------------------+ + +Usage +----- + +Launcher Mode +~~~~~~~~~~~~~ + +In MicroEJ SDK, + +- Select ``Run > Run Configurations...``. A launcher named + ``java-testsuite-runner-ui3`` should be available under + ``MicroEJ Application``. + +- In ``Execution`` tab, select the target VEE Port. + +- Click on ``Run`` button to compile the MicroEJ Application. + +- Link the BSP project with the MicroEJ Application (``microejapp.o``), + the VEE Port runtime (``microejruntime.a``) and the VEE Port header files (``*.h``). + +- See below for an output example + +:: + + ***************************************************************************************************** + * MicroEJ UI Validation - 1.7.0 * + ***************************************************************************************************** + * Copyright 2021-2024 MicroEJ Corp. All rights reserved. * + * Use of this source code is governed by a BSD-style license that can be found with this software. * + ***************************************************************************************************** + + -> Check LCD tearing: full screen (LLUI_DISPLAY_IMPL_flush validation)... + Property 'com.microej.ui.tests.clock.seconds' is not set (default to '10' second(s)) + OK: testTearingFullScreen + -> Check LCD tearing: black band (LLUI_DISPLAY_IMPL_flush validation)... + Property 'com.microej.ui.tests.clock.seconds' is not set (default to '10' second(s)) + OK: testTearingVerticalBand + Property 'com.microej.ui.tests.flush.tolerance.us' is not set (default to '200' us) + LCD framerate time is 17528 us (57.051579 Hz) + Retrieve the maximal drawing time (this will take several seconds)... + The flush time is 7.708000 us + To have an animation at 57.051579 Hz, the drawing time cannot be higher than 9.820000 ms. + To have an animation at 28.525789 Hz, the drawing time cannot be higher than 27.348000 ms. + To have an animation at 19.017193 Hz, the drawing time cannot be higher than 44.875999 ms. + OK: testDrawingTime + OK: testBackBufferRestore + flush time (several iterations): 0 + wait flush time (several iterations): 295 + OK: testFlushTime + PASSED: 5 + +VEE Port Test Suite Mode +~~~~~~~~~~~~~~~~~~~~~~~~ + +- In MicroEJ SDK, import the ``java-testsuite-runner-ui3`` project in your workspace. + +- Follow the configuration and execution steps described in VEE Port Test Suites `documentation <../../../README.rst>`_. + +Tests Suite Description +----------------------- + +All tests can be run in one step: all tests will be executed one by one +and are run in a specific order, *next one* expects *previous one* is +passed. + +Tearing +~~~~~~~ + +A tearing effect (flickering) visible on LCD indicates a synchronization issue with +the LCD tearing signal (TE). + +* "Full screen" test toggles black and white screens. If the flush job is properly synchronized and quite fast, the LCD is gray. The LCD being cut in multiple parts indicates a synchronization issue of the flush job. + +* "Black band" test moves a black band on a white background. The band being cut in multiple parts indicates a synchronization issue of the flush job. + +Drawing Time +~~~~~~~~~~~~ + +This test is useful when the implementation of ``LLUI_DISPLAY_IMPL_flush`` uses the `SWITCH mode `_. +"Drawing time" test determinates the maximum drawing time (in milliseconds) for a given +framerate. The possible framerates depend on the LCD and on the post-flush copy step. When the +drawing time exceeds the maximum drawing time, the framerate is divided by two when the flush +job is synchronized on LCD tearing signal. + +Flush Time +~~~~~~~~~~ + +The implementation of the function ``LLUI_DISPLAY_IMPL_flush`` must be as fast as possible: it is not a blocking function (see function specification). +The implementation has to launch a third-party process (software task or hardware process) to perform the operation and returns. +Once the third-party process has finished, the callback has to call the function ``LLUI_DISPLAY_flushDone``. + +This test checks that the implementation of ``LLUI_DISPLAY_IMPL_flush`` is not a blocking function. + +Dependencies +------------ + +*All dependencies are retrieved transitively by MicroEJ Module Manager*. + +Source +------ + +N/A + +Restrictions +------------ + +None. diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/build/common.properties b/microej/validation/ui/ui3/java-testsuite-runner-ui3/build/common.properties similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/build/common.properties rename to microej/validation/ui/ui3/java-testsuite-runner-ui3/build/common.properties diff --git a/microej/validation/ui/ui3/java-testsuite-runner-ui3/config.properties b/microej/validation/ui/ui3/java-testsuite-runner-ui3/config.properties new file mode 100644 index 0000000..f1396d9 --- /dev/null +++ b/microej/validation/ui/ui3/java-testsuite-runner-ui3/config.properties @@ -0,0 +1,101 @@ +# Properties +# +# Copyright 2021-2022 MicroEJ Corp. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be found with this software. + +############################################################################### +# Testsuite Configuration Options +# +# Usage: +# Uncomment and set options marked '[required]'. +# Other options are set with a value that shall not be changed by default. +# +# Each option can be declared outside this file as a system property: +# In MicroEJ SDK, select 'Window' > 'Preferences' > 'Ant' > 'Runtime' > 'Properties' +# This can be useful to avoid to share absolute file-system locations in this file. +# In this case, it overrides the option defined in this file if any. +# Moreover, options related to local setup (absolute file-system locations, trace ip & port) +# can be extracted to the file 'local.properties' which is ignored for source control. +# +# This file respects the Java properties file convention: the OS path +# must use the UNIX path convention (path separator is '/'). The WINDOWS +# paths must have been converted manually replacing '\' by '/' or by '\\'. +############################################################################### + +############################################################################### +# Target Platform [required] +############################################################################### + +# defined in module.ant +#target.platform.dir= + +############################################################################### +# BSP Connection [required] +# Uncomment one and only one option block depending on how the target Platform is connected to BSP. +# See https://docs.microej.com/en/latest/PlatformDeveloperGuide/platformCreation.html +############################################################################### + +# No BSP Connection +#microej.testsuite.properties.deploy.dir.microejapp=[absolute_path] +#microej.testsuite.properties.deploy.dir.microejlib=[absolute_path] +#microej.testsuite.properties.deploy.dir.microejinc=[absolute_path] +#microej.testsuite.properties.deploy.bsp.microejscript=[absolute_path] + +# Partial BSP Connection +#microej.testsuite.properties.deploy.bsp.root.dir=[absolute_path] +#microej.testsuite.properties.deploy.bsp.microejscript=true + +# Full BSP Connection +microej.testsuite.properties.deploy.bsp.microejscript=true + +############################################################################### +# Trace Redirection (System.out) +# [required] when trace is redirected by 'Serial to Socket Transmitter' tool, +# otherwise the trace is assumed to be redirected by 'run.bat' or 'run.sh' script. +############################################################################### + +microej.testsuite.properties.testsuite.trace.ip=localhost +microej.testsuite.properties.testsuite.trace.port=5555 + +# Platform specific option to redirect trace on dedicated UART +#microej.testsuite.properties.debug.traces.uart=SET + +############################################################################### +# Tests to run +############################################################################### + +# Comma separated list of patterns of files that must be included +test.run.includes.pattern=**/_AllTests_*.class +# Comma separated list of patterns of files that must be excluded (defaults to inner classes) +# **/_AllTests_DrawAntiAliasedArc*.class: Test failure cause of the GCC version used to build the UI pack (float approximation issue). +test.run.excludes.pattern=**/*$*.class, **/_AllTests_DrawAntiAliasedArc*.class + +####################################################################### +# Advanced Options +# These options shall not be changed by default. +############################################################################### + +# The execution target (`MICROJVM` to execute on Device, `S3` to execute on Simulator) +target.vm.name=MICROJVM + +# The deploy tool to run after the build of the microejapp.o (defaults to 'Platform Configuration Additions') +microej.testsuite.properties.microejtool.deploy.name=deployToolBSPRun + +# Set the verbose or not. Possible values: `true` or `false` +# When this option is set to `true`, the harness will output the execution trace. +microej.testsuite.verbose=true + +# The testsuite timeout (in seconds) +microej.testsuite.timeout=600 + +# The number of times we'll retry a test if it fails +microej.testsuite.retry.count=1 + +# Retry a test unless this pattern is shown +microej.testsuite.retry.unless=VM START + +# A jvm args to pass to the testsuite harness +microej.testsuite.jvmArgs=-Xmx768m + +# A jvm args to pass to launch scripts forked vm +microej.testsuite.properties.launch.properties.jvm=-Xmx2048M diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/config.properties.tpl b/microej/validation/ui/ui3/java-testsuite-runner-ui3/config.properties.tpl similarity index 97% rename from nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/config.properties.tpl rename to microej/validation/ui/ui3/java-testsuite-runner-ui3/config.properties.tpl index df25404..197e782 100644 --- a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/config.properties.tpl +++ b/microej/validation/ui/ui3/java-testsuite-runner-ui3/config.properties.tpl @@ -1,6 +1,6 @@ # Properties # -# Copyright 2021-2022 MicroEJ Corp. All rights reserved. +# Copyright 2021-2023 MicroEJ Corp. All rights reserved. # Use of this source code is governed by a BSD-style license that can be found with this software. ############################################################################### @@ -38,7 +38,7 @@ #microej.testsuite.properties.deploy.dir.microejapp=[absolute_path] #microej.testsuite.properties.deploy.dir.microejlib=[absolute_path] #microej.testsuite.properties.deploy.dir.microejinc=[absolute_path] -#microej.testsuite.properties.deploy.bsp.microejscript=[absolute_path] +#microej.testsuite.properties.deploy.dir.microejscript=[absolute_path] # Partial BSP Connection #microej.testsuite.properties.deploy.bsp.root.dir=[absolute_path] diff --git a/microej/validation/ui/ui3/java-testsuite-runner-ui3/module.ant b/microej/validation/ui/ui3/java-testsuite-runner-ui3/module.ant new file mode 100644 index 0000000..27d851b --- /dev/null +++ b/microej/validation/ui/ui3/java-testsuite-runner-ui3/module.ant @@ -0,0 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/microej/validation/ui/ui3/java-testsuite-runner-ui3/module.ivy b/microej/validation/ui/ui3/java-testsuite-runner-ui3/module.ivy new file mode 100644 index 0000000..a46c2f3 --- /dev/null +++ b/microej/validation/ui/ui3/java-testsuite-runner-ui3/module.ivy @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/override.module.ant b/microej/validation/ui/ui3/java-testsuite-runner-ui3/override.module.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/override.module.ant rename to microej/validation/ui/ui3/java-testsuite-runner-ui3/override.module.ant diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/src/main/resources/.gitkeep b/microej/validation/ui/ui3/java-testsuite-runner-ui3/src/main/java/.gitkeep similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/src/main/resources/.gitkeep rename to microej/validation/ui/ui3/java-testsuite-runner-ui3/src/main/java/.gitkeep diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/src/test/resources/.gitkeep b/microej/validation/ui/ui3/java-testsuite-runner-ui3/src/main/resources/.gitkeep similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/src/test/resources/.gitkeep rename to microej/validation/ui/ui3/java-testsuite-runner-ui3/src/main/resources/.gitkeep diff --git a/microej/validation/ui/ui3/java-testsuite-runner-ui3/src/test/java/com/microej/ui/tests/MicroejUiValidation.java b/microej/validation/ui/ui3/java-testsuite-runner-ui3/src/test/java/com/microej/ui/tests/MicroejUiValidation.java new file mode 100644 index 0000000..d5ccaa6 --- /dev/null +++ b/microej/validation/ui/ui3/java-testsuite-runner-ui3/src/test/java/com/microej/ui/tests/MicroejUiValidation.java @@ -0,0 +1,339 @@ +/* + * Java + * + * Copyright 2021-2024 MicroEJ Corp. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be found with this software. + */ +package com.microej.ui.tests; + +import static org.junit.Assert.assertTrue; + +import org.junit.AfterClass; +import org.junit.BeforeClass; +import org.junit.Test; + +import ej.bon.Constants; +import ej.bon.Util; +import ej.microui.MicroUI; +import ej.microui.display.Colors; +import ej.microui.display.Display; +import ej.microui.display.GraphicsContext; +import ej.microui.display.Painter; + +/** + * MicroEJ UI Validation tests. + */ +public class MicroejUiValidation { + + private static final String VERSION = "1.7.0"; + + /** + * Properties suffix: add "-Dcom.microej.ui.tests.xxx=xxx" in your JRE tab + */ + private static final String PROPERTY_SUFFIX = "com.microej.ui.tests."; + + /** + * Property to fix each test time; default value is 10s. + */ + private static final String OPTION_CLOCK_NB_SECONDS = "clock.seconds"; + private static final int DEFAULT_TIME_TEST_SECONDS = 10; + + /** + * Property to fix the flush time tolerance. This value must be lower than hardware flush time. + */ + private static final String OPTION_FLUSH_TOLERANCE_NB_US = "flush.tolerance.us"; + private static final int DEFAULT_TIME_TOLERANCE_US = 200; + + private static void printProduct() { + final String sep = "*****************************************************************************************************"; + System.out.println(sep); + System.out.println("* MicroEJ UI Validation - " + VERSION + + " *"); + System.out.println(sep); + System.out.println( + "* Copyright 2021-2024 MicroEJ Corp. All rights reserved. *"); + System.out.println( + "* Use of this source code is governed by a BSD-style license that can be found with this software. *"); + System.out.println(sep); + System.out.println(); + } + + private static int getOptionAsInt(String optionName, int defaultValue, String unit) { + String propertyName = PROPERTY_SUFFIX + optionName; + String valueStr = System.getProperty(propertyName); + int value; + if (valueStr == null) { + value = defaultValue; + System.out.println("Property '" + propertyName + "' is not set (default to '" + value + "' " + unit + ")"); + } else { + try { + value = Integer.parseInt(valueStr); + System.out.println("Property '" + propertyName + "' is set to '" + value + "' " + unit); + } catch (NumberFormatException e) { + value = defaultValue; + System.out.println("Property '" + propertyName + "' is invalid (set to '" + valueStr + "', default to '" + + value + "' " + unit + ")"); + } + } + return value; + } + + /** + * @throws java.lang.Exception + * If an error occurred. + */ + @BeforeClass + public static void setUpBeforeClass() throws Exception { + MicroUI.start(); + printProduct(); + } + + /** + * Stops MicroUI. + */ + @AfterClass + public static void afterClass() { + MicroUI.stop(); + } + + /** + * Tests the LLUI_DISPLAY_IMPL_flush implementation: the LCD tearing (flickering). + *

+ * Shows alternately black and white screens. The tearing effect is visible when the screen is cut in two or more + * parts. + */ + @Test + public void testTearingFullScreen() { + System.out.println("-> Check LCD tearing: full screen (LLUI_DISPLAY_IMPL_flush validation)..."); + int nbSeconds = getOptionAsInt(OPTION_CLOCK_NB_SECONDS, DEFAULT_TIME_TEST_SECONDS, "second(s)"); + + Display display = Display.getDisplay(); + GraphicsContext gc = display.getGraphicsContext(); + + // Check if a message is printed every seconds in terminal: + long timeStart = System.currentTimeMillis(); + long nbMilliSeconds = nbSeconds * 1000; + while (true) { + gc.setColor(Colors.WHITE); + Painter.fillRectangle(gc, 0, 0, display.getWidth(), display.getHeight()); + display.flush(); + gc.setColor(Colors.BLACK); + Painter.fillRectangle(gc, 0, 0, display.getWidth(), display.getHeight()); + display.flush(); + long time = System.currentTimeMillis(); + long delta = time - timeStart; + if (delta > nbMilliSeconds) { + break; // end of test + } + } + } + + /** + * Tests the LLUI_DISPLAY_IMPL_flush implementation: the LCD tearing (flickering). + *

+ * Shows a vertical black band that moves as fast as possible on a white background. The tearing effect is visible + * when the vertical band is cut in two or more parts. + */ + @Test + public void testTearingVerticalBand() { + System.out.println("-> Check LCD tearing: black band (LLUI_DISPLAY_IMPL_flush validation)..."); + + Display display = Display.getDisplay(); + GraphicsContext g = display.getGraphicsContext(); + int displayWidth = display.getWidth(); + int displayHeight = display.getHeight(); + + // retrieve test time + int nbSeconds = getOptionAsInt(OPTION_CLOCK_NB_SECONDS, DEFAULT_TIME_TEST_SECONDS, "second(s)"); + + long timeStart = System.currentTimeMillis(); + long nbMilliSeconds = nbSeconds * 1000; + int bandWidth = displayWidth / 10; + int bandX = 0; + int bandXIncrement = 4; + + do { + + // draw background + g.setColor(Colors.WHITE); + Painter.fillRectangle(g, 0, 0, displayWidth, displayHeight); + + // draw band + g.setColor(Colors.BLACK); + Painter.fillRectangle(g, bandX, 0, bandWidth, displayHeight); + + // flush content + display.flush(); + + // get next band position + bandX += bandXIncrement; + if (bandX + bandWidth >= displayWidth || bandX <= 0) { + bandXIncrement = -bandXIncrement; + } + + } while (System.currentTimeMillis() - timeStart < nbMilliSeconds); + } + + /** + * Called by {@link #testDrawingTime()} to force a flush and wait the end of this flush. + */ + private void forceFlushAndWait() { + Display display = Display.getDisplay(); + GraphicsContext gc = display.getGraphicsContext(); + + // have to draw something to "enable" the flush + Painter.writePixel(gc, 0, 0); + Painter.writePixel(gc, display.getWidth() - 1, display.getHeight() - 1); + + display.flush(); + display.waitFlushCompleted(); + } + + /** + * Called by {@link #testDrawingTime()} to get the framerate time according a given drawing time. + */ + private int getFramerateTimeUs(int drawingTimeUs) { + + int nbLoops = 20; + long timeCounter = 0; + long drawingTimeNs = drawingTimeUs * 1000; + + forceFlushAndWait(); + + for (int i = nbLoops; --i >= 0;) { + + long t0 = Util.platformTimeNanos(); + + // simulate some drawings + while (Util.platformTimeNanos() - t0 < drawingTimeNs) { + ; + } + + forceFlushAndWait(); + + long t1 = Util.platformTimeNanos(); + timeCounter += (t1 - t0); + } + return (int) (timeCounter / 1000 / nbLoops); + } + + /** + * Called by {@link #testDrawingTime()} to find the maximum drawing time without exceed framerate time. + */ + private int adjustDrawingTime(int drawingTimeUs, int drawingTimeStepUs, int framerateTimeRefUs, + int framerateTimeToleranceUs) { + + int framerateWithDrawingTimeUs = framerateTimeRefUs; + while (framerateWithDrawingTimeUs < framerateTimeRefUs + framerateTimeToleranceUs) { + drawingTimeUs += drawingTimeStepUs; + framerateWithDrawingTimeUs = getFramerateTimeUs(drawingTimeUs); + // System.out.println(drawingTimeUs + " " + framerateWithDrawingTimeUs); + } + return drawingTimeUs - drawingTimeStepUs; + } + + /** + * Called by {@link #testDrawingTime()} to print a report + */ + private void printFramerateReport(float frequency, int div, int framerateTimeUs, int flushTimeMs) { + System.out.print("To have an animation at "); + System.out.print(frequency / div); + System.out.print(" Hz, the drawing time cannot be higher than "); + System.out.print(((float) (framerateTimeUs * div - flushTimeMs)) / 1000); + System.out.print(" ms.\n"); + } + + /** + * Tests the LLUI_DISPLAY_IMPL_flush implementation: the drawing time. + *

+ * Determinates the maximum drawing time to have the better framerate as possible. + */ + @Test + public void testDrawingTime() { + + // retrieve flush time tolereance + int framerateTimeToleranceUs = getOptionAsInt(OPTION_FLUSH_TOLERANCE_NB_US, DEFAULT_TIME_TOLERANCE_US, "us"); + + // retrieve LCD framerate time and frequency + int framerateTimeUs = getFramerateTimeUs(0); + float framerateHz = 1000000 / (float) framerateTimeUs; + System.out.println("LCD framerate time is " + framerateTimeUs + " us (" + framerateHz + " Hz)"); + + // retrieve maximum drawing time to have better framerate + System.out.println("Retrieve the maximal drawing time (this will take several seconds)..."); + int drawingTimeUs = 0; + for (int drawingTimeStepUs = 1000; drawingTimeStepUs >= 10; drawingTimeStepUs /= 10) { + drawingTimeUs = adjustDrawingTime(drawingTimeUs, drawingTimeStepUs, framerateTimeUs, + framerateTimeToleranceUs); + } + + // retrieve flush time thanks to LCD framerate and maximum drawing time + int flushTimeUs = framerateTimeUs - drawingTimeUs; + + // print reports + System.out.println("The flush time is " + flushTimeUs + " us"); + printFramerateReport(framerateHz, 1, framerateTimeUs, flushTimeUs); + printFramerateReport(framerateHz, 2, framerateTimeUs, flushTimeUs); + printFramerateReport(framerateHz, 3, framerateTimeUs, flushTimeUs); + } + + /** + * Tests the LLUI_DISPLAY_IMPL_flush implementation: this function should be as fast as possible. + *

+ * The "flush" consists to update the content of the display frame buffer with the content of the application buffer + * (back buffer). This update may be instantaneous ("Switch" mode) or can take some time ("Copy" mode): memory copy, + * serial data sent, etc. The implementation has to delegate the "flush" to another asynchronous task (hardware or + * software) in order to return as soon as possible. This allows the application to do other work during this + * update. + *

+ * The Graphics Engine has the responsability to wait the end of this asynchronous task before allowing a new + * drawing in the application buffer. This waiting is automatic (first call to a drawing method after a flush is + * blocker) or explicit (call to {@link Display#waitFlushCompleted()}). + *

+ * The LLUI_DISPLAY_impl.h implementation must call LLUI_DISPLAY_flushDone() to unlock the + * Graphics Engine. + *

+ * This test has no meaning on the simulator. It is automatically disabled. + */ + @Test + public void testFlushTime() { + + if (isRunningOnSimulator()) { + // see method comment + return; + } + + Display display = Display.getDisplay(); + GraphicsContext g = display.getGraphicsContext(); + int displayWidth = display.getWidth(); + int displayHeight = display.getHeight(); + + long tFlush = 0; + long tWait = 0; + + // perform several tests + for (int i = 10; --i >= 0;) { + + // draw in all back buffer + g.setColor(Colors.WHITE); + Painter.fillRectangle(g, 0, 0, displayWidth, displayHeight); + + long t0 = System.currentTimeMillis(); + display.flush(); + long t1 = System.currentTimeMillis(); + display.waitFlushCompleted(); + long t2 = System.currentTimeMillis(); + + tFlush += (t1 - t0); + tWait += (t2 - t1); + } + + System.out.println("flush time (several iterations): " + tFlush); + System.out.println("wait flush time (several iterations): " + tWait); + assertTrue("flush time must be smaller than waitFlush time", tFlush < tWait); + } + + private boolean isRunningOnSimulator() { + return Constants.getBoolean("com.microej.library.microui.onS3"); + } +} diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/src/test/java/com/microej/ui/tests/package-info.java b/microej/validation/ui/ui3/java-testsuite-runner-ui3/src/test/java/com/microej/ui/tests/package-info.java similarity index 100% rename from nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/src/test/java/com/microej/ui/tests/package-info.java rename to microej/validation/ui/ui3/java-testsuite-runner-ui3/src/test/java/com/microej/ui/tests/package-info.java diff --git a/microej/validation/ui/ui3/java-testsuite-runner-ui3/src/test/resources/.gitkeep b/microej/validation/ui/ui3/java-testsuite-runner-ui3/src/test/resources/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/microej/validation/ui/ui3/java-testsuite-runner-ui3/validation/microej-testsuite-common.properties b/microej/validation/ui/ui3/java-testsuite-runner-ui3/validation/microej-testsuite-common.properties new file mode 100644 index 0000000..0668f20 --- /dev/null +++ b/microej/validation/ui/ui3/java-testsuite-runner-ui3/validation/microej-testsuite-common.properties @@ -0,0 +1,19 @@ +# Testsuite Application Options +# +# Copyright 2021-2022 MicroEJ Corp. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be found with this software. + +# Java memory settings +core.memory.immortal.memory=RAM +core.memory.immortal.size=4096 +core.memory.javaheap.memory=RAM +core.memory.javaheap.size=65536 +core.memory.javaheapsum.size=65536 +core.memory.thread.block.size=512 +core.memory.thread.max.size=10 +core.memory.threads.memory=RAM +core.memory.threads.pool.memory=RAM +core.memory.threads.pool.size=30 +core.memory.threads.size=18 + + ej.microui.memory.imagesheap.size=65536 \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-configuration/.project b/microej/vee-port-configuration/.project similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/.project rename to microej/vee-port-configuration/.project diff --git a/nxpvee-mimxrt595-evk-round-configuration/LICENSE.txt b/microej/vee-port-configuration/LICENSE.txt similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/LICENSE.txt rename to microej/vee-port-configuration/LICENSE.txt diff --git a/nxpvee-mimxrt595-evk-round-configuration/bsp/bsp.properties b/microej/vee-port-configuration/bsp/bsp.properties similarity index 91% rename from nxpvee-mimxrt595-evk-round-configuration/bsp/bsp.properties rename to microej/vee-port-configuration/bsp/bsp.properties index bff09b2..a67d6cc 100644 --- a/nxpvee-mimxrt595-evk-round-configuration/bsp/bsp.properties +++ b/microej/vee-port-configuration/bsp/bsp.properties @@ -19,4 +19,6 @@ microejscript.relative.dir=projects/microej/scripts # Specify the BSP root directory. Can use ${project.parent.dir} which target the parent of platform configuration project # For example, '${workspace}/${project.prefix}-bsp' specifies a BSP project beside the '-configuration' project -root.dir=${project.parent.dir}/nxpvee-mimxrt595-evk-round-bsp +root.dir=${project.parent.dir}/../bsp + +deploy.bsp.root.dir=${project.parent.dir}/../bsp diff --git a/microej/vee-port-configuration/build/CHANGELOG.md b/microej/vee-port-configuration/build/CHANGELOG.md new file mode 100644 index 0000000..2337a1e --- /dev/null +++ b/microej/vee-port-configuration/build/CHANGELOG.md @@ -0,0 +1,107 @@ +# Changelog + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/), +and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). + +## [2.1.0] - 2023-12-05 + +This version requires SDK `5.8.0` or higher. + +### Added + +- Add support for Architecture version `8.1.0`. + The _Multi Applications_ (`kf`) module has been removed and replaced by the property `com.microej.runtime.capability`. + This property can be set either in the configuration project (in `mjvm/mjvm.properties` file) or as an MMM property to override the configuration project. + The MMM property `com.microej.platformbuilder.module.multi.enabled` is deprecated but still supported when `com.microej.runtime.capability` is not set. +- Add execution of artifact checker for `CHANGELOG.rst` and `LICENSE.txt` (`README.rst` is ignored). +- Add publication of `NOTICE.txt` and `MICROEJ_SDK_EULA.txt` files. The notice describes the list of files licensed under SDK EULA. +- Add include/exclude pattern when copying the BSP project. +- Rename Platform to VEE Port in module.ivy. +- Use include/exclude pattern when copying the bsp project. + +### Fixed + +- Fix execution of artifact checker on `-configuration` project instead of `-fp` project. +- Fix build and run Linux scripts end-of-line (EOL) characters if the VEE port was built on Windows. +- Fix update in some cases of The _Multi Applications_ (`kf`) module in the `.platform` file (only when `com.microej.platformbuilder.module.multi.enabled` was set to `true`). + +## [2.0.0] - [2023-06-29] + +### Added + +- Add support to execute the optional RIP scripts that configure the RIP's module during the build of the VEE Port (`build/autoConfigurationXXX.xml` or `build/platform-XXX.ant`). + +### Changed + +- Separate files required for SDK version `5.x` from files required for Architecture version `7.x`. + +### Fixed + +- Fix new empty line generated in the `.platform` file when `com.microej.platformbuilder.module.multi.enabled` is set to `true`. This prevents a useless change in the VCS. + +## [1.4.0] - [2021-07-07] + +### Changed + +- Copy the files LICENSE.txt, README.rst, RELEASE_NOTES.rst and CHANGELOG.rst to the artifact published if the files are available. +- Plug the artifact checker to allow the check the artifact published (disabled by default). + +## [1.3.1] - [2021-06-30] + +### Changed + +- Moved `module.ivy` examples of dependencies in comments with description + +## [1.3.0] - [2021-05-11] + +### Added + +- Add MicroEJ SDK tool to deploy an executable file on device using the BSP run script +- Add an option to check if the platform project exists + +### Changed + +- Execute bash script file (`.sh`) with `/bin/bash`. This ensure the build and run scripts are properly executed regardless of their file permissions. +- Use placeholders for platform name and platform version in `default.platform` to make it obvious it is generated automatically. + +### Fixed + +- Execute `.bat` scripts on Windows 11 instead of `.sh` scripts. + +## [1.2.0] - 2021-04-16 + +### Added + +- Add `default.platform` to allow any empty project to be converted as a Platform project (no longer need to import a MicroEJ Architecture first). +- Set default module version to `0.1.0` as other MicroEJ SDK skeletons. +- Set default module organization to `com.mycompany` as other MicroEJ SDK skeletons. +- Use a new private configuration `embedded` as the default for the platform dependencies. This prevents an instance of "Too many loaded Platforms" error in `platform-loader`. + +### Fixed + +- Fix documentation in `bsp.properties`: + + - The variable `${project.prefix}` is no longer supported. + - The variables `*.relative.dir` are relative to the BSP root directory. + +- Fix execution of `run.[bat|sh]` in the directory where is defined `application.out`. +- Fix module configurations for correct Platform module import (especially in a module repository) +- Fix module build crash when no README file is declared (optional) + +## [1.1.0] - 2021-01-08 + +### Changed + + - Added scripts and `module.ivy` file for Platform module build and publication. + +## [1.0.0] - 2020-06-24 + +### Added + + - Initial version with scripts for BSP connection. + +--- +_Copyright 2020-2023 MicroEJ Corp. All rights reserved._ +_Use of this source code is governed by a BSD-style license that can be found with this software._ diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/README.md b/microej/vee-port-configuration/build/README.md similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/README.md rename to microej/vee-port-configuration/build/README.md diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/README.md b/microej/vee-port-configuration/build/module/README.md similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/README.md rename to microej/vee-port-configuration/build/module/README.md diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/license-checker.jar b/microej/vee-port-configuration/build/module/license-checker.jar similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/license-checker.jar rename to microej/vee-port-configuration/build/module/license-checker.jar diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-bsp.ant b/microej/vee-port-configuration/build/module/module-bsp.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-bsp.ant rename to microej/vee-port-configuration/build/module/module-bsp.ant diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-files.ant b/microej/vee-port-configuration/build/module/module-files.ant similarity index 94% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-files.ant rename to microej/vee-port-configuration/build/module/module-files.ant index e1345e4..13c92fe 100644 --- a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-files.ant +++ b/microej/vee-port-configuration/build/module/module-files.ant @@ -22,7 +22,7 @@ - + @@ -35,7 +35,7 @@ - + diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-frontpanel.ant b/microej/vee-port-configuration/build/module/module-frontpanel.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-frontpanel.ant rename to microej/vee-port-configuration/build/module/module-frontpanel.ant diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-group.ant b/microej/vee-port-configuration/build/module/module-group.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-group.ant rename to microej/vee-port-configuration/build/module/module-group.ant diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-group/README.md b/microej/vee-port-configuration/build/module/module-group/README.md similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-group/README.md rename to microej/vee-port-configuration/build/module/module-group/README.md diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-group/addGroup.xsl b/microej/vee-port-configuration/build/module/module-group/addGroup.xsl similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-group/addGroup.xsl rename to microej/vee-port-configuration/build/module/module-group/addGroup.xsl diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-group/removeGroup.xsl b/microej/vee-port-configuration/build/module/module-group/removeGroup.xsl similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-group/removeGroup.xsl rename to microej/vee-port-configuration/build/module/module-group/removeGroup.xsl diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-license.ant b/microej/vee-port-configuration/build/module/module-license.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-license.ant rename to microej/vee-port-configuration/build/module/module-license.ant diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-platform.ant b/microej/vee-port-configuration/build/module/module-platform.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-platform.ant rename to microej/vee-port-configuration/build/module/module-platform.ant diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-platform/MicroEJFramework.xml b/microej/vee-port-configuration/build/module/module-platform/MicroEJFramework.xml similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-platform/MicroEJFramework.xml rename to microej/vee-port-configuration/build/module/module-platform/MicroEJFramework.xml diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-platform/README.md b/microej/vee-port-configuration/build/module/module-platform/README.md similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-platform/README.md rename to microej/vee-port-configuration/build/module/module-platform/README.md diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-platform/eclipseantrunner.ant b/microej/vee-port-configuration/build/module/module-platform/eclipseantrunner.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-platform/eclipseantrunner.ant rename to microej/vee-port-configuration/build/module/module-platform/eclipseantrunner.ant diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-publish.ant b/microej/vee-port-configuration/build/module/module-publish.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-publish.ant rename to microej/vee-port-configuration/build/module/module-publish.ant diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-ripinstall.ant b/microej/vee-port-configuration/build/module/module-ripinstall.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-ripinstall.ant rename to microej/vee-port-configuration/build/module/module-ripinstall.ant diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-validation.ant b/microej/vee-port-configuration/build/module/module-validation.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module-validation.ant rename to microej/vee-port-configuration/build/module/module-validation.ant diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module.ant b/microej/vee-port-configuration/build/module/module.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/module/module.ant rename to microej/vee-port-configuration/build/module/module.ant diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/platform/README.md b/microej/vee-port-configuration/build/platform/README.md similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/platform/README.md rename to microej/vee-port-configuration/build/platform/README.md diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/platform/platform-rip.ant b/microej/vee-port-configuration/build/platform/platform-rip.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/platform/platform-rip.ant rename to microej/vee-port-configuration/build/platform/platform-rip.ant diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/platform/platform.ant b/microej/vee-port-configuration/build/platform/platform.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/build/platform/platform.ant rename to microej/vee-port-configuration/build/platform/platform.ant diff --git a/nxpvee-mimxrt595-evk-round-configuration/configuration.xml b/microej/vee-port-configuration/configuration.xml similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/configuration.xml rename to microej/vee-port-configuration/configuration.xml diff --git a/nxpvee-mimxrt595-evk-round-configuration/display/display.properties b/microej/vee-port-configuration/display/display.properties similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/display/display.properties rename to microej/vee-port-configuration/display/display.properties diff --git a/microej/vee-port-configuration/dropins/gpio/gpio.properties b/microej/vee-port-configuration/dropins/gpio/gpio.properties new file mode 100644 index 0000000..b3a0f59 --- /dev/null +++ b/microej/vee-port-configuration/dropins/gpio/gpio.properties @@ -0,0 +1,4 @@ +userButton=25 +greenLED=32 +redLED=14 +blueLED=113 \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-configuration/dropins/tools/imageGenerator-mimxrt595.jar b/microej/vee-port-configuration/dropins/tools/imageGenerator-mimxrt595.jar similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/dropins/tools/imageGenerator-mimxrt595.jar rename to microej/vee-port-configuration/dropins/tools/imageGenerator-mimxrt595.jar diff --git a/nxpvee-mimxrt595-evk-round-configuration/frontpanel/frontpanel.properties b/microej/vee-port-configuration/frontpanel/frontpanel.properties similarity index 76% rename from nxpvee-mimxrt595-evk-round-configuration/frontpanel/frontpanel.properties rename to microej/vee-port-configuration/frontpanel/frontpanel.properties index 4cc9379..8859710 100644 --- a/nxpvee-mimxrt595-evk-round-configuration/frontpanel/frontpanel.properties +++ b/microej/vee-port-configuration/frontpanel/frontpanel.properties @@ -2,5 +2,5 @@ # Copyright 2022 MicroEJ Corp. All rights reserved. # Use of this source code is governed by a BSD-style license that can be found with this software. # -project.name=nxpvee-mimxrt595-evk-round-fp +project.name=front-panel diff --git a/microej/vee-port-configuration/imxrt595evk.platform b/microej/vee-port-configuration/imxrt595evk.platform new file mode 100644 index 0000000..18f7697 --- /dev/null +++ b/microej/vee-port-configuration/imxrt595evk.platform @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/nxpvee-mimxrt595-evk-round-configuration/microui/microui.xml b/microej/vee-port-configuration/microui/microui.xml similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/microui/microui.xml rename to microej/vee-port-configuration/microui/microui.xml diff --git a/nxpvee-mimxrt595-evk-round-configuration/microui/resources/fonts/license.txt b/microej/vee-port-configuration/microui/resources/fonts/license.txt similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/microui/resources/fonts/license.txt rename to microej/vee-port-configuration/microui/resources/fonts/license.txt diff --git a/nxpvee-mimxrt595-evk-round-configuration/microui/resources/fonts/microej_system_font.ejf b/microej/vee-port-configuration/microui/resources/fonts/microej_system_font.ejf similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/microui/resources/fonts/microej_system_font.ejf rename to microej/vee-port-configuration/microui/resources/fonts/microej_system_font.ejf diff --git a/nxpvee-mimxrt595-evk-round-configuration/microvg/microvg.properties b/microej/vee-port-configuration/microvg/microvg.properties similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/microvg/microvg.properties rename to microej/vee-port-configuration/microvg/microvg.properties diff --git a/microej/vee-port-configuration/mjvm/mjvm.properties b/microej/vee-port-configuration/mjvm/mjvm.properties new file mode 100644 index 0000000..c85776f --- /dev/null +++ b/microej/vee-port-configuration/mjvm/mjvm.properties @@ -0,0 +1,7 @@ +# Copyright 2022, 2024 MicroEJ Corp. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be found with this software. + +sni.nonimmortal.access=true +# Select here the core engine capability: https://docs.microej.com/en/latest/VEEPortingGuide/coreEngine.html#capabilities +com.microej.runtime.capability=mono +#com.microej.runtime.capability=multi diff --git a/nxpvee-mimxrt595-evk-round-configuration/module.ant b/microej/vee-port-configuration/module.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/module.ant rename to microej/vee-port-configuration/module.ant diff --git a/microej/vee-port-configuration/module.ivy b/microej/vee-port-configuration/module.ivy new file mode 100644 index 0000000..5bca5cd --- /dev/null +++ b/microej/vee-port-configuration/module.ivy @@ -0,0 +1,81 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/nxpvee-mimxrt595-evk-round-configuration/module.properties b/microej/vee-port-configuration/module.properties similarity index 81% rename from nxpvee-mimxrt595-evk-round-configuration/module.properties rename to microej/vee-port-configuration/module.properties index 5347eee..9ad78d2 100644 --- a/nxpvee-mimxrt595-evk-round-configuration/module.properties +++ b/microej/vee-port-configuration/module.properties @@ -1,23 +1,17 @@ - # Copyright 2022-2023 MicroEJ Corp. All rights reserved. # Use of this source code is governed by a BSD-style license that can be found with this software. # This file is loaded by override.module.ant before loading module.ivy - # Set the platform architecture # GCC xpf.name=flopi4G25 xpf.toolchain.name=CM4hardfp_GCC48 -xpf.revision=7.20.1 +xpf.revision=8.1.1 # MicroEJ Architecture usage (Evaluation or Production). # Expected values: 'eval' (default) | 'prod' com.microej.platformbuilder.architecture.usage=eval -# Enable Multi-Sandbox capabilites -# Expected values: 'false' (default) | 'true' -com.microej.platformbuilder.module.multi.enabled=false - # Platform configuration file (relative to this project). com.microej.platformbuilder.platform.filename=imxrt595evk.platform diff --git a/nxpvee-mimxrt595-evk-round-configuration/override.module.ant b/microej/vee-port-configuration/override.module.ant similarity index 100% rename from nxpvee-mimxrt595-evk-round-configuration/override.module.ant rename to microej/vee-port-configuration/override.module.ant diff --git a/nxpvee-mimxrt595-evk-round-apps/launchers/AnimatedMascot (SIM).launch b/nxpvee-mimxrt595-evk-round-apps/launchers/AnimatedMascot (SIM).launch deleted file mode 100644 index 08480bc..0000000 --- a/nxpvee-mimxrt595-evk-round-apps/launchers/AnimatedMascot (SIM).launch +++ /dev/null @@ -1,91 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/nxpvee-mimxrt595-evk-round-apps/module.ant b/nxpvee-mimxrt595-evk-round-apps/module.ant deleted file mode 100644 index 6d0e67e..0000000 --- a/nxpvee-mimxrt595-evk-round-apps/module.ant +++ /dev/null @@ -1,7 +0,0 @@ - - - - - - - diff --git a/nxpvee-mimxrt595-evk-round-apps/module.ivy b/nxpvee-mimxrt595-evk-round-apps/module.ivy deleted file mode 100644 index 446bfec..0000000 --- a/nxpvee-mimxrt595-evk-round-apps/module.ivy +++ /dev/null @@ -1,52 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/nxpvee-mimxrt595-evk-round-apps/src/main/resources/com/nxp/animatedMascot/animatedMascot.vectorimages.list b/nxpvee-mimxrt595-evk-round-apps/src/main/resources/com/nxp/animatedMascot/animatedMascot.vectorimages.list deleted file mode 100644 index 70762bc..0000000 --- a/nxpvee-mimxrt595-evk-round-apps/src/main/resources/com/nxp/animatedMascot/animatedMascot.vectorimages.list +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: BSD-3-Clause -# - -/images/mascot.xml:VGF diff --git a/nxpvee-mimxrt595-evk-round-bsp/nvee_version.txt b/nxpvee-mimxrt595-evk-round-bsp/nvee_version.txt deleted file mode 100644 index 26aaba0..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/nvee_version.txt +++ /dev/null @@ -1 +0,0 @@ -1.2.0 diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/Makefile b/nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/Makefile deleted file mode 100644 index f8c8adc..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/common/sdk_makefile/Makefile +++ /dev/null @@ -1,100 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: BSD-3-Clause -# - -COMMON_PATH=../../common/sdk_makefile - -define del_file - $(if $(filter $(OS),Windows_NT),$(if $(wildcard $(1)),cmd /c DEL /f /q $(1),),rm -f $(1)) -endef - -define del_dir - $(if $(filter $(OS),Windows_NT),$(if $(wildcard $(1)),cmd /c RD /s /q $(subst /,\\,$(1)),),rm -fr $(1)) -endef - -ifeq ($(OS),Windows_NT) -JLINKEXE="$(JLINK_INSTALLATION_DIR)/Jlink.exe" -JLINK_GDB="$(COMMON_PATH)/debug/jlink_gdb.bat" -else -JLINKEXE=JLinkExe -JLINK_GDB="$(COMMON_PATH)"/debug/jlink_gdb.sh -endif - -JLINK_SCRIPT="jlink_flash.script" - -MAKE ?= make -OBJCOPY="$(ARMGCC_DIR)/bin/arm-none-eabi-objcopy" - - -ifeq ($(OS),Windows_NT) -GDB="$(ARMGCC_DIR)/bin/arm-none-eabi-gdb.exe" -NUM_PROC= -CLEAN_SCRIPT="./clean.bat" -else -GDB=gdb-multiarch -NUM_PROC=$(shell nproc) -CLEAN_SCRIPT="./clean.sh" -endif - -ifeq ($(MAKE),make) -MAKE_OP=-j$(NUM_PROC) -endif - -BUILD_DIR=../armgcc/$(FLAVOUR) - -all: ../armgcc/$(FLAVOUR) remake - -ifeq ($(OS),Windows_NT) -BUILD_SCRIPT="./build_$(FLAVOUR).bat" -CMSIS_GDB_TEMP_FOLDER="$(TEMP)"/gdb.cmd -else -BUILD_SCRIPT=./build_$(FLAVOUR).sh -CMSIS_GDB_TEMP_FOLDER=/tmp/gdb.cmd -endif - -../armgcc/$(FLAVOUR): - cd ../armgcc/ && $(BUILD_SCRIPT) $(MAKE) $(MAKE_OP) - -remake: - $(MAKE) $(MAKE_OP) -C ../armgcc/ - $(OBJCOPY) -Obinary "$(BUILD_DIR)/$(TARGET).elf" "$(BUILD_DIR)/$(TARGET).bin" - $(OBJCOPY) -Oihex "$(BUILD_DIR)/$(TARGET).elf" "$(BUILD_DIR)/$(TARGET).hex" - -clean: -ifneq ("$(wildcard $(../armgcc/Makefile))","") - $(MAKE) -C ../armgcc/ clean -endif - $(call del_dir,$(BUILD_DIR)) - -distclean: - cd ../armgcc/ && $(CLEAN_SCRIPT) - -flash: ../armgcc/$(FLAVOUR) remake - $(call del_file,$(JLINK_SCRIPT)) - echo r > $(JLINK_SCRIPT) - echo loadbin "$(BUILD_DIR)/$(TARGET).bin" $(ADDRESS) >> $(JLINK_SCRIPT) - echo r >> $(JLINK_SCRIPT) - echo g >> $(JLINK_SCRIPT) - echo qc >> $(JLINK_SCRIPT) - $(JLINKEXE) -NoGui 1 -device $(DEVICE) -If SWD -Speed 10000 -CommanderScript $(JLINK_SCRIPT) - $(call del_file,$(JLINK_SCRIPT)) - -flash_cmsisdap: ../armgcc/$(FLAVOUR) remake - crt_emu_cm_redlink --flash-load-exec $(BUILD_DIR)/$(TARGET).elf \ - -g --debug 2 --vendor NXP -p MIMXRT595S \ - -ProbeHandle=1 -CoreIndex=0 --flash-driver= \ - -x $(COMMON_PATH)/cmsisdap_support \ - --PreconnectScript LS_preconnect_MIMXRT500.scp \ - --flash-hashing - -gdb_cmsisdap: ../armgcc/$(FLAVOUR) remake - sed "s+FILE_VALUE+$(BUILD_DIR)/$(TARGET).elf+" $(COMMON_PATH)/cmsisdap_support/gdb.commands > $(CMSIS_GDB_TEMP_FOLDER) - $(GDB) --command=$(CMSIS_GDB_TEMP_FOLDER) - -gdb: ../armgcc/$(FLAVOUR) remake - $(JLINK_GDB) $(DEVICE) - $(GDB) --command=$(COMMON_PATH)/debug/jlink.gdb $(BUILD_DIR)/$(TARGET).elf - -.PHONY : all remake clean dist_clean gdb diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_freetype.properties b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_freetype.properties deleted file mode 100644 index 2e01b24..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_freetype.properties +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2022 MicroEJ Corp. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be found with this software. -#Wed, 22 Jun 2022 14:08:24 +0200 - -version=2.0.0 -buildLabel=20220622-1406 diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_microui-vglite.properties b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_microui-vglite.properties deleted file mode 100644 index 1a57e98..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_microui-vglite.properties +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2022 MicroEJ Corp. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be found with this software. -#Fri, 22 Jul 2022 06:53:23 +0200 - -version=3.0.0 -buildLabel=20220722-0653 diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_microui.properties b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_microui.properties deleted file mode 100644 index 5d31eab..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_microui.properties +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2022 MicroEJ Corp. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be found with this software. -#Fri, 22 Jul 2022 13:56:03 +0200 - -version=2.0.0 -buildLabel=20220722-1355 diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_microvg-vglite.properties b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_microvg-vglite.properties deleted file mode 100644 index 3fd8c99..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_microvg-vglite.properties +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2022 MicroEJ Corp. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be found with this software. -#Thu, 21 Jul 2022 16:38:02 +0200 - -version=3.0.0 -buildLabel=20220721-1637 diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_microvg.properties b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_microvg.properties deleted file mode 100644 index 92845b3..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/cco_microvg.properties +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2022 MicroEJ Corp. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be found with this software. -#Wed, 27 Jul 2022 06:07:24 +0200 - -version=2.0.0 -buildLabel=20220727-0607 diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/run.sh b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/run.sh deleted file mode 100755 index e2f06b8..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/scripts/run.sh +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/sh - -set -e -CURRENT_DIRECTORY=$(pwd) - -# go to directory of script's location -SCRIPT_DIR=$(dirname "$(realpath "$0")") - -cd "${SCRIPT_DIR}/../../nxpvee-ui/sdk_makefile/" -make RELEASE=1 flash_cmsisdap - -cd "$CURRENT_DIRECTORY" diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_base_wrapper.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_base_wrapper.c deleted file mode 100644 index 6883c5e..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_base_wrapper.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/** -* @file -* @brief MicroEJ Freetype wrapper on freetype c files -* @author MicroEJ Developer Team -* @version 2.0.0 -*/ - -#include "microvg_configuration.h" -#if defined (VG_FEATURE_FONT) - -#include "../ftbase.c" -#include "../ftinit.c" -#include "../autofit.c" -#include "../pshinter.c" -#include "../sfnt.c" -#include "../ftsystem/ftsystem.c" - -#endif // defined (VG_FEATURE_FONT) diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_bitmap_wrapper.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_bitmap_wrapper.c deleted file mode 100644 index 1b7e436..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_bitmap_wrapper.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/** -* @file -* @brief MicroEJ Freetype wrapper on freetype c files -* @author MicroEJ Developer Team -* @version 2.0.0 -*/ - -#include "microvg_configuration.h" - -#if defined (VG_FEATURE_FONT) && defined (VG_FEATURE_FONT_FREETYPE_BITMAP) && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_BITMAP) -#include "../ftsmooth.c" -#include "../ftgrays.c" -#include "../ftdebug.c" -#endif // defined (VG_FEATURE_FONT) && defined (VG_FEATURE_FONT_FREETYPE_BITMAP) && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_BITMAP) - diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_otf_wrapper.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_otf_wrapper.c deleted file mode 100644 index c82b310..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_otf_wrapper.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/** -* @file -* @brief MicroEJ Freetype wrapper on freetype c files -* @author MicroEJ Developer Team -* @version 2.0.0 -*/ - -#include "microvg_configuration.h" -#if defined (VG_FEATURE_FONT) - -#ifdef VG_FEATURE_FREETYPE_OTF -#include "../cff.c" -#include "../psaux.c" -#include "../psnames.c" -#endif // VG_FEATURE_FREETYPE_OTF - -#endif // defined (VG_FEATURE_FONT) diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_ttf_wrapper.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_ttf_wrapper.c deleted file mode 100644 index 39ab445..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_ttf_wrapper.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/** -* @file -* @brief MicroEJ Freetype wrapper on freetype c files -* @author MicroEJ Developer Team -* @version 2.0.0 -*/ - -#include "microvg_configuration.h" -#if defined (VG_FEATURE_FONT) - -#ifdef VG_FEATURE_FREETYPE_TTF -#include "../truetype.c" -#endif // VG_FEATURE_FREETYPE_TTF - -#endif // defined (VG_FEATURE_FONT) diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_vector_wrapper.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_vector_wrapper.c deleted file mode 100644 index 472752c..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/freetype/src/wrappers/ft_vector_wrapper.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/** -* @file -* @brief MicroEJ Freetype wrapper on freetype c files -* @author MicroEJ Developer Team -* @version 2.0.0 -*/ - -#include "microvg_configuration.h" - -#if defined (VG_FEATURE_FONT) && defined (VG_FEATURE_FONT_FREETYPE_VECTOR) && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_VECTOR) -#include "../ftvector/ftvector.c" -#endif // defined (VG_FEATURE_FONT) && defined (VG_FEATURE_FONT_FREETYPE_VECTOR) && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_VECTOR) diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/harfbuzz.a b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/harfbuzz.a deleted file mode 100644 index 5132540..0000000 Binary files a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/thirdparty/harfbuzz/lib/harfbuzz.a and /dev/null differ diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_configuration.h b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_configuration.h deleted file mode 100644 index 9fe1973..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_configuration.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * C - * - * Copyright 2019-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -#if !defined DISPLAY_CONFIGURATION_H -# define DISPLAY_CONFIGURATION_H - -#if defined __cplusplus -extern "C" { -#endif - -//#error "This header must be customized with platform specific configuration. Remove this #error when done. This file is not modified when a new version of the CCO is installed." - -/** - * @brief Compatibility sanity check value. - * This define value is checked in the implementation to validate that the version of this configuration - * is compatible with the implementation. - * - * This value must not be changed by the user of the CCO. - * This value must be incremented by the implementor of the CCO when a configuration define is added, deleted or modified. - */ -#define DISPLAY_CONFIGURATION_VERSION (1) - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -/* - * @brief Width of the display panel - */ -#define DISPLAY_PANEL_WIDTH (400) - -/* - * @brief Height of the display panel - */ -#define DISPLAY_PANEL_HEIGHT (392) - -/* - * @brief Width of the frame buffers - */ -#define FRAME_BUFFER_WIDTH (392) - -/* - * @brief Height of the frame buffers - */ -#define FRAME_BUFFER_HEIGHT (392) - -/* - * @brief Source image line alignment (in bytes), required by VGLite library - * when an image is used as source: 32 bits for RGB565 format - * (see _check_source_aligned() in vg_lite.c). - */ -#define VGLITE_IMAGE_LINE_ALIGN_BYTE (32) - -/* - * @brief Frame buffer line alignment (in bytes), required by VGLite library - * when frame buffer is used as source. - * Note: Set (1) to not use the frame buffer as source image. - * Note 2: Require a patch in fsl_dc_fb_dsi_cmd.c - */ -#define FRAME_BUFFER_LINE_ALIGN_BYTE (1) /* 1 | VGLITE_IMAGE_LINE_ALIGN_BYTE */ - -/* - * @brief Available number of frame buffers - */ -#define FRAME_BUFFER_COUNT (2) - -/* - * @brief GPU is less efficient than CPU to perform simple aliased drawings (line, rectangle etc.) - * - * This define forces to use the GPU. Comment it to use the software algorithms instead. - */ -//#define VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS - -/* - * @brief GPU is less efficient than CPU to perform a simple "draw image": when the image to render has - * the same pixel definition than the destination buffer and no alpha blending is required. - * - * This defines forces to use the GPU to draw RGB565 images. Comment it to use the software algorithms - * instead. - */ -//#define VGLITE_USE_GPU_FOR_RGB565_IMAGES - -/* - * @brief GCNanoLite-V does not support MSAA. By consequence the "draw image" functions (with or without - * transformation like rotation or scale) cannot use GPU when the image to render contains transparent - * pixels. - * - * This defines forces to use the GPU to draw transparent images. Comment it to use the software algorithms - * instead. - */ -//#define VGLITE_USE_GPU_FOR_TRANSPARENT_IMAGES - -/* - * @brief Option to enable and disable the use of the GPU (toggle) at runtime. When the option is disabled, - * the calls to DISPLAY_VGLITE_xxx_hardware_rendering have no effect. - * - * This defines forces to enable the option. Comment it to disable the option. - */ -//#define VGLITE_OPTION_TOGGLE_GPU - -/* - * @brief The multiple drawers option allows to use a specific drawer according to the MicroUI destination format. - * (see LLUI_DISPLAY_isCustomFormat()). - * - * When disabled, all drawings are performed in software (by the Graphics Engine) or by the VG-Lite library (GPU). - * In that case, all drawings are directly mapped on VG-Lite APIs to prevent useless indirections and performance - * loss. - * - * When enabled and the destination format is custom, the platform has the responsability to redirect the drawings - * to the expected drawer by overriding the default implementation of VG_DRAWER_get_drawer(). Note that the Graphics - * Engine software algorithms don't manage the custom formats (no check). - * - * The drawing's callers should call vg_drawer.h APIs that check this option and redirect or not the drawings to - * the registered drawer(s). - */ -//#define VGLITE_USE_MULTIPLE_DRAWERS - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#ifdef __cplusplus -} -#endif - -#endif // !defined DISPLAY_CONFIGURATION_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_dma.h b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_dma.h deleted file mode 100644 index eb19821..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_dma.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * C - * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -#if !defined DISPLAY_DMA_H -# define DISPLAY_DMA_H - -#if defined __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include "display_framebuffer.h" - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -#define DISPLAY_DMA_ENABLED ( FRAME_BUFFER_COUNT > 1 ) - -// ----------------------------------------------------------------------------- -// API -// ----------------------------------------------------------------------------- - -/* - * @brief: Initialize the DMA synchronization between the framebuffers - * - * @param[in] framebuffers: display framebuffers - */ -void DISPLAY_DMA_initialize(const framebuffer_t * framebuffers[]); - -/* - * @brief: Starts a DMA transfert - * - * @param[in] src: source framebuffer - * @param[in] dst: destination framebuffer - * @param[in] ymin: first line to transfert - * @param[in] ymax: last line to transfert + 1 - */ -void DISPLAY_DMA_start(framebuffer_t *src, framebuffer_t *dst, int ymin, int ymax); - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#ifdef __cplusplus -} -#endif - -#endif // !defined DISPLAY_DMA_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_framebuffer.h b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_framebuffer.h deleted file mode 100644 index 8f87c36..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_framebuffer.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * C - * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -#if !defined DISPLAY_FRAMEBUFFER_H -#define DISPLAY_FRAMEBUFFER_H - -#if defined __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include - -#include "display_configuration.h" - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -/* - * @brief Available number of bytes per pixels (RGB565) - */ -#define FRAME_BUFFER_BYTE_PER_PIXEL (2) - -/* - * @brief Frame buffer alignment. - * - 4 bits are required by SMARTDMA - * - 64 bits are required by DMA - * Note: Full frame buffer memory size is a value aligned on 64 too; - * so next allocation behind frame buffer memory is aligned on 64 too. - */ -#define FRAME_BUFFER_ALIGN (64) - -/* - * @brief Macro to align data - */ -#define ALIGN(value, align) (((value) + (align) - 1) & ~((align) - 1)) - -/* - * @brief Frame buffer line size in bytes (stride), according to FRAME_BUFFER_LINE_ALIGN - */ -#define FRAME_BUFFER_STRIDE_BYTE ALIGN(FRAME_BUFFER_WIDTH * FRAME_BUFFER_BYTE_PER_PIXEL, FRAME_BUFFER_LINE_ALIGN_BYTE) - -/* - * @brief Frame buffer line size in pixels (stride), according to FRAME_BUFFER_LINE_ALIGN - */ -#define FRAME_BUFFER_STRIDE_PIXELS (FRAME_BUFFER_STRIDE_BYTE / FRAME_BUFFER_BYTE_PER_PIXEL) - -// ----------------------------------------------------------------------------- -// Types -// ----------------------------------------------------------------------------- - -/* - * @brief Frame buffer structure definition - */ -typedef struct s_framebuffer { - uint16_t p[FRAME_BUFFER_HEIGHT][FRAME_BUFFER_STRIDE_PIXELS]; -} framebuffer_t; - -// ----------------------------------------------------------------------------- -// Variables -// ----------------------------------------------------------------------------- - -/* - * @brief Frame buffer address array - */ -extern const framebuffer_t * s_frameBufferAddress[FRAME_BUFFER_COUNT]; - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#ifdef __cplusplus -} -#endif - -#endif // !defined DISPLAY_FRAMEBUFFER_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_impl.h b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_impl.h deleted file mode 100644 index cb36ac5..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_impl.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - * - * @brief This file lists a set of functions called by the display*.c files. First functions - * are mandatory; optional functions are listed in a second time. - * - * These functions are - * optional and a stub implementation is already available in the CCO (see display_stub.c). - */ - -#if !defined DISPLAY_IMPL_H -# define DISPLAY_IMPL_H - -#if defined __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include -#include - -#include "display_framebuffer.h" - -// -------------------------------------------------------------------------------- -// Functions that must be implemented -// -------------------------------------------------------------------------------- - -/* - * Same signature than interrupts.h - */ -uint8_t interrupt_enter(void); - -/* - * Same signature than interrupts.h - */ -void interrupt_leave(uint8_t leave); - -/* - * Same signature than interrupts.h - */ -uint8_t interrupt_is_in(void); - -// -------------------------------------------------------------------------------- -// Optional functions to implement -// -------------------------------------------------------------------------------- - -/* - * @brief Notifies the LLUI_DISPLAY_IMPL is initialized. The implementation can - * initialize 3rd-party elements. - */ -void DISPLAY_IMPL_initialized(void); - -/* - * @brief Notifies an error has occurred. This error may be critical, in this case, - * the implementation must stop the application execution (message + infinite loop). - * - * @param[in] critical: tell whether the error is critical or not. - * @param[in] format: the error message and its arguments - */ -void DISPLAY_IMPL_error(bool critical, const char* format, ...); - -/* - * @brief Notifies the GPU will be used just after this call. The implementation - * must ensure the GPU can be used (power management, clocks, etc.). - */ -void DISPLAY_IMPL_notify_gpu_start(void); - -/* - * @brief Notifies the GPU is not used anymore by the library until next call to - * DISPLAY_IMPL_notify_gpu_start(). - */ -void DISPLAY_IMPL_notify_gpu_stop(void); - -/* - * @brief Notifies the DMA will be used just after this call. The implementation - * must ensure the DMA can be used (power management, clocks, etc.). - */ -void DISPLAY_IMPL_notify_dma_start(void); - -/* - * @brief Notifies the DMA is not used anymore by the library until next call to - * DISPLAY_IMPL_notify_dma_start(). - */ -void DISPLAY_IMPL_notify_dma_stop(void); - -/* - * @brief Notifies the first frame buffer will be used just after this call and - * the second frame buffer will not used anymore until next call to - * DISPLAY_IMPL_update_frame_buffer_status(). - * - * @param[in] frame_buffer_on: the frame buffer that will be used - * @param[in] frame_buffer_off: the frame buffer that not used anymore - */ -void DISPLAY_IMPL_update_frame_buffer_status(framebuffer_t* frame_buffer_on, framebuffer_t* frame_buffer_off); - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#ifdef __cplusplus -} -#endif - -#endif // !defined DISPLAY_IMPL_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_utils.h b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_utils.h deleted file mode 100644 index c242267..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_utils.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * C - * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -#if !defined DISPLAY_UTILS_H -#define DISPLAY_UTILS_H - -#if defined __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -/* - * @brief Unknown resource format - */ -#define DISPLAY_UNKNOWN_FORMAT -1 - -// ----------------------------------------------------------------------------- -// API -// ----------------------------------------------------------------------------- - -/* - * @brief Returns the bit per pixel from a MicroUI image format - * - * @param[in] image_format: The MicroUI format of the image - * - * @return The bit per pixel of the image, or -1 if the image format is unknown - */ -int32_t DISPLAY_UTILS_get_bpp(MICROUI_ImageFormat image_format); - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#ifdef __cplusplus -} -#endif - -#endif // !defined DISPLAY_UTILS_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_vglite.h b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_vglite.h deleted file mode 100644 index 546988d..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/display_vglite.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * C - * - * Copyright 2019-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -#if !defined DISPLAY_VGLITE_H -#define DISPLAY_VGLITE_H - -#if defined __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include - -#include "vglite_window.h" - -// ----------------------------------------------------------------------------- -// API -// ----------------------------------------------------------------------------- - -/* - * @brief Flush the GPU operations. - * - * @param[in] wakeup_graphics_engine: true to wakeup the graphics engine as soon as - * the drawing is performed, false to perform an active waiting until the GPU interrupt - * is thrown - */ -void DISPLAY_VGLITE_start_operation(bool wakeup_graphics_engine); - -/* - * @brief Enables hardware rendering - * @see VGLITE_OPTION_TOGGLE_GPU - */ -void DISPLAY_VGLITE_enable_hardware_rendering(void); - -/* - * @brief Disables hardware rendering - * @see VGLITE_OPTION_TOGGLE_GPU - */ -void DISPLAY_VGLITE_disable_hardware_rendering(void); - -/* - * @brief Checks if hardware rendering is enabled - * - * @return: true if hardware rendering is enabled, false otherwise - * @see VGLITE_OPTION_TOGGLE_GPU - */ -bool DISPLAY_VGLITE_is_hardware_rendering_enabled(void); - -/* - * @brief Toggles hardware rendering - * @see VGLITE_OPTION_TOGGLE_GPU - */ -void DISPLAY_VGLITE_toggle_hardware_rendering(void); - -/* - * @brief Create display, window contexes and initialize the VGLite library - */ -void DISPLAY_VGLITE_init(void); - -/* - * @brief Get the main VGLite window - */ -vg_lite_window_t* DISPLAY_VGLITE_get_window(void); - -/* - * @brief Get the next graphics buffer to use - */ -vg_lite_buffer_t *DISPLAY_VGLITE_get_next_graphics_buffer(void); - -/* - * Because of VGLite library implementation, - * a buffer located at the same address should not be modified and reused - * as the VGLite library check if the buffer address match with the one - * stored in its context. If matching is successfull, render target will not - * be updated. - * This function rotate over an array of vg_lite_buffers to give a different - * buffer address at each call and configures it from a MICROUI_Image. - * The caller MUST send it to the vg_lite library to update its context. - * - * @param[in] gc: graphics context of destination - * - * @return a vg_lite buffer that should not match vg_lite library render context - */ -vg_lite_buffer_t* DISPLAY_VGLITE_configure_destination(MICROUI_GraphicsContext* gc); - -/* - * This function configures a source buffer from a MICROUI_Image. - * - * @param[in] buffer: source buffer - * @param[in] image: source image - * - * @return false if source image format is not supported by vg_lite, true on success - */ -bool DISPLAY_VGLITE_configure_source(vg_lite_buffer_t *buffer, MICROUI_Image* image); - -/* - * @brief RT595 Porter-Duff operators seems to not be functional - * When using transparency, the colors passed to the RT595 - * need to be modifed to display the correct colors. - * This modification also has an impact on the front-panel - * that needs to be fixed. - * - * Note: This has been tested on SRC_OVER only. - * - * @param[in] color: the color in ARGB8888 format to convert - * @return the converted color int ARGB8888 format - */ -uint32_t DISPLAY_VGLITE_porter_duff_workaround_ARGB8888(uint32_t color); - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#ifdef __cplusplus -} -#endif - -#endif // !defined DISPLAY_VGLITE_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/framerate_conf.h b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/framerate_conf.h deleted file mode 100644 index adddcac..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/framerate_conf.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * C - * - * Copyright 2014-2020 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ -#if !defined FRAMERATE_CONF_H -#define FRAMERATE_CONF_H - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -/* - * @brief Change value to disable/enable the framerate monitoring: - * 0: Disables the framerate monitoring - * 1: Enables the framerate monitoring - */ -#define FRAMERATE_ENABLED 1 - -#endif // !defined FRAMERATE_CONF_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/trace_vglite.h b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/trace_vglite.h deleted file mode 100644 index 507e413..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/trace_vglite.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * C - * - * Copyright 2020-2021 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -#if !defined TRACE_VGLITE_H -#define TRACE_VGLITE_H - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include "trace_platform.h" - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -/* - * @brief Logs an init gpu start event - * - * @param[in] operation: The VGLite operation sent to the GPU - */ -#define TRACE_VGLITE_INIT_GPU_START(operation) \ - TRACE_PLATFORM_START_U32( \ - VGLITE, \ - TRACE_VGLITE_INIT_GPU, \ - TRACE_VGLITE_OP_ ## operation \ - ); - -/* - * @brief Logs an init gpu end event - */ -#define TRACE_VGLITE_INIT_GPU_END() \ - TRACE_PLATFORM_END_VOID( \ - VGLITE, \ - TRACE_VGLITE_INIT_GPU \ - ); - -/* - * @brief INIT_GPU event identifier - */ -#define TRACE_VGLITE_INIT_GPU 1 - -/* - * @brief VGLite operation CLEAR identifier - * This event is expected to be used to trace a call to vg_lite_clear - */ -#define TRACE_VGLITE_OP_CLEAR 1 - -/* - * @brief VGLite operation DRAW (draw path) identifier - * This event is expected to be used to trace a call to vg_lite_draw - */ -#define TRACE_VGLITE_OP_DRAW 2 - -/* - * @brief VGLite operation DRAW_GRAD (draw path with gradient) identifier - * This event is expected to be used to trace a call to vg_lite_draw_grad - */ -#define TRACE_VGLITE_OP_DRAW_GRAD 3 - -/* - * @brief VGLite operation BLIT (draw image) identifier - * This event is expected to be used to trace a call to vg_lite_blit - */ -#define TRACE_VGLITE_OP_BLIT 4 - -/* - * @brief VGLite operation BLIT_RECT (draw image area) identifier - * This event is expected to be used to trace a call to vg_lite_blit_rect - */ -#define TRACE_VGLITE_OP_BLIT_RECT 5 - -/* - * Trace start macros - * - * param[in] event: LLVGLITE Event to trace - */ -#define __TRACE_START(event) \ - TRACE_PLATFORM_START_VOID(LLVGLITE, LLVGLITE_TRACE_ ## event) - -/* - * Trace end macros - * - * param[in] event: LLVGLITE Event to trace - */ -#define __TRACE_END(event) \ - TRACE_PLATFORM_END_VOID(LLVGLITE, LLVGLITE_TRACE_ ## event); - -/* - * @brief Low Level VGLite API DRAW (draw path) identifier - * This event is expected to be used to trace a call to the java API - * vg_lite_draw - */ -#define LLVGLITE_TRACE_DRAW (10 + TRACE_VGLITE_OP_DRAW) - -/* - * @brief VLow Level VGLite API DRAW_GRAD (draw path with gradient) identifier - * This event is expected to be used to trace a call to the java API - * vg_lite_draw_grad - */ -#define LLVGLITE_TRACE_DRAW_GRAD (10 + TRACE_VGLITE_OP_DRAW_GRAD) - -/* - * @brief VLow Level VGLite API MATRIX_IDENTITY (set matrix to identity) - * identifier - * This event is expected to be used to trace a call to the java API - * vg_lite_matrix_identity - */ -#define LLVGLITE_TRACE_MATRIX_IDENTITY 21 - -/* - * @brief VLow Level VGLite API MATRIX_TRANSLATE (update matrix for translation) - * identifier - * This event is expected to be used to trace a call to the java API - * vg_lite_matrix_translate - */ -#define LLVGLITE_TRACE_MATRIX_TRANSLATE 22 - -/* - * @brief VLow Level VGLite API MATRIX_TRANSLATE (update matrix for rotation) - * identifier - * This event is expected to be used to trace a call to the java API - * vg_lite_matrix_rotate - */ -#define LLVGLITE_TRACE_MATRIX_ROTATE 23 - -/* - * @brief VLow Level VGLite API MATRIX_TRANSLATE (update matrix for scale) - * identifier - * This event is expected to be used to trace a call to the java API - * vg_lite_matrix_scale - */ -#define LLVGLITE_TRACE_MATRIX_SCALE 24 - -/* - * @brief VLow Level VGLite API MATRIX_PERPECTIVE - * identifier - * This event is expected to be used to trace a call to the java API - * vg_lite_matrix_perspective - */ -#define LLVGLITE_TRACE_MATRIX_PERSPECTIVE 25 - -/* - * @brief VLow Level VGLite API MATRIX_COPY (copy matrix parameters from an other matrix) - * identifier - * This event is expected to be used to trace a call to the java API - * vg_lite_matrix_copy - */ -#define LLVGLITE_TRACE_MATRIX_COPY 26 - -/* - * @brief VLow Level VGLite API MATRIX_COPY (copy matrix parameters from an other matrix) - * identifier - * This event is expected to be used to trace a call to the java API - * vg_lite_matrix_copy - */ -#define LLVGLITE_TRACE_MATRIX_CONCATENATE 27 - -#endif // !defined TRACE_VGLITE_H - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - - diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/vg_drawer.h b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/vg_drawer.h deleted file mode 100644 index 1a61e6b..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/vg_drawer.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief Indirection of vector drawings to VG-Lite library or to a specific drawer. - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -#if !defined VG_DRAWER_H -#define VG_DRAWER_H - -#if defined __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include - -#include "display_configuration.h" -#include "mej_math.h" - -#include "vg_lite.h" - -// ----------------------------------------------------------------------------- -// Types -// ----------------------------------------------------------------------------- - -/* - * @brief Function to update a color according to the drawer implementation. - * - * @param[in/out]: color: pointer to the color to update - * @param[in]: blend: the blending mode to apply - * - * @return: nothing - */ -typedef void (* VG_DRAWER_update_color_t) ( - vg_lite_color_t* color, - vg_lite_blend_t blend); - -/* - * @brief Function to update a gradient according to the drawer implementation. - * - * @param[in]: gradient: pointer to the gradient to update - * @param[in]: blend: the blending mode to apply - * - * @return: nothing - */ -typedef void (* VG_DRAWER_update_gradient_t) ( - vg_lite_linear_gradient_t* gradient, - vg_lite_blend_t blend); - -/* - * @brief Function to draw a path according to the drawer implementation. - * - * @see vg_lite_draw() - * - * @param[in]: target: the target used by the drawer implementation - * - * @return: the vglite error code - */ -typedef vg_lite_error_t (* VG_DRAWER_draw_path_t) ( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color); - -/* - * @brief Function to draw a path with gradient according to the drawer implementation. - * - * @see vg_lite_draw_gradient() - * - * @param[in]: target: the target used by the drawer implementation - * - * @return: the vglite error code - */ -typedef vg_lite_error_t (* VG_DRAWER_draw_gradient_t)( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_linear_gradient_t * grad, - vg_lite_blend_t blend); - -/* - * @brief Function to blit a part of the source according to the drawer implementation. - * - * @see vg_lite_blit_rect() - * - * @param[in]: target: the target used by the drawer implementation - * - * @return: the vglite error code - */ -typedef vg_lite_error_t (* VG_DRAWER_blit_rect_t)( - void* target, - vg_lite_buffer_t *source, - uint32_t *rect, - vg_lite_matrix_t *matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter); - -/* - * @brief Function to blit the source according to the drawer implementation. - * - * @see vg_lite_blit() - * - * @param[in]: target: the target used by the drawer implementation - * - * @return: the vglite error code - */ -typedef vg_lite_error_t (* VG_DRAWER_blit_t)( - void* target, - vg_lite_buffer_t * source, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter); - -/* - * @brief Function to clear a rectangle according to the drawer implementation. - * - * @see vg_lite_clear() - * - * @param[in]: target: the target used by the drawer implementation - * - * @return: the vglite error code - */ -typedef vg_lite_error_t (* VG_DRAWER_clear_t)( - void* target, - vg_lite_rectangle_t *rectangle, - vg_lite_color_t color); - -/* - * @brief Operation to perform after a drawing operation. - * - * @param[in] vg_lite_error: the drawing operation's return code. - * - * @return: the MicroUI status according to the drawing operation status. - * - */ -typedef DRAWING_Status (* VG_DRAWER_post_operation_t)(vg_lite_error_t vg_lite_error) ; - -/* - * @brief Defines a drawer - */ -typedef struct VG_DRAWER_drawer { - - /* - * @brief Draws a path using the drawer. - */ - VG_DRAWER_draw_path_t draw_path; - - /* - * @brief Draws a path with gradient using the drawer. - */ - VG_DRAWER_draw_gradient_t draw_gradient; - - /* - * @brief Blits a rectangle using the drawer. - */ - VG_DRAWER_blit_rect_t blit_rect; - - /* - * @brief Blits an image using the drawer. - */ - VG_DRAWER_blit_t blit; - - /* - * @brief Clears a rectangle using the drawer. - */ - VG_DRAWER_clear_t clear; - - /* - * @brief Updates a color according to the drawer implementation. Useful to update - * the color only once for several calls to drawing operations. - */ - VG_DRAWER_update_color_t update_color; - - /* - * @brief Updates a gradient according to the drawer implementation. Useful to update - * the gradient only once for several calls to drawing operations. - */ - VG_DRAWER_update_gradient_t update_gradient; - - /* - * @brief Performs a post operation after any drawings. - */ - VG_DRAWER_post_operation_t post_operation; - - /* - * @brief Used by the drawer to identify the destination (depends on drawer). - */ - void* target; - -} VG_DRAWER_drawer_t; - -// ----------------------------------------------------------------------------- -// API -// ----------------------------------------------------------------------------- - -/* - * @brief Gets the default drawer to use. The default drawer is the vglite drawer - * (see VGLITE_PATH_get_vglite_drawer()). This drawer may be overrided by the - * platform implementation. - * - * @see VGLITE_PATH_get_vglite_drawer() - * - * @return a drawer - */ -VG_DRAWER_drawer_t* VG_DRAWER_get_drawer(MICROUI_GraphicsContext* gc); - -/* - * @brief Configures and returns the target according to the MicroUI destination. - * The target can be the destination buffer or a drawer that will execute the - * drawings. - * - * @return: the target (a buffer or a drawer) - */ -void* VG_DRAWER_configure_target(MICROUI_GraphicsContext* gc) ; - -/* - * @brief Function to update a color to be compatible with the target. - * - * @param[in/out]: color: pointer to the color to update - * @param[in]: blend: the blending mode to apply - * - * @return: nothing - */ -void VG_DRAWER_update_color(void* target, vg_lite_color_t* color, vg_lite_blend_t blend) ; - -/* - * @brief Function to update a gradient to be compatible with the target. - * - * @param[in/out]: color: pointer to the color to update - * @param[in]: blend: the blending mode to apply - * - * @return: nothing - */ -void VG_DRAWER_update_gradient(void* target, vg_lite_linear_gradient_t* gradient, vg_lite_blend_t blend) ; - -/* - * @brief Draws a path in the target or using the target as drawer. - * - * @param[in] target the destination or a drawer - * other parameters: @see vg_lite_draw - * - * @return the VG-Lite error code. - */ -vg_lite_error_t VG_DRAWER_draw_path( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color); - -/* - * @brief Draws a path with gradient in the target or using the target as drawer. - * - * @param[in] target the destination or a drawer - * other parameters: @see vg_lite_draw_gradient - * - * @return the VG-Lite error code. - */ -vg_lite_error_t VG_DRAWER_draw_gradient( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_linear_gradient_t * grad, - vg_lite_blend_t blend); - -/* - * @brief Blits a rectangle in the target or using the target as drawer. - * - * @param[in] target the destination or a drawer - * other parameters: @see vg_lite_blit_rect - * - * @return the VG-Lite error code. - */ -vg_lite_error_t VG_DRAWER_blit_rect( - void* target, - vg_lite_buffer_t *source, - uint32_t *rect, - vg_lite_matrix_t *matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter); - -/* - * @brief Blits an image in the target or using the target as drawer. - * - * @param[in] target the destination or a drawer - * other parameters: @see vg_lite_blit - * - * @return the VG-Lite error code. - */ -vg_lite_error_t VG_DRAWER_blit( - void* target, - vg_lite_buffer_t * source, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter); - -/* - * @brief Clears a rectangle in the target or using the target as drawer. - * - * @param[in] target the destination or a drawer - * other parameters: @see vg_lite_clear - * - * @return the VG-Lite error code. - */ -vg_lite_error_t VG_DRAWER_clear( - void* target, - vg_lite_rectangle_t *rectangle, - vg_lite_color_t color); - -/* - * @brief Operation to perform after a drawing operation. - * - * @param[in] target: the destination or a drawer - * @param[in] vg_lite_error: the drawing operation's return code. - * - * @return: the MicroUI status according to the drawing operation status. - */ -DRAWING_Status VG_DRAWER_post_operation(void* target, vg_lite_error_t vg_lite_error) ; - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#ifdef __cplusplus -} -#endif - -#endif // !defined VG_DRAWER_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/vglite_path.h b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/vglite_path.h deleted file mode 100644 index dea8b0c..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/inc/vglite_path.h +++ /dev/null @@ -1,515 +0,0 @@ -/* - * C - * - * Copyright 2019-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -#if !defined VGLITE_PATH_H -#define VGLITE_PATH_H - -#if defined __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include -#include -#include - -#include "mej_math.h" - -#include "vg_lite.h" -#include "vg_drawer.h" - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -#define VGLITE_END_CMD 0 -#define VGLITE_MOVE_CMD 2 -#define VGLITE_LINE_CMD 4 -#define VGLITE_CUBIC_CMD 8 - -/* - * @brief Length of a VGLite line path - */ -#define MEJ_VGLITE_PATH_LINE_LENGTH(t) \ - (0 \ - + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ - + 6 * MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) /* line have 6 sides */ \ - + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ - ) - -/* - * @brief Length of a VGLite thick shape line path - */ -#define MEJ_VGLITE_PATH_THICK_SHAPE_LINE_LENGTH(t) \ - (0 \ - + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ - + 2 * MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) /* line have 6 sides */ \ - + 2 * MEJ_MAX( MEJ_VGLITE_PATH_ROUNDED_CAP_LENGTH(t), \ - MEJ_VGLITE_PATH_NO_CAP_LENGTH(t)) /* CAPS */ \ - + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ - ) - -/* - * @brief Length of a VGLite ellipse path - */ -#define MEJ_VGLITE_PATH_CIRCLE_LENGTH(t) \ - (0 \ - + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ - + 4 * MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(t) /* 4 sections per ellipse */ \ - + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ - ) - -/* - * @brief Length of a VGLite ellipse path - */ -#define MEJ_VGLITE_PATH_CIRCLE_ARC_OUTLINE_MAX_LENGTH(t) \ - (0 \ - + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ - + 2 * MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) /* 2 ends */ \ - + 8 * MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(t) /* 4 sections per ellipse */ \ - + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ - ) - -/* - * @brief Length of a VGLite filled rectangle path - */ -#define MEJ_VGLITE_PATH_RECT_LENGTH(t) \ - (0 \ - + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ - + 4 * MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) /* 4 sides */ \ - + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ - ) - -/* - * @brief Length of a VGLite filled rounded rectangle path - */ -#define MEJ_VGLITE_PATH_ROUND_RECT_LENGTH(t) \ - (0 \ - + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ - + 4 * MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) /* 4 sides */ \ - + 4 * MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(t) /* 4 corners */ \ - + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ - ) - -/* - * @brief Maximum length of a VGLite filled ellipse arc path - */ -#define MEJ_VGLITE_PATH_CIRCLE_ARC_MAX_LENGTH(t) \ - (0 \ - + 1 * MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) /* move to command */ \ - + 2 * MEJ_MAX( MEJ_VGLITE_PATH_ROUNDED_CAP_LENGTH(t), \ - MEJ_VGLITE_PATH_NO_CAP_LENGTH(t)) /* CAPS */ \ - + 8 * MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(t) /* Up to 4 sections per curve in and out */ \ - + 1 * MEJ_VGLITE_PATH_END_LENGTH(t) /* end command */ \ - ) - -/* - * @brief Size of a rounded cap: 2 cubic curves - */ -#define MEJ_VGLITE_PATH_ROUNDED_CAP_LENGTH(t) (2 * MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(t)) - -/* - * @brief Size of a "no cap": 1 line - */ -#define MEJ_VGLITE_PATH_NO_CAP_LENGTH(t) MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) - -/* - * @brief Size of a move_to command - */ -#define MEJ_VGLITE_PATH_MOVE_TO_LENGTH(t) (sizeof(path_move_to_ ## t)) - -/* - * @brief Size of a line_to command - */ -#define MEJ_VGLITE_PATH_LINE_TO_LENGTH(t) (sizeof(path_line_to_ ## t)) - -/* - * @brief Size of a cubic_to command - */ -#define MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(t) (sizeof(path_cubic_to_ ## t)) - -/* - * @brief Size of a end command - */ -#define MEJ_VGLITE_PATH_END_LENGTH(t) (sizeof(path_end_ ## t)) - -/* - * @brief Position of the starting cap in the caps bitfield - */ -#define MEJ_VGLITE_PATH_CAPS_START_SHIFT 0 - -/* - * @brief Position of the ending cap in the caps bitfield - */ -#define MEJ_VGLITE_PATH_CAPS_END_SHIFT 2 - -/* - * @brief Mask of a cap in the caps bitfield - */ -#define MEJ_VGLITE_PATH_CAPS_MASK 0x03 - -/* - * @brief Sets the starting cap in the bitfield - */ -#define MEJ_VGLITE_PATH_SET_CAPS_START(x) (((x) & MEJ_VGLITE_PATH_CAPS_MASK) << MEJ_VGLITE_PATH_CAPS_START_SHIFT) - -/* - * @brief Sets the ending cap in the bitfield - */ -#define MEJ_VGLITE_PATH_SET_CAPS_END(x) (((x) & MEJ_VGLITE_PATH_CAPS_MASK) << MEJ_VGLITE_PATH_CAPS_END_SHIFT) - -/* - * @brief Gets the starting cap from the bitfield - */ -#define MEJ_VGLITE_PATH_GET_CAPS_START(x) (((x) >> MEJ_VGLITE_PATH_CAPS_START_SHIFT) & MEJ_VGLITE_PATH_CAPS_MASK) - -/* - * @brief Gets the ending cap from the bitfield - */ -#define MEJ_VGLITE_PATH_GET_CAPS_END(x) (((x) >> MEJ_VGLITE_PATH_CAPS_END_SHIFT) & MEJ_VGLITE_PATH_CAPS_MASK) - -// ----------------------------------------------------------------------------- -// Types -// ----------------------------------------------------------------------------- - -/* - * @brief VGLite S16 move to command - */ -typedef struct path_move_to_s16 { - int16_t cmd; // @brief Command - int16_t x; // @brief Horizontal coordinate of the position to move to - int16_t y; // @brief Vertical coordinate of the position to move to -} path_move_to_s16_t; - -/* - * @brief VGLite S16 line to command - */ -typedef struct path_line_s16 { - int16_t cmd; // @brief Command - int16_t x; // @brief Horizontal coordinate of the position to move to - int16_t y; // @brief Vertical coordinate of the position to move to -} path_line_to_s16_t; - -/* - * @brief VGLite S16 cubic to command - */ -typedef struct path_cubic_s16 { - int16_t cmd; // @brief command - int16_t cx1; // @brief Horizontal coordinate of the first control point - int16_t cy1; // @brief Vertical coordinate of the first control point - int16_t cx2; // @brief Horizontal coordinate of the second control point - int16_t cy2; // @brief Vertical coordinate of the second control point - int16_t x; // @brief Horizontal coordinate of the end of the curve - int16_t y; // @brief Vertical coordinate of the end of the curve -} path_cubic_to_s16_t; - -/* - * @brief VGLite S16 end command - */ -typedef struct path_end_s16 { - int16_t cmd; // @brief command -} path_end_s16_t; - -/* - * @brief Fixed array size to store a line path - */ -typedef uint8_t vglite_path_line_t[MEJ_VGLITE_PATH_LINE_LENGTH(s16_t)]; - -/* - * @brief Fixed array size to store a thick shape line path - */ -typedef uint8_t vglite_path_thick_shape_line_t[MEJ_VGLITE_PATH_THICK_SHAPE_LINE_LENGTH(s16_t)]; - -/* - * @brief Fixed array size to store a ellipse - */ -typedef uint8_t vglite_path_ellipse_t[MEJ_VGLITE_PATH_CIRCLE_LENGTH(s16_t)]; - -/* - * @brief Fixed array size to store a ellipse arc - */ -typedef uint8_t vglite_path_ellipse_arc_t[MEJ_VGLITE_PATH_CIRCLE_ARC_OUTLINE_MAX_LENGTH(s16_t)]; - -/* - * @brief Fixed array size to store a rectangle path - */ -typedef uint8_t vglite_path_rectangle_t[MEJ_VGLITE_PATH_RECT_LENGTH(s16_t)]; - -/* - * @brief Fixed array size to store a line path - */ -typedef uint8_t vglite_path_rounded_rectangle_t[MEJ_VGLITE_PATH_ROUND_RECT_LENGTH(s16_t)]; - -/* - * @brief Fixed array size to store a thick ellipse arc path - */ -typedef uint8_t vglite_path_thick_ellipse_arc_t[MEJ_VGLITE_PATH_CIRCLE_ARC_MAX_LENGTH(s16_t)]; - -// ----------------------------------------------------------------------------- -// API -// ----------------------------------------------------------------------------- - -/* - * @brief Computes a ellipse arc - * - * This function uses bezier curves to apporoximate the ellipse arcs - * The path computed by this function is intended to be used with VGLite - * The function supports the followin caps: DRAWING_ENDOFLINE_NONE and DRAWING_ENDOFLINE_ROUNDED. - * DRAWING_ENDOFLINE_PERPENDICULAR is considered as DRAWING_ENDOFLINE_NONE. - * @param[out] thick_shape_ellipse_arc: the vg_lite path to compute - * @param[in]: radius_out_w: the horizontal inner radius of the ellipse arc - * @param[in]: radius_out_h: the vertical inner radius of the ellipse arc - * @param[in]: radius_in_w: the horizontal outer radius of the ellipse arc - * @param[in]: radius_in_h: the vertical outer radius of the ellipse arc - * @param[in]: start_angle_degree: the start angle of the ellipse arc in degrees - * @param[in]: arc_angle_degree: the arc angle of the ellipse arc in degrees - * @param[in] fill: the flag indicating if the ellipse arc will be filled - * - true: the ellipse arc will be filled - * - false: the ellipse arc will not be filled - * - * @return: - * -1: an error occured, - * otherwise: number of bytes written in the path - */ -int VGLITE_PATH_compute_ellipse_arc( - vg_lite_path_t *thick_ellipse_arc_shape, - int radius_out_w, - int radius_out_h, - int radius_in_w, - int radius_in_h, - float32_t start_angle_degree, - float32_t arc_angle_degree, - bool fill); - -/* - * @brief Computes a thick ellipse arc shape - * - * This function uses bezier curves to apporoximate the ellipse arcs - * The path computed by this function is intended to be used with VGLite - * The function supports the followin caps: DRAWING_ENDOFLINE_NONE and DRAWING_ENDOFLINE_ROUNDED. - * DRAWING_ENDOFLINE_PERPENDICULAR is considered as DRAWING_ENDOFLINE_NONE. - * @param[out] thick_shape_ellipse_arc: vg_lite path to compute - * @param[in]: diameter_w: diameter of the ellipse arc - * @param[in]: diameter_h: diameter of the ellipse arc - * @param[in]: thickness: thickness of the ellipse arc - * @param[in]: start_angle_degree: starting angle of the ellipse arc in degrees - * @param[in]: arc_angle_degree: angle of the ellipse arc in degrees - * @param[in]: caps of the start and end of the ellipse arc, bits [0:1] contains the starting cap, bits [2:3] contains the ending cap. - * - * @return: - * -1: an error occured, - * otherwise: number of bytes written in the path - */ -int VGLITE_PATH_compute_thick_shape_ellipse_arc( - vg_lite_path_t *thick_ellipse_arc_shape, - int diameter_w, - int diameter_h, - int thickness, - float32_t start_angle_degree, - float32_t arc_angle_degree, - int caps); - -/* - * @brief Computes a ellipse - * - * This function uses bezier curves to apporoximate the ellipse - * The path computed by this function is intended to be used with VGLite - * @param[out] point_shape: vg_lite path to compute - * @param[in] thickness: thickness (diameter) of the point - * @param[in,out] matrix: transformation matrix (updated to scale the point) - * - * @return: - * -1: an error occured, - * otherwise: number of bytes written in the path - */ -int VGLITE_PATH_compute_ellipse( - vg_lite_path_t *point_shape, - int path_offset, - int radius_w, - int radius_h, - bool end_path); - -/* - * @brief Computes a plain ellipse - * - * This function uses a hard coded path of a thircle of diameter 200. - * The matrix is updated to scale the ellipse to match the diameter. - * - * This function uses bezier curves to apporoximate the ellipse - * The path computed by this function is intended to be used with VGLite - * @param[out] point_shape: vg_lite path to compute - * @param[in] radius_w: the horizontal radius of the ellipse. - * @param[in] radius_h: the vertical radius of the ellipse. - * @param[in,out] matrix: transformation matrix (updated to scale the point) - * - * @return: - * -1: an error occured, - * otherwise: number of bytes written in the path - */ -int VGLITE_PATH_compute_filled_ellipse( - vg_lite_path_t *point_shape, - int radius_w, - int radius_h, - vg_lite_matrix_t *matrix); - -/* - * @brief Computes a rectangle - * - * The path computed by this function is intended to be used with VGLite - * @param[out] rectangle_shape: vg_lite path to compute - * @param[in] path_offset: offset in the path buffer - * @param[in] x: horizontal coordinate of the left side of the shape - * @param[in] y: vertical coordinate of the top side of the shape - * @param[in] width: width of the rectangle - * @param[in] height: height of the rectangle - * @param[in] end_path: true to end the path, false to leave path open - * - * @return: - * -1: an error occured, - * otherwise: number of bytes written in the path - */ -int VGLITE_PATH_compute_rectangle( - vg_lite_path_t *rounded_rectangle_shape, - int path_offset, - int x, - int y, - int width, - int height, - bool end_path); - -/* - * @brief Computes a rounded rectangle - * - * This function uses bezier curves to apporoximate the corners - * The path computed by this function is intended to be used with VGLite - * @param[out] rounded_rectangle_shape: vg_lite path to compute - * @param[in] path_offset: offset in the path buffer - * @param[in] x: horizontal coordinate of the left side of the shape - * @param[in] y: vertical coordinate of the top side of the shape - * @param[in] height: height of the rounded rectangle - * @param[in] width: width of the rounded rectangle - * @param[in] height: height of the rounded rectangle - * @param[in] arc_width: horizontal diameter of the rounded corner arc - * @param[in] arc_height: vertical diameter of the rounded corner arc - * @param[in] end_path: true to end the path, false to leave path open - * - * @return: - * -1: an error occured, - * otherwise: number of bytes written in the path - */ -int VGLITE_PATH_compute_rounded_rectangle( - vg_lite_path_t *rounded_rectangle_shape, - int path_offset, - int x, - int y, - int width, - int height, - int arc_width, - int arc_height, - bool end_path); - -/* - * @brief Computes a line - * - * The path computed by this function is intended to be used with VGLite - * The line will be computed from origin (0,0) to (x,y) - * @param[out] line_shape: vg_lite path to compute - * @param[in]: x: horizontal coordinate of the end point of the line - * @param[in]: y: vertical coordinate of the end point of the line - * @param[in]: xi: horizontal increment (-1 or 1) according to the line direction (left or right). - * @param[in]: yi: vertical increment (-1 or 1) according to the line direction (top or bottom). - * - * @return: - * -1: an error occured, - * otherwise: number of bytes written in the path - */ -int VGLITE_PATH_compute_line(vg_lite_path_t *line_shape, int x, int y, int xi, int yi); - -/* - * @brief Computes a thick shape line - * - * The path computed by this function is intended to be used with VGLite - * This function will compute an horizontal line and update a matrix to rotate it - * The line will be computed from origin (0,0) to sqrt(x^2,y^2) - * The matrix will be updated to rotate it by atan2(y, x) - * @param[out] line_shape: vg_lite path to compute - * @param[in]: x: horizontal coordinate of the end point of the line - * @param[in]: y: vertical coordinate of the end point of the line - * @param[in]: thickness: thickness (diameter) of the point - * @param[in]: caps: caps of the start and end of the ellipse arc, bits [0:1] contains the starting cap, bits [2:3] contains the ending cap. - * @param[out]: matrix: matrix to be updated with rotation atan2(y, x) - * - * @return: - * -1: an error occured, - * otherwise: number of bytes written in the path - */ -int VGLITE_PATH_compute_thick_shape_line( - vg_lite_path_t *thick_line_shape, - int x, - int y, - int thickness, - int caps, - vg_lite_matrix_t *matrix); - -/* - * @brief Function to update a color to be compatible with VG-Lite. - * - * @param[in/out] color: pointer to the color to update - * @param[in] blend: the blending mode to apply - * - * @return: nothing - */ -void VGLITE_PATH_update_color(vg_lite_color_t* color, vg_lite_blend_t blend) ; - -/* - * @brief Function to update a gradient to be compatible with VG-Lite. - * - * @param[in/out] color: pointer to the color to update - * @param[in] blend: the blending mode to apply - * - * @return: nothing - */ -void VGLITE_PATH_update_gradient(vg_lite_linear_gradient_t* gradient, vg_lite_blend_t blend) ; - -/* - * @brief Operation to perform after a VG-Lite drawing operation. On success, the GPU is - * started. - * - * @param[in] vg_lite_error: the VGLite drawing operation's return code. - * - * @return: the MicroUI status according to the drawing operation status. - */ -DRAWING_Status VGLITE_PATH_post_operation(vg_lite_error_t vg_lite_error); - -/* - * @brief Gets the drawer that makes an indirection to the VG-Lite library. - * - * @param[in] gc: the destination - * - * @return the VG-Lite drawer indirection - */ -VG_DRAWER_drawer_t* VGLITE_PATH_get_vglite_drawer(MICROUI_GraphicsContext* gc); - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#ifdef __cplusplus -} -#endif - -#endif // !defined VGLITE_PATH_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLDW_PAINTER_impl.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLDW_PAINTER_impl.c deleted file mode 100644 index 8f999b1..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLDW_PAINTER_impl.c +++ /dev/null @@ -1,183 +0,0 @@ - -/* - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief This file implements all "Drawing" (MicroUI extended library) drawing native functions. - * @see LLDW_PAINTER_impl.h file comment - * @author MicroEJ Developer Team - * @version 2.0.0 - * @date 22 July 2022 - * @since MicroEJ UI Pack 13.0.0 - */ - -// -------------------------------------------------------------------------------- -// Includes -// -------------------------------------------------------------------------------- - -// implements LLDW_PAINTER_impl functions -#include "LLDW_PAINTER_impl.h" - -// calls dw_drawing functions -#include "dw_drawing.h" - -// use graphical engine functions to synchronize drawings -#include "LLUI_DISPLAY.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// -------------------------------------------------------------------------------- -// Macros and Defines -// -------------------------------------------------------------------------------- - -// macros to log a drawing -#define LOG_DRAW_START(fn) LLUI_DISPLAY_logDrawingStart(CONCAT_DEFINES(LOG_DRAW_, fn)) -#define LOG_DRAW_END(fn) LLUI_DISPLAY_logDrawingEnd(CONCAT_DEFINES(LOG_DRAW_, fn)) - -/* - * LOG_DRAW_EVENT logs identifiers - */ -#define LOG_DRAW_drawThickFadedPoint 100 -#define LOG_DRAW_drawThickFadedLine 101 -#define LOG_DRAW_drawThickFadedCircle 102 -#define LOG_DRAW_drawThickFadedCircleArc 103 -#define LOG_DRAW_drawThickFadedEllipse 104 -#define LOG_DRAW_drawThickLine 105 -#define LOG_DRAW_drawThickCircle 106 -#define LOG_DRAW_drawThickEllipse 107 -#define LOG_DRAW_drawThickCircleArc 108 - -#define LOG_DRAW_drawFlippedImage 200 -#define LOG_DRAW_drawRotatedImageNearestNeighbor 201 -#define LOG_DRAW_drawRotatedImageBilinear 202 -#define LOG_DRAW_drawScaledImageNearestNeighbor 203 -#define LOG_DRAW_drawScaledImageBilinear 204 - -// -------------------------------------------------------------------------------- -// LLDW_PAINTER_impl.h functions -// -------------------------------------------------------------------------------- - -void LLDW_PAINTER_IMPL_drawThickFadedPoint(MICROUI_GraphicsContext* gc, jint x, jint y, jint thickness, jint fade) { - if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickFadedPoint)) { - LOG_DRAW_START(drawThickFadedPoint); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawThickFadedPoint(gc, x, y, thickness, fade)); - LOG_DRAW_END(drawThickFadedPoint); - } -} - -void LLDW_PAINTER_IMPL_drawThickFadedLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness, jint fade, DRAWING_Cap startCap, DRAWING_Cap endCap) { - if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickFadedLine)) { - LOG_DRAW_START(drawThickFadedLine); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawThickFadedLine(gc, startX, startY, endX, endY, thickness, fade, startCap, endCap)); - LOG_DRAW_END(drawThickFadedLine); - } -} - -void LLDW_PAINTER_IMPL_drawThickFadedCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness, jint fade) { - if ((diameter > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickFadedCircle)) { - LOG_DRAW_START(drawThickFadedCircle); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawThickFadedCircle(gc, x, y, diameter, thickness, fade)); - LOG_DRAW_END(drawThickFadedCircle); - } -} - -void LLDW_PAINTER_IMPL_drawThickFadedCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness, jint fade, DRAWING_Cap start, DRAWING_Cap end) { - if ((diameter > 0) && (int32_t)arcAngle != 0 && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickFadedCircleArc)) { - LOG_DRAW_START(drawThickFadedCircleArc); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawThickFadedCircleArc(gc, x, y, diameter, startAngle, arcAngle, thickness, fade, start, end)); - LOG_DRAW_END(drawThickFadedCircleArc); - } -} - -void LLDW_PAINTER_IMPL_drawThickFadedEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness, jint fade) { - if ((width > 0) && (height > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickFadedEllipse)) { - LOG_DRAW_START(drawThickFadedEllipse); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawThickFadedEllipse(gc, x, y, width, height, thickness, fade)); - LOG_DRAW_END(drawThickFadedEllipse); - } -} - -void LLDW_PAINTER_IMPL_drawThickLine(MICROUI_GraphicsContext* gc, jint startX, jint startY, jint endX, jint endY, jint thickness) { - if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickLine)) { - LOG_DRAW_START(drawThickLine); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawThickLine(gc, startX, startY, endX, endY, thickness)); - LOG_DRAW_END(drawThickLine); - } -} - -void LLDW_PAINTER_IMPL_drawThickCircle(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jint thickness) { - if ((diameter > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickCircle)) { - LOG_DRAW_START(drawThickCircle); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawThickCircle(gc, x, y, diameter, thickness)); - LOG_DRAW_END(drawThickCircle); - } -} - -void LLDW_PAINTER_IMPL_drawThickEllipse(MICROUI_GraphicsContext* gc, jint x, jint y, jint width, jint height, jint thickness) { - if ((width > 0) && (height > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickEllipse)) { - LOG_DRAW_START(drawThickEllipse); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawThickEllipse(gc, x, y, width, height, thickness)); - LOG_DRAW_END(drawThickEllipse); - } -} - -void LLDW_PAINTER_IMPL_drawThickCircleArc(MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter, jfloat startAngle, jfloat arcAngle, jint thickness) { - if ((diameter > 0) && ((int32_t)arcAngle != 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawThickCircleArc)) { - LOG_DRAW_START(drawThickCircleArc); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawThickCircleArc(gc, x, y, diameter, startAngle, arcAngle, thickness)); - LOG_DRAW_END(drawThickCircleArc); - } -} - -void LLDW_PAINTER_IMPL_drawFlippedImage(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint regionX, jint regionY, jint width, jint height, jint x, jint y, DRAWING_Flip transformation, jint alpha) { - if (!LLUI_DISPLAY_isClosed(img) && (alpha > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawFlippedImage)) { - LOG_DRAW_START(drawFlippedImage); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawFlippedImage(gc, img, regionX, regionY, width, height, x, y, transformation, alpha)); - LOG_DRAW_END(drawFlippedImage); - } -} - -void LLDW_PAINTER_IMPL_drawRotatedImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha) { - if (!LLUI_DISPLAY_isClosed(img) && (alpha > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawRotatedImageNearestNeighbor)) { - LOG_DRAW_START(drawRotatedImageNearestNeighbor); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawRotatedImageNearestNeighbor(gc, img, x, y, rotationX, rotationY, angle, alpha)); - LOG_DRAW_END(drawRotatedImageNearestNeighbor); - } -} - -void LLDW_PAINTER_IMPL_drawRotatedImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jint rotationX, jint rotationY, jfloat angle, jint alpha) { - if (!LLUI_DISPLAY_isClosed(img) && (alpha > 0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawRotatedImageBilinear)) { - LOG_DRAW_START(drawRotatedImageBilinear); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawRotatedImageBilinear(gc, img, x, y, rotationX, rotationY, angle, alpha)); - LOG_DRAW_END(drawRotatedImageBilinear); - } -} - -void LLDW_PAINTER_IMPL_drawScaledImageNearestNeighbor(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha) { - if (!LLUI_DISPLAY_isClosed(img) && (alpha > 0) && (factorX > 0.f) && (factorY > 0.f) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawScaledImageNearestNeighbor)) { - LOG_DRAW_START(drawScaledImageNearestNeighbor); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha)); - LOG_DRAW_END(drawScaledImageNearestNeighbor); - } -} - -void LLDW_PAINTER_IMPL_drawScaledImageBilinear(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x, jint y, jfloat factorX, jfloat factorY, jint alpha) { - if (!LLUI_DISPLAY_isClosed(img) && (alpha > 0) && (factorX > 0.f) && (factorY > 0.f) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLDW_PAINTER_IMPL_drawScaledImageBilinear)) { - LOG_DRAW_START(drawScaledImageBilinear); - LLUI_DISPLAY_setDrawingStatus(DW_DRAWING_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha)); - LOG_DRAW_END(drawScaledImageBilinear); - } -} - -// -------------------------------------------------------------------------------- -// EOF -// -------------------------------------------------------------------------------- - -#ifdef __cplusplus -} -#endif diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_DISPLAY_impl.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_DISPLAY_impl.c deleted file mode 100644 index ef5ccca..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/LLUI_DISPLAY_impl.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * C - * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include - -#include -#include - -#include "display_dma.h" -#include "display_utils.h" -#include "display_vglite.h" -#include "display_impl.h" -#include "framerate.h" - -#include "fsl_dc_fb_dsi_cmd.h" - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -#if (CUSTOM_VGLITE_MEMORY_CONFIG != 1) -#error "Application must be compiled with CUSTOM_VGLITE_MEMORY_CONFIG=1" -#else -#define VGLITE_COMMAND_BUFFER_SZ (128 * 1024) -#define VGLITE_HEAP_SZ 0x100000 -#endif - -#define DISPLAY_STACK_SIZE (8 * 1024) -#define DISPLAY_TASK_PRIORITY (12) /** Should be > tskIDLE_PRIORITY & < configTIMER_TASK_PRIORITY */ -#define DISPLAY_TASK_STACK_SIZE (DISPLAY_STACK_SIZE / 4) - -// ----------------------------------------------------------------------------- -// Global Variables -// ----------------------------------------------------------------------------- - -/* Allocate the heap and set the command buffer(s) size */ -AT_NONCACHEABLE_SECTION_ALIGN(uint8_t vglite_heap[VGLITE_HEAP_SZ], 64); - -void *vglite_heap_base = &vglite_heap; -uint32_t vglite_heap_size = VGLITE_HEAP_SZ; -uint32_t vglite_cmd_buff_size = VGLITE_COMMAND_BUFFER_SZ; - -/* - * @brief: Semaphore to synchronize the display flush with MicroUI - */ -static SemaphoreHandle_t sync_flush; -static uint8_t* dirty_area_addr; // Address of the source framebuffer -static int32_t dirty_area_ymin; // Top-most coordinate of the area to synchronize -static int32_t dirty_area_ymax; // Bottom-most coordinate of the area to synchronize - -// ----------------------------------------------------------------------------- -// Private functions -// ----------------------------------------------------------------------------- - -/* - * @brief: Flush current framebuffer to the display - */ -static void __display_task_swap_buffers(vg_lite_window_t* pWindow) { - - if ((dirty_area_ymin > 0) || (dirty_area_ymax < (FRAME_BUFFER_HEIGHT - 1))) { - // No need to send all content: modify framebuffer information to reduce - // the number of data to send - - // Retrieve framebuffer information - const dc_fb_t *dc = pWindow->display->g_fbdev.dc; - dc_fb_dsi_cmd_handle_t *dcHandle = dc->prvData; - dc_fb_dsi_cmd_layer_t *pLayer = &(dcHandle->layers[pWindow->display->g_fbdev.layer]); - dc_fb_info_t *fbInfo = &(pLayer->fbInfo); - - // Update startY and height - fbInfo->startY = dirty_area_ymin; - fbInfo->height = dirty_area_ymax - dirty_area_ymin + 1; - - // Update memory pointer to point on first dirty line - vg_lite_buffer_t * current_buffer = VGLITE_GetRenderTarget(pWindow); - uint8_t * original_memory = (uint8_t *) current_buffer->memory; - current_buffer->memory = &((uint8_t *)current_buffer->memory)[dirty_area_ymin * fbInfo->strideBytes]; - - VGLITE_SwapBuffers(pWindow); - - // Restore original context - current_buffer->memory = original_memory; - fbInfo->startY = 0; - fbInfo->height = FRAME_BUFFER_HEIGHT; - } - else { - // just have to swap both buffers - VGLITE_SwapBuffers(pWindow); - } -} - -/* - * @brief: Task to manage display flushes and synchronize with hardware rendering - * operations - */ -static void __display_task(void * pvParameters) { - (void)pvParameters; - - do { - xSemaphoreTake(sync_flush, portMAX_DELAY); - - vg_lite_window_t* window = DISPLAY_VGLITE_get_window(); - - // Two actions: - // 1- wait for the end of previous swap (if not already done): wait the - // end of sending of current frame buffer to display - // 2- start sending of current_buffer to display (without waiting the - // end) - __display_task_swap_buffers(window); - - // Increment framerate - framerate_increment(); - -#if defined (FRAME_BUFFER_COUNT) && (FRAME_BUFFER_COUNT > 1) - vg_lite_buffer_t *current_buffer = VGLITE_GetRenderTarget(window); - - // Configure frame buffer powering; at that point current_buffer is back buffer - // cppcheck-suppress [misra-c2012-11.3] cast to (framebuffer_t *) is valid - DISPLAY_IMPL_update_frame_buffer_status(current_buffer->memory, (framebuffer_t *)dirty_area_addr); - - DISPLAY_DMA_start( - (void *) dirty_area_addr, - current_buffer->memory, - dirty_area_ymin, - dirty_area_ymax); -#else - LLUI_DISPLAY_flushDone(false); -#endif - - } while (1); -} - - -// ----------------------------------------------------------------------------- -// LLUI_DISPLAY_impl.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -void LLUI_DISPLAY_IMPL_initialize(LLUI_DISPLAY_SInitData* init_data) { - - /*************** - * Init VGLite * - ***************/ - - if (kStatus_Success != BOARD_PrepareVGLiteController()) { - DISPLAY_IMPL_error(true, "Prepare VGlite controlor error"); - } - - DISPLAY_VGLITE_init(); - - /************ - * Init DMA * - ************/ - -#if defined (FRAME_BUFFER_COUNT) && (FRAME_BUFFER_COUNT > 1) - static void ** tmp; - - tmp = VGLITE_GetBuffers(); - - for (int i = 0; i < FRAME_BUFFER_COUNT; i++) { - // cppcheck-suppress [misra-c2012-11.5] VGLITE_GetBuffers() return an array of framebuffer_t* - s_frameBufferAddress[i] = tmp[i]; - } -#endif - -#if defined (DISPLAY_DMA_ENABLED) && (DISPLAY_DMA_ENABLED != 0) - DISPLAY_DMA_initialize(s_frameBufferAddress); -#endif // defined DISPLAY_DMA_ENABLED - - /************* - * Init task * - *************/ - - sync_flush = xSemaphoreCreateBinary(); - if (NULL == xTaskCreate( - __display_task, - "Display", - DISPLAY_TASK_STACK_SIZE, - NULL, - DISPLAY_TASK_PRIORITY, - NULL)){ - DISPLAY_IMPL_error(true, "failed to create task __display\n"); - } - - /**************** - * Init MicroUI * - ****************/ - - vg_lite_window_t* window = DISPLAY_VGLITE_get_window(); - vg_lite_buffer_t *buffer = VGLITE_GetRenderTarget(window); - init_data->binary_semaphore_0 = (void*)xSemaphoreCreateBinary(); - init_data->binary_semaphore_1 = (void*)xSemaphoreCreateBinary(); - init_data->lcd_width = window->width; - init_data->lcd_height = window->height; - init_data->memory_width = FRAME_BUFFER_STRIDE_PIXELS; - init_data->back_buffer_address = (uint8_t*)buffer->memory; - - // notify that the display is initialized - DISPLAY_IMPL_initialized(); -} - -// See the header file for the function documentation -uint8_t* LLUI_DISPLAY_IMPL_flush(MICROUI_GraphicsContext* gc, uint8_t* addr, uint32_t xmin, uint32_t ymin, uint32_t xmax, uint32_t ymax) { - - // x bounds are not used by the DMA - (void)gc; - (void)xmin; - (void)xmax; - - uint8_t* ret = (uint8_t*) DISPLAY_VGLITE_get_next_graphics_buffer()->memory; - - // store dirty area to restore after the flush - dirty_area_addr = addr; - dirty_area_ymin = ymin; - dirty_area_ymax = ymax; - - // wakeup display task - xSemaphoreGive(sync_flush); - - return ret; -} - -// See the header file for the function documentation -void LLUI_DISPLAY_IMPL_binarySemaphoreTake(void* sem) { - xSemaphoreTake((SemaphoreHandle_t)sem, portMAX_DELAY); -} - -// See the header file for the function documentation -void LLUI_DISPLAY_IMPL_binarySemaphoreGive(void* sem, bool under_isr) { - - if (under_isr) { - portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - xSemaphoreGiveFromISR((SemaphoreHandle_t)sem, &xHigherPriorityTaskWoken); - if(xHigherPriorityTaskWoken != pdFALSE ) { - // Force a context switch here. - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); - } - } - else { - xSemaphoreGive((SemaphoreHandle_t)sem); - } -} - -// See the header file for the function documentation -uint32_t LLUI_DISPLAY_IMPL_getNewImageStrideInBytes(jbyte image_format, uint32_t image_width, uint32_t image_height, uint32_t default_stride) { - - (void)image_height; - (void)default_stride; - - /* - * VGLite library requires a stride on 16 pixels: 64 bytes for 32bpp, 32 bytes - * for 16bpp and 16 bytes for 8bpp. Exception 8 bytes for <= 4bpp. - */ - uint32_t bpp = DISPLAY_UTILS_get_bpp((MICROUI_ImageFormat)image_format); - return (bpp >= (uint32_t)8) ? ALIGN(image_width, (uint32_t)16) * (bpp / (uint32_t)8) : ALIGN(image_width, (uint32_t)8); -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_framebuffer.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_framebuffer.c deleted file mode 100644 index 01964a1..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_framebuffer.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * C - * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include "display_framebuffer.h" - -#include "fsl_dc_fb.h" - -// ----------------------------------------------------------------------------- -// Global Variables -// ----------------------------------------------------------------------------- - -static framebuffer_t s_frameBuffer0 __attribute__((section(".framebuffer0"))); -#define FRAME_BUFFER0_ADDR &s_frameBuffer0 - -#if defined (FRAME_BUFFER_COUNT) && (FRAME_BUFFER_COUNT > 1) -static framebuffer_t s_frameBuffer1 __attribute__((section(".framebuffer1"))); -#define FRAME_BUFFER1_ADDR &s_frameBuffer1 -#endif - -#if defined (FRAME_BUFFER_COUNT) && (FRAME_BUFFER_COUNT > 2) -static framebuffer_t s_frameBuffer2 __attribute__((section(".framebuffer2"))); -#define FRAME_BUFFER2_ADDR &s_frameBuffer2 -#endif - -// cppcheck-suppress [misra-c2012-9.3] array is fully initialized -const framebuffer_t * s_frameBufferAddress[FRAME_BUFFER_COUNT] = { - FRAME_BUFFER0_ADDR, -#if defined (FRAME_BUFFER_COUNT) && (FRAME_BUFFER_COUNT > 1) - FRAME_BUFFER1_ADDR, -#endif -#if defined (FRAME_BUFFER_COUNT) && (FRAME_BUFFER_COUNT > 2) - FRAME_BUFFER2_ADDR -#endif - }; - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_stub.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_stub.c deleted file mode 100644 index 1871ce6..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_stub.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - * - * @brief Stub implementation of "display_impl.h" - */ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include - -#include "display_impl.h" -#include "bsp_util.h" -#include "fsl_debug_console.h" - -// ----------------------------------------------------------------------------- -// display_impl.h functions -// ----------------------------------------------------------------------------- - -BSP_DECLARE_WEAK_FCNT void DISPLAY_IMPL_initialized(void) { - // does nothing by default -} - -BSP_DECLARE_WEAK_FCNT void DISPLAY_IMPL_error(bool critical, const char* format, ...) { - va_list arg; - va_start (arg, format); - PRINTF(format, arg); - va_end (arg); - while (critical){} -} - -BSP_DECLARE_WEAK_FCNT void DISPLAY_IMPL_notify_gpu_start(void) { - // does nothing by default -} - -BSP_DECLARE_WEAK_FCNT void DISPLAY_IMPL_notify_gpu_stop(void) { - // does nothing by default -} - -BSP_DECLARE_WEAK_FCNT void DISPLAY_IMPL_notify_dma_start(void) { - // does nothing by default -} - -BSP_DECLARE_WEAK_FCNT void DISPLAY_IMPL_notify_dma_stop(void) { - // does nothing by default -} - -BSP_DECLARE_WEAK_FCNT void DISPLAY_IMPL_update_frame_buffer_status(framebuffer_t* frame_buffer_on, framebuffer_t* frame_buffer_off) { - // does nothing by default - (void)frame_buffer_on; - (void)frame_buffer_off; -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_utils.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_utils.c deleted file mode 100644 index e15a82d..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_utils.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * C - * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include - -#include "display_utils.h" - -// ----------------------------------------------------------------------------- -// Global Variables -// ----------------------------------------------------------------------------- - -/* - * @brief Look Up Table to translate MicroUI image to BPP - */ -static const int __microui_to_bpp[] = { - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_LCD = 0, - DISPLAY_UNKNOWN_FORMAT, // UNKNOWN = 1, - (4*8), // MICROUI_IMAGE_FORMAT_ARGB8888 = 2, - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_RGB888 = 3, unsupported - (5+6+5), // MICROUI_IMAGE_FORMAT_RGB565 = 4, - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_ARGB1555 = 5, unsupported - (4*4), // MICROUI_IMAGE_FORMAT_ARGB4444 = 6, - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_A4 = 7, unsupported - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_A8 = 8, unsupported - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_LRGB888 = 9, unsupported - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_LARGB8888 = 10, unsupported - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_A2 = 11, unsupported - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_A1 = 12, unsupported - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_C4 = 13, unsupported - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_C2 = 14, unsupported - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_C1 = 15, unsupported - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_AC44 = 16, unsupported - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_AC22 = 17, unsupported - DISPLAY_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_AC11 = 18, unsupported - // outside of the table ... MICROUI_IMAGE_FORMAT_CUSTOM = 255, -}; - -// ----------------------------------------------------------------------------- -// display_util.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -int32_t DISPLAY_UTILS_get_bpp(MICROUI_ImageFormat image_format) -{ - int bpp = DISPLAY_UNKNOWN_FORMAT; - - // cppcheck-suppress [misra-c2012-10.8] retrieve the array's length - if ((int) image_format < (int)(sizeof(__microui_to_bpp) / sizeof(__microui_to_bpp[0]))) { - bpp = __microui_to_bpp[image_format]; - } - - return (DISPLAY_UNKNOWN_FORMAT == bpp) ? -1 : bpp; -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_vglite.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_vglite.c deleted file mode 100644 index c2fc39c..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/display_vglite.c +++ /dev/null @@ -1,399 +0,0 @@ -/* - * C - * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - * - * Copyright 2023 NXP - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include - -#include - -#include "display_vglite.h" -#include "display_impl.h" -#include "display_configuration.h" -#include "color.h" - -#include "vg_lite_hal.h" - -// ----------------------------------------------------------------------------- -// Configuration Sanity Check -// ----------------------------------------------------------------------------- - -/** - * Sanity check between the expected version of the configuration and the actual version of - * the configuration. - * If an error is raised here, it means that a new version of the CCO has been installed and - * the configuration async_select_configuration.h must be updated based on the one provided - * by the new CCO version. - */ - -#if !defined DISPLAY_CONFIGURATION_VERSION -#error "Undefined DISPLAY_CONFIGURATION_VERSION, it must be defined in display_configuration.h" -#endif - -#if defined DISPLAY_CONFIGURATION_VERSION && DISPLAY_CONFIGURATION_VERSION != 1 -#error "Version of the configuration file display_configuration.h is not compatible with this implementation." -#endif - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -/* - * @brief To check if the image format is known - */ -#define VG_LITE_UNKNOWN_FORMAT ((vg_lite_buffer_format_t) -1) - -/* - * @brief Width of the Tesselation window - * - * @Warning: this impacts the VGLite allocation size - */ -#define DISPLAY_VGLITE_TESSELATION_WIDTH 256 - -/* - * @brief Height of the Tesselation window - * - * @Warning: this impacts the VGLite allocation size - */ -#define DISPLAY_VGLITE_TESSELATION_HEIGHT 256 - -// ----------------------------------------------------------------------------- -// Global Variables -// ----------------------------------------------------------------------------- - -/* - * @brief VGLite destination buffer (there is only one destination at any time) - */ -static vg_lite_buffer_t destination_buffer; - -/* - * @brief VGLite display context - */ -static vg_lite_display_t display; - -/* - * @brief VGLite window context - */ -static vg_lite_window_t window; - -#ifdef VGLITE_OPTION_TOGGLE_GPU -/* - * @brief flag to enable/disable hardware rendering - */ -static bool hardware_rendering; -#endif - -/* - * @brief flag to wakeup the Graphics Engine when GPU drawing is done - */ -static volatile bool vg_lite_operation_wakeup_graphics_engine; - -/* - * @brief vglite operation semaphore - */ -static SemaphoreHandle_t vg_lite_operation_semaphore; - -// ----------------------------------------------------------------------------- -// Static Constants -// ----------------------------------------------------------------------------- - -/* - * @brief LUT to convert MicroUI image format to VGLite image format - */ -const vg_lite_buffer_format_t __microui_to_vg_lite_format[] = { - VG_LITE_RGB565, // MICROUI_IMAGE_FORMAT_LCD = 0, - VG_LITE_UNKNOWN_FORMAT, // UNKNOWN = 1, - VG_LITE_RGBA8888, // MICROUI_IMAGE_FORMAT_ARGB8888 = 2, - VG_LITE_UNKNOWN_FORMAT, // MICROUI_IMAGE_FORMAT_RGB888 = 3, unsupported - VG_LITE_RGB565, // MICROUI_IMAGE_FORMAT_RGB565 = 4, - VG_LITE_RGBA5551, // MICROUI_IMAGE_FORMAT_ARGB1555 = 5 - VG_LITE_RGBA4444, // MICROUI_IMAGE_FORMAT_ARGB4444 = 6, - VG_LITE_A4, // MICROUI_IMAGE_FORMAT_A4 = 7, - VG_LITE_A8, // MICROUI_IMAGE_FORMAT_A8 = 8, - // outside of the table ... MICROUI_IMAGE_FORMAT_CUSTOM = 255, -}; - -// ----------------------------------------------------------------------------- -// Internal function definitions -// ----------------------------------------------------------------------------- - -/* - * @brief This callback must be called when the GCNanoLite-V gpu irq is - * triggered - */ -static void __gpu_irq_callback(void); - -/* - * @brief Configures a vg_lite buffer for a RGB565 image - * - * @param[in] b: buffer to configure - */ -static void __buffer_default_configuration(vg_lite_buffer_t* b); - -/* - * @brief Configures and return current vg_lite buffer for the given image (address and size) - * - * @param[in] image: image from which buffer should be configured - * @param[in] b: buffer to configure - */ -static void __buffer_set_address_and_size(MICROUI_Image* image, vg_lite_buffer_t* b); - -/* - * @brief Convert MICROUI_ImageFormat to vg_lite_buffer_format_t - * - * @param[in] microui_format: MicroUI image format - */ -static vg_lite_buffer_format_t __convert_format(MICROUI_ImageFormat microui_format); - -// ----------------------------------------------------------------------------- -// display_vglite.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -void DISPLAY_VGLITE_init(void) { - vg_lite_error_t ret = VG_LITE_SUCCESS; - - ret = VGLITE_CreateDisplay(&display); - if (VG_LITE_SUCCESS != ret) { - DISPLAY_IMPL_error(true, "VGLITE_CreateDisplay failed: VGLITE_CreateDisplay() returned error %d", ret); - } - - // Initialize the window. - ret = VGLITE_CreateWindow(&display, &window); - if (VG_LITE_SUCCESS != ret) { - DISPLAY_IMPL_error(true, "VGLITE_CreateWindow failed: VGLITE_CreateWindow() returned error %d", ret); - } - - // Initialize the VGLite library and it's tesselation buffer. - ret = vg_lite_init(DISPLAY_VGLITE_TESSELATION_WIDTH, DISPLAY_VGLITE_TESSELATION_HEIGHT); - if (VG_LITE_SUCCESS != ret) { - DISPLAY_IMPL_error(true, "vg_lite engine init failed: vg_lite_init() returned error %d", ret); - } - - // Configures the vg_lite destination buffer for a RGB565 image - __buffer_default_configuration(&destination_buffer); - - // Enable by default hardware rendering - DISPLAY_VGLITE_enable_hardware_rendering(); - - vg_lite_operation_semaphore = xSemaphoreCreateBinary(); - - vg_lite_hal_register_irq_callback(&__gpu_irq_callback); -} - -// See the header file for the function documentation -vg_lite_window_t* DISPLAY_VGLITE_get_window(void) { - return &window; -} - -// See the header file for the function documentation -vg_lite_buffer_t *DISPLAY_VGLITE_get_next_graphics_buffer(void) { - return VGLITE_GetNextBuffer(&window); -} - -void DISPLAY_VGLITE_enable_hardware_rendering(void) { -#ifdef VGLITE_OPTION_TOGGLE_GPU - hardware_rendering = true; -#endif -} - -// See the header file for the function documentation -void DISPLAY_VGLITE_disable_hardware_rendering(void) { -#ifdef VGLITE_OPTION_TOGGLE_GPU - hardware_rendering = false; -#endif -} - -// See the header file for the function documentation -void DISPLAY_VGLITE_toggle_hardware_rendering(void) { -#ifdef VGLITE_OPTION_TOGGLE_GPU - hardware_rendering = !hardware_rendering; -#endif -} - -// See the header file for the function documentation -bool DISPLAY_VGLITE_is_hardware_rendering_enabled(void) { -#ifdef VGLITE_OPTION_TOGGLE_GPU - return hardware_rendering; -#else - return true; -#endif -} - -// See the header file for the function documentation -vg_lite_buffer_t* DISPLAY_VGLITE_configure_destination(MICROUI_GraphicsContext* gc) { - MICROUI_Image* image = &gc->image; - - if ((uint32_t)LLUI_DISPLAY_getBufferAddress(image) != destination_buffer.address) - { - // we target another destination than previous drawing - // -> have to use another context to force vg_lite reloading the new context - __buffer_set_address_and_size(image, &destination_buffer); - } - // else: we target the same destination than previous drawing: nothing to do - - return &destination_buffer; -} - -// See the header file for the function documentation -bool DISPLAY_VGLITE_configure_source(vg_lite_buffer_t *buffer, MICROUI_Image* image) { - - bool ret = false; -#if defined (FRAME_BUFFER_LINE_ALIGN_BYTE) && defined (VGLITE_IMAGE_LINE_ALIGN_BYTE) && (FRAME_BUFFER_LINE_ALIGN_BYTE < VGLITE_IMAGE_LINE_ALIGN_BYTE) - if (!LLUI_DISPLAY_isLCD(image)){ // else: frame buffer does not respect VGLite alignment -#endif - - vg_lite_buffer_format_t format = __convert_format((MICROUI_ImageFormat)image->format); - - if (VG_LITE_UNKNOWN_FORMAT != format) { - - __buffer_default_configuration(buffer); - __buffer_set_address_and_size(image, buffer); - - buffer->image_mode = VG_LITE_MULTIPLY_IMAGE_MODE; // image only - buffer->transparency_mode = VG_LITE_IMAGE_TRANSPARENT; // FIXME - buffer->format = format; - buffer->stride = LLUI_DISPLAY_getStrideInBytes(image); - ret = true; - } -#if defined (FRAME_BUFFER_LINE_ALIGN_BYTE) && defined (VGLITE_IMAGE_LINE_ALIGN_BYTE) && (FRAME_BUFFER_LINE_ALIGN_BYTE < VGLITE_IMAGE_LINE_ALIGN_BYTE) - } -#endif - - return ret; -} - -// See the header file for the function documentation -void DISPLAY_VGLITE_start_operation(bool wakeup_graphics_engine) { - DISPLAY_IMPL_notify_gpu_start(); - vg_lite_operation_wakeup_graphics_engine = wakeup_graphics_engine; - - // VG drawing has been added to the GPU commands list: ask to start VG operation - vg_lite_flush(); - - if (!wakeup_graphics_engine) { - // active waiting until the GPU interrupt is thrown - - (void)xSemaphoreTake(vg_lite_operation_semaphore, portMAX_DELAY); - } -} - -// See the header file for the function documentation -uint32_t DISPLAY_VGLITE_porter_duff_workaround_ARGB8888(uint32_t color) { - uint8_t alpha = COLOR_GET_CHANNEL(color, ARGB8888, ALPHA); - uint32_t ret; - - if (alpha == (uint8_t)0) { - ret = 0; - } - else if(alpha == (uint8_t)0xff) { - ret = color; - } - else { - uint8_t red = (uint8_t)( - (uint32_t)(alpha * COLOR_GET_CHANNEL(color, ARGB8888, RED)) - / (uint32_t)0xff); - uint8_t green = (uint8_t)( - (uint32_t)(alpha * COLOR_GET_CHANNEL(color, ARGB8888, GREEN)) - / (uint32_t)0xff); - uint8_t blue = (uint8_t)( - (uint32_t)(alpha * COLOR_GET_CHANNEL(color, ARGB8888, BLUE)) - / (uint32_t)0xff); - ret = COLOR_SET_COLOR(alpha, red, green, blue, ARGB8888); - } - return ret; -} - -// ----------------------------------------------------------------------------- -// vg_lite.c functions -// ----------------------------------------------------------------------------- - -/* - * Updates current Graphics Context with vglite's rendering area - */ -void vg_lite_draw_notify_render_area(uint32_t x, uint32_t y, uint32_t right, uint32_t bottom) { - LLUI_DISPLAY_setDrawingLimits(x, y, right, bottom); -} - -// ----------------------------------------------------------------------------- -// Internal functions -// ----------------------------------------------------------------------------- - -// See the section 'Internal function definitions' for the function documentation -static void __gpu_irq_callback(void) { - portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - - uint8_t it = interrupt_enter(); - DISPLAY_IMPL_notify_gpu_stop(); - - if (vg_lite_operation_wakeup_graphics_engine) { - // wake up the Graphics Engine - LLUI_DISPLAY_notifyAsynchronousDrawingEnd(true); - } - else { - // wake up the caller of DISPLAY_VGLITE_start_operation() - xSemaphoreGiveFromISR(vg_lite_operation_semaphore, &xHigherPriorityTaskWoken); - if(xHigherPriorityTaskWoken != pdFALSE ) { - // Force a context switch here. - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); - } - } - interrupt_leave(it); - -} - -// See the section 'Internal function definitions' for the function documentation -static void __buffer_default_configuration(vg_lite_buffer_t* b) { - /* Reset planar. */ - b->yuv.uv_planar = 0; - b->yuv.v_planar = 0; - b->yuv.alpha_planar = 0; - - b->tiled = VG_LITE_LINEAR; - b->format = VG_LITE_RGB565; - b->handle = NULL; - b->memory = NULL; - b->address = 0; - b->yuv.swizzle = VG_LITE_SWIZZLE_UV; - b->image_mode = VG_LITE_NORMAL_IMAGE_MODE; - b->transparency_mode = VG_LITE_IMAGE_OPAQUE; -} - -// See the section 'Internal function definitions' for the function documentation -static void __buffer_set_address_and_size(MICROUI_Image* image, vg_lite_buffer_t* b) { - b->width = image->width; - b->height = image->height; - b->stride = LLUI_DISPLAY_getStrideInBytes(image); - b->memory = (void*)LLUI_DISPLAY_getBufferAddress(image); - b->address = (uint32_t)LLUI_DISPLAY_getBufferAddress(image); -} - -// See the section 'Internal function definitions' for the function documentation -vg_lite_buffer_format_t __convert_format(MICROUI_ImageFormat microui_format) { - vg_lite_buffer_format_t vg_lite_format = VG_LITE_UNKNOWN_FORMAT; - if (microui_format < (sizeof(__microui_to_vg_lite_format) / sizeof(__microui_to_vg_lite_format[0]))) { - vg_lite_format = __microui_to_vg_lite_format[microui_format]; - } - - return vg_lite_format; -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/drawing_vglite.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/drawing_vglite.c deleted file mode 100644 index b6bb21d..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/drawing_vglite.c +++ /dev/null @@ -1,2252 +0,0 @@ -/* - * C - * - * Copyright 2019-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include - -#include "ui_drawing_soft.h" -#include "dw_drawing_soft.h" -#include "ui_drawing.h" -#include "dw_drawing.h" - -#include "display_configuration.h" -#include "display_impl.h" -#include "display_vglite.h" -#include "vglite_path.h" - -#include "vg_lite.h" - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -/* - * @brief Scale factor to improve drawing quality in vector mode - */ -#define DRAWING_SCALE_FACTOR (2) -#define DRAWING_SCALE_DIV (1.0 / (vg_lite_float_t)DRAWING_SCALE_FACTOR) - -// ----------------------------------------------------------------------------- -// Global Variables -// ----------------------------------------------------------------------------- - -/* - * @brief Variable to store the vglite pathes during the GPU computation. - * - * MicroUI design must ensure that only one computation is done at a time. - */ -static union { - vglite_path_line_t line; // line - vglite_path_thick_shape_line_t thick_shape_line; // thick shape line - vglite_path_ellipse_t ellipse[2]; // ellipse (in & out) - vglite_path_ellipse_arc_t ellipse_arc; // ellipse arc - vglite_path_rounded_rectangle_t rounded_rectangle[2]; // round rect (in & out) - vglite_path_thick_ellipse_arc_t thick_ellipse_arc; // anti aliased ellipse arc -} __shape_paths; - -/* - * @brief Variable to target a vglite source buffer (there is only one source at any time) - */ -static vg_lite_buffer_t source_buffer; - -// ----------------------------------------------------------------------------- -// Internal function definitions -// ----------------------------------------------------------------------------- - -/* - * @brief Checks MicroUI clip and updates the graphical engine's drawing limits on demand. This - * update is useless when calling vg_lite draw_path function because the callback already updates - * the graphical engine drawing limits. See vg_lite_draw_notify_render_area() in display_vglite.c. - * - * @param[in] gc: Graphics context where to draw - * @param[in] x1 the top-left pixel X coordinate. - * @param[in] y1 the top-left pixel Y coordinate. - * @param[in] x2 the bottom-right pixel X coordinate. - * @param[in] y2 the top-right pixel Y coordinate. - * @param[in] update_drawing_limits true to update drawing limits - * - * @return false when the limits are fully outside the clip, true when at least - * one pixel fits the clip. - */ -static bool __check_clip( - MICROUI_GraphicsContext* gc, - int x1, - int y1, - int x2, - int y2, - bool update_drawing_limits); - -/* - * @brief Draws an ellipse arc covering the square specified by its diameter. - * See DRAWING_impl.h for more information - * - * @param[in] gc: the MicroUI GraphicsContext target. - * @param[in] x: the x coordinate of the upper-left corner of the square where the ellipse arc is drawn - * @param[in] y: the y coordinate of the upper-left corner of the square where the ellipse arc is drawn - * @param[in] diameter_w: the horizontal diameter of the ellipse arc to draw - * @param[in] diameter_h: the vertical diameter of the ellipse arc to draw - * @param[in] start_angle_deg: the beginning angle of the arc to draw - * @param[in] arc_angle_deg: the angular extent of the arc from start_angle_deg - * @param[in] fill: the flag indicating if the ellipse arc will be filled - * - true: the ellipse arc will be filled - * - false: the ellipse arc will not be filled - * - * @return the drawing status. - */ -static DRAWING_Status __draw_ellipse_arc( - MICROUI_GraphicsContext* gc, - int x, - int y, - int diameter_w, - int diameter_h, - float start_angle, - float arc_angle, - bool fill); - -/* - * @brief Draws a ellipse covering the square specified by its diameter. - * See DRAWING_impl.h for more information - * - * @param[in] gc: the MicroUI GraphicsContext target. - * @param[in] x: the x coordinate of the upper-left corner of the square where the ellipse is drawn - * @param[in] y: the y coordinate of the upper-left corner of the square where the ellipse is drawn - * @param[in] diameter_out_w: the horizontal outer diameter of the ellipse to draw - * @param[in] diameter_out_h: the vertical outer diameter of the ellipse to draw - * @param[in] diameter_in_w: the horizontal inner diameter of the ellipse to draw - * @param[in] diameter_in_h: the vertical inner diameter of the ellipse to draw - * - * @return the drawing status. - */ -static DRAWING_Status __draw_ellipse( - MICROUI_GraphicsContext* gc, - int x, - int y, - int diameter_out_w, - int diameter_out_h, - int diameter_in_w, - int diameter_in_h); - -/* - * @brief Fills a ellipse covering the square specified by its diameter. - * See DRAWING_impl.h for more information - * - * @param[in] gc: the MicroUI GraphicsContext target. - * @param[in] x: the x coordinate of the upper-left corner of the square where the ellipse is drawn - * @param[in] y: the y coordinate of the upper-left corner of the square where the ellipse is drawn - * @param[in] diameter_w: the horizontal diameter of the ellipse to draw - * @param[in] diameter_h: the vertical diameter of the ellipse to draw - * - * @return the drawing status. - */ -static DRAWING_Status __fill_ellipse( - MICROUI_GraphicsContext* gc, - int x, - int y, - int diameter_w, - int diameter_h); - -#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS -/* - * @brief Draws a line between two points - * See DRAWING_impl.h for more information - * - * @param[in] gc the MicroUI GraphicsContext target. - * @param[in] x1: the horizontal coordinate of the start of the line - * @param[in] y1: the vertical coordinate of start of the line - * @param[in] x2: the horizontal coordinate of the end of the line - * @param[in] y2: the vertical coordinate of end of the line - * - * @return the drawing status. - */ -static DRAWING_Status __draw_line( - MICROUI_GraphicsContext* gc, - int x1, - int y1, - int x2, - int y2); -#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS - -/* - * @brief Draws a thick line between two points - * See DRAWING_impl.h for more information - * - * @param[in] gc the MicroUI GraphicsContext target. - * @param[in] x1: the horizontal coordinate of the start of the line - * @param[in] y1: the vertical coordinate of start of the line - * @param[in] x2: the horizontal coordinate of the end of the line - * @param[in] y2: the vertical coordinate of end of the line - * @param[in] thickness: the line thickness. - * @param[in] start cap representation of start of the line - * @param[in] end cap representation of end of the line - * - * @return the drawing status. - */ -static DRAWING_Status __thick_line( - MICROUI_GraphicsContext* gc, - int x1, - int y1, - int x2, - int y2, - int thickness, - DRAWING_Cap start, - DRAWING_Cap end); - -/* - * @brief Draws a thick arc covering the square specified by its diameter. - * See dw_drawing.h for more information - * - * @param[in] gc: the MicroUI GraphicsContext target. - * @param[in] x: the x coordinate of the upper-left corner of the square where the arc is drawn - * @param[in] y: the y coordinate of the upper-left corner of the square where the arc is drawn - * @param[in] diameter_w: the horizontal diameter of the ellipse arc to draw - * @param[in] diameter_h: the vertical diameter of the ellipse arc to draw - * @param[in] start_angle_deg: the beginning angle of the arc to draw - * @param[in] arc_angle_deg: the angular extent of the arc from start_angle_deg - * @param[in] thickness: the arc thickness. - * @param[in] start: cap representation of start of shape - * @param[in] end: cap representation of end of shape - * - * @return the drawing status. - */ -static DRAWING_Status __draw_thick_shape_ellipse_arc( - MICROUI_GraphicsContext* gc, - int x, - int y, - int diameter_w, - int diameter_h, - float start_angle_deg, - float arc_angle, - int thickness, - DRAWING_Cap start, - DRAWING_Cap end); - -/* - * @brief Rotates an image using the GPU - * - * @param[in] gc: Graphics context where to draw - * @param[in] img: Source image to draw - * @param[in] src: Source buffer - * @param[in] x: Horizontal coordinate of the image reference anchor top-left point. - * @param[in] y: Vertical coordinate of the image reference anchor top-left point. - * @param[in] xRotation: Horizontal coordinate of the rotation center - * @param[in] yRotation: Vertical coordinate of the rotation center - * @param[in] angle: Angle that must be used to rotate the image - * @param[in] alpha: The opacity level to apply while drawing the rotated image - * @param[in] filter: Quality of drawing. - * - * @return The drawing status. - */ -static DRAWING_Status __rotate_image( - MICROUI_GraphicsContext* gc, - MICROUI_Image* img, - vg_lite_buffer_t* src, - int x, - int y, - int xRotation, - int yRotation, - float angle_deg, - int alpha, - vg_lite_filter_t filter); - -/* - * @brief Scales an image using the GPU - * - * @param[in] gc: Graphics context where to draw. - * @param[in] img: Source image to draw. - * @param[in] src: Source buffer - * @param[in] x: Horizontal coordinate of the image reference anchor top-left point. - * @param[in] y: Vertical coordinate of the image reference anchor top-left point. - * @param[in] factorX: Horizontal scaling factor. - * @param[in] yRotation: Vertical scaling factor. - * @param[in] alpha: The opacity level to apply while drawing the image - * @param[in] filter: Quality of drawing. - * - * @return The drawing status. - */ -static DRAWING_Status __scale_image( - MICROUI_GraphicsContext* gc, - MICROUI_Image* img, - vg_lite_buffer_t* src, - int x, - int y, - float factorX, - float factorY, - int alpha, - vg_lite_filter_t filter); - -/* - * @brief Get color to give to vglite library according to destination's foreground - * color, image format and opacity level. - * - * @param[in] gc: the MicroUI GraphicsContext of destination - * @param[in] img: the MicroUI Image of source - * @param[in] alpha: the application opacity - * - * @return The vg_lite color. - */ -static vg_lite_color_t __get_vglite_color(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint alpha); - -/* - * @brief Configures vg_lite_buffer_t according to the MicroUI Image. - * - * @param[in] buffer: the vg_lite_buffer_t to configure. - * @param[in] image: the MicroUI Image. - * - * @return true when the vg_lite_buffer_t has been configured, false when GPU cannot - * be used to render the image for any reason. - */ -static bool __configure_source(vg_lite_buffer_t *buffer, MICROUI_Image* image); - -/* - * Tells if the source and destination are GPU compatible. If yes, configure the given target, matrix, blit rectangle and color. - * - * @param[in] gc ... alpha: see UI_DRAWING_drawImage() - * @param[out] target: pointer on the target to configure - * @param[out] color: pointer on the color to configure - * @param[out] matrix: pointer on the matrix to configure - * @param[out] blit_rect: pointer on the blit rectangle to configure - * - * @return true if the GPU can be used, false to draw the image in software. - */ -static bool __prepare_gpu_draw_image(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x_src, jint y_src, jint width, jint height, jint x_dest, jint y_dest, jint alpha, void** target, vg_lite_color_t* color, vg_lite_matrix_t* matrix, uint32_t* blit_rect); - -/* - * Draws the image by using the Graphics Engine' software algorithm - * - * @param[in] gc ... alpha: see UI_DRAWING_drawImage() - */ -static void __soft_draw_image(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x_src, jint y_src, jint width, jint height, jint x_dest, jint y_dest, jint alpha); - -/* - * Draws a region of an image at another position by using the GPU. - * - * This function draws block per block to prevent the overlapping. - * - * @param[in] target ... rect: see __prepare_gpu_draw_image() - * @param[in] element_index: the matrix and rectangle offset (0 to target X/width and 1 to target Y/height) - * - * @return DRAWING_RUNNING on success - */ -static DRAWING_Status __draw_region_with_overlap(void* target, vg_lite_color_t color, vg_lite_matrix_t* matrix, uint32_t* rect, uint32_t element_index) ; - -// ----------------------------------------------------------------------------- -// ui_drawing.h and dw_drawing.h functions -// ----------------------------------------------------------------------------- - -#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_drawLine( - MICROUI_GraphicsContext* gc, - jint x1, jint y1, - jint x2, jint y2) { - - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_drawLine(gc, x1, y1, x2, y2); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - // Check if there is something to draw and clip drawing limits - // TODO try to crop region (x1 may lower than x2 and y1 may be lower than y2) - if (__check_clip( - gc, - 0, 0, - gc->image.width, gc->image.height, false)) { - ret = __draw_line(gc, x1, y1, x2, y2); - } - else { - // nothing to draw - ret = DRAWING_DONE; - } - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} - -#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS - -#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_drawHorizontalLine( - MICROUI_GraphicsContext* gc, - jint x1, jint x2, jint y) { - - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_drawLine(gc, x1, y, x2, y); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - // Check if there is something to draw and clip drawing limits - if (__check_clip(gc, x1, y, x2, y, false)) { - ret = __draw_line(gc, x1, y, x2, y); - } - else { - // nothing to draw - ret = DRAWING_DONE; - } - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} -#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS - -#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_drawVerticalLine( - MICROUI_GraphicsContext* gc, - jint x, jint y1, jint y2) { - - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_drawLine(gc, x, y1, x, y2); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - // Check if there is something to draw and clip drawing limits - if (__check_clip(gc, x, y1, x, y2, false)) { - ret = __draw_line(gc, x, y1, x, y2); - } - else { - // nothing to draw - ret = DRAWING_DONE; - } - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} -#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS - -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_fillRectangle( - MICROUI_GraphicsContext* gc, - jint x1, jint y1, jint x2, jint y2) { - - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_fillRectangle(gc, x1, y1, x2, y2); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - // Check if there is something to draw and clip drawing limits - if (__check_clip(gc, x1, y1, x2, y2, true)) { - - vg_lite_rectangle_t rectangle; - rectangle.x = x1; - rectangle.y = y1; - rectangle.width = (x2-x1+1); - rectangle.height = (y2-y1+1); - - void* target = VG_DRAWER_configure_target(gc); - vg_lite_error_t vg_lite_error = VG_DRAWER_clear(target, &rectangle, gc->foreground_color); - ret = VG_DRAWER_post_operation(target, vg_lite_error); - } - else { - ret = DRAWING_DONE; - } - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} - -#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_drawRoundedRectangle( - MICROUI_GraphicsContext* gc, - jint x, jint y, - jint width, jint height, - jint arc_width, jint arc_height) { - - int path_offset; - vg_lite_path_t shape_vg_path; - vg_lite_matrix_t matrix; - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_drawRoundedRectangle(gc, x, y, width, height, arc_width, arc_height); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - // Check if there is something to draw and clip drawing limits - if (__check_clip(gc, x, y, x + width, y + height, true)) { - - vg_lite_identity(&matrix); - // Compute the rounded rectangle shape path - shape_vg_path.path = &__shape_paths.rounded_rectangle[0]; - shape_vg_path.path_length = sizeof(__shape_paths.rounded_rectangle); - path_offset = 0; - path_offset = VGLITE_PATH_compute_rounded_rectangle( - &shape_vg_path, path_offset, - x, y, width, height, arc_width, arc_height, false); - - path_offset = VGLITE_PATH_compute_rounded_rectangle( - &shape_vg_path, path_offset, - x + 1, y + 1, - width - 2, height - 2, - arc_width - 1, arc_height - 1, - true); - - if (0 > path_offset) { - DISPLAY_IMPL_error(false, "Error during path computation"); - ret = DRAWING_DONE; - } - else { - // Draw the point with the GPU - void* target = VG_DRAWER_configure_target(gc); - vg_lite_error_t vg_lite_error = VG_DRAWER_draw_path( - target, - &shape_vg_path, - VG_LITE_FILL_EVEN_ODD, - &matrix, - VG_LITE_BLEND_SRC_OVER, - gc->foreground_color - ); - ret = VG_DRAWER_post_operation(target, vg_lite_error); - } - } - else { - ret = DRAWING_DONE; - } - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} -#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS - -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_fillRoundedRectangle( - MICROUI_GraphicsContext* gc, - jint x, jint y, - jint width, jint height, - jint arc_width, jint arc_height) { - - int path_offset; - vg_lite_path_t shape_vg_path; - vg_lite_matrix_t matrix; - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_fillRoundedRectangle(gc, x, y, width, height, arc_width, arc_height); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - // Check if there is something to draw and clip drawing limits - if (__check_clip(gc, x, y, x + width, y + height, true)) { - - vg_lite_identity(&matrix); - // Compute the rounded rectangle shape path - shape_vg_path.path = &__shape_paths.rounded_rectangle[0]; - shape_vg_path.path_length = sizeof(__shape_paths.rounded_rectangle); - path_offset = VGLITE_PATH_compute_rounded_rectangle(&shape_vg_path, 0, - x, y, width, height, arc_width, arc_height, true); - - if (0 > path_offset) { - DISPLAY_IMPL_error(false, "Error during path computation"); - ret = DRAWING_DONE; - } - else { - // Draw the point with the GPU - void* target = VG_DRAWER_configure_target(gc); - vg_lite_error_t vg_lite_error = VG_DRAWER_draw_path( - target, - &shape_vg_path, - VG_LITE_FILL_EVEN_ODD, - &matrix, - VG_LITE_BLEND_SRC_OVER, - gc->foreground_color - ); - ret = VG_DRAWER_post_operation(target, vg_lite_error); - } - } - else { - ret = DRAWING_DONE; - } - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} - -#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_drawCircleArc( - MICROUI_GraphicsContext* gc, - jint x, - jint y, - jint diameter, - jfloat start_angle, - jfloat arc_angle) { - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - // Check if rendering should be done in software - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_drawCircleArc(gc, x, y, diameter, start_angle, arc_angle); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - if (MEJ_ABS(arc_angle) >= 360) { - ret = UI_DRAWING_drawCircle(gc, x, y, diameter); - } - else { - ret = __draw_ellipse_arc( - gc, - x, y, - diameter, diameter, - start_angle, arc_angle, - false); - } - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} -#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS - -#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_drawEllipseArc( - MICROUI_GraphicsContext* gc, - jint x, - jint y, - jint width, - jint height, - jfloat start_angle, - jfloat arc_angle) { - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - // Check if rendering should be done in software - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_drawEllipseArc( - gc, - x, y, - width, height, - start_angle, arc_angle); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - if (MEJ_ABS(arc_angle) >= 360) { - ret = UI_DRAWING_drawEllipse(gc, x, y, width, height); - } - else { - ret = __draw_ellipse_arc( - gc, - x, y, - width, height, - start_angle, arc_angle, - false); - } - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} -#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS - -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_fillCircleArc( - MICROUI_GraphicsContext* gc, - jint x, jint y, - jint diameter, - jfloat start_angle, jfloat arc_angle) { - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - // Check if rendering should be done in software - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_fillCircleArc( - gc, - x, y, - diameter, - start_angle, arc_angle); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - if (MEJ_ABS(arc_angle) >= 360) { - ret = UI_DRAWING_fillCircle(gc, x, y, diameter); - } - else { - ret = __draw_ellipse_arc( - gc, - x, y, - diameter, diameter, - start_angle, arc_angle, - true); - } - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_fillEllipseArc( - MICROUI_GraphicsContext* gc, - jint x, jint y, - jint width, jint height, - jfloat start_angle, jfloat arc_angle) { - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - // Check if rendering should be done in software - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_fillEllipseArc( - gc, - x, y, - width, height, - start_angle, arc_angle); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - if (MEJ_ABS(arc_angle) >= 360) { - ret = UI_DRAWING_fillEllipse( - gc, - x, y, - width, height); - } - else { - ret = __draw_ellipse_arc( - gc, - x, y, - width, height, - start_angle, arc_angle, - true); - } - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} - -#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_drawEllipse( - MICROUI_GraphicsContext* gc, - jint x, jint y, - jint width, jint height) { - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_drawEllipse(gc, x, y, width, height); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - ret = __draw_ellipse(gc, x, y, width, height, width - 2, height - 2); - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} -#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS - -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_fillEllipse( - MICROUI_GraphicsContext* gc, - jint x, jint y, - jint width, jint height) { - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - // Check if rendering should be done in software - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_fillEllipse(gc, x, y, width, height); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - ret = __fill_ellipse(gc, x, y, width, height); - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} - -#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_drawCircle( - MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter) { - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_drawCircle(gc, x, y, diameter); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - ret = __draw_ellipse( - gc, - x, y, - diameter, diameter, - diameter - 2, diameter - 2); - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} -#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS - -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_fillCircle( - MICROUI_GraphicsContext* gc, jint x, jint y, jint diameter) { - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - // Check if rendering should be done in software - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - UI_DRAWING_SOFT_fillCircle(gc, x, y, diameter); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - ret = __fill_ellipse(gc, x, y, diameter, diameter); - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status DW_DRAWING_drawThickFadedPoint( - MICROUI_GraphicsContext* gc, - jint x, - jint y, - jint thickness, - jint fade) { - - DRAWING_Status ret; - if ((fade > 1) // No radial gradient with hardware -#ifdef VGLITE_OPTION_TOGGLE_GPU - || !DISPLAY_VGLITE_is_hardware_rendering_enabled() -#endif // VGLITE_OPTION_TOGGLE_GPU - ) { - DW_DRAWING_SOFT_drawThickFadedPoint(gc, x, y, thickness,fade); - ret = DRAWING_DONE; - } - else{ - ret = __fill_ellipse(gc, x - (thickness/2), y - (thickness/2), thickness, thickness); - } - return ret; -} - -// See the header file for the function documentation -DRAWING_Status DW_DRAWING_drawThickFadedLine( - MICROUI_GraphicsContext* gc, - jint x1, - jint y1, - jint x2, - jint y2, - jint thickness, - jint fade, - DRAWING_Cap start, - DRAWING_Cap end) { - DRAWING_Status ret; - - if ((fade > 1) // No radial gradient with hardware -#ifdef VGLITE_OPTION_TOGGLE_GPU - || !DISPLAY_VGLITE_is_hardware_rendering_enabled() -#endif // VGLITE_OPTION_TOGGLE_GPU - ) { - DW_DRAWING_SOFT_drawThickFadedLine( - gc, x1, y1, x2, y2, thickness, fade, start, end); - ret = DRAWING_DONE; - } - else { - ret = __thick_line( - gc, - x1, - y1, - x2, - y2, - thickness, - start, - end); - } - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status DW_DRAWING_drawThickFadedCircle( - MICROUI_GraphicsContext* gc, - jint x, jint y, - jint diameter, jint thickness, jint fade) { - - int diameter_out; - int diameter_in; - DRAWING_Status ret; - - if ((fade > 1) // No radial gradient with hardware -#ifdef VGLITE_OPTION_TOGGLE_GPU - || !DISPLAY_VGLITE_is_hardware_rendering_enabled() -#endif // VGLITE_OPTION_TOGGLE_GPU - ) { - DW_DRAWING_SOFT_drawThickFadedCircle( - gc, x, y, diameter, thickness, fade); - ret = DRAWING_DONE; - } - else { - - diameter_out = diameter + thickness; - diameter_in = diameter - thickness; - - ret = __draw_ellipse( - gc, - x - (thickness / 2), y - (thickness / 2), - diameter_out, diameter_out, - diameter_in, diameter_in); - } - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status DW_DRAWING_drawThickFadedCircleArc( - MICROUI_GraphicsContext* gc, - jint x, - jint y, - jint diameter, - jfloat start_angle_deg, - jfloat arc_angle, - jint thickness, - jint fade, - DRAWING_Cap start, - DRAWING_Cap end) { - DRAWING_Status ret; - - if ((fade > 1) // No radial gradient with hardware -#ifdef VGLITE_OPTION_TOGGLE_GPU - || !DISPLAY_VGLITE_is_hardware_rendering_enabled() -#endif // VGLITE_OPTION_TOGGLE_GPU - ) { - DW_DRAWING_SOFT_drawThickFadedCircleArc( gc, - x, - y, - diameter, - start_angle_deg, - arc_angle, - thickness, - fade, - start, - end ); - ret = DRAWING_DONE; - } - else { - ret = __draw_thick_shape_ellipse_arc( - gc, - x, y, - diameter, diameter, - start_angle_deg, arc_angle, - thickness, - start, end); - } - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status DW_DRAWING_drawThickFadedEllipse( - MICROUI_GraphicsContext* gc, - jint x, jint y, - jint width, jint height, - jint thickness, jint fade) { - - int diameter_out_w; - int diameter_out_h; - int diameter_in_w; - int diameter_in_h; - DRAWING_Status ret; - - if ((fade > 1) // No radial gradient with hardware -#ifdef VGLITE_OPTION_TOGGLE_GPU - || !DISPLAY_VGLITE_is_hardware_rendering_enabled() -#endif // VGLITE_OPTION_TOGGLE_GPU - ) { - DW_DRAWING_SOFT_drawThickFadedEllipse( - gc, - x, y, - width, height, - thickness, fade); - ret = DRAWING_DONE; - } - else { - - diameter_out_w = width + thickness; - diameter_out_h = height + thickness; - diameter_in_w = width - thickness; - diameter_in_h = height - thickness; - - ret = __draw_ellipse( - gc, - x - (thickness / 2), y - (thickness / 2), - diameter_out_w, diameter_out_h, - diameter_in_w, diameter_in_h); - } - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status DW_DRAWING_drawThickLine( - MICROUI_GraphicsContext* gc, - jint x1, - jint y1, - jint x2, - jint y2, - jint thickness) { - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - // Check if rendering should be done in software - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - DW_DRAWING_SOFT_drawThickLine(gc, x1, y1, x2, y2, thickness); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - ret = __thick_line( gc, - x1, - y1, - x2, - y2, - thickness, - DRAWING_ENDOFLINE_NONE, - DRAWING_ENDOFLINE_NONE); -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status DW_DRAWING_drawThickCircle( - MICROUI_GraphicsContext* gc, - jint x, - jint y, - jint diameter, - jint thickness) { - - int diameter_out; - int diameter_in; - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - DW_DRAWING_SOFT_drawThickCircle(gc, x, y, diameter, thickness); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - diameter_out = diameter + thickness; - diameter_in = diameter - thickness; - - ret = __draw_ellipse( - gc, - x - (thickness / 2), y - (thickness / 2), - diameter_out, diameter_out, - diameter_in, diameter_in); -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} - -DRAWING_Status DW_DRAWING_drawThickEllipse( - MICROUI_GraphicsContext* gc, - jint x, jint y, - jint width, jint height, - jint thickness) { - - int diameter_out_w; - int diameter_out_h; - int diameter_in_w; - int diameter_in_h; - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - DW_DRAWING_SOFT_drawThickEllipse(gc, x, y, width, height, thickness); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - - diameter_out_w = width + thickness; - diameter_out_h = height + thickness; - diameter_in_w = width - thickness; - diameter_in_h = height - thickness; - - ret = __draw_ellipse( - gc, - x - (thickness / 2), y - (thickness / 2), - diameter_out_w, diameter_out_h, - diameter_in_w, diameter_in_h); -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status DW_DRAWING_drawThickCircleArc( - MICROUI_GraphicsContext* gc, - jint x, - jint y, - jint diameter, - jfloat start_angle_deg, - jfloat arc_angle, - jint thickness) { - DRAWING_Status ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - DW_DRAWING_SOFT_drawThickCircleArc( - gc, x, y, diameter, start_angle_deg, arc_angle, thickness); - ret = DRAWING_DONE; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - - ret = __draw_thick_shape_ellipse_arc( - gc, - x, y, - diameter, diameter, - start_angle_deg, arc_angle, - thickness, - DRAWING_ENDOFLINE_NONE, - DRAWING_ENDOFLINE_NONE); -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status UI_DRAWING_drawImage( - MICROUI_GraphicsContext* gc, - MICROUI_Image* img, - jint x_src, - jint y_src, - jint width, - jint height, - jint x_dest, - jint y_dest, - jint alpha) { - - DRAWING_Status ret; - void* target; - vg_lite_color_t color; - vg_lite_matrix_t matrix; - uint32_t blit_rect[4]; - - if (__prepare_gpu_draw_image(gc, img, x_src, y_src, width, height, x_dest, y_dest, alpha, &target, &color, &matrix, blit_rect)){ - if (VG_LITE_SUCCESS == VG_DRAWER_blit_rect( - target, - &source_buffer, - blit_rect, - &matrix, - VG_LITE_BLEND_SRC_OVER, - color, - VG_LITE_FILTER_POINT)){ - // draw source on itself applying an opacity and without overlap - DISPLAY_VGLITE_start_operation(true); - ret = DRAWING_RUNNING; - } - else{ - DISPLAY_IMPL_error(false, "Error during draw image"); - ret = DRAWING_DONE; - } - } - else { - __soft_draw_image(gc, img, x_src, y_src, width, height, x_dest, y_dest, alpha); - ret = DRAWING_DONE; - } - - return ret; -} - -DRAWING_Status UI_DRAWING_drawRegion(MICROUI_GraphicsContext* gc, jint x_src, jint y_src, jint width, jint height, jint x_dest, jint y_dest, jint alpha){ - - DRAWING_Status ret; - void* target; - vg_lite_color_t color; - vg_lite_matrix_t matrix; - uint32_t blit_rect[4]; - - if (__prepare_gpu_draw_image(gc, &gc->image, x_src, y_src, width, height, x_dest, y_dest, alpha, &target, &color, &matrix, blit_rect)){ - - if ((y_dest == y_src) && (x_dest > x_src) && (x_dest < (x_src + width))){ - // draw with overlap: cut the drawings in several widths - ret = __draw_region_with_overlap(target, color, &matrix, blit_rect, 0); - } - else if ((y_dest > y_src) && (y_dest < (y_src + height))){ - // draw with overlap: cut the drawings in several heights - ret = __draw_region_with_overlap(target, color, &matrix, blit_rect, 1); - } - else if (VG_LITE_SUCCESS == VG_DRAWER_blit_rect( - target, - &source_buffer, - blit_rect, - &matrix, - VG_LITE_BLEND_SRC_OVER, - color, - VG_LITE_FILTER_POINT)){ - // draw source on itself applying an opacity and without overlap - DISPLAY_VGLITE_start_operation(true); - ret = DRAWING_RUNNING; - } - else{ - DISPLAY_IMPL_error(false, "Error during draw region"); - ret = DRAWING_DONE; - } - } - else { - __soft_draw_image(gc, &gc->image, x_src, y_src, width, height, x_dest, y_dest, alpha); - ret = DRAWING_DONE; - } - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status DW_DRAWING_drawFlippedImage( - MICROUI_GraphicsContext* gc, - MICROUI_Image* img, - jint region_x, - jint region_y, - jint width, - jint height, - jint x, - jint y, - DRAWING_Flip transformation, - jint alpha) { - - DRAWING_Status ret; - -#if defined (VG_BLIT_WORKAROUND) && (VG_BLIT_WORKAROUND == 1) - uint32_t blit_rect[4]; -#endif - - if(!__configure_source(&source_buffer, img) - || (region_x != 0) // GPU Limitation: origin different - || (region_y != 0) // than (0, 0) not supported - -#ifndef VGLITE_USE_GPU_FOR_RGB565_IMAGES - // CPU (memcpy) is faster than GPU - || ((MICROUI_IMAGE_FORMAT_RGB565 == img->format) && (DRAWING_FLIP_NONE == transformation) && (0xff == alpha)) -#endif - ) - { - DW_DRAWING_SOFT_drawFlippedImage( - gc, img, - region_x, region_y, - width, height, - x, y, - transformation, alpha); - ret = DRAWING_DONE; - } - else { - // Check if there is something to draw and clip drawing limits - // TODO try to crop region - if (__check_clip( - gc, - 0, 0, - gc->image.width, gc->image.height, - true)) { - - // Exclude bottom right region - source_buffer.width = width; - source_buffer.height = height; - - vg_lite_matrix_t matrix; - vg_lite_identity(&matrix); - - vg_lite_translate(x + (img->width/2), y + (img->height/2), &matrix); - - switch (transformation) { - case DRAWING_FLIP_NONE: - break; - case DRAWING_FLIP_90: - vg_lite_rotate(-90, &matrix); - break; - case DRAWING_FLIP_180: - vg_lite_rotate(-180, &matrix); - break; - case DRAWING_FLIP_270: - vg_lite_rotate(-270, &matrix); - break; - case DRAWING_FLIP_MIRROR: - vg_lite_scale(-1, 1, &matrix); - break; - case DRAWING_FLIP_MIRROR_90: - vg_lite_rotate(90, &matrix); - vg_lite_scale(1, -1, &matrix); - break; - case DRAWING_FLIP_MIRROR_180: - vg_lite_rotate(180, &matrix); - vg_lite_scale(-1, 1, &matrix); - break; - case DRAWING_FLIP_MIRROR_270: - vg_lite_rotate(270, &matrix); - vg_lite_scale(1, -1, &matrix); - break; - default: - DISPLAY_IMPL_error(false, "Unexpected transformation: %d\n", transformation); - break; - } - - vg_lite_translate(-img->width/2, -img->height/2, &matrix); - void* target = VG_DRAWER_configure_target(gc); - vg_lite_error_t vg_lite_error; - -#if defined (VG_BLIT_WORKAROUND) && (VG_BLIT_WORKAROUND == 1) - blit_rect[0] = 0; - blit_rect[1] = 0; - blit_rect[2] = img->width; - blit_rect[3] = img->height; - - vg_lite_error = VG_DRAWER_blit_rect( - target, - &source_buffer, - blit_rect, - &matrix, VG_LITE_BLEND_SRC_OVER, - __get_vglite_color(gc, img, alpha), - VG_LITE_FILTER_BI_LINEAR); -#else - vg_lite_error = VG_DRAWER_blit( - target, - &source_buffer, - &matrix, VG_LITE_BLEND_SRC_OVER, - __get_vglite_color(gc, img, alpha), - VG_LITE_FILTER_BI_LINEAR); -#endif - ret = VG_DRAWER_post_operation(target, vg_lite_error); - } - else { - ret = DRAWING_DONE; - } - } - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status DW_DRAWING_drawRotatedImageNearestNeighbor( - MICROUI_GraphicsContext* gc, - MICROUI_Image* img, - jint x, - jint y, - jint xRotation, - jint yRotation, - jfloat angle, - jint alpha) { - DRAWING_Status ret; - - if(!__configure_source(&source_buffer, img)) { - DW_DRAWING_SOFT_drawRotatedImageNearestNeighbor(gc, img, x, y, xRotation, yRotation, angle, alpha); - ret = DRAWING_DONE; - } - else { - // The GCNanoLiteV limitation: Same rendering around 90 degrees (89.0, 89.1 ... 90.9, 91) - // Render is acceptable since vglite 3.0.4-rev4 - ret = __rotate_image(gc, img, &source_buffer, x, y, xRotation, yRotation, angle, alpha, VG_LITE_FILTER_POINT); - } - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status DW_DRAWING_drawRotatedImageBilinear( - MICROUI_GraphicsContext* gc, - MICROUI_Image* img, - jint x, - jint y, - jint xRotation, - jint yRotation, - jfloat angle, - jint alpha) { - DRAWING_Status ret; - - if(!__configure_source(&source_buffer, img)) { - DW_DRAWING_SOFT_drawRotatedImageBilinear(gc, img, x, y, xRotation, yRotation, angle, alpha); - ret = DRAWING_DONE; - } - else { - // The GCNanoLiteV limitation: Same rendering around 90 degrees (89.0, 89.1 ... 90.9, 91) - // Render is acceptable since vglite 3.0.4-rev4 - ret = __rotate_image(gc, img, &source_buffer, x, y, xRotation, yRotation, angle, alpha, VG_LITE_FILTER_BI_LINEAR); - } - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status DW_DRAWING_drawScaledImageNearestNeighbor( - MICROUI_GraphicsContext* gc, - MICROUI_Image* img, - jint x, - jint y, - jfloat factorX, - jfloat factorY, - jint alpha) { - DRAWING_Status ret; - - if(!__configure_source(&source_buffer, img)){ - DW_DRAWING_SOFT_drawScaledImageNearestNeighbor(gc, img, x, y, factorX, factorY, alpha); - ret = DRAWING_DONE; - } - else { - ret =__scale_image(gc, img, &source_buffer, x, y, factorX, factorY, alpha, VG_LITE_FILTER_POINT); - } - - return ret; -} - -// See the header file for the function documentation -DRAWING_Status DW_DRAWING_drawScaledImageBilinear( - MICROUI_GraphicsContext* gc, - MICROUI_Image* img, - jint x, - jint y, - jfloat factorX, - jfloat factorY, - jint alpha) { - DRAWING_Status ret; - - if(!__configure_source(&source_buffer, img)){ - DW_DRAWING_SOFT_drawScaledImageBilinear(gc, img, x, y, factorX, factorY, alpha); - ret = DRAWING_DONE; - } - else { - ret =__scale_image(gc, img, &source_buffer, x, y, factorX, factorY, alpha, VG_LITE_FILTER_BI_LINEAR); - } - - return ret; -} - -// ----------------------------------------------------------------------------- -// Internal functions -// ----------------------------------------------------------------------------- - -// See the section 'Internal function definitions' for the function documentation -static bool __check_clip( - MICROUI_GraphicsContext* gc, - int x1, - int y1, - int x2, - int y2, - bool update_drawing_limits) { - bool ret; - - if (LLUI_DISPLAY_isClipEnabled(gc)) { - - if (LLUI_DISPLAY_clipRectangle(gc, &x1, &y1, &x2, &y2)) { - // drawing fully or partially fits the clip: - - // enable scissor for next vglite drawing - vg_lite_enable_scissor(); - vg_lite_set_scissor(gc->clip_x1, gc->clip_y1, gc->clip_x2 - gc->clip_x1 + 1, gc->clip_y2 - gc->clip_y1 + 1); - - if (update_drawing_limits) { - // update flush limits (cropped to the clip) - LLUI_DISPLAY_setDrawingLimits(x1, y1, x2, y2); - } - - // perform drawing - ret = true; - } - else { - // drawing is fully outside the clip, nothing to draw - ret = false; - } - } - else { - // clip is disabled : - - // disable scissor (vglite lib already crops to the buffer bounds) - vg_lite_disable_scissor(); - - if (update_drawing_limits) { - // update flush limits - LLUI_DISPLAY_setDrawingLimits(x1, y1, x2, y2); - } - - // perform drawing - ret = true; - } - - return ret; -} - -// See the section 'Internal function definitions' for the function documentation -static DRAWING_Status __draw_ellipse_arc( - MICROUI_GraphicsContext* gc, - int x, - int y, - int diameter_w, - int diameter_h, - float start_angle_deg, - float arc_angle_deg, - bool fill) { - - vg_lite_path_t shape_vg_path; - vg_lite_matrix_t matrix; - DRAWING_Status ret; - - // Check if there is something to draw and clip drawing limits - if (__check_clip(gc, x, y, x + diameter_w, y + diameter_h, false)) { - - vg_lite_identity(&matrix); - - int radius_out_w = diameter_w / 2; - int radius_out_h = diameter_h / 2; - int radius_in_w = radius_out_w - 1; - int radius_in_h = radius_out_h - 1; - - vg_lite_translate(x + radius_out_w, y + radius_out_h, &matrix); - - radius_out_w *= DRAWING_SCALE_FACTOR; - radius_out_h *= DRAWING_SCALE_FACTOR; - radius_in_w *= DRAWING_SCALE_FACTOR; - radius_in_h *= DRAWING_SCALE_FACTOR; - - vg_lite_scale(DRAWING_SCALE_DIV, DRAWING_SCALE_DIV, &matrix); - - shape_vg_path.path = &__shape_paths.ellipse_arc; - shape_vg_path.path_length = sizeof(__shape_paths.ellipse_arc); - int path_offset = VGLITE_PATH_compute_ellipse_arc( - &shape_vg_path, - radius_out_w, radius_out_h, - radius_in_w, radius_in_h, - - // 0 degrees: - // - MicroUI: 3 o'clock. - // - RT595 VGLite implementation : 0 o'clock. - 90.f - start_angle_deg, - - -arc_angle_deg, fill); - - if (0 > path_offset) { - DISPLAY_IMPL_error(false, "Error during path computation"); - ret = DRAWING_DONE; - } - else { - - // Draw the point with the GPU - void* target = VG_DRAWER_configure_target(gc); - vg_lite_error_t vg_lite_error = VG_DRAWER_draw_path( - target, - &shape_vg_path, - VG_LITE_FILL_EVEN_ODD, - &matrix, - VG_LITE_BLEND_SRC_OVER, - gc->foreground_color - ); - ret = VG_DRAWER_post_operation(target, vg_lite_error); - } - } - else { - ret = DRAWING_DONE; - } - return ret; -} - -// See the section 'Internal function definitions' for the function documentation -static DRAWING_Status __draw_ellipse( - MICROUI_GraphicsContext* gc, - int x, int y, - int diameter_out_w, int diameter_out_h, - int diameter_in_w, int diameter_in_h) { - - vg_lite_path_t shape_vg_path; - vg_lite_matrix_t matrix; - DRAWING_Status ret; - - // Check if there is something to draw and clip drawing limits - if (__check_clip(gc, x, y, x + diameter_out_w, y + diameter_out_h, false)) { - - vg_lite_identity(&matrix); - - int radius_w = diameter_out_w / 2; - int radius_h = diameter_out_h / 2; - - vg_lite_translate(x + radius_w, y + radius_h, &matrix); - - radius_w *= DRAWING_SCALE_FACTOR; - radius_h *= DRAWING_SCALE_FACTOR; - - vg_lite_scale(DRAWING_SCALE_DIV, DRAWING_SCALE_DIV, &matrix); - // Compute the rounded rectangle shape path - shape_vg_path.path = &__shape_paths.ellipse[0]; - shape_vg_path.path_length = sizeof(__shape_paths.ellipse); - int path_offset = VGLITE_PATH_compute_ellipse( - &shape_vg_path, 0, - radius_w, radius_h, - false); - - radius_w = diameter_in_w / 2; - radius_h = diameter_in_h / 2; - - radius_w *= DRAWING_SCALE_FACTOR; - radius_h *= DRAWING_SCALE_FACTOR; - - path_offset = VGLITE_PATH_compute_ellipse( - &shape_vg_path, - path_offset, - radius_w, radius_h, - true); - - if (0 > path_offset) { - DISPLAY_IMPL_error(false, "Error during path computation"); - ret = DRAWING_DONE; - } - else { - // Draw the point with the GPU - void* target = VG_DRAWER_configure_target(gc); - vg_lite_error_t vg_lite_error = VG_DRAWER_draw_path( - target, - &shape_vg_path, - VG_LITE_FILL_EVEN_ODD, - &matrix, - VG_LITE_BLEND_SRC_OVER, - gc->foreground_color - ); - ret = VG_DRAWER_post_operation(target, vg_lite_error); - } - } - else { - ret = DRAWING_DONE; - } - return ret; -} - -// See the section 'Internal function definitions' for the function documentation -static DRAWING_Status __fill_ellipse( - MICROUI_GraphicsContext* gc, - int x, int y, - int diameter_w, int diameter_h) { - - vg_lite_matrix_t matrix; - vg_lite_path_t shape_vg_path; - DRAWING_Status ret; - - // Check if there is something to draw and clip drawing limits - if (__check_clip( gc, - x, - y, - x + diameter_w - 1, - y + diameter_h - 1, - false)) { - - int radius_w = diameter_w / 2; - int radius_h = diameter_h / 2; - - vg_lite_identity(&matrix); - vg_lite_translate(x + radius_w, y + radius_h, &matrix); - - // Compute the thick shape path - shape_vg_path.path = &__shape_paths.ellipse; - shape_vg_path.path_length = sizeof(__shape_paths.ellipse); - (void)VGLITE_PATH_compute_filled_ellipse(&shape_vg_path, radius_w, radius_h, &matrix); - - // Draw the point with the GPU - void* target = VG_DRAWER_configure_target(gc); - vg_lite_error_t vg_lite_error = VG_DRAWER_draw_path( - target, - &shape_vg_path, - VG_LITE_FILL_NON_ZERO, - &matrix, - VG_LITE_BLEND_SRC_OVER, - gc->foreground_color - ); - ret = VG_DRAWER_post_operation(target, vg_lite_error); - } - else { - ret = DRAWING_DONE; - } - return ret; -} - -#ifdef VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS -// See the section 'Internal function definitions' for the function documentation -static DRAWING_Status __draw_line( - MICROUI_GraphicsContext* gc, - int x1, int y1, - int x2, int y2) { - - vg_lite_path_t shape_vg_path; - - vg_lite_matrix_t matrix; - vg_lite_identity(&matrix); - - // adjust parameters according to steering coefficient - int xi; - int yi; - int xs; - int ys; - int xe; - int ye; - if (x1 > x2){ - if (y1 > y2){ - xs = x2; - ys = y2; - xe = x1; - ye = y1; - xi = 1; - yi = 1; - } - else { - xs = x1; - ys = y1; - xe = x2; - ye = y2; - xi = -1; - yi = 1; - } - } - else { - if (y1 > y2){ - xs = x1; - ys = y1; - xe = x2; - ye = y2; - xi = 1; - yi = -1; - } - else { - xs = x1; - ys = y1; - xe = x2; - ye = y2; - xi = 1; - yi = 1; - } - } - - vg_lite_translate(xs, ys, &matrix); - - // Compute the thick shape path - shape_vg_path.path = &__shape_paths.line; - shape_vg_path.path_length = sizeof(__shape_paths.line); - (void)VGLITE_PATH_compute_line(&shape_vg_path, xe - xs, ye - ys, xi, yi); - - // Draw the point with the GPU - void* target = VG_DRAWER_configure_target(gc); - vg_lite_error_t vg_lite_error = VG_DRAWER_draw_path( - target, - &shape_vg_path, - VG_LITE_FILL_NON_ZERO, - &matrix, - VG_LITE_BLEND_SRC_OVER, - gc->foreground_color - ); - return VG_DRAWER_post_operation(target, vg_lite_error); -} -#endif // VGLITE_USE_GPU_FOR_SIMPLE_DRAWINGS - -// See the section 'Internal function definitions' for the function documentation -static DRAWING_Status __thick_line( - MICROUI_GraphicsContext* gc, - int x1, - int y1, - int x2, - int y2, - int thickness, - DRAWING_Cap start, - DRAWING_Cap end) { - - vg_lite_path_t shape_vg_path; - vg_lite_matrix_t matrix; - DRAWING_Status ret; - - int min_x = MIN(x1, x2); - int min_y = MIN(y1, y2); - int max_x = MAX(x1, x2); - int max_y = MAX(y1, y2); - - // Check if there is something to draw and clip drawing limits - if (__check_clip( - gc, - min_x - (thickness / 2), - min_y - (thickness / 2), - max_x + (thickness / 2), - max_y + (thickness / 2), - false)) { - - vg_lite_identity(&matrix); - vg_lite_translate(x1, y1, &matrix); - - shape_vg_path.path = &__shape_paths.thick_shape_line; - shape_vg_path.path_length = sizeof(__shape_paths.thick_shape_line); - - int caps = 0; - caps |= MEJ_VGLITE_PATH_SET_CAPS_START(start); - caps |= MEJ_VGLITE_PATH_SET_CAPS_END(end); - - (void)VGLITE_PATH_compute_thick_shape_line( - &shape_vg_path, x2 - x1, y2 - y1, thickness, caps, &matrix); - - void* target = VG_DRAWER_configure_target(gc); - vg_lite_error_t vg_lite_error = VG_DRAWER_draw_path( - target, - &shape_vg_path, - VG_LITE_FILL_NON_ZERO, - &matrix, - VG_LITE_BLEND_SRC_OVER, - gc->foreground_color); - ret = VG_DRAWER_post_operation(target, vg_lite_error); - } - else { - ret = DRAWING_DONE; - } - return ret; -} - -// See the section 'Internal function definitions' for the function documentation -static DRAWING_Status __draw_thick_shape_ellipse_arc( - MICROUI_GraphicsContext* gc, - int x, - int y, - int diameter_w, - int diameter_h, - float start_angle_deg, - float arc_angle, - int thickness, - DRAWING_Cap start, - DRAWING_Cap end) { - - vg_lite_path_t shape_vg_path; - DRAWING_Status ret; - - // Check if there is something to draw and clip drawing limits - if (__check_clip( - gc, - x - thickness, - y - thickness, - x + diameter_w + (2 * thickness) - 1, - y + diameter_h + (2 * thickness) - 1, - false)) { - - // Tunning for CircleArcs rendering like software algorithm - int m_diameter_w = diameter_w + 1; - int m_diameter_h = diameter_h + 1; - int m_thickness = thickness + 1; - int translate_x = x + (m_diameter_w / 2); - int translate_y = y + (m_diameter_h / 2); - - vg_lite_matrix_t matrix; - vg_lite_identity(&matrix); - vg_lite_translate(translate_x, translate_y, &matrix); - vg_lite_rotate(-start_angle_deg, &matrix); - vg_lite_scale(DRAWING_SCALE_DIV, DRAWING_SCALE_DIV, &matrix); - - int caps = 0; - caps |= MEJ_VGLITE_PATH_SET_CAPS_START(start); - caps |= MEJ_VGLITE_PATH_SET_CAPS_END(end); - - // Compute the thick shape path - shape_vg_path.path = &__shape_paths.thick_ellipse_arc; - shape_vg_path.path_length = sizeof(__shape_paths.thick_ellipse_arc); - - (void)VGLITE_PATH_compute_thick_shape_ellipse_arc( - &shape_vg_path, - DRAWING_SCALE_FACTOR * m_diameter_w, - DRAWING_SCALE_FACTOR * m_diameter_h, - DRAWING_SCALE_FACTOR * m_thickness, - 0, - arc_angle, - caps); - - void* target = VG_DRAWER_configure_target(gc); - vg_lite_error_t vg_lite_error = VG_DRAWER_draw_path( - target, - &shape_vg_path, - VG_LITE_FILL_NON_ZERO, - &matrix, - VG_LITE_BLEND_SRC_OVER, - gc->foreground_color); - ret = VG_DRAWER_post_operation(target, vg_lite_error); - } - else { - ret = DRAWING_DONE; - } - return ret; -} - -// See the section 'Internal function definitions' for the function documentation -static DRAWING_Status __rotate_image( - MICROUI_GraphicsContext* gc, - MICROUI_Image* img, - vg_lite_buffer_t* src, - int x, - int y, - int xRotation, - int yRotation, - float angle_deg, - int alpha, - vg_lite_filter_t filter) { - - DRAWING_Status ret; - -#if defined (VG_BLIT_WORKAROUND) && (VG_BLIT_WORKAROUND == 1) - uint32_t blit_rect[4]; -#endif - - // Check if there is something to draw and clip drawing limits - // TODO try to crop region - if (__check_clip( - gc, - 0, 0, - gc->image.width, gc->image.height, - true)) { - - vg_lite_matrix_t matrix; - vg_lite_identity(&matrix); - vg_lite_translate(xRotation, yRotation, &matrix); - vg_lite_rotate(-angle_deg, &matrix); - vg_lite_translate(x-xRotation, y-yRotation, &matrix); - - void* target = VG_DRAWER_configure_target(gc); - vg_lite_error_t vg_lite_error; - -#if defined (VG_BLIT_WORKAROUND) && (VG_BLIT_WORKAROUND == 1) - blit_rect[0] = 0; - blit_rect[1] = 0; - blit_rect[2] = img->width; - blit_rect[3] = img->height; - - vg_lite_error = VG_DRAWER_blit_rect( - target, - src, - blit_rect, - &matrix, VG_LITE_BLEND_SRC_OVER, - __get_vglite_color(gc, img, alpha), - filter); -#else - vg_lite_error = VG_DRAWER_blit( - target, - src, - &matrix, VG_LITE_BLEND_SRC_OVER, - __get_vglite_color(gc, img, alpha), - filter); -#endif - ret = VG_DRAWER_post_operation(target, vg_lite_error); - } - else { - ret = DRAWING_DONE; - } - return ret; -} - -// See the section 'Internal function definitions' for the function documentation -static DRAWING_Status __scale_image( - MICROUI_GraphicsContext* gc, - MICROUI_Image* img, - vg_lite_buffer_t* src, - int x, - int y, - float factorX, - float factorY, - int alpha, - vg_lite_filter_t filter) { - - DRAWING_Status ret; - -#if defined (VG_BLIT_WORKAROUND) && (VG_BLIT_WORKAROUND == 1) - uint32_t blit_rect[4]; -#endif - - // Check if there is something to draw and clip drawing limits - if (__check_clip( - gc, x, y, - (int) (x + (factorX * img->width)), - (int) (y + (factorY * img->height)), - true)) { - - vg_lite_matrix_t matrix; - vg_lite_identity(&matrix); - vg_lite_translate(x, y, &matrix); - vg_lite_scale(factorX, factorY, &matrix); - - void* target = VG_DRAWER_configure_target(gc); - vg_lite_error_t vg_lite_error ; - -#if defined (VG_BLIT_WORKAROUND) && (VG_BLIT_WORKAROUND == 1) - blit_rect[0] = 0; - blit_rect[1] = 0; - blit_rect[2] = img->width; - blit_rect[3] = img->height; - - vg_lite_error = VG_DRAWER_blit_rect( - target, - src, - blit_rect, - &matrix, VG_LITE_BLEND_SRC_OVER, - __get_vglite_color(gc, img, alpha), - filter); -#else - vg_lite_error = VG_DRAWER_blit( - target, - src, - &matrix, VG_LITE_BLEND_SRC_OVER, - __get_vglite_color(gc, img, alpha), - filter); -#endif - ret = VG_DRAWER_post_operation(target, vg_lite_error); - } - else { - ret = DRAWING_DONE; - } - return ret; -} - -// See the section 'Internal function definitions' for the function documentation -static vg_lite_color_t __get_vglite_color(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint alpha) { - jint fc; - - switch(img->format) { - case MICROUI_IMAGE_FORMAT_A4: - case MICROUI_IMAGE_FORMAT_A8: - if (0xff == alpha) { - fc = gc->foreground_color | 0xff000000u; - } - else { - fc = gc->foreground_color; - jint red = alpha * ((fc >> 16) & 0xff) / 0xff; - jint green = alpha * ((fc >> 8) & 0xff) / 0xff; - jint blue = alpha * (fc & 0xff) / 0xff; - fc = (alpha << 24) | (red << 16) | (green << 8) | blue; - } - break; - default: - fc = alpha * 0x01010101; - break; - } - - return (vg_lite_color_t)fc; -} - -// See the section 'Internal function definitions' for the function documentation -static bool __configure_source(vg_lite_buffer_t *buffer, MICROUI_Image* img) { - bool ret; - -#ifdef VGLITE_OPTION_TOGGLE_GPU - if (!DISPLAY_VGLITE_is_hardware_rendering_enabled()) { - // GPU disabled - ret = false; - } - else { -#endif // VGLITE_OPTION_TOGGLE_GPU - -#ifndef VGLITE_USE_GPU_FOR_TRANSPARENT_IMAGES - if (LLUI_DISPLAY_isTransparent(img) && (MICROUI_IMAGE_FORMAT_A8 != img->format) && (MICROUI_IMAGE_FORMAT_A4 != img->format)) { - // No MSAA with hardware - ret = false; - } - else { -#endif // VGLITE_USE_GPU_FOR_TRANSPARENT_IMAGES - - if (!DISPLAY_VGLITE_configure_source(buffer, img)) { - // image format not supported - ret = false; - } - else { - ret = true; - } - -#ifndef VGLITE_USE_GPU_FOR_TRANSPARENT_IMAGES - } -#endif // VGLITE_USE_GPU_FOR_TRANSPARENT_IMAGES - -#ifdef VGLITE_OPTION_TOGGLE_GPU - } -#endif // VGLITE_OPTION_TOGGLE_GPU - - return ret; -} - -// See the section 'Internal function definitions' for the function documentation -static DRAWING_Status __draw_region_with_overlap(void* target, vg_lite_color_t color, vg_lite_matrix_t* matrix, uint32_t* rect, uint32_t element_index) { - - DRAWING_Status ret = DRAWING_RUNNING; - - // rect[x,y,w,h] - uint32_t rect_index = element_index + (uint32_t)2; - - // retrieve band's size (width or height) - jint size = rect[rect_index]; - rect[rect_index] = (uint32_t)(matrix->m[element_index][2] - rect[element_index]); - - // go to x + band size - rect[element_index] += size; - matrix->m[element_index][2] = rect[element_index] + rect[rect_index]; - - while (size > 0) { - - // adjust band's size - if (size < rect[rect_index]){ - rect[rect_index] = size; - } - - // adjust src & dest positions - rect[element_index] -= rect[rect_index]; - matrix->m[element_index][2] -= rect[rect_index]; - - size -= rect[rect_index]; - - if (VG_LITE_SUCCESS != VG_DRAWER_blit_rect( - target, - &source_buffer, - rect, - matrix, - VG_LITE_BLEND_SRC_OVER, - color, - VG_LITE_FILTER_POINT)){ - ret = DRAWING_DONE; - size = 0; // stop the loop - DISPLAY_IMPL_error(false, "Error during draw image with overlap"); - } - else { - // wakeup task only for the last iteration, otherwise waits the end of the drawing before continue - DISPLAY_VGLITE_start_operation(size <= 0); - } - } - - return ret; -} - -// See the section 'Internal function definitions' for the function documentation -static bool __prepare_gpu_draw_image(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x_src, jint y_src, jint width, jint height, jint x_dest, jint y_dest, jint alpha, void** target, vg_lite_color_t* color, vg_lite_matrix_t* matrix, uint32_t* blit_rect){ - - bool gpu_compatible; - - if(__configure_source(&source_buffer, img)) { - - *target = VG_DRAWER_configure_target(gc); - *color = __get_vglite_color(gc, img, alpha); - - vg_lite_identity(matrix); - matrix->m[0][2] = x_dest; - matrix->m[1][2] = y_dest; - - blit_rect[0] = x_src; - blit_rect[1] = y_src; - blit_rect[2] = width; - blit_rect[3] = height; - - LLUI_DISPLAY_setDrawingLimits(x_dest, y_dest, x_dest + width - 1, y_dest + height - 1); - gpu_compatible = true; - } - else{ - gpu_compatible = false; - } - return gpu_compatible; -} - -// See the section 'Internal function definitions' for the function documentation -static inline void __soft_draw_image(MICROUI_GraphicsContext* gc, MICROUI_Image* img, jint x_src, jint y_src, jint width, jint height, jint x_dest, jint y_dest, jint alpha){ - -#ifdef VGLITE_USE_MULTIPLE_DRAWERS - if (!LLUI_DISPLAY_isCustomFormat(gc->image.format)) { - UI_DRAWING_SOFT_drawImage(gc, img, x_src, y_src, width, height, x_dest, y_dest, alpha); - } - // else: unsupported functionality, the drawing is abandoned! -#else // VGLITE_USE_MULTIPLE_DRAWERS - UI_DRAWING_SOFT_drawImage(gc, img, x_src, y_src, width, height, x_dest, y_dest, alpha); -#endif // VGLITE_USE_MULTIPLE_DRAWERS -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/vg_drawer.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/vg_drawer.c deleted file mode 100644 index 723c3a8..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/vg_drawer.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief Indirection of vector drawings to VG-Lite library or to a specific drawer. - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include "vg_drawer.h" -#include "display_vglite.h" -#include "vglite_path.h" - -#include "bsp_util.h" - -// ----------------------------------------------------------------------------- -// vg_drawer.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -inline BSP_DECLARE_WEAK_FCNT VG_DRAWER_drawer_t* VG_DRAWER_get_drawer(MICROUI_GraphicsContext* gc){ - // spec: default implementation returns the vglite drawer indirection - return VGLITE_PATH_get_vglite_drawer(gc); -} - -#ifndef VGLITE_USE_MULTIPLE_DRAWERS - -/* - * All drawings (and pre/post operations) are redirected to the vglite_path.h functions. - * This prevent to use the unique drawer (see VG_DRAWER_get_drawer()) that makes useless - * indirections. - */ - -// See the header file for the function documentation -inline void* VG_DRAWER_configure_target(MICROUI_GraphicsContext* gc) { - return (void*)DISPLAY_VGLITE_configure_destination(gc); -} - -// See the header file for the function documentation -inline void VG_DRAWER_update_color(void* target, vg_lite_color_t* color, vg_lite_blend_t blend) { - (void)target; - VGLITE_PATH_update_color(color, blend); -} - -// See the header file for the function documentation -inline void VG_DRAWER_update_gradient(void* target, vg_lite_linear_gradient_t* gradient, vg_lite_blend_t blend) { - (void)target; - VGLITE_PATH_update_gradient(gradient, blend); -} - -// See the header file for the function documentation -inline vg_lite_error_t VG_DRAWER_draw_path( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color){ - return vg_lite_draw((vg_lite_buffer_t*)target, path, fill_rule, matrix, blend, color); -} - -// See the header file for the function documentation -inline vg_lite_error_t VG_DRAWER_draw_gradient( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_linear_gradient_t * grad, - vg_lite_blend_t blend){ - return vg_lite_draw_gradient((vg_lite_buffer_t*)target, path, fill_rule, matrix, grad, blend); -} - -// See the header file for the function documentation -inline vg_lite_error_t VG_DRAWER_blit_rect( - void* target, - vg_lite_buffer_t *source, - uint32_t *rect, - vg_lite_matrix_t *matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter){ - return vg_lite_blit_rect((vg_lite_buffer_t*)target, source, rect, matrix, blend, color, filter); -} - -// See the header file for the function documentation -inline vg_lite_error_t VG_DRAWER_blit( - void* target, - vg_lite_buffer_t * source, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter){ - return vg_lite_blit((vg_lite_buffer_t*)target, source, matrix, blend, color, filter); -} - -// See the header file for the function documentation -inline vg_lite_error_t VG_DRAWER_clear( - void* target, - vg_lite_rectangle_t *rectangle, - vg_lite_color_t color){ - return vg_lite_clear((vg_lite_buffer_t*)target, rectangle, color); -} - -// See the header file for the function documentation -inline DRAWING_Status VG_DRAWER_post_operation(void* target, vg_lite_error_t vg_lite_error) { - (void)target; - return VGLITE_PATH_post_operation(vg_lite_error); -} - -#else // VGLITE_USE_MULTIPLE_DRAWERS - -/* - * All drawings (and pre/post operations) are redirected to a specific drawer according to - * the MicroUI destination's nature (see LLUI_DISPLAY_isCustomFormat()). - */ - -// See the header file for the function documentation -inline void* VG_DRAWER_configure_target(MICROUI_GraphicsContext* gc) { - return (void*)VG_DRAWER_get_drawer(gc); -} - -// See the header file for the function documentation -inline void VG_DRAWER_update_color(void* target, vg_lite_color_t* color, vg_lite_blend_t blend) { - // cppcheck-suppress [misra-c2012-11.5] cast to (VG_DRAWER_drawer_t *) is valid - VG_DRAWER_drawer_t* drawer = (VG_DRAWER_drawer_t*)target; - drawer->update_color(color, blend); -} - -// See the header file for the function documentation -inline void VG_DRAWER_update_gradient(void* target, vg_lite_linear_gradient_t* gradient, vg_lite_blend_t blend) { - // cppcheck-suppress [misra-c2012-11.5] cast to (VG_DRAWER_drawer_t *) is valid - VG_DRAWER_drawer_t* drawer = (VG_DRAWER_drawer_t*)target; - drawer->update_gradient(gradient, blend); -} - -// See the header file for the function documentation -inline vg_lite_error_t VG_DRAWER_draw_path( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color){ - // cppcheck-suppress [misra-c2012-11.5] cast to (VG_DRAWER_drawer_t *) is valid - VG_DRAWER_drawer_t* drawer = (VG_DRAWER_drawer_t*)target; - return drawer->draw_path(drawer->target, path, fill_rule, matrix, blend, color); -} - -// See the header file for the function documentation -inline vg_lite_error_t VG_DRAWER_draw_gradient( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_linear_gradient_t * grad, - vg_lite_blend_t blend){ - // cppcheck-suppress [misra-c2012-11.5] cast to (VG_DRAWER_drawer_t *) is valid - VG_DRAWER_drawer_t* drawer = (VG_DRAWER_drawer_t*)target; - return drawer->draw_gradient(drawer->target, path, fill_rule, matrix, grad, blend); -} - -// See the header file for the function documentation -inline vg_lite_error_t VG_DRAWER_blit_rect( - void* target, - vg_lite_buffer_t *source, - uint32_t *rect, - vg_lite_matrix_t *matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter){ - // cppcheck-suppress [misra-c2012-11.5] cast to (VG_DRAWER_drawer_t *) is valid - VG_DRAWER_drawer_t* drawer = (VG_DRAWER_drawer_t*)target; - return drawer->blit_rect(drawer->target, source, rect, matrix, blend, color, filter); -} - -// See the header file for the function documentation -inline vg_lite_error_t VG_DRAWER_blit( - void* target, - vg_lite_buffer_t * source, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter){ - // cppcheck-suppress [misra-c2012-11.5] cast to (VG_DRAWER_drawer_t *) is valid - VG_DRAWER_drawer_t* drawer = (VG_DRAWER_drawer_t*)target; - return drawer->blit(drawer->target, source, matrix, blend, color, filter); -} - -// See the header file for the function documentation -inline vg_lite_error_t VG_DRAWER_clear( - void* target, - vg_lite_rectangle_t *rectangle, - vg_lite_color_t color){ - // cppcheck-suppress [misra-c2012-11.5] cast to (VG_DRAWER_drawer_t *) is valid - VG_DRAWER_drawer_t* drawer = (VG_DRAWER_drawer_t*)target; - return drawer->clear(drawer->target, rectangle, color); -} - -// See the header file for the function documentation -inline DRAWING_Status VG_DRAWER_post_operation(void* target, vg_lite_error_t vg_lite_error) { - // cppcheck-suppress [misra-c2012-11.5] cast to (VG_DRAWER_drawer_t *) is valid - VG_DRAWER_drawer_t* drawer = (VG_DRAWER_drawer_t*)target; - return drawer->post_operation(vg_lite_error); -} - -#endif // VGLITE_USE_MULTIPLE_DRAWERS - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/vglite_path.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/vglite_path.c deleted file mode 100644 index dd980bc..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/ui/src/vglite_path.c +++ /dev/null @@ -1,1468 +0,0 @@ -/* - * C - * - * Copyright 2019-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include -#include - -#include "ui_drawing.h" -#include "dw_drawing.h" - -#include "display_impl.h" -#include "display_vglite.h" -#include "vglite_path.h" - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -/* - * Precomputation of tangente for rounded caps - */ -#define CAP_TAN 1.3333333333333333 -#define QUARTER_TAN 0.5522847498307933 - -#define COS_0 1.0 -#define COS_90 0.0 -#define COS_180 -1.0 -#define COS_270 0.0 - -#define SIN_0 0.0 -#define SIN_90 1.0 -#define SIN_180 0.0 -#define SIN_270 -1.0 - -/* - * Constant used to compute the ellipse path - */ - -#define CIRCLE_RADIUS 200 // radius -#define CIRCLE_CP 111 // control point - -// ----------------------------------------------------------------------------- -// Types -// ----------------------------------------------------------------------------- - -/* - * @brief enumeration that identifies the direction of a quarter curve - */ -typedef enum { - __horizontal = 0, // The quarter curve starts horizontaly - __vertical, // The quarter curve starts verticaly -} __axis_t; - -/* - * @brief data to draw a quarter curve - */ -typedef struct { - int x; - int y; -} __quarter_curve_data_t; - -// ----------------------------------------------------------------------------- -// Global Variables -// ----------------------------------------------------------------------------- - -/* - * @brief drawing context - */ -static struct { - uint8_t *path; // Current path buffer - int offset; // Offset in the path buffer - int length; // Length of the path buffer - int x; // Current horizontal coordinate - int y; // Current vertical coordinate - float32_t sin; // Last computed sinus - float32_t cos; // Last computed cosinus - float32_t tangent; // Last computed tangent - int center_x; // horizontal coordinate of the current ellipse center - int center_y; // vertical coordinate of the current ellipse center - float32_t control_x; // horizontal coordinate of the last control point - float32_t control_y; // vertical coordinate of the last control point - __axis_t tangent_axis; // Last tangent (if last command was a quarter curve) -} __ctxt; - -// ----------------------------------------------------------------------------- -// Constants -// ----------------------------------------------------------------------------- - -/* - * Circle path - * This path can be used to draw a circle of anysize anywhere with the proper - * transformation matrix - */ -static const int16_t __circle_s16[] = { - VGLITE_MOVE_CMD, // move to (r, 0) - CIRCLE_RADIUS, 0, - - VGLITE_CUBIC_CMD, // cubic to (r, -4/3 * tan(pi/8), 4/3 * tan(pi/8), -r, 0, -r) - CIRCLE_RADIUS, -CIRCLE_CP, CIRCLE_CP, -CIRCLE_RADIUS, 0, -CIRCLE_RADIUS, - - VGLITE_CUBIC_CMD, // cubic to (-4/3 * tan(pi/8), -r, -r, -4/3 * tan(pi/8), -r, 0) - -CIRCLE_CP, -CIRCLE_RADIUS, -CIRCLE_RADIUS, -CIRCLE_CP, -CIRCLE_RADIUS, 0, - - VGLITE_CUBIC_CMD, // cubic to (-r, 4/3 * tan(pi/8), -4/3 * tan(pi/8), r, 0, r) - -CIRCLE_RADIUS, CIRCLE_CP, -CIRCLE_CP, CIRCLE_RADIUS, 0, CIRCLE_RADIUS, - - VGLITE_CUBIC_CMD, // cubic to (4/3 * tan(pi/8), r, r, 4/3 * tan(pi/8), r, 0) - CIRCLE_CP, CIRCLE_RADIUS, CIRCLE_RADIUS, CIRCLE_CP, CIRCLE_RADIUS, 0, - - VGLITE_END_CMD, // end -}; - -/* - * @brief data to draw all the quarter curves - */ -static __quarter_curve_data_t __quarter_curve_data[4] = { - { SIN_0, COS_0, }, - { SIN_90, COS_90, }, - { SIN_180, COS_180, }, - { SIN_270, COS_270, }, -}; - -// ----------------------------------------------------------------------------- -// Internal function definitions -// ----------------------------------------------------------------------------- - -/* - * @brief Sets the center for ellipse drawing - * - * @param[out]: x: the horizontal coordinate of the point to compute - * @param[out]: y: the vertical coordinate of the point to compute - */ -static inline void __set_center(int x, int y) { - __ctxt.center_x = x; - __ctxt.center_y = y; -} - -/* - * @brief Computes the control point to approximate an ellipse arc - * - * @param[out]: x: the horizontal coordinate of the point to compute - * @param[out]: y: the vertical coordinate of the point to compute - * @param[in]: point_angle: the angle of the point to control in radians - * @param[in]: section_angle: the section angle in radians - */ -static inline void __compute_control_point( - float32_t *x, - float32_t *y, - float32_t point_angle, - float32_t section_angle) { - - __ctxt.tangent = 4 * mej_tan_f32(section_angle/4) / 3; - - __ctxt.control_x = __ctxt.tangent * arm_cos_f32(point_angle); - __ctxt.control_y = __ctxt.tangent * arm_sin_f32(point_angle); - *x = __ctxt.control_x; - *y = __ctxt.control_y; -} - -/* - * @brief Initializes the drawing context - * - * @param[in] path: vg_lite path to use for drawing - * @param[in] offset: offset in the vg_lite path - */ -static void __init_drawing(vg_lite_path_t *path, int offset); - -/* - * @brief Computes a "move_to" VGLite command - * - * @param[in] x: x coordinate of the destination - * @param[in] y: y coordinate of the destination - * - * @return: -1 if there is not enough memory in the buffer, otherwise the new path_offset - */ -static int __move_to(int16_t x, int16_t y); - -/* - * @brief Computes a "line_to" VGLite command - * - * @param[in] x: horizontal coordinate of the destination - * @param[in] y: vertical coordinate of the destination - * - * @return: -1 if there is not enough memory in the buffer, otherwise the new path_offset - */ -static int __line_to(int16_t x, int16_t y); - -/* - * @brief Computes a "cubic_to" VGLite command - * - * @param[in] cy1: y coordinate of the first control point - * @param[in] cx2: x coordinate of the second control point - * @param[in] cy2: y coordinate of the second control point - * @param[in] x: x coordinate of the destination - * @param[in] y: y coordinate of the destination - * - * @return: -1 if there is not enough memory in the buffer, otherwise the new path_offset - */ -static int __cubic_to( - int16_t cx1, - int16_t cy1, - int16_t cx2, - int16_t cy2, - int16_t x, - int16_t y); - -/* - * @brief Computes an "end" VGLite command - * - * @return: - * - 1: not enough memory in the path buffer. - * - otherwise: the updated path offset - */ -static int __end(void); - -/* - * @brief Updates a path structure - * - * @param[in,out] path: pointer to the path to update. - * @param[in] first_path: - * - if true: the bounding box is set, the offset is set to zero. - * - otherwise: the bounding box is increased. - * @param[in] last_path: - * - if true: the path is closed calling __end - * and the path_length will be set to the current offset. - * @param[in] left: left most coordinate of the shape. - * @param[in] top: top most coordinate of the shape. - * @param[in] right: right most coordinate of the shape. - * @param[in] bottom: bottom most coordinate of the shape. - * - * @return: - * - 1: not enough memory in the path buffer. - * - otherwise: the updated path offset - */ -static int __update_path(vg_lite_path_t *path, - bool first_path, - bool last_path, - int left, - int top, - int right, - int bottom); - -/* - * @brief Computes an approximation of an ellipse arc - * This computation uses multiple calls to __approximate_ellipse_arc_fragment_to - * The center point stored in the context must be set before calling this function. - * - * @param[in] radius_w: the width radius of the ellipse, sign indicates the direction: - * - if negative, drawing to the left of current point. - * - if positive, drawing to the righ of the current point. - * @param[in] radius_h: the height radius of the ellipse, sign indicates the direction: - * - if negative, drawing to the top of the current point. - * - if positive, drawing to the bottom of the current point. - * @param[in] start_angle: the angle of the start point in radians. - * @param[in] end_angle: the angle of the end point in radians. - * - * @return: - * - 1: not enough memory in the path buffer. - * - otherwise: the updated path offset - */ -static int __approximate_ellipse_arc_to( - int radius_w, - int radius_h, - float32_t start_angle, - float32_t end_angle); - -/* - * @brief Computes an approximation of an ellipse arc fragment - * This computation uses one VGLite cubic_to command * (bezier curves of 3rd order) - * This algorithm is implemented from the following source: - * https://stackoverflow.com/questions/1734745/how-to-create-circle-with-b%c3%a9zier-curves - * The approximation is acceptable if the angle is less than PI/2. - * For ellipse arcs with angles bigger than PI/2, multiple fragments should be computed - * A is the starting point - * B is the ending point - * C and D are the control points - * The computed arc will start from start_angle until end_angle - * The center point stored in the context must be set before calling this function. - * - * @param[in] radius_w: the width radius of the ellipse, sign indicates the direction: - * - if negative, drawing to the left of current point. - * - if positive, drawing to the righ of the current point. - * @param[in] radius_h: the height radius of the ellipse, sign indicates the direction: - * - if negative, drawing to the top of the current point. - * - if positive, drawing to the bottom of the current point. - * @param[in] start_angle: the angle of the start point in radians. - * @param[in] end_angle: the angle of the end point in radians. - * - * @return: - * - 1: not enough memory in the path buffer. - * - otherwise: the updated path offset - */ -static int __approximate_ellipse_arc_fragment_to( - int radius_w, - int radius_h, - float32_t start_angle, - float32_t end_angle); - -/* - * @brief Computes an approximation of a ellipse arc fragment - * This computation uses one VGLite cubic_to command * (bezier curves of 3rd order) - * This algorithm is implemented from the following source: - * https://stackoverflow.com/questions/1734745/how-to-create-circle-with-b%c3%a9zier-curves - * The approximation is acceptable if the angle is less than 90 degrees. - * For ellipse arcs with angles bigger than 90 degrees, multiple fragments should be computed - * A is the starting point - * B is the ending point - * C and D are the control points - * - * @param[in] center_x: the horizontal coordinate of the center of the ellipse - * @param[in] center_y: the vetical coordinate of the center of the ellipse - * @param[in] radius_w: the horizontal radius of the ellipse - * @param[in] radius_h: the vertical radius of the ellipse - * @param[in] start_angle_rad: the angle of the beginning of the ellipse in radians - * @param[in] end_angle_rad: the angle of the end of the ellipse in radians - * @param[in] tangent: the tangent of 1/4 th of the angle (end_angle_rad - start_angle_rad) as described - * by the algorithm (see source mentionned previously), this must be computed by the caller - * as the computation is heavy and can be reused. - * @param[in] revert: - * - 0: angle is drawn from start_angle_rad to end_angle_rad - * - 1: angle is drawn from end_angle_rad to start_angle_rad - * - * @return: - * - 1: not enough memory in the path buffer. - * - otherwise: the updated path offset - */ -static int __approximate_ellipse_arc_fragment( - uint16_t center_x, - uint16_t center_y, - int radius_w, - int radius_h, - float32_t start_angle_rad, - float32_t end_angle_rad, - float32_t tangent, - int revert); - -/* - * @brief Sets the tangent for the quarter curve algorithm. - * - * @param tangent: the orientation (tangent) of the beginning of the curve - */ -static inline void __set_quarter_curve_tangent_axis(__axis_t tangent_axis) -{ - __ctxt.tangent_axis = tangent_axis; -} - -/* - * @brief Computes a path fragment for a quarter curve from current context position to - * the given destination coordinates - * - * @param x: the horizontal coordinate of the destination point - * @param y: the vertical coordinate of the destination point - * - * @return: - * - 1: not enough memory in the path buffer. - * - otherwise: the updated path offset - */ -static int __quarter_curve_to(int x, int y); - -/* - * @brief Computes a path fragment for multiple quarter curve from current context position. - * This function approximates ellipse quarters with bezier curves. - * - * @param radius_w: the width radius of the curves, the sign indicates the direction to draw: - * - negative, draw to the left of the current point. - * - positive, draw to the right of the current point. - * @param radius_h: the height radius of the curves, the sign indeicates the direction to draw: - * - negative, draw to the top of the current point. - * - positive, draw to the bottom of the current point. - * @param start: the first quarter to draw (between 1 to 4). - * - 0: from 0 to 90 deg - * - 1: from 90 to 180 deg - * - 2: from 180 to 270 deg - * - 3: from 270 to 360 deg - * @param number: the number of quarters to draw - * - positive: clockwise - * - negative: counter clockwise - * - * @return: - * - 1: not enough memory in the path buffer. - * - otherwise: the updated path offset - */ -static int __multiple_quarter_curve_to( - int radius_w, - int radius_h, - int start, - int number); - -/* - * @brief Computes an approximation of an ellipse arc - * - * This computation is based on the function __approximate_ellipse_arc_fragment - * - * The computed path is always centered to (0, 0), the caller can use matrix - * to position the ellipse arc - * - * @param[in]: radius_out_w: the horizontal radius of the outer edge of the ellipse arc - * @param[in]: radius_out_h: the vertical radius of the outer edge of the ellipse arc - * @param[in]: radius_in_w: the horizontal radius of the inner edge of the ellipse arc - * @param[in]: radius_in_h: the vertical radius of the inner edge of the ellipse arc - * @param[in]: start_angle_rad: the angle of the beginning of the ellipse in degrees - * @param[in]: end_angle_rad: the angle of the end of the ellipse in degrees - * @param[in]: caps: the cap representation of the start and the end of the ellipse arc - * This is a bit field that can be manipulated with macros MEJ_VGLITE_PATH_CAPS_XXX, - * MEJ_VGLITE_PATH_SET_CAPS_XXX and MEJ_VGLITE_PATH_GET_CAPS_XXX, - * bits[0-1] represent the cap of the start of the shape, - * bits[2-3] represent the cap of the end of the shape, - * See DRAWING_ENDOFLINE_XXX for caps values - * - * @return: -1 if there is not enough memory in the buffer, otherwise the new path_offset - */ -static int __approximate_ellipse_arc( - int radius_out_w, - int radius_out_h, - int radius_in_w, - int radius_in_h, - float32_t start_angle_rad, - float32_t arc_angle_rad, - int caps); - -/* - * @brief Normalize an angle so that it is in the range [0, 360[ - * - * @param[in] angle_deg: the angle to normalize in degrees - * - * @return: the normalized angle - */ -static float32_t __normalize_angle(float32_t angle_deg); - -/* - * @brief Indirection to draw a path using VG-Lite library. - * - * @see vg_lite_draw - * - * @return: the VG-Lite error code - */ -static vg_lite_error_t __drawer_vglite_draw_path( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color) ; - -/* - * @brief Indirection to draw a path with gradient using VG-Lite library. - * - * @see vg_lite_draw_gradient - * - * @return: the VG-Lite error code - */ -static vg_lite_error_t __drawer_vglite_draw_gradient( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_linear_gradient_t * grad, - vg_lite_blend_t blend) ; - -/* - * @brief Indirection to blit a part of the source using VG-Lite library. - * - * @see vg_lite_blit_rect - * - * @return: the VG-Lite error code - */ -static vg_lite_error_t __drawer_vglite_blit_rect( - void* target, - vg_lite_buffer_t *source, - uint32_t *rect, - vg_lite_matrix_t *matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter) ; -/* - * @brief Indirection to blit the source using VG-Lite library. - * - * @see vg_lite_blit - * - * @return: the VG-Lite error code - */ -static vg_lite_error_t __drawer_vglite_blit( - void* target, - vg_lite_buffer_t *source, - vg_lite_matrix_t *matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter) ; -/* - * - * @brief Indirection to clear a rectangle using VG-Lite library. - * - * @see vg_lite_clear - * - * @return: the VG-Lite error code - */ -static vg_lite_error_t __drawer_vglite_clear( - void* target, - vg_lite_rectangle_t *rectangle, - vg_lite_color_t color) ; - -// ----------------------------------------------------------------------------- -// Fields -// ----------------------------------------------------------------------------- - -/* - * @brief Drawer that makes an indirection to the VG-Lite library to draw paths. - */ -static VG_DRAWER_drawer_t vglite_drawer = { - - __drawer_vglite_draw_path, - __drawer_vglite_draw_gradient, - __drawer_vglite_blit_rect, - __drawer_vglite_blit, - __drawer_vglite_clear, - - VGLITE_PATH_update_color, - VGLITE_PATH_update_gradient, - - VGLITE_PATH_post_operation, -}; - -// ----------------------------------------------------------------------------- -// vglite_path.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -int VGLITE_PATH_compute_line(vg_lite_path_t *line_shape, int x, int y, int xi, int yi) { - // Initialize the drawing context - __init_drawing(line_shape, 0); - - // Move to beginning - (void)__move_to(0, 0); - (void)__move_to(xi, 0); - - // Compute edges of the line - (void)__line_to(x + xi, y); - (void)__line_to(x + xi, y + yi); - (void)__line_to(x, y + yi); - (void)__line_to(0, yi); - (void)__line_to(0, 0); - - return __update_path(line_shape, true, true, 0, 0, x + xi, y + yi); -} - -// See the header file for the function documentation -int VGLITE_PATH_compute_rectangle( - vg_lite_path_t *rectangle_shape, - int path_offset, - int x, int y, - int width, int height, - bool end_path) { - bool first_path = (path_offset == 0); - - // Precompute all necessary coordinates - int left = x; - int right = left + width; - int top = y; - int bottom = top + height; - - // Initialize the drawing context - __init_drawing(rectangle_shape, path_offset); - - // Move to beginning (beginning of top side) - (void)__move_to(left, top); - - // Compute top side - (void)__line_to(right, top); - - // Compute right side - (void)__line_to(right, bottom); - - // Compute bottom side - (void)__line_to(left, bottom); - - // Compute left side - (void)__line_to(left, top); - - return __update_path(rectangle_shape, first_path, end_path, - left, top, right, bottom); -} - -// See the header file for the function documentation -int VGLITE_PATH_compute_rounded_rectangle( - vg_lite_path_t *rounded_rectangle_shape, - int path_offset, - int x, int y, - int width, int height, - int arc_width, int arc_height, - bool end_path) { - bool first_path = (path_offset == 0); - - // Convert diameter to radius - int radius_width = arc_width / 2; - int radius_height = arc_height / 2; - - // Precompute all necessary coordinates - int left = x; - int right = left + width; - int top = y; - int bottom = top + height; - int left_radius = left + radius_width; - int right_radius = right - radius_width; - int top_radius = top + radius_height; - int bottom_radius = bottom - radius_height; - - // Initialize the drawing context - __init_drawing(rounded_rectangle_shape, path_offset); - - // Move to beginning (beginning of top side) - (void)__move_to(left_radius, top); - - // Compute top side - (void)__line_to(right_radius, top); - - // Compute top right corner - __set_quarter_curve_tangent_axis(__horizontal); - (void)__quarter_curve_to(right, top_radius); - - // Compute right side - (void)__line_to(right, bottom_radius); - - // Compute bottom right corner - (void)__quarter_curve_to(right_radius, bottom); - - // Compute bottom side - (void)__line_to(left_radius, bottom); - - // Compute bottom left corner - (void)__quarter_curve_to(left, bottom_radius); - - // Compute left side - (void)__line_to(left, top_radius); - - // Compute top left corner - (void)__quarter_curve_to(left_radius, top); - - return __update_path(rounded_rectangle_shape, first_path, end_path, - left, top, right, bottom); -} - -// See the header file for the function documentation -int VGLITE_PATH_compute_ellipse_arc( - vg_lite_path_t *ellipse_arc, - int radius_out_w, - int radius_out_h, - int radius_in_w, - int radius_in_h, - float32_t start_angle_degree, - float32_t arc_angle_degree, - bool fill) { - float32_t start_angle; - float32_t end_angle; - float32_t arc_angle; - - arc_angle = MEJ_DEG2RAD(arc_angle_degree); - - start_angle = MEJ_DEG2RAD(start_angle_degree); - end_angle = start_angle + arc_angle; - - // Initialize the drawing context - __init_drawing(ellipse_arc, 0); - - // Move to start - __set_center(0, 0); - __ctxt.x = (int) (radius_out_w * arm_sin_f32(start_angle)); - __ctxt.y = (int) (-radius_out_h * arm_cos_f32(start_angle)); - - (void)__move_to(__ctxt.x, __ctxt.y); - - // Draw outer ellipse - (void)__approximate_ellipse_arc_to(radius_out_w, radius_out_h, start_angle, end_angle); - - if (fill == false) { - // Line to inner ellipse start - (void)__line_to( - (int) (__ctxt.center_x + (__ctxt.sin * radius_in_w)), - (int) (__ctxt.center_y - (__ctxt.cos * radius_in_h))); - - // Draw inner ellipse - (void)__approximate_ellipse_arc_to(radius_in_w, radius_in_h, end_angle, start_angle); - } else { - (void)__line_to(0, 0); - } - - (void)__end(); - - return __update_path(ellipse_arc, true, true, - -radius_out_w, -radius_out_h, radius_out_w, radius_out_h); -} - -// See the header file for the function documentation -int VGLITE_PATH_compute_ellipse( - vg_lite_path_t *ellipse_shape, - int path_offset, - int radius_w, - int radius_h, - bool end_path) { - bool first_path = (path_offset == 0); - - // Initialize the drawing context - __init_drawing(ellipse_shape, path_offset); - - // Move to top - (void)__move_to(0, -radius_h); - - (void)__multiple_quarter_curve_to(radius_w, radius_h, 0, 4); - - return __update_path(ellipse_shape, first_path, end_path, - -radius_w, -radius_h, radius_w, radius_h); -} - -// See the header file for the function documentation -int VGLITE_PATH_compute_filled_ellipse( - vg_lite_path_t *point_shape, - int radius_w, - int radius_h, - vg_lite_matrix_t *matrix) { - - // cppcheck-suppress [misra-c2012-11.8] cast to (void *) is valid - point_shape->path = (void *) __circle_s16; - vg_lite_float_t scale_w = (float32_t) radius_w / CIRCLE_RADIUS; - vg_lite_float_t scale_h = (float32_t) radius_h / CIRCLE_RADIUS; - - vg_lite_scale(scale_w, scale_h, matrix); - - point_shape->path_length = sizeof(__circle_s16); - - return __update_path(point_shape, true, false, - -CIRCLE_RADIUS, - -CIRCLE_RADIUS, - +CIRCLE_RADIUS, - +CIRCLE_RADIUS); -} - -// See the header file for the function documentation -int VGLITE_PATH_compute_thick_shape_line( - vg_lite_path_t *thick_line_shape, - int x, - int y, - int thickness, - int caps, - vg_lite_matrix_t *matrix) { - int length; - int top; - int bottom; - int cap; - - // Compute the length of the line: sqrt(dx^2 + dy^2) - length = (int) mej_sqrt_f32((x*x) + (y*y)); - - // Compute line angle with x axis - vg_lite_rotate(MEJ_RAD2DEG(atan2(y, x)), matrix); - - int half_thickness = thickness / 2; - top = -half_thickness; - bottom = thickness - half_thickness; - - // Initialize the drawing context - __init_drawing(thick_line_shape, 0); - - // Move to top - (void)__move_to(0, top); - - // Line to upper end side - (void)__line_to(length, top); - - cap = MEJ_VGLITE_PATH_GET_CAPS_END(caps); - switch(cap) { - case DRAWING_ENDOFLINE_ROUNDED: - { - // Cubics for end cap - __set_quarter_curve_tangent_axis(__horizontal); - (void)__quarter_curve_to(length + half_thickness, 0); - (void)__quarter_curve_to(length, bottom); - break; - } - case DRAWING_ENDOFLINE_NONE: - case DRAWING_ENDOFLINE_PERPENDICULAR: - { - // Compute line cap - (void)__line_to(length, bottom); - break; - } - default: - DISPLAY_IMPL_error(false, "Unknown cap: %d", cap); - break; - } - - // Line to bottom origin - (void)__line_to(0, bottom); - - // Cubics for start cap - cap = MEJ_VGLITE_PATH_GET_CAPS_START(caps); - switch(cap) { - case DRAWING_ENDOFLINE_ROUNDED: - { - // Cubics for end cap - __set_quarter_curve_tangent_axis(__horizontal); - (void)__quarter_curve_to(-half_thickness, 0); - (void)__quarter_curve_to(0, top); - break; - } - case DRAWING_ENDOFLINE_NONE: - case DRAWING_ENDOFLINE_PERPENDICULAR: - { - // Compute line cap - (void)__line_to(0, top); - break; - } - default: - DISPLAY_IMPL_error(false, "Unknown cap: %d", cap); - break; - } - - return __update_path(thick_line_shape, true, true, - -half_thickness, top, length + half_thickness, bottom); -} - -// See the header file for the function documentation -int VGLITE_PATH_compute_thick_shape_ellipse_arc( - vg_lite_path_t *thick_ellipse_arc_shape, - int diameter_w, - int diameter_h, - int thickness, - float32_t start_angle_deg, - float32_t arc_angle_deg, - int caps) { - int path_length; - - float32_t l_arc_angle_deg = arc_angle_deg; - float32_t l_start_angle_deg = start_angle_deg; - int l_caps = caps; - - if (l_arc_angle_deg < 0) { - // invert start angle and end angle - l_start_angle_deg += l_arc_angle_deg; - l_arc_angle_deg = -l_arc_angle_deg; - int cap1 = MEJ_VGLITE_PATH_GET_CAPS_START(l_caps); - int cap2 = MEJ_VGLITE_PATH_GET_CAPS_END(l_caps); - l_caps = 0; - l_caps |= MEJ_VGLITE_PATH_SET_CAPS_START(cap2); - l_caps |= MEJ_VGLITE_PATH_SET_CAPS_END(cap1); - } - - if (l_arc_angle_deg > 360) { - l_arc_angle_deg = 360; - } - l_start_angle_deg = __normalize_angle(l_start_angle_deg); - - float32_t start_angle_rad = MEJ_DEG2RAD(l_start_angle_deg); - float32_t arc_angle_rad = MEJ_DEG2RAD(l_arc_angle_deg); - - int radius_out_w = (diameter_w + thickness)/2; - int radius_out_h = (diameter_h + thickness)/2; - int radius_in_w = ((diameter_w - thickness)/2) + 1; - int radius_in_h = ((diameter_h - thickness)/2) + 1; - - // Initialize the drawing context - __init_drawing(thick_ellipse_arc_shape, 0); - - path_length = __approximate_ellipse_arc( - radius_out_w, - radius_out_h, - radius_in_w, - radius_in_h, - start_angle_rad, - arc_angle_rad, - l_caps); - - thick_ellipse_arc_shape->path_length = path_length; - - return __update_path(thick_ellipse_arc_shape, true, true, - -radius_out_w, - -radius_out_h, - +radius_out_w, - +radius_out_h); -} - -// See the header file for the function documentation -inline void VGLITE_PATH_update_color(vg_lite_color_t* color, vg_lite_blend_t blend) { - if (VG_LITE_BLEND_SRC_OVER == blend){ - *color = DISPLAY_VGLITE_porter_duff_workaround_ARGB8888(*color); - } - // else: nothing to do -} - -// See the header file for the function documentation -void VGLITE_PATH_update_gradient(vg_lite_linear_gradient_t* gradient, vg_lite_blend_t blend) { - - // convert colors to bypass porter duff limitation - if (VG_LITE_BLEND_SRC_OVER == blend){ - uint32_t count = gradient->count; - uint32_t* colors = gradient->colors; - for (uint32_t i = 0; i < count; i++) { - colors[i] = DISPLAY_VGLITE_porter_duff_workaround_ARGB8888(colors[i]); - } - } - - // update the VG-Lite internal image that represents the gradient - (void)vg_lite_update_grad(gradient); // always success -} - -// See the header file for the function documentation -DRAWING_Status VGLITE_PATH_post_operation(vg_lite_error_t vg_lite_error) { - DRAWING_Status ret; - if (VG_LITE_SUCCESS != vg_lite_error) { - DISPLAY_IMPL_error(true, "vg_lite operation failed with error: %d\n", vg_lite_error); - ret = DRAWING_DONE; - } else { - ret = DRAWING_RUNNING; - // start GPU operation - DISPLAY_VGLITE_start_operation(true); - } - return ret; -} - -// See the header file for the function documentation -inline VG_DRAWER_drawer_t* VGLITE_PATH_get_vglite_drawer(MICROUI_GraphicsContext* gc) { - vglite_drawer.target = (void*)DISPLAY_VGLITE_configure_destination(gc); - return &vglite_drawer; -} - -// ----------------------------------------------------------------------------- -// Internal functions -// ----------------------------------------------------------------------------- - -// See the section 'Internal function definitions' for the function documentation -static void __init_drawing(vg_lite_path_t *path, int offset) { - __ctxt.path = path->path; - __ctxt.offset = offset; - __ctxt.length = path->path_length; -} - -// See the section 'Internal function definitions' for the function documentation -static int __move_to(int16_t x, int16_t y) { - uint8_t *path = __ctxt.path; - - // cppcheck-suppress [misra-c2012-11.3] cast to (path_move_to_s16_t *) is valid - path_move_to_s16_t *move_to = (path_move_to_s16_t *) &path[__ctxt.offset]; - - move_to->cmd = VGLITE_MOVE_CMD; - move_to->x = x; - move_to->y = y; - - __ctxt.x = x; - __ctxt.y = y; - __ctxt.offset += (int)MEJ_VGLITE_PATH_MOVE_TO_LENGTH(s16_t); - - return __ctxt.offset; -} - -// See the section 'Internal function definitions' for the function documentation -static int __line_to(int16_t x, int16_t y) -{ - // cppcheck-suppress [misra-c2012-11.3] cast to (path_line_to_s16_t *) is valid - path_line_to_s16_t *line_to = (path_line_to_s16_t *) &__ctxt.path[__ctxt.offset]; - - line_to->cmd = VGLITE_LINE_CMD; - line_to->x = x; - line_to->y = y; - - __ctxt.x = x; - __ctxt.y = y; - __ctxt.offset += (int)MEJ_VGLITE_PATH_LINE_TO_LENGTH(s16_t); - - return __ctxt.offset; -} - -// See the section 'Internal function definitions' for the function documentation -static int __quarter_curve_to(int x, int y) { - int radius_h = x - __ctxt.x; - int radius_v = y - __ctxt.y; - int control_h = (int) (QUARTER_TAN * radius_h); - int control_v = (int) (QUARTER_TAN * radius_v); - int c1_x; - int c1_y; - int c2_x; - int c2_y; - - if (__horizontal == __ctxt.tangent_axis) { - c1_x = __ctxt.x + control_h; - c1_y = __ctxt.y; - - c2_x = x; - c2_y = y - control_v; - - __ctxt.tangent_axis = __vertical; - } else { - c1_x = __ctxt.x; - c1_y = __ctxt.y + control_v; - - c2_x = x - control_h; - c2_y = y; - - __ctxt.tangent_axis = __horizontal; - } - - // Start tangeant to horizontal - (void)__cubic_to(c1_x, c1_y, c2_x, c2_y, x, y); - - __ctxt.x = x; - __ctxt.y = y; - - return __ctxt.offset; -} - -// See the section 'Internal function definitions' for the function documentation -static int __multiple_quarter_curve_to( - int radius_w, - int radius_h, - int start, - int number) { - int data_idx; - - data_idx = start; - int l_number = number; - int l_radius_w = radius_w; - int l_radius_h = radius_h; - - if (l_number < 0) { - l_number = -l_number; - - if (1 == (data_idx & 1)) { - l_radius_h = -l_radius_h; - } else { - l_radius_w = -l_radius_w; - } - } - - if (1 == (data_idx & 1)) { - __set_quarter_curve_tangent_axis(__vertical); - } else { - __set_quarter_curve_tangent_axis(__horizontal); - } - - // Compute center - __ctxt.center_x = __ctxt.x - (l_radius_w * __quarter_curve_data[data_idx & (4 - 1)].x); - __ctxt.center_y = __ctxt.y + (l_radius_h * __quarter_curve_data[data_idx & (4 - 1)].y); - - while (0 != l_number) { - data_idx = (data_idx + 1) & (4 - 1); - - int next_x = __ctxt.center_x + (l_radius_w * __quarter_curve_data[data_idx & (4 - 1)].x); - int next_y = __ctxt.center_y - (l_radius_h * __quarter_curve_data[data_idx & (4 - 1)].y); - - (void)__quarter_curve_to(next_x, next_y); - --l_number; - } - - return __ctxt.offset; -} - -// See the section 'Internal function definitions' for the function documentation -static int __approximate_ellipse_arc( - int radius_out_w, - int radius_out_h, - int radius_in_w, - int radius_in_h, - float32_t start_angle_rad, - float32_t arc_angle_rad, - int caps) { - - // Number of sections per curve. - // CircleArc approximation from Bezier curves is acceptable if the arc angle is less than 90 degrees. - // If the caller require and arc angle bigger than 90 degrees, - // the curve should be splited in sections of less than 90 degrees. - int nb_sections = (int) ceil(arc_angle_rad / (PI / 2)); - - // angle of one section - float32_t section_angle = arc_angle_rad / nb_sections; - - float32_t cos_start_angle = arm_cos_f32(start_angle_rad); - float32_t sin_start_angle = arm_sin_f32(start_angle_rad); - float32_t cos_end_angle = arm_cos_f32(start_angle_rad + arc_angle_rad); - float32_t sin_end_angle = arm_sin_f32(start_angle_rad + arc_angle_rad); - - float32_t tangent = 4 * mej_tan_f32(section_angle/4) / 3; - - // Compute outside start point - int16_t out_start_x = (int16_t) (+radius_out_w * cos_start_angle); - int16_t out_start_y = (int16_t) (-radius_out_h * sin_start_angle); - - // Compute inside start point - int16_t in_start_x = (int16_t) (+radius_in_w * cos_start_angle); - int16_t in_start_y = (int16_t) (-radius_in_h * sin_start_angle); - - // Compute outside end point - int16_t out_end_x = (int16_t) (+radius_out_w * cos_end_angle); - int16_t out_end_y = (int16_t) (-radius_out_h * sin_end_angle); - - // Compute inside end point - int16_t in_end_x = (int16_t) (+radius_in_w * cos_end_angle); - int16_t in_end_y = (int16_t) (-radius_in_h * sin_end_angle); - - // Move to beginning - (void)__move_to(out_start_x, out_start_y); - - // Compute first (going) curve - for (int i = 0; i < nb_sections; i++) { - float32_t section_start_angle = start_angle_rad + (i * section_angle); - float32_t section_end_angle = start_angle_rad + (i+1) * section_angle; - (void)__approximate_ellipse_arc_fragment( - 0, 0, - radius_out_w, radius_out_h, - section_start_angle, section_end_angle, tangent, 0); - } - - // Compute end cap - int cap = MEJ_VGLITE_PATH_GET_CAPS_END(caps); - switch(cap) { - case DRAWING_ENDOFLINE_ROUNDED: - { - // Compute rounded cap - float32_t cap_start_angle = start_angle_rad + arc_angle_rad; - float32_t cap_end_angle = start_angle_rad + arc_angle_rad + PI; - uint16_t cap_x = (in_end_x + out_end_x) / 2; - uint16_t cap_y = (in_end_y + out_end_y) / 2; - // FIXME radius should depend on position of start/end points - uint16_t cap_radius = (uint16_t)((radius_out_w - radius_in_w) / 2); - (void)__approximate_ellipse_arc_fragment( - cap_x, cap_y, - cap_radius, cap_radius, - cap_start_angle, cap_end_angle, CAP_TAN, 0); - break; - } - case DRAWING_ENDOFLINE_NONE: - case DRAWING_ENDOFLINE_PERPENDICULAR: - { - // Compute line cap - (void)__line_to(in_end_x, in_end_y); - break; - } - default: - DISPLAY_IMPL_error(false, "Unknown cap: %d", cap); - break; - } - - // Compute second (return) curve - for (int i = 0; i < nb_sections; i++) { - float32_t section_start_angle = start_angle_rad + (nb_sections-1-i) * section_angle; - float32_t section_end_angle = start_angle_rad + (nb_sections-i) * section_angle; - (void)__approximate_ellipse_arc_fragment( - 0, 0, radius_in_w, radius_in_h, - section_start_angle, section_end_angle, tangent, 1); - } - - // Compute start cap - cap = MEJ_VGLITE_PATH_GET_CAPS_START(caps); - switch(cap) { - case DRAWING_ENDOFLINE_ROUNDED: - { - // Compute rounded cap - float32_t cap_start_angle = start_angle_rad + PI; - float32_t cap_end_angle = start_angle_rad; - uint16_t cap_x = (in_start_x + out_start_x) / 2; - uint16_t cap_y = (in_start_y + out_start_y) / 2; - // FIXME radius should depend on position of start/end points - uint16_t cap_radius = (uint16_t)((radius_out_w - radius_in_w) / 2); - (void)__approximate_ellipse_arc_fragment( - cap_x, cap_y, - cap_radius, cap_radius, - cap_start_angle, cap_end_angle, CAP_TAN, 0); - break; - } - case DRAWING_ENDOFLINE_NONE: - case DRAWING_ENDOFLINE_PERPENDICULAR: - // Compute line cap - (void)__line_to(out_start_x, out_start_y); - break; - default: - DISPLAY_IMPL_error(false, "Unknown cap: %d", cap); - break; - } - - // End path - return __end(); -} - -// See the section 'Internal function definitions' for the function documentation -static int __approximate_ellipse_arc_to( - int radius_w, - int radius_h, - float32_t start_angle, - float32_t end_angle) { - float32_t start_angle_temp; - float32_t end_angle_temp; - float32_t arc_angle; - float32_t arc_angle_temp; - float32_t arc_angle_abs; - - arc_angle = end_angle - start_angle; - - start_angle_temp = start_angle; - - arc_angle_abs = MEJ_ABS(arc_angle); - - while (arc_angle_abs > 0) { - arc_angle_temp = end_angle - start_angle_temp; - arc_angle_temp = MEJ_BOUNDS(arc_angle_temp, -(PI/2), +(PI/2)); - end_angle_temp = start_angle_temp + arc_angle_temp; - - (void)__approximate_ellipse_arc_fragment_to( - radius_w, radius_h, - start_angle_temp, - end_angle_temp); - - start_angle_temp += arc_angle_temp; - - arc_angle_abs -= PI/2; - } - - return __ctxt.offset; -} - -// See the section 'Internal function definitions' for the function documentation -static int __approximate_ellipse_arc_fragment_to( - int radius_w, - int radius_h, - float32_t start_angle, - float32_t end_angle) { - // End point angle - float32_t section_angle; - float32_t temp_x; - float32_t temp_y; - - // End point coordinates - int end_x; - int end_y; - - // Control point 1 coordinates - int c1_x; - int c1_y; - - // Control point 2 coordinates - int c2_x; - int c2_y; - - section_angle = end_angle - start_angle; - - // Compute start point - __compute_control_point( - &temp_x, &temp_y, - start_angle, - section_angle); - - c1_x = __ctxt.x + (int) (temp_x * radius_w); - c1_y = __ctxt.y + (int) (temp_y * radius_h); - - // Compute end point - __ctxt.sin = arm_sin_f32(end_angle); - __ctxt.cos = arm_cos_f32(end_angle); - - end_x = (int) (__ctxt.center_x + (radius_w * __ctxt.sin)); - end_y = (int) (__ctxt.center_y + (radius_h * -__ctxt.cos)); - - __compute_control_point( - &temp_x, &temp_y, - end_angle, - -section_angle); - - c2_x = end_x + (int) (temp_x * radius_w); - c2_y = end_y + (int) (temp_y * radius_h); - - return __cubic_to(c1_x, c1_y, c2_x, c2_y, end_x, end_y); -} - -// See the section 'Internal function definitions' for the function documentation -static int __approximate_ellipse_arc_fragment( - uint16_t center_x, uint16_t center_y, - int radius_w, int radius_h, - float32_t start_angle_rad, - float32_t end_angle_rad, - float32_t tangent, - int revert) { - float32_t tx; - float32_t ty; - - // Compute start point A1 & A2 - int16_t Ax = (int16_t) (radius_w * arm_cos_f32(start_angle_rad)); - int16_t Ay = (int16_t) (radius_h * -arm_sin_f32(start_angle_rad)); // minus because y axis is inverted (0,0 is top left) - - // Compute end point B1 & B2 - int16_t Bx = (int16_t) (radius_w * arm_cos_f32(end_angle_rad)); - int16_t By = (int16_t) (radius_h * -arm_sin_f32(end_angle_rad)); - - // Compute control point C - tx = tangent * arm_cos_f32(start_angle_rad + (PI/2)); - ty = tangent * -arm_sin_f32(start_angle_rad + (PI/2)); - - int16_t Cx = (int16_t) (Ax + (radius_w * tx)); - int16_t Cy = (int16_t) (Ay + (radius_h * ty)); - - // Compute control point D - tx = tangent * arm_cos_f32(end_angle_rad - (PI/2)); - ty = tangent * -arm_sin_f32(end_angle_rad - (PI/2)); - - int16_t Dx = (int16_t) (Bx + (radius_w * tx)); - int16_t Dy = (int16_t) (By + (radius_h * ty)); - - Ax += (int16_t)center_x; - Ay += (int16_t)center_y; - Bx += (int16_t)center_x; - By += (int16_t)center_y; - Cx += (int16_t)center_x; - Cy += (int16_t)center_y; - Dx += (int16_t)center_x; - Dy += (int16_t)center_y; - - // Compute path - return (revert == 0) ? - __cubic_to(Cx, Cy, Dx, Dy, Bx, By) : - __cubic_to(Dx, Dy, Cx, Cy, Ax, Ay); -} - -// See the section 'Internal function definitions' for the function documentation -int __cubic_to( - int16_t cx1, - int16_t cy1, - int16_t cx2, - int16_t cy2, - int16_t x, - int16_t y) -{ - // cppcheck-suppress [misra-c2012-11.3] cast to (path_cubic_to_s16_t *) is valid - path_cubic_to_s16_t *cubic_to = (path_cubic_to_s16_t *) &__ctxt.path[__ctxt.offset]; - - cubic_to->cmd = VGLITE_CUBIC_CMD; - cubic_to->cx1 = cx1; // control point 1 - cubic_to->cy1 = cy1; // control point 1 - cubic_to->cx2 = cx2; // control point 2 - cubic_to->cy2 = cy2; // control point 2 - cubic_to->x = x; // curve end - cubic_to->y = y; // curve end - - __ctxt.x = x; - __ctxt.y = y; - __ctxt.offset += (int)MEJ_VGLITE_PATH_CUBIC_TO_LENGTH(s16_t); - - return __ctxt.offset; -} - -// See the section 'Internal function definitions' for the function documentation -int __end(void) -{ - // cppcheck-suppress [misra-c2012-11.3] cast to (path_end_s16_t *) is valid - path_end_s16_t *end = (path_end_s16_t *) &__ctxt.path[__ctxt.offset]; - end->cmd = VGLITE_END_CMD; - - __ctxt.offset += (int)MEJ_VGLITE_PATH_END_LENGTH(s16_t); - - return __ctxt.offset; -} - -// See the section 'Internal function definitions' for the function documentation -int __update_path(vg_lite_path_t *path, - bool first_path, - bool last_path, - int left, - int top, - int right, - int bottom) { - - if (!first_path) { - path->bounding_box[0] = (int) MEJ_MIN(path->bounding_box[0], left); - path->bounding_box[1] = (int) MEJ_MIN(path->bounding_box[1], top); - path->bounding_box[2] = (int) MEJ_MAX(path->bounding_box[2], right); - path->bounding_box[3] = (int) MEJ_MAX(path->bounding_box[3], bottom); - } - else { - path->bounding_box[0] = left; - path->bounding_box[1] = top; - path->bounding_box[2] = right; - path->bounding_box[3] = bottom; - } - - path->quality = VG_LITE_HIGH; - path->format = VG_LITE_S16; - (void)memset(&path->uploaded, 0, - sizeof(path->uploaded)); - path->path_changed = 1; - path->path_type = VG_LITE_DRAW_FILL_PATH; - path->pdata_internal = 0; - - if (last_path) { - (void)__end(); - path->path_length = __ctxt.offset; - } - - return __ctxt.offset; -} - -// See the section 'Internal function definitions' for the function documentation -static float32_t __normalize_angle(float32_t angle) { - float32_t l_angle = fmod(angle, 360); - return (l_angle >= 0) ? l_angle : (l_angle + 360); -} - -// See the section 'Internal function definitions' for the function documentation -static vg_lite_error_t __drawer_vglite_draw_path( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color) { - return vg_lite_draw((vg_lite_buffer_t*)target, path, fill_rule, matrix, blend, color); -} - -// See the section 'Internal function definitions' for the function documentation -static vg_lite_error_t __drawer_vglite_draw_gradient( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_linear_gradient_t * grad, - vg_lite_blend_t blend) { - return vg_lite_draw_gradient((vg_lite_buffer_t*)target, path, fill_rule, matrix, grad, blend); -} - -// See the section 'Internal function definitions' for the function documentation -static vg_lite_error_t __drawer_vglite_blit_rect( - void* target, - vg_lite_buffer_t *source, - uint32_t *rect, - vg_lite_matrix_t *matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter) { - return vg_lite_blit_rect((vg_lite_buffer_t*)target, source, rect, matrix, blend, color, filter); -} - -// See the section 'Internal function definitions' for the function documentation -static vg_lite_error_t __drawer_vglite_blit( - void* target, - vg_lite_buffer_t *source, - vg_lite_matrix_t *matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter) { - return vg_lite_blit((vg_lite_buffer_t*)target, source, matrix, blend, color, filter); -} - -// See the section 'Internal function definitions' for the function documentation -static vg_lite_error_t __drawer_vglite_clear( - void* target, - vg_lite_rectangle_t *rectangle, - vg_lite_color_t color) { - return vg_lite_clear((vg_lite_buffer_t*)target, rectangle, color); -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/src/mej_math.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/src/mej_math.c deleted file mode 100644 index 9c763d6..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/util/src/mej_math.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * C - * - * Copyright 2019-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/* - * @file - * @brief MicroEJ MicroUI library low level API: implementation over VG-Lite - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include "mej_math.h" - -#include "fsl_powerquad.h" - -// ----------------------------------------------------------------------------- -// mej_math.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -float32_t mej_tan_f32(float32_t value) { - float32_t cos; - float32_t sin; - - PQ_CosF32(&value, &cos); - PQ_SinF32(&value, &sin); - - PQ_DivF32(&sin, &cos, &value); - - return value; -} - -// See the header file for the function documentation -float32_t mej_sqrt_f32(float32_t value) { - PQ_SqrtF32(&value, &value); - - return value; -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/freetype_bitmap_helper.h b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/freetype_bitmap_helper.h deleted file mode 100644 index 621f899..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/freetype_bitmap_helper.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * C - * - * Copyright 2021-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/** - * @file - * @brief Freetype bitmap helper implementation header for VectorGraphics Low Level API. - * @author MicroEJ Developer Team - * @version 2.0.0 - */ - -#ifndef FREETYPE_BITMAP_HELPER_H_ -#define FREETYPE_BITMAP_HELPER_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ - -#include - -#include -#include FT_FREETYPE_H -#include - -#include -#include - -/* Macros ------------------------------------------------------------------*/ - -/** - * The divider coefficient used to pass from 1/64th of pixels unit to pixels unit. - */ -#define METRICS_DIVISOR 6 - -#define FT_HELPER_X_MIN 0 /*!< The min start x coordinate to draw a glyph. */ -#define FT_HELPER_Y_MIN 0 /*!< The min start y coordinate to draw a glyph. */ - -#define FREETYPE_OK 0 /*!< Error code returned when function execution is successful. */ -#define FREETYPE_INTERNAL_ERROR -1 /*!< Error code returned when an error occurred after a call of a freetype function. */ -#define FREETYPE_NOT_IMPLEMENTED -2 /*!< Error code returned when the function is not implemented. */ - -#define TRANSFORM_MATRIX_POS_X 2 /*!< Position of the x coordinate inside the transform matrix when in 1D-array form. */ -#define TRANSFORM_MATRIX_POS_Y 5 /*!< Position of the y coordinate inside the transform matrix when in 1D-array form. */ - -/* Shift for the pixel red component for argb format. */ -#define FT_RED_SHIFT 16 -/* Shift for the pixel green component for argb format. */ -#define FT_GREEN_SHIFT 8 -/* Shift for the pixel blue component for argb format. */ -#define FT_BLUE_SHIFT 0 - - -/* Private Type Definitions ---------------------------------------------- */ - -/** - * @brief Data structure for pack all the variables required by freetype - * handler. - */ -typedef struct{ - FT_Library library; - FT_Face face; - FT_Error error; - FT_GlyphSlot slot; - FT_UInt glyph_index; - FT_Renderer renderer; - FT_Vector pen; -}Freetype_context_type; - -typedef struct transform_matrix { - float m[3][3]; /*! The 3x3 matrix itself, in [row][column] order. */ -} transform_matrix_t; - - -/* Public Function Prototypes ------------------------------------------------ */ - -/* - * @brief Returns the highest value between two integers. - * - * @param[in] X first integer to compare. - * @param[in] Y second integer to compare. - * - * @return X if it has the highest value, Y is returned otherwise. - */ -#define max(X, Y) (((X) > (Y)) ? (X) : (Y)) - -/* - * @brief Returns the lowest value between two integers. - * - * @param[in] X the first integer to compare. - * @param[in] Y the second integer to compare. - * - * @return X if it has the lowest value, Y is returned otherwise. - */ -#define min(X, Y) (((X) < (Y)) ? (X) : (Y)) - -/** - * @brief Prints a string in a buffer respecting the clipping area of the MicroUI Graphics Context. - * - * @param[in] gc Pointer to MicroUI GraphicsContext. - * @param[in] freetype_context The Freetype context with font face data. - * @param[in] string Pointer of the string. - * @param[in] s_size Lenght of the string in characters. - * @param[in] x The X coordinate in the frame-buffer pointer. - * @param[in] y The Y coordinate in the frame-buffer pointer. - * @param[in] color The 32 bits ARGB color of the string. - * @param[in] alpha The opacity coefficient. - * @param[in] size The character size. - * @param[in] blend the blend mode to use - * @param[in] letterSpacing the extra letter spacing to use - * - * @return FREETYPE_OK code if success, otherwise there is an error. - */ -int ft_helper_print_jstring_clipped(MICROUI_GraphicsContext* gc, Freetype_context_type *freetype_context, jchar* string, jint s_size, jint x, jint y, jint color, jint alpha, jfloat size, jint blend, jfloat letterSpacing); - -/** - * @brief Writes the current rendered glyph stored inside the Freetype context into the frame-buffer respecting the clipping area of the MicroUI Graphics Context. - * - * @param[in] gc Pointer to MicroUI GraphicsContext. - * @param[in] freetype_context The Freetype context with glyph data. - * @param[in] x The X coordinate in the frame-buffer pointer. - * @param[in] y The Y coordinate in the frame-buffer pointer. - * @param[in] color The 32 bits ARGB color of the glyph. - * @param[in] alpha The opacity coefficient. - */ -static void ft_helper_write_to_framebuffer_clipped(MICROUI_GraphicsContext* gc, Freetype_context_type *freetype_context, jint x, jint y, jint color, jint alpha); - - -/** - * @brief Frees all Freetype data context. - * - * @param[in] Freetype context of the job. - */ -void ft_helper_free(Freetype_context_type *freetype_context); - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#ifdef __cplusplus - } -#endif - -#endif // FREETYPE_BITMAP_HELPER_H_ diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_vglite_helper.h b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_vglite_helper.h deleted file mode 100644 index b0aa3d6..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/inc/microvg_vglite_helper.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -#if !defined MICROVG_VGLITE_HELPER_H -#define MICROVG_VGLITE_HELPER_H - -/** -* @file -* @brief MicroVG library low level API -* @author MicroEJ Developer Team -* @version 3.0.0 -*/ - -#if defined __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include -#include - -#include "vg_lite.h" - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -/* - * @brief The vglite matrix can be mapped on a float array - */ -#define MAP_VGLITE_MATRIX(h) ((float*)(((vg_lite_matrix_t*)(h))->m)) - -/* - * @brief The vglite gradient matrix can be mapped on a float array - */ -#define MAP_VGLITE_GRADIENT_MATRIX(h) MAP_VGLITE_MATRIX(&(((vg_lite_linear_gradient_t*)(h))->matrix)) - -// ----------------------------------------------------------------------------- -// API -// ----------------------------------------------------------------------------- - -/* - * @brief Converts the MicroVG blend in a VG-Lite blend. - * - * @param[in] blend: the drawing's blending - * - * @return the VG-Lite blend - */ -vg_lite_blend_t MICROVG_VGLITE_HELPER_get_blend(jint blend); - -/* - * @brief Converts the MicroVG fill rule in a VG-Lite rule. - * - * @param[in] blend: the drawing's fill rule - * - * @return the VG-Lite fill rule - */ -vg_lite_fill_t MICROVG_VGLITE_HELPER_get_fill_rule(jint fill_type); - -/* - * @brief Converts a MicroVG LinearGradient in a VG-Lite gradient according to - * the drawing parameters. After this call, the gradient is ready to be updated - * by calling vg_lite_update_grad() - * - * @param[in] gradient: the gradient destination (VG-Lite gradient) - * @param[in] gradientData: the gradient source - * @param[in] matrix: the gradient source's matrix - * @param[in] globalMatrix: the drawing's matrix - * @param[in] globalAlpha: the drawing's opacity - * - * @return a VG-Lite error code - */ -vg_lite_error_t MICROVG_VGLITE_HELPER_to_vg_lite_gradient(vg_lite_linear_gradient_t* gradient, jint* gradientData, jfloat* matrix, jfloat* globalMatrix, jint globalAlpha); - -/* - * @brief Configures the vg_lite's scissor according to the MicroUI clip. - * - * If the clip is empty, the drawing is useless. In that case the LLUI_DISPLAY's - * drawing status is updated and this function returns false. - * - * Otherwise the VG-Lite scissor is configured to match the MicroUI clip. - * - * @param[in] gc: the destination where performing the drawing (MicroUI Graphics Context) - * - * @return false when the drawing is useless (bounds out of clip) - */ -bool MICROVG_VGLITE_HELPER_enable_vg_lite_scissor(MICROUI_GraphicsContext* gc); - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#ifdef __cplusplus -} -#endif - -#endif // !defined MICROVG_VGLITE_HELPER_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_BVI_impl.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_BVI_impl.c deleted file mode 100644 index 6e8b856..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_BVI_impl.c +++ /dev/null @@ -1,1079 +0,0 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/** - * @file - * @brief MicroEJ MicroVG library low level API: implementation of buffered - * vector images (BVI). - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include "display_configuration.h" - -/** - * The buffered vector image feature is only available when the VGLITE multiple drawer option - * is enabled. - */ -#if defined VGLITE_USE_MULTIPLE_DRAWERS - -#include -#include - -#include -#include -#include -#include -#include - -#include "bsp_util.h" -#include "vg_lite.h" -#include "vg_lite_kernel.h" -#include "display_vglite.h" -#include "vglite_path.h" -#include "microvg_vglite_helper.h" -#include "microvg_helper.h" - -#include "fsl_debug_console.h" - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -/* - * @brief MicroUI format to Buffered vector Image format - */ -#define BVI_FORMAT (MICROUI_IMAGE_FORMAT_CUSTOM_4) // hardcoded in Java lib -#define IS_BVI(image) (BVI_FORMAT == (MICROUI_ImageFormat)((image)->format)) -#define MAP_BVI(image) (BVI_resource*)LLUI_DISPLAY_getBufferAddress((image)) - -/* - * @brief Allocator management - */ -#define HEAP_SIZE (56 * 1024) -#define HEAP_START (&allocator_heap[0]) -#define HEAP_END (&allocator_heap[HEAP_SIZE]) -#define MALLOC(s) (BESTFIT_ALLOCATOR_allocate(&allocator_instance, VG_LITE_ALIGN((s), 4))) -#define FREE(s) (BESTFIT_ALLOCATOR_free(&allocator_instance, (s))) - -/* - * @brief The vglite matrix can be mapped on a float array - */ -#define MAP_TO_VGLITE_MATRIX(m) ((vg_lite_matrix_t*)(m)) - -// -------------------------------------------------------------------------------- -// Foundation library's native functions names redefinition -// -------------------------------------------------------------------------------- - -#define LLVG_BVI_IMPL_draw Java_ej_microvg_BufferedVectorImageNatives_draw -#define LLVG_BVI_IMPL_clear Java_ej_microvg_BufferedVectorImageNatives_clear - -// ----------------------------------------------------------------------------- -// Types -// ----------------------------------------------------------------------------- - -/* - * @brief Types of image's elements. - */ -typedef enum vglite_element_kind { - - VGLITE_DRAW_PATH, - VGLITE_DRAW_GRADIENT, - VGLITE_BLIT, - VGLITE_BLIT_RECT, - -} vglite_element_kind_t; - -/* - * @brief Defines a buffered image's element. - */ -typedef struct vglite_element { - - // pointer to the next element in the image - struct vglite_element* next; - - // element's kind and pointer to specific element's data - vglite_element_kind_t kind; - void* operation; - - // common element's data for all VG drawings - vg_lite_matrix_t* matrix; - int32_t* scissor; - vg_lite_blend_t blend; - -} vglite_element_t; - -/* - * @brief Element "draw VG path". - */ -typedef struct vglite_operation_path { - - vg_lite_path_t* path; - vg_lite_color_t color; - vg_lite_fill_t fill_rule; - -} vglite_operation_path_t; - -/* - * @brief Element "draw VG gradient". - */ -typedef struct vglite_operation_gradient { - - vg_lite_path_t* path; - vg_lite_linear_gradient_t* gradient; - vg_lite_fill_t fill_rule; - -} vglite_operation_gradient_t; - -/* - * @brief Element "blit image (rect or not)". - */ -typedef struct vglite_operation_blit { - - vg_lite_buffer_t* buffer; - uint32_t* blit_rect; - vg_lite_color_t color; - vg_lite_filter_t filter; - -} vglite_operation_blit_t; - -/* - * @brief Structure to load a resource by calling SNIX_get_resource() - */ -typedef struct { - - // pointer on the first commands buffer - vglite_element_t* vglite_element_first; - - // pointer on the next commands buffer - vglite_element_t* vglite_element_next; - -} BVI_resource; - -// ----------------------------------------------------------------------------- -// Extern functions & fields -// ----------------------------------------------------------------------------- - -/* - * @brief Function to retrieve the current scissor. - */ -extern uint32_t vg_lite_get_scissor(int32_t** scissor); - -/* - * @brief Linker symbols that define the ROM block. - */ -extern uint32_t m_text_start; -extern uint32_t m_text_end; - -// ----------------------------------------------------------------------------- -// Internal function definitions -// ----------------------------------------------------------------------------- - -static vg_lite_error_t _add_draw_path( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color) ; - -static vg_lite_error_t _add_draw_gradient( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_linear_gradient_t * grad, - vg_lite_blend_t blend) ; - -static vg_lite_error_t _add_blit_rect( - void* target, - vg_lite_buffer_t *source, - uint32_t *rect, - vg_lite_matrix_t *matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter) ; - -static vg_lite_error_t _add_blit( - void* target, - vg_lite_buffer_t *source, - vg_lite_matrix_t *matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter) ; - -static vg_lite_error_t _add_clear( - void* target, - vg_lite_rectangle_t *rectangle, - vg_lite_color_t color) ; - -static void __get_original_color(vg_lite_color_t* color, vg_lite_blend_t blend) ; - -static void __get_original_gradient(vg_lite_linear_gradient_t* gradient, vg_lite_blend_t blend) ; - -static DRAWING_Status __post_drawing(vg_lite_error_t vg_lite_error) ; - -// ----------------------------------------------------------------------------- -// Global Variables -// ----------------------------------------------------------------------------- - -static BESTFIT_ALLOCATOR allocator_instance; -static uint8_t allocator_heap[HEAP_SIZE]; -static bool initialiazed = false; - -/* - * @brief Matrix used to render a path in order to not alterate the original path's matrix. - */ -static vg_lite_matrix_t render_matrix; - -static VG_DRAWER_drawer_t image_drawer = { - - _add_draw_path, - _add_draw_gradient, - _add_blit_rect, - _add_blit, - _add_clear, - - __get_original_color, - __get_original_gradient, - - __post_drawing, -}; - -/* - * @brief Gradient used for all drawings with gradient (only one image allocation, - * does not alterate the original gradient's matrix and colors, etc.). - */ -static vg_lite_linear_gradient_t gradient; - -// ----------------------------------------------------------------------------- -// Private functions to store a VG drawing -// ----------------------------------------------------------------------------- - -/* - * @brief Frees the given data from the heap or does nothing - * when targets RO memory. - * - * @param[in] data: pointer on the data to free. - */ -static void _free_data(void* data) { - if ((NULL != data) && !((data > &m_text_start) && (data < &m_text_end))) { - if ((data > (void*) HEAP_START) && (data < (void*) HEAP_END) ) { - FREE(data); - } - else { - MEJ_LOG_ERROR_MICROVG("Invalid memory pointer: 0x%x is not in HEAP section.\n", data); - } - } - // else: data in flash or null -} - -/* - * @brief Allocates the given size in the heap . - * - * @param[in] size: the data's size (in bytes). - * - * @return the pointer to the stored data. - */ -inline static uint8_t* _alloc_data(uint32_t size) { - uint8_t* ret = MALLOC(size); - if (NULL == ret) { - MEJ_LOG_ERROR_MICROVG("OOM\n"); - } - return ret; -} - -/* - * @brief Stores the given data in the heap or return the given pointer - * when targets RO memory (no need to copy). - * - * @param[in] data: pointer on the data to store. - * @param[in] size: the data's size. - * - * @return the pointer to the stored data or the ROM address. - */ -static uint8_t* _store_data(void* data, uint32_t size) { - uint8_t* ret; - if ((data > &m_text_start) && (data < &m_text_end)) { - // cppcheck-suppress [misra-c2012-11.5] cast the object in a u8 address - ret = (uint8_t*)data; - } - else { - ret = _alloc_data(size); - (void)memcpy((void*)ret, data, size); - } - return ret; -} - -/* - * @brief Stores the given rectangle in the heap. A rectangle is an array of 4 integers. - * - * @param[in] rect: pointer on the rectangle to store. - * - * @return the pointer to the stored rectangle. - */ -static uint32_t* _store_rectangle(uint32_t* rect) { - // cppcheck-suppress [misra-c2012-11.3] cast is possible (operation has been allocated with 4-byte as alignment) - return (NULL != rect) ? (uint32_t*)_store_data((void*)rect, (uint32_t)4 * sizeof(uint32_t)) : NULL; -} -static void _free_rectangle(uint32_t* rect) { - _free_data(rect); -} - -/* - * @brief Stores the given path in the heap. - * - * @param[in] path: pointer on the path to store. - * - * @return the pointer to the stored path. - */ -static vg_lite_path_t* _store_vglite_path(vg_lite_path_t * path) { - // store the path's header - vg_lite_path_t* stored_path = (vg_lite_path_t*)_store_data(path, sizeof(vg_lite_path_t)); - - // store the path's RAW data - stored_path->path = (void*)_store_data(path->path, path->path_length); - - return stored_path; -} -static void _free_vglite_path(vg_lite_path_t * path) { - _free_data(path->path); - _free_data(path); - path->path = NULL; -} - -/* - * @brief Stores the given gradient in the heap. - * - * @param[in] grad: pointer on the gradient to store. - * - * @return the pointer to the stored gradient. - */ -static vg_lite_linear_gradient_t* _store_vglite_gradient(vg_lite_linear_gradient_t * grad) { - return (vg_lite_linear_gradient_t*)_store_data(grad, sizeof(vg_lite_linear_gradient_t)); -} -static void _free_vglite_gradient(vg_lite_linear_gradient_t * grad) { - _free_data(grad); -} - -/* - * @brief Stores the given matrix in the heap. - * - * @param[in] matrix: pointer on the matrix to store. - * - * @return the pointer to the stored matrix. - */ -static vg_lite_matrix_t* _store_vglite_matrix(vg_lite_matrix_t * matrix) { - return (vg_lite_matrix_t*)_store_data(matrix, sizeof(vg_lite_matrix_t)); -} -static void _free_vglite_matrix(vg_lite_matrix_t * matrix) { - _free_data(matrix); -} - -static int32_t* _get_current_vglite_scissor(void) { - int32_t* scissor; - return ((uint32_t)0 != vg_lite_get_scissor(&scissor)) ? scissor : NULL; -} - -static int32_t* _store_vglite_scissor(int32_t* scissor) { - // cppcheck-suppress [misra-c2012-11.3] cast is possible (operation has been allocated with 4-byte as alignment) - return (NULL != scissor) ? (int32_t*)_store_data(scissor, (uint32_t)4*sizeof(int32_t)) : NULL; -} - -static void _free_vglite_scissor(int32_t* scissor) { - _free_data(scissor); -} - -/* - * @brief Stores the given buffer in the heap. It does not store the buffer's pixel (keep - * pointing on the original buffer's pixel). - * - * @param[in] buffer: pointer on the buffer to store. - * - * @return the pointer to the stored buffer. - */ -static vg_lite_buffer_t* _store_vglite_buffer(vg_lite_buffer_t* buffer) { - return (vg_lite_buffer_t*)_store_data(buffer, sizeof(vg_lite_buffer_t)); -} -static void _free_vglite_buffer(vg_lite_buffer_t* buffer) { - _free_data(buffer); -} - -/* - * @brief Allocates an image element and resets it. - * - * @return the pointer to the allocated element. - */ -static vglite_element_t* _malloc_element(void) { - // cppcheck-suppress [misra-c2012-11.3] cast is possible (operation has been allocated with 4-byte as alignment) - vglite_element_t* elem = (vglite_element_t*)_alloc_data(sizeof(vglite_element_t)); - elem->next = NULL; - elem->operation = NULL; - return elem; -} - -inline static vglite_operation_path_t* get_operation_path(void* op) { - // cppcheck-suppress [misra-c2012-11.5] cast is possible (operation has been allocated with 4-byte as alignment) - return (vglite_operation_path_t*)op; -} - -inline static vglite_operation_gradient_t* get_operation_gradient(void* op) { - // cppcheck-suppress [misra-c2012-11.5] cast is possible (operation has been allocated with 4-byte as alignment) - return (vglite_operation_gradient_t*)op; -} - -inline static vglite_operation_blit_t* get_operation_blit(void* op) { - // cppcheck-suppress [misra-c2012-11.5] cast is possible (operation has been allocated with 4-byte as alignment) - return (vglite_operation_blit_t*)op; -} - -inline static BVI_resource* get_target(void* target) { - // cppcheck-suppress [misra-c2012-11.5] cast is possible (the target stored in drawer is a BVI_resource* for sure) - return (BVI_resource*)target; -} - -/* - * @brief Stores the given element in the image. - * - * @param[in] bvi: pointer on image. - * @param[in] operation: pointer on the specific element's data. - * @param[in] kind: type of element. - * @param[in] matrix: pointer on the matrix to store. - * @param[in] blend: blending to apply. - */ -static void _store_element(BVI_resource* bvi, void* operation, vglite_element_kind_t kind, vg_lite_matrix_t * matrix, vg_lite_blend_t blend, int32_t* scissor) { - - vglite_element_t* elem = bvi->vglite_element_next; - - // store operation - elem->kind = kind; - elem->operation = operation; - - // store operation rules - elem->matrix = _store_vglite_matrix(matrix); - elem->scissor = _store_vglite_scissor(scissor); - elem->blend = blend; - - // prepare next element - bvi->vglite_element_next = _malloc_element(); - elem->next = bvi->vglite_element_next; -} - -static void _free_operation(void* operation, vglite_element_kind_t kind) { - - switch(kind) { - case VGLITE_DRAW_PATH: { - vglite_operation_path_t* op = get_operation_path(operation); - _free_vglite_path(op->path); - op->path = NULL; - } - break; - case VGLITE_DRAW_GRADIENT: { - vglite_operation_gradient_t* op = get_operation_gradient(operation); - _free_vglite_path(op->path); - _free_vglite_gradient(op->gradient); - op->path = NULL; - op->gradient = NULL; - - } - break; - case VGLITE_BLIT: - case VGLITE_BLIT_RECT: { - vglite_operation_blit_t* op = get_operation_blit(operation); - _free_vglite_buffer(op->buffer); - _free_rectangle(op->blit_rect); - op->buffer = NULL; - op->blit_rect = NULL; - } - break; - default: - MEJ_LOG_ERROR_MICROVG("unknown operation: %u\n", kind); - break; - } - - _free_data(operation); -} - -static vglite_element_t* _free_element(vglite_element_t* elem) { - - vglite_element_t* ret = NULL; - - if (NULL != elem->operation) { - - ret = elem->next; - - _free_vglite_matrix(elem->matrix); - _free_vglite_scissor(elem->scissor); - _free_operation(elem->operation, elem->kind); - - elem->matrix = NULL; - elem->scissor = NULL; - elem->operation = NULL; - elem->next = NULL; - - } - - _free_data(elem); - - return ret; -} - -// ----------------------------------------------------------------------------- -// Private functions to draw into a buffered vector image -// ----------------------------------------------------------------------------- - -/* - * @brief Transform a 2D point by a given matrix. - * - * Copy from vg_lite.c - */ -static void _transform_point(vg_lite_point_t * result, vg_lite_float_t x, vg_lite_float_t y, vg_lite_matrix_t * matrix) { - - /* Transform w. */ - vg_lite_float_t pt_w = (x * matrix->m[2][0]) + (y * matrix->m[2][1]) + matrix->m[2][2]; - if (pt_w <= 0.0f) { - result->x = 0; - result->y = 0; - } - else { - /* Transform x and y. */ - vg_lite_float_t pt_x = (x * matrix->m[0][0]) + (y * matrix->m[0][1]) + matrix->m[0][2]; - vg_lite_float_t pt_y = (x * matrix->m[1][0]) + (y * matrix->m[1][1]) + matrix->m[1][2]; - - /* Compute projected x and y. */ - result->x = (int)(pt_x / pt_w); - result->y = (int)(pt_y / pt_w); - } -} - -/* - * @brief Gets the top-left and bottom-right points scissor points adjusted with the given matrix. - * - * @param[in] scissor: pointer on the scissor (not NULL). - * @param[in] matrix: pointer on the matrix to apply on the scissor. - * @param[in] matrix: pointer on the top-left point to fill. - * @param[in] matrix: pointer on the bottom-right point to fill. - */ -static inline void _get_scissor_points(int32_t* scissor, vg_lite_matrix_t *matrix, vg_lite_point_t* top_left, vg_lite_point_t* bottom_right) { - _transform_point(top_left, (vg_lite_float_t)scissor[0], (vg_lite_float_t)scissor[1], matrix); - _transform_point(bottom_right, (vg_lite_float_t)(scissor[0] + scissor[2] - 1), (vg_lite_float_t)(scissor[1] + scissor[3] - 1), matrix); -} - -/* - * @brief Applies the scissor. The scissor is adjusted with the given matrix (image's matrix) - * and the target's bounds. - * - * @param[in] gc: pointer on the target. - * @param[in] scissor: pointer on the scissor to apply or NULL. - * @param[in] matrix: pointer on the matrix to apply on the scissor. - * - * @return false when the drawing is useless (empty scissor), true otherise. - */ -static bool _apply_scissor(MICROUI_GraphicsContext* gc, int32_t* scissor, vg_lite_matrix_t *matrix) { - - bool draw = true; - - vg_lite_enable_scissor(); - - if (NULL != scissor) { - vg_lite_point_t top_left; - vg_lite_point_t bottom_right; - - _get_scissor_points(scissor, matrix, &top_left, &bottom_right); - - if (top_left.x < gc->clip_x1) { - top_left.x = gc->clip_x1; - } - if (top_left.y < gc->clip_y1) { - top_left.y = gc->clip_y1; - } - if (bottom_right.x >= gc->clip_x2) { - bottom_right.x = gc->clip_x2; - } - if (bottom_right.y >= gc->clip_y2) { - bottom_right.y = gc->clip_y2; - } - - if ((top_left.x <= bottom_right.x) && (top_left.y <= bottom_right.y)) { - vg_lite_set_scissor(top_left.x, top_left.y, bottom_right.x - top_left.x + 1, bottom_right.y - top_left.y + 1); - } - else { - // empty clip - draw = false; - } - } - else { - vg_lite_set_scissor(gc->clip_x1, gc->clip_y1, gc->clip_x2 - gc->clip_x1 + 1, gc->clip_y2 - gc->clip_y1 + 1); - } - - return draw; -} - -/* - * @brief Derives the scissor. The scissor is adjusted with the given matrix. - * - * @param[in] scissor: pointer on the scissor to apply (not NULL). - * @param[in] matrix: pointer on the matrix to apply on the scissor. - */ -static void _derive_scissor(int32_t* scissor, vg_lite_matrix_t *matrix) { - - vg_lite_point_t top_left; - vg_lite_point_t bottom_right; - _get_scissor_points(scissor, matrix, &top_left, &bottom_right); - - scissor[0] = top_left.x; - scissor[1] = top_left.y; - scissor[2] = bottom_right.x - top_left.x + 1; - scissor[3] = bottom_right.y - top_left.y + 1; -} - -/* - * @brief Applies the given matrix (image's matrix) on the element's matrix. - * - * Copy from vg_lite.c - * - * TODO / IDEAS - * - flag matrix identity in elem - * - flag matrix identity in global param - * - check if matrix param has changed and save result in other struct element (prevent mul) - * - * @param[in] result: pointer on the matrix where storing the result. - * @param[in] elem_matrix: pointer on the element's matrix. - * @param[in] matrix: pointer on the matrix to apply on the element's matrix. - */ -static void _apply_matrix(vg_lite_matrix_t* result, vg_lite_matrix_t* elem_matrix, vg_lite_matrix_t* matrix) { - /* Process all rows. */ - for (int row = 0; row < 3; row++) { - /* Process all columns. */ - for (int column = 0; column < 3; column++) { - /* Compute matrix entry. */ - result->m[row][column] = - (matrix->m[row][0] * elem_matrix->m[0][column]) - + (matrix->m[row][1] * elem_matrix->m[1][column]) - + (matrix->m[row][2] * elem_matrix->m[2][column]); - } - } -} - -/* - * @brief Applies the global opacity on each color of given gradient operation. - * - * @param[in] gradient: the gradient operation. - * @param[in] alpha: the opacity. - * - * @return the new color. - */ -static void _apply_alpha_on_gradient(vg_lite_linear_gradient_t* gradient, uint32_t alpha) { - if (alpha != (uint32_t)0xff) { - uint32_t *colors = (uint32_t *)gradient->colors; - for(int i = 0; i < gradient->count; i++) { - colors[i] = MICROVG_HELPER_apply_alpha(colors[i], alpha); - } - } - // else: no need to apply alpha -} - -static void _draw_in_pixel_buffer(MICROUI_GraphicsContext* gc, BVI_resource* source, vg_lite_matrix_t* matrix, uint32_t alpha) { - - VG_DRAWER_drawer_t* drawer = VGLITE_PATH_get_vglite_drawer(gc); - vglite_element_t* elem = (vglite_element_t*)source->vglite_element_first; - bool draw_gradient_flushed = true; // no drawing with gradient has been added yet - - while(NULL != elem->operation) { - - if (_apply_scissor(gc, elem->scissor, matrix)) { - - // update the path's matrix - _apply_matrix(&render_matrix, elem->matrix, matrix); - - switch(elem->kind) { - case VGLITE_DRAW_PATH: { - vglite_operation_path_t* op = get_operation_path(elem->operation); - vg_lite_color_t color = MICROVG_HELPER_apply_alpha(op->color, alpha); - drawer->update_color(&color, elem->blend); - VG_DRAWER_draw_path(drawer, op->path, op->fill_rule, &render_matrix, elem->blend, color); - } - break; - case VGLITE_DRAW_GRADIENT: { - vglite_operation_gradient_t* op = get_operation_gradient(elem->operation); - - // copy the gradient content but not the image that renders the gradient - size_t copy_size = sizeof(vg_lite_linear_gradient_t) - sizeof(vg_lite_buffer_t); - - // copy op's gradient in a local gradient to apply the opacity - vg_lite_linear_gradient_t local_gradient; - (void)memcpy(&local_gradient, op->gradient, copy_size); - _apply_alpha_on_gradient(&local_gradient, alpha); - - if (0 != memcmp(&gradient, &local_gradient, copy_size)) { - // not same gradient than previous: have to: - - // 1- flush the previous gradient drawings because we will update the shared gradient's image - if (!draw_gradient_flushed) { - DISPLAY_VGLITE_start_operation(false); - } - - // 2- copy the new gradient data in shared gradient - (void)memcpy(&gradient, &local_gradient, copy_size); - - // 3- update the shared gradient's image. - drawer->update_gradient(&gradient, elem->blend); - } - // else: same gradient than previous: no need to update gradient's image again - - // update the gradient's matrix - _apply_matrix(&(gradient.matrix), &(op->gradient->matrix), matrix); - - VG_DRAWER_draw_gradient(drawer, op->path, op->fill_rule, &render_matrix, &gradient, elem->blend); - draw_gradient_flushed = false; - } - break; - case VGLITE_BLIT: { - vglite_operation_blit_t* op = get_operation_blit(elem->operation); - vg_lite_color_t color = MICROVG_HELPER_apply_alpha(op->color, alpha); - drawer->update_color(&color, elem->blend); - VG_DRAWER_blit(drawer, op->buffer, &render_matrix, elem->blend, color, op->filter); - } - break; - case VGLITE_BLIT_RECT: { - vglite_operation_blit_t* op = get_operation_blit(elem->operation); - vg_lite_color_t color = MICROVG_HELPER_apply_alpha(op->color, alpha); - drawer->update_color(&color, elem->blend); - VG_DRAWER_blit_rect(drawer, op->buffer, op->blit_rect, &render_matrix, elem->blend, color, op->filter); - } - break; - default: - MEJ_LOG_ERROR_MICROVG("unknown operation: %u\n", elem->kind); - break; - } - } - elem = elem->next; - } - - // flush all operations - DISPLAY_VGLITE_start_operation(true); -} - -static void _draw_in_command_buffer(BVI_resource* target, BVI_resource* source, vg_lite_matrix_t* matrix, uint32_t alpha) { - - // have to copy all source's commands in target because the source commands list can be cleared - - vglite_element_t* elem = (vglite_element_t*)source->vglite_element_first; - - while(NULL != elem->operation) { - - // update the path's matrix - _apply_matrix(&render_matrix, elem->matrix, matrix); - - void* operation; - - - switch(elem->kind) { - case VGLITE_DRAW_PATH: { - - vglite_operation_path_t* op_source = get_operation_path(elem->operation); - vglite_operation_path_t* op_dest = get_operation_path(_alloc_data(sizeof(vglite_operation_path_t))); - operation = (void*)op_dest; - - op_dest->path = _store_vglite_path(op_source->path); - op_dest->color = MICROVG_HELPER_apply_alpha(op_source->color, alpha); - op_dest->fill_rule = op_source->fill_rule; - } - break; - case VGLITE_DRAW_GRADIENT: { - vglite_operation_gradient_t* op_source = get_operation_gradient(elem->operation); - vglite_operation_gradient_t* op_dest = get_operation_gradient(_alloc_data(sizeof(vglite_operation_gradient_t))); - operation = (void*)op_dest; - - op_dest->path = _store_vglite_path(op_source->path); - op_dest->gradient = _store_vglite_gradient(op_source->gradient); - op_dest->fill_rule = op_source->fill_rule; - - // update the gradient's matrix and colors - _apply_matrix(&op_dest->gradient->matrix, &(op_source->gradient->matrix), matrix); - _apply_alpha_on_gradient(op_dest->gradient, alpha); - } - break; - case VGLITE_BLIT_RECT: - case VGLITE_BLIT: { - vglite_operation_blit_t* op_source = get_operation_blit(elem->operation); - vglite_operation_blit_t* op_dest = get_operation_blit(_alloc_data(sizeof(vglite_operation_blit_t))); - operation = (void*)op_dest; - - op_dest->buffer = _store_vglite_buffer(op_source->buffer); - op_dest->blit_rect = _store_rectangle(op_source->blit_rect); - op_dest->color = MICROVG_HELPER_apply_alpha(op_source->color, alpha); - op_dest->filter = op_source->filter; - } - break; - default: - MEJ_LOG_ERROR_MICROVG("unknown operation: %u\n", elem->kind); - break; - } - - vglite_element_t* new_elem = target->vglite_element_next; - _store_element(target, operation, elem->kind, &render_matrix, elem->blend, elem->scissor); - if (NULL != new_elem->scissor) { - _derive_scissor(new_elem->scissor, matrix); - } - - elem = elem->next; - } -} - -// ----------------------------------------------------------------------------- -// LLUI_DISPLAY_impl.h functions (FIXME) -// ----------------------------------------------------------------------------- - -void LLUI_DISPLAY_IMPL_adjustNewImageCharacteristics(jbyte image_format, uint32_t width, uint32_t height, uint32_t* data_size, uint32_t* data_alignment) { - (void)width; - (void)height; - (void)data_alignment; - *data_size = (BVI_FORMAT == (MICROUI_ImageFormat)image_format) ? (*data_size + sizeof(BVI_resource)) : *data_size /* unknown format */ ; -} - -void LLUI_DISPLAY_IMPL_initializeNewImage(MICROUI_Image* image) { - if (IS_BVI(image)) { - - if (!initialiazed) { - - // prepare the allocator - BESTFIT_ALLOCATOR_new(&allocator_instance); - // cppcheck-suppress [misra-c2012-11.4] force the cast to uint32_t - BESTFIT_ALLOCATOR_initialize(&allocator_instance, (uint32_t) HEAP_START, (uint32_t) HEAP_END); - - // prepare the gradient used by all draw_gradient - (void)memset(&gradient, 0, sizeof(vg_lite_linear_gradient_t)); - (void)vg_lite_init_grad(&gradient); // always success - gradient.image.format = VG_LITE_RGBA8888; // fix color format - - initialiazed = true; - } - - // map a struct on image data area - BVI_resource* bvi = MAP_BVI(image); - - bvi->vglite_element_first = _malloc_element(); - bvi->vglite_element_next = bvi->vglite_element_first; - } -} - -// ----------------------------------------------------------------------------- -// LLVG_BVI_impl.h functions (FIXME) -// ----------------------------------------------------------------------------- - -void LLVG_BVI_IMPL_clear(MICROUI_GraphicsContext* gc) { - - // cppcheck-suppress [misra-c2012-14.4] ignore warning - if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLVG_BVI_IMPL_clear)) { - - // map a struct on graphics context's pixel area - BVI_resource* bvi = MAP_BVI(&gc->image); - - vglite_element_t* elem = (vglite_element_t*)bvi->vglite_element_first; - - do { - elem = _free_element(elem); - } while(NULL != elem) ; - - bvi->vglite_element_first = _malloc_element(); - bvi->vglite_element_next = bvi->vglite_element_first; - - LLUI_DISPLAY_setDrawingStatus(DRAWING_DONE); - } -} - -void LLVG_BVI_IMPL_draw(MICROUI_GraphicsContext* gc, MICROUI_GraphicsContext* source, jint x, jint y, jfloat *matrix, uint32_t alpha) { - - if ((alpha > (uint32_t)0) && LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&LLVG_BVI_IMPL_draw)) { - - vg_lite_matrix_t vg_lite_matrix; - jfloat* mapped_matrix = MAP_VGLITE_MATRIX(&vg_lite_matrix); - - if((0 != x) || (0 != y)) { - // Create translate matrix for initial x,y translation from graphicscontext. - LLVG_MATRIX_IMPL_setTranslate(mapped_matrix, x, y); - LLVG_MATRIX_IMPL_concatenate(mapped_matrix, matrix); - } - else { - // use original matrix - LLVG_MATRIX_IMPL_copy(mapped_matrix, matrix); - } - - BVI_resource* bvi = MAP_BVI(&source->image); - - if (!IS_BVI(&gc->image)) { - _draw_in_pixel_buffer(gc, bvi, &vg_lite_matrix, alpha); - LLUI_DISPLAY_setDrawingStatus(DRAWING_RUNNING); - } - else { - _draw_in_command_buffer(MAP_BVI(&gc->image), bvi, &vg_lite_matrix, alpha); - LLUI_DISPLAY_setDrawingStatus(DRAWING_DONE); - } - } -} - -// ----------------------------------------------------------------------------- -// VGLITE Drawer redirection -// ----------------------------------------------------------------------------- - -static vg_lite_error_t _add_draw_path( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color) { - - vglite_operation_path_t* op = get_operation_path(_alloc_data(sizeof(vglite_operation_path_t))); - op->path = _store_vglite_path(path); - op->color = color; - op->fill_rule = fill_rule; - - _store_element(get_target(target), (void*)op, VGLITE_DRAW_PATH, matrix, blend, _get_current_vglite_scissor()); - return VG_LITE_SUCCESS; -} - -static vg_lite_error_t _add_draw_gradient( - void* target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_linear_gradient_t * grad, - vg_lite_blend_t blend) { - - vglite_operation_gradient_t* op = get_operation_gradient(_alloc_data(sizeof(vglite_operation_gradient_t))); - op->path = _store_vglite_path(path); - op->gradient = _store_vglite_gradient(grad); - op->fill_rule = fill_rule; - - _store_element(get_target(target), (void*)op, VGLITE_DRAW_GRADIENT, matrix, blend, _get_current_vglite_scissor()); - return VG_LITE_SUCCESS; -} - -static vg_lite_error_t _add_blit_rect( - void* target, - vg_lite_buffer_t *source, - uint32_t *rect, - vg_lite_matrix_t *matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter) { - - vglite_operation_blit_t* op = get_operation_blit(_alloc_data(sizeof(vglite_operation_blit_t))); - op->buffer = _store_vglite_buffer(source); - op->blit_rect = _store_rectangle(rect); - op->color = color; - op->filter = filter; - - _store_element(get_target(target), (void*)op, VGLITE_BLIT_RECT, matrix, blend, _get_current_vglite_scissor()); - return VG_LITE_SUCCESS; -} - -static vg_lite_error_t _add_blit( - void* target, - vg_lite_buffer_t *source, - vg_lite_matrix_t *matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter) { - - vglite_operation_blit_t* op = get_operation_blit(_alloc_data(sizeof(vglite_operation_blit_t))); - op->buffer = _store_vglite_buffer(source); - op->blit_rect = NULL; - op->color = color; - op->filter = filter; - - _store_element(get_target(target), (void*)op, VGLITE_BLIT, matrix, blend, _get_current_vglite_scissor()); - return VG_LITE_SUCCESS; -} - -static vg_lite_error_t _add_clear( - void* target, - vg_lite_rectangle_t *rectangle, - vg_lite_color_t color) { - - // create a path that represents the rectangle because there is no API to clear a rectangle with a matrix - - int path_offset; - vg_lite_path_t shape_vg_path; - vg_lite_matrix_t matrix; - vg_lite_error_t ret; - - vg_lite_identity(&matrix); - - // Compute the rectangle shape path - vglite_path_rectangle_t rectangle_path; - shape_vg_path.path = &rectangle_path; - shape_vg_path.path_length = sizeof(rectangle_path); - path_offset = VGLITE_PATH_compute_rectangle(&shape_vg_path, 0, rectangle->x, rectangle->y, rectangle->width, rectangle->height, true); - - if (0 > path_offset) { - ret = VG_LITE_INVALID_ARGUMENT; - } - else { - ret = _add_draw_path( - target, - &shape_vg_path, - VG_LITE_FILL_EVEN_ODD, - &matrix, - VG_LITE_BLEND_SRC_OVER, - color - ); - } - - return ret; -} - -static void __get_original_color(vg_lite_color_t* color, vg_lite_blend_t blend) { - (void)color; - (void)blend; - // nothing to do -} - -static void __get_original_gradient(vg_lite_linear_gradient_t* gradient, vg_lite_blend_t blend) { - (void)gradient; - (void)blend; - // nothing to do -} - -static DRAWING_Status __post_drawing(vg_lite_error_t vg_lite_error) { - (void)vg_lite_error; - // TODO manage OOM - return DRAWING_DONE; -} - -// ----------------------------------------------------------------------------- -// Replace default drawer -// ----------------------------------------------------------------------------- - -VG_DRAWER_drawer_t* VG_DRAWER_get_drawer(MICROUI_GraphicsContext* gc){ - - VG_DRAWER_drawer_t* drawer; - - if (!IS_BVI(&gc->image)) { - drawer = VGLITE_PATH_get_vglite_drawer(gc); - } - else { - // don't care about caller's drawer configuration - // see _draw_in_pixel_buffer() - image_drawer.target = (void*)MAP_BVI(&gc->image); - drawer = &image_drawer; - } - - return drawer; -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#endif // VGLITE_USE_MULTIPLE_DRAWERS diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_FONT_PAINTER_freetype_bitmap.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_FONT_PAINTER_freetype_bitmap.c deleted file mode 100644 index b45467f..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_FONT_PAINTER_freetype_bitmap.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * C - * - * Copyright 2021-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/** -* @file -* @brief MicroEJ VectorGraphics library low level API -* @author MicroEJ Developer Team -* @version 2.0.0 -*/ - -#include "microvg_configuration.h" - -#if defined (VG_FEATURE_FONT) && defined (VG_FEATURE_FONT_FREETYPE_BITMAP) && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_BITMAP) - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include -#include "ft2build.h" - -#include -#include -#include -#include -#include -#include -#include - -#include "microvg_font_freetype.h" -#include "microvg_helper.h" -#include "freetype_bitmap_helper.h" -#include "bsp_util.h" - -// ----------------------------------------------------------------------------- -// Macros -// --------------------------------------------------------------------------- - - -// ----------------------------------------------------------------------------- -// Types -// ----------------------------------------------------------------------------- - - -// ----------------------------------------------------------------------------- -// Extern variables -// ----------------------------------------------------------------------------- - -extern FT_Library library; -extern FT_Renderer renderer; - -// ----------------------------------------------------------------------------- -// Global Variables -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- -// Internal function definitions -// ----------------------------------------------------------------------------- - -/** - * @brief Sub-function used to draw a string in the frame buffer. - * - * @param[in] gc Pointer to MicroUI GraphicsContext. - * @param[in] face The font face reference. - * @param[in] size The height of the text in pixels. - * @param[in] text The pointer of the string to draw. - * @param[in] length The number of characters to draw from the array. - * @param[in] x The x coordinate of the anchor top-left point. - * @param[in] y The y coordinate of the anchor top-left point. - * @param[in] alpha The opacity coefficient. - * @param[in] blend the blend mode to use - * @param[in] letterSpacing the extra letter spacing to use - * @param[in] callback A function pointer that must points to the function that called this one. - * - * - */ -void __draw_string(MICROUI_GraphicsContext* gc, FT_Face face, jfloat size, jchar* text, jint length, jint x, jint y, jint alpha, jint blend, jfloat letterSpacing, SNI_callback callback); - - -// ----------------------------------------------------------------------------- -// LLVG_FONT_PAINTER API functions -// ----------------------------------------------------------------------------- - - -jint LLVG_FONT_PAINTER_IMPL_draw_string(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing){ - FT_Face face = (FT_Face) faceHandle; - int length = SNI_getArrayLength(text); - - // add matrix translation to x,y variables - int local_x = (int) (x + matrix[2]); - int local_y = (int) (y + matrix[5]); - - __draw_string(gc, face, size, text, length, (jint)local_x, (jint)local_y, alpha, blend, letterSpacing, (SNI_callback)&LLVG_FONT_PAINTER_IMPL_draw_string); - - return (jint)LLVG_SUCCESS; -} - - -jint LLVG_FONT_PAINTER_IMPL_draw_string_gradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix){ - SNI_throwNativeException(FREETYPE_NOT_IMPLEMENTED, "Native not implemented"); - - // Avoid unusued parameter in misra cppcheck - (void)(gc); - (void)(text); - (void)(faceHandle); - (void)(size); - (void)(x); - (void)(y); - (void)(matrix); - (void)(alpha); - (void)(blend); - (void)(letterSpacing); - (void)(gradientData); - (void)(gradientMatrix); - - return (jint)LLVG_DATA_INVALID; -} - -jint LLVG_FONT_PAINTER_IMPL_draw_string_on_circle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction){ - SNI_throwNativeException(FREETYPE_NOT_IMPLEMENTED, "Native not implemented"); - - // Avoid unusued parameter in misra cppcheck - (void)(gc); - (void)(text); - (void)(faceHandle); - (void)(size); - (void)(x); - (void)(y); - (void)(matrix); - (void)(alpha); - (void)(blend); - (void)(letterSpacing); - (void)(radius); - (void)(direction); - - return (jint)LLVG_DATA_INVALID; -} - -jint LLVG_FONT_PAINTER_IMPL_draw_string_on_circle_gradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix){ - SNI_throwNativeException(FREETYPE_NOT_IMPLEMENTED, "Native not implemented"); - - // Avoid unusued parameter in misra cppcheck - (void)(gc); - (void)(text); - (void)(faceHandle); - (void)(size); - (void)(x); - (void)(y); - (void)(matrix); - (void)(alpha); - (void)(blend); - (void)(letterSpacing); - (void)(radius); - (void)(direction); - (void)(gradientData); - (void)(gradientMatrix); - - return (jint)LLVG_DATA_INVALID; -} - - -// ----------------------------------------------------------------------------- -// Internal functions -// ----------------------------------------------------------------------------- - -void __draw_string(MICROUI_GraphicsContext* gc, FT_Face face, jfloat size, jchar* text, jint length, jint x, jint y, jint alpha, jint blend, jfloat letterSpacing, SNI_callback callback){ - Freetype_context_type local_freetype_context; - - if(!LLUI_DISPLAY_requestDrawing(gc, callback)){ - MEJ_LOG_INFO_MICROVG("request drawing declined \n"); - - } else { - - local_freetype_context.library = library; - local_freetype_context.renderer = renderer; - local_freetype_context.face = face; - - int char_height = (int)size; - local_freetype_context.error = FT_Set_Pixel_Sizes( local_freetype_context.face, 0, char_height); - if(FT_ERR(Ok) != local_freetype_context.error){ - MEJ_LOG_INFO_MICROVG("error while setting font face size: %d\n", local_freetype_context.error); - } - - // Update the y coordinate to match the wanted start position with the top-left of the string - jint y_adapt = (jint) LLVG_FONT_IMPL_get_baseline_position((jint)local_freetype_context.face, size); - MEJ_LOG_INFO_MICROVG("y_adapt = %d \n", y_adapt); - - jint font_color; - font_color = (gc->foreground_color & 0x00FFFFFF) + (alpha << 24); - - (void)ft_helper_print_jstring_clipped(gc, &local_freetype_context, text, length, x, y + y_adapt, font_color, alpha, size, blend, letterSpacing); - if(!LLUI_DISPLAY_setDrawingLimits(x, y, gc->clip_x2, y+char_height)){ - MEJ_LOG_INFO_MICROVG("Warning, drawing area out of the given graphics context!\n"); - } - LLUI_DISPLAY_setDrawingStatus(DRAWING_DONE); - } -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#endif // #if (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_BITMAP) diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_FONT_PAINTER_freetype_vglite.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_FONT_PAINTER_freetype_vglite.c deleted file mode 100644 index b54cdbf..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_FONT_PAINTER_freetype_vglite.c +++ /dev/null @@ -1,458 +0,0 @@ -/* - * C - * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - * - * Copyright 2023 NXP - * SPDX-License-Identifier: BSD-3-Clause - */ - -/** -* @file -* @brief MicroEJ MicroVG library low level API: implementation over Freetype and VG-Lite. -* @author MicroEJ Developer Team -* @version 3.0.0 -*/ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include "microvg_configuration.h" - -#if defined VG_FEATURE_FONT && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_VECTOR) - -#include - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "microvg_helper.h" -#include "microvg_font_freetype.h" -#include "microvg_vglite_helper.h" -#include "vg_lite.h" -#include "ftvector/ftvector.h" -#include "display_vglite.h" -#include "vglite_path.h" - -// ----------------------------------------------------------------------------- -// Macros and Defines -// ----------------------------------------------------------------------------- - -#define FT_COLOR_TO_INT(x) (*((int*) &(x))) -#define INT_TO_FT_COLOR(x) (*((FT_Color*) &(x))) - -#define DIRECTION_CLOCK_WISE 0 - -// ----------------------------------------------------------------------------- -// Extern Variables -// ----------------------------------------------------------------------------- - -extern FT_Library library; -extern FT_Renderer renderer; - -// ----------------------------------------------------------------------------- -// Global Variables -// ----------------------------------------------------------------------------- -static FT_Color *palette; - -// ----------------------------------------------------------------------------- -// Internal function definitions -// ----------------------------------------------------------------------------- - -/* - * @brief Computes the scale to apply to the font. - * - * @param[in] size: the font size - * @param[in] face: the face of the font - */ -static inline float __get_scale(jfloat size, FT_Face face); - -/* - * @brief Sets renderer parameters. - * - * @param[in] gc: the graphic context - * @param[in] matrix: the transformation matrix - * @param[in] alpha: the opacity of the string (from 0 to 255) - * @param[in] gradient: the gradient to apply - */ -static void __set_renderer(MICROUI_GraphicsContext* gc, vg_lite_matrix_t* matrix, int color, vg_lite_linear_gradient_t* gradient, vg_lite_blend_t blend); - -/* - * @brief Sets renderer color parameter. - * - * @param[in] color: the color to use to render the glyph - */ -static void __set_color(int color); - -/* - * @brief Updates the angle to use for the next glyph when drawn on an arc. - * When drawing on an arc, the glyph position is defined by its angle. We thus - * convert the advance (distance to the next glyph) to an angle. - */ -static float __get_angle(float advance, float radius); - -/** - * @brief load and render the selected glyph. If the glyph is a multilayer glyph, - * this function will retrieve the different layers glyphs with theirs colors and - * update the renderer to draw the glyph with the correct color. - * - * @param[in] face: the face of the font. - * @param[in] glyph: the glyph index. - * @param[in] glyph: the original color of the string index. - * @param[in,out] matrix: the transformation matrix. - */ -static int __render_glyph(FT_Face face, FT_UInt glyph_index, FT_Color color); - -/* - * @brief Draws a string along a circle, with a color or a linear gradient. - * - * @param[in] gc the MicroUI GraphicsContext target. - * @param[in] text the array of characters to draw. - * @param[in] faceHandle the font reference handle. - * @param[in] size the height of the font in pixels. - * @param[in] x the horizontal coordinate of the top/left of the first drawn character. - * @param[in] y the vertical coordinate of the top/left of the first drawn character. - * @param[in] vgGlobalMatrix: deformation matrix - * @param[in] blend the blend mode to use - * @param[in] color the color to apply if gradient is NULL - * @param[in] gradient the gradient to apply or NULL - * @param[in] letterSpacing the extra letter spacing to use - * @param[in] radius the radius of the circle - * @param[in] direction the direction of the text along the circle - */ -static void __draw_string(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* vgGlobalMatrix, jint blend, int color, vg_lite_linear_gradient_t *gradient, jfloat letterSpacing, jfloat radius, jint direction ); - -// ----------------------------------------------------------------------------- -// LLVG_FONT_PAINTER_impl.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -jint LLVG_FONT_PAINTER_IMPL_draw_string(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing){ - - jint ret; - if (LLVG_FONT_UNLOADED == faceHandle) { - ret = (jint)LLVG_RESOURCE_CLOSED; - } - else { - if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&(LLVG_FONT_PAINTER_IMPL_draw_string))){ - int color = (gc->foreground_color & 0x00FFFFFF) + (int)(((unsigned int) alpha) << 24); - jfloat* local_matrix = MICROVG_HELPER_check_matrix(matrix); - __draw_string(gc, text, faceHandle, size, x, y, local_matrix, blend, color, MICROVG_HELPER_NULL_GRADIENT, letterSpacing, 0, 0); - } - ret = (jint)LLVG_SUCCESS; - } - return ret; -} - - -// See the header file for the function documentation -jint LLVG_FONT_PAINTER_IMPL_draw_string_gradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix){ - - jint ret; - - if (LLVG_FONT_UNLOADED == faceHandle) { - ret = (jint)LLVG_RESOURCE_CLOSED; - } - else { - if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&(LLVG_FONT_PAINTER_IMPL_draw_string_gradient))){ - - vg_lite_linear_gradient_t gradient = {0}; - jfloat* local_gradient_matrix = MICROVG_HELPER_check_matrix(gradientMatrix); - - vg_lite_matrix_t local_matrix; - jfloat* mapped_local_matrix = MAP_VGLITE_MATRIX(&local_matrix); - LLVG_MATRIX_IMPL_setTranslate(mapped_local_matrix, x, y); - LLVG_MATRIX_IMPL_concatenate(mapped_local_matrix, matrix); - - MICROVG_VGLITE_HELPER_to_vg_lite_gradient(&gradient, gradientData, local_gradient_matrix, mapped_local_matrix, alpha); - - __draw_string(gc, text, faceHandle, size, x, y, matrix, blend, 0, &gradient, letterSpacing, 0, 0); - - // vg_lite_init_grad allocates a buffer in VGLite buffer, we must free it. - // No error even if init_grad is never called because vg_lite_clear_grad - // checks the allocation. - vg_lite_clear_grad(&gradient); - } - ret = (jint)LLVG_SUCCESS; - } - - return ret; -} - - -// See the header file for the function documentation -jint LLVG_FONT_PAINTER_IMPL_draw_string_on_circle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction){ - - jint ret; - - if (LLVG_FONT_UNLOADED == faceHandle) { - ret = (jint)LLVG_RESOURCE_CLOSED; - } - else { - if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&(LLVG_FONT_PAINTER_IMPL_draw_string_on_circle))){ - int color = (gc->foreground_color & 0x00FFFFFF) + (int)(((unsigned int) alpha) << 24); - __draw_string(gc, text, faceHandle, size, x, y, matrix, blend, color, MICROVG_HELPER_NULL_GRADIENT, letterSpacing, radius, direction); - } - ret = (jint)LLVG_SUCCESS; - } - - return ret; -} - -// See the header file for the function documentation -jint LLVG_FONT_PAINTER_IMPL_draw_string_on_circle_gradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix){ - - jint ret; - - if (LLVG_FONT_UNLOADED == faceHandle) { - ret = (jint)LLVG_RESOURCE_CLOSED; - } - else { - if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&(LLVG_FONT_PAINTER_IMPL_draw_string_on_circle_gradient))){ - - vg_lite_linear_gradient_t gradient = {0}; - jfloat* local_gradient_matrix = MICROVG_HELPER_check_matrix(gradientMatrix); - - vg_lite_matrix_t local_matrix; - jfloat* mapped_local_matrix = MAP_VGLITE_MATRIX(&local_matrix); - LLVG_MATRIX_IMPL_setTranslate(mapped_local_matrix, x, y); - LLVG_MATRIX_IMPL_concatenate(mapped_local_matrix, matrix); - - MICROVG_VGLITE_HELPER_to_vg_lite_gradient(&gradient, gradientData, local_gradient_matrix, mapped_local_matrix, alpha); - - __draw_string(gc, text, faceHandle, size, x, y, matrix, blend, 0, &gradient, letterSpacing, radius, direction); - - // vg_lite_init_grad allocates a buffer in VGLite buffer, we must free it. - // No error even if init_grad is never called because vg_lite_clear_grad - // checks the allocation. - vg_lite_clear_grad(&gradient); - } - ret = (jint)LLVG_SUCCESS; - } - - return ret; -} - -// ----------------------------------------------------------------------------- -// Internal functions -// ----------------------------------------------------------------------------- - -static inline float __get_scale(jfloat size, FT_Face face){ - return size / face->units_per_EM; -} - -static void __set_renderer(MICROUI_GraphicsContext* gc, vg_lite_matrix_t* matrix, int color, vg_lite_linear_gradient_t* gradient, vg_lite_blend_t blend){ - FT_Parameter vglite_params[7]; - - vglite_params[0].tag = FT_PARAM_TAG_VGLITE_DESTINATION; - vglite_params[0].data = VG_DRAWER_configure_target(gc); - - vglite_params[1].tag = FT_PARAM_TAG_VGLITE_MATRIX; - vglite_params[1].data = matrix; - - vglite_params[2].tag = FT_PARAM_TAG_VGLITE_QUALITY; - vglite_params[2].data = (void *) VG_LITE_HIGH; - - vglite_params[3].tag = FT_PARAM_TAG_VGLITE_FORMAT; - vglite_params[3].data = (void *) VG_LITE_S16; - - vglite_params[4].tag = FT_PARAM_TAG_VGLITE_BLEND; - vglite_params[4].data = (void *) blend; - - vglite_params[5].tag = FT_PARAM_TAG_VGLITE_COLOR; - // cppcheck-suppress [misra-c2012-11.6] pointer conversion to pass color - vglite_params[5].data = (void *) color; - - vglite_params[6].tag = FT_PARAM_TAG_VGLITE_GRADIENT; - vglite_params[6].data = (void *) gradient; - FT_Set_Renderer(library, renderer, 7, &vglite_params[0]); -} - -static void __set_color(int color) { - - FT_Renderer renderer = FT_Get_Renderer(library, FT_GLYPH_FORMAT_OUTLINE); - FT_Renderer_SetModeFunc set_mode = renderer->clazz->set_mode; - - // cppcheck-suppress [misra-c2012-11.6] pointer conversion to pass color - set_mode(renderer, FT_PARAM_TAG_VGLITE_COLOR, (void *)color); -} - -static float __get_angle(float advance, float radius){ - return (advance/radius) * 180.0f / M_PI; -} - -static int __render_glyph(FT_Face face, FT_UInt glyph_index, FT_Color color) { - FT_LayerIterator iterator; - - FT_Bool have_layers; - FT_UInt layer_glyph_index; - FT_UInt layer_color_index; - - int error = 0; - bool color_updated = false; - - iterator.p = NULL; - have_layers = FT_Get_Color_Glyph_Layer(face, glyph_index, - &layer_glyph_index, &layer_color_index, &iterator); - - do { - if (palette && have_layers) { - // Update renderer color with layer_color - if (layer_color_index == 0xFFFF){ - __set_color(FT_COLOR_TO_INT(color)); - } - else { - __set_color(FT_COLOR_TO_INT(palette[layer_color_index])); - color_updated = true; - } - } - else { - // Use main glyph_index as layer_glyph_index - layer_glyph_index = glyph_index; - } - - if(layer_glyph_index != glyph_index){ - error = FT_Load_Glyph(face, layer_glyph_index, FT_LOAD_NO_SCALE); - } - - if (0 == error) { - // convert to an anti-aliased bitmap - error = FT_Render_Glyph(face->glyph, FT_RENDER_MODE_NORMAL); - } - else { - MEJ_LOG_ERROR_MICROVG("Error while loading glyphid %d: 0x%x, refer to fterrdef.h\n",layer_glyph_index, error); - } - } - while ((layer_glyph_index != glyph_index) && (0 == error) && (0 != FT_Get_Color_Glyph_Layer(face, glyph_index, - &layer_glyph_index, &layer_color_index, &iterator))); - - if ((0 == error) && color_updated) { - // Revert renderer color to original color in case it has been modified. - __set_color(FT_COLOR_TO_INT(color)); - } - - return error; -} - -static void __draw_string(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* vgGlobalMatrix, jint blend, int color, vg_lite_linear_gradient_t *gradient, jfloat letterSpacing, jfloat radius, jint direction ){ - FT_Face face = (FT_Face) faceHandle; - - if (MICROVG_VGLITE_HELPER_enable_vg_lite_scissor(gc)){ - - // Select palette - if (0 != FT_Palette_Select(face, 0, &palette)){ - palette = NULL; - } - - float scale = __get_scale(size, face); - int advanceX = 0; - int advanceY = 0; - float letterSpacingScaled = letterSpacing / scale; - float radiusScaled = radius / scale; - - // baselineposition - short baselineposition = face->ascender; - - // Compute matrix to position the glyph - vg_lite_matrix_t localMatrix; - jfloat* vgLocalMatrix = MAP_VGLITE_MATRIX(&localMatrix); - - if((0.f != x) || (0.f != y)) - { - // Create translate matrix for initial x,y translation from graphicscontext. - LLVG_MATRIX_IMPL_setTranslate(vgLocalMatrix, x, y); - LLVG_MATRIX_IMPL_concatenate(vgLocalMatrix, vgGlobalMatrix); - } - else - { - // use original matrix - LLVG_MATRIX_IMPL_copy(vgLocalMatrix, vgGlobalMatrix); - } - - LLVG_MATRIX_IMPL_scale(vgLocalMatrix, scale, scale); - - vg_lite_matrix_t localGlyphMatrix; - jfloat* vglocalGlyphMatrix = MAP_VGLITE_MATRIX(&localGlyphMatrix); - - __set_renderer(gc, &localGlyphMatrix, color, gradient, MICROVG_VGLITE_HELPER_get_blend(blend)); - - // Layout variables - int glyph_index ; // current glyph index - int previous_glyph_index = 0; // previous glyph index for kerning - - int advance_x; - int advance_y; - int offset_x; - int offset_y; - - int length = (int)SNI_getArrayLength(text); - MICROVG_HELPER_layout_configure(faceHandle, text, length); - - while(0 != MICROVG_HELPER_layout_load_glyph(&glyph_index, &advance_x, &advance_y, &offset_x, &offset_y)){ - // At that point the current glyph has been loaded by Freetype - - int charWidth = advance_x; - - if (0 == previous_glyph_index){ - // first glyph: remove the first blank line - if( 0 == face->glyph->metrics.width) { - advanceX -= charWidth; - } - else { - advanceX -= face->glyph->metrics.horiBearingX; - } - } - - LLVG_MATRIX_IMPL_copy(vglocalGlyphMatrix, vgLocalMatrix); - - if(0.f == radius) { - LLVG_MATRIX_IMPL_translate(vglocalGlyphMatrix, advanceX + offset_x, baselineposition + advanceY + offset_y); - } else { - float sign = (DIRECTION_CLOCK_WISE != direction) ? -1.f : 1.f; - - // Space characters joining bboxes at baseline - float angleDegrees = 90 + __get_angle(advanceX + offset_x, radiusScaled) + __get_angle(charWidth / 2, radiusScaled); - - // Rotate to angle - LLVG_MATRIX_IMPL_rotate(vglocalGlyphMatrix, sign * angleDegrees); - - // Translate left to center of bbox - // Translate baseline over circle - LLVG_MATRIX_IMPL_translate(vglocalGlyphMatrix, -charWidth / 2, -sign * radiusScaled); - } - - // Draw the glyph - FT_Error error = __render_glyph(face, glyph_index, INT_TO_FT_COLOR(color)); - if (0 != error) { - MEJ_LOG_ERROR_MICROVG("Error while rendering glyphid %d: 0x%x, refer to fterrdef.h\n",glyph_index, error); - continue; // ignore errors - } - - // Compute advance to next glyph - advanceX += charWidth; - advanceX += (int)letterSpacingScaled; - - advanceY += advance_y; - - previous_glyph_index = glyph_index; - } - - DISPLAY_VGLITE_start_operation(true); - - LLUI_DISPLAY_setDrawingStatus(DRAWING_RUNNING); - } - // else empty clip, nothing to draw -} -#endif // defined VG_FEATURE_FONT && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_VECTOR) -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_FONT_stub.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_FONT_stub.c deleted file mode 100644 index fe927a6..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_FONT_stub.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * C - * - * Copyright 2020-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/** - * @file - * @brief MicroEJ MicroVG library low level API: implementation over FreeType - * @author MicroEJ Developer Team - * @version 2.0.0 - */ - -#include "microvg_configuration.h" - -#ifndef VG_FEATURE_FONT - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include -#include - -// ----------------------------------------------------------------------------- -// LLVG_FONT_impl.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -jint LLVG_FONT_IMPL_load_font(jchar* font_name, jboolean complex_layout) { - (void)font_name; - (void)complex_layout; - return 0; -} - -// See the header file for the function documentation -jfloat LLVG_FONT_IMPL_string_width(jchar* text, jint faceHandle, jfloat size, jfloat letterSpacing) { - (void)text; - (void)faceHandle; - (void)size; - (void)letterSpacing; - return 0; -} - -// See the header file for the function documentation -jfloat LLVG_FONT_IMPL_string_height(jchar* text, jint faceHandle, jfloat size) { - (void)text; - (void)faceHandle; - (void)size; - return 0; -} - -// See the header file for the function documentation -jfloat LLVG_FONT_IMPL_get_baseline_position(jint faceHandle, jfloat size) { - (void)faceHandle; - (void)size; - return 0; -} - -// See the header file for the function documentation -jfloat LLVG_FONT_IMPL_get_height(jint faceHandle, jfloat size) { - (void)faceHandle; - (void)size; - return 0; -} - -// See the header file for the function documentation -void LLVG_FONT_IMPL_dispose(jint faceHandle) { - (void)faceHandle; -} -// ----------------------------------------------------------------------------- -// LLVG_FONT_PAINTER_impl.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -jint LLVG_FONT_PAINTER_IMPL_draw_string(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing){ - (void)gc; - (void)text; - (void)faceHandle; - (void)size; - (void)x; - (void)y; - (void)matrix; - (void)alpha; - (void)blend; - (void)letterSpacing; - - return(0); -} - -// See the header file for the function documentation -jint LLVG_FONT_PAINTER_IMPL_draw_string_gradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jfloat x, jfloat y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jint *gradientData, jfloat *gradientMatrix){ - (void)gc; - (void)text; - (void)faceHandle; - (void)size; - (void)x; - (void)y; - (void)matrix; - (void)alpha; - (void)blend; - (void)letterSpacing; - (void)gradientData; - (void)gradientMatrix; - - return(0); -} - -// See the header file for the function documentation -jint LLVG_FONT_PAINTER_IMPL_draw_string_on_circle(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction){ - (void)gc; - (void)text; - (void)faceHandle; - (void)size; - (void)x; - (void)y; - (void)matrix; - (void)alpha; - (void)blend; - (void)letterSpacing; - (void)radius; - (void)direction; - - return(0); -} - -// See the header file for the function documentation -jint LLVG_FONT_PAINTER_IMPL_draw_string_on_circle_gradient(MICROUI_GraphicsContext* gc, jchar* text, jint faceHandle, jfloat size, jint x, jint y, jfloat* matrix, jint alpha, jint blend, jfloat letterSpacing, jfloat radius, jint direction, jint *gradientData, jfloat *gradientMatrix){ - (void)gc; - (void)text; - (void)faceHandle; - (void)size; - (void)x; - (void)y; - (void)matrix; - (void)alpha; - (void)blend; - (void)letterSpacing; - (void)radius; - (void)direction; - (void)gradientData; - (void)gradientMatrix; - - return(0); -} - -// See the header file for the function documentation -void LLVG_FONT_IMPL_set_complex_layout(bool enabled){ - (void)enabled; -} - -// See the header file for the function documentation -bool LLVG_FONT_IMPL_has_complex_layouter(void){ - return false; -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#endif // VG_FEATURE_FONT diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_MATRIX_impl.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_MATRIX_impl.c deleted file mode 100644 index 2caa725..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_MATRIX_impl.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * C - * - * Copyright 2021-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/** - * @file - * @brief MicroEJ MicroVG library low level API: basic implementation - * of matrix APIs. - * @author MicroEJ Developer Team - * @version 2.0.0 - */ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include -#include - -#include - -#include "microvg_helper.h" - -// ----------------------------------------------------------------------------- -// LLVG_MATRIX_impl.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_identity(jfloat* matrix) { - LLVG_MATRIX_IMPL_setTranslate(matrix, 0, 0); -} - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_copy(jfloat* dest, jfloat* src) { - (void)memcpy((void*)dest, (void*)src, sizeof(float) * LLVG_MATRIX_SIZE); -} - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_setTranslate(jfloat* matrix, jfloat x, jfloat y) { - matrix[0] = 1.0f; - matrix[1] = 0.0f; - matrix[2] = x; - matrix[3] = 0.0f; - matrix[4] = 1.0f; - matrix[5] = y; - matrix[6] = 0.0f; - matrix[7] = 0.0f; - matrix[8] = 1.0f; -} - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_setScale(jfloat* matrix, jfloat sx, jfloat sy) { - LLVG_MATRIX_IMPL_identity(matrix); - LLVG_MATRIX_IMPL_scale(matrix, sx, sy); -} - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_setRotate(jfloat* matrix, jfloat degrees) { - LLVG_MATRIX_IMPL_identity(matrix); - LLVG_MATRIX_IMPL_rotate(matrix, degrees); -} - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_setConcat(jfloat* dest, jfloat* a, jfloat* b) { - LLVG_MATRIX_IMPL_copy(dest, a); - LLVG_MATRIX_IMPL_concatenate(dest, b); -} - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_translate(jfloat* matrix, jfloat x, jfloat y) { - matrix[2] = (matrix[0] * x) + (matrix[1] * y) + matrix[2]; - matrix[5] = (matrix[3] * x) + (matrix[4] * y) + matrix[5]; - matrix[8] = (matrix[6] * x) + (matrix[7] * y) + matrix[8]; -} - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_scale(jfloat* matrix, jfloat scaleX, jfloat scaleY) { - matrix[0] *= scaleX; - matrix[1] *= scaleY; - matrix[3] *= scaleX; - matrix[4] *= scaleY; - matrix[6] *= scaleX; - matrix[7] *= scaleY; -} - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_rotate(jfloat* matrix, jfloat angleDegrees) { - - float angleRadians = DEG_TO_RAD(angleDegrees); - - // computes cosine and sine values. - float cosAngle = cosf(angleRadians); - float sinAngle = sinf(angleRadians); - - float tmp; - - tmp = (cosAngle * matrix[0]) + (sinAngle * matrix[1]); - matrix[1] = (cosAngle * matrix[1]) - (sinAngle * matrix[0]); - matrix[0] = tmp; - - tmp = (cosAngle * matrix[3]) + (sinAngle * matrix[4]); - matrix[4] = (cosAngle * matrix[4]) - (sinAngle * matrix[3]); - matrix[3] = tmp; - - tmp = (cosAngle * matrix[6]) + (sinAngle * matrix[7]); - matrix[7] = (cosAngle * matrix[7]) - (sinAngle * matrix[6]); - matrix[6] = tmp; -} - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_concatenate(jfloat* matrix, jfloat* other) { - // cppcheck-suppress [misra-c2012-18.8] the size is a define - float temp[LLVG_MATRIX_SIZE]; - - temp[0] = (matrix[0] * other[0]) + (matrix[1] * other[3]) + (matrix[2] * other[6]); - temp[1] = (matrix[0] * other[1]) + (matrix[1] * other[4]) + (matrix[2] * other[7]); - temp[2] = (matrix[0] * other[2]) + (matrix[1] * other[5]) + (matrix[2] * other[8]); - - temp[3] = (matrix[3] * other[0]) + (matrix[4] * other[3]) + (matrix[5] * other[6]); - temp[4] = (matrix[3] * other[1]) + (matrix[4] * other[4]) + (matrix[5] * other[7]); - temp[5] = (matrix[3] * other[2]) + (matrix[4] * other[5]) + (matrix[5] * other[8]); - - temp[6] = (matrix[6] * other[0]) + (matrix[7] * other[3]) + (matrix[8] * other[6]); - temp[7] = (matrix[6] * other[1]) + (matrix[7] * other[4]) + (matrix[8] * other[7]); - temp[8] = (matrix[6] * other[2]) + (matrix[7] * other[5]) + (matrix[8] * other[8]); - - /* Copy temporary matrix into result. */ - LLVG_MATRIX_IMPL_copy(matrix, temp); -} - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_postTranslate(jfloat* matrix, jfloat dx, jfloat dy) { - // cppcheck-suppress [misra-c2012-18.8] the size is a define - float temp[LLVG_MATRIX_SIZE]; - LLVG_MATRIX_IMPL_setTranslate(temp, dx, dy); - LLVG_MATRIX_IMPL_concatenate(temp, matrix); - LLVG_MATRIX_IMPL_copy(matrix, temp); -} - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_postScale(jfloat* matrix, jfloat sx, jfloat sy) { - // cppcheck-suppress [misra-c2012-18.8] the size is a define - float temp[LLVG_MATRIX_SIZE]; - LLVG_MATRIX_IMPL_identity(temp); - LLVG_MATRIX_IMPL_scale(temp, sx, sy); - LLVG_MATRIX_IMPL_concatenate(temp, matrix); - LLVG_MATRIX_IMPL_copy(matrix, temp); -} - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_postRotate(jfloat* matrix, jfloat degrees) { - // cppcheck-suppress [misra-c2012-18.8] the size is a define - float temp[LLVG_MATRIX_SIZE]; - LLVG_MATRIX_IMPL_identity(temp); - LLVG_MATRIX_IMPL_rotate(temp, degrees); - LLVG_MATRIX_IMPL_concatenate(temp, matrix); - LLVG_MATRIX_IMPL_copy(matrix, temp); -} - -// See the header file for the function documentation -void LLVG_MATRIX_IMPL_postConcat(jfloat* matrix, jfloat* other) { - // cppcheck-suppress [misra-c2012-18.8] the size is a define - float temp[LLVG_MATRIX_SIZE]; - LLVG_MATRIX_IMPL_copy(temp, other); - LLVG_MATRIX_IMPL_concatenate(temp, matrix); - LLVG_MATRIX_IMPL_copy(matrix, temp); -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_PATH_PAINTER_vglite.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_PATH_PAINTER_vglite.c deleted file mode 100644 index 72ebb40..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_PATH_PAINTER_vglite.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - * C - * - * Copyright 2021-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - * - * Copyright 2023 NXP - * SPDX-License-Identifier: BSD-3-Clause - */ - -/** - * @file - * @brief MicroEJ MicroVG library low level API: implementation over VG-Lite. - * @author MicroEJ Developer Team - * @version 3.0.0 - */ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include - -#include -#include -#include - -#include "microvg_path.h" -#include "microvg_helper.h" -#include "microvg_vglite_helper.h" -#include "vg_lite.h" -#include "color.h" -#include "display_vglite.h" -#include "vglite_path.h" - -// ----------------------------------------------------------------------------- -// Defines -// ----------------------------------------------------------------------------- - -#ifndef VG_FEATURE_PATH -#error "This implementation is only compatible when VG_FEATURE_PATH is set" -#endif - -/* - * @brief Specific error code when VG-Lite library throws an error. - */ -#define RET_ERROR_VGLITE -1 - -/* - * @brief Specific error code when gradient data is invalid. - */ -#define RET_ERROR_GRADIENT -2 - -/* - * @brief Fills a VGLite path with RAW path data - */ -#define PATH_TO_VGLITEPATH(p) \ - { \ - { \ - (vg_lite_float_t)(((MICROVG_PATH_HEADER_t*)(p))->bounds_xmin), (vg_lite_float_t)(((MICROVG_PATH_HEADER_t*)(p))->bounds_ymin), \ - (vg_lite_float_t)(((MICROVG_PATH_HEADER_t*)(p))->bounds_xmax), (vg_lite_float_t)(((MICROVG_PATH_HEADER_t*)(p))->bounds_ymax) \ - }, \ - VG_LITE_UPPER, \ - (vg_lite_format_t)(((MICROVG_PATH_HEADER_t*)(p))->format), \ - {0}, \ - (int32_t)(((MICROVG_PATH_HEADER_t*)(p))->data_size), \ - (void*)&(((uint8_t*)(p))[((MICROVG_PATH_HEADER_t*)(p))->data_offset]), \ - 1 \ - } - -// ----------------------------------------------------------------------------- -// microvg_path.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -uint8_t MICROVG_PATH_get_path_encoder_format(void) { - return VG_LITE_FP32; -} - -// See the header file for the function documentation -uint32_t MICROVG_PATH_convert_path_command(jint command) { - uint32_t ret; - switch (command) { - default: // unknown -> close (should not occur) - case LLVG_PATH_CMD_CLOSE: - ret = VLC_OP_END; - break; - case LLVG_PATH_CMD_MOVE: - ret = VLC_OP_MOVE; - break; - case LLVG_PATH_CMD_MOVE_REL: - ret = VLC_OP_MOVE_REL; - break; - case LLVG_PATH_CMD_LINE: - ret = VLC_OP_LINE; - break; - case LLVG_PATH_CMD_LINE_REL: - ret = VLC_OP_LINE_REL; - break; - case LLVG_PATH_CMD_QUAD: - ret = VLC_OP_QUAD; - break; - case LLVG_PATH_CMD_QUAD_REL: - ret = VLC_OP_QUAD_REL; - break; - case LLVG_PATH_CMD_CUBIC: - ret = VLC_OP_CUBIC; - break; - case LLVG_PATH_CMD_CUBIC_REL: - ret = VLC_OP_CUBIC_REL; - break; - } - return ret; -} - -// See the header file for the function documentation -uint32_t MICROVG_PATH_get_command_parameter_number(jint command) { - uint32_t ret; - switch (command) { - default: // unknown -> close (should not occur) - case LLVG_PATH_CMD_CLOSE: - ret = 0; - break; - case LLVG_PATH_CMD_MOVE: - case LLVG_PATH_CMD_MOVE_REL: - case LLVG_PATH_CMD_LINE: - case LLVG_PATH_CMD_LINE_REL: - ret = 2; - break; - case LLVG_PATH_CMD_QUAD: - case LLVG_PATH_CMD_QUAD_REL: - ret = 4; - break; - case LLVG_PATH_CMD_CUBIC: - case LLVG_PATH_CMD_CUBIC_REL: - ret = 6; - break; - } - return ret; -} - -// ----------------------------------------------------------------------------- -// LLVG_PAINTER_impl.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -jint LLVG_PATH_PAINTER_IMPL_drawPath(MICROUI_GraphicsContext* gc, jbyte* pathData, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color) { - jint ret = LLVG_SUCCESS; - if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&(LLVG_PATH_PAINTER_IMPL_drawPath)) && MICROVG_VGLITE_HELPER_enable_vg_lite_scissor(gc)) { - - vg_lite_path_t path = PATH_TO_VGLITEPATH(pathData); - void* target = VG_DRAWER_configure_target(gc); - vg_lite_blend_t vg_lite_blend = MICROVG_VGLITE_HELPER_get_blend(blend); - vg_lite_color_t vg_lite_color = (vg_lite_color_t)color; - VG_DRAWER_update_color(target, &vg_lite_color, vg_lite_blend); - - vg_lite_matrix_t vg_lite_matrix; - jfloat* mapped_matrix = MAP_VGLITE_MATRIX(&vg_lite_matrix); - - if((0 != x) || (0 != y)) { - // Create translate matrix for initial x,y translation from graphicscontext. - LLVG_MATRIX_IMPL_setTranslate(mapped_matrix, x, y); - LLVG_MATRIX_IMPL_concatenate(mapped_matrix, matrix); - } - else { - // use original matrix - LLVG_MATRIX_IMPL_copy(mapped_matrix, matrix); - } - - vg_lite_error_t vg_lite_error = VG_DRAWER_draw_path( - target, - &path, MICROVG_VGLITE_HELPER_get_fill_rule(fillRule), &vg_lite_matrix, - vg_lite_blend, vg_lite_color); - - - if (VG_LITE_SUCCESS == vg_lite_error) { - LLUI_DISPLAY_setDrawingStatus(VG_DRAWER_post_operation(target, vg_lite_error)); - } - else { - ret = RET_ERROR_VGLITE; - } - } - return ret; -} - -// See the header file for the function documentation -jint LLVG_PATH_PAINTER_IMPL_drawGradient(MICROUI_GraphicsContext* gc, jbyte* pathData, jint x, jint y, jfloat* matrix, jint fillRule, jint alpha, jint blend, jint* gradientData, jfloat* gradientMatrix) { - - jint ret = LLVG_SUCCESS; - if (LLUI_DISPLAY_requestDrawing(gc, (SNI_callback)&(LLVG_PATH_PAINTER_IMPL_drawGradient)) && MICROVG_VGLITE_HELPER_enable_vg_lite_scissor(gc)) { - - vg_lite_path_t path = PATH_TO_VGLITEPATH(pathData); - void* target = VG_DRAWER_configure_target(gc); - - vg_lite_linear_gradient_t gradient = {0}; - jfloat* local_gradient_matrix = MICROVG_HELPER_check_matrix(gradientMatrix); - vg_lite_error_t vg_lite_error = MICROVG_VGLITE_HELPER_to_vg_lite_gradient(&gradient, gradientData, local_gradient_matrix, matrix, alpha); - - if (VG_LITE_SUCCESS == vg_lite_error) { - - vg_lite_matrix_t vg_lite_matrix; - jfloat* mapped_matrix = MAP_VGLITE_MATRIX(&vg_lite_matrix); - - vg_lite_blend_t vglite_blend = MICROVG_VGLITE_HELPER_get_blend(blend); - vg_lite_fill_t vglite_fill = MICROVG_VGLITE_HELPER_get_fill_rule(fillRule); - VG_DRAWER_update_gradient(target, &gradient, vglite_blend); - - if((0 != x) || (0 != y)) { - // Create translate matrix for initial x,y translation from graphicscontext. - - LLVG_MATRIX_IMPL_setTranslate(mapped_matrix, x, y); - LLVG_MATRIX_IMPL_concatenate(mapped_matrix, matrix); - - vg_lite_linear_gradient_t translated_gradient; - (void)memcpy(&translated_gradient, &gradient, sizeof(vg_lite_linear_gradient_t)); - jfloat* mapped_translated_gradient_matrix = MAP_VGLITE_GRADIENT_MATRIX(&translated_gradient); - jfloat* mapped_gradient_matrix = MAP_VGLITE_GRADIENT_MATRIX(&gradient); - LLVG_MATRIX_IMPL_setTranslate(mapped_translated_gradient_matrix, x, y); - LLVG_MATRIX_IMPL_concatenate(mapped_translated_gradient_matrix, mapped_gradient_matrix); - - vg_lite_error = VG_DRAWER_draw_gradient( - target, - &path, - vglite_fill, - &vg_lite_matrix, &translated_gradient, - vglite_blend); - } - else { - // use original matrix and gradient - - LLVG_MATRIX_IMPL_copy(mapped_matrix, matrix); - - vg_lite_error = VG_DRAWER_draw_gradient( - target, - &path, - vglite_fill, - &vg_lite_matrix, &gradient, - vglite_blend); - } - - if (VG_LITE_SUCCESS == vg_lite_error) { - LLUI_DISPLAY_setDrawingStatus(VG_DRAWER_post_operation(target, vg_lite_error)); - } - else { - ret = RET_ERROR_VGLITE; - } - } - else { - ret = RET_ERROR_GRADIENT; - } - - // vg_lite_init_grad allocates a buffer in VGLite buffer, we must free it. - // No error even if init_grad is never called because vg_lite_clear_grad - // checks the allocation. - vg_lite_clear_grad(&gradient); - } - return ret; -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_PATH_impl.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_PATH_impl.c deleted file mode 100644 index 0bf373f..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_PATH_impl.c +++ /dev/null @@ -1,327 +0,0 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/** - * @file - * @brief MicroVG library low level API: implementation of path. - * - * This implementation uses a 32-bit "integer" value to store a path command and - * a 32-bit "float" value to store each command parameter. - * - * The encoding can be overrided, see "[optional]: weak functions" in "microvg_path.h" - * - * @author MicroEJ Developer Team - * @version 2.0.0 - */ - -#include "microvg_configuration.h" - -#ifdef VG_FEATURE_PATH - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include -#include - -#include - -#include "microvg_path.h" -#include "microvg_helper.h" -#include "bsp_util.h" - -#include "mej_math.h" - -// ----------------------------------------------------------------------------- -// Private functions -// ----------------------------------------------------------------------------- - -/* - * @brief Extends the path to be able to store the command and its parameters. - * - * @return the offset in path buffer where the command will be stored. If the path - * buffer is not large enough to contain the requested command, returns a negative - * number corresponding to size the buffer must be enlarged for this command. - */ -static int32_t _extend_path(MICROVG_PATH_HEADER_t* path, jint length, jint cmd, uint32_t nb_fields) { - uint32_t index = path->data_offset + path->data_size; - uint32_t extra_size = MICROVG_PATH_get_path_command_size(cmd, nb_fields); - int32_t ret; - - if (length >= (index + extra_size)) { - path->data_size += extra_size; - - // return next free space (return a positive value) - ret = index; - } - else { - // too small buffer, ret is the required extra size - // (return a negative value) - ret = -extra_size; - } - - return ret; -} - -static int32_t _close_path(MICROVG_PATH_HEADER_t* path, jint length, jfloat x1, jfloat y1, jfloat x2, jfloat y2) { - int32_t index = _extend_path(path, length, LLVG_PATH_CMD_CLOSE, 0); - int32_t ret = LLVG_SUCCESS; - if (index > 0) { - // finalizes the path by storing the path's bounds - path->bounds_xmin = x1; - path->bounds_xmax = x2; - path->bounds_ymin = y1; - path->bounds_ymax = y2; - (void)MICROVG_PATH_append_path_command0((jbyte*)path, (uint32_t)index, LLVG_PATH_CMD_CLOSE); - } - else { - // too small buffer, ret is the required extra size * -1 - ret = -index; - } - return ret; -} - -// ----------------------------------------------------------------------------- -// Specific path format functions [optional]: weak functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -BSP_DECLARE_WEAK_FCNT uint32_t MICROVG_PATH_get_path_header_size(void) { - return sizeof(MICROVG_PATH_HEADER_t); -} - -// See the header file for the function documentation -BSP_DECLARE_WEAK_FCNT uint32_t MICROVG_PATH_get_path_command_size(jint command, uint32_t nbParams) { - (void)command; - return (nbParams + (uint32_t)1 /* command */) * sizeof(uint32_t); -} - -// See the header file for the function documentation -BSP_DECLARE_WEAK_FCNT uint32_t MICROVG_PATH_append_path_command0(jbyte* path, uint32_t offset, jint cmd) { - uint32_t* data = (uint32_t*)(path + offset); - *data = MICROVG_PATH_convert_path_command(cmd); - return sizeof(uint32_t); -} - -// See the header file for the function documentation -BSP_DECLARE_WEAK_FCNT uint32_t MICROVG_PATH_append_path_command1(jbyte* path, uint32_t offset, jint cmd, jfloat x, jfloat y) { - uint32_t* data = (uint32_t*)(path + offset); - *data = MICROVG_PATH_convert_path_command(cmd); - ++data; - *data = JFLOAT_TO_UINT32_t(x); - ++data; - *data = JFLOAT_TO_UINT32_t(y); - return (uint32_t)3 * sizeof(uint32_t); -} - -// See the header file for the function documentation -BSP_DECLARE_WEAK_FCNT uint32_t MICROVG_PATH_append_path_command2(jbyte* path, uint32_t offset, jint cmd, jfloat x1, jfloat y1, jfloat x2, jfloat y2) { - uint32_t* data = (uint32_t*)(path + offset); - *data = MICROVG_PATH_convert_path_command(cmd); - ++data; - *data = JFLOAT_TO_UINT32_t(x1); - ++data; - *data = JFLOAT_TO_UINT32_t(y1); - ++data; - *data = JFLOAT_TO_UINT32_t(x2); - ++data; - *data = JFLOAT_TO_UINT32_t(y2); - return (uint32_t)5 * sizeof(uint32_t); -} - -// See the header file for the function documentation -BSP_DECLARE_WEAK_FCNT uint32_t MICROVG_PATH_append_path_command3(jbyte* path, uint32_t offset, jint cmd, jfloat x1, jfloat y1, jfloat x2, jfloat y2, - jfloat x3, jfloat y3) { - uint32_t* data = (uint32_t*)(path + offset); - *data = MICROVG_PATH_convert_path_command(cmd); - ++data; - *data = JFLOAT_TO_UINT32_t(x1); - ++data; - *data = JFLOAT_TO_UINT32_t(y1); - ++data; - *data = JFLOAT_TO_UINT32_t(x2); - ++data; - *data = JFLOAT_TO_UINT32_t(y2); - ++data; - *data = JFLOAT_TO_UINT32_t(x3); - ++data; - *data = JFLOAT_TO_UINT32_t(y3); - return (uint32_t)7 * sizeof(uint32_t); -} - -// ----------------------------------------------------------------------------- -// LLVG_PATH_impl.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -jint LLVG_PATH_IMPL_initializePath(jbyte* jpath, jint length) { - - MICROVG_PATH_HEADER_t* path = (MICROVG_PATH_HEADER_t*)jpath; - uint32_t header_size = MICROVG_PATH_get_path_header_size(); - jint ret = LLVG_SUCCESS; - - if (length >= header_size) { - path->data_size = 0; - path->data_offset = header_size; - path->format = MICROVG_PATH_get_path_encoder_format(); - } - else { - // the given byte array is too small - ret = header_size; - } - - return ret; -} - -// See the header file for the function documentation -jint LLVG_PATH_IMPL_appendPathCommand1(jbyte* jpath, jint length, jint cmd, jfloat x, jfloat y) { - - MICROVG_PATH_HEADER_t* path = (MICROVG_PATH_HEADER_t*)jpath; - jint ret = LLVG_SUCCESS; - - int32_t index = _extend_path(path, length, cmd, 2); - if (index > 0) { - (void)MICROVG_PATH_append_path_command1((jbyte*)path, (uint32_t)index, cmd, x, y); - } - else { - // too small buffer, ret is the required extra size * -1 - ret = -index; - } - - return ret; -} - -// See the header file for the function documentation -jint LLVG_PATH_IMPL_appendPathCommand2(jbyte* jpath, jint length, jint cmd, jfloat x1, jfloat y1, jfloat x2, - jfloat y2) { - - MICROVG_PATH_HEADER_t* path = (MICROVG_PATH_HEADER_t*)jpath; - jint ret = LLVG_SUCCESS; - - if (LLVG_PATH_CMD_CLOSE == cmd) { - // parameters are path's bounds - ret = _close_path(path, length, x1, y1, x2, y2); - } - else { - int32_t index = _extend_path(path, length, cmd, 4); - if (index > 0) { - (void)MICROVG_PATH_append_path_command2((jbyte*)path, (uint32_t)index, cmd, x1, y1, x2, y2); - } - else { - // too small buffer, ret is the required extra size * -1 - ret = -index; - } - } - - return ret; -} - -// See the header file for the function documentation -jint LLVG_PATH_IMPL_appendPathCommand3(jbyte* jpath, jint length, jint cmd, jfloat x1, jfloat y1, jfloat x2, - jfloat y2, jfloat x3, jfloat y3) { - - MICROVG_PATH_HEADER_t* path = (MICROVG_PATH_HEADER_t*)jpath; - jint ret = LLVG_SUCCESS; - - int32_t index = _extend_path(path, length, cmd, 6); - if (index > 0) { - (void)MICROVG_PATH_append_path_command3((jbyte*)path, (uint32_t)index, cmd, x1, y1, x2, y2, x3, y3); - } - else { - // too small buffer, ret is the required extra size * -1 - ret = -index; - } - - return ret; -} - -// See the header file for the function documentation -void LLVG_PATH_IMPL_reopenPath(jbyte* jpath) { - MICROVG_PATH_HEADER_t* path = (MICROVG_PATH_HEADER_t*)jpath; - path->data_size -= MICROVG_PATH_get_path_command_size(LLVG_PATH_CMD_CLOSE, 0); -} - - -// See the header file for the function documentation -jint LLVG_PATH_IMPL_mergePaths(jbyte* jpathDest, jbyte* jpathSrc1, jbyte* jpathSrc2, jfloat ratio){ - - jint ret = LLVG_SUCCESS; - float remaining = (1-ratio); - - MICROVG_PATH_HEADER_t* pathDest = (MICROVG_PATH_HEADER_t*)jpathDest; - MICROVG_PATH_HEADER_t* pathSrc1 = (MICROVG_PATH_HEADER_t*)jpathSrc1; - MICROVG_PATH_HEADER_t* pathSrc2 = (MICROVG_PATH_HEADER_t*)jpathSrc2; - - // Copy header from pathSrc1 - pathDest->data_size = pathSrc1->data_size; - pathDest->data_offset = pathSrc1->data_offset; - pathDest->format = pathSrc1->format; - - // Compute bounds - float fSrc1 = pathSrc1->bounds_xmin; - float fSrc2 = pathSrc2->bounds_xmin; - float fDest = MEJ_MIN(fSrc1, fSrc2); - pathDest->bounds_xmin = fDest; - - fSrc1 = pathSrc1->bounds_ymin; - fSrc2 = pathSrc2->bounds_ymin; - fDest = MEJ_MIN(fSrc1, fSrc2); - pathDest->bounds_ymin = fDest; - - fSrc1 = pathSrc1->bounds_xmax; - fSrc2 = pathSrc2->bounds_xmax; - fDest = MEJ_MAX(fSrc1, fSrc2); - pathDest->bounds_xmax = fDest; - - fSrc1 = pathSrc1->bounds_ymax; - fSrc2 = pathSrc2->bounds_ymax; - fDest = MEJ_MAX(fSrc1, fSrc2); - pathDest->bounds_ymax = fDest; - - // Compute commands - uint32_t* dataDest = (uint32_t*)(jpathDest + pathDest->data_offset); - uint32_t* dataSrc1 = (uint32_t*)(jpathSrc1 + pathSrc1->data_offset); - uint32_t* dataSrc2 = (uint32_t*)(jpathSrc2 + pathSrc2->data_offset); - - for(uint16_t i=0; i < pathDest->data_size;){ - - uint32_t cmdSrc1 = *dataSrc1; - - uint32_t nb_parameters = MICROVG_PATH_get_command_parameter_number(cmdSrc1); - - *dataDest = cmdSrc1; - dataSrc1++; - dataSrc2++; - dataDest++; - i += (uint16_t) 4; - - for(uint32_t j=0; j -#include - -// ----------------------------------------------------------------------------- -// LLVG_PATH_impl.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -jint LLVG_PATH_IMPL_initializePath(jbyte* jpath, jint length) { - (void)jpath; - (void)length; - return LLVG_SUCCESS; -} - -// See the header file for the function documentation -jint LLVG_PATH_IMPL_appendPathCommand1(jbyte* jpath, jint length, jint cmd, jfloat x, jfloat y) { - (void)jpath; - (void)length; - (void)cmd; - (void)x; - (void)y; - return LLVG_SUCCESS; -} - -// See the header file for the function documentation -jint LLVG_PATH_IMPL_appendPathCommand2(jbyte* jpath, jint length, jint cmd, jfloat x1, jfloat y1, jfloat x2, - jfloat y2) { - (void)jpath; - (void)length; - (void)cmd; - (void)x1; - (void)y1; - (void)x2; - (void)y2; - return LLVG_SUCCESS; -} - -// See the header file for the function documentation -jint LLVG_PATH_IMPL_appendPathCommand3(jbyte* jpath, jint length, jint cmd, jfloat x1, jfloat y1, jfloat x2, - jfloat y2, jfloat x3, jfloat y3) { - (void)jpath; - (void)length; - (void)cmd; - (void)x1; - (void)y1; - (void)x2; - (void)y2; - (void)x3; - (void)y3; - return LLVG_SUCCESS; -} - -// See the header file for the function documentation -void LLVG_PATH_IMPL_reopenPath(jbyte* jpath) { - // nothing to do - (void)jpath; -} - -// ----------------------------------------------------------------------------- -// LLVG_PAINTER_impl.h functions -// ----------------------------------------------------------------------------- - -// See the header file for the function documentation -jint LLVG_PATH_PAINTER_IMPL_drawPath(MICROUI_GraphicsContext* gc, jbyte* pathData, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint color){ - (void)gc; - (void)pathData; - (void)x; - (void)y; - (void)matrix; - (void)fillRule; - (void)blend; - (void)color; - return LLVG_SUCCESS; -} - -// See the header file for the function documentation -jint LLVG_PATH_PAINTER_IMPL_drawGradient(MICROUI_GraphicsContext* gc, jbyte* pathData, jint x, jint y, jfloat* matrix, jint fillRule, jint blend, jint* gradientData, jfloat* gradientMatrix, jint alpha){ - (void)gc; - (void)pathData; - (void)x; - (void)y; - (void)matrix; - (void)fillRule; - (void)blend; - (void)gradientData; - (void)gradientMatrix; - (void)alpha; - return LLVG_SUCCESS; -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#endif // VG_FEATURE_PATH diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_impl.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_impl.c deleted file mode 100644 index b1f35a8..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/LLVG_impl.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * C - * - * Copyright 2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/** - * @file - * @brief MicroEJ MicroVG library low level API: basic implementation - * of matrix APIs. - * @author MicroEJ Developer Team - * @version 2.0.0 - */ - -#include - -#include "microvg_configuration.h" -#include "microvg_helper.h" -#include "microvg_font_freetype.h" - -// See the header file for the function documentation -void LLVG_IMPL_initialize(void) { - MICROVG_HELPER_initialize(); - -#if defined VG_FEATURE_FONT && \ - (defined VG_FEATURE_FONT_FREETYPE_VECTOR || defined VG_FEATURE_FONT_FREETYPE_BITMAP) && \ - (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_VECTOR || VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_BITMAP) - - MICROVG_FONT_FREETYPE_initialize(); - -#endif -} diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/freetype_bitmap_helper.c b/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/freetype_bitmap_helper.c deleted file mode 100644 index d034d52..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/microej/vg/src/freetype_bitmap_helper.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * C - * - * Copyright 2021-2022 MicroEJ Corp. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be found with this software. - */ - -/** - * @file - * @brief FREETYPE helper implementation. - * @author MicroEJ Developer Team - * @version 2.0.0 - */ - -#include "microvg_configuration.h" - -#if defined VG_FEATURE_FONT && defined VG_FEATURE_FONT_FREETYPE_BITMAP && (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_BITMAP) - - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include -#include - -#include "microvg_helper.h" -#include "freetype_bitmap_helper.h" - -// ----------------------------------------------------------------------------- -// Macros -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- -// Global Variables -// ----------------------------------------------------------------------------- - -/** - * @brief Stores the actual image width in use, calculate before printing string, that is by default the screen's width. - */ -static uint32_t image_width; - -/** - * @brief Stores the actual image height in use, calculate before printing string, that is by default the screen's height. - */ -static uint32_t image_height; - -// ----------------------------------------------------------------------------- -// Public functions -// ----------------------------------------------------------------------------- - - -int ft_helper_print_jstring_clipped(MICROUI_GraphicsContext* gc, Freetype_context_type *freetype_context, jchar* string, jint s_size, jint x, jint y, jint color, jint alpha, jfloat size, jint blend, jfloat letterSpacing){ - FT_UInt previous = 0; // previous glyph index for kerning - FT_Bool use_kerning; - int res = FREETYPE_OK; - - // Misra unused variable, to be checked - (void)size; - (void)blend; - - image_width = LLUI_DISPLAY_getStrideInPixels(&gc->image); - image_height = gc->image.height; - use_kerning = FT_HAS_KERNING(freetype_context->face); - freetype_context->slot = freetype_context->face->glyph; - - uint32_t local_x = x; - int c=0; - for(c=0;cglyph_index = FT_Get_Char_Index( freetype_context->face, string[c] ); - if (!freetype_context->glyph_index){ - MEJ_LOG_INFO_MICROVG("Warning bad glyph_index = %d \n",freetype_context->glyph_index); - } - - freetype_context->error = FT_Load_Glyph (freetype_context->face, freetype_context->glyph_index, FT_LOAD_RENDER); - if(FT_ERR(Ok) != freetype_context->error){ - MEJ_LOG_INFO_MICROVG("error while loading glyph, errno=%d \n",freetype_context->error); - res = FREETYPE_INTERNAL_ERROR; - break; - } - - // metrics structure retrieved in 64th pixel unit - uint32_t bearing_x = freetype_context->face->glyph->metrics.horiBearingX >> METRICS_DIVISOR; - uint32_t bearing_y = freetype_context->face->glyph->metrics.horiBearingY >> METRICS_DIVISOR; - uint32_t advance_aux = freetype_context->face->glyph->advance.x >> METRICS_DIVISOR; - - if (use_kerning && previous && freetype_context->glyph_index){ - FT_Vector delta; - FT_Get_Kerning(freetype_context->face, previous, freetype_context->glyph_index, FT_KERNING_DEFAULT, &delta); - local_x += (delta.x >> METRICS_DIVISOR); - } - - ft_helper_write_to_framebuffer_clipped(gc, freetype_context, (local_x + bearing_x), (y - bearing_y), color, alpha); - - local_x += advance_aux + (uint32_t) letterSpacing; - - if (local_x > (image_width - (uint32_t) FT_HELPER_X_MIN - (uint32_t) freetype_context->slot->bitmap.width)){ - MEJ_LOG_INFO_MICROVG("\n FT_HELPER_OUT_RIGHT_SCREEN_LIMIT\n"); - } - previous = freetype_context->glyph_index; - } - return res; -} - -static void ft_helper_write_to_framebuffer_clipped(MICROUI_GraphicsContext* gc, Freetype_context_type *freetype_context, jint x, jint y, jint color, jint alpha){ - jint n_rows = freetype_context->slot->bitmap.rows; - jint n_cols = freetype_context->slot->bitmap.width; - jint original_foreground_color = gc->foreground_color; - - // Misra unused variable, to be checked - (void)alpha; - - if( (0 > gc->clip_x1) || (image_width < gc->clip_x1) || (0 > gc->clip_x2) || (image_width < gc->clip_x2) || - (0 > gc->clip_y1) || (image_height < gc->clip_y1) || (0 > gc->clip_y2) || (image_height < gc->clip_y2)){ - MEJ_LOG_INFO_MICROVG("The graphics context clip is out of the screen! \n"); - MEJ_LOG_INFO_MICROVG("clip_x1 = %d ; clip_x2 = %d ; clip_y1 = %d ; clip_y2 = %d ; \n",gc->clip_x1, gc->clip_x2,gc->clip_y1, gc->clip_y2); - } else { - - // Check if we have an intersection between the glyph area and the Graphics Context's area - jint intersec_xmin = max(gc->clip_x1, x); - jint intersec_ymin = max(gc->clip_y1, y); - jint intersec_xmax = min(gc->clip_x2, x+n_cols-1); - jint intersec_ymax = min(gc->clip_y2, y+n_rows-1); - jint intersec_width = intersec_xmax - intersec_xmin +1; - jint intersec_height = intersec_ymax - intersec_ymin +1; - - if((0 >= intersec_width) || (0 >= intersec_height)){ //No intersection we leave the function - MEJ_LOG_INFO_MICROVG("\n Glyph out of the Graphics Context's area!"); - } else { - jint y_start_bitmap = intersec_ymin-y; - jint x_start_bitmap = intersec_xmin-x; - for (jint y_bitmap = y_start_bitmap; y_bitmap < (y_start_bitmap + intersec_height); ++y_bitmap) { - for (jint x_bitmap = x_start_bitmap; x_bitmap < (x_start_bitmap + intersec_width); ++x_bitmap) { - if(0x00 != freetype_context->slot->bitmap.buffer[(y_bitmap * n_cols) + x_bitmap]){ - FT_Bitmap *bitmap = &freetype_context->slot->bitmap; - uint32_t pix_gray_color = bitmap->buffer[(y_bitmap * bitmap->width) + x_bitmap]; - uint32_t background_argb = LLUI_DISPLAY_readPixel(&gc->image, intersec_xmin + x_bitmap, intersec_ymin + y_bitmap); - uint32_t blended_color = LLUI_DISPLAY_blend(color, background_argb, pix_gray_color); - gc->foreground_color = blended_color; - UI_DRAWING_writePixel(gc, intersec_xmin + x_bitmap, intersec_ymin + y_bitmap); - }else{ - // Black pixel is for background, we let the pixel buffer as it is. - } - } - } - // Set back configured color - gc->foreground_color = original_foreground_color; - } - } -} - -void ft_helper_free(Freetype_context_type *freetype_context){ - FT_Done_Face ( freetype_context->face ); - FT_Done_FreeType( freetype_context->library ); -} - -// ----------------------------------------------------------------------------- -// EOF -// ----------------------------------------------------------------------------- - -#endif // #if (VG_FEATURE_FONT == VG_FEATURE_FONT_FREETYPE_BITMAP) diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/CMakeLists.txt b/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/CMakeLists.txt deleted file mode 100644 index 2d7f541..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/CMakeLists.txt +++ /dev/null @@ -1,313 +0,0 @@ -# CROSS COMPILER SETTING -SET(CMAKE_SYSTEM_NAME Generic) -CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) - -# CURRENT DIRECTORY -SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) - -if (NOT DEFINED SdkOverlayRootDirPath) - SET(SdkOverlayRootDirPath ${ProjDirPath}/../../../sdk_overlay/) -endif() - -if (NOT DEFINED SdkRootDirPath) - SET(SdkRootDirPath ${ProjDirPath}/../../../mcux-sdk/core/) -endif() - -if (NOT DEFINED RtosRootDirPath) - SET(RtosRootDirPath ${ProjDirPath}/../../../mcux-sdk/rtos/) -endif() - -if (NOT DEFINED MicroejDirPath) - SET(MicroejDirPath ${ProjDirPath}/../../microej/) -endif() - -SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) -SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) -message(${EXECUTABLE_OUTPUT_PATH}) - -set(MCUX_BUILD_TYPES debug release) - -find_package(Git) - -project(mimxrt595_freertos-bsp C) - -file (STRINGS "${ProjDirPath}/../../../nvee_version.txt" VEE_VERSION) - -set(MCUX_DEVICE MIMXRT595S_cm33) -set(PROJECT_NAME mimxrt595_freertos-bsp) -set(MCUX_SDK_PROJECT_NAME ${PROJECT_NAME}.elf) - -# config to select component, the format is CONFIG_USE_${component} -set(CONFIG_USE_component_serial_manager_uart true) -set(CONFIG_USE_driver_flexcomm_usart true) - -include (${ProjDirPath}/flags.cmake) - -execute_process(COMMAND - "${GIT_EXECUTABLE}" describe --always --abbrev=8 --dirty - WORKING_DIRECTORY "${ProjDirPath}" - OUTPUT_VARIABLE GIT_SHA_1 - ERROR_QUIET OUTPUT_STRIP_TRAILING_WHITESPACE) - -configure_file("${ProjDirPath}/../main/src/tree_version.c.in" "${CMAKE_CURRENT_BINARY_DIR}/tree_version.c" @ONLY) - -add_executable(${MCUX_SDK_PROJECT_NAME} - "${ProjDirPath}/../board/src/board.c" - "${ProjDirPath}/../board/src/clock_config.c" - "${ProjDirPath}/../board/src/display_support.c" - "${ProjDirPath}/../board/src/pin_mux.c" - "${ProjDirPath}/../freertos/src/SEGGER_SYSVIEW_Config_FreeRTOS.c" - "${ProjDirPath}/../simple_gfx_app/src/simple_gfx_app_imp.c" - "${ProjDirPath}/../main/src/cpuload.c" - "${ProjDirPath}/../main/src/cpuload_impl_FreeRTOS.c" - "${ProjDirPath}/../main/src/fault_handlers.c" - "${ProjDirPath}/../main/src/interrupts.c" - "${ProjDirPath}/../main/src/LLBSP.c" - "${ProjDirPath}/../main/src/LLEXT_RES_impl.c" - "${ProjDirPath}/../main/src/LLMJVM_FreeRTOS.c" - "${ProjDirPath}/../main/src/main.c" - "${ProjDirPath}/../main/src/microjvm_main.c" - "${ProjDirPath}/../main/src/monitor.c" - "${ProjDirPath}/../main/src/os_support.c" - "${ProjDirPath}/../main/src/stack_overflow_impl_FreeRTOS.c" - "${ProjDirPath}/../main/src/time_hardware_timer.c" - "${ProjDirPath}/../main/src/trace_platform.c" - "${MicroejDirPath}/osal/src/osal_FreeRTOS.c" - "${MicroejDirPath}/lowpower/src/power_manager.c" - "${MicroejDirPath}/lowpower/src/fsl_tickless_rtc.c" - "${MicroejDirPath}/thirdparty/freetype/src/wrappers/ft_base_wrapper.c" - "${MicroejDirPath}/thirdparty/freetype/src/wrappers/ft_otf_wrapper.c" - "${MicroejDirPath}/thirdparty/freetype/src/wrappers/ft_ttf_wrapper.c" - "${MicroejDirPath}/thirdparty/freetype/src/wrappers/ft_vector_wrapper.c" - "${MicroejDirPath}/thirdparty/harfbuzz/src/hb-alloc.c" - "${MicroejDirPath}/thirdparty/systemview/src/SEGGER_RTT.c" - "${MicroejDirPath}/thirdparty/systemview/src/SEGGER_SYSVIEW.c" - "${MicroejDirPath}/thirdparty/systemview-freertos/src/SEGGER_SYSVIEW_FreeRTOS.c" - "${MicroejDirPath}/trace/src/LLMJVM_MONITOR_sysview.c" - "${MicroejDirPath}/trace/src/LLTRACE_sysview.c" - "${MicroejDirPath}/ui/src/buttons_helper.c" - "${MicroejDirPath}/ui/src/buttons_manager.c" - "${MicroejDirPath}/ui/src/display_dma.c" - "${MicroejDirPath}/ui/src/display_framebuffer.c" - "${MicroejDirPath}/ui/src/display_impl.c" - "${MicroejDirPath}/ui/src/display_utils.c" - "${MicroejDirPath}/ui/src/display_vglite.c" - "${MicroejDirPath}/ui/src/drawing_vglite.c" - "${MicroejDirPath}/ui/src/event_generator.c" - "${MicroejDirPath}/ui/src/framerate.c" - "${MicroejDirPath}/ui/src/framerate_impl_FreeRTOS.c" - "${MicroejDirPath}/ui/src/LLDW_PAINTER_impl.c" - "${MicroejDirPath}/ui/src/LLUI_DISPLAY_impl.c" - "${MicroejDirPath}/ui/src/LLUI_INPUT_impl.c" - "${MicroejDirPath}/ui/src/LLUI_PAINTER_impl.c" - "${MicroejDirPath}/ui/src/touch_helper.c" - "${MicroejDirPath}/ui/src/touch_manager.c" - "${MicroejDirPath}/ui/src/vg_drawer.c" - "${MicroejDirPath}/ui/src/vglite_path.c" - "${MicroejDirPath}/util/src/mej_debug.c" - "${MicroejDirPath}/util/src/mej_math.c" - "${MicroejDirPath}/util/src/pool.c" - "${MicroejDirPath}/vg/src/freetype_bitmap_helper.c" - "${MicroejDirPath}/vg/src/LLVG_BVI_impl.c" - "${MicroejDirPath}/vg/src/LLVG_FONT_freetype.c" - "${MicroejDirPath}/vg/src/LLVG_FONT_PAINTER_freetype_bitmap.c" - "${MicroejDirPath}/vg/src/LLVG_FONT_PAINTER_freetype_vglite.c" - "${MicroejDirPath}/vg/src/LLVG_FONT_stub.c" - "${MicroejDirPath}/vg/src/LLVG_GRADIENT_impl.c" - "${MicroejDirPath}/vg/src/LLVG_impl.c" - "${MicroejDirPath}/vg/src/LLVG_MATRIX_impl.c" - "${MicroejDirPath}/vg/src/LLVG_PATH_impl.c" - "${MicroejDirPath}/vg/src/LLVG_PATH_PAINTER_vglite.c" - "${MicroejDirPath}/vg/src/LLVG_PATH_stub.c" - "${MicroejDirPath}/vg/src/LLVG_vglite.c" - "${MicroejDirPath}/vg/src/microvg_helper.c" - "${MicroejDirPath}/vglite_support/vglite_support.c" - "${MicroejDirPath}/vglite_window/vglite_window.c" - "${MicroejDirPath}/stub/src/stub.c" - "${SdkRootDirPath}/devices/MIMXRT595S/mcuxpresso/startup_mimxrt595s_cm33.c" - ${CMAKE_CURRENT_BINARY_DIR}/tree_version.c -) - -target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE - ${ProjDirPath}/.. - ${ProjDirPath}/../board/inc - ${ProjDirPath}/../freertos/inc - ${ProjDirPath}/../main/inc - ${MicroejDirPath}/lowpower/inc - ${MicroejDirPath}/trace/inc - ${MicroejDirPath}/ui/inc - ${MicroejDirPath}/util/inc - ${MicroejDirPath}/vg/inc - ${MicroejDirPath}/thirdparty/systemview/inc - ${MicroejDirPath}/thirdparty/systemview-freertos/inc - ${MicroejDirPath}/thirdparty/freetype/inc - ${MicroejDirPath}/osal/inc - ${MicroejDirPath}/platform/inc - ${MicroejDirPath}/vglite_support - ${MicroejDirPath}/vglite_window - ${MicroejDirPath}/thirdparty/harfbuzz/inc -) - -add_definitions( - -D__USE_CMSIS - -DDEBUG - -DFSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1 - -DBOOT_HEADER_ENABLE=1 - -DCPU_MIMXRT595SFFOB_cm33 - -DBOARD_ENABLE_PSRAM_CACHE=0 - -DFLEXIO_MCULCD_DATA_BUS_WIDTH=8 - -DDBI_FLEXIO_USE_SMARTDMA=1 - -DCUSTOM_VGLITE_MEMORY_CONFIG=1 - -DVG_RESOLVE_ENGINE=0 - -DVG_PE_COLOR_KEY=0 - -DVG_IM_INDEX_FORMAT=0 - -DVG_AYUV_INPUT_OUTPUT=0 - -DVG_DOUBLE_IMAGE=0 - -DVG_RECTANGLE_STRIP_MODE=0 - -DVG_MMU=0 - -DVG_DRIVER_SINGLE_THREAD=1 - -DVG_IM_FILTER=0 - -DVG_IM_YUV_PACKET=1 - -DVG_IM_YUV_PLANAR=0 - -DVG_PE_YUV_PACKET=1 - -DVG_TARGET_TILED=1 - -DVG_COMMAND_CALL=1 - -DVG_SHARE_BUFFER_IM_16K=0 - -DVG_OFFLINE_MODE=0 - -DVG_RESOLUTION_2880=0 - -DVG_PE_PREMULTIPLY=0 - -DVG_POST_CONVERTER=0 - -DVG_PRE_CONVERTER=0 - -DVG_RENDER_BY_MESH=0 - -DVG_TARGET_FAST_CLEAR=0 - -DVG_BUFFER_NUMBER_OF_TARGET=0 - -DVG_VIDEO_CLEAR_CONTROL=0 - -DVG_VIDEO_CONTROL=0 - -DVGLITE_TST_FIRMWARE=0 - -DVG_LITE_SYS_GPU_CTRL=0 - -DSERIAL_PORT_TYPE_UART=1 - -DFSL_RTOS_FREE_RTOS - -DPRINTF_FLOAT_ENABLE=1 - -DPRINTF_ADVANCED_ENABLE=1 - -DENABLE_SVIEW=1 - -DSDK_I2C_BASED_COMPONENT_USED=1 - -D_VG_LITE_IRQ_CALLBACK=1 - -DSL_WFX_PROD_KEY=1 - -DLWIP_2_1_2 - -DSDK_DEBUGCONSOLE_UART - -DFT_CONFIG_MODULES_H=\"freetype/config/ftmodule.h\" - -DFT2_BUILD_LIBRARY - -DRTT_USE_ASM=0 -) - -SET(CMAKE_MODULE_PATH - ${SdkRootDirPath}/boards/evkmimxrt595/flash_config/ - ${SdkRootDirPath}/components/ft3267 - ${SdkRootDirPath}/components/serial_manager - ${SdkRootDirPath}/components/pca9420 - ${SdkRootDirPath}/components/lists - ${SdkRootDirPath}/components/uart - ${SdkRootDirPath}/components/video - ${SdkRootDirPath}/components/video/display - ${SdkRootDirPath}/components/video/display/dbi - ${SdkRootDirPath}/components/video/display/dbi/flexio - ${SdkRootDirPath}/components/video/display/dc - ${SdkRootDirPath}/components/video/display/dc/ssd1963 - ${SdkRootDirPath}/components/video/display/dc/lcdif - ${SdkRootDirPath}/components/video/display/dc/dsi_cmd - ${SdkRootDirPath}/components/video/display/fbdev - ${SdkRootDirPath}/components/video/display/mipi_dsi_cmd - ${SdkRootDirPath}/components/video/display/rm67162 - ${SdkRootDirPath}/components/video/display/rm68191 - ${SdkRootDirPath}/components/video/display/rm68200 - ${SdkRootDirPath}/CMSIS/Core/Include - ${SdkRootDirPath}/CMSIS/DSP - ${SdkRootDirPath}/devices/MIMXRT595S - ${SdkRootDirPath}/devices/MIMXRT595S/drivers/ - ${SdkRootDirPath}/devices/MIMXRT595S/utilities/ - ${SdkRootDirPath}/devices/MIMXRT595S/utilities/debug_console/ - ${SdkRootDirPath}/drivers/common/ - ${SdkRootDirPath}/drivers/flexcomm/ - ${SdkRootDirPath}/drivers/mipi_dsi/ - ${SdkRootDirPath}/drivers/lpc_dma/ - ${SdkRootDirPath}/drivers/flexio/ - ${SdkRootDirPath}/drivers/flexspi/ - ${SdkRootDirPath}/drivers/inputmux/ - ${SdkRootDirPath}/drivers/lpc_gpio/ - ${SdkRootDirPath}/drivers/powerquad/ - ${SdkRootDirPath}/drivers/lpc_rtc/ - ${SdkRootDirPath}/drivers/smartdma/ - ${SdkRootDirPath}/drivers/trng/ - ${SdkRootDirPath}/drivers/ - ${SdkRootDirPath}/utilities/debug_console/ - ${SdkRootDirPath}/utilities/misc_utilities/ - ${SdkRootDirPath}/utilities/assert/ - ${SdkRootDirPath}/utilities/ - ${SdkRootDirPath}/drivers/cache/cache64/ - ${SdkRootDirPath}/drivers/ctimer/ - ${SdkRootDirPath}/drivers/lpc_iopctl/ - ${SdkRootDirPath}/drivers/pint/ - ${SdkOverlayRootDirPath}/rtos/amazon-freertos/freertos_kernel/ - ${SdkOverlayRootDirPath}/middleware/vglite/ -) - -# include modules -include(driver_pca9420) -include(component_usart_adapter) -include(component_lists) -include(component_serial_manager) -include(component_serial_manager_uart) -include(device_CMSIS) -include(driver_cache_cache64) -include(driver_clock) -include(driver_common) -include(driver_ctimer) -include(driver_dbi_flexio_smartdma) -include(driver_dc-fb-dsi-cmd) -include(driver_display-rm67162) -include(driver_display-rm68191) -include(driver_display-rm68200) -include(driver_fbdev) -include(driver_flash_config_evkmimxrt595) -include(driver_flexcomm_i2c) -include(driver_flexcomm) -include(driver_flexcomm_usart_dma) -include(driver_flexcomm_usart) -include(driver_flexio) -include(driver_flexio_spi) -include(driver_flexspi) -include(driver_ft3267) -include(driver_iap) -include(driver_inputmux) -include(driver_lpc_dma) -include(driver_lpc_gpio) -include(driver_lpc_rtc) -include(driver_lpc_smartdma) -include(driver_mipi_dsi) -include(driver_mipi_dsi_smartdma) -include(driver_power) -include(driver_powerquad_cmsis) -include(driver_powerquad) -include(driver_reset) -include(driver_trng) -include(driver_video-common) -include(middleware_freertos-kernel_cm33_nonsecure_port) -include(middleware_freertos-kernel_heap_4) -include(middleware_freertos-kernel_MIMXRT595S_cm33) -include(middleware_vglite_MIMXRT595S_cm33) -include(utilities_misc_utilities_MIMXRT595S_cm33) -include(utility_assert) -include(utility_debug_console) -include(driver_lpc_iopctl) -include(driver_pint) - -TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE - ${MicroejDirPath}/platform/lib/microejapp.o - ${MicroejDirPath}/platform/lib/microejruntime.a - ${MicroejDirPath}/thirdparty/harfbuzz/lib/harfbuzz.a -) - -ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} --Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/${PROJECT_NAME}.bin) -ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} --Oihex ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/${PROJECT_NAME}.hex) diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_all.bat b/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_all.bat deleted file mode 100644 index 4daab91..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_all.bat +++ /dev/null @@ -1,20 +0,0 @@ -SET FLAVOUR=Unix Makefiles -SET CMD=make -j -IF "%~1" == "ninja" ( - SET FLAVOUR=Ninja - SET CMD=ninja -) - -if exist CMakeFiles (RD /s /Q CMakeFiles) -if exist Makefile (DEL /s /Q /F Makefile) -if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) -if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) -cmake -DCMAKE_TOOLCHAIN_FILE="../../../mcux-sdk/core/tools/cmake_toolchain_files/armgcc.cmake" -G "%FLAVOUR%" -DCMAKE_BUILD_TYPE=debug . -%CMD% - -if exist CMakeFiles (RD /s /Q CMakeFiles) -if exist Makefile (DEL /s /Q /F Makefile) -if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) -if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) -cmake -DCMAKE_TOOLCHAIN_FILE="../../../mcux-sdk/core/tools/cmake_toolchain_files/armgcc.cmake" -G "%FLAVOUR%" -DCMAKE_BUILD_TYPE=release . -%CMD% diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_all.sh b/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_all.sh deleted file mode 100755 index 3baf650..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_all.sh +++ /dev/null @@ -1,24 +0,0 @@ -#!/bin/sh - -FLAVOUR='Unix Makefiles' -CMD='make -j' - -if [ "${1}" = "ninja" ] -then - FLAVOUR='Ninja' - CMD='ninja' -fi - -if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi -if [ -f "Makefile" ];then rm -f Makefile; fi -if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi -if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi -cmake -DCMAKE_TOOLCHAIN_FILE="../../../mcux-sdk/core/tools/cmake_toolchain_files/armgcc.cmake" -G "${FLAVOUR}" -DCMAKE_BUILD_TYPE=debug . -${CMD} - -if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi -if [ -f "Makefile" ];then rm -f Makefile; fi -if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi -if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi -cmake -DCMAKE_TOOLCHAIN_FILE="../../../mcux-sdk/core/tools/cmake_toolchain_files/armgcc.cmake" -G "${FLAVOUR}" -DCMAKE_BUILD_TYPE=release . -${CMD} diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_debug.bat b/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_debug.bat deleted file mode 100644 index 2a3e895..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_debug.bat +++ /dev/null @@ -1,13 +0,0 @@ -SET FLAVOUR=Unix Makefiles -SET CMD=make -j -IF "%~1" == "ninja" ( - SET FLAVOUR=Ninja - SET CMD=ninja -) - -if exist CMakeFiles (RD /s /Q CMakeFiles) -if exist Makefile (DEL /s /Q /F Makefile) -if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) -if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) -cmake -DCMAKE_TOOLCHAIN_FILE="../../../mcux-sdk/core/tools/cmake_toolchain_files/armgcc.cmake" -G "%FLAVOUR%" -DCMAKE_BUILD_TYPE=debug . -%CMD% diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_debug.sh b/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_debug.sh deleted file mode 100755 index bbeef9f..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_debug.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/sh - -FLAVOUR='Unix Makefiles' -CMD="make -j $(nproc)" - -if [ "${1}" = "ninja" ] -then - FLAVOUR='Ninja' - CMD='ninja' -fi - -if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi -if [ -f "Makefile" ];then rm -f Makefile; fi -if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi -if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi -cmake -DCMAKE_TOOLCHAIN_FILE="../../../mcux-sdk/core/tools/cmake_toolchain_files/armgcc.cmake" -G "${FLAVOUR}" -DCMAKE_BUILD_TYPE=debug . -${CMD} diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_release.bat b/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_release.bat deleted file mode 100644 index ee999a0..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_release.bat +++ /dev/null @@ -1,13 +0,0 @@ -SET FLAVOUR=Unix Makefiles -SET CMD=make -j -IF "%~1" == "ninja" ( - SET FLAVOUR=Ninja - SET CMD=ninja -) - -if exist CMakeFiles (RD /s /Q CMakeFiles) -if exist Makefile (DEL /s /Q /F Makefile) -if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) -if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) -cmake -DCMAKE_TOOLCHAIN_FILE="../../../mcux-sdk/core/tools/cmake_toolchain_files/armgcc.cmake" -G "%FLAVOUR%" -DCMAKE_BUILD_TYPE=release . -%CMD% diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_release.sh b/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_release.sh deleted file mode 100755 index cccb45a..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/build_release.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/sh - -FLAVOUR='Unix Makefiles' -CMD="make -j $(nproc)" - -if [ "${1}" = "ninja" ] -then - FLAVOUR='Ninja' - CMD='ninja' -fi - -if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi -if [ -f "Makefile" ];then rm -f Makefile; fi -if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi -if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi -cmake -DCMAKE_TOOLCHAIN_FILE="../../../mcux-sdk/core/tools/cmake_toolchain_files/armgcc.cmake" -G "${FLAVOUR}" -DCMAKE_BUILD_TYPE=release . -${CMD} diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/clean.bat b/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/clean.bat deleted file mode 100644 index f2a6c03..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/clean.bat +++ /dev/null @@ -1,4 +0,0 @@ -RD /s /Q CMakeFiles -DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt -IF EXIST debug RD /s /Q debug -IF EXIST release RD /s /Q release diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/clean.sh b/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/clean.sh deleted file mode 100755 index dd869de..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/clean.sh +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh -rm -rf CMakeFiles -rm -rf Makefile cmake_install.cmake CMakeCache.txt -rm -rf debug release diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/flags.cmake b/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/flags.cmake deleted file mode 100644 index 81aeae9..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/armgcc/flags.cmake +++ /dev/null @@ -1,78 +0,0 @@ -IF(NOT DEFINED FPU) - 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${CMAKE_C_FLAGS_RELEASE} \ - -DCPU_MIMXRT595SFFOC_cm33 \ - -mcpu=cortex-m33 \ - -mthumb -nostdlib \ - -O3 \ - -fno-common \ - -g3 \ - -Wall \ - -ffunction-sections \ - -fdata-sections \ - -ffreestanding \ - -fno-builtin-specs=nano.specs \ - -MMD \ - -MP \ - ${FPU} \ -") - -SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ - -Xlinker --gc-sections \ - -Xlinker -print-memory-usage \ - -Xlinker --sort-section=alignment \ - -Xlinker -Map=${ProjDirPath}/${CMAKE_BUILD_TYPE}/${PROJECT_NAME}.map \ - -u _printf_float \ - -L${ProjDirPath} \ - -T${ProjDirPath}/mimxrt595_freertos-bsp_Debug.ld \ -") diff --git a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/sdk_makefile/Makefile b/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/sdk_makefile/Makefile deleted file mode 100644 index 89e2539..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/projects/nxpvee-ui/sdk_makefile/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: BSD-3-Clause -# -TARGET=mimxrt595_freertos-bsp -DEVICE=MIMXRT595S_M33 -ADDRESS=0x08000000 -FLAVOUR=debug - -ifeq ($(strip $(RELEASE)),1) -FLAVOUR=release -endif - -include ../../common/sdk_makefile/Makefile diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/ChangeLogKSDK.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/ChangeLogKSDK.txt deleted file mode 100644 index 732ffd8..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/ChangeLogKSDK.txt +++ /dev/null @@ -1,261 +0,0 @@ -/*! -@page middleware_log Middleware Change Log - -@section vglite VGLite GPU Driver - The current version of the VGLite GPU Driver is 3.0.15_rev4. - - version 3.0.15_rev4 - - Changed: - - (IMX-2900) Renamed build switch for disabling driver multithread support - - version 3.0.15_rev3 - - Fixed: - - Relocated centerX/Y definitions in vg_lite.c - - (IMX-2918) Reduced vg_lite_finish() delay when it has nothing to do - - (IMX-2901) Fixed reversed red and blue channels in colour gradients fill colour - - (IMX-2901) Fixed linear gradient matrix transformation error - - (IMX-2901) Fixed radial gradient render error - - Changed: - - (IMX-2799) Enabled GPU auto clock gating by default - - (IMX-2799) Added build switch to disable GPU auto clock gating - - Added: - - (IMX-2900) Added initial support for single thread mode - - version 3.0.15_rev2 - - Fixed: - - (IMX-2881) Fixed memory leaks in vector path stroking implementation - - (IMX-2863) Fixed stroked polygons rendering issue - - (IMX-2842) Fixed system hang when drawing circular arcs - - (MGG-897) Use OS heap instead of application heap for stroked vector polygons - - (MGG-897) Use OS heap instead of application heap for ciecular arc rendering - - Changed: - - (IMX-2863) Allow users to configure fill colour for stroked & filled vector paths - - version 3.0.15_rev1 - - Fixed: - - (IMX-2844) Fixed missing path descriptor initialization in "vg_lite_init_arc_path" - - (IMX-2837) Fixed arc drawing direction - - (IMX-2811) Added VGPE flush after buffer clear - - Changed: - - (IMX-2835) Optimized storage of radial gradients params to allow memory saving - - Added: - - Added dithering support for RT11xx platforms - - Added color keying support for RT11xx platforms - - (IMX-2817) Added vector path stroking - - (IMX-2692) Added support for HW accelerated linear gradients on RT11xx platforms - - version 3.0.13_rev2 - - Fixed: - - (MGG-793) Fixed clipping issue when using the RT500 blit output quality workaround - - (MGG-830) Disabled RT500 blit output quality workaround for non-affine graphic transformations - - (IMX-2701) Fixed memory leak in vector arc drawing API - - (IMX-2699) Fixed build warnings in vector arc drawing API - - (MGG-836) Fixed the font/text support via main VGLite driver API - - Changed: - - (IMX-1724) Changed image width 16 pixels alignment to stride 16 byte alignment - - (MCUX-46210) Dropped useless "const" qualifier for the "name" attribute of "vg_lite_font_params_t" data structure - - (MGG-836) Reordered "vg_lite_draw_text" API arguments - - version 3.0.13_rev1 - - Fixed: - - (IMX-2577) Fixed support for colour palettes (CLUT) in multithread mode - - (MGG-735) Fixed Elementary library instability caused by using calloc/free in ElmWrapBuffer - - Changed: - - (IMX-2600) Updated "vg_lite_finish" to wait for all frames previously submitted with "vg_lite_flush" - - Aligned "vg_lite_radial_gradient_parameter" data struct with parameters in Elementary EVO object - - Added: - - Added support for drawing vector arcs/circles - - Added support for i.MXRT6Q GPU - - Added support for GCNanoliteV GPU Rev. 0x1322 - - Added vector arcs support in Elementary library - - version 3.0.11_rev3 - - Fixed: - - Fix async event reset after being initialized - - (IMX-2604) Fix polygon's rendering regression in multitasking scenarios - - Avoid "vg_lite_blit" modifying user's transformation matrix - - version 3.0.11_rev2 - - Fixed: - - (MGG-685) Added workaround to improve "blit" output quality for RT500 - - (MCUX-43004) Fixed clipping window regression issue introduced by VGLite 3.0.11.1 - - (MGG-764) Fixed VGLite heap useless splitting of memory nodes - - (MGG-765) Fixed regression issue introduced by VGLite 3.0.11.1 when loading graphic resources using Elementary library - - (IMX-2506) Fixed "vg_lite_update_rad_grad" not checking the result of memory allocation - - (MCUX-42992) Fixed IAR toolchain not recognizing optimization directive - - (MGG-763) Remove risk of out-of-bounds read in "vg_lite_update_rad_grad" function - - Changed: - - (IMX-2527) Improved memory footprint by using a common tessellation buffer for all drawing tasks - - (MGG-712) Restructured OS abstraction layer to allow easier integration with popular OSes - - version 3.0.11_rev1 - - Fixed: - - (IMX-2502) Fixed GPU command buffer overflow when copying context data - - (IMX-2503) Fixed additional colour ring incorrectly appearing at the edge of radial gradients - - (IMX-2487) Fixed risk of memory leak in "vg_lite_upload_path" - - (IMX-2429) Fixed incorrect blending of A4 and A8 images (regression since VGLite 3.0.4.x) - - (MGG-687) Fixed build warning when VG_RENDER_TEXT feature is disabled - - Changed: - - (IMX-2354) Added support for dynamic command buffer size management - - Added: - - (IMX-2435) Added new API function - vg_lite_get_transform_matrix - to calculate parameters for 2D perspective transformations - - (IMX-2411) Added support for radial gradients in Elementary library - - (IMX-2026) Added support for images embedded in EVO data in Elementary library - - (IMX-2026) Added support for patterns embedded in EVO data in Elementary library - - version 3.0.9_rev2 - - Fixed: - - (MCUX-40557) Fixed build warnings - - version 3.0.9_rev1 - - Fixed: - - (MGG-648) Fixed rendered text overlapping issue - - (MGG-650) Fixed memory leak caused by failure to unload RLE font data - - (IMX-2395) Fixed incorrect reporting of indexed images as "supported" for GC355 GPU (RT1170) - - Changed: - - (IMX-2370) Refactored GPU driver HAL and OS layers - - (MGG-646) Configured a vector font as default font - - version 3.0.9 - - Fixed: - - (IMX-2361) Fixed tessellation bounds computation error - - Changed: - - (IMX-2367) Enabled alpha channel premultiplication by default for GC355 GPU (RT1170) - - (IMX-2261) Added Elementary library input data address alignment verification - - Added: - - (IMX-2323) Added support for radial colour gradients for GC355 GPU (RT1170) - - (IMX-2317) Upgraded the Elementary library to be thread safe - - version 3.0.6_rev4 - - Fixed: - - (IMX-2357) Fixed rendering performance degradation since the implementation of the multithread/multicontext support - - (MGG-576) Elementary: Fixed hard fault when resetting translation of EVO object - - (MCUX-38672) Fixed font and text support build warnings - - (MGG-596) Fixed memory leak in raster font loading - - (MGG-596) Font and text support: Fixed out of range memory access in Elementary library - - Changed: - - (MGG-596) "VG_RENDER_TEXT=1" build symbol now required to enable font and text support - - (MGG-594) Updated font and text support to allow easy decoupling from GPU driver and Elementary when not needed - - (MGG-533) Removed "is_tspan" attribute from "vg_lite_font_attributes_t" - - (MGG-533) Added new attribute "tspan_has_dx_dy" to "vg_lite_font_attributes_t" - - (MGG-533) Added new argument "matrix" to "vg_lite_draw_text" API function - - (MGG-592) Renamed "eFontTypes_t" enum to "eFontType_t" - - (MGG-592) Renamed "eFontVectorType" identifier to "eFontTypeVector" - - (MGG-592) Renamed "eFontRasterType" identifier to "eFontTypeRaster" - - (MGG-596) Changed "vg_lite_draw_text" function return value from "int" to "vg_lite_error_t" - - Added: - - (MGG-596) Added "vg_lite_find_font" API function - - (MGG-596) Added 2 new error codes for "vg_lite_error_t": VG_LITE_ALREADY_EXISTS and VG_LITE_NOT_ALIGNED - - (IMX-2357) Allow users to override command queue task priority at build time using QUEUE_TASK_PRIO build symbol - - (MGG-551) Added text wrapping support for vector fonts - - (MGG-533) Added support for text right alignment - - version 3.0.6_rev3 - - Added: - - (MGG-551) Added support for font and text rendering - - version 3.0.6_rev2 - - Fixed: - - (IMX-2292) Fixed command buffer flushing after draw - - (IMX-2293) Fixed copy of register status when command buffer was not full - - (IMX-2305) Fixed scissor window taking no effect - - (IMX-2324) Fixed GPU feature table reset when calling "vg_lite_close" - - (IMX-2358) Fixed misuse of address operator in checking colour channel premultiplication flag - - (MGG-542) Cleaned up useless "memset" in "vg_lite_init" - - version 3.0.6_rev1 - - Fixed: - - (IMX-2295) Initialize task context to zero in vg_lite_init() - - version 3.0.6 - - Fixed: - - (MGG-525) Fixed "vg_lite_init_path" not properly initializating the "path" data structure - - Changed: - - (IMX-2255) Updated "vg_lite_set_scissor" arguments to (x, y, width, height) instead of (x0, y0, x1, y1) - - Added: - - (IMX-2104) Added API to enable/disable colour channel pre-multiplication at runtime on RT1170 - - version 3.0.5 - - Fixed: - - (IMX-2252) Reset global mutex when it is destroyed - - (IMX-2252) Fixed reset of task local context in vg_lite_close() - - Changed: - - (MGG-333) Enabled scissoring for GC255 GPU (i.MXRT500) - - Added: - - (IMX-1729) Added support for drawing from multiple threads - - version 3.0.4_rev5 - - Changed: - - (IMX-2104) Disabled by default colour channel pre-multiplication on RT1170 platform - - (MGG-517) Updated "vg_lite_draw_pattern" function to return VG_LITE_NOT_SUPPORT for A4/A8 patterns - - Fixed: - - (IMX-2155) Fixed hard coded image mode in "vg_lite_draw_pattern" - - (IMX-2153) Updated "vg_lite_draw_pattern" to take into account pattern transparency - - (KPSDK-37093) Elementary library - Fixed bad free in "load_evo" - - (KPSDK-37093) Elementary library - Avoid resource leak in "ElmCreateBuffer" - - version 3.0.4_rev4 - - Fixed: - - Fixed empty function argument lists definition for scissoring related API functions - - (IMX-1995) Extended RT500 image rotation fix to vg_lite_blit_rect, vg_lite_draw_pattern - - (IMX-1995) Isolated RT500 image rotation fix effects to RT500 platform only - - version 3.0.4_rev3 - - Fixed: - - (IMX-1995) Compensated for RT500 image shift effect when rotation is approaching multiples of 90 dgs - - version 3.0.4_rev2 - - Fixed: - - Fixed integration issue of "vg_lite_mem_avail" API - - version 3.0.4_rev1 - - Changed: - - (IMX-1768) Enabled users to query, at runtime, the support for VG_LITE_UPPER draw quality - - Fixed: - - (IMX-2074) Fixed GPU exception handling issue - - Added: - - (IMX-2045) Added API to provide available heap memory - - version 3.0.4 - - Changed: - - (IMX-1957) Enabled users to query, at runtime, the support for BORDER_CULLING and SCISSOR features - - Enable users to query, at runtime, the support for RGBA 2 bits-per-channel image formats - - Fixed: - - (IMX-1934) Fixed image stride alignment verification for TILED images - - Fix GC355 GPU (i.MXRT1170) draw error when tessellation window width is not aligned to 128 - - Added: - - (MGG-333) Added support for GC355 GPU (i.MXRT1170) scissoring - - version 3.0.1_rev1 - - Fixed: - - (MGG-250) Fixed GPU hang after a random time (mostly reproduced on RT1170 platforms) - - (KPSDK-33132) Fixed Elementary library memory leaks in case of failed EBO loading - - (MGG-336) Allow use of blend modes not affected by the border culling limitation - - (MGG-18) Fixed Elementary library memory leaks when loading EVO/EBO/EGO objects - - (MGG-353) Fixed linear colour gradient rendering error when loading EVOs using the Elementary library - - version 3.0.1 - - Changed: - - Removed "vg_lite_blit2" API function due to lack of hardware support - - Removed "vg_lite_scanline" API function due to lack of harware support - - Aggregated "vg_lite_error.h" API header file content into "vg_lite.h" - - Aggregated "vg_lite_features.h" API header file content into "vg_lite.h" - - Aggregated "vg_lite_matrix.h" API header file content into "vg_lite.h" - - Aggregated "vg_lite_path.h" API header file content into "vg_lite.h" - - Aggregated "vg_lite_util.h" API header file content into "vg_lite.h" - - (IMX-1861) Added return code to the "vg_lite_flush" API function - - Changed VGLite GPU driver license from proprietary to MIT - - Fixed: - - Fixed definition of "elm_alloc" function in Elementary toolkit - - (IMX-1869) Fixed initialization of aligned bytes in the command buffer - - (IMX-1821) Fixed inverted background colours when using "vg_lite_draw_pattern" - - Fixed hang when calling "vg_lite_flush" repeatedly - - (IMX-1861) Fix propagation of return codes from "stall", "submit", "vg_lite_flush" function calls - - version 2.0.14_rev1 - - Changed: - - (IMX-1809) Fixed misspelling of "vg_lite_buffer_transparency_mode" - - (IMX-1778) Added verification of colour gradients parameters - - (IMX-1813) Added return code to the "vg_lite_hal_allocate_contiguous" function - - (MGG-204) Added return code to "vg_lite_finish" - - Fixed: - - (IMX-1808) Fixed "vg_lite_blit" failure on dynamically allocated buffers - - (IMX-1773) Fixed failure to create 16 colours gradients - - (IMX-1790) Fixed driver incorrectly reporting available heap space - - (IMX-1810) Fixed verification of raster image stride alignment - - (IMX-1810) Fixed verification of raster image colour depth - - (IMX-1816) Fixed "vg_lite_close" not releasing memory allocated from OS heap - - (MGG-201) Fixed hard fault caused by command buffer management - - (MGG-202) Fixed "vg_lite_hal_wait_interrupt" function ignoring the timeout - - (MGG-203) Fixed "vg_lite_draw" function always returning success - - version 2.0.13_rev2 - - Fixed: - - (MGG-102) Fixed incorrect colour gradient clipping issue when using "vg_lite_draw_gradient" API - - (MGG-140) Fixed "vg_lite_draw_gradient" error when gradient is not covering the entire shape - - version 2.0.13_rev1 - - Added: - - (MGG-88) Support for operating with BGRA2222, ABGR2222, ARGB2222 type images - - (MGG-88) Support for operating with ABGR4444, ARGB4444 type images - - (MGG-88) Support for operating with ABGR8888, ARGB8888 type images - - (MGG-88) Support for operating with XBGR8888, XRGB8888 type images - - (MGG-52) Improved GPU bus error reporting by using weak functions - - Changed: - - (MGG-66) Restructured GPU driver by exposing the HAL source code for easier integration with operating systems - - Fixed: - - (MGG-72) Fixed rough edges of vector artefacts when using the "vg_lite_draw_pattern" API - - (MGG-58) Fixed "vg_lite_blit_rect" API not supporting a zero Y coordinate - - version 2.0.13_rev0 -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite.c deleted file mode 100644 index d35ef1b..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLite/vg_lite.c +++ /dev/null @@ -1,13271 +0,0 @@ -/**************************************************************************** -* -* The MIT License (MIT) -* -* Copyright 2012 - 2020 Vivante Corporation, Santa Clara, California. -* All Rights Reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining -* a copy of this software and associated documentation files (the -* 'Software'), to deal in the Software without restriction, including -* without limitation the rights to use, copy, modify, merge, publish, -* distribute, sub license, and/or sell copies of the Software, and to -* permit persons to whom the Software is furnished to do so, subject -* to the following conditions: -* -* The above copyright notice and this permission notice (including the -* next paragraph) shall be included in all copies or substantial -* portions of the Software. -* -* THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, -* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -* IN NO EVENT SHALL VIVANTE AND/OR ITS SUPPLIERS BE LIABLE FOR ANY -* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -* -* Copyright 2020-2022 MicroEJ Corp. This file has been modified by MicroEJ Corp. -* 1. Add a weak the function "vg_lite_draw_notify_render_area()" -* 2. Add "vg_lite_get_scissor()" -* -*****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include "vg_lite.h" -#include "vg_lite_kernel.h" -#if !defined(VG_DRIVER_SINGLE_THREAD) -#include "vg_lite_os.h" -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ -#if (VG_RENDER_TEXT==1) -#include "vg_lite_text.h" -#endif /* VG_RENDER_TEXT */ - -/* This is the function to call from the VGLite driver to interface with the GPU. */ -vg_lite_error_t vg_lite_kernel(vg_lite_kernel_command_t command, void * data); - - -/*** Command buffer dump ***/ -#ifndef DUMP_COMMAND -#define DUMP_COMMAND 0 -#endif - -#ifndef DUMP_IMAGE -#define DUMP_IMAGE 0 - -#else -#ifndef DUMP_COMMAND -#define DUMP_COMMAND 0 -#endif - -#ifndef DUMP_IMAGE -#define DUMP_IMAGE 0 -#endif -#endif - -#define VG_TARGET_FC_DUMP 0 - -/* Fast clear is not used by default,if SOC should use this ,set this macro to 1. */ -#ifndef VG_TARGET_FAST_CLEAR - #define VG_TARGET_FAST_CLEAR 0 -#endif /* VG_TARGET_FAST_CLEAR */ - -#if DUMP_COMMAND || DUMP_IMAGE -#ifdef __linux__ -#include -#endif -#endif - -#if defined(VG_DRIVER_SINGLE_THREAD) -/*** Global Context Access ***/ -#define GET_CONTEXT() &s_context -#endif /* VG_DRIVER_SINGLE_THREAD */ - -/*** Command buffer configurations, double buffer support ***/ -#define VG_LITE_COMMAND_BUFFER_SIZE (64 << 10) -#define CMDBUF_BUFFER(context) (context).command_buffer[(context).command_buffer_current] -#define CMDBUF_INDEX(context) (context).command_buffer_current -#define CMDBUF_SIZE(context) (context).command_buffer_size -#define CMDBUF_OFFSET(context) (context).command_offset[(context).command_buffer_current] -#define CMDBUF_SWAP(context) (context).command_buffer_current = \ - ((context).command_buffer_current + 1) % CMDBUF_COUNT - -#if !defined(VG_DRIVER_SINGLE_THREAD) -#ifndef CMDBUF_IN_QUEUE -#define CMDBUF_IN_QUEUE(context, id) \ - (vg_lite_os_event_state(&(context)->async_event[(id)]) == VG_LITE_IN_QUEUE) -#endif - -#define RESERVE_BYTES_IN_CMDBUF(context) \ - {\ - ((uint32_t *) (CMDBUF_BUFFER((context)) + CMDBUF_OFFSET((context))))[0] = VG_LITE_STATE(0x0a00);\ - ((uint32_t *) (CMDBUF_BUFFER((context)) + CMDBUF_OFFSET((context))))[1] = 0;\ - CMDBUF_OFFSET((context)) += 8;\ - } -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - -#define VG_LITE_RETURN_ERROR(func) \ -if ((error = func) != VG_LITE_SUCCESS) \ -return error - -#define VG_LITE_BREAK_ERROR(func) \ -if ((error = func) != VG_LITE_SUCCESS) \ -break - -#define VG_LITE_ERROR_HANDLER(func) \ -if ((error = func) != VG_LITE_SUCCESS) \ -goto ErrorHandler - -/*** Command macros ***/ - -#define VG_LITE_END(interrupt) (0x00000000 | interrupt) -#define VG_LITE_SEMAPHORE(id) (0x10000000 | id) -#define VG_LITE_STALL(id) (0x20000000 | id) -#define VG_LITE_STATE(address) (0x30010000 | address) -#define VG_LITE_STATES(count, address) (0x30000000 | ((count) << 16) | address) -#define VG_LITE_DATA(count) (0x40000000 | count) -#define VG_LITE_CALL(count) (0x60000000 | count) -#define VG_LITE_RETURN() (0x70000000) -#define VG_LITE_NOP() (0x80000000) - -/*** Shortcuts. ***/ -#define A(color) (color) >> 24 -#define R(color) ((color) & 0x00ff0000) >> 16 -#define G(color) ((color) & 0x0000ff00) >> 8 -#define B(color) ((color) & 0xff) -#define ARGB(a, r, g, b) ((a) << 24) | ((r) << 16) | ((g) << 8 ) | (b) -#define ARGB4(a, r, g, b) (((a) & 0xf0) << 8) | (((r) & 0xf0) << 4) | (((g) & 0xf0)) | ((b) >> 4) - -#define FC_BURST_BYTES 64 -#define FC_BIT_TO_BYTES 64 - -#define MIN(a, b) ((a) > (b) ? (b) : (a)) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) - -static uint32_t command_buffer_size = VG_LITE_COMMAND_BUFFER_SIZE; - -#define FORMAT_ALIGNMENT(stride,align) \ - { \ - if((stride) % (align) != 0) \ - return VG_LITE_INVALID_ARGUMENT; \ - return VG_LITE_SUCCESS; \ - } - -#define DEST_ALIGNMENT_LIMITATION 64 /* To match hardware alignment requirement */ -#if !defined(VG_DRIVER_SINGLE_THREAD) -#define TS_STATE_COUNT 20 /* Initial state count for tessellation buffer. */ -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - -#define MATRIX_ROWS 3 -#define GET_MATRIX_VALUES(Pointer) ((float *) (Pointer)) -#define MAT(Matrix, Row, Column) (GET_MATRIX_VALUES(Matrix)[Row * MATRIX_ROWS + Column]) - -#define COLOR_FROM_RAMP(ColorRamp) (((vg_lite_float_t *) ColorRamp) + 1) -#define CLAMP(x, min, max) (((x) < (min)) ? (min) : \ - ((x) > (max)) ? (max) : (x)) -#define LERP(v1, v2, w) ((v1) * (w) + (v2) * (1.0f - (w))) - -#define PI 3.141592653589793238462643383279502f -#define SINF(x) ((vg_lite_float_t) sin(x)) -#define COSF(x) ((vg_lite_float_t) cos(x)) -#define FABSF(x) ((vg_lite_float_t) fabs(x)) -#define SQRTF(x) ((vg_lite_float_t) sqrt(x)) -#define CLAMP(x, min, max) (((x) < (min)) ? (min) : \ - ((x) > (max)) ? (max) : (x)) -#define ACOSF(x) ((vg_lite_float_t) acos(x)) -#define FMODF(x, y) ((vg_lite_float_t) fmod((x), (y))) -#define CEILF(x) ((vg_lite_float_t) ceil(x)) -#define FALSE 0 -#define TURE 1 -#define SIZEOF(a) \ -( \ - (size_t) (sizeof(a)) \ -) - -typedef uintptr_t UINTPTR_T; - -#define PTR2SIZE(p) \ -( \ - (UINTPTR_T) (p) \ -) - -#define GETINCREMENT(pointer, datatype_size) \ - (datatype_size - (PTR2SIZE(pointer) & (datatype_size - 1))) - -#define SKIPTODATA(pointer, datatype_size, SIZE) \ - /* Determine the increment value. */ \ - increment = GETINCREMENT(pointer, datatype_size); \ - /* Skip to the data. */ \ - pointer += increment; \ - SIZE -= increment - -#define VGSL_GETVALUE(X) \ - X = get_value(data_pointer); \ - data_pointer += data_type_size; \ - size -= data_type_size - -#define VGSL_GETCOORDXY(X, Y) \ - VGSL_GETVALUE(X); \ - VGSL_GETVALUE(Y); \ - if (is_relative) { X += ox; Y += oy; } - -#define FLOAT_EPSILON 0.001f - -#define SWING_NO 0 -#define SWING_OUT 1 -#define SWING_IN 2 - -/* Point curve type for generated stroke path. */ -#define CURVE_LINE 0 -#define CURVE_QUAD_CONTROL 1 -#define CURVE_QUAD_ANCHOR 2 -#define CURVE_ARC_SCCW 3 -#define CURVE_ARC_SCCW_HALF 4 - -#define FLOAT_PI 3.141592654f -#define FLOAT_PI_TWO 6.283185307f -#define FLOAT_PI_THREE_QUARTER 2.356194490f -#define FLOAT_PI_HALF 1.570796327f -#define FLOAT_PI_QUARTER 0.7853981634f -#define FLOAT_PI_EIGHTH 0.3926990817f -/* cos(PI/8) */ -#define FLOAT_COS_PI_EIGHTH 0.9238795325f - -#define centerX tangentX -#define centerY tangentY - -#define FLOAT_DIFF_EPSILON 0.125f -#define FLOAT_SWING_CENTER_RANGE 0.125f -#define FLOAT_ANGLE_EPSILON 0.0045f -#define FLOAT_ANGLE_EPSILON_COS 0.99999f -#define FLOAT_MIN_ARC_ANGLE 0.044f -#define FLOAT_MIN_ARC_ANGLE_COS 0.999f -/* Float constants. */ -#define gcvMAX_POS_FLOAT ((vg_lite_float_t) 3.4028235e+038) -#define gcvMAX_NEG_FLOAT ((vg_lite_float_t) -3.4028235e+038) -#define FLOAT_MIN gcvMAX_NEG_FLOAT -#define FLOAT_MAX gcvMAX_POS_FLOAT - -#define FLOAT_FAT_LINE_WIDTH 2.5f - -/* Point flatten type for flattened line segments. */ -#define vgcFLATTEN_NO 0 -#define vgcFLATTEN_START 1 -#define vgcFLATTEN_MIDDLE 2 -#define vgcFLATTEN_END 3 - -/* Command size calculation shortcuts. */ -#define COMMANDSIZE(CoordinateCount, CoordinateType) \ - ((1+CoordinateCount) * SIZEOF(CoordinateType)) - -#define ABS(x) (((x) < 0) ? -(x) : (x)) -#define EPS 2.2204460492503131e-14 -#if !defined(VG_DRIVER_SINGLE_THREAD) -/* VG:24 + TS:28 + IM:345 + PE:9 + RS:16 +Debug:2 */ -#define STATES_COUNT 424 -/* STATES_COUNT size + return command size */ -#define CONTEXT_BUFFER_SIZE STATES_COUNT * 2 * 4 + 8 -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - -#define UPDATE_BOUNDING_BOX(bbx, point) \ - do { \ - if ((point).x < (bbx).x) { \ - (bbx).width += (bbx).x - (point).x; \ - (bbx).x = (point).x; \ - } \ - if ((point).y < (bbx).y) { \ - (bbx).height += (bbx).y - (point).y; \ - (bbx).y = (point).y; \ - } \ - if ((point).x > (bbx).x + (bbx).width) \ - (bbx).width = (point).x - (bbx).x; \ - if ((point).y > (bbx).y + (bbx).height) \ - (bbx).height = (point).y - (bbx).y; \ - } while(0) - -typedef vg_lite_float_t FLOATVECTOR4[4]; - -#if !defined(VG_DRIVER_SINGLE_THREAD) -typedef struct vg_lite_ftable { - uint32_t ftable[gcFEATURE_COUNT]; - uint32_t ftflag; -} vg_lite_ftable_t; - -typedef struct vg_lite_states { - uint32_t state; - uint8_t init; -}vg_lite_states_t; - -typedef struct vg_lite_hardware { - vg_lite_states_t hw_states[STATES_COUNT]; -} vg_lite_hardware_t; - -static vg_lite_hardware_t hw = {0}; -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - -typedef struct vg_lite_context { - vg_lite_kernel_context_t context; - vg_lite_capabilities_t capabilities; - uint8_t * command_buffer[CMDBUF_COUNT]; - uint32_t command_buffer_size; - uint32_t command_offset[CMDBUF_COUNT]; - uint32_t command_buffer_current; -#if !defined(VG_DRIVER_SINGLE_THREAD) - uint8_t * context_buffer[CMDBUF_COUNT]; - uint32_t context_buffer_size; - uint32_t context_buffer_offset[CMDBUF_COUNT]; -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - vg_lite_tsbuffer_info_t tsbuffer; - vg_lite_buffer_t * rtbuffer; /* DDRLess: this is used as composing buffer. */ - -#if VG_TARGET_FAST_CLEAR - vg_lite_buffer_t fcBuffer; /* Buffer used for fast clear cache. */ - uint32_t clearValue; -#endif - - uint32_t scissor_enabled; -#if defined(VG_DRIVER_SINGLE_THREAD) - uint32_t scissor_dirty; /* Indicates whether scissor states are changed or not. e.g., scissors[4] or scissor_enabled. */ -#endif /* VG_DRIVER_SINGLE_THREAD */ - int32_t scissor[4]; /* Scissor area: x, y, width, height. */ - -#if !defined(VG_DRIVER_SINGLE_THREAD) - uint32_t start_offset; - uint32_t end_offset; - uint32_t ts_init; /* Indicates whether tessellation buffer states are initialized or not. */ - uint32_t ts_record[TS_STATE_COUNT]; /* Tessellation buffer initial states record. */ - uint32_t ts_init_used; - uint32_t ts_init_use; - uint32_t ts_dirty; - -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - - uint32_t chip_id; - uint32_t chip_rev; - - uint32_t premultiply_enabled; - -#if defined(VG_DRIVER_SINGLE_THREAD) - uint32_t premultiply_dirty; - uint8_t init; -#else - uint32_t semaphore_id; - - uint32_t * colors[4]; /* index colors. */ - uint32_t clut_dirty[4]; /* clut dirty flag. */ - uint32_t index_format; /* check if use index. */ - uint32_t clut_used[4]; /* check if used index. */ - - vg_lite_ftable_t s_ftable; -#endif /* VG_DRIVER_SINGLE_THREAD */ -} vg_lite_context_t; - -#if !defined(VG_DRIVER_SINGLE_THREAD) -typedef struct vg_lite_tls{ - /* currently just contains struct vg_lite_context_t */ - vg_lite_context_t t_context; -}vg_lite_tls_t; -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - -typedef struct vg_lite_feature_database{ - uint32_t chip_id; - uint32_t chip_version; - uint32_t cid; - uint32_t vg_im_index_format:1; - uint32_t vg_pe_premultiply:1; - uint32_t vg_border_culling:1; - uint32_t vg_rgba2_format:1; - uint32_t vg_quality_8x:1; - uint32_t vg_radial_gradient:1; - uint32_t vg_linear_gradient_ext:1; - uint32_t vg_dither:1; - uint32_t vg_color_key:1; -} vg_lite_feature_database_t; - -static vg_lite_feature_database_t VGFeatureInfos[] = { - /* vg255 */ - { - GPU_CHIP_ID_GCNanoliteV, /* ChipID */ - 0x1311, /* ChipRevision */ - 0x404, /* CID */ - 0x0, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ - 0x0, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ - 0x1, /* gcFEATURE_BIT_VG_BORDER_CULLING */ - 0x1, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ - 0X0, /* gcFEATURE_BIT_VG_QUALITY_8X */ - 0X0, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ - 0x0, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ - 0x0, /* gcFEATURE_BIT_VG_DITHER */ - 0x0, /* gcFEATURE_BIT_VG_COLOR_KEY */ - }, - /* vg255 */ - { - GPU_CHIP_ID_GCNanoliteV, /* ChipID */ - 0x1311, /* ChipRevision */ - 0x40a, /* CID */ - 0x1, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ - 0x0, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ - 0x1, /* gcFEATURE_BIT_VG_BORDER_CULLING */ - 0x1, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ - 0X1, /* gcFEATURE_BIT_VG_QUALITY_8X */ - 0X0, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ - 0x0, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ - 0x0, /* gcFEATURE_BIT_VG_DITHER */ - 0x0, /* gcFEATURE_BIT_VG_COLOR_KEY */ - }, - /* vg255 */ - { - GPU_CHIP_ID_GCNanoliteV, /* ChipID */ - 0x1311, /* ChipRevision */ - 0x40b, /* CID */ - 0x1, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ - 0x0, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ - 0x1, /* gcFEATURE_BIT_VG_BORDER_CULLING */ - 0x1, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ - 0X1, /* gcFEATURE_BIT_VG_QUALITY_8X */ - 0X0, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ - 0x0, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ - 0x0, /* gcFEATURE_BIT_VG_DITHER */ - 0x0, /* gcFEATURE_BIT_VG_COLOR_KEY */ - }, - /* vg255 */ - { - GPU_CHIP_ID_GCNanoliteV, /* ChipID */ - 0x1311, /* ChipRevision */ - 0x40d, /* CID */ - 0x1, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ - 0x0, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ - 0x1, /* gcFEATURE_BIT_VG_BORDER_CULLING */ - 0x1, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ - 0X1, /* gcFEATURE_BIT_VG_QUALITY_8X */ - 0X0, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ - 0x0, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ - 0x0, /* gcFEATURE_BIT_VG_DITHER */ - 0x0, /* gcFEATURE_BIT_VG_COLOR_KEY */ - }, - /* vg255 */ - { - GPU_CHIP_ID_GCNanoliteV, /* ChipID */ - 0x1322, /* ChipRevision */ - 0x403, /* CID */ - 0x1, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ - 0x0, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ - 0x1, /* gcFEATURE_BIT_VG_BORDER_CULLING */ - 0x1, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ - 0X1, /* gcFEATURE_BIT_VG_QUALITY_8X */ - 0X0, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ - 0x0, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ - 0x0, /* gcFEATURE_BIT_VG_DITHER */ - 0x0, /* gcFEATURE_BIT_VG_COLOR_KEY */ - }, - /* vg355 */ - { - GPU_CHIP_ID_GC355, /* ChipID */ - 0x1217, /* ChipRevision */ - 0x408, /* CID */ - 0x0, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ - 0x1, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ - 0x0, /* gcFEATURE_BIT_VG_BORDER_CULLING */ - 0x0, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ - 0X0, /* gcFEATURE_BIT_VG_QUALITY_8X */ - 0X1, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ - 0x1, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ - 0x1, /* gcFEATURE_BIT_VG_DITHER */ - 0x1, /* gcFEATURE_BIT_VG_COLOR_KEY */ - }, - /* vg355 */ - { - GPU_CHIP_ID_GC355, /* ChipID */ - 0x1216, /* ChipRevision */ - 0x0, /* CID */ - 0x0, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ - 0x1, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ - 0x0, /* gcFEATURE_BIT_VG_BORDER_CULLING */ - 0x0, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ - 0X0, /* gcFEATURE_BIT_VG_QUALITY_8X */ - 0X1, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ - 0x1, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ - 0x1, /* gcFEATURE_BIT_VG_DITHER */ - 0x1, /* gcFEATURE_BIT_VG_COLOR_KEY */ - }, - /* vg355 */ - { - GPU_CHIP_ID_GC355, /* ChipID */ - 0x1215, /* ChipRevision */ - 0x0, /* CID */ - 0x0, /* gcFEATURE_BIT_VG_IM_INDEX_FORMAT */ - 0x1, /* gcFEATURE_BIT_VG_PE_PREMULTIPLY */ - 0x0, /* gcFEATURE_BIT_VG_BORDER_CULLING */ - 0x0, /* gcFEATURE_BIT_VG_RGBA2_FORMAT */ - 0X0, /* gcFEATURE_BIT_VG_QUALITY_8X */ - 0X1, /* gcFEATURE_BIT_VG_RADIAL_GRADIENT */ - 0x1, /* gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT */ - 0x1, /* gcFEATURE_BIT_VG_DITHER */ - 0x1, /* gcFEATURE_BIT_VG_COLOR_KEY */ - } -}; - -#if defined(VG_DRIVER_SINGLE_THREAD) -typedef struct vg_lite_ftable { - uint32_t ftable[gcFEATURE_COUNT]; - uint32_t ftflag; -} vg_lite_ftable_t; - -vg_lite_context_t s_context = {0}; -vg_lite_ftable_t s_ftable = {{0}, 0}; -#endif /* VG_DRIVER_SINGLE_THREAD */ - -#if DUMP_COMMAND -FILE * fp; -char filename[30]; -#endif - -int submit_flag = 0; - -static vg_lite_float_t _GetS8_NS_NB(int8_t * Data) -{ - int8_t x0 = *((int8_t *) Data); - vg_lite_float_t x = (vg_lite_float_t) x0; - - return x; -} - -static vg_lite_float_t _GetS16_NS_NB(int8_t * Data) -{ - int16_t x0 = *((int16_t *) Data); - vg_lite_float_t x = (vg_lite_float_t) x0; - - return x; -} - -static vg_lite_float_t _GetS32_NS_NB(int8_t * Data) -{ - int32_t x0 = *((int32_t *) Data); - vg_lite_float_t x = (vg_lite_float_t) x0; - - return x; -} - -static vg_lite_float_t _GetF_NS_NB(int8_t * Data) -{ - vg_lite_float_t x = *((vg_lite_float_t *) Data); - - return x; -} - -typedef vg_lite_float_t (* vg_value_getter) (int8_t * Data); - -typedef struct vg_lite_control_coord -{ - vg_lite_float_t startX; - vg_lite_float_t startY; - vg_lite_float_t lastX; - vg_lite_float_t lastY; - vg_lite_float_t controlX; - vg_lite_float_t controlY; -} -vg_lite_control_coord_t; - -static uint32_t _commandSize_float[] = -{ - COMMANDSIZE(0, vg_lite_float_t), /* 0: END */ - COMMANDSIZE(0, vg_lite_float_t), /* 1: CLOSE */ - COMMANDSIZE(2, vg_lite_float_t), /* 2: MOVE */ - COMMANDSIZE(2, vg_lite_float_t), /* 3: MOVE_REL */ - COMMANDSIZE(2, vg_lite_float_t), /* 4: LINE */ - COMMANDSIZE(2, vg_lite_float_t), /* 5: LINE_REL */ - COMMANDSIZE(4, vg_lite_float_t), /* 6: QUAD */ - COMMANDSIZE(4, vg_lite_float_t), /* 7: QUAD_REL */ - COMMANDSIZE(6, vg_lite_float_t), /* 8: CUBIC */ - COMMANDSIZE(6, vg_lite_float_t), /* 9: CUBIC_REL */ - COMMANDSIZE(5, vg_lite_float_t), /* 10: SCCWARC */ - COMMANDSIZE(5, vg_lite_float_t), /* 11: SCCWARC_REL */ - COMMANDSIZE(5, vg_lite_float_t), /* 12: SCWARC */ - COMMANDSIZE(5, vg_lite_float_t), /* 13: SCWARC_REL */ - COMMANDSIZE(5, vg_lite_float_t), /* 14: LCCWARC */ - COMMANDSIZE(5, vg_lite_float_t), /* 15: LCCWARC_REL */ - COMMANDSIZE(5, vg_lite_float_t), /* 16: LCWARC */ - COMMANDSIZE(5, vg_lite_float_t), /* 17: LCWARC_REL */ -}; - -/* Special sqrt(1.0f + x) for quick calculation when 0 <= x <= 1. */ -static vg_lite_float_t _Sqrt( - vg_lite_float_t X - ) -{ - vg_lite_float_t x = X; - vg_lite_float_t s = 1.0f; - - s += x * 0.5f; - x *= X; - s -= x * 0.12445995211601257f; - x *= X; - s += x * 0.058032196015119553f; - x *= X; - s -= x * 0.025314478203654289f; - x *= X; - s += x * 0.0059584137052297592f; - - return s; -} - -static vg_lite_error_t _set_point_tangent( - vg_lite_path_point_ptr Point, - vg_lite_float_t Dx, - vg_lite_float_t Dy - ) -{ - if(!Point) - return VG_LITE_INVALID_ARGUMENT; - - if (Dx == 0.0f) - { - if (Dy == 0.0f) - { - if (Point->prev) - { - Point->length = 0.0f; - Point->tangentX = Point->prev->tangentX; - Point->tangentY = Point->prev->tangentY; - } - else - { - Point->length = 0.0f; - Point->tangentX = 0.0f; - Point->tangentY = 0.0f; - } - } - else - { - Point->tangentX = 0.0f; - if (Dy > 0.0f) - { - Point->length = Dy; - Point->tangentY = 1.0f; - } - else - { - Point->length = -Dy; - Point->tangentY = -1.0f; - } - } - } - else if (Dy == 0.0f) - { - Point->tangentY = 0.0f; - if (Dx > 0.0f) - { - Point->length = Dx; - Point->tangentX = 1.0f; - } - else - { - Point->length = -Dx; - Point->tangentX = -1.0f; - } - } - else - { - vg_lite_float_t l, tx, ty; - - vg_lite_float_t dx, dy; - vg_lite_float_t t, t2; - - dx = (Dx >= 0.0f ? Dx : -Dx); - dy = (Dy >= 0.0f ? Dy : -Dy); - if (dx >= dy) - { - t = dy / dx; - t2 = t * t; - l = _Sqrt(t2); - Point->length = l * dx; - - tx = 1.0f / l; - ty = tx * t; - } - else - { - t = dx / dy; - t2 = t * t; - l = _Sqrt(t2); - Point->length = l * dy; - - ty = 1.0f / l; - tx = ty * t; - } - if (Dx < 0.0f) tx = -tx; - if (Dy < 0.0f) ty = -ty; - - tx = CLAMP(tx, -1.0f, 1.0f); - ty = CLAMP(ty, -1.0f, 1.0f); - Point->tangentX = tx; - Point->tangentY = ty; - } - return VG_LITE_SUCCESS; -} - -static vg_lite_error_t _add_point_to_point_list_wdelta( - vg_lite_stroke_conversion_t * stroke_conversion, - vg_lite_float_t X, - vg_lite_float_t Y, - vg_lite_float_t DX, - vg_lite_float_t DY, - uint8_t flatten_flag - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_path_point_ptr last_point; - vg_lite_path_point_ptr point; - - if(!stroke_conversion) - return VG_LITE_INVALID_ARGUMENT; - - last_point = stroke_conversion->path_last_point; - point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); - - if(!point) - return VG_LITE_OUT_OF_RESOURCES; - - memset(point, 0, sizeof(*point)); - - point->x = X; - point->y = Y; - point->flatten_flag = flatten_flag; - - /* Calculate tangent for last_point. */ - VG_LITE_ERROR_HANDLER(_set_point_tangent(last_point, DX, DY)); - - last_point->next = point; - stroke_conversion->path_last_point = point; - point->prev = last_point; - stroke_conversion->point_count++; - - return error; -ErrorHandler: - - vg_lite_os_free(point); - point = NULL; - return error; -} - -static vg_lite_error_t _add_point_to_point_list( - vg_lite_stroke_conversion_t * stroke_conversion, - vg_lite_float_t X, - vg_lite_float_t Y, - uint8_t flatten_flag - ) -{ - vg_lite_error_t status = VG_LITE_SUCCESS; - vg_lite_path_point_ptr last_point; - vg_lite_path_point_ptr point; - - if(!stroke_conversion) - return VG_LITE_INVALID_ARGUMENT; - - last_point = stroke_conversion->path_last_point; - if (last_point == NULL) - { - point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); - if(!point) - return VG_LITE_OUT_OF_RESOURCES; - memset(point, 0, sizeof(*point)); - - point->x = X; - point->y = Y; - point->flatten_flag = flatten_flag; - point->prev = NULL; - stroke_conversion->path_last_point = stroke_conversion->path_point_list = point; - stroke_conversion->point_count++; - status = VG_LITE_SUCCESS; - } - else - { - vg_lite_float_t dX = X - last_point->x; - vg_lite_float_t dY = Y - last_point->y; - vg_lite_float_t deltaX = (dX >= 0.0f ? dX : -dX); - vg_lite_float_t deltaY = (dY >= 0.0f ? dY : -dY); - - /* Check for degenerated line. */ - if (deltaX == 0.0f && deltaY == 0.0f) - { - /* Skip degenerated line. */ - status = VG_LITE_SUCCESS; - goto ErrorHandler; - } - if (deltaX < FLOAT_EPSILON && deltaY < FLOAT_EPSILON) - { - vg_lite_float_t ratioX, ratioY; - - if (deltaX == 0.0f) - { - ratioX = 0.0f; - } - else if (X == 0.0f) - { - ratioX = deltaX; - } - else - { - ratioX = deltaX / X; - if (ratioX < 0.0f) ratioX = -ratioX; - } - if (deltaY == 0.0f) - { - ratioY = 0.0f; - } - else if (Y == 0.0f) - { - ratioY = deltaY; - } - else - { - ratioY = deltaY / Y; - if (ratioY < 0.0f) ratioY = -ratioY; - } - if (ratioX < 1.0e-6f && ratioY < 1.0e-6f) - { - /* Skip degenerated line. */ - status = VG_LITE_SUCCESS; - goto ErrorHandler; - } - } - - status = _add_point_to_point_list_wdelta(stroke_conversion, X, Y, dX, dY, flatten_flag); - } - -ErrorHandler: - return status; -} - -static vg_lite_error_t -_flatten_quad_bezier( - vg_lite_stroke_conversion_t * stroke_conversion, - vg_lite_float_t X0, - vg_lite_float_t Y0, - vg_lite_float_t X1, - vg_lite_float_t Y1, - vg_lite_float_t X2, - vg_lite_float_t Y2 - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t n; - vg_lite_path_point_ptr point0, point1; - vg_lite_float_t x, y; - vg_lite_float_t a1x, a1y, a2x, a2y; - vg_lite_float_t f1, f2, t1, t2, upper_bound; - - if(!stroke_conversion) - return VG_LITE_INVALID_ARGUMENT; - - /* Formula. - * f(t) = (1 - t)^2 * p0 + 2 * t * (1 - t) * p1 + t^2 * p2 - * = a0 + a1 * t + a2 * t^2 - * a0 = p0 - * a1 = 2 * (-p0 + p1) - * a2 = p0 - 2 * p1 + p2 - */ - x = X1 - X0; - a1x = x + x; - y = Y1 - Y0; - a1y = y + y; - a2x = X0 - X1 - X1 + X2; - a2y = Y0 - Y1 - Y1 + Y2; - - /* Step 1: Calculate N. */ - /* Lefan's method. */ - /* dist(t) = ... - * t2 = ... - * if 0 <= t2 <= 1 - * upper_bound = dist(t2) - * else - * upper_bound = max(dist(0), dist(1)) - * N = ceil(sqrt(upper_bound / epsilon / 8)) - */ - /* Prepare dist(t). */ - f1 = a1x * a2y - a2x * a1y; - if (f1 != 0.0f) - { - if (f1 < 0.0f) f1 = -f1; - - /* Calculate t2. */ - t1 = a2x * a2x + a2y * a2y; - t2 = -(x * a2x + y * a2y) / t1; - /* Calculate upper_bound. */ - if (t2 >= 0.0f && t2 <= 1.0f) - { - f2 = x + a2x * t2; - f2 *= f2; - t1 = y + a2y * t2; - t1 *= t1; - upper_bound = t1 + f2; - } - else - { - f2 = x + a2x; - f2 *= f2; - t1 = y + a2y; - t1 *= t1; - t2 = t1 + f2; - t1 = x * x + y * y; - upper_bound = t1 < t2 ? t1 : t2; - } - /* Calculate n. */ - upper_bound = f1 / SQRTF(upper_bound); - upper_bound = SQRTF(upper_bound); - if (stroke_conversion->is_fat) - { - upper_bound *= stroke_conversion->stroke_line_width; - } - n = (uint32_t) ceil(upper_bound); - } - else - { - /* n = 0 => n = 256. */ - n = 256; - } - - if (n == 0 || n > 256) - { - n = 256; - } - - /* Add extra P0 for incoming tangent. */ - point0 = stroke_conversion->path_last_point; - /* First add P1 to calculate incoming tangent, which is saved in P0. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X1, Y1, vgcFLATTEN_START)); - - point1 = stroke_conversion->path_last_point; - /* Change the point1's coordinates back to P0. */ - point1->x = X0; - point1->y = Y0; - point0->length = 0.0f; - - if (n > 1) - { - vg_lite_float_t d, dsquare, dx, dy, ddx, ddy; - vg_lite_float_t ratioX, ratioY; - uint32_t i; - - /* Step 2: Calculate deltas. */ - /* Df(t) = f(t + d) - f(t) - * = a1 * d + a2 * d^2 + 2 * a2 * d * t - * DDf(t) = Df(t + d) - Df(t) - * = 2 * a2 * d^2 - * f(0) = a0 - * Df(0) = a1 * d + a2 * d^2 - * DDf(0) = 2 * a2 * d^2 - */ - d = 1.0f / (vg_lite_float_t) n; - dsquare = d * d; - ddx = a2x * dsquare; - ddy = a2y * dsquare; - dx = a1x * d + ddx; - dy = a1y * d + ddy; - ddx += ddx; - ddy += ddy; - - /* Step 3: Add points. */ - ratioX = dx / X0; - if (ratioX < 0.0f) ratioX = -ratioX; - ratioY = dy / Y0; - if (ratioY < 0.0f) ratioY = -ratioY; - if (ratioX > 1.0e-6f && ratioY > 1.0e-6f) - { - x = X0; - y = Y0; - for (i = 1; i < n; i++) - { - x += dx; - y += dy; - - /* Add a point to subpath. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list_wdelta(stroke_conversion, x, y, dx, dy, vgcFLATTEN_MIDDLE)); - - dx += ddx; - dy += ddy; - } - - } - else - { - for (i = 1; i < n; i++) - { - vg_lite_float_t t = (vg_lite_float_t) i / (vg_lite_float_t) n; - vg_lite_float_t u = 1.0f - t; - vg_lite_float_t a0 = u * u; - vg_lite_float_t a1 = 2.0f * t * u; - vg_lite_float_t a2 = t * t; - - x = a0 * X0 + a1 * X1 + a2 * X2; - y = a0 * Y0 + a1 * Y1 + a2 * Y2; - - /* Add a point to subpath. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, x, y, vgcFLATTEN_MIDDLE)); - } - } - } - - - /* Add point 2 separately to avoid cumulative errors. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X2, Y2, vgcFLATTEN_END)); - - /* Add extra P2 for outgoing tangent. */ - /* First change P2(point0)'s coordinates to P1. */ - point0 = stroke_conversion->path_last_point; - point0->x = X1; - point0->y = Y1; - - /* Add P2 to calculate outgoing tangent. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X2, Y2, vgcFLATTEN_NO)); - - point1 = stroke_conversion->path_last_point; - - /* Change point0's coordinates back to P2. */ - point0->x = X2; - point0->y = Y2; - point0->length = 0.0f; - -ErrorHandler: - return error; -} - -static vg_lite_error_t -_flatten_cubic_bezier( - vg_lite_stroke_conversion_t * stroke_conversion, - vg_lite_float_t X0, - vg_lite_float_t Y0, - vg_lite_float_t X1, - vg_lite_float_t Y1, - vg_lite_float_t X2, - vg_lite_float_t Y2, - vg_lite_float_t X3, - vg_lite_float_t Y3 - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t n; - vg_lite_path_point_ptr point0, point1; - vg_lite_float_t x, y; - vg_lite_float_t a1x, a1y, a2x, a2y, a3x, a3y; - vg_lite_float_t ddf0, ddf1, t1, t2, upper_bound; - - if(!stroke_conversion) - return VG_LITE_INVALID_ARGUMENT; - - /* Formula. - * f(t) = (1 - t)^3 * p0 + 3 * t * (1 - t)^2 * p1 + 3 * t^2 * (1 - t) * p2 + t^3 * p3 - * = a0 + a1 * t + a2 * t^2 + a3 * t^3 - */ - x = X1 - X0; - a1x = x + x + x; - y = Y1 - Y0; - a1y = y + y + y; - x = X0 - X1 - X1 + X2; - a2x = x + x + x; - y = Y0 - Y1 - Y1 + Y2; - a2y = y + y + y; - x = X1 - X2; - a3x = x + x + x + X3 - X0; - y = Y1 - Y2; - a3y = y + y + y + Y3 - Y0; - - /* Step 1: Calculate N. */ - /* Lefan's method. */ - /* df(t)/dt = a1 + 2 * a2 * t + 3 * a3 * t^2 - * d2f(t)/dt2 = 2 * a2 + 6 * a3 * t - * N = ceil(sqrt(max(ddfx(0)^2 + ddfy(0)^2, ddfx(1)^2 + ddyf(1)^2) / epsilon / 8)) - */ - - ddf0 = a2x * a2x + a2y * a2y; - t1 = a2x + a3x + a3x + a3x; - t2 = a2y + a3y + a3y + a3y; - ddf1 = t1 * t1 + t2 * t2; - upper_bound = ddf0 > ddf1 ? ddf0: ddf1; - upper_bound = SQRTF(upper_bound); - upper_bound += upper_bound; - upper_bound = SQRTF(upper_bound); - if (stroke_conversion->is_fat) - { - upper_bound *= stroke_conversion->stroke_line_width; - } - n = (uint32_t) ceil(upper_bound); - - if (n == 0 || n > 256) - { - n = 256; - } - - /* Add extra P0 for incoming tangent. */ - point0 = stroke_conversion->path_last_point; - /* First add P1/P2/P3 to calculate incoming tangent, which is saved in P0. */ - if (X0 != X1 || Y0 != Y1) - { - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X1, Y1, vgcFLATTEN_START)); - } - else if (X0 != X2 || Y0 != Y2) - { - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X2, Y2, vgcFLATTEN_START)); - } - else - { - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X3, Y3, vgcFLATTEN_START)); - } - point1 = stroke_conversion->path_last_point; - /* Change the point1's coordinates back to P0. */ - point1->x = X0; - point1->y = Y0; - point0->length = 0.0f; - - if (n > 1) - { - vg_lite_float_t d, dsquare, dcube, dx, dy, ddx, ddy, dddx, dddy; - vg_lite_float_t ratioX, ratioY; - uint32_t i; - - /* Step 2: Calculate deltas */ - /* Df(t) = f(t + d) - f(t) - * DDf(t) = Df(t + d) - Df(t) - * DDDf(t) = DDf(t + d) - DDf(t) - * f(0) = a0 - * Df(0) = a1 * d + a2 * d^2 + a3 * d^3 - * DDf(0) = 2 * a2 * d^2 + 6 * a3 * d^3 - * DDDf(0) = 6 * a3 * d^3 - */ - d = 1.0f / (vg_lite_float_t) n; - dsquare = d * d; - dcube = dsquare * d; - ddx = a2x * dsquare; - ddy = a2y * dsquare; - dddx = a3x * dcube; - dddy = a3y * dcube; - dx = a1x * d + ddx + dddx; - dy = a1y * d + ddy + dddy; - ddx += ddx; - ddy += ddy; - dddx *= 6.0f; - dddy *= 6.0f; - ddx += dddx; - ddy += dddy; - - /* Step 3: Add points. */ - ratioX = dx / X0; - if (ratioX < 0.0f) ratioX = -ratioX; - ratioY = dy / Y0; - if (ratioY < 0.0f) ratioY = -ratioY; - if (ratioX > 1.0e-6f && ratioY > 1.0e-6f) - { - x = X0; - y = Y0; - for (i = 1; i < n; i++) - { - x += dx; - y += dy; - - /* Add a point to subpath. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list_wdelta(stroke_conversion, x, y, dx, dy, vgcFLATTEN_MIDDLE)); - dx += ddx; ddx += dddx; - dy += ddy; ddy += dddy; - } - } - else - { - for (i = 1; i < n; i++) - { - vg_lite_float_t t = (vg_lite_float_t) i / (vg_lite_float_t) n; - vg_lite_float_t tSquare = t * t; - vg_lite_float_t tCube = tSquare * t; - vg_lite_float_t a0 = 1.0f - 3.0f * t + 3.0f * tSquare - tCube; - vg_lite_float_t a1 = 3.0f * t - 6.0f * tSquare + 3.0f * tCube; - vg_lite_float_t a2 = 3.0f * tSquare - 3.0f * tCube; - vg_lite_float_t a3 = tCube; - - x = a0 * X0 + a1 * X1 + a2 * X2 + a3 * X3; - y = a0 * Y0 + a1 * Y1 + a2 * Y2 + a3 * Y3; - - /* Add a point to subpath. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, x, y, vgcFLATTEN_MIDDLE)); - } - } - } - - /* Add point 3 separately to avoid cumulative errors. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X3, Y3, vgcFLATTEN_END)); - - /* Add extra P3 for outgoing tangent. */ - /* First change P3(point0)'s coordinates to P0/P1/P2. */ - point0 = stroke_conversion->path_last_point; - if (X3 != X2 || Y3 != Y2) - { - point0->x = X2; - point0->y = Y2; - } - else if (X3 != X1 || Y3 != Y1) - { - point0->x = X1; - point0->y = Y1; - } - else - { - point0->x = X0; - point0->y = Y0; - } - - /* Add P3 to calculate outgoing tangent. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, X3, Y3, vgcFLATTEN_NO)); - - point1 = stroke_conversion->path_last_point; - - /* Change point0's coordinates back to P3. */ - point0->x = X3; - point0->y = Y3; - point0->length = 0.0f; - -ErrorHandler: - return error; -} - -static vg_lite_error_t _flatten_path( - vg_lite_stroke_conversion_t * stroke_conversion, - vg_lite_path_t *path - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t increment; - uint8_t is_relative; - uint32_t size; - uint32_t path_command; - uint32_t prev_command; - uint8_t data_type_size; - int8_t* data_pointer = NULL; - vg_lite_float_t sx, sy; - vg_lite_float_t ox, oy; - vg_lite_float_t x0, y0, x1, y1, x2, y2; - vg_value_getter get_value = NULL; - - if(!stroke_conversion || !path) - return VG_LITE_INVALID_ARGUMENT; - - sx = sy = ox = oy = 0.0f; - - prev_command = VLC_OP_MOVE; - - /* Determine the data size. */ - size = path->path_length; - - /* Determine the beginning of the path data. */ - data_pointer = (int8_t*)path->path; - - /* Select the data picker. */ - switch (path->format) - { - case VG_LITE_S8: - data_type_size = 1; - get_value = _GetS8_NS_NB; - break; - - case VG_LITE_S16: - data_type_size = 2; - get_value = _GetS16_NS_NB; - break; - - case VG_LITE_S32: - data_type_size = 4; - get_value = _GetS32_NS_NB; - break; - - case VG_LITE_FP32: - data_type_size = 4; - get_value = _GetF_NS_NB; - break; - - default: - error = VG_LITE_INVALID_ARGUMENT; - goto ErrorHandler; - } - /* Add an extra gcvVGCMD_MOVE 0.0 0.0 to handle the case the first command is not gcvVGCMD_MOVE. */ - if (*data_pointer != VLC_OP_MOVE) - { - /* Add first point to subpath. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, sx, sy, vgcFLATTEN_NO)); - } - - while (size > 0) - { - /* Get the command. */ - path_command = *data_pointer & 0x1F; - - /* Assume absolute. */ - is_relative = FALSE; - - switch (path_command) - { - case VLC_OP_END: - /* Skip the command. */ - size -= 1; - - if (prev_command == VLC_OP_END) - { - /* Continuous gcvVGCMD_CLOSE - do nothing. */ - break; - } - - /* Check if subPath is already closed. */ - if (ox != sx || oy != sy) - { - /* Add a line from current point to the first point of current subpath. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, sx, sy,vgcFLATTEN_NO)); - } - if (stroke_conversion->path_point_list != stroke_conversion->path_last_point) - { - /* Copy tangent data from first point to last_point. */ - vg_lite_path_point_ptr first_point = stroke_conversion->path_point_list; - vg_lite_path_point_ptr last_point = stroke_conversion->path_last_point; - last_point->length = first_point->length; - last_point->tangentX = first_point->tangentX; - last_point->tangentY = first_point->tangentY; - } - else - { - /* Single point path. */ - vg_lite_path_point_ptr point = stroke_conversion->path_point_list; - point->tangentX = 0.0f; - point->tangentY = 0.0f; - point->length = 0.0f; - } - stroke_conversion->closed = 1; - stroke_conversion->path_last_point->next = NULL; - break; - - case VLC_OP_MOVE_REL: - is_relative = 1; - - case VLC_OP_MOVE: /* Indicate the beginning of a new sub-path. */ - /* Skip to the data. */ - SKIPTODATA(data_pointer, data_type_size, size); - VGSL_GETCOORDXY(x0, y0); - - /* First command is gcvVGCMD_MOVE. */ - /* Add first point to subpath. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, x0, y0, vgcFLATTEN_NO)); - - sx = ox = x0; - sy = oy = y0; - break; - - case VLC_OP_LINE_REL: - is_relative = 1; - - case VLC_OP_LINE: - /* Skip to the data. */ - SKIPTODATA(data_pointer, data_type_size, size); - VGSL_GETCOORDXY(x0, y0); - - /* Add a point to subpath. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list(stroke_conversion, x0, y0, vgcFLATTEN_NO)); - - ox = x0; - oy = y0; - break; - - case VLC_OP_QUAD_REL: - is_relative = 1; - - case VLC_OP_QUAD: - /* Skip to the data. */ - SKIPTODATA(data_pointer, data_type_size, size); - VGSL_GETCOORDXY(x0, y0); - VGSL_GETCOORDXY(x1, y1); - - if ((ox == x0 && oy == y0) && (ox == x1 && oy == y1)) - { - /* Degenerated Bezier curve. Becomes a point. */ - /* Discard zero-length segments. */ - } - else if ((ox == x0 && oy == y0) || (x0 == x1 && y0 == y1)) - { - /* Degenerated Bezier curve. Becomes a line. */ - /* Add a point to subpath. */ - VG_LITE_ERROR_HANDLER(_add_point_to_point_list( stroke_conversion, x1, y1, vgcFLATTEN_NO)); - } - else - { - VG_LITE_ERROR_HANDLER(_flatten_quad_bezier(stroke_conversion, ox, oy, x0, y0, x1, y1)); - } - - ox = x1; - oy = y1; - break; - - case VLC_OP_CUBIC_REL: - is_relative = 1; - - case VLC_OP_CUBIC: - /* Skip to the data. */ - SKIPTODATA(data_pointer, data_type_size, size); - VGSL_GETCOORDXY(x0, y0); - VGSL_GETCOORDXY(x1, y1); - VGSL_GETCOORDXY(x2, y2); - - if ((ox == x0 && oy == y0) && (ox == x1 && oy == y1) && (ox == x2 && oy == y2)) - { - /* Degenerated Bezier curve. Becomes a point. */ - /* Discard zero-length segments. */ - } - else - { - VG_LITE_ERROR_HANDLER(_flatten_cubic_bezier(stroke_conversion, ox, oy, x0, y0, x1, y1, x2, y2)); - } - - ox = x2; - oy = y2; - break; - - default: - error = VG_LITE_INVALID_ARGUMENT; - goto ErrorHandler; - } - prev_command = path_command; - } - - if ((prev_command != VLC_OP_END)) - { - stroke_conversion->path_last_point->next = NULL; - if (stroke_conversion->point_count == 1) - { - /* Single point path. */ - vg_lite_path_point_ptr point = stroke_conversion->path_point_list; - point->tangentX = 0.0f; - point->tangentY = 0.0f; - point->length = 0.0f; - } - } - -ErrorHandler: - return error; -} - -static vg_lite_error_t -_add_point_to_right_stroke_point_list_tail( - vg_lite_stroke_conversion_t * stroke_conversion, - vg_lite_float_t X, - vg_lite_float_t Y - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_path_point_ptr point; - - if(!stroke_conversion) - return VG_LITE_INVALID_ARGUMENT; - - point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); - if(!point) - return VG_LITE_OUT_OF_RESOURCES; - - memset(point, 0, sizeof(*point)); - - point->x = X; - point->y = Y; - point->curve_type = CURVE_LINE; - point->prev = stroke_conversion->last_right_stroke_point; - point->next = NULL; - stroke_conversion->last_right_stroke_point->next = point; - stroke_conversion->last_right_stroke_point = point; - stroke_conversion->stroke_point_count++; - - stroke_conversion->last_stroke_sub_path->point_count++; - - return error; -} - -static vg_lite_error_t -_add_point_to_left_stroke_point_list_head( - vg_lite_stroke_conversion_t * stroke_conversion, - vg_lite_float_t X, - vg_lite_float_t Y - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_path_point_ptr point; - - if(!stroke_conversion) - return VG_LITE_INVALID_ARGUMENT; - - point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); - - if(!point) - return VG_LITE_OUT_OF_RESOURCES; - - memset(point, 0, sizeof(*point)); - - point->x = X; - point->y = Y; - point->curve_type = CURVE_LINE; - point->next = stroke_conversion->left_stroke_point; - point->prev = NULL; - stroke_conversion->left_stroke_point->prev = point; - stroke_conversion->left_stroke_point = point; - stroke_conversion->stroke_point_count++; - - stroke_conversion->last_stroke_sub_path->point_count++; - - return error; -} - -static vg_lite_error_t _add_stroke_sub_path( - vg_lite_stroke_conversion_t * stroke_conversion, - vg_lite_sub_path_ptr *sub_path - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - - if(!stroke_conversion || !sub_path) - return VG_LITE_INVALID_ARGUMENT; - - *sub_path = (vg_lite_sub_path_ptr)vg_lite_os_malloc(sizeof(**sub_path)); - - if(!*sub_path) - return VG_LITE_OUT_OF_RESOURCES; - - memset(*sub_path, 0, sizeof(**sub_path)); - - if (stroke_conversion->last_stroke_sub_path != NULL) - { - stroke_conversion->last_stroke_sub_path->next = *sub_path; - stroke_conversion->last_stroke_sub_path = *sub_path; - } - else - { - stroke_conversion->last_stroke_sub_path = stroke_conversion->stroke_sub_path_list = *sub_path; - } - - return error; -} - -static vg_lite_error_t -_add_zero_length_stroke_sub_path( - vg_lite_stroke_conversion_t * stroke_conversion, - vg_lite_sub_path_ptr *stroke_subpath - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_path_point_ptr new_point,Point; - vg_lite_sub_path_ptr stroke_sub_path; - vg_lite_float_t half_width; - - if(!stroke_conversion) - return VG_LITE_INVALID_ARGUMENT; - - half_width = stroke_conversion->half_line_width; - Point = stroke_conversion->path_point_list; - if (stroke_conversion->stroke_cap_style == VG_LITE_CAP_BUTT) - { - /* No need to draw zero-length subPath for gcvCAP_BUTT. */ - error = VG_LITE_SUCCESS; - goto ErrorHandler; - } - - VG_LITE_ERROR_HANDLER(_add_stroke_sub_path(stroke_conversion, &stroke_sub_path)); - - if (stroke_conversion->stroke_cap_style == VG_LITE_CAP_SQUARE) - { - /* Draw a square along the point's direction. */ - vg_lite_float_t dx, dy; - - if (Point->tangentX == 0.0f || Point->tangentY == 0.0f) - { - dx = half_width; - dy = 0.0f; - } - else - { - dx = Point->tangentY * half_width; - dy = -Point->tangentX * half_width; - } - - new_point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*new_point)); - - if(!new_point) - return VG_LITE_OUT_OF_RESOURCES; - memset(new_point, 0, sizeof(*new_point)); - - new_point->x = Point->x + dx + dy; - new_point->y = Point->y - dx + dy; - new_point->curve_type = CURVE_LINE; - stroke_sub_path->point_list = stroke_conversion->last_right_stroke_point = new_point; - stroke_sub_path->point_count = 1; - - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, - Point->x + dx - dy, Point->y + dx + dy)); - - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, - Point->x - dx - dy, Point->y + dx - dy)); - - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, - Point->x - dx + dy, Point->y - dx - dy)); - } - else - { - /* Draw a circle. */ - new_point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*new_point)); - - if(!new_point) - return VG_LITE_OUT_OF_RESOURCES; - memset(new_point, 0, sizeof(*new_point)); - - new_point->x = Point->x + half_width; - new_point->y = Point->y; - new_point->curve_type = CURVE_LINE; - stroke_sub_path->point_list = stroke_conversion->last_right_stroke_point = new_point; - stroke_sub_path->point_count = 1; - - /* Add upper half circle. */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, - Point->x - half_width, Point->y)); - - stroke_conversion->last_right_stroke_point->curve_type = CURVE_ARC_SCCW_HALF; - stroke_conversion->last_right_stroke_point->centerX = Point->x; - stroke_conversion->last_right_stroke_point->centerY = Point->y; - - /* Add lower half circle. */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, - Point->x + half_width, Point->y)); - - stroke_conversion->last_right_stroke_point->curve_type = CURVE_ARC_SCCW_HALF; - stroke_conversion->last_right_stroke_point->centerX = Point->x; - stroke_conversion->last_right_stroke_point->centerY = Point->y; - } - - stroke_sub_path->last_point = stroke_conversion->last_right_stroke_point; - stroke_sub_path->last_point->next = NULL; - -ErrorHandler: - return error; -} - -/* Special asin(x) for quick calculation when -sqrt(0.5) <= x <= sqrt(0.5). */ -static vg_lite_float_t _Asin( - vg_lite_float_t X - ) -{ - vg_lite_float_t x = X; - vg_lite_float_t x2 = X * X; - vg_lite_float_t s = X; - - x *= x2; - s += x * 0.1660510562575219f; - x *= x2; - s += x * 0.084044676143618186f; - x *= x2; - s += x * 0.0023776176698039313f; - x *= x2; - s += x * 0.10211922020091345f; - - return s; -} -/* Special cos(x) for quick calculation when -PI <= x <= PI. */ -static vg_lite_float_t _Cos( - vg_lite_float_t X - ) -{ - vg_lite_float_t x2 = X * X; - vg_lite_float_t x = x2; - vg_lite_float_t s = 1.0f; - - s -= x * 0.49985163079668843f; - x *= x2; - s += x * 0.041518066216932693f; - x *= x2; - s -= x * 0.0013422997970712939f; - x *= x2; - s += x * 0.000018930111278021357f; - - return s; -} -/* Special sin(x) for quick calculation when -PI <= x <= PI. */ -static vg_lite_float_t _Sine( - vg_lite_float_t X - ) -{ - vg_lite_float_t x = X; - vg_lite_float_t x2 = X * X; - vg_lite_float_t s = X; - - x *= x2; - s -= x * 0.16664527099620879f; - x *= x2; - s += x * 0.0083154803736487041f; - x *= x2; - s -= x * 0.00019344151251408578f; - x *= x2; - s += x * 0.0000021810214160988925f; - - return s; -} - -static vg_lite_float_t -_Angle( - vg_lite_float_t X, - vg_lite_float_t Y, - vg_lite_float_t Length - ) -{ - vg_lite_float_t angle; - vg_lite_float_t ux = (X >= 0.0f ? X : -X); - vg_lite_float_t uy = (Y >= 0.0f ? Y : -Y); - - if (ux > uy) - { - angle = ((uy > 0.0f && ux < Length) ? _Asin(uy / Length) : 0.0f); - } - else - { - angle = ((ux > 0.0f && uy < Length) ? (FLOAT_PI_HALF - _Asin(ux / Length)) : FLOAT_PI_HALF); - } - - if (X < 0.0f) angle = FLOAT_PI - angle; - if (Y < 0.0f) angle = -angle; - - return angle; -} - -/* The arc is always counter clockwise and less than half circle (small). */ -static vg_lite_error_t -_convert_circle_arc( - vg_lite_stroke_conversion_t *stroke_conversion, - vg_lite_float_t Radius, - vg_lite_float_t CenterX, - vg_lite_float_t CenterY, - vg_lite_float_t StartX, - vg_lite_float_t StartY, - vg_lite_float_t EndX, - vg_lite_float_t EndY, - uint8_t Half_circle, - vg_lite_path_point_ptr *point_list - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - /*gceVGCMD segmentCommand;*/ - vg_lite_float_t theta1, theta_span; - uint32_t segs; - vg_lite_float_t theta, theta_half, theta2; - vg_lite_float_t cos_theta_half; - vg_lite_float_t control_ratio; - vg_lite_float_t controlX, controlY, anchorX, anchorY; - /*gctFLOAT lastX, lastY;*/ - vg_lite_path_point_ptr point, start_point, last_point; - - if(!stroke_conversion || !point_list) - return VG_LITE_INVALID_ARGUMENT; - - /* Converting. */ - theta1 = _Angle(StartX - CenterX, StartY - CenterY, Radius); - if (Half_circle) - { - theta_span = FLOAT_PI; - segs = 4; - theta = FLOAT_PI_QUARTER; - theta_half = FLOAT_PI_EIGHTH; - cos_theta_half = FLOAT_COS_PI_EIGHTH; - } - else - { - theta_span = _Angle(EndX - CenterX, EndY - CenterY, Radius) - theta1; - if (theta_span == 0.0f) - { - /* Handle specail case for huge scaling. */ - *point_list = NULL; - error = VG_LITE_SUCCESS; - return error; - } - - if ((theta_span < 0)) - { - theta_span += FLOAT_PI_TWO; - } - - /* Calculate the number of quadratic Bezier curves. */ - /* Assumption: most of angles are small angles. */ - if (theta_span <= FLOAT_PI_QUARTER) segs = 1; - else if (theta_span <= FLOAT_PI_HALF) segs = 2; - else if (theta_span <= FLOAT_PI_THREE_QUARTER) segs = 3; - else segs = 4; - - theta = theta_span / segs; - theta_half = theta / 2.0f; - cos_theta_half = _Cos(theta_half); - } - - /* Determine the segment command. */ - /*egmentCommand = gcvVGCMD_ARC_QUAD;*/ - - /* Generate quadratic Bezier curves. */ - start_point = last_point = NULL; - control_ratio = Radius / cos_theta_half; - while (segs-- > 0) - { - theta1 += theta; - - theta2 = theta1 - theta_half; - if (theta2 > FLOAT_PI) theta2 -= FLOAT_PI_TWO; - controlX = CenterX + _Cos(theta2) * control_ratio; - controlY = CenterY + _Sine(theta2) * control_ratio; - - theta2 = theta1; - if (theta2 > FLOAT_PI) theta2 -= FLOAT_PI_TWO; - anchorX = CenterX + _Cos(theta2) * Radius; - anchorY = CenterY + _Sine(theta2) * Radius; - - if (segs == 0) - { - /* Use end point directly to avoid accumulated errors. */ - anchorX = EndX; - anchorY = EndY; - } - - /* Add control point. */ - point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); - - if(!point) - return VG_LITE_OUT_OF_RESOURCES; - - memset(point, 0, sizeof(*point)); - - point->x = controlX; - point->y = controlY; - point->curve_type = CURVE_QUAD_CONTROL; - if (last_point) - { - last_point->next = point; - last_point = point; - } - else - { - start_point = last_point = point; - } - - /* Add anchor point. */ - point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); - - if(!point) { - error = VG_LITE_OUT_OF_RESOURCES; - goto ErrorHandler; - } - - memset(point, 0, sizeof(*point)); - - point->x = anchorX; - point->y = anchorY; - point->curve_type = CURVE_QUAD_ANCHOR; - last_point->next = point; - last_point = point; - } - - last_point->next = NULL; - *point_list = start_point; - - return error; -ErrorHandler: - /* Return status. */ - while (start_point) - { - point = start_point; - start_point = start_point->next; - vg_lite_os_free(point); - } - start_point = last_point = point = NULL; - return error; -} - -static vg_lite_error_t -_start_new_stroke_sub_path( - vg_lite_stroke_conversion_t * stroke_conversion, - vg_lite_float_t X, - vg_lite_float_t Y, - vg_lite_float_t Dx, - vg_lite_float_t Dy, - uint8_t add_end_cap, - vg_lite_sub_path_ptr *stroke_subpath - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - - vg_lite_sub_path_ptr stroke_sub_path; - vg_lite_path_point_ptr new_point; - - if(!stroke_conversion || !stroke_subpath) - return VG_LITE_INVALID_ARGUMENT; - - VG_LITE_ERROR_HANDLER(_add_stroke_sub_path(stroke_conversion, &stroke_sub_path)); - - new_point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*new_point)); - if(!new_point) - return VG_LITE_OUT_OF_RESOURCES; - - memset(new_point, 0, sizeof(*new_point)); - new_point->x = X + Dx; - new_point->y = Y + Dy; - new_point->prev = NULL; - new_point->curve_type = CURVE_LINE; - stroke_conversion->stroke_point_list = stroke_conversion->last_right_stroke_point = new_point; - - stroke_sub_path->point_list = stroke_conversion->last_right_stroke_point = new_point; - - new_point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*new_point)); - if(!new_point) - return VG_LITE_OUT_OF_RESOURCES; - - memset(new_point, 0, sizeof(*new_point)); - new_point->x = X - Dx; - new_point->y = Y - Dy; - new_point->curve_type = CURVE_LINE; - new_point->next = NULL; - stroke_conversion->stroke_last_point = stroke_conversion->left_stroke_point = new_point; - - stroke_conversion->stroke_point_count = 2; - - stroke_sub_path->last_point = stroke_conversion->left_stroke_point = new_point; - stroke_sub_path->point_count = 2; - - if (add_end_cap) - { - /* Add end cap if the subPath is not closed. */ - switch (stroke_conversion->stroke_cap_style) - { - case VG_LITE_CAP_BUTT: - /* No adjustment needed. */ - break; - case VG_LITE_CAP_ROUND: - /* Add curve. */ - /* Add the starting point again as arc. */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, - stroke_sub_path->point_list->x, stroke_sub_path->point_list->y)); - stroke_conversion->last_right_stroke_point->curve_type = CURVE_ARC_SCCW_HALF; - stroke_conversion->last_right_stroke_point->centerX = X; - stroke_conversion->last_right_stroke_point->centerY = Y; - /* Change the starting point to end point. */ - stroke_sub_path->point_list->x = stroke_sub_path->last_point->x; - stroke_sub_path->point_list->y = stroke_sub_path->last_point->y; - break; - case VG_LITE_CAP_SQUARE: - stroke_conversion->last_right_stroke_point->x += Dy; - stroke_conversion->last_right_stroke_point->y -= Dx; - stroke_conversion->left_stroke_point->x += Dy; - stroke_conversion->left_stroke_point->y -= Dx; - break; - } - } - - *stroke_subpath = stroke_sub_path; - -ErrorHandler: - return error; -} - -static void -_adjust_joint_point( - vg_lite_path_point_ptr Point, - vg_lite_path_point_ptr join_point, - vg_lite_float_t X, - vg_lite_float_t Y, - vg_lite_float_t Ratio - ) -{ - vg_lite_float_t mx = (join_point->x + X) / 2.0f; - vg_lite_float_t my = (join_point->y + Y) / 2.0f; - vg_lite_float_t dx = mx - Point->x; - vg_lite_float_t dy = my - Point->y; - - dx = dx * Ratio; - dy = dy * Ratio; - join_point->x = Point->x + dx; - join_point->y = Point->y + dy; -} - -static uint8_t -_is_angle_span_acute( - vg_lite_float_t Ux, - vg_lite_float_t Uy, - vg_lite_float_t Vx, - vg_lite_float_t Vy - ) -{ - return ((Ux * Vx + Uy * Vy) > 0.0f ? 1 : 0); -} - -static vg_lite_error_t -_draw_swing_pie_area( - vg_lite_stroke_conversion_t *stroke_conversion, - vg_lite_path_point_ptr center_point, - uint8_t end_at_prev_point - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - - if(!stroke_conversion) - return VG_LITE_INVALID_ARGUMENT; - - if (stroke_conversion->swing_counter_clockwise) - { - vg_lite_path_point_ptr start_point = stroke_conversion->swing_start_stroke_point; - vg_lite_path_point_ptr end_point = NULL, real_end_point = NULL; - vg_lite_path_point_ptr point, prev_point; - uint32_t count = 0; - - { - if (end_at_prev_point) - { - /* Detach the end point from leftStrokePoint. */ - /* The end point will be added back later. */ - real_end_point = stroke_conversion->left_stroke_point; - stroke_conversion->left_stroke_point = real_end_point->next; - stroke_conversion->left_stroke_point->prev = NULL; - } - - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, - center_point->x, center_point->y)); - end_point = stroke_conversion->left_stroke_point; - - /* Reverse the point list from startPoint to endPoint. */ - for (point = start_point; point; point = prev_point) - { - prev_point = point->prev; - point->prev = point->next; - point->next = prev_point; - count++; - } - end_point->next = start_point->prev; - start_point->prev->prev = end_point; - start_point->prev = NULL; - stroke_conversion->left_stroke_point = start_point; - - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, - center_point->x, center_point->y)); - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, - stroke_conversion->swing_start_point->x, - stroke_conversion->swing_start_point->y)); - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, - end_point->prev->x, end_point->prev->y)); - - if (end_at_prev_point) - { - real_end_point->next = stroke_conversion->left_stroke_point; - stroke_conversion->left_stroke_point->prev = real_end_point; - stroke_conversion->left_stroke_point = real_end_point; - } - } - } - else - { - vg_lite_path_point_ptr start_point = stroke_conversion->swing_start_stroke_point; - vg_lite_path_point_ptr end_point = NULL, real_end_point = NULL; - vg_lite_path_point_ptr point, next_point; - uint32_t count = 0; - - { - if (end_at_prev_point) - { - /* Detach the end point from leftStrokePoint. */ - /* The end point will be added back later. */ - real_end_point = stroke_conversion->last_right_stroke_point; - stroke_conversion->last_right_stroke_point = real_end_point->prev; - stroke_conversion->last_right_stroke_point->next = NULL; - } - - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, - center_point->x, center_point->y)); - end_point = stroke_conversion->last_right_stroke_point; - - /* Reverse the point list from startPoint to endPoint. */ - for (point = start_point; point; point = next_point) - { - next_point = point->next; - point->next = point->prev; - point->prev = next_point; - count++; - } - end_point->prev = start_point->next; - start_point->next->next = end_point; - start_point->next = NULL; - stroke_conversion->last_right_stroke_point = start_point; - - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, - center_point->x, center_point->y)); - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, - stroke_conversion->swing_start_point->x, - stroke_conversion->swing_start_point->y)); - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, - end_point->next->x, end_point->next->y)); - - if (end_at_prev_point) - { - real_end_point->prev = stroke_conversion->last_right_stroke_point; - stroke_conversion->last_right_stroke_point->next = real_end_point; - stroke_conversion->last_right_stroke_point = real_end_point; - } - } - } - - stroke_conversion->swing_handling = SWING_NO; - -ErrorHandler: - - return error; -} - -static vg_lite_error_t -_process_line_joint( - vg_lite_stroke_conversion_t * stroke_conversion, - vg_lite_path_point_ptr Point, - vg_lite_float_t Length, - vg_lite_float_t prev_length, - uint32_t Swing_handling, - vg_lite_float_t X1, - vg_lite_float_t Y1, - vg_lite_float_t X2, - vg_lite_float_t Y2 - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_join_style_t stroke_join_style = stroke_conversion->stroke_join_style; - vg_lite_float_t half_width = stroke_conversion->half_line_width; - vg_lite_float_t ratio; - vg_lite_float_t min_length_square; - vg_lite_float_t cos_theta; - uint8_t counter_clockwise; - uint8_t fat_line = stroke_conversion->is_fat; - uint32_t swing_handling = SWING_NO; - uint8_t handle_short_line = 0; - - if(!stroke_conversion) - return VG_LITE_INVALID_ARGUMENT; - - if (stroke_conversion->swing_accu_length < half_width) - { - if (stroke_conversion->swing_need_to_handle) - { - swing_handling = SWING_OUT; - } - else - { - handle_short_line = 1; - } - } - else if (stroke_conversion->stroke_path_length - stroke_conversion->swing_accu_length < half_width) - { - if (stroke_conversion->swing_need_to_handle) - { - swing_handling = SWING_IN; - } - else - { - handle_short_line = 1; - } - } - - if (swing_handling != Swing_handling) - { - error = VG_LITE_INVALID_ARGUMENT; - goto ErrorHandler; - } - - /* For flattened curves/arcs, the join style is always round. */ - if ((Point->flatten_flag != vgcFLATTEN_NO) && fat_line) - { - stroke_join_style = VG_LITE_JOIN_ROUND; - } - - /* First, determine the turn is clockwise or counter-clockwise. */ - cos_theta = Point->prev->tangentX * Point->tangentX + Point->prev->tangentY * Point->tangentY; - - if (cos_theta > FLOAT_ANGLE_EPSILON_COS) - { - /* Straight line or semi-straight line--no need to handle join. */ - if (stroke_conversion->swing_handling !=SWING_NO) - { - /* Begin to swing to the opposite direction. */ - /* Draw the swing area (pie area). */ - VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, Point->prev, 1)); - } - - /* Add the new stroke points. */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); - if (stroke_conversion->swing_handling != SWING_NO) - { - stroke_conversion->swing_count++; - } - - goto endCheck; - } - else if (cos_theta < -FLOAT_ANGLE_EPSILON_COS) - { - /* Almost 180 degree turn. */ - counter_clockwise = 1; - ratio = FLOAT_MAX; - min_length_square = FLOAT_MAX; - } - else - { - vg_lite_float_t angleSign = Point->prev->tangentX * Point->tangentY - Point->prev->tangentY * Point->tangentX; - counter_clockwise = (angleSign >= 0.0f ? 1 : 0); - ratio = 2.0f / (1.0f + cos_theta); - min_length_square = half_width * half_width * (1.0f - cos_theta) / (1.0f + cos_theta) + 0.02f; - } - - if (stroke_conversion->swing_handling != SWING_NO) - { - if (counter_clockwise != stroke_conversion->swing_counter_clockwise) - { - /* Swing to the opposite direction. */ - /* Draw the swing area (pie area). */ - VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, Point->prev, 1)); - } - } - - if (counter_clockwise) - { - if (stroke_conversion->swing_handling != SWING_NO) - { - vg_lite_path_point_ptr prev_point = stroke_conversion->left_stroke_point->next; /* Skip the line segment movement. */ - vg_lite_float_t deltaX = X2 - prev_point->x; - vg_lite_float_t deltaY = Y2 - prev_point->y; - if (_is_angle_span_acute(stroke_conversion->swing_stroke_deltax, - stroke_conversion->swing_stroke_deltay, - deltaX, deltaY)) - { - /* Continue swinging. */ - stroke_conversion->swing_stroke_deltax = deltaX; - stroke_conversion->swing_stroke_deltay = deltaY; - } - else - { - /* Swing to the max. */ - /* Draw the swing area (pie area). */ - VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, Point->prev, 1)); - } - } - - /* Check if the miter length is too long for inner intersection. */ - if (stroke_conversion->swing_handling == SWING_NO - && ! handle_short_line - && min_length_square <= Length * Length - && min_length_square <= prev_length * prev_length) - { - /* Adjust leftStrokePoint to the intersection point. */ - _adjust_joint_point(Point, stroke_conversion->left_stroke_point, X2, Y2, ratio); - } - else if (stroke_conversion->swing_handling == SWING_NO && Point->flatten_flag == vgcFLATTEN_NO) - { - /* Add the point to avoid incorrect sharp angle. */ - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, Point->x, Point->y)); - /* Add the point to form a loop to avoid out-of-bound problem. */ - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); - } - else if (stroke_conversion->swing_handling == SWING_NO && (! fat_line || Swing_handling == SWING_NO)) - { - /* Flattened line segments should not have sharp angle. */ - /* Add the point to form a loop to avoid out-of-bound problem. */ - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); - } - else - { - if (stroke_conversion->swing_handling == SWING_NO) - { - vg_lite_path_point_ptr prev_point = stroke_conversion->left_stroke_point; - - /* Start swing handling. */ - stroke_conversion->swing_handling = Swing_handling; - stroke_conversion->swing_counter_clockwise = 1; - stroke_conversion->swing_start_point = Point; - stroke_conversion->swing_center_length = 0.0f; - stroke_conversion->swing_count= 0; - - /* Save stroking path delta. */ - stroke_conversion->swing_stroke_deltax = X2 - prev_point->x; - stroke_conversion->swing_stroke_deltay = Y2 - prev_point->y; - - /* Add extra center point for swing out pie area. */ - /* VIV: [todo] Should adjust prev_point, instead of adding new point? */ - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, Point->x, Point->y)); - - /* Add extra start stroke point for swing out pie area. */ - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, prev_point->x, prev_point->y)); - - stroke_conversion->swing_start_stroke_point = stroke_conversion->left_stroke_point; - } - -#if USE_MIN_ARC_FILTER - if (cosTheta > FLOAT_MIN_ARC_ANGLE_COS) - { - /* Add a point. */ - gcmERR_GOTO(_add_point_to_left_stroke_point_list_head(Context, stroke_conversion, X2, Y2)); - - VGSL_STAT_COUNTER_INCREASE(vgStrokeFilteredByMinArcAngleCount); - } - else -#endif - { - /* Add curve. */ - /* Note that the curve will be reversed, so the direction is CW. */ - /* Then, left side is in reversed order, so the direction is CCW. */ - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); - stroke_conversion->left_stroke_point->curve_type = CURVE_ARC_SCCW; - stroke_conversion->left_stroke_point->centerX = Point->x; - stroke_conversion->left_stroke_point->centerY = Point->y; - } - stroke_conversion->swing_count++; - } - - switch (stroke_join_style) - { - case VG_LITE_JOIN_ROUND: - if (cos_theta > FLOAT_MIN_ARC_ANGLE_COS) - { - /* Add a point. */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); - } - else - { - /* Add curve. */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); - stroke_conversion->last_right_stroke_point->curve_type = CURVE_ARC_SCCW; - stroke_conversion->last_right_stroke_point->centerX = Point->x; - stroke_conversion->last_right_stroke_point->centerY = Point->y; - } - break; - case VG_LITE_JOIN_MITER: - if (ratio <= stroke_conversion->stroke_miter_limit_square) - { - /* Adjust lastRightStrokePoint to the outer intersection point. */ - _adjust_joint_point(Point, stroke_conversion->last_right_stroke_point, X1, Y1, ratio); - break; - } - /* Else use Bevel join style. */ - case VG_LITE_JOIN_BEVEL: - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); - break; - } - } - else - { - if (stroke_conversion->swing_handling != SWING_NO) - { - vg_lite_path_point_ptr prev_point = stroke_conversion->last_right_stroke_point->prev; /* Skip the line segment movement. */ - vg_lite_float_t deltaX = X1 - prev_point->x; - vg_lite_float_t deltaY = Y1 - prev_point->y; - if (_is_angle_span_acute(stroke_conversion->swing_stroke_deltax, - stroke_conversion->swing_stroke_deltay, - deltaX, deltaY)) - { - /* Continue swinging. */ - stroke_conversion->swing_stroke_deltax = deltaX; - stroke_conversion->swing_stroke_deltay = deltaY; - } - else - { - /* Swing to the max. */ - /* Draw the swing area (pie area). */ - VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, Point->prev, 1)); - } - } - - /* Check if the miter length is too long for inner intersection. */ - if (stroke_conversion->swing_handling == SWING_NO - && ! handle_short_line - && min_length_square <= Length * Length - && min_length_square <= prev_length * prev_length) - { - /* Adjust lastRightStrokePoint to the intersection point. */ - _adjust_joint_point(Point, stroke_conversion->last_right_stroke_point, X1, Y1, ratio); - } - else if (stroke_conversion->swing_handling == SWING_NO && Point->flatten_flag == vgcFLATTEN_NO) - { - /* Add the point to avoid incorrect sharp angle. */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, Point->x, Point->y)); - /* Add the point to form a loop to avoid out-of-bound problem. */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); - } - else if (stroke_conversion->swing_handling == SWING_NO && (! fat_line || Swing_handling == SWING_NO)) - { - /* Flattened line segments should not have sharp angle. */ - /* Add the point to form a loop to avoid out-of-bound problem. */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); - } - else - { - if (stroke_conversion->swing_handling == SWING_NO) - { - vg_lite_path_point_ptr prev_point = stroke_conversion->last_right_stroke_point; - - /* Start swing handling. */ - stroke_conversion->swing_handling = Swing_handling; - stroke_conversion->swing_counter_clockwise = 0; - stroke_conversion->swing_start_point = Point; - stroke_conversion->swing_center_length = 0.0f; - stroke_conversion->swing_count= 0; - - /* Save stroking path delta. */ - stroke_conversion->swing_stroke_deltax = X1 - prev_point->x; - stroke_conversion->swing_stroke_deltay = Y1 - prev_point->y; - - /* Add extra center point for swing out pie area. */ - /* VIV: [todo] Should adjust prev_point, instead of adding new point? */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, Point->x, Point->y)); - - /* Add extra start stroke point for swing out pie area. */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, prev_point->x, prev_point->y)); - - stroke_conversion->swing_start_stroke_point = stroke_conversion->last_right_stroke_point; - } - - if (cos_theta > FLOAT_MIN_ARC_ANGLE_COS) - { - /* Add a point. */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); - } - else - { - /* Add curve. */ - /* Note that the curve will be reversed, so the direction is CCW. */ - stroke_conversion->last_right_stroke_point->curve_type = CURVE_ARC_SCCW; - stroke_conversion->last_right_stroke_point->centerX = Point->x; - stroke_conversion->last_right_stroke_point->centerY = Point->y; - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X1, Y1)); - } - stroke_conversion->swing_count++; - } - - switch (stroke_join_style) - { - case VG_LITE_JOIN_ROUND: - if (cos_theta > FLOAT_MIN_ARC_ANGLE_COS) - { - /* Add a point. */ - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); - } - else - { - /* Add curve. */ - stroke_conversion->left_stroke_point->curve_type = CURVE_ARC_SCCW; - stroke_conversion->left_stroke_point->centerX = Point->x; - stroke_conversion->left_stroke_point->centerY = Point->y; - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); - } - break; - case VG_LITE_JOIN_MITER: - if (ratio <= stroke_conversion->stroke_miter_limit_square) - { - /* Adjust leftStrokePoint to the outer intersection point. */ - _adjust_joint_point(Point, stroke_conversion->left_stroke_point, X2, Y2, ratio); - break; - } - /* Else use Bevel join style. */ - case VG_LITE_JOIN_BEVEL: - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, X2, Y2)); - break; - } - } - -endCheck: - if (stroke_conversion->swing_need_to_handle) - { - stroke_conversion->swing_accu_length += Point->length; - } - if (stroke_conversion->swing_handling != SWING_NO) - { - if (Point->flatten_flag == vgcFLATTEN_END || - (stroke_conversion->swing_handling == SWING_OUT && - stroke_conversion->swing_accu_length > half_width)) - { - /* Draw the swing area (pie area). */ - VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, Point, 0)); - } - else - { - /* Check if center line will move too far. */ - stroke_conversion->swing_center_length += Point->length; - if (stroke_conversion->swing_center_length > FLOAT_SWING_CENTER_RANGE) - { -#if USE_NEW_SWING_HANDLE_FOR_END - if (stroke_conversion->currentSubPath->length < half_width || - Point->next->flatten_flag == vgcFLATTEN_END) -#endif - { - /* Draw the swing area (pie area). */ - VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, Point, 0)); - } - } - } - } - -ErrorHandler: - - return error; -} - -static vg_lite_error_t -_close_stroke_sub_path( - vg_lite_stroke_conversion_t * stroke_conversion, - vg_lite_path_point_ptr Point, - vg_lite_float_t Length, - vg_lite_float_t prev_length, - uint8_t Swing_handling, - vg_lite_path_point_ptr first_stroke_point, - vg_lite_path_point_ptr last_stroke_point - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - if(!stroke_conversion) - return VG_LITE_INVALID_ARGUMENT; - - /* Handle line joint style for the first/last point in closed path. */ - VG_LITE_ERROR_HANDLER(_process_line_joint( - stroke_conversion, Point, - Length, prev_length, Swing_handling, - first_stroke_point->x, first_stroke_point->y, - last_stroke_point->x, last_stroke_point->y - )); - - /* Adjust the two end ponts of the first point. */ - first_stroke_point->x = stroke_conversion->last_right_stroke_point->x; - first_stroke_point->y = stroke_conversion->last_right_stroke_point->y; - last_stroke_point->x = stroke_conversion->left_stroke_point->x; - last_stroke_point->y = stroke_conversion->left_stroke_point->y; - - /* Concatnate right and left point lists. */ - stroke_conversion->last_right_stroke_point->next = stroke_conversion->left_stroke_point; - stroke_conversion->left_stroke_point->prev = stroke_conversion->last_right_stroke_point; - - /*gcmERROR_RETURN(_CheckStrokeSubPath(stroke_conversion->lastStrokeSubPath));*/ - -ErrorHandler: - return error; -} - -static vg_lite_error_t _end_stroke_sub_path( - vg_lite_stroke_conversion_t *stroke_conversion, - vg_lite_float_t X, - vg_lite_float_t Y, - vg_lite_float_t Dx, - vg_lite_float_t Dy - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - - if(!stroke_conversion) - return VG_LITE_INVALID_ARGUMENT; - - /* Add points for end of line. */ - VG_LITE_RETURN_ERROR(_add_point_to_right_stroke_point_list_tail(stroke_conversion, X + Dx, Y + Dy)); - VG_LITE_RETURN_ERROR(_add_point_to_left_stroke_point_list_head(stroke_conversion, X - Dx, Y - Dy)); - - /* Add end cap if the subPath is not closed. */ - switch (stroke_conversion->stroke_cap_style) - { - case VG_LITE_CAP_BUTT: - /* No adjustment needed. */ - break; - case VG_LITE_CAP_ROUND: - /* Add curve. */ - stroke_conversion->left_stroke_point->curve_type = CURVE_ARC_SCCW_HALF; - stroke_conversion->left_stroke_point->centerX = X; - stroke_conversion->left_stroke_point->centerY = Y; - break; - case VG_LITE_CAP_SQUARE: - stroke_conversion->last_right_stroke_point->x -= Dy; - stroke_conversion->last_right_stroke_point->y += Dx; - stroke_conversion->left_stroke_point->x -= Dy; - stroke_conversion->left_stroke_point->y += Dx; - break; - } - - /* Concatnate right and left point lists. */ - stroke_conversion->last_right_stroke_point->next = stroke_conversion->left_stroke_point; - stroke_conversion->left_stroke_point->prev = stroke_conversion->last_right_stroke_point; - - /*gcmERROR_RETURN(_CheckStrokeSubPath(stroke_conversion->lastStrokeSubPath));*/ - return error; -} - -static vg_lite_error_t _get_next_dash_length( - vg_lite_stroke_conversion_t * stroke_conversion, - uint32_t * dash_index, - vg_lite_float_t * dash_length - ) -{ - if(!stroke_conversion || !dash_index || !dash_length) - return VG_LITE_INVALID_ARGUMENT; - - (*dash_index)++; - if (*dash_index == stroke_conversion->stroke_dash_pattern_count) - { - *dash_index = 0; - } - *dash_length = stroke_conversion->stroke_dash_pattern[*dash_index]; - - return VG_LITE_SUCCESS; -} - -static vg_lite_error_t -_create_stroke_path( - vg_lite_stroke_conversion_t * stroke_conversion - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_sub_path_ptr stroke_sub_path = NULL,first_stroke_sub_path = NULL; - vg_lite_path_point_ptr point, next_point; - vg_lite_float_t half_width; - vg_lite_float_t x, y; - vg_lite_float_t dx, dy, ux, uy; - vg_lite_float_t length, prev_length, first_length; - vg_lite_float_t dash_length; - uint32_t dash_index; - uint8_t dashing; - uint8_t add_end_cap; - uint8_t need_to_handle_swing = 1 /* (stroke_conversion->strokeCapStyle == gcvCAP_BUTT) */; - - vg_lite_path_point_ptr first_right_point = NULL; - vg_lite_path_point_ptr last_left_point = NULL; - vg_lite_float_t first_dx = 0.0f, first_dy = 0.0f; - uint8_t drawing = 0; - vg_lite_float_t total_length = 0.0f; - vg_lite_float_t accu_length = 0.0f; - uint32_t swing_handling = SWING_NO; - - if(!stroke_conversion) - return VG_LITE_INVALID_ARGUMENT; - - half_width = stroke_conversion->half_line_width; - dashing = stroke_conversion->stroke_dash_pattern_count > 0 ? 1 : 0; - dash_index = stroke_conversion->stroke_dash_initial_index; - dash_length = stroke_conversion->stroke_dash_initial_length; - - /* VIV: [todo] Need to check/debug closed stroke path. */ - need_to_handle_swing = (stroke_conversion->stroke_cap_style == VG_LITE_CAP_BUTT || stroke_conversion->closed); - if (need_to_handle_swing) - { - uint8_t reallyneed_to_handle_swing = 0; - - /* Calculate the total length. */ - for (point = stroke_conversion->path_point_list; point; point = point->next) - { - total_length += point->length; - - if (point->flatten_flag != vgcFLATTEN_NO) - { - reallyneed_to_handle_swing = 1; - } - } - stroke_conversion->stroke_path_length = total_length; - if (reallyneed_to_handle_swing) - { - swing_handling = SWING_OUT; - } - else - { - need_to_handle_swing = 0; - swing_handling = SWING_NO; - } - } - stroke_conversion->swing_need_to_handle = need_to_handle_swing; - - point = stroke_conversion->path_point_list; - next_point = point->next; - if (next_point == NULL) - { - if (!dashing || ((dash_index & 0x1) == 0)) - { - /* Single point (zero-length) subpath. */ - /* Note that one-MOVE_TO subpaths are removed during parsing. */ - VG_LITE_ERROR_HANDLER(_add_zero_length_stroke_sub_path(stroke_conversion, &stroke_sub_path)); - } - goto ErrorHandler; - } - - /* Adjust closed status for dashing. */ - if (dashing && stroke_conversion->closed && ((dash_index & 0x1) == 1)) - { - stroke_conversion->closed = FALSE; - } - - /* Set add_end_cap. */ - add_end_cap = dashing ? 1: (stroke_conversion->closed ? 0 : 1); - - /* Process first line. */ - first_length = point->length; - ux = point->tangentX; - uy = point->tangentY; - dx = uy * half_width; - dy = -ux * half_width; - if (need_to_handle_swing) - { - stroke_conversion->swing_accu_length = first_length; - } - - if (dashing) - { - vg_lite_float_t delta_length; - - /* Draw dashes. */ - x = point->x; - y = point->y; - do - { - if ((dash_index & 0x1) == 0) - { - VG_LITE_ERROR_HANDLER(_start_new_stroke_sub_path( - stroke_conversion, - x, y, - dx, dy, add_end_cap, - &stroke_sub_path - )); - - drawing = 1; - add_end_cap = 1; - if (stroke_conversion->closed && (first_stroke_sub_path == NULL)) - { - first_stroke_sub_path = stroke_conversion->last_stroke_sub_path; - first_right_point = stroke_conversion->last_right_stroke_point; - last_left_point = stroke_conversion->left_stroke_point; - first_dx = dx; - first_dy = dy; - } - } - - delta_length = first_length - dash_length; - if (delta_length >= FLOAT_EPSILON) - { - /* Move (x, y) forward along the line by dash_length. */ - x += ux * dash_length; - y += uy * dash_length; - - if ((dash_index & 0x1) == 0) - { - VG_LITE_ERROR_HANDLER(_end_stroke_sub_path( - stroke_conversion, - x, y, - dx, dy - )); - - drawing = 0; - } - - VG_LITE_ERROR_HANDLER(_get_next_dash_length(stroke_conversion, &dash_index, &dash_length)); - first_length = delta_length; - } - else if (delta_length <= -FLOAT_EPSILON) - { - dash_length = -delta_length; - break; - } - else - { - if ((dash_index & 0x1) == 0) - { - VG_LITE_ERROR_HANDLER(_end_stroke_sub_path( - stroke_conversion, - next_point->x, next_point->y, - dx, dy - )); - - drawing = 0; - } - - VG_LITE_ERROR_HANDLER(_get_next_dash_length(stroke_conversion, &dash_index, &dash_length)); - first_length = 0; - break; - } - } - while (1); - } - else - { - VG_LITE_ERROR_HANDLER(_start_new_stroke_sub_path( - stroke_conversion, - point->x, point->y, - dx, dy, add_end_cap, - &stroke_sub_path - )); - - drawing = 1; - add_end_cap = 1; - } - - /* Process the rest of lines. */ - prev_length = first_length; - for (point = next_point, next_point = point->next; next_point; - point = next_point, next_point = point->next) - { - if (!dashing || ((dash_index & 0x1) == 0 && drawing)) - { - /* Add points for end of line for line join process with next line. */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, - point->x + dx, point->y + dy)); - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, - point->x - dx, point->y - dy)); - } - - length = point->length; - ux = point->tangentX; - uy = point->tangentY; - dx = uy * half_width; - dy = -ux * half_width; - if (need_to_handle_swing) - { - accu_length += point->prev->length; - stroke_conversion->swing_accu_length = accu_length; - if (accu_length < half_width) - { - swing_handling = SWING_OUT; - } - else if (total_length - accu_length < half_width) - { - swing_handling = SWING_IN; - } - else - { - swing_handling = SWING_NO; - } - } - - if (!dashing) - { - /* Handle line joint style. */ - VG_LITE_ERROR_HANDLER(_process_line_joint( - stroke_conversion, point, - length, prev_length, swing_handling, - point->x + dx, point->y + dy, - point->x - dx, point->y - dy - )); - } - else - { - vg_lite_float_t delta_length; - - /* Draw dashes. */ - x = point->x; - y = point->y; - if ((dash_index & 0x1) == 0) - { - if (drawing) - { - /* Handle line joint style. */ - VG_LITE_ERROR_HANDLER(_process_line_joint( - stroke_conversion, point, - dash_length, prev_length, swing_handling, - x + dx, y + dy, - x - dx, y - dy - )); - } - else - { - /* Start a new sub path. */ - VG_LITE_ERROR_HANDLER(_start_new_stroke_sub_path( - stroke_conversion, - x, y, - dx, dy, add_end_cap, - &stroke_sub_path - )); - - drawing = 1; - add_end_cap = 1; - } - } - do - { - delta_length = length - dash_length; - if (delta_length >= FLOAT_EPSILON) - { - /* Move (x, y) forward along the line by dash_length. */ - x += ux * dash_length; - y += uy * dash_length; - - if ((dash_index & 0x1) == 0) - { - VG_LITE_ERROR_HANDLER(_end_stroke_sub_path( - stroke_conversion, - x, y, dx, dy - )); - - drawing = 0; - } - - VG_LITE_ERROR_HANDLER(_get_next_dash_length(stroke_conversion, &dash_index, &dash_length)); - length = delta_length; - } - else if (delta_length <= -FLOAT_EPSILON) - { - dash_length = -delta_length; - break; - } - else - { - if ((dash_index & 0x1) == 0) - { - VG_LITE_ERROR_HANDLER(_end_stroke_sub_path( - stroke_conversion, - next_point->x, next_point->y, - dx, dy - )); - - drawing = 0; - } - - VG_LITE_ERROR_HANDLER(_get_next_dash_length(stroke_conversion, &dash_index, &dash_length)); - length = 0; - break; - } - - if ((dash_index & 0x1) == 0) - { - VG_LITE_ERROR_HANDLER(_start_new_stroke_sub_path( - stroke_conversion, - x, y, - dx, dy, add_end_cap, - &stroke_sub_path - )); - - drawing = 1; - add_end_cap = 1; - } - } - while (1); - } - - prev_length = length; - } - - if (need_to_handle_swing) - { - accu_length += point->prev->length; - stroke_conversion->swing_accu_length = accu_length; - if (accu_length < half_width) - { - swing_handling = SWING_OUT; - } - else if (total_length - accu_length < half_width) - { - swing_handling = SWING_IN; - } - else - { - swing_handling = SWING_NO; - } - } - - if (stroke_conversion->swing_handling != SWING_NO) - { - /* Draw the swing area (pie area). */ - VG_LITE_ERROR_HANDLER(_draw_swing_pie_area(stroke_conversion, stroke_conversion->path_last_point, FALSE)); - } - - if (stroke_conversion->closed) - { - if (! dashing || drawing) - { - /* Add points for end of line. */ - VG_LITE_ERROR_HANDLER(_add_point_to_right_stroke_point_list_tail(stroke_conversion, - point->x + dx, point->y + dy)); - VG_LITE_ERROR_HANDLER(_add_point_to_left_stroke_point_list_head(stroke_conversion, - point->x - dx, point->y - dy)); - - if (! dashing) - { - /* Handle line joint style for the first/last point in closed path. */ - VG_LITE_ERROR_HANDLER(_close_stroke_sub_path( - stroke_conversion, point, - first_length, prev_length, swing_handling, - stroke_sub_path->point_list, stroke_sub_path->last_point - )); - } - else - { - /* Handle line joint style for the first/last point in closed path. */ - VG_LITE_ERROR_HANDLER(_close_stroke_sub_path( - stroke_conversion, point, - first_length, prev_length, swing_handling, - first_right_point, last_left_point - )); - } - } - else if (stroke_conversion->stroke_cap_style != VG_LITE_CAP_BUTT) - { - /* No closing join need. Add end cap for the starting point. */ - - if (stroke_conversion->stroke_cap_style == VG_LITE_CAP_SQUARE) - { - first_right_point->x += first_dy; - first_right_point->y -= first_dx; - last_left_point->x += first_dy; - last_left_point->y -= first_dx; - } - else - { - vg_lite_sub_path_ptr last_stroke_sub_path = stroke_conversion->last_stroke_sub_path; - vg_lite_path_point_ptr start_point = last_stroke_sub_path->point_list; - vg_lite_path_point_ptr point; - - /* Add curve. */ - /* Add extra point to the beginning with end point's coordinates. */ - point = (vg_lite_path_point_ptr)vg_lite_os_malloc(sizeof(*point)); - if(!point) - return VG_LITE_INVALID_ARGUMENT; - memset(point, 0, sizeof(*point)); - - point->x = last_stroke_sub_path->last_point->x; - point->y = last_stroke_sub_path->last_point->y; - point->next = start_point; - start_point->prev = point; - start_point->curve_type = CURVE_ARC_SCCW; - start_point->centerX = stroke_conversion->path_point_list->x; - start_point->centerY = stroke_conversion->path_point_list->y; - last_stroke_sub_path->point_list = point; - } - } - } - else if (! dashing || - (((dash_index & 0x1) == 0) && (dash_length < stroke_conversion->stroke_dash_pattern[dash_index]))) - { - /* Add end cap if the subPath is not closed. */ - VG_LITE_ERROR_HANDLER(_end_stroke_sub_path( - stroke_conversion, - point->x, point->y, - dx, dy - )); - - drawing = 0; - } - - -ErrorHandler: - return error; -} - -static vg_lite_error_t _copy_stroke_path( - vg_lite_stroke_conversion_t * stroke_conversion, - vg_lite_path_t *path - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_path_point_ptr point,prev_point,tmp_point; - uint32_t totalsize = 0,real_size = 0; - float *pfloat; - char *cpath = NULL; - char last_opcode = 0; - void *temp_stroke_path_data = NULL; - uint32_t temp_stroke_path_size; - vg_lite_sub_path_ptr sub_path; - vg_lite_float_t half_width; - - if(!stroke_conversion || !path) - return VG_LITE_INVALID_ARGUMENT; - - half_width = stroke_conversion->half_line_width; - sub_path = stroke_conversion->stroke_sub_path_list; - - if(!stroke_conversion || !path || !sub_path) - return VG_LITE_INVALID_ARGUMENT; - - while (sub_path) - { - tmp_point = prev_point = point = sub_path->point_list; - totalsize += _commandSize_float[VLC_OP_LINE] * sub_path->point_count + _commandSize_float[VLC_OP_CLOSE]; - for(;tmp_point;tmp_point = tmp_point->next) - { - if(tmp_point->curve_type == CURVE_ARC_SCCW || tmp_point->curve_type == CURVE_ARC_SCCW_HALF) { - totalsize += 4 * _commandSize_float[VLC_OP_QUAD]; - } - } - - temp_stroke_path_data = path->stroke_path_data; - temp_stroke_path_size = path->stroke_path_size; - - path->stroke_path_size += totalsize; - path->stroke_path_data = (void *)vg_lite_os_malloc(path->stroke_path_size); - if(!path->stroke_path_data) { - error = VG_LITE_INVALID_ARGUMENT; - goto ErrorHandler; - } - - memset(path->stroke_path_data, 0, path->stroke_path_size); - - if(temp_stroke_path_data) { - memcpy(path->stroke_path_data,temp_stroke_path_data,temp_stroke_path_size); - vg_lite_os_free(temp_stroke_path_data); - temp_stroke_path_data = NULL; - } - - pfloat = (vg_lite_float_t *)((char *)path->stroke_path_data + temp_stroke_path_size); - if(last_opcode == VLC_OP_CLOSE) { - cpath = (char *)(pfloat - 1) + 1; - *cpath++ = VLC_OP_MOVE; - cpath = (char *)pfloat; - } - else { - cpath = (char *)pfloat; - *cpath = VLC_OP_MOVE; - pfloat++; - } - - *pfloat++ = point->x; - *pfloat++ = point->y; - real_size += _commandSize_float[VLC_OP_MOVE]; - if(last_opcode == VLC_OP_CLOSE) - real_size -= 4; - - for (point = point->next; point; prev_point = point, point = point->next) - { - if (point->curve_type == CURVE_LINE) - { - if (point->x == prev_point->x && point->y == prev_point->y) - { - path->stroke_path_size -= _commandSize_float[VLC_OP_LINE]; - /* Skip zero-length lines. */ - continue; - } - - /* Add new command. */ - cpath = (char *)pfloat; - *cpath = VLC_OP_LINE; - pfloat++; - - /* Set the coordinates. */ - *pfloat++ = point->x; - *pfloat++ = point->y; - real_size += _commandSize_float[VLC_OP_LINE]; - } - else if (point->curve_type == CURVE_QUAD_CONTROL) - { - /* Add new command. */ - cpath = (char *)pfloat; - *cpath = VLC_OP_QUAD; - pfloat++; - - /* Set the coordinates. */ - prev_point = point, point = point->next; - *pfloat++ = prev_point->x; - *pfloat++ = prev_point->y; - *pfloat++ = point->x; - *pfloat++ = point->y; - - real_size += _commandSize_float[VLC_OP_QUAD]; - } - else - { - vg_lite_path_point_ptr point_list, p, nextP; - vg_lite_path_point_ptr p2; - - if (point->curve_type == CURVE_ARC_SCCW) - { - /* Convert an arc to Bezier curves. */ - VG_LITE_ERROR_HANDLER(_convert_circle_arc(stroke_conversion, half_width, - point->centerX, point->centerY, - prev_point->x, prev_point->y, - point->x, point->y, - 0, &point_list)); - } - else - { - /* Convert a half circle to Bezier curves. */ - VG_LITE_ERROR_HANDLER(_convert_circle_arc(stroke_conversion, half_width, - point->centerX, point->centerY, - prev_point->x, prev_point->y, - point->x, point->y, - 1, &point_list)); - - } - - if (point_list) - { - for (p = point_list; p; p = nextP) - { - /* Add new command. */ - cpath = (char *)pfloat; - *cpath = VLC_OP_QUAD; - pfloat++; - - /* Set the coordinates. */ - p2 = p->next; - nextP = p2->next; - - *pfloat++ = p->x; - *pfloat++ = p->y; - *pfloat++ = p2->x; - *pfloat++ = p2->y; - real_size += _commandSize_float[VLC_OP_QUAD]; - vg_lite_os_free(p); - vg_lite_os_free(p2); - } - } - else - { - /* Handle special case of huge scaling. */ - /* Add new command. */ - cpath = (char *)pfloat; - *cpath = VLC_OP_LINE; - pfloat++; - - /* Set the coordinates. */ - *pfloat++ = point->x; - *pfloat++ = point->y; - real_size += _commandSize_float[VLC_OP_LINE]; - } - } - } - - /* Create a CLOSE_PATH command at the end. */ - cpath = (char *)pfloat; - if(sub_path->next) - *cpath = VLC_OP_CLOSE; - else - *cpath = VLC_OP_END; - real_size += _commandSize_float[VLC_OP_CLOSE]; - path->stroke_path_size = temp_stroke_path_size + real_size; - totalsize = 0; - real_size = 0; - sub_path = sub_path->next; - last_opcode = *cpath; - } - -ErrorHandler: - - if(temp_stroke_path_data) { - vg_lite_os_free(temp_stroke_path_data); - temp_stroke_path_data = NULL; - } - - return error; -} - -static vg_lite_error_t _initialize_stroke_dash_parameters( - vg_lite_stroke_conversion_t * stroke_conversion - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t count; - uint32_t i; - vg_lite_float_t *pattern_src; - vg_lite_float_t *pattern,*temp_pattern; - vg_lite_float_t length; - - if(!stroke_conversion) - return VG_LITE_INVALID_ARGUMENT; - - count = stroke_conversion->stroke_dash_pattern_count; - if (count == 0 || !stroke_conversion->stroke_dash_pattern) - return error; - - length = stroke_conversion->stroke_dash_phase; - - /* The last pattern is ignored if the number is odd. */ - if (count & 0x1) count--; - - pattern = (vg_lite_float_t *)vg_lite_os_malloc(count * sizeof(vg_lite_float_t)); - if(!pattern) - return VG_LITE_OUT_OF_RESOURCES; - - temp_pattern = pattern; - stroke_conversion->stroke_dash_pattern_length = 0.0f; - pattern_src = stroke_conversion->stroke_dash_pattern; - - for (i = 0; i < count; i++, pattern++, pattern_src++) - { - if (*pattern_src < 0.0f) - { - *pattern = 0.0f; - } - else - { - *pattern = *pattern_src; - } - stroke_conversion->stroke_dash_pattern_length += *pattern; - } - - if (stroke_conversion->stroke_dash_pattern_length < FLOAT_EPSILON) - { - stroke_conversion->stroke_dash_pattern_count = 0; - vg_lite_os_free(temp_pattern); - temp_pattern = NULL; - return error; - } - - while (length < 0.0f) - { - length += stroke_conversion->stroke_dash_pattern_length; - } - - while (length >= stroke_conversion->stroke_dash_pattern_length) - { - length -= stroke_conversion->stroke_dash_pattern_length; - } - - pattern = stroke_conversion->stroke_dash_pattern; - for (i = 0; i < stroke_conversion->stroke_dash_pattern_count; i++, pattern++) - { - if (length <= *pattern) break; - - length -= *pattern; - } - - stroke_conversion->stroke_dash_initial_index = i; - stroke_conversion->stroke_dash_initial_length = *pattern - length; - - vg_lite_os_free(temp_pattern); - temp_pattern = NULL; - - return error; -} - -vg_lite_error_t vg_lite_update_stroke( - vg_lite_path_t *path - ) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_stroke_conversion_t * stroke_conversion; - - if(!path) - return VG_LITE_INVALID_ARGUMENT; - - stroke_conversion = &path->stroke_conversion; - - /* Free the stroke. */ - if (path->stroke_path_data) - { - vg_lite_os_free(path->stroke_path_data); - /* Reset the stroke. */ - path->stroke_path_data = NULL; - } - - if (stroke_conversion->stroke_line_width >= FLOAT_FAT_LINE_WIDTH - && stroke_conversion->stroke_line_width >= 1.0f) - { - stroke_conversion->is_fat = 1; - } - VG_LITE_RETURN_ERROR(_initialize_stroke_dash_parameters(stroke_conversion)); - VG_LITE_RETURN_ERROR(_flatten_path(stroke_conversion, path)); - VG_LITE_RETURN_ERROR(_create_stroke_path(stroke_conversion)); - VG_LITE_RETURN_ERROR(_copy_stroke_path(stroke_conversion, path)); - - return error; -} - -vg_lite_error_t vg_lite_set_stroke( - vg_lite_path_t *path, - vg_lite_cap_style_t stroke_cap_style, - vg_lite_join_style_t stroke_join_style, - vg_lite_float_t stroke_line_width, - vg_lite_float_t stroke_miter_limit, - vg_lite_float_t *stroke_dash_pattern, - uint32_t stroke_dash_pattern_count, - vg_lite_float_t stroke_dash_phase, - vg_lite_color_t stroke_color - ) -{ - if(!path || stroke_line_width <= 0) - return VG_LITE_INVALID_ARGUMENT; - - if(stroke_miter_limit < 1.0f) - stroke_miter_limit = 1.0f; - - path->stroke_conversion.stroke_cap_style = stroke_cap_style; - path->stroke_conversion.stroke_join_style = stroke_join_style; - path->stroke_conversion.stroke_line_width = stroke_line_width; - path->stroke_conversion.stroke_miter_limit = stroke_miter_limit; - path->stroke_conversion.half_line_width = stroke_line_width / 2.0f; - path->stroke_conversion.stroke_miter_limit_square = path->stroke_conversion.stroke_miter_limit * path->stroke_conversion.stroke_miter_limit; - path->stroke_conversion.stroke_dash_pattern = stroke_dash_pattern; - path->stroke_conversion.stroke_dash_pattern_count = stroke_dash_pattern_count; - path->stroke_conversion.stroke_dash_phase = stroke_dash_phase; - path->stroke_color = stroke_color; - - return VG_LITE_SUCCESS; -} - -static inline vg_lite_error_t transform_bounding_box(vg_lite_rectangle_t *in_bbx, - vg_lite_matrix_t *matrix, - vg_lite_rectangle_t *clip, - vg_lite_rectangle_t *out_bbx, - vg_lite_point_t *origin); - -#if (VG_BLIT_WORKAROUND == 1) -/* - * Calculates the minimal possible target buffer starting from a given target - * buffer and considering a source texture (to blit), graphic transformations - * and clipping window. - */ -static vg_lite_error_t config_new_target(vg_lite_buffer_t *target, - vg_lite_buffer_t *source, - vg_lite_matrix_t *matrix, - vg_lite_rectangle_t *clip, - vg_lite_buffer_t *new_target); -#endif /* VG_BLIT_WORKAROUND */ - -static vg_lite_error_t swap(float *a,float *b) -{ - float temp; - if(a == NULL || b == NULL) - return VG_LITE_INVALID_ARGUMENT; - temp = *a; - *a = *b; - *b = temp; - return VG_LITE_SUCCESS; -} - -static vg_lite_float_t _angle( - vg_lite_float_t Ux, - vg_lite_float_t Uy, - vg_lite_float_t Vx, - vg_lite_float_t Vy - ) -{ - - vg_lite_float_t dot, length, angle, cosVal; - int32_t sign; - - dot = Ux * Vx + Uy * Vy; - length = SQRTF(Ux * Ux + Uy * Uy) * SQRTF(Vx * Vx + Vy * Vy); - sign = (Ux * Vy - Uy * Vx < 0) ? -1 : 1; - cosVal = dot / length; - cosVal = CLAMP(cosVal, -1.0f, 1.0f); - angle = sign * ACOSF(cosVal); - return angle; -} - -/*! - @discussion - Convert arc to multi-segment bezier curve. - @param HorRadius - Major axis radius. - @param VerRadius - minor axis radius. - @param RotAngle - Rotation angle. - @param EndX - End coordinate x. - @param EndX - End coordinate y. - @param CounterClockwise - If this is 0,anticlockwise rotation,if this is 1,clockwise rotation. - @param Large - 1 means big arc,0 means little arc. - @param Relative - 1 means absolute coordinates,0 means relative coordinates. - @param coords - Including the start point coordinates of the path,the control point of the last segment of the path, - and the end point of the last segment of the path. - @param path_data - Path data usr for internal conversion. - @param offset - The offset of path_data. - @param last_size - The remain unconverted size of the original path data. - @result - Error code. VG_LITE_INVALID_ARGUMENTS to indicate the parameters are wrong. -*/ -vg_lite_error_t _convert_arc( - vg_lite_float_t HorRadius, - vg_lite_float_t VerRadius, - vg_lite_float_t RotAngle, - vg_lite_float_t EndX, - vg_lite_float_t EndY, - uint8_t CounterClockwise, - uint8_t Large, - uint8_t Relative, - vg_lite_control_coord_t* coords, - void ** path_data, - uint32_t *offset, - uint32_t last_size - ) -{ - vg_lite_float_t endX, endY; - uint8_t segmentCommand; - vg_lite_float_t phi, cosPhi, sinPhi; - vg_lite_float_t dxHalf, dyHalf; - vg_lite_float_t x1Prime, y1Prime; - vg_lite_float_t rx, ry; - vg_lite_float_t x1PrimeSquare, y1PrimeSquare; - vg_lite_float_t lambda; - vg_lite_float_t rxSquare, rySquare; - int32_t sign; - vg_lite_float_t sq, signedSq; - vg_lite_float_t cxPrime, cyPrime; - vg_lite_float_t theta1, thetaSpan; - int32_t segs; - vg_lite_float_t theta, ax, ay, x, y; - vg_lite_float_t controlX, controlY, anchorX, anchorY; - vg_lite_float_t lastX, lastY; - uint32_t bufferSize; - char *pchar, *arcPath; - vg_lite_float_t *pfloat; - /******************************************************************* - ** Converting. - */ - if(path_data == NULL || *path_data == NULL || offset == NULL || coords == NULL) - return VG_LITE_INVALID_ARGUMENT; - - if (Relative) - { - endX = EndX + coords->lastX; - endY = EndY + coords->lastY; - } - else - { - endX = EndX; - endY = EndY; - } - - phi = RotAngle / 180.0f * PI; - cosPhi = COSF(phi); - sinPhi = SINF(phi); - - if (Relative) - { - dxHalf = - EndX / 2.0f; - dyHalf = - EndY / 2.0f; - } - else - { - dxHalf = (coords->lastX - endX) / 2.0f; - dyHalf = (coords->lastY - endY) / 2.0f; - } - - x1Prime = cosPhi * dxHalf + sinPhi * dyHalf; - y1Prime = -sinPhi * dxHalf + cosPhi * dyHalf; - - rx = FABSF(HorRadius); - ry = FABSF(VerRadius); - - x1PrimeSquare = x1Prime * x1Prime; - y1PrimeSquare = y1Prime * y1Prime; - - lambda = x1PrimeSquare / (rx * rx) + y1PrimeSquare / (ry * ry); - if (lambda > 1.0f) - { - rx *= SQRTF(lambda); - ry *= SQRTF(lambda); - } - - rxSquare = rx * rx; - rySquare = ry * ry; - - sign = (Large == CounterClockwise) ? -1 : 1; - sq = ( rxSquare * rySquare - - rxSquare * y1PrimeSquare - - rySquare * x1PrimeSquare - ) - / - ( rxSquare * y1PrimeSquare - + rySquare * x1PrimeSquare - ); - signedSq = sign * ((sq < 0) ? 0 : SQRTF(sq)); - cxPrime = signedSq * (rx * y1Prime / ry); - cyPrime = signedSq * -(ry * x1Prime / rx); - - theta1 = _angle(1, 0, (x1Prime - cxPrime) / rx, (y1Prime - cyPrime) / ry); - theta1 = FMODF(theta1, 2 * PI); - - thetaSpan = _angle(( x1Prime - cxPrime) / rx, ( y1Prime - cyPrime) / ry, - (-x1Prime - cxPrime) / rx, (-y1Prime - cyPrime) / ry); - - if (!CounterClockwise && (thetaSpan > 0)) - { - thetaSpan -= 2 * PI; - } - else if (CounterClockwise && (thetaSpan < 0)) - { - thetaSpan += 2 * PI; - } - - thetaSpan = FMODF(thetaSpan, 2 * PI); - - - /******************************************************************* - ** Drawing. - */ - - segs = (int32_t) (CEILF(FABSF(thetaSpan) / (45.0f / 180.0f * PI))); - - theta = thetaSpan / segs; - - ax = coords->lastX - COSF(theta1) * rx; - ay = coords->lastY - SINF(theta1) * ry; - - /* Determine the segment command. */ - segmentCommand = Relative - ? VLC_OP_QUAD_REL - : VLC_OP_QUAD; - - /* Determine the size of the buffer required. */ - bufferSize = (1 + 2 * 2) * SIZEOF(vg_lite_float_t) * segs; - - arcPath = (char *)vg_lite_os_malloc(*offset + bufferSize + last_size); - if (arcPath == NULL) - return VG_LITE_OUT_OF_MEMORY; - memset(arcPath, 0, *offset + bufferSize + last_size); - memcpy(arcPath,(char *)*path_data,*offset); - vg_lite_os_free(*path_data); - - *path_data = arcPath; - - pchar = arcPath + *offset; - pfloat = (vg_lite_float_t *)pchar; - - /* Set initial last point. */ - lastX = coords->lastX; - lastY = coords->lastY; - - while (segs-- > 0) - { - theta1 += theta; - - controlX = ax + COSF(theta1 - (theta / 2.0f)) * rx / COSF(theta / 2.0f); - controlY = ay + SINF(theta1 - (theta / 2.0f)) * ry / COSF(theta / 2.0f); - - anchorX = ax + COSF(theta1) * rx; - anchorY = ay + SINF(theta1) * ry; - - if (RotAngle != 0) - { - x = coords->lastX + cosPhi * (controlX - coords->lastX) - sinPhi * (controlY - coords->lastY); - y = coords->lastY + sinPhi * (controlX - coords->lastX) + cosPhi * (controlY - coords->lastY); - controlX = x; - controlY = y; - - x = coords->lastX + cosPhi * (anchorX - coords->lastX) - sinPhi * (anchorY - coords->lastY); - y = coords->lastY + sinPhi * (anchorX - coords->lastX) + cosPhi * (anchorY - coords->lastY); - anchorX = x; - anchorY = y; - } - - if (segs == 0) - { - /* Use end point directly to avoid accumulated errors. */ - anchorX = endX; - anchorY = endY; - } - - /* Adjust relative coordinates. */ - if (Relative) - { - vg_lite_float_t nextLastX = anchorX; - vg_lite_float_t nextLastY = anchorY; - - controlX -= lastX; - controlY -= lastY; - - anchorX -= lastX; - anchorY -= lastY; - - lastX = nextLastX; - lastY = nextLastY; - } - pchar = (char*)pfloat; - *pchar = segmentCommand ; - pfloat++; - *pfloat++ = controlX; - *pfloat++ = controlY; - *pfloat++ = anchorX; - *pfloat++ = anchorY; - *offset += (1 + 2 * 2) * SIZEOF(vg_lite_float_t); - } - - /* Update the control coordinates. */ - coords->lastX = endX; - coords->lastY = endY; - coords->controlX = endX; - coords->controlY = endY; - - return VG_LITE_SUCCESS; -} - -#if defined(VG_DRIVER_SINGLE_THREAD) -vg_lite_error_t _allocate_command_buffer(uint32_t size) -{ - vg_lite_kernel_allocate_t allocate; - vg_lite_error_t error = VG_LITE_SUCCESS; - - if(size == 0) - return VG_LITE_SUCCESS; - - allocate.bytes = size; - allocate.contiguous = 1; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); - - s_context.context.command_buffer[0] = allocate.memory_handle; - s_context.context.command_buffer_logical[0] = allocate.memory; - s_context.context.command_buffer_physical[0] = allocate.memory_gpu; - - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); - - s_context.context.command_buffer[1] = allocate.memory_handle; - s_context.context.command_buffer_logical[1] = allocate.memory; - s_context.context.command_buffer_physical[1] = allocate.memory_gpu; - - s_context.command_buffer[0] = s_context.context.command_buffer_logical[0]; - s_context.command_buffer[1] = s_context.context.command_buffer_logical[1]; - - s_context.command_buffer_size = size; - s_context.command_offset[0] = 0; - s_context.command_offset[1] = 0; - s_context.command_buffer_current = 0; - - return error; -} - -vg_lite_error_t _free_command_buffer() -{ - vg_lite_kernel_free_t free; - vg_lite_error_t error = VG_LITE_SUCCESS; - - if(s_context.context.command_buffer[0]){ - free.memory_handle = s_context.context.command_buffer[0]; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &free)); - s_context.context.command_buffer[0] = 0; - s_context.context.command_buffer_logical[0] = 0; - } - - if(s_context.context.command_buffer[1]){ - free.memory_handle = s_context.context.command_buffer[1]; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &free)); - s_context.context.command_buffer[1] = 0; - s_context.context.command_buffer_logical[1] = 0; - } - - return error; -} -#else -vg_lite_error_t _allocate_command_buffer(uint32_t size) -{ - vg_lite_tls_t* tls; - vg_lite_kernel_allocate_t allocate; - vg_lite_error_t error = VG_LITE_SUCCESS; - - if(size == 0) - return VG_LITE_SUCCESS; - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - allocate.bytes = size; - allocate.contiguous = 1; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); - - tls->t_context.context.command_buffer[0] = allocate.memory_handle; - tls->t_context.context.command_buffer_logical[0] = allocate.memory; - tls->t_context.context.command_buffer_physical[0] = allocate.memory_gpu; - - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); - - tls->t_context.context.command_buffer[1] = allocate.memory_handle; - tls->t_context.context.command_buffer_logical[1] = allocate.memory; - tls->t_context.context.command_buffer_physical[1] = allocate.memory_gpu; - - tls->t_context.command_buffer[0] = tls->t_context.context.command_buffer_logical[0]; - tls->t_context.command_buffer[1] = tls->t_context.context.command_buffer_logical[1]; - - tls->t_context.command_buffer_size = size; - tls->t_context.command_offset[0] = 0; - tls->t_context.command_offset[1] = 0; - tls->t_context.command_buffer_current = 0; - tls->t_context.start_offset = 0; - tls->t_context.end_offset = 0; - tls->t_context.ts_init = 0; - memset(tls->t_context.ts_record, 0, sizeof(tls->t_context.ts_record)); - - return error; -} - -vg_lite_error_t _free_command_buffer() -{ - vg_lite_tls_t* tls; - vg_lite_kernel_free_t free; - vg_lite_error_t error = VG_LITE_SUCCESS; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - if(tls->t_context.context.command_buffer[0]){ - free.memory_handle = tls->t_context.context.command_buffer[0]; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &free)); - tls->t_context.context.command_buffer[0] = 0; - tls->t_context.context.command_buffer_logical[0] = 0; - } - - if(tls->t_context.context.command_buffer[1]){ - free.memory_handle = tls->t_context.context.command_buffer[1]; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &free)); - tls->t_context.context.command_buffer[1] = 0; - tls->t_context.context.command_buffer_logical[1] = 0; - } - - return error; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -static void ClampColor(FLOATVECTOR4 Source,FLOATVECTOR4 Target,uint8_t Premultiplied) -{ - vg_lite_float_t colorMax; - /* Clamp the alpha channel. */ - Target[3] = CLAMP(Source[3], 0.0f, 1.0f); - - /* Determine the maximum value for the color channels. */ - colorMax = Premultiplied ? Target[3] : 1.0f; - - /* Clamp the color channels. */ - Target[0] = CLAMP(Source[0], 0.0f, colorMax); - Target[1] = CLAMP(Source[1], 0.0f, colorMax); - Target[2] = CLAMP(Source[2], 0.0f, colorMax); -} - -static uint8_t PackColorComponent(vg_lite_float_t value) -{ - /* Compute the rounded normalized value. */ - vg_lite_float_t rounded = value * 255.0f + 0.5f; - - /* Get the integer part. */ - int32_t roundedInt = (int32_t) rounded; - - /* Clamp to 0..1 range. */ - uint8_t clamped = (uint8_t) CLAMP(roundedInt, 0, 255); - - /* Return result. */ - return clamped; -} - -#if !defined(VG_DRIVER_SINGLE_THREAD) -static void command_buffer_copy(void *new_cmd, void *old_cmd, uint32_t start, uint32_t end, uint32_t *cmd_count) -{ - uint32_t i = start,j; - uint32_t *p_new_cmd32,*p_cmd32,*temp; - uint32_t data_count = 0; - - memset(&hw,0,sizeof(vg_lite_hardware_t)); - temp = NULL; - p_new_cmd32 = (uint32_t *)new_cmd; - p_cmd32 = (uint32_t *)old_cmd; - while(i < end) - { - /* data command is 0x40000000 | count, and count = databytes / 8 ,and data command and databytes should align to 8 */ - if((*p_cmd32 & 0xF0000000) == 0x40000000) { - data_count = *p_cmd32 & 0x0FFFFFFF; - data_count++; - p_cmd32 += 2 * data_count; - i += data_count * 8; - /* SEMAPHORE command is 0x10000000 | id,stall command is 0x20000000 | id , call command is is 0x20000000 | count, - and this three command should occupy 8bytes*/ - }else if((*p_cmd32 & 0xF0000000) == 0x20000000 || (*p_cmd32 & 0xF0000000) == 0x10000000 - || (*p_cmd32 & 0xF0000000) == 0x60000000 || (*p_cmd32 & 0xF0000000) == 0x80000000){ - p_cmd32 += 2; - i += 8; - /* register command is 0x30000000 | ((count) << 16) | address, - and the bytes of this command add register count should align to 8 */ - }else if((*p_cmd32 & 0xF0000000) == 0x30000000) { - /* get register data count */ - data_count = (*p_cmd32 & 0x0FFFFFFF) >> 16; - if(data_count == 1) - { - temp = p_cmd32 + 1; - if(hw.hw_states[*p_cmd32 & 0xff].state != *temp || !hw.hw_states[*p_cmd32 & 0xff].init){ - hw.hw_states[*p_cmd32 & 0xff].state = *temp; - hw.hw_states[*p_cmd32 & 0xff].init = 1; - for(j = 0; j < 2; j++) { - *p_new_cmd32 = *p_cmd32; - p_new_cmd32++; - p_cmd32++; - *cmd_count += 4; - i += 4; - } - } - else - { - p_cmd32 += 2; - i += 8; - } - }else{ - /* the bytes of register count add register command */ - data_count++; - if(data_count % 2 != 0) - data_count++; - for(j = 0; j < data_count; j++) { - *p_new_cmd32 = *p_cmd32; - p_new_cmd32++; - p_cmd32++; - *cmd_count += 4; - i += 4; - } - } - } - } -} -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - -static void _memset(void *p, unsigned char value, int size) -{ - int i; - for (i = 0; i < size; i++) { - ((unsigned char*) p)[i] = value; - } -} - -static int has_valid_command_buffer(vg_lite_context_t *context) -{ - if(context == NULL) - return 0; - if(context->command_buffer_current >= CMDBUF_COUNT) - return 0; - if(context->command_buffer[context->command_buffer_current] == NULL) - return 0; - - return 1; -} - -#if !defined(VG_DRIVER_SINGLE_THREAD) -static int has_valid_context_buffer(vg_lite_context_t *context) -{ - if(context == NULL) - return 0; - if(context->context_buffer == NULL) - return 0; - - return 1; -} -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - -#if DUMP_IMAGE -static void dump_img(void * memory, int width, int height, vg_lite_buffer_format_t format) -{ - FILE * fp; - char imgname[255] = {'\0'}; - int i; - static int num = 1; - unsigned int* pt = (unsigned int*) memory; - - sprintf(imgname, "img_pid%d_%d.txt", getpid(), num++); - - fp = fopen(imgname, "w"); - - if (fp == NULL) - printf("error!\n"); - - - switch (format) { - case VG_LITE_INDEX_1: - for(i = 0; i < width * height / 32; ++i) - { - fprintf(fp, "0x%08x\n",pt[i]); - } - break; - - case VG_LITE_INDEX_2: - for(i = 0; i < width * height / 16; ++i) - { - fprintf(fp, "0x%08x\n",pt[i]); - } - break; - - case VG_LITE_INDEX_4: - for(i = 0; i < width * height / 8; ++i) - { - fprintf(fp, "0x%08x\n",pt[i]); - } - break; - - case VG_LITE_INDEX_8: - for(i = 0; i < width * height / 4; ++i) - { - fprintf(fp, "0x%08x\n",pt[i]); - } - break; - - case VG_LITE_RGBA2222: - for(i = 0; i < width * height / 4; ++i) - { - fprintf(fp, "0x%08x\n",pt[i]); - } - break; - - case VG_LITE_RGBA4444: - case VG_LITE_BGRA4444: - case VG_LITE_RGB565: - case VG_LITE_BGR565: - for(i = 0; i < width * height / 2; ++i) - { - fprintf(fp, "0x%08x\n",pt[i]); - } - break; - - case VG_LITE_RGBA8888: - case VG_LITE_BGRA8888: - case VG_LITE_RGBX8888: - case VG_LITE_BGRX8888: - for(i = 0; i < width * height; ++i) - { - fprintf(fp, "0x%08x\n",pt[i]); - } - break; - - default: - break; - } - fclose(fp); - fp = NULL; -} -#endif - -/* Convert VGLite data format to HW value. */ -static uint32_t convert_path_format(vg_lite_format_t format) -{ - switch (format) { - case VG_LITE_S8: - return 0; - - case VG_LITE_S16: - return 0x100000; - - case VG_LITE_S32: - return 0x200000; - - case VG_LITE_FP32: - return 0x300000; - - default: - return 0; - } -} - -/* Convert VGLite quality enums to HW values. */ -static uint32_t convert_path_quality(vg_lite_quality_t quality) -{ - switch (quality) { - case VG_LITE_HIGH: - return 0x3; - - case VG_LITE_UPPER: - return 0x2; - - case VG_LITE_MEDIUM: - return 0x1; - - default: - return 0x0; - } -} - -static uint32_t rgb_to_l(uint32_t color) -{ - uint32_t l = (uint32_t)((0.2126f * (vg_lite_float_t)(color & 0xFF)) + - (0.7152f * (vg_lite_float_t)((color >> 8) & 0xFF)) + - (0.0722f * (vg_lite_float_t)((color >> 16) & 0xFF))); - return l | (l << 24); -} - -/* Get the bpp information of a color format. */ -static void get_format_bytes(vg_lite_buffer_format_t format, - uint32_t *mul, - uint32_t *div, - uint32_t *bytes_align) -{ - *mul = *div = 1; - *bytes_align = 4; - switch (format) { - case VG_LITE_L8: - case VG_LITE_A8: - *bytes_align = 16; - break; - - case VG_LITE_A4: - *div = 2; - *bytes_align = 8; - break; - - case VG_LITE_ABGR1555: - case VG_LITE_ARGB1555: - case VG_LITE_BGRA5551: - case VG_LITE_RGBA5551: - case VG_LITE_RGBA4444: - case VG_LITE_BGRA4444: - case VG_LITE_ABGR4444: - case VG_LITE_ARGB4444: - case VG_LITE_RGB565: - case VG_LITE_BGR565: - case VG_LITE_YUYV: - case VG_LITE_YUY2: - case VG_LITE_YUY2_TILED: - /* AYUY2 buffer memory = YUY2 + alpha. */ - case VG_LITE_AYUY2: - case VG_LITE_AYUY2_TILED: - *mul = 2; - *bytes_align = 32; - break; - - case VG_LITE_RGBA8888: - case VG_LITE_BGRA8888: - case VG_LITE_ABGR8888: - case VG_LITE_ARGB8888: - case VG_LITE_RGBX8888: - case VG_LITE_BGRX8888: - case VG_LITE_XBGR8888: - case VG_LITE_XRGB8888: - *mul = 4; - *bytes_align = 64; - break; - - case VG_LITE_NV12: - case VG_LITE_NV12_TILED: - *mul = 3; - *bytes_align = 32; - break; - - case VG_LITE_ANV12: - case VG_LITE_ANV12_TILED: - *mul = 4; - *bytes_align = 64; - break; - - case VG_LITE_INDEX_1: - *div = 8; - *bytes_align = 8; - break; - - case VG_LITE_INDEX_2: - *div = 4; - *bytes_align = 8; - break; - - case VG_LITE_INDEX_4: - *div = 2; - *bytes_align = 8; - break; - - case VG_LITE_INDEX_8: - *bytes_align = 16; - break; - - case VG_LITE_RGBA2222: - case VG_LITE_BGRA2222: - case VG_LITE_ABGR2222: - case VG_LITE_ARGB2222: - *mul = 1; - *bytes_align = 8; - break; - - default: - break; - } -} - -/* Convert VGLite target color format to HW value. */ -static uint32_t convert_target_format(vg_lite_buffer_format_t format, vg_lite_capabilities_t caps) -{ - switch (format) { - case VG_LITE_A8: - return 0x0; - - case VG_LITE_L8: - return 0x6; - - case VG_LITE_ABGR4444: - return 0x14; - - case VG_LITE_ARGB4444: - return 0x34; - - case VG_LITE_RGBA4444: - return 0x24; - - case VG_LITE_BGRA4444: - return 0x4; - - case VG_LITE_RGB565: - return 0x21; - - case VG_LITE_BGR565: - return 0x1; - - case VG_LITE_ABGR8888: - return 0x13; - - case VG_LITE_ARGB8888: - return 0x33; - - case VG_LITE_RGBA8888: - return 0x23; - - case VG_LITE_BGRA8888: - return 0x3; - - case VG_LITE_RGBX8888: - return 0x22; - - case VG_LITE_BGRX8888: - return 0x2; - - case VG_LITE_XBGR8888: - return 0x12; - - case VG_LITE_XRGB8888: - return 0x32; - - case VG_LITE_ABGR1555: - return 0x15; - - case VG_LITE_RGBA5551: - return 0x25; - - case VG_LITE_ARGB1555: - return 0x35; - - case VG_LITE_BGRA5551: - return 0x5; - - case VG_LITE_YUYV: - case VG_LITE_YUY2: - case VG_LITE_YUY2_TILED: - return 0x8; - - case VG_LITE_NV12: - case VG_LITE_NV12_TILED: - return 0xB; - - case VG_LITE_ANV12: - case VG_LITE_ANV12_TILED: - return 0xE; - - case VG_LITE_BGRA2222: - return 0x7; - - case VG_LITE_RGBA2222: - return 0x27; - - case VG_LITE_ABGR2222: - return 0x17; - - case VG_LITE_ARGB2222: - return 0x37; - - case VG_LITE_AYUY2: - case VG_LITE_AYUY2_TILED: - default: - return 0xF; - } -} - -/* determine source IM is aligned by specified bytes */ -static vg_lite_error_t _check_source_aligned(vg_lite_buffer_format_t format,uint32_t stride) -{ - switch (format) { - case VG_LITE_A4: - case VG_LITE_INDEX_1: - case VG_LITE_INDEX_2: - case VG_LITE_INDEX_4: - FORMAT_ALIGNMENT(stride,8); - break; - - case VG_LITE_L8: - case VG_LITE_A8: - case VG_LITE_INDEX_8: - case VG_LITE_RGBA2222: - case VG_LITE_BGRA2222: - case VG_LITE_ABGR2222: - case VG_LITE_ARGB2222: - FORMAT_ALIGNMENT(stride,16); - break; - - case VG_LITE_RGBA4444: - case VG_LITE_BGRA4444: - case VG_LITE_ABGR4444: - case VG_LITE_ARGB4444: - case VG_LITE_RGB565: - case VG_LITE_BGR565: - case VG_LITE_BGRA5551: - case VG_LITE_RGBA5551: - case VG_LITE_ABGR1555: - case VG_LITE_ARGB1555: - case VG_LITE_YUYV: - case VG_LITE_YUY2: - case VG_LITE_NV12: - case VG_LITE_YV12: - case VG_LITE_YV24: - case VG_LITE_YV16: - case VG_LITE_NV16: - FORMAT_ALIGNMENT(stride,32); - break; - - case VG_LITE_RGBA8888: - case VG_LITE_BGRA8888: - case VG_LITE_ABGR8888: - case VG_LITE_ARGB8888: - case VG_LITE_RGBX8888: - case VG_LITE_BGRX8888: - case VG_LITE_XBGR8888: - case VG_LITE_XRGB8888: - FORMAT_ALIGNMENT(stride,64); - break; - - default: - return VG_LITE_SUCCESS; - } -} - -/* Convert VGLite source color format to HW values. */ -static uint32_t convert_source_format(vg_lite_buffer_format_t format) -{ - switch (format) { - case VG_LITE_L8: - return 0x0; - - case VG_LITE_A4: - return 0x1; - - case VG_LITE_A8: - return 0x2; - - case VG_LITE_RGBA4444: - return 0x23; - - case VG_LITE_BGRA4444: - return 0x3; - - case VG_LITE_ABGR4444: - return 0x13; - - case VG_LITE_ARGB4444: - return 0x33; - - case VG_LITE_RGB565: - return 0x25; - - case VG_LITE_BGR565: - return 0x5; - - case VG_LITE_RGBA8888: - return 0x27; - - case VG_LITE_BGRA8888: - return 0x7; - - case VG_LITE_ABGR8888: - return 0x17; - - case VG_LITE_ARGB8888: - return 0x37; - - case VG_LITE_RGBX8888: - return 0x26; - - case VG_LITE_BGRX8888: - return 0x6; - - case VG_LITE_XBGR8888: - return 0x16; - - case VG_LITE_XRGB8888: - return 0x36; - - case VG_LITE_BGRA5551: - return 0x4; - - case VG_LITE_RGBA5551: - return 0x24; - - case VG_LITE_ABGR1555: - return 0x14; - - case VG_LITE_ARGB1555: - return 0x34; - - case VG_LITE_YUYV: - return 0x8; - - case VG_LITE_YUY2: - case VG_LITE_YUY2_TILED: - return 0x8; - - case VG_LITE_NV12: - case VG_LITE_NV12_TILED: - return 0xB; - - case VG_LITE_ANV12: - case VG_LITE_ANV12_TILED: - return 0xE; - - case VG_LITE_YV12: - return 0x9; - - case VG_LITE_YV24: - return 0xD; - - case VG_LITE_YV16: - return 0xC; - - case VG_LITE_NV16: - return 0xA; - - case VG_LITE_AYUY2: - case VG_LITE_AYUY2_TILED: - default: - return 0xF; - - case VG_LITE_INDEX_1: - return 0x200; - - case VG_LITE_INDEX_2: - return 0x400; - - case VG_LITE_INDEX_4: - return 0x600; - - case VG_LITE_INDEX_8: - return 0x800; - - case VG_LITE_RGBA2222: - return 0xA20; - - case VG_LITE_BGRA2222: - return 0xA00; - - case VG_LITE_ABGR2222: - return 0xA10; - - case VG_LITE_ARGB2222: - return 0xA30; - } -} - -/* Convert VGLite blend modes to HW values. */ -static uint32_t convert_blend(vg_lite_blend_t blend) -{ - switch (blend) { - case VG_LITE_BLEND_SRC_OVER: - return 0x00000100; - - case VG_LITE_BLEND_DST_OVER: - return 0x00000200; - - case VG_LITE_BLEND_SRC_IN: - return 0x00000300; - - case VG_LITE_BLEND_DST_IN: - return 0x00000400; - - case VG_LITE_BLEND_SCREEN: - return 0x00000600; - - case VG_LITE_BLEND_MULTIPLY: - return 0x00000500; - - case VG_LITE_BLEND_ADDITIVE: - return 0x00000900; - - case VG_LITE_BLEND_SUBTRACT: - return 0x00000A00; - - default: - return 0; - } -} - -/* Convert VGLite uv swizzle enums to HW values. */ -static uint32_t convert_uv_swizzle(vg_lite_swizzle_t swizzle) -{ - switch (swizzle) { - case VG_LITE_SWIZZLE_UV: - return 0x00000040; - break; - - case VG_LITE_SWIZZLE_VU: - return 0x00000050; - - default: - return 0; - break; - } -} - -/* Convert VGLite yuv standard enums to HW values. */ -static uint32_t convert_yuv2rgb(vg_lite_yuv2rgb_t yuv) -{ - switch (yuv) { - case VG_LITE_YUV601: - return 0; - break; - - case VG_LITE_YUV709: - return 0x00008000; - - default: - return 0; - break; - } -} - -/* Initialize the feature table of a chip. */ -#if defined(VG_DRIVER_SINGLE_THREAD) -static vg_lite_error_t fill_feature_table(uint32_t * feature) -{ - uint16_t size = sizeof(VGFeatureInfos) / sizeof(VGFeatureInfos[0]); - uint16_t i; - uint32_t cid = 0; - - /* Clear all bits. */ - _memset(feature, 0, sizeof(uint32_t) * gcFEATURE_COUNT); - vg_lite_get_product_info(NULL,&s_context.chip_id,&s_context.chip_rev); - if(s_context.chip_id == GPU_CHIP_ID_GC355) - s_context.premultiply_enabled = 1; - vg_lite_get_register(0x30, &cid); - - for(i = 0;i < size; i++){ - if ((VGFeatureInfos[i].chip_id == s_context.chip_id) - && (VGFeatureInfos[i].chip_version == s_context.chip_rev) - && (VGFeatureInfos[i].cid == cid) - ) - { - feature[gcFEATURE_BIT_VG_IM_INDEX_FORMAT] = VGFeatureInfos[i].vg_im_index_format; - feature[gcFEATURE_BIT_VG_PE_PREMULTIPLY] = VGFeatureInfos[i].vg_pe_premultiply; - feature[gcFEATURE_BIT_VG_BORDER_CULLING] = VGFeatureInfos[i].vg_border_culling; - feature[gcFEATURE_BIT_VG_RGBA2_FORMAT] = VGFeatureInfos[i].vg_rgba2_format; - feature[gcFEATURE_BIT_VG_QUALITY_8X] = VGFeatureInfos[i].vg_quality_8x; - feature[gcFEATURE_BIT_VG_RADIAL_GRADIENT] = VGFeatureInfos[i].vg_radial_gradient; - feature[gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT] = VGFeatureInfos[i].vg_linear_gradient_ext; - feature[gcFEATURE_BIT_VG_DITHER] = VGFeatureInfos[i].vg_dither; - feature[gcFEATURE_BIT_VG_COLOR_KEY] = VGFeatureInfos[i].vg_color_key; - break; - } - } - - if(i == size) { - return VG_LITE_INVALID_ARGUMENT; - } - s_ftable.ftflag = 1; - - return VG_LITE_SUCCESS; -} -#else -static vg_lite_error_t fill_feature_table(uint32_t * feature) -{ - uint16_t size = sizeof(VGFeatureInfos) / sizeof(VGFeatureInfos[0]); - uint16_t i; - uint32_t cid = 0; - vg_lite_tls_t* tls; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - /* Clear all bits. */ - _memset(feature, 0, sizeof(uint32_t) * gcFEATURE_COUNT); - vg_lite_get_product_info(NULL,&tls->t_context.chip_id,&tls->t_context.chip_rev); - if(tls->t_context.chip_id == GPU_CHIP_ID_GC355) - tls->t_context.premultiply_enabled = 1; - vg_lite_get_register(0x30, &cid); - - for(i = 0;i < size; i++){ - if ((VGFeatureInfos[i].chip_id == tls->t_context.chip_id) - && (VGFeatureInfos[i].chip_version == tls->t_context.chip_rev) - && (VGFeatureInfos[i].cid == cid) - ) - { - feature[gcFEATURE_BIT_VG_IM_INDEX_FORMAT] = VGFeatureInfos[i].vg_im_index_format; - feature[gcFEATURE_BIT_VG_PE_PREMULTIPLY] = VGFeatureInfos[i].vg_pe_premultiply; - feature[gcFEATURE_BIT_VG_BORDER_CULLING] = VGFeatureInfos[i].vg_border_culling; - feature[gcFEATURE_BIT_VG_RGBA2_FORMAT] = VGFeatureInfos[i].vg_rgba2_format; - feature[gcFEATURE_BIT_VG_QUALITY_8X] = VGFeatureInfos[i].vg_quality_8x; - feature[gcFEATURE_BIT_VG_RADIAL_GRADIENT] = VGFeatureInfos[i].vg_radial_gradient; - feature[gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT] = VGFeatureInfos[i].vg_linear_gradient_ext; - feature[gcFEATURE_BIT_VG_DITHER] = VGFeatureInfos[i].vg_dither; - feature[gcFEATURE_BIT_VG_COLOR_KEY] = VGFeatureInfos[i].vg_color_key; - break; - } - } - - if(i == size) { - return VG_LITE_INVALID_ARGUMENT; - } - tls->t_context.s_ftable.ftflag = 1; - - return VG_LITE_SUCCESS; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -#if !defined(VG_DRIVER_SINGLE_THREAD) -static vg_lite_error_t flush(vg_lite_context_t *context); -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ -static vg_lite_error_t submit(vg_lite_context_t * context); -#if defined(VG_DRIVER_SINGLE_THREAD) -static vg_lite_error_t stall(vg_lite_context_t * context, uint32_t time_ms, uint32_t mask); -#else -static vg_lite_error_t stall(vg_lite_context_t * context, uint32_t time_ms); -#endif /* VG_DRIVER_SINGLE_THREAD */ - -#if !defined(VG_DRIVER_SINGLE_THREAD) -/* Push a state array into context buffer. */ -static vg_lite_error_t push_states_to_context(vg_lite_context_t * context, uint32_t address, uint32_t count, uint32_t *data) -{ - uint32_t i, command_id; - vg_lite_error_t error; - if (!has_valid_context_buffer(context)) - return VG_LITE_NO_CONTEXT; - - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - /* Reserve enough space in the context buffer for flush and submit */ - if (context->context_buffer_offset[command_id] + 8 >= context->context_buffer_size) { - return VG_LITE_OUT_OF_RESOURCES; - } - - ((uint32_t *) (context->context_buffer[command_id] + context->context_buffer_offset[command_id]))[0] = VG_LITE_STATES(count, address); - - for (i = 0; i < count; i++) { - ((uint32_t *) (context->context_buffer[command_id] + context->context_buffer_offset[command_id]))[1 + i] = data[i]; - } - if (i%2 == 0) { - ((uint32_t *) (context->context_buffer[command_id] + context->context_buffer_offset[command_id]))[1 + i] = VG_LITE_NOP(); - } - - context->context_buffer_offset[command_id] += VG_LITE_ALIGN(count + 1, 2) * 4; - - return VG_LITE_SUCCESS; -} - -static vg_lite_error_t update_context_buffer() -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_kernel_context_switch_t check; - vg_lite_tls_t* tls; - uint32_t command_id; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - command_id = CMDBUF_INDEX(tls->t_context); - check.context =(uint32_t)&tls->t_context.context; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_QUERY_CONTEXT_SWITCH, &check)); - /* if context have been switched and this task need use index. */ - if(check.isContextSwitched && tls->t_context.index_format) - { - uint32_t clut_addr[4]={0x0A98,0x0A9C,0x0AA0,0x0B00}; - uint32_t clut_count[4]={2,4,16,256}; - - for(int i = 0; i < 4; i++) - { - /* check which index colors would be use in this task. */ - if(tls->t_context.colors[i] && tls->t_context.clut_used[i]){ - VG_LITE_RETURN_ERROR(push_states_to_context(&tls->t_context, clut_addr[i], clut_count[i], tls->t_context.colors[i])); - tls->t_context.clut_used[i] = 0; - } - } - tls->t_context.index_format = 0; - } - - /* Set tessellation buffer states */ - if(check.isContextSwitched && tls->t_context.ts_init && !tls->t_context.ts_init_used && tls->t_context.ts_init_use){ - /* Reserve enough space in the context buffer for flush and submit */ - if (tls->t_context.context_buffer_offset[command_id] + 80 >= tls->t_context.context_buffer_size) { - return VG_LITE_OUT_OF_RESOURCES; - } - memcpy(tls->t_context.context_buffer[command_id] + tls->t_context.context_buffer_offset[command_id], tls->t_context.ts_record, 80); - tls->t_context.ts_init = 0; - tls->t_context.ts_init_used = 0; - tls->t_context.ts_init_use = 0; - tls->t_context.context_buffer_offset[command_id] += 80; - } - - if(tls->t_context.context_buffer_offset[command_id]){ - ((uint32_t *) (tls->t_context.context_buffer[command_id] + tls->t_context.context_buffer_offset[command_id]))[0] = VG_LITE_RETURN(); - ((uint32_t *) (tls->t_context.context_buffer[command_id] + tls->t_context.context_buffer_offset[command_id]))[1] = 0; - tls->t_context.context_buffer_offset[command_id] += 8; - ((uint32_t *) CMDBUF_BUFFER(tls->t_context))[0] = VG_LITE_CALL((tls->t_context.context_buffer_offset[command_id] + 7) / 8); - ((uint32_t *) CMDBUF_BUFFER(tls->t_context))[1] = tls->t_context.context.context_buffer_physical[command_id]; - tls->t_context.context_buffer_offset[command_id] = 0; - } - - return error; -} -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - -#if defined(VG_DRIVER_SINGLE_THREAD) -/* Push a state array into current command buffer. */ -static vg_lite_error_t push_states(vg_lite_context_t * context, uint32_t address, uint32_t count, uint32_t *data) -{ - uint32_t i; - vg_lite_error_t error; - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - if (CMDBUF_OFFSET(*context) + 8 + VG_LITE_ALIGN(count + 1, 2) * 4 >= CMDBUF_SIZE(*context)) { - VG_LITE_RETURN_ERROR(submit(context)); - VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); - } - - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATES(count, address); - - for (i = 0; i < count; i++) { - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1 + i] = data[i]; - } - if (i%2 == 0) { - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1 + i] = VG_LITE_NOP(); - } - - CMDBUF_OFFSET(*context) += VG_LITE_ALIGN(count + 1, 2) * 4; - - return VG_LITE_SUCCESS; -} - -/* Push a single state command into the current command buffer. */ -static vg_lite_error_t push_state(vg_lite_context_t * context, uint32_t address, uint32_t data) -{ - vg_lite_error_t error; - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - if (CMDBUF_OFFSET(*context) + 16 >= CMDBUF_SIZE(*context)) { - VG_LITE_RETURN_ERROR(submit(context)); - VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); - } - - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATE(address); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = data; - - CMDBUF_OFFSET(*context) += 8; - - return VG_LITE_SUCCESS; -} - -/* Push a single state command with given address. */ -static vg_lite_error_t push_state_ptr(vg_lite_context_t * context, uint32_t address, void * data_ptr) -{ - vg_lite_error_t error; - uint32_t data = *(uint32_t *) data_ptr; - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - if (CMDBUF_OFFSET(*context) + 16 >= CMDBUF_SIZE(*context)) { - VG_LITE_RETURN_ERROR(submit(context)); - VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); - } - - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATE(address); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = data; - - CMDBUF_OFFSET(*context) += 8; - - return VG_LITE_SUCCESS; -} - -/* Push a "call" command into the current command buffer. */ -static vg_lite_error_t push_call(vg_lite_context_t * context, uint32_t address, uint32_t bytes) -{ - vg_lite_error_t error; - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - if (CMDBUF_OFFSET(*context) + 16 >= CMDBUF_SIZE(*context)) { - VG_LITE_RETURN_ERROR(submit(context)); - VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); - } - - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_CALL((bytes + 7) / 8); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = address; - - CMDBUF_OFFSET(*context) += 8; - - return VG_LITE_SUCCESS; -} - -/* Push a rectangle command into the current command buffer. */ -static vg_lite_error_t push_rectangle(vg_lite_context_t * context, int x, int y, int width, int height) -{ - vg_lite_error_t error; - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - if (CMDBUF_OFFSET(*context) + 16 >= CMDBUF_SIZE(*context)) { - VG_LITE_RETURN_ERROR(submit(context)); - VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); - } - - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_DATA(1); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; - ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[4] = (uint16_t)x; - ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[5] = (uint16_t)y; - ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[6] = (uint16_t)width; - ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[7] = (uint16_t)height; - - CMDBUF_OFFSET(*context) += 16; - - return VG_LITE_SUCCESS; -} - -/* Push a data array into the current command buffer. */ -static vg_lite_error_t push_data(vg_lite_context_t * context, int size, void * data) -{ - vg_lite_error_t error; - int bytes = VG_LITE_ALIGN(size, 8); - - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - if (CMDBUF_OFFSET(*context) + 16 + bytes >= CMDBUF_SIZE(*context)) { - VG_LITE_RETURN_ERROR(submit(context)); - VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); - } - - ((uint64_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(bytes / 8)] = 0; - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_DATA(bytes / 8); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; - memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context) + 8, data, size); - - CMDBUF_OFFSET(*context) += 8 + bytes; - - return VG_LITE_SUCCESS; -} - -/* Push a "stall" command into the current command buffer. */ -static vg_lite_error_t push_stall(vg_lite_context_t * context, uint32_t module) -{ - vg_lite_error_t error; - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - if (CMDBUF_OFFSET(*context) + 16 >= CMDBUF_SIZE(*context)) { - VG_LITE_RETURN_ERROR(submit(context)); - VG_LITE_RETURN_ERROR(stall(context, 0, (uint32_t)~0)); - } - - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_SEMAPHORE(module); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[2] = VG_LITE_STALL(module); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[3] = 0; - - CMDBUF_OFFSET(*context) += 16; - - return VG_LITE_SUCCESS; -} - -/* Submit the current command buffer to HW and reset the current command buffer offset. */ -static vg_lite_error_t submit(vg_lite_context_t *context) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_kernel_submit_t submit; - - /* Check if there is a valid context and an allocated command buffer. */ - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - /* Check if there is anything to submit. */ - if (CMDBUF_OFFSET(*context) == 0) - return VG_LITE_INVALID_ARGUMENT; - - /* Check if there is enough space in the command buffer for the END. */ - if (CMDBUF_OFFSET(*context) + 8 > CMDBUF_SIZE(*context)) { - /* Reset command buffer offset. */ - CMDBUF_OFFSET(*context) = 0; - return VG_LITE_OUT_OF_RESOURCES; - } - - /* Append END command into the command buffer. */ - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_END(EVENT_END); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; - -#if DUMP_COMMAND - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], 0); - - fprintf(fp, "Command buffer addr is : %p,\n", CMDBUF_BUFFER(*context)); - fprintf(fp, "Command buffer offset is : %d,\n", CMDBUF_OFFSET(*context) + 8); - - fclose(fp); - fp = NULL; -#endif - - CMDBUF_OFFSET(*context) += 8; - - /* Submit the command buffer. */ - submit.context = &context->context; - submit.commands = CMDBUF_BUFFER(*context); - submit.command_size = CMDBUF_OFFSET(*context); - submit.command_id = CMDBUF_INDEX(*context); - - /* Wait if GPU has not completed previous CMD buffer */ - if (submit_flag) - { - VG_LITE_RETURN_ERROR(stall(&s_context, 0, (uint32_t)~0)); - } - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_SUBMIT, &submit)); - - submit_flag = 1; - - vglitemDUMP_BUFFER("command", (unsigned int)CMDBUF_BUFFER(*context), - submit.context->command_buffer_logical[CMDBUF_INDEX(*context)], 0, submit.command_size); - vglitemDUMP("@[commit]"); - - /* Reset command buffer. */ - CMDBUF_OFFSET(*context) = 0; - - return error; -} - -/* Wait for the HW to finish the current execution. */ -static vg_lite_error_t stall(vg_lite_context_t * context, uint32_t time_ms, uint32_t mask) -{ - vg_lite_error_t error; - vg_lite_kernel_wait_t wait; - - vglitemDUMP("@[stall]"); - /* Wait until GPU is ready. */ - wait.context = &context->context; - wait.timeout_ms = time_ms > 0 ? time_ms : VG_LITE_INFINITE; - wait.event_mask = mask; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_WAIT, &wait)); - submit_flag = 0; - return VG_LITE_SUCCESS; -} - -#else -/* Push a state array into current command buffer. */ -static vg_lite_error_t push_states(vg_lite_context_t * context, uint32_t address, uint32_t count, uint32_t *data) -{ - uint32_t i, command_id, index; - vg_lite_error_t error; - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - /* Reserve enough space in the command buffer for flush and submit */ - if (CMDBUF_OFFSET(*context) + 40 + VG_LITE_ALIGN(count + 1, 2) * 4 >= CMDBUF_SIZE(*context)) { - uint32_t cmd_count = 0,start_offset = 0; - context->end_offset = CMDBUF_OFFSET(*context); - start_offset = context->start_offset; - VG_LITE_RETURN_ERROR(flush(context)); - VG_LITE_RETURN_ERROR(submit(context)); - CMDBUF_SWAP(*context); - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - RESERVE_BYTES_IN_CMDBUF(*context); - - if(context->ts_init){ - memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); - CMDBUF_OFFSET(*context) += 80; - context->ts_init_used = 1; - } - - /* update start offset */ - context->start_offset = CMDBUF_OFFSET(*context); - - index = (command_id? 0 : 1); - command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), - start_offset, context->end_offset, &cmd_count); - CMDBUF_OFFSET(*context) += cmd_count; - } - - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATES(count, address); - - for (i = 0; i < count; i++) { - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1 + i] = data[i]; - } - if (i%2 == 0) { - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1 + i] = VG_LITE_NOP(); - } - -#if DUMP_COMMAND - { - uint32_t loops; - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, ", - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0]); - - for (loops = 0; loops < count / 2; loops++) { - fprintf(fp, "0x%08x,\nCommand buffer: 0x%08x, ", - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(loops + 1) * 2 - 1], - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(loops + 1) * 2]); - } - - fprintf(fp, "0x%08x,\n", - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(loops + 1) * 2 - 1]); - - fclose(fp); - fp = NULL; - } -#endif - - CMDBUF_OFFSET(*context) += VG_LITE_ALIGN(count + 1, 2) * 4; - - return VG_LITE_SUCCESS; -} - -/* Push a single state command into the current command buffer. */ -static vg_lite_error_t push_state(vg_lite_context_t * context, uint32_t address, uint32_t data) -{ - vg_lite_error_t error; - uint32_t command_id, index; - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - /* Reserve enough space in the command buffer for flush and submit */ - if (CMDBUF_OFFSET(*context) + 56 >= CMDBUF_SIZE(*context)) { - uint32_t cmd_count = 0,start_offset = 0; - context->end_offset = CMDBUF_OFFSET(*context); - start_offset = context->start_offset; - VG_LITE_RETURN_ERROR(flush(context)); - VG_LITE_RETURN_ERROR(submit(context)); - CMDBUF_SWAP(*context); - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - RESERVE_BYTES_IN_CMDBUF(*context); - - if(context->ts_init){ - memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); - CMDBUF_OFFSET(*context) += 80; - context->ts_init_used = 1; - } - - /* update start offset */ - context->start_offset = CMDBUF_OFFSET(*context); - - index = (command_id? 0 : 1); - command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), - start_offset, context->end_offset, &cmd_count); - CMDBUF_OFFSET(*context) += cmd_count; - } - - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATE(address); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = data; - -#if DUMP_COMMAND - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1]); - - fclose(fp); - fp = NULL; -#endif - - CMDBUF_OFFSET(*context) += 8; - - return VG_LITE_SUCCESS; -} - -/* Push a single state command with given address. */ -static vg_lite_error_t push_state_ptr(vg_lite_context_t * context, uint32_t address, void * data_ptr) -{ - vg_lite_error_t error; - uint32_t command_id, index; - uint32_t data = *(uint32_t *) data_ptr; - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - /* Reserve enough space in the command buffer for flush and submit */ - if (CMDBUF_OFFSET(*context) + 56 >= CMDBUF_SIZE(*context)) { - uint32_t cmd_count = 0,start_offset = 0; - context->end_offset = CMDBUF_OFFSET(*context); - start_offset = context->start_offset; - VG_LITE_RETURN_ERROR(flush(context)); - VG_LITE_RETURN_ERROR(submit(context)); - CMDBUF_SWAP(*context); - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - RESERVE_BYTES_IN_CMDBUF(*context); - - if(context->ts_init){ - memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); - CMDBUF_OFFSET(*context) += 80; - context->ts_init_used = 1; - } - - /* update start offset */ - context->start_offset = CMDBUF_OFFSET(*context); - - index = (command_id? 0 : 1); - command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), - start_offset, context->end_offset, &cmd_count); - CMDBUF_OFFSET(*context) += cmd_count; - } - - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATE(address); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = data; - -#if DUMP_COMMAND - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1]); - - fclose(fp); - fp = NULL; -#endif - - CMDBUF_OFFSET(*context) += 8; - - return VG_LITE_SUCCESS; -} - -/* Push a "call" command into the current command buffer. */ -static vg_lite_error_t push_call(vg_lite_context_t * context, uint32_t address, uint32_t bytes) -{ - vg_lite_error_t error; - uint32_t command_id, index; - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - /* Reserve enough space in the command buffer for flush and submit */ - if (CMDBUF_OFFSET(*context) + 56 >= CMDBUF_SIZE(*context)) { - uint32_t cmd_count = 0,start_offset = 0; - context->end_offset = CMDBUF_OFFSET(*context); - start_offset = context->start_offset; - VG_LITE_RETURN_ERROR(flush(context)); - VG_LITE_RETURN_ERROR(submit(context)); - CMDBUF_SWAP(*context); - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - RESERVE_BYTES_IN_CMDBUF(*context); - - if(context->ts_init){ - memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); - CMDBUF_OFFSET(*context) += 80; - context->ts_init_used = 1; - } - - /* update start offset */ - context->start_offset = CMDBUF_OFFSET(*context); - - index = (command_id? 0 : 1); - command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), - start_offset, context->end_offset, &cmd_count); - CMDBUF_OFFSET(*context) += cmd_count; - } - - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_CALL((bytes + 7) / 8); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = address; - -#if DUMP_COMMAND - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1]); - - fclose(fp); - fp = NULL; -#endif - - CMDBUF_OFFSET(*context) += 8; - - return VG_LITE_SUCCESS; -} - -/* Push a rectangle command into the current command buffer. */ -static vg_lite_error_t push_rectangle(vg_lite_context_t * context, int x, int y, int width, int height) -{ - vg_lite_error_t error; - uint32_t command_id, index; - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - /* Reserve enough space in the command buffer for flush and submit */ - if (CMDBUF_OFFSET(*context) + 56 >= CMDBUF_SIZE(*context)) { - uint32_t cmd_count = 0,start_offset = 0; - context->end_offset = CMDBUF_OFFSET(*context); - start_offset = context->start_offset; - VG_LITE_RETURN_ERROR(flush(context)); - VG_LITE_RETURN_ERROR(submit(context)); - CMDBUF_SWAP(*context); - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - RESERVE_BYTES_IN_CMDBUF(*context); - - if(context->ts_init){ - memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); - CMDBUF_OFFSET(*context) += 80; - context->ts_init_used = 1; - } - - /* update start offset */ - context->start_offset = CMDBUF_OFFSET(*context); - - index = (command_id? 0 : 1); - command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), - start_offset, context->end_offset, &cmd_count); - CMDBUF_OFFSET(*context) += cmd_count; - } - - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_DATA(1); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; - ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[4] = (uint16_t)x; - ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[5] = (uint16_t)y; - ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[6] = (uint16_t)width; - ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[7] = (uint16_t)height; - -#if DUMP_COMMAND - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], 0); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[5] << 16 | - ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[4], - ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[7] << 16 | - ((uint16_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[6]); - - fclose(fp); - fp = NULL; -#endif - - CMDBUF_OFFSET(*context) += 16; - - return VG_LITE_SUCCESS; -} - -/* Push a data array into the current command buffer. */ -static vg_lite_error_t push_data(vg_lite_context_t * context, int size, void * data) -{ - vg_lite_error_t error; - uint32_t command_id, index; - int bytes = VG_LITE_ALIGN(size, 8); - - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - /* Reserve enough space in the command buffer for flush and submit */ - if (CMDBUF_OFFSET(*context) + 48 + bytes >= CMDBUF_SIZE(*context)) { - uint32_t cmd_count = 0,start_offset = 0; - context->end_offset = CMDBUF_OFFSET(*context); - start_offset = context->start_offset; - VG_LITE_RETURN_ERROR(flush(context)); - VG_LITE_RETURN_ERROR(submit(context)); - CMDBUF_SWAP(*context); - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - RESERVE_BYTES_IN_CMDBUF(*context); - - if(context->ts_init){ - memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); - CMDBUF_OFFSET(*context) += 80; - context->ts_init_used = 1; - } - - /* update start offset */ - context->start_offset = CMDBUF_OFFSET(*context); - index = (command_id? 0 : 1); - command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), - start_offset, context->end_offset, &cmd_count); - CMDBUF_OFFSET(*context) += cmd_count; - } - - ((uint64_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(bytes / 8)] = 0; - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_DATA(bytes / 8); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; - memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context) + 8, data, size); - -#if DUMP_COMMAND - { - int loops; - - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], 0); - for (loops = 0; loops < bytes / 8; loops++) { - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(loops + 1) * 2], - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[(loops + 1) * 2 + 1]); - } - - fclose(fp); - fp = NULL; - } -#endif - - CMDBUF_OFFSET(*context) += 8 + bytes; - - return VG_LITE_SUCCESS; -} - -/* Push a "stall" command into the current command buffer. */ -static vg_lite_error_t push_stall(vg_lite_context_t * context, uint32_t module) -{ - vg_lite_error_t error; - uint32_t command_id, index; - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - /* Reserve enough space in the command buffer for flush and submit */ - if (CMDBUF_OFFSET(*context) + 56 >= CMDBUF_SIZE(*context)) { - uint32_t cmd_count = 0,start_offset = 0; - context->end_offset = CMDBUF_OFFSET(*context); - start_offset = context->start_offset; - VG_LITE_RETURN_ERROR(flush(context)); - VG_LITE_RETURN_ERROR(submit(context)); - CMDBUF_SWAP(*context); - command_id = CMDBUF_INDEX(*context); - if(CMDBUF_IN_QUEUE(&context->context, command_id)) - VG_LITE_RETURN_ERROR(stall(context, 0)); - - RESERVE_BYTES_IN_CMDBUF(*context); - - if(context->ts_init){ - memcpy(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context), context->ts_record, 80); - CMDBUF_OFFSET(*context) += 80; - context->ts_init_used = 1; - } - - /* update start offset */ - context->start_offset = CMDBUF_OFFSET(*context); - - index = (command_id? 0 : 1); - command_buffer_copy((void *)(CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)), (void *)(context->command_buffer[index] + start_offset), - start_offset, context->end_offset, &cmd_count); - CMDBUF_OFFSET(*context) += cmd_count; - } - - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_SEMAPHORE(module); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[2] = VG_LITE_STALL(module); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[3] = 0; - -#if DUMP_COMMAND - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], 0); - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[2], 0); - - fclose(fp); - fp = NULL; -#endif - - CMDBUF_OFFSET(*context) += 16; - - return VG_LITE_SUCCESS; -} - -static vg_lite_error_t flush(vg_lite_context_t *context) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t address0 = 0x0A34; - uint32_t address1 = 0x0A1B; - uint32_t data0 = 0; - uint32_t data1 = 0x00000001; - uint32_t module = 7; - - /* Check if there is a valid context and an allocated command buffer. */ - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - /* Check if there is anything to flush. */ - if (CMDBUF_OFFSET(*context) == 0) - return VG_LITE_INVALID_ARGUMENT; - - /* Check if there is enough space in the command buffer. */ - if (CMDBUF_OFFSET(*context) + 32 > CMDBUF_SIZE(*context)) { - return VG_LITE_OUT_OF_RESOURCES; - } - - /* Finialize command buffer. */ - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_STATE(address0); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = data0; - - /* flush target */ - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[2] = VG_LITE_STATE(address1); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[3] = data1; - - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[4] = VG_LITE_SEMAPHORE(module); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[5] = 0; - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[6] = VG_LITE_STALL(module); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[7] = 0; - - CMDBUF_OFFSET(*context) += 32; - - return error; -} - -/* Submit the current command buffer to HW and reset the current command buffer offset. */ -static vg_lite_error_t submit(vg_lite_context_t *context) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_kernel_submit_t submit; - - /* Check if there is a valid context and an allocated command buffer. */ - if (!has_valid_command_buffer(context)) - return VG_LITE_NO_CONTEXT; - - /* Check if there is anything to submit. */ - if (CMDBUF_OFFSET(*context) == 0) - return VG_LITE_INVALID_ARGUMENT; - - /* Check if there is enough space in the command buffer for the END. */ - if (CMDBUF_OFFSET(*context) + 8 > CMDBUF_SIZE(*context)) { - /* Reset command buffer offset. */ - CMDBUF_OFFSET(*context) = 0; - return VG_LITE_OUT_OF_RESOURCES; - } - - /* Append END command into the command buffer. */ - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0] = VG_LITE_END(0); - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[1] = 0; - -#if DUMP_COMMAND - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) (CMDBUF_BUFFER(*context) + CMDBUF_OFFSET(*context)))[0], 0); - - fprintf(fp, "Command buffer addr is : %p,\n", CMDBUF_BUFFER(*context)); - fprintf(fp, "Command buffer offset is : %d,\n", CMDBUF_OFFSET(*context) + 8); - - fclose(fp); - fp = NULL; -#endif - - CMDBUF_OFFSET(*context) += 8; - - /* Submit the command buffer. */ - submit.context = &context->context; - submit.commands = CMDBUF_BUFFER(*context); - submit.command_size = CMDBUF_OFFSET(*context); - submit.command_id = CMDBUF_INDEX(*context); - - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_SUBMIT, &submit)); - - vglitemDUMP_BUFFER("command", (unsigned int)CMDBUF_BUFFER(*context), - submit.context->command_buffer_logical[CMDBUF_INDEX(*context)], 0, submit.command_size); - vglitemDUMP("@[commit]"); - - /* Reset command buffer. */ - CMDBUF_OFFSET(*context) = 0; - - return error; -} - -/* Wait for the HW to finish the current execution. */ -static vg_lite_error_t stall(vg_lite_context_t * context, uint32_t time_ms) -{ - vg_lite_error_t error; - vg_lite_kernel_wait_t wait; - - vglitemDUMP("@[stall]"); - /* Wait until GPU is ready. */ - wait.context = &context->context; - wait.timeout_ms = time_ms > 0 ? time_ms : VG_LITE_MAX_WAIT_TIME; - wait.command_id = CMDBUF_INDEX(*context); - - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_WAIT, &wait)); - return VG_LITE_SUCCESS; -} - -#endif /* VG_DRIVER_SINGLE_THREAD */ - -/* Get the inversion of a matrix. */ -VG_LITE_OPTIMIZE(LOW) static int inverse(vg_lite_matrix_t * result, vg_lite_matrix_t * matrix) -{ - vg_lite_float_t det00, det01, det02; - vg_lite_float_t d; - int isAffine; - - /* Test for identity matrix. */ - if (matrix == NULL) { - result->m[0][0] = 1.0f; - result->m[0][1] = 0.0f; - result->m[0][2] = 0.0f; - result->m[1][0] = 0.0f; - result->m[1][1] = 1.0f; - result->m[1][2] = 0.0f; - result->m[2][0] = 0.0f; - result->m[2][1] = 0.0f; - result->m[2][2] = 1.0f; - - /* Success. */ - return 1; - } - - det00 = (matrix->m[1][1] * matrix->m[2][2]) - (matrix->m[2][1] * matrix->m[1][2]); - det01 = (matrix->m[2][0] * matrix->m[1][2]) - (matrix->m[1][0] * matrix->m[2][2]); - det02 = (matrix->m[1][0] * matrix->m[2][1]) - (matrix->m[2][0] * matrix->m[1][1]); - - /* Compute determinant. */ - d = (matrix->m[0][0] * det00) + (matrix->m[0][1] * det01) + (matrix->m[0][2] * det02); - - /* Return 0 if there is no inverse matrix. */ - if (d == 0.0f) - return 0; - - /* Compute reciprocal. */ - d = 1.0f / d; - - /* Determine if the matrix is affine. */ - isAffine = (matrix->m[2][0] == 0.0f) && (matrix->m[2][1] == 0.0f) && (matrix->m[2][2] == 1.0f); - - result->m[0][0] = d * det00; - result->m[0][1] = d * ((matrix->m[2][1] * matrix->m[0][2]) - (matrix->m[0][1] * matrix->m[2][2])); - result->m[0][2] = d * ((matrix->m[0][1] * matrix->m[1][2]) - (matrix->m[1][1] * matrix->m[0][2])); - result->m[1][0] = d * det01; - result->m[1][1] = d * ((matrix->m[0][0] * matrix->m[2][2]) - (matrix->m[2][0] * matrix->m[0][2])); - result->m[1][2] = d * ((matrix->m[1][0] * matrix->m[0][2]) - (matrix->m[0][0] * matrix->m[1][2])); - result->m[2][0] = isAffine ? 0.0f : d * det02; - result->m[2][1] = isAffine ? 0.0f : d * ((matrix->m[2][0] * matrix->m[0][1]) - (matrix->m[0][0] * matrix->m[2][1])); - result->m[2][2] = isAffine ? 1.0f : d * ((matrix->m[0][0] * matrix->m[1][1]) - (matrix->m[1][0] * matrix->m[0][1])); - - /* Success. */ - return 1; -} - -/* Transform a 2D point by a given matrix. */ -static int transform(vg_lite_point_t * result, vg_lite_float_t x, vg_lite_float_t y, vg_lite_matrix_t * matrix) -{ - vg_lite_float_t pt_x; - vg_lite_float_t pt_y; - vg_lite_float_t pt_w; - - /* Test for identity matrix. */ - if (matrix == NULL) { - result->x = (int)x; - result->y = (int)y; - - /* Success. */ - return 1; - } - - /* Transform x, y, and w. */ - pt_x = (x * matrix->m[0][0]) + (y * matrix->m[0][1]) + matrix->m[0][2]; - pt_y = (x * matrix->m[1][0]) + (y * matrix->m[1][1]) + matrix->m[1][2]; - pt_w = (x * matrix->m[2][0]) + (y * matrix->m[2][1]) + matrix->m[2][2]; - - if (pt_w <= 0.0f) - return 0; - - /* Compute projected x and y. */ - result->x = (int)(pt_x / pt_w); - result->y = (int)(pt_y / pt_w); - - /* Success. */ - return 1; -} - -/*! - Flush specific VG module. - */ -#if defined(VG_DRIVER_SINGLE_THREAD) -static vg_lite_error_t flush_target() - { - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_context_t *context = GET_CONTEXT(); - - do { - VG_LITE_BREAK_ERROR(push_state(context, 0x0A1B, 0x00000001)); - VG_LITE_BREAK_ERROR(push_stall(context, 7)); - } while (0); - - return error; -} -#else -static vg_lite_error_t flush_target() -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_tls_t* tls; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - do { - VG_LITE_BREAK_ERROR(push_state(&tls->t_context, 0x0A1B, 0x00000001)); - VG_LITE_BREAK_ERROR(push_stall(&tls->t_context, 7)); - } while (0); - - return error; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -/****************** FAST_CLEAR feature implementation. ***************/ -#if VG_TARGET_FAST_CLEAR -static vg_lite_error_t convert_color(vg_lite_buffer_format_t format, uint32_t value, uint32_t *result, int *bpp) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t r, g, b, a; - int Bpp = 0; - - r = B(value); - g = G(value); - b = R(value); - a = A(value); - - do { - switch (format) { - case VG_LITE_RGBA8888: - *result = ARGB(a, b, g, r); - Bpp = 32; - break; - - case VG_LITE_BGRA8888: - *result = ARGB(a, r, g, b); - Bpp = 32; - break; - - case VG_LITE_RGBX8888: - *result = ARGB(0xff, b, g, r); - Bpp = 32; - break; - - case VG_LITE_BGRX8888: - *result = ARGB(0xff, r, g, b); - Bpp = 32; - break; - - case VG_LITE_RGBA4444: - *result = ARGB4(a, b, g, r); - Bpp = 16; - break; - - case VG_LITE_BGRA4444: - *result = ARGB4(a, r, g, b); - Bpp = 16; - break; - - case VG_LITE_RGB565: - *result = ((b & 0xf8) << 8) | - ((g & 0xfc) << 3) | - ((r & 0xf8) >> 3); - Bpp = 16; - break; - - case VG_LITE_BGR565: - *result = ((r & 0xf8) << 8) | - ((g & 0xfc) << 3) | - ((b & 0xf8) >> 3); - Bpp = 16; - break; - - case VG_LITE_BGRA5551: - *result = ((b & 0xf8) << 8) | - ((g & 0xf8) << 3) | - ((r & 0xf8) >> 2) | - ((a & 0x80) >> 7); - Bpp = 16; - break; - - case VG_LITE_A8: - *result = ARGB(a, a, a, a); - Bpp = 8; - break; - - case VG_LITE_L8: - *result = ARGB(r, r, r, r); - Bpp = 8; - break; - - default: - error = VG_LITE_NOT_SUPPORT; - break; - } - } while (0); - - if (bpp != NULL) { - *bpp = Bpp; - } - - if (Bpp == 16) { - *result = ((*result) << 16) | (*result); - } - return error; -} - -/* Fill Target buffer by FC buffer. Only used in cmodel/fpga for verification. */ -#if defined(DEBUG) || defined(_DEBUG) -static vg_lite_error_t fill_fc_target(vg_lite_buffer_t *target, vg_lite_buffer_t *fcb) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint8_t *fc = (uint8_t *)fcb->memory; - uint16_t *target16; - uint32_t *target32; - uint8_t *target8; - uint32_t clear32; - int byte_done = 0; - int i, j, k; - int bpp; - - do { - convert_color(target->format, s_context.clearValue, &clear32, &bpp); - - if (bpp == 32) { - target32 = (uint32_t *)target->memory; - for (i = 0; i < fcb->width; i++) { - - for (j = 0; j < 8; j++) { /* Loop the bits*/ - - if (!(((*fc) >> j) & 1)) { - for (k = 0; k < 64 / 4; k++) { - target32[k] = clear32; - byte_done+=4; - if (byte_done >= target->stride * target->height) { - return error; - } - } - } - - target32 += 64/4; - } - - fc++; - } - } - else if (bpp == 16){ - target16 = (uint16_t *)target->memory; - for (i = 0; i < fcb->width; i++) { - - for (j = 0; j < 8; j++) { /* Loop the bits*/ - - if (!(((*fc) >> j) & 1)) { - for (k = 0; k < 64 / 2; k++) { - target16[k] = (uint16_t)clear32; - byte_done+=2; - if (byte_done >= target->stride * target->height) { - return error; - } - } - } - - target16 += 64/2; - } - - fc++; - } - } - else if (bpp == 8) { - target8 = (uint8_t *)target->memory; - for (i = 0; i < fcb->width; i++) { - - for (j = 0; j < 8; j++) { /* Loop the bits*/ - - if (!(((*fc) >> j) & 1)) { - for (k = 0; k < 64; k++) { - target8[k] = (uint8_t)clear32; - byte_done++; - if (byte_done >= target->stride * target->height) { - return error; - } - } - } - - target8 += 64; - } - - fc++; - } - } - } while (0); - - return error; -} -#endif - -/* Update the fast_clear buffer when render target switched. */ -static vg_lite_error_t update_fc_buffer(vg_lite_buffer_t *target) -{ - int rt_bytes; - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_context_t *context = GET_CONTEXT(); - vg_lite_kernel_allocate_t allocate; - - do { - if (target == NULL) { - error = VG_LITE_INVALID_ARGUMENT; - break; - } - - rt_bytes = target->stride * target->height; - rt_bytes = VG_LITE_ALIGN(rt_bytes, (FC_BIT_TO_BYTES * 8)); - rt_bytes = rt_bytes / FC_BIT_TO_BYTES / 8; - /* Only allocate new buffer when the allocated is not big enough. Yes*/ - if (rt_bytes > context->fcBuffer.stride ) { - vg_lite_free(&context->fcBuffer); - - context->fcBuffer.width = rt_bytes; /* The actually used bytes. */ - rt_bytes = VG_LITE_ALIGN(rt_bytes, FC_BURST_BYTES); /* The allocated aligned bytes. */ - context->fcBuffer.stride = rt_bytes; - allocate.bytes = rt_bytes; - allocate.contiguous = 1; - - VG_LITE_BREAK_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); - context->fcBuffer.handle = allocate.memory_handle; - context->fcBuffer.memory = allocate.memory; - context->fcBuffer.address = allocate.memory_gpu; - } - else { - /* Just update the fc buffer size. */ - context->fcBuffer.width = rt_bytes; - } - memset(context->fcBuffer.memory, 0xff, context->fcBuffer.stride); - } while (0); - - return error; -} - -/* Update FC registers and clear FC buffer. */ -static vg_lite_error_t clear_fc(uint32_t value) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_context_t *context = GET_CONTEXT(); - uint32_t bytes_to_clear = context->fcBuffer.stride / FC_BURST_BYTES; - - do { - VG_LITE_BREAK_ERROR(push_state(context, 0x0A9A, context->fcBuffer.address)); /* FC buffer address. */ - VG_LITE_BREAK_ERROR(push_state(context, 0x0A9B, value)); /* FC clear value. */ - VG_LITE_BREAK_ERROR(push_state(context, 0x0AB0, 0x80000000 | bytes_to_clear)); /* FC clear command. */ - } while (0); - - return error; -} - -#if VG_TARGET_FC_DUMP -static int fc_buf_dump(vg_lite_buffer_t *target, vg_lite_buffer_t *fcb) -{ - int error = VG_LITE_SUCCESS; - uint8_t *fc = (uint8_t *)fcb->memory; - uint8_t *target8; - int byte_done = 0; - int target_bytes; - int i, j; - - static unsigned s_cnt; - unsigned cnt = s_cnt; - - FILE *fpFCBuf; - FILE *fpTargetBuf; - FILE *fpTargetBufInfo; - char buf[256]; - - s_cnt++; - - sprintf(buf, "vg255v2.fc_buf.f%04d.txt", cnt); - fpFCBuf = fopen(buf, "wt"); - if (NULL == fpFCBuf) { - fprintf(stderr, "[Warning] Open file \'%s\' fail.\n", buf); - return -1; - } - - sprintf(buf, "vg255v2.target_buf_info.f%04d.txt", cnt); - fpTargetBufInfo = fopen(buf, "wt"); - if (NULL == fpTargetBufInfo) { - fprintf(stderr, "[Warning] Open file \'%s\' fail.\n", buf); - fclose(fpFCBuf); - return -1; - } else { - fprintf(fpTargetBufInfo, "%-12s: %d\n", "format", target->format); - fprintf(fpTargetBufInfo, "%-12s: %d\n", "tiled", target->tiled); - fprintf(fpTargetBufInfo, "%-12s: %d\n", "width", target->width); - fprintf(fpTargetBufInfo, "%-12s: %d\n", "height", target->height); - fprintf(fpTargetBufInfo, "%-12s: %d\n", "stride", target->stride); - - fclose(fpTargetBufInfo); - } - - sprintf(buf, "vg255v2.target_buf.f%04d.txt", cnt); - fpTargetBuf = fopen(buf, "wt"); - if (NULL == fpTargetBuf) { - fprintf(stderr, "[Warning] Open file \'%s\' fail.\n", buf); - fclose(fpFCBuf); - return -1; - } - - /* Dump FC buffer & Dump target buffer */ - target8 = (uint8_t *)target->memory; - target_bytes = target->stride * target->height; - - for (i = 0; i < fcb->width; ++i) - { - fprintf(fpFCBuf, "%02x\n", fc[i]); - /* 1 byte of fc related with 512 bytes of target buffer */ - for (j = 0; j < 128; ++j) { - fprintf(fpTargetBuf, "%02x", byte_done < target_bytes ? target8[0] : 0); - byte_done++; - - fprintf(fpTargetBuf, "%02x", byte_done < target_bytes ? target8[1] : 0); - byte_done++; - - fprintf(fpTargetBuf, "%02x", byte_done < target_bytes ? target8[2] : 0); - byte_done++; - - fprintf(fpTargetBuf, "%02x\n", byte_done < target_bytes ? target8[3] : 0); - byte_done++; - - target8 += 4; - } - } - - fclose(fpFCBuf); - fclose(fpTargetBuf); - - return error; -} -#endif /* VG_TARGET_FC_DUMP */ - -#endif - -/* Set the current render target. */ -#if defined(VG_DRIVER_SINGLE_THREAD) -static vg_lite_error_t set_render_target(vg_lite_buffer_t *target) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t yuv2rgb = 0; - uint32_t uv_swiz = 0; - int32_t tiled; - int32_t dst_align_width; - uint32_t mul, div, align; - if(target == NULL) { - return VG_LITE_INVALID_ARGUMENT; - } else if(s_context.scissor_enabled && (s_context.scissor[2] <= 0 || s_context.scissor[3] <= 0)) { - /* Check scissoring rectangle dimensions - A scissoring rectangle with width <= 0 or height <= 0 must be - ignored. If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs. */ - return VG_LITE_NO_CONTEXT; - } - /* Skip if render target and scissor are not changed. */ - if ((s_context.rtbuffer != NULL) && - !(memcmp(s_context.rtbuffer,target,sizeof(vg_lite_buffer_t))) && - (s_context.scissor_dirty == 0) && (s_context.premultiply_dirty == 0)) - { - return VG_LITE_SUCCESS; - } - - if ((target != NULL) && - (target->format == VG_LITE_YUY2 || - target->format == VG_LITE_AYUY2 || - target->format == VG_LITE_YUY2_TILED || - target->format == VG_LITE_AYUY2_TILED)) - { - return VG_LITE_NOT_SUPPORT; - } - - -#if VG_TARGET_FAST_CLEAR - /* Flush target if necessary when switching. */ - if (s_context.rtbuffer&& s_context.rtbuffer->memory) { /* If it's not the first time to set target. */ - vg_lite_finish(); - } - update_fc_buffer(target); -#else - if (s_context.rtbuffer && s_context.rtbuffer->memory) { - /* Flush the old target. */ - vg_lite_finish(); - } -#endif - - tiled = (target->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0; - - if (((target->format >= VG_LITE_YUY2) && - (target->format <= VG_LITE_AYUY2)) || - ((target->format >= VG_LITE_YUY2_TILED) && - (target->format <= VG_LITE_AYUY2_TILED))) { - yuv2rgb = convert_yuv2rgb(target->yuv.yuv2rgb); - uv_swiz = convert_uv_swizzle(target->yuv.swizzle); - } - - /* Program render target. */ - if (s_context.premultiply_dirty || s_context.rtbuffer != target || memcmp(s_context.rtbuffer,target,sizeof(vg_lite_buffer_t)) ) { - if(target->tiled == VG_LITE_TILED) { - if((target->stride % DEST_ALIGNMENT_LIMITATION) != 0) - return VG_LITE_INVALID_ARGUMENT; - } - if(s_context.premultiply_enabled) { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A10, - convert_target_format(target->format, s_context.capabilities) | 0x00010000 | uv_swiz | yuv2rgb)); - }else { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A10, - convert_target_format(target->format, s_context.capabilities) | 0x00010000 | uv_swiz | yuv2rgb | 0x100)); - } - if (target->yuv.uv_planar) - { /* Program uv plane address if necessary. */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A5C, target->yuv.uv_planar)); - } - if (target->yuv.alpha_planar) { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A5D, target->yuv.alpha_planar)); - } - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A11, target->address)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A12, target->stride | tiled)); - s_context.premultiply_dirty = 0; - } - - get_format_bytes(target->format, &mul, &div, &align); - dst_align_width = target->stride * div / mul; - - if (s_context.scissor_dirty != 0) { - if (s_context.scissor_enabled) { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A13, (s_context.scissor[0] + s_context.scissor[2]) | ((s_context.scissor[1] + s_context.scissor[3]) << 16))); - } - else { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A13, dst_align_width | (target->height << 16))); - } - s_context.scissor_dirty = 0; - } - else { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A13, dst_align_width | (target->height << 16))); - } - - memcpy(s_context.rtbuffer, target, sizeof(vg_lite_buffer_t)); - - return error; -} -#else -static vg_lite_error_t set_render_target(vg_lite_buffer_t *target) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t yuv2rgb = 0; - uint32_t uv_swiz = 0; - int32_t tiled; - vg_lite_tls_t* tls; - int32_t dst_align_width; - uint32_t mul, div, align; - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - if(target == NULL) { - return VG_LITE_INVALID_ARGUMENT; - } else if(tls->t_context.scissor_enabled && (tls->t_context.scissor[2] <= 0 || tls->t_context.scissor[3] <= 0)) { - /* Check scissoring rectangle dimensions - A scissoring rectangle with width <= 0 or height <= 0 must be - ignored. If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs. */ - return VG_LITE_NO_CONTEXT; - } - - tls->t_context.start_offset = CMDBUF_OFFSET(tls->t_context); - - if ((target != NULL) && - (target->format == VG_LITE_YUY2 || - target->format == VG_LITE_AYUY2 || - target->format == VG_LITE_YUY2_TILED || - target->format == VG_LITE_AYUY2_TILED)) - { - return VG_LITE_NOT_SUPPORT; - } - -#if VG_TARGET_FAST_CLEAR - /* Flush target if necessary when switching. */ - if (tls->t_context.rtbuffer != NULL) { /* If it's not the first time to set target. */ - vg_lite_finish(); - } - update_fc_buffer(target); -#endif - - tiled = (target->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0; - - if (((target->format >= VG_LITE_YUY2) && - (target->format <= VG_LITE_AYUY2)) || - ((target->format >= VG_LITE_YUY2_TILED) && - (target->format <= VG_LITE_AYUY2_TILED))) { - yuv2rgb = convert_yuv2rgb(target->yuv.yuv2rgb); - uv_swiz = convert_uv_swizzle(target->yuv.swizzle); - } - - /* Program render target. */ - if(target->tiled == VG_LITE_TILED) { - if((target->stride % DEST_ALIGNMENT_LIMITATION) != 0) - return VG_LITE_INVALID_ARGUMENT; - } - - if(tls->t_context.premultiply_enabled) { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A10, - convert_target_format(target->format, tls->t_context.capabilities) | 0x00010000 | uv_swiz | yuv2rgb)); - } else { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A10, - convert_target_format(target->format, tls->t_context.capabilities) | 0x00010000 | uv_swiz | yuv2rgb | 0x100)); - } - if (target->yuv.uv_planar) - { /* Program uv plane address if necessary. */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A5C, target->yuv.uv_planar)); - } - if (target->yuv.alpha_planar) { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A5D, target->yuv.alpha_planar)); - } - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A11, target->address)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A12, target->stride | tiled)); - get_format_bytes(target->format, &mul, &div, &align); - dst_align_width = target->stride * div / mul; - - if (tls->t_context.scissor_enabled) { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A13, (tls->t_context.scissor[0] + tls->t_context.scissor[2]) | ((tls->t_context.scissor[1] + tls->t_context.scissor[3]) << 16))); - } - else { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A13, dst_align_width | (target->height << 16))); - } - - tls->t_context.rtbuffer = target; - - return error; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -static inline vg_lite_error_t transform_bounding_box(vg_lite_rectangle_t *in_bbx, - vg_lite_matrix_t *matrix, - vg_lite_rectangle_t *clip, - vg_lite_rectangle_t *out_bbx, - vg_lite_point_t *origin) -{ - vg_lite_point_t temp; - - memset(out_bbx, 0, sizeof(vg_lite_rectangle_t)); - - /* Transform image point (0, 0). */ - if (!transform(&temp, 0.0f, 0.0f, matrix)) - return VG_LITE_INVALID_ARGUMENT; - out_bbx->x = temp.x; - out_bbx->y = temp.y; - - /* Provide position of the new origin to the caller if requested. */ - if (origin != NULL) { - origin->x = temp.x; - origin->y = temp.y; - } - - /* Transform image point (0, height). */ - if (!transform(&temp, 0.0f, in_bbx->height, matrix)) - return VG_LITE_INVALID_ARGUMENT; - UPDATE_BOUNDING_BOX(*out_bbx, temp); - - /* Transform image point (width, height). */ - if (!transform(&temp, in_bbx->width, in_bbx->height, matrix)) - return VG_LITE_INVALID_ARGUMENT; - UPDATE_BOUNDING_BOX(*out_bbx, temp); - - /* Transform image point (width, 0). */ - if (!transform(&temp, in_bbx->width, 0.0f, matrix)) - return VG_LITE_INVALID_ARGUMENT; - UPDATE_BOUNDING_BOX(*out_bbx, temp); - - /* Clip is required */ - if (clip) { - out_bbx->x = MAX(out_bbx->x, clip->x); - out_bbx->y = MAX(out_bbx->y, clip->y); - out_bbx->width = MIN((out_bbx->x + out_bbx->width), (clip->x + clip->width)) - out_bbx->x; - out_bbx->height = MIN((out_bbx->y + out_bbx->height), (clip->y + clip->height)) - out_bbx->y; - } - - return VG_LITE_SUCCESS; -} - -#if (VG_BLIT_WORKAROUND == 1) -/* - * Calculates the minimal possible target buffer starting from a given target - * buffer and considering a source texture (to blit), graphic transformations - * and clipping window. - */ -static vg_lite_error_t config_new_target(vg_lite_buffer_t *target, - vg_lite_buffer_t *source, - vg_lite_matrix_t *matrix, - vg_lite_rectangle_t *bbx, - vg_lite_buffer_t *new_target) -{ - uint8_t *p; - vg_lite_point_t origin; - vg_lite_rectangle_t src_bbx, bounding_box, clip; - int tx, ty; - uint32_t mul, div, required_align, align; - - /* - * Acquire the bounding box of the transformed source image and the location - * of its origin. - */ - memset(&src_bbx, 0, sizeof(vg_lite_rectangle_t)); - src_bbx.width = source->width; - src_bbx.height = source->height; - if (bbx == NULL) { - /* - * If no clipping rectangle provided, just configure the clip bounds to - * be as big as the target - */ - memset(&clip, 0, sizeof(vg_lite_rectangle_t)); - clip.width = target->width; - clip.height = target->height; - } else { - /* Otherwise clip according to the bounding box specified by the caller */ - memcpy(&clip, bbx, sizeof(vg_lite_rectangle_t)); - } - transform_bounding_box(&src_bbx, matrix, &clip, &bounding_box, &origin); - - /* Calculate the data address of the new target */ - get_format_bytes(target->format, &mul, &div, &required_align); - p = target->memory; - p += bounding_box.y * target->stride + bounding_box.x * (mul / div); - align = (uint32_t)p & (required_align - 1); - p -= align; - - /* - * Update pixel coordinate of the base address. The width of the target will - * increase, since the x coordinate of the bounding box decreases to - * accomodate the image data alignment. - */ - tx = align / (mul / div); - bounding_box.x -= tx; - bounding_box.width += tx; - - /* Update bounding box if provided by the caller */ - if (bbx) { - bbx->x = tx; - bbx->y = 0; - } - - /* Calculate translation from the source image origin to the target origin. */ - tx = origin.x - bounding_box.x; - ty = origin.y - bounding_box.y; - - /* Copy content of the target buffer descriptor into the new target. */ - memcpy(new_target, target, sizeof(vg_lite_buffer_t)); - - /* Update the new buffer */ - new_target->memory = p; - new_target->address = (uint32_t) p; - new_target->width = bounding_box.width; - new_target->height = bounding_box.height; - - /* Update matrix */ - matrix->m[0][2] = tx; - matrix->m[1][2] = ty; - - return VG_LITE_SUCCESS; -} -#endif /* VG_BLIT_WORKAROUND */ - -#if defined(VG_DRIVER_SINGLE_THREAD) -static vg_lite_error_t set_interpolation_steps(vg_lite_buffer_t *target, - vg_lite_float_t s_width, - vg_lite_float_t s_height, - vg_lite_matrix_t *matrix) -{ - vg_lite_matrix_t im; - vg_lite_rectangle_t src_bbx, bounding_box, clip; - vg_lite_float_t xs[3], ys[3], cs[3]; - vg_lite_error_t error = VG_LITE_SUCCESS; - float dx = 0.0f, dy = 0.0f; - - #define ERR_LIMIT 0.0000610351562f - - /* Get bounding box. */ - memset(&src_bbx, 0, sizeof(vg_lite_rectangle_t)); - memset(&clip, 0, sizeof(vg_lite_rectangle_t)); - src_bbx.width = (int32_t)s_width; - src_bbx.height = (int32_t)s_height; - - if (s_context.scissor_enabled) { - clip.x = s_context.scissor[0]; - clip.y = s_context.scissor[1]; - clip.width = s_context.scissor[2]; - clip.height = s_context.scissor[3]; - } else { - clip.x = clip.y = 0; - clip.width = s_context.rtbuffer->width; - clip.height = s_context.rtbuffer->height; - } - transform_bounding_box(&src_bbx, matrix, &clip, &bounding_box, NULL); - - /* Compute inverse matrix. */ - if (!inverse(&im, matrix)) - return VG_LITE_INVALID_ARGUMENT; - /* Compute interpolation steps. */ - /* X step */ - xs[0] = im.m[0][0] / s_width; - xs[1] = im.m[1][0] / s_height; - xs[2] = im.m[2][0]; - /* Y step */ - ys[0] = im.m[0][1] / s_width; - ys[1] = im.m[1][1] / s_height; - ys[2] = im.m[2][1]; - /* C step 2 */ - cs[2] = 0.5f * (im.m[2][0] + im.m[2][1]) + im.m[2][2]; - /* Keep track of the rounding errors (underflow) */ - if (s_context.chip_id == GPU_CHIP_ID_GCNanoliteV) { - /* Check if matrix has rotation or perspective transformations */ - if (matrix != NULL && - (matrix->m[0][1] != 0.0f || matrix->m[1][0] != 0.0f || - matrix->m[2][0] != 0.0f || matrix->m[2][1] != 0.0f || - matrix->m[2][2] != 1.0f)) { - if (xs[0] != 0.0f && -ERR_LIMIT < xs[0] && xs[0] < ERR_LIMIT) - dx = 0.5f * (2 * bounding_box.x + bounding_box.width) * im.m[0][0]; - else if (ys[0] != 0.0f && -ERR_LIMIT < ys[0] && ys[0] < ERR_LIMIT) - dx = 0.5f * (2 * bounding_box.y + bounding_box.height) * im.m[0][1]; - if (xs[1] != 0.0f && -ERR_LIMIT < xs[1] && xs[1] < ERR_LIMIT) - dy = 0.5f * (2 * bounding_box.x + bounding_box.width) * im.m[1][0]; - else if (ys[1] != 0.0f && -ERR_LIMIT < ys[1] && ys[1] < ERR_LIMIT) - dy = 0.5f * (2 * bounding_box.y + bounding_box.height) * im.m[1][1]; - } - } - /* C step 0, 1*/ - cs[0] = (0.5f * (im.m[0][0] + im.m[0][1]) + im.m[0][2] + dx) / s_width; - cs[1] = (0.5f * (im.m[1][0] + im.m[1][1]) + im.m[1][2] + dy) / s_height; - /* Set command buffer */ - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A18, (void *)&cs[0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A19, (void *)&cs[1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A1A, (void *)&cs[2])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A1C, (void *)&xs[0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A1D, (void *)&xs[1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A1E, (void *)&xs[2])); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A1F, 0x00000001)); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A20, (void *)&ys[0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A21, (void *)&ys[1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A22, (void *)&ys[2])); - - return VG_LITE_SUCCESS; -} -#else -static vg_lite_error_t set_interpolation_steps(vg_lite_buffer_t *target, - vg_lite_float_t s_width, - vg_lite_float_t s_height, - vg_lite_matrix_t *matrix) -{ - vg_lite_matrix_t im; - vg_lite_rectangle_t src_bbx, bounding_box, clip; - vg_lite_float_t xs[3], ys[3], cs[3]; - vg_lite_error_t error = VG_LITE_SUCCESS; - float dx = 0.0f, dy = 0.0f; - vg_lite_tls_t *tls; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - #define ERR_LIMIT 0.0000610351562f - - /* Get bounding box. */ - memset(&src_bbx, 0, sizeof(vg_lite_rectangle_t)); - memset(&clip, 0, sizeof(vg_lite_rectangle_t)); - src_bbx.width = (int32_t)s_width; - src_bbx.height = (int32_t)s_height; - - if (tls->t_context.scissor_enabled) { - clip.x = tls->t_context.scissor[0]; - clip.y = tls->t_context.scissor[1]; - clip.width = tls->t_context.scissor[2]; - clip.height = tls->t_context.scissor[3]; - } else { - clip.x = clip.y = 0; - clip.width = tls->t_context.rtbuffer->width; - clip.height = tls->t_context.rtbuffer->height; - } - transform_bounding_box(&src_bbx, matrix, &clip, &bounding_box, NULL); - - /* Compute inverse matrix. */ - if (!inverse(&im, matrix)) - return VG_LITE_INVALID_ARGUMENT; - /* Compute interpolation steps. */ - /* X step */ - xs[0] = im.m[0][0] / s_width; - xs[1] = im.m[1][0] / s_height; - xs[2] = im.m[2][0]; - /* Y step */ - ys[0] = im.m[0][1] / s_width; - ys[1] = im.m[1][1] / s_height; - ys[2] = im.m[2][1]; - /* C step 2 */ - cs[2] = 0.5f * (im.m[2][0] + im.m[2][1]) + im.m[2][2]; - /* Keep track of the rounding errors (underflow) */ - if (tls->t_context.chip_id == GPU_CHIP_ID_GCNanoliteV) { - /* Check if matrix has rotation or perspective transformations */ - if (matrix != NULL && - (matrix->m[0][1] != 0.0f || matrix->m[1][0] != 0.0f || - matrix->m[2][0] != 0.0f || matrix->m[2][1] != 0.0f || - matrix->m[2][2] != 1.0f)) { - if (xs[0] != 0.0f && -ERR_LIMIT < xs[0] && xs[0] < ERR_LIMIT) - dx = 0.5f * (2 * bounding_box.x + bounding_box.width) * im.m[0][0]; - else if (ys[0] != 0.0f && -ERR_LIMIT < ys[0] && ys[0] < ERR_LIMIT) - dx = 0.5f * (2 * bounding_box.y + bounding_box.height) * im.m[0][1]; - if (xs[1] != 0.0f && -ERR_LIMIT < xs[1] && xs[1] < ERR_LIMIT) - dy = 0.5f * (2 * bounding_box.x + bounding_box.width) * im.m[1][0]; - else if (ys[1] != 0.0f && -ERR_LIMIT < ys[1] && ys[1] < ERR_LIMIT) - dy = 0.5f * (2 * bounding_box.y + bounding_box.height) * im.m[1][1]; - } - } - /* C step 0, 1*/ - cs[0] = (0.5f * (im.m[0][0] + im.m[0][1]) + im.m[0][2] + dx) / s_width; - cs[1] = (0.5f * (im.m[1][0] + im.m[1][1]) + im.m[1][2] + dy) / s_height; - /* Set command buffer */ - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A18, (void *)&cs[0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A19, (void *)&cs[1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A1A, (void *)&cs[2])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A1C, (void *)&xs[0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A1D, (void *)&xs[1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A1E, (void *)&xs[2])); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A1F, 0x00000001)); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A20, (void *)&ys[0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A21, (void *)&ys[1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A22, (void *)&ys[2])); - - return VG_LITE_SUCCESS; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -/*************** API Functions ***********************************************/ -vg_lite_error_t vg_lite_get_transform_matrix(vg_lite_point4_t src, vg_lite_point4_t dst,vg_lite_matrix_t *mat) -{ - float a[8][8],b[9],A[64]; - int i, j, k, m = 8, n = 1; - int astep = 8,bstep = 1; - float d; - - if(src == NULL || dst == NULL || mat == NULL) - return VG_LITE_INVALID_ARGUMENT; - - for(i = 0; i < 4; ++i ) - { - a[i][0] = a[i+4][3] = src[i].x; - a[i][1] = a[i+4][4] = src[i].y; - a[i][2] = a[i+4][5] = 1; - a[i][3] = a[i][4] = a[i][5] = - a[i+4][0] = a[i+4][1] = a[i+4][2] = 0; - a[i][6] = -src[i].x*dst[i].x; - a[i][7] = -src[i].y*dst[i].x; - a[i+4][6] = -src[i].x*dst[i].y; - a[i+4][7] = -src[i].y*dst[i].y; - b[i] = dst[i].x; - b[i+4] = dst[i].y; - } - for(i = 0; i < 8; ++i ) - { - for(j = 0; j < 8; ++j ) - { - A[8 * i + j] = a[i][j]; - } - } - - for (i = 0; i < m; i++) - { - k = i; - for (j = i + 1; j < m; j++) - if (ABS(A[j*astep + i]) > ABS(A[k*astep + i])) - k = j; - if (ABS(A[k*astep + i]) < EPS) - return VG_LITE_INVALID_ARGUMENT; - if (k != i) - { - for (j = i; j < m; j++) - swap(&A[i*astep + j], &A[k*astep + j]); - for (j = 0; j < n; j++) - swap(&b[i*bstep + j], &b[k*bstep + j]); - } - d = -1 / A[i*astep + i]; - for (j = i + 1; j < m; j++) - { - float alpha = A[j*astep + i] * d; - for (k = i + 1; k < m; k++) - A[j*astep + k] += alpha * A[i*astep + k]; - for (k = 0; k < n; k++) - b[j*bstep + k] += alpha * b[i*bstep + k]; - } - } - - for (i = m - 1; i >= 0; i--) - for (j = 0; j < n; j++) - { - float s = b[i*bstep + j]; - for (k = i + 1; k < m; k++) - s -= A[i*astep + k] * b[k*bstep + j]; - b[i*bstep + j] = s / A[i*astep + i]; - } - b[8] = 1; - - for(i = 0; i < 3; ++i ) - { - for(j = 0; j < 3; ++j ) - { - mat->m[i][j] = b[i* 3 + j]; - } - } - - return VG_LITE_SUCCESS; -} - -#if defined(VG_DRIVER_SINGLE_THREAD) -vg_lite_error_t vg_lite_clear(vg_lite_buffer_t * target, - vg_lite_rectangle_t * rectangle, - vg_lite_color_t color) -{ - vg_lite_error_t error; - int32_t x, y, width, height; - uint32_t color32; - - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - /* Get rectangle. */ - x = (rectangle != NULL) ? rectangle->x : 0; - y = (rectangle != NULL) ? rectangle->y : 0; - width = (rectangle != NULL) ? rectangle->width : s_context.rtbuffer->width; - height = (rectangle != NULL) ? rectangle->height : s_context.rtbuffer->height; - - /* Compute the valid rectangle. */ - if (x < 0) - { - width += x; - x = 0; - } - if (y < 0) - { - height += y; - y = 0; - } - - if (s_context.scissor_enabled) - { - int right, bottom; - right = x + width; - bottom = y + height; - - /* Bounds check. */ - if ((s_context.scissor[0] >= x + width) || - (s_context.scissor[0] + s_context.scissor[2] <= x) || - (s_context.scissor[1] >= y + height) || - (s_context.scissor[1] + s_context.scissor[3] <= y)) - { - /* Do nothing. */ - return VG_LITE_SUCCESS; - } - /* Intersects the scissor and the rectangle. */ - x = (x > s_context.scissor[0] ? x : s_context.scissor[0]); - y = (y > s_context.scissor[1] ? y : s_context.scissor[1]); - right = (right < s_context.scissor[0] + s_context.scissor[2] ? right : s_context.scissor[0] + s_context.scissor[2]); - bottom = (bottom < s_context.scissor[1] + s_context.scissor[3] ? bottom : s_context.scissor[1] + s_context.scissor[3]); - width = right - x; - height = bottom - y; - } - - /* Get converted color when target is in L8 format. */ - color32 = (target->format == VG_LITE_L8) ? rgb_to_l(color) : color; - -#if VG_TARGET_FAST_CLEAR - if ((rectangle == NULL) || - ((x == 0) && (y == 0) && - (width == s_context.rtbuffer->width) && - (height == s_context.rtbuffer->height))) { - s_context.clearValue = color32; - convert_color(s_context.rtbuffer->format, color32, &color32, NULL); - clear_fc((uint32_t)color32); - } - else -#endif - { - /* Setup the command buffer. */ - if(s_context.premultiply_enabled) { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, 0x00000001)); - } else { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, 0x10000001)); - } - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A02, color32)); - VG_LITE_RETURN_ERROR(push_rectangle(&s_context, x, y, width, height)); - VG_LITE_RETURN_ERROR(flush_target()); - } - - /* Success. */ - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_blit(vg_lite_buffer_t * target, - vg_lite_buffer_t * source, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter) -{ - vg_lite_error_t error; - vg_lite_rectangle_t src_bbx, bounding_box, clip; - uint32_t imageMode; - uint32_t blend_mode; - uint32_t transparency_mode = 0; - vg_lite_blend_t forced_blending = blend; - uint32_t conversion = 0; - uint32_t tiled_source; - int32_t src_align_width; - uint32_t mul, div, align; -#if (VG_BLIT_WORKAROUND == 1) - vg_lite_matrix_t new_matrix; - vg_lite_buffer_t new_target; -#endif /* VG_BLIT_WORKAROUND */ - - /* Calculate bounding box */ - memset(&src_bbx, 0, sizeof(vg_lite_rectangle_t)); - memset(&clip, 0, sizeof(vg_lite_rectangle_t)); - src_bbx.width = source->width; - src_bbx.height = source->height; - if (s_context.scissor_enabled) { - clip.x = s_context.scissor[0]; - clip.y = s_context.scissor[1]; - clip.width = s_context.scissor[2]; - clip.height = s_context.scissor[3]; - } else { - clip.width = target->width; - clip.height = target->height; - } - transform_bounding_box(&src_bbx, matrix, &clip, &bounding_box, NULL); - -#if (VG_BLIT_WORKAROUND==1) - /* - * The blit output quality workaround works only for afine transformations - * because it is based on the process of cumulating translations into the - * matrix. This process is not possible for non-affine transformations, such - * as the perspective projections. - */ - if ((matrix->m[2][0] == 0) && (matrix->m[2][1] == 0)) { - /* - * Make a local copy of the transformation matrix in order not to mess - * up the user's matrix. - */ - memcpy(&new_matrix, matrix, sizeof(vg_lite_matrix_t)); - matrix = &new_matrix; - - config_new_target(target, source, matrix, &bounding_box, &new_target); - target = &new_target; - } -#endif /* VG_BLIT_WORKAROUND */ - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); - /* Check if the specified matrix has rotation or perspective. */ - if ( (matrix != NULL) - && ( (matrix->m[0][1] != 0.0f) - || (matrix->m[1][0] != 0.0f) - || (matrix->m[2][0] != 0.0f) - || (matrix->m[2][1] != 0.0f) - || (matrix->m[2][2] != 1.0f) - ) - && ( blend == VG_LITE_BLEND_NONE - || blend == VG_LITE_BLEND_SRC_IN - || blend == VG_LITE_BLEND_DST_IN - ) - ) { - if(vg_lite_query_feature(gcFEATURE_BIT_VG_BORDER_CULLING)) { - /* Mark that we have rotation. */ - transparency_mode = 0x8000; - }else - { - blend_mode = VG_LITE_BLEND_SRC_OVER; - } - - } - - /* Check whether L8 is supported or not. */ - if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { - conversion = 0x80000000; - } - - /* determine if source specify bytes are aligned */ - error = _check_source_aligned(source->format,source->stride); - if (error != VG_LITE_SUCCESS) { - return error; - } - - /* Determine image mode (NORMAL, NONE or MULTIPLY) depending on the color. */ - imageMode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; - blend_mode = convert_blend(forced_blending); - tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; - - /* Setup the command buffer. */ - if(!s_context.premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, 0x10000001 | imageMode | blend_mode | transparency_mode)); - } else { - /* enable pre-multiplied from VG to VGPE */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, 0x00000001 | imageMode | blend_mode | transparency_mode)); - } - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A02, color)); - get_format_bytes(source->format, &mul, &div, &align); - src_align_width = source->stride * div / mul; - - VG_LITE_RETURN_ERROR(set_interpolation_steps(target, src_align_width, source->height, matrix)); - - if(!s_context.premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { - if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A25, convert_source_format(source->format) | filter | conversion | 0x01000100)); - } else { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A25, convert_source_format(source->format) | filter | conversion | 0x00000100)); - } - } else { - /* enable pre-multiplied in imager unit */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A25, convert_source_format(source->format) | filter | conversion)); - } - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A27, 0)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A29, source->address)); - - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2B, source->stride | tiled_source)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2D, 0)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2F, src_align_width | (source->height << 16))); - VG_LITE_RETURN_ERROR(push_rectangle(&s_context, bounding_box.x, bounding_box.y, bounding_box.width, - bounding_box.height)); - error = flush_target(); - vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); - -#if DUMP_IMAGE - dump_img(source->memory, src_align_width, source->height, source->format); -#endif - - return error; -} - -vg_lite_error_t vg_lite_blit_rect(vg_lite_buffer_t * target, - vg_lite_buffer_t * source, - uint32_t * rect, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter) -{ - vg_lite_error_t error; - vg_lite_rectangle_t src_bbx, bounding_box, clip; - uint32_t imageMode; - int32_t src_align_width; - uint32_t mul, div, align; - uint32_t transparency_mode = 0; - uint32_t blend_mode; - vg_lite_blend_t forced_blending = blend; - uint32_t conversion = 0; - uint32_t tiled_source; - uint32_t rect_x = 0, rect_y = 0, rect_w = 0, rect_h = 0; - - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); - /* Check if the specified matrix has rotation or perspective. */ - if ( (matrix != NULL) - && ( (matrix->m[0][1] != 0.0f) - || (matrix->m[1][0] != 0.0f) - || (matrix->m[2][0] != 0.0f) - || (matrix->m[2][1] != 0.0f) - || (matrix->m[2][2] != 1.0f) - ) - && ( blend == VG_LITE_BLEND_NONE - || blend == VG_LITE_BLEND_SRC_IN - || blend == VG_LITE_BLEND_DST_IN - ) - ) { - if(vg_lite_query_feature(gcFEATURE_BIT_VG_BORDER_CULLING)) { - /* Mark that we have rotation. */ - transparency_mode = 0x8000; - }else - { - blend_mode = VG_LITE_BLEND_SRC_OVER; - } - - } - - /* Check whether L8 is supported or not. */ - if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { - conversion = 0x80000000; - } - - /* determine if source specify bytes are aligned */ - error = _check_source_aligned(source->format,source->stride); - if (error != VG_LITE_SUCCESS) { - return error; - } - get_format_bytes(source->format, &mul, &div, &align); - src_align_width = source->stride * div / mul; - memset(&src_bbx, 0, sizeof(vg_lite_rectangle_t)); - /* Set source region. */ - if (rect != NULL) { - rect_x = rect[0]; - rect_y = rect[1]; - rect_w = rect[2]; - rect_h = rect[3]; - - if ((rect_x > (uint32_t)src_align_width) || (rect_y > (uint32_t)source->height) || - (rect_w == 0) || (rect_h == 0)) - { - /*No intersection*/ - return VG_LITE_INVALID_ARGUMENT; - } - - if (rect_x + rect_w > (uint32_t)src_align_width) - { - rect_w = src_align_width - rect_x; - } - - if (rect_y + rect_h > (uint32_t)source->height) - { - rect_h = source->height - rect_y; - } - src_bbx.x = rect_x; - src_bbx.y = rect_y; - src_bbx.width = rect_w; - src_bbx.height = rect_h; - } - else { - rect_x = rect_y = 0; - rect_w = src_bbx.width = src_align_width; - rect_h = src_bbx.height = source->height; - } - - /* Calculate bounding box. */ - memset(&clip, 0, sizeof(vg_lite_rectangle_t)); - if (s_context.scissor_enabled) { - clip.x = s_context.scissor[0]; - clip.y = s_context.scissor[1]; - clip.width = s_context.scissor[2]; - clip.height = s_context.scissor[3]; - } else { - clip.x = clip.y = 0; - clip.width = s_context.rtbuffer->width; - clip.height = s_context.rtbuffer->height; - } - transform_bounding_box(&src_bbx, matrix, &clip, &bounding_box, NULL); - - /* Determine image mode (NORMAL, NONE or MULTIPLY) depending on the color. */ - imageMode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; - blend_mode = convert_blend(forced_blending); - tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; - - /* Setup the command buffer. */ - if(!s_context.premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, 0x10000001 | imageMode | blend_mode | transparency_mode)); - } else { - /* enable pre-multiplied from VG to VGPE */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, 0x00000001 | imageMode | blend_mode | transparency_mode)); - } - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A02, color)); - - VG_LITE_RETURN_ERROR(set_interpolation_steps(target, rect_w, rect_h, matrix)); - - if(!s_context.premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { - if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A25, convert_source_format(source->format) | filter | conversion | 0x01000100)); - } else { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A25, convert_source_format(source->format) | filter | conversion | 0x00000100)); - } - } else { - /* enable pre-multiplied in imager unit */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A25, convert_source_format(source->format) | filter | conversion)); - } - - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A27, 0)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A29, source->address)); - - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2B, source->stride | tiled_source)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2D, rect_x | (rect_y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2F, rect_w | (rect_h << 16))); - VG_LITE_RETURN_ERROR(push_rectangle(&s_context, bounding_box.x, bounding_box.y, bounding_box.width, - bounding_box.height)); - error = flush_target(); - vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); -#if DUMP_IMAGE - dump_img(source->memory, src_align_width, source->height, source->format); -#endif - - return error; -} -#else -vg_lite_error_t vg_lite_clear(vg_lite_buffer_t * target, - vg_lite_rectangle_t * rectangle, - vg_lite_color_t color) -{ - vg_lite_error_t error; - int32_t x, y, width, height; - uint32_t color32; - vg_lite_tls_t* tls; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - /* Get rectangle. */ - x = (rectangle != NULL) ? rectangle->x : 0; - y = (rectangle != NULL) ? rectangle->y : 0; - width = (rectangle != NULL) ? rectangle->width : tls->t_context.rtbuffer->width; - height = (rectangle != NULL) ? rectangle->height : tls->t_context.rtbuffer->height; - - /* Compute the valid rectangle. */ - if (x < 0) - { - width += x; - x = 0; - } - if (y < 0) - { - height += y; - y = 0; - } - - if (tls->t_context.scissor_enabled) - { - int right, bottom; - right = x + width; - bottom = y + height; - - /* Bounds check. */ - if ((tls->t_context.scissor[0] >= x + width) || - (tls->t_context.scissor[0] + tls->t_context.scissor[2] <= x) || - (tls->t_context.scissor[1] >= y + height) || - (tls->t_context.scissor[1] + tls->t_context.scissor[3] <= y)) - { - /* Do nothing. */ - return VG_LITE_SUCCESS; - } - /* Intersects the scissor and the rectangle. */ - x = (x > tls->t_context.scissor[0] ? x : tls->t_context.scissor[0]); - y = (y > tls->t_context.scissor[1] ? y : tls->t_context.scissor[1]); - right = (right < tls->t_context.scissor[0] + tls->t_context.scissor[2] ? right : tls->t_context.scissor[0] + tls->t_context.scissor[2]); - bottom = (bottom < tls->t_context.scissor[1] + tls->t_context.scissor[3] ? bottom : tls->t_context.scissor[1] + tls->t_context.scissor[3]); - width = right - x; - height = bottom - y; - } - - /* Get converted color when target is in L8 format. */ - color32 = (target->format == VG_LITE_L8) ? rgb_to_l(color) : color; - -#if VG_TARGET_FAST_CLEAR - if ((rectangle == NULL) || - ((x == 0) && (y == 0) && - (width == tls->t_context.rtbuffer->width) && - (height == tls->t_context.rtbuffer->height))) { - tls->t_context.clearValue = color32; - convert_color(tls->t_context.rtbuffer->format, color32, &color32, NULL); - clear_fc((uint32_t)color32); - } - else -#endif - { - /* Setup the command buffer. */ - if(tls->t_context.premultiply_enabled) { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x00000001)); - } else { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x10000001)); - } - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A02, color32)); - VG_LITE_RETURN_ERROR(push_rectangle(&tls->t_context, x, y, width, height)); - VG_LITE_RETURN_ERROR(flush_target()); - } - - /* Success. */ - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_blit(vg_lite_buffer_t * target, - vg_lite_buffer_t * source, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter) -{ - vg_lite_error_t error; - vg_lite_rectangle_t src_bbx, bounding_box, clip; - uint32_t imageMode; - uint32_t blend_mode; - uint32_t transparency_mode = 0; - vg_lite_blend_t forced_blending = blend; - uint32_t conversion = 0; - uint32_t tiled_source; - vg_lite_tls_t* tls; - int32_t src_align_width; - uint32_t mul, div, align; -#if (VG_BLIT_WORKAROUND == 1) - vg_lite_matrix_t new_matrix; - vg_lite_buffer_t new_target; -#endif /* VG_BLIT_WORKAROUND */ - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - /* Calculate bounding box */ - memset(&src_bbx, 0, sizeof(vg_lite_rectangle_t)); - memset(&clip, 0, sizeof(vg_lite_rectangle_t)); - src_bbx.width = source->width; - src_bbx.height = source->height; - if (tls->t_context.scissor_enabled) { - clip.x = tls->t_context.scissor[0]; - clip.y = tls->t_context.scissor[1]; - clip.width = tls->t_context.scissor[2]; - clip.height = tls->t_context.scissor[3]; - } else { - clip.width = target->width; - clip.height = target->height; - } - transform_bounding_box(&src_bbx, matrix, &clip, &bounding_box, NULL); - -#if (VG_BLIT_WORKAROUND==1) - /* - * The blit output quality workaround works only for afine transformations - * because it is based on the process of cumulating translations into the - * matrix. This process is not possible for non-affine transformations, such - * as the perspective projections. - */ - if ((matrix->m[2][0] == 0) && (matrix->m[2][1] == 0)) { - /* - * Make a local copy of the transformation matrix in order not to mess - * up the user's matrix. - */ - memcpy(&new_matrix, matrix, sizeof(vg_lite_matrix_t)); - matrix = &new_matrix; - - config_new_target(target, source, matrix, &bounding_box, &new_target); - target = &new_target; - } -#endif /* VG_BLIT_WORKAROUND */ - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); - /* Check if the specified matrix has rotation or perspective. */ - if ( (matrix != NULL) - && ( (matrix->m[0][1] != 0.0f) - || (matrix->m[1][0] != 0.0f) - || (matrix->m[2][0] != 0.0f) - || (matrix->m[2][1] != 0.0f) - || (matrix->m[2][2] != 1.0f) - ) - && ( blend == VG_LITE_BLEND_NONE - || blend == VG_LITE_BLEND_SRC_IN - || blend == VG_LITE_BLEND_DST_IN - ) - ) { - if(vg_lite_query_feature(gcFEATURE_BIT_VG_BORDER_CULLING)) { - /* Mark that we have rotation. */ - transparency_mode = 0x8000; - }else - { - blend_mode = VG_LITE_BLEND_SRC_OVER; - } - - } - - /* Check whether L8 is supported or not. */ - if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { - conversion = 0x80000000; - } - - /* determine if source specify bytes are aligned */ - error = _check_source_aligned(source->format,source->stride); - if (error != VG_LITE_SUCCESS) { - return error; - } - - /* Determine image mode (NORMAL, NONE or MULTIPLY) depending on the color. */ - imageMode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; - blend_mode = convert_blend(forced_blending); - tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; - - /* Setup the command buffer. */ - if(source->format >= VG_LITE_INDEX_1 && source->format <= VG_LITE_INDEX_8) - { - /* this task will use index format,set index_flag to 1. */ - tls->t_context.index_format = 1; - switch (source->format) { - case VG_LITE_INDEX_8: - if(tls->t_context.clut_dirty[3]){ - VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0B00, 256, tls->t_context.colors[3])); - tls->t_context.clut_dirty[3] = 0; - } - else - { - tls->t_context.clut_used[3] = 1; - } - break; - - case VG_LITE_INDEX_4: - if(tls->t_context.clut_dirty[2]){ - VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0AA0, 16, tls->t_context.colors[2])); - tls->t_context.clut_dirty[2] = 0; - } - else - { - tls->t_context.clut_used[2] = 1; - } - break; - - case VG_LITE_INDEX_2: - if(tls->t_context.clut_dirty[1]){ - VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0A9C, 4, tls->t_context.colors[1])); - tls->t_context.clut_dirty[1] = 0; - } - else - { - tls->t_context.clut_used[1] = 1; - } - break; - - default: - if(tls->t_context.clut_dirty[0]){ - VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0A98, 2, tls->t_context.colors[0])); - tls->t_context.clut_dirty[0] = 0; - } - else - { - tls->t_context.clut_used[0] = 1; - } - } - } - if(!tls->t_context.premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x10000001 | imageMode | blend_mode | transparency_mode)); - } else { - /* enable pre-multiplied from VG to VGPE */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x00000001 | imageMode | blend_mode | transparency_mode)); - } - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A02, color)); - get_format_bytes(source->format, &mul, &div, &align); - src_align_width = source->stride * div / mul; - VG_LITE_RETURN_ERROR(set_interpolation_steps(target, src_align_width, source->height, matrix)); - - if(!tls->t_context.premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { - if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A25, convert_source_format(source->format) | filter | conversion | 0x01000100)); - } else { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A25, convert_source_format(source->format) | filter | conversion | 0x00000100)); - } - } else { - /* enable pre-multiplied in imager unit */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A25, convert_source_format(source->format) | filter | conversion)); - } - - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A27, 0)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A29, source->address)); - - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2B, source->stride | tiled_source)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2D, 0)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2F, src_align_width | (source->height << 16))); - VG_LITE_RETURN_ERROR(push_rectangle(&tls->t_context, bounding_box.x, bounding_box.y, bounding_box.width, - bounding_box.height)); - error = flush_target(); - vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); - -#if DUMP_IMAGE - dump_img(source->memory, src_align_width, source->height, source->format); -#endif - - return error; -} - -vg_lite_error_t vg_lite_blit_rect(vg_lite_buffer_t * target, - vg_lite_buffer_t * source, - uint32_t * rect, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color, - vg_lite_filter_t filter) -{ - vg_lite_error_t error; - vg_lite_rectangle_t src_bbx, bounding_box, clip; - uint32_t imageMode; - uint32_t transparency_mode = 0; - uint32_t blend_mode; - vg_lite_blend_t forced_blending = blend; - uint32_t conversion = 0; - uint32_t tiled_source; - uint32_t rect_x = 0, rect_y = 0, rect_w = 0, rect_h = 0; - vg_lite_tls_t* tls; - int32_t src_align_width; - uint32_t mul, div, align; - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); - /* Check if the specified matrix has rotation or perspective. */ - if ( (matrix != NULL) - && ( (matrix->m[0][1] != 0.0f) - || (matrix->m[1][0] != 0.0f) - || (matrix->m[2][0] != 0.0f) - || (matrix->m[2][1] != 0.0f) - || (matrix->m[2][2] != 1.0f) - ) - && ( blend == VG_LITE_BLEND_NONE - || blend == VG_LITE_BLEND_SRC_IN - || blend == VG_LITE_BLEND_DST_IN - ) - ) { - if(vg_lite_query_feature(gcFEATURE_BIT_VG_BORDER_CULLING)) { - /* Mark that we have rotation. */ - transparency_mode = 0x8000; - }else - { - blend_mode = VG_LITE_BLEND_SRC_OVER; - } - - } - - /* Check whether L8 is supported or not. */ - if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { - conversion = 0x80000000; - } - - /* determine if source specify bytes are aligned */ - error = _check_source_aligned(source->format,source->stride); - if (error != VG_LITE_SUCCESS) { - return error; - } - get_format_bytes(source->format, &mul, &div, &align); - src_align_width = source->stride * div / mul; - memset(&src_bbx, 0, sizeof(vg_lite_rectangle_t)); - /* Set source region. */ - if (rect != NULL) { - rect_x = rect[0]; - rect_y = rect[1]; - rect_w = rect[2]; - rect_h = rect[3]; - - if ((rect_x > (uint32_t)src_align_width) || (rect_y > (uint32_t)source->height) || - (rect_w == 0) || (rect_h == 0)) - { - /*No intersection*/ - return VG_LITE_INVALID_ARGUMENT; - } - - if (rect_x + rect_w > (uint32_t)src_align_width) - { - rect_w = src_align_width - rect_x; - } - - if (rect_y + rect_h > (uint32_t)source->height) - { - rect_h = source->height - rect_y; - } - - src_bbx.x = rect_x; - src_bbx.y = rect_y; - src_bbx.width = rect_w; - src_bbx.height = rect_h; - } - else { - rect_x = rect_y = 0; - rect_w = src_bbx.width = src_align_width; - rect_h = src_bbx.height = source->height; - } - - /* Calculate bounding box. */ - memset(&clip, 0, sizeof(vg_lite_rectangle_t)); - if (tls->t_context.scissor_enabled) { - clip.x = tls->t_context.scissor[0]; - clip.y = tls->t_context.scissor[1]; - clip.width = tls->t_context.scissor[2]; - clip.height = tls->t_context.scissor[3]; - } else { - clip.x = clip.y = 0; - clip.width = tls->t_context.rtbuffer->width; - clip.height = tls->t_context.rtbuffer->height; - } - transform_bounding_box(&src_bbx, matrix, &clip, &bounding_box, NULL); - - /* Determine image mode (NORMAL, NONE or MULTIPLY) depending on the color. */ - imageMode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; - blend_mode = convert_blend(forced_blending); - tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; - - /* Setup the command buffer. */ - if(source->format >= VG_LITE_INDEX_1 && source->format <= VG_LITE_INDEX_8) - { - /* this task will use index format,set index_flag to 1. */ - tls->t_context.index_format = 1; - switch (source->format) { - case VG_LITE_INDEX_8: - if(tls->t_context.clut_dirty[3]){ - VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0B00, 256, tls->t_context.colors[3])); - tls->t_context.clut_dirty[3] = 0; - } - else - { - tls->t_context.clut_used[3] = 1; - } - break; - - case VG_LITE_INDEX_4: - if(tls->t_context.clut_dirty[2]){ - VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0AA0, 16, tls->t_context.colors[2])); - tls->t_context.clut_dirty[2] = 0; - } - else - { - tls->t_context.clut_used[2] = 1; - } - break; - - case VG_LITE_INDEX_2: - if(tls->t_context.clut_dirty[1]){ - VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0A9C, 4, tls->t_context.colors[1])); - tls->t_context.clut_dirty[1] = 0; - } - else - { - tls->t_context.clut_used[1] = 1; - } - break; - - default: - if(tls->t_context.clut_dirty[0]){ - VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0A98, 2, tls->t_context.colors[0])); - tls->t_context.clut_dirty[0] = 0; - } - else - { - tls->t_context.clut_used[0] = 1; - } - } - } - if(!tls->t_context.premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x10000001 | imageMode | blend_mode | transparency_mode)); - } else { - /* enable pre-multiplied from VG to VGPE */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x00000001 | imageMode | blend_mode | transparency_mode)); - } - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A02, color)); - - VG_LITE_RETURN_ERROR(set_interpolation_steps(target, rect_w, rect_h, matrix)); - - if(!tls->t_context.premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { - if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A25, convert_source_format(source->format) | filter | conversion | 0x01000100)); - } else { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A25, convert_source_format(source->format) | filter | conversion | 0x00000100)); - } - } else { - /* enable pre-multiplied in imager unit */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A25, convert_source_format(source->format) | filter | conversion)); - } - - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A27, 0)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A29, source->address)); - - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2B, source->stride | tiled_source)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2D, rect_x | (rect_y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2F, rect_w | (rect_h << 16))); - VG_LITE_RETURN_ERROR(push_rectangle(&tls->t_context, bounding_box.x, bounding_box.y, bounding_box.width, - bounding_box.height)); - error = flush_target(); - vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); -#if DUMP_IMAGE - dump_img(source->memory, src_align_width, source->height, source->format); -#endif - - return error; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -/* Program initial states for tessellation buffer. */ -static vg_lite_error_t program_tessellation(vg_lite_context_t *context) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t tessellation_size; -#if !defined(VG_DRIVER_SINGLE_THREAD) - uint32_t offset; -#endif /* not defined(VG_DRIVER_SINGLE_THREAD */ - - tessellation_size = ( context->tsbuffer.tessellation_buffer_size[2] - ? context->tsbuffer.tessellation_buffer_size[2] - : context->tsbuffer.tessellation_buffer_size[1] - ); -#if !defined(VG_DRIVER_SINGLE_THREAD) - offset = CMDBUF_OFFSET(*context); -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - - /* Since TS buffer won't change during runtime, we program it here in initialization. */ - /* Program tessellation buffer: input for VG module. */ - VG_LITE_RETURN_ERROR(push_state(context, 0x0A30, context->tsbuffer.tessellation_buffer_gpu[0])); /* Tessellation buffer address. */ - VG_LITE_RETURN_ERROR(push_state(context, 0x0A31, context->tsbuffer.tessellation_buffer_gpu[1])); /* L1 address of tessellation buffer. */ - VG_LITE_RETURN_ERROR(push_state(context, 0x0A32, context->tsbuffer.tessellation_buffer_gpu[2])); /* L2 address of tessellation buffer. */ - VG_LITE_RETURN_ERROR(push_state(context, 0x0A33, context->tsbuffer.tessellation_stride)); - /* Program tessellation control: for TS module. */ - VG_LITE_RETURN_ERROR(push_state(context, 0x0A35, context->tsbuffer.tessellation_buffer_gpu[0])); - VG_LITE_RETURN_ERROR(push_state(context, 0x0A36, context->tsbuffer.tessellation_buffer_gpu[1])); - VG_LITE_RETURN_ERROR(push_state(context, 0x0A37, context->tsbuffer.tessellation_buffer_gpu[2])); - VG_LITE_RETURN_ERROR(push_state(context, 0x0A38, context->tsbuffer.tessellation_stride)); - VG_LITE_RETURN_ERROR(push_state(context, 0x0A3A, context->tsbuffer.tessellation_width_height)); - - VG_LITE_RETURN_ERROR(push_state(context, 0x0A3D, tessellation_size / 64)); - -#if !defined(VG_DRIVER_SINGLE_THREAD) - /* Backup tessellation buffer states. */ - context->ts_init_used = 0; - context->ts_init_use = 0; - context->ts_dirty = 1; - memcpy(context->ts_record, (CMDBUF_BUFFER(*context) + offset), 80); - CMDBUF_OFFSET(*context) = 0; -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - - return error; -} - -#if defined(VG_DRIVER_SINGLE_THREAD) -vg_lite_error_t vg_lite_init(int32_t tessellation_width, - int32_t tessellation_height) -{ - vg_lite_error_t error; - vg_lite_kernel_initialize_t initialize; - - s_context.rtbuffer = (vg_lite_buffer_t *)malloc(sizeof(vg_lite_buffer_t)); - if(!s_context.rtbuffer) - return VG_LITE_OUT_OF_RESOURCES; - memset(s_context.rtbuffer, 0, sizeof(vg_lite_buffer_t)); - - if (tessellation_width <= 0) { - tessellation_width = 0; - tessellation_height = 0; - } - if (tessellation_height <= 0) { - tessellation_height = 0; - tessellation_width = 0; - } - tessellation_width = VG_LITE_ALIGN(tessellation_width, 16); - -#if VG_TARGET_FAST_CLEAR - vg_lite_get_product_info(NULL,&s_context.chip_id,&s_context.chip_rev); - vg_lite_get_register(0x30, &cid); - if(s_context.chip_id == 0x255 && s_context.chip_rev == 0x1311 && cid == 0x404) - { - tessellation_width = 64; - tessellation_height = 64; - } -#endif - - /* Allocate a command buffer and a tessellation buffer. */ - initialize.command_buffer_size = command_buffer_size; - initialize.tessellation_width = tessellation_width; - initialize.tessellation_height = tessellation_height; - initialize.context = &s_context.context; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_INITIALIZE, &initialize)); - - /* Save draw context. */ - s_context.capabilities = initialize.capabilities; - s_context.command_buffer[0] = (uint8_t *)initialize.command_buffer[0]; - s_context.command_buffer[1] = (uint8_t *)initialize.command_buffer[1]; - s_context.command_buffer_size = initialize.command_buffer_size; - s_context.command_offset[0] = 0; - s_context.command_offset[1] = 0; - - if ((tessellation_width > 0) && - (tessellation_height > 0)) - { - /* Set and Program Tessellation Buffer states. */ - s_context.tsbuffer.tessellation_buffer_gpu[0] = initialize.tessellation_buffer_gpu[0]; - s_context.tsbuffer.tessellation_buffer_gpu[1] = initialize.tessellation_buffer_gpu[1]; - s_context.tsbuffer.tessellation_buffer_gpu[2] = initialize.tessellation_buffer_gpu[2]; - s_context.tsbuffer.tessellation_buffer_logic[0] = initialize.tessellation_buffer_logic[0]; - s_context.tsbuffer.tessellation_buffer_logic[1] = initialize.tessellation_buffer_logic[1]; - s_context.tsbuffer.tessellation_buffer_logic[2] = initialize.tessellation_buffer_logic[2]; - s_context.tsbuffer.tessellation_stride = initialize.tessellation_stride; - s_context.tsbuffer.tessellation_width_height = initialize.tessellation_width_height; - s_context.tsbuffer.tessellation_buffer_size[0] = initialize.tessellation_buffer_size[0]; - s_context.tsbuffer.tessellation_buffer_size[1] = initialize.tessellation_buffer_size[1]; - s_context.tsbuffer.tessellation_buffer_size[2] = initialize.tessellation_buffer_size[2]; - s_context.tsbuffer.tessellation_shift = initialize.tessellation_shift; - - VG_LITE_RETURN_ERROR(program_tessellation(&s_context)); - } - - /* Fill feature table. */ - if (!s_ftable.ftflag){ - VG_LITE_RETURN_ERROR(fill_feature_table(s_ftable.ftable)); - } - -#if VG_TARGET_FAST_CLEAR - /* Reset the FAST_CLEAR buffer. */ - memset(&s_context.fcBuffer, 0, sizeof(s_context.fcBuffer)); - s_context.fcBuffer.format = VG_LITE_A8; - s_context.fcBuffer.height = 1; - s_context.clearValue = 0; -#endif - - /* Init scissor rect. */ - s_context.scissor[0] = - s_context.scissor[1] = - s_context.scissor[2] = - s_context.scissor[3] = 0; -#if DUMP_CAPTURE - _SetDumpFileInfo(); -#endif - -#if (VG_RENDER_TEXT==1) - vg_lite_text_init(); -#endif /* VG_RENDER_TEXT */ - - return VG_LITE_SUCCESS; -} -#else -vg_lite_error_t vg_lite_init(int32_t tessellation_width, - int32_t tessellation_height) -{ - vg_lite_error_t error; - vg_lite_kernel_initialize_t initialize; - vg_lite_tls_t* task_tls; - - task_tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(task_tls) - return VG_LITE_SUCCESS; - - task_tls = (vg_lite_tls_t *) vg_lite_os_malloc(sizeof(vg_lite_tls_t)); - if(!task_tls) - return VG_LITE_OUT_OF_RESOURCES; - memset(task_tls,0,sizeof(vg_lite_tls_t)); - error = (vg_lite_error_t)vg_lite_os_set_tls((void *) task_tls); - if(error != VG_LITE_SUCCESS) - return error; - - task_tls->t_context.rtbuffer = NULL; - - if (tessellation_width <= 0) { - tessellation_width = 0; - tessellation_height = 0; - } - if (tessellation_height <= 0) { - tessellation_height = 0; - tessellation_width = 0; - } - tessellation_width = VG_LITE_ALIGN(tessellation_width, 16); - - /* Allocate a command buffer and a tessellation buffer. */ - initialize.command_buffer_size = command_buffer_size; - initialize.context_buffer_size = CONTEXT_BUFFER_SIZE; - initialize.tessellation_width = tessellation_width; - initialize.tessellation_height = tessellation_height; - initialize.context = &task_tls->t_context.context; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_INITIALIZE, &initialize)); - - /* Save draw context. */ - task_tls->t_context.capabilities = initialize.capabilities; - task_tls->t_context.command_buffer[0] = (uint8_t *)initialize.command_buffer[0]; - task_tls->t_context.command_buffer[1] = (uint8_t *)initialize.command_buffer[1]; - task_tls->t_context.command_buffer_size = initialize.command_buffer_size; - task_tls->t_context.command_offset[0] = 0; - task_tls->t_context.command_offset[1] = 0; - task_tls->t_context.command_buffer_current = 0; - task_tls->t_context.context_buffer[0] = (uint8_t *)initialize.context_buffer[0]; - task_tls->t_context.context_buffer[1] = (uint8_t *)initialize.context_buffer[1]; - task_tls->t_context.context_buffer_size = initialize.context_buffer_size; - task_tls->t_context.context_buffer_offset[0] = 0; - task_tls->t_context.context_buffer_offset[1] = 0; - task_tls->t_context.start_offset = 0; - task_tls->t_context.end_offset = 0; - task_tls->t_context.ts_init = 0; - memset(task_tls->t_context.ts_record, 0, sizeof(task_tls->t_context.ts_record)); - - if ((tessellation_width > 0) && - (tessellation_height > 0)) - { - /* Set and Program Tessellation Buffer states. */ - task_tls->t_context.tsbuffer.tessellation_buffer_gpu[0] = initialize.tessellation_buffer_gpu[0]; - task_tls->t_context.tsbuffer.tessellation_buffer_gpu[1] = initialize.tessellation_buffer_gpu[1]; - task_tls->t_context.tsbuffer.tessellation_buffer_gpu[2] = initialize.tessellation_buffer_gpu[2]; - task_tls->t_context.tsbuffer.tessellation_buffer_logic[0] = initialize.tessellation_buffer_logic[0]; - task_tls->t_context.tsbuffer.tessellation_buffer_logic[1] = initialize.tessellation_buffer_logic[1]; - task_tls->t_context.tsbuffer.tessellation_buffer_logic[2] = initialize.tessellation_buffer_logic[2]; - task_tls->t_context.tsbuffer.tessellation_stride = initialize.tessellation_stride; - task_tls->t_context.tsbuffer.tessellation_width_height = initialize.tessellation_width_height; - task_tls->t_context.tsbuffer.tessellation_buffer_size[0] = initialize.tessellation_buffer_size[0]; - task_tls->t_context.tsbuffer.tessellation_buffer_size[1] = initialize.tessellation_buffer_size[1]; - task_tls->t_context.tsbuffer.tessellation_buffer_size[2] = initialize.tessellation_buffer_size[2]; - task_tls->t_context.tsbuffer.tessellation_shift = initialize.tessellation_shift; - - VG_LITE_RETURN_ERROR(program_tessellation(&task_tls->t_context)); - } - - VG_LITE_RETURN_ERROR(push_state(&task_tls->t_context, 0x0A00, 0x0)); - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_LOCK, NULL)); - /* Fill feature table. */ - if (!task_tls->t_context.s_ftable.ftflag){ - VG_LITE_RETURN_ERROR(fill_feature_table(task_tls->t_context.s_ftable.ftable)); - } - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_UNLOCK, NULL)); - -#if VG_TARGET_FAST_CLEAR - /* Reset the FAST_CLEAR buffer. */ - memset(&task_tls->t_context.fcBuffer, 0, sizeof(task_tls->t_context.fcBuffer)); - task_tls->t_context.fcBuffer.format = VG_LITE_A8; - task_tls->t_context.fcBuffer.height = 1; - task_tls->t_context.clearValue = 0; -#endif - - /* Init scissor rect. */ - task_tls->t_context.scissor[0] = - task_tls->t_context.scissor[1] = - task_tls->t_context.scissor[2] = - task_tls->t_context.scissor[3] = 0; -#if DUMP_CAPTURE - _SetDumpFileInfo(); -#endif - -#if (VG_RENDER_TEXT==1) - vg_lite_text_init(); -#endif /* VG_RENDER_TEXT */ - - return VG_LITE_SUCCESS; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -vg_lite_error_t vg_lite_set_draw_path_type(vg_lite_path_t * path,vg_lite_draw_path_type_t path_type) -{ - if(!path || (path_type > VG_LITE_DRAW_STROKE_PATH + 1)) - return VG_LITE_INVALID_ARGUMENT; - - path->path_type = path_type; - - return VG_LITE_SUCCESS; -} - -#if defined(VG_DRIVER_SINGLE_THREAD) -// added by MicroEJ -void __attribute__((weak)) vg_lite_draw_notify_render_area(uint32_t x, uint32_t y, uint32_t right, uint32_t bottom) -{ - /* - * Default implementation does nothing. Application can override this handler if it requires to be notified - * by the vglite rendering area. - */ - return; -} - -vg_lite_error_t vg_lite_draw(vg_lite_buffer_t * target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color) -{ - uint32_t blend_mode; - uint32_t format, quality, tiling, fill; - uint32_t tessellation_size; - vg_lite_error_t error; - int32_t dst_align_width; - uint32_t mul, div, align; - vg_lite_point_t point_min = {0}, point_max = {0}, temp = {0}; - int x, y, width, height; - uint8_t ts_is_fullscreen = 0; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_QUALITY_8X) && path->quality == VG_LITE_UPPER){ - return VG_LITE_NOT_SUPPORT; - } - - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - width = s_context.tsbuffer.tessellation_width_height & 0xFFFF; - height = s_context.tsbuffer.tessellation_width_height >> 16; - get_format_bytes(target->format, &mul, &div, &align); - dst_align_width = target->stride * div / mul; - if(width == 0 || height == 0) - return VG_LITE_NO_CONTEXT; - if ((dst_align_width <= width) && (target->height <= height)) - { - ts_is_fullscreen = 1; - point_min.x = 0; - point_min.y = 0; - point_max.x = dst_align_width; - point_max.y = target->height; - } - - if (ts_is_fullscreen == 0){ - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[1], matrix); - point_min = point_max = temp; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[1], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - if (point_min.x < 0) point_min.x = 0; - if (point_min.y < 0) point_min.y = 0; - if (point_max.x > dst_align_width) point_max.x = dst_align_width; - if (point_max.y > target->height) point_max.y = target->height; - - if (s_context.scissor_enabled) { - point_min.x = MAX(point_min.x, s_context.scissor[0]); - point_min.y = MAX(point_min.y, s_context.scissor[1]); - point_max.x = MIN(point_max.x, s_context.scissor[0] + s_context.scissor[2]); - point_max.y = MIN(point_max.y, s_context.scissor[1] + s_context.scissor[3]); - } - } - - /* Convert states into hardware values. */ - blend_mode = convert_blend(blend); - format = convert_path_format(path->format); - quality = convert_path_quality(path->quality); - tiling = (s_context.capabilities.cap.tiled == 2) ? 0x2000000 : 0; - fill = (fill_rule == VG_LITE_FILL_EVEN_ODD) ? 0x10 : 0; - tessellation_size = ( s_context.tsbuffer.tessellation_buffer_size[2] - ? s_context.tsbuffer.tessellation_buffer_size[2] - : s_context.tsbuffer.tessellation_buffer_size[1] - ); - - /* Setup the command buffer. */ - /* Program color register. */ - if(s_context.premultiply_enabled) { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, s_context.capabilities.cap.tiled | blend_mode)); - } else { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, 0x10000000 | s_context.capabilities.cap.tiled | blend_mode)); - } - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A02, color)); - /* Program tessellation control: for TS module. */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A34, 0x01000200 | format | quality | tiling | fill)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3B, 0x3F800000)); /* Path tessellation SCALE. */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3C, 0x00000000)); /* Path tessellation BIAS. */ - /* Program matrix. */ - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A40, (void *) &matrix->m[0][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A41, (void *) &matrix->m[0][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A42, (void *) &matrix->m[0][2])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A43, (void *) &matrix->m[1][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A44, (void *) &matrix->m[1][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A45, (void *) &matrix->m[1][2])); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - vglitemDUMP_BUFFER("path", path->uploaded.address, (uint8_t *)(path->uploaded.memory), 0, path->uploaded.bytes); - } - vglitemDUMP("@[memory 0x%08X 0x%08X]", s_context.tsbuffer.tessellation_buffer_gpu[0], s_context.tsbuffer.tessellation_buffer_size[0]); - /* Setup tessellation loop. */ - if((path->path_type & 0x1) == VG_LITE_DRAW_FILL_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&s_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&s_context, path->uploaded.address, path->uploaded.bytes)); -#if (DUMP_COMMAND) - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[0], 0); - - unsigned char* pt = (unsigned char*) memory.memory; - - for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) - { - if (i % 8 == 0) - fprintf(fp, "Command buffer: "); - - if (i % 4 == 0) - fprintf(fp, "0x"); - - for (int j = 3; j >= 0; --j) - fprintf(fp, "%02x", pt[i + j]); - - if ((i / 4 + 1) % 2 == 0) - fprintf(fp, ",\n"); - else - fprintf(fp, ", "); - } - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[return_offset], 0); - - fclose(fp); - fp = NULL; -#endif - } else { - push_data(&s_context, path->path_length, path->path); - } - } - } - } - /* Setup tessellation loop. */ - if(path->path_type == VG_LITE_DRAW_STROKE_PATH || path->path_type == VG_LITE_DRAW_FILL_STROKE_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&s_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&s_context, path->uploaded.address, path->uploaded.bytes)); -#if (DUMP_COMMAND) - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[0], 0); - - unsigned char* pt = (unsigned char*) memory.memory; - - for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) - { - if (i % 8 == 0) - fprintf(fp, "Command buffer: "); - - if (i % 4 == 0) - fprintf(fp, "0x"); - - for (int j = 3; j >= 0; --j) - fprintf(fp, "%02x", pt[i + j]); - - if ((i / 4 + 1) % 2 == 0) - fprintf(fp, ",\n"); - else - fprintf(fp, ", "); - } - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[return_offset], 0); - - fclose(fp); - fp = NULL; -#endif - } else { - format = convert_path_format(VG_LITE_FP32); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A34, 0x01000200 | format | quality | tiling | 0x0)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A02, path->stroke_color)); - push_data(&s_context, path->stroke_path_size, path->stroke_path_data); - } - } - } - } - - /* Notify rendering area (added by MicroEJ) */ - vg_lite_draw_notify_render_area(point_min.x, point_min.y, point_max.x, point_max.y); - - /* Finialize command buffer. */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A34, 0)); - return error; -} - -vg_lite_error_t vg_lite_close(void) -{ - vg_lite_error_t error; - vg_lite_kernel_terminate_t terminate; - -#if VG_TARGET_FAST_CLEAR - if (s_context.fcBuffer.handle != NULL) { - vg_lite_free(&s_context.fcBuffer); - } -#endif - - /* Termnate the draw context. */ - terminate.context = &s_context.context; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_TERMINATE, &terminate)); - - if(s_context.rtbuffer) - free(s_context.rtbuffer); - - submit_flag = 0; - - /* Reset the draw context. */ - _memset(&s_context, 0, sizeof(s_context)); - - /* Reset the s_ftable. */ - _memset(&s_ftable, 0, sizeof(s_ftable)); - - s_context.init = 0; -#if DUMP_CAPTURE - _SetDumpFileInfo(); -#endif - return VG_LITE_SUCCESS; -} -#else -vg_lite_error_t vg_lite_draw(vg_lite_buffer_t * target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_blend_t blend, - vg_lite_color_t color) -{ - uint32_t blend_mode; - uint32_t format, quality, tiling, fill; - uint32_t tessellation_size; - vg_lite_error_t error; - vg_lite_point_t point_min = {0}, point_max = {0}, temp = {0}; - int x, y, width, height; - uint8_t ts_is_fullscreen = 0; -#if DUMP_COMMAND - uint32_t return_offset = 0; - vg_lite_kernel_allocate_t memory; -#endif - vg_lite_tls_t* tls; - int32_t dst_align_width; - uint32_t mul, div, align; - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_QUALITY_8X) && path->quality == VG_LITE_UPPER){ - return VG_LITE_NOT_SUPPORT; - } - - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - width = tls->t_context.tsbuffer.tessellation_width_height & 0xFFFF; - height = tls->t_context.tsbuffer.tessellation_width_height >> 16; - get_format_bytes(target->format, &mul, &div, &align); - dst_align_width = target->stride * div / mul; - if(width == 0 || height == 0) - return VG_LITE_NO_CONTEXT; - if ((dst_align_width <= width) && (target->height <= height)) - { - ts_is_fullscreen = 1; - point_min.x = 0; - point_min.y = 0; - point_max.x = dst_align_width; - point_max.y = target->height; - } - - if (ts_is_fullscreen == 0){ - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[1], matrix); - point_min = point_max = temp; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[1], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - if (point_min.x < 0) point_min.x = 0; - if (point_min.y < 0) point_min.y = 0; - if (point_max.x > dst_align_width) point_max.x = dst_align_width; - if (point_max.y > target->height) point_max.y = target->height; - - if (tls->t_context.scissor_enabled) { - point_min.x = MAX(point_min.x, tls->t_context.scissor[0]); - point_min.y = MAX(point_min.y, tls->t_context.scissor[1]); - point_max.x = MIN(point_max.x, tls->t_context.scissor[0] + tls->t_context.scissor[2]); - point_max.y = MIN(point_max.y, tls->t_context.scissor[1] + tls->t_context.scissor[3]); - } - } - - /* Convert states into hardware values. */ - blend_mode = convert_blend(blend); - format = convert_path_format(path->format); - quality = convert_path_quality(path->quality); - tiling = (tls->t_context.capabilities.cap.tiled == 2) ? 0x2000000 : 0; - fill = (fill_rule == VG_LITE_FILL_EVEN_ODD) ? 0x10 : 0; - tessellation_size = ( tls->t_context.tsbuffer.tessellation_buffer_size[2] - ? tls->t_context.tsbuffer.tessellation_buffer_size[2] - : tls->t_context.tsbuffer.tessellation_buffer_size[1] - ); - - if(tls->t_context.ts_dirty){ - memcpy(CMDBUF_BUFFER(tls->t_context) + CMDBUF_OFFSET(tls->t_context), tls->t_context.ts_record, 80); - CMDBUF_OFFSET(tls->t_context) += 80; - tls->t_context.ts_dirty = 0; - tls->t_context.ts_init_used = 1; - } - else - { - tls->t_context.ts_init_use = 1; - } - - /* Setup the command buffer. */ - /* Program color register. */ - if(tls->t_context.premultiply_enabled) { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, tls->t_context.capabilities.cap.tiled | blend_mode)); - } else { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x10000000 | tls->t_context.capabilities.cap.tiled | blend_mode)); - } - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A02, color)); - /* Program tessellation control: for TS module. */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A34, 0x01000200 | format | quality | tiling | fill)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3B, 0x3F800000)); /* Path tessellation SCALE. */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3C, 0x00000000)); /* Path tessellation BIAS. */ - /* Program matrix. */ - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A40, (void *) &matrix->m[0][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A41, (void *) &matrix->m[0][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A42, (void *) &matrix->m[0][2])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A43, (void *) &matrix->m[1][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A44, (void *) &matrix->m[1][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A45, (void *) &matrix->m[1][2])); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - vglitemDUMP_BUFFER("path", path->uploaded.address, (uint8_t *)(path->uploaded.memory), 0, path->uploaded.bytes); - } - vglitemDUMP("@[memory 0x%08X 0x%08X]", tls->t_context.tsbuffer.tessellation_buffer_gpu[0], tls->t_context.tsbuffer.tessellation_buffer_size[0]); - /* Setup tessellation loop. */ - if((path->path_type & 0x1) == VG_LITE_DRAW_FILL_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&tls->t_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&tls->t_context, path->uploaded.address, path->uploaded.bytes)); -#if (DUMP_COMMAND) - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[0], 0); - - unsigned char* pt = (unsigned char*) memory.memory; - - for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) - { - if (i % 8 == 0) - fprintf(fp, "Command buffer: "); - - if (i % 4 == 0) - fprintf(fp, "0x"); - - for (int j = 3; j >= 0; --j) - fprintf(fp, "%02x", pt[i + j]); - - if ((i / 4 + 1) % 2 == 0) - fprintf(fp, ",\n"); - else - fprintf(fp, ", "); - } - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[return_offset], 0); - - fclose(fp); - fp = NULL; -#endif - } else { - push_data(&tls->t_context, path->path_length, path->path); - } - } - } - } - /* Setup tessellation loop. */ - if(path->path_type == VG_LITE_DRAW_STROKE_PATH || path->path_type == VG_LITE_DRAW_FILL_STROKE_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&tls->t_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&tls->t_context, path->uploaded.address, path->uploaded.bytes)); -#if (DUMP_COMMAND) - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[0], 0); - - unsigned char* pt = (unsigned char*) memory.memory; - - for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) - { - if (i % 8 == 0) - fprintf(fp, "Command buffer: "); - - if (i % 4 == 0) - fprintf(fp, "0x"); - - for (int j = 3; j >= 0; --j) - fprintf(fp, "%02x", pt[i + j]); - - if ((i / 4 + 1) % 2 == 0) - fprintf(fp, ",\n"); - else - fprintf(fp, ", "); - } - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[return_offset], 0); - - fclose(fp); - fp = NULL; -#endif - } else { - format = convert_path_format(VG_LITE_FP32); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A34, 0x01000200 | format | quality | tiling | 0x0)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A02, path->stroke_color)); - push_data(&tls->t_context, path->stroke_path_size, path->stroke_path_data); - } - } - } - } - - /* Finialize command buffer. */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A34, 0)); - VG_LITE_RETURN_ERROR(flush_target()); - tls->t_context.ts_init = 1; - return error; -} - -vg_lite_error_t vg_lite_close(void) -{ - vg_lite_error_t error; - vg_lite_kernel_terminate_t terminate; - vg_lite_tls_t* tls; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - -#if VG_TARGET_FAST_CLEAR - if (tls->t_context.fcBuffer.handle != NULL) { - vg_lite_free(&tls->t_context.fcBuffer); - } -#endif - - /* Termnate the draw context. */ - terminate.context = &tls->t_context.context; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_TERMINATE, &terminate)); - - /* Reset the draw context. */ - if(tls->t_context.colors){ - free(tls->t_context.colors[0]); - free(tls->t_context.colors[1]); - free(tls->t_context.colors[2]); - free(tls->t_context.colors[3]); - } - - _memset(&tls->t_context, 0, sizeof(tls->t_context)); - -#if DUMP_CAPTURE - _SetDumpFileInfo(); -#endif - - vg_lite_os_reset_tls(); - vg_lite_os_free((void *) tls); - return VG_LITE_SUCCESS; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -/* Handle tiled & yuv allocation. Currently including NV12, ANV12, YV12, YV16, NV16, YV24. */ -static vg_lite_error_t _allocate_tiled_yuv_planar(vg_lite_buffer_t *buffer) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t yplane_size = 0; - vg_lite_kernel_allocate_t allocate, uv_allocate, v_allocate; - - if ((buffer->format < VG_LITE_NV12) || (buffer->format > VG_LITE_ANV12_TILED) - || (buffer->format == VG_LITE_AYUY2) || (buffer->format == VG_LITE_YUY2_TILED)) - { - return error; - } - - /* For NV12, there are 2 planes (Y, UV); - For ANV12, there are 3 planes (Y, UV, Alpha). - Each plane must be aligned by (4, 8). - Then Y plane must be aligned by (8, 8). - For YVxx, there are 3 planes (Y, U, V). - YV12 is similar to NV12, both YUV420 format. - YV16 and NV16 are YUV422 format. - YV24 is YUV444 format. - */ - buffer->width = VG_LITE_ALIGN(buffer->width, 8); - buffer->height = VG_LITE_ALIGN(buffer->height, 8); - buffer->stride = VG_LITE_ALIGN(buffer->width, 128); - - switch (buffer->format) { - case VG_LITE_NV12: - case VG_LITE_ANV12: - case VG_LITE_NV12_TILED: - case VG_LITE_ANV12_TILED: - buffer->yuv.uv_stride = buffer->stride; - buffer->yuv.alpha_stride = buffer->stride; - buffer->yuv.uv_height = buffer->height / 2; - break; - - case VG_LITE_NV16: - buffer->yuv.uv_stride = buffer->stride; - buffer->yuv.uv_height = buffer->height; - break; - - case VG_LITE_YV12: - buffer->yuv.uv_stride = - buffer->yuv.v_stride = buffer->stride / 2; - buffer->yuv.uv_height = - buffer->yuv.v_height = buffer->height / 2; - break; - - case VG_LITE_YV16: - buffer->yuv.uv_stride = - buffer->yuv.v_stride = buffer->stride; - buffer->yuv.uv_height = - buffer->yuv.v_height = buffer->height / 2; - break; - - case VG_LITE_YV24: - buffer->yuv.uv_stride = - buffer->yuv.v_stride = buffer->stride; - buffer->yuv.uv_height = - buffer->yuv.v_height = buffer->height; - break; - - default: - return error; - } - - yplane_size = buffer->stride * buffer->height; - - /* Allocate buffer memory: Y. */ - allocate.bytes = yplane_size; - allocate.contiguous = 1; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); - - /* Save the allocation. */ - buffer->handle = allocate.memory_handle; - buffer->memory = allocate.memory; - buffer->address = allocate.memory_gpu; - - if ((buffer->format == VG_LITE_NV12) || (buffer->format == VG_LITE_ANV12) - || (buffer->format == VG_LITE_NV16) || (buffer->format == VG_LITE_NV12_TILED) - || (buffer->format == VG_LITE_ANV12_TILED)) { - /* Allocate buffer memory: UV. */ - uv_allocate.bytes = buffer->yuv.uv_stride * buffer->yuv.uv_height; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &uv_allocate)); - buffer->yuv.uv_handle = uv_allocate.memory_handle; - buffer->yuv.uv_memory = uv_allocate.memory; - buffer->yuv.uv_planar = uv_allocate.memory_gpu; - - if ((buffer->format == VG_LITE_ANV12) || (buffer->format == VG_LITE_ANV12_TILED)) { - uv_allocate.bytes = yplane_size; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &uv_allocate)); - buffer->yuv.alpha_planar = uv_allocate.memory_gpu; - } - } else { - /* Allocate buffer memory: U, V. */ - uv_allocate.bytes = buffer->yuv.uv_stride * buffer->yuv.uv_height; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &uv_allocate)); - buffer->yuv.uv_handle = uv_allocate.memory_handle; - buffer->yuv.uv_memory = uv_allocate.memory; - buffer->yuv.uv_planar = uv_allocate.memory_gpu; - - v_allocate.bytes = buffer->yuv.v_stride * buffer->yuv.v_height; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &v_allocate)); - buffer->yuv.v_handle = v_allocate.memory_handle; - buffer->yuv.v_memory = v_allocate.memory; - buffer->yuv.v_planar = v_allocate.memory_gpu; - } - - return error; -} - -#if defined(VG_DRIVER_SINGLE_THREAD) -vg_lite_error_t vg_lite_allocate(vg_lite_buffer_t * buffer) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_kernel_allocate_t allocate; - - /* Reset planar. */ - buffer->yuv.uv_planar = - buffer->yuv.v_planar = - buffer->yuv.alpha_planar = 0; - - /* Align height in case format is tiled. */ - if (buffer->format >= VG_LITE_YUY2 && buffer->format <= VG_LITE_NV16) { - buffer->height = VG_LITE_ALIGN(buffer->height, 4); - buffer->yuv.swizzle = VG_LITE_SWIZZLE_UV; - } - - if (buffer->format >= VG_LITE_YUY2_TILED && buffer->format <= VG_LITE_AYUY2_TILED) { - buffer->height = VG_LITE_ALIGN(buffer->height, 4); - buffer->tiled = VG_LITE_TILED; - buffer->yuv.swizzle = VG_LITE_SWIZZLE_UV; - } - - if ((buffer->format >= VG_LITE_NV12 && buffer->format <= VG_LITE_ANV12_TILED - && buffer->format != VG_LITE_AYUY2 && buffer->format != VG_LITE_YUY2_TILED)) { - _allocate_tiled_yuv_planar(buffer); - } - else { - /* Driver need compute the stride always with RT500 project. */ - uint32_t mul, div, align; - get_format_bytes(buffer->format, &mul, &div, &align); - vg_lite_get_product_info(NULL,&s_context.chip_id,NULL); - buffer->stride = VG_LITE_ALIGN((buffer->width * mul / div), align); - - /* Allocate the buffer. */ - allocate.bytes = buffer->stride * buffer->height; -#if VG_TARGET_FAST_CLEAR - allocate.bytes = VG_LITE_ALIGN(allocate.bytes, 64); -#endif - allocate.contiguous = 1; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); - - /* Save the buffer allocation. */ - buffer->handle = allocate.memory_handle; - buffer->memory = allocate.memory; - buffer->address = allocate.memory_gpu; - - if ((buffer->format == VG_LITE_AYUY2) || (buffer->format == VG_LITE_AYUY2_TILED)) { - allocate.bytes = buffer->stride * buffer->height; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); - buffer->yuv.alpha_planar = allocate.memory_gpu; - } - - } - - return VG_LITE_SUCCESS; -} -#else -vg_lite_error_t vg_lite_allocate(vg_lite_buffer_t * buffer) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_kernel_allocate_t allocate; - - /* Reset planar. */ - buffer->yuv.uv_planar = - buffer->yuv.v_planar = - buffer->yuv.alpha_planar = 0; - - /* Align height in case format is tiled. */ - if (buffer->format >= VG_LITE_YUY2 && buffer->format <= VG_LITE_NV16) { - buffer->height = VG_LITE_ALIGN(buffer->height, 4); - buffer->yuv.swizzle = VG_LITE_SWIZZLE_UV; - } - - if (buffer->format >= VG_LITE_YUY2_TILED && buffer->format <= VG_LITE_AYUY2_TILED) { - buffer->height = VG_LITE_ALIGN(buffer->height, 4); - buffer->tiled = VG_LITE_TILED; - buffer->yuv.swizzle = VG_LITE_SWIZZLE_UV; - } - - if ((buffer->format >= VG_LITE_NV12 && buffer->format <= VG_LITE_ANV12_TILED - && buffer->format != VG_LITE_AYUY2 && buffer->format != VG_LITE_YUY2_TILED)) { - _allocate_tiled_yuv_planar(buffer); - } - else { - /* Driver need compute the stride always with RT500 project. */ - uint32_t mul, div, align; - vg_lite_tls_t* tls; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - get_format_bytes(buffer->format, &mul, &div, &align); - vg_lite_get_product_info(NULL,&tls->t_context.chip_id,NULL); - buffer->stride = VG_LITE_ALIGN((buffer->width * mul / div), align); - - /* Allocate the buffer. */ - allocate.bytes = buffer->stride * buffer->height; -#if VG_TARGET_FAST_CLEAR - allocate.bytes = VG_LITE_ALIGN(allocate.bytes, 64); -#endif - allocate.contiguous = 1; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); - - /* Save the buffer allocation. */ - buffer->handle = allocate.memory_handle; - buffer->memory = allocate.memory; - buffer->address = allocate.memory_gpu; - - if ((buffer->format == VG_LITE_AYUY2) || (buffer->format == VG_LITE_AYUY2_TILED)) { - allocate.bytes = buffer->stride * buffer->height; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &allocate)); - buffer->yuv.alpha_planar = allocate.memory_gpu; - } - - } - - return VG_LITE_SUCCESS; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -#if defined(VG_DRIVER_SINGLE_THREAD) -vg_lite_error_t vg_lite_free(vg_lite_buffer_t * buffer) -{ - vg_lite_error_t error; - vg_lite_kernel_free_t free, uv_free, v_free; - - if(buffer == NULL) - return VG_LITE_INVALID_ARGUMENT; - if (!(memcmp(s_context.rtbuffer,buffer,sizeof(vg_lite_buffer_t))) ) { - if (VG_LITE_SUCCESS == submit(&s_context)) { - VG_LITE_RETURN_ERROR(stall(&s_context, 0, ~0)); - } - vglitemDUMP("@[swap 0x%08X %dx%d +%u]", - s_context.rtbuffer->address, - s_context.rtbuffer->width, s_context.rtbuffer->height, - s_context.rtbuffer->stride); - vglitemDUMP_BUFFER( - "framebuffer", - s_context.rtbuffer->address,s_context.rtbuffer->memory, - 0, - s_context.rtbuffer->stride*(s_context.rtbuffer->height)); - - memset(s_context.rtbuffer, 0, sizeof(vg_lite_buffer_t)); - } - - if (buffer->yuv.uv_planar) { - /* Free UV(U) planar buffer. */ - uv_free.memory_handle = buffer->yuv.uv_handle; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &uv_free)); - - /* Mark the buffer as freed. */ - buffer->yuv.uv_handle = NULL; - buffer->yuv.uv_memory = NULL; - } - - if (buffer->yuv.v_planar) { - /* Free V planar buffer. */ - v_free.memory_handle = buffer->yuv.v_handle; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &v_free)); - - /* Mark the buffer as freed. */ - buffer->yuv.v_handle = NULL; - buffer->yuv.v_memory = NULL; - } - - /* Make sure we have a valid memory handle. */ - if (buffer->handle == NULL) { - return VG_LITE_INVALID_ARGUMENT; - } - - /* Free the buffer. */ - free.memory_handle = buffer->handle; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &free)); - - /* Mark the buffer as freed. */ - buffer->handle = NULL; - buffer->memory = NULL; - - return VG_LITE_SUCCESS; -} -#else -vg_lite_error_t vg_lite_free(vg_lite_buffer_t * buffer) -{ - vg_lite_error_t error; - vg_lite_kernel_free_t free, uv_free, v_free; - vg_lite_tls_t* tls; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - if(buffer == NULL) - return VG_LITE_INVALID_ARGUMENT; - if (tls->t_context.rtbuffer == buffer && !(memcmp(tls->t_context.rtbuffer,buffer,sizeof(vg_lite_buffer_t))) ) { - if (VG_LITE_SUCCESS == submit(&tls->t_context)) { - VG_LITE_RETURN_ERROR(stall(&tls->t_context, 0)); - } - vglitemDUMP("@[swap 0x%08X %dx%d +%u]", - tls->t_context.rtbuffer->address, - tls->t_context.rtbuffer->width, tls->t_context.rtbuffer->height, - tls->t_context.rtbuffer->stride); - vglitemDUMP_BUFFER( - "framebuffer", - tls->t_context.rtbuffer->address,tls->t_context.rtbuffer->memory, - 0, - tls->t_context.rtbuffer->stride*(tls->t_context.rtbuffer->height)); - - memset(tls->t_context.rtbuffer, 0, sizeof(vg_lite_buffer_t)); - } - - if (buffer->yuv.uv_planar) { - /* Free UV(U) planar buffer. */ - uv_free.memory_handle = buffer->yuv.uv_handle; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &uv_free)); - - /* Mark the buffer as freed. */ - buffer->yuv.uv_handle = NULL; - buffer->yuv.uv_memory = NULL; - } - - if (buffer->yuv.v_planar) { - /* Free V planar buffer. */ - v_free.memory_handle = buffer->yuv.v_handle; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &v_free)); - - /* Mark the buffer as freed. */ - buffer->yuv.v_handle = NULL; - buffer->yuv.v_memory = NULL; - } - - /* Make sure we have a valid memory handle. */ - if (buffer->handle == NULL) { - return VG_LITE_INVALID_ARGUMENT; - } - - /* Free the buffer. */ - free.memory_handle = buffer->handle; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &free)); - - /* Mark the buffer as freed. */ - buffer->handle = NULL; - buffer->memory = NULL; - - return VG_LITE_SUCCESS; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -vg_lite_error_t vg_lite_map(vg_lite_buffer_t * buffer) -{ - vg_lite_error_t error; - vg_lite_kernel_map_t map; - - /* We either need a logical or physical address. */ - if (buffer->memory == NULL && buffer->address == 0) { - return VG_LITE_INVALID_ARGUMENT; - } - - /* Check if we need to compute the stride. Usually map a pre-allocated memory, so the stride - usually should be set*/ - if (buffer->stride == 0) { - uint32_t mul, div, align; - get_format_bytes(buffer->format, &mul, &div, &align); - /* Compute the stride to be aligned. */ - buffer->stride = VG_LITE_ALIGN((buffer->width * mul / div), align); - } - - /* Map the buffer. */ - map.bytes = buffer->stride * buffer->height; - map.logical = buffer->memory; - map.physical = buffer->address; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_MAP, &map)); - - /* Save the buffer allocation. */ - buffer->handle = map.memory_handle; - buffer->address = map.memory_gpu; - - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_unmap(vg_lite_buffer_t * buffer) -{ - vg_lite_error_t error; - vg_lite_kernel_unmap_t unmap; - - /* Make sure we have a valid memory handle. */ - if (buffer->handle == NULL) { - return VG_LITE_INVALID_ARGUMENT; - } - - /* Unmap the buffer. */ - unmap.memory_handle = buffer->handle; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_UNMAP, &unmap)); - - /* Mark the buffer as freed. */ - buffer->handle = NULL; - - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_get_register(uint32_t address, uint32_t * result) -{ - vg_lite_error_t error; - vg_lite_kernel_info_t data; - - /* Get input register address. */ - data.addr = address; - - /* Get register info. */ - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_CHECK, &data)); - - /* Return register info. */ - *result = data.reg; - - return VG_LITE_SUCCESS; -} - -void vg_lite_get_info(vg_lite_info_t *info) -{ - if (info != NULL) - { - info->api_version = VGLITE_API_VERSION_2_0; - info->header_version = VGLITE_HEADER_VERSION; - info->release_version = VGLITE_RELEASE_VERSION; - info->reserved = 0; - } -} - -uint32_t vg_lite_get_product_info(char *name, uint32_t *chip_id, uint32_t *chip_rev) -{ - const char *product_name = "GCNanoLiteV"; - uint32_t name_len; - uint32_t rev = 0, id = 0; - - vg_lite_get_register(0x24, &rev); - vg_lite_get_register(0x20, &id); - - name_len = strlen(product_name) + 1; - if (name != NULL) - { - memcpy(name, product_name, name_len); - } - - if (chip_id != NULL) - { - *chip_id = id; - } - - if (chip_rev != NULL) - { - *chip_rev = rev; - } - return name_len; -} - -#if defined(VG_DRIVER_SINGLE_THREAD) -uint32_t vg_lite_query_feature(vg_lite_feature_t feature) -{ - uint32_t result; - - if (feature < gcFEATURE_COUNT) - result = s_ftable.ftable[feature]; - else - result = 0; - - return result; -} - -vg_lite_error_t vg_lite_finish() -{ - vg_lite_error_t error; - - /* Return if there is nothing to submit. */ - if (CMDBUF_OFFSET(s_context) == 0) - { - if(submit_flag) - VG_LITE_RETURN_ERROR(stall(&s_context, 0, (uint32_t)~0)); - return VG_LITE_SUCCESS; - } - - /* Flush is moved from each draw to here. */ - VG_LITE_RETURN_ERROR(flush_target()); - VG_LITE_RETURN_ERROR(submit(&s_context)); - VG_LITE_RETURN_ERROR(stall(&s_context, 0, (uint32_t)~0)); - -#if VG_TARGET_FAST_CLEAR - /*Only used in cmodel/fpga. In final SOC this SW FC decoder should be removed. */ - if (s_context.rtbuffer != NULL) { -#if VG_TARGET_FC_DUMP - fc_buf_dump(s_context.rtbuffer, &s_context.fcBuffer); -#endif /* VG_TARGET_FC_DUMP */ - } -#endif - - CMDBUF_SWAP(s_context); - /* Reset command buffer. */ - CMDBUF_OFFSET(s_context) = 0; - - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_flush(void) -{ - vg_lite_error_t error; - - /* Return if there is nothing to submit. */ - if (CMDBUF_OFFSET(s_context) == 0) - return VG_LITE_SUCCESS; - - /* Wait if GPU has not completed previous CMD buffer */ - if (submit_flag) - { - VG_LITE_RETURN_ERROR(stall(&s_context, 0, (uint32_t)~0)); - } - - /* Submit the current command buffer. */ - VG_LITE_RETURN_ERROR(flush_target()); - VG_LITE_RETURN_ERROR(submit(&s_context)); - CMDBUF_SWAP(s_context); - /* Reset command buffer. */ - CMDBUF_OFFSET(s_context) = 0; - - return VG_LITE_SUCCESS; -} -#else -uint32_t vg_lite_query_feature(vg_lite_feature_t feature) -{ - uint32_t result; - vg_lite_tls_t* tls; - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return 0; - - if (feature < gcFEATURE_COUNT) - result = tls->t_context.s_ftable.ftable[feature]; - else - result = 0; - - return result; -} - -vg_lite_error_t vg_lite_finish() -{ - vg_lite_error_t error; - vg_lite_tls_t* tls; - uint32_t command_id, index; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - command_id = CMDBUF_INDEX(tls->t_context); - index = command_id ? 0 : 1; - - if (CMDBUF_OFFSET(tls->t_context) <= 8){ - /* Return if there is nothing to submit. */ - if (!CMDBUF_IN_QUEUE(&tls->t_context.context, 0) && !CMDBUF_IN_QUEUE(&tls->t_context.context, 1) ) - return VG_LITE_SUCCESS; - /* This frame has unfinished command. */ - else if(CMDBUF_IN_QUEUE(&tls->t_context.context, index)) - { - CMDBUF_SWAP(tls->t_context); - VG_LITE_RETURN_ERROR(stall(&tls->t_context, 0)); - } - /* This frame has unfinished command. */ - else if(CMDBUF_IN_QUEUE(&tls->t_context.context, command_id)) - { - VG_LITE_RETURN_ERROR(stall(&tls->t_context, 0)); - } - CMDBUF_OFFSET(tls->t_context) = 0; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x0)); - return VG_LITE_SUCCESS; - } - else - { - /* Flush is moved from each draw to here. */ - VG_LITE_RETURN_ERROR(flush_target()); - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_LOCK, NULL)); - /* if context have been switched and this task need use index. */ - VG_LITE_RETURN_ERROR(update_context_buffer()); - VG_LITE_RETURN_ERROR(submit(&tls->t_context)); - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_UNLOCK, NULL)); - VG_LITE_RETURN_ERROR(stall(&tls->t_context, 0)); - } - -#if VG_TARGET_FAST_CLEAR - /*Only used in cmodel/fpga. In final SOC this SW FC decoder should be removed. */ - if (tls->t_context.rtbuffer != NULL) { -#if VG_TARGET_FC_DUMP - fc_buf_dump(tls->t_context.rtbuffer, &tls->t_context.fcBuffer); -#endif /* VG_TARGET_FC_DUMP */ - } -#endif - - CMDBUF_SWAP(tls->t_context); - CMDBUF_OFFSET(tls->t_context) = 0; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x0)); - tls->t_context.ts_init_used = 0; - tls->t_context.ts_init_use = 0; - tls->t_context.ts_init = 0; - - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_flush(void) -{ - vg_lite_error_t error; - vg_lite_tls_t* tls; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - /* Return if there is nothing to submit. */ - if (CMDBUF_OFFSET(tls->t_context) == 0) - return VG_LITE_SUCCESS; - - /* Submit the current command buffer. */ - VG_LITE_RETURN_ERROR(flush_target()); - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_LOCK, NULL)); - /* if context have been switched and this task need use index. */ - VG_LITE_RETURN_ERROR(update_context_buffer()); - VG_LITE_RETURN_ERROR(submit(&tls->t_context)); - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_UNLOCK, NULL)); - - CMDBUF_SWAP(tls->t_context); - CMDBUF_OFFSET(tls->t_context) = 0; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x0)); - tls->t_context.ts_init_used = 0; - tls->t_context.ts_init_use = 0; - tls->t_context.ts_init = 0; - - return VG_LITE_SUCCESS; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -vg_lite_error_t vg_lite_init_arc_path(vg_lite_path_t * path, - vg_lite_format_t data_format, - vg_lite_quality_t quality, - uint32_t path_length, - void * path_data, - vg_lite_float_t min_x, vg_lite_float_t min_y, - vg_lite_float_t max_x, vg_lite_float_t max_y) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t i = 0,command = 0,offset = 0; - vg_lite_float_t moveToX,moveToY,lineToX,lineToY,controlX, controlY,quadToX, quadToY; - vg_lite_float_t controlX1, controlY1,controlX2, controlY2,cubicToX, cubicToY; - vg_lite_float_t horRadius,verRadius,rotAngle,endX,endY; - float *pfloat,*fpath; - char *cpath,*pathdata; - vg_lite_control_coord_t coords; - if(path == NULL || path_data == NULL || data_format != VG_LITE_FP32) - return VG_LITE_INVALID_ARGUMENT; - - memset(path, 0, sizeof(*path)); - memset(&coords, 0, sizeof(vg_lite_control_coord_t)); - pathdata = (char *)vg_lite_os_malloc(path_length); - if (pathdata == NULL) - return VG_LITE_OUT_OF_MEMORY; - memset(pathdata, 0, path_length); - pfloat = (vg_lite_float_t *)path_data; - while(i < path_length) - { - cpath = (char *)pfloat; - command = (uint32_t)*cpath; - pfloat++; - switch (command) - { - case VLC_OP_END: - cpath = (char *)pathdata + offset; - fpath = (vg_lite_float_t *)cpath; - *cpath = VLC_OP_END; - offset += _commandSize_float[VLC_OP_END]; - i += _commandSize_float[VLC_OP_END]; - break; - case VLC_OP_CLOSE: - /* Update the control coordinates. */ - coords.lastX = coords.startX; - coords.lastY = coords.startY; - coords.controlX = coords.startX; - coords.controlY = coords.startY; - - cpath = (char *)pathdata + offset; - fpath = (vg_lite_float_t *)cpath; - *cpath = VLC_OP_CLOSE; - offset += _commandSize_float[VLC_OP_CLOSE]; - i += _commandSize_float[VLC_OP_CLOSE]; - break; - case VLC_OP_MOVE: - moveToX = *pfloat++; - moveToY = *pfloat++; - - /* Update the control coordinates. */ - coords.startX = moveToX; - coords.startY = moveToY; - coords.lastX = moveToX; - coords.lastY = moveToY; - coords.controlX = moveToX; - coords.controlY = moveToY; - - cpath = (char *)pathdata + offset; - fpath = (vg_lite_float_t *)cpath; - *cpath = VLC_OP_MOVE; - fpath++; - *fpath++ = moveToX; - *fpath++ = moveToY; - offset += _commandSize_float[VLC_OP_MOVE]; - i += _commandSize_float[VLC_OP_MOVE]; - break; - case VLC_OP_MOVE_REL: - moveToX = *pfloat++; - moveToY = *pfloat++; - - cpath = (char *)pathdata + offset; - fpath = (vg_lite_float_t *)cpath; - *cpath = VLC_OP_MOVE_REL; - fpath++; - *fpath++ = moveToX; - *fpath++ = moveToY; - offset += _commandSize_float[VLC_OP_MOVE_REL]; - i += _commandSize_float[VLC_OP_MOVE_REL]; - - /* Determine the absolute coordinates. */ - moveToX += coords.lastX; - moveToY += coords.lastY; - - /* Update the control coordinates. */ - coords.startX = moveToX; - coords.startY = moveToY; - coords.lastX = moveToX; - coords.lastY = moveToY; - coords.controlX = moveToX; - coords.controlY = moveToY; - break; - case VLC_OP_LINE: - lineToX = *pfloat++; - lineToY = *pfloat++; - - /* Update the control coordinates. */ - coords.lastX = lineToX; - coords.lastY = lineToY; - coords.controlX = lineToX; - coords.controlY = lineToY; - - cpath = (char *)pathdata + offset; - fpath = (vg_lite_float_t *)cpath; - *cpath = VLC_OP_LINE; - fpath++; - *fpath++ = lineToX; - *fpath++ = lineToY; - offset += _commandSize_float[VLC_OP_LINE]; - i += _commandSize_float[VLC_OP_LINE]; - break; - case VLC_OP_LINE_REL: - lineToX = *pfloat++; - lineToY = *pfloat++; - - cpath = (char *)pathdata + offset; - fpath = (vg_lite_float_t *)cpath; - *cpath = VLC_OP_LINE_REL; - fpath++; - *fpath++ = lineToX; - *fpath++ = lineToY; - offset += _commandSize_float[VLC_OP_LINE_REL]; - i += _commandSize_float[VLC_OP_LINE_REL]; - - /* Determine the absolute coordinates. */ - lineToX += coords.lastX; - lineToY += coords.lastY; - - /* Update the control coordinates. */ - coords.lastX = lineToX; - coords.lastY = lineToY; - coords.controlX = lineToX; - coords.controlY = lineToY; - break; - case VLC_OP_QUAD: - controlX = *pfloat++; - controlY = *pfloat++; - quadToX = *pfloat++; - quadToY = *pfloat++; - - /* Update the control coordinates. */ - coords.lastX = quadToX; - coords.lastY = quadToY; - coords.controlX = controlX; - coords.controlY = controlY; - - cpath = (char *)pathdata + offset; - fpath = (vg_lite_float_t *)cpath; - *cpath = VLC_OP_QUAD; - fpath++; - *fpath++ = controlX; - *fpath++ = controlY; - *fpath++ = quadToX; - *fpath++ = quadToY; - offset += _commandSize_float[VLC_OP_QUAD]; - i += _commandSize_float[VLC_OP_QUAD]; - break; - case VLC_OP_QUAD_REL: - controlX = *pfloat++; - controlY = *pfloat++; - quadToX = *pfloat++; - quadToY = *pfloat++; - - cpath = (char *)pathdata + offset; - fpath = (vg_lite_float_t *)cpath; - *cpath = VLC_OP_QUAD_REL; - fpath++; - *fpath++ = controlX; - *fpath++ = controlY; - *fpath++ = quadToX; - *fpath++ = quadToY; - offset += _commandSize_float[VLC_OP_QUAD_REL]; - i += _commandSize_float[VLC_OP_QUAD_REL]; - - /* Determine the absolute coordinates. */ - controlX += coords.lastX; - controlY += coords.lastY; - quadToX += coords.lastX; - quadToY += coords.lastY; - - /* Update the control coordinates. */ - coords.lastX = quadToX; - coords.lastY = quadToY; - coords.controlX = controlX; - coords.controlY = controlY; - break; - case VLC_OP_CUBIC: - controlX1 = *pfloat++; - controlY1 = *pfloat++; - controlX2 = *pfloat++; - controlY2 = *pfloat++; - cubicToX = *pfloat++; - cubicToY = *pfloat++; - - /* Update the control coordinates. */ - coords.lastX = cubicToX; - coords.lastY = cubicToY; - coords.controlX = controlX2; - coords.controlY = controlY2; - - cpath = (char *)pathdata + offset; - fpath = (vg_lite_float_t *)cpath; - *cpath = VLC_OP_CUBIC; - fpath++; - *fpath++ = controlX1; - *fpath++ = controlY1; - *fpath++ = controlX2; - *fpath++ = controlY2; - *fpath++ = cubicToX; - *fpath++ = cubicToY; - offset += _commandSize_float[VLC_OP_CUBIC]; - i += _commandSize_float[VLC_OP_CUBIC]; - break; - case VLC_OP_CUBIC_REL: - controlX1 = *pfloat++; - controlY1 = *pfloat++; - controlX2 = *pfloat++; - controlY2 = *pfloat++; - cubicToX = *pfloat++; - cubicToY = *pfloat++; - - cpath = (char *)pathdata + offset; - fpath = (vg_lite_float_t *)cpath; - *cpath = VLC_OP_CUBIC_REL; - fpath++; - *fpath++ = controlX1; - *fpath++ = controlY1; - *fpath++ = controlX2; - *fpath++ = controlY2; - *fpath++ = cubicToX; - *fpath++ = cubicToY; - offset += _commandSize_float[VLC_OP_CUBIC_REL]; - i += _commandSize_float[VLC_OP_CUBIC_REL]; - - /* Determine the absolute coordinates. */ - controlX2 += coords.lastX; - controlY2 += coords.lastY; - cubicToX += coords.lastX; - cubicToY += coords.lastY; - - /* Update the control coordinates. */ - coords.lastX = cubicToX; - coords.lastY = cubicToY; - coords.controlX = controlX2; - coords.controlY = controlY2; - break; - case VLC_OP_SCCWARC: - horRadius = *pfloat++; - verRadius = *pfloat++; - rotAngle = *pfloat++; - endX = *pfloat++; - endY = *pfloat++; - i += _commandSize_float[VLC_OP_SCCWARC]; - VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,FALSE,FALSE,FALSE,&coords,(void *)&pathdata,&offset,path_length - i)); - break; - case VLC_OP_SCCWARC_REL: - horRadius = *pfloat++; - verRadius = *pfloat++; - rotAngle = *pfloat++; - endX = *pfloat++; - endY = *pfloat++; - i += _commandSize_float[VLC_OP_SCCWARC_REL]; - VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,FALSE,FALSE,TURE,&coords,(void *)&pathdata,&offset,path_length - i)); - break; - case VLC_OP_SCWARC: - horRadius = *pfloat++; - verRadius = *pfloat++; - rotAngle = *pfloat++; - endX = *pfloat++; - endY = *pfloat++; - i += _commandSize_float[VLC_OP_SCCWARC_REL]; - VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,TURE,FALSE,FALSE,&coords,(void *)&pathdata,&offset,path_length - i)); - break; - case VLC_OP_SCWARC_REL: - horRadius = *pfloat++; - verRadius = *pfloat++; - rotAngle = *pfloat++; - endX = *pfloat++; - endY = *pfloat++; - i += _commandSize_float[VLC_OP_SCCWARC_REL]; - VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,TURE,FALSE,TURE,&coords,(void *)&pathdata,&offset,path_length - i)); - break; - case VLC_OP_LCCWARC: - horRadius = *pfloat++; - verRadius = *pfloat++; - rotAngle = *pfloat++; - endX = *pfloat++; - endY = *pfloat++; - i += _commandSize_float[VLC_OP_SCCWARC_REL]; - VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,FALSE,TURE,FALSE,&coords,(void *)&pathdata,&offset,path_length - i)); - break; - case VLC_OP_LCCWARC_REL: - horRadius = *pfloat++; - verRadius = *pfloat++; - rotAngle = *pfloat++; - endX = *pfloat++; - endY = *pfloat++; - i += _commandSize_float[VLC_OP_SCCWARC_REL]; - VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,FALSE,TURE,TURE,&coords,(void *)&pathdata,&offset,path_length - i)); - break; - case VLC_OP_LCWARC: - horRadius = *pfloat++; - verRadius = *pfloat++; - rotAngle = *pfloat++; - endX = *pfloat++; - endY = *pfloat++; - i += _commandSize_float[VLC_OP_SCCWARC_REL]; - VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,TURE,TURE,FALSE,&coords,(void *)&pathdata,&offset,path_length - i)); - break; - case VLC_OP_LCWARC_REL: - horRadius = *pfloat++; - verRadius = *pfloat++; - rotAngle = *pfloat++; - endX = *pfloat++; - endY = *pfloat++; - i += _commandSize_float[VLC_OP_SCCWARC_REL]; - VG_LITE_ERROR_HANDLER(_convert_arc(horRadius,verRadius,rotAngle,endX,endY,TURE,TURE,TURE,&coords,(void *)&pathdata,&offset,path_length - i)); - break; - default: - break; - } - } - - path->format = data_format; - path->quality = quality; - path->bounding_box[0] = min_x; - path->bounding_box[1] = min_y; - path->bounding_box[2] = max_x; - path->bounding_box[3] = max_y; - - path->path_length = offset; - path->path = pathdata; - path->pdata_internal = 1; - path->path_changed = 1; - path->uploaded.address = 0; - path->uploaded.bytes = 0; - path->uploaded.handle = NULL; - path->uploaded.memory = NULL; - - return VG_LITE_SUCCESS; - -ErrorHandler: - vg_lite_os_free(pathdata); - pathdata = NULL; - return error; -} - -vg_lite_error_t vg_lite_init_path(vg_lite_path_t * path, - vg_lite_format_t data_format, - vg_lite_quality_t quality, - uint32_t path_length, - void * path_data, - vg_lite_float_t min_x, vg_lite_float_t min_y, - vg_lite_float_t max_x, vg_lite_float_t max_y) -{ - if(path == NULL) - return VG_LITE_INVALID_ARGUMENT; - - memset(path, 0, sizeof(*path)); - path->format = data_format; - path->quality = quality; - path->bounding_box[0] = min_x; - path->bounding_box[1] = min_y; - path->bounding_box[2] = max_x; - path->bounding_box[3] = max_y; - - path->path_length = path_length; - path->path = path_data; - - path->path_changed = 1; - path->uploaded.address = 0; - path->uploaded.bytes = 0; - path->uploaded.handle = NULL; - path->uploaded.memory = NULL; - path->uploaded.property = 0; - path->pdata_internal = 0; - - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_clear_path(vg_lite_path_t * path) -{ - vg_lite_error_t error; - if (path->uploaded.handle != NULL) - { - vg_lite_kernel_free_t free_cmd; - free_cmd.memory_handle = path->uploaded.handle; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_FREE, &free_cmd)); - } - - path->uploaded.address = 0; - path->uploaded.bytes = 0; - path->uploaded.handle = NULL; - path->uploaded.memory = NULL; - - if(path->pdata_internal == 1 && path->path != NULL){ - vg_lite_os_free(path->path); - } - path->path = NULL; - - if(path->stroke_path_data) { - vg_lite_os_free(path->stroke_path_data); - path->stroke_path_data = NULL; - - if(path->stroke_conversion.path_point_list) { - vg_lite_path_point_ptr temp_point; - while(path->stroke_conversion.path_point_list) { - temp_point = path->stroke_conversion.path_point_list->next; -#if defined(VG_DRIVER_SINGLE_THREAD) - free(path->stroke_conversion.path_point_list); -#else - vg_lite_os_free(path->stroke_conversion.path_point_list); -#endif /* VG_DRIVER_SINGLE_THREAD */ - path->stroke_conversion.path_point_list = temp_point; - } - temp_point = NULL; - } - - if(path->stroke_conversion.stroke_sub_path_list) { - vg_lite_sub_path_ptr temp_sub_path; - while(path->stroke_conversion.stroke_sub_path_list) { - temp_sub_path = path->stroke_conversion.stroke_sub_path_list->next; - if(path->stroke_conversion.stroke_sub_path_list->point_list) { - vg_lite_path_point_ptr temp_point; - while(path->stroke_conversion.stroke_sub_path_list->point_list) { - temp_point = path->stroke_conversion.stroke_sub_path_list->point_list->next; - vg_lite_os_free(path->stroke_conversion.stroke_sub_path_list->point_list); - path->stroke_conversion.stroke_sub_path_list->point_list = temp_point; - } - temp_point = NULL; - } - vg_lite_os_free(path->stroke_conversion.stroke_sub_path_list); - path->stroke_conversion.stroke_sub_path_list = temp_sub_path; - } - temp_sub_path = NULL; - } - } - - return VG_LITE_SUCCESS; -} - -#if defined(VG_DRIVER_SINGLE_THREAD) -vg_lite_error_t vg_lite_set_CLUT(uint32_t count, - uint32_t * colors) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - - uint32_t addr = 0x0B00; - - if(!s_ftable.ftable[gcFEATURE_BIT_VG_IM_INDEX_FORMAT]) - return VG_LITE_NOT_SUPPORT; - - switch (count) { - case 256: - addr = 0x0B00; - break; - - case 16: - addr = 0x0AA0; - break; - - case 4: - addr = 0x0A9C; - break; - - case 2: - addr = 0x0A98; - break; - - default: - error = VG_LITE_INVALID_ARGUMENT; - return error; - break; - } - - VG_LITE_RETURN_ERROR(push_states(&s_context, addr, count, colors)); - - return error; -} - -vg_lite_error_t vg_lite_draw_pattern(vg_lite_buffer_t * target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix0, - vg_lite_buffer_t * source, - vg_lite_matrix_t * matrix1, - vg_lite_blend_t blend, - vg_lite_pattern_mode_t pattern_mode, - vg_lite_color_t pattern_color, - vg_lite_filter_t filter) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t imageMode; - uint32_t blend_mode; - int32_t src_align_width,dst_align_width; - uint32_t mul, div, align; - uint32_t conversion = 0; - uint32_t tiled_source; - vg_lite_matrix_t * matrix = matrix1; - uint32_t pattern_tile = 0; - uint32_t transparency_mode = 0; - - /* The following code is from "draw path" */ - uint32_t format, quality, tiling, fill; - uint32_t tessellation_size; - - vg_lite_point_t point_min = {0}, point_max = {0}, temp = {0}; - int x, y, width, height; - uint8_t ts_is_fullscreen = 0; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_QUALITY_8X) && path->quality == VG_LITE_UPPER){ - return VG_LITE_NOT_SUPPORT; - } - - if(source->format == VG_LITE_A4 || source->format == VG_LITE_A8) { - return VG_LITE_NOT_SUPPORT; - } - - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); - width = s_context.tsbuffer.tessellation_width_height & 0xFFFF; - height = s_context.tsbuffer.tessellation_width_height >> 16; - get_format_bytes(target->format, &mul, &div, &align); - dst_align_width = target->stride * div / mul; - if(width == 0 || height == 0) - return VG_LITE_NO_CONTEXT; - if ((dst_align_width <= width) && (target->height <= height)) - { - ts_is_fullscreen = 1; - point_min.x = 0; - point_min.y = 0; - point_max.x = dst_align_width; - point_max.y = target->height; - } - - /* If target is L8 and source is in YUV or RGB (not L8 or A8) then we have to convert RGB into L8. */ - if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { - conversion = 0x80000000; - } - - /* Determine image mode (NORMAL or MULTIPLY) depending on the color. */ - imageMode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; - tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; - - if (pattern_mode == VG_LITE_PATTERN_COLOR) - { - uint8_t a,r,g,b; - pattern_tile = 0; - a = pattern_color >> 24; - r = pattern_color >> 16; - g = pattern_color >> 8; - b = pattern_color; - pattern_color = (a << 24) | (b << 16) | (g << 8) | r; - } - else if (pattern_mode == VG_LITE_PATTERN_PAD) - { - pattern_tile = 0x1000; - } - else - { - return VG_LITE_INVALID_ARGUMENT; - } - - /* Setup the command buffer. */ - get_format_bytes(source->format, &mul, &div, &align); - src_align_width = source->stride * div / mul; - VG_LITE_RETURN_ERROR(set_interpolation_steps(target, src_align_width, source->height, matrix)); - - if(!s_context.premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { - if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A25, convert_source_format(source->format) | - filter | pattern_tile | conversion | 0x01000100)); - } else { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A25, convert_source_format(source->format) | - filter | pattern_tile | conversion | 0x00000100)); - } - } else { - /* enable pre-multiplied in imager unit */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A25, convert_source_format(source->format) | - filter | pattern_tile | conversion)); - } - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A27, pattern_color)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A29, source->address)); - - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2B, source->stride | tiled_source)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2D, 0)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2F, src_align_width | (source->height << 16))); - - /* Work on path states. */ - matrix = matrix0; - - if (ts_is_fullscreen == 0){ - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[1], matrix); - point_min = point_max = temp; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[1], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - point_min.x = MAX(point_min.x, 0); - point_min.y = MAX(point_min.y, 0); - point_max.x = MIN(point_max.x, dst_align_width); - point_max.y = MIN(point_max.y, target->height); - - if (s_context.scissor_enabled) { - point_min.x = MAX(point_min.x, s_context.scissor[0]); - point_min.y = MAX(point_min.y, s_context.scissor[1]); - point_max.x = MIN(point_max.x, s_context.scissor[0] + s_context.scissor[2]); - point_max.y = MIN(point_max.y, s_context.scissor[1] + s_context.scissor[3]); - } - } - - /* Convert states into hardware values. */ - blend_mode = convert_blend(blend); - format = convert_path_format(path->format); - quality = convert_path_quality(path->quality); - tiling = (s_context.capabilities.cap.tiled == 2) ? 0x2000000 : 0; - fill = (fill_rule == VG_LITE_FILL_EVEN_ODD) ? 0x10 : 0; - tessellation_size = ( s_context.tsbuffer.tessellation_buffer_size[2] - ? s_context.tsbuffer.tessellation_buffer_size[2] - : s_context.tsbuffer.tessellation_buffer_size[1] - ); - - /* Setup the command buffer. */ - /* Program color register. */ - if(!s_context.premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, 0x10000000 | s_context.capabilities.cap.tiled | 0x00000002 | imageMode | blend_mode | transparency_mode)); - } else { - /* enable pre-multiplied from VG to VGPE */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, s_context.capabilities.cap.tiled | 0x00000002 | imageMode | blend_mode | transparency_mode)); - } - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A34, 0x01000400 | format | quality | tiling | fill)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3B, 0x3F800000)); /* Path tessellation SCALE. */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3C, 0x00000000)); /* Path tessellation BIAS. */ - /* Program matrix. */ - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A40, (void *) &matrix->m[0][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A41, (void *) &matrix->m[0][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A42, (void *) &matrix->m[0][2])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A43, (void *) &matrix->m[1][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A44, (void *) &matrix->m[1][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A45, (void *) &matrix->m[1][2])); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - - vglitemDUMP_BUFFER("path", path->uploaded.address, (uint8_t *)(path->uploaded.memory), 0, path->uploaded.bytes); - } - - vglitemDUMP("@[memory 0x%08X 0x%08X]", s_context.tsbuffer.tessellation_buffer_gpu[0], s_context.tsbuffer.tessellation_buffer_size[0]); - - /* Setup tessellation loop. */ - if((path->path_type & 0x1) == VG_LITE_DRAW_FILL_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&s_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&s_context, path->uploaded.address, path->uploaded.bytes)); - } else { - push_data(&s_context, path->path_length, path->path); - } - } - } - } - /* Setup tessellation loop. */ - if(path->path_type == VG_LITE_DRAW_STROKE_PATH || path->path_type == VG_LITE_DRAW_FILL_STROKE_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&s_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&s_context, path->uploaded.address, path->uploaded.bytes)); - } else { - format = convert_path_format(VG_LITE_FP32); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A34, 0x01000200 | format | quality | tiling | 0x0)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A02, path->stroke_color)); - push_data(&s_context, path->stroke_path_size, path->stroke_path_data); - } - } - } - } - - /* Finialize command buffer. */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A34, 0)); - - vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); -#if DUMP_IMAGE - dump_img(source->memory, source->width, source->height, source->format); -#endif - return error; -} - -vg_lite_error_t vg_lite_draw_linear_gradient(vg_lite_buffer_t * target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * path_matrix, - vg_lite_linear_gradient_ext_t *grad, - vg_lite_color_t paint_color, - vg_lite_blend_t blend, - vg_lite_filter_t filter) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t image_mode; - uint32_t blend_mode; - uint32_t conversion = 0; - uint32_t tiled_source; - int32_t dst_align_width; - uint32_t mul, div, align; - vg_lite_matrix_t inverse_matrix; - vg_lite_buffer_t * source = &grad->image; - vg_lite_matrix_t * matrix = &grad->matrix; - uint32_t linear_tile = 0; - uint32_t transparency_mode = 0; - void *data; - - /* The following code is from "draw path" */ - uint32_t format, quality, tiling, fill; - uint32_t tessellation_size; - - vg_lite_kernel_allocate_t memory; - vg_lite_kernel_free_t free_memory; - uint32_t return_offset = 0; - - vg_lite_point_t point_min = {0}, point_max = {0}, temp = {0}; - int x, y, width, height; - uint8_t ts_is_fullscreen = 0; - - vg_lite_float_t dx, dy, dxdx_dydy; - vg_lite_float_t lg_step_x_lin, lg_step_y_lin, lg_constant_lin; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT)) - return VG_LITE_NOT_SUPPORT; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_QUALITY_8X) && path->quality == VG_LITE_UPPER){ - return VG_LITE_NOT_SUPPORT; - } - - if(source->format == VG_LITE_A4 || source->format == VG_LITE_A8) { - return VG_LITE_NOT_SUPPORT; - } - - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); - width = s_context.tsbuffer.tessellation_width_height & 0xFFFF; - height = s_context.tsbuffer.tessellation_width_height >> 16; - get_format_bytes(target->format, &mul, &div, &align); - dst_align_width = target->stride * div / mul; - if(width == 0 || height == 0) - return VG_LITE_NO_CONTEXT; - if ((dst_align_width <= width) && (target->height <= height)) - { - ts_is_fullscreen = 1; - point_min.x = 0; - point_min.y = 0; - point_max.x = dst_align_width; - point_max.y = target->height; - } - - /* If target is L8 and source is in YUV or RGB (not L8 or A8) then we have to convert RGB into L8. */ - if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { - conversion = 0x80000000; - } - - /* Determine image mode (NORMAL or MULTIPLY) depending on the color. */ - image_mode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; - tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; - - linear_tile = (grad->spread_mode == VG_LITE_RADIAL_GRADIENT_SPREAD_FILL) ? 0 : - (grad->spread_mode == VG_LITE_RADIAL_GRADIENT_SPREAD_PAD) ? 0x1000 : - (grad->spread_mode == VG_LITE_RADIAL_GRADIENT_SPREAD_REPEAT) ? 0x2000 : 0x3000; - - /* compute radial gradient paremeters */ - - if (!inverse(&inverse_matrix, matrix)) - /* Compute inverse matrix. */ - return VG_LITE_INVALID_ARGUMENT; - - dx = grad->linear_gradient.X1 - grad->linear_gradient.X0; - dy = grad->linear_gradient.Y1 - grad->linear_gradient.Y0; - dxdx_dydy = dx * dx + dy * dy; - - /* - ** dx (T(x) - x0) + dy (T(y) - y0) - ** g = ------------------------------- - ** dx^2 + dy^2 - ** - ** where - ** - ** dx := x1 - x0 - ** dy := y1 - y1 - ** T(x) := (x + 0.5) m00 + (y + 0.5) m01 + m02 - ** = x m00 + y m01 + 0.5 (m00 + m01) + m02 - ** T(y) := (x + 0.5) m10 + (y + 0.5) m11 + m12 - ** = x m10 + y m11 + 0.5 (m10 + m11) + m12. - ** - ** We can factor the top line into: - ** - ** = dx (x m00 + y m01 + 0.5 (m00 + m01) + m02 - x0) - ** + dy (x m10 + y m11 + 0.5 (m10 + m11) + m12 - y0) - ** - ** = x (dx m00 + dy m10) - ** + y (dx m01 + dy m11) - ** + dx (0.5 (m00 + m01) + m02 - x0) - ** + dy (0.5 (m10 + m11) + m12 - y0). - */ - - lg_step_x_lin - = (dx * MAT(&inverse_matrix, 0, 0) + dy * MAT(&inverse_matrix, 1, 0)) - / dxdx_dydy; - - lg_step_y_lin - = (dx * MAT(&inverse_matrix, 0, 1) + dy * MAT(&inverse_matrix, 1, 1)) - / dxdx_dydy; - - lg_constant_lin = - ( - ( - 0.5f * ( MAT(&inverse_matrix, 0, 0) + MAT(&inverse_matrix, 0, 1) ) - + MAT(&inverse_matrix, 0, 2) - grad->linear_gradient.X0 - ) * dx - - + - - ( - 0.5f * ( MAT(&inverse_matrix, 1, 0) + MAT(&inverse_matrix, 1, 1) ) - + MAT(&inverse_matrix, 1, 2) - grad->linear_gradient.Y0 - ) * dy - ) - / dxdx_dydy; - - /* Setup the command buffer. */ - - /* linear gradient parameters*/ - data = &lg_constant_lin; - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A04,*(uint32_t*) data)); - data = &lg_step_x_lin; - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A06,*(uint32_t*) data)); - data = &lg_step_y_lin; - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A08,*(uint32_t*) data)); - - VG_LITE_RETURN_ERROR(set_interpolation_steps(target, source->width, source->height, matrix)); - - if(!s_context.premultiply_enabled) { - if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A24, convert_source_format(source->format) | - filter | linear_tile | conversion | 0x01000100)); - } else { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A24, convert_source_format(source->format) | - filter | linear_tile | conversion | 0x00000100)); - } - } else { - /* enable pre-multiplied in imager unit */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A24, convert_source_format(source->format) | - filter | linear_tile | conversion)); - } - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A26, paint_color)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A28, source->address)); - - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2A, tiled_source)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2C, 0)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2E, source->width)); - - /* Work on path states. */ - matrix = path_matrix; - - if (ts_is_fullscreen == 0){ - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[1], matrix); - point_min = point_max = temp; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[1], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - point_min.x = MAX(point_min.x, 0); - point_min.y = MAX(point_min.y, 0); - point_max.x = MIN(point_max.x, dst_align_width); - point_max.y = MIN(point_max.y, target->height); - - if (s_context.scissor_enabled) { - point_min.x = MAX(point_min.x, s_context.scissor[0]); - point_min.y = MAX(point_min.y, s_context.scissor[1]); - point_max.x = MIN(point_max.x, s_context.scissor[0] + s_context.scissor[2]); - point_max.y = MIN(point_max.y, s_context.scissor[1] + s_context.scissor[3]); - } - } - - /* Convert states into hardware values. */ - blend_mode = convert_blend(blend); - format = convert_path_format(path->format); - quality = convert_path_quality(path->quality); - tiling = (s_context.capabilities.cap.tiled == 2) ? 0x2000000 : 0; - fill = (fill_rule == VG_LITE_FILL_EVEN_ODD) ? 0x10 : 0; - tessellation_size = ( s_context.tsbuffer.tessellation_buffer_size[2] - ? s_context.tsbuffer.tessellation_buffer_size[2] - : s_context.tsbuffer.tessellation_buffer_size[1] - ); - - /* Setup the command buffer. */ - /* Program color register. */ - if(!s_context.premultiply_enabled) { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, 0x11000000 | s_context.capabilities.cap.tiled | 0x00000002 | image_mode | blend_mode | transparency_mode)); - } else { - /* enable pre-multiplied from VG to VGPE */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, 0x01000000 | s_context.capabilities.cap.tiled | 0x00000002 | image_mode | blend_mode | transparency_mode)); - } - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A34, 0x01000400 | format | quality | tiling | fill)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3B, 0x3F800000)); /* Path tessellation SCALE. */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3C, 0x00000000)); /* Path tessellation BIAS. */ - /* Program matrix. */ - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A40, (void *) &matrix->m[0][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A41, (void *) &matrix->m[0][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A42, (void *) &matrix->m[0][2])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A43, (void *) &matrix->m[1][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A44, (void *) &matrix->m[1][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A45, (void *) &matrix->m[1][2])); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) - { - if (path->path_changed != 0) { - if (path->uploaded.handle != NULL) { - free_memory.memory_handle = path->uploaded.handle; - vg_lite_kernel(VG_LITE_FREE, &free_memory); - path->uploaded.address = 0; - path->uploaded.memory = NULL; - path->uploaded.handle = NULL; - } - /* Allocate memory for the path data. */ - memory.bytes = 16 + VG_LITE_ALIGN(path->path_length, 8); - return_offset = (8 + VG_LITE_ALIGN(path->path_length, 8)) / 4; - memory.contiguous = 1; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &memory)); - ((uint64_t *) memory.memory)[(path->path_length + 7) / 8] = 0; - ((uint32_t *) memory.memory)[0] = VG_LITE_DATA((path->path_length + 7) / 8); - ((uint32_t *) memory.memory)[1] = 0; - memcpy((uint8_t *) memory.memory + 8, path->path, path->path_length); - ((uint32_t *) memory.memory)[return_offset] = VG_LITE_RETURN(); - ((uint32_t *) memory.memory)[return_offset + 1] = 0; - - path->uploaded.handle = memory.memory_handle; - path->uploaded.memory = memory.memory; - path->uploaded.address = memory.memory_gpu; - path->uploaded.bytes = memory.bytes; - path->path_changed = 0; - } - } - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - - vglitemDUMP_BUFFER("path", path->uploaded.address, (uint8_t *)(path->uploaded.memory), 0, path->uploaded.bytes); - } - - vglitemDUMP("@[memory 0x%08X 0x%08X]", s_context.tsbuffer.tessellation_buffer_gpu[0], s_context.tsbuffer.tessellation_buffer_size[0]); - - /* Setup tessellation loop. */ - if((path->path_type & 0x1) == VG_LITE_DRAW_FILL_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&s_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&s_context, path->uploaded.address, path->uploaded.bytes)); - } else { - push_data(&s_context, path->path_length, path->path); - } - } - } - } - /* Setup tessellation loop. */ - if(path->path_type == VG_LITE_DRAW_STROKE_PATH || path->path_type == VG_LITE_DRAW_FILL_STROKE_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&s_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&s_context, path->uploaded.address, path->uploaded.bytes)); - } else { - format = convert_path_format(VG_LITE_FP32); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A34, 0x01000200 | format | quality | tiling | 0x0)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A02, path->stroke_color)); - push_data(&s_context, path->stroke_path_size, path->stroke_path_data); - } - } - } - } - - /* Finialize command buffer. */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A34, 0)); - - vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); -#if DUMP_IMAGE - dump_img(source->memory, source->width, source->height, source->format); -#endif - return error; -} - -vg_lite_error_t vg_lite_draw_radial_gradient(vg_lite_buffer_t * target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * path_matrix, - vg_lite_radial_gradient_t *grad, - vg_lite_color_t paint_color, - vg_lite_blend_t blend, - vg_lite_filter_t filter) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t imageMode; - uint32_t blend_mode; - uint32_t conversion = 0; - uint32_t tiled_source; - int32_t dst_align_width; - uint32_t mul, div, align; - vg_lite_matrix_t inverse_matrix; - vg_lite_buffer_t * source = &grad->image; - vg_lite_matrix_t * matrix = &grad->matrix; - uint32_t rad_tile = 0; - uint32_t transparency_mode = 0; - void *data; - - /* The following code is from "draw path" */ - uint32_t format, quality, tiling, fill; - uint32_t tessellation_size; - - vg_lite_kernel_allocate_t memory; - vg_lite_kernel_free_t free_memory; - uint32_t return_offset = 0; - - vg_lite_point_t point_min = {0}, point_max = {0}, temp = {0}; - int x, y, width, height; - uint8_t ts_is_fullscreen = 0; - - vg_lite_float_t radius; - - vg_lite_float_t centerX, centerY; - vg_lite_float_t focalX, focalY; - vg_lite_float_t fx, fy; - vg_lite_float_t fxfy_2; - vg_lite_float_t radius2; - vg_lite_float_t r2_fx2, r2_fy2; - vg_lite_float_t r2_fx2_2, r2_fy2_2; - vg_lite_float_t r2_fx2_fy2; - vg_lite_float_t r2_fx2_fy2sq; - vg_lite_float_t cx, cy; - - vg_lite_float_t rgConstantLin, rgStepXLin, rgStepYLin; - vg_lite_float_t rgConstantRad, rgStepXRad, rgStepYRad; - vg_lite_float_t rgStepXXRad, rgStepYYRad, rgStepXYRad; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_RADIAL_GRADIENT)) - return VG_LITE_NOT_SUPPORT; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_QUALITY_8X) && path->quality == VG_LITE_UPPER){ - return VG_LITE_NOT_SUPPORT; - } - - if(source->format == VG_LITE_A4 || source->format == VG_LITE_A8) { - return VG_LITE_NOT_SUPPORT; - } - - radius = grad->radialGradient.r; - if(radius <= 0) - return VG_LITE_INVALID_ARGUMENT; - - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); - width = s_context.tsbuffer.tessellation_width_height & 0xFFFF; - height = s_context.tsbuffer.tessellation_width_height >> 16; - get_format_bytes(target->format, &mul, &div, &align); - dst_align_width = target->stride * div / mul; - if(width == 0 || height == 0) - return VG_LITE_NO_CONTEXT; - if ((dst_align_width <= width) && (target->height <= height)) - { - ts_is_fullscreen = 1; - point_min.x = 0; - point_min.y = 0; - point_max.x = dst_align_width; - point_max.y = target->height; - } - - /* If target is L8 and source is in YUV or RGB (not L8 or A8) then we have to convert RGB into L8. */ - if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { - conversion = 0x80000000; - } - - /* Determine image mode (NORMAL or MULTIPLY) depending on the color. */ - imageMode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; - tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; - - rad_tile = (grad->SpreadMode == VG_LITE_RADIAL_GRADIENT_SPREAD_FILL) ? 0 : - (grad->SpreadMode == VG_LITE_RADIAL_GRADIENT_SPREAD_PAD) ? 0x1000 : - (grad->SpreadMode == VG_LITE_RADIAL_GRADIENT_SPREAD_REPEAT) ? 0x2000 : 0x3000; - - /* compute radial gradient paremeters */ - - /* Compute inverse matrix. */ - if (!inverse(&inverse_matrix, matrix)) - return VG_LITE_INVALID_ARGUMENT; - - /* Make shortcuts to the gradient information. */ - centerX = grad->radialGradient.cx; - centerY = grad->radialGradient.cy; - focalX = grad->radialGradient.fx; - focalY = grad->radialGradient.fy; - - /* Compute constants of the equation. */ - fx = focalX - centerX; - fy = focalY - centerY; - radius2 = radius * radius; - if (fx*fx + fy*fy > radius2) - { - /* If the focal point is outside the circle, let's move it - to inside the circle. Per vg11 spec pg125 "If (fx, fy) lies outside ... - For here, we set it at 0.9 ratio to the center. - */ - vg_lite_float_t fr = (vg_lite_float_t)sqrt(fx*fx + fy*fy); - fx = radius * fx / fr * 0.9f; - fy = radius * fy / fr * 0.9f; - focalX = grad->radialGradient.fx + fx; - focalY = grad->radialGradient.fy + fy; - } - - fxfy_2 = 2.0f * fx * fy; - r2_fx2 = radius2 - fx * fx; - r2_fy2 = radius2 - fy * fy; - r2_fx2_2 = 2.0f * r2_fx2; - r2_fy2_2 = 2.0f * r2_fy2; - r2_fx2_fy2 = r2_fx2 - fy * fy; - r2_fx2_fy2sq = r2_fx2_fy2 * r2_fx2_fy2; - - /* _____________________________________ - ** dx fx + dy fy + \/r^2 (dx^2 + dy^2) - (dx fy - dy fx)^2 - ** g = ------------------------------------------------------- - ** r^2 - fx^2 - fy^2 - ** - ** Where - ** - ** dx := F(x) - focalX - ** dy := F(y) - focalY - ** fx := focalX - centerX - ** fy := focalX - centerY - ** - ** and - ** - ** F(x) := (x + 0.5) m00 + (y + 0.5) m01 + m02 - ** F(y) := (x + 0.5) m10 + (y + 0.5) m11 + m12 - ** - ** So, dx can be factored into - ** - ** dx = (x + 0.5) m00 + (y + 0.5) m01 + m02 - focalX - ** = x m00 + y m01 + 0.5 m00 + 0.5 m01 + m02 - focalX - ** - ** = x m00 + y m01 + cx - ** - ** where - ** - ** cx := 0.5 m00 + 0.5 m01 + m02 - focalX - ** - ** The same way we can factor dy into - ** - ** dy = x m10 + y m11 + cy - ** - ** where - ** - ** cy := 0.5 m10 + 0.5 m11 + m12 - focalY. - ** - ** Now we can rewrite g as - ** ______________________________________ - ** dx fx + dy fy / r^2 (dx^2 + dy^2) - (dx fy - dy fx)^2 - ** g = ----------------- + \ / ------------------------------------- - ** r^2 - fx^2 - fy^2 \/ (r^2 - fx^2 - fy^2)^2 - ** ____ - ** = gLin + \/gRad - ** - ** where - ** - ** dx fx + dy fy - ** gLin := ----------------- - ** r^2 - fx^2 - fy^2 - ** - ** r^2 (dx^2 + dy^2) - (dx fy - dy fx)^2 - ** gRad := ------------------------------------- - ** (r^2 - fx^2 - fy^2)^2 - */ - - cx - = 0.5f * ( MAT(&inverse_matrix, 0, 0) + MAT(&inverse_matrix, 0, 1) ) - + MAT(&inverse_matrix, 0, 2) - - focalX; - - cy - = 0.5f * ( MAT(&inverse_matrix, 1, 0) + MAT(&inverse_matrix, 1, 1) ) - + MAT(&inverse_matrix, 1, 2) - - focalY; - - /* - ** dx fx + dy fy - ** gLin := ----------------- - ** r^2 - fx^2 - fy^2 - ** - ** We can factor the top half into - ** - ** = (x m00 + y m01 + cx) fx + (x m10 + y m11 + cy) fy - ** - ** = x (m00 fx + m10 fy) - ** + y (m01 fx + m11 fy) - ** + cx fx + cy fy. - */ - - rgStepXLin - = ( MAT(&inverse_matrix, 0, 0) * fx + MAT(&inverse_matrix, 1, 0) * fy ) - / r2_fx2_fy2; - - rgStepYLin - = ( MAT(&inverse_matrix, 0, 1) * fx + MAT(&inverse_matrix, 1, 1) * fy ) - / r2_fx2_fy2; - - rgConstantLin = ( cx * fx + cy * fy ) / r2_fx2_fy2; - - /* - ** r^2 (dx^2 + dy^2) - (dx fy - dy fx)^2 - ** gRad := ------------------------------------- - ** (r^2 - fx^2 - fy^2)^2 - ** - ** r^2 (dx^2 + dy^2) - dx^2 fy^2 - dy^2 fx^2 + 2 dx dy fx fy - ** := --------------------------------------------------------- - ** (r^2 - fx^2 - fy^2)^2 - ** - ** dx^2 (r^2 - fy^2) + dy^2 (r^2 - fx^2) + 2 dx dy fx fy - ** := ----------------------------------------------------- - ** (r^2 - fx^2 - fy^2)^2 - ** - ** First, lets factor dx^2 into - ** - ** dx^2 = (x m00 + y m01 + cx)^2 - ** = x^2 m00^2 + y^2 m01^2 + 2 x y m00 m01 - ** + 2 x m00 cx + 2 y m01 cx + cx^2 - ** - ** = x^2 (m00^2) - ** + y^2 (m01^2) - ** + x y (2 m00 m01) - ** + x (2 m00 cx) - ** + y (2 m01 cx) - ** + cx^2. - ** - ** The same can be done for dy^2: - ** - ** dy^2 = x^2 (m10^2) - ** + y^2 (m11^2) - ** + x y (2 m10 m11) - ** + x (2 m10 cy) - ** + y (2 m11 cy) - ** + cy^2. - ** - ** Let's also factor dx dy into - ** - ** dx dy = (x m00 + y m01 + cx) (x m10 + y m11 + cy) - ** = x^2 m00 m10 + y^2 m01 m11 + x y m00 m11 + x y m01 m10 - ** + x m00 cy + x m10 cx + y m01 cy + y m11 cx + cx cy - ** - ** = x^2 (m00 m10) - ** + y^2 (m01 m11) - ** + x y (m00 m11 + m01 m10) - ** + x (m00 cy + m10 cx) - ** + y (m01 cy + m11 cx) - ** + cx cy. - ** - ** Now that we have all this, lets look at the top of gRad. - ** - ** = dx^2 (r^2 - fy^2) + dy^2 (r^2 - fx^2) + 2 dx dy fx fy - ** = x^2 m00^2 (r^2 - fy^2) + y^2 m01^2 (r^2 - fy^2) - ** + x y 2 m00 m01 (r^2 - fy^2) + x 2 m00 cx (r^2 - fy^2) - ** + y 2 m01 cx (r^2 - fy^2) + cx^2 (r^2 - fy^2) - ** + x^2 m10^2 (r^2 - fx^2) + y^2 m11^2 (r^2 - fx^2) - ** + x y 2 m10 m11 (r^2 - fx^2) + x 2 m10 cy (r^2 - fx^2) - ** + y 2 m11 cy (r^2 - fx^2) + cy^2 (r^2 - fx^2) - ** + x^2 m00 m10 2 fx fy + y^2 m01 m11 2 fx fy - ** + x y (m00 m11 + m01 m10) 2 fx fy - ** + x (m00 cy + m10 cx) 2 fx fy + y (m01 cy + m11 cx) 2 fx fy - ** + cx cy 2 fx fy - ** - ** = x^2 ( m00^2 (r^2 - fy^2) - ** + m10^2 (r^2 - fx^2) - ** + m00 m10 2 fx fy - ** ) - ** + y^2 ( m01^2 (r^2 - fy^2) - ** + m11^2 (r^2 - fx^2) - ** + m01 m11 2 fx fy - ** ) - ** + x y ( 2 m00 m01 (r^2 - fy^2) - ** + 2 m10 m11 (r^2 - fx^2) - ** + (m00 m11 + m01 m10) 2 fx fy - ** ) - ** + x ( 2 m00 cx (r^2 - fy^2) - ** + 2 m10 cy (r^2 - fx^2) - ** + (m00 cy + m10 cx) 2 fx fy - ** ) - ** + y ( 2 m01 cx (r^2 - fy^2) - ** + 2 m11 cy (r^2 - fx^2) - ** + (m01 cy + m11 cx) 2 fx fy - ** ) - ** + cx^2 (r^2 - fy^2) + cy^2 (r^2 - fx^2) + cx cy 2 fx fy. - */ - - rgStepXXRad = - ( - MAT(&inverse_matrix, 0, 0) * MAT(&inverse_matrix, 0, 0) * r2_fy2 - + MAT(&inverse_matrix, 1, 0) * MAT(&inverse_matrix, 1, 0) * r2_fx2 - + MAT(&inverse_matrix, 0, 0) * MAT(&inverse_matrix, 1, 0) * fxfy_2 - ) - / r2_fx2_fy2sq; - - rgStepYYRad = - ( - MAT(&inverse_matrix, 0, 1) * MAT(&inverse_matrix, 0, 1) * r2_fy2 - + MAT(&inverse_matrix, 1, 1) * MAT(&inverse_matrix, 1, 1) * r2_fx2 - + MAT(&inverse_matrix, 0, 1) * MAT(&inverse_matrix, 1, 1) * fxfy_2 - ) - / r2_fx2_fy2sq; - - rgStepXYRad = - ( - MAT(&inverse_matrix, 0, 0) * MAT(&inverse_matrix, 0, 1) * r2_fy2_2 - + MAT(&inverse_matrix, 1, 0) * MAT(&inverse_matrix, 1, 1) * r2_fx2_2 - + ( - MAT(&inverse_matrix, 0, 0) * MAT(&inverse_matrix, 1, 1) - + MAT(&inverse_matrix, 0, 1) * MAT(&inverse_matrix, 1, 0) - ) - * fxfy_2 - ) - / r2_fx2_fy2sq; - - rgStepXRad = - ( - MAT(&inverse_matrix, 0, 0) * cx * r2_fy2_2 - + MAT(&inverse_matrix, 1, 0) * cy * r2_fx2_2 - + ( - MAT(&inverse_matrix, 0, 0) * cy - + MAT(&inverse_matrix, 1, 0) * cx - ) - * fxfy_2 - ) - / r2_fx2_fy2sq; - - rgStepYRad = - ( - MAT(&inverse_matrix, 0, 1) * cx * r2_fy2_2 - + MAT(&inverse_matrix, 1, 1) * cy * r2_fx2_2 - + ( - MAT(&inverse_matrix, 0, 1) * cy - + MAT(&inverse_matrix, 1, 1) * cx - ) - * fxfy_2 - ) - / r2_fx2_fy2sq; - - rgConstantRad = - ( - cx * cx * r2_fy2 - + cy * cy * r2_fx2 - + cx * cy * fxfy_2 - ) - / r2_fx2_fy2sq; - - /* Setup the command buffer. */ - data = &rgConstantLin; - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A04,*(uint32_t*) data)); - data = &rgStepXLin; - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A06,*(uint32_t*) data)); - data = &rgStepYLin; - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A08,*(uint32_t*) data)); - data = &rgConstantRad; - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A05,*(uint32_t*) data)); - data = &rgStepXRad; - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A07,*(uint32_t*) data)); - data = &rgStepYRad; - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A09,*(uint32_t*) data)); - data = &rgStepXXRad; - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A03,*(uint32_t*) data)); - data = &rgStepYYRad; - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A0A,*(uint32_t*) data)); - data = &rgStepXYRad; - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A0B,*(uint32_t*) data)); - VG_LITE_RETURN_ERROR(set_interpolation_steps(target, source->width, source->height, matrix)); - - if(!s_context.premultiply_enabled) { - if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A24, convert_source_format(source->format) | - filter | rad_tile | conversion | 0x01000100)); - } else { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A24, convert_source_format(source->format) | - filter | rad_tile | conversion | 0x00000100)); - } - } else { - /* enable pre-multiplied in imager unit */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A24, convert_source_format(source->format) | - filter | rad_tile | conversion)); - } - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A26, paint_color)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A28, source->address)); - - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2A, tiled_source)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2C, 0)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A2E, source->width)); - - /* Work on path states. */ - matrix = path_matrix; - - if (ts_is_fullscreen == 0){ - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[1], matrix); - point_min = point_max = temp; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[1], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - point_min.x = MAX(point_min.x, 0); - point_min.y = MAX(point_min.y, 0); - point_max.x = MIN(point_max.x, dst_align_width); - point_max.y = MIN(point_max.y, target->height); - - if (s_context.scissor_enabled) { - point_min.x = MAX(point_min.x, s_context.scissor[0]); - point_min.y = MAX(point_min.y, s_context.scissor[1]); - point_max.x = MIN(point_max.x, s_context.scissor[0] + s_context.scissor[2]); - point_max.y = MIN(point_max.y, s_context.scissor[1] + s_context.scissor[3]); - } - } - - /* Convert states into hardware values. */ - blend_mode = convert_blend(blend); - format = convert_path_format(path->format); - quality = convert_path_quality(path->quality); - tiling = (s_context.capabilities.cap.tiled == 2) ? 0x2000000 : 0; - fill = (fill_rule == VG_LITE_FILL_EVEN_ODD) ? 0x10 : 0; - tessellation_size = ( s_context.tsbuffer.tessellation_buffer_size[2] - ? s_context.tsbuffer.tessellation_buffer_size[2] - : s_context.tsbuffer.tessellation_buffer_size[1] - ); - - /* Setup the command buffer. */ - /* Program color register. */ - if(!s_context.premultiply_enabled) { - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, 0x12000000 | s_context.capabilities.cap.tiled | 0x00000002 | imageMode | blend_mode | transparency_mode)); - } else { - /* enable pre-multiplied from VG to VGPE */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A00, 0x02000000 | s_context.capabilities.cap.tiled | 0x00000002 | imageMode | blend_mode | transparency_mode)); - } - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A34, 0x01000400 | format | quality | tiling | fill)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3B, 0x3F800000)); /* Path tessellation SCALE. */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3C, 0x00000000)); /* Path tessellation BIAS. */ - /* Program matrix. */ - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A40, (void *) &matrix->m[0][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A41, (void *) &matrix->m[0][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A42, (void *) &matrix->m[0][2])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A43, (void *) &matrix->m[1][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A44, (void *) &matrix->m[1][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&s_context, 0x0A45, (void *) &matrix->m[1][2])); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) - { - if (path->path_changed != 0) { - if (path->uploaded.handle != NULL) { - free_memory.memory_handle = path->uploaded.handle; - vg_lite_kernel(VG_LITE_FREE, &free_memory); - path->uploaded.address = 0; - path->uploaded.memory = NULL; - path->uploaded.handle = NULL; - } - /* Allocate memory for the path data. */ - memory.bytes = 16 + VG_LITE_ALIGN(path->path_length, 8); - return_offset = (8 + VG_LITE_ALIGN(path->path_length, 8)) / 4; - memory.contiguous = 1; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &memory)); - ((uint64_t *) memory.memory)[(path->path_length + 7) / 8] = 0; - ((uint32_t *) memory.memory)[0] = VG_LITE_DATA((path->path_length + 7) / 8); - ((uint32_t *) memory.memory)[1] = 0; - memcpy((uint8_t *) memory.memory + 8, path->path, path->path_length); - ((uint32_t *) memory.memory)[return_offset] = VG_LITE_RETURN(); - ((uint32_t *) memory.memory)[return_offset + 1] = 0; - - path->uploaded.handle = memory.memory_handle; - path->uploaded.memory = memory.memory; - path->uploaded.address = memory.memory_gpu; - path->uploaded.bytes = memory.bytes; - path->path_changed = 0; - } - } - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - - vglitemDUMP_BUFFER("path", path->uploaded.address, (uint8_t *)(path->uploaded.memory), 0, path->uploaded.bytes); - } - - vglitemDUMP("@[memory 0x%08X 0x%08X]", s_context.tsbuffer.tessellation_buffer_gpu[0], s_context.tsbuffer.tessellation_buffer_size[0]); - - /* Setup tessellation loop. */ - if((path->path_type & 0x1) == VG_LITE_DRAW_FILL_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&s_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&s_context, path->uploaded.address, path->uploaded.bytes)); - } else { - push_data(&s_context, path->path_length, path->path); - } - } - } - } - /* Setup tessellation loop. */ - if(path->path_type == VG_LITE_DRAW_STROKE_PATH || path->path_type == VG_LITE_DRAW_FILL_STROKE_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&s_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&s_context, path->uploaded.address, path->uploaded.bytes)); - } else { - format = convert_path_format(VG_LITE_FP32); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A34, 0x01000200 | format | quality | tiling | 0x0)); - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A02, path->stroke_color)); - push_data(&s_context, path->stroke_path_size, path->stroke_path_data); - } - } - } - } - - /* Notify rendering area (added by MicroEJ) */ - vg_lite_draw_notify_render_area(point_min.x, point_min.y, point_max.x, point_max.y); - - /* Finialize command buffer. */ - VG_LITE_RETURN_ERROR(push_state(&s_context, 0x0A34, 0)); - - vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); -#if DUMP_IMAGE - dump_img(source->memory, source->width, source->height, source->format); -#endif - return error; -} -#else -vg_lite_error_t vg_lite_set_CLUT(uint32_t count, - uint32_t * colors) -{ - vg_lite_tls_t* tls; - vg_lite_error_t error = VG_LITE_SUCCESS; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - if(!tls->t_context.s_ftable.ftable[gcFEATURE_BIT_VG_IM_INDEX_FORMAT]) - return VG_LITE_NOT_SUPPORT; - - switch (count) { - case 2: - tls->t_context.clut_dirty[0] = 1; - tls->t_context.clut_used[0] = 0; - if(!tls->t_context.colors[0]) - tls->t_context.colors[0] = (uint32_t *)malloc(count * sizeof(uint32_t)); - memcpy(tls->t_context.colors[0], colors, count * sizeof(uint32_t)); - break; - case 4: - tls->t_context.clut_dirty[1] = 1; - tls->t_context.clut_used[1] = 0; - if(!tls->t_context.colors[1]) - tls->t_context.colors[1] = (uint32_t *)malloc(count * sizeof(uint32_t)); - memcpy(tls->t_context.colors[1], colors, count * sizeof(uint32_t)); - break; - case 16: - tls->t_context.clut_dirty[2] = 1; - tls->t_context.clut_used[2] = 0; - if(!tls->t_context.colors[2]) - tls->t_context.colors[2] = (uint32_t *)malloc(count * sizeof(uint32_t)); - memcpy(tls->t_context.colors[2], colors, count * sizeof(uint32_t)); - break; - case 256: - tls->t_context.clut_dirty[3] = 1; - tls->t_context.clut_used[3] = 0; - if(!tls->t_context.colors[3]) - tls->t_context.colors[3] = (uint32_t *)malloc(count * sizeof(uint32_t)); - memcpy(tls->t_context.colors[3], colors, count * sizeof(uint32_t)); - break; - - default: - error = VG_LITE_INVALID_ARGUMENT; - return error; - break; - } - - return error; -} - -vg_lite_error_t vg_lite_draw_pattern(vg_lite_buffer_t * target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix0, - vg_lite_buffer_t * source, - vg_lite_matrix_t * matrix1, - vg_lite_blend_t blend, - vg_lite_pattern_mode_t pattern_mode, - vg_lite_color_t pattern_color, - vg_lite_filter_t filter) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t imageMode; - uint32_t blend_mode; - uint32_t conversion = 0; - uint32_t tiled_source; - vg_lite_matrix_t * matrix = matrix1; - uint32_t pattern_tile = 0; - uint32_t transparency_mode = 0; - vg_lite_tls_t* tls; - int32_t src_align_width,dst_align_width; - uint32_t mul, div, align; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - /* The following code is from "draw path" */ - uint32_t format, quality, tiling, fill; - uint32_t tessellation_size; -#if DUMP_COMMAND - vg_lite_kernel_allocate_t memory; - uint32_t return_offset = 0; -#endif - vg_lite_point_t point_min = {0}, point_max = {0}, temp = {0}; - int x, y, width, height; - uint8_t ts_is_fullscreen = 0; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_QUALITY_8X) && path->quality == VG_LITE_UPPER){ - return VG_LITE_NOT_SUPPORT; - } - - if(source->format == VG_LITE_A4 || source->format == VG_LITE_A8) { - return VG_LITE_NOT_SUPPORT; - } - - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); - width = tls->t_context.tsbuffer.tessellation_width_height & 0xFFFF; - height = tls->t_context.tsbuffer.tessellation_width_height >> 16; - get_format_bytes(target->format, &mul, &div, &align); - dst_align_width = target->stride * div / mul; - - if(width == 0 || height == 0) - return VG_LITE_NO_CONTEXT; - if ((dst_align_width <= width) && (target->height <= height)) - { - ts_is_fullscreen = 1; - point_min.x = 0; - point_min.y = 0; - point_max.x = dst_align_width; - point_max.y = target->height; - } - - /* If target is L8 and source is in YUV or RGB (not L8 or A8) then we have to convert RGB into L8. */ - if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { - conversion = 0x80000000; - } - - /* Determine image mode (NORMAL or MULTIPLY) depending on the color. */ - imageMode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; - tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; - - if (pattern_mode == VG_LITE_PATTERN_COLOR) - { - uint8_t a,r,g,b; - pattern_tile = 0; - a = pattern_color >> 24; - r = pattern_color >> 16; - g = pattern_color >> 8; - b = pattern_color; - pattern_color = (a << 24) | (b << 16) | (g << 8) | r; - } - else if (pattern_mode == VG_LITE_PATTERN_PAD) - { - pattern_tile = 0x1000; - } - else - { - return VG_LITE_INVALID_ARGUMENT; - } - - if(tls->t_context.ts_dirty){ - memcpy(CMDBUF_BUFFER(tls->t_context) + CMDBUF_OFFSET(tls->t_context), tls->t_context.ts_record, 80); - CMDBUF_OFFSET(tls->t_context) += 80; - tls->t_context.ts_dirty = 0; - tls->t_context.ts_init_used = 1; - } - else - { - tls->t_context.ts_init_use = 1; - } - - /* Setup the command buffer. */ - if(source->format >= VG_LITE_INDEX_1 && source->format <= VG_LITE_INDEX_8) - { - /* this task will use index format,set index_flag to 1. */ - tls->t_context.index_format = 1; - switch (source->format) { - case VG_LITE_INDEX_8: - if(tls->t_context.clut_dirty[3]){ - VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0B00, 256, tls->t_context.colors[3])); - tls->t_context.clut_dirty[3] = 0; - } - else - { - tls->t_context.clut_used[3] = 1; - } - break; - - case VG_LITE_INDEX_4: - if(tls->t_context.clut_dirty[2]){ - VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0AA0, 16, tls->t_context.colors[2])); - tls->t_context.clut_dirty[2] = 0; - } - else - { - tls->t_context.clut_used[2] = 1; - } - break; - - case VG_LITE_INDEX_2: - if(tls->t_context.clut_dirty[1]){ - VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0A9C, 4, tls->t_context.colors[1])); - tls->t_context.clut_dirty[1] = 0; - } - else - { - tls->t_context.clut_used[1] = 1; - } - break; - - default: - if(tls->t_context.clut_dirty[0]){ - VG_LITE_RETURN_ERROR(push_states(&tls->t_context, 0x0A98, 2, tls->t_context.colors[0])); - tls->t_context.clut_dirty[0] = 0; - } - else - { - tls->t_context.clut_used[0] = 1; - } - } - } - get_format_bytes(source->format, &mul, &div, &align); - src_align_width = source->stride * div / mul; - VG_LITE_RETURN_ERROR(set_interpolation_steps(target, src_align_width, source->height, matrix)); - - if(!tls->t_context.premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { - if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A25, convert_source_format(source->format) | - filter | pattern_tile | conversion | 0x01000100)); - } else { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A25, convert_source_format(source->format) | - filter | pattern_tile | conversion | 0x00000100)); - } - } else { - /* enable pre-multiplied in imager unit */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A25, convert_source_format(source->format) | - filter | pattern_tile | conversion)); - } - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A27, pattern_color)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A29, source->address)); - - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2B, source->stride | tiled_source)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2D, 0)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2F, src_align_width | (source->height << 16))); - - /* Work on path states. */ - matrix = matrix0; - - if (ts_is_fullscreen == 0){ - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[1], matrix); - point_min = point_max = temp; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[1], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - point_min.x = MAX(point_min.x, 0); - point_min.y = MAX(point_min.y, 0); - point_max.x = MIN(point_max.x, dst_align_width); - point_max.y = MIN(point_max.y, target->height); - - if (tls->t_context.scissor_enabled) { - point_min.x = MAX(point_min.x, tls->t_context.scissor[0]); - point_min.y = MAX(point_min.y, tls->t_context.scissor[1]); - point_max.x = MIN(point_max.x, tls->t_context.scissor[0] + tls->t_context.scissor[2]); - point_max.y = MIN(point_max.y, tls->t_context.scissor[1] + tls->t_context.scissor[3]); - } - } - - /* Convert states into hardware values. */ - blend_mode = convert_blend(blend); - format = convert_path_format(path->format); - quality = convert_path_quality(path->quality); - tiling = (tls->t_context.capabilities.cap.tiled == 2) ? 0x2000000 : 0; - fill = (fill_rule == VG_LITE_FILL_EVEN_ODD) ? 0x10 : 0; - tessellation_size = ( tls->t_context.tsbuffer.tessellation_buffer_size[2] - ? tls->t_context.tsbuffer.tessellation_buffer_size[2] - : tls->t_context.tsbuffer.tessellation_buffer_size[1] - ); - - /* Setup the command buffer. */ - /* Program color register. */ - if(!tls->t_context.premultiply_enabled && source->format != VG_LITE_A8 && source->format != VG_LITE_A4) { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x10000000 | tls->t_context.capabilities.cap.tiled | 0x00000002 | imageMode | blend_mode | transparency_mode)); - } else { - /* enable pre-multiplied from VG to VGPE */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, tls->t_context.capabilities.cap.tiled | 0x00000002 | imageMode | blend_mode | transparency_mode)); - } - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A34, 0x01000400 | format | quality | tiling | fill)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3B, 0x3F800000)); /* Path tessellation SCALE. */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3C, 0x00000000)); /* Path tessellation BIAS. */ - /* Program matrix. */ - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A40, (void *) &matrix->m[0][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A41, (void *) &matrix->m[0][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A42, (void *) &matrix->m[0][2])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A43, (void *) &matrix->m[1][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A44, (void *) &matrix->m[1][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A45, (void *) &matrix->m[1][2])); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - - vglitemDUMP_BUFFER("path", path->uploaded.address, (uint8_t *)(path->uploaded.memory), 0, path->uploaded.bytes); - } - - vglitemDUMP("@[memory 0x%08X 0x%08X]", tls->t_context.tsbuffer.tessellation_buffer_gpu[0], tls->t_context.tsbuffer.tessellation_buffer_size[0]); - - /* Setup tessellation loop. */ - if((path->path_type & 0x1) == VG_LITE_DRAW_FILL_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&tls->t_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&tls->t_context, path->uploaded.address, path->uploaded.bytes)); -#if (DUMP_COMMAND) - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[0], 0); - - unsigned char* pt = (unsigned char*) memory.memory; - - for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) - { - if (i % 8 == 0) - fprintf(fp, "Command buffer: "); - - if (i % 4 == 0) - fprintf(fp, "0x"); - - for (int j = 3; j >= 0; --j) - fprintf(fp, "%02x", pt[i + j]); - - if ((i / 4 + 1) % 2 == 0) - fprintf(fp, ",\n"); - else - fprintf(fp, ", "); - } - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[return_offset], 0); - - fclose(fp); - fp = NULL; -#endif - } else { - push_data(&tls->t_context, path->path_length, path->path); - } - } - } - } - /* Setup tessellation loop. */ - if(path->path_type == VG_LITE_DRAW_STROKE_PATH || path->path_type == VG_LITE_DRAW_FILL_STROKE_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&tls->t_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&tls->t_context, path->uploaded.address, path->uploaded.bytes)); -#if (DUMP_COMMAND) - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[0], 0); - - unsigned char* pt = (unsigned char*) memory.memory; - - for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) - { - if (i % 8 == 0) - fprintf(fp, "Command buffer: "); - - if (i % 4 == 0) - fprintf(fp, "0x"); - - for (int j = 3; j >= 0; --j) - fprintf(fp, "%02x", pt[i + j]); - - if ((i / 4 + 1) % 2 == 0) - fprintf(fp, ",\n"); - else - fprintf(fp, ", "); - } - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[return_offset], 0); - - fclose(fp); - fp = NULL; -#endif - } else { - format = convert_path_format(VG_LITE_FP32); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A34, 0x01000200 | format | quality | tiling | 0x0)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A02, path->stroke_color)); - push_data(&tls->t_context, path->stroke_path_size, path->stroke_path_data); - } - } - } - } - - /* Finialize command buffer. */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A34, 0)); - VG_LITE_RETURN_ERROR(flush_target()); - - vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); -#if DUMP_IMAGE - dump_img(source->memory, src_align_width, source->height, source->format); -#endif - - tls->t_context.ts_init = 1; - return error; -} - -vg_lite_error_t vg_lite_draw_linear_gradient(vg_lite_buffer_t * target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * path_matrix, - vg_lite_linear_gradient_ext_t *grad, - vg_lite_color_t paint_color, - vg_lite_blend_t blend, - vg_lite_filter_t filter) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t image_mode; - uint32_t blend_mode; - uint32_t conversion = 0; - uint32_t tiled_source; - int32_t dst_align_width; - uint32_t mul, div, align; - vg_lite_matrix_t inverse_matrix; - vg_lite_buffer_t * source = &grad->image; - vg_lite_matrix_t * matrix = &grad->matrix; - uint32_t linear_tile = 0; - uint32_t transparency_mode = 0; - void *data; - - /* The following code is from "draw path" */ - uint32_t format, quality, tiling, fill; - uint32_t tessellation_size; - - vg_lite_kernel_allocate_t memory; - vg_lite_kernel_free_t free_memory; - uint32_t return_offset = 0; - - vg_lite_point_t point_min = {0}, point_max = {0}, temp = {0}; - int x, y, width, height; - uint8_t ts_is_fullscreen = 0; - - vg_lite_float_t dx, dy, dxdx_dydy; - vg_lite_float_t lg_step_x_lin, lg_step_y_lin, lg_constant_lin; - - vg_lite_tls_t* tls; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_LINEAR_GRADIENT_EXT)) - return VG_LITE_NOT_SUPPORT; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_QUALITY_8X) && path->quality == VG_LITE_UPPER){ - return VG_LITE_NOT_SUPPORT; - } - - if(source->format == VG_LITE_A4 || source->format == VG_LITE_A8) { - return VG_LITE_NOT_SUPPORT; - } - - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); - width = tls->t_context.tsbuffer.tessellation_width_height & 0xFFFF; - height = tls->t_context.tsbuffer.tessellation_width_height >> 16; - get_format_bytes(target->format, &mul, &div, &align); - dst_align_width = target->stride * div / mul; - if(width == 0 || height == 0) - return VG_LITE_NO_CONTEXT; - if ((dst_align_width <= width) && (target->height <= height)) - { - ts_is_fullscreen = 1; - point_min.x = 0; - point_min.y = 0; - point_max.x = dst_align_width; - point_max.y = target->height; - } - - /* If target is L8 and source is in YUV or RGB (not L8 or A8) then we have to convert RGB into L8. */ - if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { - conversion = 0x80000000; - } - - /* Determine image mode (NORMAL or MULTIPLY) depending on the color. */ - image_mode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; - tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; - - linear_tile = (grad->spread_mode == VG_LITE_RADIAL_GRADIENT_SPREAD_FILL) ? 0 : - (grad->spread_mode == VG_LITE_RADIAL_GRADIENT_SPREAD_PAD) ? 0x1000 : - (grad->spread_mode == VG_LITE_RADIAL_GRADIENT_SPREAD_REPEAT) ? 0x2000 : 0x3000; - - if (grad->spread_mode == VG_LITE_RADIAL_GRADIENT_SPREAD_FILL) - { - uint8_t a,r,g,b; - a = paint_color >> 24; - r = paint_color >> 16; - g = paint_color >> 8; - b = paint_color; - paint_color = (a << 24) | (b << 16) | (g << 8) | r; - } - - /* compute radial gradient paremeters */ - - if (!inverse(&inverse_matrix, matrix)) - return VG_LITE_INVALID_ARGUMENT; - - dx = grad->linear_gradient.X1 - grad->linear_gradient.X0; - dy = grad->linear_gradient.Y1 - grad->linear_gradient.Y0; - dxdx_dydy = dx * dx + dy * dy; - - /* - ** dx (T(x) - x0) + dy (T(y) - y0) - ** g = ------------------------------- - ** dx^2 + dy^2 - ** - ** where - ** - ** dx := x1 - x0 - ** dy := y1 - y1 - ** T(x) := (x + 0.5) m00 + (y + 0.5) m01 + m02 - ** = x m00 + y m01 + 0.5 (m00 + m01) + m02 - ** T(y) := (x + 0.5) m10 + (y + 0.5) m11 + m12 - ** = x m10 + y m11 + 0.5 (m10 + m11) + m12. - ** - ** We can factor the top line into: - ** - ** = dx (x m00 + y m01 + 0.5 (m00 + m01) + m02 - x0) - ** + dy (x m10 + y m11 + 0.5 (m10 + m11) + m12 - y0) - ** - ** = x (dx m00 + dy m10) - ** + y (dx m01 + dy m11) - ** + dx (0.5 (m00 + m01) + m02 - x0) - ** + dy (0.5 (m10 + m11) + m12 - y0). - */ - - lg_step_x_lin - = (dx * MAT(&inverse_matrix, 0, 0) + dy * MAT(&inverse_matrix, 1, 0)) - / dxdx_dydy; - - lg_step_y_lin - = (dx * MAT(&inverse_matrix, 0, 1) + dy * MAT(&inverse_matrix, 1, 1)) - / dxdx_dydy; - - lg_constant_lin = - ( - ( - 0.5f * ( MAT(&inverse_matrix, 0, 0) + MAT(&inverse_matrix, 0, 1) ) - + MAT(&inverse_matrix, 0, 2) - grad->linear_gradient.X0 - ) * dx - - + - - ( - 0.5f * ( MAT(&inverse_matrix, 1, 0) + MAT(&inverse_matrix, 1, 1) ) - + MAT(&inverse_matrix, 1, 2) - grad->linear_gradient.Y0 - ) * dy - ) - / dxdx_dydy; - - if(tls->t_context.ts_dirty){ - memcpy(CMDBUF_BUFFER(tls->t_context) + CMDBUF_OFFSET(tls->t_context), tls->t_context.ts_record, 80); - CMDBUF_OFFSET(tls->t_context) += 80; - tls->t_context.ts_dirty = 0; - tls->t_context.ts_init_used = 1; - } - else - { - tls->t_context.ts_init_use = 1; - } - - /* Setup the command buffer. */ - - /* linear gradient parameters*/ - data = &lg_constant_lin; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A04,*(uint32_t*) data)); - data = &lg_step_x_lin; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A06,*(uint32_t*) data)); - data = &lg_step_y_lin; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A08,*(uint32_t*) data)); - - VG_LITE_RETURN_ERROR(set_interpolation_steps(target, source->width, source->height, matrix)); - - if(!tls->t_context.premultiply_enabled) { - if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A24, convert_source_format(source->format) | - filter | linear_tile | conversion | 0x01000100)); - } else { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A24, convert_source_format(source->format) | - filter | linear_tile | conversion | 0x00000100)); - } - } else { - /* enable pre-multiplied in imager unit */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A24, convert_source_format(source->format) | - filter | linear_tile | conversion)); - } - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A26, paint_color)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A28, source->address)); - - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2A, tiled_source)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2C, 0)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2E, source->width)); - - /* Work on path states. */ - matrix = path_matrix; - - if (ts_is_fullscreen == 0){ - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[1], matrix); - point_min = point_max = temp; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[1], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - point_min.x = MAX(point_min.x, 0); - point_min.y = MAX(point_min.y, 0); - point_max.x = MIN(point_max.x, dst_align_width); - point_max.y = MIN(point_max.y, target->height); - - if (tls->t_context.scissor_enabled) { - point_min.x = MAX(point_min.x, tls->t_context.scissor[0]); - point_min.y = MAX(point_min.y, tls->t_context.scissor[1]); - point_max.x = MIN(point_max.x, tls->t_context.scissor[0] + tls->t_context.scissor[2]); - point_max.y = MIN(point_max.y, tls->t_context.scissor[1] + tls->t_context.scissor[3]); - } - } - - /* Convert states into hardware values. */ - blend_mode = convert_blend(blend); - format = convert_path_format(path->format); - quality = convert_path_quality(path->quality); - tiling = (tls->t_context.capabilities.cap.tiled == 2) ? 0x2000000 : 0; - fill = (fill_rule == VG_LITE_FILL_EVEN_ODD) ? 0x10 : 0; - tessellation_size = ( tls->t_context.tsbuffer.tessellation_buffer_size[2] - ? tls->t_context.tsbuffer.tessellation_buffer_size[2] - : tls->t_context.tsbuffer.tessellation_buffer_size[1] - ); - - /* Setup the command buffer. */ - /* Program color register. */ - if(!tls->t_context.premultiply_enabled) { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x11000000 | tls->t_context.capabilities.cap.tiled | 0x00000002 | image_mode | blend_mode | transparency_mode)); - } else { - /* enable pre-multiplied from VG to VGPE */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x01000000 | tls->t_context.capabilities.cap.tiled | 0x00000002 | image_mode | blend_mode | transparency_mode)); - } - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A34, 0x01000400 | format | quality | tiling | fill)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3B, 0x3F800000)); /* Path tessellation SCALE. */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3C, 0x00000000)); /* Path tessellation BIAS. */ - /* Program matrix. */ - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A40, (void *) &matrix->m[0][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A41, (void *) &matrix->m[0][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A42, (void *) &matrix->m[0][2])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A43, (void *) &matrix->m[1][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A44, (void *) &matrix->m[1][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A45, (void *) &matrix->m[1][2])); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) - { - if (path->path_changed != 0) { - if (path->uploaded.handle != NULL) { - free_memory.memory_handle = path->uploaded.handle; - vg_lite_kernel(VG_LITE_FREE, &free_memory); - path->uploaded.address = 0; - path->uploaded.memory = NULL; - path->uploaded.handle = NULL; - } - /* Allocate memory for the path data. */ - memory.bytes = 16 + VG_LITE_ALIGN(path->path_length, 8); - return_offset = (8 + VG_LITE_ALIGN(path->path_length, 8)) / 4; - memory.contiguous = 1; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &memory)); - ((uint64_t *) memory.memory)[(path->path_length + 7) / 8] = 0; - ((uint32_t *) memory.memory)[0] = VG_LITE_DATA((path->path_length + 7) / 8); - ((uint32_t *) memory.memory)[1] = 0; - memcpy((uint8_t *) memory.memory + 8, path->path, path->path_length); - ((uint32_t *) memory.memory)[return_offset] = VG_LITE_RETURN(); - ((uint32_t *) memory.memory)[return_offset + 1] = 0; - - path->uploaded.handle = memory.memory_handle; - path->uploaded.memory = memory.memory; - path->uploaded.address = memory.memory_gpu; - path->uploaded.bytes = memory.bytes; - path->path_changed = 0; - } - } - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - - vglitemDUMP_BUFFER("path", path->uploaded.address, (uint8_t *)(path->uploaded.memory), 0, path->uploaded.bytes); - } - - vglitemDUMP("@[memory 0x%08X 0x%08X]", tls->t_context.tsbuffer.tessellation_buffer_gpu[0], tls->t_context.tsbuffer.tessellation_buffer_size[0]); - - /* Setup tessellation loop. */ - if((path->path_type & 0x1) == VG_LITE_DRAW_FILL_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&tls->t_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&tls->t_context, path->uploaded.address, path->uploaded.bytes)); -#if (DUMP_COMMAND) - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[0], 0); - - unsigned char* pt = (unsigned char*) memory.memory; - - for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) - { - if (i % 8 == 0) - fprintf(fp, "Command buffer: "); - - if (i % 4 == 0) - fprintf(fp, "0x"); - - for (int j = 3; j >= 0; --j) - fprintf(fp, "%02x", pt[i + j]); - - if ((i / 4 + 1) % 2 == 0) - fprintf(fp, ",\n"); - else - fprintf(fp, ", "); - } - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[return_offset], 0); - - fclose(fp); - fp = NULL; -#endif - } else { - push_data(&tls->t_context, path->path_length, path->path); - } - } - } - } - /* Setup tessellation loop. */ - if(path->path_type == VG_LITE_DRAW_STROKE_PATH || path->path_type == VG_LITE_DRAW_FILL_STROKE_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&tls->t_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&tls->t_context, path->uploaded.address, path->uploaded.bytes)); -#if (DUMP_COMMAND) - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[0], 0); - - unsigned char* pt = (unsigned char*) memory.memory; - - for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) - { - if (i % 8 == 0) - fprintf(fp, "Command buffer: "); - - if (i % 4 == 0) - fprintf(fp, "0x"); - - for (int j = 3; j >= 0; --j) - fprintf(fp, "%02x", pt[i + j]); - - if ((i / 4 + 1) % 2 == 0) - fprintf(fp, ",\n"); - else - fprintf(fp, ", "); - } - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[return_offset], 0); - - fclose(fp); - fp = NULL; -#endif - } else { - format = convert_path_format(VG_LITE_FP32); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A34, 0x01000200 | format | quality | tiling | 0x0)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A02, path->stroke_color)); - push_data(&tls->t_context, path->stroke_path_size, path->stroke_path_data); - } - } - } - } - - /* Finialize command buffer. */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A34, 0)); - - vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); -#if DUMP_IMAGE - dump_img(source->memory, source->width, source->height, source->format); -#endif - - tls->t_context.ts_init = 1; - return error; -} - -vg_lite_error_t vg_lite_draw_radial_gradient(vg_lite_buffer_t * target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * path_matrix, - vg_lite_radial_gradient_t *grad, - vg_lite_color_t paint_color, - vg_lite_blend_t blend, - vg_lite_filter_t filter) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - uint32_t imageMode; - uint32_t blend_mode; - uint32_t conversion = 0; - uint32_t tiled_source; - int32_t dst_align_width; - uint32_t mul, div, align; - vg_lite_matrix_t inverse_matrix; - vg_lite_buffer_t * source = &grad->image; - vg_lite_matrix_t * matrix = &grad->matrix; - uint32_t rad_tile = 0; - uint32_t transparency_mode = 0; - void *data; - - /* The following code is from "draw path" */ - uint32_t format, quality, tiling, fill; - uint32_t tessellation_size; - - vg_lite_kernel_allocate_t memory; - vg_lite_kernel_free_t free_memory; - uint32_t return_offset = 0; - - vg_lite_point_t point_min = {0}, point_max = {0}, temp = {0}; - int x, y, width, height; - uint8_t ts_is_fullscreen = 0; - - vg_lite_float_t radius; - - vg_lite_float_t centerX, centerY; - vg_lite_float_t focalX, focalY; - vg_lite_float_t fx, fy; - vg_lite_float_t fxfy_2; - vg_lite_float_t radius2; - vg_lite_float_t r2_fx2, r2_fy2; - vg_lite_float_t r2_fx2_2, r2_fy2_2; - vg_lite_float_t r2_fx2_fy2; - vg_lite_float_t r2_fx2_fy2sq; - vg_lite_float_t cx, cy; - - vg_lite_float_t rgConstantLin, rgStepXLin, rgStepYLin; - vg_lite_float_t rgConstantRad, rgStepXRad, rgStepYRad; - vg_lite_float_t rgStepXXRad, rgStepYYRad, rgStepXYRad; - - vg_lite_tls_t* tls; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_RADIAL_GRADIENT)) - return VG_LITE_NOT_SUPPORT; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_QUALITY_8X) && path->quality == VG_LITE_UPPER){ - return VG_LITE_NOT_SUPPORT; - } - - if(source->format == VG_LITE_A4 || source->format == VG_LITE_A8) { - return VG_LITE_NOT_SUPPORT; - } - - radius = grad->radialGradient.r; - if(radius <= 0) - return VG_LITE_INVALID_ARGUMENT; - - error = set_render_target(target); - if (error != VG_LITE_SUCCESS) { - return error; - } else if (error == VG_LITE_NO_CONTEXT) { - /* If scissoring is enabled and no valid scissoring rectangles - are present, no drawing occurs */ - return VG_LITE_SUCCESS; - } - - transparency_mode = (source->transparency_mode == VG_LITE_IMAGE_TRANSPARENT ? 0x8000:0); - width = tls->t_context.tsbuffer.tessellation_width_height & 0xFFFF; - height = tls->t_context.tsbuffer.tessellation_width_height >> 16; - get_format_bytes(target->format, &mul, &div, &align); - dst_align_width = target->stride * div / mul; - if(width == 0 || height == 0) - return VG_LITE_NO_CONTEXT; - if ((dst_align_width <= width) && (target->height <= height)) - { - ts_is_fullscreen = 1; - point_min.x = 0; - point_min.y = 0; - point_max.x = dst_align_width; - point_max.y = target->height; - } - - /* If target is L8 and source is in YUV or RGB (not L8 or A8) then we have to convert RGB into L8. */ - if ((target->format == VG_LITE_L8) && ((source->format != VG_LITE_L8) && (source->format != VG_LITE_A8))) { - conversion = 0x80000000; - } - - /* Determine image mode (NORMAL or MULTIPLY) depending on the color. */ - imageMode = (source->image_mode == VG_LITE_NONE_IMAGE_MODE) ? 0 : (source->image_mode == VG_LITE_MULTIPLY_IMAGE_MODE) ? 0x00002000 : 0x00001000; - tiled_source = (source->tiled != VG_LITE_LINEAR) ? 0x10000000 : 0 ; - - rad_tile = (grad->SpreadMode == VG_LITE_RADIAL_GRADIENT_SPREAD_FILL) ? 0 : - (grad->SpreadMode == VG_LITE_RADIAL_GRADIENT_SPREAD_PAD) ? 0x1000 : - (grad->SpreadMode == VG_LITE_RADIAL_GRADIENT_SPREAD_REPEAT) ? 0x2000 : 0x3000; - - if (grad->SpreadMode == VG_LITE_RADIAL_GRADIENT_SPREAD_FILL) - { - uint8_t a,r,g,b; - a = paint_color >> 24; - r = paint_color >> 16; - g = paint_color >> 8; - b = paint_color; - paint_color = (a << 24) | (b << 16) | (g << 8) | r; - } - - /* compute radial gradient paremeters */ - - /* Compute inverse matrix. */ - if (!inverse(&inverse_matrix, matrix)) - return VG_LITE_INVALID_ARGUMENT; - - /* Make shortcuts to the gradient information. */ - centerX = grad->radialGradient.cx; - centerY = grad->radialGradient.cy; - focalX = grad->radialGradient.fx; - focalY = grad->radialGradient.fy; - - /* Compute constants of the equation. */ - fx = focalX - centerX; - fy = focalY - centerY; - radius2 = radius * radius; - if (fx*fx + fy*fy > radius2) - { - /* If the focal point is outside the circle, let's move it - to inside the circle. Per vg11 spec pg125 "If (fx, fy) lies outside ... - For here, we set it at 0.9 ratio to the center. - */ - vg_lite_float_t fr = (vg_lite_float_t)sqrt(fx*fx + fy*fy); - fx = radius * fx / fr * 0.9f; - fy = radius * fy / fr * 0.9f; - focalX = grad->radialGradient.fx + fx; - focalY = grad->radialGradient.fy + fy; - } - - fxfy_2 = 2.0f * fx * fy; - r2_fx2 = radius2 - fx * fx; - r2_fy2 = radius2 - fy * fy; - r2_fx2_2 = 2.0f * r2_fx2; - r2_fy2_2 = 2.0f * r2_fy2; - r2_fx2_fy2 = r2_fx2 - fy * fy; - r2_fx2_fy2sq = r2_fx2_fy2 * r2_fx2_fy2; - - /* _____________________________________ - ** dx fx + dy fy + \/r^2 (dx^2 + dy^2) - (dx fy - dy fx)^2 - ** g = ------------------------------------------------------- - ** r^2 - fx^2 - fy^2 - ** - ** Where - ** - ** dx := F(x) - focalX - ** dy := F(y) - focalY - ** fx := focalX - centerX - ** fy := focalX - centerY - ** - ** and - ** - ** F(x) := (x + 0.5) m00 + (y + 0.5) m01 + m02 - ** F(y) := (x + 0.5) m10 + (y + 0.5) m11 + m12 - ** - ** So, dx can be factored into - ** - ** dx = (x + 0.5) m00 + (y + 0.5) m01 + m02 - focalX - ** = x m00 + y m01 + 0.5 m00 + 0.5 m01 + m02 - focalX - ** - ** = x m00 + y m01 + cx - ** - ** where - ** - ** cx := 0.5 m00 + 0.5 m01 + m02 - focalX - ** - ** The same way we can factor dy into - ** - ** dy = x m10 + y m11 + cy - ** - ** where - ** - ** cy := 0.5 m10 + 0.5 m11 + m12 - focalY. - ** - ** Now we can rewrite g as - ** ______________________________________ - ** dx fx + dy fy / r^2 (dx^2 + dy^2) - (dx fy - dy fx)^2 - ** g = ----------------- + \ / ------------------------------------- - ** r^2 - fx^2 - fy^2 \/ (r^2 - fx^2 - fy^2)^2 - ** ____ - ** = gLin + \/gRad - ** - ** where - ** - ** dx fx + dy fy - ** gLin := ----------------- - ** r^2 - fx^2 - fy^2 - ** - ** r^2 (dx^2 + dy^2) - (dx fy - dy fx)^2 - ** gRad := ------------------------------------- - ** (r^2 - fx^2 - fy^2)^2 - */ - - cx - = 0.5f * ( MAT(&inverse_matrix, 0, 0) + MAT(&inverse_matrix, 0, 1) ) - + MAT(&inverse_matrix, 0, 2) - - focalX; - - cy - = 0.5f * ( MAT(&inverse_matrix, 1, 0) + MAT(&inverse_matrix, 1, 1) ) - + MAT(&inverse_matrix, 1, 2) - - focalY; - - /* - ** dx fx + dy fy - ** gLin := ----------------- - ** r^2 - fx^2 - fy^2 - ** - ** We can factor the top half into - ** - ** = (x m00 + y m01 + cx) fx + (x m10 + y m11 + cy) fy - ** - ** = x (m00 fx + m10 fy) - ** + y (m01 fx + m11 fy) - ** + cx fx + cy fy. - */ - - rgStepXLin - = ( MAT(&inverse_matrix, 0, 0) * fx + MAT(&inverse_matrix, 1, 0) * fy ) - / r2_fx2_fy2; - - rgStepYLin - = ( MAT(&inverse_matrix, 0, 1) * fx + MAT(&inverse_matrix, 1, 1) * fy ) - / r2_fx2_fy2; - - rgConstantLin = ( cx * fx + cy * fy ) / r2_fx2_fy2; - - /* - ** r^2 (dx^2 + dy^2) - (dx fy - dy fx)^2 - ** gRad := ------------------------------------- - ** (r^2 - fx^2 - fy^2)^2 - ** - ** r^2 (dx^2 + dy^2) - dx^2 fy^2 - dy^2 fx^2 + 2 dx dy fx fy - ** := --------------------------------------------------------- - ** (r^2 - fx^2 - fy^2)^2 - ** - ** dx^2 (r^2 - fy^2) + dy^2 (r^2 - fx^2) + 2 dx dy fx fy - ** := ----------------------------------------------------- - ** (r^2 - fx^2 - fy^2)^2 - ** - ** First, lets factor dx^2 into - ** - ** dx^2 = (x m00 + y m01 + cx)^2 - ** = x^2 m00^2 + y^2 m01^2 + 2 x y m00 m01 - ** + 2 x m00 cx + 2 y m01 cx + cx^2 - ** - ** = x^2 (m00^2) - ** + y^2 (m01^2) - ** + x y (2 m00 m01) - ** + x (2 m00 cx) - ** + y (2 m01 cx) - ** + cx^2. - ** - ** The same can be done for dy^2: - ** - ** dy^2 = x^2 (m10^2) - ** + y^2 (m11^2) - ** + x y (2 m10 m11) - ** + x (2 m10 cy) - ** + y (2 m11 cy) - ** + cy^2. - ** - ** Let's also factor dx dy into - ** - ** dx dy = (x m00 + y m01 + cx) (x m10 + y m11 + cy) - ** = x^2 m00 m10 + y^2 m01 m11 + x y m00 m11 + x y m01 m10 - ** + x m00 cy + x m10 cx + y m01 cy + y m11 cx + cx cy - ** - ** = x^2 (m00 m10) - ** + y^2 (m01 m11) - ** + x y (m00 m11 + m01 m10) - ** + x (m00 cy + m10 cx) - ** + y (m01 cy + m11 cx) - ** + cx cy. - ** - ** Now that we have all this, lets look at the top of gRad. - ** - ** = dx^2 (r^2 - fy^2) + dy^2 (r^2 - fx^2) + 2 dx dy fx fy - ** = x^2 m00^2 (r^2 - fy^2) + y^2 m01^2 (r^2 - fy^2) - ** + x y 2 m00 m01 (r^2 - fy^2) + x 2 m00 cx (r^2 - fy^2) - ** + y 2 m01 cx (r^2 - fy^2) + cx^2 (r^2 - fy^2) - ** + x^2 m10^2 (r^2 - fx^2) + y^2 m11^2 (r^2 - fx^2) - ** + x y 2 m10 m11 (r^2 - fx^2) + x 2 m10 cy (r^2 - fx^2) - ** + y 2 m11 cy (r^2 - fx^2) + cy^2 (r^2 - fx^2) - ** + x^2 m00 m10 2 fx fy + y^2 m01 m11 2 fx fy - ** + x y (m00 m11 + m01 m10) 2 fx fy - ** + x (m00 cy + m10 cx) 2 fx fy + y (m01 cy + m11 cx) 2 fx fy - ** + cx cy 2 fx fy - ** - ** = x^2 ( m00^2 (r^2 - fy^2) - ** + m10^2 (r^2 - fx^2) - ** + m00 m10 2 fx fy - ** ) - ** + y^2 ( m01^2 (r^2 - fy^2) - ** + m11^2 (r^2 - fx^2) - ** + m01 m11 2 fx fy - ** ) - ** + x y ( 2 m00 m01 (r^2 - fy^2) - ** + 2 m10 m11 (r^2 - fx^2) - ** + (m00 m11 + m01 m10) 2 fx fy - ** ) - ** + x ( 2 m00 cx (r^2 - fy^2) - ** + 2 m10 cy (r^2 - fx^2) - ** + (m00 cy + m10 cx) 2 fx fy - ** ) - ** + y ( 2 m01 cx (r^2 - fy^2) - ** + 2 m11 cy (r^2 - fx^2) - ** + (m01 cy + m11 cx) 2 fx fy - ** ) - ** + cx^2 (r^2 - fy^2) + cy^2 (r^2 - fx^2) + cx cy 2 fx fy. - */ - - rgStepXXRad = - ( - MAT(&inverse_matrix, 0, 0) * MAT(&inverse_matrix, 0, 0) * r2_fy2 - + MAT(&inverse_matrix, 1, 0) * MAT(&inverse_matrix, 1, 0) * r2_fx2 - + MAT(&inverse_matrix, 0, 0) * MAT(&inverse_matrix, 1, 0) * fxfy_2 - ) - / r2_fx2_fy2sq; - - rgStepYYRad = - ( - MAT(&inverse_matrix, 0, 1) * MAT(&inverse_matrix, 0, 1) * r2_fy2 - + MAT(&inverse_matrix, 1, 1) * MAT(&inverse_matrix, 1, 1) * r2_fx2 - + MAT(&inverse_matrix, 0, 1) * MAT(&inverse_matrix, 1, 1) * fxfy_2 - ) - / r2_fx2_fy2sq; - - rgStepXYRad = - ( - MAT(&inverse_matrix, 0, 0) * MAT(&inverse_matrix, 0, 1) * r2_fy2_2 - + MAT(&inverse_matrix, 1, 0) * MAT(&inverse_matrix, 1, 1) * r2_fx2_2 - + ( - MAT(&inverse_matrix, 0, 0) * MAT(&inverse_matrix, 1, 1) - + MAT(&inverse_matrix, 0, 1) * MAT(&inverse_matrix, 1, 0) - ) - * fxfy_2 - ) - / r2_fx2_fy2sq; - - rgStepXRad = - ( - MAT(&inverse_matrix, 0, 0) * cx * r2_fy2_2 - + MAT(&inverse_matrix, 1, 0) * cy * r2_fx2_2 - + ( - MAT(&inverse_matrix, 0, 0) * cy - + MAT(&inverse_matrix, 1, 0) * cx - ) - * fxfy_2 - ) - / r2_fx2_fy2sq; - - rgStepYRad = - ( - MAT(&inverse_matrix, 0, 1) * cx * r2_fy2_2 - + MAT(&inverse_matrix, 1, 1) * cy * r2_fx2_2 - + ( - MAT(&inverse_matrix, 0, 1) * cy - + MAT(&inverse_matrix, 1, 1) * cx - ) - * fxfy_2 - ) - / r2_fx2_fy2sq; - - rgConstantRad = - ( - cx * cx * r2_fy2 - + cy * cy * r2_fx2 - + cx * cy * fxfy_2 - ) - / r2_fx2_fy2sq; - - if(tls->t_context.ts_dirty){ - memcpy(CMDBUF_BUFFER(tls->t_context) + CMDBUF_OFFSET(tls->t_context), tls->t_context.ts_record, 80); - CMDBUF_OFFSET(tls->t_context) += 80; - tls->t_context.ts_dirty = 0; - tls->t_context.ts_init_used = 1; - } - else - { - tls->t_context.ts_init_use = 1; - } - - /* Setup the command buffer. */ - - /* rad gradient parameters*/ - data = &rgConstantLin; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A04,*(uint32_t*) data)); - data = &rgStepXLin; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A06,*(uint32_t*) data)); - data = &rgStepYLin; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A08,*(uint32_t*) data)); - data = &rgConstantRad; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A05,*(uint32_t*) data)); - data = &rgStepXRad; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A07,*(uint32_t*) data)); - data = &rgStepYRad; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A09,*(uint32_t*) data)); - data = &rgStepXXRad; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A03,*(uint32_t*) data)); - data = &rgStepYYRad; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A0A,*(uint32_t*) data)); - data = &rgStepXYRad; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A0B,*(uint32_t*) data)); - VG_LITE_RETURN_ERROR(set_interpolation_steps(target, source->width, source->height, matrix)); - - if(!tls->t_context.premultiply_enabled) { - if(source->transparency_mode == VG_LITE_IMAGE_OPAQUE){ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A24, convert_source_format(source->format) | - filter | rad_tile | conversion | 0x01000100)); - } else { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A24, convert_source_format(source->format) | - filter | rad_tile | conversion | 0x00000100)); - } - } else { - /* enable pre-multiplied in imager unit */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A24, convert_source_format(source->format) | - filter | rad_tile | conversion)); - } - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A26, paint_color)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A28, source->address)); - - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2A, tiled_source)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2C, 0)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A2E, source->width)); - - /* Work on path states. */ - matrix = path_matrix; - - if (ts_is_fullscreen == 0){ - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[1], matrix); - point_min = point_max = temp; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[1], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[2], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - transform(&temp, (vg_lite_float_t)path->bounding_box[0], (vg_lite_float_t)path->bounding_box[3], matrix); - if (temp.x < point_min.x) point_min.x = temp.x; - if (temp.y < point_min.y) point_min.y = temp.y; - if (temp.x > point_max.x) point_max.x = temp.x; - if (temp.y > point_max.y) point_max.y = temp.y; - - point_min.x = MAX(point_min.x, 0); - point_min.y = MAX(point_min.y, 0); - point_max.x = MIN(point_max.x, dst_align_width); - point_max.y = MIN(point_max.y, target->height); - - if (tls->t_context.scissor_enabled) { - point_min.x = MAX(point_min.x, tls->t_context.scissor[0]); - point_min.y = MAX(point_min.y, tls->t_context.scissor[1]); - point_max.x = MIN(point_max.x, tls->t_context.scissor[0] + tls->t_context.scissor[2]); - point_max.y = MIN(point_max.y, tls->t_context.scissor[1] + tls->t_context.scissor[3]); - } - } - - /* Convert states into hardware values. */ - blend_mode = convert_blend(blend); - format = convert_path_format(path->format); - quality = convert_path_quality(path->quality); - tiling = (tls->t_context.capabilities.cap.tiled == 2) ? 0x2000000 : 0; - fill = (fill_rule == VG_LITE_FILL_EVEN_ODD) ? 0x10 : 0; - tessellation_size = ( tls->t_context.tsbuffer.tessellation_buffer_size[2] - ? tls->t_context.tsbuffer.tessellation_buffer_size[2] - : tls->t_context.tsbuffer.tessellation_buffer_size[1] - ); - - /* Setup the command buffer. */ - /* Program color register. */ - if(!tls->t_context.premultiply_enabled) { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x12000000 | tls->t_context.capabilities.cap.tiled | 0x00000002 | imageMode | blend_mode | transparency_mode)); - } else { - /* enable pre-multiplied from VG to VGPE */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A00, 0x02000000 | tls->t_context.capabilities.cap.tiled | 0x00000002 | imageMode | blend_mode | transparency_mode)); - } - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A34, 0x01000400 | format | quality | tiling | fill)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3B, 0x3F800000)); /* Path tessellation SCALE. */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3C, 0x00000000)); /* Path tessellation BIAS. */ - /* Program matrix. */ - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A40, (void *) &matrix->m[0][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A41, (void *) &matrix->m[0][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A42, (void *) &matrix->m[0][2])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A43, (void *) &matrix->m[1][0])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A44, (void *) &matrix->m[1][1])); - VG_LITE_RETURN_ERROR(push_state_ptr(&tls->t_context, 0x0A45, (void *) &matrix->m[1][2])); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) - { - if (path->path_changed != 0) { - if (path->uploaded.handle != NULL) { - free_memory.memory_handle = path->uploaded.handle; - vg_lite_kernel(VG_LITE_FREE, &free_memory); - path->uploaded.address = 0; - path->uploaded.memory = NULL; - path->uploaded.handle = NULL; - } - /* Allocate memory for the path data. */ - memory.bytes = 16 + VG_LITE_ALIGN(path->path_length, 8); - return_offset = (8 + VG_LITE_ALIGN(path->path_length, 8)) / 4; - memory.contiguous = 1; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_ALLOCATE, &memory)); - ((uint64_t *) memory.memory)[(path->path_length + 7) / 8] = 0; - ((uint32_t *) memory.memory)[0] = VG_LITE_DATA((path->path_length + 7) / 8); - ((uint32_t *) memory.memory)[1] = 0; - memcpy((uint8_t *) memory.memory + 8, path->path, path->path_length); - ((uint32_t *) memory.memory)[return_offset] = VG_LITE_RETURN(); - ((uint32_t *) memory.memory)[return_offset + 1] = 0; - - path->uploaded.handle = memory.memory_handle; - path->uploaded.memory = memory.memory; - path->uploaded.address = memory.memory_gpu; - path->uploaded.bytes = memory.bytes; - path->path_changed = 0; - } - } - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - - vglitemDUMP_BUFFER("path", path->uploaded.address, (uint8_t *)(path->uploaded.memory), 0, path->uploaded.bytes); - } - - vglitemDUMP("@[memory 0x%08X 0x%08X]", tls->t_context.tsbuffer.tessellation_buffer_gpu[0], tls->t_context.tsbuffer.tessellation_buffer_size[0]); - - /* Setup tessellation loop. */ - if((path->path_type & 0x1) == VG_LITE_DRAW_FILL_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&tls->t_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&tls->t_context, path->uploaded.address, path->uploaded.bytes)); -#if (DUMP_COMMAND) - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[0], 0); - - unsigned char* pt = (unsigned char*) memory.memory; - - for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) - { - if (i % 8 == 0) - fprintf(fp, "Command buffer: "); - - if (i % 4 == 0) - fprintf(fp, "0x"); - - for (int j = 3; j >= 0; --j) - fprintf(fp, "%02x", pt[i + j]); - - if ((i / 4 + 1) % 2 == 0) - fprintf(fp, ",\n"); - else - fprintf(fp, ", "); - } - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[return_offset], 0); - - fclose(fp); - fp = NULL; -#endif - } else { - push_data(&tls->t_context, path->path_length, path->path); - } - } - } - } - /* Setup tessellation loop. */ - if(path->path_type == VG_LITE_DRAW_STROKE_PATH || path->path_type == VG_LITE_DRAW_FILL_STROKE_PATH) { - for (y = point_min.y; y < point_max.y; y += height) { - for (x = point_min.x; x < point_max.x; x += width) { - /* Tessellate path. */ - VG_LITE_RETURN_ERROR(push_stall(&tls->t_context, 15)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A1B, 0x00011000)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A01, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A39, x | (y << 16))); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A3D, tessellation_size / 64)); - - if (VLM_PATH_GET_UPLOAD_BIT(*path) == 1) { - VG_LITE_RETURN_ERROR(push_call(&tls->t_context, path->uploaded.address, path->uploaded.bytes)); -#if (DUMP_COMMAND) - if (strncmp(filename, "Commandbuffer", 13)) { - sprintf(filename, "Commandbuffer_pid%d.txt", getpid()); - } - - fp = fopen(filename, "a"); - - if (fp == NULL) - printf("error!\n"); - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[0], 0); - - unsigned char* pt = (unsigned char*) memory.memory; - - for(int i = 8; i <= return_offset * 4 - 1; i = i + 4) - { - if (i % 8 == 0) - fprintf(fp, "Command buffer: "); - - if (i % 4 == 0) - fprintf(fp, "0x"); - - for (int j = 3; j >= 0; --j) - fprintf(fp, "%02x", pt[i + j]); - - if ((i / 4 + 1) % 2 == 0) - fprintf(fp, ",\n"); - else - fprintf(fp, ", "); - } - - fprintf(fp, "Command buffer: 0x%08x, 0x%08x,\n", - ((uint32_t *) memory.memory)[return_offset], 0); - - fclose(fp); - fp = NULL; -#endif - } else { - format = convert_path_format(VG_LITE_FP32); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A34, 0x01000200 | format | quality | tiling | 0x0)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A02, path->stroke_color)); - push_data(&tls->t_context, path->stroke_path_size, path->stroke_path_data); - } - } - } - } - - /* Finialize command buffer. */ - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A34, 0)); - - vglitemDUMP_BUFFER("image", source->address, source->memory, 0, (source->stride)*(source->height)); -#if DUMP_IMAGE - dump_img(source->memory, src_align_width, source->height, source->format); -#endif - - tls->t_context.ts_init = 1; - return error; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -vg_lite_error_t vg_lite_init_grad(vg_lite_linear_gradient_t *grad) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - - /* Set the member values according to driver defaults. */ - grad->image.width = VLC_GRADBUFFER_WIDTH; - grad->image.height = 1; - grad->image.stride = 0; - grad->image.format = VG_LITE_BGRA8888; - - /* Allocate the image for gradient. */ - error = vg_lite_allocate(&grad->image); - - grad->count = 0; - - return error; -} - -vg_lite_error_t vg_lite_set_linear_grad(vg_lite_linear_gradient_ext_t *grad, - uint32_t count, - vg_lite_color_ramp_t *vg_color_ramp, - vg_lite_linear_gradient_parameter_t linear_gradient, - vg_lite_radial_gradient_spreadmode_t spread_mode, - uint8_t color_ramp_premultiplied) -{ - int i; - static vg_lite_color_ramp_t default_ramp[] = - { - { - 0.0f, - 0.0f, 0.0f, 0.0f, 1.0f - }, - { - 1.0f, - 1.0f, 1.0f, 1.0f, 1.0f - } - }; - - uint32_t trg_count; - vg_lite_float_t prev_stop; - vg_lite_color_ramp_ptr src_ramp; - vg_lite_color_ramp_ptr src_ramp_last; - vg_lite_color_ramp_ptr trg_ramp; - - /* Reset the count. */ - trg_count = 0; - - if ((linear_gradient.X0 == linear_gradient.X1) && (linear_gradient.Y0 == linear_gradient.Y1)) - return VG_LITE_INVALID_ARGUMENT; - - grad->linear_gradient = linear_gradient; - grad->color_ramp_premultiplied = color_ramp_premultiplied; - grad->spread_mode = spread_mode; - - if (!count || count > MAX_COLOR_RAMP_STOPS || vg_color_ramp == NULL) - goto Empty_sequence_handler; - - for(i = 0; i < count;i++) - grad->vg_color_ramp[i] = vg_color_ramp[i]; - grad->vg_color_ramp_length = count; - - /* Determine the last source ramp. */ - src_ramp_last - = grad->vg_color_ramp - + grad->vg_color_ramp_length; - - /* Set the initial previous stop. */ - prev_stop = -1; - - /* Reset the count. */ - trg_count = 0; - - /* Walk through the source ramp. */ - for ( - src_ramp = grad->vg_color_ramp, trg_ramp = grad->int_color_ramp; - (src_ramp < src_ramp_last) && (trg_count < MAX_COLOR_RAMP_STOPS + 2); - src_ramp += 1 - ) - { - /* Must be in increasing order. */ - if (src_ramp->stop < prev_stop) - { - /* Ignore the entire sequence. */ - trg_count = 0; - break; - } - - /* Update the previous stop value. */ - prev_stop = src_ramp->stop; - - /* Must be within [0..1] range. */ - if ((src_ramp->stop < 0.0f) || (src_ramp->stop > 1.0f)) - { - /* Ignore. */ - continue; - } - - /* Clamp color. */ - ClampColor(COLOR_FROM_RAMP(src_ramp),COLOR_FROM_RAMP(trg_ramp),0); - - /* First stop greater then zero? */ - if ((trg_count == 0) && (src_ramp->stop > 0.0f)) - { - /* Force the first stop to 0.0f. */ - trg_ramp->stop = 0.0f; - - /* Replicate the entry. */ - trg_ramp[1] = *trg_ramp; - trg_ramp[1].stop = src_ramp->stop; - - /* Advance. */ - trg_ramp += 2; - trg_count += 2; - } - else - { - /* Set the stop value. */ - trg_ramp->stop = src_ramp->stop; - - /* Advance. */ - trg_ramp += 1; - trg_count += 1; - } - } - - /* Empty sequence? */ - if (trg_count == 0) - { - memcpy(grad->int_color_ramp,default_ramp,sizeof(default_ramp)); - grad->int_color_ramp_length = sizeof(default_ramp) / 5; - } - else - { - /* The last stop must be at 1.0. */ - if (trg_ramp[-1].stop != 1.0f) - { - /* Replicate the last entry. */ - *trg_ramp = trg_ramp[-1]; - - /* Force the last stop to 1.0f. */ - trg_ramp->stop = 1.0f; - - /* Update the final entry count. */ - trg_count += 1; - } - - /* Set new length. */ - grad->int_color_ramp_length = trg_count; - } - return VG_LITE_SUCCESS; - -Empty_sequence_handler: - memcpy(grad->int_color_ramp,default_ramp,sizeof(default_ramp)); - grad->int_color_ramp_length = sizeof(default_ramp) / 5; - - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_update_linear_grad(vg_lite_linear_gradient_ext_t *grad) -{ - uint32_t color_ramp_length; - vg_lite_color_ramp_ptr color_ramp; - uint32_t common, stop; - uint32_t i, width; - uint8_t* bits; - vg_lite_float_t x0,y0,x1,y1,length; - vg_lite_error_t error = VG_LITE_SUCCESS; - - /* Get shortcuts to the color ramp. */ - color_ramp_length = grad->int_color_ramp_length; - color_ramp = grad->int_color_ramp; - - x0 = grad->linear_gradient.X0; - y0 = grad->linear_gradient.Y0; - x1 = grad->linear_gradient.X1; - y1 = grad->linear_gradient.Y1; - length = (vg_lite_float_t)sqrt((x1-x0)*(x1-x0) + (y1-y0)*(y1-y0)); - - if(length <= 0) - return VG_LITE_INVALID_ARGUMENT; - /* Find the common denominator of the color ramp stops. */ - if (length < 1) - { - common = 1; - } - else - { - common = (uint32_t)length; - } - - for (i = 0; i < color_ramp_length; ++i) - { - if (color_ramp[i].stop != 0.0f) - { - vg_lite_float_t mul = common * color_ramp[i].stop; - vg_lite_float_t frac = mul - (vg_lite_float_t) floor(mul); - if (frac > 0.00013f) /* Suppose error for zero is 0.00013 */ - { - common = MAX(common, (uint32_t) (1.0f / frac + 0.5f)); - } - } - } - - /* Compute the width of the required color array. */ - width = common + 1; - - /* Allocate the color ramp surface. */ - memset(&grad->image, 0, sizeof(grad->image)); - grad->image.width = width; - grad->image.height = 1; - grad->image.stride = 0; - grad->image.image_mode = VG_LITE_NONE_IMAGE_MODE; - grad->image.format = VG_LITE_ABGR8888; - - /* Allocate the image for gradient. */ - VG_LITE_RETURN_ERROR(vg_lite_allocate(&grad->image)); - - grad->image.width = width; - - /* Set pointer to color array. */ - bits = (uint8_t *)grad->image.memory; - - /* Start filling the color array. */ - stop = 0; - for (i = 0; i < width; ++i) - { - vg_lite_float_t gradient; - vg_lite_float_t color[4]; - vg_lite_float_t color1[4]; - vg_lite_float_t color2[4]; - vg_lite_float_t weight; - - /* Compute gradient for current color array entry. */ - gradient = (vg_lite_float_t) i / (vg_lite_float_t) (width - 1); - - /* Find the entry in the color ramp that matches or exceeds this - ** gradient. */ - while ((stop < color_ramp_length - 1) && (gradient > color_ramp[stop].stop)) - { - ++stop; - } - - if (gradient == color_ramp[stop].stop) - { - /* Perfect match weight 1.0. */ - weight = 1.0f; - - /* Use color ramp color. */ - color1[3] = color_ramp[stop].alpha; - color1[2] = color_ramp[stop].blue; - color1[1] = color_ramp[stop].green; - color1[0] = color_ramp[stop].red; - - color2[3] = - color2[2] = - color2[1] = - color2[0] = 0.0f; - } - else - { - /* Compute weight. */ - weight = (color_ramp[stop].stop - gradient) - / (color_ramp[stop].stop - color_ramp[stop - 1].stop); - - /* Grab color ramp color of previous stop. */ - color1[3] = color_ramp[stop - 1].alpha; - color1[2] = color_ramp[stop - 1].blue; - color1[1] = color_ramp[stop - 1].green; - color1[0] = color_ramp[stop - 1].red; - - /* Grab color ramp color of current stop. */ - color2[3] = color_ramp[stop].alpha; - color2[2] = color_ramp[stop].blue; - color2[1] = color_ramp[stop].green; - color2[0] = color_ramp[stop].red; - } - - if (grad->color_ramp_premultiplied) - { - /* Pre-multiply the first color. */ - color1[2] *= color1[3]; - color1[1] *= color1[3]; - color1[0] *= color1[3]; - - /* Pre-multiply the second color. */ - color2[2] *= color2[3]; - color2[1] *= color2[3]; - color2[0] *= color2[3]; - } - - /* Filter the colors per channel. */ - color[3] = LERP(color1[3], color2[3], weight); - color[2] = LERP(color1[2], color2[2], weight); - color[1] = LERP(color1[1], color2[1], weight); - color[0] = LERP(color1[0], color2[0], weight); - - /* Pack the final color. */ - *bits++ = PackColorComponent(color[3]); - *bits++ = PackColorComponent(color[2]); - *bits++ = PackColorComponent(color[1]); - *bits++ = PackColorComponent(color[0]); - } - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_set_rad_grad(vg_lite_radial_gradient_t *grad, - uint32_t count, - vg_lite_color_ramp_t *vgColorRamp, - vg_lite_radial_gradient_parameter_t radialGradient, - vg_lite_radial_gradient_spreadmode_t SpreadMode, - uint8_t colorRampPremultiplied) -{ - int i; - static vg_lite_color_ramp_t defaultRamp[] = - { - { - 0.0f, - 0.0f, 0.0f, 0.0f, 1.0f - }, - { - 1.0f, - 1.0f, 1.0f, 1.0f, 1.0f - } - }; - - uint32_t trgCount; - vg_lite_float_t prevStop; - vg_lite_color_ramp_ptr srcRamp; - vg_lite_color_ramp_ptr srcRampLast; - vg_lite_color_ramp_ptr trgRamp; - - /* Reset the count. */ - trgCount = 0; - - if(radialGradient.r <= 0) - return VG_LITE_INVALID_ARGUMENT; - - grad->radialGradient = radialGradient; - grad->colorRampPremultiplied = colorRampPremultiplied; - grad->SpreadMode = SpreadMode; - - if (!count || count > MAX_COLOR_RAMP_STOPS || vgColorRamp == NULL) - goto Empty_sequence_handler; - - for(i = 0; i < count;i++) - grad->vgColorRamp[i] = vgColorRamp[i]; - grad->vgColorRampLength = count; - - /* Determine the last source ramp. */ - srcRampLast - = grad->vgColorRamp - + grad->vgColorRampLength; - - /* Set the initial previous stop. */ - prevStop = -1; - - /* Reset the count. */ - trgCount = 0; - - /* Walk through the source ramp. */ - for ( - srcRamp = grad->vgColorRamp, trgRamp = grad->intColorRamp; - (srcRamp < srcRampLast) && (trgCount < MAX_COLOR_RAMP_STOPS + 2); - srcRamp += 1 - ) - { - /* Must be in increasing order. */ - if (srcRamp->stop < prevStop) - { - /* Ignore the entire sequence. */ - trgCount = 0; - break; - } - - /* Update the previous stop value. */ - prevStop = srcRamp->stop; - - /* Must be within [0..1] range. */ - if ((srcRamp->stop < 0.0f) || (srcRamp->stop > 1.0f)) - { - /* Ignore. */ - continue; - } - - /* Clamp color. */ - ClampColor(COLOR_FROM_RAMP(srcRamp),COLOR_FROM_RAMP(trgRamp),0); - - /* First stop greater then zero? */ - if ((trgCount == 0) && (srcRamp->stop > 0.0f)) - { - /* Force the first stop to 0.0f. */ - trgRamp->stop = 0.0f; - - /* Replicate the entry. */ - trgRamp[1] = *trgRamp; - trgRamp[1].stop = srcRamp->stop; - - /* Advance. */ - trgRamp += 2; - trgCount += 2; - } - else - { - /* Set the stop value. */ - trgRamp->stop = srcRamp->stop; - - /* Advance. */ - trgRamp += 1; - trgCount += 1; - } - } - - /* Empty sequence? */ - if (trgCount == 0) - { - memcpy(grad->intColorRamp,defaultRamp,sizeof(defaultRamp)); - grad->intColorRampLength = sizeof(defaultRamp) / 5; - } - else - { - /* The last stop must be at 1.0. */ - if (trgRamp[-1].stop != 1.0f) - { - /* Replicate the last entry. */ - *trgRamp = trgRamp[-1]; - - /* Force the last stop to 1.0f. */ - trgRamp->stop = 1.0f; - - /* Update the final entry count. */ - trgCount += 1; - } - - /* Set new length. */ - grad->intColorRampLength = trgCount; - } - return VG_LITE_SUCCESS; - -Empty_sequence_handler: - memcpy(grad->intColorRamp,defaultRamp,sizeof(defaultRamp)); - grad->intColorRampLength = sizeof(defaultRamp) / 5; - - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_update_rad_grad(vg_lite_radial_gradient_t *grad) -{ - uint32_t colorRampLength; - vg_lite_color_ramp_ptr colorRamp; - uint32_t common, stop; - uint32_t i, width; - uint8_t* bits; - vg_lite_float_t r; - vg_lite_error_t error = VG_LITE_SUCCESS; - - /* Get shortcuts to the color ramp. */ - colorRampLength = grad->intColorRampLength; - colorRamp = grad->intColorRamp; - - r = grad->radialGradient.r; - - if(r <= 0) - return VG_LITE_INVALID_ARGUMENT; - /* Find the common denominator of the color ramp stops. */ - if (r < 1) - { - common = 1; - } - else - { - common = (uint32_t)r; - } - - for (i = 0; i < colorRampLength; ++i) - { - if (colorRamp[i].stop != 0.0f) - { - vg_lite_float_t mul = common * colorRamp[i].stop; - vg_lite_float_t frac = mul - (vg_lite_float_t) floor(mul); - if (frac > 0.00013f) /* Suppose error for zero is 0.00013 */ - { - common = MAX(common, (uint32_t) (1.0f / frac + 0.5f)); - } - } - } - - /* Compute the width of the required color array. */ - width = common + 1; - - /* Allocate the color ramp surface. */ - memset(&grad->image, 0, sizeof(grad->image)); - grad->image.width = width; - grad->image.height = 1; - grad->image.stride = 0; - grad->image.image_mode = VG_LITE_NONE_IMAGE_MODE; - grad->image.format = VG_LITE_ABGR8888; - - /* Allocate the image for gradient. */ - VG_LITE_RETURN_ERROR(vg_lite_allocate(&grad->image)); - - grad->image.width = width; - - /* Set pointer to color array. */ - bits = (uint8_t *)grad->image.memory; - - /* Start filling the color array. */ - stop = 0; - for (i = 0; i < width; ++i) - { - vg_lite_float_t gradient; - vg_lite_float_t color[4]; - vg_lite_float_t color1[4]; - vg_lite_float_t color2[4]; - vg_lite_float_t weight; - - /* Compute gradient for current color array entry. */ - gradient = (vg_lite_float_t) i / (vg_lite_float_t) (width - 1); - - /* Find the entry in the color ramp that matches or exceeds this - ** gradient. */ - while ((stop < colorRampLength - 1) && (gradient > colorRamp[stop].stop)) - { - ++stop; - } - - if (gradient == colorRamp[stop].stop) - { - /* Perfect match weight 1.0. */ - weight = 1.0f; - - /* Use color ramp color. */ - color1[3] = colorRamp[stop].alpha; - color1[2] = colorRamp[stop].blue; - color1[1] = colorRamp[stop].green; - color1[0] = colorRamp[stop].red; - - color2[3] = - color2[2] = - color2[1] = - color2[0] = 0.0f; - } - else - { - /* Compute weight. */ - weight = (colorRamp[stop].stop - gradient) - / (colorRamp[stop].stop - colorRamp[stop - 1].stop); - - /* Grab color ramp color of previous stop. */ - color1[3] = colorRamp[stop - 1].alpha; - color1[2] = colorRamp[stop - 1].blue; - color1[1] = colorRamp[stop - 1].green; - color1[0] = colorRamp[stop - 1].red; - - /* Grab color ramp color of current stop. */ - color2[3] = colorRamp[stop].alpha; - color2[2] = colorRamp[stop].blue; - color2[1] = colorRamp[stop].green; - color2[0] = colorRamp[stop].red; - } - - if (grad->colorRampPremultiplied) - { - /* Pre-multiply the first color. */ - color1[2] *= color1[3]; - color1[1] *= color1[3]; - color1[0] *= color1[3]; - - /* Pre-multiply the second color. */ - color2[2] *= color2[3]; - color2[1] *= color2[3]; - color2[0] *= color2[3]; - } - - /* Filter the colors per channel. */ - color[3] = LERP(color1[3], color2[3], weight); - color[2] = LERP(color1[2], color2[2], weight); - color[1] = LERP(color1[1], color2[1], weight); - color[0] = LERP(color1[0], color2[0], weight); - - /* Pack the final color. */ - *bits++ = PackColorComponent(color[3]); - *bits++ = PackColorComponent(color[2]); - *bits++ = PackColorComponent(color[1]); - *bits++ = PackColorComponent(color[0]); - } - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_set_grad(vg_lite_linear_gradient_t *grad, - uint32_t count, - uint32_t * colors, - uint32_t * stops) -{ - uint32_t i; - - grad->count = 0; /* Opaque B&W gradient */ - if (!count || count > VLC_MAX_GRAD || colors == NULL || stops == NULL) - return VG_LITE_SUCCESS; - /* Check stops validity */ - for (i = 0; i < count; i++) - if (stops[i] <= 255) { - if (!grad->count || stops[i] > grad->stops[grad->count - 1]) { - grad->stops[grad->count] = stops[i]; - grad->colors[grad->count] = colors[i]; - grad->count++; - } else if (stops[i] == grad->stops[grad->count - 1]) { - /* Equal stops : use the color corresponding to the last stop - in the sequence */ - grad->colors[grad->count - 1] = colors[i]; - } - } - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_update_grad(vg_lite_linear_gradient_t *grad) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - int32_t r0, g0, b0, a0; - int32_t r1, g1, b1, a1; - int32_t lr, lg, lb, la; - uint32_t i; - int32_t j; - int32_t ds, dr, dg, db, da; - uint32_t *buffer = (uint32_t *)grad->image.memory; - - if (grad->count == 0) { - /* If no valid stops have been specified (e.g., due to an empty input - * array, out-of-range, or out-of-order stops), a stop at 0 with color - * 0xFF000000 (opaque black) and a stop at 255 with color 0xFFFFFFFF - * (opaque white) are implicitly defined. */ - grad->stops[0] = 0; - grad->colors[0] = 0xFF000000; /* Opaque black */ - grad->stops[1] = 255; - grad->colors[1] = 0xFFFFFFFF; /* Opaque white */ - grad->count = 2; - } else if (grad->count && grad->stops[0] != 0) { - /* If at least one valid stop has been specified, but none has been - * defined with an offset of 0, an implicit stop is added with an - * offset of 0 and the same color as the first user-defined stop. */ - for (i = 0; i < grad->stops[0]; i++) - buffer[i] = grad->colors[0]; - } - a0 = A(grad->colors[0]); - r0 = R(grad->colors[0]); - g0 = G(grad->colors[0]); - b0 = B(grad->colors[0]); - - /* Calculate the colors for each pixel of the image. */ - for (i = 0; i < grad->count - 1; i++) { - buffer[grad->stops[i]] = grad->colors[i]; - ds = grad->stops[i + 1] - grad->stops[i]; - a1 = A(grad->colors[i + 1]); - r1 = R(grad->colors[i + 1]); - g1 = G(grad->colors[i + 1]); - b1 = B(grad->colors[i + 1]); - - da = a1 - a0; - dr = r1 - r0; - dg = g1 - g0; - db = b1 - b0; - - for (j = 1; j < ds; j++) { - la = a0 + da * j / ds; - lr = r0 + dr * j / ds; - lg = g0 + dg * j / ds; - lb = b0 + db * j / ds; - - buffer[grad->stops[i] + j] = ARGB(la, lr, lg, lb); - } - - a0 = a1; - r0 = r1; - g0 = g1; - b0 = b1; - } - /* If at least one valid stop has been specified, but none has been defined - * with an offset of 255, an implicit stop is added with an offset of 255 - * and the same color as the last user-defined stop. */ - for (i = grad->stops[grad->count - 1]; i < 255; i++) - buffer[i] = grad->colors[grad->count - 1]; - /* Last pixel */ - buffer[i] = grad->colors[grad->count - 1]; - return error; -} - -vg_lite_error_t vg_lite_clear_grad(vg_lite_linear_gradient_t *grad) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - - grad->count = 0; - /* Release the image resource. */ - if (grad->image.handle != NULL) - { - error = vg_lite_free(&grad->image); - } - - return error; -} - -vg_lite_error_t vg_lite_clear_rad_grad(vg_lite_radial_gradient_t *grad) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - - grad->count = 0; - /* Release the image resource. */ - if (grad->image.handle != NULL) - { - error = vg_lite_free(&grad->image); - } - - return error; -} - -vg_lite_error_t vg_lite_clear_linear_grad(vg_lite_linear_gradient_ext_t *grad) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - - grad->count = 0; - /* Release the image resource. */ - if (grad->image.handle != NULL) - { - error = vg_lite_free(&grad->image); - } - - return error; -} - -vg_lite_matrix_t * vg_lite_get_linear_grad_matrix(vg_lite_linear_gradient_ext_t *grad) -{ - return &grad->matrix; -} - -vg_lite_matrix_t * vg_lite_get_grad_matrix(vg_lite_linear_gradient_t *grad) -{ - return &grad->matrix; -} - -vg_lite_matrix_t * vg_lite_get_rad_grad_matrix(vg_lite_radial_gradient_t *grad) -{ - return &grad->matrix; -} - -vg_lite_error_t vg_lite_draw_gradient(vg_lite_buffer_t * target, - vg_lite_path_t * path, - vg_lite_fill_t fill_rule, - vg_lite_matrix_t * matrix, - vg_lite_linear_gradient_t * grad, - vg_lite_blend_t blend) -{ - return vg_lite_draw_pattern(target, path, fill_rule, matrix, - &grad->image, &grad->matrix, blend, VG_LITE_PATTERN_PAD, 0, VG_LITE_FILTER_LINEAR); -} - -#if defined(VG_DRIVER_SINGLE_THREAD) -vg_lite_error_t vg_lite_set_command_buffer_size(uint32_t size) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - - if(!s_context.init){ - if(!size) - return VG_LITE_INVALID_ARGUMENT; - command_buffer_size = size; - } - else{ - VG_LITE_RETURN_ERROR(_free_command_buffer()); - VG_LITE_RETURN_ERROR(_allocate_command_buffer(size)); - VG_LITE_RETURN_ERROR(program_tessellation(&s_context)); - } - - return error; -} - -vg_lite_error_t vg_lite_set_scissor(int32_t x, int32_t y, int32_t width, int32_t height) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - - /* Save scissor Box States. */ - s_context.scissor[0] = x; - s_context.scissor[1] = y; - s_context.scissor[2] = width; - s_context.scissor[3] = height; - - /* Scissor dirty. */ - s_context.scissor_dirty = 1; - - return error; -} - -vg_lite_error_t vg_lite_enable_scissor(void) -{ - /* Enable scissor Mode. */ - s_context.scissor_enabled = 1; - - /* Scissor dirty. */ - s_context.scissor_dirty = 1; - - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_disable_scissor(void) -{ - /* disable scissor Mode. */ - s_context.scissor_enabled = 0; - - /* Scissor dirty. */ - s_context.scissor_dirty = 1; - - return VG_LITE_SUCCESS; -} - -// added by MicroEJ -uint32_t vg_lite_get_scissor(int32_t** scissor) -{ - *scissor = s_context.scissor; - return s_context.scissor_enabled; -} - -#else -vg_lite_error_t vg_lite_set_command_buffer_size(uint32_t size) -{ - vg_lite_tls_t* tls; - vg_lite_error_t error = VG_LITE_SUCCESS; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - if(CMDBUF_IN_QUEUE(&tls->t_context.context, 0) || - CMDBUF_IN_QUEUE(&tls->t_context.context, 1)) - return VG_LITE_INVALID_ARGUMENT; - - VG_LITE_RETURN_ERROR(_free_command_buffer()); - VG_LITE_RETURN_ERROR(_allocate_command_buffer(size)); - VG_LITE_RETURN_ERROR(program_tessellation(&tls->t_context)); - - return error; -} - -vg_lite_error_t vg_lite_set_scissor(int32_t x, int32_t y, int32_t width, int32_t height) -{ - vg_lite_tls_t* tls; - vg_lite_error_t error = VG_LITE_SUCCESS; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - /* Save scissor Box States. */ - tls->t_context.scissor[0] = x; - tls->t_context.scissor[1] = y; - tls->t_context.scissor[2] = width; - tls->t_context.scissor[3] = height; - - return error; -} - -vg_lite_error_t vg_lite_enable_scissor(void) -{ - vg_lite_tls_t* tls; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - /* Enable scissor Mode. */ - tls->t_context.scissor_enabled = 1; - - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_disable_scissor(void) -{ - vg_lite_tls_t* tls; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - /* disable scissor Mode. */ - tls->t_context.scissor_enabled = 0; - - return VG_LITE_SUCCESS; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -vg_lite_error_t vg_lite_mem_avail(uint32_t *size) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_kernel_mem_t mem; - VG_LITE_RETURN_ERROR(vg_lite_kernel(VG_LITE_QUERY_MEM,&mem)); - *size = mem.bytes; - - return error; -} - -#if defined(VG_DRIVER_SINGLE_THREAD) -vg_lite_error_t vg_lite_enable_premultiply(void) -{ - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_PE_PREMULTIPLY)) - return VG_LITE_NOT_SUPPORT; - - /* Enable premultiply Mode. */ - s_context.premultiply_enabled = 1; - - s_context.premultiply_dirty = 1; - - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_disable_premultiply(void) -{ - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_PE_PREMULTIPLY)) - return VG_LITE_NOT_SUPPORT; - - /* disable premultiply Mode. */ - s_context.premultiply_enabled = 0; - - s_context.premultiply_dirty = 1; - - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_set_dither(int enable) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_context_t *context = GET_CONTEXT(); - uint32_t table_low = 0x7B48F3C0; - uint32_t table_high = 0x596AD1E2; - int dither_enable = enable; - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_DITHER)) { - return VG_LITE_NOT_SUPPORT; - } - if(dither_enable) { - VG_LITE_RETURN_ERROR(push_state(context, 0x0A5A, table_low)); - VG_LITE_RETURN_ERROR(push_state(context, 0x0A5B, table_high)); - } - else { - VG_LITE_RETURN_ERROR(push_state(context, 0x0A5A, 0xFFFFFFFF)); - VG_LITE_RETURN_ERROR(push_state(context, 0x0A5B, 0xFFFFFFFF)); - } - - return error; -} - -vg_lite_error_t vg_lite_set_color_key(vg_lite_color_key4_t colorkey) -{ - uint8_t i; - uint32_t value_low = 0; - uint32_t value_high = 0; - uint8_t r, g, b, a, e; - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_context_t *context = GET_CONTEXT(); - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_COLOR_KEY)) - return VG_LITE_NOT_SUPPORT; - - /* Set color key states. */ - for (i = 0; i < 4; i++) - { - /* Set gcregVGPEColorKeyLow. Layout "E/R/G/B". */ - r = colorkey[i].low_r; - g = colorkey[i].low_g; - b = colorkey[i].low_b; - e = colorkey[i].enable; - value_low = (e << 24) | (r << 16) | (g << 8) | b; - VG_LITE_RETURN_ERROR(push_state(context, 0x0A90 + i , value_low)); - - /* Set gcregVGPEColorKeyHigh. Layout "A/R/G/B". */ - r = colorkey[i].hign_r; - g = colorkey[i].hign_g; - b = colorkey[i].hign_b; - a = colorkey[i].alpha; - value_high = (a << 24) | (r << 16) | (g << 8) | b; - VG_LITE_RETURN_ERROR(push_state(context, 0x0A94 + i , value_high)); - } - - return error; -} - -#else -vg_lite_error_t vg_lite_enable_premultiply(void) -{ - vg_lite_tls_t* tls; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_PE_PREMULTIPLY)) - return VG_LITE_NOT_SUPPORT; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - /* Enable premultiply Mode. */ - tls->t_context.premultiply_enabled = 1; - - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_disable_premultiply(void) -{ - vg_lite_tls_t* tls; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_PE_PREMULTIPLY)) - return VG_LITE_NOT_SUPPORT; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - /* disable premultiply Mode. */ - tls->t_context.premultiply_enabled = 0; - - return VG_LITE_SUCCESS; -} - -vg_lite_error_t vg_lite_set_dither(int enable) -{ - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_tls_t* tls; - uint32_t table_low = 0x7B48F3C0; - uint32_t table_high = 0x596AD1E2; - int dither_enable = enable; - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_DITHER)) { - return VG_LITE_NOT_SUPPORT; - } - - if(dither_enable) { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A5A, table_low)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A5B, table_high)); - } - else { - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A5A, 0xFFFFFFFF)); - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A5B, 0xFFFFFFFF)); - } - - return error; -} - -vg_lite_error_t vg_lite_set_color_key(vg_lite_color_key4_t colorkey) -{ - uint8_t i; - uint32_t value_low = 0; - uint32_t value_high = 0; - uint8_t r, g, b, a, e; - vg_lite_error_t error = VG_LITE_SUCCESS; - vg_lite_tls_t* tls; - - tls = (vg_lite_tls_t *) vg_lite_os_get_tls(); - if(tls == NULL) - return VG_LITE_NO_CONTEXT; - - if(!vg_lite_query_feature(gcFEATURE_BIT_VG_COLOR_KEY)) - return VG_LITE_NOT_SUPPORT; - - /* Set color key states. */ - for (i = 0; i < 4; i++) - { - /* Set gcregVGPEColorKeyLow. Layout "E/R/G/B". */ - r = colorkey[i].low_r; - g = colorkey[i].low_g; - b = colorkey[i].low_b; - e = colorkey[i].enable; - value_low = (e << 24) | (r << 16) | (g << 8) | b; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A90 + i , value_low)); - - /* Set gcregVGPEColorKeyHigh. Layout "A/R/G/B". */ - r = colorkey[i].hign_r; - g = colorkey[i].hign_g; - b = colorkey[i].hign_b; - a = colorkey[i].alpha; - value_high = (a << 24) | (r << 16) | (g << 8) | b; - VG_LITE_RETURN_ERROR(push_state(&tls->t_context, 0x0A94 + i , value_high)); - } - - return error; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLiteKernel/rtos/vg_lite_hal.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLiteKernel/rtos/vg_lite_hal.c deleted file mode 100644 index 8bdbec8..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/VGLiteKernel/rtos/vg_lite_hal.c +++ /dev/null @@ -1,689 +0,0 @@ -/**************************************************************************** -* -* The MIT License (MIT) -* -* Copyright (c) 2014 - 2020 Vivante Corporation -* -* Permission is hereby granted, free of charge, to any person obtaining a -* copy of this software and associated documentation files (the "Software"), -* to deal in the Software without restriction, including without limitation -* the rights to use, copy, modify, merge, publish, distribute, sublicense, -* and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -* DEALINGS IN THE SOFTWARE. -* -* Copyright 2020-2022 MicroEJ Corp. This file has been modified by MicroEJ Corp. -* 1. Add callback mecanism to notify MicroEJ when a VGLite operation -* is complete -* -*****************************************************************************/ - -#include "vg_lite_platform.h" -#include "vg_lite_kernel.h" -#include "vg_lite_hal.h" -#include "vg_lite_hw.h" -#if !defined(VG_DRIVER_SINGLE_THREAD) -#include "vg_lite_os.h" -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - -#if !_BAREMETAL -#include "FreeRTOS.h" -#include "semphr.h" -#include "task.h" -#if !defined(VG_DRIVER_SINGLE_THREAD) -#include "queue.h" -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ -#else -#include "xil_cache.h" -#if defined(VG_DRIVER_SINGLE_THREAD) -#include "sleep.h" -#endif /* VG_DRIVER_SINGLE_THREAD */ -#endif - -#if defined(VG_DRIVER_SINGLE_THREAD) -#if !_BAREMETAL -static void sleep(uint32_t msec) -{ - vTaskDelay((configTICK_RATE_HZ * msec + 999)/ 1000); -} -#endif -#endif /* VG_DRIVER_SINGLE_THREAD */ - -#if _BAREMETAL -/* The followings should be configured by FPGA. */ -static uint32_t registerMemBase = 0x43c80000; -#else -static uint32_t registerMemBase = 0x40240000; -#endif - -#if defined(VG_DRIVER_SINGLE_THREAD) -/* If bit31 is activated this indicates a bus error */ -#define IS_AXI_BUS_ERR(x) ((x)&(1U << 31)) -#endif /* VG_DRIVER_SINGLE_THREAD */ - -#define HEAP_NODE_USED 0xABBAF00D - -volatile void* contiguousMem = NULL; -uint32_t gpuMemBase = 0; - -/* Default heap size is 16MB. */ -static int heap_size = MAX_CONTIGUOUS_SIZE; - -#if defined(VG_DRIVER_SINGLE_THREAD) -void __attribute__((weak)) vg_lite_bus_error_handler(); - -// added by MicroEJ -#if _VG_LITE_IRQ_CALLBACK == 1 -static vg_lite_irq_callback __irq_callback = NULL; -#endif /* _VG_LITE_IRQ_CALLBACK */ - -#endif /* VG_DRIVER_SINGLE_THREAD */ - -void vg_lite_init_mem(uint32_t register_mem_base, - uint32_t gpu_mem_base, - volatile void * contiguous_mem_base, - uint32_t contiguous_mem_size) -{ - registerMemBase = register_mem_base; - gpuMemBase = gpu_mem_base; - contiguousMem = contiguous_mem_base; - heap_size = contiguous_mem_size; -} - -/* Implementation of list. ****************************************/ -typedef struct list_head { - struct list_head *next; - struct list_head *prev; -}list_head_t; - -#define INIT_LIST_HEAD(entry) \ - (entry)->next = (entry);\ - (entry)->prev = (entry); - -/* Add the list item in front of "head". */ -static inline void add_list(list_head_t *to_add, list_head_t *head) -{ - /* Link the new item. */ - to_add->next = head; - to_add->prev = head->prev; - - /* Modify the neighbor. */ - head->prev = to_add; - if (to_add->prev != NULL) { - to_add->prev->next = to_add; - } -} - -/* Remove an entry out of the list. */ -static inline void delete_list(list_head_t *entry) -{ - if (entry->prev != NULL) { - entry->prev->next = entry->next; - } - if (entry->next != NULL) { - entry->next->prev = entry->prev; - } -} - -/* End of list implementation. ***********/ -static inline void _memset(void *mem, unsigned char value, int size) -{ - int i; - for (i = 0; i < size; i++) { - ((unsigned char*)mem)[i] = value; - } -} - -typedef struct heap_node { - list_head_t list; /* TODO: Linux specific, needs to rewrite. */ - uint32_t offset; - unsigned long size; - uint32_t status; -}heap_node_t; - -struct memory_heap { - uint32_t free; - list_head_t list; -}; - -struct mapped_memory { - void * logical; - uint32_t physical; - int page_count; - struct page ** pages; -}; - -struct vg_lite_device { - /* void * gpu; */ - uint32_t gpu; /* Always use physical for register access in RTOS. */ - /* struct page * pages; */ - volatile void * contiguous; - unsigned int order; - unsigned int heap_size; - void * virtual; - uint32_t physical; - uint32_t size; - struct memory_heap heap; - int irq_enabled; - -#if defined(VG_DRIVER_SINGLE_THREAD) - volatile uint32_t int_flags; -#if _BAREMETAL - /* wait_queue_head_t int_queue; */ - xSemaphoreHandle int_queue; -#else - /* wait_queue_head_t int_queue; */ - SemaphoreHandle_t int_queue; -#endif -#endif /* VG_DRIVER_SINGLE_THREAD */ - - void * device; - int registered; - int major; - struct class * class; - int created; -}; - -struct client_data { - struct vg_lite_device * device; - struct vm_area_struct * vm; - void * contiguous_mapped; -}; - -static struct vg_lite_device Device, * device; - -#if defined(VG_DRIVER_SINGLE_THREAD) -void * vg_lite_hal_alloc(unsigned long size) -{ -#if _BAREMETAL - /* Alloc is not supported in BAREMETAL / DDRLESS. */ - return NULL; -#else - /* TODO: Allocate some memory. No more kernel mode in RTOS. */ - return pvPortMalloc(size); -#endif -} - -void vg_lite_hal_free(void * memory) -{ -#if !_BAREMETAL - /* TODO: Free some memory. No more kernel mode in RTOS. */ - vPortFree(memory); -#endif -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -void vg_lite_hal_delay(uint32_t ms) -{ -#if defined(VG_DRIVER_SINGLE_THREAD) - sleep(ms); -#else - vg_lite_os_sleep(ms); -#endif /* VG_DRIVER_SINGLE_THREAD */ -} - -void vg_lite_hal_barrier(void) -{ - /*Memory barrier. */ -#if _BAREMETAL - Xil_DCacheFlush(); -#else - __asm("DSB"); -#endif -} - -static int vg_lite_init(void); -#if defined(VG_DRIVER_SINGLE_THREAD) -void vg_lite_hal_initialize(void) -{ - /* TODO: Turn on the power. */ - vg_lite_init(); - /* TODO: Turn on the clock. */ -} -#else -vg_lite_error_t vg_lite_hal_initialize(void) -{ - int32_t error = VG_LITE_SUCCESS; - /* TODO: Turn on the power. */ - vg_lite_init(); - /* TODO: Turn on the clock. */ - error = vg_lite_os_initialize(); - - return (vg_lite_error_t)error; -} -#endif /* VG_DRIVER_SINGLE_THREAD */ - -void vg_lite_hal_deinitialize(void) -{ - /* TODO: Remove clock. */ -#if defined(VG_DRIVER_SINGLE_THREAD) - vSemaphoreDelete(device->int_queue); -#else - vg_lite_os_deinitialize(); -#endif /* VG_DRIVER_SINGLE_THREAD */ - /* TODO: Remove power. */ -} - -static int split_node(heap_node_t * node, unsigned long size) -{ - /* TODO: the original is linux specific list based, needs rewrite. - */ - heap_node_t * split; - - /* - * If the newly allocated object fits exactly the size of the free - * node, there is no need to split. - */ - if (node->size - size == 0) - return 0; - - /* Allocate a new node. */ -#if defined(VG_DRIVER_SINGLE_THREAD) - split = vg_lite_hal_alloc(sizeof(heap_node_t)); -#else - split = (heap_node_t *)vg_lite_os_malloc(sizeof(heap_node_t)); -#endif /* VG_DRIVER_SINGLE_THREAD */ - - if (split == NULL) - return -1; - - /* Fill in the data of this node of the remaning size. */ - split->offset = node->offset + size; - split->size = node->size - size; - split->status = 0; - - /* Add the new node behind the current node. */ - add_list(&split->list, &node->list); - - /* Adjust the size of the current node. */ - node->size = size; - return 0; -} - -vg_lite_error_t vg_lite_hal_allocate_contiguous(unsigned long size, void ** logical, uint32_t * physical,void ** node) -{ - unsigned long aligned_size; - heap_node_t * pos; - - /* Align the size to 64 bytes. */ - aligned_size = (size + 63) & ~63; - - /* Check if there is enough free memory available. */ - if (aligned_size > device->heap.free) { - return VG_LITE_OUT_OF_MEMORY; - } - - /* Walk the heap backwards. */ - for (pos = (heap_node_t*)device->heap.list.prev; - &pos->list != &device->heap.list; - pos = (heap_node_t*) pos->list.prev) { - /* Check if the current node is free and is big enough. */ - if (pos->status == 0 && pos->size >= aligned_size) { - /* See if we the current node is big enough to split. */ - if (0 != split_node(pos, aligned_size)) - { - return VG_LITE_OUT_OF_RESOURCES; - } - /* Mark the current node as used. */ - pos->status = HEAP_NODE_USED; - - /* Return the logical/physical address. */ - /* *logical = (uint8_t *) private_data->contiguous_mapped + pos->offset; */ - *logical = (uint8_t *)device->virtual + pos->offset; - *physical = gpuMemBase + (uint32_t)(*logical);/* device->physical + pos->offset; */ - device->heap.free -= aligned_size; - - *node = pos; - return VG_LITE_SUCCESS; - } - } - - /* Out of memory. */ - return VG_LITE_OUT_OF_MEMORY; -} - -void vg_lite_hal_free_contiguous(void * memory_handle) -{ - /* TODO: no list available in RTOS. */ - heap_node_t * pos, * node; - - /* Get pointer to node. */ - node = memory_handle; - - if (node->status != HEAP_NODE_USED) { - return; - } - - /* Mark node as free. */ - node->status = 0; - - /* Add node size to free count. */ - device->heap.free += node->size; - - /* Check if next node is free. */ - pos = node; - for (pos = (heap_node_t *)pos->list.next; - &pos->list != &device->heap.list; - pos = (heap_node_t *)pos->list.next) { - if (pos->status == 0) { - /* Merge the nodes. */ - node->size += pos->size; - if(node->offset > pos->offset) - node->offset = pos->offset; - /* Delete the next node from the list. */ - delete_list(&pos->list); -#if defined(VG_DRIVER_SINGLE_THREAD) - vg_lite_hal_free(pos); -#else - vg_lite_os_free(pos); -#endif /* VG_DRIVER_SINGLE_THREAD */ - } - break; - } - - /* Check if the previous node is free. */ - pos = node; - for (pos = (heap_node_t *)pos->list.prev; - &pos->list != &device->heap.list; - pos = (heap_node_t *)pos->list.prev) { - if (pos->status == 0) { - /* Merge the nodes. */ - pos->size += node->size; - if(pos->offset > node->offset) - pos->offset = node->offset; - /* Delete the current node from the list. */ - delete_list(&node->list); -#if defined(VG_DRIVER_SINGLE_THREAD) - vg_lite_hal_free(node); -#else - vg_lite_os_free(node); -#endif /* VG_DRIVER_SINGLE_THREAD */ - } - break; - } - /* when release command buffer node and ts buffer node to exit,release the linked list*/ - if(device->heap.list.next == device->heap.list.prev) { - delete_list(&pos->list); -#if defined(VG_DRIVER_SINGLE_THREAD) - vg_lite_hal_free(pos); -#else - vg_lite_os_free(pos); -#endif /* VG_DRIVER_SINGLE_THREAD */ - } -} - -void vg_lite_hal_free_os_heap(void) -{ - struct heap_node *pos, *n; - - /* Check for valid device. */ - if (device != NULL) { - /* Process each node. */ - for (pos = (heap_node_t *)device->heap.list.next, - n = (heap_node_t *)pos->list.next; - &pos->list != &device->heap.list; - pos = n, n = (heap_node_t *)n->list.next) { - /* Remove it from the linked list. */ - delete_list(&pos->list); - /* Free up the memory. */ -#if defined(VG_DRIVER_SINGLE_THREAD) - vg_lite_hal_free(pos); -#else - vg_lite_os_free(pos); -#endif /* VG_DRIVER_SINGLE_THREAD */ - } - } -} - -/* Portable: read register value. */ -uint32_t vg_lite_hal_peek(uint32_t address) -{ - /* Read data from the GPU register. */ - return (uint32_t) (*(volatile uint32_t *) (device->gpu + address)); -} - -/* Portable: write register. */ -void vg_lite_hal_poke(uint32_t address, uint32_t data) -{ - /* Write data to the GPU register. */ - uint32_t *LocalAddr = (uint32_t *)(device->gpu + address); - *LocalAddr = data; -} - -vg_lite_error_t vg_lite_hal_query_mem(vg_lite_kernel_mem_t *mem) -{ - if(device != NULL){ - mem->bytes = device->heap.free; - return VG_LITE_SUCCESS; - } - mem->bytes = 0; - return VG_LITE_NO_CONTEXT; -} - -#if defined(VG_DRIVER_SINGLE_THREAD) -void __attribute__((weak)) vg_lite_bus_error_handler() -{ - /* - * Default implementation of the bus error handler does nothing. Application - * should override this handler if it requires to be notified when a bus - * error event occurs. - */ - return; -} - -// added by MicroEJ -#if _VG_LITE_IRQ_CALLBACK == 1 -void vg_lite_hal_register_irq_callback(vg_lite_irq_callback cb) { - __irq_callback = cb; -} -#endif /* _VG_LITE_IRQ_CALLBACK */ - -#endif /* VG_DRIVER_SINGLE_THREAD */ - -void vg_lite_IRQHandler(void) -{ -#if defined(VG_DRIVER_SINGLE_THREAD) - uint32_t flags = vg_lite_hal_peek(VG_LITE_INTR_STATUS); - portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - - if (flags) { - /* Combine with current interrupt flags. */ - device->int_flags |= flags; - - /* Wake up any waiters. */ - if(device->int_queue){ - xSemaphoreGiveFromISR(device->int_queue, &xHigherPriorityTaskWoken); - if(xHigherPriorityTaskWoken != pdFALSE ) - { - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); - } - } - } - - // added by MicroEJ -#if _VG_LITE_IRQ_CALLBACK == 1 - if (__irq_callback != NULL) { - __irq_callback(); - } -#endif /* _VG_LITE_IRQ_CALLBACK */ -#else - vg_lite_os_IRQHandler(); -#endif /* VG_DRIVER_SINGLE_THREAD */ - -} - -int32_t vg_lite_hal_wait_interrupt(uint32_t timeout, uint32_t mask, uint32_t * value) -{ -#if defined(VG_DRIVER_SINGLE_THREAD) -#if _BAREMETAL - uint32_t int_status=0; - int_status = vg_lite_hal_peek(VG_LITE_INTR_STATUS); - (void)value; - - while (int_status==0){ - int_status = vg_lite_hal_peek(VG_LITE_INTR_STATUS); - usleep(1); - } - - if (IS_AXI_BUS_ERR(*value)) - { - vg_lite_bus_error_handler(); - } - return 1; -#else /*for rt500*/ - if(device->int_queue) { - if (xSemaphoreTake(device->int_queue, timeout / portTICK_PERIOD_MS) == pdTRUE) { - if (value != NULL) { - *value = device->int_flags & mask; - if (IS_AXI_BUS_ERR(*value)) - { - vg_lite_bus_error_handler(); - } - } - device->int_flags = 0; - - return 1; - } - } - return 0; -#endif -#else - return vg_lite_os_wait_interrupt(timeout,mask,value); -#endif /* VG_DRIVER_SINGLE_THREAD */ -} - -void * vg_lite_hal_map(unsigned long bytes, void * logical, uint32_t physical, uint32_t * gpu) -{ - - (void) bytes; - (void) logical; - (void) physical; - (void) gpu; - return (void *)0; -} - -void vg_lite_hal_unmap(void * handle) -{ - - (void) handle; -} - -#if !defined(VG_DRIVER_SINGLE_THREAD) -vg_lite_error_t vg_lite_hal_submit(uint32_t context,uint32_t physical, uint32_t offset, uint32_t size, vg_lite_os_async_event_t *event) -{ - return (vg_lite_error_t)vg_lite_os_submit(context,physical,offset,size,event); -} - -vg_lite_error_t vg_lite_hal_wait(uint32_t timeout, vg_lite_os_async_event_t *event) -{ - return (vg_lite_error_t)vg_lite_os_wait(timeout,event); -} -#endif /* not defined(VG_DRIVER_SINGLE_THREAD) */ - -static void vg_lite_exit(void) -{ - heap_node_t * pos; - heap_node_t * n; - - /* Check for valid device. */ - if (device != NULL) { - /* TODO: unmap register mem should be unnecessary. */ - device->gpu = 0; - - /* Process each node. */ - for (pos = (heap_node_t *)device->heap.list.next, n = (heap_node_t *)pos->list.next; - &pos->list != &device->heap.list; - pos = n, n = (heap_node_t *)n->list.next) { - /* Remove it from the linked list. */ - delete_list(&pos->list); - - /* Free up the memory. */ -#if defined(VG_DRIVER_SINGLE_THREAD) - vg_lite_hal_free(pos); -#else - vg_lite_os_free(pos); -#endif /* VG_DRIVER_SINGLE_THREAD */ - } - - /* Free up the device structure. */ -#if defined(VG_DRIVER_SINGLE_THREAD) - vg_lite_hal_free(device); -#else - vg_lite_os_free(device); -#endif /* VG_DRIVER_SINGLE_THREAD */ - } -} - -static int vg_lite_init(void) -{ - heap_node_t * node; - - /* Initialize memory and objects ***************************************/ - /* Create device structure. */ - device = &Device; - - /* Zero out the enture structure. */ - _memset(device, 0, sizeof(struct vg_lite_device)); - - /* Setup register memory. **********************************************/ - device->gpu = registerMemBase; - - /* Initialize contiguous memory. ***************************************/ - /* Allocate the contiguous memory. */ - device->heap_size = heap_size; - device->contiguous = (volatile void *)contiguousMem; - _memset((void *)device->contiguous, 0, heap_size); - /* Make 64byte aligned. */ - while ((((uint32_t)device->contiguous) & 63) != 0) - { - device->contiguous = ((unsigned char*) device->contiguous) + 4; - device->heap_size -= 4; - } - - /* Check if we allocated any contiguous memory or not. */ - if (device->contiguous == NULL) { - vg_lite_exit(); - return -1; - } - - device->virtual = (void *)device->contiguous; - device->physical = gpuMemBase + (uint32_t)device->virtual; - device->size = device->heap_size; - - /* Create the heap. */ - INIT_LIST_HEAD(&device->heap.list); - device->heap.free = device->size; - -#if defined(VG_DRIVER_SINGLE_THREAD) - node = vg_lite_hal_alloc(sizeof(heap_node_t)); -#else - node = (heap_node_t *)vg_lite_os_malloc(sizeof(heap_node_t)); -#endif /* VG_DRIVER_SINGLE_THREAD */ - - if (node == NULL) { - vg_lite_exit(); - return -1; - } - node->offset = 0; - node->size = device->size; - node->status = 0; - add_list(&node->list, &device->heap.list); -#if defined(VG_DRIVER_SINGLE_THREAD) -#if !_BAREMETAL /*for rt500*/ - device->int_queue = xSemaphoreCreateBinary(); - device->int_flags = 0; -#endif -#endif /* VG_DRIVER_SINGLE_THREAD */ - /* Success. */ - return 0; -} diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/LICENSE b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/LICENSE deleted file mode 100644 index d1fad06..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/font/mcufont/LICENSE +++ /dev/null @@ -1,31 +0,0 @@ -mcufont is available under the MIT license: - -Copyright (C) 2013 Petteri Aimonen - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice shall be -included in all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - ---- - -In addition, the files under the "decoder" folder and all font files -generated by the encoder are placed in the public domain. You can do -anything with them without any restriction from me. - -Note that the licenses of the fonts you import may pose additional -restrictions. diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/middleware_vglite_MIMXRT595S_cm33.cmake b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/middleware_vglite_MIMXRT595S_cm33.cmake deleted file mode 100644 index 4051a0d..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/middleware_vglite_MIMXRT595S_cm33.cmake +++ /dev/null @@ -1,37 +0,0 @@ -include_guard() -message("middleware_vglite component is included.") - -target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE - ${CMAKE_CURRENT_LIST_DIR}/VGLite/vg_lite.c - ${CMAKE_CURRENT_LIST_DIR}/VGLite/vg_lite_image.c - ${CMAKE_CURRENT_LIST_DIR}/VGLite/vg_lite_matrix.c - ${CMAKE_CURRENT_LIST_DIR}/VGLite/vg_lite_path.c - ${CMAKE_CURRENT_LIST_DIR}/VGLite/rtos/vg_lite_os.c - ${CMAKE_CURRENT_LIST_DIR}/font/buf_reader.c - ${CMAKE_CURRENT_LIST_DIR}/font/rle_font_read.c - ${CMAKE_CURRENT_LIST_DIR}/font/vft_debug.c - ${CMAKE_CURRENT_LIST_DIR}/font/vft_draw.c - ${CMAKE_CURRENT_LIST_DIR}/font/vg_lite_text.c - ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_bwfont.c - ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_encoding.c - ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_font.c - ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_justify.c - ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_kerning.c - ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_rlefont.c - ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_scaledfont.c - ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder/mf_wordwrap.c - ${CMAKE_CURRENT_LIST_DIR}/VGLiteKernel/vg_lite_kernel.c - ${CMAKE_CURRENT_LIST_DIR}/VGLiteKernel/rtos/vg_lite_hal.c -) - - -target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE - ${CMAKE_CURRENT_LIST_DIR}/inc - ${CMAKE_CURRENT_LIST_DIR}/font - ${CMAKE_CURRENT_LIST_DIR}/font/mcufont/decoder - ${CMAKE_CURRENT_LIST_DIR}/VGLite/rtos - ${CMAKE_CURRENT_LIST_DIR}/VGLiteKernel - ${CMAKE_CURRENT_LIST_DIR}/VGLiteKernel/rtos -) - - diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/middleware_vglite_elementary_MIMXRT595S_cm33.cmake b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/middleware_vglite_elementary_MIMXRT595S_cm33.cmake deleted file mode 100644 index cf45905..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/middleware/vglite/middleware_vglite_elementary_MIMXRT595S_cm33.cmake +++ /dev/null @@ -1,19 +0,0 @@ -include_guard() -message("middleware_vglite_elementary component is included.") - -target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE - ${CMAKE_CURRENT_LIST_DIR}/elementary/src/elm_buffer.c - ${CMAKE_CURRENT_LIST_DIR}/elementary/src/elm_draw.c - ${CMAKE_CURRENT_LIST_DIR}/elementary/src/elm_init.c - ${CMAKE_CURRENT_LIST_DIR}/elementary/src/elm_object.c - ${CMAKE_CURRENT_LIST_DIR}/elementary/src/elm_os.c - ${CMAKE_CURRENT_LIST_DIR}/elementary/src/elm_text.c -) - - -target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE - ${CMAKE_CURRENT_LIST_DIR}/elementary/inc - ${CMAKE_CURRENT_LIST_DIR}/elementary/src -) - - diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/CHANGELOG.md b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/CHANGELOG.md deleted file mode 100644 index 3564e83..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/CHANGELOG.md +++ /dev/null @@ -1,833 +0,0 @@ -# Change Log for Amazon FreeRTOS - -## 201908.00 08/26/2019 - -### New Features -#### New Board:Nuvoton NuMaker-IoT-M487 -- Nuvoton NuMaker-IoT-M487 is now qualified for Amazon FreeRTOS. -- Disclaimer on RNG: The random number generation solution in this port is for demonstration purposes only. - -#### FreeRTOS Kernel V10.2.1 -- Kernel version for Amazon FreeRTOS is updated to V10.2.1. -- Add ARM Cortex-M23 (ARMv8-M) GCC/ARMclang and IAR ports. -- Add support to automatically switch between 32-bit and 64-bit cores to RISC-V port. - -#### HTTPS Client Library V1.0.0 -- The HTTPS Client library for Amazon FreeRTOS supports the HTTP/1.1 protocol over TLS. -- The current request methods supported are GET and HEAD. -- Examples demonstrate downloading a file from S3 using GET with a pre-signed URL. - -### Updates -#### PKCS #11 -- Update the Amazon FreeRTOS mbedTLS-based PKCS #11 implementation, tests, demos, and PKCS #11 consuming libraries for compliance with standard. -- Add PKCS #11 wrapper functions for easy use of commonly grouped PKCS #11 calls. - -#### Demo specific stack size and priority -- Make stack size and priority to be demo specific. In current release all demos have same stack size and priority. This change will make stack size and priority configurable for each demo. Demo can use default stack size/ priority or define its own. -#### Ethernet for Microchip Curiosity PIC32MZEF -- Update Microchip Curiosity PIC32MZEF project and configuration files to support Ethernet connectivty. Developers must define PIC32_USE_ETHERNET at the project level to use Ethernet instead of Wi-Fi. -#### lwIP 2.1.2 -- Update lwIP to version 2.1.2, and change existing ports as necessary. - -### Test Updates -- Remove elliptic curve tests from "quarantine" test group and add them back to the TLS test group. - -#### AWS OTA Agent -- OTA Callback changes for custom and secondary processor jobs. Modifying the OTA Agent to use callback structure instead of directly calling PAL functions. This allows users to pass in custom callbacks for the PAL functions. - -## 201906.00 Major 06/17/2019 -### Release Versioning -- Move Amazon FreeRTOS to a new versioning scheme (YYYYMM.NN [optional "Major" tag]), while retaining semantic versioning (x.y.z) used for individual libraries within Amazon FreeRTOS. This release contains multiple major version updates for individual libraries. See below for details. - -### Folder Structure -- Update folder structure to provide a cleaner separation between FreeRTOS kernel, standard libraries, AWS libraries, platform-specific ports and 3rd party libraries. Customers upgrading from earlier versions will need to update their project files. - -### New Features -#### Bluetooth Low Energy Management Library V1.0.0 -- Bluetooth Low Energy management API for GAP and GATT services, with support for - - Bluetooth Low Energy v4.2 and above. - - Device discovery, notifications and indications. - - Creating, starting, stopping, and deleting GATT services. - - “Just Works” and “Secure Connections - Numeric Comparison” connection methods. -- Companion device SDK 1.0.0 release for - - Android https://github.com/aws/amazon-freertos-ble-android-sdk/ - - iOS https://github.com/aws/amazon-freertos-ble-ios-sdk/ -- GATT services for - - Device information. - - Wi-Fi credentials provisioning. - - MQTT-over-Bluetooth Low Energy through Android or iOS device proxy to support. - - OTA and Device Shadow functionality. - -#### MQTT Library V2.0.0, Device Shadow Library V2.0.0, and Device Defender Library V2.0.0 -- Enable consistent re-use pattern of one single connection across all libraries. -- Add support for MQTT 3.1.1 standard features. - - Last Will and Testament. - - QoS1 with randomized retry logic. - - Persistent sessions. -- Add programming model revisions to enable. - - Fully non-blocking programming model. - - Per-operation user callback. - - Fully dynamic or fully static memory management. - - Full support for Bluetooth Low Energy transport as well as TCP/IP. - - Re-implementable abstraction layer to allow port on any network stacks. - - Standard, configurable logging mechanism. -- Extend Device Defender support to additional development boards. Current set of metrics now available on all development boards that implement Secure Sockets abstraction. - -#### Task Pool library V1.0.0 -- Task (Thread) pool library for asynchronous processing. - -#### Atomic Operations Library V1.0.0 -- Add library for atomic operations support. - -### Updates -#### Wi-Fi Management Library V1.0.3 -- Add new API ```WIFI_RegisterNetworkStateChangeEventCallback``` to allow application notifications for Wi-Fi state transitions. - -#### CMake Builds -- Extend the ability to build projects using CMake in addition to providing IDE project files. CMake files are now available for the following development boards: - - Espressif ESP32-DevKitC - - Espressif ESP-WROVER-KIT - - Infineon XMC4800 IoT Connectivity Kit - - Marvell MW320 AWS IoT Starter Kit - - Marvell MW322 AWS IoT Starter Kit - - Microchip Curiosity PIC32MZEF Bundle - - STMicroelectronicsSTM32L4 Discovery Kit IoT Node - - Texas Instruments CC3220SF-LAUNCHXL - - Microsoft Windows Simulator - -### Updates -- mbedTLS library is upgraded to version 2.16.0. -- ESP-IDF version is upgraded to 3.1.3. -- Update demo projects for cleaner separation of platform specific code. -- Documentation update. - -## V1.4.8 05/21/2019 -### New Features -#### New Boards: Marvell MW320 and MW322 -- Marvell boards MW320 and MW322 are now qualified for Amazon FreeRTOS. -- Disclaimer on RNG: The random number generation solution in this port is for demonstration purposes only. - -#### FreeRTOS Kernel V10.2.0 -- Kernel version for Amazon FreeRTOS is updated to V10.2.0. -- Add Support for RISC-V. -- Include pre-existing ARM Cortex-M33 (ARMv8-M) GCC/ARMclang and IAR ports. - -### Updates - -#### Greengrass Discovery V1.0.4 -- Include C runtime header for snprintf. -- Sanity check the number of bytes written. -- Thing name can be a non-string literal. - -#### MQTT Agent V1.1.5 -- Set the socket to block on sends with a timeout in prvSetupConnection. - -#### Secure Sockets for FreeRTOS+TCP V1.1.6 -- ulApplicationGetNextSequenceNumber is now thread safe without stopping the scheduler. -- Leave the scheduler running during PKCS #11 calls. - -#### Wi-Fi for ESP32-DevKitC ESP-WROVER-KIT V1.0.2 -- lib/wifi: fix issue with WiFi configuration for non-null strings, and fix scanning failure under certain disconnect scenarios. -- ib/FreeRTOS-Plus-TCP: do not send eNetworkDownEvent to stack if interface is already down. -- mbedtls: configurable options for controlling dynamic memory allocations. -- lib/third_party: update ESP-IDF to latest v3.1.3 release. -- NetworkInterface: check interface state before sending packets to WiFi driver. -- Fix WIFI_GetMac returning wrong mac address. - -#### PKCS #11 PAL for Cypress CYW943907AEVAL1F development kit V1.0.1 -- Fix Cypress build error with IDE. - -#### PKCS #11 PAL for Cypress CYW954907AEVAL1F development kit V1.0.1 -- Fix Cypress build error with IDE. - -#### FreeRTOS+TCP V2.0.11 -- Make RST packet handling more robust. -- Make TCP window high and low watermark thresholds runtime configurable. -- Fix parsing of the last option in a DHCP response packet. -- Fix TCP window size calculation. -- Allow the DNS cache to be programmatically cleared. -- Free the memory allocated by the pcap_compile routine in the WinPCap network interface module. - -#### Shadow V1.0.6 -- Add a debug message in the event that JSMN runs out of memory trying to parse JSON. -- Print a debug message for any JSMN error, not just 'JSMN_ERROR_NOMEM'. - -#### PKCS #11 PAL for Windows Simulator V1.0.4 -- Update to permit multithreaded read from object storage. - -#### OTA Agent V1.0.2 -- Update documentation. - -#### TLS V1.1.4 -- TLS_Send now handles the error condition when space is not avaiable. -- Convert errors in TLS wrapper to negative error codes. - -#### Curiosity PIC32MZEF Linker Update for XC32 Compiler -- The latest XC32 compiler (version 2.15) does not allow multiple definitions by default. Explicitly enabling multiple definitions in aws_tests and aws_demos projects for now. - -## V1.4.7 02/18/2019 -### New Features -### New Boards: Cypress CYW43907 and CYW54907 -- Cypress boards CYW54907 and CYW43907 are now qualified for Amazon FreeRTOS. - -#### FreeRTOS Kernel V10.1.1 -- Kernel version for Amazon FreeRTOS is updated to 10.1.1. -- Update all object handles (TaskHandle_t, QueueHandle_t, etc.) to be unique types instead of void pointers, improving type safety. -- Add Xtensa port. -- Update to the latest trace recorder code. -- Update lint checked MISRA compliance to use the latest MISRA standard. -- Add configUSE_POSIX_ERRNO to enable per task POSIX style errno functionality. - -### Updates - -#### FreeRTOS+POSIX V1.0.3 -- Use stack based alloaction for POSIX types. Stack based allocation will reduce heap fragmentation. -- Fixed potential overflow in Posix timespec utils. -- Stopped Posix timer spawnning thread every time it is invoked. -- Unlock and update owner atomically, while unlocking mutex. - -#### MQTT Agent V1.1.4 -- Bug fix: MQTT agent tries to setup a connection with the MQTT broker when the socket does not exist. - -#### Upgrading ESP-IDF to 3.1.1 -- ESP-IDF upgraded to 3.1.1. - -#### OTA PAL for Curiosity PIC32MZEF V1.0.3 -- Rename variables to comply with style guidelines. - -#### OTA PAL for Windows Simulator V1.0.2 -- Rename variables to comply with style guidelines. - -#### OTA PAL for CC3220SF-LAUNCHXL V1.0.1 -- Rename variables to comply with style guidelines. - -#### OTA Agent V1.0.1 -- Rename variables to comply with style guidelines. - -#### PKCS #11 PAL for Cypress CYW943907AEVAL1F development kit V1.0.0 -- Added as part of Cypress CYW43907 board port. -- Note that the random number generation solution in this port is provided for demonstration purposes only. See the comment in lib/pkcs11/portable/cypress/CYW943907AEVAL1F/hw_poll.c. - -#### PKCS #11 PAL for Cypress CYW954907AEVAL1F development kit V1.0.0 -- Added as part of Cypress CYW54907 board port. -- Note that the random number generation solution in this port is provided for demonstration purposes only. See the comment in lib/pkcs11/portable/cypress/CYW954907AEVAL1F/hw_poll.c - -#### PKCS #11 PAL for ESP32-DevKitC ESP-WROVER-KIT V1.0.2 -- Updated as part of Updrade to ESP-IDF to 3.1.1. - -#### mbedTLS-based PKCS#11 V1.0.7 -- Bug Fix: Multi-threaded use of PKCS #11 Sign/Verify could cause key corruption. - -#### Wi-Fi for Cypress CYW943907AEVAL1F development kit V1.0.0 -- Added as part of Cypress CYW43907 board port. - -#### Wi-Fi for Cypress CYW954907AEVAL1F development kit V1.0.0 -- Added as part of Cypress CYW54907 board port. - -#### Wi-Fi for ESP32-DevKitC ESP-WROVER-KIT V1.0.1 -- Update as part of Updrade to ESP-IDF to 3.1.1. - -#### Wi-Fi for LPC54018 IoT Module V1.0.3 -- Bug fix: Update WIFI init API to return success if WIFI module was already successfully initialized. -- Bug fix: Update WIFI AP connection API for NXP to check if DHCP was successful. - -## V1.4.6 12/27/2018 -### New Features - -#### New Board: Renesas Starter Kit+ for RX65N-2MB -The Renesas Starter Kit+ for RX65N-2MB is now qualified for Amazon FreeRTOS. This port updates the PKCS #11 portable layer, demo projects, and tests. - -### Updates - -#### FreeRTOS+POSIX V1.0.2 -- Improvement to reduce the size of a pthread object and make the object user allocatable from stack. - -#### FreeRTOS+TCP V2.0.10 -- Add FreeRTOS+TCP support for the Renesas Starter Kit+ for RX65N-2MB. - -#### FreeRTOS Kernel V10.0.1 -- Add FreeRTOS Kernel support for the Renesas Starter Kit+ for RX65N-2MB. - -#### PKCS #11 PAL for MT7697Hx-Dev-Kit V1.0.1 -- Update license information. - -#### PKCS #11 PAL for Renesas Starter Kit+ for RX65N-2MB V1.0.0 -- Add PKCS #11 support for the Renesas Starter Kit+ for RX65N-2MB. -- Note that the random number generation solution in this port is provided for demonstration purposes only. See the comment in lib/third_party/mcu_vendor/renesas/amazon_freertos_common/entropy_hardware_poll.c for more information. - -#### Wi-Fi for MT7697Hx-Dev-Kit V1.0.1 -- Update license information. - -## V1.4.5 12/13/2018 -### New Features - -#### New Board: MediaTek MT7697Hx-Dev-Kit -The MediaTek MT7697 System on Chip (SoC) is now qualified for Amazon FreeRTOS. You can take advantage of Amazon FreeRTOS features and benefits using the MediaTek MT7697Hx Development Kit available from MediaTek Labs. This development board contains the MT7697 SoC, which includes an Arm Cortex-M4 MCU, low power 1T1R 802.11 b/g/n Wi-Fi, Bluetooth 4.2 subsystem and power management unit. - -#### lwIP Support -Amazon FreeRTOS support for the MediaTek MT7697Hx-Dev-Kit includes for the first time support for the Lightweight TCP / IP network stack (lwIP). This flexibility will support customer choice in identifying the best TCP stack solution for IoT devices. - -### Updates - -#### FreeRTOS+TCP V2.0.9 -- Update to flush ARP cache when then network is down. - -#### mbedTLS-based PKCS#11 V1.0.6 -- Delete extra include headers. - -#### PKCS #11 PAL for MT7697Hx-Dev-Kit V1.0.0 -- Add PKCS #11 support for the MediaTek MT7697Hx-Dev-Kit. - -#### Secure Sockets for FreeRTOS+TCP V1.1.5 -- Update documentation. - -#### Secure Sockets for lwIP V1.0.0 -- Add Secure Sockets support for lwIP. - -#### Wi-Fi for Infineon XMC4800 IoT Connectivity Kit V1.0.1 -- Update documentation. - -#### Wi-Fi for MT7697Hx-Dev-Kit V1.0.0 -- Add Wi-Fi support for the MediaTek MT7697Hx-Dev-Kit. - -## V1.4.4 11/19/2018 -### Updates - -#### Device Defender Demo V1.4.4 -- Remove warnings in Device Defender Demo build. - -#### Microchip "OTA Demo" Factory Image Script -- Fix post-build command and python script for generating OTA factory image for Mac users. - -#### Device Defender Agent V1.0.2 -- Update formatting and build warnings. - -#### OTA PAL for ESP32-DevKitC ESP-WROVER-KIT V1.0.2 -- Fix bug in retrieving code signature verification certificate. - -#### OTA PAL for Curiosity PIC32MZEF V1.0.2 -- Fix bug in retrieving code signature verification certificate. - -## V1.4.3 11/07/2018 -### New Features - -#### New Board: Xilinx Zynq-7000 based MicroZed Industrial IoT Bundle -- Update Amazon FreeRTOS with port files, demo projects, and tests for the Xilinx Zynq-7000 based MicroZed Industrial IoT Bundle - -### Updates - -#### mbedTLS Library -- Upgrade to mbedTLS version 2.13.1. - -#### FreeRTOS+POSIX V1.0.1 -- Minor bug fixes. - -#### FreeRTOS+TCP V2.0.8 -- Update the Zynq-7000 portable layer for receive descriptor alignment. - -#### PKCS #11 Updates -Update mbedTLS-based PKCS #11, and PKCS #11 PAL. These changes have been made to more closely align with the PKCS #11 standard, respond to feedback from users and partners, and make it easy for users to go to production from a prototype. -Applications calling into PKCS #11 functions directly (rather than indirectly via an Amazon provided secure sockets or TLS layer) may experience breaking changes. - -##### mbedTLS-based PKCS #11 -- C_Initialize handles initialization of randomness in an effort to minimize entropy generation (or seed access) every time sessions are created and destroyed. To protect random values, thread safety has been enabled in mbedTLS. -- C_SignInit and C_VerifyInit utilize the key handle that is passed in, rather than the first key found in order to comply with the PKCS #11 standard -- C_FindObject APIs no longer instantiate keys from the aws_clientcredential_keys.h header file if keys are not found. This removes the dependency of PKCS #11 on values that will be unique per-device (a transition step for enabling production-scale provisioning). Note that calling vDevModeKeyProvisioning() is now necessary to provision the device. -- C_FindObject PKCS #11 objects can be looked up by CKA_LABEL, in order to provide a standard-compliant object lookup. Note that pkcs11configFILE_NAME_* configurations have been removed from aws_pkcs11_config.h, see aws_pkcs11.h for pkcs11configLABEL_* defines to access labels, and aws_pkcs11_pal.c for pkcs11palFILE_NAME_* defines. -- C_FindObject and C_GetAttributeValue accept different attribute arguments. -- C_CreateObject requires DER encoded certificates and keys instead of PEM formatted and object attributes required for creating objects have changed. Note that vDevModeKeyProvisioning() has been updated to supply required attributes and convert inputs from DER to PEM if necessary. -- C_GenerateKeyPair now stores keys in non-volatile memory. -- C_Finalize is no longer invoked by helper functions to prevent threads from interfering with each other's PKCS #11 instances. -- Some error codes have been changes to better match the PKCS #11 standard. -- aws_tls.c and PKCS #11 AFQP tests have updates to reflect these changes. - - mbedTLS-based PKCS #11 V1.0.5 - - TLS V1.1.3 - -##### PKCS #11 PAL for mbedTLS-based PKCS #11 -- Breaking changes were made to PAL PKCS #11 functions in order to transition from file-centric API to object handle and object label based API. - - PKCS #11 PAL for ESP32-DevKitC ESP-WROVER-KIT V1.0.1 - - PKCS #11 PAL for XMC4800 IoT Kit V1.0.1 - - PKCS #11 PAL for Curiosity PIC32MZEF V1.0.4 - - PKCS #11 PAL for LPC54018 IoT Module V1.0.3 - - PKCS #11 PAL for Windows Simulator V1.0.3 - - PKCS #11 PAL for STM32L4 Discovery kit IoT node V1.0.3 - - PKCS #11 PAL for Xilinx Zynq MicroZed V1.0.0 (new) - -##### PKCS #11 for CC3220SF-LAUNCHXL -- Updates to match behavior of mbedTLS-based PKCS #11. -- mbedTLS added to support conversion between DER and PEM objects. Note that after provisioning the device, mbedTLS and provisiong PKCS #11 functions may be removed to reduce code size. - - PKCS #11 PAL for CC3220SF-LAUNCHXL V1.0.3 - -##### OTA PAL Updates -- The OTA PALs for the Curiosity PIC32MZEF and ESP32-DevKitC ESP-WROVER-KIT boards have been modified to utilize PKCS #11 API to retrieve code signing keys, rather than calling into PKCS #11 PAL functions. - - OTA PAL for Curiosity PIC32MZEF V1.0.1 - - OTA PAL for ESP32-DevKitC ESP-WROVER-KIT V1.0.1 - -#### Secure Socket for FreeRTOS+TCP V1.1.4 -- Minor update to handle PKCS #11 error codes. -- Update formatting. - -#### Secure Sockets for Infineon XMC4800 IoT Connectivity Kit V1.0.1 -- Fix the license header from Secure Socket to Secure Sockets. - -#### Secure Sockets for STM32L4 Discovery kit IoT node V1.0.0 Beta 4 -- Bug fix to support Amazon Trust Services endpoints. For more information, please see https://aws.amazon.com/blogs/iot/aws-iot-core-ats-endpoints/. - -#### Secure Sockets for CC3220SF-LAUNCHXL V1.0.5 -- Remove duplicate file name definitions. See aws_secure_sockets_config.h for file name defines. - -#### Shadow V1.0.5 -- Minor bug fixes. - - -## V1.4.2 10/17/2018 -### New Features - -#### New Board: Infineon XMC4800 IoT Connectivity Kit -Update Amazon FreeRTOS with port files, demo projects, and tests for the Infineon XMC4800 IoT Connectivity Kit. - -### Updates - -#### Update pthread Implementation in ESP-IDF -Incorporate an update to Espressif's ESP-IDF which improves the implementation of pthread. - -#### Build Improvement: MPLAB PIC32 Projects -Resolve several warnings in the MPLAB project builds, and update the projects to no longer assume that the XC32 compiler is in the host computer's path. - -#### Move Helper Utilities to the 'tools/' Directory -Move a few utilities to the root-level 'tools/' directory, from the 'tests/common/tools/' and 'demos/common/tools/' directories. - -#### Styling Updates -Improve consistency of Hungarian Notation usage, update a number of methods to use 'void' instead of an empty argument list, and update the style guide. - -#### New POSIX Functions -Add POSIX functions including `time`, `localtime_r`, and `strftime`. - -#### Refactor Device Defender Direcory Structure -Update Device Defender code to use the same 'lib/' and 'include/' directory structures as the other libraries. - -#### AFQP Documentation Updates -Update the Amazon FreeRTOS Qualification Program's documentation to reflect updated directory structures. - -## V1.4.1 08/29/2018 -### New Features -None - -### Updates - -#### OTA PAL for Windows Simulator V1.0.1 -- Update Amazon FreeRTOS Windows Simulator to use ECDSA/SHA-256 for OTA image verification. - - -## V1.4.0 08/27/2018 -### New Features - -#### Demo Bootloader for Microchip Curiosity PIC32MZEF V1.0.0 -The demo bootloader supports Amazon FreeRTOS over-the-air (OTA) update by implementing firmware version checking, cryptographic signature verification, and application self-test. The firmware verification includes verifying the authenticity and integrity of the new firmware received over the air. The bootloader verifies the cryptographic signature of the application before boot. The elliptic-curve digital signature algorithm (ECDSA) with SHA256 is used. The utilities provided can be used to generate a signed application that can be flashed on the device. This enables signature verification of the initial image. - -### Updates - -#### Over-the-air (OTA) updates -The over-the-air (OTA) updates feature of Amazon FreeRTOS is now generally available. The release includes enhancements to the OTA Agent and changes to the OTA Portable Abstraction Layer (PAL) interface. - -#### OTA PAL for Curiosity PIC32MZEF V1.0.0 -Update for API changes for OTA general availability release. - -#### OTA PAL for Windows Simulator V1.0.0 -Update for API changes for OTA general availability release. - -#### OTA PAL for CC3220SF-LAUNCHXL V1.0.0 -Update for API changes for OTA general availability release. - -#### OTA PAL for Espressif ESP32 V1.0.0 -Update for API changes for OTA general availability release. - -#### OTA Agent V1.0.0 -Enhancements and API changes for OTA general availability release. - - -## V1.3.2 08/21/2018 -### New Features -None - -### Updates - -#### FreeRTOS+TCP -- Multiple security improvements and fixes in packet parsing routines, DNS caching, and TCP sequence number and ID generation. -- Disable NBNS and LLMNR by default. -- Add TCP hang protection by default. - -#### Secure Sockets for FreeRTOS+TCP -- Improve security in Amazon FreeRTOS Secure Sockets usage of mbedTLS and ALPN. - -We thank Ori Karliner of Zimperium zLabs Team for reporting these issues. - - -## V1.3.1 08/10/2018 -### New Features -None - -### Updates - -#### OTA Beta Update -- Updates to OTA Beta to incorporate a new API for the OTA service. This API is not compatible with the API used in the original OTA Beta released on Dec. 20th. -- Add a "reference bootloader" for use in the OTA process. This bootloader is for use with the Microchip MCU. - -#### Amazon FreeRTOS Qualification Program (AFQP) Update -- Update AFQP documentation. For more info on the changes to AFQP, reference the Revision History of the "Amazon FreeRTOS Qualification Program Developer Guide" in the "tests" directory. - -#### Device Defender Update -- Add a demo to illustrate the operation of Device Defender for the Windows Simulator and Microchip PIC32MZEF MCU. - -#### TI "Hello World" Build Failure Resolution -- Address an issue where the "Hello World" demo did not build with TI CCS 7.3 in AFR 1.3.0 when downloaded from OCW. - - -## V1.3.0 07/31/2018 - -### New Features - -#### AFQP 1.0 Support -This release of AFR has support for vendors who wish to have their ports qualified for Amazon FreeRTOS through the Amazon FreeRTOS Qualification Program (AFQP). This is the first public release of AFQP tests and documentation. A new top level "tests" directory is added to support this functionality. AFQP documents are available in "tests" directory. [Learn more.](https://docs.aws.amazon.com/freertos/latest/userguide/freertos-qualification-program.html) - -#### Device Defender 1.0 Support -AWS IoT Device Defender is an AWS IoT security service that allows users to audit the configuration of their devices, monitor connected devices to detect abnormal behavior, and to mitigate security risks. It gives you the ability to enforce consistent security policies across your AWS IoT device fleet and respond quickly when devices are compromised. Device side support of this feature is part of this release. Devices supported are WinSim and Microchip PIC32MZEF. [Learn more.](https://docs.aws.amazon.com/freertos/latest/userguide/afr-device-defender-library.html) - -#### FreeRTOS+POSIX 1.0 Interface -This release includes version 1.0.0 of FreeRTOS+POSIX. FreeRTOS+POSIX is a POSIX compatibility layer that allows existing POSIX applications to run without modifications of FreeRTOS. This release supports POSIX threads, mutexes, barriers, condition variables, semaphores, message queues, clocks, timers, and error numbers. While most of the POSIX functions are implemented and up to specification, limitations in the FreeRTOS kernel precluded the standard implementations of certain functions. The functions which differ from the POSIX specification are identified in their header files. Currently, FreeRTOS+POSIX is only used by drivers of the TI CC3220SF. - -### Updates - -#### FreeRTOS Kernel V10.0.1 -- Add Idle tick counter interface -- Rename posix/ to FreeRTOS_POSIX/ - -#### FreeRTOS+TCP V2.0.4 -- Fix issues raised by the Coverity scan - - Fix a typo ulRxWindowLength -> ulTxWindowLength in FreeRTOS_Sockets.c - - Fix strncmp length in FreeRTOS_DNS.c - - Fix styling in FreeRTOS_ARP.c -- Fix a spelling typo ";east" -> "least" (response from a pull request) -- Add auto check of network interfaces for WinSim - -#### MQTT Agent V1.1.2 -- Move MQTT metrics to agent - -#### mbedTLS-based PKCS #11 V1.0.3 -- Reduce the number of warnings generated - -#### PKCS #11 for LPC54018 IoT Module V1.0.1 -- Change project baudrate setting to resolve AFQP test failures - -#### Secure Sockets for NXP54018_IoT_Module V1.0.0 Beta 3 -- Update to latest NXP driver to address AFQP 1.0 test failures - -#### Secure Sockets for STM32L4 Discovery kit IoT node V1.0.0 Beta 2 -- Update to new Inventek driver to resolve AFQP 1.0 test failures - -#### Wi-Fi for Curiosity PIC32MZEF V1.0.3 -- Change Microchip network param to use a direct address instead of a section to reduce the size of the binary image to allow OTA to continue working. -- Reduce number of warnings generated. - -#### Wi-Fi for LPC54018 IoT Module V1.0.1 -- Add fixes for Demo and DHCP. - -#### Wi-Fi STM32L4 Discovery kit IoT node V1.0.2 -- Update for release of AFQP 1.0 - -#### Wi-Fi for CC3220SF-LAUNCHXL V1.0.2 -- Update for release of AFQP 1.0 - ---------------------------------------------------------------------------------------- - -## V1.2.7 05/31/2018 - -- Update the Texas Instruments SimpleLink CC3220SF SDK from version 1.40.01.00 to version 2.10.00.04. -- Fix the MQTT Echo Demo (Hello World Demo) to avoid truncating received strings. -- Modify the Getting Started scripts to check if the AWS CLI is configured. - -#### Secure Sockets for CC3220SF-LAUNCHXL V1.0.4 -- Update comments for SimpleLink CC3220SF SDK version 2.10.00.04. - --------------- - -## V1.2.6 05/18/2018 - -- Fix NXP MCUXpresso project build failure on Linux. - ----------------- - -## V1.2.5 05/14/2018 - -- Add support for Espressif's ESP32-DevKitC and ESP-WROVER-KIT. - -#### FreeRTOS+TCP V2.0.4 - - Add Espressif ESP32 network interface support. - -#### mbedTLS-based PKCS #11 V1.0.3 - - Implement C_DigestInit, C_DigestUpdate, and C_DigestFinal for SHA-256. - - Implement C_GenerateKeyPair for non-persistent ECDSA P256. - -#### PKCS #11 for ESP32-DevKitC ESP-WROVER-KIT V1.0.0 - - Add support for Espressif's ESP32-DevKitC and ESP-WROVER-KIT. - -#### Wi-Fi STM32L4 Discovery kit IoT node V1.0.2 - - Bug fix to ensure that WIFI_ConnectAP() switches to the network parameters input, - even when already connected to a different set. - -#### Wi-Fi for ESP32-DevKitC ESP-WROVER-KIT V1.0.0 - - Add support for Espressif's ESP32-DevKitC and ESP-WROVER-KIT. - ---------------------------------------------------------------------------------------- - -## V1.2.4 05/01/2018 - - - Upgrade to mbedTLS version 2.8. - - Add MCUXpresso IDE demo project for the NXP LPC54018 IoT Module. - -#### Crypto V1.0.2 - - Minor updates due to mbedTLS crypto interface changes. - -#### FreeRTOS+TCP V2.0.3 - - Fix a bug where re-transmission and duplicated TCP packets would create a - computation underflow as well as a memory leak. - - Add new public function FreeRTOS_UpdateMACAddress() to allow changing the MAC address - after FreeRTOS_IPInit. Sometimes the device MAC address is not available at the - time FreeRTOS_IPInit() is called, so it needs to be changed afterward. - - Remove non-cryptographic rand() implementation. - - Remove a static variable in functions prvGetHostByName() and prvCreateDNSSocket() to - make them threadsafe. - -#### Greengrass Discovery V1.0.3 - - Provide a helpful error message if the Greengrass Discovery JSON does not fit in - the supplied buffer. - -#### MQTT Agent V1.1.2 - - Bug fix to avoid socket leak if MQTT Connect fails after a successful TCP - connection. - - Add support for disabling subscription management feature by defining the macro - mqttconfigENABLE_SUBSCRIPTION_MANAGEMENT as 0. - -#### OTA PAL for Curiosity PIC32MZEF V0.9.1 - - Update for PKCS #11 PAL layer API changes. - -#### OTA PAL for Windows Simulator V0.9.2 -- Minor restructuring of file locations. - -#### OTA PAL for CC3220SF-LAUNCHXL V0.9.3 - - Minor changes to enable test integration. - -#### OTA Agent V0.9.4 - - Minor restructuring of file locations. - -#### mbedTLS-based PKCS #11 V1.0.2 - - Combine the mbedTLS based PKCS #11 implementation from Curiosity PIC32MZEF, - LPC54018 IoT Module, Windows Simulator, and STM32L4 Discovery kit IoT node into a - single file. - - Add support for public key verification of signatures. - - Fix to free context structures on session failure. - - Update C_OpenSession to use CKF_SERIAL_SESSION flag. - -#### PKCS #11 for Curiosity PIC32MZEF V1.0.2 - - Create port specific functions for certificate and key access: - PKCS11_PAL_SaveFile(), PKCS11_PAL_ReadFile(), PKCS11_PAL_ReleaseFileData(). - -#### PKCS #11 for LPC54018 IoT Module V1.0.1 - - Create port specific functions for certificate and key access: - PKCS11_PAL_SaveFile(), PKCS11_PAL_ReadFile(), PKCS11_PAL_ReleaseFileData(). - -#### PKCS #11 PAL for Windows Simulator V1.0.2 - - Create port specific functions for certificate and key access: - PKCS11_PAL_SaveFile(), PKCS11_PAL_ReadFile(), PKCS11_PAL_ReleaseFileData(). - -#### PKCS #11 for STM32L4 Discovery kit IoT node V1.0.1 - - Create port specific functions for certificate and key access: - PKCS11_PAL_SaveFile(), PKCS11_PAL_ReadFile(), PKCS11_PAL_ReleaseFileData(). - -#### PKCS #11 for CC3220SF-LAUNCHXL V1.0.2 - - PKCS #11 implementation for TI based on mbedTLS moved into this file. - -#### Secure Socket for FreeRTOS+TCP V1.1.2 - - Combine Secure Sockets implementation for Curiosity PIC32MZEF and Windows - Simulator into a single file. - - Fix return value of SOCKETS_Socket on error. - - Attempting to create an unsupported UDP socket now triggers an assert. - - Add cryptographic random number generator function for TCP sequence numbers. - - Update the Socket structure to keep track of a connection attempt and added - support of the ECONN error. - -#### Secure Sockets for LPC54018 IoT Module V1.0.0 Beta 3 - - Fix minor bug in SOCKETS_Recv(). - -#### Secure Sockets for STM32L4 Discovery kit IoT node V1.0.0 Beta 2 - - Fix return value of SOCKETS_Close on error. - -#### Secure Sockets for CC3220SF-LAUNCHXL V1.0.3 - - Secure sockets printing is now controlled independently using the SOCKETS_PRINT - macro. SOCKETS_PRINT prints TI driver error codes. - -#### Shadow V1.0.3 - - Change names of configuration constants to be consistent with FreeRTOS style. - -#### TLS V1.1.1 - - Support AWS IoT Just-in-Time Registration (JITR) by sending optional - client-issuer certificate. - - Use CKF_SERIAL_SESSION flag with PKCS #11. - -#### Wi-Fi for Curiosity PIC32MZEF V1.0.3 - - Update for setting the MAC Address in WIFI_On() by using new FreeRTOS+TCP - function FreeRTOS_UpdateMACAddress(). - - Redefine printing and assert stubs used in the Wi-Fi driver code. - - Add implementation of WIFI_GetMAC(). - - Add implementation of WIFI_IsConnected(). - - Minor bug fixes. - -#### Wi-Fi for LPC54018 IoT Module V1.0.2 - - Add implementation of WIFI_IsConnected(). - - Fix max DNS name length redefinition. - - Fix compiler errors in MCUXpresso IDE. - - Minor bug fixes. - -#### Wi-Fi STM32L4 Discovery kit IoT node V1.0.1 - - Add implementation of WIFI_IsConnected(). - - Add NULL pointer checks throughout. - - Minor bug fixes. - -#### Wi-Fi for CC3220SF-LAUNCHXL V1.0.2 - - Add implementation of WIFI_IsConnected(). - - Add NULL pointer checks throughout. - - Minor bug fixes. - ---------------------------------------------------------------------------------------- - -## V1.2.3 03/29/2018 - - Fix TI IAR project build failure. - ---------------------------------------------------------------------------------------- - -## V1.2.2 02/27/2018 - -#### OTA Agent V0.9.3 - - Formatting update. - -#### OTA PAL for Curiosity PIC32MZEF V0.9.0 - - Beta release of the OTA Update support for the Microchip Curiosity PIC32MZEF. - -#### PKCS #11 for Curiosity_PIC32MZEF V1.0.1 - - Add support for the management of OTA update code signing keys. - -#### Wi-Fi for Curiosity PIC32MZEF V1.0.1 - - Update to conditionally compile the entire file. - ---------------------------------------------------------------------------------------- - -## V1.2.1 02/23/2018 - - - Add an IAR IDE demo project for the Texas Instruments CC3220SF-LAUNCHXL. - - Add Wi-Fi support for the Microchip Curiosity PIC32MZEF. - -#### FreeRTOS+TCP V2.0.2 - - Improve NULL variable check in buffer management. - -#### MQTT Agent V1.1.1 - - Minor bug fix checking for a NULL pointer. - -#### OTA Agent V0.9.2 - - Update to support NULL OTA file handles. - -#### Amazon FreeRTOS OTA PAL for CC3220SF-LAUNCHXL V0.9.2 - - Update to support NULL OTA file handles. - -#### PKCS #11 for CC3220SF-LAUNCHXL V1.0.1 - - Add a dummy variable to a previously empty structure to fix IAR compiler errors. - -#### Secure Socket for Windows Simulator V1.1.1 - - Formatting update. - -#### Secure Sockets for CC3220SF-LAUNCHXL V1.0.2 - - Update to print SimpleLink driver-specific error codes when debugging. - - Add error handling for non-blocking sockets. - - Update socket option to return an error if security options are specified after - a connection. - -#### Wi-Fi for Curiosity PIC32MZEF V1.0.1 - - Update such that Wi-Fi disconnection waits until the link is down before - returning. - -#### Wi-Fi for CC3220SF-LAUNCHXL V1.0.1 - - Fix error in attempting to overwrite a const memory. - ---------------------------------------------------------------------------------------- - -## V1.2.0 02/06/2018 - -#### Greengrass Discovery V1.0.2 - - Update to send all data until an error is received. - -#### MQTT Agent V1.1.0 - - Add support for ALPN. ALPN allows MQTT traffic to be sent to - the AWS IoT broker over port 443 instead of 8883. - -#### OTA Agent V0.9.1 - - Send a FAILED status from agent when a file too large for the platform - is received. - - Rename some files. - -#### PKCS #11 for Windows Simulator - - Add developer mode key provisioning support. - -#### Secure Socket for Curiosity PIC32MZEF V1.0.1 - - Add support for ALPN. - -#### Secure Socket for Windows Simulator V1.1.0 - - Add support for ALPN. - -#### Secure Sockets for CC3220SF-LAUNCHXL V1.0.1 -- Remove unnecessary server certificate storage on the client side. -- Remove unnecessary global synchronization semaphore. -- Update for other small bugs. - -#### Shadow V1.0.2 -- Fix error handling bugs. -- Require client tokens. -- Update for other small bugs. - -#### TLS V1.1.0 -- Add support for ALPN. - ---------------------------------------- - -## V1.1.0 12/20/2017 - -#### Crypto V1.0.1 -- Fix compiler warning for the Microchip Curiosity PIC32MZEF. - -#### FreeRTOS+TCP V2.0.1 -- Add support for the Microchip Curiosity PIC32MZEF. - -#### FreeRTOS Kernel V10.0.1 -- Minor bug fixes to allow Linux and C++ builds. - -#### Greengrass Discovery V1.0.1 -- Reformat console display messages in order to better facilitate demos and debugging. - -#### MQTT Agent V1.0.1 -- The MQTT Agent now processes commands between successive socket reads to enable faster command handling, especially when the connected socket is receiving data continuously. - -#### OTA Agent V0.9.0 -- Beta release of OTA Update library for Amazon FreeRTOS. Includes support for the Texas Instruments CC3220SF-LAUNCHXL and Windows Simulator. - -#### PKCS #11 for Curiosity PIC32MZEF V1.0.0 Beta 1 -- Add support for the Microchip Curiosity PIC32MZEF. - -#### Secure Socket for Curiosity PIC32MZEF V1.0.0 -- Add support for the Microchip Curiosity PIC32MZEF. - -#### Secure Sockets for LPC54018 IoT Module V1.0.0 Beta 2 -- Fix bugs in the Secure Sockets implementation for the NXP LPC54018 IoT Module. - -#### Shadow V1.0.1 -- Fix compiler warning for the Microchip Curiosity PIC32MZEF. - -#### Wi-Fi for LPC54018 IoT Module V1.0.1 -- Change the Wi-Fi Connection timeout to 10 seconds. diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/CMakeLists.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/CMakeLists.txt deleted file mode 100644 index 202ca4e..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/CMakeLists.txt +++ /dev/null @@ -1,131 +0,0 @@ -cmake_minimum_required(VERSION 3.13) - -# Disable in-source build. -if("${CMAKE_SOURCE_DIR}" STREQUAL "${CMAKE_BINARY_DIR}") - message(FATAL_ERROR "In-source build is not allowed, please use a separate build folder.") -endif() - -project(amazon-freertos) -set(PROJECT_VERSION "201908.00") -set(PROJECT_VERSION_MAJOR "201908") -set(PROJECT_VERSION_MINOR "00") - -# Import global configurations. -include("tools/cmake/afr.cmake") - -# Add 3rdparty modules. -add_subdirectory("libraries/3rdparty") - -# ------------------------------------------------------------------------------------------------- -# Configure target board -# ------------------------------------------------------------------------------------------------- -# Get list of supported boards. -afr_get_boards(AFR_SUPPORTED_BOARDS) - -set(AFR_BOARD "vendor.board" CACHE STRING "Target board chosen by the user at configure time") -set_property(CACHE AFR_BOARD PROPERTY STRINGS ${AFR_SUPPORTED_BOARDS}) - -string(REGEX MATCH [[(.+)\.(.+)]] __match_result ${AFR_BOARD}) -set(AFR_VENDOR_NAME ${CMAKE_MATCH_1} CACHE INTERNAL "MCU vendor name") -set(AFR_BOARD_NAME ${CMAKE_MATCH_2} CACHE INTERNAL "MCU board name") - -# Abort if the target board is not supported, i.e., corresponding folder is not present. -if(NOT AFR_BOARD IN_LIST AFR_SUPPORTED_BOARDS) - message(FATAL_ERROR "Board is not supported: ${AFR_BOARD}") -endif() - -# Import board CMake build. -set(AFR_VENDOR_PATH "vendors/${AFR_VENDOR_NAME}" CACHE INTERNAL "") -include("${AFR_VENDOR_PATH}/manifest.cmake") -if(DEFINED AFR_MANIFEST_BOARD_DIR_${AFR_BOARD_NAME}) - set(AFR_BOARD_PATH "${AFR_VENDOR_PATH}/${AFR_MANIFEST_BOARD_DIR_${AFR_BOARD_NAME}}" CACHE INTERNAL "") -elseif(DEFINED AFR_MANIFEST_BOARD_DIR) - set(AFR_BOARD_PATH "${AFR_VENDOR_PATH}/${AFR_MANIFEST_BOARD_DIR}/${AFR_BOARD_NAME}" CACHE INTERNAL "") -else() - message(FATAL_ERROR "Could not import board CMakeLists.txt.") -endif() -add_subdirectory("${AFR_BOARD_PATH}") - -# ------------------------------------------------------------------------------------------------- -# Amazon FreeRTOS modules -# ------------------------------------------------------------------------------------------------- -# Initialize all modules. -add_subdirectory("libraries") -add_subdirectory("demos") -add_subdirectory("tests") - -# Resolve dependencies. -afr_status("=========================Resolving dependencies==========================") -afr_resolve_dependencies() - -# ------------------------------------------------------------------------------------------------- -# Summary -# ------------------------------------------------------------------------------------------------- -afr_status("") -afr_status("====================Configuration for Amazon FreeRTOS====================") -afr_status(" Version: " "${AFR_VERSION}") -afr_status(" Git version: " "${AFR_VERSION_VCS}") - -# ================ Target microcontroller ================= -afr_status("") -afr_status("Target microcontroller:") - -afr_get_board_metadata(vendor_name VENDOR_NAME) -afr_get_board_metadata(board_name DISPLAY_NAME) -afr_get_board_metadata(description DESCRIPTION) -afr_get_board_metadata(family FAMILY_NAME) -afr_get_board_metadata(data_ram DATA_RAM_MEMORY) -afr_get_board_metadata(program_mem PROGRAM_MEMORY) - -afr_status(" vendor: " "${vendor_name}") -afr_status(" board: " "${board_name}") -afr_status(" description: " "${description}") -afr_status(" family: " "${family}") -afr_status(" data ram size: " "${data_ram}") -afr_status(" program memory size: " "${program_mem}") - -# ===================== Host platform ===================== -afr_status("") -afr_status("Host platform:") - -afr_status(" OS: " "${CMAKE_HOST_SYSTEM}") -afr_status(" Toolchain: " "${AFR_TOOLCHAIN}") -afr_status(" Toolchain path: " "${CMAKE_FIND_ROOT_PATH}") -afr_status(" CMake generator: " "${CMAKE_GENERATOR}") - -# ================ Amazon FreeRTOS modules ================ -afr_status("") -afr_status("Amazon FreeRTOS modules:") - -afr_status(" Modules to build: " "${AFR_MODULES_BUILD}") -afr_status(" Enabled by user: " "${AFR_MODULES_ENABLED_USER}") -afr_status(" Enabled by dependency: " "${AFR_MODULES_ENABLED_DEPS}") -afr_status(" 3rdparty dependencies: " "${3RDPARTY_MODULES_ENABLED}") -afr_status(" Available demos: " "${AFR_DEMOS_ENABLED}") -afr_status(" Available tests: " "${AFR_TESTS_ENABLED}") - -afr_status("=========================================================================") -afr_status("") - -# ------------------------------------------------------------------------------------------------- -# Demos and tests -# ------------------------------------------------------------------------------------------------- -# Enable us to use targets defined in vendor CMake files. -cmake_policy(SET CMP0079 NEW) - -if(TARGET aws_demos) - list(TRANSFORM AFR_DEMOS_ENABLED PREPEND "AFR::" OUTPUT_VARIABLE demos_list) - target_link_libraries(aws_demos PRIVATE ${demos_list}) -endif() - -if(TARGET aws_tests) - list(TRANSFORM AFR_TESTS_ENABLED PREPEND "AFR::" OUTPUT_VARIABLE tests_list) - target_link_libraries(aws_tests PRIVATE ${tests_list}) -endif() - -# ------------------------------------------------------------------------------------------------- -# Output metadata information -# ------------------------------------------------------------------------------------------------- -if(AFR_METADATA_MODE) - afr_write_metadata() -endif() diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/CODE_OF_CONDUCT.md b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/CODE_OF_CONDUCT.md deleted file mode 100644 index 2e2a43e..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/CODE_OF_CONDUCT.md +++ /dev/null @@ -1,4 +0,0 @@ -## Code of Conduct -This project has adopted the [Amazon Open Source Code of Conduct](https://aws.github.io/code-of-conduct). -For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or contact -opensource-codeofconduct@amazon.com with any additional questions or comments. \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/CONTRIBUTING.md b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/CONTRIBUTING.md deleted file mode 100644 index e3f253f..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/CONTRIBUTING.md +++ /dev/null @@ -1,66 +0,0 @@ -# Contributing Guidelines - -Thank you for your interest in contributing to our project. Whether it's a bug report, new feature, correction, or additional -documentation, we greatly value feedback and contributions from our community. - -Please read through this document before submitting any issues or pull requests to ensure we have all the necessary -information to effectively respond to your bug report or contribution. - - -## Reporting Bugs/Feature Requests - -We welcome you to use the GitHub issue tracker to report bugs or suggest features. - -When filing an issue, please check existing open, or recently closed, issues to make sure somebody else hasn't already -reported the issue. Please try to include as much information as you can. Details like these are incredibly useful: - -* A reproducible test case or series of steps -* The version of our code being used -* Any modifications you've made relevant to the bug -* Anything unusual about your environment or deployment - - -## Contributing via Pull Requests -Contributions via pull requests are much appreciated. Before sending us a pull request, please ensure that: - -1. You are working against the latest source on the *master* branch. -2. You check existing open, and recently merged, pull requests to make sure someone else hasn't addressed the problem already. -3. You open an issue to discuss any significant work - we would hate for your time to be wasted. - -To send us a pull request, please: - -1. Ensure you are considering a change to AWS source code (FreeRTOS kernel, AWS libraries). Proposed changes to 3rd party code should be submitted instead to the 3rd party. -2. Fork the repository. -3. Modify the source; please focus on the specific change you are contributing. If you also reformat all the code, it will be hard for us to focus on your change. -4. Ensure local tests pass. -5. Commit to your fork using clear commit messages. -6. Send us a pull request, answering any default questions in the pull request interface. - NOTE: Please make sure the default option (Allow edits from maintainers) is left checked. -7. Pay attention to any automated CI failures reported in the pull request, and stay involved in the conversation. - -GitHub provides additional document on [forking a repository](https://help.github.com/articles/fork-a-repo/) and -[creating a pull request](https://help.github.com/articles/creating-a-pull-request/). - -## Getting Your Pull Request Merged -All Pull Requests must be approved by our review team before it can be merged in. We appreciate your patience while pull requests are reviewed as the time taken will depend on its complexity and wider implications. - - -## Finding contributions to work on -Looking at the existing issues is a great way to find something to contribute on. As our projects, by default, use the default GitHub issue labels (enhancement/bug/duplicate/help wanted/invalid/question/wontfix), looking at any 'help wanted' issues is a great place to start. - - -## Code of Conduct -This project has adopted the [Amazon Open Source Code of Conduct](https://aws.github.io/code-of-conduct). -For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or contact -opensource-codeofconduct@amazon.com with any additional questions or comments. - - -## Security issue notifications -If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security via our [vulnerability reporting page](http://aws.amazon.com/security/vulnerability-reporting/). Please do **not** create a public github issue. - - -## Licensing - -See the LICENSE file for our project's licensing. We will ask you to confirm the licensing of your contribution. - -We may ask you to sign a [Contributor License Agreement (CLA)](http://en.wikipedia.org/wiki/Contributor_License_Agreement) for larger changes. diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/ChangeLogKSDK.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/ChangeLogKSDK.txt deleted file mode 100644 index 2471dfb..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/ChangeLogKSDK.txt +++ /dev/null @@ -1,89 +0,0 @@ -/** -@page rtos_log RTOS Change Log - -@section FreeRTOS FreeRTOS for MCUXpresso SDK. -The current version is Amazon-FreeRTOS 201908.00 Original package is available at github.com/aws/amazon-freertos. - - - 201908.00_rev0 - - update amazon freertos version - - Fix freertos_tasks_c_additions.h - fix IAR build fail - - update queue.c - add definition for pvBuffer necessary for segger sysview - - iot_crypto.c - change include file to be possible include mbedtls config file defined by MBEDTLS_CONFIG_FILE macro - - iot_mqtt_agent.h - extend MQTTAgentConnectParams_t structure - required by se_hostlib examples - - Fixed build warnings: - - aws_dev_mode_key_provisioning.c - some variables were declared but never referenced - - aws_iot_network_manager.c - some functions were declared but never referenced - - iot_device_metrics.c - add include - - iot_pkcs11_mbedtls.c - incompatible pointer type, unused variable - - - 1.4.9_rev0 - - Remove 3rd party libraries lwip, mbedtls (use MCUXpresso SDK versions). - - Add missing comments to heap_useNewlib.c. - - - 1.4.7_rev0 - - New features: - - Add optional allocation scheme heap_useNewlib.c by D. Nadler. - - Enable task aware debugging for cm33 platforms - - Move tickless implementation to application layer - - Other changes: - - Fix other build warnings, errors - - - 1.4.6_rev0 - - New features: - - Update support of CM33 port with Trustzone, MPU, FPU support - - Add support for AWS test for Cypress WiFi - - Use lwip netif api to avoid lwIP raw API calls outside of tcpip thread in aws_wifi.c - - Other changes: - - Fix issues with mflash driver - - Fix other build warnings, errors - - - 1.4.0_rev1 - - New features: - - Add implementation of vTaskEndScheduler for CM0 GCC port. - - Support for CM33, CM33F architectures based on CM3, CM4F ports - - - 1.4.0_rev0 - - New features: - - Support for pkcs11 for several platforms, secure element host library under pkcs11/portable/nxp folder - - Lwip, wifi_qca support for secure_sockets in secure_sockets/portable/nxp folder - - Flash driver support for several platforms in third_party/mcu_vendor/nxp folder - - Generic support for aws_wifi under wifi/portable/nxp/common folder - - Other changes: - - Fix several build warnings, errors - -Updates applied to FreeRTOS kernel up to version 10.0.0 (up to Amazon - FreeRTOS merge). -New kernel related changes will be described in section above as part of AWS package. - - - 9.0.0_rev3 - - New features: - - Tickless idle mode support for Cortex-A7. Add fsl_tickless_epit.c and fsl_tickless_generic.h in portable/IAR/ARM_CA9 folder. - - Enabled float context saving in IAR for Cortex-A7. Added configUSE_TASK_FPU_SUPPORT macros. Modified port.c and portmacro.h in portable/IAR/ARM_CA9 folder. - - Other changes: - - Transformed ARM_CM core specific tickless low power support into generic form under freertos/Source/portable/low_power_tickless/. - - - 9.0.0_rev2 - - New features: - - Enabled MCUXpresso thread aware debugging. Add freertos_tasks_c_additions.h and configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H and configFRTOS_MEMORY_SCHEME macros. - - - 9.0.0_rev1 - - New features: - - Enabled -flto optimization in GCC by adding __attribute__((used)) for vTaskSwitchContext. - - Enabled KDS Task Aware Debugger. Apply FreeRTOS patch to enable configRECORD_STACK_HIGH_ADDRESS macro. Modified files are task.c and FreeRTOS.h. - - - 9.0.0_rev0 - - New features: - - Example freertos_sem_static. - - Static allocation support RTOS driver wrappers. - - Other changes: - - Tickless idle rework. Support for different timers is in separated files (fsl_tickless_systick.c, fsl_tickless_lptmr.c). - - Removed configuration option configSYSTICK_USE_LOW_POWER_TIMER. Low power timer is now selected by linking of apropriate file fsl_tickless_lptmr.c. - - Removed configOVERRIDE_DEFAULT_TICK_CONFIGURATION in RVDS port. Use of __attribute__((weak)) is the preferred solution. Not same as _weak! - - - 8.2.3 - - New features: - - Tickless idle mode support. - - Added template application for Kinetis Expert (KEx) tool (template_application). - - Other changes: - - Folder structure reduction. Keep only Kinetis related parts. - -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/LICENSE b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/LICENSE deleted file mode 100644 index dff8fc7..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/LICENSE +++ /dev/null @@ -1,21 +0,0 @@ -MIT License - -Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/PreLoad.cmake b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/PreLoad.cmake deleted file mode 100644 index 5ae9b96..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/PreLoad.cmake +++ /dev/null @@ -1,58 +0,0 @@ -# Set your compiler path here if it's not in the PATH environment variable. -set(AFR_TOOLCHAIN_PATH "" CACHE INTERNAL "") - -# If VENDOR or BOARD is specified, try to find a match. -if(DEFINED VENDOR OR DEFINED BOARD) - include("${CMAKE_CURRENT_LIST_DIR}/tools/cmake/afr_utils.cmake") - - set(matched_boards) - afr_get_boards(all_boards) - foreach(board IN LISTS all_boards) - string(REGEX MATCH "${VENDOR}.*\\.${BOARD}.*" match "${board}") - if(match) - list(APPEND matched_boards "${match}") - endif() - endforeach() - - list(LENGTH matched_boards size) - if(size EQUAL 0) - message(FATAL_ERROR "No matching board found, please check your VENDOR and BOARD value.") - endif() - if(NOT size EQUAL 1) - list(JOIN matched_boards ", " matched_boards) - message(FATAL_ERROR "Multiple matching boards found: ${matched_boards}") - else() - set(AFR_BOARD "${matched_boards}" CACHE INTERNAL "") - endif() -endif() - -# If COMPILER is specified, set toolchain file to ${COMPILER}.cmake. -if(DEFINED COMPILER) - if(DEFINED CMAKE_TOOLCHAIN_FILE) - get_filename_component(toolchain "${CMAKE_TOOLCHAIN_FILE}" NAME_WE) - if(NOT "${COMPILER}" STREQUAL "${toolchain}") - message(WARNING "CMAKE_TOOLCHAIN_FILE is already defined to ${toolchain}.cmake, you\ - need to delete cache and reconfigure if you want to switch compiler.") - endif() - else() - set(toolchain_dir "${CMAKE_CURRENT_LIST_DIR}/tools/cmake/toolchains") - set(toolchain_file "${toolchain_dir}/${COMPILER}.cmake") - if(EXISTS "${toolchain_file}") - set(CMAKE_TOOLCHAIN_FILE "${toolchain_file}" CACHE INTERNAL "") - else() - message(FATAL_ERROR "Toolchain file \"${COMPILER}.cmake\" does not exist, please\ - select one from \"cmake/toolchains\" folder.") - endif() - endif() -endif() - -# Disable compiler checks when only outputing metadata. -if(AFR_METADATA_MODE) - set(CMAKE_C_COMPILER_FORCED TRUE CACHE INTERNAL "") - set(CMAKE_CXX_COMPILER_FORCED TRUE CACHE INTERNAL "") -endif() - -# Remove these helper variables from CMake cache. -unset(VENDOR CACHE) -unset(BOARD CACHE) -unset(COMPILER CACHE) diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/README.md b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/README.md deleted file mode 100644 index af87687..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/README.md +++ /dev/null @@ -1,59 +0,0 @@ -## Getting Started - -For more information on Amazon FreeRTOS, refer to the [Getting Started section of Amazon FreeRTOS webpage](https://aws.amazon.com/freertos). - -To directly access the **Getting Started Guide** for supported hardware platforms, click the corresponding link in the Supported Hardware section below. - -For detailed documentation on Amazon FreeRTOS, refer to the [Amazon FreeRTOS User Guide](https://aws.amazon.com/documentation/freertos). - -## Supported Hardware - -The following MCU boards are supported for Amazon FreeRTOS: -1. **Texas Instruments** - [CC3220SF-LAUNCHXL](http://www.ti.com/tool/cc3220sf-launchxl). - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_ti.html) - * IDEs: [Code Composer Studio](http://www.ti.com/tools-software/ccs.html), [IAR Embedded Workbench](https://www.iar.com/iar-embedded-workbench/partners/texas-instruments) -2. **STMicroelectronics** - [STM32L4 Discovery kit IoT node](http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html). - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_st.html) - * IDE: [STM32 System Workbench](http://openstm32.org/HomePage) -3. **NXP** - [LPC54018 IoT Module](http://www.nxp.com/LPC-AWS-Module). - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_nxp.html) - * IDEs: [IAR Embedded Workbench](https://www.iar.com/iar-embedded-workbench/partners/nxp), [MCUXpresso IDE](https://www.nxp.com/mcuxpresso/ide/download) -4. **Microchip** - [Curiosity PIC32MZEF](http://www.microchipdirect.com/product/search/all/dm320104-BNDL). - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_mch.html) - * IDE: [MPLAB X IDE](http://www.microchip.com/mplab/mplab-x-ide) -5. **Espressif** - [ESP32-DevKitC](https://www.espressif.com/en/products/hardware/esp32-devkitc/overview), [ESP-WROVER-KIT](https://www.espressif.com/en/products/hardware/esp-wrover-kit/overview). - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_espressif.html) -6. **Infineon** - [Infineon XMC4800 IoT Connectivity Kit](https://www.infineon.com/connectivitykit) - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_infineon.html) - * IDE: [DAVE](https://infineoncommunity.com/dave-download_ID645) -7. **Xilinx** - [Xilinx Zynq-7000 based MicroZed Industrial IoT Bundle](http://www.zedboard.org/product/microzed-iiot-bundle-afreertos) - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_xilinx.html) - * IDE: [Xilinx SDK](https://www.xilinx.com/products/design-tools/embedded-software/sdk.html) -8. **MediaTek** - [MediaTek MT7697Hx Development Kit](https://www.mediatek.com/products/smartHome/mt7697h) - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_mediatek.html) - * IDE: [Keil uVision](http://www2.keil.com/mdk5/install/) -9. **Renesas** - [Renesas Starter Kit+ for RX65N-2MB](https://www.renesas.com/us/en/products/software-tools/boards-and-kits/renesas-starter-kits/renesas-starter-kitplus-for-rx65n-2mb.html) - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_renesas.html) - * IDE: [e2 studio](https://www.renesas.com/us/en/products/software-tools/tools/ide/e2studio.html) -10. **Cypress CYW54907** - [Cypress CYW954907AEVAL1F Evaluation Kit](https://www.cypress.com/documentation/development-kitsboards/cyw954907aeval1f-evaluation-kit) - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_cypress_54.html) - * IDE: [WICED Studio](https://community.cypress.com/community/wiced-wifi) -11. **Cypress CYW43907** - [Cypress CYW943907AEVAL1F Evaluation Kit](https://www.cypress.com/documentation/development-kitsboards/cyw943907aeval1f-evaluation-kit) - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_cypress_43.html) - * IDE: [WICED Studio](https://community.cypress.com/community/wiced-wifi) -12. **Marvell MW320** - [Marvell MW320 AWS IoT Starter Kit](https://www.marvell.com/microcontrollers/aws-iot-starter-kit/) - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_marvell320.html) -13. **Marvell MW322** - [Marvell MW322 AWS IoT Starter Kit](https://www.marvell.com/microcontrollers/aws-iot-starter-kit/) - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_marvell322.html) -14. **Nordic nRF52840 DK** - [nRF52840 DK Development kit](https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK/) - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_nordic.html) -15. **Nuvoton** - [NuMaker-IoT-M487](https://direct.nuvoton.com/en/numaker-iot-m487) - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting-started-nuvoton-m487.html) -16. **Windows Simulator** - To evaluate Amazon FreeRTOS without using MCU-based hardware, you can use the Windows Simulator. - * Requirements: Microsoft Windows 7 or newer, with at least a dual core and a hard-wired Ethernet connection - * [Getting Started Guide](https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_windows.html) - * IDE: [Visual Studio Community Edition](https://www.visualstudio.com/downloads/) - - -## amazon-freeRTOS/projects -The ```./projects``` folder contains the IDE test and demo projects for each vendor and their boards. The majority of boards can be built with both IDE and cmake (there are some exceptions!). Please refer to the Getting Started Guides above for board specific instructions. diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/checksums.json b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/checksums.json deleted file mode 100644 index 24ad268..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/checksums.json +++ /dev/null @@ -1,1189 +0,0 @@ -{ - "demos/CMakeLists.txt": "77fb17881347537adc58e7c88feb80459781758d5c24c61ae70b67246f84f741", - "demos/README.md": "3986f2712054d81e89b81b900a4d8a0d9e33b161f930453c68b28e086e64386f", - "demos/ble/CMakeLists.txt": "f7fed40866933cf3adf7d518b252b5b362d7155b4b776bd31402cfb14764950f", - "demos/ble/README.md": "74470be4344309d26227c7bd63f21e63d41a3a9dd61db6c255364b96d52cf802", - "demos/ble/aws_ble_gatt_server_demo.c": "4d9c78857c82ac367d2b60b533e6c6ce2274566984c26278eaa25a2f08d98249", - "demos/ble/iot_ble_numericComparison.c": "abaadf4737fc532dde892d684cfd439c0c0efa412e988bab81fec6b05bd221ca", - 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-doc: -Contains Doxygen configuration, and board qualification guide. - -freertos_kernel: -Contains FreeRTOS kernel distribution. - -libraries: -Contains standard libraries, AWS libraries, and third-party libraries. - -projects: -Contains IDE project files. - -tests: -Contains Unity framework and test runner. - -vendors: -Contains platform-specific ports, SDKs, and tools. \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/AFQ Developer Guide - Board Qualification Errata.pdf b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/AFQ Developer Guide - Board Qualification Errata.pdf deleted file mode 100644 index 5321f1e..0000000 Binary files a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/AFQ Developer Guide - Board Qualification Errata.pdf and /dev/null differ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/Amazon FreeRTOS Qualification Developer Guide.pdf b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/Amazon FreeRTOS Qualification Developer Guide.pdf deleted file mode 100644 index 18ea53a..0000000 Binary files a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/Amazon FreeRTOS Qualification Developer Guide.pdf and /dev/null differ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/README.md b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/README.md deleted file mode 100644 index cd75f5f..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# Documentation - -The API documentation for Amazon FreeRTOS is available [here](https://docs.aws.amazon.com/freertos/latest/lib-ref/index.html). - -Documentation for the AWS IoT Embedded C SDK, which is used with Amazon FreeRTOS, is available [here](https://docs.aws.amazon.com/freertos/latest/lib-ref/html3/main/index.html). - -For instructions on generating the documentation, see [guidance.md](guidance.md). diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/atomic b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/atomic deleted file mode 100644 index aec9562..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/atomic +++ /dev/null @@ -1,29 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "Atomics" - -# Library documentation output directory. -HTML_OUTPUT = atomic - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/atomic.tag - -# Directories containing library source code. -INPUT = doc \ - doc/lib \ - libraries/c_sdk/standard/common/include \ - freertos_kernel/include - -# Library file names. -FILE_PATTERNS = *atomic*.h *atomic*.c *atomic*.txt - -EXAMPLE_PATH = libraries/c_sdk/standard/common/include/iot_atomic.h - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main \ - -# Excluded symbols -EXCLUDE_SYMBOLS = ATOMIC_ENTER_CRITICAL ATOMIC_EXIT_CRITICAL portFORCE_INLINE diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/ble b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/ble deleted file mode 100644 index edf9631..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/ble +++ /dev/null @@ -1,29 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "BLE" -PROJECT_BRIEF = "BLE" - -# Library documentation output directory. -HTML_OUTPUT = ble - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/ble.tag - -# Directories containing library source code. -INPUT = doc \ - doc/lib \ - libraries/c_sdk/standard/ble/include \ - libraries/abstractions/ble_hal/include - -# Library file names. -FILE_PATTERNS = *ble*.c *ble*.h *ble*.txt - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main \ - doc/tag/linear_containers.tag=../linear_containers \ - doc/tag/logging.tag=../logging \ - doc/tag/platform.tag=../platform \ - doc/tag/static_memory.tag=../static_memory \ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/common b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/common deleted file mode 100644 index f69ed0e..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/common +++ /dev/null @@ -1,130 +0,0 @@ -# SDK version. -PROJECT_NUMBER = "4.0.0b1" - -# Doxygen layout file for libraries. -LAYOUT_FILE = doc/config/layout_library.xml - -# Documentation output directory. -OUTPUT_DIRECTORY = doc/output/ - -# Don't generate LaTeX documentation -GENERATE_LATEX = NO - -# Directories containing images. -IMAGE_PATH = doc/plantuml/images - -# Don't rearrange members in the input files. -SORT_MEMBER_DOCS = NO - -# Silence output (warnings only). -QUIET = YES - -# Define the following preprocessor constants when generating documentation. -PREDEFINED = "DOXYGEN=1" \ - "IOT_STATIC_MEMORY_ONLY=1" \ - "_LIBRARY_LOG_LEVEL=IOT_LOG_DEBUG" \ - "_LIBRARY_LOG_NAME=\"DOXYGEN\"" - -# Ignore the constants used for setting log levels and names. -EXCLUDE_SYMBOLS = "_LIBRARY_LOG_*" - -# Configure Doxygen for C. -OPTIMIZE_OUTPUT_FOR_C = YES -TYPEDEF_HIDES_STRUCT = YES -EXTRACT_STATIC = YES - -# Disable the tab bar and use treeview instead. -DISABLE_INDEX = YES -GENERATE_TREEVIEW = YES - -# All files should have unique names, so showing the full path is unnecessary. -FULL_PATH_NAMES = NO - -# Disable the default Doxygen diagrams. -HAVE_DOT = NO - -# Disable the default Doxygen search engine (for now). -SEARCHENGINE = NO - -# Use custom header file, footer file, and stylesheet. -HTML_HEADER = doc/config/html/header.html -HTML_FOOTER = doc/config/html/footer.html -HTML_EXTRA_STYLESHEET = doc/config/html/style.css - -# Don't show external pages or groups. -EXTERNAL_GROUPS = NO -EXTERNAL_PAGES = NO - -# Enable expansion of Unity test macros. -ENABLE_PREPROCESSING = YES -MACRO_EXPANSION = YES -EXPAND_ONLY_PREDEF = YES - -# Expand the TEST macro, but ignore the _run functions generated from macro expansion. -EXPAND_AS_DEFINED = TEST -EXCLUDE_SYMBOLS += "TEST_*_run" - -# Alias for starting a dependencies section. -ALIASES += dependencies_section{1}="@section \1_dependencies Dependencies" -ALIASES += dependencies_brief{1}="@brief Dependencies of the \1." - -# Alias for starting a configuration settings page. -ALIASES += describeconfig="Configuration settings are C pre-processor constants. They can be set with a @c #`define` in the iot_config.h or by using a compiler option such as `-D` in gcc. If a configuration setting is not defined, the library will use a \"sensible\" default value (unless otherwise noted). Because they are compile-time constants, a library must be rebuilt if a configuration setting is changed." - -ALIASES += config_page{1}="@page \1_config Configuration" -ALIASES += config_page{2}="@page \1_config \2 Configuration" - -ALIASES += config_brief{1}="@brief Configuration settings of the \1.
@describeconfig @par configpagemarker" -ALIASES += config_brief{3}="@brief Configuration settings of the \2.
@describeconfig

The settings on this page only affect the [\2](@ref \1). In addition to the settings on this page, the \2 will also be affected by [settings that affect all \3](@ref global_\3_config).@par configpagemarker" - -# Aliases for "Possible values", "Recommended values", and "Default values" -# used in configuration setting pages. -ALIASES += configpossible="Possible values: " -ALIASES += configrecommended="Recommended values: " -ALIASES += configdefault="Default value (if undefined): " - -# Alias for starting a constants page. -ALIASES += constants_page{1}="@page \1_constants Constants" -ALIASES += constants_brief{1}="@brief Defined constants of the \1.

Libraries may @c #`define` constants in their headers with special meanings. This page describes the meanings and uses of any constants defined by the \1. Related constants are shown in a single section on this page.
" - -# Alias for starting a functions page. -ALIASES += functions_page{2}="@page \1_functions Functions" -ALIASES += functions_brief{1}="@brief Functions of the \1 library.

The \1 library consists of the following functions." - -# Alias for listing a single function on a functions page. -ALIASES += function_name{1}="@subpage \1" -ALIASES += function_brief{1}="
@copybrief \1" - -# Alias for creating a page for a single function. -ALIASES += function_page{3}="@page \2_function_\3 \1" -ALIASES += function_snippet{3}="@snippet \3 declare_\1_\2" - -# Alias for starting a handles group. -ALIASES += handles_group{1}="@defgroup \1_datatypes_handles Handles" -ALIASES += handles_brief{1}="@brief Opaque handles of the \1." - -# Alias for starting an enum group. -ALIASES += enums_group{1}="@defgroup \1_datatypes_enums Enumerated types" -ALIASES += enums_brief{1}="@brief Enumerated types of the \1." - -# Alias for starting a function pointers group. -ALIASES += functionpointers_group{1}="@defgroup \1_datatypes_functionpointers Function pointer types" -ALIASES += functionpointers_brief{1}="@brief Function pointer types of the \1." - -# Alias for starting a structs group. -ALIASES += structs_group{1}="@defgroup \1_datatypes_structs Structured types" -ALIASES += structs_brief{1}="@brief Structured types of the \1." - -# Alias for starting a parameter structures group. -ALIASES += paramstructs_group{1}="@defgroup \1_datatypes_paramstructs Parameter structures" -ALIASES += paramstructs_brief{2}="@brief Structures passed as parameters to [\2 functions](@ref \1_functions)
These structures are passed as parameters to library functions. Documentation for these structures will state the functions associated with each parameter structure and the purpose of each member." - -# Alias for starting a return structures group. -ALIASES += returnstructs_group{1}="@defgroup \1_datatypes_returnstructs Return structures" -ALIASES += returnstructs_brief{1}="@brief Structures returned from [\1 functions](@ref \1_functions)
These structures are returned from library functions. Documentation for these structures will state the functions associated with each parameter structure and the purpose of each member." - -# Alias for "Parameter for". -ALIASES += paramfor="Parameter for: " - -# Alias for parameter structure initializers. -ALIASES += initializer{2}="All instances of #\1 should be initialized with #\2.
" diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/defender b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/defender deleted file mode 100644 index 13a46b6..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/defender +++ /dev/null @@ -1,31 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "Defender" -PROJECT_BRIEF = "AWS IoT Device Defender library" - -# Library documentation output directory. -HTML_OUTPUT = defender - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/defender.tag - -# Directories containing library source code. -INPUT = doc/lib \ - libraries/c_sdk/aws/defender/include \ - libraries/c_sdk/aws/defender/src \ - libraries/c_sdk/aws/defender/src/private - - -# Library file names. -FILE_PATTERNS = *defender*.h *defender*.c *defender*.txt - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main \ - doc/tag/mqtt.tag=../mqtt \ - doc/tag/logging.tag=../logging \ - doc/tag/static_memory.tag=../static_memory \ - doc/tag/platform.tag=../platform \ - doc/tag/linear_containers.tag=../linear_containers diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/html/footer.html b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/html/footer.html deleted file mode 100644 index 8f8932a..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/html/footer.html +++ /dev/null @@ -1,35 +0,0 @@ - - - -

- - - -
-
- - $generatedby   - doxygen - $doxygenversion - -
- - - - \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/html/header.html b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/html/header.html deleted file mode 100644 index 74e3383..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/html/header.html +++ /dev/null @@ -1,88 +0,0 @@ - - - - - - - - - - - - - - $projectname: $title - - - - - $title - - - - - - $search - $mathjax - - $extrastylesheet - - - -
- - -
- - - - - - - - - - - - - - - - - - - - - - - - -
-
- Amazon FreeRTOS: - $projectname -
- -
- $projectbrief -
- - 		-
- $projectbrief -
- 		- $searchbox -
- Return to main page ↑ -
-
- -$treeview - - - \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/html/style.css b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/html/style.css deleted file mode 100644 index a44efee..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/html/style.css +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Stylesheet for Doxygen HTML output. - * - * This file defines styles for custom elements in the header/footer and - * overrides some of the default Doxygen styles. - * - * Styles in this file do not affect the treeview sidebar. - */ - -/* Set the margins to place a small amount of whitespace on the left and right - * side of the page. */ -div.contents { - margin-left:4em; - margin-right:4em; -} - -/* Justify text in paragraphs. */ -p { - text-align: justify; -} - -/* Style of section headings. */ -h1 { - border-bottom: 1px solid #879ECB; - color: #354C7B; - font-size: 160%; - font-weight: normal; - padding-bottom: 4px; - padding-top: 8px; -} - -/* Style of the prefix "AWS IoT Device SDK C" that appears in the header. */ -#afrprefix { - color: #757575; -} - -/* Style of the "Return to main page" link that appears in the header. */ -#returntomain { - padding: 0.5em; -} - -/* Style of configuration setting names. */ -dl.section.user ~ h1 { - border-bottom: none; - color: #000000; - font-family: monospace, fixed; - font-size: 16px; - margin-bottom: 0px; - margin-left: 2em; - margin-top: 1.5em; -} - -/* Style of paragraphs on a configuration settings page. */ -dl.section.user ~ * { - margin-bottom: 10px; - margin-left: 4em; - margin-right: 4em; - margin-top: 0px; -} - -/* Hide the configuration setting marker. */ -dl.section.user { - display: none; -} - -/* Overrides for code fragments and lines. */ -div.fragment { - background: #ffffff; - border: none; - padding: 5px; -} - -div.line { - color: #3a3a3a; -} - -/* Overrides for code syntax highlighting colors. */ -span.comment { - color: #008000; -} - -span.keyword, span.keywordtype, span.keywordflow { - color: #0000ff; -} - -span.preprocessor { - color: #50015a; -} - -span.stringliteral, span.charliteral { - color: #800c0c; -} - -a.code, a.code:visited, a.line, a.line:visited { - color: #496194; -} \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/https b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/https deleted file mode 100644 index b884afd..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/https +++ /dev/null @@ -1,33 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "HTTPS Client" -PROJECT_BRIEF = "HTTPS Client v1.0.0 library" - -# Library documentation output directory. -HTML_OUTPUT = https - -# Directories containing extra files. -HTML_EXTRA_FILES = doc/extra_files/https/gettysburg.txt - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/https.tag - -# Directories containing library source code. -INPUT = doc \ - doc/lib \ - libraries/c_sdk/standard/https/include \ - libraries/c_sdk/standard/https/include/types \ - libraries/c_sdk/standard/https/src \ - libraries/c_sdk/standard/https/src/private - -# Library file names. -FILE_PATTERNS = *https*.c *https*.h *https*.txt - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main \ - doc/tag/linear_containers.tag=../linear_containers \ - doc/tag/logging.tag=../logging \ - doc/tag/platform.tag=../platform diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/layout_library.xml b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/layout_library.xml deleted file mode 100644 index cf88e3e..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/layout_library.xml +++ /dev/null @@ -1,197 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/layout_main.xml b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/layout_main.xml deleted file mode 100644 index 6a57ad4..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/layout_main.xml +++ /dev/null @@ -1,215 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/linear_containers b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/linear_containers deleted file mode 100644 index f6a6216..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/linear_containers +++ /dev/null @@ -1,23 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "Linear Containers" -PROJECT_BRIEF = "Linked lists and Queues" - -# Library documentation output directory. -HTML_OUTPUT = linear_containers - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/linear_containers.tag - -# Directories containing library source code. -INPUT = doc/lib \ - libraries/c_sdk/standard/common/include - -# Library file names. -FILE_PATTERNS = *linear_containers*.h *linear_containers*.txt - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/logging b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/logging deleted file mode 100644 index bb574b1..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/logging +++ /dev/null @@ -1,28 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "Logging" -PROJECT_BRIEF = "Generate and print log messages" - -# Library documentation output directory. -HTML_OUTPUT = logging - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/logging.tag - -# Directories containing library source code. -INPUT = doc/lib \ - libraries/c_sdk/standard/common/include \ - libraries/c_sdk/standard/common/include/private \ - libraries/c_sdk/standard/common/include \ - libraries/c_sdk/standard/common/logging - -# Library file names. -FILE_PATTERNS = *logging*.c *logging*.h *logging*.txt - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main \ - doc/tag/static_memory.tag=../static_memory \ - doc/tag/platform.tag=../platform diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/main b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/main deleted file mode 100644 index 9020aba..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/main +++ /dev/null @@ -1,35 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "Main" - -# Library documentation output directory. -HTML_OUTPUT = main - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/main.tag - -# Input directories. -INPUT = doc/ \ - doc/guide - -# Library file names. -FILE_PATTERNS = *.txt - -# Don't automatically link to library symbols. -AUTOLINK_SUPPORT = NO - -# External tag files required by this library. -TAGFILES = doc/tag/logging.tag=../logging \ - doc/tag/platform.tag=../platform \ - doc/tag/mqtt.tag=../mqtt \ - doc/tag/shadow.tag=../shadow - -# Use the Main page layout file -LAYOUT_FILE = doc/config/layout_main.xml - -# Aliases for tables on the Style Guide page. -ALIASES += formattable{1}="This table contains the formats for the names of the most common SDK \1. It is not intended to be comprehensive. Bold text indicates a variable but required part of the \1 name. Italic text indicates a variable but optional part of the \1 name.^^^^| Format | Applies to | Example |^^| ------ | ---------- | ------- |" -ALIASES += formattableentry{3}="| \1 | \2 | \3 |" diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/mqtt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/mqtt deleted file mode 100644 index 1bbe142..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/mqtt +++ /dev/null @@ -1,39 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "MQTT" -PROJECT_BRIEF = "MQTT 3.1.1 client library" - -# Library documentation output directory. -HTML_OUTPUT = mqtt - -# Generate documentation for MQTT packet serializer overrides. -PREDEFINED += "IOT_MQTT_ENABLE_SERIALIZER_OVERRIDES=1" - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/mqtt.tag - -# Directories containing library source code. -INPUT = doc \ - doc/lib \ - libraries/c_sdk/standard/mqtt/include \ - libraries/c_sdk/standard/mqtt/include/types \ - libraries/c_sdk/standard/mqtt/src/private \ - libraries/c_sdk/standard/mqtt/src \ - demos/ \ - libraries/c_sdk/standard/mqtt/test \ - libraries/c_sdk/standard/mqtt/test/unit \ - libraries/c_sdk/standard/mqtt/test/access \ - libraries/c_sdk/standard/mqtt/test/system - -# Library file names. -FILE_PATTERNS = *mqtt*.c *mqtt*.h *mqtt*.txt - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main \ - doc/tag/logging.tag=../logging \ - doc/tag/static_memory.tag=../static_memory \ - doc/tag/platform.tag=../platform \ - doc/tag/linear_containers.tag=../linear_containers diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/platform b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/platform deleted file mode 100644 index 1575ef4..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/platform +++ /dev/null @@ -1,31 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "Platform" -PROJECT_BRIEF = "Platform portability layer" - -# Library documentation output directory. -HTML_OUTPUT = platform - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/platform.tag - -# Directories containing library source code. -INPUT = doc/lib \ - libraries/abstractions/platform/include/platform \ - libraries/abstractions/platform/include/types - -# Library file names. -FILE_PATTERNS = platform.txt \ - iot_network.h \ - iot_clock.h \ - iot_threads.h \ - iot_platform_types.h - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main \ - doc/tag/logging.tag=../logging \ - doc/tag/mqtt.tag=../mqtt \ - doc/tag/shadow.tag=../shadow diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/secure_sockets b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/secure_sockets deleted file mode 100644 index c105a8a..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/secure_sockets +++ /dev/null @@ -1,25 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "Secure Sockets" - -# Library documentation output directory. -HTML_OUTPUT = secure_sockets - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/secure_sockets.tag - -# Directories containing library source code. -INPUT = libraries/abstractions/secure_sockets/include/iot_secure_sockets.h \ - libraries/abstractions/secure_sockets/include/iot_secure_sockets_config_defaults.h \ - doc/lib/secure_sockets.txt - -# Library file names. -FILE_PATTERNS = *.h *.c *.txt - -EXAMPLE_PATH = libraries/abstractions/secure_sockets/include/iot_secure_sockets.h - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main \ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/shadow b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/shadow deleted file mode 100644 index d4c8685..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/shadow +++ /dev/null @@ -1,33 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "Shadow" -PROJECT_BRIEF = "AWS IoT Device Shadow library" - -# Library documentation output directory. -HTML_OUTPUT = shadow - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/shadow.tag - -# Directories containing library source code. -INPUT = doc/lib/ \ - libraries/c_sdk/aws/shadow \ - libraries/c_sdk/aws/shadow/include \ - libraries/c_sdk/aws/shadow/src/private \ - libraries/c_sdk/aws/shadow/src \ - libraries/c_sdk/aws/shadow/include/types - - -# Library file names. -FILE_PATTERNS = *shadow*.h *shadow*.c *shadow*.txt - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main \ - doc/tag/mqtt.tag=../mqtt \ - doc/tag/logging.tag=../logging \ - doc/tag/static_memory.tag=../static_memory \ - doc/tag/platform.tag=../platform \ - doc/tag/linear_containers.tag=../linear_containers diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/static_memory b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/static_memory deleted file mode 100644 index a943a8a..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/static_memory +++ /dev/null @@ -1,27 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "Static Memory" -PROJECT_BRIEF = "Statically-allocated buffer pools" - -# Library documentation output directory. -HTML_OUTPUT = static_memory - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/static_memory.tag - -# Directories containing library source code. -INPUT = doc/lib \ - libraries/c_sdk/standard/serializer/src \ - libraries/c_sdk/standard/common \ - libraries/c_sdk/standard/common/include/private - -# Library file names. -FILE_PATTERNS = *static_memory*.h *static_memory*.c *static_memory*.txt - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main \ - doc/tag/mqtt.tag=../mqtt \ - doc/tag/shadow.tag=../shadow diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/taskpool b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/taskpool deleted file mode 100644 index 42157dd..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/taskpool +++ /dev/null @@ -1,31 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "Task Pool" -PROJECT_BRIEF = "Task pool library" - -# Library documentation output directory. -HTML_OUTPUT = taskpool - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/taskpool.tag - -# Directories containing library source code. -INPUT = doc/lib \ - libraries/c_sdk/standard/common/include/private \ - libraries/c_sdk/standard/common/include/types \ - libraries/c_sdk/standard/common/include \ - libraries/c_sdk/standard/common/taskpool \ - libraries/c_sdk/standard/common/test - -# Library file names. -FILE_PATTERNS = *taskpool*.c *taskpool*.h *taskpool*.txt - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main \ - doc/tag/linear_containers.tag=../linear_containers \ - doc/tag/logging.tag=../logging \ - doc/tag/platform.tag=../platform \ - doc/tag/static_memory.tag=../static_memory \ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/wifi b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/wifi deleted file mode 100644 index d9a3f3b..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/config/wifi +++ /dev/null @@ -1,24 +0,0 @@ -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "Wi-Fi Management Library" - -# Library documentation output directory. -HTML_OUTPUT = wifi - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/wifi.tag - -# Directories containing library source code. -INPUT = libraries/abstractions/wifi/include/iot_wifi.h \ - doc/lib/wifi.txt - -# Library file names. -FILE_PATTERNS = *wifi*.h *wifi*.c *wifi*.txt - -EXAMPLE_PATH = libraries/abstractions/wifi/include/iot_wifi.h - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main \ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/extra_files/https/gettysburg.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/extra_files/https/gettysburg.txt deleted file mode 100644 index f470c2a..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/extra_files/https/gettysburg.txt +++ /dev/null @@ -1,8 +0,0 @@ -Four score and seven years ago our fathers brought forth on this continent, a new nation, conceived in Liberty, and dedicated to the proposition that all men are created equal. - -Now we are engaged in a great civil war, testing whether that nation, or any nation so conceived and so dedicated, can long endure. We are met on a great battle-field of that war. We have come to dedicate a portion of that field, as a final resting place for those who here gave their lives that that nation might live. It is altogether fitting and proper that we should do this. - -But, in a larger sense, we can not dedicate -- we can not consecrate -- we can not hallow -- this ground. The brave men, living and dead, who struggled here, have consecrated it, far above our poor power to add or detract. The world will little note, nor long remember what we say here, but it can never forget what they did here. It is for us the living, rather, to be dedicated here to the unfinished work which they who fought here have thus far so nobly advanced. It is rather for us to be here dedicated to the great task remaining before us -- that from these honored dead we take increased devotion to that cause for which they gave the last full measure of devotion -- that we here highly resolve that these dead shall not have died in vain -- that this nation, under God, shall have a new birth of freedom -- and that government of the people, by the people, for the people, shall not perish from the earth. - -Abraham Lincoln -November 19, 1863 \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/freertos_port_qual/aFreeRTOS_Porting_Guide.pdf b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/freertos_port_qual/aFreeRTOS_Porting_Guide.pdf deleted file mode 100644 index 551ac1e..0000000 Binary files a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/freertos_port_qual/aFreeRTOS_Porting_Guide.pdf and /dev/null differ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/freertos_port_qual/aFreeRTOS_Qualification_Guide.pdf b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/freertos_port_qual/aFreeRTOS_Qualification_Guide.pdf deleted file mode 100644 index 4c02712..0000000 Binary files a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/freertos_port_qual/aFreeRTOS_Qualification_Guide.pdf and /dev/null differ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/guidance.md b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/guidance.md deleted file mode 100644 index 548f055..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/guidance.md +++ /dev/null @@ -1,188 +0,0 @@ -# Overview -This is about how to use Doxygen to maintain the API documents. There are three parts: - -- Doxygen configuration and layout. -- A separate file to structure the documents -- Comment properly in source code with Doxygen special commands - -# Setup Doxygen - -[Doxygen Manual](http://www.stack.nl/~dimitri/doxygen/manual/index.html) - -- download and install Doxygen -- install graphviz - - on Mac, run `brew install graphviz` - - on Windows: https://graphviz.gitlab.io/_pages/Download/Download_windows.html - - Make sure that the directory location of "dot.exe" is added to the system PATH. -- goto the root directory of "amazon-freertos" (this will be referenced as $ROOT_AFR_DIR) - - `cd $ROOT_AFR_DIR` -- run Doxygen command to generate the documents - - `doxygen doc/config/main` - - `doxygen doc/config/secure_sockets` -- the entry doc is $ROOT_AFR_DIR/doc/output/main/html, open it with browser and verify it looks good - -# Add documents for a new library - -**Let's say the library name is "Foo"** - -## 1. Doxygen configuration and layout - -### create a new configuration file for "Foo" - -The new configuration's path is $ROOT_AFR_DIR/doc/config/foo - -Copy below as content: -- [REQUIRED] update the library name accordingly (anywhere appear as "foo" below) -- [REQUIRED] update "INPUT" configuration -- [REQUIRED] update "EXAMPLE_PATH" configuraton -- [OPTIONAL] update "FILE_PATTERNS" configuration if new file extension is introduced - - - -``` -# Include common configuration options. -@INCLUDE_PATH = doc/config -@INCLUDE = common - -# Basic project information. -PROJECT_NAME = "Foo" - -# Library documentation output directory. -HTML_OUTPUT = foo - -# Generate Doxygen tag file for this library. -GENERATE_TAGFILE = doc/tag/foo.tag - -# Directories containing library source code. -INPUT = [The source files path] - -# Library file names. -FILE_PATTERNS = *.h *.c *.txt - -EXAMPLE_PATH = [The source files path] - -# External tag files required by this library. -TAGFILES = doc/tag/main.tag=../main \ -``` - -## 2. A separate file to structure the documents - -The path to put this txt file: $ROOT_AFR_DIR/doc/lib/foo.txt - -In the following sections, follow each of them and **append** the content to the txt file. - -### denote mainpage - -``` -/** -@mainpage -*/ -``` - -### add configuration page - -TODO: this section is copy-pasted currently. Need a better way. - -``` -/** -@config_page{Foo} -@config_brief{library} - -@section ...... -@brief ...... - -...... - -@configpossible ...... -@configrecommended ...... -@configdefault ...... -*/ -``` - -### add constant page - -``` -/** -@constants_page{Foo} -@constants_brief{library} - -@section foo_constants_single Single Value Constants -- @ref ...... - -@section foo_constants_multiple Multiple Values Constants -- @ref ...... -*/ -``` - -### add function page - -``` -/** -@functions_page{foo, Foo} -@functions_brief{foo} -- @function_name{foo_function_socket} -- @function_brief{foo_function_socket} -*/ - -/** -@page foo_function_func FOO_func -@snippet aws_foo.h declare_foo_func -@copydoc FOO_func" -*/ -``` - -### add data type page - -``` -/** -@handles_group{Foo} -@handles_brief{library} - -@paramstructs_group{Foo} -@paramstructs_brief{Foo, Foo library} -*/ -``` - -## 3. Comment properly in source code with Doxygen special commands - -### add @[] declaration block to functions - -``` -/* @[declare_foo_func] */ -void FOO_func(); -/* @[declare_foo_func] */ -``` - -### add @ingroup to data types - -``` -@ingroup Foo_datatypes_handles -``` - -``` -@ingroup Foo_datatypes_enums -``` - -``` -@ingroup Foo_datatypes_paramstructs -``` - -### add @anchor and @name to group of constants - -``` -/** - * @anchor AGroupOfConstants - * @name AGroupOfConstants - * ... - */ - -/**@{ */ - - #define Constants_1 - #define Constants_2 - -/**@} */ - -``` - - diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/guide/building.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/guide/building.txt deleted file mode 100644 index d2afc17..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/guide/building.txt +++ /dev/null @@ -1,124 +0,0 @@ -/** -@page building Building the SDK -@brief Guide for building the SDK. - -This SDK builds with [CMake](https://cmake.org/), a cross-platform build tool. - -@pre -- CMake version 3.5.0 or later and a supported C compiler. -- One of the following security libraries: - - OpenSSL development libraries and header files, version 1.0.2g or later. - -@pre -Additional requirements for POSIX systems: -- POSIX threads, mutexes, and semaphores. -- POSIX timers. - -In addition, credentials and Things for AWS IoT must be provisioned before running the demos. See [this page](https://docs.aws.amazon.com/iot/latest/developerguide/iot-gs.html) for a tutorial on setting up AWS IoT. - -@section building_demo Building the demo applications -@brief How to build the demo applications. - -Before building the demos, all desired configuration settings should be defined. Configuration settings include global [library](@ref global_library_config) and [demo](@ref global_demos_config) settings, as well as settings for specific libraries and demos. Settings for demo applications should be placed in `demos/iot_demo_config.h`. Any undefined settings will use a default value when possible. - -The demo applications build with CMake. - -In-source CMake builds are not allowed. A build directory should be created under the SDK root directory. Since CMake is cross-platform, build steps will vary depending on host OS. On Linux, the demo applications are built as follows: -@code{sh} -# Create build directory and change to build directory. -mkdir build -cd build - -# Configure build using CMake. -cmake .. - -# Build the demo applications. -make -@endcode - -Demo application executables will be placed in a `bin` directory of the CMake build directory, i.e. `build/bin` in the example above. The executables will be named `aws_iot_demo_library` or `iot_demo_library`, depending on whether the demo is specific to AWS IoT. For example, the MQTT demo application, which may be used with any MQTT server, will be named `iot_demo_mqtt`. The Thing Shadow demo, which is specific to AWS IoT, will be named `aws_iot_demo_shadow`. - -Configuration settings may also be set using CMake by setting `CMAKE_C_FLAGS`. However, placing configuration settings in `demos/iot_demo_config.h` is recommended over setting them using CMake. -@code{sh} -# Example: Set IOT_STATIC_MEMORY_ONLY using CMake -cmake .. -DCMAKE_C_FLAGS=-DIOT_STATIC_MEMORY_ONLY=1 -@endcode - -By default, CMake may build in `Release` configuration. To enable debugging symbols, set `CMAKE_BUILD_TYPE` to `Debug`. -@code{sh} -cmake .. -DCMAKE_BUILD_TYPE=Debug -@endcode - -Delete the build directory to remove all demo application executables and build files. - -@section demo_commandlineoptions Demo command line options -@brief Command line options of the demo applications. - -Demo applications accept the following command line options. - -@subsection demo_optionn -n -@brief Disable AWS IoT MQTT mode. - -By default, the demo applications expect to run with an AWS IoT MQTT server. Passing this option disables [AWS IoT MQTT mode](@ref IotMqttConnectInfo_t.awsIotMqttMode) and treats the remote MQTT server as a fully-compliant MQTT server. This option should not have an argument. - -Because Thing Shadows are specific to AWS IoT, this option is ignored by the [Shadow demo](@ref shadow_demo). - -@subsection demo_optionsu -s and -u -@brief Secured or unsecured demo connection, respectively. - -Neither `-s` nor `-u` should have an argument, and only one of the two should be used at a time. - -See @ref IOT_DEMO_SECURED_CONNECTION for the compile-time default setting of this option. - -Because Thing Shadows are specific to AWS IoT (which requires secured connections), this option is ignored by the [Shadow demo](@ref shadow_demo). - -@subsection demo_optionh -h host -@brief Remote host for demo application. - -Must be followed by a host name. - -See @ref IOT_DEMO_SERVER for the compile-time default setting of this option. - -@subsection demo_optionp -p port -@brief Remote port for demo application. - -Must be followed by a port in the range of `[1,65535]`. - -See @ref IOT_DEMO_PORT for the compile-time default setting of this option. - -@subsection demo_optionr -r rootCA, -c clientCert, -k privateKey -@brief Paths to trusted server root certificate, client certificate, and client certificate private key, respectively. - -Must be followed by a filesystem path to the respective PEM-encoded credential. - -See @ref IOT_DEMO_ROOT_CA, @ref IOT_DEMO_CLIENT_CERT, and @ref IOT_DEMO_PRIVATE_KEY for the compile-time default settings of these options. - -@subsection demo_optioni -i identifier -@brief MQTT client identifier OR Thing Name. - -Must be followed by a string representing either an MQTT client identifier (MQTT demo only) or a Thing Name (all other demos). Because AWS IoT recommends that MQTT client identifier and Thing Name match, demos will use the Thing Name as the MQTT client identifier when possible. - -See @ref IOT_DEMO_IDENTIFIER for the compile-time default settings of this option. - -@section building_tests Building and running the tests -@brief How to build and run the SDK tests. - -Like the demo applications, the tests also build with CMake. [Global test configuration settings](@ref global_tests_config), as well as specific library test settings, should be defined in `tests/iot_tests_config.h`. - -Unlike the demos, the tests are currently only supported on POSIX systems that support all of the POSIX prerequisites. They are built by passing the option `IOT_BUILD_TESTS=1` to CMake. -@code{sh} -# Create build directory and change to build directory. -mkdir build -cd build - -# Configure build using CMake. -cmake .. -DIOT_BUILD_TESTS=1 - -# Build both the demos and tests. -make -@endcode - -Test executables will be placed in a `bin` directory of the CMake build directory (i.e. `build/bin`) alongside the demo applications. They will be named `aws_iot_tests_library` or `iot_tests_library`, depending on whether the tests are specific to AWS IoT. For example, the MQTT tests application, which may be used with any MQTT server, will be named `iot_tests_mqtt`. The Thing Shadow tests, which are specific to AWS IoT, will be named `aws_iot_tests_shadow`. - -By default, running a test executable with no command line arguments will only run the basic unit tests and system tests. This run is expected to take up to a few minutes per library test. The command line option `-l` may be passed to a test executable to enable long-running tests (such as stress tests) which may run for several hours. Individual tests may support other command line options; see the test application files for more information. -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/guide/developer.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/guide/developer.txt deleted file mode 100644 index bf06c14..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/guide/developer.txt +++ /dev/null @@ -1,8 +0,0 @@ -/** -@page guide_developer Developer's Guide -@brief Guide for maintaining and contributing code to this project. - -This guide contains the following pages. All pages assume the reader has intermediate familiarity with this SDK. -- @subpage guide_developer_styleguide
- @copybrief guide_developer_styleguide -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/guide/style.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/guide/style.txt deleted file mode 100644 index d7a4b8d..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/guide/style.txt +++ /dev/null @@ -1,297 +0,0 @@ -/** -@page guide_developer_styleguide Style Guide -@brief Guide for the coding style used in this SDK. - -The goal of this style guide is to encourage a readable and consistent coding style across the entire SDK. - -@section guide_developer_styleguide_codingstyle Coding Style -@brief The coding style used in this SDK. - -The coding style aims to produce code that is readable and easy to debug. An example is provided in @ref guide_developer_styleguide_codingstyle_example. - -@subsection guide_developer_styleguide_codingstyle_generalguidelines General guidelines -@brief General guidelines for library style. -- Libraries should only use features from [C99](https://en.wikipedia.org/wiki/C99) and earlier. - -- Libraries should [log](@ref logging) extensively. -- Code should be well-commented. -- Only `/*` and @c *`/` should be used to start and end comments. -- All comments end with a period. -- Only spaces should be used for indenting. A single indent is 4 spaces. No tab characters should be used. -- A parenthesis is usually followed by a space (see @ref guide_developer_styleguide_codingstyle_example). -- Lines of code should be less than 80 characters long, although longer lines are permitted. -- All local variables should be declared at the top of a function. -- All global variables should be declared at the top of a file. -- Variables are always initialized. -- A separator is placed between different sections of a file. The current separator is: -@code{c} -/*-----------------------------------------------------------*/ -@endcode -- All files must include @ref IOT_CONFIG_FILE at the top of the file before any other includes. -- `static` functions must have a declaration at the top of the file and be implemented before any application-facing functions. - -@subsection guide_developer_styleguide_codingstyle_typeguidelines Type guidelines -@brief Guidelines for variable types. -- Only fixed-width integer types should be used. Exceptions for `bool` and types required by third-party APIs. -- The default integer in the libraries should be 32 bits wide, i.e. `int32_t` or `uint32_t`. -- Sizes and lengths should be represented with `size_t`, and Boolean variables with `bool`. -- The portable format specifiers in `` should be used for logging fixed-width integers. - -@subsection guide_developer_styleguide_codingstyle_example Example File -@brief An example file that follows the coding style rules. - -See @ref guide_developer_styleguide_naming for how to name the functions, variables, and macros. - -@code{c} -/* Included headers are at the top of the file. The config file include is always first. */ - -/* Build using a config header, if provided. */ -#ifdef IOT_CONFIG_FILE -#include IOT_CONFIG_FILE -#endif - -/* Standard includes are immediately after the config file. They are sorted alphabetically. - * They use angle brackets <> around the file name. */ - -/* Standard includes. */ -#include -#include -#include -#include -#include - -/* Library internal headers are included next. They use quotes "" around the file name. */ - -/* Library internal include. */ -#include "private/iot_library_internal.h" - -/* Library application-facing headers are included last. They use quotes "" around the file name. */ - -/* Library include. */ -#include "iot_library.h" - -/*-----------------------------------------------------------*/ - -/* Defined constants follow the included headers. */ - -/* When possible, parentheses () should be placed around contant values and a type - * should be specified. */ -#define _LIBRARY_CONSTANT ( ( int32_t ) 10 ) - -#define _LIBRARY_FUNCTION_MACRO( argument ) \ /* Line continuators are right-aligned. */ - { \ /* Function-like macros are surrounded by curly braces {}. */ - macro_body( argument ); \ - } - -/*-----------------------------------------------------------*/ - -/* Library typedefs follow the defined constants. */ - -/* Forward declarations are used only when necessary. They are placed before all - * other typedefs. */ - -typedef int32_t _type_t; - -typedef struct _structType /* Structs are named along with the typedef. */ -{ - int32_t member; - - union /* Anonymous structs/unions are permitted only inside of other structs. */ - { - int32_t a; - int32_t b; - }; - - int32_t variableLengthMember[]; /* Variable length arrays (a C99 feature) are permitted. */ -} _structType_t; - -/*-----------------------------------------------------------*/ - -/* Declarations of static and extern functions follow the typedefs. */ - -static bool _libraryStaticFunction( void * pArgument, - size_t argumentLength ); - -/* External function declarations should be used sparingly (using an internal - * header file to declare functions is preferred). */ -extern int32_t IotLibrary_ExternalFunction( void * pArgument ); - -/*-----------------------------------------------------------*/ - -/* Declarations of global variables follow the static and extern function - * declarations. Global variables are permitted, but should be avoided when - * possible. */ - -/* Global variables are always initialized. */ -static int _globalVariable = 0; -static int _globalArray[ _LIBRARY_CONSTANT ] = { 0 }; - -/*-----------------------------------------------------------*/ - -/* Implementations of static functions follow the global variable declarations. */ - -static bool _libraryStaticFunction( void * pArgument, - size_t argumentLength ) -{ - /* All local variables are declared at the top of the function. Variables are - * always initialized. */ - size_t i = 0; - int32_t localVariable = 0; - int32_t * pLocalPointer = ( int32_t * ) pArgument; - - /* All functions make generous use of the logging library. */ - IotLogInfo( "Performing calculation..." ); - - /* Checking parameters at the beginning of functions and returning on bad - * parameter values is encouraged. */ - if( ( pArgument == NULL ) || ( argumentLength == 0 ) ) /* Note the parentheses and spacing in if statements */ - { - IotLogError( "Bad parameters." ); - - return false; - } - - for( i = 0; i < argumentLength; i++ ) /* Note the spacing in the for loop. */ - { - localVariable += IotLibrary_ExternalFunction( pArgument ); - - /* Use portable format specifier for fixed-width integer. */ - IotLogDebug( "Current value is " PRId32 ".", localVariable ); - } - - if( localVariable < 0 ) - { - IotLogWarn( "Failed to calculate positive value." ); - } - - IotLogInfo( "Calculation done." ); - - return true; -} - -/* A separator is placed between all function implementations. */ -/*-----------------------------------------------------------*/ - -/* Implementations of application-facing functions are at the bottom of the file. */ - -bool IotLibrary_ApplicationFunction( void ) /* Functions with no arguments have void in their argument list. */ -{ - _LIBRARY_FUNCTION_MACRO( _globalArray ); - - return true; -} - -/* Separator and newline at end of file */ -/*-----------------------------------------------------------*/ - -@endcode - -@section guide_developer_styleguide_naming Naming -@brief Naming convention used in this SDK. - -The naming convention aims to differentiate this SDK's files, variables, and functions to avoid name collisions. In general: -- The first characters of all publicly visible names should identify the name as part of this SDK.
- Example: For general-purpose libraries (such as MQTT), names start with `iot_` or `Iot`.
- Example: For libraries specific to AWS IoT (such as Shadow), names start with `aws_iot_` or `AwsIot`. -- Words in names should be ordered with the most general word first and the most specific word last. Names for internal use begin with `_`.
- Example: `iot_mqtt_api.c` identifies a file as part of the general MQTT library. `_IotMqtt_ValidateConnect` identifies a function as part of the Internal component of the general MQTT library. -- Names should avoid using abbreviations. - -@subsection guide_developer_styleguide_naming_definedconstantsandenumvalues Defined constants and enum values -@brief Naming convention for constants set using preprocessor @c #`define` and enum values. - -@formattable{defined constants and enum values} -@formattableentry{`IOT_`LIBRARY`_`DESCRIPTION
`AWS_IOT_`LIBRARY`_`DESCRIPTION,Defined constants and enum values in application-facing library header files,`IOT_MQTT_SUCCESS` (iot_mqtt.h)
`AWS_IOT_SHADOW_SUCCESS` (aws_iot_shadow.h)} -@formattableentry{`IOT_DEMO_`DESCRIPTION
`IOT_TEST_`DESCRIPTION,Defined constants and enum values in demos and tests,`IOT_DEMO_MQTT_PUBLISH_BURST_SIZE`
`IOT_TEST_MQTT_THREADS`} -@formattableentry{`AWS_IOT_DEMO_`DESCRIPTION
`AWS_IOT_TEST_`DESCRIPTION,Defined constants and enum values in demos and tests specific to AWS IoT,`AWS_IOT_DEMO_THING_NAME`
`AWS_IOT_TEST_SHADOW_THING_NAME`} -@formattableentry{`_`DESCRIPTION,Internal constants and enum values
No `AWS_` prefix for internal namesin AWS-specific libraries,`_MQTT_PACKET_TYPE_CONNECT`
(iot_mqtt_internal.h)
`_SHADOW_OPERATION_COUNT`
(aws_iot_shadow_internal.h)} - -Names of constants and enum values should contain only uppercase letters and underscores. All names intended for application use must begin with `IOT_` or `AWS_IOT_`, while names intended for internal use must begin with only `_`. - -@subsection guide_developer_styleguide_naming_files Files -@brief Naming convention for files. - -@formattable{files} -@formattableentry{`iot_`library`_`description`.extension`
`aws_iot_`library`_`description`.extension`,General library file,`iot_mqtt_api.c`
`aws_iot_shadow_api.c`} -@formattableentry{`iot_`library`_internal.h`
`aws_iot_`library`_internal.h`,Internal library header,`iot_mqtt_internal.h`
`aws_iot_shadow_internal.h`} -@formattableentry{`iot_demo_`library`.c`
`aws_iot_demo_`library`.c`,Library demo source,`iot_demo_mqtt.c`
`aws_iot_demo_shadow.c`} -@formattableentry{`iot_tests_`library`_`description`.c`
`aws_iot_tests_`library`_`description`.c`,Library test source,`iot_tests_mqtt_api.c`
`aws_iot_tests_shadow_api.c`} - -File names contain only lowercase letters and underscores. All file names should start with `iot_` or `aws_iot_` and be named according to their purpose. For example: -- `iot_mqtt_api.c`: A file in the MQTT library that implements the MQTT API functions. -- `iot_demo_mqtt.c`: A file in the Demos for the MQTT library. -- `iot_demo_mqtt_posix.c`: A file in the Demos for the MQTT library on POSIX systems. -- `iot_tests_mqtt_api.c`: A file in the Tests for the MQTT library. Since the tests currently only run on POSIX systems, test file names do not use the `_posix` suffix. - -Library file names should use one or two words to describe the functions implemented in that file. For example: -- `iot_mqtt_serialize.c`: Implements the MQTT library's packet serialization and deserialization functions. -- `iot_clock_posix.c`: Implements the platform clock component for POSIX systems. - -Declarations of internal functions, structures, macros, etc. of a library should be placed in a header file with an `_internal` suffix. The `_internal` header file should go in the `lib/include/private` directory. For example: -- `iot_mqtt_internal.h`: Declares the MQTT library's internal functions, structures, macros, etc. - -File names for tests and demos should all begin with `iot_demo_` and `iot_tests_`, respectively. The names should then specify the library being demoed or or tested; for example, the files names of the MQTT library's demos and tests start with `iot_demo_mqtt_` and `iot_tests_mqtt_`. Additionally, test file names should describe what tests are implemented in the file, such as `iot_tests_mqtt_api.c` for a file containing tests for the MQTT library API functions. - -@subsection guide_developer_styleguide_naming_functions Functions (and function-like macros) -@brief Naming convention of functions and function-like macros. - -@formattable{functions} -@formattableentry{`Iot`Library`_`Description
`AwsIot`Library`_`Description,Externally-visible library function,`IotMqtt_Publish`
`AwsIotShadow_Update`} -@formattableentry{`_Iot`Library`_`Description
`_AwsIot`Library`_`Description,Internal (but not `static`) library function,`_IotMqtt_ValidateNetIf`
`_AwsIotShadow_ParseShadowStatus`} -@formattableentry{`IotTest`Library`_`Description,Function only used in tests,`IotTest_NetworkConnect`
`IotTestMqtt_createMqttConnection`} -@formattableentry{`_`description,`static` function (never uses `Aws` prefix),`_createMqttConnection`
`_codeToShadowStatus`} -@formattableentry{`IotTest`Library`_`accessedFunction,Test access function,`IotTestMqtt_createMqttConnection`} - -Externally visible (i.e. not `static`) functions are [UpperCamelCased](https://en.wikipedia.org/wiki/Camel_case) and must begin with `Iot` or `AwsIot` (public API functions); or `_Iot` or `_AwsIot` (internal functions). Function names should then specify their library name; followed by an underscore; followed by a brief description of what the function does. For example: -- `IotMqtt_Publish`: This function is part of the public MQTT API. It Publishes an MQTT message. -- `_IotMqtt_ValidateNetIf`: This function is internal to the MQTT library, but not `static`. It validates an `IotMqttNetIf_t`. - -Functions not visible outside their source file (i.e. `static` functions) have names that are [lowerCamelCased](https://en.wikipedia.org/wiki/Camel_case) and begin with an underscore. These function names do not contain the library name or `Aws`. For example: -- `_createMqttConnection`: A `static` function in `iot_mqtt_api.c`. -- `_codeToShadowStatus`: A `static` function in `aws_iot_shadow_parser.c`. - -Test access functions begin with `IotTest`; followed by the library name; followed by an underscore; followed by the function that the test function accesses. Since the accessed function is always `static`, the accessed function will be [lowerCamelCased](https://en.wikipedia.org/wiki/Camel_case). - -@subsection guide_developer_styleguide_naming_types Types -@brief Naming conventions of library `typedef` types. - -@formattable{types} -@formattableentry{`Iot`LibraryDescription`_t`
`AwsIot`LibraryDescription`_t`,General types in application-facing library header files,`IotMqttError_t` (iot_mqtt.h)
`AwsIotShadowError_t` (aws_iot_shadow.h)} -@formattableentry{`Iot`LibraryFunction`Info_t`
`AwsIot`LibraryFunction`Info_t`,Application-facing parameter structure,`IotMqttPublishInfo_t`
(Parameter structure to `IotMqtt_Publish`)
`AwsIotShadowDocumentInfo_t`
(Parameter structure for Shadow documents)} -@formattableentry{`_`libraryDescription`_t`,Type in an `internal` header,`_mqttOperation_t` (iot_mqtt_internal.h)
`_shadowOperation_t` (aws_iot_shadow_internal.h)} -@formattableentry{`_`description`_t`,Internal type in source file,`_topicMatchParams_t` (iot_mqtt_subscription.c)} - -Types intended for use in applications are [UpperCamelCased](https://en.wikipedia.org/wiki/Camel_case). The names must start with `Iot` or `AwsIot` and end with `_t`. Parameter structures should indicate their associated function: for example, `IotMqttPublishInfo_t` is passed as a parameter to `IotMqtt_Publish`. - -Types intended for internal library use defined in a header file are [lowerCamelCased](https://en.wikipedia.org/wiki/Camel_case). The names must start with `_`, followed by the library name, and end with `_t`. Internal types defined in a library source file must start with `_`, end with `_t`, and not include the library name. - -`struct` typedefs should always be named along with the `typedef`. The struct name should be identical to the `typedef` name, but without the `_t` at the end. For example: -@code{c} -typedef struct IotLibraryStruct -{ - int32_t member; -} IotLibraryStruct_t; - -typedef struct _libraryInternalStruct -{ - int32_t member; -} _libraryInternalStruct_t; -@endcode - -A `struct` may contain anonymous `struct` or `union` members. - -@subsection guide_developer_styleguide_naming_variables Variables -@brief Naming conventions of variables. - -@formattable{variables} -@formattableentry{variableDescription,General local variable,`startTime`} -@formattableentry{`p`VariableDescription,Local variable pointers and arrays (including strings),`pSubscriptionList`} -@formattableentry{`_`variableDescription,Global variable that is `static`,`_connectMutex` (iot_mqtt_api.c)
`_pSamplePayload` (string)} -@formattableentry{`_Iot`LibraryDescription
`_AwsIot`LibraryDescription,Global variable that is NOT `static`,`_IotMqttTaskPool` (iot_mqtt_operation.c)
`_pIotSamplePayload` (string)} - -Local variable names are [lowerCamelCased](https://en.wikipedia.org/wiki/Camel_case) and consist only of a description of the variable. Names like `i` or `j` are acceptable for loop counters, but all other variables should have a descriptive name. - -Global variable names always start with a `_`. Global variables that are `static` consist of only the description in [lowerCamelCase](https://en.wikipedia.org/wiki/Camel_case). Global variables that are not static consist of the library name and the description in [UpperCamelCase](https://en.wikipedia.org/wiki/Camel_case); for example: `_IotLibraryNonStaticGlobalVariable`. - -All pointers, arrays, and strings (both global and local) start with `p` (local) or `_p` (global). -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/atomic.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/atomic.txt deleted file mode 100644 index ecebb2b..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/atomic.txt +++ /dev/null @@ -1,93 +0,0 @@ -/** -@mainpage -@anchor atomic -@brief Atomic data structures and functions.

- -Provide lock-free and wait-free mutually exclusive access to a memory location. -*/ - -/** -@config_page{Atomic} -@config_brief{library} - -@brief Atomic component does not need a configuration file. We do, however, provide two implementations -- the default atomic implementation (implemented with enter/exit critical section) and optimized atomic implementation (implemented with GCC atomic built-in, which gets compiled into architecture supported atomic instructions). To use the default implementation, user solely needs to import atomic.h. To use optimized atomic implementation, user needs to confirm whether GCC compiler version in use supports atomic built-in functions (>= 4.7), and whether the target architecture has atomic instructions. - -@section configUSE_GCC_BUILTIN_ATOMICS -@brief To use optimized implementation, define this macro in project specific FreeRTOSConfig.h AND set the value to 1. - -*/ - -/** -@functions_page{atomic, Atomic} -@functions_brief{atomic} -- @function_name{atomic_function_atomic_compareandswap_u32} -@function_brief{atomic_function_atomic_compareandswap_u32} -- @function_name{atomic_function_atomic_swappointers_p32} -@function_brief{atomic_function_atomic_swappointers_p32} -- @function_name{atomic_function_atomic_compareandswappointers_p32} -@function_brief{atomic_function_atomic_compareandswappointers_p32} -- @function_name{atomic_function_atomic_add_u32} -@function_brief{atomic_function_atomic_add_u32} -- @function_name{atomic_function_atomic_subtract_u32} -@function_brief{atomic_function_atomic_subtract_u32} -- @function_name{atomic_function_atomic_increment_u32} -@function_brief{atomic_function_atomic_increment_u32} -- @function_name{atomic_function_atomic_decrement_u32} -@function_brief{atomic_function_atomic_decrement_u32} -- @function_name{atomic_function_atomic_or_u32} -@function_brief{atomic_function_atomic_or_u32} -- @function_name{atomic_function_atomic_and_u32} -@function_brief{atomic_function_atomic_and_u32} -- @function_name{atomic_function_atomic_nand_u32} -@function_brief{atomic_function_atomic_nand_u32} -- @function_name{atomic_function_atomic_xor_u32} -@function_brief{atomic_function_atomic_xor_u32} - -*/ - -/** -@function_page{Atomic_CompareAndSwap_u32,atomic,atomic_compareandswap_u32} -@function_snippet{atomic,atomic_compareandswap_u32,atomic.h} -@copydoc Atomic_CompareAndSwap_u32 - -@function_page{Atomic_SwapPointers_p32,atomic,atomic_swappointers_p32} -@function_snippet{atomic,atomic_compareandswap_u32,atomic.h} -@copydoc Atomic_CompareAndSwap_u32 - -@function_page{Atomic_CompareAndSwapPointers_p32,atomic,atomic_compareandswappointers_p32} -@function_snippet{atomic,atomic_compareandswappointers_p32,atomic.h} -@copydoc Atomic_CompareAndSwapPointers_p32 - -@function_page{Atomic_Add_u32,atomic,atomic_add_u32} -@function_snippet{atomic,atomic_add_u32,atomic.h} -@copydoc Atomic_Add_u32 - -@function_page{Atomic_Subtract_u32,atomic,atomic_subtract_u32} -@function_snippet{atomic,atomic_subtract_u32,atomic.h} -@copydoc Atomic_Subtract_u32 - -@function_page{Atomic_Increment_u32,atomic,atomic_increment_u32} -@function_snippet{atomic,atomic_increment_u32,atomic.h} -@copydoc Atomic_Increment_u32 - -@function_page{Atomic_Decrement_u32,atomic,atomic_decrement_u32} -@function_snippet{atomic,atomic_decrement_u32,atomic.h} -@copydoc Atomic_Decrement_u32 - -@function_page{Atomic_OR_u32,atomic,atomic_or_u32} -@function_snippet{atomic,atomic_or_u32,atomic.h} -@copydoc Atomic_OR_u32 - -@function_page{Atomic_AND_u32,atomic,atomic_and_u32} -@function_snippet{atomic,atomic_and_u32,atomic.h} -@copydoc Atomic_AND_u32 - -@function_page{Atomic_NAND_u32,atomic,atomic_nand_u32} -@function_snippet{atomic,atomic_nand_u32,atomic.h} -@copydoc Atomic_NAND_u32 - -@function_page{Atomic_XOR_u32,atomic,atomic_xor_u32} -@function_snippet{atomic,atomic_xor_u32,atomic.h} -@copydoc Atomic_XOR_u32 - -*/ \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/ble.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/ble.txt deleted file mode 100644 index a2055d6..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/ble.txt +++ /dev/null @@ -1,114 +0,0 @@ -/** -@mainpage -@anchor iotble -@brief BLE library. - -> Amazon FreeRTOS supports publishing and subscribing to MQTT topics over Bluetooth Low Energy (BLE) through a proxy device, such as a mobile phone. With the Amazon FreeRTOS BLE library, your microcontroller can securely communicate with the AWS IoT MQTT broker. - -@image html blediagram.png width=40% - -Using the Mobile SDKs for Amazon FreeRTOS Bluetooth Devices, you can write native mobile applications that communicate with the embedded applications on your microcontroller over BLE. For more information about the mobile SDKs, see [Mobile SDKs for Amazon FreeRTOS Bluetooth Devices](https://docs.aws.amazon.com/freertos/latest/userguide/freertos-ble-mobile.html). - -In addition to supporting MQTT, the Amazon FreeRTOS BLE library includes services for configuring Wi-Fi networks. The Amazon FreeRTOS BLE library also includes some middleware and lower-level APIs for more direct control over your BLE stack. The source files for the Amazon FreeRTOS BLE library are located in [AmazonFreeRTOS/lib/bluetooth_low_energy](https://github.com/aws/amazon-freertos/tree/feature/ble-beta/lib/bluetooth_low_energy). - -Amazon FreeRTOS BLE Architecture -The Amazon FreeRTOS BLE library is made up of three layers: services, middleware, and low-level wrappers. - -@image html BLE-architecture.png width=40% - -@dependencies_section{ble} -@dependencies_brief{ble library} - -@dot "BLE direct dependencies" -digraph ble_dependencies -{ - node[shape=box, fontname=Helvetica, fontsize=10, style=filled]; - edge[fontname=Helvetica, fontsize=10]; - subgraph - { - ble[label="BLE", fillcolor="#cc00ccff"]; - } - subgraph - { - node[fillcolor="#aed8a9ff"]; - rank = same; - linear_containers[label="List/Queue", URL="@ref linear_containers"]; - } - subgraph - { - rank = same; - platform_network[label="Network", fillcolor="#e89025ff", URL="@ref platform_network"]; - platform_clock[label="Clock", fillcolor="#e89025ff", URL="@ref platform_clock"]; - } - ble -> linear_containers; - ble -> platform_clock; - ble -> platform_network; -} -@enddot - -Currently, the BLE library has the following dependencies: -- The linear containers (list/queue) library for maintaining the data structures for scheduled and in-progress BLE operations. -- The platform layer provides an interface to the operating system for thread management, timers, clock functions, network access, etc. - -In addition to the components above, the BLE library may also depend on C standard library headers. -*/ - -/** -@page ble_tests Tests -@brief Tests written for the BLE library. - -The BLE tests reside in the `???` directory. They are divided into the following subdirectories: -- `system`: BLE system and stress tests. Stress tests may run for a long time, so they are not run unless the `-l` option is passed to the test executable. -- `unit`: BLE unit tests. These tests do not require a network connection. - -The current BLE tests use the [Unity test framework](http://www.throwtheswitch.org/unity/). -*/ - -/** -@config_page{ble} -@config_brief{BLE library} - -Amazon FreeRTOS BLE Library Configuration File - -Applications that use the Amazon FreeRTOS MQTT over BLE service must provide an aws_ble_config.h header file, in which configuration parameters are defined. Undefined configuration parameters take the default values specified in lib\include\private\aws_ble_config_defaults.h. - -*/ - -/** -@enums_group{ble} -@enums_brief{BLE library} -@paramstructs_group{ble} -@paramstructs_brief{ble,BLE library} -@handles_group{ble} -@handles_brief{BLE library} -@functionpointers_group{ble} -@functionpointers_brief{BLE library} -@structs_group{ble} -@structs_brief{BLE library} - -*/ - -/** -@functions_page{BLE, BLE} -@functions_brief{BLE} -- @subpage iotble_functions
- @copybrief iotble_functions -- @subpage iotbledeviceinfo_functions
- @copybrief iotbledeviceinfo_functions -- @subpage iotblewifiprov_functions
- @copybrief iotblewifiprov_functions -- @subpage iotblemqtt_functions
- @copybrief iotblemqtt_functions -*/ - -/** -@constants_page{ble} -@constants_brief{BLE library} - -- @subpage iotbledeviceinfo_constants
- @copybrief iotbledeviceinfo_constants -- @subpage iotblewifiprov_constants
- @copybrief iotblewifiprov_constants -- @subpage iotblemqtt_constants
- @copybrief iotblemqtt_constants -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/https.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/https.txt deleted file mode 100644 index 420d65b..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/https.txt +++ /dev/null @@ -1,538 +0,0 @@ -/** -@mainpage -@anchor https -@brief HTTPS Client v1.0.0 library. - -- HTTPS Client Main page text. - -> The Hypertext Transfer Protocol (HTTP) is a stateless application-level protocol for distributed, collaborative, hypertext information systems. - - — Official description of HTTP from [RFC 7231](https://tools.ietf.org/html/rfc7231)
- -This HTTP library implements a subset of the HTTP/1.1 standard for compatibility with the [AWS IoT HTTP Server](https://docs.aws.amazon.com/iot/latest/developerguide/http.html) and the [AWS S3 HTTP Server](https://docs.aws.amazon.com/AmazonS3/latest/API/RESTObjectOps.html). It is also compatible with other HTTP servers. Feature of this library include: -- Both fully asynchronous and synchronous (blocking) API functions. -- Application managed memory for internal context and HTTP formatted headers. -- Thread-aware and parallelized connections. - -@dependencies_section{https} -@dependencies_brief{HTTPS Client library} - -@dot "HTTPS Client direct dependencies" -digraph https_dependencies -{ - node[shape=box, fontname=Helvetica, fontsize=10, style=filled]; - edge[fontname=Helvetica, fontsize=10]; - subgraph - { - https[label="HTTPS", fillcolor="#cc00ccff"]; - } - subgraph - { - node[fillcolor="#aed8a9ff"]; - rank = same; - linear_containers[label="List/Queue", URL="@ref linear_containers"]; - logging[label="Logging", URL="@ref logging"]; - } - subgraph - { - rank = same; - platform_threads[label="Thread management", fillcolor="#e89025ff", URL="@ref platform_threads"]; - platform_clock[label="Clock", fillcolor="#e89025ff", URL="@ref platform_clock"]; - platform_network[label="Network", fillcolor="#e89025ff", URL="@ref platform_network"]; - } - https -> linear_containers; - https -> logging [label=" if logging enabled", style="dashed"]; - https -> platform_threads; - https -> platform_clock; - https -> platform_network; - logging -> platform_clock; -} -@enddot - -Currently, the HTTPS Client library has the following dependencies: -- The queue library for maintaining of list of pending requests and responses on the connection. -- The logging library may be used if @ref IOT_LOG_LEVEL_HTTPS is not @ref IOT_LOG_NONE. -- The platform layer provides an interface to the operating system for thread management, clock functions, networking, etc. - -In addition to the components above, the HTTPS Client library also depends on C standard library headers. -*/ - -/** -@page https_design Design -@brief Architecture behind the HTTPS library. - -The HTTPS Client library will invoke a task pool worker to send a request. It will then receive the response during the network receive callback context. If there are more requests in the connection's request queue, it will schedule another task pool worker to send that request. - -@section Synchronous_Design Synchronous Design -@image html https_client_sync_workflow.png width=100% - -@section Asynchronous_Design Asynchronous Design -@image html https_client_async_workflow.png width=100% - -@section Asynchronous_Callback_Order Asynchronous Callbacks Ordering -@image html https_client_async_callback_order.png width=100% -*/ - -/** -@page https_demo Demos -@brief The HTTPS Client demos demonstrates usage of the HTTPS Client library. - -These demos shows downloading a file from S3 using a pre-signed URL using the Amazon FreeRTOS HTTP Client library. The HTTPS Client library is a generic HTTP/1.1 client library that be used to download files from other web servers as well. - -See @subpage https_demo_usage for information on how to get the demo up and running. - -The main HTTPS Client demo files are [iot_demo_https_s3_download_async.c](https://github.com/aws/amazon-freertos/tree/master/demos/https/iot_demo_https_s3_download_async.c) and [iot_demo_https_s3_download_sync.c](https://github.com/aws/amazon-freertos/tree/master/demos/https/iot_demo_https_s3_download_sync.c), which contain platform-independent code. See @ref building_demo for instructions on building the HTTPS Client demo. - -

iot_demo_https_s3_download_sync.c

-@brief Synchronously download a file from S3 using a pre-signed URL. - -This demo will use @ref https_client_function_sendsync to download the file specified in S3. - -

iot_demo_https_s3_download_async.c

-@brief Asynchronously download a file from S3 using a pre-signed URL. - -This demo will use @ref https_client_function_sendasync to download the file specified in S3. - -See @subpage https_demo_config for configuration settings that change the behavior of the demo. - -@page https_demo_usage Demo Usage Instructions - -
    -
  1. - Ensure that you have permissions in your AWS account to access S3. - For information on AWS S3 please see: https://docs.aws.amazon.com/AmazonS3/latest/dev/Welcome.html -
    2. -
  2. - In an existing bucket or creating a new bucket upload the following file: - gettysburg.txt -
    3. -
  3. - Install and configured the AWS CLI. - For AWS CLI installation information please see: https://docs.aws.amazon.com/cli/latest/userguide/cli-chap-install.html - For AWS CLI configuration information please see: https://docs.aws.amazon.com/cli/latest/userguide/cli-chap-configure.html -
    4. -
  4. - Run [demos/https/presigned_url_gen.py](https://github.com/aws/amazon-freertos/tree/master/demos/https/presigned_urls_gen.py) with your s3 **bucket-name** and s3 object key **object-key**. - \code - python presigned_url_gen.py --bucket my-bucket --key object-key - \endcode - - Please see [demos/https/README.md](https://github.com/aws/amazon-freertos/tree/master/demos/https/README.md) for information on the required Python version and Python package dependencies. - - Example output: - \code - #define IOT_DEMO_HTTPS_PRESIGNED_GET_URL https://my-bucket.s3.amazonaws.com/object-key.txt?AWSAccessKeyId=AAAAAAAAAAAAAAAAAAAA&Expires=1560555644&Signature=SomeHash12345UrlABcdEFgfIjK%3D - #define IOT_DEMO_HTTPS_PRESIGNED_PUT_URL https://my-bucket.s3.amazonaws.com/object-key.txt?AWSAccessKeyId=ABABABABABABABABABAB&Expires=1560555644&Signature=SomeHash12345UrlLMnmOPqrStUvW - \endcode - - Paste this output to iot_config.h. -
    -
    - Note: - If your bucket is less than 24 hours old, then you will need to append the region the bucket was created in to the pre-signed URL: - \code - https://my-bucket.s3-.amazonaws.com/object-key.txt?AWSAccessKeyId=AAAAAAAAAAAAAAAAAAAA&Expires=1560555644&Signature=SomeHash12345UrlABcdEFgfIjK%3D - \endcode - Example: - \code - https://my-bucket.s3-us-west-2.amazonaws.com/object-key.txt?AWSAccessKeyId=AAAAAAAAAAAAAAAAAAAA&Expires=1560555644&Signature=SomeHash12345UrlABcdEFgfIjK%3D - \endcode - Please see https://aws.amazon.com/premiumsupport/knowledge-center/s3-http-307-response/ for more information. -
    5. -
  5. - Paste your RSA-2048 or ECC-P256 keys into [aws_clientcredential_keys.h](https://github.com/aws/amazon-freertos/blob/master/demos/include/aws_clientcredential_keys.h). This is needed to for the TLS handshake with the AWS S3 HTTP Server. -
    6. -
  6. - Enable the Synchronous download demo by defining @ref CONFIG_HTTPS_SYNC_DOWNLOAD_DEMO_ENABLED in aws_demo_config.h: - \code - /* To run a particular demo you need to define one of these. - * Only one demo can be configured at a time - * - * CONFIG_MQTT_DEMO_ENABLED - * CONFIG_SHADOW_DEMO_ENABLED - * CONFIG_GREENGRASS_DISCOVERY_DEMO_ENABLED - * CONFIG_TCP_ECHO_CLIENT_DEMO_ENABLED - * CONFIG_DEFENDER_DEMO_ENABLED - * CONFIG_POSIX_DEMO_ENABLED - * CONFIG_OTA_UPDATE_DEMO_ENABLED - * CONFIG_HTTPS_SYNC_DOWNLOAD_DEMO_ENABLED - * CONFIG_HTTPS_ASYNC_DOWNLOAD_DEMO_ENABLED - * - * These defines are used in iot_demo_runner.h for demo selection */ - - #define CONFIG_HTTPS_SYNC_DOWNLOAD_DEMO_ENABLED - \endcode -
    7. -
  7. - See @ref building_demo for instructions on building the demo. - A successful output looks like this: - \code - 11 558 [iot_thread] [INFO ][INIT][557] SDK successfully initialized. - 12 558 [iot_thread] [INFO ][DEMO][558] Successfully initialized the demo. Network type for the demo: 4 - 13 558 [iot_thread] [INFO ][DEMO][558] S3 Download demo using pre-signed URL: https://my-bucket.s3.amazonaws.com/object-key.txt?AWSAccessKeyId=AAAAAAAAAAAAAAAAAAAA&Expires=1560555644&Signature=SomeHash12345UrlABcdEFgfIjK%3D - 14 2880 [NetRecv] [ERROR][NET][2880] Error 0 while receiving data. - 15 2880 [NetRecv] [WARN ][NET][2880] Receive requested 760 bytes, but 400 bytes received instead. - 16 2880 [iot_thread] [INFO ][DEMO][2880] Now requesting Range: bytes=0-511. - 17 2920 [iot_thread] [INFO ][DEMO][2920] Response return code: 206 - 18 2920 [iot_thread] [INFO ][DEMO][2920] Response Body: - Four score and seven years ago our fathers brought forth on this continent, a new nation, conceived in Liberty, and dedicated to the proposition that all men are created equal. - - Now we are engaged in a great civil war, testing whether that nation, or any nation so conceived and so dedicated, can long endure. We are met on a great battle-field of that war. We have come to dedicate a portion of that field, as a final resting place for those who here gave their lives that that nation might live. It is altoge - 19 2920 [iot_thread] [INFO ][DEMO][2920] Downloaded 512/1517 - 20 2920 [iot_thread] [INFO ][DEMO][2920] Now requesting Range: bytes=512-1023. - 21 2979 [iot_thread] [INFO ][DEMO][2979] Response return code: 206 - 22 2979 [iot_thread] [INFO ][DEMO][2979] Response Body: - ther fitting and proper that we should do this. - - But, in a larger sense, we can not dedicate -- we can not consecrate -- we can not hallow -- this ground. The brave men, living and dead, who struggled here, have consecrated it, far above our poor power to add or detract. The world will little note, nor long remember what we say here, but it can never forget what they did here. It is for us the living, rather, to be dedicated here to the unfinished work which they who fought here have thus far so nobly adv - 23 2979 [iot_thread] [INFO ][DEMO][2979] Downloaded 1024/1517 - 24 2979 [iot_thread] [INFO ][DEMO][2979] Now requesting Range: bytes=1024-1516. - 25 5019 [NetRecv] [ERROR][NET][5019] Error 0 while receiving data. - 26 5019 [NetRecv] [WARN ][NET][5019] Receive requested 159 bytes, but 140 bytes received instead. - 27 5019 [iot_thread] [INFO ][DEMO][5019] Response return code: 206 - 28 5019 [iot_thread] [INFO ][DEMO][5019] Response Body: - anced. It is rather for us to be here dedicated to the great task remaining before us -- that from these honored dead we take increased devotion to that cause for which they gave the last full measure of devotion -- that we here highly resolve that these dead shall not have died in vain -- that this nation, under God, shall have a new birth of freedom -- and that government of the people, by the people, for the people, shall not perish from the earth. - - Abraham Lincoln - November 19, 1863 - 29 5019 [iot_thread] [INFO ][DEMO][5019] Downloaded 1517/1517 - 30 5058 [iot_thread] [INFO ][DEMO][5058] Demo completed successfully. - 31 5060 [iot_thread] [INFO ][INIT][5060] SDK cleanup done. - \endcode -
    8. -
  8. - Enable the Asynchronous download demo by defining either @ref CONFIG_HTTPS_ASYNC_DOWNLOAD_DEMO_ENABLED in aws_demo_config.h: - \code - /* To run a particular demo you need to define one of these. - * Only one demo can be configured at a time - * - * CONFIG_MQTT_DEMO_ENABLED - * CONFIG_SHADOW_DEMO_ENABLED - * CONFIG_GREENGRASS_DISCOVERY_DEMO_ENABLED - * CONFIG_TCP_ECHO_CLIENT_DEMO_ENABLED - * CONFIG_DEFENDER_DEMO_ENABLED - * CONFIG_POSIX_DEMO_ENABLED - * CONFIG_OTA_UPDATE_DEMO_ENABLED - * CONFIG_HTTPS_SYNC_DOWNLOAD_DEMO_ENABLED - * CONFIG_HTTPS_ASYNC_DOWNLOAD_DEMO_ENABLED - * - * These defines are used in iot_demo_runner.h for demo selection */ - - #define CONFIG_HTTPS_ASYNC_DOWNLOAD_DEMO_ENABLED - \endcode -
    9. -
  9. - See @ref building_demo for instructions on building the demo. - A successful output looks like this: - - \code - 11 682 [iot_thread] [INFO ][INIT][682] SDK successfully initialized. - 12 682 [iot_thread] [INFO ][DEMO][682] Successfully initialized the demo. Network type for the demo: 4 - 13 682 [iot_thread] [INFO ][DEMO][682] S3 Download demo using pre-signed URL: https://my-bucket.s3.amazonaws.com/object-key.txt?AWSAccessKeyId=AAAAAAAAAAAAAAAAAAAA&Expires=1560555644&Signature=SomeHash12345UrlABcdEFgfIjK%3D - 14 2977 [NetRecv] [ERROR][NET][2977] Error 0 while receiving data. - 15 2977 [NetRecv] [WARN ][NET][2977] Receive requested 768 bytes, but 400 bytes received instead. - 16 2977 [iot_thread] [INFO ][DEMO][2977] Inside of the append header callback for part bytes=0-511 - 17 3018 [NetRecv] [INFO ][DEMO][3018] Inside of the read ready callback for part bytes=0-511 with network return code: 0 - 18 3018 [NetRecv] [INFO ][DEMO][3018] Response return code: 206 for bytes=0-511 - 19 3018 [NetRecv] [INFO ][DEMO][3018] Response Body for bytes=0-511: - Four score and seven years ago our fathers brought forth on this continent, a new nation, conceived in Liberty, and dedicated to the proposition that all men are created equal. - - Now we are engaged in a great civil war, testing whether that nation, or any nation so conceived and so dedicated, can long endure. We are met on a great battle-field of that war. We have come to dedicate a portion of that field, as a final resting place for those who here gave their lives that that nation might live. It is altoge - 20 3018 [iot_thread] [INFO ][DEMO][3018] Inside of the append header callback for part bytes=512-1023 - 21 3018 [NetRecv] [INFO ][DEMO][3018] Part bytes=0-511 has been fully processed. - 22 3018 [NetRecv] [INFO ][DEMO][3018] Downloaded: 512/1517 - 23 3078 [NetRecv] [INFO ][DEMO][3078] Inside of the read ready callback for part bytes=512-1023 with network return code: 0 - 24 3078 [NetRecv] [INFO ][DEMO][3078] Response return code: 206 for bytes=512-1023 - 25 3078 [NetRecv] [INFO ][DEMO][3078] Response Body for bytes=512-1023: - their fitting and proper that we should do this. - - But, in a larger sense, we can not dedicate -- we can not consecrate -- we can not hallow -- this ground. The brave men, living and dead, who struggled here, have consecrated it, far above our poor power to add or detract. The world will little note, nor long remember what we say here, but it can never forget what they did here. It is for us the living, rather, to be dedicated here to the unfinished work which they who fought here have thus far so nobly adv - 26 3078 [iot_thread] [INFO ][DEMO][3078] Inside of the append header callback for part bytes=1024-1516 - 27 3079 [NetRecv] [INFO ][DEMO][3079] Part bytes=512-1023 has been fully processed. - 28 3079 [NetRecv] [INFO ][DEMO][3079] Downloaded: 1024/1517 - 29 3118 [NetRecv] [INFO ][DEMO][3118] Inside of the read ready callback for part bytes=1024-1516 with network return code: 0 - 30 5118 [NetRecv] [ERROR][NET][5118] Error 0 while receiving data. - 31 5118 [NetRecv] [WARN ][NET][5118] Receive requested 151 bytes, but 132 bytes received instead. - 32 5118 [NetRecv] [INFO ][DEMO][5118] Response return code: 206 for bytes=1024-1516 - 33 5118 [NetRecv] [INFO ][DEMO][5118] Response Body for bytes=1024-1516: - anced. It is rather for us to be here dedicated to the great task remaining before us -- that from these honored dead we take increased devotion to that cause for which they gave the last full measure of devotion -- that we here highly resolve that these dead shall not have died in vain -- that this nation, under God, shall have a new birth of freedom -- and that government of the people, by the people, for the people, shall not perish from the earth. - - Abraham Lincoln - November 19, 1863 - 34 5118 [NetRecv] [INFO ][DEMO][5118] Part bytes=1024-1516 has been fully processed. - 35 5118 [NetRecv] [INFO ][DEMO][5118] Downloaded: 1517/1517 - 36 5177 [iot_thread] [INFO ][DEMO][5177] Demo completed successfully. - 37 5179 [iot_thread] [INFO ][INIT][5179] SDK cleanup done. - \endcode - -
    10. -
- -Note: - Please note that the buffer for printing may be smaller than 512 characters and the printed received response body may be truncated.
- "[NetRecv] [WARN ][NET][2977] Receive requested 768 bytes, but 400 bytes received instead." is OK because the library requests from the network interface the full size of the header buffer or body buffer. - -*/ - -/** -@config_page{https_demo,Demo} -@config_brief{https_demo,HTTP Client demo,demos} - -@section IOT_DEMO_HTTPS_PRESIGNED_GET_URL -@brief Presigned URL for AWS S3 GET Object access. - -This is generated using the script demos/https/presigned_url_gen.py. demos/https/README.md explains how to use the script. - -@configpossible Presigned URL of the form: `https://my-bucket.s3.amazonaws.com/object-key.txt?AWSAccessKeyId=AAAAAAAAAAAAAAAAAAAA&Expires=1560555644&Signature=SomeHash12345UrlABcdEFgfIjK%3D`.
-@configdefault `"Please configure a presigned GET URL in iot_config.h."` - -@section IOT_DEMO_HTTPS_PORT -@brief The port number for the TLS connection to AWS S3's HTTP server. - -@configpossible Any positive integer up to 2^16.
-@configdefault `443` - -@section IOT_DEMO_HTTPS_TRUSTED_ROOT_CA -@brief The trusted root CA needed to connected to AWS S3's HTTP server. - -@configpossible A valid PEM encoded certificate string.
-@configdefault The Baltimore Cybertrust root CA. - -@section IOT_DEMO_HTTPS_CONN_BUFFER_SIZE -@brief The size of the static user buffer to store the HTTP Client connection context. - -Size in bytes of the User Buffer used to store the internal connection context. The size presented here accounts for - storage of the internal connection context. The minimum size can be found in @ref connectionUserBufferMinimumSize. - -@configpossible Any positive integer.
-@configdefault `400` - -@section IOT_DEMO_HTTPS_REQ_USER_BUFFER_SIZE -@brief The size of the static user buffer to store the HTTP Client request context and HTTP formatted request headers. - -Size in bytes of the user buffer used to store the internal request context and HTTP request header lines. - The size presented here accounts for the storage of the internal context, the first request line in the HTTP - formatted header and extra headers. The minimum size can be found in @ref requestUserBufferMinimumSize. Keep in mind that this @ref requestUserBufferMinimumSize does not include the size of the - path in the request line. The path could be well over 100 characters long as it includes not only the object key name - in S3, but also the query following. The query following has the AWSAccessKeyId, the expiration time, and the - AWS Signature Version 4 signature. - -@configpossible Any positive integer.
-@configdefault `512` - -@section IOT_DEMO_HTTPS_RESP_USER_BUFFER_SIZE -@brief The size of the static user buffer to store the HTTP Client response context and HTTP formatted response headers. - -Size in bytes of the user buffer used to store the internal response context and the HTTP response header lines. - The size presented here accounts for the storage of the internal context, the first request line in the HTTP - formatted header and extra headers. The minimum can be found in @ref requestUserBufferMinimumSize. - Keep in mind that if the headers from the response do not all fit into this buffer, then the rest of the headers - will be discarded. The minimum size can be found in @ref responseUserBufferMinimumSize. - -@configpossible Any positive integer.
-@configdefault `1024` - -@section IOT_DEMO_HTTPS_RESP_BODY_BUFFER_SIZE -@brief The size of the static buffer to store an increment of the response body. - -Size in bytes of the buffer used to store the response body (parts of it). This should be greater than or equal to - the size of the file we want to download - -@configpossible Any positive integer.
-@configdefault `512` - -@section IOT_DEMO_HTTPS_CONNECTION_RETRY_WAIT_MS -@brief Time to wait in milliseconds before retrying the HTTPS Connection. - -A connection is only attempted again if @ref IOT_HTTPS_CONNECTION_ERROR is returned from IotHttpsClient_Connect(). This -indicates an error in the network layer. To view network errors update @ref IOT_LOG_LEVEL_NETWORK to @ref IOT_LOG_ERROR -in iot_config.h. - -@configpossible Any positive integer. -@configdefault `3000` - -@section IOT_DEMO_HTTPS_CONNECTION_NUM_RETRY -@brief Number of times to retry the HTTPS connection. - -A connection is only attempted again if @ref IOT_HTTPS_CONNECTION_ERROR is returned from IotHttpsClient_Connect(). This -indicates an error in the network layer. To view network errors update @ref IOT_LOG_LEVEL_NETWORK to @ref IOT_LOG_ERROR -in iot_config.h. - -@configpossible Any positive integer. -@configdefault `3` - -

Asynchronous Download Demo specific configurations:

-These configurations apply only to [iot_demo_https_s3_download_async.c](https://github.com/aws/amazon-freertos/tree/master/demos/https/iot_demo_https_s3_download_async.c). - -@section IOT_HTTPS_DEMO_MAX_ASYNC_REQUESTS -@brief The maximum number of inflight asynchronous requests. - -This configures the total number of requests in the pool of HTTPS Client library configurations and handles. In order to send - a request asynchronously the memory for both the request buffers and the response buffers must not be shared between - other asynchronous requests on the same connection. You can reuse the buffer only after the request/response process - has been finished. It is finished when the responseCompleteCallback() is invoked. We create a pool of memory so that - all available requests in the pool can be scheduled right away without over-writing each other. - -@configpossible Any positive integer.
-@configdefault `3` - -@section IOT_HTTPS_DEMO_ASYNC_TIMEOUT_MS -@brief Timeout in milliseconds to wait for all asynchronous requests to finish. - -This timeout starts when the last @ref IOT_HTTPS_DEMO_MAX_ASYNC_REQUESTS sent have been scheduled. - -@configpossible Any positive integer.
-@configdefault `300000` -*/ - -/** -@page https_tests Tests -@brief Tests written for the HTTPS Client library. - -The HTTPS Client tests reside in the `tests` directory. They are divided into the following subdirectories: -- `access`: Helper files that allow access to internal variables and functions of the HTTPS Client library. -- `system`: HTTPS Client integration testing. These tests require a network connection. -- `unit`: HTTPS Client unit tests. These tests do not require a network connection. - -See @subpage https_tests_config for configuration settings that change the behavior of the tests. - -The current HTTPS Client tests use the [Unity test framework](http://www.throwtheswitch.org/unity/). See @ref building_tests for a guide on running the tests. -*/ - -/** -@config_page{https_tests,Test} -@config_brief{https_tests,HTTPS Client tests,tests} - -@section IOT_TEST_HTTPS_SERVER_HOST_NAME -@brief The HTTP server used for this test. - -This server needs to accept methods HEAD, GET, POST, and PUT. This server needs to send some data on a GET request. It can be a simple HTTP echo server. - -@configpossible Any server host name string. This host name must not include "https://" or "http://" in the name.
-@configdefault `"httpbin.org"` - -@section IOT_TEST_HTTPS_PORT -@brief The socket port number of the server to connect to. - -@configpossible Any positive integer up to 2^16.
-@configdefault `443` - -@section IOT_TEST_HTTPS_ALPN_PROTOCOLS -@brief APLN protocol string if necessary to connect to a secure testing server configured in @ref IOT_TEST_HTTPS_SERVER_HOST_NAME. - -This is a comma separated list of protocol. Please see [Transport Layer Security (TLS) Application-Layer Protocol Negotiation Extension](https://tools.ietf.org/html/rfc7301) for more information. - -@configpossible A comma separated string of ALPN protocol names or NULL. An empty string is not allowed.
-@configdefault `NULL` - -@section IOT_TEST_HTTPS_ROOT_CA -@brief Root certificate authority to verify the server that the HTTPS_Client_System tests are connecting to. - -@configpossible A valid PEM encoded certificate string.
-@configdefault `NULL` - -@section IOT_TEST_HTTPS_CLIENT_CERTIFICATE -@brief The client certificate used in TLS negotiation with the test HTTP server configured in @ref IOT_TEST_HTTPS_SERVER_HOST_NAME. - -With PKCS #11 provisioning of the keys these parameters are deprecated. - -@configpossible A valid RSA-2048 or ECC-P256 PEM encoded certificate string.
-@configdefault The system provisioned client certificate. - -@section IOT_TEST_HTTPS_CLIENT_PRIVATE_KEY -@brief The client private key used in TLS negotiation with the test HTTP server configured in @ref IOT_TEST_HTTPS_SERVER_HOST_NAME. - -With PKCS #11 provisioning of the keys these parameters are deprecated. - -@configpossible A valid RSA-2048 or ECC-P256 PEM encoded private key string.
-@configdefault The system provisioned client private key. - -@section IOT_TEST_HTTPS_SYNC_TIMEOUT_MS -@brief Timeout in milliseconds for tests that synchronously send HTTP requests. - -This timeout encompasses the waiting time for the both sending of the request and receiving the response. - -@configpossible Any positive integer.
-@configdefault `60000` - -@section IOT_TEST_HTTPS_ASYNC_TIMEOUT_MS -@brief Timeout in milliseconds for tests asynchronously send HTTP requests. - -This timeout encompasses the waiting time for the both sending of the request and receiving the response. - -@configpossible Any positive integer.
-@configdefault `60000` - -@section IOT_TEST_HTTPS_INITIAL_CONNECTION_RETRY_DELAY -@brief The initial delay in milliseconds that is doubled each retry of server connection. - -@configpossible Any positive integer.
-@configdefault `300` - -@section IOT_TEST_HTTPS_CONNECTION_NUM_RETRIES -@brief The amount of times to retry the server connection if it fails. - -@configpossible Any positive integer.
-@configdefault `3` - -*/ - -/** -@config_page{https} -@config_brief{HTTPS Client library} - -@section AWS_IOT_HTTPS_ENABLE_METRICS -@brief Set this to `1` to enable anonymous metrics reporting to AWS IoT. - -Metrics allow AWS IoT to prioritize engineering resources based on SDK usage. SDK name and version are reported; no personal or identifying information is reported. - -@configpossible `0` (metrics reporting disabled) or `1` (metrics reporting enabled)
-@configrecommended `1`
-@configdefault `1` - -@section IOT_HTTPS_USER_AGENT -@brief The name of the application type, operating system, software vendor, or software version of the requesting software agent. - -This configuration will dictate the header value written to required header field "User-Agent". This value is written when the request is initialized with @ref https_client_function_initializerequest. - -@configpossible Any string.
-@configdefault `"amazon-freertos"` - -@section IOT_LOG_LEVEL_HTTPS -@brief Set the log level of the HTTPS Client library. - -Log messages from the HTTPS Client library at or below this setting will be printed. - -@configpossible One of the @ref logging_constants_levels.
-@configdefault @ref IOT_LOG_LEVEL_GLOBAL; if that is undefined, then @ref IOT_LOG_NONE. - -@section IOT_HTTPS_MAX_FLUSH_BUFFER_SIZE -@brief The size of a buffer instantiated in stack to flush the socket of the rest of possible unread response. - -@configpossible Any positive integer.
-@configdefault `1024` - -@section IOT_HTTPS_RESPONSE_WAIT_MS -@brief The time in milliseconds to wait for a response from the network before timing out. - -@configpossible Any positive integer.
-@configdefault `1000` - -@section IOT_HTTPS_MAX_HOST_NAME_LENGTH -@brief The maximum length of the DNS resolvable host name string allowed to be configured in #IotHttpsConnectionInfo_t.pAddress. - -An array of this length is allocated on stack during @ref https_client_function_connect. - -@configpossible Any positive integer.
-@configrecommended It is recommended that this be less or equal to 255. 255 is the maximum host length according to FQDN.
-@configdefault `255` - -@section IOT_HTTPS_MAX_ALPN_PROTOCOLS_LENGTH -@brief The maximum length of the ALPN protocols names string allowed to be configured in #IotHttpsConnectionInfo_t.pAlpnProtocols. - -An array of this length is allocated on stack during @ref https_client_function_connect. - -@configpossible Any positive integer.
-@configdefault `255` - -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/linear_containers.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/linear_containers.txt deleted file mode 100644 index 4e10ba9..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/linear_containers.txt +++ /dev/null @@ -1,29 +0,0 @@ -/** -@mainpage -@anchor linear_containers -@brief Linked list and queue data structures and functions.

- -This library provides linear containers, such as linked lists and queues. Linked lists and queues may hold any data type that contain an #IotLink_t member. By default, these containers do not provide thread-safety. - -Currently, linear containers are implemented with `static inline` functions and have no dependencies other than C standard library types. -*/ - -/** -@config_page{linear_containers} -@config_brief{linear containers library} - -@section IOT_CONTAINERS_ENABLE_ASSERTS -@brief Set this to `1` to perform sanity checks when using linear containers. - -Asserts are useful for debugging, but should be disabled in production code. If this is set to `1`, @ref IotContainers_Assert can be defined to set the assert function; otherwise, the standard library's [assert](http://pubs.opengroup.org/onlinepubs/9699919799/functions/assert.html) function will be used. - -@configpossible `0` (asserts disabled) or `1` (asserts enabled)
-@configrecommended `1` when debugging; `0` in production code.
-@configdefault `0` - -@section IotContainers_Assert -@brief Assertion function used when @ref IOT_CONTAINERS_ENABLE_ASSERTS is `1`. - -@configpossible Any function with the same signature as the standard library's [assert](http://pubs.opengroup.org/onlinepubs/9699919799/functions/assert.html) function.
-@configdefault Standard library [assert](http://pubs.opengroup.org/onlinepubs/9699919799/functions/assert.html) function if @ref IOT_CONTAINERS_ENABLE_ASSERTS is `1`; otherwise, nothing. -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/logging.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/logging.txt deleted file mode 100644 index b11aef7..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/logging.txt +++ /dev/null @@ -1,120 +0,0 @@ -/** -@mainpage Logging -@anchor logging -@brief Generate and print log messages.

- -This library allows other libraries to generate and print log messages, which can aid in debugging. Log messages are printed by passing strings to one of the [logging functions]( @ref logging_functions). The features of this library include: -- [Configurable levels](@ref logging_constants_levels) for log messages and libraries. -- Automatic printing of log level, library name, and time with every message. The information printed with each message [may be customized](@ref IotLogConfig_t). -- A [function to print the contents of buffers](@ref logging_function_printbuffer) when using the [debug](@ref IOT_LOG_DEBUG) log level. This allows the contents of memory to be easily examined. - -@dependencies_section{logging} -@dependencies_brief{logging library} - -@dot "Logging direct dependencies" -digraph logging_dependencies -{ - node[shape=box, fontname=Helvetica, fontsize=10, style=filled]; - edge[fontname=Helvetica, fontsize=10]; - logging[label="Logging", fillcolor="#aed8a9ff"]; - subgraph - { - rank = same; - platform_clock[label="Clock", fillcolor="#e89025ff", URL="@ref platform_clock"]; - static_memory[label="Static memory", fillcolor="#e89025ff" URL="@ref static_memory"]; - } - standard_library[label="Standard library\nstdarg, stdbool, stddef,\nstdint, stdio, string", fillcolor="#d15555ff"]; - logging -> platform_clock; - logging -> static_memory [style="dashed", label=" if static memory only"]; - logging -> standard_library; -} -@enddot - -Currently, the logging library has the following dependencies: -- The [platform clock component](@ref platform_clock) for [generating the timestring](@ref platform_clock_function_gettimestring) to print in log messages. -- When @ref IOT_STATIC_MEMORY_ONLY is `1`, the logging library depends on the [platform static memory component](@ref static_memory) to allocate buffers for log messages. When @ref IOT_STATIC_MEMORY_ONLY is `0`, the logging library will default to using the standard library's [malloc](http://pubs.opengroup.org/onlinepubs/9699919799/functions/malloc.html) and [free](http://pubs.opengroup.org/onlinepubs/9699919799/functions/free.html) functions. The logging library's memory allocation functions [may always be overridden](@ref logging_config_memory). Note that the logging library will silently discard logs if it fails to allocate memory for the message. - -@section logging_setup_use Setup and use -@brief How to set up and use the logging library. - -The file iot_logging_setup.h should be included to configure logging for a single source file. Before including iot_logging_setup.h, the constants @ref _LIBRARY_LOG_LEVEL and @ref _LIBRARY_LOG_NAME must be defined. - -For example, to configure all the "SAMPLE" library to print all messages below the [info](@ref IOT_LOG_INFO) log level: - -@code{c} -// Print log messages up to the "info" level. -#define _LIBRARY_LOG_LEVEL IOT_LOG_INFO - -// Print library name "SAMPLE". -#define _LIBRARY_LOG_NAME "SAMPLE" - -// Including this header defines the logging macros using _LIBRARY_LOG_LEVEL and -// _LIBRARY_LOG_NAME. -#include "iot_logging_setup.h" - -int main( void ) -{ - // After including iot_logging_setup.h, the logging functions can be used. - IotLogError( "Error." ); // Will be printed because IOT_LOG_ERROR <= _LIBRARY_LOG_LEVEL - IotLogWarn( "Warning. " ); // Will be printed because IOT_LOG_WARN <= _LIBRARY_LOG_LEVEL - IotLogInfo( "Info." ); // Will be printed because IOT_LOG_INFO <= _LIBRARY_LOG_LEVEL - IotLogDebug( "Debug." ); // Will not be printed because IOT_LOG_DEBUG > _LIBRARY_LOG_LEVEL - - return 0; -} -@endcode - -The code above will print something like the following: - -@code -[ERROR][SAMPLE][2018-01-01 12:00:00] Error. -[WARN ][SAMPLE][2018-01-01 12:00:00] Warning. -[INFO ][SAMPLE][2018-01-01 12:00:00] Info. -@endcode -*/ - -/** -@config_page{logging} -@config_brief{logging library} - -@section _LIBRARY_LOG_LEVEL -@brief The log level for a source file. - -Sets the log level for a single source file. A log message will only be printed if its level is less than this setting. - -Both this constant and @ref _LIBRARY_LOG_NAME must be defined before including iot_logging_setup.h. See @ref logging_setup_use for an example on how to use this setting. - -@configpossible One of the @ref logging_constants_levels. -@note This value must be defined if iot_logging_setup.h is included. The library will not provide a default value for this setting. - -@section _LIBRARY_LOG_NAME -@brief The library name printed in log messages. - -Sets the library name for a single source file. By default, all log messages contain the library name. The library name may be disabled for a single log message by setting passing an #IotLogConfig_t with [hideLibraryName](@ref IotLogConfig_t.hideLibraryName) set to `true`. - -Both this constant and @ref _LIBRARY_LOG_LEVEL must be defined before including iot_logging_setup.h. See @ref logging_setup_use for an example on how to use this setting. - -@configpossible Any string. -@note This value must be defined if iot_logging_setup.h is included. The library will not provide a default value for this setting. - -@section IotLogging_Puts -@brief Logging library output function. - -The logging library calls this function to print strings. Like the standard library's [puts](http://pubs.opengroup.org/onlinepubs/9699919799/functions/puts.html) function, this function should write a newline after the string, as log messages may not end with a newline. This setting provided the flexibility to log over different channels. For example, if no `stdout` is available, this function may be set to log over other channels such as UART or a network. - -Although this function is supposed to return an `int`, the logging library does not check its return value. Therefore, a function with no return type is also acceptable. - -@configpossible Any function with the same parameter as the standard library's [puts](http://pubs.opengroup.org/onlinepubs/9699919799/functions/puts.html) function. Since the logging library does not check the return value of this function, the return type may differ from [puts](http://pubs.opengroup.org/onlinepubs/9699919799/functions/puts.html).
-@configdefault Standard library [puts](http://pubs.opengroup.org/onlinepubs/9699919799/functions/puts.html) function. - -@section logging_config_memory Memory allocation -@brief If @ref IOT_STATIC_MEMORY_ONLY is `1`, then the following functions must be re-implemented for the logging library. -- #IotLogging_Malloc
- @copybrief IotLogging_Malloc -- #IotLogging_Free
- @copybrief IotLogging_Free -- #IotLogging_StaticBufferSize
- @copybrief IotLogging_StaticBufferSize - -Note that the logging library will silently discard logs if it fails to allocate memory for the message. -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/mqtt.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/mqtt.txt deleted file mode 100644 index c03bbea..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/mqtt.txt +++ /dev/null @@ -1,309 +0,0 @@ -/** -@mainpage -@anchor mqtt -@brief MQTT 3.1.1 client library. - -> MQTT stands for MQ Telemetry Transport. It is a publish/subscribe, extremely simple and lightweight messaging protocol, designed for constrained devices and low-bandwidth, high-latency or unreliable networks. The design principles are to minimise network bandwidth and device resource requirements whilst also attempting to ensure reliability and some degree of assurance of delivery. These principles also turn out to make the protocol ideal of the emerging "machine-to-machine" (M2M) or "Internet of Things" world of connected devices, and for mobile applications where bandwidth and battery power are at a premium. - - — Official description of MQTT from [mqtt.org](http://mqtt.org)
- -This MQTT library implements a subset of the MQTT 3.1.1 standard for compatibility with the [AWS IoT MQTT server](https://docs.aws.amazon.com/iot/latest/developerguide/protocols.html#mqtt). It is also compatible with other MQTT servers. Features of this library include: -- Both fully asynchronous and blocking API functions. -- Thread-aware and parallelizable for high throughput. -- Scalable performance and footprint. The [configuration settings](@ref mqtt_config) allow this library to be tailored to a system's resources. - -@attention Currently, this library does not support QoS 2 MQTT messages. - -@dependencies_section{mqtt} -@dependencies_brief{MQTT library} - -@dot "MQTT direct dependencies" -digraph mqtt_dependencies -{ - node[shape=box, fontname=Helvetica, fontsize=10, style=filled]; - edge[fontname=Helvetica, fontsize=10]; - subgraph - { - mqtt[label="MQTT", fillcolor="#cc00ccff"]; - } - subgraph - { - node[fillcolor="#aed8a9ff"]; - rank = same; - linear_containers[label="List/Queue", URL="@ref linear_containers"]; - logging[label="Logging", URL="@ref logging"]; - static_memory[label="Static memory", URL="@ref static_memory"]; - } - subgraph - { - rank = same; - platform_threads[label="Thread management", fillcolor="#e89025ff", URL="@ref platform_threads"]; - platform_clock[label="Clock", fillcolor="#e89025ff", URL="@ref platform_clock"]; - platform_network[label="Network", fillcolor="#e89025ff", URL="@ref platform_network"]; - } - mqtt -> linear_containers; - mqtt -> logging [label=" if logging enabled", style="dashed"]; - mqtt -> platform_threads; - mqtt -> platform_clock; - mqtt -> platform_network; - mqtt -> static_memory [label=" if static memory only", style="dashed"]; - logging -> platform_clock; - logging -> static_memory [label=" if static memory only", style="dashed"]; -} -@enddot - -Currently, the MQTT library has the following dependencies: -- The queue library for maintaining the data structures for managing in-progress MQTT operations. -- The logging library may be used if @ref IOT_LOG_LEVEL_MQTT is not #IOT_LOG_NONE. -- The platform layer provides an interface to the operating system for thread management, clock functions, networking, etc. - -In addition to the components above, the MQTT library also depends on C standard library headers. -*/ - -/** -@page mqtt_design Design -@brief Architecture behind the MQTT library. - -@image html mqtt_design_typicaloperation.png width=100% -*/ - -/** -@page mqtt_demo Demo -@brief The MQTT demo demonstrates usage of the MQTT library. - -The MQTT demo demonstrates the subscribe-publish workflow of MQTT. After subscribing to multiple topic filters, it publishes [bursts](@ref IOT_DEMO_MQTT_PUBLISH_BURST_SIZE) of data to various topic names. The demo then waits for all messages in a burst to be received on a topic filter. As each message arrives, the demo publishes an acknowledgement message back to the MQTT server. It repeats this cycle @ref IOT_DEMO_MQTT_PUBLISH_BURST_COUNT times. - -@image html mqtt_demo.png "MQTT Demo Workflow" width=80% - -See @subpage mqtt_demo_config for configuration settings that change the behavior of the demo. - -The main MQTT demo file is iot_demo_mqtt.c, which contains platform-independent code. See @ref building_demo for instructions on building the MQTT demo. -*/ - -/** -@page mqtt_tests Tests -@brief Tests written for the MQTT library. - -The MQTT tests reside in the `tests/mqtt` directory. They are divided into the following subdirectories: -- `access`: Helper files that allow access to internal variables and functions of the MQTT library. -- `system`: MQTT system and stress tests. These tests require a network connection. Stress tests may run for a long time, so they are not run unless the command line option `-l` is given to the test executable. -- `unit`: MQTT unit tests. These tests do not require a network connection. - -See @subpage mqtt_tests_config for configuration settings that change the behavior of the tests. - -The current MQTT tests use the [Unity test framework](http://www.throwtheswitch.org/unity/) and only run on POSIX systems. See @ref building_tests for a guide on running the tests. -*/ - -/** -@config_page{mqtt_tests,Test} -@config_brief{mqtt_tests,MQTT tests,tests} - -@section IOT_TEST_MQTT_CLIENT_IDENTIFIER -@brief The MQTT client identifier to use for the tests. - -No two clients may connect using the same client identifier simultaneously. If this setting is undefined, the tests will generate a unique client identifier to use. - -@configpossible Any string representing an MQTT client identifier. MQTT client identifiers may be subject to certain constraints; for example, servers are not obligated to accept client identifiers longer than 23 characters or client identifiers containing non-alphanumeric characters.
-@configdefault The tests will generate a unique client identifier if this setting is undefined. - -@section IOT_TEST_MQTT_MOSQUITTO -@brief Test the MQTT library against the [public Mosquitto test server](https://test.mosquitto.org/). - -When this setting is `1`, the MQTT tests will be built to test against an unsecured [public Mosquitto test server](https://test.mosquitto.org/). This allows the MQTT library to be tested against a fully-compliant MQTT server. Because the connection is unsecured, no credentials are needed for testing against Mosquitto. - -@configpossible `0` (use AWS IoT MQTT server) or `1` (use public Mosquitto server)
-@configdefault `0` - -
The settings below only affect the [system](@ref iot_tests_mqtt_system.c) and [stress](@ref iot_tests_mqtt_stress.c) tests.
- -@section IOT_TEST_MQTT_TIMEOUT_MS -@brief Timeout in milliseconds for MQTT operations. - -This value will be passed as `timeoutMs` to all calls to @ref mqtt_function_wait (and similar functions requiring a timeout). Ensure that this value is large enough to accommodate delays caused by the network. - -@configpossible Any non-negative integer.
-@configrecommended This setting should be at least `1000`.
-@configdefault `5000` - -@section IOT_TEST_MQTT_TOPIC_PREFIX -@brief The string prepended to topic filters. - -This string will be prepended as the common part of topic filters as a way to differentiate MQTT traffic generated by the tests. - -@configpossible Any string that adheres to the [specification for MQTT client identifiers](http://docs.oasis-open.org/mqtt/mqtt/v3.1.1/os/mqtt-v3.1.1-os.html#_Toc385349242).
-@configdefault `"iotmqtttest"` - -
The settings below only affect the [stress](@ref iot_tests_mqtt_stress.c) tests.
- -@section IOT_TEST_MQTT_SHORT_KEEPALIVE_INTERVAL_S -@brief The keep-alive interval for the stress tests. - -MQTT PINGREQ packets will be sent at this interval. - -@configpossible Any positive integer.
-@configrecommended This value should be the shortest keep-alive interval supported by the connection.
-@configdefault `30` when using the AWS IoT MQTT server; `5` otherwise - -@section IOT_TEST_MQTT_RETRY_MS -@brief The value of #IotMqttPublishInfo_t.retryMs used in the stress tests. - -Any lost publish messages will be retransmitted at this time. - -@configpossible Any positive integer.
-@configrecommended This setting should be at least `250` to avoid excessive network congestion caused by retransmissions.
-@configdefault `350` - -@section IOT_TEST_MQTT_RETRY_LIMIT -@brief The value of #IotMqttPublishInfo_t.retryLimit used in the stress tests. - -Any lost publish messages will be retried up to this limit. - -@configpossible Any positive integer.
-@configdefault `32` - -@section IOT_TEST_MQTT_DECONGEST_S -@brief The time to wait for resources to be freed. - -Should an MQTT operation fail due to insufficient resources (such as a return value of @ref IOT_MQTT_NO_MEMORY), the test thread will sleep for this amount to time before retrying to wait for resources to be freed. Larger values for this setting provide a higher change for a successful retry, but will cause the tests to run longer. - -@configpossible Any positive integer.
-@configdefault `30` - -@section IOT_TEST_MQTT_THREADS -@brief The number of threads to use in the stress tests. - -The number of threads to spawn for the stress tests. Up to @ref IOT_TEST_MQTT_THREADS `*` @ref IOT_TEST_MQTT_PUBLISHES_PER_THREAD publish messages are sent by stress test. - -@configpossible Any positive integer.
-@configdefault `16` - -@section IOT_TEST_MQTT_PUBLISHES_PER_THREAD -@brief The number of publish messages each thread in the stress test should send. - -Up to @ref IOT_TEST_MQTT_THREADS `*` @ref IOT_TEST_MQTT_PUBLISHES_PER_THREAD publish messages are sent by stress test. - -@configpossible Any non-negative integer.
-@configdefault When @ref IOT_STATIC_MEMORY_ONLY is `1`, this value defaults to @ref IOT_MQTT_MAX_IN_PROGRESS_OPERATIONS. Otherwise, it defaults to `100`. -*/ - -/** -@config_page{mqtt_demo,Demo} -@config_brief{mqtt_demo,MQTT demo,demos} - -@section IOT_DEMO_MQTT_TOPIC_PREFIX -@brief The string prepended to topic filters in the demo. - -The string will be prepended as the common part of topic filters as a way to differentiate MQTT traffic generated by the demo. - -@configpossible Any string that adheres to the [specification for MQTT client identifiers](http://docs.oasis-open.org/mqtt/mqtt/v3.1.1/os/mqtt-v3.1.1-os.html#_Toc385349242).
-@configdefault `"iotmqttdemo"` - -@section IOT_DEMO_MQTT_PUBLISH_BURST_SIZE -@brief The number of messages published in each burst. - -Messages in a burst are rapidly published. After a complete burst is published, the demo waits for the messages to be received on a subscription topic filter. This value may be increased for higher throughput, at the expense of an increased chance of dropped messages. The MQTT demo publishes a total of @ref IOT_DEMO_MQTT_PUBLISH_BURST_SIZE `*` @ref IOT_DEMO_MQTT_PUBLISH_BURST_COUNT messages. - -@configpossible Any positive integer.
-@configdefault `10` - -@section IOT_DEMO_MQTT_PUBLISH_BURST_COUNT -@brief The number of [publish bursts](@ref IOT_DEMO_MQTT_PUBLISH_BURST_SIZE) in this demo. - -Each burst will rapidly publish @ref IOT_DEMO_MQTT_PUBLISH_BURST_SIZE messages. After publishing, the demo will wait for the published messages to be received on a subscription topic filter. - -This setting can be increased for a longer demo. The MQTT demo publishes a total of @ref IOT_DEMO_MQTT_PUBLISH_BURST_SIZE `*` @ref IOT_DEMO_MQTT_PUBLISH_BURST_COUNT messages. - -@configpossible Any positive integer.
-@configdefault `10` -*/ - -/** -@config_page{mqtt} -@config_brief{MQTT library} - -@section IOT_MQTT_ENABLE_ASSERTS -@brief Set this to `1` to perform sanity checks when using the MQTT library. - -Asserts are useful for debugging, but should be disabled in production code. If this is set to `1`, @ref IotMqtt_Assert can be defined to set the assertion function; otherwise, the standard library's [assert](http://pubs.opengroup.org/onlinepubs/9699919799/functions/assert.html) function will be used. - -@configpossible `0` (asserts disabled) or `1` (asserts enabled)
-@configrecommended `1` when debugging; `0` in production code.
-@configdefault `0` - -@section AWS_IOT_MQTT_ENABLE_METRICS -@brief Set this to `1` to enable anonymous metrics reporting to AWS IoT. - -Metrics allow AWS IoT to prioritize engineering resources based on SDK usage. SDK name and version are reported; no personal or identifying information is reported. - -@configpossible `0` (metrics reporting disabled) or `1` (metrics reporting enabled)
-@configrecommended `1`
-@configdefault `1` -@note This setting is only in effect for [MQTT connections with AWS IoT](@ref IotMqttConnectInfo_t.awsIotMqttMode). Metrics are reported through [the MQTT username.](@ref IotMqttConnectInfo_t.pUserName) The MQTT library may overwrite any provided user name if metrics are enabled. - -@section IOT_MQTT_ENABLE_SERIALIZER_OVERRIDES -@brief Set this to `1` to allow the MQTT packet serializer and deserializer functions to be overridden. - -Serializer overrides allow the functions that generate and decode MQTT packets to be overridden. When this setting is `1`, each connection may have different serializer and deserializer functions. This allows the MQTT library to be used as a general-purpose transport library (with limitations). Currently, this setting is used to support MQTT over Bluetooth Low-Energy on Amazon FreeRTOS. See #IotMqttSerializer_t for a list of functions that can be overridden. If this setting is `1`, the serializer [initialization](@ref _IotMqtt_InitSerialize) and [cleanup](@ref _IotMqtt_CleanupSerialize) functions may be extended by defining `_IotMqtt_InitSerializeAdditional` and `_IotMqtt_CleanupSerializeAdditional`. These functions will be called along with the default serializer initialization and cleanup functions. They must have the following signatures: -@code{c} -#include - -// Returns true on success and false on failure. -bool _IotMqtt_InitSerializeAdditional( void ); -void _IotMqtt_CleanupSerializeAdditional( void ); -@endcode - -@configpossible `0` (serializer overrides disabled) or `1` (serializer overrides enabled)
-@configrecommended The default value is strongly recommended.
-@configdefault The default value of this setting depends on the platform. For example, when running on FreeRTOS with BLE support, this setting will be automatically enabled. Conversely, when running on Linux, this setting will be disabled. - -@section IOT_LOG_LEVEL_MQTT -@brief Set the log level of the MQTT library. - -Log messages from the MQTT library at or below this setting will be printed. - -@configpossible One of the @ref logging_constants_levels.
-@configdefault @ref IOT_LOG_LEVEL_GLOBAL; if that is undefined, then #IOT_LOG_NONE. - -@section IOT_MQTT_RESPONSE_WAIT_MS -@brief A "reasonable amount of time" to wait for keep-alive responses from the MQTT server. - -The MQTT spec states that if a response to a keep-alive request is not received within a "reasonable amount of time", the network connection should be closed. Since the meaning of "reasonable" depends heavily on use case, the amount of time to wait for keep-alive responses is defined by this setting. This setting is also used as the amount of time to wait for a final PUBACK to a QoS 1 PUBLISH message before returning #IOT_MQTT_RETRY_NO_RESPONSE. See #IotMqttPublishInfo_t for a description of QoS 1 PUBLISH retries. - -@configpossible Any positive integer.
-@configdefault `1000` - -@section IOT_MQTT_RETRY_MS_CEILING -@brief Controls the maximum [retry interval](@ref IotMqttPublishInfo_t.retryMs) of QoS 1 PUBLISH retransmissions. - -QoS 1 PUBLISH retransmissions follow a truncated exponential backoff strategy. The interval of time between retransmissions increases exponentially until @ref IOT_MQTT_RETRY_MS_CEILING (or the [retransmission limit)](@ref IotMqttPublishInfo_t.retryLimit) is reached, then increases by @ref IOT_MQTT_RETRY_MS_CEILING until the [retransmission limit](@ref IotMqttPublishInfo_t.retryLimit) is reached. - -@see #IotMqttPublishInfo_t for a detailed description of the QoS 1 PUBLISH retransmission strategy. - -@configpossible Any positive integer.
-@configdefault `60000` - -@section IotMqtt_Assert -@brief Assertion function used when @ref IOT_MQTT_ENABLE_ASSERTS is `1`. - -@configpossible Any function with the same signature as the standard library's [assert](http://pubs.opengroup.org/onlinepubs/9699919799/functions/assert.html) function.
-@configdefault Standard library [assert](http://pubs.opengroup.org/onlinepubs/9699919799/functions/assert.html) function if @ref IOT_MQTT_ENABLE_ASSERTS is `1`; otherwise, nothing. - -@section mqtt_config_memory Memory allocation -@brief If @ref IOT_STATIC_MEMORY_ONLY is `1`, then the following functions must be re-implemented for the MQTT library. -- #IotMqtt_MallocConnection
- @copybrief IotMqtt_MallocConnection -- #IotMqtt_FreeConnection
- @copybrief IotMqtt_FreeConnection -- #IotMqtt_MallocMessage
- @copybrief IotMqtt_MallocMessage -- #IotMqtt_FreeMessage
- @copybrief IotMqtt_FreeMessage -- #IotMqtt_MallocOperation
- @copybrief IotMqtt_MallocOperation -- #IotMqtt_FreeOperation
- @copybrief IotMqtt_FreeOperation -- #IotMqtt_MallocSubscription
- @copybrief IotMqtt_MallocSubscription -- #IotMqtt_FreeSubscription
- @copybrief IotMqtt_FreeSubscription -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/platform.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/platform.txt deleted file mode 100644 index e50dc1b..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/platform.txt +++ /dev/null @@ -1,212 +0,0 @@ -/** -@mainpage -@anchor platform -@brief The platform layer provides portability across different operating systems.

- -All system calls (including networking) used in this SDK's libraries go through a lightweight platform layer. The functions of the platform layer are intended to be easily implementable on a wide variety of operating systems. The current platform layer has the following components: -- @ref platform_clock
- @copybrief platform_clock -- @ref platform_threads
- @copybrief platform_threads -- @ref platform_network
- @copybrief platform_network - -All of the functions in each component will need to be implemented to port the libraries to a new platform. Currently, implementations exist for the following platforms: -Component | Supported platforms ---------- | ------------------- -@ref platform_clock | [POSIX](https://en.wikipedia.org/wiki/POSIX) -@ref platform_threads | [POSIX](https://en.wikipedia.org/wiki/POSIX) -@ref platform_network | [Berkeley sockets](https://en.wikipedia.org/wiki/Berkeley_sockets) + [OpenSSL](https://en.wikipedia.org/wiki/OpenSSL) + [POSIX](https://en.wikipedia.org/wiki/POSIX)
[Amazon FreeRTOS Secure Sockets](https://docs.aws.amazon.com/freertos/latest/userguide/secure-sockets.html) -*/ - -/** -@page platform_clock Clock -@brief @copybrief iot_clock.h - -The platform clock component provides other libraries with functions relating to timers and clocks. It interfaces directly with the operation system to provide: -- Clocks for reading the current time. -- Timers that create a notification thread when they expire. - -@dependencies_section{platform_clock} -@dependencies_brief{platform clock component} - -@dot "Clock direct dependencies" -digraph clock_dependencies -{ - node[shape=box, fontname=Helvetica, fontsize=10, style=filled]; - edge[fontname=Helvetica, fontsize=10]; - subgraph { rank=min; logging[label="Logging", fillcolor="#aed8a9ff" URL="@ref logging"]; } - subgraph - { - platform_clock[label="Clock", fillcolor="#e89025ff"]; - } - subgraph - { - rank = same; - rankdir = LR; - operating_system[label="Operating system", fillcolor="#999999ff"] - standard_library[label="Standard library\nstdbool, stddef, stdint", fillcolor="#d15555ff"]; - } - platform_clock -> operating_system; - platform_clock -> standard_library; - platform_clock -> logging [label=" if logging enabled", style="dashed"]; -} -@enddot - -Currently, the platform clock component has the following dependencies: -- The operating system must provide the necessary APIs to implement the clock component's functions. -- The logging library may be used if @ref IOT_LOG_LEVEL_PLATFORM is not #IOT_LOG_NONE. -*/ - -/** -@page platform_network Networking -@brief @copybrief iot_network.h - -The platform networking component provides other libraries with an abstraction for interacting with the network through an #IotNetworkInterface_t. Libraries that require the network will request an #IotNetworkInterface_t as a parameter and use those function pointers to access the network. This allows libraries to use different network stacks simultaneously. - -@dependencies_section{platform_network} -@dependencies_brief{platform networking component} - -@dot "Networking direct dependencies" -digraph network_dependencies -{ - node[shape=box, fontname=Helvetica, fontsize=10, style=filled]; - edge[fontname=Helvetica, fontsize=10]; - subgraph { rank=min; logging[label="Logging", fillcolor="#aed8a9ff", URL="@ref logging"]; } - subgraph - { - rank = same; - platform_network[label="Networking", fillcolor="#e89025ff"]; - } - subgraph - { - rank = same; - rankdir = LR; - operating_system[label="Operating system", fillcolor="#999999ff"]; - security_library[label="Security library", fillcolor="#999999ff"]; - standard_library[label="Standard library", fillcolor="#d15555ff"]; - } - platform_network -> operating_system; - platform_network -> security_library [label=" secured connection", style="dashed"]; - platform_network -> standard_library; - platform_network -> logging [label=" if logging enabled", style="dashed"]; - security_library -> operating_system; -} -@enddot - -Functions should be implemented against the system's network stack to match the signatures given in an #IotNetworkInterface_t. -- The operating system must provide the necessary networking APIs, such as a sockets API. -- A third-party security library is needed to encrypt secured connections. -- The logging library may be used if @ref IOT_LOG_LEVEL_PLATFORM is not @ref IOT_LOG_NONE. -*/ - -/** -@page platform_threads Thread Management -@brief @copybrief iot_threads.h - -The platform thread management component provides other libraries with functions relating to threading and synchronization. It interfaces directly with the operating system to provide: -- A function to create new threads. -- Synchronization mechanisms such as [mutexes](@ref IotMutex_t) and [counting semaphores](@ref IotSemaphore_t). - -@dependencies_section{platform_threads} -@dependencies_brief{platform thread management component} - -@dot "Thread management direct dependencies" -digraph threads_dependencies -{ - node[shape=box, fontname=Helvetica, fontsize=10, style=filled]; - edge[fontname=Helvetica, fontsize=10]; - subgraph { rank=min; logging[label="Logging", fillcolor="#aed8a9ff" URL="@ref logging"]; } - subgraph - { - platform_threads[label="Thread management", fillcolor="#e89025ff"]; - } - subgraph - { - rank = same; - operating_system[label="Operating system", fillcolor="#999999ff"] - standard_library[label="Standard library\nstdbool, stddef, stdint", fillcolor="#d15555ff"]; - } - platform_threads -> operating_system; - platform_threads -> standard_library; - platform_threads -> logging [label=" if logging enabled", style="dashed"]; -} -@enddot - -Currently, the platform thread management component has the following dependencies: -- The operating system must provide the necessary APIs to implement the [thread management functions](@ref platform_threads_functions). -- The logging library may be used if @ref IOT_LOG_LEVEL_PLATFORM is not #IOT_LOG_NONE. -*/ - -/** -@config_page{platform} -@config_brief{platform layer} - -@section IOT_LOG_LEVEL_PLATFORM -@brief Set the log level of all platform components except the [networking component](@ref platform_network). - -This setting overrides @ref IOT_LOG_LEVEL_GLOBAL for the platform layer components that it affects. All log messages with a level at or below this setting will be printed. The [platform networking component](@ref platform_network) is generally more verbose than others, so its logging is controlled separately by @ref IOT_LOG_LEVEL_NETWORK. - -@configpossible One of the @ref logging_constants_levels.
-@configdefault @ref IOT_LOG_LEVEL_GLOBAL; if that is undefined, then #IOT_LOG_NONE. - -@section IOT_LOG_LEVEL_NETWORK -@brief Set the log level of the [platform networking component](@ref platform_network). - -This setting overrides @ref IOT_LOG_LEVEL_GLOBAL for the [platform networking component](@ref platform_network). All log messages with a level at or below this setting will be printed. See @ref IOT_LOG_LEVEL_PLATFORM to set the log level of other platform components. - -@configpossible One of the @ref logging_constants_levels.
-@configdefault @ref IOT_LOG_LEVEL_GLOBAL; if that is undefined, then #IOT_LOG_NONE. - -@section platform_config_memory Memory allocation -@brief Memory allocation function overrides for the platform layer. - -Some platform layers are not affected by @ref IOT_STATIC_MEMORY_ONLY. Currently, the following platform implementations require memory allocation: -- POSIX
- This implementation is not affected by @ref IOT_STATIC_MEMORY_ONLY. However, its memory allocation functions may be overridden by setting the following constants. All memory allocation functions must have the same signatures as [malloc](http://pubs.opengroup.org/onlinepubs/9699919799/functions/malloc.html) and [free](http://pubs.opengroup.org/onlinepubs/9699919799/functions/free.html). - - `IotThreads_Malloc` and `IotThreads_Free`. - - `IotNetwork_Malloc` and `IotNetwork_Free`. - -@section platform_config_posixheaders POSIX headers -@brief The POSIX platform layer allows the standard POSIX header includes to be overridden. Overrides only affect the POSIX platform layer. - -Any substitute headers are expected to provide the same functionality as the standard POSIX headers. The POSIX header overrides should only be used if the system's headers do not follow the standard names for POSIX headers. The POSIX headers may be overridden by defining the following settings: -Standard name | Setting -------------- | ------- -[errno.h](http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/errno.h.html) | `POSIX_ERRNO_HEADER` -[limits.h](http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/limits.h.html) | `POSIX_LIMITS_HEADER` -[pthread.h](http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/pthread.h.html) | `POSIX_PTHREAD_HEADER` -[signal.h](http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/signal.h.html) | `POSIX_SIGNAL_HEADER` -[semaphore.h](http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/semaphore.h.html) | `POSIX_SEMAPHORE_HEADER` -[time.h](http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/time.h.html) | `POSIX_TIME_HEADER` -[sys/types.h](http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/sys_types.h.html) | `POSIX_TYPES_HEADER` - -Example:
-To use a header named `custom_errno.h` instead of `errno.h`, the `POSIX_ERRNO_HEADER` setting should be defined. -@code{c} -#define POSIX_ERRNO_HEADER "custom_errno.h" -@endcode - -@configpossible Strings representing file names. These files must be in the compiler's include path.
-@configdefault Standard POSIX header names. -*/ - -/** -@handles_group{platform} -@handles_brief{platform layer} -@enums_group{platform} -@enums_brief{platform layer} -@paramstructs_group{platform} -@paramstructs_brief{platform, platform layer} -*/ - -/** -@functions_page{platform, Platform} -@functions_brief{platform layer} -- @subpage platform_clock_functions
- @copybrief platform_clock_functions -- @subpage platform_network_functions
- @copybrief platform_network_functions -- @subpage platform_threads_functions
- @copybrief platform_threads_functions -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/secure_sockets.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/secure_sockets.txt deleted file mode 100644 index 29089ef..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/secure_sockets.txt +++ /dev/null @@ -1,145 +0,0 @@ -/** -@mainpage - -## Introduction - -The Secure Sockets interface is based on the Berkeley sockets interface with the addition of a secure communication option by TLS protocol. At this time, only client APIs are supported. - -The Amazon FreeRTOS Secure Socket API allows you to create embedded applications that communicate securely. It is designed for easy onboarding of software developers from various network programming backgrounds. The reference implementation for Secure Sockets supports TLS and TCP/IP over Ethernet and Wi-Fi. - -## Secure Sockets Library dependencies - -@dot "Secure Sockets Library dependencies" -digraph library_dependencies -{ - node[shape=box, fontname=Helvetica, fontsize=10, style=filled]; - edge[fontname=Helvetica, fontsize=10]; - high_level[label="Secure Sockets Library", fillcolor="#aed8a9ff"]; - low_level1[label="FreeRTOS+TCP", fillcolor="#e89025ff"]; - low_level2[label="TLS Layer", fillcolor="#e89025ff"]; - low_low_level2[label="mbedTLS", fillcolor="#e89025ff"]; - high_level -> low_level1 [style="dashed"]; - high_level -> low_level2 [style="dashed"]; - low_level2 -> low_low_level2 [style="dashed"]; -} -@enddot - -*/ - -/** -@config_page{SecureSockets} -@config_brief{library} - -@section socketsconfigBYTE_ORDER -@brief Byte order of the target MCU must be defined. For detail, please refer to [Endian](https://freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/endian.html) in freertos.org - -Valid values are pdLITTLE_ENDIAN and pdBIG_ENDIAN. - -If this configuration is not set, compiler will generate an error warning about it, which is written in @ref iot_secure_sockets_config_defaults.h - -@configpossible `pdLITTLE_ENDIAN` (little endian) or `pdBIG_ENDIAN` (big endian)
-@configrecommended must be set correctly for the MCU
-@configdefault `None` - -@section socketsconfigDEFAULT_SEND_TIMEOUT -@brief Default socket send timeout. - -The user can change the send timeout for a socket using the @ref SOCKETS_SetSockOpt API -with the SOCKETS_SO_SNDTIMEO option. - -The unit is milliseconds that @ref SOCKETS_Send should wait before timing out. -Setting to 0 causes send to wait forever. - -This configuration is defined in @ref iot_secure_sockets_config_defaults.h - -@configpossible `Any positive integer`
-@configdefault `10000` - -@section socketsconfigDEFAULT_RECV_TIMEOUT -@brief Default socket receive timeout. - -The user can change the receive timeout for a socket using the @ref SOCKETS_SetSockOpt API -with the SOCKETS_SO_RCVTIMEO option. - -The unit is milliseconds that @ref SOCKETS_Recv should wait before timing out. -Setting to 0 causes receive to wait forever. - -This configuration is defined in @ref iot_secure_sockets_config_defaults.h - -@configpossible `Any positive integer`
-@configdefault `10000` -*/ - -/** -@functions_page{SecureSockets,Secure Sockets} -@functions_brief{Secure Sockets} -- @subpage secure_sockets_function_primary -- @subpage secure_sockets_function_helper -@page secure_sockets_function_primary Primary Functions -- @function_name{secure_sockets_function_socket} -@function_brief{secure_sockets_function_socket} -- @function_name{secure_sockets_function_connect} -@function_brief{secure_sockets_function_connect} -- @function_name{secure_sockets_function_recv} -@function_brief{secure_sockets_function_recv} -- @function_name{secure_sockets_function_send} -@function_brief{secure_sockets_function_send} -- @function_name{secure_sockets_function_shutdown} -@function_brief{secure_sockets_function_shutdown} -- @function_name{secure_sockets_function_close} -@function_brief{secure_sockets_function_close} -- @function_name{secure_sockets_function_setsockopt} -@function_brief{secure_sockets_function_setsockopt} -- @function_name{secure_sockets_function_gethostbyname} -@function_brief{secure_sockets_function_gethostbyname} -@page secure_sockets_function_helper Helper Functions -- @subpage SOCKETS_htonl -- @subpage SOCKETS_ntohl -- @subpage SOCKETS_htons -- @subpage SOCKETS_ntohs -- @subpage SOCKETS_inet_addr_quick -- @subpage SOCKETS_inet_ntoa -*/ - -/** -@page secure_sockets_function_socket SOCKETS_Socket -@snippet iot_secure_sockets.h declare_secure_sockets_socket -@copydoc SOCKETS_Socket - -@page secure_sockets_function_connect SOCKETS_Connect -@snippet iot_secure_sockets.h declare_secure_sockets_connect -@copydoc SOCKETS_Connect - -@page secure_sockets_function_recv SOCKETS_Recv -@snippet iot_secure_sockets.h declare_secure_sockets_recv -@copydoc SOCKETS_Recv - -@page secure_sockets_function_send SOCKETS_Send -@snippet iot_secure_sockets.h declare_secure_sockets_send -@copydoc SOCKETS_Send - -@page secure_sockets_function_shutdown SOCKETS_Shutdown -@snippet iot_secure_sockets.h declare_secure_sockets_shutdown -@copydoc SOCKETS_Shutdown - -@page secure_sockets_function_close SOCKETS_Close -@snippet iot_secure_sockets.h declare_secure_sockets_close -@copydoc SOCKETS_Close - -@page secure_sockets_function_setsockopt SOCKETS_SetSockOpt -@snippet iot_secure_sockets.h declare_secure_sockets_setsockopt -@copydoc SOCKETS_SetSockOpt - -@page secure_sockets_function_gethostbyname SOCKETS_GetHostByName -@snippet iot_secure_sockets.h declare_secure_sockets_gethostbyname -@copydoc SOCKETS_GetHostByName - -*/ - -/** -@handles_group{SecureSockets} -@handles_brief{SecureSockets library} -@paramstructs_group{SecureSockets} -@paramstructs_brief{SecureSockets, secure sockets} - -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/shadow.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/shadow.txt deleted file mode 100644 index e5bfb26..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/shadow.txt +++ /dev/null @@ -1,107 +0,0 @@ -/** -@mainpage -@anchor shadow -@brief AWS IoT Device Shadow library. - -> A device's shadow is a JSON document that is used to store and retrieve current state information for a device. The Device Shadow service maintains a shadow for each device you connect to AWS IoT. You can use the shadow to get and set the state of a device over MQTT or HTTP, regardless of whether the device is connected to the Internet. Each device's shadow is uniquely identified by the name of the corresponding thing. - - — Description of Device Shadows from [AWS IoT documentation](https://docs.aws.amazon.com/iot/latest/developerguide/iot-device-shadows.html)
- -Thing Shadows are the always-available device state in the AWS cloud. They are stored as JSON documents, and available via AWS even if the associated device goes offline. Common use cases for Thing Shadows include backing up device state, or sending commands to devices. - -This library provides an API for interacting with AWS IoT Thing Shadows. Features of this library include: -- Both fully asynchronous and blocking API functions. -- API functions for modifying Thing Shadows and for registering notifications of a Thing Shadow change. - -@dependencies_section{shadow} -@dependencies_brief{Shadow library} - -@dot "Shadow direct dependencies" -digraph shadow_dependencies -{ - node[shape=box, fontname=Helvetica, fontsize=10, style=filled]; - edge[fontname=Helvetica, fontsize=10]; - subgraph - { - shadow[label="Shadow", fillcolor="#cc00ccff"]; - mqtt[label="MQTT", fillcolor="#cc00ccff", URL="@ref mqtt"]; - } - subgraph - { - node[fillcolor="#aed8a9ff"]; - rank = same; - linear_containers[label="List/Queue", URL="@ref linear_containers"]; - logging[label="Logging", URL="@ref logging"]; - static_memory[label="Static memory", URL="@ref static_memory"]; - } - shadow -> mqtt; - shadow -> linear_containers; - shadow -> logging [label=" if logging enabled", style="dashed"]; - shadow -> static_memory [label=" if static memory only", style="dashed"]; -} -@enddot - -Currently, the Shadow library has the following dependencies: -- The MQTT library for sending the messages that interact with the Thing Shadow service. See [this page](@ref mqtt_dependencies) for the dependencies of the MQTT library, which are not shown in the graph above. -- The queue library for maintaining the data structures for managing in-progress Shadow operations. -- The logging library may be used if @ref AWS_IOT_LOG_LEVEL_SHADOW is not #IOT_LOG_NONE. - -In addition to the components above, the Shadow library also depends on C standard library headers. -*/ - -/** -@page shadow_demo Demo -@brief The Shadow demo demonstrates usage of the Shadow library. -*/ - -/** -@config_page{shadow} -@config_brief{Shadow library} - -@section AWS_IOT_SHADOW_ENABLE_ASSERTS -@brief Set this to `1` to perform sanity checks when using the Shadow library. - -Asserts are useful for debugging, but should be disabled in production code. If this is set to `1`, @ref AwsIotShadow_Assert can be defined to set the assertion function; otherwise, the standard library's [assert](http://pubs.opengroup.org/onlinepubs/9699919799/functions/assert.html) function will be used. - -@configpossible `0` (asserts disabled) or `1` (asserts enabled)
-@configrecommended `1` when debugging; `0` in production code.
-@configdefault `0` - -@section AWS_IOT_SHADOW_DEFAULT_MQTT_TIMEOUT_MS -@brief Set the default timeout (in milliseconds) for [MQTT library](@ref mqtt_functions) called by the Shadow library. - -If the `mqttTimeout` argument of @ref shadow_function_init is `0`, the Shadow library uses this setting for MQTT timeouts. This timeout is passed to functions such as @ref mqtt_function_timedsubscribe, @ref mqtt_function_timedunsubscribe, and @ref mqtt_function_timedpublish to limit amount of time an MQTT function may block. - -@configpossible Any positive integer.
-@configrecommended This setting must be at least the network round-trip time, as an MQTT packet must be sent to the AWS IoT server and a response must be received. The recommended minimum value is `500`.
-@configdefault `5000` - -@section AWS_IOT_LOG_LEVEL_SHADOW -@brief Set the log level of the Shadow library. - -Log messages from the Shadow library at or below this setting will be printed. - -@configpossible One of the @ref logging_constants_levels.
-@configdefault @ref IOT_LOG_LEVEL_GLOBAL; if that is undefined, then #IOT_LOG_NONE. - -@section AwsIotShadow_Assert -@brief Assertion function used when @ref AWS_IOT_SHADOW_ENABLE_ASSERTS is `1`. - -@configpossible Any function with the same signature as the standard library's [assert](http://pubs.opengroup.org/onlinepubs/9699919799/functions/assert.html) function.
-@configdefault Standard library [assert](http://pubs.opengroup.org/onlinepubs/9699919799/functions/assert.html) function if @ref AWS_IOT_SHADOW_ENABLE_ASSERTS is `1`; otherwise, nothing. - -@section shadow_config_memory Memory allocation -@brief If @ref IOT_STATIC_MEMORY_ONLY is `1`, then the following functions must be re-implemented for the Shadow library. -- #AwsIotShadow_MallocOperation
- @copybrief AwsIotShadow_MallocOperation -- #AwsIotShadow_FreeOperation
- @copybrief AwsIotShadow_FreeOperation -- #AwsIotShadow_MallocString
- @copybrief AwsIotShadow_MallocString -- #AwsIotShadow_FreeString
- @copybrief AwsIotShadow_FreeString -- #AwsIotShadow_MallocSubscription
- @copybrief AwsIotShadow_MallocSubscription -- #AwsIotShadow_FreeSubscription
- @copybrief AwsIotShadow_FreeSubscription -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/static_memory.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/static_memory.txt deleted file mode 100644 index e53a514..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/static_memory.txt +++ /dev/null @@ -1,117 +0,0 @@ -/** -@mainpage -@anchor static_memory -@brief @copybrief iot_static_memory.h

- -The static memory component provides statically-allocated buffers that are used instead of dynamic memory allocation when @ref IOT_STATIC_MEMORY_ONLY is `1`. Using static memory only does not guarantee that memory allocation will always succeed; it's possible for all statically-allocated buffers to be in-use. However, static memory only can guarantee the availability of at least a certain amount of resources. Because space must be reserved for statically-allocated buffers, binaries compiled with static memory only will be larger. - -@section static_memory_types Types of buffers -@brief The types of statically-allocated buffers provided by the static memory component. - -@subsection static_memory_types_messagebuffers Message buffers -Message buffers are fixed-size buffers used for strings, such as log messages or bytes transmitted over a network. Their size and number can be configured with the constants @ref IOT_MESSAGE_BUFFERS (number) and @ref IOT_MESSAGE_BUFFER_SIZE (size of each message buffer). Message buffers may be used by any library, and are analogous to the generic buffers allocated by [malloc](http://pubs.opengroup.org/onlinepubs/9699919799/functions/malloc.html) (though all message buffers are the same size). - -@subsection static_memory_mqtt MQTT static buffers -@brief Statically-allocated buffers used by the [MQTT library](@ref mqtt). - -@subsubsection static_memory_types_mqttconnections Connections -MQTT connections correspond to a statically-allocated MQTT session between a single client and server. In static memory mode, the number of simultaneous, active MQTT connections is controlled by the constant @ref IOT_MQTT_CONNECTIONS. - -@subsubsection static_memory_types_mqttoperations Operations -MQTT operations correspond to in-progress requests between a client and the MQTT server, such as CONNECT, PUBLISH, or publish acknowledgement (PUBACK). In static memory mode, the number of simultaneous, active MQTT operations is controlled by the constant @ref IOT_MQTT_MAX_IN_PROGRESS_OPERATIONS. - -@subsubsection static_memory_types_mqttsubscriptions Subscriptions -MQTT subscriptions store records on callbacks registered for MQTT topic filters. In static memory mode, the number of simultaneous, active MQTT subscriptions (across all connections) is controlled by the constant @ref IOT_MQTT_SUBSCRIPTIONS. - -@subsection static_memory_shadow Shadow static buffers -@brief Statically-allocated buffers used by the [Shadow library](@ref shadow). - -@subsubsection static_memory_types_shadowoperations Operations -Shadow operations correspond to in-progress Shadow [DELETE](@ref shadow_function_delete), [GET](@ref shadow_function_get), or [UPDATE](@ref shadow_function_update) operations. In static memory mode, the number of simultaneous, active Shadow operations is controlled by the constant @ref AWS_IOT_SHADOW_MAX_IN_PROGRESS_OPERATIONS. - -@subsubsection static_memory_types_shadowsubscriptions Subscriptions -A Shadow subscriptions object groups MQTT subscriptions for a Thing. Shadow operations require pairs of subscriptions to determine their status (i.e. `/accepted` or `/rejected`); these subscriptions (as well as subscriptions for Shadow callbacks) are tracked by a Shadow subscriptions object. In static memory mode, the number of simultaneous, active Shadow subscriptions is controlled by the constant @ref AWS_IOT_SHADOW_SUBSCRIPTIONS. - -@dependencies_section{static_memory} -@dependencies_brief{static memory component} - -@dot "Static memory direct dependencies" -digraph static_memory_dependencies -{ - node[shape=box, fontname=Helvetica, fontsize=10, style=filled]; - static_memory[label="Static memory", fillcolor="#aed8a9ff"]; - subgraph - { - rank = same; - operating_system[label="Operating system", fillcolor="#999999ff"] - standard_library[label="Standard library\nstdbool, stddef, string", fillcolor="#d15555ff"]; - } - static_memory -> operating_system; - static_memory -> standard_library; -} -@enddot - -Currently, the static memory component has the following dependencies: -- The operating system must provide a mechanism to implement critical sections. -*/ - -/** -@config_page{static_memory} -@config_brief{statically-allocated buffer pools} - -@section IOT_MESSAGE_BUFFERS -@brief The number of statically-allocated [message buffers](@ref static_memory_types_messagebuffers). This setting has no effect if @ref IOT_STATIC_MEMORY_ONLY is `0`. - -@see @ref static_memory_types_messagebuffers - -@configpossible Any positive integer.
-@configdefault `8` - -@section IOT_MESSAGE_BUFFER_SIZE -@brief The size (in bytes) of each statically-allocated [message buffer](@ref static_memory_types_messagebuffers). This setting has no effect if @ref IOT_STATIC_MEMORY_ONLY is `0`. - -@see @ref static_memory_types_messagebuffers - -@configpossible Any positive integer.
-@configdefault `1024` - -@section IOT_MQTT_CONNECTIONS -@brief The number of statically-allocated [MQTT connections](@ref static_memory_types_mqttconnections). This setting has no effect if @ref IOT_STATIC_MEMORY_ONLY is `0`. - -@see [MQTT connections](@ref static_memory_types_mqttconnections) - -@configpossible Any positive integer.
-@configdefault `1` - -@section IOT_MQTT_MAX_IN_PROGRESS_OPERATIONS -@brief The number of statically-allocated [MQTT operations](@ref static_memory_types_mqttoperations). This setting has no effect if @ref IOT_STATIC_MEMORY_ONLY is `0`. - -@see [In-progress MQTT operations](@ref static_memory_types_mqttoperations) - -@configpossible Any positive integer.
-@configdefault `10` - -@section IOT_MQTT_SUBSCRIPTIONS -@brief The number of statically-allocated [MQTT subscriptions](@ref static_memory_types_mqttsubscriptions). This setting has no effect if @ref IOT_STATIC_MEMORY_ONLY is `0`. - -@see [MQTT subscriptions](@ref static_memory_types_mqttsubscriptions) - -@configpossible Any positive integer.
-@configdefault `8` - -@section AWS_IOT_SHADOW_MAX_IN_PROGRESS_OPERATIONS -@brief The number of statically-allocated [Shadow operations](@ref static_memory_types_shadowoperations). This setting has no effect if @ref IOT_STATIC_MEMORY_ONLY is `0`. - -@see [In-progress Shadow operations](@ref static_memory_types_shadowoperations) - -@configpossible Any positive integer.
-@configdefault `10` - -@section AWS_IOT_SHADOW_SUBSCRIPTIONS -@brief The number of statically-allocated [Shadow subscriptions](@ref static_memory_types_shadowsubscriptions). This setting has no effect if @ref IOT_STATIC_MEMORY_ONLY is `0`. - -@see [Shadow subscriptions objects](@ref static_memory_types_shadowsubscriptions) - -@configpossible Any positive integer.
-@configdefault `2` -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/taskpool.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/taskpool.txt deleted file mode 100644 index a572735..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/taskpool.txt +++ /dev/null @@ -1,147 +0,0 @@ -/** -@mainpage -@anchor taskpool -@brief Task pool library. - -> A task pool is an adaptive set of threads that can grow and shrink to execute a user-provided callback through a user-defined job that can be scheduled with a non-blocking call. The design principles are to minimize the memory footprint while allowing non-blocking execution. The adaptive behavior allows serving jobs in a timely manner, without allocating system resources for the entire duration of the application, or causing recurring allocation/deallocation patterns. The user does not have to worry about synchronization and thread management other than within its own application. - -Features of this library include: -- Non-blocking API functions to schedule immediate and deferred jobs. -- Ability to create statically and dynamically allocated jobs. -- Scalable performance and footprint. The [configuration settings](@ref taskpool_config) allow this library to be tailored to a system's resources. -- Customizable caching for low memory overhead when creating jobs dynamically. - -This library uses a user-specified set of threads to process jobs specified by the user as a callback and a context. -Overall, the task pool hinges on two main data structures: the task pool Job (IotTaskPoolJob_t) and the task pool itself (IotTaskPool_t). A task pool job carries the information about the user callback and context, one flag to track the status and a link structure for moving the job in and out of the dispatch queue and cache. User can create two types of jobs: static and recyclable. Static jobs are intended for users that know exactly how many jobs they will schedule (e.g. see Defender scenario above) or for embedding in other data structures. Static jobs need no destruction, and creation simply sets the user callback and context. Recyclable jobs are intended for scenario where user cannot know ahead of time how many jobs she will need. Recyclable jobs are dynamically allocated, and can be either destroyed after use or recycled. If jobs are recycled they are maintained in a cache (IotTaskPoolCache_t) owned by the task pool itself, and re-used when user wants to create more recyclable jobs. The task pool cache has a compile time limit, and can be pre-populated with recyclable jobs by simply creating recyclable jobs and recycling them, in an effort to limit memory allocations at run-time. This is handy for scenarios where user is aware of the steady state requirements for his application. -User jobs are queued through a non-blocking call and processed asynchronously in the order they are received. -- [Task pool API functions](@ref taskpool_functions) Provides a set of functions to queue an asynchronous operation on the Dispatch Queue. API functions are non-blocking and return after successfully queuing an operation. -- Worker threads in the task pool are woken up when operations arrive in the dispatch queue. These threads remove operations from the dispatch queue in FIFO order and execute the user-provided callback. After executing the user callback, the task pool threads try and execute any remaining jobs in the dispatch queue. The task pool tries and execute a user job as soon as it is received and if there are no threads available it will try and create one, up to the maximum number of allowed threads. The user can specificy the minimum and maximum number of threads allowed when creating the task pool. -- The user can try and cancel a job after the task has been scheduled. Cancellation is only allowed before the task enters execution. - -Threads are created with @ref platform_threads_function_createdetachedthread. Because the platform layer may be re-implemented across systems, threads will be allocated for the task pool library on-the-go on some systems, while other systems may use an always-allocated thread pool. - -@dependencies_section{taskpool} -@dependencies_brief{task pool library} - -@dot "Task pool direct dependencies" -digraph taskpool_dependencies -{ - node[shape=box, fontname=Helvetica, fontsize=10, style=filled]; - edge[fontname=Helvetica, fontsize=10]; - subgraph - { - taskpool[label="Task pool", fillcolor="#cc00ccff"]; - } - subgraph - { - node[fillcolor="#aed8a9ff"]; - rank = same; - linear_containers[label="List/Queue", URL="@ref linear_containers"]; - logging[label="Logging", URL="@ref logging"]; - static_memory[label="Static memory", URL="@ref static_memory"]; - } - subgraph - { - rank = same; - platform_threads[label="Thread management", fillcolor="#e89025ff", URL="@ref platform_threads"]; - platform_clock[label="Clock", fillcolor="#e89025ff", URL="@ref platform_clock"]; - } - taskpool -> linear_containers; - taskpool -> platform_clock; - taskpool -> platform_threads; - taskpool -> static_memory [label=" if static memory only", style="dashed"]; - taskpool -> logging [label=" if logging enabled", style="dashed"]; - logging -> platform_clock; - logging -> static_memory [label=" if static memory only", style="dashed"]; -} -@enddot - -Currently, the task pool library has the following dependencies: -- The linear containers (list/queue) library for maintaining the data structures for scheduled and in-progress task pool operations. -- The logging library may be used if @ref IOT_LOG_LEVEL_TASKPOOL is not @ref IOT_LOG_NONE. -- The platform layer provides an interface to the operating system for thread management, timers, clock functions, etc. - -In addition to the components above, the task pool library may also depend on C standard library headers. -*/ - -/** -@page taskpool_design Design -@brief Architecture behind the task pool library. - -The sequence diagram below illustrates the workflow described above. The application thread is able to continue executing while the task pool library processes the operation. - -@image html taskpool_design_typicaloperation.png width=100% - -The state diagrams for statically allocated, non-recyclable jobs with all legal transitions is presented in the diagram below. A static job can be created, schedule and canceled. Cancellation always succeeds, unless the job was already canceled, or completed (i.e. executed). Static jobs cannot be recycled and do no need to be destroyed. Static jobs are suitable for embedding on other data structures that own them. - -@image html StaticJobStatus.png width=40% - -The state diagram and legal transitions for all recyclable jobs is presented in the diagram below. A recyclable job is dynamically allocated. Just like a static job, a recyclable job can be created, schedule and canceled. Cancellation always succeeds, unless the job was already canceled, or completed (i.e. executed). Unlike static jobs, recyclable jobs can be recycled, or destroyed. Recycling a job effectively pushes a job to the task pool cache, where the task pool manages the lifetime of the job itself. The size of the cache is controlled via a compile time parameter. A user can get rid of a recyclable job by destroying it explicitly. Recyclable jobs should not be embedded in other data structures, but could be referenced from other data structures. - -@image html RecyclableJobStatus.png width=50% - -*/ - -/** -@page taskpool_tests Tests -@brief Tests written for the task pool library. - -The task pool tests reside in the `tests/common` directory. They are divided into the following subdirectories: -- `system`: task pool system and stress tests. Stress tests may run for a long time, so they are not run unless the `-l` option is passed to the test executable. -- `unit`: task pool unit tests. These tests do not require a network connection. - -The current task pool tests use the [Unity test framework](http://www.throwtheswitch.org/unity/). -*/ - -/** -@config_page{taskpool} -@config_brief{task pool library} - -@section IOT_TASKPOOL_JOB_WAIT_TIMEOUT_MS -@brief Set this to the desired wait timeout in milliseconds for a worker in the task pool to wait for an incoming job. - -If a worker in the task pool wakes up because of a timeout, then the worker will terminate if it exceeds the desired minimum thread quota, which the user can configure via @ref IotTaskPoolInfo_t.minThreads. - -@configdefault `1 minute` - -@section IOT_TASKPOOL_JOBS_RECYCLE_LIMIT -@brief Set this to the number of recyclable tasks for the task pool to cache. - -Caching dynamically allocated tasks (recyclable tasks) helps the application to limit the number of allocations at runtime. -Caching recyclable tasks may help making the application more responsive and predictable, by removing a potential -for memory allocation failures, but it may also have negative repercussions on the amount of memory available at any given time. -It is up to the application developer to strike the correct balance these competing needs. -The task pool will cache when the application calling @ref IotTaskPool_RecycleJob. Any recycled tasks in excess of @ref IOT_TASKPOOL_JOBS_RECYCLE_LIMIT will be destroyed and its memory will be release. - -@configdefault `8` - -@section IOT_TASKPOOL_ENABLE_ASSERTS -@brief Set this to `1` to perform sanity checks when using the task pool library. - -Asserts are useful for debugging, but should be disabled in production code. If this is set to `1`, @ref IotTaskPool_Assert can be defined to set the assertion function; otherwise, the standard library's [assert](http://pubs.opengroup.org/onlinepubs/9699919799/functions/assert.html) function will be used. - -@configpossible `0` (asserts disabled) or `1` (asserts enabled)
-@configrecommended `1` when debugging; `0` in production code.
-@configdefault `0` - -@section IOT_LOG_LEVEL_TASKPOOL -@brief Set the log level of the task pool library. - -Log messages from the task pool library at or below this setting will be printed. - -@configpossible One of the @ref logging_constants_levels.
-@configdefault @ref IOT_LOG_LEVEL_GLOBAL; if that is undefined, then #IOT_LOG_NONE. -*/ - -/** -@enums_group{taskpool} -@enums_brief{task pool} -@paramstructs_group{taskpool} -@paramstructs_brief{taskpool,task pool} -@functionpointers_group{taskpool} -@functionpointers_brief{task pool} -@structs_group{taskpool} -@structs_brief{task pool} -@handles_group{taskpool} -@handles_brief{task pool} -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/wifi.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/wifi.txt deleted file mode 100644 index 89d2f18..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/lib/wifi.txt +++ /dev/null @@ -1,175 +0,0 @@ -/** -@mainpage - -The Wi-Fi interface API provides a common abstraction layer that enables applications to communicate with the lower-level wireless stack. Wi-Fi chip sets differ in features, driver implementations, and APIs. The common Wi-Fi interface simplifies application development and porting for all supported Wi-Fi chip sets. The interface provides a primary API for managing all aspects of Wi-Fi devices. -*/ - -/** -@config_page{SecureSockets} -@config_brief{Wifi library} - -@brief The Wi-Fi Management library does not have a configuration file provided, but the following identifiers must be \c \#define'd in any application using the Wi-Fi Management library. Example values for these identifiers can be found in aws_wifi_config.h from the AWS FreeRTOS demo for the specific board being used. - -Note that some of these identifiers are only utilized by certain ports of the Wi-Fi library and may not have an effect on all boards. - -@section wificonfigMAX_CONNECTED_STATIONS -@brief Maximum number of connected stations in Access Point mode. - -__Example value:__ 4 - -@section wificonfigMAX_NETWORK_PROFILES -@brief Maximum number of network profiles stored in Non Volatile memory, set to zero if not supported. - -__Example value:__ 0 - -@section wificonfigMAX_SSID_LEN -@brief Maximum length of SSID for access points (used to allocate memory for SSID strings), not including a NULL terminator. - -__Example value:__ 32 - -@section wificonfigMAX_BSSID_LEN -@brief Maximum length of BSSID for access points (used to allocate memory for BSSID strings), not including a NULL terminator. - -__Example value:__ 6 - -@section wificonfigMAX_PASSPHRASE_LEN -@brief Maximum length of passphrase for access points (used to allocate memory for passphrase strings), not including a NULL terminator. - -__Example value:__ 32 - -This length is designated by the Wi-Fi driver as both the WPA PSK and Passphrase length. - -@section wificonfigMAX_SEMAPHORE_WAIT_TIME_MS -@brief Maximum time to wait in milliseconds for obtaining the Wi-Fi semaphore before failing the operation. - -__Example value:__ 60000 - -*/ - -/** -@functions_page{wifi, WiFi} -@functions_brief{wifi} -- @function_name{wifi_function_wifi_on} -@function_brief{wifi_function_wifi_on} -- @function_name{wifi_function_wifi_off} -@function_brief{wifi_function_wifi_off} -- @function_name{wifi_function_wifi_connectap} -@function_brief{wifi_function_wifi_connectap} -- @function_name{wifi_function_wifi_disconnect} -@function_brief{wifi_function_wifi_disconnect} -- @function_name{wifi_function_wifi_reset} -@function_brief{wifi_function_wifi_reset} -- @function_name{wifi_function_wifi_setmode} -@function_brief{wifi_function_wifi_setmode} -- @function_name{wifi_function_wifi_getmode} -@function_brief{wifi_function_wifi_getmode} -- @function_name{wifi_function_wifi_networkadd} -@function_brief{wifi_function_wifi_networkadd} -- @function_name{wifi_function_wifi_networkget} -@function_brief{wifi_function_wifi_networkget} -- @function_name{wifi_function_wifi_networkdelete} -@function_brief{wifi_function_wifi_networkdelete} -- @function_name{wifi_function_wifi_ping} -@function_brief{wifi_function_wifi_ping} -- @function_name{wifi_function_wifi_getip} -@function_brief{wifi_function_wifi_getip} -- @function_name{wifi_function_wifi_getmac} -@function_brief{wifi_function_wifi_getmac} -- @function_name{wifi_function_wifi_gethostip} -@function_brief{wifi_function_wifi_gethostip} -- @function_name{wifi_function_wifi_scan} -@function_brief{wifi_function_wifi_scan} -- @function_name{wifi_function_wifi_startap} -@function_brief{wifi_function_wifi_startap} -- @function_name{wifi_function_wifi_stopap} -@function_brief{wifi_function_wifi_stopap} -- @function_name{wifi_function_wifi_configureap} -@function_brief{wifi_function_wifi_configureap} -- @function_name{wifi_function_wifi_setpmmode} -@function_brief{wifi_function_wifi_setpmmode} -- @function_name{wifi_function_wifi_getpmmode} -@function_brief{wifi_function_wifi_getpmmode} -- @function_name{wifi_function_wifi_isconnected} -@function_brief{wifi_function_wifi_isconnected} -- @function_name{wifi_function_wifi_registernetworkstatechangeeventcallback} -@function_brief{wifi_function_wifi_registernetworkstatechangeeventcallback} -*/ - -/** -@function_page{WIFI_On,wifi,wifi_on} -@function_snippet{wifi,wifi_on,iot_wifi.h} -@copydoc WIFI_On -@function_page{WIFI_Off,wifi,wifi_off} -@function_snippet{wifi,wifi_off,iot_wifi.h} -@copydoc WIFI_Off -@function_page{WIFI_ConnectAP,wifi,wifi_connectap} -@function_snippet{wifi,wifi_connectap,iot_wifi.h} -@copydoc WIFI_ConnectAP -@function_page{WIFI_Disconnect,wifi,wifi_disconnect} -@function_snippet{wifi,wifi_disconnect,iot_wifi.h} -@copydoc WIFI_Disconnect -@function_page{WIFI_Reset,wifi,wifi_reset} -@function_snippet{wifi,wifi_reset,iot_wifi.h} -@copydoc WIFI_Reset -@function_page{WIFI_SetMode,wifi,wifi_setmode} -@function_snippet{wifi,wifi_setmode,iot_wifi.h} -@copydoc WIFI_SetMode -@function_page{WIFI_GetMode,wifi,wifi_getmode} -@function_snippet{wifi,wifi_getmode,iot_wifi.h} -@copydoc WIFI_GetMode -@function_page{WIFI_NetworkAdd,wifi,wifi_networkadd} -@function_snippet{wifi,wifi_networkadd,iot_wifi.h} -@copydoc WIFI_NetworkAdd -@function_page{WIFI_NetworkGet,wifi,wifi_networkget} -@function_snippet{wifi,wifi_networkget,iot_wifi.h} -@copydoc WIFI_NetworkGet -@function_page{WIFI_NetworkDelete,wifi,wifi_networkdelete} -@function_snippet{wifi,wifi_networkdelete,iot_wifi.h} -@copydoc WIFI_NetworkDelete -@function_page{WIFI_Ping,wifi,wifi_ping} -@function_snippet{wifi,wifi_ping,iot_wifi.h} -@copydoc WIFI_Ping -@function_page{WIFI_GetIP,wifi,wifi_getip} -@function_snippet{wifi,wifi_getip,iot_wifi.h} -@copydoc WIFI_GetIP -@function_page{WIFI_GetMAC,wifi,wifi_getmac} -@function_snippet{wifi,wifi_getmac,iot_wifi.h} -@copydoc WIFI_GetMAC -@function_page{WIFI_GetHostIP,wifi,wifi_gethostip} -@function_snippet{wifi,wifi_gethostip,iot_wifi.h} -@copydoc WIFI_GetHostIP -@function_page{WIFI_Scan,wifi,wifi_scan} -@function_snippet{wifi,wifi_scan,iot_wifi.h} -@copydoc WIFI_Scan -@function_page{WIFI_StartAP,wifi,wifi_startap} -@function_snippet{wifi,wifi_startap,iot_wifi.h} -@copydoc WIFI_StartAP -@function_page{WIFI_StopAP,wifi,wifi_stopap} -@function_snippet{wifi,wifi_stopap,iot_wifi.h} -@copydoc WIFI_StopAP -@function_page{WIFI_ConfigureAP,wifi,wifi_configureap} -@function_snippet{wifi,wifi_configureap,iot_wifi.h} -@copydoc WIFI_ConfigureAP -@function_page{WIFI_SetPMMode,wifi,wifi_setpmmode} -@function_snippet{wifi,wifi_setpmmode,iot_wifi.h} -@copydoc WIFI_SetPMMode -@function_page{WIFI_GetPMMode,wifi,wifi_getpmmode} -@function_snippet{wifi,wifi_getpmmode,iot_wifi.h} -@copydoc WIFI_GetPMMode -@function_page{WIFI_IsConnected,wifi,wifi_isconnected} -@function_snippet{wifi,wifi_isconnected,iot_wifi.h} -@copydoc WIFI_IsConnected -@function_page{WIFI_RegisterNetworkStateChangeEventCallback,wifi,wifi_registernetworkstatechangeeventcallback} -@function_snippet{wifi,wifi_registernetworkstatechangeeventcallback,iot_wifi.h} -@copydoc WIFI_RegisterNetworkStateChangeEventCallback -*/ - -/** -@enums_group{wifi} -@enums_brief{WiFi library} - -@paramstructs_group{wifi} -@paramstructs_brief{wifi,wifi} -@returnstructs_group{wifi} -@returnstructs_brief{wifi} -*/ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/RecyclableJobStatus.pu b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/RecyclableJobStatus.pu deleted file mode 100644 index 41e2bca..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/RecyclableJobStatus.pu +++ /dev/null @@ -1,46 +0,0 @@ -@startuml - -skinparam classFontSize 8 -skinparam classFontName Helvetica -skinparam state { - BackgroundColor<> Gray -} -state READY { -} -state SCHEDULED { -} -state DEFERRED { -} -state COMPLETED { -} -state CANCELED { -} -state UNDEFINED { -} -state CACHED <> { -} - -[*] --[#green]> READY : CreateRecyclableJob -READY --[#blue]> SCHEDULED : Schedule -READY --[#blue]> DEFERRED : ScheduleDeferred -DEFERRED --[#red]> SCHEDULED : -SCHEDULED --[#green]> COMPLETED : -COMPLETED -up[#blue]-> CACHED : RecycleJob -COMPLETED --[#blue]> UNDEFINED : DestroyRecyclableJob - -READY -right[#blue]-> CANCELED : TryCancel -DEFERRED -right[#blue]-> CANCELED : TryCancel -SCHEDULED -right[#blue]-> CANCELED : TryCancel - -CANCELED --[#blue]> CACHED : RecycleJob -CANCELED --[#blue]> UNDEFINED : DestroyRecyclableJob - -READY -up[#blue]-> CACHED : RecycleJob -DEFERRED -up[#blue]-> CACHED : RecycleJob -SCHEDULED -up[#blue]-> CACHED : RecycleJob - -READY --[#blue]> UNDEFINED : DestroyRecyclableJob -DEFERRED --[#blue]> UNDEFINED : DestroyRecyclableJob -SCHEDULED --[#blue]> UNDEFINED : DestroyRecyclableJob - -@enduml \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/StaticJobStatus.pu b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/StaticJobStatus.pu deleted file mode 100644 index 617a15d..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/StaticJobStatus.pu +++ /dev/null @@ -1,32 +0,0 @@ -@startuml - -skinparam classFontSize 8 -skinparam classFontName Helvetica - -state READY { -} -state SCHEDULED { -} -state DEFERRED { -} -state COMPLETED { -} -state CANCELED { -} -state UNDEFINED { -} - -[*] --[#blue]> READY : CreateJob -READY --[#blue]> SCHEDULED : Schedule -READY --[#blue]> DEFERRED : ScheduleDeferred -DEFERRED --[#red]> SCHEDULED : -SCHEDULED --[#green]> COMPLETED : -COMPLETED --[#blue]> READY : CreateJob - -READY --[#blue]> CANCELED : TryCancel -DEFERRED --[#blue]> CANCELED : TryCancel -SCHEDULED --[#blue]> CANCELED : TryCancel - -CANCELED --[#blue]> READY : CreateJob - -@enduml \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/https_client_async_callback_order.pu b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/https_client_async_callback_order.pu deleted file mode 100644 index 497d6b6..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/https_client_async_callback_order.pu +++ /dev/null @@ -1,15 +0,0 @@ -@startuml -hide empty description -[*] -right-> appendHeaderCallback -appendHeaderCallback -right-> writeCallback : Success -appendHeaderCallback -down-> errorCallback : Application cancels the request -writeCallback -down-> readReadyCallback : Success in network send -writeCallback -down-> errorCallback : Failure in network send \nor application cancels the request -readReadyCallback -down-> responseCompleteCallback : Success in everything and a \npersistent request -readReadyCallback -left-> errorCallback : Failure in network receive, response parsing, or the application cancels the request -readReadyCallback -down-> connectionCloseCallback : Success in everything and a \nnon-persistent request -errorCallback -down-> connectionCloseCallback : Network error or \nresponse parsing error -errorCallback -down-> responseCompleteCallback : Application cancels the requset -connectionCloseCallback -down-> responseCompleteCallback : Always -responseCompleteCallback -right-> [*] -@enduml diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/https_client_async_workflow.xml b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/https_client_async_workflow.xml deleted file mode 100644 index 8d6bbd8..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/https_client_async_workflow.xml +++ /dev/null @@ -1 +0,0 @@ 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\ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/https_client_sync_workflow.xml b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/https_client_sync_workflow.xml deleted file mode 100644 index 848491c..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/https_client_sync_workflow.xml +++ /dev/null @@ -1 +0,0 @@ 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a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/images/taskpool_design_typicaloperation.png b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/images/taskpool_design_typicaloperation.png deleted file mode 100644 index f423616..0000000 Binary files a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/images/taskpool_design_typicaloperation.png and /dev/null differ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/mqtt_demo.pu b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/mqtt_demo.pu deleted file mode 100644 index b46be74..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/mqtt_demo.pu +++ /dev/null @@ -1,38 +0,0 @@ -@startuml -skinparam classFontSize 8 -skinparam classFontName Helvetica -autonumber - -participant "Main Demo Thread" as main -participant "Incoming PUBLISH callback" as callback - -box "MQTT Client" #LightBlue - participant main - participant callback -end box - -participant "MQTT Server" as server - -main -> server: Subscribe to topic filters -server -> main: Subscription ACK - -loop AWS_IOT_DEMO_MQTT_PUBLISH_BURST_COUNT times - loop AWS_IOT_DEMO_MQTT_PUBLISH_BURST_SIZE times - main -> server: Publish "Hello world n!" - server -> main: Publish ACK - server -> server: Check for\nmatching subscriptions - server -> callback: Publish to\nmatching topic filter - callback -> server: Publish "Received message n" - callback -> main: Notify "Publish received" - server -> callback: Publish ACK - end - - main -> main: Wait for\nAWS_IOT_DEMO_MQTT_BURST_SIZE\nmessages to be received -end - -main -> server: Unsubscribe from topic filters -server -> main: Unsubscribe ACK - -main -> server: Disconnect - -@enduml diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/mqtt_design_typicaloperation.pu b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/mqtt_design_typicaloperation.pu deleted file mode 100644 index 50f8d42..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/mqtt_design_typicaloperation.pu +++ /dev/null @@ -1,71 +0,0 @@ -@startuml -skinparam classFontSize 8 -skinparam classFontName Helvetica -autonumber - -box "Application thread" #LightGreen - participant "Application" as application - create participant "MQTT API\nfunction" as api -end box - -database "Send queue" as send_queue - -== Enqueue Operation == -activate application -application -> api: Call MQTT\noperation\nfunction -deactivate application -activate api -api -> api: Allocate resources\nand generate\nMQTT packet -api -> send_queue: Add operation to\nsend queue -activate send_queue -api -> application: Return\nSTATUS_PENDING -destroy api -activate application - -== Transmit MQTT Packet == -create participant "Send thread" as send_thread -database "Receive queue" as receive_queue -participant "Network" as network - -send_queue -> send_thread: Remove oldest\noperation -activate send_thread -send_thread -> network: Transmit operation -activate network -send_thread -> receive_queue: Add operation to\nreceive queue -activate receive_queue -send_thread -> send_queue: Check for more\noperations -send_queue -> send_thread: Send queue empty -deactivate send_queue -destroy send_thread - -network -> network: Wait for\nserver response - -== Parse Server Response == -create participant "Receive\ncallback" as receive_callback -network -> receive_callback: Parse server\nresponse -deactivate network - -database "Callback queue" as callback_queue - -activate receive_callback -receive_callback -> receive_queue: Find operation\nwaiting for response -receive_queue -> receive_callback: Remove waiting\noperation -deactivate receive_queue -receive_callback -> callback_queue: Add operation to\ncallback queue -activate callback_queue -deactivate receive_callback - -== Notify Application of Result == -create participant "Callback\nthread" as callback_thread -callback_queue -> callback_thread: Remove oldest\noperation - -activate callback_thread -callback_thread -> application: Notify application\nof result -callback_thread -> callback_queue: Check for more\noperations -callback_queue -> callback_thread: Callback queue empty -deactivate callback_queue -destroy callback_thread - -deactivate application - -@enduml diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/taskpool_design_typicaloperation.pu b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/taskpool_design_typicaloperation.pu deleted file mode 100644 index dc77940..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/plantuml/taskpool_design_typicaloperation.pu +++ /dev/null @@ -1,77 +0,0 @@ -@startuml -skinparam classFontSize 8 -skinparam classFontName Helvetica -autonumber - -participant "Application" as app -participant "User Callback" as callback -participant "Job" as job - -participant "Task Pool public API" as TP -participant "Dispatch queue" as queue -participant "Worker Threads" as workers - -box "Task Pool" #LightBlue - participant TP - participant queue - participant workers -end box - -== Create Task Pool == - -activate app - -app -[#blue]> TP: IotTaskPool_Create: create a Task -TP -> queue: Initialize dispatch queue -activate queue -TP -> workers: Create minimum number of worker threads -activate workers -TP --[#blue]> app -activate TP -workers -> workers: Wait on incoming jobs - -== Use Task Pool == - -loop Application loop: Create and schedule jobs - app -[#blue]> TP: IotTaskPool_CreateRecyclableJob: create a job - TP --[#blue]> app - activate job - note left: job status: //ready// - - app -[#blue]> TP: IotTaskPool_Schedule: schedule a job - TP -> queue: Queue job - TP -> TP: Grow pool up to maximum threads, if all threads are busy - TP -> workers: Signal incoming job - TP --[#blue]> app - note left: job status: //scheduled// - - loop Outer dispatch loop: Wait on incoming jobs - workers -> queue: Dequeue next job - loop Inner dispatch loop: Execute any queue jobs in order - workers -[#green]> job: Invoke user callback - note left: job status: //executing// - job -[#green]> callback: Invoke - activate callback - callback -[#blue]> TP: IotTaskPool_RecycleJob: recycles job - TP --[#blue]> callback - note left: job status: //completed// - deactivate job - deactivate callback - workers -> workers: Move to next job - end - workers -> workers: Wait on incoming jobs - end - -end - -== Destroy Task Pool == - - app -[#blue]> TP: IotTaskPool_Destroy: destroy the task pool - TP -> workers: Shutdown worker threads - deactivate workers - TP -> queue: Destroy all jobs in the dispatch queue - deactivate queue - TP --[#blue]> app - deactivate TP - -@enduml diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/tag/README.md b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/tag/README.md deleted file mode 100644 index 32bcacf..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/tag/README.md +++ /dev/null @@ -1,4 +0,0 @@ -This folder is for generating working Doxygen tags. -During Doxygen generation, this folder needs to be present. -\.tag will be created in this folder. -Deleting this folder may cause generation to fail. \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/user_guide/global_config.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/user_guide/global_config.txt deleted file mode 100644 index 22bf1fe..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/doc/user_guide/global_config.txt +++ /dev/null @@ -1,5 +0,0 @@ -/** -@page ug_globalconfig Global configuration -@brief Configuration settings that affect all libraries. - -*/ \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/croutine.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/croutine.c deleted file mode 100644 index ff2b20e..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/croutine.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/* Remove the whole file is co-routines are not being used. */ -#if( configUSE_CO_ROUTINES != 0 ) - -/* - * Some kernel aware debuggers require data to be viewed to be global, rather - * than file scope. - */ -#ifdef portREMOVE_STATIC_QUALIFIER - #define static -#endif - - -/* Lists for ready and blocked co-routines. --------------------*/ -static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ -static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */ -static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ -static List_t * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ -static List_t * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ -static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ - -/* Other file private variables. --------------------------------*/ -CRCB_t * pxCurrentCoRoutine = NULL; -static UBaseType_t uxTopCoRoutineReadyPriority = 0; -static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0; - -/* The initial state of the co-routine when it is created. */ -#define corINITIAL_STATE ( 0 ) - -/* - * Place the co-routine represented by pxCRCB into the appropriate ready queue - * for the priority. It is inserted at the end of the list. - * - * This macro accesses the co-routine ready lists and therefore must not be - * used from within an ISR. - */ -#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ -{ \ - if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ - { \ - uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ - } \ - vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ -} - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first co-routine. - */ -static void prvInitialiseCoRoutineLists( void ); - -/* - * Co-routines that are readied by an interrupt cannot be placed directly into - * the ready lists (there is no mutual exclusion). Instead they are placed in - * in the pending ready list in order that they can later be moved to the ready - * list by the co-routine scheduler. - */ -static void prvCheckPendingReadyList( void ); - -/* - * Macro that looks at the list of co-routines that are currently delayed to - * see if any require waking. - * - * Co-routines are stored in the queue in the order of their wake time - - * meaning once one co-routine has been found whose timer has not expired - * we need not look any further down the list. - */ -static void prvCheckDelayedList( void ); - -/*-----------------------------------------------------------*/ - -BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ) -{ -BaseType_t xReturn; -CRCB_t *pxCoRoutine; - - /* Allocate the memory that will store the co-routine control block. */ - pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) ); - if( pxCoRoutine ) - { - /* If pxCurrentCoRoutine is NULL then this is the first co-routine to - be created and the co-routine data structures need initialising. */ - if( pxCurrentCoRoutine == NULL ) - { - pxCurrentCoRoutine = pxCoRoutine; - prvInitialiseCoRoutineLists(); - } - - /* Check the priority is within limits. */ - if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) - { - uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; - } - - /* Fill out the co-routine control block from the function parameters. */ - pxCoRoutine->uxState = corINITIAL_STATE; - pxCoRoutine->uxPriority = uxPriority; - pxCoRoutine->uxIndex = uxIndex; - pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; - - /* Initialise all the other co-routine control block parameters. */ - vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); - vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); - - /* Set the co-routine control block as a link back from the ListItem_t. - This is so we can get back to the containing CRCB from a generic item - in a list. */ - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) ); - - /* Now the co-routine has been initialised it can be added to the ready - list at the correct priority. */ - prvAddCoRoutineToReadyQueue( pxCoRoutine ); - - xReturn = pdPASS; - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ) -{ -TickType_t xTimeToWake; - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xCoRoutineTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xCoRoutineTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - - if( pxEventList ) - { - /* Also add the co-routine to an event list. If this is done then the - function must be called with interrupts disabled. */ - vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); - } -} -/*-----------------------------------------------------------*/ - -static void prvCheckPendingReadyList( void ) -{ - /* Are there any co-routines waiting to get moved to the ready list? These - are co-routines that have been readied by an ISR. The ISR cannot access - the ready lists itself. */ - while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE ) - { - CRCB_t *pxUnblockedCRCB; - - /* The pending ready list can be accessed by an ISR. */ - portDISABLE_INTERRUPTS(); - { - pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) ); - ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - } - portENABLE_INTERRUPTS(); - - ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); - prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); - } -} -/*-----------------------------------------------------------*/ - -static void prvCheckDelayedList( void ) -{ -CRCB_t *pxCRCB; - - xPassedTicks = xTaskGetTickCount() - xLastTickCount; - while( xPassedTicks ) - { - xCoRoutineTickCount++; - xPassedTicks--; - - /* If the tick count has overflowed we need to swap the ready lists. */ - if( xCoRoutineTickCount == 0 ) - { - List_t * pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. If there are - any items in pxDelayedCoRoutineList here then there is an error! */ - pxTemp = pxDelayedCoRoutineList; - pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; - pxOverflowDelayedCoRoutineList = pxTemp; - } - - /* See if this tick has made a timeout expire. */ - while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE ) - { - pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ); - - if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) - { - /* Timeout not yet expired. */ - break; - } - - portDISABLE_INTERRUPTS(); - { - /* The event could have occurred just before this critical - section. If this is the case then the generic list item will - have been moved to the pending ready list and the following - line is still valid. Also the pvContainer parameter will have - been set to NULL so the following lines are also valid. */ - ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); - - /* Is the co-routine waiting on an event also? */ - if( pxCRCB->xEventListItem.pxContainer ) - { - ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); - } - } - portENABLE_INTERRUPTS(); - - prvAddCoRoutineToReadyQueue( pxCRCB ); - } - } - - xLastTickCount = xCoRoutineTickCount; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineSchedule( void ) -{ - /* See if any co-routines readied by events need moving to the ready lists. */ - prvCheckPendingReadyList(); - - /* See if any delayed co-routines have timed out. */ - prvCheckDelayedList(); - - /* Find the highest priority queue that contains ready co-routines. */ - while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) - { - if( uxTopCoRoutineReadyPriority == 0 ) - { - /* No more co-routines to check. */ - return; - } - --uxTopCoRoutineReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines - of the same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); - - /* Call the co-routine. */ - ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); - - return; -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseCoRoutineLists( void ) -{ -UBaseType_t uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); - } - - vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 ); - vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 ); - vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList ); - - /* Start with pxDelayedCoRoutineList using list1 and the - pxOverflowDelayedCoRoutineList using list2. */ - pxDelayedCoRoutineList = &xDelayedCoRoutineList1; - pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; -} -/*-----------------------------------------------------------*/ - -BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ) -{ -CRCB_t *pxUnblockedCRCB; -BaseType_t xReturn; - - /* This function is called from within an interrupt. It can only access - event lists and the pending ready list. This function assumes that a - check has already been made to ensure pxEventList is not empty. */ - pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); - - if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) - { - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} - -#endif /* configUSE_CO_ROUTINES == 0 */ \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/event_groups.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/event_groups.c deleted file mode 100644 index 81c1965..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/event_groups.c +++ /dev/null @@ -1,753 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Standard includes. */ -#include - -/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining -all the API functions to use the MPU wrappers. That should only be done when -task.h is included from an application file. */ -#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "timers.h" -#include "event_groups.h" - -/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified -because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined -for the header files above, but not in this file, in order to generate the -correct privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ - -/* The following bit fields convey control information in a task's event list -item value. It is important they don't clash with the -taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ -#if configUSE_16_BIT_TICKS == 1 - #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U - #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U - #define eventWAIT_FOR_ALL_BITS 0x0400U - #define eventEVENT_BITS_CONTROL_BYTES 0xff00U -#else - #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL - #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL - #define eventWAIT_FOR_ALL_BITS 0x04000000UL - #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL -#endif - -typedef struct EventGroupDef_t -{ - EventBits_t uxEventBits; - List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ - - #if( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxEventGroupNumber; - #endif - - #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) - uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ - #endif -} EventGroup_t; - -/*-----------------------------------------------------------*/ - -/* - * Test the bits set in uxCurrentEventBits to see if the wait condition is met. - * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is - * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor - * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the - * wait condition is met if any of the bits set in uxBitsToWait for are also set - * in uxCurrentEventBits. - */ -static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; - -/*-----------------------------------------------------------*/ - -#if( configSUPPORT_STATIC_ALLOCATION == 1 ) - - EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) - { - EventGroup_t *pxEventBits; - - /* A StaticEventGroup_t object must be provided. */ - configASSERT( pxEventGroupBuffer ); - - #if( configASSERT_DEFINED == 1 ) - { - /* Sanity check that the size of the structure used to declare a - variable of type StaticEventGroup_t equals the size of the real - event group structure. */ - volatile size_t xSize = sizeof( StaticEventGroup_t ); - configASSERT( xSize == sizeof( EventGroup_t ) ); - } /*lint !e529 xSize is referenced if configASSERT() is defined. */ - #endif /* configASSERT_DEFINED */ - - /* The user has provided a statically allocated event group - use it. */ - pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ - - if( pxEventBits != NULL ) - { - pxEventBits->uxEventBits = 0; - vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); - - #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - { - /* Both static and dynamic allocation can be used, so note that - this event group was created statically in case the event group - is later deleted. */ - pxEventBits->ucStaticallyAllocated = pdTRUE; - } - #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ - - traceEVENT_GROUP_CREATE( pxEventBits ); - } - else - { - /* xEventGroupCreateStatic should only ever be called with - pxEventGroupBuffer pointing to a pre-allocated (compile time - allocated) StaticEventGroup_t variable. */ - traceEVENT_GROUP_CREATE_FAILED(); - } - - return pxEventBits; - } - -#endif /* configSUPPORT_STATIC_ALLOCATION */ -/*-----------------------------------------------------------*/ - -#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - - EventGroupHandle_t xEventGroupCreate( void ) - { - EventGroup_t *pxEventBits; - - /* Allocate the event group. Justification for MISRA deviation as - follows: pvPortMalloc() always ensures returned memory blocks are - aligned per the requirements of the MCU stack. In this case - pvPortMalloc() must return a pointer that is guaranteed to meet the - alignment requirements of the EventGroup_t structure - which (if you - follow it through) is the alignment requirements of the TickType_t type - (EventBits_t being of TickType_t itself). Therefore, whenever the - stack alignment requirements are greater than or equal to the - TickType_t alignment requirements the cast is safe. In other cases, - where the natural word size of the architecture is less than - sizeof( TickType_t ), the TickType_t variables will be accessed in two - or more reads operations, and the alignment requirements is only that - of each individual read. */ - pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ - - if( pxEventBits != NULL ) - { - pxEventBits->uxEventBits = 0; - vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); - - #if( configSUPPORT_STATIC_ALLOCATION == 1 ) - { - /* Both static and dynamic allocation can be used, so note this - event group was allocated statically in case the event group is - later deleted. */ - pxEventBits->ucStaticallyAllocated = pdFALSE; - } - #endif /* configSUPPORT_STATIC_ALLOCATION */ - - traceEVENT_GROUP_CREATE( pxEventBits ); - } - else - { - traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ - } - - return pxEventBits; - } - -#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ -/*-----------------------------------------------------------*/ - -EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) -{ -EventBits_t uxOriginalBitValue, uxReturn; -EventGroup_t *pxEventBits = xEventGroup; -BaseType_t xAlreadyYielded; -BaseType_t xTimeoutOccurred = pdFALSE; - - configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); - configASSERT( uxBitsToWaitFor != 0 ); - #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) - { - configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); - } - #endif - - vTaskSuspendAll(); - { - uxOriginalBitValue = pxEventBits->uxEventBits; - - ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); - - if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) - { - /* All the rendezvous bits are now set - no need to block. */ - uxReturn = ( uxOriginalBitValue | uxBitsToSet ); - - /* Rendezvous always clear the bits. They will have been cleared - already unless this is the only task in the rendezvous. */ - pxEventBits->uxEventBits &= ~uxBitsToWaitFor; - - xTicksToWait = 0; - } - else - { - if( xTicksToWait != ( TickType_t ) 0 ) - { - traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); - - /* Store the bits that the calling task is waiting for in the - task's event list item so the kernel knows when a match is - found. Then enter the blocked state. */ - vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); - - /* This assignment is obsolete as uxReturn will get set after - the task unblocks, but some compilers mistakenly generate a - warning about uxReturn being returned without being set if the - assignment is omitted. */ - uxReturn = 0; - } - else - { - /* The rendezvous bits were not set, but no block time was - specified - just return the current event bit value. */ - uxReturn = pxEventBits->uxEventBits; - xTimeoutOccurred = pdTRUE; - } - } - } - xAlreadyYielded = xTaskResumeAll(); - - if( xTicksToWait != ( TickType_t ) 0 ) - { - if( xAlreadyYielded == pdFALSE ) - { - portYIELD_WITHIN_API(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - - /* The task blocked to wait for its required bits to be set - at this - point either the required bits were set or the block time expired. If - the required bits were set they will have been stored in the task's - event list item, and they should now be retrieved then cleared. */ - uxReturn = uxTaskResetEventItemValue(); - - if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) - { - /* The task timed out, just return the current event bit value. */ - taskENTER_CRITICAL(); - { - uxReturn = pxEventBits->uxEventBits; - - /* Although the task got here because it timed out before the - bits it was waiting for were set, it is possible that since it - unblocked another task has set the bits. If this is the case - then it needs to clear the bits before exiting. */ - if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) - { - pxEventBits->uxEventBits &= ~uxBitsToWaitFor; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - taskEXIT_CRITICAL(); - - xTimeoutOccurred = pdTRUE; - } - else - { - /* The task unblocked because the bits were set. */ - } - - /* Control bits might be set as the task had blocked should not be - returned. */ - uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; - } - - traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); - - /* Prevent compiler warnings when trace macros are not used. */ - ( void ) xTimeoutOccurred; - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) -{ -EventGroup_t *pxEventBits = xEventGroup; -EventBits_t uxReturn, uxControlBits = 0; -BaseType_t xWaitConditionMet, xAlreadyYielded; -BaseType_t xTimeoutOccurred = pdFALSE; - - /* Check the user is not attempting to wait on the bits used by the kernel - itself, and that at least one bit is being requested. */ - configASSERT( xEventGroup ); - configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); - configASSERT( uxBitsToWaitFor != 0 ); - #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) - { - configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); - } - #endif - - vTaskSuspendAll(); - { - const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; - - /* Check to see if the wait condition is already met or not. */ - xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); - - if( xWaitConditionMet != pdFALSE ) - { - /* The wait condition has already been met so there is no need to - block. */ - uxReturn = uxCurrentEventBits; - xTicksToWait = ( TickType_t ) 0; - - /* Clear the wait bits if requested to do so. */ - if( xClearOnExit != pdFALSE ) - { - pxEventBits->uxEventBits &= ~uxBitsToWaitFor; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - else if( xTicksToWait == ( TickType_t ) 0 ) - { - /* The wait condition has not been met, but no block time was - specified, so just return the current value. */ - uxReturn = uxCurrentEventBits; - xTimeoutOccurred = pdTRUE; - } - else - { - /* The task is going to block to wait for its required bits to be - set. uxControlBits are used to remember the specified behaviour of - this call to xEventGroupWaitBits() - for use when the event bits - unblock the task. */ - if( xClearOnExit != pdFALSE ) - { - uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - - if( xWaitForAllBits != pdFALSE ) - { - uxControlBits |= eventWAIT_FOR_ALL_BITS; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - - /* Store the bits that the calling task is waiting for in the - task's event list item so the kernel knows when a match is - found. Then enter the blocked state. */ - vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); - - /* This is obsolete as it will get set after the task unblocks, but - some compilers mistakenly generate a warning about the variable - being returned without being set if it is not done. */ - uxReturn = 0; - - traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); - } - } - xAlreadyYielded = xTaskResumeAll(); - - if( xTicksToWait != ( TickType_t ) 0 ) - { - if( xAlreadyYielded == pdFALSE ) - { - portYIELD_WITHIN_API(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - - /* The task blocked to wait for its required bits to be set - at this - point either the required bits were set or the block time expired. If - the required bits were set they will have been stored in the task's - event list item, and they should now be retrieved then cleared. */ - uxReturn = uxTaskResetEventItemValue(); - - if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) - { - taskENTER_CRITICAL(); - { - /* The task timed out, just return the current event bit value. */ - uxReturn = pxEventBits->uxEventBits; - - /* It is possible that the event bits were updated between this - task leaving the Blocked state and running again. */ - if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) - { - if( xClearOnExit != pdFALSE ) - { - pxEventBits->uxEventBits &= ~uxBitsToWaitFor; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - xTimeoutOccurred = pdTRUE; - } - taskEXIT_CRITICAL(); - } - else - { - /* The task unblocked because the bits were set. */ - } - - /* The task blocked so control bits may have been set. */ - uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; - } - traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); - - /* Prevent compiler warnings when trace macros are not used. */ - ( void ) xTimeoutOccurred; - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) -{ -EventGroup_t *pxEventBits = xEventGroup; -EventBits_t uxReturn; - - /* Check the user is not attempting to clear the bits used by the kernel - itself. */ - configASSERT( xEventGroup ); - configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); - - taskENTER_CRITICAL(); - { - traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); - - /* The value returned is the event group value prior to the bits being - cleared. */ - uxReturn = pxEventBits->uxEventBits; - - /* Clear the bits. */ - pxEventBits->uxEventBits &= ~uxBitsToClear; - } - taskEXIT_CRITICAL(); - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) - - BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) - { - BaseType_t xReturn; - - traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); - xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ - - return xReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) -{ -UBaseType_t uxSavedInterruptStatus; -EventGroup_t const * const pxEventBits = xEventGroup; -EventBits_t uxReturn; - - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); - { - uxReturn = pxEventBits->uxEventBits; - } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); - - return uxReturn; -} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ -/*-----------------------------------------------------------*/ - -EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) -{ -ListItem_t *pxListItem, *pxNext; -ListItem_t const *pxListEnd; -List_t const * pxList; -EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; -EventGroup_t *pxEventBits = xEventGroup; -BaseType_t xMatchFound = pdFALSE; - - /* Check the user is not attempting to set the bits used by the kernel - itself. */ - configASSERT( xEventGroup ); - configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); - - pxList = &( pxEventBits->xTasksWaitingForBits ); - pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ - vTaskSuspendAll(); - { - traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); - - pxListItem = listGET_HEAD_ENTRY( pxList ); - - /* Set the bits. */ - pxEventBits->uxEventBits |= uxBitsToSet; - - /* See if the new bit value should unblock any tasks. */ - while( pxListItem != pxListEnd ) - { - pxNext = listGET_NEXT( pxListItem ); - uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); - xMatchFound = pdFALSE; - - /* Split the bits waited for from the control bits. */ - uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; - uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; - - if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) - { - /* Just looking for single bit being set. */ - if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) - { - xMatchFound = pdTRUE; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) - { - /* All bits are set. */ - xMatchFound = pdTRUE; - } - else - { - /* Need all bits to be set, but not all the bits were set. */ - } - - if( xMatchFound != pdFALSE ) - { - /* The bits match. Should the bits be cleared on exit? */ - if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) - { - uxBitsToClear |= uxBitsWaitedFor; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - - /* Store the actual event flag value in the task's event list - item before removing the task from the event list. The - eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows - that is was unblocked due to its required bits matching, rather - than because it timed out. */ - vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); - } - - /* Move onto the next list item. Note pxListItem->pxNext is not - used here as the list item may have been removed from the event list - and inserted into the ready/pending reading list. */ - pxListItem = pxNext; - } - - /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT - bit was set in the control word. */ - pxEventBits->uxEventBits &= ~uxBitsToClear; - } - ( void ) xTaskResumeAll(); - - return pxEventBits->uxEventBits; -} -/*-----------------------------------------------------------*/ - -void vEventGroupDelete( EventGroupHandle_t xEventGroup ) -{ -EventGroup_t *pxEventBits = xEventGroup; -const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); - - vTaskSuspendAll(); - { - traceEVENT_GROUP_DELETE( xEventGroup ); - - while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) - { - /* Unblock the task, returning 0 as the event list is being deleted - and cannot therefore have any bits set. */ - configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); - vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); - } - - #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) - { - /* The event group can only have been allocated dynamically - free - it again. */ - vPortFree( pxEventBits ); - } - #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) - { - /* The event group could have been allocated statically or - dynamically, so check before attempting to free the memory. */ - if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) - { - vPortFree( pxEventBits ); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ - } - ( void ) xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -/* For internal use only - execute a 'set bits' command that was pended from -an interrupt. */ -void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) -{ - ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ -} -/*-----------------------------------------------------------*/ - -/* For internal use only - execute a 'clear bits' command that was pended from -an interrupt. */ -void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) -{ - ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ -} -/*-----------------------------------------------------------*/ - -static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) -{ -BaseType_t xWaitConditionMet = pdFALSE; - - if( xWaitForAllBits == pdFALSE ) - { - /* Task only has to wait for one bit within uxBitsToWaitFor to be - set. Is one already set? */ - if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) - { - xWaitConditionMet = pdTRUE; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - else - { - /* Task has to wait for all the bits in uxBitsToWaitFor to be set. - Are they set already? */ - if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) - { - xWaitConditionMet = pdTRUE; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - - return xWaitConditionMet; -} -/*-----------------------------------------------------------*/ - -#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) - - BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) - { - BaseType_t xReturn; - - traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); - xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ - - return xReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if (configUSE_TRACE_FACILITY == 1) - - UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) - { - UBaseType_t xReturn; - EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ - - if( xEventGroup == NULL ) - { - xReturn = 0; - } - else - { - xReturn = pxEventBits->uxEventGroupNumber; - } - - return xReturn; - } - -#endif /* configUSE_TRACE_FACILITY */ -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber ) - { - ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ - } - -#endif /* configUSE_TRACE_FACILITY */ -/*-----------------------------------------------------------*/ - - diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/FreeRTOS.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/FreeRTOS.h deleted file mode 100644 index 26443ed..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/FreeRTOS.h +++ /dev/null @@ -1,1325 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - * - * Copyright 2019 MicroEJ Corp. This file has been modified by MicroEJ Corp. - * 1. Patch for SystemView support - */ - -#ifndef INC_FREERTOS_H -#define INC_FREERTOS_H - -/* - * Include the generic headers required for the FreeRTOS port being used. - */ -#include - -/* - * If stdint.h cannot be located then: - * + If using GCC ensure the -nostdint options is *not* being used. - * + Ensure the project's include path includes the directory in which your - * compiler stores stdint.h. - * + Set any compiler options necessary for it to support C99, as technically - * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any - * other way). - * + The FreeRTOS download includes a simple stdint.h definition that can be - * used in cases where none is provided by the compiler. The files only - * contains the typedefs required to build FreeRTOS. Read the instructions - * in FreeRTOS/source/stdint.readme for more information. - */ -#include /* READ COMMENT ABOVE. */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Application specific configuration options. */ -#include "FreeRTOSConfig.h" - -/* Basic FreeRTOS definitions. */ -#include "projdefs.h" - -/* Definitions specific to the port being used. */ -#include "portable.h" - -/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ -#ifndef configUSE_NEWLIB_REENTRANT - #define configUSE_NEWLIB_REENTRANT 0 -#endif - -/* Required if struct _reent is used. */ -#if ( configUSE_NEWLIB_REENTRANT == 1 ) - #include -#endif -/* - * Check all the required application specific macros have been defined. - * These macros are application specific and (as downloaded) are defined - * within FreeRTOSConfig.h. - */ - -#ifndef configMINIMAL_STACK_SIZE - #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. -#endif - -#ifndef configMAX_PRIORITIES - #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#if configMAX_PRIORITIES < 1 - #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. -#endif - -#ifndef configUSE_PREEMPTION - #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_IDLE_HOOK - #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_TICK_HOOK - #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_16_BIT_TICKS - #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_CO_ROUTINES - #define configUSE_CO_ROUTINES 0 -#endif - -#ifndef INCLUDE_vTaskPrioritySet - #define INCLUDE_vTaskPrioritySet 0 -#endif - -#ifndef INCLUDE_uxTaskPriorityGet - #define INCLUDE_uxTaskPriorityGet 0 -#endif - -#ifndef INCLUDE_vTaskDelete - #define INCLUDE_vTaskDelete 0 -#endif - -#ifndef INCLUDE_vTaskSuspend - #define INCLUDE_vTaskSuspend 0 -#endif - -#ifndef INCLUDE_vTaskDelayUntil - #define INCLUDE_vTaskDelayUntil 0 -#endif - -#ifndef INCLUDE_vTaskDelay - #define INCLUDE_vTaskDelay 0 -#endif - -#ifndef INCLUDE_xTaskGetIdleTaskHandle - #define INCLUDE_xTaskGetIdleTaskHandle 0 -#endif - -#ifndef INCLUDE_xTaskAbortDelay - #define INCLUDE_xTaskAbortDelay 0 -#endif - -#ifndef INCLUDE_xQueueGetMutexHolder - #define INCLUDE_xQueueGetMutexHolder 0 -#endif - -#ifndef INCLUDE_xSemaphoreGetMutexHolder - #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder -#endif - -#ifndef INCLUDE_xTaskGetHandle - #define INCLUDE_xTaskGetHandle 0 -#endif - -#ifndef INCLUDE_uxTaskGetStackHighWaterMark - #define INCLUDE_uxTaskGetStackHighWaterMark 0 -#endif - -#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 - #define INCLUDE_uxTaskGetStackHighWaterMark2 0 -#endif - -#ifndef INCLUDE_pxTaskGetStackStart - #define INCLUDE_pxTaskGetStackStart 0 -#endif - -#ifndef INCLUDE_eTaskGetState - #define INCLUDE_eTaskGetState 0 -#endif - -#ifndef INCLUDE_xTaskResumeFromISR - #define INCLUDE_xTaskResumeFromISR 1 -#endif - -#ifndef INCLUDE_xTimerPendFunctionCall - #define INCLUDE_xTimerPendFunctionCall 0 -#endif - -#ifndef INCLUDE_xTaskGetSchedulerState - #define INCLUDE_xTaskGetSchedulerState 0 -#endif - -#ifndef INCLUDE_xTaskGetCurrentTaskHandle - #define INCLUDE_xTaskGetCurrentTaskHandle 0 -#endif - -#if configUSE_CO_ROUTINES != 0 - #ifndef configMAX_CO_ROUTINE_PRIORITIES - #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. - #endif -#endif - -#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK - #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 -#endif - -#ifndef configUSE_APPLICATION_TASK_TAG - #define configUSE_APPLICATION_TASK_TAG 0 -#endif - -#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS - #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 -#endif - -#ifndef configUSE_RECURSIVE_MUTEXES - #define configUSE_RECURSIVE_MUTEXES 0 -#endif - -#ifndef configUSE_MUTEXES - #define configUSE_MUTEXES 0 -#endif - -#ifndef configUSE_TIMERS - #define configUSE_TIMERS 0 -#endif - -#ifndef configUSE_COUNTING_SEMAPHORES - #define configUSE_COUNTING_SEMAPHORES 0 -#endif - -#ifndef configUSE_ALTERNATIVE_API - #define configUSE_ALTERNATIVE_API 0 -#endif - -#ifndef portCRITICAL_NESTING_IN_TCB - #define portCRITICAL_NESTING_IN_TCB 0 -#endif - -#ifndef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 16 -#endif - -#ifndef configIDLE_SHOULD_YIELD - #define configIDLE_SHOULD_YIELD 1 -#endif - -#if configMAX_TASK_NAME_LEN < 1 - #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h -#endif - -#ifndef configASSERT - #define configASSERT( x ) - #define configASSERT_DEFINED 0 -#else - #define configASSERT_DEFINED 1 -#endif - -/* configPRECONDITION should be resolve to configASSERT. - The CBMC proofs need a way to track assumptions and assertions. - A configPRECONDITION statement should express an implicit invariant or assumption made. - A configASSERT statement should express an invariant that must hold explicit before calling - the code. */ -#ifndef configPRECONDITION - #define configPRECONDITION( X ) configASSERT(X) - #define configPRECONDITION_DEFINED 0 -#else - #define configPRECONDITION_DEFINED 1 -#endif - -#ifndef portMEMORY_BARRIER - #define portMEMORY_BARRIER() -#endif - -/* The timers module relies on xTaskGetSchedulerState(). */ -#if configUSE_TIMERS == 1 - - #ifndef configTIMER_TASK_PRIORITY - #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. - #endif /* configTIMER_TASK_PRIORITY */ - - #ifndef configTIMER_QUEUE_LENGTH - #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. - #endif /* configTIMER_QUEUE_LENGTH */ - - #ifndef configTIMER_TASK_STACK_DEPTH - #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. - #endif /* configTIMER_TASK_STACK_DEPTH */ - -#endif /* configUSE_TIMERS */ - -#ifndef portSET_INTERRUPT_MASK_FROM_ISR - #define portSET_INTERRUPT_MASK_FROM_ISR() 0 -#endif - -#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue -#endif - -#ifndef portCLEAN_UP_TCB - #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB -#endif - -#ifndef portPRE_TASK_DELETE_HOOK - #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) -#endif - -#ifndef portSETUP_TCB - #define portSETUP_TCB( pxTCB ) ( void ) pxTCB -#endif - -#ifndef configQUEUE_REGISTRY_SIZE - #define configQUEUE_REGISTRY_SIZE 0U -#endif - -#if ( configQUEUE_REGISTRY_SIZE < 1 ) - #define vQueueAddToRegistry( xQueue, pcName ) - #define vQueueUnregisterQueue( xQueue ) - #define pcQueueGetName( xQueue ) -#endif - -#ifndef portPOINTER_SIZE_TYPE - #define portPOINTER_SIZE_TYPE uint32_t -#endif - -/* Remove any unused trace macros. */ -#ifndef traceSTART - /* Used to perform any necessary initialisation - for example, open a file - into which trace is to be written. */ - #define traceSTART() -#endif - -#ifndef traceEND - /* Use to close a trace, for example close a file into which trace has been - written. */ - #define traceEND() -#endif - -#ifndef traceTASK_SWITCHED_IN - /* Called after a task has been selected to run. pxCurrentTCB holds a pointer - to the task control block of the selected task. */ - #define traceTASK_SWITCHED_IN() -#endif - -#ifndef traceINCREASE_TICK_COUNT - /* Called before stepping the tick count after waking from tickless idle - sleep. */ - #define traceINCREASE_TICK_COUNT( x ) -#endif - -#ifndef traceLOW_POWER_IDLE_BEGIN - /* Called immediately before entering tickless idle. */ - #define traceLOW_POWER_IDLE_BEGIN() -#endif - -#ifndef traceLOW_POWER_IDLE_END - /* Called when returning to the Idle task after a tickless idle. */ - #define traceLOW_POWER_IDLE_END() -#endif - -#ifndef traceTASK_SWITCHED_OUT - /* Called before a task has been selected to run. pxCurrentTCB holds a pointer - to the task control block of the task being switched out. */ - #define traceTASK_SWITCHED_OUT() -#endif - -#ifndef traceTASK_PRIORITY_INHERIT - /* Called when a task attempts to take a mutex that is already held by a - lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task - that holds the mutex. uxInheritedPriority is the priority the mutex holder - will inherit (the priority of the task that is attempting to obtain the - muted. */ - #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) -#endif - -#ifndef traceTASK_PRIORITY_DISINHERIT - /* Called when a task releases a mutex, the holding of which had resulted in - the task inheriting the priority of a higher priority task. - pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the - mutex. uxOriginalPriority is the task's configured (base) priority. */ - #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) -#endif - -#ifndef traceBLOCKING_ON_QUEUE_RECEIVE - /* Task is about to block because it cannot read from a - queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore - upon which the read was attempted. pxCurrentTCB points to the TCB of the - task that attempted the read. */ - #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) -#endif - -#ifndef traceBLOCKING_ON_QUEUE_PEEK - /* Task is about to block because it cannot read from a - queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore - upon which the read was attempted. pxCurrentTCB points to the TCB of the - task that attempted the read. */ - #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) -#endif - -#ifndef traceBLOCKING_ON_QUEUE_SEND - /* Task is about to block because it cannot write to a - queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore - upon which the write was attempted. pxCurrentTCB points to the TCB of the - task that attempted the write. */ - #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) -#endif - -#ifndef configCHECK_FOR_STACK_OVERFLOW - #define configCHECK_FOR_STACK_OVERFLOW 0 -#endif - -#ifndef configRECORD_STACK_HIGH_ADDRESS - #define configRECORD_STACK_HIGH_ADDRESS 0 -#endif - -#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H - #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 -#endif - -/* The following event macros are embedded in the kernel API calls. */ - -#ifndef traceMOVED_TASK_TO_READY_STATE - #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) -#endif - -#ifndef tracePOST_MOVED_TASK_TO_READY_STATE - #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) -#endif - -#ifndef traceREADDED_TASK_TO_READY_STATE - #define traceREADDED_TASK_TO_READY_STATE( pxTCB ) traceMOVED_TASK_TO_READY_STATE( pxTCB ) -#endif - -#ifndef traceMOVED_TASK_TO_DELAYED_LIST - #define traceMOVED_TASK_TO_DELAYED_LIST() -#endif - -#ifndef traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST - #define traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST() -#endif - -#ifndef traceMOVED_TASK_TO_SUSPENDED_LIST - #define traceMOVED_TASK_TO_SUSPENDED_LIST( pxTCB ) -#endif - -#ifndef traceQUEUE_CREATE - #define traceQUEUE_CREATE( pxNewQueue ) -#endif - -#ifndef traceQUEUE_CREATE_FAILED - #define traceQUEUE_CREATE_FAILED( ucQueueType ) -#endif - -#ifndef traceCREATE_MUTEX - #define traceCREATE_MUTEX( pxNewQueue ) -#endif - -#ifndef traceCREATE_MUTEX_FAILED - #define traceCREATE_MUTEX_FAILED() -#endif - -#ifndef traceGIVE_MUTEX_RECURSIVE - #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) -#endif - -#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED - #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) -#endif - -#ifndef traceTAKE_MUTEX_RECURSIVE - #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) -#endif - -#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED - #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) -#endif - -#ifndef traceCREATE_COUNTING_SEMAPHORE - #define traceCREATE_COUNTING_SEMAPHORE() -#endif - -#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED - #define traceCREATE_COUNTING_SEMAPHORE_FAILED() -#endif - -#ifndef traceQUEUE_SEND - #define traceQUEUE_SEND( pxQueue ) -#endif - -#ifndef traceQUEUE_SEND_FAILED - #define traceQUEUE_SEND_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_RECEIVE - #define traceQUEUE_RECEIVE( pxQueue ) -#endif - -#ifndef traceQUEUE_PEEK - #define traceQUEUE_PEEK( pxQueue ) -#endif - -#ifndef traceQUEUE_PEEK_FAILED - #define traceQUEUE_PEEK_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_PEEK_FROM_ISR - #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) -#endif - -#ifndef traceQUEUE_RECEIVE_FAILED - #define traceQUEUE_RECEIVE_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_SEND_FROM_ISR - #define traceQUEUE_SEND_FROM_ISR( pxQueue ) -#endif - -#ifndef traceQUEUE_SEND_FROM_ISR_FAILED - #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_RECEIVE_FROM_ISR - #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) -#endif - -#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED - #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED - #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_DELETE - #define traceQUEUE_DELETE( pxQueue ) -#endif - -#ifndef traceTASK_CREATE - #define traceTASK_CREATE( pxNewTCB ) -#endif - -#ifndef traceTASK_CREATE_FAILED - #define traceTASK_CREATE_FAILED() -#endif - -#ifndef traceTASK_DELETE - #define traceTASK_DELETE( pxTaskToDelete ) -#endif - -#ifndef traceTASK_DELAY_UNTIL - #define traceTASK_DELAY_UNTIL( x ) -#endif - -#ifndef traceTASK_DELAY - #define traceTASK_DELAY() -#endif - -#ifndef traceTASK_PRIORITY_SET - #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) -#endif - -#ifndef traceTASK_SUSPEND - #define traceTASK_SUSPEND( pxTaskToSuspend ) -#endif - -#ifndef traceTASK_RESUME - #define traceTASK_RESUME( pxTaskToResume ) -#endif - -#ifndef traceTASK_RESUME_FROM_ISR - #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) -#endif - -#ifndef traceTASK_INCREMENT_TICK - #define traceTASK_INCREMENT_TICK( xTickCount ) -#endif - -#ifndef traceTIMER_CREATE - #define traceTIMER_CREATE( pxNewTimer ) -#endif - -#ifndef traceTIMER_CREATE_FAILED - #define traceTIMER_CREATE_FAILED() -#endif - -#ifndef traceTIMER_COMMAND_SEND - #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) -#endif - -#ifndef traceTIMER_EXPIRED - #define traceTIMER_EXPIRED( pxTimer ) -#endif - -#ifndef traceTIMER_COMMAND_RECEIVED - #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) -#endif - -#ifndef traceMALLOC - #define traceMALLOC( pvAddress, uiSize ) -#endif - -#ifndef traceFREE - #define traceFREE( pvAddress, uiSize ) -#endif - -#ifndef traceEVENT_GROUP_CREATE - #define traceEVENT_GROUP_CREATE( xEventGroup ) -#endif - -#ifndef traceEVENT_GROUP_CREATE_FAILED - #define traceEVENT_GROUP_CREATE_FAILED() -#endif - -#ifndef traceEVENT_GROUP_SYNC_BLOCK - #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) -#endif - -#ifndef traceEVENT_GROUP_SYNC_END - #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred -#endif - -#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK - #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) -#endif - -#ifndef traceEVENT_GROUP_WAIT_BITS_END - #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred -#endif - -#ifndef traceEVENT_GROUP_CLEAR_BITS - #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) -#endif - -#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR - #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) -#endif - -#ifndef traceEVENT_GROUP_SET_BITS - #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) -#endif - -#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR - #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) -#endif - -#ifndef traceEVENT_GROUP_DELETE - #define traceEVENT_GROUP_DELETE( xEventGroup ) -#endif - -#ifndef tracePEND_FUNC_CALL - #define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret) -#endif - -#ifndef tracePEND_FUNC_CALL_FROM_ISR - #define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret) -#endif - -#ifndef traceQUEUE_REGISTRY_ADD - #define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName) -#endif - -#ifndef traceTASK_NOTIFY_TAKE_BLOCK - #define traceTASK_NOTIFY_TAKE_BLOCK() -#endif - -#ifndef traceTASK_NOTIFY_TAKE - #define traceTASK_NOTIFY_TAKE() -#endif - -#ifndef traceTASK_NOTIFY_WAIT_BLOCK - #define traceTASK_NOTIFY_WAIT_BLOCK() -#endif - -#ifndef traceTASK_NOTIFY_WAIT - #define traceTASK_NOTIFY_WAIT() -#endif - -#ifndef traceTASK_NOTIFY - #define traceTASK_NOTIFY() -#endif - -#ifndef traceTASK_NOTIFY_FROM_ISR - #define traceTASK_NOTIFY_FROM_ISR() -#endif - -#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR - #define traceTASK_NOTIFY_GIVE_FROM_ISR() -#endif - -#ifndef traceISR_EXIT_TO_SCHEDULER - #define traceISR_EXIT_TO_SCHEDULER() -#endif - -#ifndef traceISR_EXIT - #define traceISR_EXIT() -#endif - -#ifndef traceISR_ENTER - #define traceISR_ENTER() -#endif - -#ifndef traceSTREAM_BUFFER_CREATE_FAILED - #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED - #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_CREATE - #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_DELETE - #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_RESET - #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) -#endif - -#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND - #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_SEND - #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) -#endif - -#ifndef traceSTREAM_BUFFER_SEND_FAILED - #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR - #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) -#endif - -#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE - #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_RECEIVE - #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) -#endif - -#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED - #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR - #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) -#endif - -#ifndef configGENERATE_RUN_TIME_STATS - #define configGENERATE_RUN_TIME_STATS 0 -#endif - -#if ( configGENERATE_RUN_TIME_STATS == 1 ) - - #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS - #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. - #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ - - #ifndef portGET_RUN_TIME_COUNTER_VALUE - #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE - #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. - #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ - #endif /* portGET_RUN_TIME_COUNTER_VALUE */ - -#endif /* configGENERATE_RUN_TIME_STATS */ - -#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS - #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() -#endif - -#ifndef configUSE_MALLOC_FAILED_HOOK - #define configUSE_MALLOC_FAILED_HOOK 0 -#endif - -#ifndef portPRIVILEGE_BIT - #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) -#endif - -#ifndef portYIELD_WITHIN_API - #define portYIELD_WITHIN_API portYIELD -#endif - -#ifndef portSUPPRESS_TICKS_AND_SLEEP - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) -#endif - -#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP - #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 -#endif - -#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 - #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 -#endif - -#ifndef configUSE_TICKLESS_IDLE - #define configUSE_TICKLESS_IDLE 0 -#endif - -#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING - #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) -#endif - -#ifndef configPRE_SLEEP_PROCESSING - #define configPRE_SLEEP_PROCESSING( x ) -#endif - -#ifndef configPOST_SLEEP_PROCESSING - #define configPOST_SLEEP_PROCESSING( x ) -#endif - -#ifndef configUSE_QUEUE_SETS - #define configUSE_QUEUE_SETS 0 -#endif - -#ifndef portTASK_USES_FLOATING_POINT - #define portTASK_USES_FLOATING_POINT() -#endif - -#ifndef portALLOCATE_SECURE_CONTEXT - #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) -#endif - -#ifndef portDONT_DISCARD - #define portDONT_DISCARD -#endif - -#ifndef configUSE_TIME_SLICING - #define configUSE_TIME_SLICING 1 -#endif - -#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS - #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 -#endif - -#ifndef configUSE_STATS_FORMATTING_FUNCTIONS - #define configUSE_STATS_FORMATTING_FUNCTIONS 0 -#endif - -#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() -#endif - -#ifndef configUSE_TRACE_FACILITY - #define configUSE_TRACE_FACILITY 0 -#endif - -#ifndef mtCOVERAGE_TEST_MARKER - #define mtCOVERAGE_TEST_MARKER() -#endif - -#ifndef mtCOVERAGE_TEST_DELAY - #define mtCOVERAGE_TEST_DELAY() -#endif - -#ifndef portASSERT_IF_IN_ISR - #define portASSERT_IF_IN_ISR() -#endif - -#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#endif - -#ifndef configAPPLICATION_ALLOCATED_HEAP - #define configAPPLICATION_ALLOCATED_HEAP 0 -#endif - -#ifndef configUSE_TASK_NOTIFICATIONS - #define configUSE_TASK_NOTIFICATIONS 1 -#endif - -#ifndef configUSE_POSIX_ERRNO - #define configUSE_POSIX_ERRNO 0 -#endif - -#ifndef portTICK_TYPE_IS_ATOMIC - #define portTICK_TYPE_IS_ATOMIC 0 -#endif - -#ifndef configSUPPORT_STATIC_ALLOCATION - /* Defaults to 0 for backward compatibility. */ - #define configSUPPORT_STATIC_ALLOCATION 0 -#endif - -#ifndef configSUPPORT_DYNAMIC_ALLOCATION - /* Defaults to 1 for backward compatibility. */ - #define configSUPPORT_DYNAMIC_ALLOCATION 1 -#endif - -#ifndef configSTACK_DEPTH_TYPE - /* Defaults to uint16_t for backward compatibility, but can be overridden - in FreeRTOSConfig.h if uint16_t is too restrictive. */ - #define configSTACK_DEPTH_TYPE uint16_t -#endif - -#ifndef configMESSAGE_BUFFER_LENGTH_TYPE - /* Defaults to size_t for backward compatibility, but can be overridden - in FreeRTOSConfig.h if lengths will always be less than the number of bytes - in a size_t. */ - #define configMESSAGE_BUFFER_LENGTH_TYPE size_t -#endif - -/* Sanity check the configuration. */ -#if( configUSE_TICKLESS_IDLE != 0 ) - #if( INCLUDE_vTaskSuspend != 1 ) - #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0 - #endif /* INCLUDE_vTaskSuspend */ -#endif /* configUSE_TICKLESS_IDLE */ - -#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) - #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. -#endif - -#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) - #error configUSE_MUTEXES must be set to 1 to use recursive mutexes -#endif - -#ifndef configINITIAL_TICK_COUNT - #define configINITIAL_TICK_COUNT 0 -#endif - -#if( portTICK_TYPE_IS_ATOMIC == 0 ) - /* Either variables of tick type cannot be read atomically, or - portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when - the tick count is returned to the standard critical section macros. */ - #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() - #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() - #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() - #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) -#else - /* The tick type can be read atomically, so critical sections used when the - tick count is returned can be defined away. */ - #define portTICK_TYPE_ENTER_CRITICAL() - #define portTICK_TYPE_EXIT_CRITICAL() - #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 - #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x -#endif - -/* Definitions to allow backward compatibility with FreeRTOS versions prior to -V8 if desired. */ -#ifndef configENABLE_BACKWARD_COMPATIBILITY - #define configENABLE_BACKWARD_COMPATIBILITY 1 -#endif - -#ifndef configPRINTF - /* configPRINTF() was not defined, so define it away to nothing. To use - configPRINTF() then define it as follows (where MyPrintFunction() is - provided by the application writer): - - void MyPrintFunction(const char *pcFormat, ... ); - #define configPRINTF( X ) MyPrintFunction X - - Then call like a standard printf() function, but placing brackets around - all parameters so they are passed as a single parameter. For example: - configPRINTF( ("Value = %d", MyVariable) ); */ - #define configPRINTF( X ) -#endif - -#ifndef configMAX - /* The application writer has not provided their own MAX macro, so define - the following generic implementation. */ - #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) -#endif - -#ifndef configMIN - /* The application writer has not provided their own MAX macro, so define - the following generic implementation. */ - #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) -#endif - -#if configENABLE_BACKWARD_COMPATIBILITY == 1 - #define eTaskStateGet eTaskGetState - #define portTickType TickType_t - #define xTaskHandle TaskHandle_t - #define xQueueHandle QueueHandle_t - #define xSemaphoreHandle SemaphoreHandle_t - #define xQueueSetHandle QueueSetHandle_t - #define xQueueSetMemberHandle QueueSetMemberHandle_t - #define xTimeOutType TimeOut_t - #define xMemoryRegion MemoryRegion_t - #define xTaskParameters TaskParameters_t - #define xTaskStatusType TaskStatus_t - #define xTimerHandle TimerHandle_t - #define xCoRoutineHandle CoRoutineHandle_t - #define pdTASK_HOOK_CODE TaskHookFunction_t - #define portTICK_RATE_MS portTICK_PERIOD_MS - #define pcTaskGetTaskName pcTaskGetName - #define pcTimerGetTimerName pcTimerGetName - #define pcQueueGetQueueName pcQueueGetName - #define vTaskGetTaskInfo vTaskGetInfo - - /* Backward compatibility within the scheduler code only - these definitions - are not really required but are included for completeness. */ - #define tmrTIMER_CALLBACK TimerCallbackFunction_t - #define pdTASK_CODE TaskFunction_t - #define xListItem ListItem_t - #define xList List_t - - /* For libraries that break the list data hiding, and access list structure - members directly (which is not supposed to be done). */ - #define pxContainer pvContainer -#endif /* configENABLE_BACKWARD_COMPATIBILITY */ - -#if( configUSE_ALTERNATIVE_API != 0 ) - #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 -#endif - -/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even -if floating point hardware is otherwise supported by the FreeRTOS port in use. -This constant is not supported by all FreeRTOS ports that include floating -point support. */ -#ifndef configUSE_TASK_FPU_SUPPORT - #define configUSE_TASK_FPU_SUPPORT 1 -#endif - -/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is -currently used in ARMv8M ports. */ -#ifndef configENABLE_MPU - #define configENABLE_MPU 0 -#endif - -/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is -currently used in ARMv8M ports. */ -#ifndef configENABLE_FPU - #define configENABLE_FPU 1 -#endif - -/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. -This is currently used in ARMv8M ports. */ -#ifndef configENABLE_TRUSTZONE - #define configENABLE_TRUSTZONE 1 -#endif - -/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on -the Secure Side only. */ -#ifndef configRUN_FREERTOS_SECURE_ONLY - #define configRUN_FREERTOS_SECURE_ONLY 0 -#endif - -/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using - * dynamically allocated RAM, in which case when any task is deleted it is known - * that both the task's stack and TCB need to be freed. Sometimes the - * FreeRTOSConfig.h settings only allow a task to be created using statically - * allocated RAM, in which case when any task is deleted it is known that neither - * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h - * settings allow a task to be created using either statically or dynamically - * allocated RAM, in which case a member of the TCB is used to record whether the - * stack and/or TCB were allocated statically or dynamically, so when a task is - * deleted the RAM that was allocated dynamically is freed again and no attempt is - * made to free the RAM that was allocated statically. - * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a - * task to be created using either statically or dynamically allocated RAM. Note - * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with - * a statically allocated stack and a dynamically allocated TCB. - * - * The following table lists various combinations of portUSING_MPU_WRAPPERS, - * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and - * when it is possible to have both static and dynamic allocation: - * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ - * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | - * | | | | | | Static Possible | | - * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ - * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | - * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| - * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | - * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| - * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | - * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | - * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| - * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | - * | | | | xTaskCreateRestrictedStatic | | | | - * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| - * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | - * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | - * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| - * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | - * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | - * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | - * | | | | xTaskCreateRestrictedStatic | | | | - * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ - */ -#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ - ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) - -/* - * In line with software engineering best practice, FreeRTOS implements a strict - * data hiding policy, so the real structures used by FreeRTOS to maintain the - * state of tasks, queues, semaphores, etc. are not accessible to the application - * code. However, if the application writer wants to statically allocate such - * an object then the size of the object needs to be know. Dummy structures - * that are guaranteed to have the same size and alignment requirements of the - * real objects are used for this purpose. The dummy list and list item - * structures below are used for inclusion in such a dummy structure. - */ -struct xSTATIC_LIST_ITEM -{ - #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) - TickType_t xDummy1; - #endif - TickType_t xDummy2; - void *pvDummy3[ 4 ]; - #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) - TickType_t xDummy4; - #endif -}; -typedef struct xSTATIC_LIST_ITEM StaticListItem_t; - -/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ -struct xSTATIC_MINI_LIST_ITEM -{ - #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) - TickType_t xDummy1; - #endif - TickType_t xDummy2; - void *pvDummy3[ 2 ]; -}; -typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; - -/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ -typedef struct xSTATIC_LIST -{ - #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) - TickType_t xDummy1; - #endif - UBaseType_t uxDummy2; - void *pvDummy3; - StaticMiniListItem_t xDummy4; - #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) - TickType_t xDummy5; - #endif -} StaticList_t; - -/* - * In line with software engineering best practice, especially when supplying a - * library that is likely to change in future versions, FreeRTOS implements a - * strict data hiding policy. This means the Task structure used internally by - * FreeRTOS is not accessible to application code. However, if the application - * writer wants to statically allocate the memory required to create a task then - * the size of the task object needs to be know. The StaticTask_t structure - * below is provided for this purpose. Its sizes and alignment requirements are - * guaranteed to match those of the genuine structure, no matter which - * architecture is being used, and no matter how the values in FreeRTOSConfig.h - * are set. Its contents are somewhat obfuscated in the hope users will - * recognise that it would be unwise to make direct use of the structure members. - */ -typedef struct xSTATIC_TCB -{ - void *pxDummy1; - #if ( portUSING_MPU_WRAPPERS == 1 ) - xMPU_SETTINGS xDummy2; - #endif - StaticListItem_t xDummy3[ 2 ]; - UBaseType_t uxDummy5; - void *pxDummy6; - uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; - #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) - void *pxDummy8; - #endif - #if ( portCRITICAL_NESTING_IN_TCB == 1 ) - UBaseType_t uxDummy9; - #endif - #if ( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxDummy10[ 2 ]; - #endif - #if ( configUSE_MUTEXES == 1 ) - UBaseType_t uxDummy12[ 2 ]; - #endif - #if ( configUSE_APPLICATION_TASK_TAG == 1 ) - void *pxDummy14; - #endif - #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) - void *pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; - #endif - #if ( configGENERATE_RUN_TIME_STATS == 1 ) - uint32_t ulDummy16; - #endif - #if ( configUSE_NEWLIB_REENTRANT == 1 ) - struct _reent xDummy17; - #endif - #if ( configUSE_TASK_NOTIFICATIONS == 1 ) - uint32_t ulDummy18; - uint8_t ucDummy19; - #endif - #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) - uint8_t uxDummy20; - #endif - - #if( INCLUDE_xTaskAbortDelay == 1 ) - uint8_t ucDummy21; - #endif - #if ( configUSE_POSIX_ERRNO == 1 ) - int iDummy22; - #endif -} StaticTask_t; - -/* - * In line with software engineering best practice, especially when supplying a - * library that is likely to change in future versions, FreeRTOS implements a - * strict data hiding policy. This means the Queue structure used internally by - * FreeRTOS is not accessible to application code. However, if the application - * writer wants to statically allocate the memory required to create a queue - * then the size of the queue object needs to be know. The StaticQueue_t - * structure below is provided for this purpose. Its sizes and alignment - * requirements are guaranteed to match those of the genuine structure, no - * matter which architecture is being used, and no matter how the values in - * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope - * users will recognise that it would be unwise to make direct use of the - * structure members. - */ -typedef struct xSTATIC_QUEUE -{ - void *pvDummy1[ 3 ]; - - union - { - void *pvDummy2; - UBaseType_t uxDummy2; - } u; - - StaticList_t xDummy3[ 2 ]; - UBaseType_t uxDummy4[ 3 ]; - uint8_t ucDummy5[ 2 ]; - - #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) - uint8_t ucDummy6; - #endif - - #if ( configUSE_QUEUE_SETS == 1 ) - void *pvDummy7; - #endif - - #if ( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxDummy8; - uint8_t ucDummy9; - #endif - -} StaticQueue_t; -typedef StaticQueue_t StaticSemaphore_t; - -/* - * In line with software engineering best practice, especially when supplying a - * library that is likely to change in future versions, FreeRTOS implements a - * strict data hiding policy. This means the event group structure used - * internally by FreeRTOS is not accessible to application code. However, if - * the application writer wants to statically allocate the memory required to - * create an event group then the size of the event group object needs to be - * know. The StaticEventGroup_t structure below is provided for this purpose. - * Its sizes and alignment requirements are guaranteed to match those of the - * genuine structure, no matter which architecture is being used, and no matter - * how the values in FreeRTOSConfig.h are set. Its contents are somewhat - * obfuscated in the hope users will recognise that it would be unwise to make - * direct use of the structure members. - */ -typedef struct xSTATIC_EVENT_GROUP -{ - TickType_t xDummy1; - StaticList_t xDummy2; - - #if( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxDummy3; - #endif - - #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) - uint8_t ucDummy4; - #endif - -} StaticEventGroup_t; - -/* - * In line with software engineering best practice, especially when supplying a - * library that is likely to change in future versions, FreeRTOS implements a - * strict data hiding policy. This means the software timer structure used - * internally by FreeRTOS is not accessible to application code. However, if - * the application writer wants to statically allocate the memory required to - * create a software timer then the size of the queue object needs to be know. - * The StaticTimer_t structure below is provided for this purpose. Its sizes - * and alignment requirements are guaranteed to match those of the genuine - * structure, no matter which architecture is being used, and no matter how the - * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in - * the hope users will recognise that it would be unwise to make direct use of - * the structure members. - */ -typedef struct xSTATIC_TIMER -{ - void *pvDummy1; - StaticListItem_t xDummy2; - TickType_t xDummy3; - void *pvDummy5; - TaskFunction_t pvDummy6; - #if( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxDummy7; - #endif - uint8_t ucDummy8; - -} StaticTimer_t; - -/* -* In line with software engineering best practice, especially when supplying a -* library that is likely to change in future versions, FreeRTOS implements a -* strict data hiding policy. This means the stream buffer structure used -* internally by FreeRTOS is not accessible to application code. However, if -* the application writer wants to statically allocate the memory required to -* create a stream buffer then the size of the stream buffer object needs to be -* know. The StaticStreamBuffer_t structure below is provided for this purpose. -* Its size and alignment requirements are guaranteed to match those of the -* genuine structure, no matter which architecture is being used, and no matter -* how the values in FreeRTOSConfig.h are set. Its contents are somewhat -* obfuscated in the hope users will recognise that it would be unwise to make -* direct use of the structure members. -*/ -typedef struct xSTATIC_STREAM_BUFFER -{ - size_t uxDummy1[ 4 ]; - void * pvDummy2[ 3 ]; - uint8_t ucDummy3; - #if ( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxDummy4; - #endif -} StaticStreamBuffer_t; - -/* Message buffers are built on stream buffers. */ -typedef StaticStreamBuffer_t StaticMessageBuffer_t; - -#ifdef __cplusplus -} -#endif - -#endif /* INC_FREERTOS_H */ - diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/atomic.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/atomic.h deleted file mode 100644 index ada77a4..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/atomic.h +++ /dev/null @@ -1,547 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/** - * @file atomic.h - * @brief FreeRTOS atomic operation support. - * - * Two implementations of atomic are given in this header file: - * 1. Disabling interrupt globally. - * 2. ISA native atomic support. - * The former is available to all ports (compiler-architecture combination), - * while the latter is only available to ports compiling with GCC (version at - * least 4.7.0), which also have ISA atomic support. - * - * User can select which implementation to use by: - * setting/clearing configUSE_ATOMIC_INSTRUCTION in FreeRTOSConfig.h. - * Define AND set configUSE_ATOMIC_INSTRUCTION to 1 for ISA native atomic support. - * Undefine OR clear configUSE_ATOMIC_INSTRUCTION for disabling global interrupt - * implementation. - * - * @see GCC Built-in Functions for Memory Model Aware Atomic Operations - * https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html - */ - -#ifndef ATOMIC_H -#define ATOMIC_H - -#ifndef INC_FREERTOS_H - #error "include FreeRTOS.h must appear in source files before include atomic.h" -#endif - -/* Standard includes. */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - /* Needed for __atomic_compare_exchange() weak=false. */ - #include - - /* This branch is for GCC compiler and GCC compiler only. */ - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__((always_inline)) - #endif - -#else - - /* Port specific definitions -- entering/exiting critical section. - * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h - * - * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with - * ATOMIC_ENTER_CRITICAL(). - */ - #if defined( portSET_INTERRUPT_MASK_FROM_ISR ) - - /* Nested interrupt scheme is supported in this port. */ - #define ATOMIC_ENTER_CRITICAL() \ - UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR() - - #define ATOMIC_EXIT_CRITICAL() \ - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType ) - - #else - - /* Nested interrupt scheme is NOT supported in this port. */ - #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL() - #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL() - - #endif /* portSET_INTERRUPT_MASK_FROM_ISR() */ - - /* Port specific definition -- "always inline". - * Inline is compiler specific, and may not always get inlined depending on your optimization level. - * Also, inline is considerred as performance optimization for atomic. - * Thus, if portFORCE_INLINE is not provided by portmacro.h, instead of resulting error, - * simply define it. - */ - #ifndef portFORCE_INLINE - #define portFORCE_INLINE - #endif - -#endif /* configUSE_GCC_BUILTIN_ATOMICS */ - -#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */ -#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */ - -/*----------------------------- Swap && CAS ------------------------------*/ - -/** - * Atomic compare-and-swap - * - * @brief Performs an atomic compare-and-swap operation on the specified values. - * - * @param[in, out] pDestination Pointer to memory location from where value is - * to be loaded and checked. - * @param[in] ulExchange If condition meets, write this value to memory. - * @param[in] ulComparand Swap condition. - * - * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. - * - * @note This function only swaps *pDestination with ulExchange, if previous - * *pDestination value equals ulComparand. - */ -static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( - uint32_t volatile * pDestination, - uint32_t ulExchange, - uint32_t ulComparand ) -{ - - uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; - -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - if ( __atomic_compare_exchange( pDestination, - &ulComparand, - &ulExchange, - false, - __ATOMIC_SEQ_CST, - __ATOMIC_SEQ_CST ) ) - { - ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; - } - -#else - - ATOMIC_ENTER_CRITICAL(); - - if ( *pDestination == ulComparand ) - { - *pDestination = ulExchange; - ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; - } - - ATOMIC_EXIT_CRITICAL(); - -#endif - - return ulReturnValue; - -} - -/** - * Atomic swap (pointers) - * - * @brief Atomically sets the address pointed to by *ppDestination to the value - * of *pExchange. - * - * @param[in, out] ppDestination Pointer to memory location from where a pointer - * value is to be loaded and written back to. - * @param[in] pExchange Pointer value to be written to *ppDestination. - * - * @return The initial value of *ppDestination. - */ -static portFORCE_INLINE void * Atomic_SwapPointers_p32( - void * volatile * ppDestination, - void * pExchange ) -{ - void * pReturnValue; - -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - __atomic_exchange( ppDestination, &pExchange, &pReturnValue, __ATOMIC_SEQ_CST ); - -#else - - ATOMIC_ENTER_CRITICAL(); - - pReturnValue = *ppDestination; - - *ppDestination = pExchange; - - ATOMIC_EXIT_CRITICAL(); - -#endif - - return pReturnValue; -} - -/** - * Atomic compare-and-swap (pointers) - * - * @brief Performs an atomic compare-and-swap operation on the specified pointer - * values. - * - * @param[in, out] ppDestination Pointer to memory location from where a pointer - * value is to be loaded and checked. - * @param[in] pExchange If condition meets, write this value to memory. - * @param[in] pComparand Swap condition. - * - * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. - * - * @note This function only swaps *ppDestination with pExchange, if previous - * *ppDestination value equals pComparand. - */ -static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( - void * volatile * ppDestination, - void * pExchange, void * pComparand ) -{ - uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; - -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - if ( __atomic_compare_exchange( ppDestination, - &pComparand, - &pExchange, - false, - __ATOMIC_SEQ_CST, - __ATOMIC_SEQ_CST ) ) - { - ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; - } - -#else - - ATOMIC_ENTER_CRITICAL(); - - if ( *ppDestination == pComparand ) - { - *ppDestination = pExchange; - ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; - } - - ATOMIC_EXIT_CRITICAL(); - -#endif - - return ulReturnValue; -} - - -/*----------------------------- Arithmetic ------------------------------*/ - -/** - * Atomic add - * - * @brief Atomically adds count to the value of the specified pointer points to. - * - * @param[in,out] pAddend Pointer to memory location from where value is to be - * loaded and written back to. - * @param[in] ulCount Value to be added to *pAddend. - * - * @return previous *pAddend value. - */ -static portFORCE_INLINE uint32_t Atomic_Add_u32( - uint32_t volatile * pAddend, - uint32_t ulCount ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_add(pAddend, ulCount, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pAddend; - - *pAddend += ulCount; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/** - * Atomic subtract - * - * @brief Atomically subtracts count from the value of the specified pointer - * pointers to. - * - * @param[in,out] pAddend Pointer to memory location from where value is to be - * loaded and written back to. - * @param[in] ulCount Value to be subtract from *pAddend. - * - * @return previous *pAddend value. - */ -static portFORCE_INLINE uint32_t Atomic_Subtract_u32( - uint32_t volatile * pAddend, - uint32_t ulCount ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_sub(pAddend, ulCount, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pAddend; - - *pAddend -= ulCount; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/** - * Atomic increment - * - * @brief Atomically increments the value of the specified pointer points to. - * - * @param[in,out] pAddend Pointer to memory location from where value is to be - * loaded and written back to. - * - * @return *pAddend value before increment. - */ -static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pAddend ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_add(pAddend, 1, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pAddend; - - *pAddend += 1; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/** - * Atomic decrement - * - * @brief Atomically decrements the value of the specified pointer points to - * - * @param[in,out] pAddend Pointer to memory location from where value is to be - * loaded and written back to. - * - * @return *pAddend value before decrement. - */ -static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pAddend ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_sub(pAddend, 1, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pAddend; - - *pAddend -= 1; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/*----------------------------- Bitwise Logical ------------------------------*/ - -/** - * Atomic OR - * - * @brief Performs an atomic OR operation on the specified values. - * - * @param [in, out] pDestination Pointer to memory location from where value is - * to be loaded and written back to. - * @param [in] ulValue Value to be ORed with *pDestination. - * - * @return The original value of *pDestination. - */ -static portFORCE_INLINE uint32_t Atomic_OR_u32( - uint32_t volatile * pDestination, - uint32_t ulValue ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_or(pDestination, ulValue, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pDestination; - - *pDestination |= ulValue; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/** - * Atomic AND - * - * @brief Performs an atomic AND operation on the specified values. - * - * @param [in, out] pDestination Pointer to memory location from where value is - * to be loaded and written back to. - * @param [in] ulValue Value to be ANDed with *pDestination. - * - * @return The original value of *pDestination. - */ -static portFORCE_INLINE uint32_t Atomic_AND_u32( - uint32_t volatile * pDestination, - uint32_t ulValue ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_and(pDestination, ulValue, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pDestination; - - *pDestination &= ulValue; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/** - * Atomic NAND - * - * @brief Performs an atomic NAND operation on the specified values. - * - * @param [in, out] pDestination Pointer to memory location from where value is - * to be loaded and written back to. - * @param [in] ulValue Value to be NANDed with *pDestination. - * - * @return The original value of *pDestination. - */ -static portFORCE_INLINE uint32_t Atomic_NAND_u32( - uint32_t volatile * pDestination, - uint32_t ulValue ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_nand(pDestination, ulValue, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pDestination; - - *pDestination = ~(ulCurrent & ulValue); - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/** - * Atomic XOR - * - * @brief Performs an atomic XOR operation on the specified values. - * - * @param [in, out] pDestination Pointer to memory location from where value is - * to be loaded and written back to. - * @param [in] ulValue Value to be XORed with *pDestination. - * - * @return The original value of *pDestination. - */ -static portFORCE_INLINE uint32_t Atomic_XOR_u32( - uint32_t volatile * pDestination, - uint32_t ulValue ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_xor(pDestination, ulValue, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pDestination; - - *pDestination ^= ulValue; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -#ifdef __cplusplus -} -#endif - -#endif /* ATOMIC_H */ diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/croutine.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/croutine.h deleted file mode 100644 index a77be94..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/croutine.h +++ /dev/null @@ -1,679 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef CO_ROUTINE_H -#define CO_ROUTINE_H - -#ifndef INC_FREERTOS_H - #error "include FreeRTOS.h must appear in source files before include croutine.h" -#endif - -#include "list.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Used to hide the implementation of the co-routine control block. The -control block structure however has to be included in the header due to -the macro implementation of the co-routine functionality. */ -typedef void * CoRoutineHandle_t; - -/* Defines the prototype to which co-routine functions must conform. */ -typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t ); - -typedef struct corCoRoutineControlBlock -{ - crCOROUTINE_CODE pxCoRoutineFunction; - ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ - ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */ - UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ - UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ - uint16_t uxState; /*< Used internally by the co-routine implementation. */ -} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */ - -/** - * croutine. h - *
- BaseType_t xCoRoutineCreate(
-                                 crCOROUTINE_CODE pxCoRoutineCode,
-                                 UBaseType_t uxPriority,
-                                 UBaseType_t uxIndex
-                               );
- * - * Create a new co-routine and add it to the list of co-routines that are - * ready to run. - * - * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine - * functions require special syntax - see the co-routine section of the WEB - * documentation for more information. - * - * @param uxPriority The priority with respect to other co-routines at which - * the co-routine will run. - * - * @param uxIndex Used to distinguish between different co-routines that - * execute the same function. See the example below and the co-routine section - * of the WEB documentation for further information. - * - * @return pdPASS if the co-routine was successfully created and added to a ready - * list, otherwise an error code defined with ProjDefs.h. - * - * Example usage: - 
- // Co-routine to be created.
- void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- static const char cLedToFlash[ 2 ] = { 5, 6 };
- static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-     for( ;; )
-     {
-         // This co-routine just delays for a fixed period, then toggles
-         // an LED.  Two co-routines are created using this function, so
-         // the uxIndex parameter is used to tell the co-routine which
-         // LED to flash and how int32_t to delay.  This assumes xQueue has
-         // already been created.
-         vParTestToggleLED( cLedToFlash[ uxIndex ] );
-         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
-     }
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- // Function that creates two co-routines.
- void vOtherFunction( void )
- {
- uint8_t ucParameterToPass;
- TaskHandle_t xHandle;
-     // Create two co-routines at priority 0.  The first is given index 0
-     // so (from the code above) toggles LED 5 every 200 ticks.  The second
-     // is given index 1 so toggles LED 6 every 400 ticks.
-     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
-     {
-         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
-     }
- }
-
- * \defgroup xCoRoutineCreate xCoRoutineCreate - * \ingroup Tasks - */ -BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ); - - -/** - * croutine. h - *
- void vCoRoutineSchedule( void );
- * - * Run a co-routine. - * - * vCoRoutineSchedule() executes the highest priority co-routine that is able - * to run. The co-routine will execute until it either blocks, yields or is - * preempted by a task. Co-routines execute cooperatively so one - * co-routine cannot be preempted by another, but can be preempted by a task. - * - * If an application comprises of both tasks and co-routines then - * vCoRoutineSchedule should be called from the idle task (in an idle task - * hook). - * - * Example usage: - 
- // This idle task hook will schedule a co-routine each time it is called.
- // The rest of the idle task will execute between co-routine calls.
- void vApplicationIdleHook( void )
- {
-    vCoRoutineSchedule();
- }
- // Alternatively, if you do not require any other part of the idle task to
- // execute, the idle task hook can call vCoRoutineScheduler() within an
- // infinite loop.
- void vApplicationIdleHook( void )
- {
-    for( ;; )
-    {
-        vCoRoutineSchedule();
-    }
- }
-
- * \defgroup vCoRoutineSchedule vCoRoutineSchedule - * \ingroup Tasks - */ -void vCoRoutineSchedule( void ); - -/** - * croutine. h - * 
- crSTART( CoRoutineHandle_t xHandle );
- * - * This macro MUST always be called at the start of a co-routine function. - * - * Example usage: - 
- // Co-routine to be created.
- void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static int32_t ulAVariable;
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0: - -/** - * croutine. h - * 
- crEND();
- * - * This macro MUST always be called at the end of a co-routine function. - * - * Example usage: - 
- // Co-routine to be created.
- void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static int32_t ulAVariable;
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crEND() } - -/* - * These macros are intended for internal use by the co-routine implementation - * only. The macros should not be used directly by application writers. - */ -#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): -#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): - -/** - * croutine. h - *
- crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
- * - * Delay a co-routine for a fixed period of time. - * - * crDELAY can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * @param xHandle The handle of the co-routine to delay. This is the xHandle - * parameter of the co-routine function. - * - * @param xTickToDelay The number of ticks that the co-routine should delay - * for. The actual amount of time this equates to is defined by - * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS - * can be used to convert ticks to milliseconds. - * - * Example usage: - 
- // Co-routine to be created.
- void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- // We are to delay for 200ms.
- static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-     for( ;; )
-     {
-        // Delay for 200ms.
-        crDELAY( xHandle, xDelayTime );
-        // Do something here.
-     }
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crDELAY crDELAY - * \ingroup Tasks - */ -#define crDELAY( xHandle, xTicksToDelay ) \ - if( ( xTicksToDelay ) > 0 ) \ - { \ - vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ - } \ - crSET_STATE0( ( xHandle ) ); - -/** - * 
- crQUEUE_SEND(
-                  CoRoutineHandle_t xHandle,
-                  QueueHandle_t pxQueue,
-                  void *pvItemToQueue,
-                  TickType_t xTicksToWait,
-                  BaseType_t *pxResult
-             )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_SEND can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue on which the data will be posted. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvItemToQueue A pointer to the data being posted onto the queue. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied from pvItemToQueue into the queue - * itself. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for space to become available on the queue, should space not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example - * below). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully posted onto the queue, otherwise it will be set to an - * error defined within ProjDefs.h. - * - * Example usage: - 
- // Co-routine function that blocks for a fixed period then posts a number onto
- // a queue.
- static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static BaseType_t xNumberToPost = 0;
- static BaseType_t xResult;
-    // Co-routines must begin with a call to crSTART().
-    crSTART( xHandle );
-    for( ;; )
-    {
-        // This assumes the queue has already been created.
-        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
-        if( xResult != pdPASS )
-        {
-            // The message was not posted!
-        }
-        // Increment the number to be posted onto the queue.
-        xNumberToPost++;
-        // Delay for 100 ticks.
-        crDELAY( xHandle, 100 );
-    }
-    // Co-routines must end with a call to crEND().
-    crEND();
- }
- * \defgroup crQUEUE_SEND crQUEUE_SEND - * \ingroup Tasks - */ -#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ -{ \ - *( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \ - if( *( pxResult ) == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( ( xHandle ) ); \ - *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( ( xHandle ) ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - * 
-  crQUEUE_RECEIVE(
-                     CoRoutineHandle_t xHandle,
-                     QueueHandle_t pxQueue,
-                     void *pvBuffer,
-                     TickType_t xTicksToWait,
-                     BaseType_t *pxResult
-                 )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_RECEIVE can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue from which the data will be received. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvBuffer The buffer into which the received item is to be copied. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied into pvBuffer. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for data to become available from the queue, should data not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the - * crQUEUE_SEND example). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully retrieved from the queue, otherwise it will be set to - * an error code as defined within ProjDefs.h. - * - * Example usage: - 
- // A co-routine receives the number of an LED to flash from a queue.  It
- // blocks on the queue until the number is received.
- static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static BaseType_t xResult;
- static UBaseType_t uxLEDToFlash;
-    // All co-routines must start with a call to crSTART().
-    crSTART( xHandle );
-    for( ;; )
-    {
-        // Wait for data to become available on the queue.
-        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-        if( xResult == pdPASS )
-        {
-            // We received the LED to flash - flash it!
-            vParTestToggleLED( uxLEDToFlash );
-        }
-    }
-    crEND();
- }
- * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ -{ \ - *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \ - if( *( pxResult ) == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( ( xHandle ) ); \ - *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \ - } \ - if( *( pxResult ) == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( ( xHandle ) ); \ - *( pxResult ) = pdPASS; \ - } \ -} - -/** - * croutine. h - * 
-  crQUEUE_SEND_FROM_ISR(
-                            QueueHandle_t pxQueue,
-                            void *pvItemToQueue,
-                            BaseType_t xCoRoutinePreviouslyWoken
-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue - * that is being used from within a co-routine. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. - * - * @return pdTRUE if a co-routine was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: - 
- // A co-routine that blocks on a queue waiting for characters to be received.
- static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- char cRxedChar;
- BaseType_t xResult;
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-     for( ;; )
-     {
-         // Wait for data to become available on the queue.  This assumes the
-         // queue xCommsRxQueue has already been created!
-         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-         // Was a character received?
-         if( xResult == pdPASS )
-         {
-             // Process the character here.
-         }
-     }
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
- // An ISR that uses a queue to send characters received on a serial port to
- // a co-routine.
- void vUART_ISR( void )
- {
- char cRxedChar;
- BaseType_t xCRWokenByPost = pdFALSE;
-     // We loop around reading characters until there are none left in the UART.
-     while( UART_RX_REG_NOT_EMPTY() )
-     {
-         // Obtain the character from the UART.
-         cRxedChar = UART_RX_REG;
-         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
-         // the first time around the loop.  If the post causes a co-routine
-         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
-         // In this manner we can ensure that if more than one co-routine is
-         // blocked on the queue only one is woken by this ISR no matter how
-         // many characters are posted to the queue.
-         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
-     }
- }
- * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) - - -/** - * croutine. h - * 
-  crQUEUE_SEND_FROM_ISR(
-                            QueueHandle_t pxQueue,
-                            void *pvBuffer,
-                            BaseType_t * pxCoRoutineWoken
-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data - * from a queue that is being used from within a co-routine (a co-routine - * posted to the queue). - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvBuffer A pointer to a buffer into which the received item will be - * placed. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from the queue into - * pvBuffer. - * - * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become - * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a - * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise - * *pxCoRoutineWoken will remain unchanged. - * - * @return pdTRUE an item was successfully received from the queue, otherwise - * pdFALSE. - * - * Example usage: - 
- // A co-routine that posts a character to a queue then blocks for a fixed
- // period.  The character is incremented each time.
- static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // cChar holds its value while this co-routine is blocked and must therefore
- // be declared static.
- static char cCharToTx = 'a';
- BaseType_t xResult;
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-     for( ;; )
-     {
-         // Send the next character to the queue.
-         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
-         if( xResult == pdPASS )
-         {
-             // The character was successfully posted to the queue.
-         }
-         else
-         {
-            // Could not post the character to the queue.
-         }
-         // Enable the UART Tx interrupt to cause an interrupt in this
-         // hypothetical UART.  The interrupt will obtain the character
-         // from the queue and send it.
-         ENABLE_RX_INTERRUPT();
-         // Increment to the next character then block for a fixed period.
-         // cCharToTx will maintain its value across the delay as it is
-         // declared static.
-         cCharToTx++;
-         if( cCharToTx > 'x' )
-         {
-            cCharToTx = 'a';
-         }
-         crDELAY( 100 );
-     }
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
- // An ISR that uses a queue to receive characters to send on a UART.
- void vUART_ISR( void )
- {
- char cCharToTx;
- BaseType_t xCRWokenByPost = pdFALSE;
-     while( UART_TX_REG_EMPTY() )
-     {
-         // Are there any characters in the queue waiting to be sent?
-         // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
-         // is woken by the post - ensuring that only a single co-routine is
-         // woken no matter how many times we go around this loop.
-         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
-         {
-             SEND_CHARACTER( cCharToTx );
-         }
-     }
- }
- * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) - -/* - * This function is intended for internal use by the co-routine macros only. - * The macro nature of the co-routine implementation requires that the - * prototype appears here. The function should not be used by application - * writers. - * - * Removes the current co-routine from its ready list and places it in the - * appropriate delayed list. - */ -void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ); - -/* - * This function is intended for internal use by the queue implementation only. - * The function should not be used by application writers. - * - * Removes the highest priority co-routine from the event list and places it in - * the pending ready list. - */ -BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ); - -#ifdef __cplusplus -} -#endif - -#endif /* CO_ROUTINE_H */ \ No newline at end of file diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/deprecated_definitions.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/deprecated_definitions.h deleted file mode 100644 index 4d0ce01..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/deprecated_definitions.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef DEPRECATED_DEFINITIONS_H -#define DEPRECATED_DEFINITIONS_H - - -/* Each FreeRTOS port has a unique portmacro.h header file. Originally a -pre-processor definition was used to ensure the pre-processor found the correct -portmacro.h file for the port being used. That scheme was deprecated in favour -of setting the compiler's include path such that it found the correct -portmacro.h file - removing the need for the constant and allowing the -portmacro.h file to be located anywhere in relation to the port being used. The -definitions below remain in the code for backward compatibility only. New -projects should not use them. */ - -#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT - #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT - #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef GCC_MEGA_AVR - #include "../portable/GCC/ATMega323/portmacro.h" -#endif - -#ifdef IAR_MEGA_AVR - #include "../portable/IAR/ATMega323/portmacro.h" -#endif - -#ifdef MPLAB_PIC24_PORT - #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" -#endif - -#ifdef MPLAB_DSPIC_PORT - #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" -#endif - -#ifdef MPLAB_PIC18F_PORT - #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" -#endif - -#ifdef MPLAB_PIC32MX_PORT - #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" -#endif - -#ifdef _FEDPICC - #include "libFreeRTOS/Include/portmacro.h" -#endif - -#ifdef SDCC_CYGNAL - #include "../../Source/portable/SDCC/Cygnal/portmacro.h" -#endif - -#ifdef GCC_ARM7 - #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" -#endif - -#ifdef GCC_ARM7_ECLIPSE - #include "portmacro.h" -#endif - -#ifdef ROWLEY_LPC23xx - #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" -#endif - -#ifdef IAR_MSP430 - #include "..\..\Source\portable\IAR\MSP430\portmacro.h" -#endif - -#ifdef GCC_MSP430 - #include "../../Source/portable/GCC/MSP430F449/portmacro.h" -#endif - -#ifdef ROWLEY_MSP430 - #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" -#endif - -#ifdef ARM7_LPC21xx_KEIL_RVDS - #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" -#endif - -#ifdef SAM7_GCC - #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" -#endif - -#ifdef SAM7_IAR - #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" -#endif - -#ifdef SAM9XE_IAR - #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" -#endif - -#ifdef LPC2000_IAR - #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" -#endif - -#ifdef STR71X_IAR - #include "..\..\Source\portable\IAR\STR71x\portmacro.h" -#endif - -#ifdef STR75X_IAR - #include "..\..\Source\portable\IAR\STR75x\portmacro.h" -#endif - -#ifdef STR75X_GCC - #include "..\..\Source\portable\GCC\STR75x\portmacro.h" -#endif - -#ifdef STR91X_IAR - #include "..\..\Source\portable\IAR\STR91x\portmacro.h" -#endif - -#ifdef GCC_H8S - #include "../../Source/portable/GCC/H8S2329/portmacro.h" -#endif - -#ifdef GCC_AT91FR40008 - #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" -#endif - -#ifdef RVDS_ARMCM3_LM3S102 - #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" -#endif - -#ifdef GCC_ARMCM3_LM3S102 - #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" -#endif - -#ifdef GCC_ARMCM3 - #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" -#endif - -#ifdef IAR_ARM_CM3 - #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" -#endif - -#ifdef IAR_ARMCM3_LM - #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" -#endif - -#ifdef HCS12_CODE_WARRIOR - #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" -#endif - -#ifdef MICROBLAZE_GCC - #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" -#endif - -#ifdef TERN_EE - #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" -#endif - -#ifdef GCC_HCS12 - #include "../../Source/portable/GCC/HCS12/portmacro.h" -#endif - -#ifdef GCC_MCF5235 - #include "../../Source/portable/GCC/MCF5235/portmacro.h" -#endif - -#ifdef COLDFIRE_V2_GCC - #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" -#endif - -#ifdef COLDFIRE_V2_CODEWARRIOR - #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" -#endif - -#ifdef GCC_PPC405 - #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" -#endif - -#ifdef GCC_PPC440 - #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" -#endif - -#ifdef _16FX_SOFTUNE - #include "..\..\Source\portable\Softune\MB96340\portmacro.h" -#endif - -#ifdef BCC_INDUSTRIAL_PC_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef BCC_FLASH_LITE_186_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef __GNUC__ - #ifdef __AVR32_AVR32A__ - #include "portmacro.h" - #endif -#endif - -#ifdef __ICCAVR32__ - #ifdef __CORE__ - #if __CORE__ == __AVR32A__ - #include "portmacro.h" - #endif - #endif -#endif - -#ifdef __91467D - #include "portmacro.h" -#endif - -#ifdef __96340 - #include "portmacro.h" -#endif - - -#ifdef __IAR_V850ES_Fx3__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_V850ES_Jx3__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_V850ES_Jx3_L__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_V850ES_Jx2__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_V850ES_Hx2__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_78K0R_Kx3__ - #include "../../Source/portable/IAR/78K0R/portmacro.h" -#endif - -#ifdef __IAR_78K0R_Kx3L__ - #include "../../Source/portable/IAR/78K0R/portmacro.h" -#endif - -#endif /* DEPRECATED_DEFINITIONS_H */ - diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/event_groups.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/event_groups.h deleted file mode 100644 index 522b0b6..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/event_groups.h +++ /dev/null @@ -1,757 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef EVENT_GROUPS_H -#define EVENT_GROUPS_H - -#ifndef INC_FREERTOS_H - #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" -#endif - -/* FreeRTOS includes. */ -#include "timers.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * An event group is a collection of bits to which an application can assign a - * meaning. For example, an application may create an event group to convey - * the status of various CAN bus related events in which bit 0 might mean "A CAN - * message has been received and is ready for processing", bit 1 might mean "The - * application has queued a message that is ready for sending onto the CAN - * network", and bit 2 might mean "It is time to send a SYNC message onto the - * CAN network" etc. A task can then test the bit values to see which events - * are active, and optionally enter the Blocked state to wait for a specified - * bit or a group of specified bits to be active. To continue the CAN bus - * example, a CAN controlling task can enter the Blocked state (and therefore - * not consume any processing time) until either bit 0, bit 1 or bit 2 are - * active, at which time the bit that was actually active would inform the task - * which action it had to take (process a received message, send a message, or - * send a SYNC). - * - * The event groups implementation contains intelligence to avoid race - * conditions that would otherwise occur were an application to use a simple - * variable for the same purpose. This is particularly important with respect - * to when a bit within an event group is to be cleared, and when bits have to - * be set and then tested atomically - as is the case where event groups are - * used to create a synchronisation point between multiple tasks (a - * 'rendezvous'). - * - * \defgroup EventGroup - */ - - - -/** - * event_groups.h - * - * Type by which event groups are referenced. For example, a call to - * xEventGroupCreate() returns an EventGroupHandle_t variable that can then - * be used as a parameter to other event group functions. - * - * \defgroup EventGroupHandle_t EventGroupHandle_t - * \ingroup EventGroup - */ -struct EventGroupDef_t; -typedef struct EventGroupDef_t * EventGroupHandle_t; - -/* - * The type that holds event bits always matches TickType_t - therefore the - * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, - * 32 bits if set to 0. - * - * \defgroup EventBits_t EventBits_t - * \ingroup EventGroup - */ -typedef TickType_t EventBits_t; - -/** - * event_groups.h - *
- EventGroupHandle_t xEventGroupCreate( void );
-
- * - * Create a new event group. - * - * Internally, within the FreeRTOS implementation, event groups use a [small] - * block of memory, in which the event group's structure is stored. If an event - * groups is created using xEventGropuCreate() then the required memory is - * automatically dynamically allocated inside the xEventGroupCreate() function. - * (see http://www.freertos.org/a00111.html). If an event group is created - * using xEventGropuCreateStatic() then the application writer must instead - * provide the memory that will get used by the event group. - * xEventGroupCreateStatic() therefore allows an event group to be created - * without using any dynamic memory allocation. - * - * Although event groups are not related to ticks, for internal implementation - * reasons the number of bits available for use in an event group is dependent - * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If - * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit - * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has - * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store - * event bits within an event group. - * - * @return If the event group was created then a handle to the event group is - * returned. If there was insufficient FreeRTOS heap available to create the - * event group then NULL is returned. See http://www.freertos.org/a00111.html - * - * Example usage: - 
-	// Declare a variable to hold the created event group.
-	EventGroupHandle_t xCreatedEventGroup;
-
-	// Attempt to create the event group.
-	xCreatedEventGroup = xEventGroupCreate();
-
-	// Was the event group created successfully?
-	if( xCreatedEventGroup == NULL )
-	{
-		// The event group was not created because there was insufficient
-		// FreeRTOS heap available.
-	}
-	else
-	{
-		// The event group was created.
-	}
-
- * \defgroup xEventGroupCreate xEventGroupCreate - * \ingroup EventGroup - */ -#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; -#endif - -/** - * event_groups.h - *
- EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
-
- * - * Create a new event group. - * - * Internally, within the FreeRTOS implementation, event groups use a [small] - * block of memory, in which the event group's structure is stored. If an event - * groups is created using xEventGropuCreate() then the required memory is - * automatically dynamically allocated inside the xEventGroupCreate() function. - * (see http://www.freertos.org/a00111.html). If an event group is created - * using xEventGropuCreateStatic() then the application writer must instead - * provide the memory that will get used by the event group. - * xEventGroupCreateStatic() therefore allows an event group to be created - * without using any dynamic memory allocation. - * - * Although event groups are not related to ticks, for internal implementation - * reasons the number of bits available for use in an event group is dependent - * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If - * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit - * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has - * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store - * event bits within an event group. - * - * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type - * StaticEventGroup_t, which will be then be used to hold the event group's data - * structures, removing the need for the memory to be allocated dynamically. - * - * @return If the event group was created then a handle to the event group is - * returned. If pxEventGroupBuffer was NULL then NULL is returned. - * - * Example usage: - 
-	// StaticEventGroup_t is a publicly accessible structure that has the same
-	// size and alignment requirements as the real event group structure.  It is
-	// provided as a mechanism for applications to know the size of the event
-	// group (which is dependent on the architecture and configuration file
-	// settings) without breaking the strict data hiding policy by exposing the
-	// real event group internals.  This StaticEventGroup_t variable is passed
-	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
-	// the event group's data structures
-	StaticEventGroup_t xEventGroupBuffer;
-
-	// Create the event group without dynamically allocating any memory.
-	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
-
- */ -#if( configSUPPORT_STATIC_ALLOCATION == 1 ) - EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION; -#endif - -/** - * event_groups.h - *
-	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
-										const EventBits_t uxBitsToWaitFor,
-										const BaseType_t xClearOnExit,
-										const BaseType_t xWaitForAllBits,
-										const TickType_t xTicksToWait );
-
- * - * [Potentially] block to wait for one or more bits to be set within a - * previously created event group. - * - * This function cannot be called from an interrupt. - * - * @param xEventGroup The event group in which the bits are being tested. The - * event group must have previously been created using a call to - * xEventGroupCreate(). - * - * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test - * inside the event group. For example, to wait for bit 0 and/or bit 2 set - * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set - * uxBitsToWaitFor to 0x07. Etc. - * - * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within - * uxBitsToWaitFor that are set within the event group will be cleared before - * xEventGroupWaitBits() returns if the wait condition was met (if the function - * returns for a reason other than a timeout). If xClearOnExit is set to - * pdFALSE then the bits set in the event group are not altered when the call to - * xEventGroupWaitBits() returns. - * - * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then - * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor - * are set or the specified block time expires. If xWaitForAllBits is set to - * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set - * in uxBitsToWaitFor is set or the specified block time expires. The block - * time is specified by the xTicksToWait parameter. - * - * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait - * for one/all (depending on the xWaitForAllBits value) of the bits specified by - * uxBitsToWaitFor to become set. - * - * @return The value of the event group at the time either the bits being waited - * for became set, or the block time expired. Test the return value to know - * which bits were set. If xEventGroupWaitBits() returned because its timeout - * expired then not all the bits being waited for will be set. If - * xEventGroupWaitBits() returned because the bits it was waiting for were set - * then the returned value is the event group value before any bits were - * automatically cleared in the case that xClearOnExit parameter was set to - * pdTRUE. - * - * Example usage: - 
-   #define BIT_0	( 1 << 0 )
-   #define BIT_4	( 1 << 4 )
-
-   void aFunction( EventGroupHandle_t xEventGroup )
-   {
-   EventBits_t uxBits;
-   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
-
-		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
-		// the event group.  Clear the bits before exiting.
-		uxBits = xEventGroupWaitBits(
-					xEventGroup,	// The event group being tested.
-					BIT_0 | BIT_4,	// The bits within the event group to wait for.
-					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
-					pdFALSE,		// Don't wait for both bits, either bit will do.
-					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
-
-		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
-		{
-			// xEventGroupWaitBits() returned because both bits were set.
-		}
-		else if( ( uxBits & BIT_0 ) != 0 )
-		{
-			// xEventGroupWaitBits() returned because just BIT_0 was set.
-		}
-		else if( ( uxBits & BIT_4 ) != 0 )
-		{
-			// xEventGroupWaitBits() returned because just BIT_4 was set.
-		}
-		else
-		{
-			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
-			// without either BIT_0 or BIT_4 becoming set.
-		}
-   }
-
- * \defgroup xEventGroupWaitBits xEventGroupWaitBits - * \ingroup EventGroup - */ -EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; - -/** - * event_groups.h - *
-	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
-
- * - * Clear bits within an event group. This function cannot be called from an - * interrupt. - * - * @param xEventGroup The event group in which the bits are to be cleared. - * - * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear - * in the event group. For example, to clear bit 3 only, set uxBitsToClear to - * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. - * - * @return The value of the event group before the specified bits were cleared. - * - * Example usage: - 
-   #define BIT_0	( 1 << 0 )
-   #define BIT_4	( 1 << 4 )
-
-   void aFunction( EventGroupHandle_t xEventGroup )
-   {
-   EventBits_t uxBits;
-
-		// Clear bit 0 and bit 4 in xEventGroup.
-		uxBits = xEventGroupClearBits(
-								xEventGroup,	// The event group being updated.
-								BIT_0 | BIT_4 );// The bits being cleared.
-
-		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
-		{
-			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
-			// called.  Both will now be clear (not set).
-		}
-		else if( ( uxBits & BIT_0 ) != 0 )
-		{
-			// Bit 0 was set before xEventGroupClearBits() was called.  It will
-			// now be clear.
-		}
-		else if( ( uxBits & BIT_4 ) != 0 )
-		{
-			// Bit 4 was set before xEventGroupClearBits() was called.  It will
-			// now be clear.
-		}
-		else
-		{
-			// Neither bit 0 nor bit 4 were set in the first place.
-		}
-   }
-
- * \defgroup xEventGroupClearBits xEventGroupClearBits - * \ingroup EventGroup - */ -EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; - -/** - * event_groups.h - *
-	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
-
- * - * A version of xEventGroupClearBits() that can be called from an interrupt. - * - * Setting bits in an event group is not a deterministic operation because there - * are an unknown number of tasks that may be waiting for the bit or bits being - * set. FreeRTOS does not allow nondeterministic operations to be performed - * while interrupts are disabled, so protects event groups that are accessed - * from tasks by suspending the scheduler rather than disabling interrupts. As - * a result event groups cannot be accessed directly from an interrupt service - * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the - * timer task to have the clear operation performed in the context of the timer - * task. - * - * @param xEventGroup The event group in which the bits are to be cleared. - * - * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. - * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 - * and bit 0 set uxBitsToClear to 0x09. - * - * @return If the request to execute the function was posted successfully then - * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned - * if the timer service queue was full. - * - * Example usage: - 
-   #define BIT_0	( 1 << 0 )
-   #define BIT_4	( 1 << 4 )
-
-   // An event group which it is assumed has already been created by a call to
-   // xEventGroupCreate().
-   EventGroupHandle_t xEventGroup;
-
-   void anInterruptHandler( void )
-   {
-		// Clear bit 0 and bit 4 in xEventGroup.
-		xResult = xEventGroupClearBitsFromISR(
-							xEventGroup,	 // The event group being updated.
-							BIT_0 | BIT_4 ); // The bits being set.
-
-		if( xResult == pdPASS )
-		{
-			// The message was posted successfully.
-		}
-  }
-
- * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR - * \ingroup EventGroup - */ -#if( configUSE_TRACE_FACILITY == 1 ) - BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; -#else - #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) -#endif - -/** - * event_groups.h - *
-	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
-
- * - * Set bits within an event group. - * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() - * is a version that can be called from an interrupt. - * - * Setting bits in an event group will automatically unblock tasks that are - * blocked waiting for the bits. - * - * @param xEventGroup The event group in which the bits are to be set. - * - * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. - * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 - * and bit 0 set uxBitsToSet to 0x09. - * - * @return The value of the event group at the time the call to - * xEventGroupSetBits() returns. There are two reasons why the returned value - * might have the bits specified by the uxBitsToSet parameter cleared. First, - * if setting a bit results in a task that was waiting for the bit leaving the - * blocked state then it is possible the bit will be cleared automatically - * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any - * unblocked (or otherwise Ready state) task that has a priority above that of - * the task that called xEventGroupSetBits() will execute and may change the - * event group value before the call to xEventGroupSetBits() returns. - * - * Example usage: - 
-   #define BIT_0	( 1 << 0 )
-   #define BIT_4	( 1 << 4 )
-
-   void aFunction( EventGroupHandle_t xEventGroup )
-   {
-   EventBits_t uxBits;
-
-		// Set bit 0 and bit 4 in xEventGroup.
-		uxBits = xEventGroupSetBits(
-							xEventGroup,	// The event group being updated.
-							BIT_0 | BIT_4 );// The bits being set.
-
-		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
-		{
-			// Both bit 0 and bit 4 remained set when the function returned.
-		}
-		else if( ( uxBits & BIT_0 ) != 0 )
-		{
-			// Bit 0 remained set when the function returned, but bit 4 was
-			// cleared.  It might be that bit 4 was cleared automatically as a
-			// task that was waiting for bit 4 was removed from the Blocked
-			// state.
-		}
-		else if( ( uxBits & BIT_4 ) != 0 )
-		{
-			// Bit 4 remained set when the function returned, but bit 0 was
-			// cleared.  It might be that bit 0 was cleared automatically as a
-			// task that was waiting for bit 0 was removed from the Blocked
-			// state.
-		}
-		else
-		{
-			// Neither bit 0 nor bit 4 remained set.  It might be that a task
-			// was waiting for both of the bits to be set, and the bits were
-			// cleared as the task left the Blocked state.
-		}
-   }
-
- * \defgroup xEventGroupSetBits xEventGroupSetBits - * \ingroup EventGroup - */ -EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; - -/** - * event_groups.h - *
-	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
-
- * - * A version of xEventGroupSetBits() that can be called from an interrupt. - * - * Setting bits in an event group is not a deterministic operation because there - * are an unknown number of tasks that may be waiting for the bit or bits being - * set. FreeRTOS does not allow nondeterministic operations to be performed in - * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() - * sends a message to the timer task to have the set operation performed in the - * context of the timer task - where a scheduler lock is used in place of a - * critical section. - * - * @param xEventGroup The event group in which the bits are to be set. - * - * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. - * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 - * and bit 0 set uxBitsToSet to 0x09. - * - * @param pxHigherPriorityTaskWoken As mentioned above, calling this function - * will result in a message being sent to the timer daemon task. If the - * priority of the timer daemon task is higher than the priority of the - * currently running task (the task the interrupt interrupted) then - * *pxHigherPriorityTaskWoken will be set to pdTRUE by - * xEventGroupSetBitsFromISR(), indicating that a context switch should be - * requested before the interrupt exits. For that reason - * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the - * example code below. - * - * @return If the request to execute the function was posted successfully then - * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned - * if the timer service queue was full. - * - * Example usage: - 
-   #define BIT_0	( 1 << 0 )
-   #define BIT_4	( 1 << 4 )
-
-   // An event group which it is assumed has already been created by a call to
-   // xEventGroupCreate().
-   EventGroupHandle_t xEventGroup;
-
-   void anInterruptHandler( void )
-   {
-   BaseType_t xHigherPriorityTaskWoken, xResult;
-
-		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
-		xHigherPriorityTaskWoken = pdFALSE;
-
-		// Set bit 0 and bit 4 in xEventGroup.
-		xResult = xEventGroupSetBitsFromISR(
-							xEventGroup,	// The event group being updated.
-							BIT_0 | BIT_4   // The bits being set.
-							&xHigherPriorityTaskWoken );
-
-		// Was the message posted successfully?
-		if( xResult == pdPASS )
-		{
-			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
-			// switch should be requested.  The macro used is port specific and
-			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
-			// refer to the documentation page for the port being used.
-			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-		}
-  }
-
- * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR - * \ingroup EventGroup - */ -#if( configUSE_TRACE_FACILITY == 1 ) - BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; -#else - #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) -#endif - -/** - * event_groups.h - *
-	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
-									const EventBits_t uxBitsToSet,
-									const EventBits_t uxBitsToWaitFor,
-									TickType_t xTicksToWait );
-
- * - * Atomically set bits within an event group, then wait for a combination of - * bits to be set within the same event group. This functionality is typically - * used to synchronise multiple tasks, where each task has to wait for the other - * tasks to reach a synchronisation point before proceeding. - * - * This function cannot be used from an interrupt. - * - * The function will return before its block time expires if the bits specified - * by the uxBitsToWait parameter are set, or become set within that time. In - * this case all the bits specified by uxBitsToWait will be automatically - * cleared before the function returns. - * - * @param xEventGroup The event group in which the bits are being tested. The - * event group must have previously been created using a call to - * xEventGroupCreate(). - * - * @param uxBitsToSet The bits to set in the event group before determining - * if, and possibly waiting for, all the bits specified by the uxBitsToWait - * parameter are set. - * - * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test - * inside the event group. For example, to wait for bit 0 and bit 2 set - * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set - * uxBitsToWaitFor to 0x07. Etc. - * - * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait - * for all of the bits specified by uxBitsToWaitFor to become set. - * - * @return The value of the event group at the time either the bits being waited - * for became set, or the block time expired. Test the return value to know - * which bits were set. If xEventGroupSync() returned because its timeout - * expired then not all the bits being waited for will be set. If - * xEventGroupSync() returned because all the bits it was waiting for were - * set then the returned value is the event group value before any bits were - * automatically cleared. - * - * Example usage: - 
- // Bits used by the three tasks.
- #define TASK_0_BIT		( 1 << 0 )
- #define TASK_1_BIT		( 1 << 1 )
- #define TASK_2_BIT		( 1 << 2 )
-
- #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
-
- // Use an event group to synchronise three tasks.  It is assumed this event
- // group has already been created elsewhere.
- EventGroupHandle_t xEventBits;
-
- void vTask0( void *pvParameters )
- {
- EventBits_t uxReturn;
- TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
-
-	 for( ;; )
-	 {
-		// Perform task functionality here.
-
-		// Set bit 0 in the event flag to note this task has reached the
-		// sync point.  The other two tasks will set the other two bits defined
-		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
-		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
-		// for this to happen.
-		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
-
-		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
-		{
-			// All three tasks reached the synchronisation point before the call
-			// to xEventGroupSync() timed out.
-		}
-	}
- }
-
- void vTask1( void *pvParameters )
- {
-	 for( ;; )
-	 {
-		// Perform task functionality here.
-
-		// Set bit 1 in the event flag to note this task has reached the
-		// synchronisation point.  The other two tasks will set the other two
-		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
-		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
-		// indefinitely for this to happen.
-		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
-
-		// xEventGroupSync() was called with an indefinite block time, so
-		// this task will only reach here if the syncrhonisation was made by all
-		// three tasks, so there is no need to test the return value.
-	 }
- }
-
- void vTask2( void *pvParameters )
- {
-	 for( ;; )
-	 {
-		// Perform task functionality here.
-
-		// Set bit 2 in the event flag to note this task has reached the
-		// synchronisation point.  The other two tasks will set the other two
-		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
-		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
-		// indefinitely for this to happen.
-		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
-
-		// xEventGroupSync() was called with an indefinite block time, so
-		// this task will only reach here if the syncrhonisation was made by all
-		// three tasks, so there is no need to test the return value.
-	}
- }
-
-
- * \defgroup xEventGroupSync xEventGroupSync - * \ingroup EventGroup - */ -EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; - - -/** - * event_groups.h - *
-	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
-
- * - * Returns the current value of the bits in an event group. This function - * cannot be used from an interrupt. - * - * @param xEventGroup The event group being queried. - * - * @return The event group bits at the time xEventGroupGetBits() was called. - * - * \defgroup xEventGroupGetBits xEventGroupGetBits - * \ingroup EventGroup - */ -#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 ) - -/** - * event_groups.h - *
-	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
-
- * - * A version of xEventGroupGetBits() that can be called from an ISR. - * - * @param xEventGroup The event group being queried. - * - * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. - * - * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR - * \ingroup EventGroup - */ -EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; - -/** - * event_groups.h - *
-	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
-
- * - * Delete an event group that was previously created by a call to - * xEventGroupCreate(). Tasks that are blocked on the event group will be - * unblocked and obtain 0 as the event group's value. - * - * @param xEventGroup The event group being deleted. - */ -void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; - -/* For internal use only. */ -void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; -void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; - - -#if (configUSE_TRACE_FACILITY == 1) - UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION; - void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* EVENT_GROUPS_H */ - - diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/freertos_tasks_c_additions.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/freertos_tasks_c_additions.h deleted file mode 100644 index 00f5646..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/freertos_tasks_c_additions.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright 2017-2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* freertos_tasks_c_additions.h Rev. 1.3 */ -#ifndef FREERTOS_TASKS_C_ADDITIONS_H -#define FREERTOS_TASKS_C_ADDITIONS_H - -#include - -#if (configUSE_TRACE_FACILITY == 0) -#error "configUSE_TRACE_FACILITY must be enabled" -#endif - -#define FREERTOS_DEBUG_CONFIG_MAJOR_VERSION 1 -#define FREERTOS_DEBUG_CONFIG_MINOR_VERSION 3 - -/* NOTE!! - * Default to a FreeRTOS version which didn't include these macros. FreeRTOS - * v7.5.3 is used here. - */ -#ifndef tskKERNEL_VERSION_BUILD -#define tskKERNEL_VERSION_BUILD 3 -#endif -#ifndef tskKERNEL_VERSION_MINOR -#define tskKERNEL_VERSION_MINOR 5 -#endif -#ifndef tskKERNEL_VERSION_MAJOR -#define tskKERNEL_VERSION_MAJOR 7 -#endif - -/* NOTE!! - * The configFRTOS_MEMORY_SCHEME macro describes the heap scheme using a value - * 1 - 5 which corresponds to the following schemes: - * - * heap_1 - the very simplest, does not permit memory to be freed - * heap_2 - permits memory to be freed, but not does coalescence adjacent free - * blocks. - * heap_3 - simply wraps the standard malloc() and free() for thread safety - * heap_4 - coalesces adjacent free blocks to avoid fragmentation. Includes - * absolute address placement option - * heap_5 - as per heap_4, with the ability to span the heap across - * multiple nonOadjacent memory areas - */ -#ifndef configFRTOS_MEMORY_SCHEME -#define configFRTOS_MEMORY_SCHEME 3 /* thread safe malloc */ -#endif - -#if ((configFRTOS_MEMORY_SCHEME > 5) || (configFRTOS_MEMORY_SCHEME < 1)) -#error "Invalid configFRTOS_MEMORY_SCHEME setting!" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -extern const uint8_t FreeRTOSDebugConfig[]; - -/* NOTES!! - * IAR documentation is confusing. It suggests the data must be statically - * linked, and the #pragma placed immediately before the symbol definition. - * The IAR supplied examples violate both "rules", so this is a best guess. - */ - -#if (tskKERNEL_VERSION_MAJOR >= 10) && (tskKERNEL_VERSION_MINOR >= 2) -#if defined(__GNUC__) -char *const portArch_Name __attribute__((section(".rodata"))) = portARCH_NAME; -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -char *const portArch_Name __attribute__((used)) = portARCH_NAME; -#elif defined(__IAR_SYSTEMS_ICC__) -char *const portArch_Name = portARCH_NAME; -#pragma required=portArch_Name -#endif -#else -char *const portArch_Name = NULL; -#endif // tskKERNEL_VERSION_MAJOR - -#if defined(__GNUC__) -const uint8_t FreeRTOSDebugConfig[] __attribute__((section(".rodata"))) = -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -const uint8_t FreeRTOSDebugConfig[] __attribute__((used)) = -#elif defined(__IAR_SYSTEMS_ICC__) -#pragma required=FreeRTOSDebugConfig -const uint8_t FreeRTOSDebugConfig[] = -#endif -{ - FREERTOS_DEBUG_CONFIG_MAJOR_VERSION, - FREERTOS_DEBUG_CONFIG_MINOR_VERSION, - tskKERNEL_VERSION_MAJOR, - tskKERNEL_VERSION_MINOR, - tskKERNEL_VERSION_BUILD, - configFRTOS_MEMORY_SCHEME, - offsetof(struct tskTaskControlBlock, pxTopOfStack), -#if (tskKERNEL_VERSION_MAJOR > 8) - offsetof(struct tskTaskControlBlock, xStateListItem), -#else - offsetof(struct tskTaskControlBlock, xGenericListItem), -#endif - offsetof(struct tskTaskControlBlock, xEventListItem), - offsetof(struct tskTaskControlBlock, pxStack), - offsetof(struct tskTaskControlBlock, pcTaskName), - offsetof(struct tskTaskControlBlock, uxTCBNumber), - offsetof(struct tskTaskControlBlock, uxTaskNumber), - configMAX_TASK_NAME_LEN, - configMAX_PRIORITIES, - configENABLE_MPU, - configENABLE_FPU, - configENABLE_TRUSTZONE, - configRUN_FREERTOS_SECURE_ONLY, - 0, // 32-bit align - 0, 0, 0, 0 // padding -}; - -#ifdef __cplusplus -} -#endif - -#endif // FREERTOS_TASKS_C_ADDITIONS_H diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/list.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/list.h deleted file mode 100644 index b2bb46d..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/list.h +++ /dev/null @@ -1,412 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* - * This is the list implementation used by the scheduler. While it is tailored - * heavily for the schedulers needs, it is also available for use by - * application code. - * - * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a - * numeric value (xItemValue). Most of the time the lists are sorted in - * descending item value order. - * - * Lists are created already containing one list item. The value of this - * item is the maximum possible that can be stored, it is therefore always at - * the end of the list and acts as a marker. The list member pxHead always - * points to this marker - even though it is at the tail of the list. This - * is because the tail contains a wrap back pointer to the true head of - * the list. - * - * In addition to it's value, each list item contains a pointer to the next - * item in the list (pxNext), a pointer to the list it is in (pxContainer) - * and a pointer to back to the object that contains it. These later two - * pointers are included for efficiency of list manipulation. There is - * effectively a two way link between the object containing the list item and - * the list item itself. - * - * - * \page ListIntroduction List Implementation - * \ingroup FreeRTOSIntro - */ - -#ifndef INC_FREERTOS_H - #error FreeRTOS.h must be included before list.h -#endif - -#ifndef LIST_H -#define LIST_H - -/* - * The list structure members are modified from within interrupts, and therefore - * by rights should be declared volatile. However, they are only modified in a - * functionally atomic way (within critical sections of with the scheduler - * suspended) and are either passed by reference into a function or indexed via - * a volatile variable. Therefore, in all use cases tested so far, the volatile - * qualifier can be omitted in order to provide a moderate performance - * improvement without adversely affecting functional behaviour. The assembly - * instructions generated by the IAR, ARM and GCC compilers when the respective - * compiler's options were set for maximum optimisation has been inspected and - * deemed to be as intended. That said, as compiler technology advances, and - * especially if aggressive cross module optimisation is used (a use case that - * has not been exercised to any great extend) then it is feasible that the - * volatile qualifier will be needed for correct optimisation. It is expected - * that a compiler removing essential code because, without the volatile - * qualifier on the list structure members and with aggressive cross module - * optimisation, the compiler deemed the code unnecessary will result in - * complete and obvious failure of the scheduler. If this is ever experienced - * then the volatile qualifier can be inserted in the relevant places within the - * list structures by simply defining configLIST_VOLATILE to volatile in - * FreeRTOSConfig.h (as per the example at the bottom of this comment block). - * If configLIST_VOLATILE is not defined then the preprocessor directives below - * will simply #define configLIST_VOLATILE away completely. - * - * To use volatile list structure members then add the following line to - * FreeRTOSConfig.h (without the quotes): - * "#define configLIST_VOLATILE volatile" - */ -#ifndef configLIST_VOLATILE - #define configLIST_VOLATILE -#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Macros that can be used to place known values within the list structures, -then check that the known values do not get corrupted during the execution of -the application. These may catch the list data structures being overwritten in -memory. They will not catch data errors caused by incorrect configuration or -use of FreeRTOS.*/ -#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) - /* Define the macros to do nothing. */ - #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE - #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE - #define listFIRST_LIST_INTEGRITY_CHECK_VALUE - #define listSECOND_LIST_INTEGRITY_CHECK_VALUE - #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) - #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) - #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) - #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) - #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) - #define listTEST_LIST_INTEGRITY( pxList ) -#else - /* Define macros that add new members into the list structures. */ - #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; - #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; - #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; - #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; - - /* Define macros that set the new structure members to known values. */ - #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE - #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE - #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE - #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE - - /* Define macros that will assert if one of the structure members does not - contain its expected value. */ - #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) - #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) -#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ - - -/* - * Definition of the only type of object that a list can contain. - */ -struct xLIST; -struct xLIST_ITEM -{ - listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ - configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ - struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ - struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ - void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ - struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ - listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ -}; -typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ - -struct xMINI_LIST_ITEM -{ - listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ - configLIST_VOLATILE TickType_t xItemValue; - struct xLIST_ITEM * configLIST_VOLATILE pxNext; - struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; -}; -typedef struct xMINI_LIST_ITEM MiniListItem_t; - -/* - * Definition of the type of queue used by the scheduler. - */ -typedef struct xLIST -{ - listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ - volatile UBaseType_t uxNumberOfItems; - ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ - MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ - listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ -} List_t; - -/* - * Access macro to set the owner of a list item. The owner of a list item - * is the object (usually a TCB) that contains the list item. - * - * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) - -/* - * Access macro to get the owner of a list item. The owner of a list item - * is the object (usually a TCB) that contains the list item. - * - * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER - * \ingroup LinkedList - */ -#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) - -/* - * Access macro to set the value of the list item. In most cases the value is - * used to sort the list in descending order. - * - * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) - -/* - * Access macro to retrieve the value of the list item. The value can - * represent anything - for example the priority of a task, or the time at - * which a task should be unblocked. - * - * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) - -/* - * Access macro to retrieve the value of the list item at the head of a given - * list. - * - * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) - -/* - * Return the list item at the head of the list. - * - * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY - * \ingroup LinkedList - */ -#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) - -/* - * Return the list item at the head of the list. - * - * \page listGET_NEXT listGET_NEXT - * \ingroup LinkedList - */ -#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) - -/* - * Return the list item that marks the end of the list - * - * \page listGET_END_MARKER listGET_END_MARKER - * \ingroup LinkedList - */ -#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) - -/* - * Access macro to determine if a list contains any items. The macro will - * only have the value true if the list is empty. - * - * \page listLIST_IS_EMPTY listLIST_IS_EMPTY - * \ingroup LinkedList - */ -#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) - -/* - * Access macro to return the number of items in the list. - */ -#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) - -/* - * Access function to obtain the owner of the next entry in a list. - * - * The list member pxIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list - * and returns that entry's pxOwner parameter. Using multiple calls to this - * function it is therefore possible to move through every item contained in - * a list. - * - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxTCB pxTCB is set to the address of the owner of the next list item. - * @param pxList The list from which the next item owner is to be returned. - * - * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ -{ \ -List_t * const pxConstList = ( pxList ); \ - /* Increment the index to the next item and return the item, ensuring */ \ - /* we don't return the marker used at the end of the list. */ \ - ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ - if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ - { \ - ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ - } \ - ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ -} - - -/* - * Access function to obtain the owner of the first entry in a list. Lists - * are normally sorted in ascending item value order. - * - * This function returns the pxOwner member of the first item in the list. - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the owner of the head item is to be - * returned. - * - * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner ) - -/* - * Check to see if a list item is within a list. The list item maintains a - * "container" pointer that points to the list it is in. All this macro does - * is check to see if the container and the list match. - * - * @param pxList The list we want to know if the list item is within. - * @param pxListItem The list item we want to know if is in the list. - * @return pdTRUE if the list item is in the list, otherwise pdFALSE. - */ -#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) - -/* - * Return the list a list item is contained within (referenced from). - * - * @param pxListItem The list item being queried. - * @return A pointer to the List_t object that references the pxListItem - */ -#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) - -/* - * This provides a crude means of knowing if a list has been initialised, as - * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() - * function. - */ -#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) - -/* - * Must be called before a list is used! This initialises all the members - * of the list structure and inserts the xListEnd item into the list as a - * marker to the back of the list. - * - * @param pxList Pointer to the list being initialised. - * - * \page vListInitialise vListInitialise - * \ingroup LinkedList - */ -void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; - -/* - * Must be called before a list item is used. This sets the list container to - * null so the item does not think that it is already contained in a list. - * - * @param pxItem Pointer to the list item being initialised. - * - * \page vListInitialiseItem vListInitialiseItem - * \ingroup LinkedList - */ -void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; - -/* - * Insert a list item into a list. The item will be inserted into the list in - * a position determined by its item value (descending item value order). - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The item that is to be placed in the list. - * - * \page vListInsert vListInsert - * \ingroup LinkedList - */ -void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; - -/* - * Insert a list item into a list. The item will be inserted in a position - * such that it will be the last item within the list returned by multiple - * calls to listGET_OWNER_OF_NEXT_ENTRY. - * - * The list member pxIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. - * Placing an item in a list using vListInsertEnd effectively places the item - * in the list position pointed to by pxIndex. This means that every other - * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before - * the pxIndex parameter again points to the item being inserted. - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The list item to be inserted into the list. - * - * \page vListInsertEnd vListInsertEnd - * \ingroup LinkedList - */ -void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; - -/* - * Remove an item from a list. The list item has a pointer to the list that - * it is in, so only the list item need be passed into the function. - * - * @param uxListRemove The item to be removed. The item will remove itself from - * the list pointed to by it's pxContainer parameter. - * - * @return The number of items that remain in the list after the list item has - * been removed. - * - * \page uxListRemove uxListRemove - * \ingroup LinkedList - */ -UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/message_buffer.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/message_buffer.h deleted file mode 100644 index 9ee3f4d..0000000 --- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/message_buffer.h +++ /dev/null @@ -1,799 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - -/* - * Message buffers build functionality on top of FreeRTOS stream buffers. - * Whereas stream buffers are used to send a continuous stream of data from one - * task or interrupt to another, message buffers are used to send variable - * length discrete messages from one task or interrupt to another. Their - * implementation is light weight, making them particularly suited for interrupt - * to task and core to core communication scenarios. - * - * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer - * implementation (so also the message buffer implementation, as message buffers - * are built on top of stream buffers) assumes there is only one task or - * interrupt that will write to the buffer (the writer), and only one task or - * interrupt that will read from the buffer (the reader). It is safe for the - * writer and reader to be different tasks or interrupts, but, unlike other - * FreeRTOS objects, it is not safe to have multiple different writers or - * multiple different readers. If there are to be multiple different writers - * then the application writer must place each call to a writing API function - * (such as xMessageBufferSend()) inside a critical section and set the send - * block time to 0. Likewise, if there are to be multiple different readers - * then the application writer must place each call to a reading API function - * (such as xMessageBufferRead()) inside a critical section and set the receive - * timeout to 0. - * - * Message buffers hold variable length messages. To enable that, when a - * message is written to the message buffer an additional sizeof( size_t ) bytes - * are also written to store the message's length (that happens internally, with - * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit - * architecture, so writing a 10 byte message to a message buffer on a 32-bit - * architecture will actually reduce the available space in the message buffer - * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length - * of the message). - */ - -#ifndef FREERTOS_MESSAGE_BUFFER_H -#define FREERTOS_MESSAGE_BUFFER_H - -/* Message buffers are built onto of stream buffers. */ -#include "stream_buffer.h" - -#if defined( __cplusplus ) -extern "C" { -#endif - -/** - * Type by which message buffers are referenced. For example, a call to - * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can - * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), - * etc. - */ -typedef void * MessageBufferHandle_t; - -/*-----------------------------------------------------------*/ - -/** - * message_buffer.h - * -
-MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
-
- * - * Creates a new message buffer using dynamically allocated memory. See - * xMessageBufferCreateStatic() for a version that uses statically allocated - * memory (memory that is allocated at compile time). - * - * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in - * FreeRTOSConfig.h for xMessageBufferCreate() to be available. - * - * @param xBufferSizeBytes The total number of bytes (not messages) the message - * buffer will be able to hold at any one time. When a message is written to - * the message buffer an additional sizeof( size_t ) bytes are also written to - * store the message's length. sizeof( size_t ) is typically 4 bytes on a - * 32-bit architecture, so on most 32-bit architectures a 10 byte message will - * take up 14 bytes of message buffer space. - * - * @return If NULL is returned, then the message buffer cannot be created - * because there is insufficient heap memory available for FreeRTOS to allocate - * the message buffer data structures and storage area. A non-NULL value being - * returned indicates that the message buffer has been created successfully - - * the returned value should be stored as the handle to the created message - * buffer. - * - * Example use: -
-
-void vAFunction( void )
-{
-MessageBufferHandle_t xMessageBuffer;
-const size_t xMessageBufferSizeBytes = 100;
-
-    // Create a message buffer that can hold 100 bytes.  The memory used to hold
-    // both the message buffer structure and the messages themselves is allocated
-    // dynamically.  Each message added to the buffer consumes an additional 4
-    // bytes which are used to hold the lengh of the message.
-    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
-
-    if( xMessageBuffer == NULL )
-    {
-        // There was not enough heap memory space available to create the
-        // message buffer.
-    }
-    else
-    {
-        // The message buffer was created successfully and can now be used.
-    }
-
-
- * \defgroup xMessageBufferCreate xMessageBufferCreate - * \ingroup MessageBufferManagement - */ -#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE ) - -/** - * message_buffer.h - * -
-MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
-                                                  uint8_t *pucMessageBufferStorageArea,
-                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
-
- * Creates a new message buffer using statically allocated memory. See - * xMessageBufferCreate() for a version that uses dynamically allocated memory. - * - * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the - * pucMessageBufferStorageArea parameter. When a message is written to the - * message buffer an additional sizeof( size_t ) bytes are also written to store - * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit - * architecture, so on most 32-bit architecture a 10 byte message will take up - * 14 bytes of message buffer space. The maximum number of bytes that can be - * stored in the message buffer is actually (xBufferSizeBytes - 1). - * - * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at - * least xBufferSizeBytes + 1 big. This is the array to which messages are - * copied when they are written to the message buffer. - * - * @param pxStaticMessageBuffer Must point to a variable of type - * StaticMessageBuffer_t, which will be used to hold the message buffer's data - * structure. - * - * @return If the message buffer is created successfully then a handle to the - * created message buffer is returned. If either pucMessageBufferStorageArea or - * pxStaticmessageBuffer are NULL then NULL is returned. - * - * Example use: -
-
-// Used to dimension the array used to hold the messages.  The available space
-// will actually be one less than this, so 999.
-#define STORAGE_SIZE_BYTES 1000
-
-// Defines the memory that will actually hold the messages within the message
-// buffer.
-static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
-
-// The variable used to hold the message buffer structure.
-StaticMessageBuffer_t xMessageBufferStruct;
-
-void MyFunction( void )
-{
-MessageBufferHandle_t xMessageBuffer;
-
-    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
-                                                 ucBufferStorage,
-                                                 &xMessageBufferStruct );
-
-    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
-    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
-    // reference the created message buffer in other message buffer API calls.
-
-    // Other code that uses the message buffer can go here.
-}
-
-
- * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic - * \ingroup MessageBufferManagement - */ -#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer ) - -/** - * message_buffer.h - * -
-size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
-                           const void *pvTxData,
-                           size_t xDataLengthBytes,
-                           TickType_t xTicksToWait );
-
- *
- * Sends a discrete message to the message buffer.  The message can be any
- * length that fits within the buffer's free space, and is copied into the
- * buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xMessageBufferSend() to write to a message buffer from a task.  Use
- * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
- * service routine (ISR).
- *
- * @param xMessageBuffer The handle of the message buffer to which a message is
- * being sent.
- *
- * @param pvTxData A pointer to the message that is to be copied into the
- * message buffer.
- *
- * @param xDataLengthBytes The length of the message.  That is, the number of
- * bytes to copy from pvTxData into the message buffer.  When a message is
- * written to the message buffer an additional sizeof( size_t ) bytes are also
- * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
- * on a 32-bit architecture, so on most 32-bit architecture setting
- * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
- * bytes (20 bytes of message data and 4 bytes to hold the message length).
- *
- * @param xTicksToWait The maximum amount of time the calling task should remain
- * in the Blocked state to wait for enough space to become available in the
- * message buffer, should the message buffer have insufficient space when
- * xMessageBufferSend() is called.  The calling task will never block if
- * xTicksToWait is zero.  The block time is specified in tick periods, so the
- * absolute time it represents is dependent on the tick frequency.  The macro
- * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
- * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
- * the task to wait indefinitely (without timing out), provided
- * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
- * CPU time when they are in the Blocked state.
- *
- * @return The number of bytes written to the message buffer.  If the call to
- * xMessageBufferSend() times out before there was enough space to write the
- * message into the message buffer then zero is returned.  If the call did not
- * time out then xDataLengthBytes is returned.
- *
- * Example use:
-
-void vAFunction( MessageBufferHandle_t xMessageBuffer )
-{
-size_t xBytesSent;
-uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
-char *pcStringToSend = "String to send";
-const TickType_t x100ms = pdMS_TO_TICKS( 100 );
-
-    // Send an array to the message buffer, blocking for a maximum of 100ms to
-    // wait for enough space to be available in the message buffer.
-    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
-
-    if( xBytesSent != sizeof( ucArrayToSend ) )
-    {
-        // The call to xMessageBufferSend() times out before there was enough
-        // space in the buffer for the data to be written.
-    }
-
-    // Send the string to the message buffer.  Return immediately if there is
-    // not enough space in the buffer.
-    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
-
-    if( xBytesSent != strlen( pcStringToSend ) )
-    {
-        // The string could not be added to the message buffer because there was
-        // not enough free space in the buffer.
-    }
-}
-

- * \defgroup xMessageBufferSend xMessageBufferSend
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
-
-/**
- * message_buffer.h
- *
-
-size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
-                                  const void *pvTxData,
-                                  size_t xDataLengthBytes,
-                                  BaseType_t *pxHigherPriorityTaskWoken );
-
- *
- * Interrupt safe version of the API function that sends a discrete message to
- * the message buffer.  The message can be any length that fits within the
- * buffer's free space, and is copied into the buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xMessageBufferSend() to write to a message buffer from a task.  Use
- * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
- * service routine (ISR).
- *
- * @param xMessageBuffer The handle of the message buffer to which a message is
- * being sent.
- *
- * @param pvTxData A pointer to the message that is to be copied into the
- * message buffer.
- *
- * @param xDataLengthBytes The length of the message.  That is, the number of
- * bytes to copy from pvTxData into the message buffer.  When a message is
- * written to the message buffer an additional sizeof( size_t ) bytes are also
- * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
- * on a 32-bit architecture, so on most 32-bit architecture setting
- * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
- * bytes (20 bytes of message data and 4 bytes to hold the message length).
- *
- * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
- * have a task blocked on it waiting for data.  Calling
- * xMessageBufferSendFromISR() can make data available, and so cause a task that
- * was waiting for data to leave the Blocked state.  If calling
- * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently executing task (the
- * task that was interrupted), then, internally, xMessageBufferSendFromISR()
- * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
- * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
- * context switch should be performed before the interrupt is exited.  This will
- * ensure that the interrupt returns directly to the highest priority Ready
- * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
- * is passed into the function.  See the code example below for an example.
- *
- * @return The number of bytes actually written to the message buffer.  If the
- * message buffer didn't have enough free space for the message to be stored
- * then 0 is returned, otherwise xDataLengthBytes is returned.
- *
- * Example use:
-
-// A message buffer that has already been created.
-MessageBufferHandle_t xMessageBuffer;
-
-void vAnInterruptServiceRoutine( void )
-{
-size_t xBytesSent;
-char *pcStringToSend = "String to send";
-BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
-
-    // Attempt to send the string to the message buffer.
-    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
-                                            ( void * ) pcStringToSend,
-                                            strlen( pcStringToSend ),
-                                            &xHigherPriorityTaskWoken );
-
-    if( xBytesSent != strlen( pcStringToSend ) )
-    {
-        // The string could not be added to the message buffer because there was
-        // not enough free space in the buffer.
-    }
-
-    // If xHigherPriorityTaskWoken was set to pdTRUE inside
-    // xMessageBufferSendFromISR() then a task that has a priority above the
-    // priority of the currently executing task was unblocked and a context
-    // switch should be performed to ensure the ISR returns to the unblocked
-    // task.  In most FreeRTOS ports this is done by simply passing
-    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
-    // variables value, and perform the context switch if necessary.  Check the
-    // documentation for the port in use for port specific instructions.
-    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-}
-

- * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
-
-/**
- * message_buffer.h
- *
-
-size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
-                              void *pvRxData,
-                              size_t xBufferLengthBytes,
-                              TickType_t xTicksToWait );
-

- *
- * Receives a discrete message from a message buffer.  Messages can be of
- * variable length and are copied out of the buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
- * xMessageBufferReceiveFromISR() to read from a message buffer from an
- * interrupt service routine (ISR).
- *
- * @param xMessageBuffer The handle of the message buffer from which a message
- * is being received.
- *
- * @param pvRxData A pointer to the buffer into which the received message is
- * to be copied.
- *
- * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
- * parameter.  This sets the maximum length of the message that can be received.
- * If xBufferLengthBytes is too small to hold the next message then the message
- * will be left in the message buffer and 0 will be returned.
- *
- * @param xTicksToWait The maximum amount of time the task should remain in the
- * Blocked state to wait for a message, should the message buffer be empty.
- * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
- * the message buffer is empty.  The block time is specified in tick periods, so
- * the absolute time it represents is dependent on the tick frequency.  The
- * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
- * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
- * cause the task to wait indefinitely (without timing out), provided
- * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
- * CPU time when they are in the Blocked state.
- *
- * @return The length, in bytes, of the message read from the message buffer, if
- * any.  If xMessageBufferReceive() times out before a message became available
- * then zero is returned.  If the length of the message is greater than
- * xBufferLengthBytes then the message will be left in the message buffer and
- * zero is returned.
- *
- * Example use:
-
-void vAFunction( MessageBuffer_t xMessageBuffer )
-{
-uint8_t ucRxData[ 20 ];
-size_t xReceivedBytes;
-const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
-
-    // Receive the next message from the message buffer.  Wait in the Blocked
-    // state (so not using any CPU processing time) for a maximum of 100ms for
-    // a message to become available.
-    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
-                                            ( void * ) ucRxData,
-                                            sizeof( ucRxData ),
-                                            xBlockTime );
-
-    if( xReceivedBytes > 0 )
-    {
-        // A ucRxData contains a message that is xReceivedBytes long.  Process
-        // the message here....
-    }
-}
-

- * \defgroup xMessageBufferReceive xMessageBufferReceive
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
-
-
-/**
- * message_buffer.h
- *
-
-size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
-                                     void *pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * An interrupt safe version of the API function that receives a discrete
- * message from a message buffer.  Messages can be of variable length and are
- * copied out of the buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
- * xMessageBufferReceiveFromISR() to read from a message buffer from an
- * interrupt service routine (ISR).
- *
- * @param xMessageBuffer The handle of the message buffer from which a message
- * is being received.
- *
- * @param pvRxData A pointer to the buffer into which the received message is
- * to be copied.
- *
- * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
- * parameter.  This sets the maximum length of the message that can be received.
- * If xBufferLengthBytes is too small to hold the next message then the message
- * will be left in the message buffer and 0 will be returned.
- *
- * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
- * have a task blocked on it waiting for space to become available.  Calling
- * xMessageBufferReceiveFromISR() can make space available, and so cause a task
- * that is waiting for space to leave the Blocked state.  If calling
- * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
- * the unblocked task has a priority higher than the currently executing task
- * (the task that was interrupted), then, internally,
- * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
- * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
- * context switch should be performed before the interrupt is exited.  That will
- * ensure the interrupt returns directly to the highest priority Ready state
- * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
- * passed into the function.  See the code example below for an example.
- *
- * @return The length, in bytes, of the message read from the message buffer, if
- * any.
- *
- * Example use:
-
-// A message buffer that has already been created.
-MessageBuffer_t xMessageBuffer;
-
-void vAnInterruptServiceRoutine( void )
-{
-uint8_t ucRxData[ 20 ];
-size_t xReceivedBytes;
-BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
-
-    // Receive the next message from the message buffer.
-    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
-                                                  ( void * ) ucRxData,
-                                                  sizeof( ucRxData ),
-                                                  &xHigherPriorityTaskWoken );
-
-    if( xReceivedBytes > 0 )
-    {
-        // A ucRxData contains a message that is xReceivedBytes long.  Process
-        // the message here....
-    }
-
-    // If xHigherPriorityTaskWoken was set to pdTRUE inside
-    // xMessageBufferReceiveFromISR() then a task that has a priority above the
-    // priority of the currently executing task was unblocked and a context
-    // switch should be performed to ensure the ISR returns to the unblocked
-    // task.  In most FreeRTOS ports this is done by simply passing
-    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
-    // variables value, and perform the context switch if necessary.  Check the
-    // documentation for the port in use for port specific instructions.
-    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-}
-

- * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
-
-/**
- * message_buffer.h
- *
-
-void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
-

- *
- * Deletes a message buffer that was previously created using a call to
- * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
- * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
- * then the allocated memory is freed.
- *
- * A message buffer handle must not be used after the message buffer has been
- * deleted.
- *
- * @param xMessageBuffer The handle of the message buffer to be deleted.
- *
- */
-#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
-
-/**
- * message_buffer.h
-
-BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
-

- *
- * Tests to see if a message buffer is full.  A message buffer is full if it
- * cannot accept any more messages, of any size, until space is made available
- * by a message being removed from the message buffer.
- *
- * @param xMessageBuffer The handle of the message buffer being queried.
- *
- * @return If the message buffer referenced by xMessageBuffer is full then
- * pdTRUE is returned.  Otherwise pdFALSE is returned.
- */
-#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
-
-/**
- * message_buffer.h
-
-BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
-

- *
- * Tests to see if a message buffer is empty (does not contain any messages).
- *
- * @param xMessageBuffer The handle of the message buffer being queried.
- *
- * @return If the message buffer referenced by xMessageBuffer is empty then
- * pdTRUE is returned.  Otherwise pdFALSE is returned.
- *
- */
-#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
-
-/**
- * message_buffer.h
-
-BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
-

- *
- * Resets a message buffer to its initial empty state, discarding any message it
- * contained.
- *
- * A message buffer can only be reset if there are no tasks blocked on it.
- *
- * @param xMessageBuffer The handle of the message buffer being reset.
- *
- * @return If the message buffer was reset then pdPASS is returned.  If the
- * message buffer could not be reset because either there was a task blocked on
- * the message queue to wait for space to become available, or to wait for a
- * a message to be available, then pdFAIL is returned.
- *
- * \defgroup xMessageBufferReset xMessageBufferReset
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
-
-
-/**
- * message_buffer.h
-
-size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
-

- * Returns the number of bytes of free space in the message buffer.
- *
- * @param xMessageBuffer The handle of the message buffer being queried.
- *
- * @return The number of bytes that can be written to the message buffer before
- * the message buffer would be full.  When a message is written to the message
- * buffer an additional sizeof( size_t ) bytes are also written to store the
- * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
- * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
- * of the largest message that can be written to the message buffer is 6 bytes.
- *
- * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
-#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
-
-/**
- * message_buffer.h
- 
- size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
- 

- * Returns the length (in bytes) of the next message in a message buffer.
- * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
- * passed into xMessageBufferReceive() was too small to hold the next message.
- *
- * @param xMessageBuffer The handle of the message buffer being queried.
- *
- * @return The length (in bytes) of the next message in the message buffer, or 0
- * if the message buffer is empty.
- *
- * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * message_buffer.h
- *
-
-BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * For advanced users only.
- *
- * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
- * data is sent to a message buffer or stream buffer.  If there was a task that
- * was blocked on the message or stream buffer waiting for data to arrive then
- * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
- * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
- * thing.  It is provided to enable application writers to implement their own
- * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
- *
- * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
- * additional information.
- *
- * @param xStreamBuffer The handle of the stream buffer to which data was
- * written.
- *
- * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
- * initialised to pdFALSE before it is passed into
- * xMessageBufferSendCompletedFromISR().  If calling
- * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
- * and the task has a priority above the priority of the currently running task,
- * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
- * context switch should be performed before exiting the ISR.
- *
- * @return If a task was removed from the Blocked state then pdTRUE is returned.
- * Otherwise pdFALSE is returned.
- *
- * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
- * \ingroup StreamBufferManagement
- */
-#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
-
-/**
- * message_buffer.h
- *
-
-BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * For advanced users only.
- *
- * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
- * data is read out of a message buffer or stream buffer.  If there was a task
- * that was blocked on the message or stream buffer waiting for data to arrive
- * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
- * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
- * does the same thing.  It is provided to enable application writers to
- * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
- * ANY OTHER TIME.
- *
- * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
- * additional information.
- *
- * @param xStreamBuffer The handle of the stream buffer from which data was
- * read.
- *
- * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
- * initialised to pdFALSE before it is passed into
- * xMessageBufferReceiveCompletedFromISR().  If calling
- * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
- * and the task has a priority above the priority of the currently running task,
- * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
- * context switch should be performed before exiting the ISR.
- *
- * @return If a task was removed from the Blocked state then pdTRUE is returned.
- * Otherwise pdFALSE is returned.
- *
- * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
- * \ingroup StreamBufferManagement
- */
-#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
-
-#if defined( __cplusplus )
-} /* extern "C" */
-#endif
-
-#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/mpu_prototypes.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/mpu_prototypes.h
deleted file mode 100644
index f0b3337..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/mpu_prototypes.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * When the MPU is used the standard (non MPU) API functions are mapped to
- * equivalents that start "MPU_", the prototypes for which are defined in this
- * header files.  This will cause the application code to call the MPU_ version
- * which wraps the non-MPU version with privilege promoting then demoting code,
- * so the kernel code always runs will full privileges.
- */
-
-
-#ifndef MPU_PROTOTYPES_H
-#define MPU_PROTOTYPES_H
-
-/* MPU versions of tasks.h API functions. */
-BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of queue.h API functions. */
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of timers.h API functions. */
-TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
-TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of event_group.h API functions. */
-EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
-EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of message/stream_buffer.h API functions. */
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
-StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
-StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
-
-
-
-#endif /* MPU_PROTOTYPES_H */
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/mpu_wrappers.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/mpu_wrappers.h
deleted file mode 100644
index 56d9c7e..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/mpu_wrappers.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef MPU_WRAPPERS_H
-#define MPU_WRAPPERS_H
-
-/* This file redefines API functions to be called through a wrapper macro, but
-only for ports that are using the MPU. */
-#ifdef portUSING_MPU_WRAPPERS
-
-	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
-	included from queue.c or task.c to prevent it from having an effect within
-	those files. */
-	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-		/*
-		 * Map standard (non MPU) API functions to equivalents that start
-		 * "MPU_".  This will cause the application code to call the MPU_
-		 * version, which wraps the non-MPU version with privilege promoting
-		 * then demoting code, so the kernel code always runs will full
-		 * privileges.
-		 */
-
-		/* Map standard tasks.h API functions to the MPU equivalents. */
-		#define xTaskCreate								MPU_xTaskCreate
-		#define xTaskCreateStatic						MPU_xTaskCreateStatic
-		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
-		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
-		#define vTaskDelete								MPU_vTaskDelete
-		#define vTaskDelay								MPU_vTaskDelay
-		#define vTaskDelayUntil							MPU_vTaskDelayUntil
-		#define xTaskAbortDelay							MPU_xTaskAbortDelay
-		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
-		#define eTaskGetState							MPU_eTaskGetState
-		#define vTaskGetInfo							MPU_vTaskGetInfo
-		#define vTaskPrioritySet						MPU_vTaskPrioritySet
-		#define vTaskSuspend							MPU_vTaskSuspend
-		#define vTaskResume								MPU_vTaskResume
-		#define vTaskSuspendAll							MPU_vTaskSuspendAll
-		#define xTaskResumeAll							MPU_xTaskResumeAll
-		#define xTaskGetTickCount						MPU_xTaskGetTickCount
-		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
-		#define pcTaskGetName							MPU_pcTaskGetName
-		#define xTaskGetHandle							MPU_xTaskGetHandle
-		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
-		#define uxTaskGetStackHighWaterMark2			MPU_uxTaskGetStackHighWaterMark2
-		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
-		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
-		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
-		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
-		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
-		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
-		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
-		#define vTaskList								MPU_vTaskList
-		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
-		#define xTaskGetIdleRunTimeCounter				MPU_xTaskGetIdleRunTimeCounter
-		#define xTaskGenericNotify						MPU_xTaskGenericNotify
-		#define xTaskNotifyWait							MPU_xTaskNotifyWait
-		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
-		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
-
-		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
-		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
-		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
-		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
-
-		/* Map standard queue.h API functions to the MPU equivalents. */
-		#define xQueueGenericSend						MPU_xQueueGenericSend
-		#define xQueueReceive							MPU_xQueueReceive
-		#define xQueuePeek								MPU_xQueuePeek
-		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
-		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
-		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
-		#define vQueueDelete							MPU_vQueueDelete
-		#define xQueueCreateMutex						MPU_xQueueCreateMutex
-		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
-		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
-		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
-		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
-		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
-		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
-		#define xQueueGenericCreate						MPU_xQueueGenericCreate
-		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
-		#define xQueueCreateSet							MPU_xQueueCreateSet
-		#define xQueueAddToSet							MPU_xQueueAddToSet
-		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
-		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
-		#define xQueueGenericReset						MPU_xQueueGenericReset
-
-		#if( configQUEUE_REGISTRY_SIZE > 0 )
-			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
-			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
-			#define pcQueueGetName							MPU_pcQueueGetName
-		#endif
-
-		/* Map standard timer.h API functions to the MPU equivalents. */
-		#define xTimerCreate							MPU_xTimerCreate
-		#define xTimerCreateStatic						MPU_xTimerCreateStatic
-		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
-		#define vTimerSetTimerID						MPU_vTimerSetTimerID
-		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
-		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
-		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
-		#define pcTimerGetName							MPU_pcTimerGetName
-		#define vTimerSetReloadMode						MPU_vTimerSetReloadMode
-		#define xTimerGetPeriod							MPU_xTimerGetPeriod
-		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
-		#define xTimerGenericCommand					MPU_xTimerGenericCommand
-
-		/* Map standard event_group.h API functions to the MPU equivalents. */
-		#define xEventGroupCreate						MPU_xEventGroupCreate
-		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
-		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
-		#define xEventGroupClearBits					MPU_xEventGroupClearBits
-		#define xEventGroupSetBits						MPU_xEventGroupSetBits
-		#define xEventGroupSync							MPU_xEventGroupSync
-		#define vEventGroupDelete						MPU_vEventGroupDelete
-
-		/* Map standard message/stream_buffer.h API functions to the MPU
-		equivalents. */
-		#define xStreamBufferSend						MPU_xStreamBufferSend
-		#define xStreamBufferReceive					MPU_xStreamBufferReceive
-		#define xStreamBufferNextMessageLengthBytes		MPU_xStreamBufferNextMessageLengthBytes
-		#define vStreamBufferDelete						MPU_vStreamBufferDelete
-		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
-		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
-		#define xStreamBufferReset						MPU_xStreamBufferReset
-		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
-		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
-		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
-		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
-		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
-
-
-		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
-		macro so applications can place data in privileged access sections
-		(useful when using statically allocated objects). */
-		#define PRIVILEGED_FUNCTION
-		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
-		#define FREERTOS_SYSTEM_CALL
-
-	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
-
-		/* Ensure API functions go in the privileged execution section. */
-		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
-		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
-		#define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
-
-	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
-
-#else /* portUSING_MPU_WRAPPERS */
-
-	#define PRIVILEGED_FUNCTION
-	#define PRIVILEGED_DATA
-	#define FREERTOS_SYSTEM_CALL
-	#define portUSING_MPU_WRAPPERS 0
-
-#endif /* portUSING_MPU_WRAPPERS */
-
-
-#endif /* MPU_WRAPPERS_H */
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/portable.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/portable.h
deleted file mode 100644
index a1bb449..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/portable.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Portable layer API.  Each function must be defined for each port.
- *----------------------------------------------------------*/
-
-#ifndef PORTABLE_H
-#define PORTABLE_H
-
-/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
-pre-processor definition was used to ensure the pre-processor found the correct
-portmacro.h file for the port being used.  That scheme was deprecated in favour
-of setting the compiler's include path such that it found the correct
-portmacro.h file - removing the need for the constant and allowing the
-portmacro.h file to be located anywhere in relation to the port being used.
-Purely for reasons of backward compatibility the old method is still valid, but
-to make it clear that new projects should not use it, support for the port
-specific constants has been moved into the deprecated_definitions.h header
-file. */
-#include "deprecated_definitions.h"
-
-/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
-did not result in a portmacro.h header file being included - and it should be
-included here.  In this case the path to the correct portmacro.h header file
-must be set in the compiler's include path. */
-#ifndef portENTER_CRITICAL
-	#include "portmacro.h"
-#endif
-
-#if portBYTE_ALIGNMENT == 32
-	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
-#endif
-
-#if portBYTE_ALIGNMENT == 16
-	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
-#endif
-
-#if portBYTE_ALIGNMENT == 8
-	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
-#endif
-
-#if portBYTE_ALIGNMENT == 4
-	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
-#endif
-
-#if portBYTE_ALIGNMENT == 2
-	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
-#endif
-
-#if portBYTE_ALIGNMENT == 1
-	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
-#endif
-
-#ifndef portBYTE_ALIGNMENT_MASK
-	#error "Invalid portBYTE_ALIGNMENT definition"
-#endif
-
-#ifndef portNUM_CONFIGURABLE_REGIONS
-	#define portNUM_CONFIGURABLE_REGIONS 1
-#endif
-
-#ifndef portHAS_STACK_OVERFLOW_CHECKING
-	#define portHAS_STACK_OVERFLOW_CHECKING 0
-#endif
-
-#ifndef portARCH_NAME
-	#define portARCH_NAME NULL
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "mpu_wrappers.h"
-
-/*
- * Setup the stack of a new task so it is ready to be placed under the
- * scheduler control.  The registers have to be placed on the stack in
- * the order that the port expects to find them.
- *
- */
-#if( portUSING_MPU_WRAPPERS == 1 )
-	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
-	#else
-		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
-	#endif
-#else
-	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
-	#else
-		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
-	#endif
-#endif
-
-/* Used by heap_5.c. */
-typedef struct HeapRegion
-{
-	uint8_t *pucStartAddress;
-	size_t xSizeInBytes;
-} HeapRegion_t;
-
-/*
- * Used to define multiple heap regions for use by heap_5.c.  This function
- * must be called before any calls to pvPortMalloc() - not creating a task,
- * queue, semaphore, mutex, software timer, event group, etc. will result in
- * pvPortMalloc being called.
- *
- * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
- * defines a region of memory that can be used as the heap.  The array is
- * terminated by a HeapRegions_t structure that has a size of 0.  The region
- * with the lowest start address must appear first in the array.
- */
-void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
-
-
-/*
- * Map to the memory management routines required for the port.
- */
-void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
-void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
-void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
-size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
-size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Setup the hardware ready for the scheduler to take control.  This generally
- * sets up a tick interrupt and sets timers for the correct tick frequency.
- */
-BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
- * the hardware is left in its original condition after the scheduler stops
- * executing.
- */
-void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
-
-/*
- * The structures and methods of manipulating the MPU are contained within the
- * port layer.
- *
- * Fills the xMPUSettings structure with the memory region information
- * contained in xRegions.
- */
-#if( portUSING_MPU_WRAPPERS == 1 )
-	struct xMEMORY_REGION;
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTABLE_H */
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/projdefs.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/projdefs.h
deleted file mode 100644
index dbcf9bb..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/projdefs.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PROJDEFS_H
-#define PROJDEFS_H
-
-/*
- * Defines the prototype to which task functions must conform.  Defined in this
- * file to ensure the type is known before portable.h is included.
- */
-typedef void (*TaskFunction_t)( void * );
-
-/* Converts a time in milliseconds to a time in ticks.  This macro can be
-overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
-definition here is not suitable for your application. */
-#ifndef pdMS_TO_TICKS
-	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
-#endif
-
-#define pdFALSE			( ( BaseType_t ) 0 )
-#define pdTRUE			( ( BaseType_t ) 1 )
-
-#define pdPASS			( pdTRUE )
-#define pdFAIL			( pdFALSE )
-#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
-#define errQUEUE_FULL	( ( BaseType_t ) 0 )
-
-/* FreeRTOS error definitions. */
-#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
-#define errQUEUE_BLOCKED						( -4 )
-#define errQUEUE_YIELD							( -5 )
-
-/* Macros used for basic data corruption checks. */
-#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
-	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
-#endif
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
-#else
-	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
-#endif
-
-/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
-itself. */
-#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
-#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
-#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
-#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
-#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
-#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
-#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
-#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
-#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
-#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
-#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
-#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
-#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
-#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
-#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
-#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
-#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
-#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
-#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
-#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
-#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
-#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
-#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
-#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
-#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
-#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
-#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
-#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
-#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
-#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
-#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
-#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
-#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
-#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
-#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
-#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
-#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
-#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
-#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
-#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
-
-/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
-itself. */
-#define pdFREERTOS_LITTLE_ENDIAN		0
-#define pdFREERTOS_BIG_ENDIAN			1
-
-/* Re-defining endian values for generic naming. */
-#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
-#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
-
-
-#endif /* PROJDEFS_H */
-
-
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/queue.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/queue.h
deleted file mode 100644
index 5072c45..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/queue.h
+++ /dev/null
@@ -1,1655 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef QUEUE_H
-#define QUEUE_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "task.h"
-
-/**
- * Type by which queues are referenced.  For example, a call to xQueueCreate()
- * returns an QueueHandle_t variable that can then be used as a parameter to
- * xQueueSend(), xQueueReceive(), etc.
- */
-struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
-typedef struct QueueDefinition * QueueHandle_t;
-
-/**
- * Type by which queue sets are referenced.  For example, a call to
- * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
- * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
- */
-typedef struct QueueDefinition * QueueSetHandle_t;
-
-/**
- * Queue sets can contain both queues and semaphores, so the
- * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
- * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
- */
-typedef struct QueueDefinition * QueueSetMemberHandle_t;
-
-/* For internal use only. */
-#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
-#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
-#define queueOVERWRITE			( ( BaseType_t ) 2 )
-
-/* For internal use only.  These definitions *must* match those in queue.c. */
-#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
-#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
-#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
-#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
-#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
-#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
-
-/**
- * queue. h
- * 
- QueueHandle_t xQueueCreate(
-							  UBaseType_t uxQueueLength,
-							  UBaseType_t uxItemSize
-						  );
- * 

- *
- * Creates a new queue instance, and returns a handle by which the new queue
- * can be referenced.
- *
- * Internally, within the FreeRTOS implementation, queues use two blocks of
- * memory.  The first block is used to hold the queue's data structures.  The
- * second block is used to hold items placed into the queue.  If a queue is
- * created using xQueueCreate() then both blocks of memory are automatically
- * dynamically allocated inside the xQueueCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a queue is created using
- * xQueueCreateStatic() then the application writer must provide the memory that
- * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
- * be created without using any dynamic memory allocation.
- *
- * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
- *
- * @param uxQueueLength The maximum number of items that the queue can contain.
- *
- * @param uxItemSize The number of bytes each item in the queue will require.
- * Items are queued by copy, not by reference, so this is the number of bytes
- * that will be copied for each posted item.  Each item on the queue must be
- * the same size.
- *
- * @return If the queue is successfully create then a handle to the newly
- * created queue is returned.  If the queue cannot be created then 0 is
- * returned.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- };
-
- void vATask( void *pvParameters )
- {
- QueueHandle_t xQueue1, xQueue2;
-
-	// Create a queue capable of containing 10 uint32_t values.
-	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
-	if( xQueue1 == 0 )
-	{
-		// Queue was not created and must not be used.
-	}
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-	if( xQueue2 == 0 )
-	{
-		// Queue was not created and must not be used.
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueCreate xQueueCreate
- * \ingroup QueueManagement
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
-#endif
-
-/**
- * queue. h
- * 
- QueueHandle_t xQueueCreateStatic(
-							  UBaseType_t uxQueueLength,
-							  UBaseType_t uxItemSize,
-							  uint8_t *pucQueueStorageBuffer,
-							  StaticQueue_t *pxQueueBuffer
-						  );
- * 

- *
- * Creates a new queue instance, and returns a handle by which the new queue
- * can be referenced.
- *
- * Internally, within the FreeRTOS implementation, queues use two blocks of
- * memory.  The first block is used to hold the queue's data structures.  The
- * second block is used to hold items placed into the queue.  If a queue is
- * created using xQueueCreate() then both blocks of memory are automatically
- * dynamically allocated inside the xQueueCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a queue is created using
- * xQueueCreateStatic() then the application writer must provide the memory that
- * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
- * be created without using any dynamic memory allocation.
- *
- * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
- *
- * @param uxQueueLength The maximum number of items that the queue can contain.
- *
- * @param uxItemSize The number of bytes each item in the queue will require.
- * Items are queued by copy, not by reference, so this is the number of bytes
- * that will be copied for each posted item.  Each item on the queue must be
- * the same size.
- *
- * @param pucQueueStorageBuffer If uxItemSize is not zero then
- * pucQueueStorageBuffer must point to a uint8_t array that is at least large
- * enough to hold the maximum number of items that can be in the queue at any
- * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
- * zero then pucQueueStorageBuffer can be NULL.
- *
- * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
- * will be used to hold the queue's data structure.
- *
- * @return If the queue is created then a handle to the created queue is
- * returned.  If pxQueueBuffer is NULL then NULL is returned.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- };
-
- #define QUEUE_LENGTH 10
- #define ITEM_SIZE sizeof( uint32_t )
-
- // xQueueBuffer will hold the queue structure.
- StaticQueue_t xQueueBuffer;
-
- // ucQueueStorage will hold the items posted to the queue.  Must be at least
- // [(queue length) * ( queue item size)] bytes long.
- uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
-
- void vATask( void *pvParameters )
- {
- QueueHandle_t xQueue1;
-
-	// Create a queue capable of containing 10 uint32_t values.
-	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
-							ITEM_SIZE	  // The size of each item in the queue
-							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
-							&xQueueBuffer ); // The buffer that will hold the queue structure.
-
-	// The queue is guaranteed to be created successfully as no dynamic memory
-	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueCreateStatic xQueueCreateStatic
- * \ingroup QueueManagement
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * queue. h
- * 
- BaseType_t xQueueSendToToFront(
-								   QueueHandle_t	xQueue,
-								   const void		*pvItemToQueue,
-								   TickType_t		xTicksToWait
-							   );
- * 

- *
- * Post an item to the front of a queue.  The item is queued by copy, not by
- * reference.  This function must not be called from an interrupt service
- * routine.  See xQueueSendFromISR () for an alternative which may be used
- * in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the
- * queue is full.  The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- uint32_t ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- QueueHandle_t xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 uint32_t values.
-	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-	// ...
-
-	if( xQueue1 != 0 )
-	{
-		// Send an uint32_t.  Wait for 10 ticks for space to become
-		// available if necessary.
-		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
-		{
-			// Failed to post the message, even after 10 ticks.
-		}
-	}
-
-	if( xQueue2 != 0 )
-	{
-		// Send a pointer to a struct AMessage object.  Don't block if the
-		// queue is already full.
-		pxMessage = & xMessage;
-		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueSend xQueueSend
- * \ingroup QueueManagement
- */
-#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
-
-/**
- * queue. h
- * 
- BaseType_t xQueueSendToBack(
-								   QueueHandle_t	xQueue,
-								   const void		*pvItemToQueue,
-								   TickType_t		xTicksToWait
-							   );
- * 

- *
- * This is a macro that calls xQueueGenericSend().
- *
- * Post an item to the back of a queue.  The item is queued by copy, not by
- * reference.  This function must not be called from an interrupt service
- * routine.  See xQueueSendFromISR () for an alternative which may be used
- * in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the queue
- * is full.  The  time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- uint32_t ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- QueueHandle_t xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 uint32_t values.
-	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-	// ...
-
-	if( xQueue1 != 0 )
-	{
-		// Send an uint32_t.  Wait for 10 ticks for space to become
-		// available if necessary.
-		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
-		{
-			// Failed to post the message, even after 10 ticks.
-		}
-	}
-
-	if( xQueue2 != 0 )
-	{
-		// Send a pointer to a struct AMessage object.  Don't block if the
-		// queue is already full.
-		pxMessage = & xMessage;
-		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueSend xQueueSend
- * \ingroup QueueManagement
- */
-#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
-
-/**
- * queue. h
- * 
- BaseType_t xQueueSend(
-							  QueueHandle_t xQueue,
-							  const void * pvItemToQueue,
-							  TickType_t xTicksToWait
-						 );
- * 

- *
- * This is a macro that calls xQueueGenericSend().  It is included for
- * backward compatibility with versions of FreeRTOS.org that did not
- * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
- * equivalent to xQueueSendToBack().
- *
- * Post an item on a queue.  The item is queued by copy, not by reference.
- * This function must not be called from an interrupt service routine.
- * See xQueueSendFromISR () for an alternative which may be used in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the
- * queue is full.  The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- uint32_t ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- QueueHandle_t xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 uint32_t values.
-	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-	// ...
-
-	if( xQueue1 != 0 )
-	{
-		// Send an uint32_t.  Wait for 10 ticks for space to become
-		// available if necessary.
-		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
-		{
-			// Failed to post the message, even after 10 ticks.
-		}
-	}
-
-	if( xQueue2 != 0 )
-	{
-		// Send a pointer to a struct AMessage object.  Don't block if the
-		// queue is already full.
-		pxMessage = & xMessage;
-		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueSend xQueueSend
- * \ingroup QueueManagement
- */
-#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
-
-/**
- * queue. h
- * 
- BaseType_t xQueueOverwrite(
-							  QueueHandle_t xQueue,
-							  const void * pvItemToQueue
-						 );
- * 

- *
- * Only for use with queues that have a length of one - so the queue is either
- * empty or full.
- *
- * Post an item on a queue.  If the queue is already full then overwrite the
- * value held in the queue.  The item is queued by copy, not by reference.
- *
- * This function must not be called from an interrupt service routine.
- * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
- *
- * @param xQueue The handle of the queue to which the data is being sent.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
- * therefore has the same return values as xQueueSendToFront().  However, pdPASS
- * is the only value that can be returned because xQueueOverwrite() will write
- * to the queue even when the queue is already full.
- *
- * Example usage:
-   
-
- void vFunction( void *pvParameters )
- {
- QueueHandle_t xQueue;
- uint32_t ulVarToSend, ulValReceived;
-
-	// Create a queue to hold one uint32_t value.  It is strongly
-	// recommended *not* to use xQueueOverwrite() on queues that can
-	// contain more than one value, and doing so will trigger an assertion
-	// if configASSERT() is defined.
-	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
-
-	// Write the value 10 to the queue using xQueueOverwrite().
-	ulVarToSend = 10;
-	xQueueOverwrite( xQueue, &ulVarToSend );
-
-	// Peeking the queue should now return 10, but leave the value 10 in
-	// the queue.  A block time of zero is used as it is known that the
-	// queue holds a value.
-	ulValReceived = 0;
-	xQueuePeek( xQueue, &ulValReceived, 0 );
-
-	if( ulValReceived != 10 )
-	{
-		// Error unless the item was removed by a different task.
-	}
-
-	// The queue is still full.  Use xQueueOverwrite() to overwrite the
-	// value held in the queue with 100.
-	ulVarToSend = 100;
-	xQueueOverwrite( xQueue, &ulVarToSend );
-
-	// This time read from the queue, leaving the queue empty once more.
-	// A block time of 0 is used again.
-	xQueueReceive( xQueue, &ulValReceived, 0 );
-
-	// The value read should be the last value written, even though the
-	// queue was already full when the value was written.
-	if( ulValReceived != 100 )
-	{
-		// Error!
-	}
-
-	// ...
-}
- 

- * \defgroup xQueueOverwrite xQueueOverwrite
- * \ingroup QueueManagement
- */
-#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
-
-
-/**
- * queue. h
- * 
- BaseType_t xQueueGenericSend(
-									QueueHandle_t xQueue,
-									const void * pvItemToQueue,
-									TickType_t xTicksToWait
-									BaseType_t xCopyPosition
-								);
- * 

- *
- * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
- * xQueueSendToBack() are used in place of calling this function directly.
- *
- * Post an item on a queue.  The item is queued by copy, not by reference.
- * This function must not be called from an interrupt service routine.
- * See xQueueSendFromISR () for an alternative which may be used in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the
- * queue is full.  The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
- * item at the back of the queue, or queueSEND_TO_FRONT to place the item
- * at the front of the queue (for high priority messages).
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- uint32_t ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- QueueHandle_t xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 uint32_t values.
-	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-	// ...
-
-	if( xQueue1 != 0 )
-	{
-		// Send an uint32_t.  Wait for 10 ticks for space to become
-		// available if necessary.
-		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
-		{
-			// Failed to post the message, even after 10 ticks.
-		}
-	}
-
-	if( xQueue2 != 0 )
-	{
-		// Send a pointer to a struct AMessage object.  Don't block if the
-		// queue is already full.
-		pxMessage = & xMessage;
-		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueSend xQueueSend
- * \ingroup QueueManagement
- */
-BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- BaseType_t xQueuePeek(
-							 QueueHandle_t xQueue,
-							 void * const pvBuffer,
-							 TickType_t xTicksToWait
-						 );

- *
- * Receive an item from a queue without removing the item from the queue.
- * The item is received by copy so a buffer of adequate size must be
- * provided.  The number of bytes copied into the buffer was defined when
- * the queue was created.
- *
- * Successfully received items remain on the queue so will be returned again
- * by the next call, or a call to xQueueReceive().
- *
- * This macro must not be used in an interrupt service routine.  See
- * xQueuePeekFromISR() for an alternative that can be called from an interrupt
- * service routine.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for an item to receive should the queue be empty at the time
- * of the call.	 The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
- * is empty.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- QueueHandle_t xQueue;
-
- // Task to create a queue and post a value.
- void vATask( void *pvParameters )
- {
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
-	if( xQueue == 0 )
-	{
-		// Failed to create the queue.
-	}
-
-	// ...
-
-	// Send a pointer to a struct AMessage object.  Don't block if the
-	// queue is already full.
-	pxMessage = & xMessage;
-	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
-
-	// ... Rest of task code.
- }
-
- // Task to peek the data from the queue.
- void vADifferentTask( void *pvParameters )
- {
- struct AMessage *pxRxedMessage;
-
-	if( xQueue != 0 )
-	{
-		// Peek a message on the created queue.  Block for 10 ticks if a
-		// message is not immediately available.
-		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
-		{
-			// pcRxedMessage now points to the struct AMessage variable posted
-			// by vATask, but the item still remains on the queue.
-		}
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueuePeek xQueuePeek
- * \ingroup QueueManagement
- */
-BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- BaseType_t xQueuePeekFromISR(
-									QueueHandle_t xQueue,
-									void *pvBuffer,
-								);

- *
- * A version of xQueuePeek() that can be called from an interrupt service
- * routine (ISR).
- *
- * Receive an item from a queue without removing the item from the queue.
- * The item is received by copy so a buffer of adequate size must be
- * provided.  The number of bytes copied into the buffer was defined when
- * the queue was created.
- *
- * Successfully received items remain on the queue so will be returned again
- * by the next call, or a call to xQueueReceive().
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * \defgroup xQueuePeekFromISR xQueuePeekFromISR
- * \ingroup QueueManagement
- */
-BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- BaseType_t xQueueReceive(
-								 QueueHandle_t xQueue,
-								 void *pvBuffer,
-								 TickType_t xTicksToWait
-							);

- *
- * Receive an item from a queue.  The item is received by copy so a buffer of
- * adequate size must be provided.  The number of bytes copied into the buffer
- * was defined when the queue was created.
- *
- * Successfully received items are removed from the queue.
- *
- * This function must not be used in an interrupt service routine.  See
- * xQueueReceiveFromISR for an alternative that can.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for an item to receive should the queue be empty at the time
- * of the call.	 xQueueReceive() will return immediately if xTicksToWait
- * is zero and the queue is empty.  The time is defined in tick periods so the
- * constant portTICK_PERIOD_MS should be used to convert to real time if this is
- * required.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- QueueHandle_t xQueue;
-
- // Task to create a queue and post a value.
- void vATask( void *pvParameters )
- {
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
-	if( xQueue == 0 )
-	{
-		// Failed to create the queue.
-	}
-
-	// ...
-
-	// Send a pointer to a struct AMessage object.  Don't block if the
-	// queue is already full.
-	pxMessage = & xMessage;
-	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
-
-	// ... Rest of task code.
- }
-
- // Task to receive from the queue.
- void vADifferentTask( void *pvParameters )
- {
- struct AMessage *pxRxedMessage;
-
-	if( xQueue != 0 )
-	{
-		// Receive a message on the created queue.  Block for 10 ticks if a
-		// message is not immediately available.
-		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
-		{
-			// pcRxedMessage now points to the struct AMessage variable posted
-			// by vATask.
-		}
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueReceive xQueueReceive
- * \ingroup QueueManagement
- */
-BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );

- *
- * Return the number of messages stored in a queue.
- *
- * @param xQueue A handle to the queue being queried.
- *
- * @return The number of messages available in the queue.
- *
- * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
- * \ingroup QueueManagement
- */
-UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );

- *
- * Return the number of free spaces available in a queue.  This is equal to the
- * number of items that can be sent to the queue before the queue becomes full
- * if no items are removed.
- *
- * @param xQueue A handle to the queue being queried.
- *
- * @return The number of spaces available in the queue.
- *
- * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
- * \ingroup QueueManagement
- */
-UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
void vQueueDelete( QueueHandle_t xQueue );

- *
- * Delete a queue - freeing all the memory allocated for storing of items
- * placed on the queue.
- *
- * @param xQueue A handle to the queue to be deleted.
- *
- * \defgroup vQueueDelete vQueueDelete
- * \ingroup QueueManagement
- */
-void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- BaseType_t xQueueSendToFrontFromISR(
-										 QueueHandle_t xQueue,
-										 const void *pvItemToQueue,
-										 BaseType_t *pxHigherPriorityTaskWoken
-									  );
- 

- *
- * This is a macro that calls xQueueGenericSendFromISR().
- *
- * Post an item to the front of a queue.  It is safe to use this macro from
- * within an interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
-   
- void vBufferISR( void )
- {
- char cIn;
- BaseType_t xHigherPrioritTaskWoken;
-
-	// We have not woken a task at the start of the ISR.
-	xHigherPriorityTaskWoken = pdFALSE;
-
-	// Loop until the buffer is empty.
-	do
-	{
-		// Obtain a byte from the buffer.
-		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
-
-		// Post the byte.
-		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
-
-	} while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-	// Now the buffer is empty we can switch context if necessary.
-	if( xHigherPriorityTaskWoken )
-	{
-		taskYIELD ();
-	}
- }
- 

- *
- * \defgroup xQueueSendFromISR xQueueSendFromISR
- * \ingroup QueueManagement
- */
-#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
-
-
-/**
- * queue. h
- * 
- BaseType_t xQueueSendToBackFromISR(
-										 QueueHandle_t xQueue,
-										 const void *pvItemToQueue,
-										 BaseType_t *pxHigherPriorityTaskWoken
-									  );
- 

- *
- * This is a macro that calls xQueueGenericSendFromISR().
- *
- * Post an item to the back of a queue.  It is safe to use this macro from
- * within an interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
-   
- void vBufferISR( void )
- {
- char cIn;
- BaseType_t xHigherPriorityTaskWoken;
-
-	// We have not woken a task at the start of the ISR.
-	xHigherPriorityTaskWoken = pdFALSE;
-
-	// Loop until the buffer is empty.
-	do
-	{
-		// Obtain a byte from the buffer.
-		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
-
-		// Post the byte.
-		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
-
-	} while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-	// Now the buffer is empty we can switch context if necessary.
-	if( xHigherPriorityTaskWoken )
-	{
-		taskYIELD ();
-	}
- }
- 

- *
- * \defgroup xQueueSendFromISR xQueueSendFromISR
- * \ingroup QueueManagement
- */
-#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
-
-/**
- * queue. h
- * 
- BaseType_t xQueueOverwriteFromISR(
-							  QueueHandle_t xQueue,
-							  const void * pvItemToQueue,
-							  BaseType_t *pxHigherPriorityTaskWoken
-						 );
- * 

- *
- * A version of xQueueOverwrite() that can be used in an interrupt service
- * routine (ISR).
- *
- * Only for use with queues that can hold a single item - so the queue is either
- * empty or full.
- *
- * Post an item on a queue.  If the queue is already full then overwrite the
- * value held in the queue.  The item is queued by copy, not by reference.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return xQueueOverwriteFromISR() is a macro that calls
- * xQueueGenericSendFromISR(), and therefore has the same return values as
- * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
- * returned because xQueueOverwriteFromISR() will write to the queue even when
- * the queue is already full.
- *
- * Example usage:
-   
-
- QueueHandle_t xQueue;
-
- void vFunction( void *pvParameters )
- {
- 	// Create a queue to hold one uint32_t value.  It is strongly
-	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
-	// contain more than one value, and doing so will trigger an assertion
-	// if configASSERT() is defined.
-	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
-}
-
-void vAnInterruptHandler( void )
-{
-// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
-BaseType_t xHigherPriorityTaskWoken = pdFALSE;
-uint32_t ulVarToSend, ulValReceived;
-
-	// Write the value 10 to the queue using xQueueOverwriteFromISR().
-	ulVarToSend = 10;
-	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
-
-	// The queue is full, but calling xQueueOverwriteFromISR() again will still
-	// pass because the value held in the queue will be overwritten with the
-	// new value.
-	ulVarToSend = 100;
-	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
-
-	// Reading from the queue will now return 100.
-
-	// ...
-
-	if( xHigherPrioritytaskWoken == pdTRUE )
-	{
-		// Writing to the queue caused a task to unblock and the unblocked task
-		// has a priority higher than or equal to the priority of the currently
-		// executing task (the task this interrupt interrupted).  Perform a context
-		// switch so this interrupt returns directly to the unblocked task.
-		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
-	}
-}
- 

- * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
- * \ingroup QueueManagement
- */
-#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
-
-/**
- * queue. h
- * 
- BaseType_t xQueueSendFromISR(
-									 QueueHandle_t xQueue,
-									 const void *pvItemToQueue,
-									 BaseType_t *pxHigherPriorityTaskWoken
-								);
- 

- *
- * This is a macro that calls xQueueGenericSendFromISR().  It is included
- * for backward compatibility with versions of FreeRTOS.org that did not
- * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
- * macros.
- *
- * Post an item to the back of a queue.  It is safe to use this function from
- * within an interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
-   
- void vBufferISR( void )
- {
- char cIn;
- BaseType_t xHigherPriorityTaskWoken;
-
-	// We have not woken a task at the start of the ISR.
-	xHigherPriorityTaskWoken = pdFALSE;
-
-	// Loop until the buffer is empty.
-	do
-	{
-		// Obtain a byte from the buffer.
-		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
-
-		// Post the byte.
-		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
-
-	} while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-	// Now the buffer is empty we can switch context if necessary.
-	if( xHigherPriorityTaskWoken )
-	{
-		// Actual macro used here is port specific.
-		portYIELD_FROM_ISR ();
-	}
- }
- 

- *
- * \defgroup xQueueSendFromISR xQueueSendFromISR
- * \ingroup QueueManagement
- */
-#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
-
-/**
- * queue. h
- * 
- BaseType_t xQueueGenericSendFromISR(
-										   QueueHandle_t		xQueue,
-										   const	void	*pvItemToQueue,
-										   BaseType_t	*pxHigherPriorityTaskWoken,
-										   BaseType_t	xCopyPosition
-									   );
- 

- *
- * It is preferred that the macros xQueueSendFromISR(),
- * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
- * of calling this function directly.  xQueueGiveFromISR() is an
- * equivalent for use by semaphores that don't actually copy any data.
- *
- * Post an item on a queue.  It is safe to use this function from within an
- * interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
- * item at the back of the queue, or queueSEND_TO_FRONT to place the item
- * at the front of the queue (for high priority messages).
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
-   
- void vBufferISR( void )
- {
- char cIn;
- BaseType_t xHigherPriorityTaskWokenByPost;
-
-	// We have not woken a task at the start of the ISR.
-	xHigherPriorityTaskWokenByPost = pdFALSE;
-
-	// Loop until the buffer is empty.
-	do
-	{
-		// Obtain a byte from the buffer.
-		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
-
-		// Post each byte.
-		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
-
-	} while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-	// Now the buffer is empty we can switch context if necessary.  Note that the
-	// name of the yield function required is port specific.
-	if( xHigherPriorityTaskWokenByPost )
-	{
-		taskYIELD_YIELD_FROM_ISR();
-	}
- }
- 

- *
- * \defgroup xQueueSendFromISR xQueueSendFromISR
- * \ingroup QueueManagement
- */
-BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- BaseType_t xQueueReceiveFromISR(
-									   QueueHandle_t	xQueue,
-									   void	*pvBuffer,
-									   BaseType_t *pxTaskWoken
-								   );
- * 

- *
- * Receive an item from a queue.  It is safe to use this function from within an
- * interrupt service routine.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param pxTaskWoken A task may be blocked waiting for space to become
- * available on the queue.  If xQueueReceiveFromISR causes such a task to
- * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
- * remain unchanged.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
-   
-
- QueueHandle_t xQueue;
-
- // Function to create a queue and post some values.
- void vAFunction( void *pvParameters )
- {
- char cValueToPost;
- const TickType_t xTicksToWait = ( TickType_t )0xff;
-
-	// Create a queue capable of containing 10 characters.
-	xQueue = xQueueCreate( 10, sizeof( char ) );
-	if( xQueue == 0 )
-	{
-		// Failed to create the queue.
-	}
-
-	// ...
-
-	// Post some characters that will be used within an ISR.  If the queue
-	// is full then this task will block for xTicksToWait ticks.
-	cValueToPost = 'a';
-	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
-	cValueToPost = 'b';
-	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
-
-	// ... keep posting characters ... this task may block when the queue
-	// becomes full.
-
-	cValueToPost = 'c';
-	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
- }
-
- // ISR that outputs all the characters received on the queue.
- void vISR_Routine( void )
- {
- BaseType_t xTaskWokenByReceive = pdFALSE;
- char cRxedChar;
-
-	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
-	{
-		// A character was received.  Output the character now.
-		vOutputCharacter( cRxedChar );
-
-		// If removing the character from the queue woke the task that was
-		// posting onto the queue cTaskWokenByReceive will have been set to
-		// pdTRUE.  No matter how many times this loop iterates only one
-		// task will be woken.
-	}
-
-	if( cTaskWokenByPost != ( char ) pdFALSE;
-	{
-		taskYIELD ();
-	}
- }
- 

- * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
- * \ingroup QueueManagement
- */
-BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/*
- * Utilities to query queues that are safe to use from an ISR.  These utilities
- * should be used only from witin an ISR, or within a critical section.
- */
-BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * The functions defined above are for passing data to and from tasks.  The
- * functions below are the equivalents for passing data to and from
- * co-routines.
- *
- * These functions are called from the co-routine macro implementation and
- * should not be called directly from application code.  Instead use the macro
- * wrappers defined within croutine.h.
- */
-BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
-BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
-BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
-BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
-
-/*
- * For internal use only.  Use xSemaphoreCreateMutex(),
- * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
- * these functions directly.
- */
-QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
-TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
-
-/*
- * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
- * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
- */
-BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
-
-/*
- * Reset a queue back to its original empty state.  The return value is now
- * obsolete and is always set to pdPASS.
- */
-#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
-
-/*
- * The registry is provided as a means for kernel aware debuggers to
- * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
- * a queue, semaphore or mutex handle to the registry if you want the handle
- * to be available to a kernel aware debugger.  If you are not using a kernel
- * aware debugger then this function can be ignored.
- *
- * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
- * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
- * within FreeRTOSConfig.h for the registry to be available.  Its value
- * does not effect the number of queues, semaphores and mutexes that can be
- * created - just the number that the registry can hold.
- *
- * @param xQueue The handle of the queue being added to the registry.  This
- * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
- * handles can also be passed in here.
- *
- * @param pcName The name to be associated with the handle.  This is the
- * name that the kernel aware debugger will display.  The queue registry only
- * stores a pointer to the string - so the string must be persistent (global or
- * preferably in ROM/Flash), not on the stack.
- */
-#if( configQUEUE_REGISTRY_SIZE > 0 )
-	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-#endif
-
-/*
- * The registry is provided as a means for kernel aware debuggers to
- * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
- * a queue, semaphore or mutex handle to the registry if you want the handle
- * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
- * remove the queue, semaphore or mutex from the register.  If you are not using
- * a kernel aware debugger then this function can be ignored.
- *
- * @param xQueue The handle of the queue being removed from the registry.
- */
-#if( configQUEUE_REGISTRY_SIZE > 0 )
-	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-#endif
-
-/*
- * The queue registry is provided as a means for kernel aware debuggers to
- * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
- * up and return the name of a queue in the queue registry from the queue's
- * handle.
- *
- * @param xQueue The handle of the queue the name of which will be returned.
- * @return If the queue is in the registry then a pointer to the name of the
- * queue is returned.  If the queue is not in the registry then NULL is
- * returned.
- */
-#if( configQUEUE_REGISTRY_SIZE > 0 )
-	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-#endif
-
-/*
- * Generic version of the function used to creaet a queue using dynamic memory
- * allocation.  This is called by other functions and macros that create other
- * RTOS objects that use the queue structure as their base.
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-#endif
-
-/*
- * Generic version of the function used to creaet a queue using dynamic memory
- * allocation.  This is called by other functions and macros that create other
- * RTOS objects that use the queue structure as their base.
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-#endif
-
-/*
- * Queue sets provide a mechanism to allow a task to block (pend) on a read
- * operation from multiple queues or semaphores simultaneously.
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * A queue set must be explicitly created using a call to xQueueCreateSet()
- * before it can be used.  Once created, standard FreeRTOS queues and semaphores
- * can be added to the set using calls to xQueueAddToSet().
- * xQueueSelectFromSet() is then used to determine which, if any, of the queues
- * or semaphores contained in the set is in a state where a queue read or
- * semaphore take operation would be successful.
- *
- * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
- * for reasons why queue sets are very rarely needed in practice as there are
- * simpler methods of blocking on multiple objects.
- *
- * Note 2:  Blocking on a queue set that contains a mutex will not cause the
- * mutex holder to inherit the priority of the blocked task.
- *
- * Note 3:  An additional 4 bytes of RAM is required for each space in a every
- * queue added to a queue set.  Therefore counting semaphores that have a high
- * maximum count value should not be added to a queue set.
- *
- * Note 4:  A receive (in the case of a queue) or take (in the case of a
- * semaphore) operation must not be performed on a member of a queue set unless
- * a call to xQueueSelectFromSet() has first returned a handle to that set member.
- *
- * @param uxEventQueueLength Queue sets store events that occur on
- * the queues and semaphores contained in the set.  uxEventQueueLength specifies
- * the maximum number of events that can be queued at once.  To be absolutely
- * certain that events are not lost uxEventQueueLength should be set to the
- * total sum of the length of the queues added to the set, where binary
- * semaphores and mutexes have a length of 1, and counting semaphores have a
- * length set by their maximum count value.  Examples:
- *  + If a queue set is to hold a queue of length 5, another queue of length 12,
- *    and a binary semaphore, then uxEventQueueLength should be set to
- *    (5 + 12 + 1), or 18.
- *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
- *    should be set to (1 + 1 + 1 ), or 3.
- *  + If a queue set is to hold a counting semaphore that has a maximum count of
- *    5, and a counting semaphore that has a maximum count of 3, then
- *    uxEventQueueLength should be set to (5 + 3), or 8.
- *
- * @return If the queue set is created successfully then a handle to the created
- * queue set is returned.  Otherwise NULL is returned.
- */
-QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
-
-/*
- * Adds a queue or semaphore to a queue set that was previously created by a
- * call to xQueueCreateSet().
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * Note 1:  A receive (in the case of a queue) or take (in the case of a
- * semaphore) operation must not be performed on a member of a queue set unless
- * a call to xQueueSelectFromSet() has first returned a handle to that set member.
- *
- * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
- * the queue set (cast to an QueueSetMemberHandle_t type).
- *
- * @param xQueueSet The handle of the queue set to which the queue or semaphore
- * is being added.
- *
- * @return If the queue or semaphore was successfully added to the queue set
- * then pdPASS is returned.  If the queue could not be successfully added to the
- * queue set because it is already a member of a different queue set then pdFAIL
- * is returned.
- */
-BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-
-/*
- * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
- * be removed from a set if the queue or semaphore is empty.
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
- * from the queue set (cast to an QueueSetMemberHandle_t type).
- *
- * @param xQueueSet The handle of the queue set in which the queue or semaphore
- * is included.
- *
- * @return If the queue or semaphore was successfully removed from the queue set
- * then pdPASS is returned.  If the queue was not in the queue set, or the
- * queue (or semaphore) was not empty, then pdFAIL is returned.
- */
-BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-
-/*
- * xQueueSelectFromSet() selects from the members of a queue set a queue or
- * semaphore that either contains data (in the case of a queue) or is available
- * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
- * allows a task to block (pend) on a read operation on all the queues and
- * semaphores in a queue set simultaneously.
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
- * for reasons why queue sets are very rarely needed in practice as there are
- * simpler methods of blocking on multiple objects.
- *
- * Note 2:  Blocking on a queue set that contains a mutex will not cause the
- * mutex holder to inherit the priority of the blocked task.
- *
- * Note 3:  A receive (in the case of a queue) or take (in the case of a
- * semaphore) operation must not be performed on a member of a queue set unless
- * a call to xQueueSelectFromSet() has first returned a handle to that set member.
- *
- * @param xQueueSet The queue set on which the task will (potentially) block.
- *
- * @param xTicksToWait The maximum time, in ticks, that the calling task will
- * remain in the Blocked state (with other tasks executing) to wait for a member
- * of the queue set to be ready for a successful queue read or semaphore take
- * operation.
- *
- * @return xQueueSelectFromSet() will return the handle of a queue (cast to
- * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
- * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
- * in the queue set that is available, or NULL if no such queue or semaphore
- * exists before before the specified block time expires.
- */
-QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/*
- * A version of xQueueSelectFromSet() that can be used from an ISR.
- */
-QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-
-/* Not public API functions. */
-void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
-void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
-UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* QUEUE_H */
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/semphr.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/semphr.h
deleted file mode 100644
index 32b4e5e..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/semphr.h
+++ /dev/null
@@ -1,1140 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef SEMAPHORE_H
-#define SEMAPHORE_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
-#endif
-
-#include "queue.h"
-
-typedef QueueHandle_t SemaphoreHandle_t;
-
-#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
-#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
-#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
-
-
-/**
- * semphr. h
- * 
vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )

- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a binary semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
- * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
- * the vSemaphoreCreateBinary() macro are created in a state such that the
- * first call to 'take' the semaphore would pass, whereas binary semaphores
- * created using xSemaphoreCreateBinary() are created in a state such that the
- * the semaphore must first be 'given' before it can be 'taken'.
- *
- * Macro that implements a semaphore by using the existing queue mechanism.
- * The queue length is 1 as this is a binary semaphore.  The data size is 0
- * as we don't want to actually store any data - we just want to know if the
- * queue is empty or full.
- *
- * This type of semaphore can be used for pure synchronisation between tasks or
- * between an interrupt and a task.  The semaphore need not be given back once
- * obtained, so one task/interrupt can continuously 'give' the semaphore while
- * another continuously 'takes' the semaphore.  For this reason this type of
- * semaphore does not use a priority inheritance mechanism.  For an alternative
- * that does use priority inheritance see xSemaphoreCreateMutex().
- *
- * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore = NULL;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
-    // This is a macro so pass the variable in directly.
-    vSemaphoreCreateBinary( xSemaphore );
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.
-    }
- }
- 

- * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
- * \ingroup Semaphores
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define vSemaphoreCreateBinary( xSemaphore )																							\
-		{																																	\
-			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
-			if( ( xSemaphore ) != NULL )																									\
-			{																																\
-				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
-			}																																\
-		}
-#endif
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateBinary( void )

- *
- * Creates a new binary semaphore instance, and returns a handle by which the
- * new semaphore can be referenced.
- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a binary semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, binary semaphores use a block
- * of memory, in which the semaphore structure is stored.  If a binary semaphore
- * is created using xSemaphoreCreateBinary() then the required memory is
- * automatically dynamically allocated inside the xSemaphoreCreateBinary()
- * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
- * is created using xSemaphoreCreateBinaryStatic() then the application writer
- * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
- * binary semaphore to be created without using any dynamic memory allocation.
- *
- * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
- * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
- * the vSemaphoreCreateBinary() macro are created in a state such that the
- * first call to 'take' the semaphore would pass, whereas binary semaphores
- * created using xSemaphoreCreateBinary() are created in a state such that the
- * the semaphore must first be 'given' before it can be 'taken'.
- *
- * This type of semaphore can be used for pure synchronisation between tasks or
- * between an interrupt and a task.  The semaphore need not be given back once
- * obtained, so one task/interrupt can continuously 'give' the semaphore while
- * another continuously 'takes' the semaphore.  For this reason this type of
- * semaphore does not use a priority inheritance mechanism.  For an alternative
- * that does use priority inheritance see xSemaphoreCreateMutex().
- *
- * @return Handle to the created semaphore, or NULL if the memory required to
- * hold the semaphore's data structures could not be allocated.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore = NULL;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
-    // This is a macro so pass the variable in directly.
-    xSemaphore = xSemaphoreCreateBinary();
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.
-    }
- }
- 

- * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
- * \ingroup Semaphores
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
-#endif
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )

- *
- * Creates a new binary semaphore instance, and returns a handle by which the
- * new semaphore can be referenced.
- *
- * NOTE: In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a binary semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, binary semaphores use a block
- * of memory, in which the semaphore structure is stored.  If a binary semaphore
- * is created using xSemaphoreCreateBinary() then the required memory is
- * automatically dynamically allocated inside the xSemaphoreCreateBinary()
- * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
- * is created using xSemaphoreCreateBinaryStatic() then the application writer
- * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
- * binary semaphore to be created without using any dynamic memory allocation.
- *
- * This type of semaphore can be used for pure synchronisation between tasks or
- * between an interrupt and a task.  The semaphore need not be given back once
- * obtained, so one task/interrupt can continuously 'give' the semaphore while
- * another continuously 'takes' the semaphore.  For this reason this type of
- * semaphore does not use a priority inheritance mechanism.  For an alternative
- * that does use priority inheritance see xSemaphoreCreateMutex().
- *
- * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
- * which will then be used to hold the semaphore's data structure, removing the
- * need for the memory to be allocated dynamically.
- *
- * @return If the semaphore is created then a handle to the created semaphore is
- * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore = NULL;
- StaticSemaphore_t xSemaphoreBuffer;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
-    // The semaphore's data structures will be placed in the xSemaphoreBuffer
-    // variable, the address of which is passed into the function.  The
-    // function's parameter is not NULL, so the function will not attempt any
-    // dynamic memory allocation, and therefore the function will not return
-    // return NULL.
-    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
-
-    // Rest of task code goes here.
- }
- 

- * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
- * \ingroup Semaphores
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * semphr. h
- * 
xSemaphoreTake(
- *                   SemaphoreHandle_t xSemaphore,
- *                   TickType_t xBlockTime
- *               )

- *
- * Macro to obtain a semaphore.  The semaphore must have previously been
- * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
- * xSemaphoreCreateCounting().
- *
- * @param xSemaphore A handle to the semaphore being taken - obtained when
- * the semaphore was created.
- *
- * @param xBlockTime The time in ticks to wait for the semaphore to become
- * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
- * real time.  A block time of zero can be used to poll the semaphore.  A block
- * time of portMAX_DELAY can be used to block indefinitely (provided
- * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
- *
- * @return pdTRUE if the semaphore was obtained.  pdFALSE
- * if xBlockTime expired without the semaphore becoming available.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore = NULL;
-
- // A task that creates a semaphore.
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    xSemaphore = xSemaphoreCreateBinary();
- }
-
- // A task that uses the semaphore.
- void vAnotherTask( void * pvParameters )
- {
-    // ... Do other things.
-
-    if( xSemaphore != NULL )
-    {
-        // See if we can obtain the semaphore.  If the semaphore is not available
-        // wait 10 ticks to see if it becomes free.
-        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
-        {
-            // We were able to obtain the semaphore and can now access the
-            // shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource.  Release the
-            // semaphore.
-            xSemaphoreGive( xSemaphore );
-        }
-        else
-        {
-            // We could not obtain the semaphore and can therefore not access
-            // the shared resource safely.
-        }
-    }
- }
- 

- * \defgroup xSemaphoreTake xSemaphoreTake
- * \ingroup Semaphores
- */
-#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
-
-/**
- * semphr. h
- * xSemaphoreTakeRecursive(
- *                          SemaphoreHandle_t xMutex,
- *                          TickType_t xBlockTime
- *                        )
- *
- * Macro to recursively obtain, or 'take', a mutex type semaphore.
- * The mutex must have previously been created using a call to
- * xSemaphoreCreateRecursiveMutex();
- *
- * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
- * macro to be available.
- *
- * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * @param xMutex A handle to the mutex being obtained.  This is the
- * handle returned by xSemaphoreCreateRecursiveMutex();
- *
- * @param xBlockTime The time in ticks to wait for the semaphore to become
- * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
- * real time.  A block time of zero can be used to poll the semaphore.  If
- * the task already owns the semaphore then xSemaphoreTakeRecursive() will
- * return immediately no matter what the value of xBlockTime.
- *
- * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
- * expired without the semaphore becoming available.
- *
- * Example usage:
- 
- SemaphoreHandle_t xMutex = NULL;
-
- // A task that creates a mutex.
- void vATask( void * pvParameters )
- {
-    // Create the mutex to guard a shared resource.
-    xMutex = xSemaphoreCreateRecursiveMutex();
- }
-
- // A task that uses the mutex.
- void vAnotherTask( void * pvParameters )
- {
-    // ... Do other things.
-
-    if( xMutex != NULL )
-    {
-        // See if we can obtain the mutex.  If the mutex is not available
-        // wait 10 ticks to see if it becomes free.
-        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
-        {
-            // We were able to obtain the mutex and can now access the
-            // shared resource.
-
-            // ...
-            // For some reason due to the nature of the code further calls to
-            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
-            // code these would not be just sequential calls as this would make
-            // no sense.  Instead the calls are likely to be buried inside
-            // a more complex call structure.
-            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
-            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
-
-            // The mutex has now been 'taken' three times, so will not be
-            // available to another task until it has also been given back
-            // three times.  Again it is unlikely that real code would have
-            // these calls sequentially, but instead buried in a more complex
-            // call structure.  This is just for illustrative purposes.
-            xSemaphoreGiveRecursive( xMutex );
-            xSemaphoreGiveRecursive( xMutex );
-            xSemaphoreGiveRecursive( xMutex );
-
-            // Now the mutex can be taken by other tasks.
-        }
-        else
-        {
-            // We could not obtain the mutex and can therefore not access
-            // the shared resource safely.
-        }
-    }
- }
- 

- * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
- * \ingroup Semaphores
- */
-#if( configUSE_RECURSIVE_MUTEXES == 1 )
-	#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
-#endif
-
-/**
- * semphr. h
- * 
xSemaphoreGive( SemaphoreHandle_t xSemaphore )

- *
- * Macro to release a semaphore.  The semaphore must have previously been
- * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
- * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
- *
- * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
- * an alternative which can be used from an ISR.
- *
- * This macro must also not be used on semaphores created using
- * xSemaphoreCreateRecursiveMutex().
- *
- * @param xSemaphore A handle to the semaphore being released.  This is the
- * handle returned when the semaphore was created.
- *
- * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
- * Semaphores are implemented using queues.  An error can occur if there is
- * no space on the queue to post a message - indicating that the
- * semaphore was not first obtained correctly.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore = NULL;
-
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    xSemaphore = vSemaphoreCreateBinary();
-
-    if( xSemaphore != NULL )
-    {
-        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-        {
-            // We would expect this call to fail because we cannot give
-            // a semaphore without first "taking" it!
-        }
-
-        // Obtain the semaphore - don't block if the semaphore is not
-        // immediately available.
-        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
-        {
-            // We now have the semaphore and can access the shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource so can free the
-            // semaphore.
-            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-            {
-                // We would not expect this call to fail because we must have
-                // obtained the semaphore to get here.
-            }
-        }
-    }
- }
- 

- * \defgroup xSemaphoreGive xSemaphoreGive
- * \ingroup Semaphores
- */
-#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
-
-/**
- * semphr. h
- * 
xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )

- *
- * Macro to recursively release, or 'give', a mutex type semaphore.
- * The mutex must have previously been created using a call to
- * xSemaphoreCreateRecursiveMutex();
- *
- * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
- * macro to be available.
- *
- * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * @param xMutex A handle to the mutex being released, or 'given'.  This is the
- * handle returned by xSemaphoreCreateMutex();
- *
- * @return pdTRUE if the semaphore was given.
- *
- * Example usage:
- 
- SemaphoreHandle_t xMutex = NULL;
-
- // A task that creates a mutex.
- void vATask( void * pvParameters )
- {
-    // Create the mutex to guard a shared resource.
-    xMutex = xSemaphoreCreateRecursiveMutex();
- }
-
- // A task that uses the mutex.
- void vAnotherTask( void * pvParameters )
- {
-    // ... Do other things.
-
-    if( xMutex != NULL )
-    {
-        // See if we can obtain the mutex.  If the mutex is not available
-        // wait 10 ticks to see if it becomes free.
-        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
-        {
-            // We were able to obtain the mutex and can now access the
-            // shared resource.
-
-            // ...
-            // For some reason due to the nature of the code further calls to
-			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
-			// code these would not be just sequential calls as this would make
-			// no sense.  Instead the calls are likely to be buried inside
-			// a more complex call structure.
-            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
-            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
-
-            // The mutex has now been 'taken' three times, so will not be
-			// available to another task until it has also been given back
-			// three times.  Again it is unlikely that real code would have
-			// these calls sequentially, it would be more likely that the calls
-			// to xSemaphoreGiveRecursive() would be called as a call stack
-			// unwound.  This is just for demonstrative purposes.
-            xSemaphoreGiveRecursive( xMutex );
-			xSemaphoreGiveRecursive( xMutex );
-			xSemaphoreGiveRecursive( xMutex );
-
-			// Now the mutex can be taken by other tasks.
-        }
-        else
-        {
-            // We could not obtain the mutex and can therefore not access
-            // the shared resource safely.
-        }
-    }
- }
- 

- * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
- * \ingroup Semaphores
- */
-#if( configUSE_RECURSIVE_MUTEXES == 1 )
-	#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
-#endif
-
-/**
- * semphr. h
- * 
- xSemaphoreGiveFromISR(
-                          SemaphoreHandle_t xSemaphore,
-                          BaseType_t *pxHigherPriorityTaskWoken
-                      )

- *
- * Macro to  release a semaphore.  The semaphore must have previously been
- * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
- *
- * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
- * must not be used with this macro.
- *
- * This macro can be used from an ISR.
- *
- * @param xSemaphore A handle to the semaphore being released.  This is the
- * handle returned when the semaphore was created.
- *
- * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
- *
- * Example usage:
- 
- \#define LONG_TIME 0xffff
- \#define TICKS_TO_WAIT	10
- SemaphoreHandle_t xSemaphore = NULL;
-
- // Repetitive task.
- void vATask( void * pvParameters )
- {
-    for( ;; )
-    {
-        // We want this task to run every 10 ticks of a timer.  The semaphore
-        // was created before this task was started.
-
-        // Block waiting for the semaphore to become available.
-        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
-        {
-            // It is time to execute.
-
-            // ...
-
-            // We have finished our task.  Return to the top of the loop where
-            // we will block on the semaphore until it is time to execute
-            // again.  Note when using the semaphore for synchronisation with an
-			// ISR in this manner there is no need to 'give' the semaphore back.
-        }
-    }
- }
-
- // Timer ISR
- void vTimerISR( void * pvParameters )
- {
- static uint8_t ucLocalTickCount = 0;
- static BaseType_t xHigherPriorityTaskWoken;
-
-    // A timer tick has occurred.
-
-    // ... Do other time functions.
-
-    // Is it time for vATask () to run?
-	xHigherPriorityTaskWoken = pdFALSE;
-    ucLocalTickCount++;
-    if( ucLocalTickCount >= TICKS_TO_WAIT )
-    {
-        // Unblock the task by releasing the semaphore.
-        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
-
-        // Reset the count so we release the semaphore again in 10 ticks time.
-        ucLocalTickCount = 0;
-    }
-
-    if( xHigherPriorityTaskWoken != pdFALSE )
-    {
-        // We can force a context switch here.  Context switching from an
-        // ISR uses port specific syntax.  Check the demo task for your port
-        // to find the syntax required.
-    }
- }
- 

- * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
- * \ingroup Semaphores
- */
-#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
-
-/**
- * semphr. h
- * 
- xSemaphoreTakeFromISR(
-                          SemaphoreHandle_t xSemaphore,
-                          BaseType_t *pxHigherPriorityTaskWoken
-                      )

- *
- * Macro to  take a semaphore from an ISR.  The semaphore must have
- * previously been created with a call to xSemaphoreCreateBinary() or
- * xSemaphoreCreateCounting().
- *
- * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
- * must not be used with this macro.
- *
- * This macro can be used from an ISR, however taking a semaphore from an ISR
- * is not a common operation.  It is likely to only be useful when taking a
- * counting semaphore when an interrupt is obtaining an object from a resource
- * pool (when the semaphore count indicates the number of resources available).
- *
- * @param xSemaphore A handle to the semaphore being taken.  This is the
- * handle returned when the semaphore was created.
- *
- * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the semaphore was successfully taken, otherwise
- * pdFALSE
- */
-#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateMutex( void )

- *
- * Creates a new mutex type semaphore instance, and returns a handle by which
- * the new mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, mutex semaphores use a block
- * of memory, in which the mutex structure is stored.  If a mutex is created
- * using xSemaphoreCreateMutex() then the required memory is automatically
- * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
- * http://www.freertos.org/a00111.html).  If a mutex is created using
- * xSemaphoreCreateMutexStatic() then the application writer must provided the
- * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
- * without using any dynamic memory allocation.
- *
- * Mutexes created using this function can be accessed using the xSemaphoreTake()
- * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
- * xSemaphoreGiveRecursive() macros must not be used.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @return If the mutex was successfully created then a handle to the created
- * semaphore is returned.  If there was not enough heap to allocate the mutex
- * data structures then NULL is returned.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
-    // This is a macro so pass the variable in directly.
-    xSemaphore = xSemaphoreCreateMutex();
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.
-    }
- }
- 

- * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
- * \ingroup Semaphores
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
-#endif
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )

- *
- * Creates a new mutex type semaphore instance, and returns a handle by which
- * the new mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, mutex semaphores use a block
- * of memory, in which the mutex structure is stored.  If a mutex is created
- * using xSemaphoreCreateMutex() then the required memory is automatically
- * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
- * http://www.freertos.org/a00111.html).  If a mutex is created using
- * xSemaphoreCreateMutexStatic() then the application writer must provided the
- * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
- * without using any dynamic memory allocation.
- *
- * Mutexes created using this function can be accessed using the xSemaphoreTake()
- * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
- * xSemaphoreGiveRecursive() macros must not be used.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
- * which will be used to hold the mutex's data structure, removing the need for
- * the memory to be allocated dynamically.
- *
- * @return If the mutex was successfully created then a handle to the created
- * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore;
- StaticSemaphore_t xMutexBuffer;
-
- void vATask( void * pvParameters )
- {
-    // A mutex cannot be used before it has been created.  xMutexBuffer is
-    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
-    // attempted.
-    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
-
-    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
-    // so there is no need to check it.
- }
- 

- * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
- * \ingroup Semaphores
- */
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )

- *
- * Creates a new recursive mutex type semaphore instance, and returns a handle
- * by which the new recursive mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, recursive mutexs use a block
- * of memory, in which the mutex structure is stored.  If a recursive mutex is
- * created using xSemaphoreCreateRecursiveMutex() then the required memory is
- * automatically dynamically allocated inside the
- * xSemaphoreCreateRecursiveMutex() function.  (see
- * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
- * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
- * provide the memory that will get used by the mutex.
- * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
- * be created without using any dynamic memory allocation.
- *
- * Mutexes created using this macro can be accessed using the
- * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
- * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
- * SemaphoreHandle_t.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
-    // This is a macro so pass the variable in directly.
-    xSemaphore = xSemaphoreCreateRecursiveMutex();
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.
-    }
- }
- 

- * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
- * \ingroup Semaphores
- */
-#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
-	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
-#endif
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )

- *
- * Creates a new recursive mutex type semaphore instance, and returns a handle
- * by which the new recursive mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, recursive mutexs use a block
- * of memory, in which the mutex structure is stored.  If a recursive mutex is
- * created using xSemaphoreCreateRecursiveMutex() then the required memory is
- * automatically dynamically allocated inside the
- * xSemaphoreCreateRecursiveMutex() function.  (see
- * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
- * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
- * provide the memory that will get used by the mutex.
- * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
- * be created without using any dynamic memory allocation.
- *
- * Mutexes created using this macro can be accessed using the
- * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
- * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
- * which will then be used to hold the recursive mutex's data structure,
- * removing the need for the memory to be allocated dynamically.
- *
- * @return If the recursive mutex was successfully created then a handle to the
- * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
- * returned.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore;
- StaticSemaphore_t xMutexBuffer;
-
- void vATask( void * pvParameters )
- {
-    // A recursive semaphore cannot be used before it is created.  Here a
-    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
-    // The address of xMutexBuffer is passed into the function, and will hold
-    // the mutexes data structures - so no dynamic memory allocation will be
-    // attempted.
-    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
-
-    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
-    // so there is no need to check it.
- }
- 

- * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
- * \ingroup Semaphores
- */
-#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
-	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )

- *
- * Creates a new counting semaphore instance, and returns a handle by which the
- * new counting semaphore can be referenced.
- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a counting semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, counting semaphores use a
- * block of memory, in which the counting semaphore structure is stored.  If a
- * counting semaphore is created using xSemaphoreCreateCounting() then the
- * required memory is automatically dynamically allocated inside the
- * xSemaphoreCreateCounting() function.  (see
- * http://www.freertos.org/a00111.html).  If a counting semaphore is created
- * using xSemaphoreCreateCountingStatic() then the application writer can
- * instead optionally provide the memory that will get used by the counting
- * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
- * semaphore to be created without using any dynamic memory allocation.
- *
- * Counting semaphores are typically used for two things:
- *
- * 1) Counting events.
- *
- *    In this usage scenario an event handler will 'give' a semaphore each time
- *    an event occurs (incrementing the semaphore count value), and a handler
- *    task will 'take' a semaphore each time it processes an event
- *    (decrementing the semaphore count value).  The count value is therefore
- *    the difference between the number of events that have occurred and the
- *    number that have been processed.  In this case it is desirable for the
- *    initial count value to be zero.
- *
- * 2) Resource management.
- *
- *    In this usage scenario the count value indicates the number of resources
- *    available.  To obtain control of a resource a task must first obtain a
- *    semaphore - decrementing the semaphore count value.  When the count value
- *    reaches zero there are no free resources.  When a task finishes with the
- *    resource it 'gives' the semaphore back - incrementing the semaphore count
- *    value.  In this case it is desirable for the initial count value to be
- *    equal to the maximum count value, indicating that all resources are free.
- *
- * @param uxMaxCount The maximum count value that can be reached.  When the
- *        semaphore reaches this value it can no longer be 'given'.
- *
- * @param uxInitialCount The count value assigned to the semaphore when it is
- *        created.
- *
- * @return Handle to the created semaphore.  Null if the semaphore could not be
- *         created.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore;
-
- void vATask( void * pvParameters )
- {
- SemaphoreHandle_t xSemaphore = NULL;
-
-    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
-    // The max value to which the semaphore can count should be 10, and the
-    // initial value assigned to the count should be 0.
-    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.
-    }
- }
- 

- * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
- * \ingroup Semaphores
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
-#endif
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )

- *
- * Creates a new counting semaphore instance, and returns a handle by which the
- * new counting semaphore can be referenced.
- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a counting semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, counting semaphores use a
- * block of memory, in which the counting semaphore structure is stored.  If a
- * counting semaphore is created using xSemaphoreCreateCounting() then the
- * required memory is automatically dynamically allocated inside the
- * xSemaphoreCreateCounting() function.  (see
- * http://www.freertos.org/a00111.html).  If a counting semaphore is created
- * using xSemaphoreCreateCountingStatic() then the application writer must
- * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
- * counting semaphore to be created without using any dynamic memory allocation.
- *
- * Counting semaphores are typically used for two things:
- *
- * 1) Counting events.
- *
- *    In this usage scenario an event handler will 'give' a semaphore each time
- *    an event occurs (incrementing the semaphore count value), and a handler
- *    task will 'take' a semaphore each time it processes an event
- *    (decrementing the semaphore count value).  The count value is therefore
- *    the difference between the number of events that have occurred and the
- *    number that have been processed.  In this case it is desirable for the
- *    initial count value to be zero.
- *
- * 2) Resource management.
- *
- *    In this usage scenario the count value indicates the number of resources
- *    available.  To obtain control of a resource a task must first obtain a
- *    semaphore - decrementing the semaphore count value.  When the count value
- *    reaches zero there are no free resources.  When a task finishes with the
- *    resource it 'gives' the semaphore back - incrementing the semaphore count
- *    value.  In this case it is desirable for the initial count value to be
- *    equal to the maximum count value, indicating that all resources are free.
- *
- * @param uxMaxCount The maximum count value that can be reached.  When the
- *        semaphore reaches this value it can no longer be 'given'.
- *
- * @param uxInitialCount The count value assigned to the semaphore when it is
- *        created.
- *
- * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
- * which will then be used to hold the semaphore's data structure, removing the
- * need for the memory to be allocated dynamically.
- *
- * @return If the counting semaphore was successfully created then a handle to
- * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
- * then NULL is returned.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore;
- StaticSemaphore_t xSemaphoreBuffer;
-
- void vATask( void * pvParameters )
- {
- SemaphoreHandle_t xSemaphore = NULL;
-
-    // Counting semaphore cannot be used before they have been created.  Create
-    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
-    // value to which the semaphore can count is 10, and the initial value
-    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
-    // passed in and will be used to hold the semaphore structure, so no dynamic
-    // memory allocation will be used.
-    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
-
-    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
-    // is no need to check its value.
- }
- 

- * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
- * \ingroup Semaphores
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * semphr. h
- * 
void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );

- *
- * Delete a semaphore.  This function must be used with care.  For example,
- * do not delete a mutex type semaphore if the mutex is held by a task.
- *
- * @param xSemaphore A handle to the semaphore to be deleted.
- *
- * \defgroup vSemaphoreDelete vSemaphoreDelete
- * \ingroup Semaphores
- */
-#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
-
-/**
- * semphr.h
- * 
TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );

- *
- * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
- * If xMutex is not a mutex type semaphore, or the mutex is available (not held
- * by a task), return NULL.
- *
- * Note: This is a good way of determining if the calling task is the mutex
- * holder, but not a good way of determining the identity of the mutex holder as
- * the holder may change between the function exiting and the returned value
- * being tested.
- */
-#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
-
-/**
- * semphr.h
- * 
TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );

- *
- * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
- * If xMutex is not a mutex type semaphore, or the mutex is available (not held
- * by a task), return NULL.
- *
- */
-#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
-
-/**
- * semphr.h
- * 
UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );

- *
- * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
- * its current count value.  If the semaphore is a binary semaphore then
- * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
- * semaphore is not available.
- *
- */
-#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
-
-#endif /* SEMAPHORE_H */
-
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/stack_macros.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/stack_macros.h
deleted file mode 100644
index fb5ed15..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/stack_macros.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef STACK_MACROS_H
-#define STACK_MACROS_H
-
-/*
- * Call the stack overflow hook function if the stack of the task being swapped
- * out is currently overflowed, or looks like it might have overflowed in the
- * past.
- *
- * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
- * the current stack state only - comparing the current top of stack value to
- * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
- * will also cause the last few stack bytes to be checked to ensure the value
- * to which the bytes were set when the task was created have not been
- * overwritten.  Note this second test does not guarantee that an overflowed
- * stack will always be recognised.
- */
-
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
-
-	/* Only the current stack state is to be checked. */
-	#define taskCHECK_FOR_STACK_OVERFLOW()																\
-	{																									\
-		/* Is the currently saved stack pointer within the stack limit? */								\
-		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
-		}																								\
-	}
-
-#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
-
-	/* Only the current stack state is to be checked. */
-	#define taskCHECK_FOR_STACK_OVERFLOW()																\
-	{																									\
-																										\
-		/* Is the currently saved stack pointer within the stack limit? */								\
-		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
-		}																								\
-	}
-
-#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
-
-	#define taskCHECK_FOR_STACK_OVERFLOW()																\
-	{																									\
-		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
-		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
-																										\
-		if( ( pulStack[ 0 ] != ulCheckValue ) ||														\
-			( pulStack[ 1 ] != ulCheckValue ) ||														\
-			( pulStack[ 2 ] != ulCheckValue ) ||														\
-			( pulStack[ 3 ] != ulCheckValue ) )															\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
-		}																								\
-	}
-
-#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
-
-	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
-	{																																	\
-	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
-	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
-																																		\
-																																		\
-		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
-																																		\
-		/* Has the extremity of the task stack ever been written over? */																\
-		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
-		{																																\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
-		}																																\
-	}
-
-#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
-/*-----------------------------------------------------------*/
-
-/* Remove stack overflow macro if not being used. */
-#ifndef taskCHECK_FOR_STACK_OVERFLOW
-	#define taskCHECK_FOR_STACK_OVERFLOW()
-#endif
-
-
-
-#endif /* STACK_MACROS_H */
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/stream_buffer.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/stream_buffer.h
deleted file mode 100644
index 5f9e012..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/stream_buffer.h
+++ /dev/null
@@ -1,855 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * Stream buffers are used to send a continuous stream of data from one task or
- * interrupt to another.  Their implementation is light weight, making them
- * particularly suited for interrupt to task and core to core communication
- * scenarios.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferRead()) inside a critical section section and set the
- * receive block time to 0.
- *
- */
-
-#ifndef STREAM_BUFFER_H
-#define STREAM_BUFFER_H
-
-#if defined( __cplusplus )
-extern "C" {
-#endif
-
-/**
- * Type by which stream buffers are referenced.  For example, a call to
- * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
- * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
- * etc.
- */
-struct StreamBufferDef_t;
-typedef struct StreamBufferDef_t * StreamBufferHandle_t;
-
-
-/**
- * message_buffer.h
- *
-
-StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
-

- *
- * Creates a new stream buffer using dynamically allocated memory.  See
- * xStreamBufferCreateStatic() for a version that uses statically allocated
- * memory (memory that is allocated at compile time).
- *
- * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
- * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
- *
- * @param xBufferSizeBytes The total number of bytes the stream buffer will be
- * able to hold at any one time.
- *
- * @param xTriggerLevelBytes The number of bytes that must be in the stream
- * buffer before a task that is blocked on the stream buffer to wait for data is
- * moved out of the blocked state.  For example, if a task is blocked on a read
- * of an empty stream buffer that has a trigger level of 1 then the task will be
- * unblocked when a single byte is written to the buffer or the task's block
- * time expires.  As another example, if a task is blocked on a read of an empty
- * stream buffer that has a trigger level of 10 then the task will not be
- * unblocked until the stream buffer contains at least 10 bytes or the task's
- * block time expires.  If a reading task's block time expires before the
- * trigger level is reached then the task will still receive however many bytes
- * are actually available.  Setting a trigger level of 0 will result in a
- * trigger level of 1 being used.  It is not valid to specify a trigger level
- * that is greater than the buffer size.
- *
- * @return If NULL is returned, then the stream buffer cannot be created
- * because there is insufficient heap memory available for FreeRTOS to allocate
- * the stream buffer data structures and storage area.  A non-NULL value being
- * returned indicates that the stream buffer has been created successfully -
- * the returned value should be stored as the handle to the created stream
- * buffer.
- *
- * Example use:
-
-
-void vAFunction( void )
-{
-StreamBufferHandle_t xStreamBuffer;
-const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
-
-    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
-    // both the stream buffer structure and the data in the stream buffer is
-    // allocated dynamically.
-    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
-
-    if( xStreamBuffer == NULL )
-    {
-        // There was not enough heap memory space available to create the
-        // stream buffer.
-    }
-    else
-    {
-        // The stream buffer was created successfully and can now be used.
-    }
-}
-

- * \defgroup xStreamBufferCreate xStreamBufferCreate
- * \ingroup StreamBufferManagement
- */
-#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
-
-/**
- * stream_buffer.h
- *
-
-StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
-                                                size_t xTriggerLevelBytes,
-                                                uint8_t *pucStreamBufferStorageArea,
-                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
-

- * Creates a new stream buffer using statically allocated memory.  See
- * xStreamBufferCreate() for a version that uses dynamically allocated memory.
- *
- * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
- * xStreamBufferCreateStatic() to be available.
- *
- * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
- * pucStreamBufferStorageArea parameter.
- *
- * @param xTriggerLevelBytes The number of bytes that must be in the stream
- * buffer before a task that is blocked on the stream buffer to wait for data is
- * moved out of the blocked state.  For example, if a task is blocked on a read
- * of an empty stream buffer that has a trigger level of 1 then the task will be
- * unblocked when a single byte is written to the buffer or the task's block
- * time expires.  As another example, if a task is blocked on a read of an empty
- * stream buffer that has a trigger level of 10 then the task will not be
- * unblocked until the stream buffer contains at least 10 bytes or the task's
- * block time expires.  If a reading task's block time expires before the
- * trigger level is reached then the task will still receive however many bytes
- * are actually available.  Setting a trigger level of 0 will result in a
- * trigger level of 1 being used.  It is not valid to specify a trigger level
- * that is greater than the buffer size.
- *
- * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
- * least xBufferSizeBytes + 1 big.  This is the array to which streams are
- * copied when they are written to the stream buffer.
- *
- * @param pxStaticStreamBuffer Must point to a variable of type
- * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
- * structure.
- *
- * @return If the stream buffer is created successfully then a handle to the
- * created stream buffer is returned. If either pucStreamBufferStorageArea or
- * pxStaticstreamBuffer are NULL then NULL is returned.
- *
- * Example use:
-
-
-// Used to dimension the array used to hold the streams.  The available space
-// will actually be one less than this, so 999.
-#define STORAGE_SIZE_BYTES 1000
-
-// Defines the memory that will actually hold the streams within the stream
-// buffer.
-static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
-
-// The variable used to hold the stream buffer structure.
-StaticStreamBuffer_t xStreamBufferStruct;
-
-void MyFunction( void )
-{
-StreamBufferHandle_t xStreamBuffer;
-const size_t xTriggerLevel = 1;
-
-    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
-                                               xTriggerLevel,
-                                               ucBufferStorage,
-                                               &xStreamBufferStruct );
-
-    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
-    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
-    // reference the created stream buffer in other stream buffer API calls.
-
-    // Other code that uses the stream buffer can go here.
-}
-
-

- * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
- * \ingroup StreamBufferManagement
- */
-#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
-
-/**
- * stream_buffer.h
- *
-
-size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                          const void *pvTxData,
-                          size_t xDataLengthBytes,
-                          TickType_t xTicksToWait );
-

- *
- * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
- * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
- * service routine (ISR).
- *
- * @param xStreamBuffer The handle of the stream buffer to which a stream is
- * being sent.
- *
- * @param pvTxData A pointer to the buffer that holds the bytes to be copied
- * into the stream buffer.
- *
- * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
- * into the stream buffer.
- *
- * @param xTicksToWait The maximum amount of time the task should remain in the
- * Blocked state to wait for enough space to become available in the stream
- * buffer, should the stream buffer contain too little space to hold the
- * another xDataLengthBytes bytes.  The block time is specified in tick periods,
- * so the absolute time it represents is dependent on the tick frequency.  The
- * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
- * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
- * cause the task to wait indefinitely (without timing out), provided
- * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
- * before it can write all xDataLengthBytes into the buffer it will still write
- * as many bytes as possible.  A task does not use any CPU time when it is in
- * the blocked state.
- *
- * @return The number of bytes written to the stream buffer.  If a task times
- * out before it can write all xDataLengthBytes into the buffer it will still
- * write as many bytes as possible.
- *
- * Example use:
-
-void vAFunction( StreamBufferHandle_t xStreamBuffer )
-{
-size_t xBytesSent;
-uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
-char *pcStringToSend = "String to send";
-const TickType_t x100ms = pdMS_TO_TICKS( 100 );
-
-    // Send an array to the stream buffer, blocking for a maximum of 100ms to
-    // wait for enough space to be available in the stream buffer.
-    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
-
-    if( xBytesSent != sizeof( ucArrayToSend ) )
-    {
-        // The call to xStreamBufferSend() times out before there was enough
-        // space in the buffer for the data to be written, but it did
-        // successfully write xBytesSent bytes.
-    }
-
-    // Send the string to the stream buffer.  Return immediately if there is not
-    // enough space in the buffer.
-    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
-
-    if( xBytesSent != strlen( pcStringToSend ) )
-    {
-        // The entire string could not be added to the stream buffer because
-        // there was not enough free space in the buffer, but xBytesSent bytes
-        // were sent.  Could try again to send the remaining bytes.
-    }
-}
-

- * \defgroup xStreamBufferSend xStreamBufferSend
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-						  const void *pvTxData,
-						  size_t xDataLengthBytes,
-						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
-                                 const void *pvTxData,
-                                 size_t xDataLengthBytes,
-                                 BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * Interrupt safe version of the API function that sends a stream of bytes to
- * the stream buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
- * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
- * service routine (ISR).
- *
- * @param xStreamBuffer The handle of the stream buffer to which a stream is
- * being sent.
- *
- * @param pvTxData A pointer to the data that is to be copied into the stream
- * buffer.
- *
- * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
- * into the stream buffer.
- *
- * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
- * have a task blocked on it waiting for data.  Calling
- * xStreamBufferSendFromISR() can make data available, and so cause a task that
- * was waiting for data to leave the Blocked state.  If calling
- * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently executing task (the
- * task that was interrupted), then, internally, xStreamBufferSendFromISR()
- * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
- * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
- * context switch should be performed before the interrupt is exited.  This will
- * ensure that the interrupt returns directly to the highest priority Ready
- * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
- * is passed into the function.  See the example code below for an example.
- *
- * @return The number of bytes actually written to the stream buffer, which will
- * be less than xDataLengthBytes if the stream buffer didn't have enough free
- * space for all the bytes to be written.
- *
- * Example use:
-
-// A stream buffer that has already been created.
-StreamBufferHandle_t xStreamBuffer;
-
-void vAnInterruptServiceRoutine( void )
-{
-size_t xBytesSent;
-char *pcStringToSend = "String to send";
-BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
-
-    // Attempt to send the string to the stream buffer.
-    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
-                                           ( void * ) pcStringToSend,
-                                           strlen( pcStringToSend ),
-                                           &xHigherPriorityTaskWoken );
-
-    if( xBytesSent != strlen( pcStringToSend ) )
-    {
-        // There was not enough free space in the stream buffer for the entire
-        // string to be written, ut xBytesSent bytes were written.
-    }
-
-    // If xHigherPriorityTaskWoken was set to pdTRUE inside
-    // xStreamBufferSendFromISR() then a task that has a priority above the
-    // priority of the currently executing task was unblocked and a context
-    // switch should be performed to ensure the ISR returns to the unblocked
-    // task.  In most FreeRTOS ports this is done by simply passing
-    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
-    // variables value, and perform the context switch if necessary.  Check the
-    // documentation for the port in use for port specific instructions.
-    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-}
-

- * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
-								 const void *pvTxData,
-								 size_t xDataLengthBytes,
-								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                             void *pvRxData,
-                             size_t xBufferLengthBytes,
-                             TickType_t xTicksToWait );
-

- *
- * Receives bytes from a stream buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
- * xStreamBufferReceiveFromISR() to read from a stream buffer from an
- * interrupt service routine (ISR).
- *
- * @param xStreamBuffer The handle of the stream buffer from which bytes are to
- * be received.
- *
- * @param pvRxData A pointer to the buffer into which the received bytes will be
- * copied.
- *
- * @param xBufferLengthBytes The length of the buffer pointed to by the
- * pvRxData parameter.  This sets the maximum number of bytes to receive in one
- * call.  xStreamBufferReceive will return as many bytes as possible up to a
- * maximum set by xBufferLengthBytes.
- *
- * @param xTicksToWait The maximum amount of time the task should remain in the
- * Blocked state to wait for data to become available if the stream buffer is
- * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
- * zero.  The block time is specified in tick periods, so the absolute time it
- * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
- * be used to convert a time specified in milliseconds into a time specified in
- * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
- * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
- * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
- * Blocked state.
- *
- * @return The number of bytes actually read from the stream buffer, which will
- * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
- * out before xBufferLengthBytes were available.
- *
- * Example use:
-
-void vAFunction( StreamBuffer_t xStreamBuffer )
-{
-uint8_t ucRxData[ 20 ];
-size_t xReceivedBytes;
-const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
-
-    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
-    // Wait in the Blocked state (so not using any CPU processing time) for a
-    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
-    // available.
-    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
-                                           ( void * ) ucRxData,
-                                           sizeof( ucRxData ),
-                                           xBlockTime );
-
-    if( xReceivedBytes > 0 )
-    {
-        // A ucRxData contains another xRecievedBytes bytes of data, which can
-        // be processed here....
-    }
-}
-

- * \defgroup xStreamBufferReceive xStreamBufferReceive
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-							 void *pvRxData,
-							 size_t xBufferLengthBytes,
-							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
-                                    void *pvRxData,
-                                    size_t xBufferLengthBytes,
-                                    BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * An interrupt safe version of the API function that receives bytes from a
- * stream buffer.
- *
- * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
- * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
- * interrupt service routine (ISR).
- *
- * @param xStreamBuffer The handle of the stream buffer from which a stream
- * is being received.
- *
- * @param pvRxData A pointer to the buffer into which the received bytes are
- * copied.
- *
- * @param xBufferLengthBytes The length of the buffer pointed to by the
- * pvRxData parameter.  This sets the maximum number of bytes to receive in one
- * call.  xStreamBufferReceive will return as many bytes as possible up to a
- * maximum set by xBufferLengthBytes.
- *
- * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
- * have a task blocked on it waiting for space to become available.  Calling
- * xStreamBufferReceiveFromISR() can make space available, and so cause a task
- * that is waiting for space to leave the Blocked state.  If calling
- * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
- * the unblocked task has a priority higher than the currently executing task
- * (the task that was interrupted), then, internally,
- * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
- * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
- * context switch should be performed before the interrupt is exited.  That will
- * ensure the interrupt returns directly to the highest priority Ready state
- * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
- * passed into the function.  See the code example below for an example.
- *
- * @return The number of bytes read from the stream buffer, if any.
- *
- * Example use:
-
-// A stream buffer that has already been created.
-StreamBuffer_t xStreamBuffer;
-
-void vAnInterruptServiceRoutine( void )
-{
-uint8_t ucRxData[ 20 ];
-size_t xReceivedBytes;
-BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
-
-    // Receive the next stream from the stream buffer.
-    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
-                                                  ( void * ) ucRxData,
-                                                  sizeof( ucRxData ),
-                                                  &xHigherPriorityTaskWoken );
-
-    if( xReceivedBytes > 0 )
-    {
-        // ucRxData contains xReceivedBytes read from the stream buffer.
-        // Process the stream here....
-    }
-
-    // If xHigherPriorityTaskWoken was set to pdTRUE inside
-    // xStreamBufferReceiveFromISR() then a task that has a priority above the
-    // priority of the currently executing task was unblocked and a context
-    // switch should be performed to ensure the ISR returns to the unblocked
-    // task.  In most FreeRTOS ports this is done by simply passing
-    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
-    // variables value, and perform the context switch if necessary.  Check the
-    // documentation for the port in use for port specific instructions.
-    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-}
-

- * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
-									void *pvRxData,
-									size_t xBufferLengthBytes,
-									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
-

- *
- * Deletes a stream buffer that was previously created using a call to
- * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
- * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
- * then the allocated memory is freed.
- *
- * A stream buffer handle must not be used after the stream buffer has been
- * deleted.
- *
- * @param xStreamBuffer The handle of the stream buffer to be deleted.
- *
- * \defgroup vStreamBufferDelete vStreamBufferDelete
- * \ingroup StreamBufferManagement
- */
-void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
-

- *
- * Queries a stream buffer to see if it is full.  A stream buffer is full if it
- * does not have any free space, and therefore cannot accept any more data.
- *
- * @param xStreamBuffer The handle of the stream buffer being queried.
- *
- * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
- * pdFALSE is returned.
- *
- * \defgroup xStreamBufferIsFull xStreamBufferIsFull
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
-

- *
- * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
- * it does not contain any data.
- *
- * @param xStreamBuffer The handle of the stream buffer being queried.
- *
- * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
- * pdFALSE is returned.
- *
- * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
-

- *
- * Resets a stream buffer to its initial, empty, state.  Any data that was in
- * the stream buffer is discarded.  A stream buffer can only be reset if there
- * are no tasks blocked waiting to either send to or receive from the stream
- * buffer.
- *
- * @param xStreamBuffer The handle of the stream buffer being reset.
- *
- * @return If the stream buffer is reset then pdPASS is returned.  If there was
- * a task blocked waiting to send to or read from the stream buffer then the
- * stream buffer is not reset and pdFAIL is returned.
- *
- * \defgroup xStreamBufferReset xStreamBufferReset
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
-

- *
- * Queries a stream buffer to see how much free space it contains, which is
- * equal to the amount of data that can be sent to the stream buffer before it
- * is full.
- *
- * @param xStreamBuffer The handle of the stream buffer being queried.
- *
- * @return The number of bytes that can be written to the stream buffer before
- * the stream buffer would be full.
- *
- * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
-

- *
- * Queries a stream buffer to see how much data it contains, which is equal to
- * the number of bytes that can be read from the stream buffer before the stream
- * buffer would be empty.
- *
- * @param xStreamBuffer The handle of the stream buffer being queried.
- *
- * @return The number of bytes that can be read from the stream buffer before
- * the stream buffer would be empty.
- *
- * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
-

- *
- * A stream buffer's trigger level is the number of bytes that must be in the
- * stream buffer before a task that is blocked on the stream buffer to
- * wait for data is moved out of the blocked state.  For example, if a task is
- * blocked on a read of an empty stream buffer that has a trigger level of 1
- * then the task will be unblocked when a single byte is written to the buffer
- * or the task's block time expires.  As another example, if a task is blocked
- * on a read of an empty stream buffer that has a trigger level of 10 then the
- * task will not be unblocked until the stream buffer contains at least 10 bytes
- * or the task's block time expires.  If a reading task's block time expires
- * before the trigger level is reached then the task will still receive however
- * many bytes are actually available.  Setting a trigger level of 0 will result
- * in a trigger level of 1 being used.  It is not valid to specify a trigger
- * level that is greater than the buffer size.
- *
- * A trigger level is set when the stream buffer is created, and can be modified
- * using xStreamBufferSetTriggerLevel().
- *
- * @param xStreamBuffer The handle of the stream buffer being updated.
- *
- * @param xTriggerLevel The new trigger level for the stream buffer.
- *
- * @return If xTriggerLevel was less than or equal to the stream buffer's length
- * then the trigger level will be updated and pdTRUE is returned.  Otherwise
- * pdFALSE is returned.
- *
- * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * For advanced users only.
- *
- * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
- * data is sent to a message buffer or stream buffer.  If there was a task that
- * was blocked on the message or stream buffer waiting for data to arrive then
- * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
- * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
- * thing.  It is provided to enable application writers to implement their own
- * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
- *
- * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
- * additional information.
- *
- * @param xStreamBuffer The handle of the stream buffer to which data was
- * written.
- *
- * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
- * initialised to pdFALSE before it is passed into
- * xStreamBufferSendCompletedFromISR().  If calling
- * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
- * and the task has a priority above the priority of the currently running task,
- * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
- * context switch should be performed before exiting the ISR.
- *
- * @return If a task was removed from the Blocked state then pdTRUE is returned.
- * Otherwise pdFALSE is returned.
- *
- * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * For advanced users only.
- *
- * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
- * data is read out of a message buffer or stream buffer.  If there was a task
- * that was blocked on the message or stream buffer waiting for data to arrive
- * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
- * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
- * does the same thing.  It is provided to enable application writers to
- * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
- * ANY OTHER TIME.
- *
- * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
- * additional information.
- *
- * @param xStreamBuffer The handle of the stream buffer from which data was
- * read.
- *
- * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
- * initialised to pdFALSE before it is passed into
- * xStreamBufferReceiveCompletedFromISR().  If calling
- * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
- * and the task has a priority above the priority of the currently running task,
- * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
- * context switch should be performed before exiting the ISR.
- *
- * @return If a task was removed from the Blocked state then pdTRUE is returned.
- * Otherwise pdFALSE is returned.
- *
- * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/* Functions below here are not part of the public API. */
-StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
-												 size_t xTriggerLevelBytes,
-												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
-
-StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
-													   size_t xTriggerLevelBytes,
-													   BaseType_t xIsMessageBuffer,
-													   uint8_t * const pucStreamBufferStorageArea,
-													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
-
-size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-#if( configUSE_TRACE_FACILITY == 1 )
-	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
-	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-#endif
-
-#if defined( __cplusplus )
-}
-#endif
-
-#endif	/* !defined( STREAM_BUFFER_H ) */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/task.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/task.h
deleted file mode 100644
index 956366b..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/task.h
+++ /dev/null
@@ -1,2443 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- *
- * Copyright 2019 MicroEJ Corp. This file has been modified by MicroEJ Corp.
- * 1. Patch for SystemView support
- */
-
-
-#ifndef INC_TASK_H
-#define INC_TASK_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h must appear in source files before include task.h"
-#endif
-
-#include "list.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * MACROS AND DEFINITIONS
- *----------------------------------------------------------*/
-
-#define tskKERNEL_VERSION_NUMBER "V10.2.1"
-#define tskKERNEL_VERSION_MAJOR 10
-#define tskKERNEL_VERSION_MINOR 2
-#define tskKERNEL_VERSION_BUILD 1
-
-/* MPU region parameters passed in ulParameters
- * of MemoryRegion_t struct. */
-#define tskMPU_REGION_READ_ONLY			( 1UL << 0UL )
-#define tskMPU_REGION_READ_WRITE		( 1UL << 1UL )
-#define tskMPU_REGION_EXECUTE_NEVER		( 1UL << 2UL )
-#define tskMPU_REGION_NORMAL_MEMORY		( 1UL << 3UL )
-#define tskMPU_REGION_DEVICE_MEMORY		( 1UL << 4UL )
-
-/**
- * task. h
- *
- * Type by which tasks are referenced.  For example, a call to xTaskCreate
- * returns (via a pointer parameter) an TaskHandle_t variable that can then
- * be used as a parameter to vTaskDelete to delete the task.
- *
- * \defgroup TaskHandle_t TaskHandle_t
- * \ingroup Tasks
- */
-struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
-typedef struct tskTaskControlBlock* TaskHandle_t;
-
-/*
- * Defines the prototype to which the application task hook function must
- * conform.
- */
-typedef BaseType_t (*TaskHookFunction_t)( void * );
-
-/* Task states returned by eTaskGetState. */
-typedef enum
-{
-	eRunning = 0,	/* A task is querying the state of itself, so must be running. */
-	eReady,			/* The task being queried is in a read or pending ready list. */
-	eBlocked,		/* The task being queried is in the Blocked state. */
-	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
-	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
-	eInvalid		/* Used as an 'invalid state' value. */
-} eTaskState;
-
-/* Actions that can be performed when vTaskNotify() is called. */
-typedef enum
-{
-	eNoAction = 0,				/* Notify the task without updating its notify value. */
-	eSetBits,					/* Set bits in the task's notification value. */
-	eIncrement,					/* Increment the task's notification value. */
-	eSetValueWithOverwrite,		/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
-	eSetValueWithoutOverwrite	/* Set the task's notification value if the previous value has been read by the task. */
-} eNotifyAction;
-
-/*
- * Used internally only.
- */
-typedef struct xTIME_OUT
-{
-	BaseType_t xOverflowCount;
-	TickType_t xTimeOnEntering;
-} TimeOut_t;
-
-/*
- * Defines the memory ranges allocated to the task when an MPU is used.
- */
-typedef struct xMEMORY_REGION
-{
-	void *pvBaseAddress;
-	uint32_t ulLengthInBytes;
-	uint32_t ulParameters;
-} MemoryRegion_t;
-
-/*
- * Parameters required to create an MPU protected task.
- */
-typedef struct xTASK_PARAMETERS
-{
-	TaskFunction_t pvTaskCode;
-	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	configSTACK_DEPTH_TYPE usStackDepth;
-	void *pvParameters;
-	UBaseType_t uxPriority;
-	StackType_t *puxStackBuffer;
-	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
-	#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-		StaticTask_t * const pxTaskBuffer;
-	#endif
-} TaskParameters_t;
-
-/* Used with the uxTaskGetSystemState() function to return the state of each task
-in the system. */
-typedef struct xTASK_STATUS
-{
-	TaskHandle_t xHandle;			/* The handle of the task to which the rest of the information in the structure relates. */
-	const char *pcTaskName;			/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	UBaseType_t xTaskNumber;		/* A number unique to the task. */
-	eTaskState eCurrentState;		/* The state in which the task existed when the structure was populated. */
-	UBaseType_t uxCurrentPriority;	/* The priority at which the task was running (may be inherited) when the structure was populated. */
-	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
-	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
-	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
-	configSTACK_DEPTH_TYPE usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
-} TaskStatus_t;
-
-/* Possible return values for eTaskConfirmSleepModeStatus(). */
-typedef enum
-{
-	eAbortSleep = 0,		/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
-	eStandardSleep,			/* Enter a sleep mode that will not last any longer than the expected idle time. */
-	eNoTasksWaitingTimeout	/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
-} eSleepModeStatus;
-
-/**
- * Defines the priority used by the idle task.  This must not be modified.
- *
- * \ingroup TaskUtils
- */
-#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
-
-/**
- * task. h
- *
- * Macro for forcing a context switch.
- *
- * \defgroup taskYIELD taskYIELD
- * \ingroup SchedulerControl
- */
-#define taskYIELD()					portYIELD()
-
-/**
- * task. h
- *
- * Macro to mark the start of a critical code region.  Preemptive context
- * switches cannot occur when in a critical region.
- *
- * NOTE: This may alter the stack (depending on the portable implementation)
- * so must be used with care!
- *
- * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
- * \ingroup SchedulerControl
- */
-#define taskENTER_CRITICAL()		portENTER_CRITICAL()
-#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
-
-/**
- * task. h
- *
- * Macro to mark the end of a critical code region.  Preemptive context
- * switches cannot occur when in a critical region.
- *
- * NOTE: This may alter the stack (depending on the portable implementation)
- * so must be used with care!
- *
- * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
- * \ingroup SchedulerControl
- */
-#define taskEXIT_CRITICAL()			portEXIT_CRITICAL()
-#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
-/**
- * task. h
- *
- * Macro to disable all maskable interrupts.
- *
- * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
- * \ingroup SchedulerControl
- */
-#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
-
-/**
- * task. h
- *
- * Macro to enable microcontroller interrupts.
- *
- * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
- * \ingroup SchedulerControl
- */
-#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
-
-/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
-0 to generate more optimal code when configASSERT() is defined as the constant
-is used in assert() statements. */
-#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
-#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
-#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
-
-
-/*-----------------------------------------------------------
- * TASK CREATION API
- *----------------------------------------------------------*/
-
-/**
- * task. h
- *
- BaseType_t xTaskCreate(
-							  TaskFunction_t pvTaskCode,
-							  const char * const pcName,
-							  configSTACK_DEPTH_TYPE usStackDepth,
-							  void *pvParameters,
-							  UBaseType_t uxPriority,
-							  TaskHandle_t *pvCreatedTask
-						  );

- *
- * Create a new task and add it to the list of tasks that are ready to run.
- *
- * Internally, within the FreeRTOS implementation, tasks use two blocks of
- * memory.  The first block is used to hold the task's data structures.  The
- * second block is used by the task as its stack.  If a task is created using
- * xTaskCreate() then both blocks of memory are automatically dynamically
- * allocated inside the xTaskCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a task is created using
- * xTaskCreateStatic() then the application writer must provide the required
- * memory.  xTaskCreateStatic() therefore allows a task to be created without
- * using any dynamic memory allocation.
- *
- * See xTaskCreateStatic() for a version that does not use any dynamic memory
- * allocation.
- *
- * xTaskCreate() can only be used to create a task that has unrestricted
- * access to the entire microcontroller memory map.  Systems that include MPU
- * support can alternatively create an MPU constrained task using
- * xTaskCreateRestricted().
- *
- * @param pvTaskCode Pointer to the task entry function.  Tasks
- * must be implemented to never return (i.e. continuous loop).
- *
- * @param pcName A descriptive name for the task.  This is mainly used to
- * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
- * is 16.
- *
- * @param usStackDepth The size of the task stack specified as the number of
- * variables the stack can hold - not the number of bytes.  For example, if
- * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
- * will be allocated for stack storage.
- *
- * @param pvParameters Pointer that will be used as the parameter for the task
- * being created.
- *
- * @param uxPriority The priority at which the task should run.  Systems that
- * include MPU support can optionally create tasks in a privileged (system)
- * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
- * example, to create a privileged task at priority 2 the uxPriority parameter
- * should be set to ( 2 | portPRIVILEGE_BIT ).
- *
- * @param pvCreatedTask Used to pass back a handle by which the created task
- * can be referenced.
- *
- * @return pdPASS if the task was successfully created and added to a ready
- * list, otherwise an error code defined in the file projdefs.h
- *
- * Example usage:
-   
- // Task to be created.
- void vTaskCode( void * pvParameters )
- {
-	 for( ;; )
-	 {
-		 // Task code goes here.
-	 }
- }
-
- // Function that creates a task.
- void vOtherFunction( void )
- {
- static uint8_t ucParameterToPass;
- TaskHandle_t xHandle = NULL;
-
-	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
-	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
-	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
-	 // the new task attempts to access it.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
-     configASSERT( xHandle );
-
-	 // Use the handle to delete the task.
-     if( xHandle != NULL )
-     {
-	     vTaskDelete( xHandle );
-     }
- }
-   

- * \defgroup xTaskCreate xTaskCreate
- * \ingroup Tasks
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
-							const char * const pcName,	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-							const configSTACK_DEPTH_TYPE usStackDepth,
-							void * const pvParameters,
-							UBaseType_t uxPriority,
-							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * task. h
- *
- TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
-								 const char * const pcName,
-								 uint32_t ulStackDepth,
-								 void *pvParameters,
-								 UBaseType_t uxPriority,
-								 StackType_t *pxStackBuffer,
-								 StaticTask_t *pxTaskBuffer );

- *
- * Create a new task and add it to the list of tasks that are ready to run.
- *
- * Internally, within the FreeRTOS implementation, tasks use two blocks of
- * memory.  The first block is used to hold the task's data structures.  The
- * second block is used by the task as its stack.  If a task is created using
- * xTaskCreate() then both blocks of memory are automatically dynamically
- * allocated inside the xTaskCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a task is created using
- * xTaskCreateStatic() then the application writer must provide the required
- * memory.  xTaskCreateStatic() therefore allows a task to be created without
- * using any dynamic memory allocation.
- *
- * @param pvTaskCode Pointer to the task entry function.  Tasks
- * must be implemented to never return (i.e. continuous loop).
- *
- * @param pcName A descriptive name for the task.  This is mainly used to
- * facilitate debugging.  The maximum length of the string is defined by
- * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
- *
- * @param ulStackDepth The size of the task stack specified as the number of
- * variables the stack can hold - not the number of bytes.  For example, if
- * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
- * will be allocated for stack storage.
- *
- * @param pvParameters Pointer that will be used as the parameter for the task
- * being created.
- *
- * @param uxPriority The priority at which the task will run.
- *
- * @param pxStackBuffer Must point to a StackType_t array that has at least
- * ulStackDepth indexes - the array will then be used as the task's stack,
- * removing the need for the stack to be allocated dynamically.
- *
- * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
- * then be used to hold the task's data structures, removing the need for the
- * memory to be allocated dynamically.
- *
- * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
- * be created and a handle to the created task is returned.  If either
- * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
- * NULL is returned.
- *
- * Example usage:
-   
-
-    // Dimensions the buffer that the task being created will use as its stack.
-    // NOTE:  This is the number of words the stack will hold, not the number of
-    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
-    // then 400 bytes (100 * 32-bits) will be allocated.
-    #define STACK_SIZE 200
-
-    // Structure that will hold the TCB of the task being created.
-    StaticTask_t xTaskBuffer;
-
-    // Buffer that the task being created will use as its stack.  Note this is
-    // an array of StackType_t variables.  The size of StackType_t is dependent on
-    // the RTOS port.
-    StackType_t xStack[ STACK_SIZE ];
-
-    // Function that implements the task being created.
-    void vTaskCode( void * pvParameters )
-    {
-        // The parameter value is expected to be 1 as 1 is passed in the
-        // pvParameters value in the call to xTaskCreateStatic().
-        configASSERT( ( uint32_t ) pvParameters == 1UL );
-
-        for( ;; )
-        {
-            // Task code goes here.
-        }
-    }
-
-    // Function that creates a task.
-    void vOtherFunction( void )
-    {
-        TaskHandle_t xHandle = NULL;
-
-        // Create the task without using any dynamic memory allocation.
-        xHandle = xTaskCreateStatic(
-                      vTaskCode,       // Function that implements the task.
-                      "NAME",          // Text name for the task.
-                      STACK_SIZE,      // Stack size in words, not bytes.
-                      ( void * ) 1,    // Parameter passed into the task.
-                      tskIDLE_PRIORITY,// Priority at which the task is created.
-                      xStack,          // Array to use as the task's stack.
-                      &xTaskBuffer );  // Variable to hold the task's data structure.
-
-        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
-        // been created, and xHandle will be the task's handle.  Use the handle
-        // to suspend the task.
-        vTaskSuspend( xHandle );
-    }
-   

- * \defgroup xTaskCreateStatic xTaskCreateStatic
- * \ingroup Tasks
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
-									const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-									const uint32_t ulStackDepth,
-									void * const pvParameters,
-									UBaseType_t uxPriority,
-									StackType_t * const puxStackBuffer,
-									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * task. h
- *
- BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

- *
- * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
- *
- * xTaskCreateRestricted() should only be used in systems that include an MPU
- * implementation.
- *
- * Create a new task and add it to the list of tasks that are ready to run.
- * The function parameters define the memory regions and associated access
- * permissions allocated to the task.
- *
- * See xTaskCreateRestrictedStatic() for a version that does not use any
- * dynamic memory allocation.
- *
- * @param pxTaskDefinition Pointer to a structure that contains a member
- * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
- * documentation) plus an optional stack buffer and the memory region
- * definitions.
- *
- * @param pxCreatedTask Used to pass back a handle by which the created task
- * can be referenced.
- *
- * @return pdPASS if the task was successfully created and added to a ready
- * list, otherwise an error code defined in the file projdefs.h
- *
- * Example usage:
-   
-// Create an TaskParameters_t structure that defines the task to be created.
-static const TaskParameters_t xCheckTaskParameters =
-{
-	vATask,		// pvTaskCode - the function that implements the task.
-	"ATask",	// pcName - just a text name for the task to assist debugging.
-	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
-	NULL,		// pvParameters - passed into the task function as the function parameters.
-	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
-	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
-
-	// xRegions - Allocate up to three separate memory regions for access by
-	// the task, with appropriate access permissions.  Different processors have
-	// different memory alignment requirements - refer to the FreeRTOS documentation
-	// for full information.
-	{
-		// Base address					Length	Parameters
-        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
-        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
-        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
-	}
-};
-
-int main( void )
-{
-TaskHandle_t xHandle;
-
-	// Create a task from the const structure defined above.  The task handle
-	// is requested (the second parameter is not NULL) but in this case just for
-	// demonstration purposes as its not actually used.
-	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
-
-	// Start the scheduler.
-	vTaskStartScheduler();
-
-	// Will only get here if there was insufficient memory to create the idle
-	// and/or timer task.
-	for( ;; );
-}
-   

- * \defgroup xTaskCreateRestricted xTaskCreateRestricted
- * \ingroup Tasks
- */
-#if( portUSING_MPU_WRAPPERS == 1 )
-	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * task. h
- *
- BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

- *
- * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
- *
- * xTaskCreateRestrictedStatic() should only be used in systems that include an
- * MPU implementation.
- *
- * Internally, within the FreeRTOS implementation, tasks use two blocks of
- * memory.  The first block is used to hold the task's data structures.  The
- * second block is used by the task as its stack.  If a task is created using
- * xTaskCreateRestricted() then the stack is provided by the application writer,
- * and the memory used to hold the task's data structure is automatically
- * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
- * is created using xTaskCreateRestrictedStatic() then the application writer
- * must provide the memory used to hold the task's data structures too.
- * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
- * created without using any dynamic memory allocation.
- *
- * @param pxTaskDefinition Pointer to a structure that contains a member
- * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
- * documentation) plus an optional stack buffer and the memory region
- * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
- * contains an additional member, which is used to point to a variable of type
- * StaticTask_t - which is then used to hold the task's data structure.
- *
- * @param pxCreatedTask Used to pass back a handle by which the created task
- * can be referenced.
- *
- * @return pdPASS if the task was successfully created and added to a ready
- * list, otherwise an error code defined in the file projdefs.h
- *
- * Example usage:
-   
-// Create an TaskParameters_t structure that defines the task to be created.
-// The StaticTask_t variable is only included in the structure when
-// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
-// be used to force the variable into the RTOS kernel's privileged data area.
-static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
-static const TaskParameters_t xCheckTaskParameters =
-{
-	vATask,		// pvTaskCode - the function that implements the task.
-	"ATask",	// pcName - just a text name for the task to assist debugging.
-	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
-	NULL,		// pvParameters - passed into the task function as the function parameters.
-	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
-	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
-
-	// xRegions - Allocate up to three separate memory regions for access by
-	// the task, with appropriate access permissions.  Different processors have
-	// different memory alignment requirements - refer to the FreeRTOS documentation
-	// for full information.
-	{
-		// Base address					Length	Parameters
-        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
-        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
-        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
-	}
-
-	&xTaskBuffer; // Holds the task's data structure.
-};
-
-int main( void )
-{
-TaskHandle_t xHandle;
-
-	// Create a task from the const structure defined above.  The task handle
-	// is requested (the second parameter is not NULL) but in this case just for
-	// demonstration purposes as its not actually used.
-	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
-
-	// Start the scheduler.
-	vTaskStartScheduler();
-
-	// Will only get here if there was insufficient memory to create the idle
-	// and/or timer task.
-	for( ;; );
-}
-   

- * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
- * \ingroup Tasks
- */
-#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * task. h
- *
- void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );

- *
- * Memory regions are assigned to a restricted task when the task is created by
- * a call to xTaskCreateRestricted().  These regions can be redefined using
- * vTaskAllocateMPURegions().
- *
- * @param xTask The handle of the task being updated.
- *
- * @param xRegions A pointer to an MemoryRegion_t structure that contains the
- * new memory region definitions.
- *
- * Example usage:
-   
-// Define an array of MemoryRegion_t structures that configures an MPU region
-// allowing read/write access for 1024 bytes starting at the beginning of the
-// ucOneKByte array.  The other two of the maximum 3 definable regions are
-// unused so set to zero.
-static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
-{
-	// Base address		Length		Parameters
-	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
-	{ 0,				0,			0 },
-	{ 0,				0,			0 }
-};
-
-void vATask( void *pvParameters )
-{
-	// This task was created such that it has access to certain regions of
-	// memory as defined by the MPU configuration.  At some point it is
-	// desired that these MPU regions are replaced with that defined in the
-	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
-	// for this purpose.  NULL is used as the task handle to indicate that this
-	// function should modify the MPU regions of the calling task.
-	vTaskAllocateMPURegions( NULL, xAltRegions );
-
-	// Now the task can continue its function, but from this point on can only
-	// access its stack and the ucOneKByte array (unless any other statically
-	// defined or shared regions have been declared elsewhere).
-}
-   

- * \defgroup xTaskCreateRestricted xTaskCreateRestricted
- * \ingroup Tasks
- */
-void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskDelete( TaskHandle_t xTask );

- *
- * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Remove a task from the RTOS real time kernel's management.  The task being
- * deleted will be removed from all ready, blocked, suspended and event lists.
- *
- * NOTE:  The idle task is responsible for freeing the kernel allocated
- * memory from tasks that have been deleted.  It is therefore important that
- * the idle task is not starved of microcontroller processing time if your
- * application makes any calls to vTaskDelete ().  Memory allocated by the
- * task code is not automatically freed, and should be freed before the task
- * is deleted.
- *
- * See the demo application file death.c for sample code that utilises
- * vTaskDelete ().
- *
- * @param xTask The handle of the task to be deleted.  Passing NULL will
- * cause the calling task to be deleted.
- *
- * Example usage:
-   
- void vOtherFunction( void )
- {
- TaskHandle_t xHandle;
-
-	 // Create the task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // Use the handle to delete the task.
-	 vTaskDelete( xHandle );
- }
-   

- * \defgroup vTaskDelete vTaskDelete
- * \ingroup Tasks
- */
-void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------
- * TASK CONTROL API
- *----------------------------------------------------------*/
-
-/**
- * task. h
- * 
void vTaskDelay( const TickType_t xTicksToDelay );

- *
- * Delay a task for a given number of ticks.  The actual time that the
- * task remains blocked depends on the tick rate.  The constant
- * portTICK_PERIOD_MS can be used to calculate real time from the tick
- * rate - with the resolution of one tick period.
- *
- * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- *
- * vTaskDelay() specifies a time at which the task wishes to unblock relative to
- * the time at which vTaskDelay() is called.  For example, specifying a block
- * period of 100 ticks will cause the task to unblock 100 ticks after
- * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
- * of controlling the frequency of a periodic task as the path taken through the
- * code, as well as other task and interrupt activity, will effect the frequency
- * at which vTaskDelay() gets called and therefore the time at which the task
- * next executes.  See vTaskDelayUntil() for an alternative API function designed
- * to facilitate fixed frequency execution.  It does this by specifying an
- * absolute time (rather than a relative time) at which the calling task should
- * unblock.
- *
- * @param xTicksToDelay The amount of time, in tick periods, that
- * the calling task should block.
- *
- * Example usage:
-
- void vTaskFunction( void * pvParameters )
- {
- // Block for 500ms.
- const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
-
-	 for( ;; )
-	 {
-		 // Simply toggle the LED every 500ms, blocking between each toggle.
-		 vToggleLED();
-		 vTaskDelay( xDelay );
-	 }
- }
-
- * \defgroup vTaskDelay vTaskDelay
- * \ingroup TaskCtrl
- */
-void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );

- *
- * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Delay a task until a specified time.  This function can be used by periodic
- * tasks to ensure a constant execution frequency.
- *
- * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
- * cause a task to block for the specified number of ticks from the time vTaskDelay () is
- * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
- * execution frequency as the time between a task starting to execute and that task
- * calling vTaskDelay () may not be fixed [the task may take a different path though the
- * code between calls, or may get interrupted or preempted a different number of times
- * each time it executes].
- *
- * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
- * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
- * unblock.
- *
- * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
- * rate - with the resolution of one tick period.
- *
- * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
- * task was last unblocked.  The variable must be initialised with the current time
- * prior to its first use (see the example below).  Following this the variable is
- * automatically updated within vTaskDelayUntil ().
- *
- * @param xTimeIncrement The cycle time period.  The task will be unblocked at
- * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
- * same xTimeIncrement parameter value will cause the task to execute with
- * a fixed interface period.
- *
- * Example usage:
-   
- // Perform an action every 10 ticks.
- void vTaskFunction( void * pvParameters )
- {
- TickType_t xLastWakeTime;
- const TickType_t xFrequency = 10;
-
-	 // Initialise the xLastWakeTime variable with the current time.
-	 xLastWakeTime = xTaskGetTickCount ();
-	 for( ;; )
-	 {
-		 // Wait for the next cycle.
-		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
-
-		 // Perform action here.
-	 }
- }
-   

- * \defgroup vTaskDelayUntil vTaskDelayUntil
- * \ingroup TaskCtrl
- */
-void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
BaseType_t xTaskAbortDelay( TaskHandle_t xTask );

- *
- * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
- * function to be available.
- *
- * A task will enter the Blocked state when it is waiting for an event.  The
- * event it is waiting for can be a temporal event (waiting for a time), such
- * as when vTaskDelay() is called, or an event on an object, such as when
- * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
- * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
- * task will leave the Blocked state, and return from whichever function call
- * placed the task into the Blocked state.
- *
- * @param xTask The handle of the task to remove from the Blocked state.
- *
- * @return If the task referenced by xTask was not in the Blocked state then
- * pdFAIL is returned.  Otherwise pdPASS is returned.
- *
- * \defgroup xTaskAbortDelay xTaskAbortDelay
- * \ingroup TaskCtrl
- */
-BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );

- *
- * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Obtain the priority of any task.
- *
- * @param xTask Handle of the task to be queried.  Passing a NULL
- * handle results in the priority of the calling task being returned.
- *
- * @return The priority of xTask.
- *
- * Example usage:
-   
- void vAFunction( void )
- {
- TaskHandle_t xHandle;
-
-	 // Create a task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // ...
-
-	 // Use the handle to obtain the priority of the created task.
-	 // It was created with tskIDLE_PRIORITY, but may have changed
-	 // it itself.
-	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
-	 {
-		 // The task has changed it's priority.
-	 }
-
-	 // ...
-
-	 // Is our priority higher than the created task?
-	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
-	 {
-		 // Our priority (obtained using NULL handle) is higher.
-	 }
- }
-   

- * \defgroup uxTaskPriorityGet uxTaskPriorityGet
- * \ingroup TaskCtrl
- */
-UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );

- *
- * A version of uxTaskPriorityGet() that can be used from an ISR.
- */
-UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
eTaskState eTaskGetState( TaskHandle_t xTask );

- *
- * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Obtain the state of any task.  States are encoded by the eTaskState
- * enumerated type.
- *
- * @param xTask Handle of the task to be queried.
- *
- * @return The state of xTask at the time the function was called.  Note the
- * state of the task might change between the function being called, and the
- * functions return value being tested by the calling task.
- */
-eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );

- *
- * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
- * available.  See the configuration section for more information.
- *
- * Populates a TaskStatus_t structure with information about a task.
- *
- * @param xTask Handle of the task being queried.  If xTask is NULL then
- * information will be returned about the calling task.
- *
- * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
- * filled with information about the task referenced by the handle passed using
- * the xTask parameter.
- *
- * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
- * the stack high water mark of the task being queried.  Calculating the stack
- * high water mark takes a relatively long time, and can make the system
- * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
- * allow the high water mark checking to be skipped.  The high watermark value
- * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
- * not set to pdFALSE;
- *
- * @param eState The TaskStatus_t structure contains a member to report the
- * state of the task being queried.  Obtaining the task state is not as fast as
- * a simple assignment - so the eState parameter is provided to allow the state
- * information to be omitted from the TaskStatus_t structure.  To obtain state
- * information then set eState to eInvalid - otherwise the value passed in
- * eState will be reported as the task state in the TaskStatus_t structure.
- *
- * Example usage:
-   
- void vAFunction( void )
- {
- TaskHandle_t xHandle;
- TaskStatus_t xTaskDetails;
-
-    // Obtain the handle of a task from its name.
-    xHandle = xTaskGetHandle( "Task_Name" );
-
-    // Check the handle is not NULL.
-    configASSERT( xHandle );
-
-    // Use the handle to obtain further information about the task.
-    vTaskGetInfo( xHandle,
-                  &xTaskDetails,
-                  pdTRUE, // Include the high water mark in xTaskDetails.
-                  eInvalid ); // Include the task state in xTaskDetails.
- }
-   

- * \defgroup vTaskGetInfo vTaskGetInfo
- * \ingroup TaskCtrl
- */
-void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );

- *
- * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Set the priority of any task.
- *
- * A context switch will occur before the function returns if the priority
- * being set is higher than the currently executing task.
- *
- * @param xTask Handle to the task for which the priority is being set.
- * Passing a NULL handle results in the priority of the calling task being set.
- *
- * @param uxNewPriority The priority to which the task will be set.
- *
- * Example usage:
-   
- void vAFunction( void )
- {
- TaskHandle_t xHandle;
-
-	 // Create a task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // ...
-
-	 // Use the handle to raise the priority of the created task.
-	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
-
-	 // ...
-
-	 // Use a NULL handle to raise our priority to the same value.
-	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
- }
-   

- * \defgroup vTaskPrioritySet vTaskPrioritySet
- * \ingroup TaskCtrl
- */
-void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskSuspend( TaskHandle_t xTaskToSuspend );

- *
- * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Suspend any task.  When suspended a task will never get any microcontroller
- * processing time, no matter what its priority.
- *
- * Calls to vTaskSuspend are not accumulative -
- * i.e. calling vTaskSuspend () twice on the same task still only requires one
- * call to vTaskResume () to ready the suspended task.
- *
- * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
- * handle will cause the calling task to be suspended.
- *
- * Example usage:
-   
- void vAFunction( void )
- {
- TaskHandle_t xHandle;
-
-	 // Create a task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // ...
-
-	 // Use the handle to suspend the created task.
-	 vTaskSuspend( xHandle );
-
-	 // ...
-
-	 // The created task will not run during this period, unless
-	 // another task calls vTaskResume( xHandle ).
-
-	 //...
-
-
-	 // Suspend ourselves.
-	 vTaskSuspend( NULL );
-
-	 // We cannot get here unless another task calls vTaskResume
-	 // with our handle as the parameter.
- }
-   

- * \defgroup vTaskSuspend vTaskSuspend
- * \ingroup TaskCtrl
- */
-void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskResume( TaskHandle_t xTaskToResume );

- *
- * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Resumes a suspended task.
- *
- * A task that has been suspended by one or more calls to vTaskSuspend ()
- * will be made available for running again by a single call to
- * vTaskResume ().
- *
- * @param xTaskToResume Handle to the task being readied.
- *
- * Example usage:
-   
- void vAFunction( void )
- {
- TaskHandle_t xHandle;
-
-	 // Create a task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // ...
-
-	 // Use the handle to suspend the created task.
-	 vTaskSuspend( xHandle );
-
-	 // ...
-
-	 // The created task will not run during this period, unless
-	 // another task calls vTaskResume( xHandle ).
-
-	 //...
-
-
-	 // Resume the suspended task ourselves.
-	 vTaskResume( xHandle );
-
-	 // The created task will once again get microcontroller processing
-	 // time in accordance with its priority within the system.
- }
-   

- * \defgroup vTaskResume vTaskResume
- * \ingroup TaskCtrl
- */
-void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void xTaskResumeFromISR( TaskHandle_t xTaskToResume );

- *
- * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
- * available.  See the configuration section for more information.
- *
- * An implementation of vTaskResume() that can be called from within an ISR.
- *
- * A task that has been suspended by one or more calls to vTaskSuspend ()
- * will be made available for running again by a single call to
- * xTaskResumeFromISR ().
- *
- * xTaskResumeFromISR() should not be used to synchronise a task with an
- * interrupt if there is a chance that the interrupt could arrive prior to the
- * task being suspended - as this can lead to interrupts being missed. Use of a
- * semaphore as a synchronisation mechanism would avoid this eventuality.
- *
- * @param xTaskToResume Handle to the task being readied.
- *
- * @return pdTRUE if resuming the task should result in a context switch,
- * otherwise pdFALSE. This is used by the ISR to determine if a context switch
- * may be required following the ISR.
- *
- * \defgroup vTaskResumeFromISR vTaskResumeFromISR
- * \ingroup TaskCtrl
- */
-BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------
- * SCHEDULER CONTROL
- *----------------------------------------------------------*/
-
-/**
- * task. h
- * 
void vTaskStartScheduler( void );

- *
- * Starts the real time kernel tick processing.  After calling the kernel
- * has control over which tasks are executed and when.
- *
- * See the demo application file main.c for an example of creating
- * tasks and starting the kernel.
- *
- * Example usage:
-   
- void vAFunction( void )
- {
-	 // Create at least one task before starting the kernel.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-	 // Start the real time kernel with preemption.
-	 vTaskStartScheduler ();
-
-	 // Will not get here unless a task calls vTaskEndScheduler ()
- }
-   

- *
- * \defgroup vTaskStartScheduler vTaskStartScheduler
- * \ingroup SchedulerControl
- */
-void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskEndScheduler( void );

- *
- * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
- * in place of DOS, implements this function.
- *
- * Stops the real time kernel tick.  All created tasks will be automatically
- * deleted and multitasking (either preemptive or cooperative) will
- * stop.  Execution then resumes from the point where vTaskStartScheduler ()
- * was called, as if vTaskStartScheduler () had just returned.
- *
- * See the demo application file main. c in the demo/PC directory for an
- * example that uses vTaskEndScheduler ().
- *
- * vTaskEndScheduler () requires an exit function to be defined within the
- * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
- * performs hardware specific operations such as stopping the kernel tick.
- *
- * vTaskEndScheduler () will cause all of the resources allocated by the
- * kernel to be freed - but will not free resources allocated by application
- * tasks.
- *
- * Example usage:
-   
- void vTaskCode( void * pvParameters )
- {
-	 for( ;; )
-	 {
-		 // Task code goes here.
-
-		 // At some point we want to end the real time kernel processing
-		 // so call ...
-		 vTaskEndScheduler ();
-	 }
- }
-
- void vAFunction( void )
- {
-	 // Create at least one task before starting the kernel.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-	 // Start the real time kernel with preemption.
-	 vTaskStartScheduler ();
-
-	 // Will only get here when the vTaskCode () task has called
-	 // vTaskEndScheduler ().  When we get here we are back to single task
-	 // execution.
- }
-   

- *
- * \defgroup vTaskEndScheduler vTaskEndScheduler
- * \ingroup SchedulerControl
- */
-void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskSuspendAll( void );

- *
- * Suspends the scheduler without disabling interrupts.  Context switches will
- * not occur while the scheduler is suspended.
- *
- * After calling vTaskSuspendAll () the calling task will continue to execute
- * without risk of being swapped out until a call to xTaskResumeAll () has been
- * made.
- *
- * API functions that have the potential to cause a context switch (for example,
- * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
- * is suspended.
- *
- * Example usage:
-   
- void vTask1( void * pvParameters )
- {
-	 for( ;; )
-	 {
-		 // Task code goes here.
-
-		 // ...
-
-		 // At some point the task wants to perform a long operation during
-		 // which it does not want to get swapped out.  It cannot use
-		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-		 // operation may cause interrupts to be missed - including the
-		 // ticks.
-
-		 // Prevent the real time kernel swapping out the task.
-		 vTaskSuspendAll ();
-
-		 // Perform the operation here.  There is no need to use critical
-		 // sections as we have all the microcontroller processing time.
-		 // During this time interrupts will still operate and the kernel
-		 // tick count will be maintained.
-
-		 // ...
-
-		 // The operation is complete.  Restart the kernel.
-		 xTaskResumeAll ();
-	 }
- }
-   

- * \defgroup vTaskSuspendAll vTaskSuspendAll
- * \ingroup SchedulerControl
- */
-void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
BaseType_t xTaskResumeAll( void );

- *
- * Resumes scheduler activity after it was suspended by a call to
- * vTaskSuspendAll().
- *
- * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
- * that were previously suspended by a call to vTaskSuspend().
- *
- * @return If resuming the scheduler caused a context switch then pdTRUE is
- *		  returned, otherwise pdFALSE is returned.
- *
- * Example usage:
-   
- void vTask1( void * pvParameters )
- {
-	 for( ;; )
-	 {
-		 // Task code goes here.
-
-		 // ...
-
-		 // At some point the task wants to perform a long operation during
-		 // which it does not want to get swapped out.  It cannot use
-		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-		 // operation may cause interrupts to be missed - including the
-		 // ticks.
-
-		 // Prevent the real time kernel swapping out the task.
-		 vTaskSuspendAll ();
-
-		 // Perform the operation here.  There is no need to use critical
-		 // sections as we have all the microcontroller processing time.
-		 // During this time interrupts will still operate and the real
-		 // time kernel tick count will be maintained.
-
-		 // ...
-
-		 // The operation is complete.  Restart the kernel.  We want to force
-		 // a context switch - but there is no point if resuming the scheduler
-		 // caused a context switch already.
-		 if( !xTaskResumeAll () )
-		 {
-			  taskYIELD ();
-		 }
-	 }
- }
-   

- * \defgroup xTaskResumeAll xTaskResumeAll
- * \ingroup SchedulerControl
- */
-BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------
- * TASK UTILITIES
- *----------------------------------------------------------*/
-
-/**
- * task. h
- * 
TickType_t xTaskGetTickCount( void );

- *
- * @return The count of ticks since vTaskStartScheduler was called.
- *
- * \defgroup xTaskGetTickCount xTaskGetTickCount
- * \ingroup TaskUtils
- */
-TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
TickType_t xTaskGetTickCountFromISR( void );

- *
- * @return The count of ticks since vTaskStartScheduler was called.
- *
- * This is a version of xTaskGetTickCount() that is safe to be called from an
- * ISR - provided that TickType_t is the natural word size of the
- * microcontroller being used or interrupt nesting is either not supported or
- * not being used.
- *
- * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
- * \ingroup TaskUtils
- */
-TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
uint16_t uxTaskGetNumberOfTasks( void );

- *
- * @return The number of tasks that the real time kernel is currently managing.
- * This includes all ready, blocked and suspended tasks.  A task that
- * has been deleted but not yet freed by the idle task will also be
- * included in the count.
- *
- * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
- * \ingroup TaskUtils
- */
-UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
char *pcTaskGetName( TaskHandle_t xTaskToQuery );

- *
- * @return The text (human readable) name of the task referenced by the handle
- * xTaskToQuery.  A task can query its own name by either passing in its own
- * handle, or by setting xTaskToQuery to NULL.
- *
- * \defgroup pcTaskGetName pcTaskGetName
- * \ingroup TaskUtils
- */
-char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * task. h
- * 
TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );

- *
- * NOTE:  This function takes a relatively long time to complete and should be
- * used sparingly.
- *
- * @return The handle of the task that has the human readable name pcNameToQuery.
- * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
- * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
- *
- * \defgroup pcTaskGetHandle pcTaskGetHandle
- * \ingroup TaskUtils
- */
-TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * task.h
- * 
UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );

- *
- * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
- * this function to be available.
- *
- * Returns the high water mark of the stack associated with xTask.  That is,
- * the minimum free stack space there has been (in words, so on a 32 bit machine
- * a value of 1 means 4 bytes) since the task started.  The smaller the returned
- * number the closer the task has come to overflowing its stack.
- *
- * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
- * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
- * user to determine the return type.  It gets around the problem of the value
- * overflowing on 8-bit types without breaking backward compatibility for
- * applications that expect an 8-bit return type.
- *
- * @param xTask Handle of the task associated with the stack to be checked.
- * Set xTask to NULL to check the stack of the calling task.
- *
- * @return The smallest amount of free stack space there has been (in words, so
- * actual spaces on the stack rather than bytes) since the task referenced by
- * xTask was created.
- */
-UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task.h
- * 
configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );

- *
- * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
- * this function to be available.
- *
- * Returns the high water mark of the stack associated with xTask.  That is,
- * the minimum free stack space there has been (in words, so on a 32 bit machine
- * a value of 1 means 4 bytes) since the task started.  The smaller the returned
- * number the closer the task has come to overflowing its stack.
- *
- * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
- * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
- * user to determine the return type.  It gets around the problem of the value
- * overflowing on 8-bit types without breaking backward compatibility for
- * applications that expect an 8-bit return type.
- *
- * @param xTask Handle of the task associated with the stack to be checked.
- * Set xTask to NULL to check the stack of the calling task.
- *
- * @return The smallest amount of free stack space there has been (in words, so
- * actual spaces on the stack rather than bytes) since the task referenced by
- * xTask was created.
- */
-configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task.h
- * 
uint8_t* pxTaskGetStackStart( TaskHandle_t xTask);

- *
- * INCLUDE_pxTaskGetStackStart must be set to 1 in FreeRTOSConfig.h for
- * this function to be available.
- *
- * Returns the start of the stack associated with xTask.  That is,
- * the highest stack memory address on architectures where the stack grows down
- * from high memory, and the lowest memory address on architectures where the
- * stack grows up from low memory.
- *
- * @param xTask Handle of the task associated with the stack returned.
- * Set xTask to NULL to return the stack of the calling task.
- *
- * @return A pointer to the start of the stack.
- */
-uint8_t* pxTaskGetStackStart( TaskHandle_t xTask) PRIVILEGED_FUNCTION;
-
-/* When using trace macros it is sometimes necessary to include task.h before
-FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
-so the following two prototypes will cause a compilation error.  This can be
-fixed by simply guarding against the inclusion of these two prototypes unless
-they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
-constant. */
-#ifdef configUSE_APPLICATION_TASK_TAG
-	#if configUSE_APPLICATION_TASK_TAG == 1
-		/**
-		 * task.h
-		 * 
void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );

-		 *
-		 * Sets pxHookFunction to be the task hook function used by the task xTask.
-		 * Passing xTask as NULL has the effect of setting the calling tasks hook
-		 * function.
-		 */
-		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
-
-		/**
-		 * task.h
-		 * 
void xTaskGetApplicationTaskTag( TaskHandle_t xTask );

-		 *
-		 * Returns the pxHookFunction value assigned to the task xTask.  Do not
-		 * call from an interrupt service routine - call
-		 * xTaskGetApplicationTaskTagFromISR() instead.
-		 */
-		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-		/**
-		 * task.h
-		 * 
void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );

-		 *
-		 * Returns the pxHookFunction value assigned to the task xTask.  Can
-		 * be called from an interrupt service routine.
-		 */
-		TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
-#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
-
-#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
-
-	/* Each task contains an array of pointers that is dimensioned by the
-	configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
-	kernel does not use the pointers itself, so the application writer can use
-	the pointers for any purpose they wish.  The following two functions are
-	used to set and query a pointer respectively. */
-	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
-	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/**
- * task.h
- * 
BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );

- *
- * Calls the hook function associated with xTask.  Passing xTask as NULL has
- * the effect of calling the Running tasks (the calling task) hook function.
- *
- * pvParameter is passed to the hook function for the task to interpret as it
- * wants.  The return value is the value returned by the task hook function
- * registered by the user.
- */
-BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
-
-/**
- * xTaskGetIdleTaskHandle() is only available if
- * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
- *
- * Simply returns the handle of the idle task.  It is not valid to call
- * xTaskGetIdleTaskHandle() before the scheduler has been started.
- */
-TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
-
-/**
- * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
- * uxTaskGetSystemState() to be available.
- *
- * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
- * the system.  TaskStatus_t structures contain, among other things, members
- * for the task handle, task name, task priority, task state, and total amount
- * of run time consumed by the task.  See the TaskStatus_t structure
- * definition in this file for the full member list.
- *
- * NOTE:  This function is intended for debugging use only as its use results in
- * the scheduler remaining suspended for an extended period.
- *
- * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
- * The array must contain at least one TaskStatus_t structure for each task
- * that is under the control of the RTOS.  The number of tasks under the control
- * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
- *
- * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
- * parameter.  The size is specified as the number of indexes in the array, or
- * the number of TaskStatus_t structures contained in the array, not by the
- * number of bytes in the array.
- *
- * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
- * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
- * total run time (as defined by the run time stats clock, see
- * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
- * pulTotalRunTime can be set to NULL to omit the total run time information.
- *
- * @return The number of TaskStatus_t structures that were populated by
- * uxTaskGetSystemState().  This should equal the number returned by the
- * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
- * in the uxArraySize parameter was too small.
- *
- * Example usage:
-   
-    // This example demonstrates how a human readable table of run time stats
-	// information is generated from raw data provided by uxTaskGetSystemState().
-	// The human readable table is written to pcWriteBuffer
-	void vTaskGetRunTimeStats( char *pcWriteBuffer )
-	{
-	TaskStatus_t *pxTaskStatusArray;
-	volatile UBaseType_t uxArraySize, x;
-	uint32_t ulTotalRunTime, ulStatsAsPercentage;
-
-		// Make sure the write buffer does not contain a string.
-		*pcWriteBuffer = 0x00;
-
-		// Take a snapshot of the number of tasks in case it changes while this
-		// function is executing.
-		uxArraySize = uxTaskGetNumberOfTasks();
-
-		// Allocate a TaskStatus_t structure for each task.  An array could be
-		// allocated statically at compile time.
-		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
-
-		if( pxTaskStatusArray != NULL )
-		{
-			// Generate raw status information about each task.
-			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
-
-			// For percentage calculations.
-			ulTotalRunTime /= 100UL;
-
-			// Avoid divide by zero errors.
-			if( ulTotalRunTime > 0 )
-			{
-				// For each populated position in the pxTaskStatusArray array,
-				// format the raw data as human readable ASCII data
-				for( x = 0; x < uxArraySize; x++ )
-				{
-					// What percentage of the total run time has the task used?
-					// This will always be rounded down to the nearest integer.
-					// ulTotalRunTimeDiv100 has already been divided by 100.
-					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
-
-					if( ulStatsAsPercentage > 0UL )
-					{
-						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
-					}
-					else
-					{
-						// If the percentage is zero here then the task has
-						// consumed less than 1% of the total run time.
-						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
-					}
-
-					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
-				}
-			}
-
-			// The array is no longer needed, free the memory it consumes.
-			vPortFree( pxTaskStatusArray );
-		}
-	}
-	

- */
-UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskList( char *pcWriteBuffer );

- *
- * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
- * both be defined as 1 for this function to be available.  See the
- * configuration section of the FreeRTOS.org website for more information.
- *
- * NOTE 1: This function will disable interrupts for its duration.  It is
- * not intended for normal application runtime use but as a debug aid.
- *
- * Lists all the current tasks, along with their current state and stack
- * usage high water mark.
- *
- * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
- * suspended ('S').
- *
- * PLEASE NOTE:
- *
- * This function is provided for convenience only, and is used by many of the
- * demo applications.  Do not consider it to be part of the scheduler.
- *
- * vTaskList() calls uxTaskGetSystemState(), then formats part of the
- * uxTaskGetSystemState() output into a human readable table that displays task
- * names, states and stack usage.
- *
- * vTaskList() has a dependency on the sprintf() C library function that might
- * bloat the code size, use a lot of stack, and provide different results on
- * different platforms.  An alternative, tiny, third party, and limited
- * functionality implementation of sprintf() is provided in many of the
- * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
- * printf-stdarg.c does not provide a full snprintf() implementation!).
- *
- * It is recommended that production systems call uxTaskGetSystemState()
- * directly to get access to raw stats data, rather than indirectly through a
- * call to vTaskList().
- *
- * @param pcWriteBuffer A buffer into which the above mentioned details
- * will be written, in ASCII form.  This buffer is assumed to be large
- * enough to contain the generated report.  Approximately 40 bytes per
- * task should be sufficient.
- *
- * \defgroup vTaskList vTaskList
- * \ingroup TaskUtils
- */
-void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * task. h
- * 
void vTaskGetRunTimeStats( char *pcWriteBuffer );

- *
- * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
- * must both be defined as 1 for this function to be available.  The application
- * must also then provide definitions for
- * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
- * to configure a peripheral timer/counter and return the timers current count
- * value respectively.  The counter should be at least 10 times the frequency of
- * the tick count.
- *
- * NOTE 1: This function will disable interrupts for its duration.  It is
- * not intended for normal application runtime use but as a debug aid.
- *
- * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
- * accumulated execution time being stored for each task.  The resolution
- * of the accumulated time value depends on the frequency of the timer
- * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
- * Calling vTaskGetRunTimeStats() writes the total execution time of each
- * task into a buffer, both as an absolute count value and as a percentage
- * of the total system execution time.
- *
- * NOTE 2:
- *
- * This function is provided for convenience only, and is used by many of the
- * demo applications.  Do not consider it to be part of the scheduler.
- *
- * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
- * uxTaskGetSystemState() output into a human readable table that displays the
- * amount of time each task has spent in the Running state in both absolute and
- * percentage terms.
- *
- * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
- * that might bloat the code size, use a lot of stack, and provide different
- * results on different platforms.  An alternative, tiny, third party, and
- * limited functionality implementation of sprintf() is provided in many of the
- * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
- * printf-stdarg.c does not provide a full snprintf() implementation!).
- *
- * It is recommended that production systems call uxTaskGetSystemState() directly
- * to get access to raw stats data, rather than indirectly through a call to
- * vTaskGetRunTimeStats().
- *
- * @param pcWriteBuffer A buffer into which the execution times will be
- * written, in ASCII form.  This buffer is assumed to be large enough to
- * contain the generated report.  Approximately 40 bytes per task should
- * be sufficient.
- *
- * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
- * \ingroup TaskUtils
- */
-void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
-* task. h
-* 
TickType_t xTaskGetIdleRunTimeCounter( void );

-*
-* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
-* must both be defined as 1 for this function to be available.  The application
-* must also then provide definitions for
-* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
-* to configure a peripheral timer/counter and return the timers current count
-* value respectively.  The counter should be at least 10 times the frequency of
-* the tick count.
-*
-* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
-* accumulated execution time being stored for each task.  The resolution
-* of the accumulated time value depends on the frequency of the timer
-* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
-* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
-* execution time of each task into a buffer, xTaskGetIdleRunTimeCounter()
-* returns the total execution time of just the idle task.
-*
-* @return The total run time of the idle task.  This is the amount of time the
-* idle task has actually been executing.  The unit of time is dependent on the
-* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
-* portGET_RUN_TIME_COUNTER_VALUE() macros.
-*
-* \defgroup xTaskGetIdleRunTimeCounter xTaskGetIdleRunTimeCounter
-* \ingroup TaskUtils
-*/
-TickType_t xTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );

- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * A notification sent to a task will remain pending until it is cleared by the
- * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
- * already in the Blocked state to wait for a notification when the notification
- * arrives then the task will automatically be removed from the Blocked state
- * (unblocked) and the notification cleared.
- *
- * A task can use xTaskNotifyWait() to [optionally] block to wait for a
- * notification to be pending, or ulTaskNotifyTake() to [optionally] block
- * to wait for its notification value to have a non-zero value.  The task does
- * not consume any CPU time while it is in the Blocked state.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @param ulValue Data that can be sent with the notification.  How the data is
- * used depends on the value of the eAction parameter.
- *
- * @param eAction Specifies how the notification updates the task's notification
- * value, if at all.  Valid values for eAction are as follows:
- *
- * eSetBits -
- * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
- * always returns pdPASS in this case.
- *
- * eIncrement -
- * The task's notification value is incremented.  ulValue is not used and
- * xTaskNotify() always returns pdPASS in this case.
- *
- * eSetValueWithOverwrite -
- * The task's notification value is set to the value of ulValue, even if the
- * task being notified had not yet processed the previous notification (the
- * task already had a notification pending).  xTaskNotify() always returns
- * pdPASS in this case.
- *
- * eSetValueWithoutOverwrite -
- * If the task being notified did not already have a notification pending then
- * the task's notification value is set to ulValue and xTaskNotify() will
- * return pdPASS.  If the task being notified already had a notification
- * pending then no action is performed and pdFAIL is returned.
- *
- * eNoAction -
- * The task receives a notification without its notification value being
- * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
- * this case.
- *
- *  pulPreviousNotificationValue -
- *  Can be used to pass out the subject task's notification value before any
- *  bits are modified by the notify function.
- *
- * @return Dependent on the value of eAction.  See the description of the
- * eAction parameter.
- *
- * \defgroup xTaskNotify xTaskNotify
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
-#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
-#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
-
-/**
- * task. h
- * 
BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );

- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * A version of xTaskNotify() that can be used from an interrupt service routine
- * (ISR).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * A notification sent to a task will remain pending until it is cleared by the
- * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
- * already in the Blocked state to wait for a notification when the notification
- * arrives then the task will automatically be removed from the Blocked state
- * (unblocked) and the notification cleared.
- *
- * A task can use xTaskNotifyWait() to [optionally] block to wait for a
- * notification to be pending, or ulTaskNotifyTake() to [optionally] block
- * to wait for its notification value to have a non-zero value.  The task does
- * not consume any CPU time while it is in the Blocked state.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @param ulValue Data that can be sent with the notification.  How the data is
- * used depends on the value of the eAction parameter.
- *
- * @param eAction Specifies how the notification updates the task's notification
- * value, if at all.  Valid values for eAction are as follows:
- *
- * eSetBits -
- * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
- * always returns pdPASS in this case.
- *
- * eIncrement -
- * The task's notification value is incremented.  ulValue is not used and
- * xTaskNotify() always returns pdPASS in this case.
- *
- * eSetValueWithOverwrite -
- * The task's notification value is set to the value of ulValue, even if the
- * task being notified had not yet processed the previous notification (the
- * task already had a notification pending).  xTaskNotify() always returns
- * pdPASS in this case.
- *
- * eSetValueWithoutOverwrite -
- * If the task being notified did not already have a notification pending then
- * the task's notification value is set to ulValue and xTaskNotify() will
- * return pdPASS.  If the task being notified already had a notification
- * pending then no action is performed and pdFAIL is returned.
- *
- * eNoAction -
- * The task receives a notification without its notification value being
- * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
- * this case.
- *
- * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
- * task to which the notification was sent to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently running task.  If
- * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
- * be requested before the interrupt is exited.  How a context switch is
- * requested from an ISR is dependent on the port - see the documentation page
- * for the port in use.
- *
- * @return Dependent on the value of eAction.  See the description of the
- * eAction parameter.
- *
- * \defgroup xTaskNotify xTaskNotify
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
-#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
-
-/**
- * task. h
- * 
BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );

- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * A notification sent to a task will remain pending until it is cleared by the
- * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
- * already in the Blocked state to wait for a notification when the notification
- * arrives then the task will automatically be removed from the Blocked state
- * (unblocked) and the notification cleared.
- *
- * A task can use xTaskNotifyWait() to [optionally] block to wait for a
- * notification to be pending, or ulTaskNotifyTake() to [optionally] block
- * to wait for its notification value to have a non-zero value.  The task does
- * not consume any CPU time while it is in the Blocked state.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
- * will be cleared in the calling task's notification value before the task
- * checks to see if any notifications are pending, and optionally blocks if no
- * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
- * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
- * the effect of resetting the task's notification value to 0.  Setting
- * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
- *
- * @param ulBitsToClearOnExit If a notification is pending or received before
- * the calling task exits the xTaskNotifyWait() function then the task's
- * notification value (see the xTaskNotify() API function) is passed out using
- * the pulNotificationValue parameter.  Then any bits that are set in
- * ulBitsToClearOnExit will be cleared in the task's notification value (note
- * *pulNotificationValue is set before any bits are cleared).  Setting
- * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
- * (if limits.h is not included) will have the effect of resetting the task's
- * notification value to 0 before the function exits.  Setting
- * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
- * when the function exits (in which case the value passed out in
- * pulNotificationValue will match the task's notification value).
- *
- * @param pulNotificationValue Used to pass the task's notification value out
- * of the function.  Note the value passed out will not be effected by the
- * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
- *
- * @param xTicksToWait The maximum amount of time that the task should wait in
- * the Blocked state for a notification to be received, should a notification
- * not already be pending when xTaskNotifyWait() was called.  The task
- * will not consume any processing time while it is in the Blocked state.  This
- * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
- * used to convert a time specified in milliseconds to a time specified in
- * ticks.
- *
- * @return If a notification was received (including notifications that were
- * already pending when xTaskNotifyWait was called) then pdPASS is
- * returned.  Otherwise pdFAIL is returned.
- *
- * \defgroup xTaskNotifyWait xTaskNotifyWait
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );

- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
- * to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * xTaskNotifyGive() is a helper macro intended for use when task notifications
- * are used as light weight and faster binary or counting semaphore equivalents.
- * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
- * the equivalent action that instead uses a task notification is
- * xTaskNotifyGive().
- *
- * When task notifications are being used as a binary or counting semaphore
- * equivalent then the task being notified should wait for the notification
- * using the ulTaskNotificationTake() API function rather than the
- * xTaskNotifyWait() API function.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
- * eAction parameter set to eIncrement - so pdPASS is always returned.
- *
- * \defgroup xTaskNotifyGive xTaskNotifyGive
- * \ingroup TaskNotifications
- */
-#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
-
-/**
- * task. h
- * 
void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
- * to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * A version of xTaskNotifyGive() that can be called from an interrupt service
- * routine (ISR).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * vTaskNotifyGiveFromISR() is intended for use when task notifications are
- * used as light weight and faster binary or counting semaphore equivalents.
- * Actual FreeRTOS semaphores are given from an ISR using the
- * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
- * a task notification is vTaskNotifyGiveFromISR().
- *
- * When task notifications are being used as a binary or counting semaphore
- * equivalent then the task being notified should wait for the notification
- * using the ulTaskNotificationTake() API function rather than the
- * xTaskNotifyWait() API function.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
- * task to which the notification was sent to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently running task.  If
- * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
- * should be requested before the interrupt is exited.  How a context switch is
- * requested from an ISR is dependent on the port - see the documentation page
- * for the port in use.
- *
- * \defgroup xTaskNotifyWait xTaskNotifyWait
- * \ingroup TaskNotifications
- */
-void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );

- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * ulTaskNotifyTake() is intended for use when a task notification is used as a
- * faster and lighter weight binary or counting semaphore alternative.  Actual
- * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
- * equivalent action that instead uses a task notification is
- * ulTaskNotifyTake().
- *
- * When a task is using its notification value as a binary or counting semaphore
- * other tasks should send notifications to it using the xTaskNotifyGive()
- * macro, or xTaskNotify() function with the eAction parameter set to
- * eIncrement.
- *
- * ulTaskNotifyTake() can either clear the task's notification value to
- * zero on exit, in which case the notification value acts like a binary
- * semaphore, or decrement the task's notification value on exit, in which case
- * the notification value acts like a counting semaphore.
- *
- * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
- * the task's notification value to be non-zero.  The task does not consume any
- * CPU time while it is in the Blocked state.
- *
- * Where as xTaskNotifyWait() will return when a notification is pending,
- * ulTaskNotifyTake() will return when the task's notification value is
- * not zero.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
- * notification value is decremented when the function exits.  In this way the
- * notification value acts like a counting semaphore.  If xClearCountOnExit is
- * not pdFALSE then the task's notification value is cleared to zero when the
- * function exits.  In this way the notification value acts like a binary
- * semaphore.
- *
- * @param xTicksToWait The maximum amount of time that the task should wait in
- * the Blocked state for the task's notification value to be greater than zero,
- * should the count not already be greater than zero when
- * ulTaskNotifyTake() was called.  The task will not consume any processing
- * time while it is in the Blocked state.  This is specified in kernel ticks,
- * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
- * specified in milliseconds to a time specified in ticks.
- *
- * @return The task's notification count before it is either cleared to zero or
- * decremented (see the xClearCountOnExit parameter).
- *
- * \defgroup ulTaskNotifyTake ulTaskNotifyTake
- * \ingroup TaskNotifications
- */
-uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );

- *
- * If the notification state of the task referenced by the handle xTask is
- * eNotified, then set the task's notification state to eNotWaitingNotification.
- * The task's notification value is not altered.  Set xTask to NULL to clear the
- * notification state of the calling task.
- *
- * @return pdTRUE if the task's notification state was set to
- * eNotWaitingNotification, otherwise pdFALSE.
- * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
-
-/*-----------------------------------------------------------
- * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
- *----------------------------------------------------------*/
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
- * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
- * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * Called from the real time kernel tick (either preemptive or cooperative),
- * this increments the tick count and checks if any tasks that are blocked
- * for a finite period required removing from a blocked list and placing on
- * a ready list.  If a non-zero value is returned then a context switch is
- * required because either:
- *   + A task was removed from a blocked list because its timeout had expired,
- *     or
- *   + Time slicing is in use and there is a task of equal priority to the
- *     currently running task.
- */
-BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * Removes the calling task from the ready list and places it both
- * on the list of tasks waiting for a particular event, and the
- * list of delayed tasks.  The task will be removed from both lists
- * and replaced on the ready list should either the event occur (and
- * there be no higher priority tasks waiting on the same event) or
- * the delay period expires.
- *
- * The 'unordered' version replaces the event list item value with the
- * xItemValue value, and inserts the list item at the end of the list.
- *
- * The 'ordered' version uses the existing event list item value (which is the
- * owning tasks priority) to insert the list item into the event list is task
- * priority order.
- *
- * @param pxEventList The list containing tasks that are blocked waiting
- * for the event to occur.
- *
- * @param xItemValue The item value to use for the event list item when the
- * event list is not ordered by task priority.
- *
- * @param xTicksToWait The maximum amount of time that the task should wait
- * for the event to occur.  This is specified in kernel ticks,the constant
- * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
- * period.
- */
-void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * This function performs nearly the same function as vTaskPlaceOnEventList().
- * The difference being that this function does not permit tasks to block
- * indefinitely, whereas vTaskPlaceOnEventList() does.
- *
- */
-void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * Removes a task from both the specified event list and the list of blocked
- * tasks, and places it on a ready queue.
- *
- * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
- * if either an event occurs to unblock a task, or the block timeout period
- * expires.
- *
- * xTaskRemoveFromEventList() is used when the event list is in task priority
- * order.  It removes the list item from the head of the event list as that will
- * have the highest priority owning task of all the tasks on the event list.
- * vTaskRemoveFromUnorderedEventList() is used when the event list is not
- * ordered and the event list items hold something other than the owning tasks
- * priority.  In this case the event list item value is updated to the value
- * passed in the xItemValue parameter.
- *
- * @return pdTRUE if the task being removed has a higher priority than the task
- * making the call, otherwise pdFALSE.
- */
-BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
-void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
- * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
- * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * Sets the pointer to the current TCB to the TCB of the highest priority task
- * that is ready to run.
- */
-portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
-
-/*
- * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
- * THE EVENT BITS MODULE.
- */
-TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Return the handle of the calling task.
- */
-TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Capture the current time status for future reference.
- */
-void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
-
-/*
- * Compare the time status now with that previously captured to see if the
- * timeout has expired.
- */
-BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
-
-/*
- * Shortcut used by the queue implementation to prevent unnecessary call to
- * taskYIELD();
- */
-void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Returns the scheduler state as taskSCHEDULER_RUNNING,
- * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
- */
-BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Raises the priority of the mutex holder to that of the calling task should
- * the mutex holder have a priority less than the calling task.
- */
-BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
-
-/*
- * Set the priority of a task back to its proper priority in the case that it
- * inherited a higher priority while it was holding a semaphore.
- */
-BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
-
-/*
- * If a higher priority task attempting to obtain a mutex caused a lower
- * priority task to inherit the higher priority task's priority - but the higher
- * priority task then timed out without obtaining the mutex, then the lower
- * priority task will disinherit the priority again - but only down as far as
- * the highest priority task that is still waiting for the mutex (if there were
- * more than one task waiting for the mutex).
- */
-void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
-
-/*
- * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
- */
-UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/*
- * Set the uxTaskNumber of the task referenced by the xTask parameter to
- * uxHandle.
- */
-void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
-
-/*
- * Only available when configUSE_TICKLESS_IDLE is set to 1.
- * If tickless mode is being used, or a low power mode is implemented, then
- * the tick interrupt will not execute during idle periods.  When this is the
- * case, the tick count value maintained by the scheduler needs to be kept up
- * to date with the actual execution time by being skipped forward by a time
- * equal to the idle period.
- */
-void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
-
-/*
- * Only available when configUSE_TICKLESS_IDLE is set to 1.
- * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
- * specific sleep function to determine if it is ok to proceed with the sleep,
- * and if it is ok to proceed, if it is ok to sleep indefinitely.
- *
- * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
- * called with the scheduler suspended, not from within a critical section.  It
- * is therefore possible for an interrupt to request a context switch between
- * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
- * entered.  eTaskConfirmSleepModeStatus() should be called from a short
- * critical section between the timer being stopped and the sleep mode being
- * entered to ensure it is ok to proceed into the sleep mode.
- */
-eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
-
-/*
- * For internal use only.  Increment the mutex held count when a mutex is
- * taken and return the handle of the task that has taken the mutex.
- */
-TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
-
-/*
- * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
- * section.
- */
-void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
-
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* INC_TASK_H */
-
-
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/timers.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/timers.h
deleted file mode 100644
index 5abb7f1..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/include/timers.h
+++ /dev/null
@@ -1,1295 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef TIMERS_H
-#define TIMERS_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h must appear in source files before include timers.h"
-#endif
-
-/*lint -save -e537 This headers are only multiply included if the application code
-happens to also be including task.h. */
-#include "task.h"
-/*lint -restore */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * MACROS AND DEFINITIONS
- *----------------------------------------------------------*/
-
-/* IDs for commands that can be sent/received on the timer queue.  These are to
-be used solely through the macros that make up the public software timer API,
-as defined below.  The commands that are sent from interrupts must use the
-highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
-or interrupt version of the queue send function should be used. */
-#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
-#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
-#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
-#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
-#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
-#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
-#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
-#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
-
-#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
-#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
-#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
-#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
-#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
-
-
-/**
- * Type by which software timers are referenced.  For example, a call to
- * xTimerCreate() returns an TimerHandle_t variable that can then be used to
- * reference the subject timer in calls to other software timer API functions
- * (for example, xTimerStart(), xTimerReset(), etc.).
- */
-struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
-typedef struct tmrTimerControl * TimerHandle_t;
-
-/*
- * Defines the prototype to which timer callback functions must conform.
- */
-typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
-
-/*
- * Defines the prototype to which functions used with the
- * xTimerPendFunctionCallFromISR() function must conform.
- */
-typedef void (*PendedFunction_t)( void *, uint32_t );
-
-/**
- * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
- * 								TickType_t xTimerPeriodInTicks,
- * 								UBaseType_t uxAutoReload,
- * 								void * pvTimerID,
- * 								TimerCallbackFunction_t pxCallbackFunction );
- *
- * Creates a new software timer instance, and returns a handle by which the
- * created software timer can be referenced.
- *
- * Internally, within the FreeRTOS implementation, software timers use a block
- * of memory, in which the timer data structure is stored.  If a software timer
- * is created using xTimerCreate() then the required memory is automatically
- * dynamically allocated inside the xTimerCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a software timer is created using
- * xTimerCreateStatic() then the application writer must provide the memory that
- * will get used by the software timer.  xTimerCreateStatic() therefore allows a
- * software timer to be created without using any dynamic memory allocation.
- *
- * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
- * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
- * xTimerChangePeriodFromISR() API functions can all be used to transition a
- * timer into the active state.
- *
- * @param pcTimerName A text name that is assigned to the timer.  This is done
- * purely to assist debugging.  The kernel itself only ever references a timer
- * by its handle, and never by its name.
- *
- * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
- * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
- * has been specified in milliseconds.  For example, if the timer must expire
- * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
- * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
- * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
- * equal to 1000.
- *
- * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
- * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
- * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
- * enter the dormant state after it expires.
- *
- * @param pvTimerID An identifier that is assigned to the timer being created.
- * Typically this would be used in the timer callback function to identify which
- * timer expired when the same callback function is assigned to more than one
- * timer.
- *
- * @param pxCallbackFunction The function to call when the timer expires.
- * Callback functions must have the prototype defined by TimerCallbackFunction_t,
- * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
- *
- * @return If the timer is successfully created then a handle to the newly
- * created timer is returned.  If the timer cannot be created (because either
- * there is insufficient FreeRTOS heap remaining to allocate the timer
- * structures, or the timer period was set to 0) then NULL is returned.
- *
- * Example usage:
- * @verbatim
- * #define NUM_TIMERS 5
- *
- * // An array to hold handles to the created timers.
- * TimerHandle_t xTimers[ NUM_TIMERS ];
- *
- * // An array to hold a count of the number of times each timer expires.
- * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
- *
- * // Define a callback function that will be used by multiple timer instances.
- * // The callback function does nothing but count the number of times the
- * // associated timer expires, and stop the timer once the timer has expired
- * // 10 times.
- * void vTimerCallback( TimerHandle_t pxTimer )
- * {
- * int32_t lArrayIndex;
- * const int32_t xMaxExpiryCountBeforeStopping = 10;
- *
- * 	   // Optionally do something if the pxTimer parameter is NULL.
- * 	   configASSERT( pxTimer );
- *
- *     // Which timer expired?
- *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
- *
- *     // Increment the number of times that pxTimer has expired.
- *     lExpireCounters[ lArrayIndex ] += 1;
- *
- *     // If the timer has expired 10 times then stop it from running.
- *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
- *     {
- *         // Do not use a block time if calling a timer API function from a
- *         // timer callback function, as doing so could cause a deadlock!
- *         xTimerStop( pxTimer, 0 );
- *     }
- * }
- *
- * void main( void )
- * {
- * int32_t x;
- *
- *     // Create then start some timers.  Starting the timers before the scheduler
- *     // has been started means the timers will start running immediately that
- *     // the scheduler starts.
- *     for( x = 0; x < NUM_TIMERS; x++ )
- *     {
- *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
- *                                         ( 100 * x ),   // The timer period in ticks.
- *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
- *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
- *                                         vTimerCallback // Each timer calls the same callback when it expires.
- *                                     );
- *
- *         if( xTimers[ x ] == NULL )
- *         {
- *             // The timer was not created.
- *         }
- *         else
- *         {
- *             // Start the timer.  No block time is specified, and even if one was
- *             // it would be ignored because the scheduler has not yet been
- *             // started.
- *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
- *             {
- *                 // The timer could not be set into the Active state.
- *             }
- *         }
- *     }
- *
- *     // ...
- *     // Create tasks here.
- *     // ...
- *
- *     // Starting the scheduler will start the timers running as they have already
- *     // been set into the active state.
- *     vTaskStartScheduler();
- *
- *     // Should not reach here.
- *     for( ;; );
- * }
- * @endverbatim
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-								const TickType_t xTimerPeriodInTicks,
-								const UBaseType_t uxAutoReload,
-								void * const pvTimerID,
-								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
- * 									TickType_t xTimerPeriodInTicks,
- * 									UBaseType_t uxAutoReload,
- * 									void * pvTimerID,
- * 									TimerCallbackFunction_t pxCallbackFunction,
- *									StaticTimer_t *pxTimerBuffer );
- *
- * Creates a new software timer instance, and returns a handle by which the
- * created software timer can be referenced.
- *
- * Internally, within the FreeRTOS implementation, software timers use a block
- * of memory, in which the timer data structure is stored.  If a software timer
- * is created using xTimerCreate() then the required memory is automatically
- * dynamically allocated inside the xTimerCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a software timer is created using
- * xTimerCreateStatic() then the application writer must provide the memory that
- * will get used by the software timer.  xTimerCreateStatic() therefore allows a
- * software timer to be created without using any dynamic memory allocation.
- *
- * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
- * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
- * xTimerChangePeriodFromISR() API functions can all be used to transition a
- * timer into the active state.
- *
- * @param pcTimerName A text name that is assigned to the timer.  This is done
- * purely to assist debugging.  The kernel itself only ever references a timer
- * by its handle, and never by its name.
- *
- * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
- * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
- * has been specified in milliseconds.  For example, if the timer must expire
- * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
- * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
- * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
- * equal to 1000.
- *
- * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
- * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
- * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
- * enter the dormant state after it expires.
- *
- * @param pvTimerID An identifier that is assigned to the timer being created.
- * Typically this would be used in the timer callback function to identify which
- * timer expired when the same callback function is assigned to more than one
- * timer.
- *
- * @param pxCallbackFunction The function to call when the timer expires.
- * Callback functions must have the prototype defined by TimerCallbackFunction_t,
- * which is "void vCallbackFunction( TimerHandle_t xTimer );".
- *
- * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
- * will be then be used to hold the software timer's data structures, removing
- * the need for the memory to be allocated dynamically.
- *
- * @return If the timer is created then a handle to the created timer is
- * returned.  If pxTimerBuffer was NULL then NULL is returned.
- *
- * Example usage:
- * @verbatim
- *
- * // The buffer used to hold the software timer's data structure.
- * static StaticTimer_t xTimerBuffer;
- *
- * // A variable that will be incremented by the software timer's callback
- * // function.
- * UBaseType_t uxVariableToIncrement = 0;
- *
- * // A software timer callback function that increments a variable passed to
- * // it when the software timer was created.  After the 5th increment the
- * // callback function stops the software timer.
- * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
- * {
- * UBaseType_t *puxVariableToIncrement;
- * BaseType_t xReturned;
- *
- *     // Obtain the address of the variable to increment from the timer ID.
- *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
- *
- *     // Increment the variable to show the timer callback has executed.
- *     ( *puxVariableToIncrement )++;
- *
- *     // If this callback has executed the required number of times, stop the
- *     // timer.
- *     if( *puxVariableToIncrement == 5 )
- *     {
- *         // This is called from a timer callback so must not block.
- *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
- *     }
- * }
- *
- *
- * void main( void )
- * {
- *     // Create the software time.  xTimerCreateStatic() has an extra parameter
- *     // than the normal xTimerCreate() API function.  The parameter is a pointer
- *     // to the StaticTimer_t structure that will hold the software timer
- *     // structure.  If the parameter is passed as NULL then the structure will be
- *     // allocated dynamically, just as if xTimerCreate() had been called.
- *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
- *                                  xTimerPeriod,     // The period of the timer in ticks.
- *                                  pdTRUE,           // This is an auto-reload timer.
- *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
- *                                  prvTimerCallback, // The function to execute when the timer expires.
- *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
- *
- *     // The scheduler has not started yet so a block time is not used.
- *     xReturned = xTimerStart( xTimer, 0 );
- *
- *     // ...
- *     // Create tasks here.
- *     // ...
- *
- *     // Starting the scheduler will start the timers running as they have already
- *     // been set into the active state.
- *     vTaskStartScheduler();
- *
- *     // Should not reach here.
- *     for( ;; );
- * }
- * @endverbatim
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-										const TickType_t xTimerPeriodInTicks,
-										const UBaseType_t uxAutoReload,
-										void * const pvTimerID,
-										TimerCallbackFunction_t pxCallbackFunction,
-										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * void *pvTimerGetTimerID( TimerHandle_t xTimer );
- *
- * Returns the ID assigned to the timer.
- *
- * IDs are assigned to timers using the pvTimerID parameter of the call to
- * xTimerCreated() that was used to create the timer, and by calling the
- * vTimerSetTimerID() API function.
- *
- * If the same callback function is assigned to multiple timers then the timer
- * ID can be used as time specific (timer local) storage.
- *
- * @param xTimer The timer being queried.
- *
- * @return The ID assigned to the timer being queried.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- */
-void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
- * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
- *
- * Sets the ID assigned to the timer.
- *
- * IDs are assigned to timers using the pvTimerID parameter of the call to
- * xTimerCreated() that was used to create the timer.
- *
- * If the same callback function is assigned to multiple timers then the timer
- * ID can be used as time specific (timer local) storage.
- *
- * @param xTimer The timer being updated.
- *
- * @param pvNewID The ID to assign to the timer.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- */
-void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
-
-/**
- * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
- *
- * Queries a timer to see if it is active or dormant.
- *
- * A timer will be dormant if:
- *     1) It has been created but not started, or
- *     2) It is an expired one-shot timer that has not been restarted.
- *
- * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
- * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
- * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
- * active state.
- *
- * @param xTimer The timer being queried.
- *
- * @return pdFALSE will be returned if the timer is dormant.  A value other than
- * pdFALSE will be returned if the timer is active.
- *
- * Example usage:
- * @verbatim
- * // This function assumes xTimer has already been created.
- * void vAFunction( TimerHandle_t xTimer )
- * {
- *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
- *     {
- *         // xTimer is active, do something.
- *     }
- *     else
- *     {
- *         // xTimer is not active, do something else.
- *     }
- * }
- * @endverbatim
- */
-BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
- * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
- *
- * Simply returns the handle of the timer service/daemon task.  It it not valid
- * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
- */
-TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
-
-/**
- * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerStart() starts a timer that was previously created using the
- * xTimerCreate() API function.  If the timer had already been started and was
- * already in the active state, then xTimerStart() has equivalent functionality
- * to the xTimerReset() API function.
- *
- * Starting a timer ensures the timer is in the active state.  If the timer
- * is not stopped, deleted, or reset in the mean time, the callback function
- * associated with the timer will get called 'n' ticks after xTimerStart() was
- * called, where 'n' is the timers defined period.
- *
- * It is valid to call xTimerStart() before the scheduler has been started, but
- * when this is done the timer will not actually start until the scheduler is
- * started, and the timers expiry time will be relative to when the scheduler is
- * started, not relative to when xTimerStart() was called.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
- * to be available.
- *
- * @param xTimer The handle of the timer being started/restarted.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the start command to be successfully
- * sent to the timer command queue, should the queue already be full when
- * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
- * before the scheduler is started.
- *
- * @return pdFAIL will be returned if the start command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system, although the
- * timers expiry time is relative to when xTimerStart() is actually called.  The
- * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- *
- */
-#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerStop() stops a timer that was previously started using either of the
- * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
- * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
- *
- * Stopping a timer ensures the timer is not in the active state.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
- * to be available.
- *
- * @param xTimer The handle of the timer being stopped.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the stop command to be successfully
- * sent to the timer command queue, should the queue already be full when
- * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
- * before the scheduler is started.
- *
- * @return pdFAIL will be returned if the stop command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system.  The timer
- * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- *
- */
-#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
- *										TickType_t xNewPeriod,
- *										TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerChangePeriod() changes the period of a timer that was previously
- * created using the xTimerCreate() API function.
- *
- * xTimerChangePeriod() can be called to change the period of an active or
- * dormant state timer.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for
- * xTimerChangePeriod() to be available.
- *
- * @param xTimer The handle of the timer that is having its period changed.
- *
- * @param xNewPeriod The new period for xTimer. Timer periods are specified in
- * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
- * that has been specified in milliseconds.  For example, if the timer must
- * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
- * if the timer must expire after 500ms, then xNewPeriod can be set to
- * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
- * or equal to 1000.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the change period command to be
- * successfully sent to the timer command queue, should the queue already be
- * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
- * xTimerChangePeriod() is called before the scheduler is started.
- *
- * @return pdFAIL will be returned if the change period command could not be
- * sent to the timer command queue even after xTicksToWait ticks had passed.
- * pdPASS will be returned if the command was successfully sent to the timer
- * command queue.  When the command is actually processed will depend on the
- * priority of the timer service/daemon task relative to other tasks in the
- * system.  The timer service/daemon task priority is set by the
- * configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This function assumes xTimer has already been created.  If the timer
- * // referenced by xTimer is already active when it is called, then the timer
- * // is deleted.  If the timer referenced by xTimer is not active when it is
- * // called, then the period of the timer is set to 500ms and the timer is
- * // started.
- * void vAFunction( TimerHandle_t xTimer )
- * {
- *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
- *     {
- *         // xTimer is already active - delete it.
- *         xTimerDelete( xTimer );
- *     }
- *     else
- *     {
- *         // xTimer is not active, change its period to 500ms.  This will also
- *         // cause the timer to start.  Block for a maximum of 100 ticks if the
- *         // change period command cannot immediately be sent to the timer
- *         // command queue.
- *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
- *         {
- *             // The command was successfully sent.
- *         }
- *         else
- *         {
- *             // The command could not be sent, even after waiting for 100 ticks
- *             // to pass.  Take appropriate action here.
- *         }
- *     }
- * }
- * @endverbatim
- */
- #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerDelete() deletes a timer that was previously created using the
- * xTimerCreate() API function.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for
- * xTimerDelete() to be available.
- *
- * @param xTimer The handle of the timer being deleted.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the delete command to be
- * successfully sent to the timer command queue, should the queue already be
- * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
- * is called before the scheduler is started.
- *
- * @return pdFAIL will be returned if the delete command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system.  The timer
- * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- *
- * See the xTimerChangePeriod() API function example usage scenario.
- */
-#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerReset() re-starts a timer that was previously created using the
- * xTimerCreate() API function.  If the timer had already been started and was
- * already in the active state, then xTimerReset() will cause the timer to
- * re-evaluate its expiry time so that it is relative to when xTimerReset() was
- * called.  If the timer was in the dormant state then xTimerReset() has
- * equivalent functionality to the xTimerStart() API function.
- *
- * Resetting a timer ensures the timer is in the active state.  If the timer
- * is not stopped, deleted, or reset in the mean time, the callback function
- * associated with the timer will get called 'n' ticks after xTimerReset() was
- * called, where 'n' is the timers defined period.
- *
- * It is valid to call xTimerReset() before the scheduler has been started, but
- * when this is done the timer will not actually start until the scheduler is
- * started, and the timers expiry time will be relative to when the scheduler is
- * started, not relative to when xTimerReset() was called.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
- * to be available.
- *
- * @param xTimer The handle of the timer being reset/started/restarted.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the reset command to be successfully
- * sent to the timer command queue, should the queue already be full when
- * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
- * before the scheduler is started.
- *
- * @return pdFAIL will be returned if the reset command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system, although the
- * timers expiry time is relative to when xTimerStart() is actually called.  The
- * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- * @verbatim
- * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
- * // without a key being pressed, then the LCD back-light is switched off.  In
- * // this case, the timer is a one-shot timer.
- *
- * TimerHandle_t xBacklightTimer = NULL;
- *
- * // The callback function assigned to the one-shot timer.  In this case the
- * // parameter is not used.
- * void vBacklightTimerCallback( TimerHandle_t pxTimer )
- * {
- *     // The timer expired, therefore 5 seconds must have passed since a key
- *     // was pressed.  Switch off the LCD back-light.
- *     vSetBacklightState( BACKLIGHT_OFF );
- * }
- *
- * // The key press event handler.
- * void vKeyPressEventHandler( char cKey )
- * {
- *     // Ensure the LCD back-light is on, then reset the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
- *     // if it cannot be sent immediately.
- *     vSetBacklightState( BACKLIGHT_ON );
- *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
- *     {
- *         // The reset command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // Perform the rest of the key processing here.
- * }
- *
- * void main( void )
- * {
- * int32_t x;
- *
- *     // Create then start the one-shot timer that is responsible for turning
- *     // the back-light off if no keys are pressed within a 5 second period.
- *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
- *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
- *                                     pdFALSE,                    // The timer is a one-shot timer.
- *                                     0,                          // The id is not used by the callback so can take any value.
- *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
- *                                   );
- *
- *     if( xBacklightTimer == NULL )
- *     {
- *         // The timer was not created.
- *     }
- *     else
- *     {
- *         // Start the timer.  No block time is specified, and even if one was
- *         // it would be ignored because the scheduler has not yet been
- *         // started.
- *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
- *         {
- *             // The timer could not be set into the Active state.
- *         }
- *     }
- *
- *     // ...
- *     // Create tasks here.
- *     // ...
- *
- *     // Starting the scheduler will start the timer running as it has already
- *     // been set into the active state.
- *     vTaskStartScheduler();
- *
- *     // Should not reach here.
- *     for( ;; );
- * }
- * @endverbatim
- */
-#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
- *									BaseType_t *pxHigherPriorityTaskWoken );
- *
- * A version of xTimerStart() that can be called from an interrupt service
- * routine.
- *
- * @param xTimer The handle of the timer being started/restarted.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerStartFromISR() writes a message to the timer
- * command queue, so has the potential to transition the timer service/daemon
- * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
- * timer service/daemon task to leave the Blocked state, and the timer service/
- * daemon task has a priority equal to or greater than the currently executing
- * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
- * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
- * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
- * be performed before the interrupt exits.
- *
- * @return pdFAIL will be returned if the start command could not be sent to
- * the timer command queue.  pdPASS will be returned if the command was
- * successfully sent to the timer command queue.  When the command is actually
- * processed will depend on the priority of the timer service/daemon task
- * relative to other tasks in the system, although the timers expiry time is
- * relative to when xTimerStartFromISR() is actually called.  The timer
- * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This scenario assumes xBacklightTimer has already been created.  When a
- * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
- * // without a key being pressed, then the LCD back-light is switched off.  In
- * // this case, the timer is a one-shot timer, and unlike the example given for
- * // the xTimerReset() function, the key press event handler is an interrupt
- * // service routine.
- *
- * // The callback function assigned to the one-shot timer.  In this case the
- * // parameter is not used.
- * void vBacklightTimerCallback( TimerHandle_t pxTimer )
- * {
- *     // The timer expired, therefore 5 seconds must have passed since a key
- *     // was pressed.  Switch off the LCD back-light.
- *     vSetBacklightState( BACKLIGHT_OFF );
- * }
- *
- * // The key press interrupt service routine.
- * void vKeyPressEventInterruptHandler( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // Ensure the LCD back-light is on, then restart the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  This is an interrupt service routine so can only
- *     // call FreeRTOS API functions that end in "FromISR".
- *     vSetBacklightState( BACKLIGHT_ON );
- *
- *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
- *     // as both cause the timer to re-calculate its expiry time.
- *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
- *     // declared (in this function).
- *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The start command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // Perform the rest of the key processing here.
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endverbatim
- */
-#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
-
-/**
- * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
- *									BaseType_t *pxHigherPriorityTaskWoken );
- *
- * A version of xTimerStop() that can be called from an interrupt service
- * routine.
- *
- * @param xTimer The handle of the timer being stopped.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerStopFromISR() writes a message to the timer
- * command queue, so has the potential to transition the timer service/daemon
- * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
- * timer service/daemon task to leave the Blocked state, and the timer service/
- * daemon task has a priority equal to or greater than the currently executing
- * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
- * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
- * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
- * be performed before the interrupt exits.
- *
- * @return pdFAIL will be returned if the stop command could not be sent to
- * the timer command queue.  pdPASS will be returned if the command was
- * successfully sent to the timer command queue.  When the command is actually
- * processed will depend on the priority of the timer service/daemon task
- * relative to other tasks in the system.  The timer service/daemon task
- * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This scenario assumes xTimer has already been created and started.  When
- * // an interrupt occurs, the timer should be simply stopped.
- *
- * // The interrupt service routine that stops the timer.
- * void vAnExampleInterruptServiceRoutine( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // The interrupt has occurred - simply stop the timer.
- *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
- *     // (within this function).  As this is an interrupt service routine, only
- *     // FreeRTOS API functions that end in "FromISR" can be used.
- *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The stop command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endverbatim
- */
-#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
-
-/**
- * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
- *										 TickType_t xNewPeriod,
- *										 BaseType_t *pxHigherPriorityTaskWoken );
- *
- * A version of xTimerChangePeriod() that can be called from an interrupt
- * service routine.
- *
- * @param xTimer The handle of the timer that is having its period changed.
- *
- * @param xNewPeriod The new period for xTimer. Timer periods are specified in
- * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
- * that has been specified in milliseconds.  For example, if the timer must
- * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
- * if the timer must expire after 500ms, then xNewPeriod can be set to
- * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
- * or equal to 1000.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
- * timer command queue, so has the potential to transition the timer service/
- * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
- * causes the timer service/daemon task to leave the Blocked state, and the
- * timer service/daemon task has a priority equal to or greater than the
- * currently executing task (the task that was interrupted), then
- * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
- * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
- * this value to pdTRUE then a context switch should be performed before the
- * interrupt exits.
- *
- * @return pdFAIL will be returned if the command to change the timers period
- * could not be sent to the timer command queue.  pdPASS will be returned if the
- * command was successfully sent to the timer command queue.  When the command
- * is actually processed will depend on the priority of the timer service/daemon
- * task relative to other tasks in the system.  The timer service/daemon task
- * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This scenario assumes xTimer has already been created and started.  When
- * // an interrupt occurs, the period of xTimer should be changed to 500ms.
- *
- * // The interrupt service routine that changes the period of xTimer.
- * void vAnExampleInterruptServiceRoutine( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // The interrupt has occurred - change the period of xTimer to 500ms.
- *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
- *     // (within this function).  As this is an interrupt service routine, only
- *     // FreeRTOS API functions that end in "FromISR" can be used.
- *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The command to change the timers period was not executed
- *         // successfully.  Take appropriate action here.
- *     }
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endverbatim
- */
-#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
-
-/**
- * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
- *									BaseType_t *pxHigherPriorityTaskWoken );
- *
- * A version of xTimerReset() that can be called from an interrupt service
- * routine.
- *
- * @param xTimer The handle of the timer that is to be started, reset, or
- * restarted.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerResetFromISR() writes a message to the timer
- * command queue, so has the potential to transition the timer service/daemon
- * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
- * timer service/daemon task to leave the Blocked state, and the timer service/
- * daemon task has a priority equal to or greater than the currently executing
- * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
- * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
- * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
- * be performed before the interrupt exits.
- *
- * @return pdFAIL will be returned if the reset command could not be sent to
- * the timer command queue.  pdPASS will be returned if the command was
- * successfully sent to the timer command queue.  When the command is actually
- * processed will depend on the priority of the timer service/daemon task
- * relative to other tasks in the system, although the timers expiry time is
- * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
- * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This scenario assumes xBacklightTimer has already been created.  When a
- * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
- * // without a key being pressed, then the LCD back-light is switched off.  In
- * // this case, the timer is a one-shot timer, and unlike the example given for
- * // the xTimerReset() function, the key press event handler is an interrupt
- * // service routine.
- *
- * // The callback function assigned to the one-shot timer.  In this case the
- * // parameter is not used.
- * void vBacklightTimerCallback( TimerHandle_t pxTimer )
- * {
- *     // The timer expired, therefore 5 seconds must have passed since a key
- *     // was pressed.  Switch off the LCD back-light.
- *     vSetBacklightState( BACKLIGHT_OFF );
- * }
- *
- * // The key press interrupt service routine.
- * void vKeyPressEventInterruptHandler( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // Ensure the LCD back-light is on, then reset the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  This is an interrupt service routine so can only
- *     // call FreeRTOS API functions that end in "FromISR".
- *     vSetBacklightState( BACKLIGHT_ON );
- *
- *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
- *     // as both cause the timer to re-calculate its expiry time.
- *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
- *     // declared (in this function).
- *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The reset command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // Perform the rest of the key processing here.
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endverbatim
- */
-#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
-
-
-/**
- * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
- *                                          void *pvParameter1,
- *                                          uint32_t ulParameter2,
- *                                          BaseType_t *pxHigherPriorityTaskWoken );
- *
- *
- * Used from application interrupt service routines to defer the execution of a
- * function to the RTOS daemon task (the timer service task, hence this function
- * is implemented in timers.c and is prefixed with 'Timer').
- *
- * Ideally an interrupt service routine (ISR) is kept as short as possible, but
- * sometimes an ISR either has a lot of processing to do, or needs to perform
- * processing that is not deterministic.  In these cases
- * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
- * to the RTOS daemon task.
- *
- * A mechanism is provided that allows the interrupt to return directly to the
- * task that will subsequently execute the pended callback function.  This
- * allows the callback function to execute contiguously in time with the
- * interrupt - just as if the callback had executed in the interrupt itself.
- *
- * @param xFunctionToPend The function to execute from the timer service/
- * daemon task.  The function must conform to the PendedFunction_t
- * prototype.
- *
- * @param pvParameter1 The value of the callback function's first parameter.
- * The parameter has a void * type to allow it to be used to pass any type.
- * For example, unsigned longs can be cast to a void *, or the void * can be
- * used to point to a structure.
- *
- * @param ulParameter2 The value of the callback function's second parameter.
- *
- * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
- * will result in a message being sent to the timer daemon task.  If the
- * priority of the timer daemon task (which is set using
- * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
- * the currently running task (the task the interrupt interrupted) then
- * *pxHigherPriorityTaskWoken will be set to pdTRUE within
- * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
- * requested before the interrupt exits.  For that reason
- * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
- * example code below.
- *
- * @return pdPASS is returned if the message was successfully sent to the
- * timer daemon task, otherwise pdFALSE is returned.
- *
- * Example usage:
- * @verbatim
- *
- *	// The callback function that will execute in the context of the daemon task.
- *  // Note callback functions must all use this same prototype.
- *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
- *	{
- *		BaseType_t xInterfaceToService;
- *
- *		// The interface that requires servicing is passed in the second
- *      // parameter.  The first parameter is not used in this case.
- *		xInterfaceToService = ( BaseType_t ) ulParameter2;
- *
- *		// ...Perform the processing here...
- *	}
- *
- *	// An ISR that receives data packets from multiple interfaces
- *  void vAnISR( void )
- *	{
- *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
- *
- *		// Query the hardware to determine which interface needs processing.
- *		xInterfaceToService = prvCheckInterfaces();
- *
- *      // The actual processing is to be deferred to a task.  Request the
- *      // vProcessInterface() callback function is executed, passing in the
- *		// number of the interface that needs processing.  The interface to
- *		// service is passed in the second parameter.  The first parameter is
- *		// not used in this case.
- *		xHigherPriorityTaskWoken = pdFALSE;
- *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
- *
- *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
- *		// switch should be requested.  The macro used is port specific and will
- *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
- *		// the documentation page for the port being used.
- *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
- *
- *	}
- * @endverbatim
- */
-BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
- /**
-  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
-  *                                    void *pvParameter1,
-  *                                    uint32_t ulParameter2,
-  *                                    TickType_t xTicksToWait );
-  *
-  *
-  * Used to defer the execution of a function to the RTOS daemon task (the timer
-  * service task, hence this function is implemented in timers.c and is prefixed
-  * with 'Timer').
-  *
-  * @param xFunctionToPend The function to execute from the timer service/
-  * daemon task.  The function must conform to the PendedFunction_t
-  * prototype.
-  *
-  * @param pvParameter1 The value of the callback function's first parameter.
-  * The parameter has a void * type to allow it to be used to pass any type.
-  * For example, unsigned longs can be cast to a void *, or the void * can be
-  * used to point to a structure.
-  *
-  * @param ulParameter2 The value of the callback function's second parameter.
-  *
-  * @param xTicksToWait Calling this function will result in a message being
-  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
-  * time the calling task should remain in the Blocked state (so not using any
-  * processing time) for space to become available on the timer queue if the
-  * queue is found to be full.
-  *
-  * @return pdPASS is returned if the message was successfully sent to the
-  * timer daemon task, otherwise pdFALSE is returned.
-  *
-  */
-BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * const char * const pcTimerGetName( TimerHandle_t xTimer );
- *
- * Returns the name that was assigned to a timer when the timer was created.
- *
- * @param xTimer The handle of the timer being queried.
- *
- * @return The name assigned to the timer specified by the xTimer parameter.
- */
-const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
- *
- * Updates a timer to be either an autoreload timer, in which case the timer
- * automatically resets itself each time it expires, or a one shot timer, in
- * which case the timer will only expire once unless it is manually restarted.
- *
- * @param xTimer The handle of the timer being updated.
- *
- * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
- * expire repeatedly with a frequency set by the timer's period (see the
- * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
- * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
- * enter the dormant state after it expires.
- */
-void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
-
-/**
- * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
- *
- * Returns the period of a timer.
- *
- * @param xTimer The handle of the timer being queried.
- *
- * @return The period of the timer in ticks.
- */
-TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
-* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
-*
-* Returns the time in ticks at which the timer will expire.  If this is less
-* than the current tick count then the expiry time has overflowed from the
-* current time.
-*
-* @param xTimer The handle of the timer being queried.
-*
-* @return If the timer is running then the time in ticks at which the timer
-* will next expire is returned.  If the timer is not running then the return
-* value is undefined.
-*/
-TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/*
- * Functions beyond this part are not part of the public API and are intended
- * for use by the kernel only.
- */
-BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
-BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-#if( configUSE_TRACE_FACILITY == 1 )
-	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
-	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* TIMERS_H */
-
-
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/list.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/list.c
deleted file mode 100644
index 9875b90..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/list.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#include 
-#include "FreeRTOS.h"
-#include "list.h"
-
-/*-----------------------------------------------------------
- * PUBLIC LIST API documented in list.h
- *----------------------------------------------------------*/
-
-void vListInitialise( List_t * const pxList )
-{
-	/* The list structure contains a list item which is used to mark the
-	end of the list.  To initialise the list the list end is inserted
-	as the only list entry. */
-	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-
-	/* The list end value is the highest possible value in the list to
-	ensure it remains at the end of the list. */
-	pxList->xListEnd.xItemValue = portMAX_DELAY;
-
-	/* The list end next and previous pointers point to itself so we know
-	when the list is empty. */
-	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-
-	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
-
-	/* Write known values into the list if
-	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
-	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
-}
-/*-----------------------------------------------------------*/
-
-void vListInitialiseItem( ListItem_t * const pxItem )
-{
-	/* Make sure the list item is not recorded as being on a list. */
-	pxItem->pxContainer = NULL;
-
-	/* Write known values into the list item if
-	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
-	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
-}
-/*-----------------------------------------------------------*/
-
-void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
-{
-ListItem_t * const pxIndex = pxList->pxIndex;
-
-	/* Only effective when configASSERT() is also defined, these tests may catch
-	the list data structures being overwritten in memory.  They will not catch
-	data errors caused by incorrect configuration or use of FreeRTOS. */
-	listTEST_LIST_INTEGRITY( pxList );
-	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
-
-	/* Insert a new list item into pxList, but rather than sort the list,
-	makes the new list item the last item to be removed by a call to
-	listGET_OWNER_OF_NEXT_ENTRY(). */
-	pxNewListItem->pxNext = pxIndex;
-	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
-
-	/* Only used during decision coverage testing. */
-	mtCOVERAGE_TEST_DELAY();
-
-	pxIndex->pxPrevious->pxNext = pxNewListItem;
-	pxIndex->pxPrevious = pxNewListItem;
-
-	/* Remember which list the item is in. */
-	pxNewListItem->pxContainer = pxList;
-
-	( pxList->uxNumberOfItems )++;
-}
-/*-----------------------------------------------------------*/
-
-void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
-{
-ListItem_t *pxIterator;
-const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
-
-	/* Only effective when configASSERT() is also defined, these tests may catch
-	the list data structures being overwritten in memory.  They will not catch
-	data errors caused by incorrect configuration or use of FreeRTOS. */
-	listTEST_LIST_INTEGRITY( pxList );
-	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
-
-	/* Insert the new list item into the list, sorted in xItemValue order.
-
-	If the list already contains a list item with the same item value then the
-	new list item should be placed after it.  This ensures that TCBs which are
-	stored in ready lists (all of which have the same xItemValue value) get a
-	share of the CPU.  However, if the xItemValue is the same as the back marker
-	the iteration loop below will not end.  Therefore the value is checked
-	first, and the algorithm slightly modified if necessary. */
-	if( xValueOfInsertion == portMAX_DELAY )
-	{
-		pxIterator = pxList->xListEnd.pxPrevious;
-	}
-	else
-	{
-		/* *** NOTE ***********************************************************
-		If you find your application is crashing here then likely causes are
-		listed below.  In addition see https://www.freertos.org/FAQHelp.html for
-		more tips, and ensure configASSERT() is defined!
-		https://www.freertos.org/a00110.html#configASSERT
-
-			1) Stack overflow -
-			   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
-			2) Incorrect interrupt priority assignment, especially on Cortex-M
-			   parts where numerically high priority values denote low actual
-			   interrupt priorities, which can seem counter intuitive.  See
-			   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
-			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
-			   https://www.freertos.org/a00110.html
-			3) Calling an API function from within a critical section or when
-			   the scheduler is suspended, or calling an API function that does
-			   not end in "FromISR" from an interrupt.
-			4) Using a queue or semaphore before it has been initialised or
-			   before the scheduler has been started (are interrupts firing
-			   before vTaskStartScheduler() has been called?).
-		**********************************************************************/
-
-		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
-		{
-			/* There is nothing to do here, just iterating to the wanted
-			insertion position. */
-		}
-	}
-
-	pxNewListItem->pxNext = pxIterator->pxNext;
-	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
-	pxNewListItem->pxPrevious = pxIterator;
-	pxIterator->pxNext = pxNewListItem;
-
-	/* Remember which list the item is in.  This allows fast removal of the
-	item later. */
-	pxNewListItem->pxContainer = pxList;
-
-	( pxList->uxNumberOfItems )++;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
-{
-/* The list item knows which list it is in.  Obtain the list from the list
-item. */
-List_t * const pxList = pxItemToRemove->pxContainer;
-
-	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
-	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
-
-	/* Only used during decision coverage testing. */
-	mtCOVERAGE_TEST_DELAY();
-
-	/* Make sure the index is left pointing to a valid item. */
-	if( pxList->pxIndex == pxItemToRemove )
-	{
-		pxList->pxIndex = pxItemToRemove->pxPrevious;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	pxItemToRemove->pxContainer = NULL;
-	( pxList->uxNumberOfItems )--;
-
-	return pxList->uxNumberOfItems;
-}
-/*-----------------------------------------------------------*/
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/middleware_freertos-kernel_heap_4.cmake b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/middleware_freertos-kernel_heap_4.cmake
deleted file mode 100644
index 1550bb4..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/middleware_freertos-kernel_heap_4.cmake
+++ /dev/null
@@ -1,163 +0,0 @@
-#Description: FreeRTOS heap 4; user_visible: False
-include_guard(GLOBAL)
-message("middleware_freertos-kernel_heap_4 component is included.")
-
-target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
-    ${CMAKE_CURRENT_LIST_DIR}/portable/MemMang/heap_4.c
-)
-
-target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
-)
-
-#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "LPC55S36")
-    include(middleware_freertos-kernel_LPC55S36)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1166_cm4")
-    include(middleware_freertos-kernel_MIMXRT1166_cm4)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1166_cm7")
-    include(middleware_freertos-kernel_MIMXRT1166_cm7)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC5506CPXXXX")
-    include(middleware_freertos-kernel_LPC5506CPXXXX)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
-    include(middleware_freertos-kernel_MIMXRT1052)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
-    include(middleware_freertos-kernel_MIMXRT1064)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6")
-    include(middleware_freertos-kernel_MIMX8MQ6)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8MM6")
-    include(middleware_freertos-kernel_MIMX8MM6)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
-    include(middleware_freertos-kernel_MKE15Z7)
-endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2B31A")
-    include(middleware_freertos-kernel_K32L2B31A)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKE16Z4")
-    include(middleware_freertos-kernel_MKE16Z4)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S06")
-    include(middleware_freertos-kernel_LPC55S06)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKV11Z7")
-    include(middleware_freertos-kernel_MKV11Z7)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
-    include(middleware_freertos-kernel_MKV31F51212)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC54628")
-    include(middleware_freertos-kernel_LPC54628)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MK22F51212")
-    include(middleware_freertos-kernel_MK22F51212)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKM34ZA5")
-    include(middleware_freertos-kernel_MKM34ZA5)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
-    include(middleware_freertos-kernel_MIMXRT1021)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S16")
-    include(middleware_freertos-kernel_LPC55S16)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
-    include(middleware_freertos-kernel_MIMXRT1062)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8MN6")
-    include(middleware_freertos-kernel_MIMX8MN6)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC54S018")
-    include(middleware_freertos-kernel_LPC54S018)
-endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
-    include(middleware_freertos-kernel_K32L3A60_cm0plus)
-endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
-    include(middleware_freertos-kernel_K32L3A60_cm4)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1176_cm4")
-    include(middleware_freertos-kernel_MIMXRT1176_cm4)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1176_cm7")
-    include(middleware_freertos-kernel_MIMXRT1176_cm7)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC54S018M")
-    include(middleware_freertos-kernel_LPC54S018M)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
-    include(middleware_freertos-kernel_MKM35Z7)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC51U68")
-    include(middleware_freertos-kernel_LPC51U68)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKM34Z7")
-    include(middleware_freertos-kernel_MKM34Z7)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKE17Z7")
-    include(middleware_freertos-kernel_MKE17Z7)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
-    include(middleware_freertos-kernel_LPC55S69_cm33_core0)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core1")
-    include(middleware_freertos-kernel_LPC55S69_cm33_core1)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
-    include(middleware_freertos-kernel_MCIMX7U5)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
-    include(middleware_freertos-kernel_MIMXRT1024)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
-    include(middleware_freertos-kernel_MIMXRT1011)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S28")
-    include(middleware_freertos-kernel_LPC55S28)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8ML8")
-    include(middleware_freertos-kernel_MIMX8ML8)
-endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
-    include(middleware_freertos-kernel_K32L2A41A)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
-    include(middleware_freertos-kernel_MIMXRT685S_cm33)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT595S_cm33")
-    include(middleware_freertos-kernel_MIMXRT595S_cm33)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
-    include(middleware_freertos-kernel_MIMXRT1015)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MK64F12")
-    include(middleware_freertos-kernel_MK64F12)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MK66F18")
-    include(middleware_freertos-kernel_MK66F18)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC54114_cm4")
-    include(middleware_freertos-kernel_LPC54114_cm4)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
-    include(middleware_freertos-kernel_MIMX8QM6_cm4_core0)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core1")
-    include(middleware_freertos-kernel_MIMX8QM6_cm4_core1)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
-    include(middleware_freertos-kernel_MIMX8QX6)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MK28FA15")
-    include(middleware_freertos-kernel_MK28FA15)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
-    include(middleware_freertos-kernel_MKL27Z644)
-endif()
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/ReadMe.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/ReadMe.txt
deleted file mode 100644
index 0bb046a..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/ReadMe.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
-Do not use the files located here!  These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
-FreeRTOS release.
-
-If your Cortex-M33 application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
-
-If your Cortex-M33 application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/copy_files.py b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/copy_files.py
deleted file mode 100644
index e99c1b1..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/copy_files.py
+++ /dev/null
@@ -1,103 +0,0 @@
-#/*
-# * FreeRTOS Kernel V10.2.1
-# * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-# *
-# * Permission is hereby granted, free of charge, to any person obtaining a copy of
-# * this software and associated documentation files (the "Software"), to deal in
-# * the Software without restriction, including without limitation the rights to
-# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-# * the Software, and to permit persons to whom the Software is furnished to do so,
-# * subject to the following conditions:
-# *
-# * The above copyright notice and this permission notice shall be included in all
-# * copies or substantial portions of the Software.
-# *
-# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-# *
-# * http://www.FreeRTOS.org
-# * http://aws.amazon.com/freertos
-# *
-# * 1 tab == 4 spaces!
-# */
-
-import os
-import shutil
-
-_THIS_FILE_DIRECTORY_ = os.path.dirname(os.path.realpath(__file__))
-_FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_)
-
-_COMPILERS_ = ['GCC', 'IAR']
-_ARCH_NS_ = ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
-_ARCH_S_ = ['ARM_CM33', 'ARM_CM23']
-
-_SUPPORTED_CONFIGS_ =   {
-                            'GCC' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ'],
-                            'IAR' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
-                        }
-
-# Files to be complied in the Secure Project
-_SECURE_FILE_PATHS_ = [
-    os.path.join('secure', 'context'),
-    os.path.join('secure', 'context', 'portable', '_COMPILER_ARCH_'),
-    os.path.join('secure', 'heap'),
-    os.path.join('secure', 'init'),
-    os.path.join('secure', 'macros')
-]
-
-# Files to be complied in the Non-Secure Project
-_NONSECURE_FILE_PATHS_ = [
-    'non_secure',
-    os.path.join('non_secure', 'portable', '_COMPILER_ARCH_')
-]
-
-
-def is_supported_config(compiler, arch):
-    return arch in _SUPPORTED_CONFIGS_[compiler]
-
-
-def copy_files_in_dir(src_abs_path, dst_abs_path):
-    for src_file in os.listdir(src_abs_path):
-        src_file_abs_path = os.path.join(src_abs_path, src_file)
-        if os.path.isfile(src_file_abs_path) and src_file != 'ReadMe.txt':
-            if not os.path.exists(dst_abs_path):
-                os.makedirs(dst_abs_path)
-            print('Copying {}...'.format(os.path.basename(src_file_abs_path)))
-            shutil.copy2(src_file_abs_path, dst_abs_path)
-
-
-def copy_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path):
-    _COMPILER_ARCH_ = os.path.join(compiler, arch)
-    for src_path in src_paths:
-        src_path_sanitized = src_path.replace('_COMPILER_ARCH_', _COMPILER_ARCH_ )
-
-        src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path_sanitized)
-        dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, _COMPILER_ARCH_, dst_path)
-
-        copy_files_in_dir(src_abs_path, dst_abs_path)
-
-
-def copy_files():
-    # Copy Secure Files
-    for compiler in _COMPILERS_:
-        for arch in _ARCH_S_:
-            if is_supported_config(compiler, arch):
-                copy_files_for_compiler_and_arch(compiler, arch, _SECURE_FILE_PATHS_, 'secure')
-
-    # Copy Non-Secure Files
-    for compiler in _COMPILERS_:
-        for arch in _ARCH_NS_:
-            if is_supported_config(compiler, arch):
-                copy_files_for_compiler_and_arch(compiler, arch, _NONSECURE_FILE_PATHS_, 'non_secure')
-
-
-def main():
-    copy_files()
-
-
-if __name__ == '__main__':
-    main()
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/ReadMe.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/ReadMe.txt
deleted file mode 100644
index 994d937..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/ReadMe.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
-Do not use the files located here!  These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
-FreeRTOS release.
-
-If your Cortex-M33 application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
-
-If your Cortex-M33 application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/port.c
deleted file mode 100644
index 9020541..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-__weak void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
deleted file mode 100644
index f4be178..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
+++ /dev/null
@@ -1,415 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str  r4, [r2]									\n" /* Program RNR = 4. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r3!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	"	ldr  r5, xSecureContextConst2					\n"
-	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	"	ldr  r4, xSecureContextConst2					\n"
-	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	"xSecureContextConst2: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne											\n"
-	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs r0, control									\n" /* Read the CONTROL register. */
-	"	bic r0, #1										\n" /* Clear the bit 0. */
-	"	msr control, r0									\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	orr r0, #1										\n" /* r0 = r0 | 1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	cpsie f											\n"
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* To avoid compiler warnings.  The return statement will never be reached,
-	 * but some compilers warn if it is not included, while others won't compile
-	 * if it is. */
-	return 0;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* Just to avoid compiler warning.  ulMask is used from the asm code but
-	 * the compiler can't see that.  Some compilers generate warnings without
-	 * the following line, while others generate warnings if the line is
-	 * included. */
-	( void ) ulMask;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"	.extern SecureContext_SaveContext				\n"
-	"	.extern SecureContext_LoadContext				\n"
-	"													\n"
-	"	mrs r1, psp										\n" /* Read PSP in r1. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-	"													\n"
-	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
-	"	push {r0-r2, r14}								\n"
-	"	bl SecureContext_SaveContext					\n"
-	"	pop {r0-r3}										\n" /* LR is now in r3. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"	b select_next_task								\n"
-	"													\n"
-	" save_ns_context:									\n"
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vstmdbeq r1!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
-	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	subs r1, r1, #16								\n" /* r1 = r1 - 16. */
-	"	stm r1, {r0, r2-r4}								\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #12								\n" /* r1 = r1 + 12. */
-	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	subs r1, r1, #12								\n" /* r1 = r1 - 12. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" select_next_task:									\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str r4, [r2]									\n" /* Program RNR = 4. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r3!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r4}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r4}										\n"
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#else /* configENABLE_MPU */
-	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r3}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r3}										\n"
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" restore_ns_context:								\n"
-	"	ldmia r1!, {r4-r11}								\n" /* Restore the registers that are not automatically restored. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vldmiaeq r1!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	"xSecureContextConst: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	tst lr, #4										\n"
-	"	ite eq											\n"
-	"	mrseq r0, msp									\n"
-	"	mrsne r0, psp									\n"
-	"	ldr r1, svchandler_address_const				\n"
-	"	bx r1											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
-	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
-	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
-	"	it ne											\n"
-	"	svcne %0										\n" /* Secure context is freed in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
deleted file mode 100644
index 90d9bc2..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
deleted file mode 100644
index 2f87d0f..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr  r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r3, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r3, #4										\n" /* r3 = 4. */
-	"	str  r3, [r2]									\n" /* Program RNR = 4. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r1!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne											\n"
-	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs  r0, control								\n" /* Read the CONTROL register. */
-	"	bic r0, #1										\n" /* Clear the bit 0. */
-	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	orr r0, #1										\n" /* r0 = r0 | 1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	cpsie f											\n"
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* To avoid compiler warnings.  The return statement will never be reached,
-	 * but some compilers warn if it is not included, while others won't compile
-	 * if it is. */
-	return 0;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* Just to avoid compiler warning.  ulMask is used from the asm code but
-	 * the compiler can't see that.  Some compilers generate warnings without
-	 * the following line, while others generate warnings if the line is
-	 * included. */
-	( void ) ulMask;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	mrs r0, psp										\n" /* Read PSP in r0. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vstmdbeq r0!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
-	"	mrs r2, control									\n" /* r2 = CONTROL. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmdb r0!, {r1-r11}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
-	#else /* configENABLE_MPU */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmdb r0!, {r2-r11}								\n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
-	"													\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r3, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r3, #4										\n" /* r3 = 4. */
-	"	str r3, [r2]									\n" /* Program RNR = 4. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	ldr r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r1!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r0!, {r1-r11}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
-	#else /* configENABLE_MPU */
-	"	ldmia r0!, {r2-r11}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_FPU == 1 )
-	"	tst r3, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vldmiaeq r0!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
-	#else /* configENABLE_MPU */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	#endif /* configENABLE_MPU */
-	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
-	"	bx r3											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	tst lr, #4										\n"
-	"	ite eq											\n"
-	"	mrseq r0, msp									\n"
-	"	mrsne r0, psp									\n"
-	"	ldr r1, svchandler_address_const				\n"
-	"	bx r1											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
deleted file mode 100644
index 90d9bc2..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
deleted file mode 100644
index 8d9bcc9..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	EXTERN pxCurrentTCB
-	EXTERN xSecureContext
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-	EXTERN SecureContext_SaveContext
-	EXTERN SecureContext_LoadContext
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vPortAllocateSecureContext
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMaskFromISR
-	PUBLIC vClearInterruptMaskFromISR
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-	PUBLIC vPortFreeSecureContext
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	ite ne
-	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	orr r0, r0, #1							/* r0 = r0 | 1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vPortAllocateSecureContext:
-	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r3, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
-	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str  r4, [r2]							/* Program MAIR0. */
-	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r4, #4								/* r4 = 4. */
-	str  r4, [r2]							/* Program RNR = 4. */
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	ldr  r2, =0xe000ed9c					/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r3!, {r4-r11}						/* Read 4 set of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	ldr  r5, =xSecureContext
-	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	msr  control, r3						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r4									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	ldr  r4, =xSecureContext
-	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs  r0, control						/* Read the CONTROL register. */
-	bic r0, r0, #1							/* Clear the bit 0. */
-	msr  control, r0						/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	cpsie f
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMaskFromISR:
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-/*-----------------------------------------------------------*/
-
-vClearInterruptMaskFromISR:
-	msr PRIMASK, r0
-	bx lr
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	mrs r1, psp								/* Read PSP in r1. */
-	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-
-	cbz r0, save_ns_context					/* No secure context to save. */
-	push {r0-r2, r14}
-	bl SecureContext_SaveContext
-	pop {r0-r3}								/* LR is now in r3. */
-	mov lr, r3								/* LR = r3. */
-	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r2, [r3]							/* Read pxCurrentTCB. */
-#if ( configENABLE_MPU == 1 )
-	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mrs r3, control							/* r3 = CONTROL. */
-	mov r4, lr								/* r4 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-#else /* configENABLE_MPU */
-	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
-#endif /* configENABLE_MPU */
-	b select_next_task
-
-	save_ns_context:
-		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r2, [r3]						/* Read pxCurrentTCB. */
-	#if ( configENABLE_FPU == 1 )
-		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-		it eq
-		vstmdbeq r1!, {s16-s31}				/* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if ( configENABLE_MPU == 1 )
-		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #16					/* r1 = r1 + 16. */
-		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
-		mrs r3, control						/* r3 = CONTROL. */
-		mov r4, lr							/* r4 = LR/EXC_RETURN. */
-		subs r1, r1, #16					/* r1 = r1 - 16. */
-		stm r1, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #12					/* r1 = r1 + 12. */
-		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
-		mov r3, lr							/* r3 = LR/EXC_RETURN. */
-		subs r1, r1, #12					/* r1 = r1 - 12. */
-		stmia r1!, {r0, r2-r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-
-	select_next_task:
-		cpsid i
-		bl vTaskSwitchContext
-		cpsie i
-
-		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r3, [r2]						/* Read pxCurrentTCB. */
-		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-
-	#if ( configENABLE_MPU == 1 )
-		dmb									/* Complete outstanding transfers before disabling MPU. */
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
-		bic r4, r4, #1						/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-		str r4, [r2]						/* Disable MPU. */
-
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
-		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-		str r4, [r2]						/* Program MAIR0. */
-		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-		movs r4, #4							/* r4 = 4. */
-		str r4, [r2]						/* Program RNR = 4. */
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-		ldr  r2, =0xe000ed9c				/* r2 = 0xe000ed9c [Location of RBAR]. */
-		ldmia r3!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
-		stmia r2!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
-		orr r4, r4, #1						/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-		str r4, [r2]						/* Enable MPU. */
-		dsb									/* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-
-	#if ( configENABLE_MPU == 1 )
-		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		msr control, r3						/* Restore the CONTROL register value for the task. */
-		mov lr, r4							/* LR = r4. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r4}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r4}
-		mov lr, r4							/* LR = r4. */
-		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-	#else /* configENABLE_MPU */
-		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		mov lr, r3							/* LR = r3. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r3}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r3}
-		mov lr, r3							/* LR = r3. */
-		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-	#endif /* configENABLE_MPU */
-
-	restore_ns_context:
-		ldmia r1!, {r4-r11}					/* Restore the registers that are not automatically restored. */
-	#if ( configENABLE_FPU == 1 )
-		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-		it eq
-		vldmiaeq r1!, {s16-s31}				/* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	tst lr, #4
-	ite eq
-	mrseq r0, msp
-	mrsne r0, psp
-	b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-vPortFreeSecureContext:
-	/* r0 = uint32_t *pulTCB. */
-	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
-	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
-	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
-	it ne
-	svcne 1									/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
deleted file mode 100644
index c09b3ce..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
deleted file mode 100644
index 31623f2..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	EXTERN pxCurrentTCB
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMaskFromISR
-	PUBLIC vClearInterruptMaskFromISR
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	ite ne
-	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	orr r0, r0, #1							/* r0 = r0 | 1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r1, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
-	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str r3, [r2]							/* Program MAIR0. */
-	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r3, #4								/* r3 = 4. */
-	str r3, [r2]							/* Program RNR = 4. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	msr  control, r2						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r2									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs  r0, control						/* Read the CONTROL register. */
-	bic r0, r0, #1							/* Clear the bit 0. */
-	msr  control, r0						/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	cpsie f
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMaskFromISR:
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-/*-----------------------------------------------------------*/
-
-vClearInterruptMaskFromISR:
-	msr PRIMASK, r0
-	bx lr
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	mrs r0, psp								/* Read PSP in r0. */
-#if ( configENABLE_FPU == 1 )
-	tst lr, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	it eq
-	vstmdbeq r0!, {s16-s31}					/* Store the FPU registers which are not saved automatically. */
-#endif /* configENABLE_FPU */
-#if ( configENABLE_MPU == 1 )
-	mrs r1, psplim							/* r1 = PSPLIM. */
-	mrs r2, control							/* r2 = CONTROL. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmdb r0!, {r1-r11}						/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
-#else /* configENABLE_MPU */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmdb r0!, {r2-r11}						/* Store on the stack - PSPLIM, LR and registers that are not automatically. */
-#endif /* configENABLE_MPU */
-
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-	str r0, [r1]							/* Save the new top of stack in TCB. */
-
-	cpsid i
-	bl vTaskSwitchContext
-	cpsie i
-
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
-	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str r3, [r2]							/* Program MAIR0. */
-	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r3, #4								/* r3 = 4. */
-	str r3, [r2]							/* Program RNR = 4. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldmia r0!, {r1-r11}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
-#else /* configENABLE_MPU */
-	ldmia r0!, {r2-r11}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_FPU == 1 )
-	tst r3, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	it eq
-	vldmiaeq r0!, {s16-s31}					/* Restore the FPU registers which are not restored automatically. */
-#endif /* configENABLE_FPU */
-
- #if ( configENABLE_MPU == 1 )
-	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
-	msr control, r2							/* Restore the CONTROL register value for the task. */
-#else /* configENABLE_MPU */
-	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
-#endif /* configENABLE_MPU */
-	msr psp, r0								/* Remember the new top of stack for the task. */
-	bx r3
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	tst lr, #4
-	ite eq
-	mrseq r0, msp
-	mrsne r0, psp
-	b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
deleted file mode 100644
index c09b3ce..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portasm.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portasm.h
deleted file mode 100644
index 6314e96..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portmacro.h
deleted file mode 100644
index 5042570..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/non_secure/portmacro.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.0
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portPRIVILEGED_RAM_REGION							( 2UL )
-#define portUNPRIVILEGED_DEVICE_REGION						( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Devices Region. */
-#define portDEVICE_REGION_START_ADDRESS						( 0x50000000 )
-#define portDEVICE_REGION_END_ADDRESS						( 0x5FFFFFFF )
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/ReadMe.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/ReadMe.txt
deleted file mode 100644
index 0bb046a..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/ReadMe.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
-Do not use the files located here!  These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
-FreeRTOS release.
-
-If your Cortex-M33 application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
-
-If your Cortex-M33 application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
deleted file mode 100644
index 245adff..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	"	msr control, r3							\n" /* CONTROL = r3. */
-	#endif /* configENABLE_MPU */
-	"	msr psplim, r2							\n" /* PSPLIM = r2. */
-	"	msr psp, r1								\n" /* PSP = r1. */
-	"											\n"
-	" load_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:::"r0", "r1", "r2"
-	);
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	mrs r1, psp								\n" /* r1 = PSP. */
-	#if( configENABLE_FPU == 1 )
-	"	vstmdb r1!, {s0}						\n" /* Trigger the defferred stacking of FPU registers. */
-	"	vldmia r1!, {s0}						\n" /* Nullify the effect of the pervious statement. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r2, control							\n" /* r2 = CONTROL. */
-	"	stmdb r1!, {r2}							\n" /* Store CONTROL value on the stack. */
-	#endif /* configENABLE_MPU */
-	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
-	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
-	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-	"											\n"
-	" save_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c
deleted file mode 100644
index 6df620d..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/* Functions implemented in assembler file. */
-extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
-extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
-{
-	SecureContext_LoadContextAsm( xSecureContextHandle );
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
-{
-	SecureContext_SaveContextAsm( xSecureContextHandle );
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
deleted file mode 100644
index 759a21f..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-
-	PUBLIC SecureContext_LoadContextAsm
-	PUBLIC SecureContext_SaveContextAsm
-/*-----------------------------------------------------------*/
-
-SecureContext_LoadContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-#if ( configENABLE_MPU == 1 )
-	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	msr control, r3							/* CONTROL = r3. */
-#endif /* configENABLE_MPU */
-	msr psplim, r2							/* PSPLIM = r2. */
-	msr psp, r1								/* PSP = r1. */
-
-	load_ctx_therad_mode:
-		bx lr
-/*-----------------------------------------------------------*/
-
-SecureContext_SaveContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	mrs r1, psp								/* r1 = PSP. */
-#if ( configENABLE_FPU == 1 )
-	vstmdb r1!, {s0}						/* Trigger the defferred stacking of FPU registers. */
-	vldmia r1!, {s0}						/* Nullify the effect of the pervious statement. */
-#endif /* configENABLE_FPU */
-#if ( configENABLE_MPU == 1 )
-	mrs r2, control							/* r2 = CONTROL. */
-	stmdb r1!, {r2}							/* Store CONTROL value on the stack. */
-#endif /* configENABLE_MPU */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	movs r1, #0								/* r1 = securecontextNO_STACK. */
-	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
-	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-
-	save_ctx_therad_mode:
-		bx lr
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/secure_context.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/secure_context.c
deleted file mode 100644
index 8a42230..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/secure_context.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief CONTROL value for privileged tasks.
- *
- * Bit[0] - 0 --> Thread mode is privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
-
-/**
- * @brief CONTROL value for un-privileged tasks.
- *
- * Bit[0] - 1 --> Thread mode is un-privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Structure to represent secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first addess of the allocated memory.
- */
-typedef struct SecureContext
-{
-	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
-	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
-	uint8_t *pucStackStart;				/**< First location of the stack memory. */
-} SecureContext_t;
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* No stack for thread mode until a task's context is loaded. */
-		secureportSET_PSPLIM( securecontextNO_STACK );
-		secureportSET_PSP( securecontextNO_STACK );
-
-		#if( configENABLE_MPU == 1 )
-		{
-			/* Configure thread mode to use PSP and to be unprivileged. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-		}
-		#else /* configENABLE_MPU */
-		{
-			/* Configure thread mode to use PSP and to be privileged.. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-		}
-		#endif /* configENABLE_MPU */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
-#else /* configENABLE_MPU */
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
-#endif /* configENABLE_MPU */
-{
-	uint8_t *pucStackMemory = NULL;
-	uint32_t ulIPSR;
-	SecureContextHandle_t xSecureContextHandle = NULL;
-	#if( configENABLE_MPU == 1 )
-		uint32_t *pulCurrentStackPointer = NULL;
-	#endif /* configENABLE_MPU */
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Allocate the context structure. */
-		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
-
-		if( xSecureContextHandle != NULL )
-		{
-			/* Allocate the stack space. */
-			pucStackMemory = pvPortMalloc( ulSecureStackSize );
-
-			if( pucStackMemory != NULL )
-			{
-				/* Since stack grows down, the starting point will be the last
-				 * location. Note that this location is next to the last
-				 * allocated byte because the hardware decrements the stack
-				 * pointer before writing i.e. if stack pointer is 0x2, a push
-				 * operation will decrement the stack pointer to 0x1 and then
-				 * write at 0x1. */
-				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
-
-				/* The stack cannot go beyond this location. This value is
-				 * programmed in the PSPLIM register on context switch.*/
-				xSecureContextHandle->pucStackLimit = pucStackMemory;
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Store the correct CONTROL value for the task on the stack.
-					 * This value is programmed in the CONTROL register on
-					 * context switch. */
-					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
-					pulCurrentStackPointer--;
-					if( ulIsTaskPrivileged )
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-					}
-					else
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-					}
-
-					/* Store the current stack pointer. This value is programmed in
-					 * the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
-				}
-				#else /* configENABLE_MPU */
-				{
-					/* Current SP is set to the starting of the stack. This
-					 * value programmed in the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
-
-				}
-				#endif /* configENABLE_MPU */
-			}
-			else
-			{
-				/* Free the context to avoid memory leak and make sure to return
-				 * NULL to indicate failure. */
-				vPortFree( xSecureContextHandle );
-				xSecureContextHandle = NULL;
-			}
-		}
-	}
-
-	return xSecureContextHandle;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Ensure that valid parameters are passed. */
-		secureportASSERT( xSecureContextHandle != NULL );
-
-		/* Free the stack space. */
-		vPortFree( xSecureContextHandle->pucStackLimit );
-
-		/* Free the context itself. */
-		vPortFree( xSecureContextHandle );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/secure_context.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/secure_context.h
deleted file mode 100644
index a98a7d0..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/context/secure_context.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_CONTEXT_H__
-#define __SECURE_CONTEXT_H__
-
-/* Standard includes. */
-#include 
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/**
- * @brief PSP value when no task's context is loaded.
- */
-#define securecontextNO_STACK	0x0
-
-/**
- * @brief Opaque handle.
- */
-struct SecureContext;
-typedef struct SecureContext*	SecureContextHandle_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Initializes the secure context management system.
- *
- * PSP is set to NULL and therefore a task must allocate and load a context
- * before calling any secure side function in the thread mode.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureContext_Init( void );
-
-/**
- * @brief Allocates a context on the secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
- * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
- *
- * @return Opaque context handle if context is successfully allocated, NULL
- * otherwise.
- */
-#if( configENABLE_MPU == 1 )
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
-#else /* configENABLE_MPU */
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
-#endif /* configENABLE_MPU */
-
-/**
- * @brief Frees the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the
- * context to be freed.
- */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Loads the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be loaded.
- */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Saves the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be saved.
- */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
-
-#endif /* __SECURE_CONTEXT_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/heap/secure_heap.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/heap/secure_heap.c
deleted file mode 100644
index c4f613f..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/heap/secure_heap.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure context heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Total heap size.
- */
-#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
-
-/* No test marker by default. */
-#ifndef mtCOVERAGE_TEST_MARKER
-	#define mtCOVERAGE_TEST_MARKER()
-#endif
-
-/* No tracing by default. */
-#ifndef traceMALLOC
-	#define traceMALLOC( pvReturn, xWantedSize )
-#endif
-
-/* No tracing by default. */
-#ifndef traceFREE
-	#define traceFREE( pv, xBlockSize )
-#endif
-
-/* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
-/*-----------------------------------------------------------*/
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	 * heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#else /* configAPPLICATION_ALLOCATED_HEAP */
-	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/**
- * @brief The linked list structure.
- *
- * This is used to link free blocks in order of their memory address.
- */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
-	size_t xBlockSize;						/**< The size of the free block. */
-} BlockLink_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Called automatically to setup the required heap structures the first
- * time pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/**
- * @brief Inserts a block of memory that is being freed into the correct
- * position in the list of free memory blocks.
- *
- * The block being freed will be merged with the block in front it and/or the
- * block behind it if the memory blocks are adjacent to each other.
- *
- * @param[in] pxBlockToInsert The block being freed.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The size of the structure placed at the beginning of each allocated
- * memory block must by correctly byte aligned.
- */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-
-/**
- * @brief Create a couple of list links to mark the start and end of the list.
- */
-static BlockLink_t xStart, *pxEnd = NULL;
-
-/**
- * @brief Keeps track of the number of free bytes remaining, but says nothing
- * about fragmentation.
- */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-size_t uxAddress;
-size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
-
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	uxAddress = ( size_t ) ucHeap;
-
-	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
-	{
-		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
-		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-	}
-
-	pucAlignedHeap = ( uint8_t * ) uxAddress;
-
-	/* xStart is used to hold a pointer to the first item in the list of free
-	 * blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
-
-	/* pxEnd is used to mark the end of the list of free blocks and is inserted
-	 * at the end of the heap space. */
-	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-	uxAddress -= xHeapStructSize;
-	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-	pxEnd = ( void * ) uxAddress;
-	pxEnd->xBlockSize = 0;
-	pxEnd->pxNextFreeBlock = NULL;
-
-	/* To start with there is a single free block that is sized to take up the
-	 * entire heap space, minus the space taken by pxEnd. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
-	/* Only one block exists - and it covers the entire usable heap space. */
-	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
-{
-BlockLink_t *pxIterator;
-uint8_t *puc;
-
-	/* Iterate through the list until a block is found that has a higher address
-	 * than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
-
-	/* Do the block being inserted, and the block it is being inserted after
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Do the block being inserted, and the block it is being inserted before
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
-
-	/* If the block being inserted plugged a gab, so was merged with the block
-	 * before and the block after, then it's pxNextFreeBlock pointer will have
-	 * already been set, and should not be set here as that would make it point
-	 * to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
-
-	/* If this is the first call to malloc then the heap will require
-	 * initialisation to setup the list of free blocks. */
-	if( pxEnd == NULL )
-	{
-		prvHeapInit();
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Check the requested block size is not so large that the top bit is set.
-	 * The top bit of the block size member of the BlockLink_t structure is used
-	 * to determine who owns the block - the application or the kernel, so it
-	 * must be free. */
-	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-	{
-		/* The wanted size is increased so it can contain a BlockLink_t
-		 * structure in addition to the requested amount of bytes. */
-		if( xWantedSize > 0 )
-		{
-			xWantedSize += xHeapStructSize;
-
-			/* Ensure that blocks are always aligned to the required number of
-			 * bytes. */
-			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
-			{
-				/* Byte alignment required. */
-				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-		{
-			/* Traverse the list from the start (lowest address) block until
-			 * one of adequate size is found. */
-			pxPreviousBlock = &xStart;
-			pxBlock = xStart.pxNextFreeBlock;
-			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-			{
-				pxPreviousBlock = pxBlock;
-				pxBlock = pxBlock->pxNextFreeBlock;
-			}
-
-			/* If the end marker was reached then a block of adequate size was
-			 * not found. */
-			if( pxBlock != pxEnd )
-			{
-				/* Return the memory space pointed to - jumping over the
-				 * BlockLink_t structure at its start. */
-				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-				/* This block is being returned for use so must be taken out
-				 * of the list of free blocks. */
-				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-				/* If the block is larger than required it can be split into
-				 * two. */
-				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
-				{
-					/* This block is to be split into two.  Create a new
-					 * block following the number of bytes requested. The void
-					 * cast is used to prevent byte alignment warnings from the
-					 * compiler. */
-					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-
-					/* Calculate the sizes of two blocks split from the single
-					 * block. */
-					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-					pxBlock->xBlockSize = xWantedSize;
-
-					/* Insert the new block into the list of free blocks. */
-					prvInsertBlockIntoFreeList( pxNewBlockLink );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-				{
-					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* The block is being returned - it is allocated and owned by
-				 * the application and has no "next" block. */
-				pxBlock->xBlockSize |= xBlockAllocatedBit;
-				pxBlock->pxNextFreeBlock = NULL;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	traceMALLOC( pvReturn, xWantedSize );
-
-	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
-
-	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		 * before it. */
-		puc -= xHeapStructSize;
-
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
-
-		/* Check the block is actually allocated. */
-		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
-
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				 * allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-				secureportDISABLE_NON_SECURE_INTERRUPTS();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				secureportENABLE_NON_SECURE_INTERRUPTS();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/heap/secure_heap.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/heap/secure_heap.h
deleted file mode 100644
index aae5cfc..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/heap/secure_heap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_HEAP_H__
-#define __SECURE_HEAP_H__
-
-/* Standard includes. */
-#include 
-
-/**
- * @brief Allocates memory from heap.
- *
- * @param[in] xWantedSize The size of the memory to be allocated.
- *
- * @return Pointer to the memory region if the allocation is successful, NULL
- * otherwise.
- */
-void *pvPortMalloc( size_t xWantedSize );
-
-/**
- * @brief Frees the previously allocated memory.
- *
- * @param[in] pv Pointer to the memory to be freed.
- */
-void vPortFree( void *pv );
-
-#endif /* __SECURE_HEAP_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/init/secure_init.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/init/secure_init.c
deleted file mode 100644
index 60ef1e8..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/init/secure_init.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure init includes. */
-#include "secure_init.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS			( 29UL )
-#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS				( 26UL )
-#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
-
-#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS			( 10UL )
-#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS			( 11UL )
-#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
-									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
-									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
-		 * permitted. CP11 should be programmed to the same value as CP10. */
-		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
-
-		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
-		 * that we can enable/disable lazy stacking in port.c file. */
-		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
-
-		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
-		 * registers (S16-S31) are also pushed to stack on exception entry and
-		 * restored on exception return. */
-		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/init/secure_init.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/init/secure_init.h
deleted file mode 100644
index 3954e13..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/init/secure_init.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_INIT_H__
-#define __SECURE_INIT_H__
-
-/**
- * @brief De-prioritizes the non-secure exceptions.
- *
- * This is needed to ensure that the non-secure PendSV runs at the lowest
- * priority. Context switch is done in the non-secure PendSV handler.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_DePrioritizeNSExceptions( void );
-
-/**
- * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
- *
- * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
- * Registers are not leaked to the non-secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_EnableNSFPUAccess( void );
-
-#endif /* __SECURE_INIT_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/macros/secure_port_macros.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/macros/secure_port_macros.h
deleted file mode 100644
index f392537..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/ARMv8M/secure/macros/secure_port_macros.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_PORT_MACROS_H__
-#define __SECURE_PORT_MACROS_H__
-
-/**
- * @brief Byte alignment requirements.
- */
-#define secureportBYTE_ALIGNMENT					8
-#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
-
-/**
- * @brief Macro to declare a function as non-secure callable.
- */
-#if defined( __IAR_SYSTEMS_ICC__ )
-	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
-#else
-	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
-#endif
-
-/**
- * @brief Set the secure PRIMASK value.
- */
-#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Set the non-secure PRIMASK value.
- */
-#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Read the PSP value in the given variable.
- */
-#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
-	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
-
-/**
- * @brief Set the PSP to the given value.
- */
-#define secureportSET_PSP( pucCurrentStackPointer ) \
-	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
-
-/**
- * @brief Set the PSPLIM to the given value.
- */
-#define secureportSET_PSPLIM( pucStackLimit ) \
-	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
-
-/**
- * @brief Set the NonSecure MSP to the given value.
- */
-#define secureportSET_MSP_NS( pucMainStackPointer ) \
-	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
-
-/**
- * @brief Set the CONTROL register to the given value.
- */
-#define secureportSET_CONTROL( ulControl ) \
-	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
-
-/**
- * @brief Read the Interrupt Program Status Register (IPSR) value in the given
- * variable.
- */
-#define secureportREAD_IPSR( ulIPSR ) \
-	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
-
-/**
- * @brief PRIMASK value to enable interrupts.
- */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
-
-/**
- * @brief PRIMASK value to disable interrupts.
- */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
-
-/**
- * @brief Disable secure interrupts.
- */
-#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Disable non-secure interrupts.
- *
- * This effectively disables context switches.
- */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Enable non-secure interrupts.
- */
-#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Assert definition.
- */
-#define secureportASSERT( x )						\
-	if( ( x ) == 0 )								\
-	{												\
-		secureportDISABLE_SECURE_INTERRUPTS();		\
-		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
-		for( ;; );									\
-	}
-
-#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/Common/mpu_wrappers.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/Common/mpu_wrappers.c
deleted file mode 100644
index fd4db0b..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/Common/mpu_wrappers.c
+++ /dev/null
@@ -1,1337 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * Implementation of the wrapper functions used to raise the processor privilege
- * before calling a standard FreeRTOS API function.
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-#include "timers.h"
-#include "event_groups.h"
-#include "stream_buffer.h"
-#include "mpu_prototypes.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * @brief Calls the port specific code to raise the privilege.
- *
- * @return pdFALSE if privilege was raised, pdTRUE otherwise.
- */
-BaseType_t xPortRaisePrivilege( void ) FREERTOS_SYSTEM_CALL;
-
-/**
- * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
- * code to reset the privilege, otherwise does nothing.
- */
-void vPortResetPrivilege( BaseType_t xRunningPrivileged );
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortRaisePrivilege( void ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged;
-
-	/* Check whether the processor is already privileged. */
-	xRunningPrivileged = portIS_PRIVILEGED();
-
-	/* If the processor is not already privileged, raise privilege. */
-	if( xRunningPrivileged != pdTRUE )
-	{
-		portRAISE_PRIVILEGE();
-	}
-
-	return xRunningPrivileged;
-}
-/*-----------------------------------------------------------*/
-
-void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-	if( xRunningPrivileged != pdTRUE )
-	{
-		portRESET_PRIVILEGE();
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif /* conifgSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif /* conifgSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TaskHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	vTaskAllocateMPURegions( xTask, xRegions );
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelete == 1 )
-	void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskDelete( pxTaskToDelete );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelayUntil == 1 )
-	void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskAbortDelay == 1 )
-	BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskAbortDelay( xTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelay == 1 )
-	void MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskDelay( xTicksToDelay );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
-	UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	UBaseType_t uxReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		uxReturn = uxTaskPriorityGet( pxTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return uxReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskPrioritySet == 1 )
-	void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskPrioritySet( pxTask, uxNewPriority );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_eTaskGetState == 1 )
-	eTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-	eTaskState eReturn;
-
-		eReturn = eTaskGetState( pxTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return eReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TRACE_FACILITY == 1 )
-	void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
-	TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TaskHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGetIdleTaskHandle();
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-	void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskSuspend( pxTaskToSuspend );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-	void MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskResume( pxTaskToResume );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-void MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	vTaskSuspendAll();
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xTaskResumeAll();
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
-{
-TickType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xTaskGetTickCount();
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
-{
-UBaseType_t uxReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	uxReturn = uxTaskGetNumberOfTasks();
-	vPortResetPrivilege( xRunningPrivileged );
-	return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */
-{
-char *pcReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	pcReturn = pcTaskGetName( xTaskToQuery );
-	vPortResetPrivilege( xRunningPrivileged );
-	return pcReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetHandle == 1 )
-	TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TaskHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGetHandle( pcNameToQuery );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	void MPU_vTaskList( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskList( pcWriteBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskGetRunTimeStats( pcWriteBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
-	TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TickType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGetIdleRunTimeCounter();
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-	void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskSetApplicationTaskTag( xTask, pxTagValue );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-	TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TaskHookFunction_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGetApplicationTaskTag( xTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-	void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-	void *MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */
-	{
-	void *pvReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );
-		vPortResetPrivilege( xRunningPrivileged );
-		return pvReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-	BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-	UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */
-	{
-	UBaseType_t uxReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
-		vPortResetPrivilege( xRunningPrivileged );
-		return uxReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
-	UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	UBaseType_t uxReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		uxReturn = uxTaskGetStackHighWaterMark( xTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return uxReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
-	configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	configSTACK_DEPTH_TYPE uxReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		uxReturn = uxTaskGetStackHighWaterMark2( xTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return uxReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )
-	TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TaskHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGetCurrentTaskHandle();
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
-	BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGetSchedulerState();
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	vTaskSetTimeOutState( pxTimeOut );
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-	BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGenericNotify( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-	BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-	uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-	{
-	uint32_t ulReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		ulReturn = ulTaskNotifyTake( xClearCountOnExit, xTicksToWait );
-		vPortResetPrivilege( xRunningPrivileged );
-		return ulReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-	BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskNotifyStateClear( xTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xQueueGenericReset( pxQueue, xNewQueue );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-UBaseType_t uxReturn;
-
-	uxReturn = uxQueueMessagesWaiting( pxQueue );
-	vPortResetPrivilege( xRunningPrivileged );
-	return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-UBaseType_t uxReturn;
-
-	uxReturn = uxQueueSpacesAvailable( xQueue );
-	vPortResetPrivilege( xRunningPrivileged );
-	return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-BaseType_t xReturn;
-
-	xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-BaseType_t xReturn;
-
-	xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-BaseType_t xReturn;
-
-	xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
-	TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-	void * xReturn;
-
-		xReturn = xQueueGetMutexHolder( xSemaphore );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueCreateMutex( ucQueueType );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-	QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
-	QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-	BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-	BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueGiveMutexRecursive( xMutex );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueSetHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueCreateSet( uxEventQueueLength );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-	QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueSetMemberHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-	BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-	BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if configQUEUE_REGISTRY_SIZE > 0
-	void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vQueueAddToRegistry( xQueue, pcName );
-
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if configQUEUE_REGISTRY_SIZE > 0
-	void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vQueueUnregisterQueue( xQueue );
-
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if configQUEUE_REGISTRY_SIZE > 0
-	const char *MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-	const char *pcReturn;
-
-		pcReturn = pcQueueGetName( xQueue );
-
-		vPortResetPrivilege( xRunningPrivileged );
-		return pcReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	vQueueDelete( xQueue );
-
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	void *MPU_pvPortMalloc( size_t xSize ) /* FREERTOS_SYSTEM_CALL */
-	{
-	void *pvReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		pvReturn = pvPortMalloc( xSize );
-
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return pvReturn;
-	}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	void MPU_vPortFree( void *pv ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vPortFree( pv );
-
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	void MPU_vPortInitialiseBlocks( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vPortInitialiseBlocks();
-
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	size_t MPU_xPortGetFreeHeapSize( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	size_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xPortGetFreeHeapSize();
-
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
-	TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TimerHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerCreate( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
-	TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TimerHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	void *MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	void * pvReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		pvReturn = pvTimerGetTimerID( xTimer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return pvReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTimerSetTimerID( xTimer, pvNewID );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerIsTimerActive( xTimer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TaskHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerGetTimerDaemonTaskHandle();
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
-	BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTimerSetReloadMode( xTimer, uxAutoReload );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	const char * pcReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		pcReturn = pcTimerGetName( xTimer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return pcReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TickType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerGetPeriod( xTimer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TickType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerGetExpiryTime( xTimer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	EventGroupHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xEventGroupCreate();
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	EventGroupHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xEventGroupCreateStatic( pxEventGroupBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-EventBits_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
-{
-EventBits_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
-{
-EventBits_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-EventBits_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	vEventGroupDelete( xEventGroup );
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-size_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-size_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-size_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	vStreamBufferDelete( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferIsFull( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferIsEmpty( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferReset( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-size_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-size_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	StreamBufferHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	StreamBufferHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-
-/* Functions that the application writer wants to execute in privileged mode
-can be defined in application_defined_privileged_functions.h.  The functions
-must take the same format as those above whereby the privilege state on exit
-equals the privilege state on entry.  For example:
-
-void MPU_FunctionName( [parameters ] )
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	FunctionName( [parameters ] );
-
-	vPortResetPrivilege( xRunningPrivileged );
-}
-*/
-
-#if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1
-	#include "application_defined_privileged_functions.h"
-#endif
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/port.c
deleted file mode 100644
index 161767b..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portasm.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portasm.c
deleted file mode 100644
index f4be178..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portasm.c
+++ /dev/null
@@ -1,415 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str  r4, [r2]									\n" /* Program RNR = 4. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r3!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	"	ldr  r5, xSecureContextConst2					\n"
-	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	"	ldr  r4, xSecureContextConst2					\n"
-	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	"xSecureContextConst2: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne											\n"
-	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs r0, control									\n" /* Read the CONTROL register. */
-	"	bic r0, #1										\n" /* Clear the bit 0. */
-	"	msr control, r0									\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	orr r0, #1										\n" /* r0 = r0 | 1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	cpsie f											\n"
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* To avoid compiler warnings.  The return statement will never be reached,
-	 * but some compilers warn if it is not included, while others won't compile
-	 * if it is. */
-	return 0;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* Just to avoid compiler warning.  ulMask is used from the asm code but
-	 * the compiler can't see that.  Some compilers generate warnings without
-	 * the following line, while others generate warnings if the line is
-	 * included. */
-	( void ) ulMask;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"	.extern SecureContext_SaveContext				\n"
-	"	.extern SecureContext_LoadContext				\n"
-	"													\n"
-	"	mrs r1, psp										\n" /* Read PSP in r1. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-	"													\n"
-	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
-	"	push {r0-r2, r14}								\n"
-	"	bl SecureContext_SaveContext					\n"
-	"	pop {r0-r3}										\n" /* LR is now in r3. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"	b select_next_task								\n"
-	"													\n"
-	" save_ns_context:									\n"
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vstmdbeq r1!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
-	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	subs r1, r1, #16								\n" /* r1 = r1 - 16. */
-	"	stm r1, {r0, r2-r4}								\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #12								\n" /* r1 = r1 + 12. */
-	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	subs r1, r1, #12								\n" /* r1 = r1 - 12. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" select_next_task:									\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str r4, [r2]									\n" /* Program RNR = 4. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r3!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r4}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r4}										\n"
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#else /* configENABLE_MPU */
-	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r3}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r3}										\n"
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" restore_ns_context:								\n"
-	"	ldmia r1!, {r4-r11}								\n" /* Restore the registers that are not automatically restored. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vldmiaeq r1!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	"xSecureContextConst: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	tst lr, #4										\n"
-	"	ite eq											\n"
-	"	mrseq r0, msp									\n"
-	"	mrsne r0, psp									\n"
-	"	ldr r1, svchandler_address_const				\n"
-	"	bx r1											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
-	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
-	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
-	"	it ne											\n"
-	"	svcne %0										\n" /* Secure context is freed in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portasm.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portasm.h
deleted file mode 100644
index 6314e96..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portmacro.h
deleted file mode 100644
index 980cc10..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context.c
deleted file mode 100644
index 8a42230..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief CONTROL value for privileged tasks.
- *
- * Bit[0] - 0 --> Thread mode is privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
-
-/**
- * @brief CONTROL value for un-privileged tasks.
- *
- * Bit[0] - 1 --> Thread mode is un-privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Structure to represent secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first addess of the allocated memory.
- */
-typedef struct SecureContext
-{
-	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
-	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
-	uint8_t *pucStackStart;				/**< First location of the stack memory. */
-} SecureContext_t;
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* No stack for thread mode until a task's context is loaded. */
-		secureportSET_PSPLIM( securecontextNO_STACK );
-		secureportSET_PSP( securecontextNO_STACK );
-
-		#if( configENABLE_MPU == 1 )
-		{
-			/* Configure thread mode to use PSP and to be unprivileged. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-		}
-		#else /* configENABLE_MPU */
-		{
-			/* Configure thread mode to use PSP and to be privileged.. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-		}
-		#endif /* configENABLE_MPU */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
-#else /* configENABLE_MPU */
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
-#endif /* configENABLE_MPU */
-{
-	uint8_t *pucStackMemory = NULL;
-	uint32_t ulIPSR;
-	SecureContextHandle_t xSecureContextHandle = NULL;
-	#if( configENABLE_MPU == 1 )
-		uint32_t *pulCurrentStackPointer = NULL;
-	#endif /* configENABLE_MPU */
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Allocate the context structure. */
-		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
-
-		if( xSecureContextHandle != NULL )
-		{
-			/* Allocate the stack space. */
-			pucStackMemory = pvPortMalloc( ulSecureStackSize );
-
-			if( pucStackMemory != NULL )
-			{
-				/* Since stack grows down, the starting point will be the last
-				 * location. Note that this location is next to the last
-				 * allocated byte because the hardware decrements the stack
-				 * pointer before writing i.e. if stack pointer is 0x2, a push
-				 * operation will decrement the stack pointer to 0x1 and then
-				 * write at 0x1. */
-				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
-
-				/* The stack cannot go beyond this location. This value is
-				 * programmed in the PSPLIM register on context switch.*/
-				xSecureContextHandle->pucStackLimit = pucStackMemory;
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Store the correct CONTROL value for the task on the stack.
-					 * This value is programmed in the CONTROL register on
-					 * context switch. */
-					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
-					pulCurrentStackPointer--;
-					if( ulIsTaskPrivileged )
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-					}
-					else
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-					}
-
-					/* Store the current stack pointer. This value is programmed in
-					 * the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
-				}
-				#else /* configENABLE_MPU */
-				{
-					/* Current SP is set to the starting of the stack. This
-					 * value programmed in the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
-
-				}
-				#endif /* configENABLE_MPU */
-			}
-			else
-			{
-				/* Free the context to avoid memory leak and make sure to return
-				 * NULL to indicate failure. */
-				vPortFree( xSecureContextHandle );
-				xSecureContextHandle = NULL;
-			}
-		}
-	}
-
-	return xSecureContextHandle;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Ensure that valid parameters are passed. */
-		secureportASSERT( xSecureContextHandle != NULL );
-
-		/* Free the stack space. */
-		vPortFree( xSecureContextHandle->pucStackLimit );
-
-		/* Free the context itself. */
-		vPortFree( xSecureContextHandle );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context.h
deleted file mode 100644
index a98a7d0..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_CONTEXT_H__
-#define __SECURE_CONTEXT_H__
-
-/* Standard includes. */
-#include 
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/**
- * @brief PSP value when no task's context is loaded.
- */
-#define securecontextNO_STACK	0x0
-
-/**
- * @brief Opaque handle.
- */
-struct SecureContext;
-typedef struct SecureContext*	SecureContextHandle_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Initializes the secure context management system.
- *
- * PSP is set to NULL and therefore a task must allocate and load a context
- * before calling any secure side function in the thread mode.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureContext_Init( void );
-
-/**
- * @brief Allocates a context on the secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
- * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
- *
- * @return Opaque context handle if context is successfully allocated, NULL
- * otherwise.
- */
-#if( configENABLE_MPU == 1 )
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
-#else /* configENABLE_MPU */
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
-#endif /* configENABLE_MPU */
-
-/**
- * @brief Frees the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the
- * context to be freed.
- */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Loads the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be loaded.
- */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Saves the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be saved.
- */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
-
-#endif /* __SECURE_CONTEXT_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context_port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context_port.c
deleted file mode 100644
index 245adff..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context_port.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	"	msr control, r3							\n" /* CONTROL = r3. */
-	#endif /* configENABLE_MPU */
-	"	msr psplim, r2							\n" /* PSPLIM = r2. */
-	"	msr psp, r1								\n" /* PSP = r1. */
-	"											\n"
-	" load_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:::"r0", "r1", "r2"
-	);
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	mrs r1, psp								\n" /* r1 = PSP. */
-	#if( configENABLE_FPU == 1 )
-	"	vstmdb r1!, {s0}						\n" /* Trigger the defferred stacking of FPU registers. */
-	"	vldmia r1!, {s0}						\n" /* Nullify the effect of the pervious statement. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r2, control							\n" /* r2 = CONTROL. */
-	"	stmdb r1!, {r2}							\n" /* Store CONTROL value on the stack. */
-	#endif /* configENABLE_MPU */
-	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
-	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
-	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-	"											\n"
-	" save_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_heap.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_heap.c
deleted file mode 100644
index c4f613f..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_heap.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure context heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Total heap size.
- */
-#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
-
-/* No test marker by default. */
-#ifndef mtCOVERAGE_TEST_MARKER
-	#define mtCOVERAGE_TEST_MARKER()
-#endif
-
-/* No tracing by default. */
-#ifndef traceMALLOC
-	#define traceMALLOC( pvReturn, xWantedSize )
-#endif
-
-/* No tracing by default. */
-#ifndef traceFREE
-	#define traceFREE( pv, xBlockSize )
-#endif
-
-/* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
-/*-----------------------------------------------------------*/
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	 * heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#else /* configAPPLICATION_ALLOCATED_HEAP */
-	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/**
- * @brief The linked list structure.
- *
- * This is used to link free blocks in order of their memory address.
- */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
-	size_t xBlockSize;						/**< The size of the free block. */
-} BlockLink_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Called automatically to setup the required heap structures the first
- * time pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/**
- * @brief Inserts a block of memory that is being freed into the correct
- * position in the list of free memory blocks.
- *
- * The block being freed will be merged with the block in front it and/or the
- * block behind it if the memory blocks are adjacent to each other.
- *
- * @param[in] pxBlockToInsert The block being freed.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The size of the structure placed at the beginning of each allocated
- * memory block must by correctly byte aligned.
- */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-
-/**
- * @brief Create a couple of list links to mark the start and end of the list.
- */
-static BlockLink_t xStart, *pxEnd = NULL;
-
-/**
- * @brief Keeps track of the number of free bytes remaining, but says nothing
- * about fragmentation.
- */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-size_t uxAddress;
-size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
-
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	uxAddress = ( size_t ) ucHeap;
-
-	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
-	{
-		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
-		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-	}
-
-	pucAlignedHeap = ( uint8_t * ) uxAddress;
-
-	/* xStart is used to hold a pointer to the first item in the list of free
-	 * blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
-
-	/* pxEnd is used to mark the end of the list of free blocks and is inserted
-	 * at the end of the heap space. */
-	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-	uxAddress -= xHeapStructSize;
-	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-	pxEnd = ( void * ) uxAddress;
-	pxEnd->xBlockSize = 0;
-	pxEnd->pxNextFreeBlock = NULL;
-
-	/* To start with there is a single free block that is sized to take up the
-	 * entire heap space, minus the space taken by pxEnd. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
-	/* Only one block exists - and it covers the entire usable heap space. */
-	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
-{
-BlockLink_t *pxIterator;
-uint8_t *puc;
-
-	/* Iterate through the list until a block is found that has a higher address
-	 * than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
-
-	/* Do the block being inserted, and the block it is being inserted after
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Do the block being inserted, and the block it is being inserted before
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
-
-	/* If the block being inserted plugged a gab, so was merged with the block
-	 * before and the block after, then it's pxNextFreeBlock pointer will have
-	 * already been set, and should not be set here as that would make it point
-	 * to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
-
-	/* If this is the first call to malloc then the heap will require
-	 * initialisation to setup the list of free blocks. */
-	if( pxEnd == NULL )
-	{
-		prvHeapInit();
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Check the requested block size is not so large that the top bit is set.
-	 * The top bit of the block size member of the BlockLink_t structure is used
-	 * to determine who owns the block - the application or the kernel, so it
-	 * must be free. */
-	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-	{
-		/* The wanted size is increased so it can contain a BlockLink_t
-		 * structure in addition to the requested amount of bytes. */
-		if( xWantedSize > 0 )
-		{
-			xWantedSize += xHeapStructSize;
-
-			/* Ensure that blocks are always aligned to the required number of
-			 * bytes. */
-			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
-			{
-				/* Byte alignment required. */
-				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-		{
-			/* Traverse the list from the start (lowest address) block until
-			 * one of adequate size is found. */
-			pxPreviousBlock = &xStart;
-			pxBlock = xStart.pxNextFreeBlock;
-			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-			{
-				pxPreviousBlock = pxBlock;
-				pxBlock = pxBlock->pxNextFreeBlock;
-			}
-
-			/* If the end marker was reached then a block of adequate size was
-			 * not found. */
-			if( pxBlock != pxEnd )
-			{
-				/* Return the memory space pointed to - jumping over the
-				 * BlockLink_t structure at its start. */
-				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-				/* This block is being returned for use so must be taken out
-				 * of the list of free blocks. */
-				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-				/* If the block is larger than required it can be split into
-				 * two. */
-				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
-				{
-					/* This block is to be split into two.  Create a new
-					 * block following the number of bytes requested. The void
-					 * cast is used to prevent byte alignment warnings from the
-					 * compiler. */
-					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-
-					/* Calculate the sizes of two blocks split from the single
-					 * block. */
-					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-					pxBlock->xBlockSize = xWantedSize;
-
-					/* Insert the new block into the list of free blocks. */
-					prvInsertBlockIntoFreeList( pxNewBlockLink );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-				{
-					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* The block is being returned - it is allocated and owned by
-				 * the application and has no "next" block. */
-				pxBlock->xBlockSize |= xBlockAllocatedBit;
-				pxBlock->pxNextFreeBlock = NULL;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	traceMALLOC( pvReturn, xWantedSize );
-
-	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
-
-	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		 * before it. */
-		puc -= xHeapStructSize;
-
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
-
-		/* Check the block is actually allocated. */
-		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
-
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				 * allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-				secureportDISABLE_NON_SECURE_INTERRUPTS();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				secureportENABLE_NON_SECURE_INTERRUPTS();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_heap.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_heap.h
deleted file mode 100644
index aae5cfc..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_heap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_HEAP_H__
-#define __SECURE_HEAP_H__
-
-/* Standard includes. */
-#include 
-
-/**
- * @brief Allocates memory from heap.
- *
- * @param[in] xWantedSize The size of the memory to be allocated.
- *
- * @return Pointer to the memory region if the allocation is successful, NULL
- * otherwise.
- */
-void *pvPortMalloc( size_t xWantedSize );
-
-/**
- * @brief Frees the previously allocated memory.
- *
- * @param[in] pv Pointer to the memory to be freed.
- */
-void vPortFree( void *pv );
-
-#endif /* __SECURE_HEAP_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_init.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_init.c
deleted file mode 100644
index 60ef1e8..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_init.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure init includes. */
-#include "secure_init.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS			( 29UL )
-#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS				( 26UL )
-#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
-
-#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS			( 10UL )
-#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS			( 11UL )
-#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
-									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
-									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
-		 * permitted. CP11 should be programmed to the same value as CP10. */
-		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
-
-		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
-		 * that we can enable/disable lazy stacking in port.c file. */
-		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
-
-		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
-		 * registers (S16-S31) are also pushed to stack on exception entry and
-		 * restored on exception return. */
-		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_init.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_init.h
deleted file mode 100644
index 3954e13..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_init.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_INIT_H__
-#define __SECURE_INIT_H__
-
-/**
- * @brief De-prioritizes the non-secure exceptions.
- *
- * This is needed to ensure that the non-secure PendSV runs at the lowest
- * priority. Context switch is done in the non-secure PendSV handler.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_DePrioritizeNSExceptions( void );
-
-/**
- * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
- *
- * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
- * Registers are not leaked to the non-secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_EnableNSFPUAccess( void );
-
-#endif /* __SECURE_INIT_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_port_macros.h
deleted file mode 100644
index f392537..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_port_macros.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_PORT_MACROS_H__
-#define __SECURE_PORT_MACROS_H__
-
-/**
- * @brief Byte alignment requirements.
- */
-#define secureportBYTE_ALIGNMENT					8
-#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
-
-/**
- * @brief Macro to declare a function as non-secure callable.
- */
-#if defined( __IAR_SYSTEMS_ICC__ )
-	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
-#else
-	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
-#endif
-
-/**
- * @brief Set the secure PRIMASK value.
- */
-#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Set the non-secure PRIMASK value.
- */
-#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Read the PSP value in the given variable.
- */
-#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
-	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
-
-/**
- * @brief Set the PSP to the given value.
- */
-#define secureportSET_PSP( pucCurrentStackPointer ) \
-	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
-
-/**
- * @brief Set the PSPLIM to the given value.
- */
-#define secureportSET_PSPLIM( pucStackLimit ) \
-	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
-
-/**
- * @brief Set the NonSecure MSP to the given value.
- */
-#define secureportSET_MSP_NS( pucMainStackPointer ) \
-	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
-
-/**
- * @brief Set the CONTROL register to the given value.
- */
-#define secureportSET_CONTROL( ulControl ) \
-	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
-
-/**
- * @brief Read the Interrupt Program Status Register (IPSR) value in the given
- * variable.
- */
-#define secureportREAD_IPSR( ulIPSR ) \
-	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
-
-/**
- * @brief PRIMASK value to enable interrupts.
- */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
-
-/**
- * @brief PRIMASK value to disable interrupts.
- */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
-
-/**
- * @brief Disable secure interrupts.
- */
-#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Disable non-secure interrupts.
- *
- * This effectively disables context switches.
- */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Enable non-secure interrupts.
- */
-#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Assert definition.
- */
-#define secureportASSERT( x )						\
-	if( ( x ) == 0 )								\
-	{												\
-		secureportDISABLE_SECURE_INTERRUPTS();		\
-		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
-		for( ;; );									\
-	}
-
-#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
deleted file mode 100644
index 161767b..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
deleted file mode 100644
index 2f87d0f..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr  r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r3, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r3, #4										\n" /* r3 = 4. */
-	"	str  r3, [r2]									\n" /* Program RNR = 4. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r1!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne											\n"
-	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs  r0, control								\n" /* Read the CONTROL register. */
-	"	bic r0, #1										\n" /* Clear the bit 0. */
-	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	orr r0, #1										\n" /* r0 = r0 | 1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	cpsie f											\n"
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* To avoid compiler warnings.  The return statement will never be reached,
-	 * but some compilers warn if it is not included, while others won't compile
-	 * if it is. */
-	return 0;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* Just to avoid compiler warning.  ulMask is used from the asm code but
-	 * the compiler can't see that.  Some compilers generate warnings without
-	 * the following line, while others generate warnings if the line is
-	 * included. */
-	( void ) ulMask;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	mrs r0, psp										\n" /* Read PSP in r0. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vstmdbeq r0!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
-	"	mrs r2, control									\n" /* r2 = CONTROL. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmdb r0!, {r1-r11}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
-	#else /* configENABLE_MPU */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmdb r0!, {r2-r11}								\n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
-	"													\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r3, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r3, #4										\n" /* r3 = 4. */
-	"	str r3, [r2]									\n" /* Program RNR = 4. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	ldr r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r1!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r0!, {r1-r11}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
-	#else /* configENABLE_MPU */
-	"	ldmia r0!, {r2-r11}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_FPU == 1 )
-	"	tst r3, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vldmiaeq r0!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
-	#else /* configENABLE_MPU */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	#endif /* configENABLE_MPU */
-	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
-	"	bx r3											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	tst lr, #4										\n"
-	"	ite eq											\n"
-	"	mrseq r0, msp									\n"
-	"	mrsne r0, psp									\n"
-	"	ldr r1, svchandler_address_const				\n"
-	"	bx r1											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
deleted file mode 100644
index 6314e96..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
deleted file mode 100644
index 980cc10..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/non_secure/port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/non_secure/port.c
deleted file mode 100644
index 9020541..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-__weak void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/non_secure/portasm.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/non_secure/portasm.h
deleted file mode 100644
index 6314e96..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/non_secure/portasm.s b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/non_secure/portasm.s
deleted file mode 100644
index fcfd930..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/non_secure/portasm.s
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include 
-
-	EXTERN pxCurrentTCB
-	EXTERN xSecureContext
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-	EXTERN SecureContext_SaveContext
-	EXTERN SecureContext_LoadContext
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vPortAllocateSecureContext
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMaskFromISR
-	PUBLIC vClearInterruptMaskFromISR
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-	PUBLIC vPortFreeSecureContext
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	ite ne
-	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	orr r0, r0, #1							/* r0 = r0 | 1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vPortAllocateSecureContext:
-	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r3, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
-	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str  r4, [r2]							/* Program MAIR0. */
-	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r4, #4								/* r4 = 4. */
-	str  r4, [r2]							/* Program RNR = 4. */
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	ldr  r2, =0xe000ed9c					/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r3!, {r4-r11}						/* Read 4 set of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	ldr  r5, =xSecureContext
-	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	msr  control, r3						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r4									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	ldr  r4, =xSecureContext
-	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs  r0, control						/* Read the CONTROL register. */
-	bic r0, r0, #1							/* Clear the bit 0. */
-	msr  control, r0						/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	cpsie f
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMaskFromISR:
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-/*-----------------------------------------------------------*/
-
-vClearInterruptMaskFromISR:
-	msr PRIMASK, r0
-	bx lr
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	mrs r1, psp								/* Read PSP in r1. */
-	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-
-	cbz r0, save_ns_context					/* No secure context to save. */
-	push {r0-r2, r14}
-	bl SecureContext_SaveContext
-	pop {r0-r3}								/* LR is now in r3. */
-	mov lr, r3								/* LR = r3. */
-	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r2, [r3]							/* Read pxCurrentTCB. */
-#if ( configENABLE_MPU == 1 )
-	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mrs r3, control							/* r3 = CONTROL. */
-	mov r4, lr								/* r4 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-#else /* configENABLE_MPU */
-	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
-#endif /* configENABLE_MPU */
-	b select_next_task
-
-	save_ns_context:
-		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r2, [r3]						/* Read pxCurrentTCB. */
-	#if ( configENABLE_FPU == 1 )
-		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-		it eq
-		vstmdbeq r1!, {s16-s31}				/* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if ( configENABLE_MPU == 1 )
-		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #16					/* r1 = r1 + 16. */
-		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
-		mrs r3, control						/* r3 = CONTROL. */
-		mov r4, lr							/* r4 = LR/EXC_RETURN. */
-		subs r1, r1, #16					/* r1 = r1 - 16. */
-		stm r1, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #12					/* r1 = r1 + 12. */
-		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
-		mov r3, lr							/* r3 = LR/EXC_RETURN. */
-		subs r1, r1, #12					/* r1 = r1 - 12. */
-		stmia r1!, {r0, r2-r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-
-	select_next_task:
-		cpsid i
-		bl vTaskSwitchContext
-		cpsie i
-
-		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r3, [r2]						/* Read pxCurrentTCB. */
-		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-
-	#if ( configENABLE_MPU == 1 )
-		dmb									/* Complete outstanding transfers before disabling MPU. */
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
-		bic r4, r4, #1						/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-		str r4, [r2]						/* Disable MPU. */
-
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
-		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-		str r4, [r2]						/* Program MAIR0. */
-		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-		movs r4, #4							/* r4 = 4. */
-		str r4, [r2]						/* Program RNR = 4. */
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-		ldr  r2, =0xe000ed9c				/* r2 = 0xe000ed9c [Location of RBAR]. */
-		ldmia r3!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
-		stmia r2!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
-		orr r4, r4, #1						/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-		str r4, [r2]						/* Enable MPU. */
-		dsb									/* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-
-	#if ( configENABLE_MPU == 1 )
-		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		msr control, r3						/* Restore the CONTROL register value for the task. */
-		mov lr, r4							/* LR = r4. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r4}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r4}
-		mov lr, r4							/* LR = r4. */
-		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-	#else /* configENABLE_MPU */
-		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		mov lr, r3							/* LR = r3. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r3}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r3}
-		mov lr, r3							/* LR = r3. */
-		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-	#endif /* configENABLE_MPU */
-
-	restore_ns_context:
-		ldmia r1!, {r4-r11}					/* Restore the registers that are not automatically restored. */
-	#if ( configENABLE_FPU == 1 )
-		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-		it eq
-		vldmiaeq r1!, {s16-s31}				/* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	tst lr, #4
-	ite eq
-	mrseq r0, msp
-	mrsne r0, psp
-	b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-vPortFreeSecureContext:
-	/* r0 = uint32_t *pulTCB. */
-	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
-	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
-	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
-	it ne
-	svcne 1									/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/non_secure/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/non_secure/portmacro.h
deleted file mode 100644
index 29d8477..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_context.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_context.c
deleted file mode 100644
index 8a42230..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_context.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief CONTROL value for privileged tasks.
- *
- * Bit[0] - 0 --> Thread mode is privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
-
-/**
- * @brief CONTROL value for un-privileged tasks.
- *
- * Bit[0] - 1 --> Thread mode is un-privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Structure to represent secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first addess of the allocated memory.
- */
-typedef struct SecureContext
-{
-	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
-	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
-	uint8_t *pucStackStart;				/**< First location of the stack memory. */
-} SecureContext_t;
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* No stack for thread mode until a task's context is loaded. */
-		secureportSET_PSPLIM( securecontextNO_STACK );
-		secureportSET_PSP( securecontextNO_STACK );
-
-		#if( configENABLE_MPU == 1 )
-		{
-			/* Configure thread mode to use PSP and to be unprivileged. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-		}
-		#else /* configENABLE_MPU */
-		{
-			/* Configure thread mode to use PSP and to be privileged.. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-		}
-		#endif /* configENABLE_MPU */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
-#else /* configENABLE_MPU */
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
-#endif /* configENABLE_MPU */
-{
-	uint8_t *pucStackMemory = NULL;
-	uint32_t ulIPSR;
-	SecureContextHandle_t xSecureContextHandle = NULL;
-	#if( configENABLE_MPU == 1 )
-		uint32_t *pulCurrentStackPointer = NULL;
-	#endif /* configENABLE_MPU */
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Allocate the context structure. */
-		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
-
-		if( xSecureContextHandle != NULL )
-		{
-			/* Allocate the stack space. */
-			pucStackMemory = pvPortMalloc( ulSecureStackSize );
-
-			if( pucStackMemory != NULL )
-			{
-				/* Since stack grows down, the starting point will be the last
-				 * location. Note that this location is next to the last
-				 * allocated byte because the hardware decrements the stack
-				 * pointer before writing i.e. if stack pointer is 0x2, a push
-				 * operation will decrement the stack pointer to 0x1 and then
-				 * write at 0x1. */
-				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
-
-				/* The stack cannot go beyond this location. This value is
-				 * programmed in the PSPLIM register on context switch.*/
-				xSecureContextHandle->pucStackLimit = pucStackMemory;
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Store the correct CONTROL value for the task on the stack.
-					 * This value is programmed in the CONTROL register on
-					 * context switch. */
-					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
-					pulCurrentStackPointer--;
-					if( ulIsTaskPrivileged )
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-					}
-					else
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-					}
-
-					/* Store the current stack pointer. This value is programmed in
-					 * the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
-				}
-				#else /* configENABLE_MPU */
-				{
-					/* Current SP is set to the starting of the stack. This
-					 * value programmed in the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
-
-				}
-				#endif /* configENABLE_MPU */
-			}
-			else
-			{
-				/* Free the context to avoid memory leak and make sure to return
-				 * NULL to indicate failure. */
-				vPortFree( xSecureContextHandle );
-				xSecureContextHandle = NULL;
-			}
-		}
-	}
-
-	return xSecureContextHandle;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Ensure that valid parameters are passed. */
-		secureportASSERT( xSecureContextHandle != NULL );
-
-		/* Free the stack space. */
-		vPortFree( xSecureContextHandle->pucStackLimit );
-
-		/* Free the context itself. */
-		vPortFree( xSecureContextHandle );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_context.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_context.h
deleted file mode 100644
index a98a7d0..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_context.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_CONTEXT_H__
-#define __SECURE_CONTEXT_H__
-
-/* Standard includes. */
-#include 
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/**
- * @brief PSP value when no task's context is loaded.
- */
-#define securecontextNO_STACK	0x0
-
-/**
- * @brief Opaque handle.
- */
-struct SecureContext;
-typedef struct SecureContext*	SecureContextHandle_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Initializes the secure context management system.
- *
- * PSP is set to NULL and therefore a task must allocate and load a context
- * before calling any secure side function in the thread mode.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureContext_Init( void );
-
-/**
- * @brief Allocates a context on the secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
- * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
- *
- * @return Opaque context handle if context is successfully allocated, NULL
- * otherwise.
- */
-#if( configENABLE_MPU == 1 )
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
-#else /* configENABLE_MPU */
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
-#endif /* configENABLE_MPU */
-
-/**
- * @brief Frees the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the
- * context to be freed.
- */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Loads the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be loaded.
- */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Saves the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be saved.
- */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
-
-#endif /* __SECURE_CONTEXT_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_context_port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_context_port.c
deleted file mode 100644
index 6df620d..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_context_port.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/* Functions implemented in assembler file. */
-extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
-extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
-{
-	SecureContext_LoadContextAsm( xSecureContextHandle );
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
-{
-	SecureContext_SaveContextAsm( xSecureContextHandle );
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
deleted file mode 100644
index 759a21f..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-
-	PUBLIC SecureContext_LoadContextAsm
-	PUBLIC SecureContext_SaveContextAsm
-/*-----------------------------------------------------------*/
-
-SecureContext_LoadContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-#if ( configENABLE_MPU == 1 )
-	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	msr control, r3							/* CONTROL = r3. */
-#endif /* configENABLE_MPU */
-	msr psplim, r2							/* PSPLIM = r2. */
-	msr psp, r1								/* PSP = r1. */
-
-	load_ctx_therad_mode:
-		bx lr
-/*-----------------------------------------------------------*/
-
-SecureContext_SaveContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	mrs r1, psp								/* r1 = PSP. */
-#if ( configENABLE_FPU == 1 )
-	vstmdb r1!, {s0}						/* Trigger the defferred stacking of FPU registers. */
-	vldmia r1!, {s0}						/* Nullify the effect of the pervious statement. */
-#endif /* configENABLE_FPU */
-#if ( configENABLE_MPU == 1 )
-	mrs r2, control							/* r2 = CONTROL. */
-	stmdb r1!, {r2}							/* Store CONTROL value on the stack. */
-#endif /* configENABLE_MPU */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	movs r1, #0								/* r1 = securecontextNO_STACK. */
-	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
-	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-
-	save_ctx_therad_mode:
-		bx lr
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_heap.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_heap.c
deleted file mode 100644
index c4f613f..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_heap.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure context heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Total heap size.
- */
-#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
-
-/* No test marker by default. */
-#ifndef mtCOVERAGE_TEST_MARKER
-	#define mtCOVERAGE_TEST_MARKER()
-#endif
-
-/* No tracing by default. */
-#ifndef traceMALLOC
-	#define traceMALLOC( pvReturn, xWantedSize )
-#endif
-
-/* No tracing by default. */
-#ifndef traceFREE
-	#define traceFREE( pv, xBlockSize )
-#endif
-
-/* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
-/*-----------------------------------------------------------*/
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	 * heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#else /* configAPPLICATION_ALLOCATED_HEAP */
-	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/**
- * @brief The linked list structure.
- *
- * This is used to link free blocks in order of their memory address.
- */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
-	size_t xBlockSize;						/**< The size of the free block. */
-} BlockLink_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Called automatically to setup the required heap structures the first
- * time pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/**
- * @brief Inserts a block of memory that is being freed into the correct
- * position in the list of free memory blocks.
- *
- * The block being freed will be merged with the block in front it and/or the
- * block behind it if the memory blocks are adjacent to each other.
- *
- * @param[in] pxBlockToInsert The block being freed.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The size of the structure placed at the beginning of each allocated
- * memory block must by correctly byte aligned.
- */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-
-/**
- * @brief Create a couple of list links to mark the start and end of the list.
- */
-static BlockLink_t xStart, *pxEnd = NULL;
-
-/**
- * @brief Keeps track of the number of free bytes remaining, but says nothing
- * about fragmentation.
- */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-size_t uxAddress;
-size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
-
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	uxAddress = ( size_t ) ucHeap;
-
-	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
-	{
-		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
-		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-	}
-
-	pucAlignedHeap = ( uint8_t * ) uxAddress;
-
-	/* xStart is used to hold a pointer to the first item in the list of free
-	 * blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
-
-	/* pxEnd is used to mark the end of the list of free blocks and is inserted
-	 * at the end of the heap space. */
-	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-	uxAddress -= xHeapStructSize;
-	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-	pxEnd = ( void * ) uxAddress;
-	pxEnd->xBlockSize = 0;
-	pxEnd->pxNextFreeBlock = NULL;
-
-	/* To start with there is a single free block that is sized to take up the
-	 * entire heap space, minus the space taken by pxEnd. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
-	/* Only one block exists - and it covers the entire usable heap space. */
-	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
-{
-BlockLink_t *pxIterator;
-uint8_t *puc;
-
-	/* Iterate through the list until a block is found that has a higher address
-	 * than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
-
-	/* Do the block being inserted, and the block it is being inserted after
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Do the block being inserted, and the block it is being inserted before
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
-
-	/* If the block being inserted plugged a gab, so was merged with the block
-	 * before and the block after, then it's pxNextFreeBlock pointer will have
-	 * already been set, and should not be set here as that would make it point
-	 * to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
-
-	/* If this is the first call to malloc then the heap will require
-	 * initialisation to setup the list of free blocks. */
-	if( pxEnd == NULL )
-	{
-		prvHeapInit();
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Check the requested block size is not so large that the top bit is set.
-	 * The top bit of the block size member of the BlockLink_t structure is used
-	 * to determine who owns the block - the application or the kernel, so it
-	 * must be free. */
-	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-	{
-		/* The wanted size is increased so it can contain a BlockLink_t
-		 * structure in addition to the requested amount of bytes. */
-		if( xWantedSize > 0 )
-		{
-			xWantedSize += xHeapStructSize;
-
-			/* Ensure that blocks are always aligned to the required number of
-			 * bytes. */
-			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
-			{
-				/* Byte alignment required. */
-				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-		{
-			/* Traverse the list from the start (lowest address) block until
-			 * one of adequate size is found. */
-			pxPreviousBlock = &xStart;
-			pxBlock = xStart.pxNextFreeBlock;
-			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-			{
-				pxPreviousBlock = pxBlock;
-				pxBlock = pxBlock->pxNextFreeBlock;
-			}
-
-			/* If the end marker was reached then a block of adequate size was
-			 * not found. */
-			if( pxBlock != pxEnd )
-			{
-				/* Return the memory space pointed to - jumping over the
-				 * BlockLink_t structure at its start. */
-				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-				/* This block is being returned for use so must be taken out
-				 * of the list of free blocks. */
-				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-				/* If the block is larger than required it can be split into
-				 * two. */
-				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
-				{
-					/* This block is to be split into two.  Create a new
-					 * block following the number of bytes requested. The void
-					 * cast is used to prevent byte alignment warnings from the
-					 * compiler. */
-					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-
-					/* Calculate the sizes of two blocks split from the single
-					 * block. */
-					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-					pxBlock->xBlockSize = xWantedSize;
-
-					/* Insert the new block into the list of free blocks. */
-					prvInsertBlockIntoFreeList( pxNewBlockLink );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-				{
-					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* The block is being returned - it is allocated and owned by
-				 * the application and has no "next" block. */
-				pxBlock->xBlockSize |= xBlockAllocatedBit;
-				pxBlock->pxNextFreeBlock = NULL;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	traceMALLOC( pvReturn, xWantedSize );
-
-	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
-
-	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		 * before it. */
-		puc -= xHeapStructSize;
-
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
-
-		/* Check the block is actually allocated. */
-		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
-
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				 * allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-				secureportDISABLE_NON_SECURE_INTERRUPTS();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				secureportENABLE_NON_SECURE_INTERRUPTS();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_heap.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_heap.h
deleted file mode 100644
index aae5cfc..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_heap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_HEAP_H__
-#define __SECURE_HEAP_H__
-
-/* Standard includes. */
-#include 
-
-/**
- * @brief Allocates memory from heap.
- *
- * @param[in] xWantedSize The size of the memory to be allocated.
- *
- * @return Pointer to the memory region if the allocation is successful, NULL
- * otherwise.
- */
-void *pvPortMalloc( size_t xWantedSize );
-
-/**
- * @brief Frees the previously allocated memory.
- *
- * @param[in] pv Pointer to the memory to be freed.
- */
-void vPortFree( void *pv );
-
-#endif /* __SECURE_HEAP_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_init.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_init.c
deleted file mode 100644
index 60ef1e8..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_init.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure init includes. */
-#include "secure_init.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS			( 29UL )
-#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS				( 26UL )
-#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
-
-#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS			( 10UL )
-#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS			( 11UL )
-#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
-									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
-									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
-		 * permitted. CP11 should be programmed to the same value as CP10. */
-		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
-
-		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
-		 * that we can enable/disable lazy stacking in port.c file. */
-		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
-
-		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
-		 * registers (S16-S31) are also pushed to stack on exception entry and
-		 * restored on exception return. */
-		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_init.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_init.h
deleted file mode 100644
index 3954e13..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_init.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_INIT_H__
-#define __SECURE_INIT_H__
-
-/**
- * @brief De-prioritizes the non-secure exceptions.
- *
- * This is needed to ensure that the non-secure PendSV runs at the lowest
- * priority. Context switch is done in the non-secure PendSV handler.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_DePrioritizeNSExceptions( void );
-
-/**
- * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
- *
- * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
- * Registers are not leaked to the non-secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_EnableNSFPUAccess( void );
-
-#endif /* __SECURE_INIT_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_port_macros.h
deleted file mode 100644
index f392537..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33/secure/secure_port_macros.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_PORT_MACROS_H__
-#define __SECURE_PORT_MACROS_H__
-
-/**
- * @brief Byte alignment requirements.
- */
-#define secureportBYTE_ALIGNMENT					8
-#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
-
-/**
- * @brief Macro to declare a function as non-secure callable.
- */
-#if defined( __IAR_SYSTEMS_ICC__ )
-	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
-#else
-	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
-#endif
-
-/**
- * @brief Set the secure PRIMASK value.
- */
-#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Set the non-secure PRIMASK value.
- */
-#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Read the PSP value in the given variable.
- */
-#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
-	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
-
-/**
- * @brief Set the PSP to the given value.
- */
-#define secureportSET_PSP( pucCurrentStackPointer ) \
-	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
-
-/**
- * @brief Set the PSPLIM to the given value.
- */
-#define secureportSET_PSPLIM( pucStackLimit ) \
-	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
-
-/**
- * @brief Set the NonSecure MSP to the given value.
- */
-#define secureportSET_MSP_NS( pucMainStackPointer ) \
-	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
-
-/**
- * @brief Set the CONTROL register to the given value.
- */
-#define secureportSET_CONTROL( ulControl ) \
-	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
-
-/**
- * @brief Read the Interrupt Program Status Register (IPSR) value in the given
- * variable.
- */
-#define secureportREAD_IPSR( ulIPSR ) \
-	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
-
-/**
- * @brief PRIMASK value to enable interrupts.
- */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
-
-/**
- * @brief PRIMASK value to disable interrupts.
- */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
-
-/**
- * @brief Disable secure interrupts.
- */
-#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Disable non-secure interrupts.
- *
- * This effectively disables context switches.
- */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Enable non-secure interrupts.
- */
-#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Assert definition.
- */
-#define secureportASSERT( x )						\
-	if( ( x ) == 0 )								\
-	{												\
-		secureportDISABLE_SECURE_INTERRUPTS();		\
-		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
-		for( ;; );									\
-	}
-
-#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
deleted file mode 100644
index 9020541..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-__weak void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
deleted file mode 100644
index 6314e96..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
deleted file mode 100644
index 01dd392..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include 
-
-	EXTERN pxCurrentTCB
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMaskFromISR
-	PUBLIC vClearInterruptMaskFromISR
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	ite ne
-	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	orr r0, r0, #1							/* r0 = r0 | 1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r1, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
-	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str r3, [r2]							/* Program MAIR0. */
-	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r3, #4								/* r3 = 4. */
-	str r3, [r2]							/* Program RNR = 4. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	msr  control, r2						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r2									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs  r0, control						/* Read the CONTROL register. */
-	bic r0, r0, #1							/* Clear the bit 0. */
-	msr  control, r0						/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	cpsie f
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMaskFromISR:
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-/*-----------------------------------------------------------*/
-
-vClearInterruptMaskFromISR:
-	msr PRIMASK, r0
-	bx lr
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	mrs r0, psp								/* Read PSP in r0. */
-#if ( configENABLE_FPU == 1 )
-	tst lr, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	it eq
-	vstmdbeq r0!, {s16-s31}					/* Store the FPU registers which are not saved automatically. */
-#endif /* configENABLE_FPU */
-#if ( configENABLE_MPU == 1 )
-	mrs r1, psplim							/* r1 = PSPLIM. */
-	mrs r2, control							/* r2 = CONTROL. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmdb r0!, {r1-r11}						/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
-#else /* configENABLE_MPU */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmdb r0!, {r2-r11}						/* Store on the stack - PSPLIM, LR and registers that are not automatically. */
-#endif /* configENABLE_MPU */
-
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-	str r0, [r1]							/* Save the new top of stack in TCB. */
-
-	cpsid i
-	bl vTaskSwitchContext
-	cpsie i
-
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
-	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str r3, [r2]							/* Program MAIR0. */
-	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r3, #4								/* r3 = 4. */
-	str r3, [r2]							/* Program RNR = 4. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldmia r0!, {r1-r11}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
-#else /* configENABLE_MPU */
-	ldmia r0!, {r2-r11}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_FPU == 1 )
-	tst r3, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	it eq
-	vldmiaeq r0!, {s16-s31}					/* Restore the FPU registers which are not restored automatically. */
-#endif /* configENABLE_FPU */
-
- #if ( configENABLE_MPU == 1 )
-	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
-	msr control, r2							/* Restore the CONTROL register value for the task. */
-#else /* configENABLE_MPU */
-	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
-#endif /* configENABLE_MPU */
-	msr psp, r0								/* Remember the new top of stack for the task. */
-	bx r3
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	tst lr, #4
-	ite eq
-	mrseq r0, msp
-	mrsne r0, psp
-	b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
deleted file mode 100644
index cd7090d..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- *
- * Copyright 2019 MicroEJ Corp. This file has been modified by MicroEJ Corp.
- * 1. Patch for SystemView support
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			{ if( xSwitchRequired ) { traceISR_EXIT_TO_SCHEDULER(); portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } else { traceISR_EXIT(); } }
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/ReadMe.url b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/ReadMe.url
deleted file mode 100644
index b04bfe3..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/ReadMe.url
+++ /dev/null
@@ -1,5 +0,0 @@
-[{000214A0-0000-0000-C000-000000000046}]
-Prop3=19,2
-[InternetShortcut]
-URL=http://www.freertos.org/a00111.html
-IDList=
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_1.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_1.c
deleted file mode 100644
index 137733a..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_1.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*
- * The simplest possible implementation of pvPortMalloc().  Note that this
- * implementation does NOT allow allocated memory to be freed again.
- *
- * See heap_2.c, heap_3.c and heap_4.c for alternative implementations, and the
- * memory management pages of http://www.FreeRTOS.org for more information.
- */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/* A few bytes might be lost to byte aligning the heap start address. */
-#define configADJUSTED_HEAP_SIZE	( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#else
-	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/* Index into the ucHeap array. */
-static size_t xNextFreeByte = ( size_t ) 0;
-
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-void *pvReturn = NULL;
-static uint8_t *pucAlignedHeap = NULL;
-
-	/* Ensure that blocks are always aligned to the required number of bytes. */
-	#if( portBYTE_ALIGNMENT != 1 )
-	{
-		if( xWantedSize & portBYTE_ALIGNMENT_MASK )
-		{
-			/* Byte alignment required. */
-			xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
-		}
-	}
-	#endif
-
-	vTaskSuspendAll();
-	{
-		if( pucAlignedHeap == NULL )
-		{
-			/* Ensure the heap starts on a correctly aligned boundary. */
-			pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
-		}
-
-		/* Check there is enough room left for the allocation. */
-		if( ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) &&
-			( ( xNextFreeByte + xWantedSize ) > xNextFreeByte )	)/* Check for overflow. */
-		{
-			/* Return the next free byte then increment the index past this
-			block. */
-			pvReturn = pucAlignedHeap + xNextFreeByte;
-			xNextFreeByte += xWantedSize;
-		}
-
-		traceMALLOC( pvReturn, xWantedSize );
-	}
-	( void ) xTaskResumeAll();
-
-	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-	}
-	#endif
-
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-	/* Memory cannot be freed using this scheme.  See heap_2.c, heap_3.c and
-	heap_4.c for alternative implementations, and the memory management pages of
-	http://www.FreeRTOS.org for more information. */
-	( void ) pv;
-
-	/* Force an assert as it is invalid to call this function. */
-	configASSERT( pv == NULL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* Only required when static memory is not cleared. */
-	xNextFreeByte = ( size_t ) 0;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return ( configADJUSTED_HEAP_SIZE - xNextFreeByte );
-}
-
-
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_2.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_2.c
deleted file mode 100644
index 2c5ceb8..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_2.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * A sample implementation of pvPortMalloc() and vPortFree() that permits
- * allocated blocks to be freed, but does not combine adjacent free blocks
- * into a single larger block (and so will fragment memory).  See heap_4.c for
- * an equivalent that does combine adjacent blocks into single larger blocks.
- *
- * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the
- * memory management pages of http://www.FreeRTOS.org for more information.
- */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/* A few bytes might be lost to byte aligning the heap start address. */
-#define configADJUSTED_HEAP_SIZE	( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
-
-/*
- * Initialises the heap structures before their first use.
- */
-static void prvHeapInit( void );
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#else
-	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-
-/* Define the linked list structure.  This is used to link free blocks in order
-of their size. */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
-	size_t xBlockSize;						/*<< The size of the free block. */
-} BlockLink_t;
-
-
-static const uint16_t heapSTRUCT_SIZE	= ( ( sizeof ( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );
-#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )
-
-/* Create a couple of list links to mark the start and end of the list. */
-static BlockLink_t xStart, xEnd;
-
-/* Keeps track of the number of free bytes remaining, but says nothing about
-fragmentation. */
-static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
-
-/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */
-
-/*
- * Insert a block into the list of free blocks - which is ordered by size of
- * the block.  Small blocks at the start of the list and large blocks at the end
- * of the list.
- */
-#define prvInsertBlockIntoFreeList( pxBlockToInsert )								\
-{																					\
-BlockLink_t *pxIterator;															\
-size_t xBlockSize;																	\
-																					\
-	xBlockSize = pxBlockToInsert->xBlockSize;										\
-																					\
-	/* Iterate through the list until a block is found that has a larger size */	\
-	/* than the block we are inserting. */											\
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock )	\
-	{																				\
-		/* There is nothing to do here - just iterate to the correct position. */	\
-	}																				\
-																					\
-	/* Update the list to include the block being inserted in the correct */		\
-	/* position. */																	\
-	pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;					\
-	pxIterator->pxNextFreeBlock = pxBlockToInsert;									\
-}
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-static BaseType_t xHeapHasBeenInitialised = pdFALSE;
-void *pvReturn = NULL;
-
-	vTaskSuspendAll();
-	{
-		/* If this is the first call to malloc then the heap will require
-		initialisation to setup the list of free blocks. */
-		if( xHeapHasBeenInitialised == pdFALSE )
-		{
-			prvHeapInit();
-			xHeapHasBeenInitialised = pdTRUE;
-		}
-
-		/* The wanted size is increased so it can contain a BlockLink_t
-		structure in addition to the requested amount of bytes. */
-		if( xWantedSize > 0 )
-		{
-			xWantedSize += heapSTRUCT_SIZE;
-
-			/* Ensure that blocks are always aligned to the required number of bytes. */
-			if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0 )
-			{
-				/* Byte alignment required. */
-				xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
-			}
-		}
-
-		if( ( xWantedSize > 0 ) && ( xWantedSize < configADJUSTED_HEAP_SIZE ) )
-		{
-			/* Blocks are stored in byte order - traverse the list from the start
-			(smallest) block until one of adequate size is found. */
-			pxPreviousBlock = &xStart;
-			pxBlock = xStart.pxNextFreeBlock;
-			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-			{
-				pxPreviousBlock = pxBlock;
-				pxBlock = pxBlock->pxNextFreeBlock;
-			}
-
-			/* If we found the end marker then a block of adequate size was not found. */
-			if( pxBlock != &xEnd )
-			{
-				/* Return the memory space - jumping over the BlockLink_t structure
-				at its start. */
-				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );
-
-				/* This block is being returned for use so must be taken out of the
-				list of free blocks. */
-				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-				/* If the block is larger than required it can be split into two. */
-				if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
-				{
-					/* This block is to be split into two.  Create a new block
-					following the number of bytes requested. The void cast is
-					used to prevent byte alignment warnings from the compiler. */
-					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-
-					/* Calculate the sizes of two blocks split from the single
-					block. */
-					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-					pxBlock->xBlockSize = xWantedSize;
-
-					/* Insert the new block into the list of free blocks. */
-					prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
-				}
-
-				xFreeBytesRemaining -= pxBlock->xBlockSize;
-			}
-		}
-
-		traceMALLOC( pvReturn, xWantedSize );
-	}
-	( void ) xTaskResumeAll();
-
-	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-	}
-	#endif
-
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		before it. */
-		puc -= heapSTRUCT_SIZE;
-
-		/* This unexpected casting is to keep some compilers from issuing
-		byte alignment warnings. */
-		pxLink = ( void * ) puc;
-
-		vTaskSuspendAll();
-		{
-			/* Add this block to the list of free blocks. */
-			prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-			xFreeBytesRemaining += pxLink->xBlockSize;
-			traceFREE( pv, pxLink->xBlockSize );
-		}
-		( void ) xTaskResumeAll();
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
-
-	/* xStart is used to hold a pointer to the first item in the list of free
-	blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
-
-	/* xEnd is used to mark the end of the list of free blocks. */
-	xEnd.xBlockSize = configADJUSTED_HEAP_SIZE;
-	xEnd.pxNextFreeBlock = NULL;
-
-	/* To start with there is a single free block that is sized to take up the
-	entire heap space. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;
-	pxFirstFreeBlock->pxNextFreeBlock = &xEnd;
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_3.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_3.c
deleted file mode 100644
index c391d46..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_3.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*
- * Implementation of pvPortMalloc() and vPortFree() that relies on the
- * compilers own malloc() and free() implementations.
- *
- * This file can only be used if the linker is configured to to generate
- * a heap memory area.
- *
- * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the
- * memory management pages of http://www.FreeRTOS.org for more information.
- */
-
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-void *pvReturn;
-
-	vTaskSuspendAll();
-	{
-		pvReturn = malloc( xWantedSize );
-		traceMALLOC( pvReturn, xWantedSize );
-	}
-	( void ) xTaskResumeAll();
-
-	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-	}
-	#endif
-
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-	if( pv )
-	{
-		vTaskSuspendAll();
-		{
-			free( pv );
-			traceFREE( pv, 0 );
-		}
-		( void ) xTaskResumeAll();
-	}
-}
-
-
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_4.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_4.c
deleted file mode 100644
index 23714eb..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_4.c
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * A sample implementation of pvPortMalloc() and vPortFree() that combines
- * (coalescences) adjacent memory blocks as they are freed, and in so doing
- * limits memory fragmentation.
- *
- * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
- * memory management pages of http://www.FreeRTOS.org for more information.
- */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/* Block sizes must not get too small. */
-#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define heapBITS_PER_BYTE		( ( size_t ) 8 )
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#else
-	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/* Define the linked list structure.  This is used to link free blocks in order
-of their memory address. */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
-	size_t xBlockSize;						/*<< The size of the free block. */
-} BlockLink_t;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Inserts a block of memory that is being freed into the correct position in
- * the list of free memory blocks.  The block being freed will be merged with
- * the block in front it and/or the block behind it if the memory blocks are
- * adjacent to each other.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
-
-/*
- * Called automatically to setup the required heap structures the first time
- * pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/*-----------------------------------------------------------*/
-
-/* The size of the structure placed at the beginning of each allocated memory
-block must by correctly byte aligned. */
-static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
-
-/* Create a couple of list links to mark the start and end of the list. */
-static BlockLink_t xStart, *pxEnd = NULL;
-
-/* Keeps track of the number of free bytes remaining, but says nothing about
-fragmentation. */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
-member of an BlockLink_t structure is set then the block belongs to the
-application.  When the bit is free the block is still part of the free heap
-space. */
-static size_t xBlockAllocatedBit = 0;
-
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
-
-	vTaskSuspendAll();
-	{
-		/* If this is the first call to malloc then the heap will require
-		initialisation to setup the list of free blocks. */
-		if( pxEnd == NULL )
-		{
-			prvHeapInit();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		/* Check the requested block size is not so large that the top bit is
-		set.  The top bit of the block size member of the BlockLink_t structure
-		is used to determine who owns the block - the application or the
-		kernel, so it must be free. */
-		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-		{
-			/* The wanted size is increased so it can contain a BlockLink_t
-			structure in addition to the requested amount of bytes. */
-			if( xWantedSize > 0 )
-			{
-				xWantedSize += xHeapStructSize;
-
-				/* Ensure that blocks are always aligned to the required number
-				of bytes. */
-				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
-				{
-					/* Byte alignment required. */
-					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
-					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-			{
-				/* Traverse the list from the start	(lowest address) block until
-				one	of adequate size is found. */
-				pxPreviousBlock = &xStart;
-				pxBlock = xStart.pxNextFreeBlock;
-				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-				{
-					pxPreviousBlock = pxBlock;
-					pxBlock = pxBlock->pxNextFreeBlock;
-				}
-
-				/* If the end marker was reached then a block of adequate size
-				was	not found. */
-				if( pxBlock != pxEnd )
-				{
-					/* Return the memory space pointed to - jumping over the
-					BlockLink_t structure at its start. */
-					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-					/* This block is being returned for use so must be taken out
-					of the list of free blocks. */
-					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-					/* If the block is larger than required it can be split into
-					two. */
-					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
-					{
-						/* This block is to be split into two.  Create a new
-						block following the number of bytes requested. The void
-						cast is used to prevent byte alignment warnings from the
-						compiler. */
-						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
-
-						/* Calculate the sizes of two blocks split from the
-						single block. */
-						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-						pxBlock->xBlockSize = xWantedSize;
-
-						/* Insert the new block into the list of free blocks. */
-						prvInsertBlockIntoFreeList( pxNewBlockLink );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-					{
-						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* The block is being returned - it is allocated and owned
-					by the application and has no "next" block. */
-					pxBlock->xBlockSize |= xBlockAllocatedBit;
-					pxBlock->pxNextFreeBlock = NULL;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		traceMALLOC( pvReturn, xWantedSize );
-	}
-	( void ) xTaskResumeAll();
-
-	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
-
-	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		before it. */
-		puc -= xHeapStructSize;
-
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
-
-		/* Check the block is actually allocated. */
-		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		configASSERT( pxLink->pxNextFreeBlock == NULL );
-
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-				vTaskSuspendAll();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				( void ) xTaskResumeAll();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-size_t uxAddress;
-size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
-
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	uxAddress = ( size_t ) ucHeap;
-
-	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
-	{
-		uxAddress += ( portBYTE_ALIGNMENT - 1 );
-		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
-		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-	}
-
-	pucAlignedHeap = ( uint8_t * ) uxAddress;
-
-	/* xStart is used to hold a pointer to the first item in the list of free
-	blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
-
-	/* pxEnd is used to mark the end of the list of free blocks and is inserted
-	at the end of the heap space. */
-	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-	uxAddress -= xHeapStructSize;
-	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
-	pxEnd = ( void * ) uxAddress;
-	pxEnd->xBlockSize = 0;
-	pxEnd->pxNextFreeBlock = NULL;
-
-	/* To start with there is a single free block that is sized to take up the
-	entire heap space, minus the space taken by pxEnd. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
-	/* Only one block exists - and it covers the entire usable heap space. */
-	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
-{
-BlockLink_t *pxIterator;
-uint8_t *puc;
-
-	/* Iterate through the list until a block is found that has a higher address
-	than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
-
-	/* Do the block being inserted, and the block it is being inserted after
-	make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Do the block being inserted, and the block it is being inserted before
-	make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
-
-	/* If the block being inserted plugged a gab, so was merged with the block
-	before and the block after, then it's pxNextFreeBlock pointer will have
-	already been set, and should not be set here as that would make it point
-	to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_5.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_5.c
deleted file mode 100644
index 8e50762..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_5.c
+++ /dev/null
@@ -1,485 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * A sample implementation of pvPortMalloc() that allows the heap to be defined
- * across multiple non-contigous blocks and combines (coalescences) adjacent
- * memory blocks as they are freed.
- *
- * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative
- * implementations, and the memory management pages of http://www.FreeRTOS.org
- * for more information.
- *
- * Usage notes:
- *
- * vPortDefineHeapRegions() ***must*** be called before pvPortMalloc().
- * pvPortMalloc() will be called if any task objects (tasks, queues, event
- * groups, etc.) are created, therefore vPortDefineHeapRegions() ***must*** be
- * called before any other objects are defined.
- *
- * vPortDefineHeapRegions() takes a single parameter.  The parameter is an array
- * of HeapRegion_t structures.  HeapRegion_t is defined in portable.h as
- *
- * typedef struct HeapRegion
- * {
- *	uint8_t *pucStartAddress; << Start address of a block of memory that will be part of the heap.
- *	size_t xSizeInBytes;	  << Size of the block of memory.
- * } HeapRegion_t;
- *
- * The array is terminated using a NULL zero sized region definition, and the
- * memory regions defined in the array ***must*** appear in address order from
- * low address to high address.  So the following is a valid example of how
- * to use the function.
- *
- * HeapRegion_t xHeapRegions[] =
- * {
- * 	{ ( uint8_t * ) 0x80000000UL, 0x10000 }, << Defines a block of 0x10000 bytes starting at address 0x80000000
- * 	{ ( uint8_t * ) 0x90000000UL, 0xa0000 }, << Defines a block of 0xa0000 bytes starting at address of 0x90000000
- * 	{ NULL, 0 }                << Terminates the array.
- * };
- *
- * vPortDefineHeapRegions( xHeapRegions ); << Pass the array into vPortDefineHeapRegions().
- *
- * Note 0x80000000 is the lower address so appears in the array first.
- *
- */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/* Block sizes must not get too small. */
-#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define heapBITS_PER_BYTE		( ( size_t ) 8 )
-
-/* Define the linked list structure.  This is used to link free blocks in order
-of their memory address. */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
-	size_t xBlockSize;						/*<< The size of the free block. */
-} BlockLink_t;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Inserts a block of memory that is being freed into the correct position in
- * the list of free memory blocks.  The block being freed will be merged with
- * the block in front it and/or the block behind it if the memory blocks are
- * adjacent to each other.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
-
-/*-----------------------------------------------------------*/
-
-/* The size of the structure placed at the beginning of each allocated memory
-block must by correctly byte aligned. */
-static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
-
-/* Create a couple of list links to mark the start and end of the list. */
-static BlockLink_t xStart, *pxEnd = NULL;
-
-/* Keeps track of the number of free bytes remaining, but says nothing about
-fragmentation. */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
-member of an BlockLink_t structure is set then the block belongs to the
-application.  When the bit is free the block is still part of the free heap
-space. */
-static size_t xBlockAllocatedBit = 0;
-
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
-
-	/* The heap must be initialised before the first call to
-	prvPortMalloc(). */
-	configASSERT( pxEnd );
-
-	vTaskSuspendAll();
-	{
-		/* Check the requested block size is not so large that the top bit is
-		set.  The top bit of the block size member of the BlockLink_t structure
-		is used to determine who owns the block - the application or the
-		kernel, so it must be free. */
-		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-		{
-			/* The wanted size is increased so it can contain a BlockLink_t
-			structure in addition to the requested amount of bytes. */
-			if( xWantedSize > 0 )
-			{
-				xWantedSize += xHeapStructSize;
-
-				/* Ensure that blocks are always aligned to the required number
-				of bytes. */
-				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
-				{
-					/* Byte alignment required. */
-					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-			{
-				/* Traverse the list from the start	(lowest address) block until
-				one	of adequate size is found. */
-				pxPreviousBlock = &xStart;
-				pxBlock = xStart.pxNextFreeBlock;
-				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-				{
-					pxPreviousBlock = pxBlock;
-					pxBlock = pxBlock->pxNextFreeBlock;
-				}
-
-				/* If the end marker was reached then a block of adequate size
-				was	not found. */
-				if( pxBlock != pxEnd )
-				{
-					/* Return the memory space pointed to - jumping over the
-					BlockLink_t structure at its start. */
-					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-					/* This block is being returned for use so must be taken out
-					of the list of free blocks. */
-					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-					/* If the block is larger than required it can be split into
-					two. */
-					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
-					{
-						/* This block is to be split into two.  Create a new
-						block following the number of bytes requested. The void
-						cast is used to prevent byte alignment warnings from the
-						compiler. */
-						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-
-						/* Calculate the sizes of two blocks split from the
-						single block. */
-						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-						pxBlock->xBlockSize = xWantedSize;
-
-						/* Insert the new block into the list of free blocks. */
-						prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-					{
-						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* The block is being returned - it is allocated and owned
-					by the application and has no "next" block. */
-					pxBlock->xBlockSize |= xBlockAllocatedBit;
-					pxBlock->pxNextFreeBlock = NULL;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		traceMALLOC( pvReturn, xWantedSize );
-	}
-	( void ) xTaskResumeAll();
-
-	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
-
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		before it. */
-		puc -= xHeapStructSize;
-
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
-
-		/* Check the block is actually allocated. */
-		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		configASSERT( pxLink->pxNextFreeBlock == NULL );
-
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-				vTaskSuspendAll();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				( void ) xTaskResumeAll();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
-{
-BlockLink_t *pxIterator;
-uint8_t *puc;
-
-	/* Iterate through the list until a block is found that has a higher address
-	than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
-
-	/* Do the block being inserted, and the block it is being inserted after
-	make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Do the block being inserted, and the block it is being inserted before
-	make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
-
-	/* If the block being inserted plugged a gab, so was merged with the block
-	before and the block after, then it's pxNextFreeBlock pointer will have
-	already been set, and should not be set here as that would make it point
-	to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
-{
-BlockLink_t *pxFirstFreeBlockInRegion = NULL, *pxPreviousFreeBlock;
-size_t xAlignedHeap;
-size_t xTotalRegionSize, xTotalHeapSize = 0;
-BaseType_t xDefinedRegions = 0;
-size_t xAddress;
-const HeapRegion_t *pxHeapRegion;
-
-	/* Can only call once! */
-	configASSERT( pxEnd == NULL );
-
-	pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
-
-	while( pxHeapRegion->xSizeInBytes > 0 )
-	{
-		xTotalRegionSize = pxHeapRegion->xSizeInBytes;
-
-		/* Ensure the heap region starts on a correctly aligned boundary. */
-		xAddress = ( size_t ) pxHeapRegion->pucStartAddress;
-		if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
-		{
-			xAddress += ( portBYTE_ALIGNMENT - 1 );
-			xAddress &= ~portBYTE_ALIGNMENT_MASK;
-
-			/* Adjust the size for the bytes lost to alignment. */
-			xTotalRegionSize -= xAddress - ( size_t ) pxHeapRegion->pucStartAddress;
-		}
-
-		xAlignedHeap = xAddress;
-
-		/* Set xStart if it has not already been set. */
-		if( xDefinedRegions == 0 )
-		{
-			/* xStart is used to hold a pointer to the first item in the list of
-			free blocks.  The void cast is used to prevent compiler warnings. */
-			xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap;
-			xStart.xBlockSize = ( size_t ) 0;
-		}
-		else
-		{
-			/* Should only get here if one region has already been added to the
-			heap. */
-			configASSERT( pxEnd != NULL );
-
-			/* Check blocks are passed in with increasing start addresses. */
-			configASSERT( xAddress > ( size_t ) pxEnd );
-		}
-
-		/* Remember the location of the end marker in the previous region, if
-		any. */
-		pxPreviousFreeBlock = pxEnd;
-
-		/* pxEnd is used to mark the end of the list of free blocks and is
-		inserted at the end of the region space. */
-		xAddress = xAlignedHeap + xTotalRegionSize;
-		xAddress -= xHeapStructSize;
-		xAddress &= ~portBYTE_ALIGNMENT_MASK;
-		pxEnd = ( BlockLink_t * ) xAddress;
-		pxEnd->xBlockSize = 0;
-		pxEnd->pxNextFreeBlock = NULL;
-
-		/* To start with there is a single free block in this region that is
-		sized to take up the entire heap region minus the space taken by the
-		free block structure. */
-		pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap;
-		pxFirstFreeBlockInRegion->xBlockSize = xAddress - ( size_t ) pxFirstFreeBlockInRegion;
-		pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;
-
-		/* If this is not the first region that makes up the entire heap space
-		then link the previous region to this region. */
-		if( pxPreviousFreeBlock != NULL )
-		{
-			pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion;
-		}
-
-		xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize;
-
-		/* Move onto the next HeapRegion_t structure. */
-		xDefinedRegions++;
-		pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
-	}
-
-	xMinimumEverFreeBytesRemaining = xTotalHeapSize;
-	xFreeBytesRemaining = xTotalHeapSize;
-
-	/* Check something was actually defined before it is accessed. */
-	configASSERT( xTotalHeapSize );
-
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
-}
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_useNewlib.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_useNewlib.c
deleted file mode 100644
index 7310cd7..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/MemMang/heap_useNewlib.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/**
- * \file heap_useNewlib.c
- * \brief Wrappers required to use newlib malloc-family within FreeRTOS.
- *
- * \par Overview
- * Route FreeRTOS memory management functions to newlib's malloc family.
- * Thus newlib and FreeRTOS share memory-management routines and memory pool,
- * and all newlib's internal memory-management requirements are supported.
- *
- * \author Dave Nadler
- * \date 2-July-2017
- * \version 11-Sep-2019 malloc accounting, comments, newlib version check
- *
- * \see http://www.nadler.com/embedded/newlibAndFreeRTOS.html
- * \see https://sourceware.org/newlib/libc.html#Reentrancy
- * \see https://sourceware.org/newlib/libc.html#malloc
- * \see https://sourceware.org/newlib/libc.html#index-_005f_005fenv_005flock
- * \see https://sourceware.org/newlib/libc.html#index-_005f_005fmalloc_005flock
- * \see https://sourceforge.net/p/freertos/feature-requests/72/
- * \see http://www.billgatliff.com/newlib.html
- * \see http://wiki.osdev.org/Porting_Newlib
- * \see http://www.embecosm.com/appnotes/ean9/ean9-howto-newlib-1.0.html
- *
- *
- * \copyright
- * (c) Dave Nadler 2017-2019, All Rights Reserved.
- * Web:         http://www.nadler.com
- * email:       drn@nadler.com
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * - Use or redistributions of source code must retain the above copyright notice,
- *   this list of conditions, ALL ORIGINAL COMMENTS, and the following disclaimer.
- *
- * - Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include  // maps to newlib...
-#include  // mallinfo...
-#include   // ENOMEM
-#include 
-#include 
-
-#include "newlib.h"
-#if (__NEWLIB__ != 3) || (__NEWLIB_MINOR__ != 0)
-  #warning "This wrapper was verified for newlib version 3.0.0; please ensure newlib's external requirements for malloc-family are unchanged!"
-#endif
-
-#include "freeRTOS.h" // defines public interface we're implementing here
-#if !defined(configUSE_NEWLIB_REENTRANT) ||  (configUSE_NEWLIB_REENTRANT!=1)
-  #warning "#define configUSE_NEWLIB_REENTRANT 1 // Required for thread-safety of newlib sprintf, strtok, etc..."
-  // If you're *REALLY* sure you don't need FreeRTOS's newlib reentrancy support, remove this warning...
-#endif
-#include "task.h"
-
-// ================================================================================================
-// External routines required by newlib's malloc (sbrk/_sbrk, __malloc_lock/unlock)
-// ================================================================================================
-
-#ifndef NDEBUG
-    static int totalBytesProvidedBySBRK = 0;
-#endif
-
-// Simplistic sbrk implementations assume stack grows downwards from top of memory,
-// and heap grows upwards starting just after BSS.
-// FreeRTOS normally allocates task stacks from a pool placed within BSS or DATA.
-// Thus within a FreeRTOS task, stack pointer is always below end of BSS.
-// When using this module, stacks are allocated from malloc pool, still always prior
-// current unused heap area...
-#if defined(__MCUXPRESSO)
-  #define configLINKER_HEAP_BASE_SYMBOL _pvHeapStart
-  #define configLINKER_HEAP_LIMIT_SYMBOL _pvHeapLimit
-  #define configLINKER_HEAP_SIZE_SYMBOL _HeapSize
-#elif defined(__GNUC__)
-  #define configLINKER_HEAP_BASE_SYMBOL end
-  #define configLINKER_HEAP_LIMIT_SYMBOL __HeapLimit
-  #define configLINKER_HEAP_SIZE_SYMBOL HEAP_SIZE
-#endif
-extern char configLINKER_HEAP_BASE_SYMBOL;
-extern char configLINKER_HEAP_LIMIT_SYMBOL;
-extern char configLINKER_HEAP_SIZE_SYMBOL;
-
-static int heapBytesRemaining = (int)&configLINKER_HEAP_SIZE_SYMBOL; // that's (&__HeapLimit)-(&__HeapBase)
-
-//! sbrk/_sbrk version supporting reentrant newlib (depends upon above symbols defined by linker control file).
-char * sbrk(int incr) {
-    static char *currentHeapEnd = &configLINKER_HEAP_BASE_SYMBOL;
-    vTaskSuspendAll(); // Note: safe to use before FreeRTOS scheduler started
-    char *previousHeapEnd = currentHeapEnd;
-    if (currentHeapEnd + incr > &configLINKER_HEAP_LIMIT_SYMBOL) {
-        #if( configUSE_MALLOC_FAILED_HOOK == 1 )
-        {
-            extern void vApplicationMallocFailedHook( void );
-            vApplicationMallocFailedHook();
-        }
-        #elif 1 // safest default when user doesn't explicitly code configUSE_MALLOC_FAILED_HOOK
-            // If you want to alert debugger or halt...
-            while(1) { __asm("bkpt #0"); }; // Stop in GUI as if at a breakpoint (if debugging, otherwise loop forever)
-        #else
-            // If you prefer to believe your application will gracefully trap out-of-memory...
-            _impure_ptr->_errno = ENOMEM; // newlib's thread-specific errno
-            xTaskResumeAll();
-        #endif
-        return (char *)-1; // the malloc-family routine that called sbrk will return 0
-    }
-    // 'incr' of memory is available: update accounting and return it.
-    currentHeapEnd += incr;
-    heapBytesRemaining -= incr;
-    #ifndef NDEBUG
-        totalBytesProvidedBySBRK += incr;
-    #endif
-    xTaskResumeAll();
-    return (char *) previousHeapEnd;
-}
-//! Synonym for sbrk.
-char * _sbrk(int incr) { return sbrk(incr); };
-
-void __malloc_lock(struct _reent *p)   { configASSERT( !xPortIsInsideInterrupt() ); // Make damn sure no mallocs inside ISRs!!
-                                               vTaskSuspendAll(); };
-void __malloc_unlock(struct _reent *p) { (void)xTaskResumeAll();  };
-
-// newlib also requires implementing locks for the application's environment memory space,
-// accessed by newlib's setenv() and getenv() functions.
-// As these are trivial functions, momentarily suspend task switching (rather than semaphore).
-// ToDo: Move __env_lock/unlock to a separate newlib helper file.
-void __env_lock()    {       vTaskSuspendAll(); };
-void __env_unlock()  { (void)xTaskResumeAll();  };
-
-#if 1 // Provide malloc debug and accounting wrappers
-  /// /brief  Wrap malloc/malloc_r to help debug who requests memory and why.
-  /// To use these, add linker options: -Xlinker --wrap=malloc -Xlinker --wrap=_malloc_r
-  // Note: These functions are normally unused and stripped by linker.
-  int TotalMallocdBytes;
-  int MallocCallCnt;
-  static bool inside_malloc;
-  void *__wrap_malloc(size_t nbytes) {
-    extern void * __real_malloc(size_t nbytes);
-    MallocCallCnt++;
-    TotalMallocdBytes += nbytes;
-    inside_malloc = true;
-      void *p = __real_malloc(nbytes); // will call malloc_r...
-    inside_malloc = false;
-    return p;
-  };
-  void *__wrap__malloc_r(void *reent, size_t nbytes) {
-    extern void * __real__malloc_r(size_t nbytes);
-    if(!inside_malloc) {
-      MallocCallCnt++;
-      TotalMallocdBytes += nbytes;
-    };
-    void *p = __real__malloc_r(nbytes);
-    return p;
-  };
-#endif
-
-// ================================================================================================
-// Implement FreeRTOS's memory API using newlib-provided malloc family.
-// ================================================================================================
-
-void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION {
-    void *p = malloc(xSize);
-    return p;
-}
-void vPortFree( void *pv ) PRIVILEGED_FUNCTION {
-    free(pv);
-};
-
-size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION {
-    struct mallinfo mi = mallinfo(); // available space now managed by newlib
-    return mi.fordblks + heapBytesRemaining; // plus space not yet handed to newlib by sbrk
-}
-
-// GetMinimumEverFree is not available in newlib's malloc implementation.
-// So, no implementation is provided: size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
-
-//! No implementation needed, but stub provided in case application already calls vPortInitialiseBlocks
-void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION {};
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/readme.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/readme.txt
deleted file mode 100644
index b22b36b..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/portable/readme.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Each real time kernel port consists of three files that contain the core kernel
-components and are common to every port, and one or more files that are
-specific to a particular microcontroller and/or compiler.
-
-
-+ The FreeRTOS/Source/Portable/MemMang directory contains the five sample
-memory allocators as described on the http://www.FreeRTOS.org WEB site.
-
-+ The other directories each contain files specific to a particular
-microcontroller or compiler, where the directory name denotes the compiler
-specific files the directory contains.
-
-
-
-For example, if you are interested in the [compiler] port for the [architecture]
-microcontroller, then the port specific files are contained in
-FreeRTOS/Source/Portable/[compiler]/[architecture] directory.  If this is the
-only port you are interested in then all the other directories can be
-ignored.
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/queue.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/queue.c
deleted file mode 100644
index 28993d5..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/queue.c
+++ /dev/null
@@ -1,2943 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include 
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-
-#if ( configUSE_CO_ROUTINES == 1 )
-	#include "croutine.h"
-#endif
-
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
-because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
-for the header files above, but not in this file, in order to generate the
-correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
-
-
-/* Constants used with the cRxLock and cTxLock structure members. */
-#define queueUNLOCKED					( ( int8_t ) -1 )
-#define queueLOCKED_UNMODIFIED			( ( int8_t ) 0 )
-
-/* When the Queue_t structure is used to represent a base queue its pcHead and
-pcTail members are used as pointers into the queue storage area.  When the
-Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
-not necessary, and the pcHead pointer is set to NULL to indicate that the
-structure instead holds a pointer to the mutex holder (if any).  Map alternative
-names to the pcHead and structure member to ensure the readability of the code
-is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
-a union as their usage is mutually exclusive dependent on what the queue is
-being used for. */
-#define uxQueueType						pcHead
-#define queueQUEUE_IS_MUTEX				NULL
-
-typedef struct QueuePointers
-{
-	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
-	int8_t *pcReadFrom;				/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
-} QueuePointers_t;
-
-typedef struct SemaphoreData
-{
-	TaskHandle_t xMutexHolder;		 /*< The handle of the task that holds the mutex. */
-	UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
-} SemaphoreData_t;
-
-/* Semaphores do not actually store or copy data, so have an item size of
-zero. */
-#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
-#define queueMUTEX_GIVE_BLOCK_TIME		 ( ( TickType_t ) 0U )
-
-#if( configUSE_PREEMPTION == 0 )
-	/* If the cooperative scheduler is being used then a yield should not be
-	performed just because a higher priority task has been woken. */
-	#define queueYIELD_IF_USING_PREEMPTION()
-#else
-	#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
-#endif
-
-/*
- * Definition of the queue used by the scheduler.
- * Items are queued by copy, not reference.  See the following link for the
- * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
- */
-typedef struct QueueDefinition 		/* The old naming convention is used to prevent breaking kernel aware debuggers. */
-{
-	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
-	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
-
-	union
-	{
-		QueuePointers_t xQueue;		/*< Data required exclusively when this structure is used as a queue. */
-		SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
-	} u;
-
-	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
-	List_t xTasksWaitingToReceive;	/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
-
-	volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
-	UBaseType_t uxLength;			/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
-	UBaseType_t uxItemSize;			/*< The size of each items that the queue will hold. */
-
-	volatile int8_t cRxLock;		/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
-	volatile int8_t cTxLock;		/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
-
-	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-		uint8_t ucStaticallyAllocated;	/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
-	#endif
-
-	#if ( configUSE_QUEUE_SETS == 1 )
-		struct QueueDefinition *pxQueueSetContainer;
-	#endif
-
-	#if ( configUSE_TRACE_FACILITY == 1 )
-		UBaseType_t uxQueueNumber;
-		uint8_t ucQueueType;
-	#endif
-
-} xQUEUE;
-
-/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
-name below to enable the use of older kernel aware debuggers. */
-typedef xQUEUE Queue_t;
-
-/*-----------------------------------------------------------*/
-
-/*
- * The queue registry is just a means for kernel aware debuggers to locate
- * queue structures.  It has no other purpose so is an optional component.
- */
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-	/* The type stored within the queue registry array.  This allows a name
-	to be assigned to each queue making kernel aware debugging a little
-	more user friendly. */
-	typedef struct QUEUE_REGISTRY_ITEM
-	{
-		const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-		QueueHandle_t xHandle;
-	} xQueueRegistryItem;
-
-	/* The old xQueueRegistryItem name is maintained above then typedefed to the
-	new xQueueRegistryItem name below to enable the use of older kernel aware
-	debuggers. */
-	typedef xQueueRegistryItem QueueRegistryItem_t;
-
-	/* The queue registry is simply an array of QueueRegistryItem_t structures.
-	The pcQueueName member of a structure being NULL is indicative of the
-	array position being vacant. */
-	PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
-
-#endif /* configQUEUE_REGISTRY_SIZE */
-
-/*
- * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
- * prevent an ISR from adding or removing items to the queue, but does prevent
- * an ISR from removing tasks from the queue event lists.  If an ISR finds a
- * queue is locked it will instead increment the appropriate queue lock count
- * to indicate that a task may require unblocking.  When the queue in unlocked
- * these lock counts are inspected, and the appropriate action taken.
- */
-static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * Uses a critical section to determine if there is any data in a queue.
- *
- * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
- */
-static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * Uses a critical section to determine if there is any space in a queue.
- *
- * @return pdTRUE if there is no space, otherwise pdFALSE;
- */
-static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * Copies an item into the queue, either at the front of the queue or the
- * back of the queue.
- */
-static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
-
-/*
- * Copies an item out of a queue.
- */
-static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
-
-#if ( configUSE_QUEUE_SETS == 1 )
-	/*
-	 * Checks to see if a queue is a member of a queue set, and if so, notifies
-	 * the queue set that the queue contains data.
-	 */
-	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
-#endif
-
-/*
- * Called after a Queue_t structure has been allocated either statically or
- * dynamically to fill in the structure's members.
- */
-static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * Mutexes are a special type of queue.  When a mutex is created, first the
- * queue is created, then prvInitialiseMutex() is called to configure the queue
- * as a mutex.
- */
-#if( configUSE_MUTEXES == 1 )
-	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
-#endif
-
-#if( configUSE_MUTEXES == 1 )
-	/*
-	 * If a task waiting for a mutex causes the mutex holder to inherit a
-	 * priority, but the waiting task times out, then the holder should
-	 * disinherit the priority - but only down to the highest priority of any
-	 * other tasks that are waiting for the same mutex.  This function returns
-	 * that priority.
-	 */
-	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
-#endif
-/*-----------------------------------------------------------*/
-
-/*
- * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
- * accessing the queue event lists.
- */
-#define prvLockQueue( pxQueue )								\
-	taskENTER_CRITICAL();									\
-	{														\
-		if( ( pxQueue )->cRxLock == queueUNLOCKED )			\
-		{													\
-			( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;	\
-		}													\
-		if( ( pxQueue )->cTxLock == queueUNLOCKED )			\
-		{													\
-			( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;	\
-		}													\
-	}														\
-	taskEXIT_CRITICAL()
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
-{
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-
-	taskENTER_CRITICAL();
-	{
-		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
-		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
-		pxQueue->pcWriteTo = pxQueue->pcHead;
-		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
-		pxQueue->cRxLock = queueUNLOCKED;
-		pxQueue->cTxLock = queueUNLOCKED;
-
-		if( xNewQueue == pdFALSE )
-		{
-			/* If there are tasks blocked waiting to read from the queue, then
-			the tasks will remain blocked as after this function exits the queue
-			will still be empty.  If there are tasks blocked waiting to write to
-			the queue, then one should be unblocked as after this function exits
-			it will be possible to write to it. */
-			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-			{
-				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-				{
-					queueYIELD_IF_USING_PREEMPTION();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			/* Ensure the event queues start in the correct state. */
-			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
-			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	/* A value is returned for calling semantic consistency with previous
-	versions. */
-	return pdPASS;
-}
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
-	{
-	Queue_t *pxNewQueue;
-
-		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
-
-		/* The StaticQueue_t structure and the queue storage area must be
-		supplied. */
-		configASSERT( pxStaticQueue != NULL );
-
-		/* A queue storage area should be provided if the item size is not 0, and
-		should not be provided if the item size is 0. */
-		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
-		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
-
-		#if( configASSERT_DEFINED == 1 )
-		{
-			/* Sanity check that the size of the structure used to declare a
-			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
-			the real queue and semaphore structures. */
-			volatile size_t xSize = sizeof( StaticQueue_t );
-			configASSERT( xSize == sizeof( Queue_t ) );
-			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
-		}
-		#endif /* configASSERT_DEFINED */
-
-		/* The address of a statically allocated queue was passed in, use it.
-		The address of a statically allocated storage area was also passed in
-		but is already set. */
-		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
-
-		if( pxNewQueue != NULL )
-		{
-			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-			{
-				/* Queues can be allocated wither statically or dynamically, so
-				note this queue was allocated statically in case the queue is
-				later deleted. */
-				pxNewQueue->ucStaticallyAllocated = pdTRUE;
-			}
-			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-
-			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
-		}
-		else
-		{
-			traceQUEUE_CREATE_FAILED( ucQueueType );
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return pxNewQueue;
-	}
-
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
-	{
-	Queue_t *pxNewQueue;
-	size_t xQueueSizeInBytes;
-	uint8_t *pucQueueStorage;
-
-		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
-
-		if( uxItemSize == ( UBaseType_t ) 0 )
-		{
-			/* There is not going to be a queue storage area. */
-			xQueueSizeInBytes = ( size_t ) 0;
-		}
-		else
-		{
-			/* Allocate enough space to hold the maximum number of items that
-			can be in the queue at any time. */
-			xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-		}
-
-		/* Allocate the queue and storage area.  Justification for MISRA
-		deviation as follows:  pvPortMalloc() always ensures returned memory
-		blocks are aligned per the requirements of the MCU stack.  In this case
-		pvPortMalloc() must return a pointer that is guaranteed to meet the
-		alignment requirements of the Queue_t structure - which in this case
-		is an int8_t *.  Therefore, whenever the stack alignment requirements
-		are greater than or equal to the pointer to char requirements the cast
-		is safe.  In other cases alignment requirements are not strict (one or
-		two bytes). */
-		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
-
-		if( pxNewQueue != NULL )
-		{
-			/* Jump past the queue structure to find the location of the queue
-			storage area. */
-			pucQueueStorage = ( uint8_t * ) pxNewQueue;
-			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
-
-			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-			{
-				/* Queues can be created either statically or dynamically, so
-				note this task was created dynamically in case it is later
-				deleted. */
-				pxNewQueue->ucStaticallyAllocated = pdFALSE;
-			}
-			#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
-		}
-		else
-		{
-			traceQUEUE_CREATE_FAILED( ucQueueType );
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return pxNewQueue;
-	}
-
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
-{
-	/* Remove compiler warnings about unused parameters should
-	configUSE_TRACE_FACILITY not be set to 1. */
-	( void ) ucQueueType;
-
-	if( uxItemSize == ( UBaseType_t ) 0 )
-	{
-		/* No RAM was allocated for the queue storage area, but PC head cannot
-		be set to NULL because NULL is used as a key to say the queue is used as
-		a mutex.  Therefore just set pcHead to point to the queue as a benign
-		value that is known to be within the memory map. */
-		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
-	}
-	else
-	{
-		/* Set the head to the start of the queue storage area. */
-		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
-	}
-
-	/* Initialise the queue members as described where the queue type is
-	defined. */
-	pxNewQueue->uxLength = uxQueueLength;
-	pxNewQueue->uxItemSize = uxItemSize;
-	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
-
-	#if ( configUSE_TRACE_FACILITY == 1 )
-	{
-		pxNewQueue->ucQueueType = ucQueueType;
-	}
-	#endif /* configUSE_TRACE_FACILITY */
-
-	#if( configUSE_QUEUE_SETS == 1 )
-	{
-		pxNewQueue->pxQueueSetContainer = NULL;
-	}
-	#endif /* configUSE_QUEUE_SETS */
-
-	traceQUEUE_CREATE( pxNewQueue );
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_MUTEXES == 1 )
-
-	static void prvInitialiseMutex( Queue_t *pxNewQueue )
-	{
-		if( pxNewQueue != NULL )
-		{
-			/* The queue create function will set all the queue structure members
-			correctly for a generic queue, but this function is creating a
-			mutex.  Overwrite those members that need to be set differently -
-			in particular the information required for priority inheritance. */
-			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
-			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
-
-			/* In case this is a recursive mutex. */
-			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
-
-			traceCREATE_MUTEX( pxNewQueue );
-
-			/* Start with the semaphore in the expected state. */
-			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
-		}
-		else
-		{
-			traceCREATE_MUTEX_FAILED();
-		}
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
-	{
-	QueueHandle_t xNewQueue;
-	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
-
-		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
-		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
-
-		return xNewQueue;
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
-	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
-	{
-	QueueHandle_t xNewQueue;
-	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
-
-		/* Prevent compiler warnings about unused parameters if
-		configUSE_TRACE_FACILITY does not equal 1. */
-		( void ) ucQueueType;
-
-		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
-		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
-
-		return xNewQueue;
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
-
-	TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
-	{
-	TaskHandle_t pxReturn;
-	Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
-
-		/* This function is called by xSemaphoreGetMutexHolder(), and should not
-		be called directly.  Note:  This is a good way of determining if the
-		calling task is the mutex holder, but not a good way of determining the
-		identity of the mutex holder, as the holder may change between the
-		following critical section exiting and the function returning. */
-		taskENTER_CRITICAL();
-		{
-			if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
-			{
-				pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
-			}
-			else
-			{
-				pxReturn = NULL;
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		return pxReturn;
-	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
-
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
-
-	TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
-	{
-	TaskHandle_t pxReturn;
-
-		configASSERT( xSemaphore );
-
-		/* Mutexes cannot be used in interrupt service routines, so the mutex
-		holder should not change in an ISR, and therefore a critical section is
-		not required here. */
-		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
-		{
-			pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
-		}
-		else
-		{
-			pxReturn = NULL;
-		}
-
-		return pxReturn;
-	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
-
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-
-	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
-	{
-	BaseType_t xReturn;
-	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
-
-		configASSERT( pxMutex );
-
-		/* If this is the task that holds the mutex then xMutexHolder will not
-		change outside of this task.  If this task does not hold the mutex then
-		pxMutexHolder can never coincidentally equal the tasks handle, and as
-		this is the only condition we are interested in it does not matter if
-		pxMutexHolder is accessed simultaneously by another task.  Therefore no
-		mutual exclusion is required to test the pxMutexHolder variable. */
-		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
-		{
-			traceGIVE_MUTEX_RECURSIVE( pxMutex );
-
-			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
-			the task handle, therefore no underflow check is required.  Also,
-			uxRecursiveCallCount is only modified by the mutex holder, and as
-			there can only be one, no mutual exclusion is required to modify the
-			uxRecursiveCallCount member. */
-			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
-
-			/* Has the recursive call count unwound to 0? */
-			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
-			{
-				/* Return the mutex.  This will automatically unblock any other
-				task that might be waiting to access the mutex. */
-				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			xReturn = pdPASS;
-		}
-		else
-		{
-			/* The mutex cannot be given because the calling task is not the
-			holder. */
-			xReturn = pdFAIL;
-
-			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_RECURSIVE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-
-	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
-	{
-	BaseType_t xReturn;
-	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
-
-		configASSERT( pxMutex );
-
-		/* Comments regarding mutual exclusion as per those within
-		xQueueGiveMutexRecursive(). */
-
-		traceTAKE_MUTEX_RECURSIVE( pxMutex );
-
-		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
-		{
-			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
-			xReturn = pdPASS;
-		}
-		else
-		{
-			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
-
-			/* pdPASS will only be returned if the mutex was successfully
-			obtained.  The calling task may have entered the Blocked state
-			before reaching here. */
-			if( xReturn != pdFAIL )
-			{
-				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
-			}
-			else
-			{
-				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
-			}
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_RECURSIVE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
-	QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
-	{
-	QueueHandle_t xHandle;
-
-		configASSERT( uxMaxCount != 0 );
-		configASSERT( uxInitialCount <= uxMaxCount );
-
-		xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
-
-		if( xHandle != NULL )
-		{
-			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
-
-			traceCREATE_COUNTING_SEMAPHORE();
-		}
-		else
-		{
-			traceCREATE_COUNTING_SEMAPHORE_FAILED();
-		}
-
-		return xHandle;
-	}
-
-#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-	QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
-	{
-	QueueHandle_t xHandle;
-
-		configASSERT( uxMaxCount != 0 );
-		configASSERT( uxInitialCount <= uxMaxCount );
-
-		xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
-
-		if( xHandle != NULL )
-		{
-			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
-
-			traceCREATE_COUNTING_SEMAPHORE();
-		}
-		else
-		{
-			traceCREATE_COUNTING_SEMAPHORE_FAILED();
-		}
-
-		return xHandle;
-	}
-
-#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
-{
-BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
-TimeOut_t xTimeOut;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
-	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-	{
-		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-	}
-	#endif
-
-
-	/*lint -save -e904 This function relaxes the coding standard somewhat to
-	allow return statements within the function itself.  This is done in the
-	interest of execution time efficiency. */
-	for( ;; )
-	{
-		taskENTER_CRITICAL();
-		{
-			/* Is there room on the queue now?  The running task must be the
-			highest priority task wanting to access the queue.  If the head item
-			in the queue is to be overwritten then it does not matter if the
-			queue is full. */
-			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
-			{
-				traceQUEUE_SEND( pxQueue );
-
-				#if ( configUSE_QUEUE_SETS == 1 )
-				{
-				UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
-
-					if( pxQueue->pxQueueSetContainer != NULL )
-					{
-						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
-						{
-							/* Do not notify the queue set as an existing item
-							was overwritten in the queue so the number of items
-							in the queue has not changed. */
-							mtCOVERAGE_TEST_MARKER();
-						}
-						else if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
-						{
-							/* The queue is a member of a queue set, and posting
-							to the queue set caused a higher priority task to
-							unblock. A context switch is required. */
-							queueYIELD_IF_USING_PREEMPTION();
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						/* If there was a task waiting for data to arrive on the
-						queue then unblock it now. */
-						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-						{
-							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-							{
-								/* The unblocked task has a priority higher than
-								our own so yield immediately.  Yes it is ok to
-								do this from within the critical section - the
-								kernel takes care of that. */
-								queueYIELD_IF_USING_PREEMPTION();
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else if( xYieldRequired != pdFALSE )
-						{
-							/* This path is a special case that will only get
-							executed if the task was holding multiple mutexes
-							and the mutexes were given back in an order that is
-							different to that in which they were taken. */
-							queueYIELD_IF_USING_PREEMPTION();
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-				}
-				#else /* configUSE_QUEUE_SETS */
-				{
-					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
-
-					/* If there was a task waiting for data to arrive on the
-					queue then unblock it now. */
-					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-					{
-						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-						{
-							/* The unblocked task has a priority higher than
-							our own so yield immediately.  Yes it is ok to do
-							this from within the critical section - the kernel
-							takes care of that. */
-							queueYIELD_IF_USING_PREEMPTION();
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else if( xYieldRequired != pdFALSE )
-					{
-						/* This path is a special case that will only get
-						executed if the task was holding multiple mutexes and
-						the mutexes were given back in an order that is
-						different to that in which they were taken. */
-						queueYIELD_IF_USING_PREEMPTION();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				#endif /* configUSE_QUEUE_SETS */
-
-				taskEXIT_CRITICAL();
-				return pdPASS;
-			}
-			else
-			{
-				if( xTicksToWait == ( TickType_t ) 0 )
-				{
-					/* The queue was full and no block time is specified (or
-					the block time has expired) so leave now. */
-					taskEXIT_CRITICAL();
-
-					/* Return to the original privilege level before exiting
-					the function. */
-					traceQUEUE_SEND_FAILED( pxQueue );
-					return errQUEUE_FULL;
-				}
-				else if( xEntryTimeSet == pdFALSE )
-				{
-					/* The queue was full and a block time was specified so
-					configure the timeout structure. */
-					vTaskInternalSetTimeOutState( &xTimeOut );
-					xEntryTimeSet = pdTRUE;
-				}
-				else
-				{
-					/* Entry time was already set. */
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		/* Interrupts and other tasks can send to and receive from the queue
-		now the critical section has been exited. */
-
-		vTaskSuspendAll();
-		prvLockQueue( pxQueue );
-
-		/* Update the timeout state to see if it has expired yet. */
-		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
-		{
-			if( prvIsQueueFull( pxQueue ) != pdFALSE )
-			{
-				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
-				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
-
-				/* Unlocking the queue means queue events can effect the
-				event list.  It is possible that interrupts occurring now
-				remove this task from the event list again - but as the
-				scheduler is suspended the task will go onto the pending
-				ready last instead of the actual ready list. */
-				prvUnlockQueue( pxQueue );
-
-				/* Resuming the scheduler will move tasks from the pending
-				ready list into the ready list - so it is feasible that this
-				task is already in a ready list before it yields - in which
-				case the yield will not cause a context switch unless there
-				is also a higher priority task in the pending ready list. */
-				if( xTaskResumeAll() == pdFALSE )
-				{
-					portYIELD_WITHIN_API();
-				}
-			}
-			else
-			{
-				/* Try again. */
-				prvUnlockQueue( pxQueue );
-				( void ) xTaskResumeAll();
-			}
-		}
-		else
-		{
-			/* The timeout has expired. */
-			prvUnlockQueue( pxQueue );
-			( void ) xTaskResumeAll();
-
-			traceQUEUE_SEND_FAILED( pxQueue );
-			return errQUEUE_FULL;
-		}
-	} /*lint -restore */
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
-{
-BaseType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
-
-	/* RTOS ports that support interrupt nesting have the concept of a maximum
-	system call (or maximum API call) interrupt priority.  Interrupts that are
-	above the maximum system call priority are kept permanently enabled, even
-	when the RTOS kernel is in a critical section, but cannot make any calls to
-	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-	failure if a FreeRTOS API function is called from an interrupt that has been
-	assigned a priority above the configured maximum system call priority.
-	Only FreeRTOS functions that end in FromISR can be called from interrupts
-	that have been assigned a priority at or (logically) below the maximum
-	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
-	safe API to ensure interrupt entry is as fast and as simple as possible.
-	More information (albeit Cortex-M specific) is provided on the following
-	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
-	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-	/* Similar to xQueueGenericSend, except without blocking if there is no room
-	in the queue.  Also don't directly wake a task that was blocked on a queue
-	read, instead return a flag to say whether a context switch is required or
-	not (i.e. has a task with a higher priority than us been woken by this
-	post). */
-	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
-		{
-			const int8_t cTxLock = pxQueue->cTxLock;
-
-			traceQUEUE_SEND_FROM_ISR( pxQueue );
-
-			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
-			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
-			in a task disinheriting a priority and prvCopyDataToQueue() can be
-			called here even though the disinherit function does not check if
-			the scheduler is suspended before accessing the ready lists. */
-			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
-
-			/* The event list is not altered if the queue is locked.  This will
-			be done when the queue is unlocked later. */
-			if( cTxLock == queueUNLOCKED )
-			{
-				#if ( configUSE_QUEUE_SETS == 1 )
-				{
-					if( pxQueue->pxQueueSetContainer != NULL )
-					{
-						if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
-						{
-							/* The queue is a member of a queue set, and posting
-							to the queue set caused a higher priority task to
-							unblock.  A context switch is required. */
-							if( pxHigherPriorityTaskWoken != NULL )
-							{
-								*pxHigherPriorityTaskWoken = pdTRUE;
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-						{
-							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-							{
-								/* The task waiting has a higher priority so
-								record that a context switch is required. */
-								if( pxHigherPriorityTaskWoken != NULL )
-								{
-									*pxHigherPriorityTaskWoken = pdTRUE;
-								}
-								else
-								{
-									mtCOVERAGE_TEST_MARKER();
-								}
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-				}
-				#else /* configUSE_QUEUE_SETS */
-				{
-					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-					{
-						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-						{
-							/* The task waiting has a higher priority so record that a
-							context	switch is required. */
-							if( pxHigherPriorityTaskWoken != NULL )
-							{
-								*pxHigherPriorityTaskWoken = pdTRUE;
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				#endif /* configUSE_QUEUE_SETS */
-			}
-			else
-			{
-				/* Increment the lock count so the task that unlocks the queue
-				knows that data was posted while it was locked. */
-				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
-			}
-
-			xReturn = pdPASS;
-		}
-		else
-		{
-			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
-			xReturn = errQUEUE_FULL;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
-{
-BaseType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = xQueue;
-
-	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
-	item size is 0.  Don't directly wake a task that was blocked on a queue
-	read, instead return a flag to say whether a context switch is required or
-	not (i.e. has a task with a higher priority than us been woken by this
-	post). */
-
-	configASSERT( pxQueue );
-
-	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
-	if the item size is not 0. */
-	configASSERT( pxQueue->uxItemSize == 0 );
-
-	/* Normally a mutex would not be given from an interrupt, especially if
-	there is a mutex holder, as priority inheritance makes no sense for an
-	interrupts, only tasks. */
-	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
-
-	/* RTOS ports that support interrupt nesting have the concept of a maximum
-	system call (or maximum API call) interrupt priority.  Interrupts that are
-	above the maximum system call priority are kept permanently enabled, even
-	when the RTOS kernel is in a critical section, but cannot make any calls to
-	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-	failure if a FreeRTOS API function is called from an interrupt that has been
-	assigned a priority above the configured maximum system call priority.
-	Only FreeRTOS functions that end in FromISR can be called from interrupts
-	that have been assigned a priority at or (logically) below the maximum
-	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
-	safe API to ensure interrupt entry is as fast and as simple as possible.
-	More information (albeit Cortex-M specific) is provided on the following
-	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
-	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-		/* When the queue is used to implement a semaphore no data is ever
-		moved through the queue but it is still valid to see if the queue 'has
-		space'. */
-		if( uxMessagesWaiting < pxQueue->uxLength )
-		{
-			const int8_t cTxLock = pxQueue->cTxLock;
-
-			traceQUEUE_SEND_FROM_ISR( pxQueue );
-
-			/* A task can only have an inherited priority if it is a mutex
-			holder - and if there is a mutex holder then the mutex cannot be
-			given from an ISR.  As this is the ISR version of the function it
-			can be assumed there is no mutex holder and no need to determine if
-			priority disinheritance is needed.  Simply increase the count of
-			messages (semaphores) available. */
-			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
-
-			/* The event list is not altered if the queue is locked.  This will
-			be done when the queue is unlocked later. */
-			if( cTxLock == queueUNLOCKED )
-			{
-				#if ( configUSE_QUEUE_SETS == 1 )
-				{
-					if( pxQueue->pxQueueSetContainer != NULL )
-					{
-						if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
-						{
-							/* The semaphore is a member of a queue set, and
-							posting	to the queue set caused a higher priority
-							task to	unblock.  A context switch is required. */
-							if( pxHigherPriorityTaskWoken != NULL )
-							{
-								*pxHigherPriorityTaskWoken = pdTRUE;
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-						{
-							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-							{
-								/* The task waiting has a higher priority so
-								record that a context switch is required. */
-								if( pxHigherPriorityTaskWoken != NULL )
-								{
-									*pxHigherPriorityTaskWoken = pdTRUE;
-								}
-								else
-								{
-									mtCOVERAGE_TEST_MARKER();
-								}
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-				}
-				#else /* configUSE_QUEUE_SETS */
-				{
-					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-					{
-						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-						{
-							/* The task waiting has a higher priority so record that a
-							context	switch is required. */
-							if( pxHigherPriorityTaskWoken != NULL )
-							{
-								*pxHigherPriorityTaskWoken = pdTRUE;
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				#endif /* configUSE_QUEUE_SETS */
-			}
-			else
-			{
-				/* Increment the lock count so the task that unlocks the queue
-				knows that data was posted while it was locked. */
-				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
-			}
-
-			xReturn = pdPASS;
-		}
-		else
-		{
-			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
-			xReturn = errQUEUE_FULL;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
-{
-BaseType_t xEntryTimeSet = pdFALSE;
-TimeOut_t xTimeOut;
-Queue_t * const pxQueue = xQueue;
-
-	/* Check the pointer is not NULL. */
-	configASSERT( ( pxQueue ) );
-
-	/* The buffer into which data is received can only be NULL if the data size
-	is zero (so no data is copied into the buffer. */
-	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
-
-	/* Cannot block if the scheduler is suspended. */
-	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-	{
-		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-	}
-	#endif
-
-
-	/*lint -save -e904  This function relaxes the coding standard somewhat to
-	allow return statements within the function itself.  This is done in the
-	interest of execution time efficiency. */
-	for( ;; )
-	{
-		taskENTER_CRITICAL();
-		{
-			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-			/* Is there data in the queue now?  To be running the calling task
-			must be the highest priority task wanting to access the queue. */
-			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
-			{
-				/* Data available, remove one item. */
-				prvCopyDataFromQueue( pxQueue, pvBuffer );
-				traceQUEUE_RECEIVE( pxQueue );
-				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
-
-				/* There is now space in the queue, were any tasks waiting to
-				post to the queue?  If so, unblock the highest priority waiting
-				task. */
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-				{
-					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-					{
-						queueYIELD_IF_USING_PREEMPTION();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				taskEXIT_CRITICAL();
-				return pdPASS;
-			}
-			else
-			{
-				if( xTicksToWait == ( TickType_t ) 0 )
-				{
-					/* The queue was empty and no block time is specified (or
-					the block time has expired) so leave now. */
-					taskEXIT_CRITICAL();
-					traceQUEUE_RECEIVE_FAILED( pxQueue );
-					return errQUEUE_EMPTY;
-				}
-				else if( xEntryTimeSet == pdFALSE )
-				{
-					/* The queue was empty and a block time was specified so
-					configure the timeout structure. */
-					vTaskInternalSetTimeOutState( &xTimeOut );
-					xEntryTimeSet = pdTRUE;
-				}
-				else
-				{
-					/* Entry time was already set. */
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		/* Interrupts and other tasks can send to and receive from the queue
-		now the critical section has been exited. */
-
-		vTaskSuspendAll();
-		prvLockQueue( pxQueue );
-
-		/* Update the timeout state to see if it has expired yet. */
-		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
-		{
-			/* The timeout has not expired.  If the queue is still empty place
-			the task on the list of tasks waiting to receive from the queue. */
-			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-			{
-				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
-				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
-				prvUnlockQueue( pxQueue );
-				if( xTaskResumeAll() == pdFALSE )
-				{
-					portYIELD_WITHIN_API();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				/* The queue contains data again.  Loop back to try and read the
-				data. */
-				prvUnlockQueue( pxQueue );
-				( void ) xTaskResumeAll();
-			}
-		}
-		else
-		{
-			/* Timed out.  If there is no data in the queue exit, otherwise loop
-			back and attempt to read the data. */
-			prvUnlockQueue( pxQueue );
-			( void ) xTaskResumeAll();
-
-			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-			{
-				traceQUEUE_RECEIVE_FAILED( pxQueue );
-				return errQUEUE_EMPTY;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-	} /*lint -restore */
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
-{
-BaseType_t xEntryTimeSet = pdFALSE;
-TimeOut_t xTimeOut;
-Queue_t * const pxQueue = xQueue;
-void *pvBuffer = NULL;
-(void)pvBuffer;
-
-#if( configUSE_MUTEXES == 1 )
-	BaseType_t xInheritanceOccurred = pdFALSE;
-#endif
-
-	/* Check the queue pointer is not NULL. */
-	configASSERT( ( pxQueue ) );
-
-	/* Check this really is a semaphore, in which case the item size will be
-	0. */
-	configASSERT( pxQueue->uxItemSize == 0 );
-
-	/* Cannot block if the scheduler is suspended. */
-	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-	{
-		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-	}
-	#endif
-
-
-	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
-	statements within the function itself.  This is done in the interest
-	of execution time efficiency. */
-	for( ;; )
-	{
-		taskENTER_CRITICAL();
-		{
-			/* Semaphores are queues with an item size of 0, and where the
-			number of messages in the queue is the semaphore's count value. */
-			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
-
-			/* Is there data in the queue now?  To be running the calling task
-			must be the highest priority task wanting to access the queue. */
-			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
-			{
-				traceQUEUE_RECEIVE( pxQueue );
-
-				/* Semaphores are queues with a data size of zero and where the
-				messages waiting is the semaphore's count.  Reduce the count. */
-				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
-
-				#if ( configUSE_MUTEXES == 1 )
-				{
-					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
-					{
-						/* Record the information required to implement
-						priority inheritance should it become necessary. */
-						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				#endif /* configUSE_MUTEXES */
-
-				/* Check to see if other tasks are blocked waiting to give the
-				semaphore, and if so, unblock the highest priority such task. */
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-				{
-					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-					{
-						queueYIELD_IF_USING_PREEMPTION();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				taskEXIT_CRITICAL();
-				return pdPASS;
-			}
-			else
-			{
-				if( xTicksToWait == ( TickType_t ) 0 )
-				{
-					/* For inheritance to have occurred there must have been an
-					initial timeout, and an adjusted timeout cannot become 0, as
-					if it were 0 the function would have exited. */
-					#if( configUSE_MUTEXES == 1 )
-					{
-						configASSERT( xInheritanceOccurred == pdFALSE );
-					}
-					#endif /* configUSE_MUTEXES */
-
-					/* The semaphore count was 0 and no block time is specified
-					(or the block time has expired) so exit now. */
-					taskEXIT_CRITICAL();
-					traceQUEUE_RECEIVE_FAILED( pxQueue );
-					return errQUEUE_EMPTY;
-				}
-				else if( xEntryTimeSet == pdFALSE )
-				{
-					/* The semaphore count was 0 and a block time was specified
-					so configure the timeout structure ready to block. */
-					vTaskInternalSetTimeOutState( &xTimeOut );
-					xEntryTimeSet = pdTRUE;
-				}
-				else
-				{
-					/* Entry time was already set. */
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		/* Interrupts and other tasks can give to and take from the semaphore
-		now the critical section has been exited. */
-
-		vTaskSuspendAll();
-		prvLockQueue( pxQueue );
-
-		/* Update the timeout state to see if it has expired yet. */
-		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
-		{
-			/* A block time is specified and not expired.  If the semaphore
-			count is 0 then enter the Blocked state to wait for a semaphore to
-			become available.  As semaphores are implemented with queues the
-			queue being empty is equivalent to the semaphore count being 0. */
-			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-			{
-				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
-
-				#if ( configUSE_MUTEXES == 1 )
-				{
-					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
-					{
-						taskENTER_CRITICAL();
-						{
-							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
-						}
-						taskEXIT_CRITICAL();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				#endif
-
-				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
-				prvUnlockQueue( pxQueue );
-				if( xTaskResumeAll() == pdFALSE )
-				{
-					portYIELD_WITHIN_API();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				/* There was no timeout and the semaphore count was not 0, so
-				attempt to take the semaphore again. */
-				prvUnlockQueue( pxQueue );
-				( void ) xTaskResumeAll();
-			}
-		}
-		else
-		{
-			/* Timed out. */
-			prvUnlockQueue( pxQueue );
-			( void ) xTaskResumeAll();
-
-			/* If the semaphore count is 0 exit now as the timeout has
-			expired.  Otherwise return to attempt to take the semaphore that is
-			known to be available.  As semaphores are implemented by queues the
-			queue being empty is equivalent to the semaphore count being 0. */
-			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-			{
-				#if ( configUSE_MUTEXES == 1 )
-				{
-					/* xInheritanceOccurred could only have be set if
-					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
-					test the mutex type again to check it is actually a mutex. */
-					if( xInheritanceOccurred != pdFALSE )
-					{
-						taskENTER_CRITICAL();
-						{
-							UBaseType_t uxHighestWaitingPriority;
-
-							/* This task blocking on the mutex caused another
-							task to inherit this task's priority.  Now this task
-							has timed out the priority should be disinherited
-							again, but only as low as the next highest priority
-							task that is waiting for the same mutex. */
-							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
-							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
-						}
-						taskEXIT_CRITICAL();
-					}
-				}
-				#endif /* configUSE_MUTEXES */
-
-				traceQUEUE_RECEIVE_FAILED( pxQueue );
-				return errQUEUE_EMPTY;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-	} /*lint -restore */
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
-{
-BaseType_t xEntryTimeSet = pdFALSE;
-TimeOut_t xTimeOut;
-int8_t *pcOriginalReadPosition;
-Queue_t * const pxQueue = xQueue;
-
-	/* Check the pointer is not NULL. */
-	configASSERT( ( pxQueue ) );
-
-	/* The buffer into which data is received can only be NULL if the data size
-	is zero (so no data is copied into the buffer. */
-	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
-
-	/* Cannot block if the scheduler is suspended. */
-	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-	{
-		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-	}
-	#endif
-
-
-	/*lint -save -e904  This function relaxes the coding standard somewhat to
-	allow return statements within the function itself.  This is done in the
-	interest of execution time efficiency. */
-	for( ;; )
-	{
-		taskENTER_CRITICAL();
-		{
-			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-			/* Is there data in the queue now?  To be running the calling task
-			must be the highest priority task wanting to access the queue. */
-			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
-			{
-				/* Remember the read position so it can be reset after the data
-				is read from the queue as this function is only peeking the
-				data, not removing it. */
-				pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
-
-				prvCopyDataFromQueue( pxQueue, pvBuffer );
-				traceQUEUE_PEEK( pxQueue );
-
-				/* The data is not being removed, so reset the read pointer. */
-				pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
-
-				/* The data is being left in the queue, so see if there are
-				any other tasks waiting for the data. */
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-				{
-					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-					{
-						/* The task waiting has a higher priority than this task. */
-						queueYIELD_IF_USING_PREEMPTION();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				taskEXIT_CRITICAL();
-				return pdPASS;
-			}
-			else
-			{
-				if( xTicksToWait == ( TickType_t ) 0 )
-				{
-					/* The queue was empty and no block time is specified (or
-					the block time has expired) so leave now. */
-					taskEXIT_CRITICAL();
-					traceQUEUE_PEEK_FAILED( pxQueue );
-					return errQUEUE_EMPTY;
-				}
-				else if( xEntryTimeSet == pdFALSE )
-				{
-					/* The queue was empty and a block time was specified so
-					configure the timeout structure ready to enter the blocked
-					state. */
-					vTaskInternalSetTimeOutState( &xTimeOut );
-					xEntryTimeSet = pdTRUE;
-				}
-				else
-				{
-					/* Entry time was already set. */
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		/* Interrupts and other tasks can send to and receive from the queue
-		now the critical section has been exited. */
-
-		vTaskSuspendAll();
-		prvLockQueue( pxQueue );
-
-		/* Update the timeout state to see if it has expired yet. */
-		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
-		{
-			/* Timeout has not expired yet, check to see if there is data in the
-			queue now, and if not enter the Blocked state to wait for data. */
-			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-			{
-				traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
-				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
-				prvUnlockQueue( pxQueue );
-				if( xTaskResumeAll() == pdFALSE )
-				{
-					portYIELD_WITHIN_API();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				/* There is data in the queue now, so don't enter the blocked
-				state, instead return to try and obtain the data. */
-				prvUnlockQueue( pxQueue );
-				( void ) xTaskResumeAll();
-			}
-		}
-		else
-		{
-			/* The timeout has expired.  If there is still no data in the queue
-			exit, otherwise go back and try to read the data again. */
-			prvUnlockQueue( pxQueue );
-			( void ) xTaskResumeAll();
-
-			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-			{
-				traceQUEUE_PEEK_FAILED( pxQueue );
-				return errQUEUE_EMPTY;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-	} /*lint -restore */
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
-{
-BaseType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-
-	/* RTOS ports that support interrupt nesting have the concept of a maximum
-	system call (or maximum API call) interrupt priority.  Interrupts that are
-	above the maximum system call priority are kept permanently enabled, even
-	when the RTOS kernel is in a critical section, but cannot make any calls to
-	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-	failure if a FreeRTOS API function is called from an interrupt that has been
-	assigned a priority above the configured maximum system call priority.
-	Only FreeRTOS functions that end in FromISR can be called from interrupts
-	that have been assigned a priority at or (logically) below the maximum
-	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
-	safe API to ensure interrupt entry is as fast and as simple as possible.
-	More information (albeit Cortex-M specific) is provided on the following
-	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
-	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-		/* Cannot block in an ISR, so check there is data available. */
-		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
-		{
-			const int8_t cRxLock = pxQueue->cRxLock;
-
-			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
-
-			prvCopyDataFromQueue( pxQueue, pvBuffer );
-			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
-
-			/* If the queue is locked the event list will not be modified.
-			Instead update the lock count so the task that unlocks the queue
-			will know that an ISR has removed data while the queue was
-			locked. */
-			if( cRxLock == queueUNLOCKED )
-			{
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-				{
-					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-					{
-						/* The task waiting has a higher priority than us so
-						force a context switch. */
-						if( pxHigherPriorityTaskWoken != NULL )
-						{
-							*pxHigherPriorityTaskWoken = pdTRUE;
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				/* Increment the lock count so the task that unlocks the queue
-				knows that data was removed while it was locked. */
-				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
-			}
-
-			xReturn = pdPASS;
-		}
-		else
-		{
-			xReturn = pdFAIL;
-			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
-{
-BaseType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-int8_t *pcOriginalReadPosition;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-	configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
-
-	/* RTOS ports that support interrupt nesting have the concept of a maximum
-	system call (or maximum API call) interrupt priority.  Interrupts that are
-	above the maximum system call priority are kept permanently enabled, even
-	when the RTOS kernel is in a critical section, but cannot make any calls to
-	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-	failure if a FreeRTOS API function is called from an interrupt that has been
-	assigned a priority above the configured maximum system call priority.
-	Only FreeRTOS functions that end in FromISR can be called from interrupts
-	that have been assigned a priority at or (logically) below the maximum
-	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
-	safe API to ensure interrupt entry is as fast and as simple as possible.
-	More information (albeit Cortex-M specific) is provided on the following
-	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
-	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Cannot block in an ISR, so check there is data available. */
-		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
-		{
-			traceQUEUE_PEEK_FROM_ISR( pxQueue );
-
-			/* Remember the read position so it can be reset as nothing is
-			actually being removed from the queue. */
-			pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
-			prvCopyDataFromQueue( pxQueue, pvBuffer );
-			pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
-
-			xReturn = pdPASS;
-		}
-		else
-		{
-			xReturn = pdFAIL;
-			traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
-{
-UBaseType_t uxReturn;
-
-	configASSERT( xQueue );
-
-	taskENTER_CRITICAL();
-	{
-		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
-	}
-	taskEXIT_CRITICAL();
-
-	return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
-{
-UBaseType_t uxReturn;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-
-	taskENTER_CRITICAL();
-	{
-		uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
-	}
-	taskEXIT_CRITICAL();
-
-	return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
-{
-UBaseType_t uxReturn;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	uxReturn = pxQueue->uxMessagesWaiting;
-
-	return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
-/*-----------------------------------------------------------*/
-
-void vQueueDelete( QueueHandle_t xQueue )
-{
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	traceQUEUE_DELETE( pxQueue );
-
-	#if ( configQUEUE_REGISTRY_SIZE > 0 )
-	{
-		vQueueUnregisterQueue( pxQueue );
-	}
-	#endif
-
-	#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
-	{
-		/* The queue can only have been allocated dynamically - free it
-		again. */
-		vPortFree( pxQueue );
-	}
-	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-	{
-		/* The queue could have been allocated statically or dynamically, so
-		check before attempting to free the memory. */
-		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
-		{
-			vPortFree( pxQueue );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#else
-	{
-		/* The queue must have been statically allocated, so is not going to be
-		deleted.  Avoid compiler warnings about the unused parameter. */
-		( void ) pxQueue;
-	}
-	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
-	{
-		return ( ( Queue_t * ) xQueue )->uxQueueNumber;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
-	{
-		( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
-	{
-		return ( ( Queue_t * ) xQueue )->ucQueueType;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if( configUSE_MUTEXES == 1 )
-
-	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
-	{
-	UBaseType_t uxHighestPriorityOfWaitingTasks;
-
-		/* If a task waiting for a mutex causes the mutex holder to inherit a
-		priority, but the waiting task times out, then the holder should
-		disinherit the priority - but only down to the highest priority of any
-		other tasks that are waiting for the same mutex.  For this purpose,
-		return the priority of the highest priority task that is waiting for the
-		mutex. */
-		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
-		{
-			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
-		}
-		else
-		{
-			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
-		}
-
-		return uxHighestPriorityOfWaitingTasks;
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
-{
-BaseType_t xReturn = pdFALSE;
-UBaseType_t uxMessagesWaiting;
-
-	/* This function is called from a critical section. */
-
-	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
-	{
-		#if ( configUSE_MUTEXES == 1 )
-		{
-			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
-			{
-				/* The mutex is no longer being held. */
-				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
-				pxQueue->u.xSemaphore.xMutexHolder = NULL;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* configUSE_MUTEXES */
-	}
-	else if( xPosition == queueSEND_TO_BACK )
-	{
-		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
-		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
-		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
-		{
-			pxQueue->pcWriteTo = pxQueue->pcHead;
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
-		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
-		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
-		{
-			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		if( xPosition == queueOVERWRITE )
-		{
-			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
-			{
-				/* An item is not being added but overwritten, so subtract
-				one from the recorded number of items in the queue so when
-				one is added again below the number of recorded items remains
-				correct. */
-				--uxMessagesWaiting;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
-{
-	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
-	{
-		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
-		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
-		{
-			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvUnlockQueue( Queue_t * const pxQueue )
-{
-	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
-
-	/* The lock counts contains the number of extra data items placed or
-	removed from the queue while the queue was locked.  When a queue is
-	locked items can be added or removed, but the event lists cannot be
-	updated. */
-	taskENTER_CRITICAL();
-	{
-		int8_t cTxLock = pxQueue->cTxLock;
-
-		/* See if data was added to the queue while it was locked. */
-		while( cTxLock > queueLOCKED_UNMODIFIED )
-		{
-			/* Data was posted while the queue was locked.  Are any tasks
-			blocked waiting for data to become available? */
-			#if ( configUSE_QUEUE_SETS == 1 )
-			{
-				if( pxQueue->pxQueueSetContainer != NULL )
-				{
-					if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
-					{
-						/* The queue is a member of a queue set, and posting to
-						the queue set caused a higher priority task to unblock.
-						A context switch is required. */
-						vTaskMissedYield();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					/* Tasks that are removed from the event list will get
-					added to the pending ready list as the scheduler is still
-					suspended. */
-					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-					{
-						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-						{
-							/* The task waiting has a higher priority so record that a
-							context	switch is required. */
-							vTaskMissedYield();
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						break;
-					}
-				}
-			}
-			#else /* configUSE_QUEUE_SETS */
-			{
-				/* Tasks that are removed from the event list will get added to
-				the pending ready list as the scheduler is still suspended. */
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-				{
-					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-					{
-						/* The task waiting has a higher priority so record that
-						a context switch is required. */
-						vTaskMissedYield();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					break;
-				}
-			}
-			#endif /* configUSE_QUEUE_SETS */
-
-			--cTxLock;
-		}
-
-		pxQueue->cTxLock = queueUNLOCKED;
-	}
-	taskEXIT_CRITICAL();
-
-	/* Do the same for the Rx lock. */
-	taskENTER_CRITICAL();
-	{
-		int8_t cRxLock = pxQueue->cRxLock;
-
-		while( cRxLock > queueLOCKED_UNMODIFIED )
-		{
-			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-			{
-				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-				{
-					vTaskMissedYield();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				--cRxLock;
-			}
-			else
-			{
-				break;
-			}
-		}
-
-		pxQueue->cRxLock = queueUNLOCKED;
-	}
-	taskEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
-{
-BaseType_t xReturn;
-
-	taskENTER_CRITICAL();
-	{
-		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
-		{
-			xReturn = pdTRUE;
-		}
-		else
-		{
-			xReturn = pdFALSE;
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
-{
-BaseType_t xReturn;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
-	{
-		xReturn = pdTRUE;
-	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
-
-	return xReturn;
-} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
-{
-BaseType_t xReturn;
-
-	taskENTER_CRITICAL();
-	{
-		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
-		{
-			xReturn = pdTRUE;
-		}
-		else
-		{
-			xReturn = pdFALSE;
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
-{
-BaseType_t xReturn;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
-	{
-		xReturn = pdTRUE;
-	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
-
-	return xReturn;
-} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_CO_ROUTINES == 1 )
-
-	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
-	{
-	BaseType_t xReturn;
-	Queue_t * const pxQueue = xQueue;
-
-		/* If the queue is already full we may have to block.  A critical section
-		is required to prevent an interrupt removing something from the queue
-		between the check to see if the queue is full and blocking on the queue. */
-		portDISABLE_INTERRUPTS();
-		{
-			if( prvIsQueueFull( pxQueue ) != pdFALSE )
-			{
-				/* The queue is full - do we want to block or just leave without
-				posting? */
-				if( xTicksToWait > ( TickType_t ) 0 )
-				{
-					/* As this is called from a coroutine we cannot block directly, but
-					return indicating that we need to block. */
-					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
-					portENABLE_INTERRUPTS();
-					return errQUEUE_BLOCKED;
-				}
-				else
-				{
-					portENABLE_INTERRUPTS();
-					return errQUEUE_FULL;
-				}
-			}
-		}
-		portENABLE_INTERRUPTS();
-
-		portDISABLE_INTERRUPTS();
-		{
-			if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
-			{
-				/* There is room in the queue, copy the data into the queue. */
-				prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
-				xReturn = pdPASS;
-
-				/* Were any co-routines waiting for data to become available? */
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-				{
-					/* In this instance the co-routine could be placed directly
-					into the ready list as we are within a critical section.
-					Instead the same pending ready list mechanism is used as if
-					the event were caused from within an interrupt. */
-					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-					{
-						/* The co-routine waiting has a higher priority so record
-						that a yield might be appropriate. */
-						xReturn = errQUEUE_YIELD;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				xReturn = errQUEUE_FULL;
-			}
-		}
-		portENABLE_INTERRUPTS();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_CO_ROUTINES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_CO_ROUTINES == 1 )
-
-	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
-	{
-	BaseType_t xReturn;
-	Queue_t * const pxQueue = xQueue;
-
-		/* If the queue is already empty we may have to block.  A critical section
-		is required to prevent an interrupt adding something to the queue
-		between the check to see if the queue is empty and blocking on the queue. */
-		portDISABLE_INTERRUPTS();
-		{
-			if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
-			{
-				/* There are no messages in the queue, do we want to block or just
-				leave with nothing? */
-				if( xTicksToWait > ( TickType_t ) 0 )
-				{
-					/* As this is a co-routine we cannot block directly, but return
-					indicating that we need to block. */
-					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
-					portENABLE_INTERRUPTS();
-					return errQUEUE_BLOCKED;
-				}
-				else
-				{
-					portENABLE_INTERRUPTS();
-					return errQUEUE_FULL;
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		portENABLE_INTERRUPTS();
-
-		portDISABLE_INTERRUPTS();
-		{
-			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
-			{
-				/* Data is available from the queue. */
-				pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
-				if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
-				{
-					pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-				--( pxQueue->uxMessagesWaiting );
-				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
-
-				xReturn = pdPASS;
-
-				/* Were any co-routines waiting for space to become available? */
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-				{
-					/* In this instance the co-routine could be placed directly
-					into the ready list as we are within a critical section.
-					Instead the same pending ready list mechanism is used as if
-					the event were caused from within an interrupt. */
-					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-					{
-						xReturn = errQUEUE_YIELD;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				xReturn = pdFAIL;
-			}
-		}
-		portENABLE_INTERRUPTS();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_CO_ROUTINES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_CO_ROUTINES == 1 )
-
-	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
-	{
-	Queue_t * const pxQueue = xQueue;
-
-		/* Cannot block within an ISR so if there is no space on the queue then
-		exit without doing anything. */
-		if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
-		{
-			prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
-
-			/* We only want to wake one co-routine per ISR, so check that a
-			co-routine has not already been woken. */
-			if( xCoRoutinePreviouslyWoken == pdFALSE )
-			{
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-				{
-					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-					{
-						return pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return xCoRoutinePreviouslyWoken;
-	}
-
-#endif /* configUSE_CO_ROUTINES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_CO_ROUTINES == 1 )
-
-	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
-	{
-	BaseType_t xReturn;
-	Queue_t * const pxQueue = xQueue;
-
-		/* We cannot block from an ISR, so check there is data available. If
-		not then just leave without doing anything. */
-		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
-		{
-			/* Copy the data from the queue. */
-			pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
-			if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
-			{
-				pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-			--( pxQueue->uxMessagesWaiting );
-			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
-
-			if( ( *pxCoRoutineWoken ) == pdFALSE )
-			{
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-				{
-					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-					{
-						*pxCoRoutineWoken = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			xReturn = pdPASS;
-		}
-		else
-		{
-			xReturn = pdFAIL;
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_CO_ROUTINES */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	{
-	UBaseType_t ux;
-
-		/* See if there is an empty space in the registry.  A NULL name denotes
-		a free slot. */
-		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
-		{
-			if( xQueueRegistry[ ux ].pcQueueName == NULL )
-			{
-				/* Store the information on this queue. */
-				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
-				xQueueRegistry[ ux ].xHandle = xQueue;
-
-				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
-				break;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-	}
-
-#endif /* configQUEUE_REGISTRY_SIZE */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-	const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	{
-	UBaseType_t ux;
-	const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-		/* Note there is nothing here to protect against another task adding or
-		removing entries from the registry while it is being searched. */
-		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
-		{
-			if( xQueueRegistry[ ux ].xHandle == xQueue )
-			{
-				pcReturn = xQueueRegistry[ ux ].pcQueueName;
-				break;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-
-		return pcReturn;
-	} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
-
-#endif /* configQUEUE_REGISTRY_SIZE */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-	void vQueueUnregisterQueue( QueueHandle_t xQueue )
-	{
-	UBaseType_t ux;
-
-		/* See if the handle of the queue being unregistered in actually in the
-		registry. */
-		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
-		{
-			if( xQueueRegistry[ ux ].xHandle == xQueue )
-			{
-				/* Set the name to NULL to show that this slot if free again. */
-				xQueueRegistry[ ux ].pcQueueName = NULL;
-
-				/* Set the handle to NULL to ensure the same queue handle cannot
-				appear in the registry twice if it is added, removed, then
-				added again. */
-				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
-				break;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-
-	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
-
-#endif /* configQUEUE_REGISTRY_SIZE */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
-	{
-	Queue_t * const pxQueue = xQueue;
-
-		/* This function should not be called by application code hence the
-		'Restricted' in its name.  It is not part of the public API.  It is
-		designed for use by kernel code, and has special calling requirements.
-		It can result in vListInsert() being called on a list that can only
-		possibly ever have one item in it, so the list will be fast, but even
-		so it should be called with the scheduler locked and not from a critical
-		section. */
-
-		/* Only do anything if there are no messages in the queue.  This function
-		will not actually cause the task to block, just place it on a blocked
-		list.  It will not block until the scheduler is unlocked - at which
-		time a yield will be performed.  If an item is added to the queue while
-		the queue is locked, and the calling task blocks on the queue, then the
-		calling task will be immediately unblocked when the queue is unlocked. */
-		prvLockQueue( pxQueue );
-		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
-		{
-			/* There is nothing in the queue, block for the specified period. */
-			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-		prvUnlockQueue( pxQueue );
-	}
-
-#endif /* configUSE_TIMERS */
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-	QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
-	{
-	QueueSetHandle_t pxQueue;
-
-		pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
-
-		return pxQueue;
-	}
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-	BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
-	{
-	BaseType_t xReturn;
-
-		taskENTER_CRITICAL();
-		{
-			if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
-			{
-				/* Cannot add a queue/semaphore to more than one queue set. */
-				xReturn = pdFAIL;
-			}
-			else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
-			{
-				/* Cannot add a queue/semaphore to a queue set if there are already
-				items in the queue/semaphore. */
-				xReturn = pdFAIL;
-			}
-			else
-			{
-				( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
-				xReturn = pdPASS;
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-	BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
-	{
-	BaseType_t xReturn;
-	Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
-
-		if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
-		{
-			/* The queue was not a member of the set. */
-			xReturn = pdFAIL;
-		}
-		else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
-		{
-			/* It is dangerous to remove a queue from a set when the queue is
-			not empty because the queue set will still hold pending events for
-			the queue. */
-			xReturn = pdFAIL;
-		}
-		else
-		{
-			taskENTER_CRITICAL();
-			{
-				/* The queue is no longer contained in the set. */
-				pxQueueOrSemaphore->pxQueueSetContainer = NULL;
-			}
-			taskEXIT_CRITICAL();
-			xReturn = pdPASS;
-		}
-
-		return xReturn;
-	} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-	QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
-	{
-	QueueSetMemberHandle_t xReturn = NULL;
-
-		( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
-		return xReturn;
-	}
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-	QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
-	{
-	QueueSetMemberHandle_t xReturn = NULL;
-
-		( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
-		return xReturn;
-	}
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )
-	{
-	Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
-	BaseType_t xReturn = pdFALSE;
-
-		/* This function must be called form a critical section. */
-
-		configASSERT( pxQueueSetContainer );
-		configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
-
-		if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
-		{
-			const int8_t cTxLock = pxQueueSetContainer->cTxLock;
-
-			traceQUEUE_SEND( pxQueueSetContainer );
-
-			/* The data copied is the handle of the queue that contains data. */
-			xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );
-
-			if( cTxLock == queueUNLOCKED )
-			{
-				if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
-				{
-					if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
-					{
-						/* The task waiting has a higher priority. */
-						xReturn = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_QUEUE_SETS */
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/stream_buffer.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/stream_buffer.c
deleted file mode 100644
index 8cda238..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/stream_buffer.c
+++ /dev/null
@@ -1,1263 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* FreeRTOS includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "stream_buffer.h"
-
-#if( configUSE_TASK_NOTIFICATIONS != 1 )
-	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
-#endif
-
-/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
-because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
-for the header files above, but not in this file, in order to generate the
-correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
-
-/* If the user has not provided application specific Rx notification macros,
-or #defined the notification macros away, them provide default implementations
-that uses task notifications. */
-/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
-#ifndef sbRECEIVE_COMPLETED
-	#define sbRECEIVE_COMPLETED( pxStreamBuffer )										\
-		vTaskSuspendAll();																\
-		{																				\
-			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
-			{																			\
-				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,			\
-									  ( uint32_t ) 0,									\
-									  eNoAction );										\
-				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
-			}																			\
-		}																				\
-		( void ) xTaskResumeAll();
-#endif /* sbRECEIVE_COMPLETED */
-
-#ifndef sbRECEIVE_COMPLETED_FROM_ISR
-	#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,								\
-										  pxHigherPriorityTaskWoken )					\
-	{																					\
-	UBaseType_t uxSavedInterruptStatus;													\
-																						\
-		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
-		{																				\
-			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
-			{																			\
-				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,	\
-											 ( uint32_t ) 0,							\
-											 eNoAction,									\
-											 pxHigherPriorityTaskWoken );				\
-				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
-			}																			\
-		}																				\
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
-	}
-#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
-
-/* If the user has not provided an application specific Tx notification macro,
-or #defined the notification macro away, them provide a default implementation
-that uses task notifications. */
-#ifndef sbSEND_COMPLETED
-	#define sbSEND_COMPLETED( pxStreamBuffer )											\
-		vTaskSuspendAll();																\
-		{																				\
-			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
-			{																			\
-				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,		\
-									  ( uint32_t ) 0,									\
-									  eNoAction );										\
-				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
-			}																			\
-		}																				\
-		( void ) xTaskResumeAll();
-#endif /* sbSEND_COMPLETED */
-
-#ifndef sbSEND_COMPLETE_FROM_ISR
-	#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )		\
-	{																					\
-	UBaseType_t uxSavedInterruptStatus;													\
-																						\
-		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
-		{																				\
-			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
-			{																			\
-				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,	\
-											 ( uint32_t ) 0,							\
-											 eNoAction,									\
-											 pxHigherPriorityTaskWoken );				\
-				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
-			}																			\
-		}																				\
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
-	}
-#endif /* sbSEND_COMPLETE_FROM_ISR */
-/*lint -restore (9026) */
-
-/* The number of bytes used to hold the length of a message in the buffer. */
-#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
-
-/* Bits stored in the ucFlags field of the stream buffer. */
-#define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
-#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
-
-/*-----------------------------------------------------------*/
-
-/* Structure that hold state information on the buffer. */
-typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
-{
-	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
-	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
-	size_t xLength;						/* The length of the buffer pointed to by pucBuffer. */
-	size_t xTriggerLevelBytes;			/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
-	volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
-	volatile TaskHandle_t xTaskWaitingToSend;	/* Holds the handle of a task waiting to send data to a message buffer that is full. */
-	uint8_t *pucBuffer;					/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
-	uint8_t ucFlags;
-
-	#if ( configUSE_TRACE_FACILITY == 1 )
-		UBaseType_t uxStreamBufferNumber;		/* Used for tracing purposes. */
-	#endif
-} StreamBuffer_t;
-
-/*
- * The number of bytes available to be read from the buffer.
- */
-static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/*
- * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
- * Returns the number of bytes written, which will either equal xCount in the
- * success case, or 0 if there was not enough space in the buffer (in which case
- * no data is written into the buffer).
- */
-static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
-
-/*
- * If the stream buffer is being used as a message buffer, then reads an entire
- * message out of the buffer.  If the stream buffer is being used as a stream
- * buffer then read as many bytes as possible from the buffer.
- * prvReadBytesFromBuffer() is called to actually extract the bytes from the
- * buffer's data storage area.
- */
-static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
-										void *pvRxData,
-										size_t xBufferLengthBytes,
-										size_t xBytesAvailable,
-										size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
-
-/*
- * If the stream buffer is being used as a message buffer, then writes an entire
- * message to the buffer.  If the stream buffer is being used as a stream
- * buffer then write as many bytes as possible to the buffer.
- * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
- * data storage area.
- */
-static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
-										const void * pvTxData,
-										size_t xDataLengthBytes,
-										size_t xSpace,
-										size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
-
-/*
- * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
- * to pucData.
- */
-static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
-									  uint8_t *pucData,
-									  size_t xMaxCount,
-									  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
-
-/*
- * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
- * initialise the members of the newly created stream buffer structure.
- */
-static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
-										  uint8_t * const pucBuffer,
-										  size_t xBufferSizeBytes,
-										  size_t xTriggerLevelBytes,
-										  uint8_t ucFlags ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
-	{
-	uint8_t *pucAllocatedMemory;
-	uint8_t ucFlags;
-
-		/* In case the stream buffer is going to be used as a message buffer
-		(that is, it will hold discrete messages with a little meta data that
-		says how big the next message is) check the buffer will be large enough
-		to hold at least one message. */
-		if( xIsMessageBuffer == pdTRUE )
-		{
-			/* Is a message buffer but not statically allocated. */
-			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
-			configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
-		}
-		else
-		{
-			/* Not a message buffer and not statically allocated. */
-			ucFlags = 0;
-			configASSERT( xBufferSizeBytes > 0 );
-		}
-		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
-
-		/* A trigger level of 0 would cause a waiting task to unblock even when
-		the buffer was empty. */
-		if( xTriggerLevelBytes == ( size_t ) 0 )
-		{
-			xTriggerLevelBytes = ( size_t ) 1;
-		}
-
-		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
-		Both are allocated in a single call to pvPortMalloc().  The
-		StreamBuffer_t structure is placed at the start of the allocated memory
-		and the buffer follows immediately after.  The requested size is
-		incremented so the free space is returned as the user would expect -
-		this is a quirk of the implementation that means otherwise the free
-		space would be reported as one byte smaller than would be logically
-		expected. */
-		xBufferSizeBytes++;
-		pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
-
-		if( pucAllocatedMemory != NULL )
-		{
-			prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
-										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
-										   xBufferSizeBytes,
-										   xTriggerLevelBytes,
-										   ucFlags );
-
-			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
-		}
-		else
-		{
-			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
-		}
-
-		return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
-	}
-
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-	StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
-														   size_t xTriggerLevelBytes,
-														   BaseType_t xIsMessageBuffer,
-														   uint8_t * const pucStreamBufferStorageArea,
-														   StaticStreamBuffer_t * const pxStaticStreamBuffer )
-	{
-	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
-	StreamBufferHandle_t xReturn;
-	uint8_t ucFlags;
-
-		configASSERT( pucStreamBufferStorageArea );
-		configASSERT( pxStaticStreamBuffer );
-		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
-
-		/* A trigger level of 0 would cause a waiting task to unblock even when
-		the buffer was empty. */
-		if( xTriggerLevelBytes == ( size_t ) 0 )
-		{
-			xTriggerLevelBytes = ( size_t ) 1;
-		}
-
-		if( xIsMessageBuffer != pdFALSE )
-		{
-			/* Statically allocated message buffer. */
-			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
-		}
-		else
-		{
-			/* Statically allocated stream buffer. */
-			ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
-		}
-
-		/* In case the stream buffer is going to be used as a message buffer
-		(that is, it will hold discrete messages with a little meta data that
-		says how big the next message is) check the buffer will be large enough
-		to hold at least one message. */
-		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
-
-		#if( configASSERT_DEFINED == 1 )
-		{
-			/* Sanity check that the size of the structure used to declare a
-			variable of type StaticStreamBuffer_t equals the size of the real
-			message buffer structure. */
-			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
-			configASSERT( xSize == sizeof( StreamBuffer_t ) );
-		} /*lint !e529 xSize is referenced is configASSERT() is defined. */
-		#endif /* configASSERT_DEFINED */
-
-		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
-		{
-			prvInitialiseNewStreamBuffer( pxStreamBuffer,
-										  pucStreamBufferStorageArea,
-										  xBufferSizeBytes,
-										  xTriggerLevelBytes,
-										  ucFlags );
-
-			/* Remember this was statically allocated in case it is ever deleted
-			again. */
-			pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
-
-			traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
-
-			xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
-		}
-		else
-		{
-			xReturn = NULL;
-			traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
-		}
-
-		return xReturn;
-	}
-
-#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-/*-----------------------------------------------------------*/
-
-void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
-{
-StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
-
-	configASSERT( pxStreamBuffer );
-
-	traceSTREAM_BUFFER_DELETE( xStreamBuffer );
-
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
-	{
-		#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-		{
-			/* Both the structure and the buffer were allocated using a single call
-			to pvPortMalloc(), hence only one call to vPortFree() is required. */
-			vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
-		}
-		#else
-		{
-			/* Should not be possible to get here, ucFlags must be corrupt.
-			Force an assert. */
-			configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
-		}
-		#endif
-	}
-	else
-	{
-		/* The structure and buffer were not allocated dynamically and cannot be
-		freed - just scrub the structure so future use will assert. */
-		( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
-	}
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-BaseType_t xReturn = pdFAIL;
-
-#if( configUSE_TRACE_FACILITY == 1 )
-	UBaseType_t uxStreamBufferNumber;
-#endif
-
-	configASSERT( pxStreamBuffer );
-
-	#if( configUSE_TRACE_FACILITY == 1 )
-	{
-		/* Store the stream buffer number so it can be restored after the
-		reset. */
-		uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
-	}
-	#endif
-
-	/* Can only reset a message buffer if there are no tasks blocked on it. */
-	taskENTER_CRITICAL();
-	{
-		if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
-		{
-			if( pxStreamBuffer->xTaskWaitingToSend == NULL )
-			{
-				prvInitialiseNewStreamBuffer( pxStreamBuffer,
-											  pxStreamBuffer->pucBuffer,
-											  pxStreamBuffer->xLength,
-											  pxStreamBuffer->xTriggerLevelBytes,
-											  pxStreamBuffer->ucFlags );
-				xReturn = pdPASS;
-
-				#if( configUSE_TRACE_FACILITY == 1 )
-				{
-					pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
-				}
-				#endif
-
-				traceSTREAM_BUFFER_RESET( xStreamBuffer );
-			}
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-BaseType_t xReturn;
-
-	configASSERT( pxStreamBuffer );
-
-	/* It is not valid for the trigger level to be 0. */
-	if( xTriggerLevel == ( size_t ) 0 )
-	{
-		xTriggerLevel = ( size_t ) 1;
-	}
-
-	/* The trigger level is the number of bytes that must be in the stream
-	buffer before a task that is waiting for data is unblocked. */
-	if( xTriggerLevel <= pxStreamBuffer->xLength )
-	{
-		pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
-		xReturn = pdPASS;
-	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
-{
-const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xSpace;
-
-	configASSERT( pxStreamBuffer );
-
-	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
-	xSpace -= pxStreamBuffer->xHead;
-	xSpace -= ( size_t ) 1;
-
-	if( xSpace >= pxStreamBuffer->xLength )
-	{
-		xSpace -= pxStreamBuffer->xLength;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	return xSpace;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
-{
-const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xReturn;
-
-	configASSERT( pxStreamBuffer );
-
-	xReturn = prvBytesInBuffer( pxStreamBuffer );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-						  const void *pvTxData,
-						  size_t xDataLengthBytes,
-						  TickType_t xTicksToWait )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xReturn, xSpace = 0;
-size_t xRequiredSpace = xDataLengthBytes;
-TimeOut_t xTimeOut;
-
-	configASSERT( pvTxData );
-	configASSERT( pxStreamBuffer );
-
-	/* This send function is used to write to both message buffers and stream
-	buffers.  If this is a message buffer then the space needed must be
-	increased by the amount of bytes needed to store the length of the
-	message. */
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-	{
-		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
-
-		/* Overflow? */
-		configASSERT( xRequiredSpace > xDataLengthBytes );
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	if( xTicksToWait != ( TickType_t ) 0 )
-	{
-		vTaskSetTimeOutState( &xTimeOut );
-
-		do
-		{
-			/* Wait until the required number of bytes are free in the message
-			buffer. */
-			taskENTER_CRITICAL();
-			{
-				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
-
-				if( xSpace < xRequiredSpace )
-				{
-					/* Clear notification state as going to wait for space. */
-					( void ) xTaskNotifyStateClear( NULL );
-
-					/* Should only be one writer. */
-					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
-					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
-				}
-				else
-				{
-					taskEXIT_CRITICAL();
-					break;
-				}
-			}
-			taskEXIT_CRITICAL();
-
-			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
-			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
-			pxStreamBuffer->xTaskWaitingToSend = NULL;
-
-		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	if( xSpace == ( size_t ) 0 )
-	{
-		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
-
-	if( xReturn > ( size_t ) 0 )
-	{
-		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
-
-		/* Was a task waiting for the data? */
-		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
-		{
-			sbSEND_COMPLETED( pxStreamBuffer );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
-								 const void *pvTxData,
-								 size_t xDataLengthBytes,
-								 BaseType_t * const pxHigherPriorityTaskWoken )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xReturn, xSpace;
-size_t xRequiredSpace = xDataLengthBytes;
-
-	configASSERT( pvTxData );
-	configASSERT( pxStreamBuffer );
-
-	/* This send function is used to write to both message buffers and stream
-	buffers.  If this is a message buffer then the space needed must be
-	increased by the amount of bytes needed to store the length of the
-	message. */
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-	{
-		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
-	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
-
-	if( xReturn > ( size_t ) 0 )
-	{
-		/* Was a task waiting for the data? */
-		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
-		{
-			sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
-									   const void * pvTxData,
-									   size_t xDataLengthBytes,
-									   size_t xSpace,
-									   size_t xRequiredSpace )
-{
-	BaseType_t xShouldWrite;
-	size_t xReturn;
-
-	if( xSpace == ( size_t ) 0 )
-	{
-		/* Doesn't matter if this is a stream buffer or a message buffer, there
-		is no space to write. */
-		xShouldWrite = pdFALSE;
-	}
-	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
-	{
-		/* This is a stream buffer, as opposed to a message buffer, so writing a
-		stream of bytes rather than discrete messages.  Write as many bytes as
-		possible. */
-		xShouldWrite = pdTRUE;
-		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
-	}
-	else if( xSpace >= xRequiredSpace )
-	{
-		/* This is a message buffer, as opposed to a stream buffer, and there
-		is enough space to write both the message length and the message itself
-		into the buffer.  Start by writing the length of the data, the data
-		itself will be written later in this function. */
-		xShouldWrite = pdTRUE;
-		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
-	}
-	else
-	{
-		/* There is space available, but not enough space. */
-		xShouldWrite = pdFALSE;
-	}
-
-	if( xShouldWrite != pdFALSE )
-	{
-		/* Writes the data itself. */
-		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
-	}
-	else
-	{
-		xReturn = 0;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-							 void *pvRxData,
-							 size_t xBufferLengthBytes,
-							 TickType_t xTicksToWait )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
-
-	configASSERT( pvRxData );
-	configASSERT( pxStreamBuffer );
-
-	/* This receive function is used by both message buffers, which store
-	discrete messages, and stream buffers, which store a continuous stream of
-	bytes.  Discrete messages include an additional
-	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
-	message. */
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-	{
-		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
-	}
-	else
-	{
-		xBytesToStoreMessageLength = 0;
-	}
-
-	if( xTicksToWait != ( TickType_t ) 0 )
-	{
-		/* Checking if there is data and clearing the notification state must be
-		performed atomically. */
-		taskENTER_CRITICAL();
-		{
-			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-
-			/* If this function was invoked by a message buffer read then
-			xBytesToStoreMessageLength holds the number of bytes used to hold
-			the length of the next discrete message.  If this function was
-			invoked by a stream buffer read then xBytesToStoreMessageLength will
-			be 0. */
-			if( xBytesAvailable <= xBytesToStoreMessageLength )
-			{
-				/* Clear notification state as going to wait for data. */
-				( void ) xTaskNotifyStateClear( NULL );
-
-				/* Should only be one reader. */
-				configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
-				pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		if( xBytesAvailable <= xBytesToStoreMessageLength )
-		{
-			/* Wait for data to be available. */
-			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
-			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
-			pxStreamBuffer->xTaskWaitingToReceive = NULL;
-
-			/* Recheck the data available after blocking. */
-			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-	}
-
-	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
-	holds the number of bytes used to store the message length) or a stream of
-	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
-	available must be greater than xBytesToStoreMessageLength to be able to
-	read bytes from the buffer. */
-	if( xBytesAvailable > xBytesToStoreMessageLength )
-	{
-		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
-
-		/* Was a task waiting for space in the buffer? */
-		if( xReceivedLength != ( size_t ) 0 )
-		{
-			traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
-			sbRECEIVE_COMPLETED( pxStreamBuffer );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	return xReceivedLength;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xReturn, xBytesAvailable, xOriginalTail;
-configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
-
-	configASSERT( pxStreamBuffer );
-
-	/* Ensure the stream buffer is being used as a message buffer. */
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-	{
-		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-		if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
-		{
-			/* The number of bytes available is greater than the number of bytes
-			required to hold the length of the next message, so another message
-			is available.  Return its length without removing the length bytes
-			from the buffer.  A copy of the tail is stored so the buffer can be
-			returned to its prior state as the message is not actually being
-			removed from the buffer. */
-			xOriginalTail = pxStreamBuffer->xTail;
-			( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
-			xReturn = ( size_t ) xTempReturn;
-			pxStreamBuffer->xTail = xOriginalTail;
-		}
-		else
-		{
-			/* The minimum amount of bytes in a message buffer is
-			( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
-			less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
-			value is 0. */
-			configASSERT( xBytesAvailable == 0 );
-			xReturn = 0;
-		}
-	}
-	else
-	{
-		xReturn = 0;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
-									void *pvRxData,
-									size_t xBufferLengthBytes,
-									BaseType_t * const pxHigherPriorityTaskWoken )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
-
-	configASSERT( pvRxData );
-	configASSERT( pxStreamBuffer );
-
-	/* This receive function is used by both message buffers, which store
-	discrete messages, and stream buffers, which store a continuous stream of
-	bytes.  Discrete messages include an additional
-	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
-	message. */
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-	{
-		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
-	}
-	else
-	{
-		xBytesToStoreMessageLength = 0;
-	}
-
-	xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-
-	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
-	holds the number of bytes used to store the message length) or a stream of
-	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
-	available must be greater than xBytesToStoreMessageLength to be able to
-	read bytes from the buffer. */
-	if( xBytesAvailable > xBytesToStoreMessageLength )
-	{
-		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
-
-		/* Was a task waiting for space in the buffer? */
-		if( xReceivedLength != ( size_t ) 0 )
-		{
-			sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
-
-	return xReceivedLength;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
-										void *pvRxData,
-										size_t xBufferLengthBytes,
-										size_t xBytesAvailable,
-										size_t xBytesToStoreMessageLength )
-{
-size_t xOriginalTail, xReceivedLength, xNextMessageLength;
-configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
-
-	if( xBytesToStoreMessageLength != ( size_t ) 0 )
-	{
-		/* A discrete message is being received.  First receive the length
-		of the message.  A copy of the tail is stored so the buffer can be
-		returned to its prior state if the length of the message is too
-		large for the provided buffer. */
-		xOriginalTail = pxStreamBuffer->xTail;
-		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
-		xNextMessageLength = ( size_t ) xTempNextMessageLength;
-
-		/* Reduce the number of bytes available by the number of bytes just
-		read out. */
-		xBytesAvailable -= xBytesToStoreMessageLength;
-
-		/* Check there is enough space in the buffer provided by the
-		user. */
-		if( xNextMessageLength > xBufferLengthBytes )
-		{
-			/* The user has provided insufficient space to read the message
-			so return the buffer to its previous state (so the length of
-			the message is in the buffer again). */
-			pxStreamBuffer->xTail = xOriginalTail;
-			xNextMessageLength = 0;
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		/* A stream of bytes is being received (as opposed to a discrete
-		message), so read as many bytes as possible. */
-		xNextMessageLength = xBufferLengthBytes;
-	}
-
-	/* Read the actual data. */
-	xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
-
-	return xReceivedLength;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
-{
-const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-BaseType_t xReturn;
-size_t xTail;
-
-	configASSERT( pxStreamBuffer );
-
-	/* True if no bytes are available. */
-	xTail = pxStreamBuffer->xTail;
-	if( pxStreamBuffer->xHead == xTail )
-	{
-		xReturn = pdTRUE;
-	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
-{
-BaseType_t xReturn;
-size_t xBytesToStoreMessageLength;
-const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-
-	configASSERT( pxStreamBuffer );
-
-	/* This generic version of the receive function is used by both message
-	buffers, which store discrete messages, and stream buffers, which store a
-	continuous stream of bytes.  Discrete messages include an additional
-	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-	{
-		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
-	}
-	else
-	{
-		xBytesToStoreMessageLength = 0;
-	}
-
-	/* True if the available space equals zero. */
-	if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
-	{
-		xReturn = pdTRUE;
-	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-BaseType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-
-	configASSERT( pxStreamBuffer );
-
-	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
-		{
-			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
-										 ( uint32_t ) 0,
-										 eNoAction,
-										 pxHigherPriorityTaskWoken );
-			( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
-			xReturn = pdTRUE;
-		}
-		else
-		{
-			xReturn = pdFALSE;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-BaseType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-
-	configASSERT( pxStreamBuffer );
-
-	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
-		{
-			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
-										 ( uint32_t ) 0,
-										 eNoAction,
-										 pxHigherPriorityTaskWoken );
-			( pxStreamBuffer )->xTaskWaitingToSend = NULL;
-			xReturn = pdTRUE;
-		}
-		else
-		{
-			xReturn = pdFALSE;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
-{
-size_t xNextHead, xFirstLength;
-
-	configASSERT( xCount > ( size_t ) 0 );
-
-	xNextHead = pxStreamBuffer->xHead;
-
-	/* Calculate the number of bytes that can be added in the first write -
-	which may be less than the total number of bytes that need to be added if
-	the buffer will wrap back to the beginning. */
-	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
-
-	/* Write as many bytes as can be written in the first write. */
-	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
-	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
-
-	/* If the number of bytes written was less than the number that could be
-	written in the first write... */
-	if( xCount > xFirstLength )
-	{
-		/* ...then write the remaining bytes to the start of the buffer. */
-		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
-		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	xNextHead += xCount;
-	if( xNextHead >= pxStreamBuffer->xLength )
-	{
-		xNextHead -= pxStreamBuffer->xLength;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	pxStreamBuffer->xHead = xNextHead;
-
-	return xCount;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
-{
-size_t xCount, xFirstLength, xNextTail;
-
-	/* Use the minimum of the wanted bytes and the available bytes. */
-	xCount = configMIN( xBytesAvailable, xMaxCount );
-
-	if( xCount > ( size_t ) 0 )
-	{
-		xNextTail = pxStreamBuffer->xTail;
-
-		/* Calculate the number of bytes that can be read - which may be
-		less than the number wanted if the data wraps around to the start of
-		the buffer. */
-		xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
-
-		/* Obtain the number of bytes it is possible to obtain in the first
-		read.  Asserts check bounds of read and write. */
-		configASSERT( xFirstLength <= xMaxCount );
-		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
-		( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
-
-		/* If the total number of wanted bytes is greater than the number
-		that could be read in the first read... */
-		if( xCount > xFirstLength )
-		{
-			/*...then read the remaining bytes from the start of the buffer. */
-			configASSERT( xCount <= xMaxCount );
-			( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		/* Move the tail pointer to effectively remove the data read from
-		the buffer. */
-		xNextTail += xCount;
-
-		if( xNextTail >= pxStreamBuffer->xLength )
-		{
-			xNextTail -= pxStreamBuffer->xLength;
-		}
-
-		pxStreamBuffer->xTail = xNextTail;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	return xCount;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
-{
-/* Returns the distance between xTail and xHead. */
-size_t xCount;
-
-	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
-	xCount -= pxStreamBuffer->xTail;
-	if ( xCount >= pxStreamBuffer->xLength )
-	{
-		xCount -= pxStreamBuffer->xLength;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	return xCount;
-}
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
-										  uint8_t * const pucBuffer,
-										  size_t xBufferSizeBytes,
-										  size_t xTriggerLevelBytes,
-										  uint8_t ucFlags )
-{
-	/* Assert here is deliberately writing to the entire buffer to ensure it can
-	be written to without generating exceptions, and is setting the buffer to a
-	known value to assist in development/debugging. */
-	#if( configASSERT_DEFINED == 1 )
-	{
-		/* The value written just has to be identifiable when looking at the
-		memory.  Don't use 0xA5 as that is the stack fill value and could
-		result in confusion as to what is actually being observed. */
-		const BaseType_t xWriteValue = 0x55;
-		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
-	} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
-	#endif
-
-	( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
-	pxStreamBuffer->pucBuffer = pucBuffer;
-	pxStreamBuffer->xLength = xBufferSizeBytes;
-	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
-	pxStreamBuffer->ucFlags = ucFlags;
-}
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
-	{
-		return xStreamBuffer->uxStreamBufferNumber;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
-	{
-		xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
-	{
-		return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/tasks.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/tasks.c
deleted file mode 100644
index c69cb4d..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/tasks.c
+++ /dev/null
@@ -1,5248 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- *
- * Copyright 2019 MicroEJ Corp. This file has been modified by MicroEJ Corp.
- * 1. Patch for SystemView support
- */
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* FreeRTOS includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "timers.h"
-#include "stack_macros.h"
-
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
-because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
-for the header files above, but not in this file, in order to generate the
-correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
-
-/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
-functions but without including stdio.h here. */
-#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
-	/* At the bottom of this file are two optional functions that can be used
-	to generate human readable text from the raw data generated by the
-	uxTaskGetSystemState() function.  Note the formatting functions are provided
-	for convenience only, and are NOT considered part of the kernel. */
-	#include 
-#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
-
-#if( configUSE_PREEMPTION == 0 )
-	/* If the cooperative scheduler is being used then a yield should not be
-	performed just because a higher priority task has been woken. */
-	#define taskYIELD_IF_USING_PREEMPTION()
-#else
-	#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
-#endif
-
-/* Values that can be assigned to the ucNotifyState member of the TCB. */
-#define taskNOT_WAITING_NOTIFICATION	( ( uint8_t ) 0 )
-#define taskWAITING_NOTIFICATION		( ( uint8_t ) 1 )
-#define taskNOTIFICATION_RECEIVED		( ( uint8_t ) 2 )
-
-/*
- * The value used to fill the stack of a task when the task is created.  This
- * is used purely for checking the high water mark for tasks.
- */
-#define tskSTACK_FILL_BYTE	( 0xa5U )
-
-/* Bits used to recored how a task's stack and TCB were allocated. */
-#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
-#define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
-#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
-
-/* If any of the following are set then task stacks are filled with a known
-value so the high water mark can be determined.  If none of the following are
-set then don't fill the stack so there is no unnecessary dependency on memset. */
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
-	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
-#else
-	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
-#endif
-
-/*
- * Macros used by vListTask to indicate which state a task is in.
- */
-#define tskRUNNING_CHAR		( 'X' )
-#define tskBLOCKED_CHAR		( 'B' )
-#define tskREADY_CHAR		( 'R' )
-#define tskDELETED_CHAR		( 'D' )
-#define tskSUSPENDED_CHAR	( 'S' )
-
-/*
- * Some kernel aware debuggers require the data the debugger needs access to be
- * global, rather than file scope.
- */
-#ifdef portREMOVE_STATIC_QUALIFIER
-	#define static
-#endif
-
-/* The name allocated to the Idle task.  This can be overridden by defining
-configIDLE_TASK_NAME in FreeRTOSConfig.h. */
-#ifndef configIDLE_TASK_NAME
-	#define configIDLE_TASK_NAME "IDLE"
-#endif
-
-#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
-
-	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
-	performed in a generic way that is not optimised to any particular
-	microcontroller architecture. */
-
-	/* uxTopReadyPriority holds the priority of the highest priority ready
-	state task. */
-	#define taskRECORD_READY_PRIORITY( uxPriority )														\
-	{																									\
-		if( ( uxPriority ) > uxTopReadyPriority )														\
-		{																								\
-			uxTopReadyPriority = ( uxPriority );														\
-		}																								\
-	} /* taskRECORD_READY_PRIORITY */
-
-	/*-----------------------------------------------------------*/
-
-	#define taskSELECT_HIGHEST_PRIORITY_TASK()															\
-	{																									\
-	UBaseType_t uxTopPriority = uxTopReadyPriority;														\
-																										\
-		/* Find the highest priority queue that contains ready tasks. */								\
-		while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )							\
-		{																								\
-			configASSERT( uxTopPriority );																\
-			--uxTopPriority;																			\
-		}																								\
-																										\
-		/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of						\
-		the	same priority get an equal share of the processor time. */									\
-		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );			\
-		uxTopReadyPriority = uxTopPriority;																\
-	} /* taskSELECT_HIGHEST_PRIORITY_TASK */
-
-	/*-----------------------------------------------------------*/
-
-	/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
-	they are only required when a port optimised method of task selection is
-	being used. */
-	#define taskRESET_READY_PRIORITY( uxPriority )
-	#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
-
-#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
-	performed in a way that is tailored to the particular microcontroller
-	architecture being used. */
-
-	/* A port optimised version is provided.  Call the port defined macros. */
-	#define taskRECORD_READY_PRIORITY( uxPriority )	portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
-
-	/*-----------------------------------------------------------*/
-
-	#define taskSELECT_HIGHEST_PRIORITY_TASK()														\
-	{																								\
-	UBaseType_t uxTopPriority;																		\
-																									\
-		/* Find the highest priority list that contains ready tasks. */								\
-		portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );								\
-		configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );		\
-		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );		\
-	} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
-
-	/*-----------------------------------------------------------*/
-
-	/* A port optimised version is provided, call it only if the TCB being reset
-	is being referenced from a ready list.  If it is referenced from a delayed
-	or suspended list then it won't be in a ready list. */
-	#define taskRESET_READY_PRIORITY( uxPriority )														\
-	{																									\
-		if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )	\
-		{																								\
-			portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );							\
-		}																								\
-	}
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
-count overflows. */
-#define taskSWITCH_DELAYED_LISTS()																	\
-{																									\
-	List_t *pxTemp;																					\
-																									\
-	/* The delayed tasks list should be empty when the lists are switched. */						\
-	configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );										\
-																									\
-	pxTemp = pxDelayedTaskList;																		\
-	pxDelayedTaskList = pxOverflowDelayedTaskList;													\
-	pxOverflowDelayedTaskList = pxTemp;																\
-	xNumOfOverflows++;																				\
-	prvResetNextTaskUnblockTime();																	\
-}
-
-/*-----------------------------------------------------------*/
-
-/*
- * Place the task represented by pxTCB into the appropriate ready list for
- * the task.  It is inserted at the end of the list.
- */
-#define prvAddTaskToReadyList( pxTCB )																\
-	traceMOVED_TASK_TO_READY_STATE( pxTCB );														\
-	taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );												\
-	vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
-	tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
-
-/*
- * Place the task represented by pxTCB which has been in a ready list before
- * into the appropriate ready list for the task.
- * It is inserted at the end of the list.
- */
-#define prvReaddTaskToReadyList( pxTCB ) \
-       traceREADDED_TASK_TO_READY_STATE( pxTCB ); \
-       taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority ); \
-       vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
-       tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
-/*-----------------------------------------------------------*/
-
-/*
- * Several functions take an TaskHandle_t parameter that can optionally be NULL,
- * where NULL is used to indicate that the handle of the currently executing
- * task should be used in place of the parameter.  This macro simply checks to
- * see if the parameter is NULL and returns a pointer to the appropriate TCB.
- */
-#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
-
-/* The item value of the event list item is normally used to hold the priority
-of the task to which it belongs (coded to allow it to be held in reverse
-priority order).  However, it is occasionally borrowed for other purposes.  It
-is important its value is not updated due to a task priority change while it is
-being used for another purpose.  The following bit definition is used to inform
-the scheduler that the value should not be changed - in which case it is the
-responsibility of whichever module is using the value to ensure it gets set back
-to its original value when it is released. */
-#if( configUSE_16_BIT_TICKS == 1 )
-	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x8000U
-#else
-	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x80000000UL
-#endif
-
-/*
- * Task control block.  A task control block (TCB) is allocated for each task,
- * and stores task state information, including a pointer to the task's context
- * (the task's run time environment, including register values)
- */
-typedef struct tskTaskControlBlock 			/* The old naming convention is used to prevent breaking kernel aware debuggers. */
-{
-	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
-
-	#if ( portUSING_MPU_WRAPPERS == 1 )
-		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
-	#endif
-
-	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
-	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
-	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
-	StackType_t			*pxStack;			/*< Points to the start of the stack. */
-	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
-		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
-	#endif
-
-	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
-		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
-	#endif
-
-	#if ( configUSE_TRACE_FACILITY == 1 )
-		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
-		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
-	#endif
-
-	#if ( configUSE_MUTEXES == 1 )
-		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
-		UBaseType_t		uxMutexesHeld;
-	#endif
-
-	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-		TaskHookFunction_t pxTaskTag;
-	#endif
-
-	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
-		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
-	#endif
-
-	#if( configGENERATE_RUN_TIME_STATS == 1 )
-		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
-	#endif
-
-	#if ( configUSE_NEWLIB_REENTRANT == 1 )
-		/* Allocate a Newlib reent structure that is specific to this task.
-		Note Newlib support has been included by popular demand, but is not
-		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
-		responsible for resulting newlib operation.  User must be familiar with
-		newlib and must provide system-wide implementations of the necessary
-		stubs. Be warned that (at the time of writing) the current newlib design
-		implements a system-wide malloc() that must be provided with locks. */
-		struct	_reent xNewLib_reent;
-	#endif
-
-	#if( configUSE_TASK_NOTIFICATIONS == 1 )
-		volatile uint32_t ulNotifiedValue;
-		volatile uint8_t ucNotifyState;
-	#endif
-
-	/* See the comments in FreeRTOS.h with the definition of
-	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
-	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
-		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
-	#endif
-
-	#if( INCLUDE_xTaskAbortDelay == 1 )
-		uint8_t ucDelayAborted;
-	#endif
-
-	#if( configUSE_POSIX_ERRNO == 1 )
-		int iTaskErrno;
-	#endif
-
-} tskTCB;
-
-/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
-below to enable the use of older kernel aware debuggers. */
-typedef tskTCB TCB_t;
-
-/*lint -save -e956 A manual analysis and inspection has been used to determine
-which static variables must be declared volatile. */
-PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
-
-/* Lists for ready and blocked tasks. --------------------
-xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
-doing so breaks some kernel aware debuggers and debuggers that rely on removing
-the static qualifier. */
-PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */
-PRIVILEGED_DATA static List_t xDelayedTaskList1;						/*< Delayed tasks. */
-PRIVILEGED_DATA static List_t xDelayedTaskList2;						/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
-PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;				/*< Points to the delayed task list currently being used. */
-PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;		/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
-PRIVILEGED_DATA static List_t xPendingReadyList;						/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
-
-#if( INCLUDE_vTaskDelete == 1 )
-
-	PRIVILEGED_DATA static List_t xTasksWaitingTermination;				/*< Tasks that have been deleted - but their memory not yet freed. */
-	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
-
-#endif
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-	PRIVILEGED_DATA static List_t xSuspendedTaskList;					/*< Tasks that are currently suspended. */
-
-#endif
-
-/* Global POSIX errno. Its value is changed upon context switching to match
-the errno of the currently running task. */
-#if ( configUSE_POSIX_ERRNO == 1 )
-	int FreeRTOS_errno = 0;
-#endif
-
-/* Other file private variables. --------------------------------*/
-PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
-PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
-PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
-PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
-PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks 			= ( UBaseType_t ) 0U;
-PRIVILEGED_DATA static volatile BaseType_t xYieldPending 			= pdFALSE;
-PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows 			= ( BaseType_t ) 0;
-PRIVILEGED_DATA static UBaseType_t uxTaskNumber 					= ( UBaseType_t ) 0U;
-PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime		= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
-PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle					= NULL;			/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
-
-/* Context switches are held pending while the scheduler is suspended.  Also,
-interrupts must not manipulate the xStateListItem of a TCB, or any of the
-lists the xStateListItem can be referenced from, if the scheduler is suspended.
-If an interrupt needs to unblock a task while the scheduler is suspended then it
-moves the task's event list item into the xPendingReadyList, ready for the
-kernel to move the task from the pending ready list into the real ready list
-when the scheduler is unsuspended.  The pending ready list itself can only be
-accessed from a critical section. */
-PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t ) pdFALSE;
-
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
-
-	/* Do not move these variables to function scope as doing so prevents the
-	code working with debuggers that need to remove the static qualifier. */
-	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
-	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
-
-#endif
-
-/*lint -restore */
-
-/*-----------------------------------------------------------*/
-
-/* Callback function prototypes. --------------------------*/
-#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
-
-	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
-
-#endif
-
-#if( configUSE_TICK_HOOK > 0 )
-
-	extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
-
-#endif
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
-
-#endif
-
-/* File private functions. --------------------------------*/
-
-/**
- * Utility task that simply returns pdTRUE if the task referenced by xTask is
- * currently in the Suspended state, or pdFALSE if the task referenced by xTask
- * is in any other state.
- */
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-#endif /* INCLUDE_vTaskSuspend */
-
-/*
- * Utility to ready all the lists used by the scheduler.  This is called
- * automatically upon the creation of the first task.
- */
-static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
-
-/*
- * The idle task, which as all tasks is implemented as a never ending loop.
- * The idle task is automatically created and added to the ready lists upon
- * creation of the first user task.
- *
- * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
- * language extensions.  The equivalent prototype for this function is:
- *
- * void prvIdleTask( void *pvParameters );
- *
- */
-static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
-
-/*
- * Utility to free all memory allocated by the scheduler to hold a TCB,
- * including the stack pointed to by the TCB.
- *
- * This does not free memory allocated by the task itself (i.e. memory
- * allocated by calls to pvPortMalloc from within the tasks application code).
- */
-#if ( INCLUDE_vTaskDelete == 1 )
-
-	static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Used only by the idle task.  This checks to see if anything has been placed
- * in the list of tasks waiting to be deleted.  If so the task is cleaned up
- * and its TCB deleted.
- */
-static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
-
-/*
- * The currently executing task is entering the Blocked state.  Add the task to
- * either the current or the overflow delayed task list.
- */
-static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
-
-/*
- * Fills an TaskStatus_t structure with information on each task that is
- * referenced from the pxList list (which may be a ready list, a delayed list,
- * a suspended list, etc.).
- *
- * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
- * NORMAL APPLICATION CODE.
- */
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Searches pxList for a task with name pcNameToQuery - returning a handle to
- * the task if it is found, or NULL if the task is not found.
- */
-#if ( INCLUDE_xTaskGetHandle == 1 )
-
-	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * When a task is created, the stack of the task is filled with a known value.
- * This function determines the 'high water mark' of the task stack by
- * determining how much of the stack remains at the original preset value.
- */
-#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
-
-	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Return the amount of time, in ticks, that will pass before the kernel will
- * next move a task from the Blocked state to the Running state.
- *
- * This conditional compilation should use inequality to 0, not equality to 1.
- * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
- * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
- * set to a value other than 1.
- */
-#if ( configUSE_TICKLESS_IDLE != 0 )
-
-	static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Set xNextTaskUnblockTime to the time at which the next Blocked state task
- * will exit the Blocked state.
- */
-static void prvResetNextTaskUnblockTime( void );
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
-
-	/*
-	 * Helper function used to pad task names with spaces when printing out
-	 * human readable tables of task information.
-	 */
-	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Called after a Task_t structure has been allocated either statically or
- * dynamically to fill in the structure's members.
- */
-static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
-									const char * const pcName, 		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-									const uint32_t ulStackDepth,
-									void * const pvParameters,
-									UBaseType_t uxPriority,
-									TaskHandle_t * const pxCreatedTask,
-									TCB_t *pxNewTCB,
-									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
-
-/*
- * Called after a new task has been created and initialised to place the task
- * under the control of the scheduler.
- */
-static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
-
-/*
- * freertos_tasks_c_additions_init() should only be called if the user definable
- * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
- * called by the function.
- */
-#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
-
-	static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
-									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-									const uint32_t ulStackDepth,
-									void * const pvParameters,
-									UBaseType_t uxPriority,
-									StackType_t * const puxStackBuffer,
-									StaticTask_t * const pxTaskBuffer )
-	{
-	TCB_t *pxNewTCB;
-	TaskHandle_t xReturn;
-
-		configASSERT( puxStackBuffer != NULL );
-		configASSERT( pxTaskBuffer != NULL );
-
-		#if( configASSERT_DEFINED == 1 )
-		{
-			/* Sanity check that the size of the structure used to declare a
-			variable of type StaticTask_t equals the size of the real task
-			structure. */
-			volatile size_t xSize = sizeof( StaticTask_t );
-			configASSERT( xSize == sizeof( TCB_t ) );
-			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
-		}
-		#endif /* configASSERT_DEFINED */
-
-
-		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
-		{
-			/* The memory used for the task's TCB and stack are passed into this
-			function - use them. */
-			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
-			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
-
-			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
-			{
-				/* Tasks can be created statically or dynamically, so note this
-				task was created statically in case the task is later deleted. */
-				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
-			}
-			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
-
-			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
-			prvAddNewTaskToReadyList( pxNewTCB );
-		}
-		else
-		{
-			xReturn = NULL;
-		}
-
-		return xReturn;
-	}
-
-#endif /* SUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
-	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
-	{
-	TCB_t *pxNewTCB;
-	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
-
-		configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
-		configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
-
-		if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
-		{
-			/* Allocate space for the TCB.  Where the memory comes from depends
-			on the implementation of the port malloc function and whether or
-			not static allocation is being used. */
-			pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
-
-			/* Store the stack location in the TCB. */
-			pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
-
-			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
-			{
-				/* Tasks can be created statically or dynamically, so note this
-				task was created statically in case the task is later deleted. */
-				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
-			}
-			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
-
-			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
-									pxTaskDefinition->pcName,
-									( uint32_t ) pxTaskDefinition->usStackDepth,
-									pxTaskDefinition->pvParameters,
-									pxTaskDefinition->uxPriority,
-									pxCreatedTask, pxNewTCB,
-									pxTaskDefinition->xRegions );
-
-			prvAddNewTaskToReadyList( pxNewTCB );
-			xReturn = pdPASS;
-		}
-
-		return xReturn;
-	}
-
-#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
-	{
-	TCB_t *pxNewTCB;
-	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
-
-		configASSERT( pxTaskDefinition->puxStackBuffer );
-
-		if( pxTaskDefinition->puxStackBuffer != NULL )
-		{
-			/* Allocate space for the TCB.  Where the memory comes from depends
-			on the implementation of the port malloc function and whether or
-			not static allocation is being used. */
-			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
-
-			if( pxNewTCB != NULL )
-			{
-				/* Store the stack location in the TCB. */
-				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
-
-				#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
-				{
-					/* Tasks can be created statically or dynamically, so note
-					this task had a statically allocated stack in case it is
-					later deleted.  The TCB was allocated dynamically. */
-					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
-				}
-				#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
-
-				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
-										pxTaskDefinition->pcName,
-										( uint32_t ) pxTaskDefinition->usStackDepth,
-										pxTaskDefinition->pvParameters,
-										pxTaskDefinition->uxPriority,
-										pxCreatedTask, pxNewTCB,
-										pxTaskDefinition->xRegions );
-
-				prvAddNewTaskToReadyList( pxNewTCB );
-				xReturn = pdPASS;
-			}
-		}
-
-		return xReturn;
-	}
-
-#endif /* portUSING_MPU_WRAPPERS */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
-							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-							const configSTACK_DEPTH_TYPE usStackDepth,
-							void * const pvParameters,
-							UBaseType_t uxPriority,
-							TaskHandle_t * const pxCreatedTask )
-	{
-	TCB_t *pxNewTCB;
-	BaseType_t xReturn;
-
-		/* If the stack grows down then allocate the stack then the TCB so the stack
-		does not grow into the TCB.  Likewise if the stack grows up then allocate
-		the TCB then the stack. */
-		#if( portSTACK_GROWTH > 0 )
-		{
-			/* Allocate space for the TCB.  Where the memory comes from depends on
-			the implementation of the port malloc function and whether or not static
-			allocation is being used. */
-			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
-
-			if( pxNewTCB != NULL )
-			{
-				/* Allocate space for the stack used by the task being created.
-				The base of the stack memory stored in the TCB so the task can
-				be deleted later if required. */
-				pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
-				if( pxNewTCB->pxStack == NULL )
-				{
-					/* Could not allocate the stack.  Delete the allocated TCB. */
-					vPortFree( pxNewTCB );
-					pxNewTCB = NULL;
-				}
-			}
-		}
-		#else /* portSTACK_GROWTH */
-		{
-		StackType_t *pxStack;
-
-			/* Allocate space for the stack used by the task being created. */
-			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
-
-			if( pxStack != NULL )
-			{
-				/* Allocate space for the TCB. */
-				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
-
-				if( pxNewTCB != NULL )
-				{
-					/* Store the stack location in the TCB. */
-					pxNewTCB->pxStack = pxStack;
-				}
-				else
-				{
-					/* The stack cannot be used as the TCB was not created.  Free
-					it again. */
-					vPortFree( pxStack );
-				}
-			}
-			else
-			{
-				pxNewTCB = NULL;
-			}
-		}
-		#endif /* portSTACK_GROWTH */
-
-		if( pxNewTCB != NULL )
-		{
-			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
-			{
-				/* Tasks can be created statically or dynamically, so note this
-				task was created dynamically in case it is later deleted. */
-				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
-			}
-			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
-
-			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
-			prvAddNewTaskToReadyList( pxNewTCB );
-			xReturn = pdPASS;
-		}
-		else
-		{
-			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
-		}
-
-		return xReturn;
-	}
-
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
-									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-									const uint32_t ulStackDepth,
-									void * const pvParameters,
-									UBaseType_t uxPriority,
-									TaskHandle_t * const pxCreatedTask,
-									TCB_t *pxNewTCB,
-									const MemoryRegion_t * const xRegions )
-{
-StackType_t *pxTopOfStack;
-UBaseType_t x;
-
-	#if( portUSING_MPU_WRAPPERS == 1 )
-		/* Should the task be created in privileged mode? */
-		BaseType_t xRunPrivileged;
-		if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
-		{
-			xRunPrivileged = pdTRUE;
-		}
-		else
-		{
-			xRunPrivileged = pdFALSE;
-		}
-		uxPriority &= ~portPRIVILEGE_BIT;
-	#endif /* portUSING_MPU_WRAPPERS == 1 */
-
-	/* Avoid dependency on memset() if it is not required. */
-	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
-	{
-		/* Fill the stack with a known value to assist debugging. */
-		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
-	}
-	#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
-
-	/* Calculate the top of stack address.  This depends on whether the stack
-	grows from high memory to low (as per the 80x86) or vice versa.
-	portSTACK_GROWTH is used to make the result positive or negative as required
-	by the port. */
-	#if( portSTACK_GROWTH < 0 )
-	{
-		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
-		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
-
-		/* Check the alignment of the calculated top of stack is correct. */
-		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
-
-		#if( configRECORD_STACK_HIGH_ADDRESS == 1 )
-		{
-			/* Also record the stack's high address, which may assist
-			debugging. */
-			pxNewTCB->pxEndOfStack = pxTopOfStack;
-		}
-		#endif /* configRECORD_STACK_HIGH_ADDRESS */
-	}
-	#else /* portSTACK_GROWTH */
-	{
-		pxTopOfStack = pxNewTCB->pxStack;
-
-		/* Check the alignment of the stack buffer is correct. */
-		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
-
-		/* The other extreme of the stack space is required if stack checking is
-		performed. */
-		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
-	}
-	#endif /* portSTACK_GROWTH */
-
-	/* Store the task name in the TCB. */
-	if( pcName != NULL )
-	{
-		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
-		{
-			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
-
-			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
-			configMAX_TASK_NAME_LEN characters just in case the memory after the
-			string is not accessible (extremely unlikely). */
-			if( pcName[ x ] == ( char ) 0x00 )
-			{
-				break;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-
-		/* Ensure the name string is terminated in the case that the string length
-		was greater or equal to configMAX_TASK_NAME_LEN. */
-		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
-	}
-	else
-	{
-		/* The task has not been given a name, so just ensure there is a NULL
-		terminator when it is read out. */
-		pxNewTCB->pcTaskName[ 0 ] = 0x00;
-	}
-
-	/* This is used as an array index so must ensure it's not too large.  First
-	remove the privilege bit if one is present. */
-	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
-	{
-		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	pxNewTCB->uxPriority = uxPriority;
-	#if ( configUSE_MUTEXES == 1 )
-	{
-		pxNewTCB->uxBasePriority = uxPriority;
-		pxNewTCB->uxMutexesHeld = 0;
-	}
-	#endif /* configUSE_MUTEXES */
-
-	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
-	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
-
-	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
-	back to	the containing TCB from a generic item in a list. */
-	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
-
-	/* Event lists are always in priority order. */
-	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
-
-	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
-	{
-		pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
-	}
-	#endif /* portCRITICAL_NESTING_IN_TCB */
-
-	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-	{
-		pxNewTCB->pxTaskTag = NULL;
-	}
-	#endif /* configUSE_APPLICATION_TASK_TAG */
-
-	#if ( configGENERATE_RUN_TIME_STATS == 1 )
-	{
-		pxNewTCB->ulRunTimeCounter = 0UL;
-	}
-	#endif /* configGENERATE_RUN_TIME_STATS */
-
-	#if ( portUSING_MPU_WRAPPERS == 1 )
-	{
-		vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
-	}
-	#else
-	{
-		/* Avoid compiler warning about unreferenced parameter. */
-		( void ) xRegions;
-	}
-	#endif
-
-	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-	{
-		for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
-		{
-			pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
-		}
-	}
-	#endif
-
-	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-	{
-		pxNewTCB->ulNotifiedValue = 0;
-		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
-	}
-	#endif
-
-	#if ( configUSE_NEWLIB_REENTRANT == 1 )
-	{
-		/* Initialise this task's Newlib reent structure. */
-		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
-	}
-	#endif
-
-	#if( INCLUDE_xTaskAbortDelay == 1 )
-	{
-		pxNewTCB->ucDelayAborted = pdFALSE;
-	}
-	#endif
-
-	/* Initialize the TCB stack to look as if the task was already running,
-	but had been interrupted by the scheduler.  The return address is set
-	to the start of the task function. Once the stack has been initialised
-	the top of stack variable is updated. */
-	#if( portUSING_MPU_WRAPPERS == 1 )
-	{
-		/* If the port has capability to detect stack overflow,
-		pass the stack end address to the stack initialization
-		function as well. */
-		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-		{
-			#if( portSTACK_GROWTH < 0 )
-			{
-				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
-			}
-			#else /* portSTACK_GROWTH */
-			{
-				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
-			}
-			#endif /* portSTACK_GROWTH */
-		}
-		#else /* portHAS_STACK_OVERFLOW_CHECKING */
-		{
-			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
-		}
-		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
-	}
-	#else /* portUSING_MPU_WRAPPERS */
-	{
-		/* If the port has capability to detect stack overflow,
-		pass the stack end address to the stack initialization
-		function as well. */
-		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-		{
-			#if( portSTACK_GROWTH < 0 )
-			{
-				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
-			}
-			#else /* portSTACK_GROWTH */
-			{
-				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
-			}
-			#endif /* portSTACK_GROWTH */
-		}
-		#else /* portHAS_STACK_OVERFLOW_CHECKING */
-		{
-			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
-		}
-		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
-	}
-	#endif /* portUSING_MPU_WRAPPERS */
-
-	if( pxCreatedTask != NULL )
-	{
-		/* Pass the handle out in an anonymous way.  The handle can be used to
-		change the created task's priority, delete the created task, etc.*/
-		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
-{
-	/* Ensure interrupts don't access the task lists while the lists are being
-	updated. */
-	taskENTER_CRITICAL();
-	{
-		uxCurrentNumberOfTasks++;
-		if( pxCurrentTCB == NULL )
-		{
-			/* There are no other tasks, or all the other tasks are in
-			the suspended state - make this the current task. */
-			pxCurrentTCB = pxNewTCB;
-
-			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
-			{
-				/* This is the first task to be created so do the preliminary
-				initialisation required.  We will not recover if this call
-				fails, but we will report the failure. */
-				prvInitialiseTaskLists();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			/* If the scheduler is not already running, make this task the
-			current task if it is the highest priority task to be created
-			so far. */
-			if( xSchedulerRunning == pdFALSE )
-			{
-				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
-				{
-					pxCurrentTCB = pxNewTCB;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-
-		uxTaskNumber++;
-
-		#if ( configUSE_TRACE_FACILITY == 1 )
-		{
-			/* Add a counter into the TCB for tracing only. */
-			pxNewTCB->uxTCBNumber = uxTaskNumber;
-		}
-		#endif /* configUSE_TRACE_FACILITY */
-		traceTASK_CREATE( pxNewTCB );
-
-		prvAddTaskToReadyList( pxNewTCB );
-
-		portSETUP_TCB( pxNewTCB );
-	}
-	taskEXIT_CRITICAL();
-
-	if( xSchedulerRunning != pdFALSE )
-	{
-		/* If the created task is of a higher priority than the current task
-		then it should run now. */
-		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
-		{
-			taskYIELD_IF_USING_PREEMPTION();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelete == 1 )
-
-	void vTaskDelete( TaskHandle_t xTaskToDelete )
-	{
-	TCB_t *pxTCB;
-
-		taskENTER_CRITICAL();
-		{
-			/* If null is passed in here then it is the calling task that is
-			being deleted. */
-			pxTCB = prvGetTCBFromHandle( xTaskToDelete );
-
-			/* Remove task from the ready list. */
-			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-			{
-				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			/* Is the task waiting on an event also? */
-			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-			{
-				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			/* Increment the uxTaskNumber also so kernel aware debuggers can
-			detect that the task lists need re-generating.  This is done before
-			portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
-			not return. */
-			uxTaskNumber++;
-
-			if( pxTCB == pxCurrentTCB )
-			{
-				/* A task is deleting itself.  This cannot complete within the
-				task itself, as a context switch to another task is required.
-				Place the task in the termination list.  The idle task will
-				check the termination list and free up any memory allocated by
-				the scheduler for the TCB and stack of the deleted task. */
-				vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
-
-				/* Increment the ucTasksDeleted variable so the idle task knows
-				there is a task that has been deleted and that it should therefore
-				check the xTasksWaitingTermination list. */
-				++uxDeletedTasksWaitingCleanUp;
-
-				/* The pre-delete hook is primarily for the Windows simulator,
-				in which Windows specific clean up operations are performed,
-				after which it is not possible to yield away from this task -
-				hence xYieldPending is used to latch that a context switch is
-				required. */
-				portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
-			}
-			else
-			{
-				--uxCurrentNumberOfTasks;
-				prvDeleteTCB( pxTCB );
-
-				/* Reset the next expected unblock time in case it referred to
-				the task that has just been deleted. */
-				prvResetNextTaskUnblockTime();
-			}
-
-			traceTASK_DELETE( pxTCB );
-		}
-		taskEXIT_CRITICAL();
-
-		/* Force a reschedule if it is the currently running task that has just
-		been deleted. */
-		if( xSchedulerRunning != pdFALSE )
-		{
-			if( pxTCB == pxCurrentTCB )
-			{
-				configASSERT( uxSchedulerSuspended == 0 );
-				portYIELD_WITHIN_API();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-	}
-
-#endif /* INCLUDE_vTaskDelete */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelayUntil == 1 )
-
-	void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
-	{
-	TickType_t xTimeToWake;
-	BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
-
-		configASSERT( pxPreviousWakeTime );
-		configASSERT( ( xTimeIncrement > 0U ) );
-		configASSERT( uxSchedulerSuspended == 0 );
-
-		vTaskSuspendAll();
-		{
-			/* Minor optimisation.  The tick count cannot change in this
-			block. */
-			const TickType_t xConstTickCount = xTickCount;
-
-			/* Generate the tick time at which the task wants to wake. */
-			xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
-
-			if( xConstTickCount < *pxPreviousWakeTime )
-			{
-				/* The tick count has overflowed since this function was
-				lasted called.  In this case the only time we should ever
-				actually delay is if the wake time has also	overflowed,
-				and the wake time is greater than the tick time.  When this
-				is the case it is as if neither time had overflowed. */
-				if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
-				{
-					xShouldDelay = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				/* The tick time has not overflowed.  In this case we will
-				delay if either the wake time has overflowed, and/or the
-				tick time is less than the wake time. */
-				if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
-				{
-					xShouldDelay = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-
-			/* Update the wake time ready for the next call. */
-			*pxPreviousWakeTime = xTimeToWake;
-
-			if( xShouldDelay != pdFALSE )
-			{
-				traceTASK_DELAY_UNTIL( xTimeToWake );
-
-				/* prvAddCurrentTaskToDelayedList() needs the block time, not
-				the time to wake, so subtract the current tick count. */
-				prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		xAlreadyYielded = xTaskResumeAll();
-
-		/* Force a reschedule if xTaskResumeAll has not already done so, we may
-		have put ourselves to sleep. */
-		if( xAlreadyYielded == pdFALSE )
-		{
-			portYIELD_WITHIN_API();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* INCLUDE_vTaskDelayUntil */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelay == 1 )
-
-	void vTaskDelay( const TickType_t xTicksToDelay )
-	{
-	BaseType_t xAlreadyYielded = pdFALSE;
-
-		/* A delay time of zero just forces a reschedule. */
-		if( xTicksToDelay > ( TickType_t ) 0U )
-		{
-			configASSERT( uxSchedulerSuspended == 0 );
-			vTaskSuspendAll();
-			{
-				traceTASK_DELAY();
-
-				/* A task that is removed from the event list while the
-				scheduler is suspended will not get placed in the ready
-				list or removed from the blocked list until the scheduler
-				is resumed.
-
-				This task cannot be in an event list as it is the currently
-				executing task. */
-				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
-			}
-			xAlreadyYielded = xTaskResumeAll();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		/* Force a reschedule if xTaskResumeAll has not already done so, we may
-		have put ourselves to sleep. */
-		if( xAlreadyYielded == pdFALSE )
-		{
-			portYIELD_WITHIN_API();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* INCLUDE_vTaskDelay */
-/*-----------------------------------------------------------*/
-
-#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
-
-	eTaskState eTaskGetState( TaskHandle_t xTask )
-	{
-	eTaskState eReturn;
-	List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
-	const TCB_t * const pxTCB = xTask;
-
-		configASSERT( pxTCB );
-
-		if( pxTCB == pxCurrentTCB )
-		{
-			/* The task calling this function is querying its own state. */
-			eReturn = eRunning;
-		}
-		else
-		{
-			taskENTER_CRITICAL();
-			{
-				pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
-				pxDelayedList = pxDelayedTaskList;
-				pxOverflowedDelayedList = pxOverflowDelayedTaskList;
-			}
-			taskEXIT_CRITICAL();
-
-			if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
-			{
-				/* The task being queried is referenced from one of the Blocked
-				lists. */
-				eReturn = eBlocked;
-			}
-
-			#if ( INCLUDE_vTaskSuspend == 1 )
-				else if( pxStateList == &xSuspendedTaskList )
-				{
-					/* The task being queried is referenced from the suspended
-					list.  Is it genuinely suspended or is it blocked
-					indefinitely? */
-					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
-					{
-						#if( configUSE_TASK_NOTIFICATIONS == 1 )
-						{
-							/* The task does not appear on the event list item of
-							and of the RTOS objects, but could still be in the
-							blocked state if it is waiting on its notification
-							rather than waiting on an object. */
-							if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
-							{
-								eReturn = eBlocked;
-							}
-							else
-							{
-								eReturn = eSuspended;
-							}
-						}
-						#else
-						{
-							eReturn = eSuspended;
-						}
-						#endif
-					}
-					else
-					{
-						eReturn = eBlocked;
-					}
-				}
-			#endif
-
-			#if ( INCLUDE_vTaskDelete == 1 )
-				else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
-				{
-					/* The task being queried is referenced from the deleted
-					tasks list, or it is not referenced from any lists at
-					all. */
-					eReturn = eDeleted;
-				}
-			#endif
-
-			else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
-			{
-				/* If the task is not in any other state, it must be in the
-				Ready (including pending ready) state. */
-				eReturn = eReady;
-			}
-		}
-
-		return eReturn;
-	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
-
-#endif /* INCLUDE_eTaskGetState */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
-
-	UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
-	{
-	TCB_t const *pxTCB;
-	UBaseType_t uxReturn;
-
-		taskENTER_CRITICAL();
-		{
-			/* If null is passed in here then it is the priority of the task
-			that called uxTaskPriorityGet() that is being queried. */
-			pxTCB = prvGetTCBFromHandle( xTask );
-			uxReturn = pxTCB->uxPriority;
-		}
-		taskEXIT_CRITICAL();
-
-		return uxReturn;
-	}
-
-#endif /* INCLUDE_uxTaskPriorityGet */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
-
-	UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
-	{
-	TCB_t const *pxTCB;
-	UBaseType_t uxReturn, uxSavedInterruptState;
-
-		/* RTOS ports that support interrupt nesting have the concept of a
-		maximum	system call (or maximum API call) interrupt priority.
-		Interrupts that are	above the maximum system call priority are keep
-		permanently enabled, even when the RTOS kernel is in a critical section,
-		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
-		is defined in FreeRTOSConfig.h then
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-		failure if a FreeRTOS API function is called from an interrupt that has
-		been assigned a priority above the configured maximum system call
-		priority.  Only FreeRTOS functions that end in FromISR can be called
-		from interrupts	that have been assigned a priority at or (logically)
-		below the maximum system call interrupt priority.  FreeRTOS maintains a
-		separate interrupt safe API to ensure interrupt entry is as fast and as
-		simple as possible.  More information (albeit Cortex-M specific) is
-		provided on the following link:
-		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
-		{
-			/* If null is passed in here then it is the priority of the calling
-			task that is being queried. */
-			pxTCB = prvGetTCBFromHandle( xTask );
-			uxReturn = pxTCB->uxPriority;
-		}
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
-
-		return uxReturn;
-	}
-
-#endif /* INCLUDE_uxTaskPriorityGet */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskPrioritySet == 1 )
-
-	void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
-	{
-	TCB_t *pxTCB;
-	UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
-	BaseType_t xYieldRequired = pdFALSE;
-
-		configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
-
-		/* Ensure the new priority is valid. */
-		if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
-		{
-			uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		taskENTER_CRITICAL();
-		{
-			/* If null is passed in here then it is the priority of the calling
-			task that is being changed. */
-			pxTCB = prvGetTCBFromHandle( xTask );
-
-			traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
-
-			#if ( configUSE_MUTEXES == 1 )
-			{
-				uxCurrentBasePriority = pxTCB->uxBasePriority;
-			}
-			#else
-			{
-				uxCurrentBasePriority = pxTCB->uxPriority;
-			}
-			#endif
-
-			if( uxCurrentBasePriority != uxNewPriority )
-			{
-				/* The priority change may have readied a task of higher
-				priority than the calling task. */
-				if( uxNewPriority > uxCurrentBasePriority )
-				{
-					if( pxTCB != pxCurrentTCB )
-					{
-						/* The priority of a task other than the currently
-						running task is being raised.  Is the priority being
-						raised above that of the running task? */
-						if( uxNewPriority >= pxCurrentTCB->uxPriority )
-						{
-							xYieldRequired = pdTRUE;
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						/* The priority of the running task is being raised,
-						but the running task must already be the highest
-						priority task able to run so no yield is required. */
-					}
-				}
-				else if( pxTCB == pxCurrentTCB )
-				{
-					/* Setting the priority of the running task down means
-					there may now be another task of higher priority that
-					is ready to execute. */
-					xYieldRequired = pdTRUE;
-				}
-				else
-				{
-					/* Setting the priority of any other task down does not
-					require a yield as the running task must be above the
-					new priority of the task being modified. */
-				}
-
-				/* Remember the ready list the task might be referenced from
-				before its uxPriority member is changed so the
-				taskRESET_READY_PRIORITY() macro can function correctly. */
-				uxPriorityUsedOnEntry = pxTCB->uxPriority;
-
-				#if ( configUSE_MUTEXES == 1 )
-				{
-					/* Only change the priority being used if the task is not
-					currently using an inherited priority. */
-					if( pxTCB->uxBasePriority == pxTCB->uxPriority )
-					{
-						pxTCB->uxPriority = uxNewPriority;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* The base priority gets set whatever. */
-					pxTCB->uxBasePriority = uxNewPriority;
-				}
-				#else
-				{
-					pxTCB->uxPriority = uxNewPriority;
-				}
-				#endif
-
-				/* Only reset the event list item value if the value is not
-				being used for anything else. */
-				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
-				{
-					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* If the task is in the blocked or suspended list we need do
-				nothing more than change its priority variable. However, if
-				the task is in a ready list it needs to be removed and placed
-				in the list appropriate to its new priority. */
-				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
-				{
-					/* The task is currently in its ready list - remove before
-					adding it to it's new ready list.  As we are in a critical
-					section we can do this even if the scheduler is suspended. */
-					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-					{
-						/* It is known that the task is in its ready list so
-						there is no need to check again and the port level
-						reset macro can be called directly. */
-						portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-					prvReaddTaskToReadyList( pxTCB );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				if( xYieldRequired != pdFALSE )
-				{
-					taskYIELD_IF_USING_PREEMPTION();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* Remove compiler warning about unused variables when the port
-				optimised task selection is not being used. */
-				( void ) uxPriorityUsedOnEntry;
-			}
-		}
-		taskEXIT_CRITICAL();
-	}
-
-#endif /* INCLUDE_vTaskPrioritySet */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-	void vTaskSuspend( TaskHandle_t xTaskToSuspend )
-	{
-	TCB_t *pxTCB;
-
-		taskENTER_CRITICAL();
-		{
-			/* If null is passed in here then it is the running task that is
-			being suspended. */
-			pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
-
-			traceTASK_SUSPEND( pxTCB );
-
-			/* Remove task from the ready/delayed list and place in the
-			suspended list. */
-			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-			{
-				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			/* Is the task waiting on an event also? */
-			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-			{
-				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			traceMOVED_TASK_TO_SUSPENDED_LIST(pxTCB);
-			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
-
-			#if( configUSE_TASK_NOTIFICATIONS == 1 )
-			{
-				if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
-				{
-					/* The task was blocked to wait for a notification, but is
-					now suspended, so no notification was received. */
-					pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
-				}
-			}
-			#endif
-		}
-		taskEXIT_CRITICAL();
-
-		if( xSchedulerRunning != pdFALSE )
-		{
-			/* Reset the next expected unblock time in case it referred to the
-			task that is now in the Suspended state. */
-			taskENTER_CRITICAL();
-			{
-				prvResetNextTaskUnblockTime();
-			}
-			taskEXIT_CRITICAL();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		if( pxTCB == pxCurrentTCB )
-		{
-			if( xSchedulerRunning != pdFALSE )
-			{
-				/* The current task has just been suspended. */
-				configASSERT( uxSchedulerSuspended == 0 );
-				portYIELD_WITHIN_API();
-			}
-			else
-			{
-				/* The scheduler is not running, but the task that was pointed
-				to by pxCurrentTCB has just been suspended and pxCurrentTCB
-				must be adjusted to point to a different task. */
-				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
-				{
-					/* No other tasks are ready, so set pxCurrentTCB back to
-					NULL so when the next task is created pxCurrentTCB will
-					be set to point to it no matter what its relative priority
-					is. */
-					pxCurrentTCB = NULL;
-				}
-				else
-				{
-					vTaskSwitchContext();
-				}
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* INCLUDE_vTaskSuspend */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
-	{
-	BaseType_t xReturn = pdFALSE;
-	const TCB_t * const pxTCB = xTask;
-
-		/* Accesses xPendingReadyList so must be called from a critical
-		section. */
-
-		/* It does not make sense to check if the calling task is suspended. */
-		configASSERT( xTask );
-
-		/* Is the task being resumed actually in the suspended list? */
-		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
-		{
-			/* Has the task already been resumed from within an ISR? */
-			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
-			{
-				/* Is it in the suspended list because it is in the	Suspended
-				state, or because is is blocked with no timeout? */
-				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
-				{
-					xReturn = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return xReturn;
-	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
-
-#endif /* INCLUDE_vTaskSuspend */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-	void vTaskResume( TaskHandle_t xTaskToResume )
-	{
-	TCB_t * const pxTCB = xTaskToResume;
-
-		/* It does not make sense to resume the calling task. */
-		configASSERT( xTaskToResume );
-
-		/* The parameter cannot be NULL as it is impossible to resume the
-		currently executing task. */
-		if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
-		{
-			taskENTER_CRITICAL();
-			{
-				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
-				{
-					traceTASK_RESUME( pxTCB );
-
-					/* The ready list can be accessed even if the scheduler is
-					suspended because this is inside a critical section. */
-					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
-					prvAddTaskToReadyList( pxTCB );
-
-					/* A higher priority task may have just been resumed. */
-					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
-					{
-						/* This yield may not cause the task just resumed to run,
-						but will leave the lists in the correct state for the
-						next yield. */
-						taskYIELD_IF_USING_PREEMPTION();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			taskEXIT_CRITICAL();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* INCLUDE_vTaskSuspend */
-
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
-
-	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
-	{
-	BaseType_t xYieldRequired = pdFALSE;
-	TCB_t * const pxTCB = xTaskToResume;
-	UBaseType_t uxSavedInterruptStatus;
-
-		configASSERT( xTaskToResume );
-
-		/* RTOS ports that support interrupt nesting have the concept of a
-		maximum	system call (or maximum API call) interrupt priority.
-		Interrupts that are	above the maximum system call priority are keep
-		permanently enabled, even when the RTOS kernel is in a critical section,
-		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
-		is defined in FreeRTOSConfig.h then
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-		failure if a FreeRTOS API function is called from an interrupt that has
-		been assigned a priority above the configured maximum system call
-		priority.  Only FreeRTOS functions that end in FromISR can be called
-		from interrupts	that have been assigned a priority at or (logically)
-		below the maximum system call interrupt priority.  FreeRTOS maintains a
-		separate interrupt safe API to ensure interrupt entry is as fast and as
-		simple as possible.  More information (albeit Cortex-M specific) is
-		provided on the following link:
-		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-		{
-			if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
-			{
-				traceTASK_RESUME_FROM_ISR( pxTCB );
-
-				/* Check the ready lists can be accessed. */
-				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-				{
-					/* Ready lists can be accessed so move the task from the
-					suspended list to the ready list directly. */
-					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
-					{
-						xYieldRequired = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-					prvAddTaskToReadyList( pxTCB );
-				}
-				else
-				{
-					/* The delayed or ready lists cannot be accessed so the task
-					is held in the pending ready list until the scheduler is
-					unsuspended. */
-					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-		return xYieldRequired;
-	}
-
-#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-void vTaskStartScheduler( void )
-{
-BaseType_t xReturn;
-
-	/* Add the idle task at the lowest priority. */
-	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	{
-		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
-		StackType_t *pxIdleTaskStackBuffer = NULL;
-		uint32_t ulIdleTaskStackSize;
-
-		/* The Idle task is created using user provided RAM - obtain the
-		address of the RAM then create the idle task. */
-		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
-		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
-												configIDLE_TASK_NAME,
-												ulIdleTaskStackSize,
-												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
-												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-												pxIdleTaskStackBuffer,
-												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-
-		if( xIdleTaskHandle != NULL )
-		{
-			xReturn = pdPASS;
-		}
-		else
-		{
-			xReturn = pdFAIL;
-		}
-	}
-	#else
-	{
-		/* The Idle task is being created using dynamically allocated RAM. */
-		xReturn = xTaskCreate(	prvIdleTask,
-								configIDLE_TASK_NAME,
-								configMINIMAL_STACK_SIZE,
-								( void * ) NULL,
-								portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-	}
-	#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-	#if ( configUSE_TIMERS == 1 )
-	{
-		if( xReturn == pdPASS )
-		{
-			xReturn = xTimerCreateTimerTask();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif /* configUSE_TIMERS */
-
-	if( xReturn == pdPASS )
-	{
-		/* freertos_tasks_c_additions_init() should only be called if the user
-		definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
-		the only macro called by the function. */
-		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
-		{
-			freertos_tasks_c_additions_init();
-		}
-		#endif
-
-		/* Interrupts are turned off here, to ensure a tick does not occur
-		before or during the call to xPortStartScheduler().  The stacks of
-		the created tasks contain a status word with interrupts switched on
-		so interrupts will automatically get re-enabled when the first task
-		starts to run. */
-		portDISABLE_INTERRUPTS();
-
-		#if ( configUSE_NEWLIB_REENTRANT == 1 )
-		{
-			/* Switch Newlib's _impure_ptr variable to point to the _reent
-			structure specific to the task that will run first. */
-			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
-		}
-		#endif /* configUSE_NEWLIB_REENTRANT */
-
-		xNextTaskUnblockTime = portMAX_DELAY;
-		xSchedulerRunning = pdTRUE;
-		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
-
-		/* If configGENERATE_RUN_TIME_STATS is defined then the following
-		macro must be defined to configure the timer/counter used to generate
-		the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
-		is set to 0 and the following line fails to build then ensure you do not
-		have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
-		FreeRTOSConfig.h file. */
-		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
-
-		traceTASK_SWITCHED_IN();
-
-		/* Setting up the timer tick is hardware specific and thus in the
-		portable interface. */
-		if( xPortStartScheduler() != pdFALSE )
-		{
-			/* Should not reach here as if the scheduler is running the
-			function will not return. */
-		}
-		else
-		{
-			/* Should only reach here if a task calls xTaskEndScheduler(). */
-		}
-	}
-	else
-	{
-		/* This line will only be reached if the kernel could not be started,
-		because there was not enough FreeRTOS heap to create the idle task
-		or the timer task. */
-		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
-	}
-
-	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
-	meaning xIdleTaskHandle is not used anywhere else. */
-	( void ) xIdleTaskHandle;
-}
-/*-----------------------------------------------------------*/
-
-void vTaskEndScheduler( void )
-{
-	/* Stop the scheduler interrupts and call the portable scheduler end
-	routine so the original ISRs can be restored if necessary.  The port
-	layer must ensure interrupts enable	bit is left in the correct state. */
-	portDISABLE_INTERRUPTS();
-	xSchedulerRunning = pdFALSE;
-	vPortEndScheduler();
-}
-/*----------------------------------------------------------*/
-
-void vTaskSuspendAll( void )
-{
-	/* A critical section is not required as the variable is of type
-	BaseType_t.  Please read Richard Barry's reply in the following link to a
-	post in the FreeRTOS support forum before reporting this as a bug! -
-	http://goo.gl/wu4acr */
-	++uxSchedulerSuspended;
-	portMEMORY_BARRIER();
-}
-/*----------------------------------------------------------*/
-
-#if ( configUSE_TICKLESS_IDLE != 0 )
-
-	static TickType_t prvGetExpectedIdleTime( void )
-	{
-	TickType_t xReturn;
-	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
-
-		/* uxHigherPriorityReadyTasks takes care of the case where
-		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
-		task that are in the Ready state, even though the idle task is
-		running. */
-		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
-		{
-			if( uxTopReadyPriority > tskIDLE_PRIORITY )
-			{
-				uxHigherPriorityReadyTasks = pdTRUE;
-			}
-		}
-		#else
-		{
-			const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
-
-			/* When port optimised task selection is used the uxTopReadyPriority
-			variable is used as a bit map.  If bits other than the least
-			significant bit are set then there are tasks that have a priority
-			above the idle priority that are in the Ready state.  This takes
-			care of the case where the co-operative scheduler is in use. */
-			if( uxTopReadyPriority > uxLeastSignificantBit )
-			{
-				uxHigherPriorityReadyTasks = pdTRUE;
-			}
-		}
-		#endif
-
-		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
-		{
-			xReturn = 0;
-		}
-		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
-		{
-			/* There are other idle priority tasks in the ready state.  If
-			time slicing is used then the very next tick interrupt must be
-			processed. */
-			xReturn = 0;
-		}
-		else if( uxHigherPriorityReadyTasks != pdFALSE )
-		{
-			/* There are tasks in the Ready state that have a priority above the
-			idle priority.  This path can only be reached if
-			configUSE_PREEMPTION is 0. */
-			xReturn = 0;
-		}
-		else
-		{
-			xReturn = xNextTaskUnblockTime - xTickCount;
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*----------------------------------------------------------*/
-
-BaseType_t xTaskResumeAll( void )
-{
-TCB_t *pxTCB = NULL;
-BaseType_t xAlreadyYielded = pdFALSE;
-
-	/* If uxSchedulerSuspended is zero then this function does not match a
-	previous call to vTaskSuspendAll(). */
-	configASSERT( uxSchedulerSuspended );
-
-	/* It is possible that an ISR caused a task to be removed from an event
-	list while the scheduler was suspended.  If this was the case then the
-	removed task will have been added to the xPendingReadyList.  Once the
-	scheduler has been resumed it is safe to move all the pending ready
-	tasks from this list into their appropriate ready list. */
-	taskENTER_CRITICAL();
-	{
-		--uxSchedulerSuspended;
-
-		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-		{
-			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
-			{
-				/* Move any readied tasks from the pending list into the
-				appropriate ready list. */
-				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
-				{
-					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-					prvAddTaskToReadyList( pxTCB );
-
-					/* If the moved task has a priority higher than the current
-					task then a yield must be performed. */
-					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
-					{
-						xYieldPending = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-
-				if( pxTCB != NULL )
-				{
-					/* A task was unblocked while the scheduler was suspended,
-					which may have prevented the next unblock time from being
-					re-calculated, in which case re-calculate it now.  Mainly
-					important for low power tickless implementations, where
-					this can prevent an unnecessary exit from low power
-					state. */
-					prvResetNextTaskUnblockTime();
-				}
-
-				/* If any ticks occurred while the scheduler was suspended then
-				they should be processed now.  This ensures the tick count does
-				not	slip, and that any delayed tasks are resumed at the correct
-				time. */
-				{
-					UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
-
-					if( uxPendedCounts > ( UBaseType_t ) 0U )
-					{
-						do
-						{
-							if( xTaskIncrementTick() != pdFALSE )
-							{
-								xYieldPending = pdTRUE;
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-							--uxPendedCounts;
-						} while( uxPendedCounts > ( UBaseType_t ) 0U );
-
-						uxPendedTicks = 0;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-
-				if( xYieldPending != pdFALSE )
-				{
-					#if( configUSE_PREEMPTION != 0 )
-					{
-						xAlreadyYielded = pdTRUE;
-					}
-					#endif
-					taskYIELD_IF_USING_PREEMPTION();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	return xAlreadyYielded;
-}
-/*-----------------------------------------------------------*/
-
-TickType_t xTaskGetTickCount( void )
-{
-TickType_t xTicks;
-
-	/* Critical section required if running on a 16 bit processor. */
-	portTICK_TYPE_ENTER_CRITICAL();
-	{
-		xTicks = xTickCount;
-	}
-	portTICK_TYPE_EXIT_CRITICAL();
-
-	return xTicks;
-}
-/*-----------------------------------------------------------*/
-
-TickType_t xTaskGetTickCountFromISR( void )
-{
-TickType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-
-	/* RTOS ports that support interrupt nesting have the concept of a maximum
-	system call (or maximum API call) interrupt priority.  Interrupts that are
-	above the maximum system call priority are kept permanently enabled, even
-	when the RTOS kernel is in a critical section, but cannot make any calls to
-	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-	failure if a FreeRTOS API function is called from an interrupt that has been
-	assigned a priority above the configured maximum system call priority.
-	Only FreeRTOS functions that end in FromISR can be called from interrupts
-	that have been assigned a priority at or (logically) below the maximum
-	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
-	safe API to ensure interrupt entry is as fast and as simple as possible.
-	More information (albeit Cortex-M specific) is provided on the following
-	link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
-	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
-	{
-		xReturn = xTickCount;
-	}
-	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxTaskGetNumberOfTasks( void )
-{
-	/* A critical section is not required because the variables are of type
-	BaseType_t. */
-	return uxCurrentNumberOfTasks;
-}
-/*-----------------------------------------------------------*/
-
-char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-{
-TCB_t *pxTCB;
-
-	/* If null is passed in here then the name of the calling task is being
-	queried. */
-	pxTCB = prvGetTCBFromHandle( xTaskToQuery );
-	configASSERT( pxTCB );
-	return &( pxTCB->pcTaskName[ 0 ] );
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetHandle == 1 )
-
-	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
-	{
-	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
-	UBaseType_t x;
-	char cNextChar;
-	BaseType_t xBreakLoop;
-
-		/* This function is called with the scheduler suspended. */
-
-		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
-		{
-			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
-			do
-			{
-				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
-				/* Check each character in the name looking for a match or
-				mismatch. */
-				xBreakLoop = pdFALSE;
-				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
-				{
-					cNextChar = pxNextTCB->pcTaskName[ x ];
-
-					if( cNextChar != pcNameToQuery[ x ] )
-					{
-						/* Characters didn't match. */
-						xBreakLoop = pdTRUE;
-					}
-					else if( cNextChar == ( char ) 0x00 )
-					{
-						/* Both strings terminated, a match must have been
-						found. */
-						pxReturn = pxNextTCB;
-						xBreakLoop = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					if( xBreakLoop != pdFALSE )
-					{
-						break;
-					}
-				}
-
-				if( pxReturn != NULL )
-				{
-					/* The handle has been found. */
-					break;
-				}
-
-			} while( pxNextTCB != pxFirstTCB );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return pxReturn;
-	}
-
-#endif /* INCLUDE_xTaskGetHandle */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetHandle == 1 )
-
-	TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	{
-	UBaseType_t uxQueue = configMAX_PRIORITIES;
-	TCB_t* pxTCB;
-
-		/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
-		configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
-
-		vTaskSuspendAll();
-		{
-			/* Search the ready lists. */
-			do
-			{
-				uxQueue--;
-				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
-
-				if( pxTCB != NULL )
-				{
-					/* Found the handle. */
-					break;
-				}
-
-			} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
-			/* Search the delayed lists. */
-			if( pxTCB == NULL )
-			{
-				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
-			}
-
-			if( pxTCB == NULL )
-			{
-				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
-			}
-
-			#if ( INCLUDE_vTaskSuspend == 1 )
-			{
-				if( pxTCB == NULL )
-				{
-					/* Search the suspended list. */
-					pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
-				}
-			}
-			#endif
-
-			#if( INCLUDE_vTaskDelete == 1 )
-			{
-				if( pxTCB == NULL )
-				{
-					/* Search the deleted list. */
-					pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
-				}
-			}
-			#endif
-		}
-		( void ) xTaskResumeAll();
-
-		return pxTCB;
-	}
-
-#endif /* INCLUDE_xTaskGetHandle */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
-	{
-	UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
-
-		vTaskSuspendAll();
-		{
-			/* Is there a space in the array for each task in the system? */
-			if( uxArraySize >= uxCurrentNumberOfTasks )
-			{
-				/* Fill in an TaskStatus_t structure with information on each
-				task in the Ready state. */
-				do
-				{
-					uxQueue--;
-					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
-
-				} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
-				/* Fill in an TaskStatus_t structure with information on each
-				task in the Blocked state. */
-				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
-				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
-
-				#if( INCLUDE_vTaskDelete == 1 )
-				{
-					/* Fill in an TaskStatus_t structure with information on
-					each task that has been deleted but not yet cleaned up. */
-					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
-				}
-				#endif
-
-				#if ( INCLUDE_vTaskSuspend == 1 )
-				{
-					/* Fill in an TaskStatus_t structure with information on
-					each task in the Suspended state. */
-					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
-				}
-				#endif
-
-				#if ( configGENERATE_RUN_TIME_STATS == 1)
-				{
-					if( pulTotalRunTime != NULL )
-					{
-						#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
-							portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
-						#else
-							*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
-						#endif
-					}
-				}
-				#else
-				{
-					if( pulTotalRunTime != NULL )
-					{
-						*pulTotalRunTime = 0;
-					}
-				}
-				#endif
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		( void ) xTaskResumeAll();
-
-		return uxTask;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
-
-	TaskHandle_t xTaskGetIdleTaskHandle( void )
-	{
-		/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
-		started, then xIdleTaskHandle will be NULL. */
-		configASSERT( ( xIdleTaskHandle != NULL ) );
-		return xIdleTaskHandle;
-	}
-
-#endif /* INCLUDE_xTaskGetIdleTaskHandle */
-/*----------------------------------------------------------*/
-
-/* This conditional compilation should use inequality to 0, not equality to 1.
-This is to ensure vTaskStepTick() is available when user defined low power mode
-implementations require configUSE_TICKLESS_IDLE to be set to a value other than
-1. */
-#if ( configUSE_TICKLESS_IDLE != 0 )
-
-	void vTaskStepTick( const TickType_t xTicksToJump )
-	{
-		/* Correct the tick count value after a period during which the tick
-		was suppressed.  Note this does *not* call the tick hook function for
-		each stepped tick. */
-		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
-		xTickCount += xTicksToJump;
-		traceINCREASE_TICK_COUNT( xTicksToJump );
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskAbortDelay == 1 )
-
-	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
-	{
-	TCB_t *pxTCB = xTask;
-	BaseType_t xReturn;
-
-		configASSERT( pxTCB );
-
-		vTaskSuspendAll();
-		{
-			/* A task can only be prematurely removed from the Blocked state if
-			it is actually in the Blocked state. */
-			if( eTaskGetState( xTask ) == eBlocked )
-			{
-				xReturn = pdPASS;
-
-				/* Remove the reference to the task from the blocked list.  An
-				interrupt won't touch the xStateListItem because the
-				scheduler is suspended. */
-				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-
-				/* Is the task waiting on an event also?  If so remove it from
-				the event list too.  Interrupts can touch the event list item,
-				even though the scheduler is suspended, so a critical section
-				is used. */
-				taskENTER_CRITICAL();
-				{
-					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-					{
-						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-						pxTCB->ucDelayAborted = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				taskEXIT_CRITICAL();
-
-				/* Place the unblocked task into the appropriate ready list. */
-				prvAddTaskToReadyList( pxTCB );
-
-				/* A task being unblocked cannot cause an immediate context
-				switch if preemption is turned off. */
-				#if (  configUSE_PREEMPTION == 1 )
-				{
-					/* Preemption is on, but a context switch should only be
-					performed if the unblocked task has a priority that is
-					equal to or higher than the currently executing task. */
-					if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-					{
-						/* Pend the yield to be performed when the scheduler
-						is unsuspended. */
-						xYieldPending = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				#endif /* configUSE_PREEMPTION */
-			}
-			else
-			{
-				xReturn = pdFAIL;
-			}
-		}
-		( void ) xTaskResumeAll();
-
-		return xReturn;
-	}
-
-#endif /* INCLUDE_xTaskAbortDelay */
-/*----------------------------------------------------------*/
-
-BaseType_t xTaskIncrementTick( void )
-{
-TCB_t * pxTCB;
-TickType_t xItemValue;
-BaseType_t xSwitchRequired = pdFALSE;
-
-	/* Called by the portable layer each time a tick interrupt occurs.
-	Increments the tick then checks to see if the new tick value will cause any
-	tasks to be unblocked. */
-	traceTASK_INCREMENT_TICK( xTickCount );
-	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-	{
-		/* Minor optimisation.  The tick count cannot change in this
-		block. */
-		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
-
-		/* Increment the RTOS tick, switching the delayed and overflowed
-		delayed lists if it wraps to 0. */
-		xTickCount = xConstTickCount;
-
-		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
-		{
-			taskSWITCH_DELAYED_LISTS();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		/* See if this tick has made a timeout expire.  Tasks are stored in
-		the	queue in the order of their wake time - meaning once one task
-		has been found whose block time has not expired there is no need to
-		look any further down the list. */
-		if( xConstTickCount >= xNextTaskUnblockTime )
-		{
-			for( ;; )
-			{
-				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
-				{
-					/* The delayed list is empty.  Set xNextTaskUnblockTime
-					to the maximum possible value so it is extremely
-					unlikely that the
-					if( xTickCount >= xNextTaskUnblockTime ) test will pass
-					next time through. */
-					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-					break;
-				}
-				else
-				{
-					/* The delayed list is not empty, get the value of the
-					item at the head of the delayed list.  This is the time
-					at which the task at the head of the delayed list must
-					be removed from the Blocked state. */
-					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
-
-					if( xConstTickCount < xItemValue )
-					{
-						/* It is not time to unblock this item yet, but the
-						item value is the time at which the task at the head
-						of the blocked list must be removed from the Blocked
-						state -	so record the item value in
-						xNextTaskUnblockTime. */
-						xNextTaskUnblockTime = xItemValue;
-						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* It is time to remove the item from the Blocked state. */
-					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-
-					/* Is the task waiting on an event also?  If so remove
-					it from the event list. */
-					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-					{
-						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* Place the unblocked task into the appropriate ready
-					list. */
-					prvAddTaskToReadyList( pxTCB );
-
-					/* A task being unblocked cannot cause an immediate
-					context switch if preemption is turned off. */
-					#if (  configUSE_PREEMPTION == 1 )
-					{
-						/* Preemption is on, but a context switch should
-						only be performed if the unblocked task has a
-						priority that is equal to or higher than the
-						currently executing task. */
-						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
-						{
-							xSwitchRequired = pdTRUE;
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					#endif /* configUSE_PREEMPTION */
-				}
-			}
-		}
-
-		/* Tasks of equal priority to the currently running task will share
-		processing time (time slice) if preemption is on, and the application
-		writer has not explicitly turned time slicing off. */
-		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
-		{
-			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
-			{
-				xSwitchRequired = pdTRUE;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
-
-		#if ( configUSE_TICK_HOOK == 1 )
-		{
-			/* Guard against the tick hook being called when the pended tick
-			count is being unwound (when the scheduler is being unlocked). */
-			if( uxPendedTicks == ( UBaseType_t ) 0U )
-			{
-				vApplicationTickHook();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* configUSE_TICK_HOOK */
-	}
-	else
-	{
-		++uxPendedTicks;
-
-		/* The tick hook gets called at regular intervals, even if the
-		scheduler is locked. */
-		#if ( configUSE_TICK_HOOK == 1 )
-		{
-			vApplicationTickHook();
-		}
-		#endif
-	}
-
-	#if ( configUSE_PREEMPTION == 1 )
-	{
-		if( xYieldPending != pdFALSE )
-		{
-			xSwitchRequired = pdTRUE;
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif /* configUSE_PREEMPTION */
-
-	return xSwitchRequired;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-
-	void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
-	{
-	TCB_t *xTCB;
-
-		/* If xTask is NULL then it is the task hook of the calling task that is
-		getting set. */
-		if( xTask == NULL )
-		{
-			xTCB = ( TCB_t * ) pxCurrentTCB;
-		}
-		else
-		{
-			xTCB = xTask;
-		}
-
-		/* Save the hook function in the TCB.  A critical section is required as
-		the value can be accessed from an interrupt. */
-		taskENTER_CRITICAL();
-		{
-			xTCB->pxTaskTag = pxHookFunction;
-		}
-		taskEXIT_CRITICAL();
-	}
-
-#endif /* configUSE_APPLICATION_TASK_TAG */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-
-	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
-	{
-	TCB_t *pxTCB;
-	TaskHookFunction_t xReturn;
-
-		/* If xTask is NULL then set the calling task's hook. */
-		pxTCB = prvGetTCBFromHandle( xTask );
-
-		/* Save the hook function in the TCB.  A critical section is required as
-		the value can be accessed from an interrupt. */
-		taskENTER_CRITICAL();
-		{
-			xReturn = pxTCB->pxTaskTag;
-		}
-		taskEXIT_CRITICAL();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_APPLICATION_TASK_TAG */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-
-	TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
-	{
-	TCB_t *pxTCB;
-	TaskHookFunction_t xReturn;
-	UBaseType_t uxSavedInterruptStatus;
-
-		/* If xTask is NULL then set the calling task's hook. */
-		pxTCB = prvGetTCBFromHandle( xTask );
-
-		/* Save the hook function in the TCB.  A critical section is required as
-		the value can be accessed from an interrupt. */
-		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-		{
-			xReturn = pxTCB->pxTaskTag;
-		}
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-		return xReturn;
-	}
-
-#endif /* configUSE_APPLICATION_TASK_TAG */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-
-	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
-	{
-	TCB_t *xTCB;
-	BaseType_t xReturn;
-
-		/* If xTask is NULL then we are calling our own task hook. */
-		if( xTask == NULL )
-		{
-			xTCB = pxCurrentTCB;
-		}
-		else
-		{
-			xTCB = xTask;
-		}
-
-		if( xTCB->pxTaskTag != NULL )
-		{
-			xReturn = xTCB->pxTaskTag( pvParameter );
-		}
-		else
-		{
-			xReturn = pdFAIL;
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_APPLICATION_TASK_TAG */
-/*-----------------------------------------------------------*/
-
-void vTaskSwitchContext( void )
-{
-	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
-	{
-		/* The scheduler is currently suspended - do not allow a context
-		switch. */
-		xYieldPending = pdTRUE;
-	}
-	else
-	{
-		xYieldPending = pdFALSE;
-		traceTASK_SWITCHED_OUT();
-
-		#if ( configGENERATE_RUN_TIME_STATS == 1 )
-		{
-			#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
-				portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
-			#else
-				ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
-			#endif
-
-			/* Add the amount of time the task has been running to the
-			accumulated time so far.  The time the task started running was
-			stored in ulTaskSwitchedInTime.  Note that there is no overflow
-			protection here so count values are only valid until the timer
-			overflows.  The guard against negative values is to protect
-			against suspect run time stat counter implementations - which
-			are provided by the application, not the kernel. */
-			if( ulTotalRunTime > ulTaskSwitchedInTime )
-			{
-				pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-			ulTaskSwitchedInTime = ulTotalRunTime;
-		}
-		#endif /* configGENERATE_RUN_TIME_STATS */
-
-		/* Check for stack overflow, if configured. */
-		taskCHECK_FOR_STACK_OVERFLOW();
-
-		/* Before the currently running task is switched out, save its errno. */
-		#if( configUSE_POSIX_ERRNO == 1 )
-		{
-			pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
-		}
-		#endif
-
-		/* Select a new task to run using either the generic C or port
-		optimised asm code. */
-		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-		traceTASK_SWITCHED_IN();
-
-		/* After the new task is switched in, update the global errno. */
-		#if( configUSE_POSIX_ERRNO == 1 )
-		{
-			FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
-		}
-		#endif
-
-		#if ( configUSE_NEWLIB_REENTRANT == 1 )
-		{
-			/* Switch Newlib's _impure_ptr variable to point to the _reent
-			structure specific to this task. */
-			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
-		}
-		#endif /* configUSE_NEWLIB_REENTRANT */
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
-{
-	configASSERT( pxEventList );
-
-	/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
-	SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
-
-	/* Place the event list item of the TCB in the appropriate event list.
-	This is placed in the list in priority order so the highest priority task
-	is the first to be woken by the event.  The queue that contains the event
-	list is locked, preventing simultaneous access from interrupts. */
-	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
-
-	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-}
-/*-----------------------------------------------------------*/
-
-void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
-{
-	configASSERT( pxEventList );
-
-	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
-	the event groups implementation. */
-	configASSERT( uxSchedulerSuspended != 0 );
-
-	/* Store the item value in the event list item.  It is safe to access the
-	event list item here as interrupts won't access the event list item of a
-	task that is not in the Blocked state. */
-	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
-
-	/* Place the event list item of the TCB at the end of the appropriate event
-	list.  It is safe to access the event list here because it is part of an
-	event group implementation - and interrupts don't access event groups
-	directly (instead they access them indirectly by pending function calls to
-	the task level). */
-	vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
-
-	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-
-	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
-	{
-		configASSERT( pxEventList );
-
-		/* This function should not be called by application code hence the
-		'Restricted' in its name.  It is not part of the public API.  It is
-		designed for use by kernel code, and has special calling requirements -
-		it should be called with the scheduler suspended. */
-
-
-		/* Place the event list item of the TCB in the appropriate event list.
-		In this case it is assume that this is the only task that is going to
-		be waiting on this event list, so the faster vListInsertEnd() function
-		can be used in place of vListInsert. */
-		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
-
-		/* If the task should block indefinitely then set the block time to a
-		value that will be recognised as an indefinite delay inside the
-		prvAddCurrentTaskToDelayedList() function. */
-		if( xWaitIndefinitely != pdFALSE )
-		{
-			xTicksToWait = portMAX_DELAY;
-		}
-
-		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
-		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
-	}
-
-#endif /* configUSE_TIMERS */
-/*-----------------------------------------------------------*/
-
-BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
-{
-TCB_t *pxUnblockedTCB;
-BaseType_t xReturn;
-
-	/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
-	called from a critical section within an ISR. */
-
-	/* The event list is sorted in priority order, so the first in the list can
-	be removed as it is known to be the highest priority.  Remove the TCB from
-	the delayed list, and add it to the ready list.
-
-	If an event is for a queue that is locked then this function will never
-	get called - the lock count on the queue will get modified instead.  This
-	means exclusive access to the event list is guaranteed here.
-
-	This function assumes that a check has already been made to ensure that
-	pxEventList is not empty. */
-	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-	configASSERT( pxUnblockedTCB );
-	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
-
-	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-	{
-		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
-		prvAddTaskToReadyList( pxUnblockedTCB );
-
-		#if( configUSE_TICKLESS_IDLE != 0 )
-		{
-			/* If a task is blocked on a kernel object then xNextTaskUnblockTime
-			might be set to the blocked task's time out time.  If the task is
-			unblocked for a reason other than a timeout xNextTaskUnblockTime is
-			normally left unchanged, because it is automatically reset to a new
-			value when the tick count equals xNextTaskUnblockTime.  However if
-			tickless idling is used it might be more important to enter sleep mode
-			at the earliest possible time - so reset xNextTaskUnblockTime here to
-			ensure it is updated at the earliest possible time. */
-			prvResetNextTaskUnblockTime();
-		}
-		#endif
-	}
-	else
-	{
-		/* The delayed and ready lists cannot be accessed, so hold this task
-		pending until the scheduler is resumed. */
-		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
-	}
-
-	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
-	{
-		/* Return true if the task removed from the event list has a higher
-		priority than the calling task.  This allows the calling task to know if
-		it should force a context switch now. */
-		xReturn = pdTRUE;
-
-		/* Mark that a yield is pending in case the user is not using the
-		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
-		xYieldPending = pdTRUE;
-	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
-{
-TCB_t *pxUnblockedTCB;
-
-	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
-	the event flags implementation. */
-	configASSERT( uxSchedulerSuspended != pdFALSE );
-
-	/* Store the new item value in the event list. */
-	listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
-
-	/* Remove the event list form the event flag.  Interrupts do not access
-	event flags. */
-	pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-	configASSERT( pxUnblockedTCB );
-	( void ) uxListRemove( pxEventListItem );
-
-	/* Remove the task from the delayed list and add it to the ready list.  The
-	scheduler is suspended so interrupts will not be accessing the ready
-	lists. */
-	( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
-	prvAddTaskToReadyList( pxUnblockedTCB );
-
-	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
-	{
-		/* The unblocked task has a priority above that of the calling task, so
-		a context switch is required.  This function is called with the
-		scheduler suspended so xYieldPending is set so the context switch
-		occurs immediately that the scheduler is resumed (unsuspended). */
-		xYieldPending = pdTRUE;
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
-{
-	configASSERT( pxTimeOut );
-	taskENTER_CRITICAL();
-	{
-		pxTimeOut->xOverflowCount = xNumOfOverflows;
-		pxTimeOut->xTimeOnEntering = xTickCount;
-	}
-	taskEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
-{
-	/* For internal use only as it does not use a critical section. */
-	pxTimeOut->xOverflowCount = xNumOfOverflows;
-	pxTimeOut->xTimeOnEntering = xTickCount;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
-{
-BaseType_t xReturn;
-
-	configASSERT( pxTimeOut );
-	configASSERT( pxTicksToWait );
-
-	taskENTER_CRITICAL();
-	{
-		/* Minor optimisation.  The tick count cannot change in this block. */
-		const TickType_t xConstTickCount = xTickCount;
-		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
-
-		#if( INCLUDE_xTaskAbortDelay == 1 )
-			if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
-			{
-				/* The delay was aborted, which is not the same as a time out,
-				but has the same result. */
-				pxCurrentTCB->ucDelayAborted = pdFALSE;
-				xReturn = pdTRUE;
-			}
-			else
-		#endif
-
-		#if ( INCLUDE_vTaskSuspend == 1 )
-			if( *pxTicksToWait == portMAX_DELAY )
-			{
-				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
-				specified is the maximum block time then the task should block
-				indefinitely, and therefore never time out. */
-				xReturn = pdFALSE;
-			}
-			else
-		#endif
-
-		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
-		{
-			/* The tick count is greater than the time at which
-			vTaskSetTimeout() was called, but has also overflowed since
-			vTaskSetTimeOut() was called.  It must have wrapped all the way
-			around and gone past again. This passed since vTaskSetTimeout()
-			was called. */
-			xReturn = pdTRUE;
-		}
-		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
-		{
-			/* Not a genuine timeout. Adjust parameters for time remaining. */
-			*pxTicksToWait -= xElapsedTime;
-			vTaskInternalSetTimeOutState( pxTimeOut );
-			xReturn = pdFALSE;
-		}
-		else
-		{
-			*pxTicksToWait = 0;
-			xReturn = pdTRUE;
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vTaskMissedYield( void )
-{
-	xYieldPending = pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
-	{
-	UBaseType_t uxReturn;
-	TCB_t const *pxTCB;
-
-		if( xTask != NULL )
-		{
-			pxTCB = xTask;
-			uxReturn = pxTCB->uxTaskNumber;
-		}
-		else
-		{
-			uxReturn = 0U;
-		}
-
-		return uxReturn;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
-	{
-	TCB_t * pxTCB;
-
-		if( xTask != NULL )
-		{
-			pxTCB = xTask;
-			pxTCB->uxTaskNumber = uxHandle;
-		}
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-
-/*
- * -----------------------------------------------------------
- * The Idle task.
- * ----------------------------------------------------------
- *
- * The portTASK_FUNCTION() macro is used to allow port/compiler specific
- * language extensions.  The equivalent prototype for this function is:
- *
- * void prvIdleTask( void *pvParameters );
- *
- */
-static portTASK_FUNCTION( prvIdleTask, pvParameters )
-{
-	/* Stop warnings. */
-	( void ) pvParameters;
-
-	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
-	SCHEDULER IS STARTED. **/
-
-	/* In case a task that has a secure context deletes itself, in which case
-	the idle task is responsible for deleting the task's secure context, if
-	any. */
-	portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
-
-	for( ;; )
-	{
-		/* See if any tasks have deleted themselves - if so then the idle task
-		is responsible for freeing the deleted task's TCB and stack. */
-		prvCheckTasksWaitingTermination();
-
-		#if ( configUSE_PREEMPTION == 0 )
-		{
-			/* If we are not using preemption we keep forcing a task switch to
-			see if any other task has become available.  If we are using
-			preemption we don't need to do this as any task becoming available
-			will automatically get the processor anyway. */
-			taskYIELD();
-		}
-		#endif /* configUSE_PREEMPTION */
-
-		#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
-		{
-			/* When using preemption tasks of equal priority will be
-			timesliced.  If a task that is sharing the idle priority is ready
-			to run then the idle task should yield before the end of the
-			timeslice.
-
-			A critical region is not required here as we are just reading from
-			the list, and an occasional incorrect value will not matter.  If
-			the ready list at the idle priority contains more than one task
-			then a task other than the idle task is ready to execute. */
-			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
-			{
-				taskYIELD();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
-
-		#if ( configUSE_IDLE_HOOK == 1 )
-		{
-			extern void vApplicationIdleHook( void );
-
-			/* Call the user defined function from within the idle task.  This
-			allows the application designer to add background functionality
-			without the overhead of a separate task.
-			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
-			CALL A FUNCTION THAT MIGHT BLOCK. */
-			vApplicationIdleHook();
-		}
-		#endif /* configUSE_IDLE_HOOK */
-
-		/* This conditional compilation should use inequality to 0, not equality
-		to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
-		user defined low power mode	implementations require
-		configUSE_TICKLESS_IDLE to be set to a value other than 1. */
-		#if ( configUSE_TICKLESS_IDLE != 0 )
-		{
-		TickType_t xExpectedIdleTime;
-
-			/* It is not desirable to suspend then resume the scheduler on
-			each iteration of the idle task.  Therefore, a preliminary
-			test of the expected idle time is performed without the
-			scheduler suspended.  The result here is not necessarily
-			valid. */
-			xExpectedIdleTime = prvGetExpectedIdleTime();
-
-			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
-			{
-				vTaskSuspendAll();
-				{
-					/* Now the scheduler is suspended, the expected idle
-					time can be sampled again, and this time its value can
-					be used. */
-					configASSERT( xNextTaskUnblockTime >= xTickCount );
-					xExpectedIdleTime = prvGetExpectedIdleTime();
-
-					/* Define the following macro to set xExpectedIdleTime to 0
-					if the application does not want
-					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
-					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
-
-					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
-					{
-						traceLOW_POWER_IDLE_BEGIN();
-						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
-						traceLOW_POWER_IDLE_END();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				( void ) xTaskResumeAll();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* configUSE_TICKLESS_IDLE */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TICKLESS_IDLE != 0 )
-
-	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
-	{
-	/* The idle task exists in addition to the application tasks. */
-	const UBaseType_t uxNonApplicationTasks = 1;
-	eSleepModeStatus eReturn = eStandardSleep;
-
-		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
-		{
-			/* A task was made ready while the scheduler was suspended. */
-			eReturn = eAbortSleep;
-		}
-		else if( xYieldPending != pdFALSE )
-		{
-			/* A yield was pended while the scheduler was suspended. */
-			eReturn = eAbortSleep;
-		}
-		else
-		{
-			/* If all the tasks are in the suspended list (which might mean they
-			have an infinite block time rather than actually being suspended)
-			then it is safe to turn all clocks off and just wait for external
-			interrupts. */
-			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
-			{
-				eReturn = eNoTasksWaitingTimeout;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-
-		return eReturn;
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-
-	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
-	{
-	TCB_t *pxTCB;
-
-		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
-		{
-			pxTCB = prvGetTCBFromHandle( xTaskToSet );
-			pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
-		}
-	}
-
-#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-
-	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
-	{
-	void *pvReturn = NULL;
-	TCB_t *pxTCB;
-
-		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
-		{
-			pxTCB = prvGetTCBFromHandle( xTaskToQuery );
-			pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
-		}
-		else
-		{
-			pvReturn = NULL;
-		}
-
-		return pvReturn;
-	}
-
-#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
-/*-----------------------------------------------------------*/
-
-#if ( portUSING_MPU_WRAPPERS == 1 )
-
-	void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
-	{
-	TCB_t *pxTCB;
-
-		/* If null is passed in here then we are modifying the MPU settings of
-		the calling task. */
-		pxTCB = prvGetTCBFromHandle( xTaskToModify );
-
-		vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
-	}
-
-#endif /* portUSING_MPU_WRAPPERS */
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseTaskLists( void )
-{
-UBaseType_t uxPriority;
-
-	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
-	{
-		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
-	}
-
-	vListInitialise( &xDelayedTaskList1 );
-	vListInitialise( &xDelayedTaskList2 );
-	vListInitialise( &xPendingReadyList );
-
-	#if ( INCLUDE_vTaskDelete == 1 )
-	{
-		vListInitialise( &xTasksWaitingTermination );
-	}
-	#endif /* INCLUDE_vTaskDelete */
-
-	#if ( INCLUDE_vTaskSuspend == 1 )
-	{
-		vListInitialise( &xSuspendedTaskList );
-	}
-	#endif /* INCLUDE_vTaskSuspend */
-
-	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
-	using list2. */
-	pxDelayedTaskList = &xDelayedTaskList1;
-	pxOverflowDelayedTaskList = &xDelayedTaskList2;
-}
-/*-----------------------------------------------------------*/
-
-static void prvCheckTasksWaitingTermination( void )
-{
-
-	/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
-
-	#if ( INCLUDE_vTaskDelete == 1 )
-	{
-		TCB_t *pxTCB;
-
-		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
-		being called too often in the idle task. */
-		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
-		{
-			taskENTER_CRITICAL();
-			{
-				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-				--uxCurrentNumberOfTasks;
-				--uxDeletedTasksWaitingCleanUp;
-			}
-			taskEXIT_CRITICAL();
-
-			prvDeleteTCB( pxTCB );
-		}
-	}
-	#endif /* INCLUDE_vTaskDelete */
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TRACE_FACILITY == 1 )
-
-	void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
-	{
-	TCB_t *pxTCB;
-
-		/* xTask is NULL then get the state of the calling task. */
-		pxTCB = prvGetTCBFromHandle( xTask );
-
-		pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
-		pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
-		pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
-		pxTaskStatus->pxStackBase = pxTCB->pxStack;
-		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
-
-		#if ( configUSE_MUTEXES == 1 )
-		{
-			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
-		}
-		#else
-		{
-			pxTaskStatus->uxBasePriority = 0;
-		}
-		#endif
-
-		#if ( configGENERATE_RUN_TIME_STATS == 1 )
-		{
-			pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
-		}
-		#else
-		{
-			pxTaskStatus->ulRunTimeCounter = 0;
-		}
-		#endif
-
-		/* Obtaining the task state is a little fiddly, so is only done if the
-		value of eState passed into this function is eInvalid - otherwise the
-		state is just set to whatever is passed in. */
-		if( eState != eInvalid )
-		{
-			if( pxTCB == pxCurrentTCB )
-			{
-				pxTaskStatus->eCurrentState = eRunning;
-			}
-			else
-			{
-				pxTaskStatus->eCurrentState = eState;
-
-				#if ( INCLUDE_vTaskSuspend == 1 )
-				{
-					/* If the task is in the suspended list then there is a
-					chance it is actually just blocked indefinitely - so really
-					it should be reported as being in the Blocked state. */
-					if( eState == eSuspended )
-					{
-						vTaskSuspendAll();
-						{
-							if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-							{
-								pxTaskStatus->eCurrentState = eBlocked;
-							}
-						}
-						( void ) xTaskResumeAll();
-					}
-				}
-				#endif /* INCLUDE_vTaskSuspend */
-			}
-		}
-		else
-		{
-			pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
-		}
-
-		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
-		parameter is provided to allow it to be skipped. */
-		if( xGetFreeStackSpace != pdFALSE )
-		{
-			#if ( portSTACK_GROWTH > 0 )
-			{
-				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
-			}
-			#else
-			{
-				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
-			}
-			#endif
-		}
-		else
-		{
-			pxTaskStatus->usStackHighWaterMark = 0;
-		}
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
-	{
-	configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
-	UBaseType_t uxTask = 0;
-
-		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
-		{
-			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
-			/* Populate an TaskStatus_t structure within the
-			pxTaskStatusArray array for each task that is referenced from
-			pxList.  See the definition of TaskStatus_t in task.h for the
-			meaning of each TaskStatus_t structure member. */
-			do
-			{
-				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
-				uxTask++;
-			} while( pxNextTCB != pxFirstTCB );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return uxTask;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
-
-	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
-	{
-	uint32_t ulCount = 0U;
-
-		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
-		{
-			pucStackByte -= portSTACK_GROWTH;
-			ulCount++;
-		}
-
-		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
-
-		return ( configSTACK_DEPTH_TYPE ) ulCount;
-	}
-
-#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
-
-	/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
-	same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
-	user to determine the return type.  It gets around the problem of the value
-	overflowing on 8-bit types without breaking backward compatibility for
-	applications that expect an 8-bit return type. */
-	configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
-	{
-	TCB_t *pxTCB;
-	uint8_t *pucEndOfStack;
-	configSTACK_DEPTH_TYPE uxReturn;
-
-		/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
-		the same except for their return type.  Using configSTACK_DEPTH_TYPE
-		allows the user to determine the return type.  It gets around the
-		problem of the value overflowing on 8-bit types without breaking
-		backward compatibility for applications that expect an 8-bit return
-		type. */
-
-		pxTCB = prvGetTCBFromHandle( xTask );
-
-		#if portSTACK_GROWTH < 0
-		{
-			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
-		}
-		#else
-		{
-			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
-		}
-		#endif
-
-		uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
-
-		return uxReturn;
-	}
-
-#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
-
-	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
-	{
-	TCB_t *pxTCB;
-	uint8_t *pucEndOfStack;
-	UBaseType_t uxReturn;
-
-		pxTCB = prvGetTCBFromHandle( xTask );
-
-		#if portSTACK_GROWTH < 0
-		{
-			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
-		}
-		#else
-		{
-			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
-		}
-		#endif
-
-		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
-
-		return uxReturn;
-	}
-
-#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
-/*-----------------------------------------------------------*/
-
-#if (INCLUDE_pxTaskGetStackStart == 1)
-	uint8_t* pxTaskGetStackStart( TaskHandle_t xTask)
-	{
-		TCB_t *pxTCB;
-		UBaseType_t uxReturn;
-		(void)uxReturn;
-
-		pxTCB = prvGetTCBFromHandle( xTask );
-		return ( uint8_t * ) pxTCB->pxStack;
-	}
-
-#endif /* INCLUDE_pxTaskGetStackStart */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelete == 1 )
-
-	static void prvDeleteTCB( TCB_t *pxTCB )
-	{
-		/* This call is required specifically for the TriCore port.  It must be
-		above the vPortFree() calls.  The call is also used by ports/demos that
-		want to allocate and clean RAM statically. */
-		portCLEAN_UP_TCB( pxTCB );
-
-		/* Free up the memory allocated by the scheduler for the task.  It is up
-		to the task to free any memory allocated at the application level. */
-		#if ( configUSE_NEWLIB_REENTRANT == 1 )
-		{
-			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
-		}
-		#endif /* configUSE_NEWLIB_REENTRANT */
-
-		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
-		{
-			/* The task can only have been allocated dynamically - free both
-			the stack and TCB. */
-			vPortFree( pxTCB->pxStack );
-			vPortFree( pxTCB );
-		}
-		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
-		{
-			/* The task could have been allocated statically or dynamically, so
-			check what was statically allocated before trying to free the
-			memory. */
-			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
-			{
-				/* Both the stack and TCB were allocated dynamically, so both
-				must be freed. */
-				vPortFree( pxTCB->pxStack );
-				vPortFree( pxTCB );
-			}
-			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
-			{
-				/* Only the stack was statically allocated, so the TCB is the
-				only memory that must be freed. */
-				vPortFree( pxTCB );
-			}
-			else
-			{
-				/* Neither the stack nor the TCB were allocated dynamically, so
-				nothing needs to be freed. */
-				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-	}
-
-#endif /* INCLUDE_vTaskDelete */
-/*-----------------------------------------------------------*/
-
-static void prvResetNextTaskUnblockTime( void )
-{
-TCB_t *pxTCB;
-
-	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
-	{
-		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
-		the maximum possible value so it is	extremely unlikely that the
-		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
-		there is an item in the delayed list. */
-		xNextTaskUnblockTime = portMAX_DELAY;
-	}
-	else
-	{
-		/* The new current delayed list is not empty, get the value of
-		the item at the head of the delayed list.  This is the time at
-		which the task at the head of the delayed list should be removed
-		from the Blocked state. */
-		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
-
-	TaskHandle_t xTaskGetCurrentTaskHandle( void )
-	{
-	TaskHandle_t xReturn;
-
-		/* A critical section is not required as this is not called from
-		an interrupt and the current TCB will always be the same for any
-		individual execution thread. */
-		xReturn = pxCurrentTCB;
-
-		return xReturn;
-	}
-
-#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-
-	BaseType_t xTaskGetSchedulerState( void )
-	{
-	BaseType_t xReturn;
-
-		if( xSchedulerRunning == pdFALSE )
-		{
-			xReturn = taskSCHEDULER_NOT_STARTED;
-		}
-		else
-		{
-			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-			{
-				xReturn = taskSCHEDULER_RUNNING;
-			}
-			else
-			{
-				xReturn = taskSCHEDULER_SUSPENDED;
-			}
-		}
-
-		return xReturn;
-	}
-
-#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
-	{
-	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
-	BaseType_t xReturn = pdFALSE;
-
-		/* If the mutex was given back by an interrupt while the queue was
-		locked then the mutex holder might now be NULL.  _RB_ Is this still
-		needed as interrupts can no longer use mutexes? */
-		if( pxMutexHolder != NULL )
-		{
-			/* If the holder of the mutex has a priority below the priority of
-			the task attempting to obtain the mutex then it will temporarily
-			inherit the priority of the task attempting to obtain the mutex. */
-			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
-			{
-				/* Adjust the mutex holder state to account for its new
-				priority.  Only reset the event list item value if the value is
-				not being used for anything else. */
-				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
-				{
-					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* If the task being modified is in the ready state it will need
-				to be moved into a new list. */
-				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
-				{
-					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-					{
-						taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* Inherit the priority before being moved into the new list. */
-					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
-					prvReaddTaskToReadyList( pxMutexHolderTCB );
-				}
-				else
-				{
-					/* Just inherit the priority. */
-					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
-				}
-
-				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
-
-				/* Inheritance occurred. */
-				xReturn = pdTRUE;
-			}
-			else
-			{
-				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
-				{
-					/* The base priority of the mutex holder is lower than the
-					priority of the task attempting to take the mutex, but the
-					current priority of the mutex holder is not lower than the
-					priority of the task attempting to take the mutex.
-					Therefore the mutex holder must have already inherited a
-					priority, but inheritance would have occurred if that had
-					not been the case. */
-					xReturn = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
-	{
-	TCB_t * const pxTCB = pxMutexHolder;
-	BaseType_t xReturn = pdFALSE;
-
-		if( pxMutexHolder != NULL )
-		{
-			/* A task can only have an inherited priority if it holds the mutex.
-			If the mutex is held by a task then it cannot be given from an
-			interrupt, and if a mutex is given by the holding task then it must
-			be the running state task. */
-			configASSERT( pxTCB == pxCurrentTCB );
-			configASSERT( pxTCB->uxMutexesHeld );
-			( pxTCB->uxMutexesHeld )--;
-
-			/* Has the holder of the mutex inherited the priority of another
-			task? */
-			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
-			{
-				/* Only disinherit if no other mutexes are held. */
-				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
-				{
-					/* A task can only have an inherited priority if it holds
-					the mutex.  If the mutex is held by a task then it cannot be
-					given from an interrupt, and if a mutex is given by the
-					holding task then it must be the running state task.  Remove
-					the holding task from the ready list. */
-					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-					{
-						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* Disinherit the priority before adding the task into the
-					new	ready list. */
-					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
-					pxTCB->uxPriority = pxTCB->uxBasePriority;
-
-					/* Reset the event list item value.  It cannot be in use for
-					any other purpose if this task is running, and it must be
-					running to give back the mutex. */
-					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-					prvReaddTaskToReadyList( pxTCB );
-
-					/* Return true to indicate that a context switch is required.
-					This is only actually required in the corner case whereby
-					multiple mutexes were held and the mutexes were given back
-					in an order different to that in which they were taken.
-					If a context switch did not occur when the first mutex was
-					returned, even if a task was waiting on it, then a context
-					switch should occur when the last mutex is returned whether
-					a task is waiting on it or not. */
-					xReturn = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
-	{
-	TCB_t * const pxTCB = pxMutexHolder;
-	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
-	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
-
-		if( pxMutexHolder != NULL )
-		{
-			/* If pxMutexHolder is not NULL then the holder must hold at least
-			one mutex. */
-			configASSERT( pxTCB->uxMutexesHeld );
-
-			/* Determine the priority to which the priority of the task that
-			holds the mutex should be set.  This will be the greater of the
-			holding task's base priority and the priority of the highest
-			priority task that is waiting to obtain the mutex. */
-			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
-			{
-				uxPriorityToUse = uxHighestPriorityWaitingTask;
-			}
-			else
-			{
-				uxPriorityToUse = pxTCB->uxBasePriority;
-			}
-
-			/* Does the priority need to change? */
-			if( pxTCB->uxPriority != uxPriorityToUse )
-			{
-				/* Only disinherit if no other mutexes are held.  This is a
-				simplification in the priority inheritance implementation.  If
-				the task that holds the mutex is also holding other mutexes then
-				the other mutexes may have caused the priority inheritance. */
-				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
-				{
-					/* If a task has timed out because it already holds the
-					mutex it was trying to obtain then it cannot of inherited
-					its own priority. */
-					configASSERT( pxTCB != pxCurrentTCB );
-
-					/* Disinherit the priority, remembering the previous
-					priority to facilitate determining the subject task's
-					state. */
-					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
-					uxPriorityUsedOnEntry = pxTCB->uxPriority;
-					pxTCB->uxPriority = uxPriorityToUse;
-
-					/* Only reset the event list item value if the value is not
-					being used for anything else. */
-					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
-					{
-						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* If the running task is not the task that holds the mutex
-					then the task that holds the mutex could be in either the
-					Ready, Blocked or Suspended states.  Only remove the task
-					from its current state list if it is in the Ready state as
-					the task's priority is going to change and there is one
-					Ready list per priority. */
-					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
-					{
-						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-						{
-							taskRESET_READY_PRIORITY( pxTCB->uxPriority );
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-
-						prvAddTaskToReadyList( pxTCB );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( portCRITICAL_NESTING_IN_TCB == 1 )
-
-	void vTaskEnterCritical( void )
-	{
-		portDISABLE_INTERRUPTS();
-
-		if( xSchedulerRunning != pdFALSE )
-		{
-			( pxCurrentTCB->uxCriticalNesting )++;
-
-			/* This is not the interrupt safe version of the enter critical
-			function so	assert() if it is being called from an interrupt
-			context.  Only API functions that end in "FromISR" can be used in an
-			interrupt.  Only assert if the critical nesting count is 1 to
-			protect against recursive calls if the assert function also uses a
-			critical section. */
-			if( pxCurrentTCB->uxCriticalNesting == 1 )
-			{
-				portASSERT_IF_IN_ISR();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* portCRITICAL_NESTING_IN_TCB */
-/*-----------------------------------------------------------*/
-
-#if ( portCRITICAL_NESTING_IN_TCB == 1 )
-
-	void vTaskExitCritical( void )
-	{
-		if( xSchedulerRunning != pdFALSE )
-		{
-			if( pxCurrentTCB->uxCriticalNesting > 0U )
-			{
-				( pxCurrentTCB->uxCriticalNesting )--;
-
-				if( pxCurrentTCB->uxCriticalNesting == 0U )
-				{
-					portENABLE_INTERRUPTS();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* portCRITICAL_NESTING_IN_TCB */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
-
-	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
-	{
-	size_t x;
-
-		/* Start by copying the entire string. */
-		strcpy( pcBuffer, pcTaskName );
-
-		/* Pad the end of the string with spaces to ensure columns line up when
-		printed out. */
-		for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
-		{
-			pcBuffer[ x ] = ' ';
-		}
-
-		/* Terminate. */
-		pcBuffer[ x ] = ( char ) 0x00;
-
-		/* Return the new end of string. */
-		return &( pcBuffer[ x ] );
-	}
-
-#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-	void vTaskList( char * pcWriteBuffer )
-	{
-	TaskStatus_t *pxTaskStatusArray;
-	UBaseType_t uxArraySize, x;
-	char cStatus;
-
-		/*
-		 * PLEASE NOTE:
-		 *
-		 * This function is provided for convenience only, and is used by many
-		 * of the demo applications.  Do not consider it to be part of the
-		 * scheduler.
-		 *
-		 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
-		 * uxTaskGetSystemState() output into a human readable table that
-		 * displays task names, states and stack usage.
-		 *
-		 * vTaskList() has a dependency on the sprintf() C library function that
-		 * might bloat the code size, use a lot of stack, and provide different
-		 * results on different platforms.  An alternative, tiny, third party,
-		 * and limited functionality implementation of sprintf() is provided in
-		 * many of the FreeRTOS/Demo sub-directories in a file called
-		 * printf-stdarg.c (note printf-stdarg.c does not provide a full
-		 * snprintf() implementation!).
-		 *
-		 * It is recommended that production systems call uxTaskGetSystemState()
-		 * directly to get access to raw stats data, rather than indirectly
-		 * through a call to vTaskList().
-		 */
-
-
-		/* Make sure the write buffer does not contain a string. */
-		*pcWriteBuffer = ( char ) 0x00;
-
-		/* Take a snapshot of the number of tasks in case it changes while this
-		function is executing. */
-		uxArraySize = uxCurrentNumberOfTasks;
-
-		/* Allocate an array index for each task.  NOTE!  if
-		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
-		equate to NULL. */
-		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
-
-		if( pxTaskStatusArray != NULL )
-		{
-			/* Generate the (binary) data. */
-			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
-
-			/* Create a human readable table from the binary data. */
-			for( x = 0; x < uxArraySize; x++ )
-			{
-				switch( pxTaskStatusArray[ x ].eCurrentState )
-				{
-					case eRunning:		cStatus = tskRUNNING_CHAR;
-										break;
-
-					case eReady:		cStatus = tskREADY_CHAR;
-										break;
-
-					case eBlocked:		cStatus = tskBLOCKED_CHAR;
-										break;
-
-					case eSuspended:	cStatus = tskSUSPENDED_CHAR;
-										break;
-
-					case eDeleted:		cStatus = tskDELETED_CHAR;
-										break;
-
-					case eInvalid:		/* Fall through. */
-					default:			/* Should not get here, but it is included
-										to prevent static checking errors. */
-										cStatus = ( char ) 0x00;
-										break;
-				}
-
-				/* Write the task name to the string, padding with spaces so it
-				can be printed in tabular form more easily. */
-				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
-
-				/* Write the rest of the string. */
-				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
-				pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
-			}
-
-			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
-			is 0 then vPortFree() will be #defined to nothing. */
-			vPortFree( pxTaskStatusArray );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*----------------------------------------------------------*/
-
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-	void vTaskGetRunTimeStats( char *pcWriteBuffer )
-	{
-	TaskStatus_t *pxTaskStatusArray;
-	UBaseType_t uxArraySize, x;
-	uint32_t ulTotalTime, ulStatsAsPercentage;
-
-		#if( configUSE_TRACE_FACILITY != 1 )
-		{
-			#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
-		}
-		#endif
-
-		/*
-		 * PLEASE NOTE:
-		 *
-		 * This function is provided for convenience only, and is used by many
-		 * of the demo applications.  Do not consider it to be part of the
-		 * scheduler.
-		 *
-		 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
-		 * of the uxTaskGetSystemState() output into a human readable table that
-		 * displays the amount of time each task has spent in the Running state
-		 * in both absolute and percentage terms.
-		 *
-		 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
-		 * function that might bloat the code size, use a lot of stack, and
-		 * provide different results on different platforms.  An alternative,
-		 * tiny, third party, and limited functionality implementation of
-		 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
-		 * a file called printf-stdarg.c (note printf-stdarg.c does not provide
-		 * a full snprintf() implementation!).
-		 *
-		 * It is recommended that production systems call uxTaskGetSystemState()
-		 * directly to get access to raw stats data, rather than indirectly
-		 * through a call to vTaskGetRunTimeStats().
-		 */
-
-		/* Make sure the write buffer does not contain a string. */
-		*pcWriteBuffer = ( char ) 0x00;
-
-		/* Take a snapshot of the number of tasks in case it changes while this
-		function is executing. */
-		uxArraySize = uxCurrentNumberOfTasks;
-
-		/* Allocate an array index for each task.  NOTE!  If
-		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
-		equate to NULL. */
-		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
-
-		if( pxTaskStatusArray != NULL )
-		{
-			/* Generate the (binary) data. */
-			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
-
-			/* For percentage calculations. */
-			ulTotalTime /= 100UL;
-
-			/* Avoid divide by zero errors. */
-			if( ulTotalTime > 0UL )
-			{
-				/* Create a human readable table from the binary data. */
-				for( x = 0; x < uxArraySize; x++ )
-				{
-					/* What percentage of the total run time has the task used?
-					This will always be rounded down to the nearest integer.
-					ulTotalRunTimeDiv100 has already been divided by 100. */
-					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
-
-					/* Write the task name to the string, padding with
-					spaces so it can be printed in tabular form more
-					easily. */
-					pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
-
-					if( ulStatsAsPercentage > 0UL )
-					{
-						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
-						{
-							sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
-						}
-						#else
-						{
-							/* sizeof( int ) == sizeof( long ) so a smaller
-							printf() library can be used. */
-							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
-						}
-						#endif
-					}
-					else
-					{
-						/* If the percentage is zero here then the task has
-						consumed less than 1% of the total run time. */
-						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
-						{
-							sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
-						}
-						#else
-						{
-							/* sizeof( int ) == sizeof( long ) so a smaller
-							printf() library can be used. */
-							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
-						}
-						#endif
-					}
-
-					pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
-			is 0 then vPortFree() will be #defined to nothing. */
-			vPortFree( pxTaskStatusArray );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-TickType_t uxTaskResetEventItemValue( void )
-{
-TickType_t uxReturn;
-
-	uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
-
-	/* Reset the event list item to its normal value - so it can be used with
-	queues and semaphores. */
-	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
-	return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
-	{
-		/* If xSemaphoreCreateMutex() is called before any tasks have been created
-		then pxCurrentTCB will be NULL. */
-		if( pxCurrentTCB != NULL )
-		{
-			( pxCurrentTCB->uxMutexesHeld )++;
-		}
-
-		return pxCurrentTCB;
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-
-	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
-	{
-	uint32_t ulReturn;
-
-		taskENTER_CRITICAL();
-		{
-			/* Only block if the notification count is not already non-zero. */
-			if( pxCurrentTCB->ulNotifiedValue == 0UL )
-			{
-				/* Mark this task as waiting for a notification. */
-				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
-
-				if( xTicksToWait > ( TickType_t ) 0 )
-				{
-					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-					traceTASK_NOTIFY_TAKE_BLOCK();
-
-					/* All ports are written to allow a yield in a critical
-					section (some will yield immediately, others wait until the
-					critical section exits) - but it is not something that
-					application code should ever do. */
-					portYIELD_WITHIN_API();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		taskENTER_CRITICAL();
-		{
-			traceTASK_NOTIFY_TAKE();
-			ulReturn = pxCurrentTCB->ulNotifiedValue;
-
-			if( ulReturn != 0UL )
-			{
-				if( xClearCountOnExit != pdFALSE )
-				{
-					pxCurrentTCB->ulNotifiedValue = 0UL;
-				}
-				else
-				{
-					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
-		}
-		taskEXIT_CRITICAL();
-
-		return ulReturn;
-	}
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-
-	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
-	{
-	BaseType_t xReturn;
-
-		taskENTER_CRITICAL();
-		{
-			/* Only block if a notification is not already pending. */
-			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
-			{
-				/* Clear bits in the task's notification value as bits may get
-				set	by the notifying task or interrupt.  This can be used to
-				clear the value to zero. */
-				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
-
-				/* Mark this task as waiting for a notification. */
-				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
-
-				if( xTicksToWait > ( TickType_t ) 0 )
-				{
-					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-					traceTASK_NOTIFY_WAIT_BLOCK();
-
-					/* All ports are written to allow a yield in a critical
-					section (some will yield immediately, others wait until the
-					critical section exits) - but it is not something that
-					application code should ever do. */
-					portYIELD_WITHIN_API();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		taskENTER_CRITICAL();
-		{
-			traceTASK_NOTIFY_WAIT();
-
-			if( pulNotificationValue != NULL )
-			{
-				/* Output the current notification value, which may or may not
-				have changed. */
-				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
-			}
-
-			/* If ucNotifyValue is set then either the task never entered the
-			blocked state (because a notification was already pending) or the
-			task unblocked because of a notification.  Otherwise the task
-			unblocked because of a timeout. */
-			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
-			{
-				/* A notification was not received. */
-				xReturn = pdFALSE;
-			}
-			else
-			{
-				/* A notification was already pending or a notification was
-				received while the task was waiting. */
-				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
-				xReturn = pdTRUE;
-			}
-
-			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
-		}
-		taskEXIT_CRITICAL();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-
-	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
-	{
-	TCB_t * pxTCB;
-	BaseType_t xReturn = pdPASS;
-	uint8_t ucOriginalNotifyState;
-
-		configASSERT( xTaskToNotify );
-		pxTCB = xTaskToNotify;
-
-		taskENTER_CRITICAL();
-		{
-			if( pulPreviousNotificationValue != NULL )
-			{
-				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
-			}
-
-			ucOriginalNotifyState = pxTCB->ucNotifyState;
-
-			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
-
-			switch( eAction )
-			{
-				case eSetBits	:
-					pxTCB->ulNotifiedValue |= ulValue;
-					break;
-
-				case eIncrement	:
-					( pxTCB->ulNotifiedValue )++;
-					break;
-
-				case eSetValueWithOverwrite	:
-					pxTCB->ulNotifiedValue = ulValue;
-					break;
-
-				case eSetValueWithoutOverwrite :
-					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
-					{
-						pxTCB->ulNotifiedValue = ulValue;
-					}
-					else
-					{
-						/* The value could not be written to the task. */
-						xReturn = pdFAIL;
-					}
-					break;
-
-				case eNoAction:
-					/* The task is being notified without its notify value being
-					updated. */
-					break;
-
-				default:
-					/* Should not get here if all enums are handled.
-					Artificially force an assert by testing a value the
-					compiler can't assume is const. */
-					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
-
-					break;
-			}
-
-			traceTASK_NOTIFY();
-
-			/* If the task is in the blocked state specifically to wait for a
-			notification then unblock it now. */
-			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
-			{
-				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-				prvAddTaskToReadyList( pxTCB );
-
-				/* The task should not have been on an event list. */
-				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
-
-				#if( configUSE_TICKLESS_IDLE != 0 )
-				{
-					/* If a task is blocked waiting for a notification then
-					xNextTaskUnblockTime might be set to the blocked task's time
-					out time.  If the task is unblocked for a reason other than
-					a timeout xNextTaskUnblockTime is normally left unchanged,
-					because it will automatically get reset to a new value when
-					the tick count equals xNextTaskUnblockTime.  However if
-					tickless idling is used it might be more important to enter
-					sleep mode at the earliest possible time - so reset
-					xNextTaskUnblockTime here to ensure it is updated at the
-					earliest possible time. */
-					prvResetNextTaskUnblockTime();
-				}
-				#endif
-
-				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-				{
-					/* The notified task has a priority above the currently
-					executing task so a yield is required. */
-					taskYIELD_IF_USING_PREEMPTION();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-
-	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
-	{
-	TCB_t * pxTCB;
-	uint8_t ucOriginalNotifyState;
-	BaseType_t xReturn = pdPASS;
-	UBaseType_t uxSavedInterruptStatus;
-
-		configASSERT( xTaskToNotify );
-
-		/* RTOS ports that support interrupt nesting have the concept of a
-		maximum	system call (or maximum API call) interrupt priority.
-		Interrupts that are	above the maximum system call priority are keep
-		permanently enabled, even when the RTOS kernel is in a critical section,
-		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
-		is defined in FreeRTOSConfig.h then
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-		failure if a FreeRTOS API function is called from an interrupt that has
-		been assigned a priority above the configured maximum system call
-		priority.  Only FreeRTOS functions that end in FromISR can be called
-		from interrupts	that have been assigned a priority at or (logically)
-		below the maximum system call interrupt priority.  FreeRTOS maintains a
-		separate interrupt safe API to ensure interrupt entry is as fast and as
-		simple as possible.  More information (albeit Cortex-M specific) is
-		provided on the following link:
-		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-		pxTCB = xTaskToNotify;
-
-		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-		{
-			if( pulPreviousNotificationValue != NULL )
-			{
-				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
-			}
-
-			ucOriginalNotifyState = pxTCB->ucNotifyState;
-			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
-
-			switch( eAction )
-			{
-				case eSetBits	:
-					pxTCB->ulNotifiedValue |= ulValue;
-					break;
-
-				case eIncrement	:
-					( pxTCB->ulNotifiedValue )++;
-					break;
-
-				case eSetValueWithOverwrite	:
-					pxTCB->ulNotifiedValue = ulValue;
-					break;
-
-				case eSetValueWithoutOverwrite :
-					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
-					{
-						pxTCB->ulNotifiedValue = ulValue;
-					}
-					else
-					{
-						/* The value could not be written to the task. */
-						xReturn = pdFAIL;
-					}
-					break;
-
-				case eNoAction :
-					/* The task is being notified without its notify value being
-					updated. */
-					break;
-
-				default:
-					/* Should not get here if all enums are handled.
-					Artificially force an assert by testing a value the
-					compiler can't assume is const. */
-					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
-					break;
-			}
-
-			traceTASK_NOTIFY_FROM_ISR();
-
-			/* If the task is in the blocked state specifically to wait for a
-			notification then unblock it now. */
-			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
-			{
-				/* The task should not have been on an event list. */
-				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
-
-				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-				{
-					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-					prvAddTaskToReadyList( pxTCB );
-				}
-				else
-				{
-					/* The delayed and ready lists cannot be accessed, so hold
-					this task pending until the scheduler is resumed. */
-					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
-				}
-
-				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-				{
-					/* The notified task has a priority above the currently
-					executing task so a yield is required. */
-					if( pxHigherPriorityTaskWoken != NULL )
-					{
-						*pxHigherPriorityTaskWoken = pdTRUE;
-					}
-
-					/* Mark that a yield is pending in case the user is not
-					using the "xHigherPriorityTaskWoken" parameter to an ISR
-					safe FreeRTOS function. */
-					xYieldPending = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-		return xReturn;
-	}
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-
-	void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
-	{
-	TCB_t * pxTCB;
-	uint8_t ucOriginalNotifyState;
-	UBaseType_t uxSavedInterruptStatus;
-
-		configASSERT( xTaskToNotify );
-
-		/* RTOS ports that support interrupt nesting have the concept of a
-		maximum	system call (or maximum API call) interrupt priority.
-		Interrupts that are	above the maximum system call priority are keep
-		permanently enabled, even when the RTOS kernel is in a critical section,
-		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
-		is defined in FreeRTOSConfig.h then
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-		failure if a FreeRTOS API function is called from an interrupt that has
-		been assigned a priority above the configured maximum system call
-		priority.  Only FreeRTOS functions that end in FromISR can be called
-		from interrupts	that have been assigned a priority at or (logically)
-		below the maximum system call interrupt priority.  FreeRTOS maintains a
-		separate interrupt safe API to ensure interrupt entry is as fast and as
-		simple as possible.  More information (albeit Cortex-M specific) is
-		provided on the following link:
-		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-		pxTCB = xTaskToNotify;
-
-		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-		{
-			ucOriginalNotifyState = pxTCB->ucNotifyState;
-			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
-
-			/* 'Giving' is equivalent to incrementing a count in a counting
-			semaphore. */
-			( pxTCB->ulNotifiedValue )++;
-
-			traceTASK_NOTIFY_GIVE_FROM_ISR();
-
-			/* If the task is in the blocked state specifically to wait for a
-			notification then unblock it now. */
-			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
-			{
-				/* The task should not have been on an event list. */
-				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
-
-				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-				{
-					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-					prvAddTaskToReadyList( pxTCB );
-				}
-				else
-				{
-					/* The delayed and ready lists cannot be accessed, so hold
-					this task pending until the scheduler is resumed. */
-					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
-				}
-
-				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-				{
-					/* The notified task has a priority above the currently
-					executing task so a yield is required. */
-					if( pxHigherPriorityTaskWoken != NULL )
-					{
-						*pxHigherPriorityTaskWoken = pdTRUE;
-					}
-
-					/* Mark that a yield is pending in case the user is not
-					using the "xHigherPriorityTaskWoken" parameter in an ISR
-					safe FreeRTOS function. */
-					xYieldPending = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-	}
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-
-	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
-	{
-	TCB_t *pxTCB;
-	BaseType_t xReturn;
-
-		/* If null is passed in here then it is the calling task that is having
-		its notification state cleared. */
-		pxTCB = prvGetTCBFromHandle( xTask );
-
-		taskENTER_CRITICAL();
-		{
-			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
-			{
-				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
-				xReturn = pdPASS;
-			}
-			else
-			{
-				xReturn = pdFAIL;
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
-	TickType_t xTaskGetIdleRunTimeCounter( void )
-	{
-		return xIdleTaskHandle->ulRunTimeCounter;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
-{
-TickType_t xTimeToWake;
-const TickType_t xConstTickCount = xTickCount;
-
-	#if( INCLUDE_xTaskAbortDelay == 1 )
-	{
-		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
-		reset to pdFALSE so it can be detected as having been set to pdTRUE
-		when the task leaves the Blocked state. */
-		pxCurrentTCB->ucDelayAborted = pdFALSE;
-	}
-	#endif
-
-	/* Remove the task from the ready list before adding it to the blocked list
-	as the same list item is used for both lists. */
-	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-	{
-		/* The current task must be in a ready list, so there is no need to
-		check, and the port reset macro can be called directly. */
-		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	#if ( INCLUDE_vTaskSuspend == 1 )
-	{
-		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
-		{
-			/* Add the task to the suspended task list instead of a delayed task
-			list to ensure it is not woken by a timing event.  It will block
-			indefinitely. */
-			traceMOVED_TASK_TO_SUSPENDED_LIST(pxCurrentTCB);
-			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
-		}
-		else
-		{
-			/* Calculate the time at which the task should be woken if the event
-			does not occur.  This may overflow but this doesn't matter, the
-			kernel will manage it correctly. */
-			xTimeToWake = xConstTickCount + xTicksToWait;
-
-			/* The list item will be inserted in wake time order. */
-			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
-
-			if( xTimeToWake < xConstTickCount )
-			{
-				/* Wake time has overflowed.  Place this item in the overflow
-				list. */
-				traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST();
-				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
-			}
-			else
-			{
-				/* The wake time has not overflowed, so the current block list
-				is used. */
-				traceMOVED_TASK_TO_DELAYED_LIST();
-				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
-
-				/* If the task entering the blocked state was placed at the
-				head of the list of blocked tasks then xNextTaskUnblockTime
-				needs to be updated too. */
-				if( xTimeToWake < xNextTaskUnblockTime )
-				{
-					xNextTaskUnblockTime = xTimeToWake;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-	}
-	#else /* INCLUDE_vTaskSuspend */
-	{
-		/* Calculate the time at which the task should be woken if the event
-		does not occur.  This may overflow but this doesn't matter, the kernel
-		will manage it correctly. */
-		xTimeToWake = xConstTickCount + xTicksToWait;
-
-		/* The list item will be inserted in wake time order. */
-		listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
-
-		if( xTimeToWake < xConstTickCount )
-		{
-			/* Wake time has overflowed.  Place this item in the overflow list. */
-			traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST();
-			vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
-		}
-		else
-		{
-			/* The wake time has not overflowed, so the current block list is used. */
-			traceMOVED_TASK_TO_DELAYED_LIST();
-			vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
-
-			/* If the task entering the blocked state was placed at the head of the
-			list of blocked tasks then xNextTaskUnblockTime needs to be updated
-			too. */
-			if( xTimeToWake < xNextTaskUnblockTime )
-			{
-				xNextTaskUnblockTime = xTimeToWake;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-
-		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
-		( void ) xCanBlockIndefinitely;
-	}
-	#endif /* INCLUDE_vTaskSuspend */
-}
-
-/* Code below here allows additional code to be inserted into this source file,
-especially where access to file scope functions and data is needed (for example
-when performing module tests). */
-
-#ifdef FREERTOS_MODULE_TEST
-	#include "tasks_test_access_functions.h"
-#endif
-
-
-#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
-
-	#include "freertos_tasks_c_additions.h"
-
-	#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
-		static void freertos_tasks_c_additions_init( void )
-		{
-			FREERTOS_TASKS_C_ADDITIONS_INIT();
-		}
-	#endif
-
-#endif
-
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/timers.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/timers.c
deleted file mode 100644
index 80c8d9b..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/freertos_kernel/timers.c
+++ /dev/null
@@ -1,1102 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-#include "timers.h"
-
-#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
-	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
-#endif
-
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
-because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
-for the header files above, but not in this file, in order to generate the
-correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
-
-
-/* This entire source file will be skipped if the application is not configured
-to include software timer functionality.  This #if is closed at the very bottom
-of this file.  If you want to include software timer functionality then ensure
-configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
-#if ( configUSE_TIMERS == 1 )
-
-/* Misc definitions. */
-#define tmrNO_DELAY		( TickType_t ) 0U
-
-/* The name assigned to the timer service task.  This can be overridden by
-defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
-#ifndef configTIMER_SERVICE_TASK_NAME
-	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
-#endif
-
-/* Bit definitions used in the ucStatus member of a timer structure. */
-#define tmrSTATUS_IS_ACTIVE					( ( uint8_t ) 0x01 )
-#define tmrSTATUS_IS_STATICALLY_ALLOCATED	( ( uint8_t ) 0x02 )
-#define tmrSTATUS_IS_AUTORELOAD				( ( uint8_t ) 0x04 )
-
-/* The definition of the timers themselves. */
-typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
-{
-	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
-	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
-	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
-	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
-	#if( configUSE_TRACE_FACILITY == 1 )
-		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
-	#endif
-	uint8_t 				ucStatus;			/*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
-} xTIMER;
-
-/* The old xTIMER name is maintained above then typedefed to the new Timer_t
-name below to enable the use of older kernel aware debuggers. */
-typedef xTIMER Timer_t;
-
-/* The definition of messages that can be sent and received on the timer queue.
-Two types of message can be queued - messages that manipulate a software timer,
-and messages that request the execution of a non-timer related callback.  The
-two message types are defined in two separate structures, xTimerParametersType
-and xCallbackParametersType respectively. */
-typedef struct tmrTimerParameters
-{
-	TickType_t			xMessageValue;		/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
-	Timer_t *			pxTimer;			/*<< The timer to which the command will be applied. */
-} TimerParameter_t;
-
-
-typedef struct tmrCallbackParameters
-{
-	PendedFunction_t	pxCallbackFunction;	/* << The callback function to execute. */
-	void *pvParameter1;						/* << The value that will be used as the callback functions first parameter. */
-	uint32_t ulParameter2;					/* << The value that will be used as the callback functions second parameter. */
-} CallbackParameters_t;
-
-/* The structure that contains the two message types, along with an identifier
-that is used to determine which message type is valid. */
-typedef struct tmrTimerQueueMessage
-{
-	BaseType_t			xMessageID;			/*<< The command being sent to the timer service task. */
-	union
-	{
-		TimerParameter_t xTimerParameters;
-
-		/* Don't include xCallbackParameters if it is not going to be used as
-		it makes the structure (and therefore the timer queue) larger. */
-		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
-			CallbackParameters_t xCallbackParameters;
-		#endif /* INCLUDE_xTimerPendFunctionCall */
-	} u;
-} DaemonTaskMessage_t;
-
-/*lint -save -e956 A manual analysis and inspection has been used to determine
-which static variables must be declared volatile. */
-
-/* The list in which active timers are stored.  Timers are referenced in expire
-time order, with the nearest expiry time at the front of the list.  Only the
-timer service task is allowed to access these lists.
-xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
-breaks some kernel aware debuggers, and debuggers that reply on removing the
-static qualifier. */
-PRIVILEGED_DATA static List_t xActiveTimerList1;
-PRIVILEGED_DATA static List_t xActiveTimerList2;
-PRIVILEGED_DATA static List_t *pxCurrentTimerList;
-PRIVILEGED_DATA static List_t *pxOverflowTimerList;
-
-/* A queue that is used to send commands to the timer service task. */
-PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
-PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
-
-/*lint -restore */
-
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-	/* If static allocation is supported then the application must provide the
-	following callback function - which enables the application to optionally
-	provide the memory that will be used by the timer task as the task's stack
-	and TCB. */
-	extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
-
-#endif
-
-/*
- * Initialise the infrastructure used by the timer service task if it has not
- * been initialised already.
- */
-static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
-
-/*
- * The timer service task (daemon).  Timer functionality is controlled by this
- * task.  Other tasks communicate with the timer service task using the
- * xTimerQueue queue.
- */
-static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
-
-/*
- * Called by the timer service task to interpret and process a command it
- * received on the timer queue.
- */
-static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
- * depending on if the expire time causes a timer counter overflow.
- */
-static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
-
-/*
- * An active timer has reached its expire time.  Reload the timer if it is an
- * auto reload timer, then call its callback.
- */
-static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
-
-/*
- * The tick count has overflowed.  Switch the timer lists after ensuring the
- * current timer list does not still reference some timers.
- */
-static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
- * if a tick count overflow occurred since prvSampleTimeNow() was last called.
- */
-static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
-
-/*
- * If the timer list contains any active timers then return the expire time of
- * the timer that will expire first and set *pxListWasEmpty to false.  If the
- * timer list does not contain any timers then return 0 and set *pxListWasEmpty
- * to pdTRUE.
- */
-static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
-
-/*
- * If a timer has expired, process it.  Otherwise, block the timer service task
- * until either a timer does expire or a command is received.
- */
-static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
-
-/*
- * Called after a Timer_t structure has been allocated either statically or
- * dynamically to fill in the structure's members.
- */
-static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-									const TickType_t xTimerPeriodInTicks,
-									const UBaseType_t uxAutoReload,
-									void * const pvTimerID,
-									TimerCallbackFunction_t pxCallbackFunction,
-									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-BaseType_t xTimerCreateTimerTask( void )
-{
-BaseType_t xReturn = pdFAIL;
-
-	/* This function is called when the scheduler is started if
-	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
-	timer service task has been created/initialised.  If timers have already
-	been created then the initialisation will already have been performed. */
-	prvCheckForValidListAndQueue();
-
-	if( xTimerQueue != NULL )
-	{
-		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-		{
-			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
-			StackType_t *pxTimerTaskStackBuffer = NULL;
-			uint32_t ulTimerTaskStackSize;
-
-			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
-			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
-													configTIMER_SERVICE_TASK_NAME,
-													ulTimerTaskStackSize,
-													NULL,
-													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
-													pxTimerTaskStackBuffer,
-													pxTimerTaskTCBBuffer );
-
-			if( xTimerTaskHandle != NULL )
-			{
-				xReturn = pdPASS;
-			}
-		}
-		#else
-		{
-			xReturn = xTaskCreate(	prvTimerTask,
-									configTIMER_SERVICE_TASK_NAME,
-									configTIMER_TASK_STACK_DEPTH,
-									NULL,
-									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
-									&xTimerTaskHandle );
-		}
-		#endif /* configSUPPORT_STATIC_ALLOCATION */
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	configASSERT( xReturn );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-								const TickType_t xTimerPeriodInTicks,
-								const UBaseType_t uxAutoReload,
-								void * const pvTimerID,
-								TimerCallbackFunction_t pxCallbackFunction )
-	{
-	Timer_t *pxNewTimer;
-
-		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
-
-		if( pxNewTimer != NULL )
-		{
-			/* Status is thus far zero as the timer is not created statically
-			and has not been started.  The autoreload bit may get set in
-			prvInitialiseNewTimer. */
-			pxNewTimer->ucStatus = 0x00;
-			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
-		}
-
-		return pxNewTimer;
-	}
-
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-										const TickType_t xTimerPeriodInTicks,
-										const UBaseType_t uxAutoReload,
-										void * const pvTimerID,
-										TimerCallbackFunction_t pxCallbackFunction,
-										StaticTimer_t *pxTimerBuffer )
-	{
-	Timer_t *pxNewTimer;
-
-		#if( configASSERT_DEFINED == 1 )
-		{
-			/* Sanity check that the size of the structure used to declare a
-			variable of type StaticTimer_t equals the size of the real timer
-			structure. */
-			volatile size_t xSize = sizeof( StaticTimer_t );
-			configASSERT( xSize == sizeof( Timer_t ) );
-			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
-		}
-		#endif /* configASSERT_DEFINED */
-
-		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
-		configASSERT( pxTimerBuffer );
-		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
-
-		if( pxNewTimer != NULL )
-		{
-			/* Timers can be created statically or dynamically so note this
-			timer was created statically in case it is later deleted.  The
-			autoreload bit may get set in prvInitialiseNewTimer(). */
-			pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
-
-			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
-		}
-
-		return pxNewTimer;
-	}
-
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-									const TickType_t xTimerPeriodInTicks,
-									const UBaseType_t uxAutoReload,
-									void * const pvTimerID,
-									TimerCallbackFunction_t pxCallbackFunction,
-									Timer_t *pxNewTimer )
-{
-	/* 0 is not a valid value for xTimerPeriodInTicks. */
-	configASSERT( ( xTimerPeriodInTicks > 0 ) );
-
-	if( pxNewTimer != NULL )
-	{
-		/* Ensure the infrastructure used by the timer service task has been
-		created/initialised. */
-		prvCheckForValidListAndQueue();
-
-		/* Initialise the timer structure members using the function
-		parameters. */
-		pxNewTimer->pcTimerName = pcTimerName;
-		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
-		pxNewTimer->pvTimerID = pvTimerID;
-		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
-		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
-		if( uxAutoReload != pdFALSE )
-		{
-			pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
-		}
-		traceTIMER_CREATE( pxNewTimer );
-	}
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
-{
-BaseType_t xReturn = pdFAIL;
-DaemonTaskMessage_t xMessage;
-
-	configASSERT( xTimer );
-
-	/* Send a message to the timer service task to perform a particular action
-	on a particular timer definition. */
-	if( xTimerQueue != NULL )
-	{
-		/* Send a command to the timer service task to start the xTimer timer. */
-		xMessage.xMessageID = xCommandID;
-		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
-		xMessage.u.xTimerParameters.pxTimer = xTimer;
-
-		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
-		{
-			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
-			{
-				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
-			}
-			else
-			{
-				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
-			}
-		}
-		else
-		{
-			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
-		}
-
-		traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
-{
-	/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
-	started, then xTimerTaskHandle will be NULL. */
-	configASSERT( ( xTimerTaskHandle != NULL ) );
-	return xTimerTaskHandle;
-}
-/*-----------------------------------------------------------*/
-
-TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
-{
-Timer_t *pxTimer = xTimer;
-
-	configASSERT( xTimer );
-	return pxTimer->xTimerPeriodInTicks;
-}
-/*-----------------------------------------------------------*/
-
-void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )
-{
-Timer_t * pxTimer =  xTimer;
-
-	configASSERT( xTimer );
-	taskENTER_CRITICAL();
-	{
-		if( uxAutoReload != pdFALSE )
-		{
-			pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
-		}
-		else
-		{
-			pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
-		}
-	}
-	taskEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
-{
-Timer_t * pxTimer =  xTimer;
-TickType_t xReturn;
-
-	configASSERT( xTimer );
-	xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-{
-Timer_t *pxTimer = xTimer;
-
-	configASSERT( xTimer );
-	return pxTimer->pcTimerName;
-}
-/*-----------------------------------------------------------*/
-
-static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
-{
-BaseType_t xResult;
-Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
-	/* Remove the timer from the list of active timers.  A check has already
-	been performed to ensure the list is not empty. */
-	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
-	traceTIMER_EXPIRED( pxTimer );
-
-	/* If the timer is an auto reload timer then calculate the next
-	expiry time and re-insert the timer in the list of active timers. */
-	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
-	{
-		/* The timer is inserted into a list using a time relative to anything
-		other than the current time.  It will therefore be inserted into the
-		correct list relative to the time this task thinks it is now. */
-		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
-		{
-			/* The timer expired before it was added to the active timer
-			list.  Reload it now.  */
-			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
-			configASSERT( xResult );
-			( void ) xResult;
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Call the timer callback. */
-	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
-}
-/*-----------------------------------------------------------*/
-
-static portTASK_FUNCTION( prvTimerTask, pvParameters )
-{
-TickType_t xNextExpireTime;
-BaseType_t xListWasEmpty;
-
-	/* Just to avoid compiler warnings. */
-	( void ) pvParameters;
-
-	#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
-	{
-		extern void vApplicationDaemonTaskStartupHook( void );
-
-		/* Allow the application writer to execute some code in the context of
-		this task at the point the task starts executing.  This is useful if the
-		application includes initialisation code that would benefit from
-		executing after the scheduler has been started. */
-		vApplicationDaemonTaskStartupHook();
-	}
-	#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
-
-	for( ;; )
-	{
-		/* Query the timers list to see if it contains any timers, and if so,
-		obtain the time at which the next timer will expire. */
-		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
-
-		/* If a timer has expired, process it.  Otherwise, block this task
-		until either a timer does expire, or a command is received. */
-		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
-
-		/* Empty the command queue. */
-		prvProcessReceivedCommands();
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
-{
-TickType_t xTimeNow;
-BaseType_t xTimerListsWereSwitched;
-
-	vTaskSuspendAll();
-	{
-		/* Obtain the time now to make an assessment as to whether the timer
-		has expired or not.  If obtaining the time causes the lists to switch
-		then don't process this timer as any timers that remained in the list
-		when the lists were switched will have been processed within the
-		prvSampleTimeNow() function. */
-		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
-		if( xTimerListsWereSwitched == pdFALSE )
-		{
-			/* The tick count has not overflowed, has the timer expired? */
-			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
-			{
-				( void ) xTaskResumeAll();
-				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
-			}
-			else
-			{
-				/* The tick count has not overflowed, and the next expire
-				time has not been reached yet.  This task should therefore
-				block to wait for the next expire time or a command to be
-				received - whichever comes first.  The following line cannot
-				be reached unless xNextExpireTime > xTimeNow, except in the
-				case when the current timer list is empty. */
-				if( xListWasEmpty != pdFALSE )
-				{
-					/* The current timer list is empty - is the overflow list
-					also empty? */
-					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
-				}
-
-				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
-
-				if( xTaskResumeAll() == pdFALSE )
-				{
-					/* Yield to wait for either a command to arrive, or the
-					block time to expire.  If a command arrived between the
-					critical section being exited and this yield then the yield
-					will not cause the task to block. */
-					portYIELD_WITHIN_API();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		else
-		{
-			( void ) xTaskResumeAll();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
-{
-TickType_t xNextExpireTime;
-
-	/* Timers are listed in expiry time order, with the head of the list
-	referencing the task that will expire first.  Obtain the time at which
-	the timer with the nearest expiry time will expire.  If there are no
-	active timers then just set the next expire time to 0.  That will cause
-	this task to unblock when the tick count overflows, at which point the
-	timer lists will be switched and the next expiry time can be
-	re-assessed.  */
-	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
-	if( *pxListWasEmpty == pdFALSE )
-	{
-		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
-	}
-	else
-	{
-		/* Ensure the task unblocks when the tick count rolls over. */
-		xNextExpireTime = ( TickType_t ) 0U;
-	}
-
-	return xNextExpireTime;
-}
-/*-----------------------------------------------------------*/
-
-static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
-{
-TickType_t xTimeNow;
-PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
-
-	xTimeNow = xTaskGetTickCount();
-
-	if( xTimeNow < xLastTime )
-	{
-		prvSwitchTimerLists();
-		*pxTimerListsWereSwitched = pdTRUE;
-	}
-	else
-	{
-		*pxTimerListsWereSwitched = pdFALSE;
-	}
-
-	xLastTime = xTimeNow;
-
-	return xTimeNow;
-}
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
-{
-BaseType_t xProcessTimerNow = pdFALSE;
-
-	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
-	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
-
-	if( xNextExpiryTime <= xTimeNow )
-	{
-		/* Has the expiry time elapsed between the command to start/reset a
-		timer was issued, and the time the command was processed? */
-		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-		{
-			/* The time between a command being issued and the command being
-			processed actually exceeds the timers period.  */
-			xProcessTimerNow = pdTRUE;
-		}
-		else
-		{
-			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
-		}
-	}
-	else
-	{
-		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
-		{
-			/* If, since the command was issued, the tick count has overflowed
-			but the expiry time has not, then the timer must have already passed
-			its expiry time and should be processed immediately. */
-			xProcessTimerNow = pdTRUE;
-		}
-		else
-		{
-			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
-		}
-	}
-
-	return xProcessTimerNow;
-}
-/*-----------------------------------------------------------*/
-
-static void	prvProcessReceivedCommands( void )
-{
-DaemonTaskMessage_t xMessage;
-Timer_t *pxTimer;
-BaseType_t xTimerListsWereSwitched, xResult;
-TickType_t xTimeNow;
-
-	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
-	{
-		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
-		{
-			/* Negative commands are pended function calls rather than timer
-			commands. */
-			if( xMessage.xMessageID < ( BaseType_t ) 0 )
-			{
-				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
-
-				/* The timer uses the xCallbackParameters member to request a
-				callback be executed.  Check the callback is not NULL. */
-				configASSERT( pxCallback );
-
-				/* Call the function. */
-				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* INCLUDE_xTimerPendFunctionCall */
-
-		/* Commands that are positive are timer commands rather than pended
-		function calls. */
-		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
-		{
-			/* The messages uses the xTimerParameters member to work on a
-			software timer. */
-			pxTimer = xMessage.u.xTimerParameters.pxTimer;
-
-			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
-			{
-				/* The timer is in a list, remove it. */
-				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
-
-			/* In this case the xTimerListsWereSwitched parameter is not used, but
-			it must be present in the function call.  prvSampleTimeNow() must be
-			called after the message is received from xTimerQueue so there is no
-			possibility of a higher priority task adding a message to the message
-			queue with a time that is ahead of the timer daemon task (because it
-			pre-empted the timer daemon task after the xTimeNow value was set). */
-			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
-
-			switch( xMessage.xMessageID )
-			{
-				case tmrCOMMAND_START :
-				case tmrCOMMAND_START_FROM_ISR :
-				case tmrCOMMAND_RESET :
-				case tmrCOMMAND_RESET_FROM_ISR :
-				case tmrCOMMAND_START_DONT_TRACE :
-					/* Start or restart a timer. */
-					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
-					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
-					{
-						/* The timer expired before it was added to the active
-						timer list.  Process it now. */
-						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
-						traceTIMER_EXPIRED( pxTimer );
-
-						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
-						{
-							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
-							configASSERT( xResult );
-							( void ) xResult;
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-					break;
-
-				case tmrCOMMAND_STOP :
-				case tmrCOMMAND_STOP_FROM_ISR :
-					/* The timer has already been removed from the active list. */
-					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
-					break;
-
-				case tmrCOMMAND_CHANGE_PERIOD :
-				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
-					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
-					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
-					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
-
-					/* The new period does not really have a reference, and can
-					be longer or shorter than the old one.  The command time is
-					therefore set to the current time, and as the period cannot
-					be zero the next expiry time can only be in the future,
-					meaning (unlike for the xTimerStart() case above) there is
-					no fail case that needs to be handled here. */
-					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
-					break;
-
-				case tmrCOMMAND_DELETE :
-					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-					{
-						/* The timer has already been removed from the active list,
-						just free up the memory if the memory was dynamically
-						allocated. */
-						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
-						{
-							vPortFree( pxTimer );
-						}
-						else
-						{
-							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
-						}
-					}
-					#else
-					{
-						/* If dynamic allocation is not enabled, the memory
-						could not have been dynamically allocated. So there is
-						no need to free the memory - just mark the timer as
-						"not active". */
-						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
-					}
-					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-					break;
-
-				default	:
-					/* Don't expect to get here. */
-					break;
-			}
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvSwitchTimerLists( void )
-{
-TickType_t xNextExpireTime, xReloadTime;
-List_t *pxTemp;
-Timer_t *pxTimer;
-BaseType_t xResult;
-
-	/* The tick count has overflowed.  The timer lists must be switched.
-	If there are any timers still referenced from the current timer list
-	then they must have expired and should be processed before the lists
-	are switched. */
-	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
-	{
-		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
-
-		/* Remove the timer from the list. */
-		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
-		traceTIMER_EXPIRED( pxTimer );
-
-		/* Execute its callback, then send a command to restart the timer if
-		it is an auto-reload timer.  It cannot be restarted here as the lists
-		have not yet been switched. */
-		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
-
-		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
-		{
-			/* Calculate the reload value, and if the reload value results in
-			the timer going into the same timer list then it has already expired
-			and the timer should be re-inserted into the current list so it is
-			processed again within this loop.  Otherwise a command should be sent
-			to restart the timer to ensure it is only inserted into a list after
-			the lists have been swapped. */
-			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
-			if( xReloadTime > xNextExpireTime )
-			{
-				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
-				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
-				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
-			}
-			else
-			{
-				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
-				configASSERT( xResult );
-				( void ) xResult;
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-	pxTemp = pxCurrentTimerList;
-	pxCurrentTimerList = pxOverflowTimerList;
-	pxOverflowTimerList = pxTemp;
-}
-/*-----------------------------------------------------------*/
-
-static void prvCheckForValidListAndQueue( void )
-{
-	/* Check that the list from which active timers are referenced, and the
-	queue used to communicate with the timer service, have been
-	initialised. */
-	taskENTER_CRITICAL();
-	{
-		if( xTimerQueue == NULL )
-		{
-			vListInitialise( &xActiveTimerList1 );
-			vListInitialise( &xActiveTimerList2 );
-			pxCurrentTimerList = &xActiveTimerList1;
-			pxOverflowTimerList = &xActiveTimerList2;
-
-			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-			{
-				/* The timer queue is allocated statically in case
-				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
-				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
-				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
-
-				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
-			}
-			#else
-			{
-				xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
-			}
-			#endif
-
-			#if ( configQUEUE_REGISTRY_SIZE > 0 )
-			{
-				if( xTimerQueue != NULL )
-				{
-					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			#endif /* configQUEUE_REGISTRY_SIZE */
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	taskEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
-{
-BaseType_t xReturn;
-Timer_t *pxTimer = xTimer;
-
-	configASSERT( xTimer );
-
-	/* Is the timer in the list of active timers? */
-	taskENTER_CRITICAL();
-	{
-		if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
-		{
-			xReturn = pdFALSE;
-		}
-		else
-		{
-			xReturn = pdTRUE;
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	return xReturn;
-} /*lint !e818 Can't be pointer to const due to the typedef. */
-/*-----------------------------------------------------------*/
-
-void *pvTimerGetTimerID( const TimerHandle_t xTimer )
-{
-Timer_t * const pxTimer = xTimer;
-void *pvReturn;
-
-	configASSERT( xTimer );
-
-	taskENTER_CRITICAL();
-	{
-		pvReturn = pxTimer->pvTimerID;
-	}
-	taskEXIT_CRITICAL();
-
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
-{
-Timer_t * const pxTimer = xTimer;
-
-	configASSERT( xTimer );
-
-	taskENTER_CRITICAL();
-	{
-		pxTimer->pvTimerID = pvNewID;
-	}
-	taskEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-#if( INCLUDE_xTimerPendFunctionCall == 1 )
-
-	BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
-	{
-	DaemonTaskMessage_t xMessage;
-	BaseType_t xReturn;
-
-		/* Complete the message with the function parameters and post it to the
-		daemon task. */
-		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
-		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
-		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
-		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
-
-		xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
-
-		tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
-
-		return xReturn;
-	}
-
-#endif /* INCLUDE_xTimerPendFunctionCall */
-/*-----------------------------------------------------------*/
-
-#if( INCLUDE_xTimerPendFunctionCall == 1 )
-
-	BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
-	{
-	DaemonTaskMessage_t xMessage;
-	BaseType_t xReturn;
-
-		/* This function can only be called after a timer has been created or
-		after the scheduler has been started because, until then, the timer
-		queue does not exist. */
-		configASSERT( xTimerQueue );
-
-		/* Complete the message with the function parameters and post it to the
-		daemon task. */
-		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
-		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
-		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
-		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
-
-		xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
-
-		tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
-
-		return xReturn;
-	}
-
-#endif /* INCLUDE_xTimerPendFunctionCall */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
-	{
-		return ( ( Timer_t * ) xTimer )->uxTimerNumber;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
-	{
-		( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-/* This entire source file will be skipped if the application is not configured
-to include software timer functionality.  If you want to include software timer
-functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
-#endif /* configUSE_TIMERS == 1 */
-
-
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/template/ARM_CM33/FreeRTOSConfig.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/template/ARM_CM33/FreeRTOSConfig.h
deleted file mode 100644
index 7641a84..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/amazon-freertos/template/ARM_CM33/FreeRTOSConfig.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://aws.amazon.com/freertos
- * http://www.FreeRTOS.org
- */
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *
- * See http://www.freertos.org/a00110.html.
- *----------------------------------------------------------*/
-
-#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
-    /* Clock manager provides in this variable system core clock frequency */
-    #include 
-    extern uint32_t SystemCoreClock;
-#endif
-
-#ifndef configENABLE_FPU
-  #define configENABLE_FPU                      0
-#endif
-#ifndef configENABLE_MPU
-  #define configENABLE_MPU                      0
-#endif
-#ifndef configENABLE_TRUSTZONE
-  #define configENABLE_TRUSTZONE                0
-#endif
-#ifndef configRUN_FREERTOS_SECURE_ONLY
-  #define configRUN_FREERTOS_SECURE_ONLY        1
-#endif
-
-#define configUSE_PREEMPTION                    1
-#define configUSE_TICKLESS_IDLE                 0
-#define configCPU_CLOCK_HZ                      (SystemCoreClock)
-#define configTICK_RATE_HZ                      ((TickType_t)200)
-#define configMAX_PRIORITIES                    5
-#define configMINIMAL_STACK_SIZE                ((unsigned short)90)
-#define configMAX_TASK_NAME_LEN                 20
-#define configUSE_16_BIT_TICKS                  0
-#define configIDLE_SHOULD_YIELD                 1
-#define configUSE_TASK_NOTIFICATIONS            1
-#define configUSE_MUTEXES                       1
-#define configUSE_RECURSIVE_MUTEXES             1
-#define configUSE_COUNTING_SEMAPHORES           1
-#define configUSE_ALTERNATIVE_API               0 /* Deprecated! */
-#define configQUEUE_REGISTRY_SIZE               8
-#define configUSE_QUEUE_SETS                    0
-#define configUSE_TIME_SLICING                  0
-#define configUSE_NEWLIB_REENTRANT              0
-#define configENABLE_BACKWARD_COMPATIBILITY     1
-#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
-#define configUSE_APPLICATION_TASK_TAG          0
-
-/* Memory allocation related definitions. */
-#define configSUPPORT_STATIC_ALLOCATION         0
-#define configSUPPORT_DYNAMIC_ALLOCATION        1
-#define configTOTAL_HEAP_SIZE                   ((size_t)(10240))
-#define configAPPLICATION_ALLOCATED_HEAP        0
-
-/* Hook function related definitions. */
-#define configUSE_IDLE_HOOK                     0
-#define configUSE_TICK_HOOK                     0
-#define configCHECK_FOR_STACK_OVERFLOW          0
-#define configUSE_MALLOC_FAILED_HOOK            0
-#define configUSE_DAEMON_TASK_STARTUP_HOOK      0
-
-/* Run time and task stats gathering related definitions. */
-#define configGENERATE_RUN_TIME_STATS           0
-#define configUSE_TRACE_FACILITY                1
-#define configUSE_STATS_FORMATTING_FUNCTIONS    0
-
-/* Co-routine related definitions. */
-#define configUSE_CO_ROUTINES                   0
-#define configMAX_CO_ROUTINE_PRIORITIES         2
-
-/* Software timer related definitions. */
-#define configUSE_TIMERS                        1
-#define configTIMER_TASK_PRIORITY               (configMAX_PRIORITIES - 1)
-#define configTIMER_QUEUE_LENGTH                10
-#define configTIMER_TASK_STACK_DEPTH            (configMINIMAL_STACK_SIZE * 2)
-
-/* Define to trap errors during development. */
-#define configASSERT(x) if((x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
-
-/* Optional functions - most linkers will remove unused functions anyway. */
-#define INCLUDE_vTaskPrioritySet                1
-#define INCLUDE_uxTaskPriorityGet               1
-#define INCLUDE_vTaskDelete                     1
-#define INCLUDE_vTaskSuspend                    1
-#define INCLUDE_vTaskDelayUntil                 1
-#define INCLUDE_vTaskDelay                      1
-#define INCLUDE_xTaskGetSchedulerState          1
-#define INCLUDE_xTaskGetCurrentTaskHandle       1
-#define INCLUDE_uxTaskGetStackHighWaterMark     0
-#define INCLUDE_xTaskGetIdleTaskHandle          0
-#define INCLUDE_eTaskGetState                   0
-#define INCLUDE_xTimerPendFunctionCall          1
-#define INCLUDE_xTaskAbortDelay                 0
-#define INCLUDE_xTaskGetHandle                  0
-#define INCLUDE_xTaskResumeFromISR              1
-
-#ifdef __NVIC_PRIO_BITS
-/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
-#define configPRIO_BITS __NVIC_PRIO_BITS
-#else
-#define configPRIO_BITS 4 /* 15 priority levels */
-#endif
-
-/* The lowest interrupt priority that can be used in a call to a "set priority"
-function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
-
-/* The highest interrupt priority that can be used by any interrupt service
-routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
-
-/* Interrupt priorities used by the kernel port layer itself.  These are generic
-to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
-
-/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
-standard names. */
-#define vPortSVCHandler SVC_Handler
-#define xPortPendSVHandler PendSV_Handler
-#define xPortSysTickHandler SysTick_Handler
-
-#endif /* FREERTOS_CONFIG_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/CHANGELOG.md b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/CHANGELOG.md
deleted file mode 100644
index facd7b0..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/CHANGELOG.md
+++ /dev/null
@@ -1,935 +0,0 @@
-# Change Log for FreeRTOS
-
-## 202002.00 2/18/2020
-
-### New Features
-
-#### FreeRTOS kernel V10.3.0
-- Includes FreeRTOS kernel V10.3.0
-- Additional details can be found here: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/V10.3.0-kernel-only/History.txt
-
-#### Product Name Change
-- The name 'Amazon FreeRTOS' has been changed to 'FreeRTOS'
-- The name 'Amazon FreeRTOS Qualification (AFQ)' has been changed to 'Device Qualification Program for FreeRTOS'
-- Changes were applied only to comments and headers
-
-### Updates
-### Cmake
-- Fix a dependency parsing bug in CMake
-
-## 201912.00 12/17/2019
-
-### New Features
-
-#### Over the Air Update V1.1.0
-- Refactor OTA agent and separate data transfer and control interface.
-- Support OTA data transfer over HTTP.
-
-#### Common I/O Library V0.1.0
-- A preview of Common I/O library is included.
-- Common I/O library provides a set of standard APIs, across supported reference boards, for accessing common devices.
-- This preview supports UART, SPI and I2C. Support for other peripherals will follow.
-
-### Updates
-#### lwIP
-- Enable lwIP full duplex feature
-    - The same socket may be used by multiple tasks concurrently
-- lwIP is now a submodule from https://github.com/lwip-tcpip/lwip.git
-
-#### Ethernet Support on Nuvoton NuMaker-IoT-M487
-- Ethernet is now available for Nuvoton NuMaker-IoT-M487.
-- Either Wi-Fi or Ethernet can be enabled exclusively.
-
-#### HTTPS Client Library V1.1.1
-- Documentation updates and additional debug logging.
-
-#### Greengrass Discovery V2.0.0
-- Remove demo configuration dependency from library files.
-- Update demonstration code to use MQTT V2 APIs.
-
-#### Bluetooth Low Energy V4.0.0
-- HAL modification to replace bonded callback with pairing state change callback.
-- HAL modification to change to 16-bit value for advertisement duration.
-
-## 201910.00 10/29/2019
-
-### New Features
-#### New Board: Infineon XMC4800 IoT Connectivity Kit with OPTIGA Trust X
-- The Infineon XMC4800 IoT Connectivity Kit with OPTIGA Trust X secure element is now qualified for Amazon FreeRTOS.
-
-#### New Board: Microchip ATECC608A with Windows Simulator
-- The Microchip ATECC608A secure element with Windows Simulator is now qualified for Amazon FreeRTOS.
-
-#### Defender Client Library V3.0.0
-- Defender Library API change to shared MQTT connection.
-- Demonstration code for Defender Library updated to show use of shared connection.
-
-#### HTTPS Client Library V1.1.0
-- Upload support with HTTP methods PUT and POST is now available in the HTTPS Client Library.
-- Demonstration code with PUT and POST methods are now available in demos/https.
-
-#### SoftHSMv2 port for PKCS #11
-- A port for SoftHSMv2, a third-party open-source implementation of PKCS #11, has been provided for use with the Windows Simulator project for Amazon FreeRTOS.
-- The purpose of the SoftHSMv2 port is to allow ad hoc interoperability testing with an independent implementation of the PKCS #11 standard.
-
-#### CMake Builds
-- CMake build is now supported for Nordic nRF52840 DK Development kit.
-
-### Updates
-#### FreeRTOS Kernel
-- FreeRTOS kernel is now a submodule from https://github.com/FreeRTOS/FreeRTOS-Kernel.git
-
-#### HTTP Parser
-- Add nodejs/http_parser as a submodule in place of copied-over files.
-
-#### Unity
-- Add ThrowTheSwitch/Unity as a submodule in place of copied-over files.
-
-#### PKCS #11
-- Update the PKCS #11 third-party headers to be the latest from OASIS (version 2.40 Plus Errata 01).
-- Add PKCS #11 as a submodule.
-
-#### Bluetooth Low Energy
-- ESP32 board supports NIMBLE as the default underlying stack for Bluetooth Low Energy.
-- Contains bug fixes and enhancements in ESP NIMBLE stack.
-- Contains bug fixes in ESP Bluedroid stack.
-
-#### Marvell SDK Update
-- Marvell SDK now updated to R8 P2 (v1.2.r8.p2)
-
-#### Bluetooth Low Energy
-- ESP32 board supports NIMBLE as the default underlying stack for Bluetooth Low Energy.
-- Contains bug fixes and enhancements in ESP NIMBLE stack.
-- Contains bug fixes in ESP Bluedroid stack.
-
-## 201908.00 08/26/2019
-
-### New Features
-#### New Board:Nuvoton NuMaker-IoT-M487
-- Nuvoton NuMaker-IoT-M487 is now qualified for Amazon FreeRTOS.
-- Disclaimer on RNG: The random number generation solution in this port is for demonstration purposes only.
-
-#### FreeRTOS Kernel V10.2.1
-- Kernel version for Amazon FreeRTOS is updated to V10.2.1.
-- Add ARM Cortex-M23 (ARMv8-M) GCC/ARMclang and IAR ports.
-- Add support to automatically switch between 32-bit and 64-bit cores to RISC-V port.
-
-#### HTTPS Client Library V1.0.0
-- The HTTPS Client library for Amazon FreeRTOS supports the HTTP/1.1 protocol over TLS.
-- The current request methods supported are GET and HEAD.
-- Examples demonstrate downloading a file from S3 using GET with a pre-signed URL.
-
-### Updates
-#### PKCS #11
-- Update the Amazon FreeRTOS mbedTLS-based PKCS #11 implementation, tests, demos, and PKCS #11 consuming libraries for compliance with standard.
-- Add PKCS #11 wrapper functions for easy use of commonly grouped PKCS #11 calls.
-
-#### Demo specific stack size and priority
-- Make stack size and priority to be demo specific. In current release all demos have same stack size and priority. This change will make stack size and priority configurable for each demo. Demo can use default stack size/ priority or define its own.
-#### Ethernet for Microchip Curiosity PIC32MZEF
-- Update Microchip Curiosity PIC32MZEF project and configuration files to support Ethernet connectivty. Developers must define PIC32_USE_ETHERNET at the project level to use Ethernet instead of Wi-Fi.
-#### lwIP 2.1.2
-- Update lwIP to version 2.1.2, and change existing ports as necessary.
-
-### Test Updates
-- Remove elliptic curve tests from "quarantine" test group and add them back to the TLS test group.
-
-#### AWS OTA Agent
-- OTA Callback changes for custom and secondary processor jobs. Modifying the OTA Agent to use callback structure instead of directly calling PAL functions. This allows users to pass in custom callbacks for the PAL functions.
-
-## 201906.00 Major 06/17/2019
-### Release Versioning
-- Move Amazon FreeRTOS to a new versioning scheme (YYYYMM.NN [optional "Major" tag]), while retaining semantic versioning (x.y.z) used for individual libraries within Amazon FreeRTOS. This release contains multiple major version updates for individual libraries. See below for details.
-
-### Folder Structure
-- Update folder structure to provide a cleaner separation between FreeRTOS kernel, standard libraries, AWS libraries, platform-specific ports and 3rd party libraries. Customers upgrading from earlier versions will need to update their project files.
-
-### New Features
-#### Bluetooth Low Energy Management Library V1.0.0
-- Bluetooth Low Energy management API for GAP and GATT services, with support for
-    - Bluetooth Low Energy v4.2 and above.
-    - Device discovery, notifications and indications.
-    - Creating, starting, stopping, and deleting GATT services.
-    - “Just Works” and “Secure Connections - Numeric Comparison” connection methods.
-- Companion device SDK 1.0.0 release for
-    - Android https://github.com/aws/amazon-freertos-ble-android-sdk/
-    - iOS https://github.com/aws/amazon-freertos-ble-ios-sdk/
-- GATT services for
-    - Device information.
-    - Wi-Fi credentials provisioning.
-    - MQTT-over-Bluetooth Low Energy through Android or iOS device proxy to support.
-        - OTA and Device Shadow functionality.
-
-#### MQTT Library V2.0.0, Device Shadow Library V2.0.0, and Device Defender Library V2.0.0
-- Enable consistent re-use pattern of one single connection across all libraries.
-- Add support for MQTT 3.1.1 standard features.
-    - Last Will and Testament.
-    - QoS1 with randomized retry logic.
-    - Persistent sessions.
-- Add programming model revisions to enable.
-    - Fully non-blocking programming model.
-    - Per-operation user callback.
-    - Fully dynamic or fully static memory management.
-    - Full support for Bluetooth Low Energy transport as well as TCP/IP.
-    - Re-implementable abstraction layer to allow port on any network stacks.
-    - Standard, configurable logging mechanism.
-- Extend Device Defender support to additional development boards. Current set of metrics now available on all development boards that implement Secure Sockets abstraction.
-
-#### Task Pool library V1.0.0
-- Task (Thread) pool library for asynchronous processing.
-
-#### Atomic Operations Library V1.0.0
-- Add library for atomic operations support.
-
-### Updates
-#### Wi-Fi Management Library V1.0.3
-- Add new API ```WIFI_RegisterNetworkStateChangeEventCallback``` to allow application notifications for Wi-Fi state transitions.
-
-#### CMake Builds
-- Extend the ability to build projects using CMake in addition to providing IDE project files. CMake files are now available for the following development boards:
-    - Espressif ESP32-DevKitC
-    - Espressif ESP-WROVER-KIT
-    - Infineon XMC4800 IoT Connectivity Kit
-    - Marvell MW320 AWS IoT Starter Kit
-    - Marvell MW322 AWS IoT Starter Kit
-    - Microchip Curiosity PIC32MZEF Bundle
-    - STMicroelectronicsSTM32L4 Discovery Kit IoT Node
-    - Texas Instruments CC3220SF-LAUNCHXL
-    - Microsoft Windows Simulator
-
-### Updates
-- mbedTLS library is upgraded to version 2.16.0.
-- ESP-IDF version is upgraded to 3.1.3.
-- Update demo projects for cleaner separation of platform specific code.
-- Documentation update.
-
-## V1.4.8 05/21/2019
-### New Features
-#### New Boards: Marvell MW320 and MW322
-- Marvell boards MW320 and MW322 are now qualified for Amazon FreeRTOS.
-- Disclaimer on RNG: The random number generation solution in this port is for demonstration purposes only.
-
-#### FreeRTOS Kernel V10.2.0
-- Kernel version for Amazon FreeRTOS is updated to V10.2.0.
-- Add Support for RISC-V.
-- Include pre-existing ARM Cortex-M33 (ARMv8-M) GCC/ARMclang and IAR ports.
-
-### Updates
-
-#### Greengrass Discovery V1.0.4
-- Include C runtime header for snprintf.
-- Sanity check the number of bytes written.
-- Thing name can be a non-string literal.
-
-#### MQTT Agent V1.1.5
-- Set the socket to block on sends with a timeout in prvSetupConnection.
-
-#### Secure Sockets for FreeRTOS+TCP V1.1.6
-- ulApplicationGetNextSequenceNumber is now thread safe without stopping the scheduler.
-- Leave the scheduler running during PKCS #11 calls.
-
-#### Wi-Fi for ESP32-DevKitC ESP-WROVER-KIT V1.0.2
-- lib/wifi: fix issue with WiFi configuration for non-null strings, and fix scanning failure under certain disconnect scenarios.
-- ib/FreeRTOS-Plus-TCP: do not send eNetworkDownEvent to stack if interface is already down.
-- mbedtls: configurable options for controlling dynamic memory allocations.
-- lib/third_party: update ESP-IDF to latest v3.1.3 release.
-- NetworkInterface: check interface state before sending packets to WiFi driver.
-- Fix WIFI_GetMac returning wrong mac address.
-
-#### PKCS #11 PAL for Cypress CYW943907AEVAL1F development kit V1.0.1
-- Fix Cypress build error with IDE.
-
-#### PKCS #11 PAL for Cypress CYW954907AEVAL1F development kit V1.0.1
-- Fix Cypress build error with  IDE.
-
-#### FreeRTOS+TCP V2.0.11
-- Make RST packet handling more robust.
-- Make TCP window high and low watermark thresholds runtime configurable.
-- Fix parsing of the last option in a DHCP response packet.
-- Fix TCP window size calculation.
-- Allow the DNS cache to be programmatically cleared.
-- Free the memory allocated by the pcap_compile routine in the WinPCap network interface module.
-
-#### Shadow V1.0.6
-- Add a debug message in the event that JSMN runs out of memory trying to parse JSON.
-- Print a debug message for any JSMN error, not just 'JSMN_ERROR_NOMEM'.
-
-#### PKCS #11 PAL for Windows Simulator V1.0.4
-- Update to permit multithreaded read from object storage.
-
-#### OTA Agent V1.0.2
-- Update documentation.
-
-#### TLS V1.1.4
-- TLS_Send now handles the error condition when space is not avaiable.
-- Convert errors in TLS wrapper to negative error codes.
-
-#### Curiosity PIC32MZEF Linker Update for XC32 Compiler
-- The latest XC32 compiler (version 2.15) does not allow multiple definitions by default. Explicitly enabling multiple definitions in aws_tests and aws_demos projects for now.
-
-## V1.4.7 02/18/2019
-### New Features
-### New Boards: Cypress CYW43907 and CYW54907
-- Cypress boards CYW54907 and CYW43907 are now qualified for Amazon FreeRTOS.
-
-#### FreeRTOS Kernel V10.1.1
-- Kernel version for Amazon FreeRTOS is updated to 10.1.1.
-- Update all object handles (TaskHandle_t, QueueHandle_t, etc.) to be unique types instead of void pointers, improving type safety.
-- Add Xtensa port.
-- Update to the latest trace recorder code.
-- Update lint checked MISRA compliance to use the latest MISRA standard.
-- Add configUSE_POSIX_ERRNO to enable per task POSIX style errno functionality.
-
-### Updates
-
-#### FreeRTOS+POSIX V1.0.3
-- Use stack based alloaction for POSIX types. Stack based allocation will reduce heap fragmentation.
-- Fixed potential overflow in Posix timespec utils.
-- Stopped Posix timer spawnning thread every time it is invoked.
-- Unlock and update owner atomically, while unlocking mutex.
-
-#### MQTT Agent V1.1.4
-- Bug fix: MQTT agent tries to setup a connection with the MQTT broker when the socket does not exist.
-
-####  Upgrading ESP-IDF to 3.1.1
-- ESP-IDF upgraded to 3.1.1.
-
-#### OTA PAL for Curiosity PIC32MZEF V1.0.3
-- Rename variables to comply with style guidelines.
-
-#### OTA PAL for Windows Simulator V1.0.2
-- Rename variables to comply with style guidelines.
-
-#### OTA PAL for CC3220SF-LAUNCHXL V1.0.1
-- Rename variables to comply with style guidelines.
-
-#### OTA Agent V1.0.1
-- Rename variables to comply with style guidelines.
-
-#### PKCS #11 PAL for Cypress CYW943907AEVAL1F development kit V1.0.0
-- Added as part of Cypress CYW43907 board port.
-- Note that the random number generation solution in this port is provided for demonstration purposes only. See the comment in lib/pkcs11/portable/cypress/CYW943907AEVAL1F/hw_poll.c.
-
-#### PKCS #11 PAL for Cypress CYW954907AEVAL1F development kit V1.0.0
-- Added as part of Cypress CYW54907 board port.
-- Note that the random number generation solution in this port is provided for demonstration purposes only. See the comment in lib/pkcs11/portable/cypress/CYW954907AEVAL1F/hw_poll.c
-
-#### PKCS #11 PAL for ESP32-DevKitC ESP-WROVER-KIT V1.0.2
-- Updated as part of Updrade to ESP-IDF to 3.1.1.
-
-#### mbedTLS-based PKCS#11 V1.0.7
-- Bug Fix: Multi-threaded use of PKCS #11 Sign/Verify could cause key corruption.
-
-#### Wi-Fi for Cypress CYW943907AEVAL1F development kit V1.0.0
-- Added as part of Cypress CYW43907 board port.
-
-#### Wi-Fi for Cypress CYW954907AEVAL1F development kit V1.0.0
-- Added as part of Cypress CYW54907 board port.
-
-#### Wi-Fi for ESP32-DevKitC ESP-WROVER-KIT V1.0.1
-- Update as part of Updrade to ESP-IDF to 3.1.1.
-
-#### Wi-Fi for LPC54018 IoT Module V1.0.3
-- Bug fix: Update WIFI init API to return success if WIFI module was already successfully initialized.
-- Bug fix: Update WIFI AP connection API for NXP to check if DHCP was successful.
-
-## V1.4.6 12/27/2018
-### New Features
-
-#### New Board: Renesas Starter Kit+ for RX65N-2MB
-The Renesas Starter Kit+ for RX65N-2MB is now qualified for Amazon FreeRTOS. This port updates the PKCS #11 portable layer, demo projects, and tests.
-
-### Updates
-
-#### FreeRTOS+POSIX V1.0.2
-- Improvement to reduce the size of a pthread object and make the object user allocatable from stack.
-
-#### FreeRTOS+TCP V2.0.10
-- Add FreeRTOS+TCP support for the Renesas Starter Kit+ for RX65N-2MB.
-
-#### FreeRTOS Kernel V10.0.1
-- Add FreeRTOS Kernel support for the Renesas Starter Kit+ for RX65N-2MB.
-
-#### PKCS #11 PAL for MT7697Hx-Dev-Kit V1.0.1
-- Update license information.
-
-#### PKCS #11 PAL for Renesas Starter Kit+ for RX65N-2MB V1.0.0
-- Add PKCS #11 support for the Renesas Starter Kit+ for RX65N-2MB.
-- Note that the random number generation solution in this port is provided for demonstration purposes only. See the comment in lib/third_party/mcu_vendor/renesas/amazon_freertos_common/entropy_hardware_poll.c for more information.
-
-#### Wi-Fi for MT7697Hx-Dev-Kit V1.0.1
-- Update license information.
-
-## V1.4.5 12/13/2018
-### New Features
-
-#### New Board: MediaTek MT7697Hx-Dev-Kit
-The MediaTek MT7697 System on Chip (SoC) is now qualified for Amazon FreeRTOS. You can take advantage of Amazon FreeRTOS features and benefits using the MediaTek MT7697Hx Development Kit available from MediaTek Labs.  This development board contains the MT7697 SoC, which includes an Arm Cortex-M4 MCU, low power 1T1R 802.11 b/g/n Wi-Fi, Bluetooth 4.2 subsystem and power management unit.
-
-#### lwIP Support
-Amazon FreeRTOS support for the MediaTek MT7697Hx-Dev-Kit includes for the first time support for the Lightweight TCP / IP network stack (lwIP). This flexibility will support customer choice in identifying the best TCP stack solution for IoT devices.
-
-### Updates
-
-#### FreeRTOS+TCP V2.0.9
-- Update to flush ARP cache when then network is down.
-
-#### mbedTLS-based PKCS#11 V1.0.6
-- Delete extra include headers.
-
-#### PKCS #11 PAL for MT7697Hx-Dev-Kit V1.0.0
-- Add PKCS #11 support for the MediaTek MT7697Hx-Dev-Kit.
-
-#### Secure Sockets for FreeRTOS+TCP V1.1.5
-- Update documentation.
-
-#### Secure Sockets for lwIP V1.0.0
-- Add Secure Sockets support for lwIP.
-
-#### Wi-Fi for Infineon XMC4800 IoT Connectivity Kit V1.0.1
-- Update documentation.
-
-#### Wi-Fi for MT7697Hx-Dev-Kit V1.0.0
-- Add Wi-Fi support for the MediaTek MT7697Hx-Dev-Kit.
-
-## V1.4.4 11/19/2018
-### Updates
-
-#### Device Defender Demo V1.4.4
-- Remove warnings in Device Defender Demo build.
-
-#### Microchip "OTA Demo" Factory Image Script
-- Fix post-build command and python script for generating OTA factory image for Mac users.
-
-#### Device Defender Agent V1.0.2
-- Update formatting and build warnings.
-
-#### OTA PAL for ESP32-DevKitC ESP-WROVER-KIT V1.0.2
-- Fix bug in retrieving code signature verification certificate.
-
-#### OTA PAL for Curiosity PIC32MZEF V1.0.2
-- Fix bug in retrieving code signature verification certificate.
-
-## V1.4.3 11/07/2018
-### New Features
-
-#### New Board: Xilinx Zynq-7000 based MicroZed Industrial IoT Bundle
-- Update Amazon FreeRTOS with port files, demo projects, and tests for the Xilinx Zynq-7000 based MicroZed Industrial IoT Bundle
-
-### Updates
-
-#### mbedTLS Library
-- Upgrade to mbedTLS version 2.13.1.
-
-#### FreeRTOS+POSIX V1.0.1
-- Minor bug fixes.
-
-#### FreeRTOS+TCP V2.0.8
-- Update the Zynq-7000 portable layer for receive descriptor alignment.
-
-#### PKCS #11 Updates
-Update mbedTLS-based PKCS #11, and PKCS #11 PAL. These changes have been made to more closely align with the PKCS #11 standard, respond to feedback from users and partners, and make it easy for users to go to production from a prototype.
-Applications calling into PKCS #11 functions directly (rather than indirectly via an Amazon provided secure sockets or TLS layer) may experience breaking changes.
-
-##### mbedTLS-based PKCS #11
-- C_Initialize handles initialization of randomness in an effort to minimize entropy generation (or seed access) every time sessions are created and destroyed.  To protect random values, thread safety has been enabled in mbedTLS.
-- C_SignInit and C_VerifyInit utilize the key handle that is passed in, rather than the first key found in order to comply with the PKCS #11 standard
-- C_FindObject APIs no longer instantiate keys from the aws_clientcredential_keys.h header file if keys are not found. This removes the dependency of PKCS #11 on values that will be unique per-device (a transition step for enabling production-scale provisioning). Note that calling vDevModeKeyProvisioning() is now necessary to provision the device.
-- C_FindObject PKCS #11 objects can be looked up by CKA_LABEL, in order to provide a standard-compliant object lookup.  Note that pkcs11configFILE_NAME_* configurations have been removed from aws_pkcs11_config.h, see aws_pkcs11.h for pkcs11configLABEL_* defines to access labels, and aws_pkcs11_pal.c for pkcs11palFILE_NAME_* defines.
-- C_FindObject and C_GetAttributeValue accept different attribute arguments.
-- C_CreateObject requires DER encoded certificates and keys instead of PEM formatted and object attributes required for creating objects have changed.  Note that vDevModeKeyProvisioning() has been updated to supply required attributes and convert inputs from DER to PEM if necessary.
-- C_GenerateKeyPair now stores keys in non-volatile memory.
-- C_Finalize is no longer invoked by helper functions to prevent threads from interfering with each other's PKCS #11 instances.
-- Some error codes have been changes to better match the PKCS #11 standard.
-- aws_tls.c and PKCS #11 AFQP tests have updates to reflect these changes.
-    - mbedTLS-based PKCS #11 V1.0.5
-    - TLS V1.1.3
-
-##### PKCS #11 PAL for mbedTLS-based PKCS #11
-- Breaking changes were made to PAL PKCS #11 functions in order to transition from file-centric API to object handle and object label based API.
-    - PKCS #11 PAL for ESP32-DevKitC ESP-WROVER-KIT V1.0.1
-    - PKCS #11 PAL for XMC4800 IoT Kit V1.0.1
-    - PKCS #11 PAL for Curiosity PIC32MZEF V1.0.4
-    - PKCS #11 PAL for LPC54018 IoT Module V1.0.3
-    - PKCS #11 PAL for Windows Simulator V1.0.3
-    - PKCS #11 PAL for STM32L4 Discovery kit IoT node V1.0.3
-    - PKCS #11 PAL for Xilinx Zynq MicroZed V1.0.0 (new)
-
-##### PKCS #11 for CC3220SF-LAUNCHXL
-- Updates to match behavior of mbedTLS-based PKCS #11.
-- mbedTLS added to support conversion between DER and PEM objects.  Note that after provisioning the device, mbedTLS and provisiong PKCS #11 functions may be removed to reduce code size.
-    - PKCS #11 PAL for CC3220SF-LAUNCHXL V1.0.3
-
-##### OTA PAL Updates
-- The OTA PALs for the Curiosity PIC32MZEF and ESP32-DevKitC ESP-WROVER-KIT boards have been modified to utilize PKCS #11 API to retrieve code signing keys, rather than calling into PKCS #11 PAL functions.
-    - OTA PAL for Curiosity PIC32MZEF V1.0.1
-    - OTA PAL for ESP32-DevKitC ESP-WROVER-KIT V1.0.1
-
-#### Secure Socket for FreeRTOS+TCP V1.1.4
-- Minor update to handle PKCS #11 error codes.
-- Update formatting.
-
-#### Secure Sockets for Infineon XMC4800 IoT Connectivity Kit V1.0.1
-- Fix the license header from Secure Socket to Secure Sockets.
-
-#### Secure Sockets for STM32L4 Discovery kit IoT node V1.0.0 Beta 4
-- Bug fix to support Amazon Trust Services endpoints. For more information, please see https://aws.amazon.com/blogs/iot/aws-iot-core-ats-endpoints/.
-
-#### Secure Sockets for CC3220SF-LAUNCHXL V1.0.5
-- Remove duplicate file name definitions.  See aws_secure_sockets_config.h for file name defines.
-
-#### Shadow V1.0.5
-- Minor bug fixes.
-
-
-## V1.4.2 10/17/2018
-### New Features
-
-#### New Board: Infineon XMC4800 IoT Connectivity Kit
-Update Amazon FreeRTOS with port files, demo projects, and tests for the Infineon XMC4800 IoT Connectivity Kit.
-
-### Updates
-
-#### Update pthread Implementation in ESP-IDF
-Incorporate an update to Espressif's ESP-IDF which improves the implementation of pthread.
-
-#### Build Improvement: MPLAB PIC32 Projects
-Resolve several warnings in the MPLAB project builds, and update the projects to no longer assume that the XC32 compiler is in the host computer's path.
-
-#### Move Helper Utilities to the 'tools/' Directory
-Move a few utilities to the root-level 'tools/' directory, from the 'tests/common/tools/' and 'demos/common/tools/' directories.
-
-#### Styling Updates
-Improve consistency of Hungarian Notation usage, update a number of methods to use 'void' instead of an empty argument list, and update the style guide.
-
-#### New POSIX Functions
-Add POSIX functions including `time`, `localtime_r`, and `strftime`.
-
-#### Refactor Device Defender Direcory Structure
-Update Device Defender code to use the same 'lib/' and 'include/' directory structures as the other libraries.
-
-#### AFQP Documentation Updates
-Update the Amazon FreeRTOS Qualification Program's documentation to reflect updated directory structures.
-
-## V1.4.1 08/29/2018
-### New Features
-None
-
-### Updates
-
-#### OTA PAL for Windows Simulator V1.0.1
-- Update Amazon FreeRTOS Windows Simulator to use ECDSA/SHA-256 for OTA image verification.
-
-
-## V1.4.0 08/27/2018
-### New Features
-
-#### Demo Bootloader for Microchip Curiosity PIC32MZEF V1.0.0
-The demo bootloader supports Amazon FreeRTOS over-the-air (OTA) update by implementing firmware version checking, cryptographic signature verification, and application self-test. The firmware verification includes verifying the authenticity and integrity of the new firmware received over the air. The bootloader verifies the cryptographic signature of the application before boot. The elliptic-curve digital signature algorithm (ECDSA) with SHA256 is used. The utilities provided can be used to generate a signed application that can be flashed on the device. This enables signature verification of the initial image.
-
-### Updates
-
-#### Over-the-air (OTA) updates
-The over-the-air (OTA) updates feature of Amazon FreeRTOS is now generally available. The release includes enhancements to the OTA Agent and changes to the OTA Portable Abstraction Layer (PAL) interface.
-
-#### OTA PAL for Curiosity PIC32MZEF V1.0.0
-Update for API changes for OTA general availability release.
-
-#### OTA PAL for Windows Simulator V1.0.0
-Update for API changes for OTA general availability release.
-
-#### OTA PAL for CC3220SF-LAUNCHXL V1.0.0
-Update for API changes for OTA general availability release.
-
-#### OTA PAL for Espressif ESP32 V1.0.0
-Update for API changes for OTA general availability release.
-
-#### OTA Agent V1.0.0
-Enhancements and API changes for OTA general availability release.
-
-
-## V1.3.2 08/21/2018
-### New Features
-None
-
-### Updates
-
-#### FreeRTOS+TCP
-- Multiple security improvements and fixes in packet parsing routines, DNS caching, and TCP sequence number and ID generation.
-- Disable NBNS and LLMNR by default.
-- Add TCP hang protection by default.
-
-#### Secure Sockets for FreeRTOS+TCP
-- Improve security in Amazon FreeRTOS Secure Sockets usage of mbedTLS and ALPN.
-
-We thank Ori Karliner of Zimperium zLabs Team for reporting these issues.
-
-
-## V1.3.1 08/10/2018
-### New Features
-None
-
-### Updates
-
-#### OTA Beta Update
-- Updates to OTA Beta to incorporate a new API for the OTA service. This API is not compatible with the  API used in the original OTA Beta released on Dec. 20th.
-- Add a "reference bootloader" for use in the OTA process. This bootloader is for use with the Microchip MCU.
-
-#### Amazon FreeRTOS Qualification Program (AFQP) Update
-- Update AFQP documentation. For more info on the changes to AFQP, reference the Revision History of the "Amazon FreeRTOS Qualification Program Developer Guide" in the "tests" directory.
-
-#### Device Defender Update
-- Add a demo to illustrate the operation of Device Defender for the Windows Simulator and Microchip PIC32MZEF MCU.
-
-#### TI "Hello World" Build Failure Resolution
-- Address an issue where the "Hello World" demo did not build with TI CCS 7.3 in AFR 1.3.0 when downloaded from OCW.
-
-
-## V1.3.0 07/31/2018
-
-### New Features
-
-#### AFQP 1.0 Support
-This release of AFR has support for vendors who wish to have their ports qualified for Amazon FreeRTOS through the Amazon FreeRTOS Qualification Program (AFQP). This is the first public release of AFQP tests and documentation. A new top level "tests" directory is added to support this functionality. AFQP documents are available in "tests" directory. [Learn more.](https://docs.aws.amazon.com/freertos/latest/userguide/freertos-qualification-program.html)
-
-#### Device Defender 1.0 Support
-AWS IoT Device Defender is an AWS IoT security service that allows users to audit the configuration of their devices, monitor connected devices to detect abnormal behavior, and to mitigate security risks. It gives you the ability to enforce consistent security policies across your AWS IoT device fleet and respond quickly when devices are compromised. Device side support of this feature is part of this release. Devices supported are WinSim and Microchip PIC32MZEF. [Learn more.](https://docs.aws.amazon.com/freertos/latest/userguide/afr-device-defender-library.html)
-
-#### FreeRTOS+POSIX 1.0 Interface
-This release includes version 1.0.0 of FreeRTOS+POSIX.  FreeRTOS+POSIX is a POSIX compatibility layer that allows existing POSIX applications to run without modifications of FreeRTOS.  This release supports POSIX threads, mutexes, barriers, condition variables, semaphores, message queues, clocks, timers, and error numbers.  While most of the POSIX functions are implemented and up to specification, limitations in the FreeRTOS kernel precluded the standard implementations of certain functions.  The functions which differ from the POSIX specification are identified in their header files. Currently, FreeRTOS+POSIX is only used by drivers of the TI CC3220SF.
-
-### Updates
-
-#### FreeRTOS Kernel V10.0.1
-- Add Idle tick counter interface
-- Rename posix/ to FreeRTOS_POSIX/
-
-#### FreeRTOS+TCP V2.0.4
-- Fix issues raised by the Coverity scan
-    - Fix a typo ulRxWindowLength -> ulTxWindowLength in FreeRTOS_Sockets.c
-    - Fix strncmp length in FreeRTOS_DNS.c
-    - Fix styling in FreeRTOS_ARP.c
-- Fix a spelling typo ";east" -> "least" (response from a pull request)
-- Add auto check of network interfaces for WinSim
-
-#### MQTT Agent V1.1.2
-- Move MQTT metrics to agent
-
-#### mbedTLS-based PKCS #11 V1.0.3
-- Reduce the number of warnings generated
-
-#### PKCS #11 for LPC54018 IoT Module V1.0.1
-- Change project baudrate setting to resolve AFQP test failures
-
-#### Secure Sockets for NXP54018_IoT_Module V1.0.0 Beta 3
-- Update to latest NXP driver to address AFQP 1.0 test failures
-
-#### Secure Sockets for STM32L4 Discovery kit IoT node V1.0.0 Beta 2
-- Update to new Inventek driver to resolve AFQP 1.0 test failures
-
-#### Wi-Fi for Curiosity PIC32MZEF V1.0.3
-- Change Microchip network param to use a direct address instead of a section to reduce the size of the binary image to allow OTA to continue working.
-- Reduce number of warnings generated.
-
-#### Wi-Fi for LPC54018 IoT Module V1.0.1
-- Add fixes for Demo and DHCP.
-
-#### Wi-Fi STM32L4 Discovery kit IoT node V1.0.2
-- Update for release of AFQP 1.0
-
-#### Wi-Fi for CC3220SF-LAUNCHXL V1.0.2
-- Update for release of AFQP 1.0
-
----------------------------------------------------------------------------------------
-
-## V1.2.7 05/31/2018
-
-- Update the Texas Instruments SimpleLink CC3220SF SDK from version 1.40.01.00 to version 2.10.00.04.
-- Fix the MQTT Echo Demo (Hello World Demo) to avoid truncating received strings.
-- Modify the Getting Started scripts to check if the AWS CLI is configured.
-
-#### Secure Sockets for CC3220SF-LAUNCHXL V1.0.4
-- Update comments for SimpleLink CC3220SF SDK version 2.10.00.04.
-
---------------
-
-## V1.2.6 05/18/2018
-
-- Fix NXP MCUXpresso project build failure on Linux.
-
-----------------
-
-## V1.2.5 05/14/2018
-
-- Add support for Espressif's ESP32-DevKitC and ESP-WROVER-KIT.
-
-#### FreeRTOS+TCP V2.0.4
- - Add Espressif ESP32 network interface support.
-
-#### mbedTLS-based PKCS #11 V1.0.3
- - Implement C_DigestInit, C_DigestUpdate, and C_DigestFinal for SHA-256.
- - Implement C_GenerateKeyPair for non-persistent ECDSA P256.
-
-#### PKCS #11 for ESP32-DevKitC ESP-WROVER-KIT V1.0.0
- - Add support for Espressif's ESP32-DevKitC and ESP-WROVER-KIT.
-
-#### Wi-Fi STM32L4 Discovery kit IoT node V1.0.2
- - Bug fix to ensure that WIFI_ConnectAP() switches to the network parameters input,
-      even when already connected to a different set.
-
-#### Wi-Fi for ESP32-DevKitC ESP-WROVER-KIT V1.0.0
- - Add support for Espressif's ESP32-DevKitC and ESP-WROVER-KIT.
-
----------------------------------------------------------------------------------------
-
-## V1.2.4 05/01/2018
-
- - Upgrade to mbedTLS version 2.8.
- - Add MCUXpresso IDE demo project for the NXP LPC54018 IoT Module.
-
-#### Crypto V1.0.2
- - Minor updates due to mbedTLS crypto interface changes.
-
-#### FreeRTOS+TCP V2.0.3
- - Fix a bug where re-transmission and duplicated TCP packets would create a
-      computation underflow as well as a memory leak.
- - Add new public function FreeRTOS_UpdateMACAddress() to allow changing the MAC address
-      after FreeRTOS_IPInit. Sometimes the device MAC address is not available at the
-      time FreeRTOS_IPInit() is called, so it needs to be changed afterward.
- - Remove non-cryptographic rand() implementation.
- - Remove a static variable in functions prvGetHostByName() and prvCreateDNSSocket() to
-      make them threadsafe.
-
-#### Greengrass Discovery V1.0.3
- - Provide a helpful error message if the Greengrass Discovery JSON does not fit in
-      the supplied buffer.
-
-#### MQTT Agent V1.1.2
- - Bug fix to avoid socket leak if MQTT Connect fails after a successful TCP
-      connection.
- - Add support for disabling subscription management feature by defining the macro
-      mqttconfigENABLE_SUBSCRIPTION_MANAGEMENT as 0.
-
-#### OTA PAL for Curiosity PIC32MZEF V0.9.1
- - Update for PKCS #11 PAL layer API changes.
-
-#### OTA PAL for Windows Simulator V0.9.2
-- Minor restructuring of file locations.
-
-#### OTA PAL for CC3220SF-LAUNCHXL V0.9.3
- - Minor changes to enable test integration.
-
-#### OTA Agent V0.9.4
- - Minor restructuring of file locations.
-
-#### mbedTLS-based PKCS #11 V1.0.2
- - Combine the mbedTLS based PKCS #11 implementation from Curiosity PIC32MZEF,
-      LPC54018 IoT Module, Windows Simulator, and STM32L4 Discovery kit IoT node into a
-      single file.
- - Add support for public key verification of signatures.
- - Fix to free context structures on session failure.
- - Update C_OpenSession to use CKF_SERIAL_SESSION flag.
-
-#### PKCS #11 for Curiosity PIC32MZEF V1.0.2
- - Create port specific functions for certificate and key access:
-      PKCS11_PAL_SaveFile(), PKCS11_PAL_ReadFile(), PKCS11_PAL_ReleaseFileData().
-
-#### PKCS #11 for LPC54018 IoT Module V1.0.1
- - Create port specific functions for certificate and key access:
-      PKCS11_PAL_SaveFile(), PKCS11_PAL_ReadFile(), PKCS11_PAL_ReleaseFileData().
-
-#### PKCS #11 PAL for Windows Simulator V1.0.2
- - Create port specific functions for certificate and key access:
-      PKCS11_PAL_SaveFile(), PKCS11_PAL_ReadFile(), PKCS11_PAL_ReleaseFileData().
-
-#### PKCS #11 for STM32L4 Discovery kit IoT node V1.0.1
- - Create port specific functions for certificate and key access:
-      PKCS11_PAL_SaveFile(), PKCS11_PAL_ReadFile(), PKCS11_PAL_ReleaseFileData().
-
-#### PKCS #11 for CC3220SF-LAUNCHXL V1.0.2
- - PKCS #11 implementation for TI based on mbedTLS moved into this file.
-
-#### Secure Socket for FreeRTOS+TCP V1.1.2
- - Combine Secure Sockets implementation for Curiosity PIC32MZEF and Windows
-      Simulator into a single file.
- - Fix return value of SOCKETS_Socket on error.
- - Attempting to create an unsupported UDP socket now triggers an assert.
- - Add cryptographic random number generator function for TCP sequence numbers.
- - Update the Socket structure to keep track of a connection attempt and added
-      support of the ECONN error.
-
-#### Secure Sockets for LPC54018 IoT Module V1.0.0 Beta 3
- - Fix minor bug in SOCKETS_Recv().
-
-#### Secure Sockets for STM32L4 Discovery kit IoT node V1.0.0 Beta 2
- - Fix return value of SOCKETS_Close on error.
-
-#### Secure Sockets for CC3220SF-LAUNCHXL V1.0.3
- - Secure sockets printing is now controlled independently using the SOCKETS_PRINT
-      macro. SOCKETS_PRINT prints TI driver error codes.
-
-#### Shadow V1.0.3
- - Change names of configuration constants to be consistent with FreeRTOS style.
-
-#### TLS V1.1.1
- - Support AWS IoT Just-in-Time Registration (JITR) by sending optional
-      client-issuer certificate.
- - Use CKF_SERIAL_SESSION flag with PKCS #11.
-
-#### Wi-Fi for Curiosity PIC32MZEF V1.0.3
- - Update for setting the MAC Address in WIFI_On() by using new FreeRTOS+TCP
-      function FreeRTOS_UpdateMACAddress().
- - Redefine printing and assert stubs used in the Wi-Fi driver code.
- - Add implementation of WIFI_GetMAC().
- - Add implementation of WIFI_IsConnected().
- - Minor bug fixes.
-
-#### Wi-Fi for LPC54018 IoT Module V1.0.2
- - Add implementation of WIFI_IsConnected().
- - Fix max DNS name length redefinition.
- - Fix compiler errors in MCUXpresso IDE.
- - Minor bug fixes.
-
-#### Wi-Fi STM32L4 Discovery kit IoT node V1.0.1
- - Add implementation of WIFI_IsConnected().
- - Add NULL pointer checks throughout.
- - Minor bug fixes.
-
-#### Wi-Fi for CC3220SF-LAUNCHXL V1.0.2
- - Add implementation of WIFI_IsConnected().
- - Add NULL pointer checks throughout.
- - Minor bug fixes.
-
----------------------------------------------------------------------------------------
-
-## V1.2.3 03/29/2018
- - Fix TI IAR project build failure.
-
----------------------------------------------------------------------------------------
-
-## V1.2.2 02/27/2018
-
-#### OTA Agent V0.9.3
- - Formatting update.
-
-#### OTA PAL for Curiosity PIC32MZEF V0.9.0
- - Beta release of the OTA Update support for the Microchip Curiosity PIC32MZEF.
-
-#### PKCS #11 for Curiosity_PIC32MZEF V1.0.1
- - Add support for the management of OTA update code signing keys.
-
-#### Wi-Fi for Curiosity PIC32MZEF V1.0.1
- - Update to conditionally compile the entire file.
-
----------------------------------------------------------------------------------------
-
-## V1.2.1 02/23/2018
-
- - Add an IAR IDE demo project for the Texas Instruments CC3220SF-LAUNCHXL.
- - Add Wi-Fi support for the Microchip Curiosity PIC32MZEF.
-
-#### FreeRTOS+TCP V2.0.2
- - Improve NULL variable check in buffer management.
-
-#### MQTT Agent V1.1.1
- - Minor bug fix checking for a NULL pointer.
-
-#### OTA Agent V0.9.2
- - Update to support NULL OTA file handles.
-
-#### Amazon FreeRTOS OTA PAL for CC3220SF-LAUNCHXL V0.9.2
- - Update to support NULL OTA file handles.
-
-#### PKCS #11 for CC3220SF-LAUNCHXL V1.0.1
- - Add a dummy variable to a previously empty structure to fix IAR compiler errors.
-
-#### Secure Socket for Windows Simulator V1.1.1
- - Formatting update.
-
-#### Secure Sockets for CC3220SF-LAUNCHXL V1.0.2
- - Update to print SimpleLink driver-specific error codes when debugging.
- - Add error handling for non-blocking sockets.
- - Update socket option to return an error if security options are specified after
-      a connection.
-
-#### Wi-Fi for Curiosity PIC32MZEF V1.0.1
- - Update such that Wi-Fi disconnection waits until the link is down before
-      returning.
-
-#### Wi-Fi for CC3220SF-LAUNCHXL V1.0.1
- - Fix error in attempting to overwrite a const memory.
-
----------------------------------------------------------------------------------------
-
-## V1.2.0 02/06/2018
-
-#### Greengrass Discovery V1.0.2
- - Update to send all data until an error is received.
-
-#### MQTT Agent V1.1.0
- - Add support for ALPN. ALPN allows MQTT traffic to be sent to
-      the AWS IoT broker over port 443 instead of 8883.
-
-#### OTA Agent V0.9.1
- - Send a FAILED status from agent when a file too large for the platform
-      is received.
- - Rename some files.
-
-#### PKCS #11 for Windows Simulator
- - Add developer mode key provisioning support.
-
-#### Secure Socket for Curiosity PIC32MZEF V1.0.1
- - Add support for ALPN.
-
-#### Secure Socket for Windows Simulator V1.1.0
- - Add support for ALPN.
-
-#### Secure Sockets for CC3220SF-LAUNCHXL V1.0.1
-- Remove unnecessary server certificate storage on the client side.
-- Remove unnecessary global synchronization semaphore.
-- Update for other small bugs.
-
-#### Shadow V1.0.2
-- Fix error handling bugs.
-- Require client tokens.
-- Update for other small bugs.
-
-#### TLS V1.1.0
-- Add support for ALPN.
-
----------------------------------------
-
-## V1.1.0 12/20/2017
-
-#### Crypto V1.0.1
-- Fix compiler warning for the Microchip Curiosity PIC32MZEF.
-
-#### FreeRTOS+TCP V2.0.1
-- Add support for the Microchip Curiosity PIC32MZEF.
-
-#### FreeRTOS Kernel V10.0.1
-- Minor bug fixes to allow Linux and C++ builds.
-
-#### Greengrass Discovery V1.0.1
-- Reformat console display messages in order to better facilitate demos and debugging.
-
-#### MQTT Agent V1.0.1
-- The MQTT Agent now processes commands between successive socket reads to       enable faster command handling, especially when the connected socket is       receiving data continuously.
-
-#### OTA Agent V0.9.0
-- Beta release of OTA Update library for Amazon FreeRTOS. Includes support   for the Texas Instruments CC3220SF-LAUNCHXL and Windows Simulator.
-
-#### PKCS #11 for Curiosity PIC32MZEF V1.0.0 Beta 1
-- Add support for the Microchip Curiosity PIC32MZEF.
-
-#### Secure Socket for Curiosity PIC32MZEF V1.0.0
-- Add support for the Microchip Curiosity PIC32MZEF.
-
-#### Secure Sockets for LPC54018 IoT Module V1.0.0 Beta 2
-- Fix bugs in the Secure Sockets implementation for the NXP LPC54018 IoT       Module.
-
-#### Shadow V1.0.1
-- Fix compiler warning for the Microchip Curiosity PIC32MZEF.
-
-#### Wi-Fi for LPC54018 IoT Module V1.0.1
-- Change the Wi-Fi Connection timeout to 10 seconds.
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/LICENSE b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/LICENSE
deleted file mode 100644
index dff8fc7..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/LICENSE
+++ /dev/null
@@ -1,21 +0,0 @@
-MIT License
-
-Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/PreLoad.cmake b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/PreLoad.cmake
deleted file mode 100644
index 5ae9b96..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/PreLoad.cmake
+++ /dev/null
@@ -1,58 +0,0 @@
-# Set your compiler path here if it's not in the PATH environment variable.
-set(AFR_TOOLCHAIN_PATH "" CACHE INTERNAL "")
-
-# If VENDOR or BOARD is specified, try to find a match.
-if(DEFINED VENDOR OR DEFINED BOARD)
-    include("${CMAKE_CURRENT_LIST_DIR}/tools/cmake/afr_utils.cmake")
-
-    set(matched_boards)
-    afr_get_boards(all_boards)
-    foreach(board IN LISTS all_boards)
-        string(REGEX MATCH "${VENDOR}.*\\.${BOARD}.*" match "${board}")
-        if(match)
-            list(APPEND matched_boards "${match}")
-        endif()
-    endforeach()
-
-    list(LENGTH matched_boards size)
-    if(size EQUAL 0)
-        message(FATAL_ERROR "No matching board found, please check your VENDOR and BOARD value.")
-    endif()
-    if(NOT size EQUAL 1)
-        list(JOIN matched_boards ", " matched_boards)
-        message(FATAL_ERROR "Multiple matching boards found: ${matched_boards}")
-    else()
-        set(AFR_BOARD "${matched_boards}" CACHE INTERNAL "")
-    endif()
-endif()
-
-# If COMPILER is specified, set toolchain file to ${COMPILER}.cmake.
-if(DEFINED COMPILER)
-    if(DEFINED CMAKE_TOOLCHAIN_FILE)
-        get_filename_component(toolchain "${CMAKE_TOOLCHAIN_FILE}" NAME_WE)
-        if(NOT "${COMPILER}" STREQUAL "${toolchain}")
-            message(WARNING "CMAKE_TOOLCHAIN_FILE is already defined to ${toolchain}.cmake, you\
-                need to delete cache and reconfigure if you want to switch compiler.")
-        endif()
-    else()
-        set(toolchain_dir "${CMAKE_CURRENT_LIST_DIR}/tools/cmake/toolchains")
-        set(toolchain_file "${toolchain_dir}/${COMPILER}.cmake")
-        if(EXISTS "${toolchain_file}")
-            set(CMAKE_TOOLCHAIN_FILE "${toolchain_file}" CACHE INTERNAL "")
-        else()
-            message(FATAL_ERROR "Toolchain file \"${COMPILER}.cmake\" does not exist, please\
-                select one from \"cmake/toolchains\" folder.")
-        endif()
-    endif()
-endif()
-
-# Disable compiler checks when only outputing metadata.
-if(AFR_METADATA_MODE)
-    set(CMAKE_C_COMPILER_FORCED TRUE CACHE INTERNAL "")
-    set(CMAKE_CXX_COMPILER_FORCED TRUE CACHE INTERNAL "")
-endif()
-
-# Remove these helper variables from CMake cache.
-unset(VENDOR CACHE)
-unset(BOARD CACHE)
-unset(COMPILER CACHE)
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/directories.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/directories.txt
deleted file mode 100644
index 5528a9b..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/directories.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-This file describes the directories found at the root of the FreeRTOS
-distribution.
-
-demos:
-Contains a set of pre-configured demo projects for various target platforms.
-The projects in the demos directory build the libraries from the lib directory.
-
-doc:
-Contains Doxygen configuration, and board qualification guide.
-
-freertos_kernel:
-Contains FreeRTOS kernel distribution.
-
-libraries:
-Contains standard libraries, AWS libraries, and third-party libraries.
-
-projects:
-Contains IDE project files.
-
-tests:
-Contains Unity framework and test runner.
-
-vendors:
-Contains platform-specific ports, SDKs, and tools.
\ No newline at end of file
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/ChangeLogKSDK.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/ChangeLogKSDK.txt
deleted file mode 100644
index b453fb1..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/ChangeLogKSDK.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
-@page rtos_log RTOS Change Log
-
-@section FreeRTOS kernel for MCUXpresso SDK.
-The current version is FreeRTOS kernel 10.4.3-LTS-Patch-2 Original package is available at github.com/FreeRTOS/FreeRTOS-Kernel.
-
-  - 10.4.3_rev1
-      - Apply CM33 security fix from 10.4.3-LTS-Patch-2. See rtos\freertos\freertos_kernel\History.txt
-      - Apply CM33 security fix from 10.4.3-LTS-Patch-1. See rtos\freertos\freertos_kernel\History.txt
-  - 10.4.3_rev0
-      - update amazon freertos version.
-
-  - 10.4.3_rev0
-      - update amazon freertos version.
-
-  - 9.0.0_rev3
-    - New features:
-      - Tickless idle mode support for Cortex-A7. Add fsl_tickless_epit.c and fsl_tickless_generic.h in portable/IAR/ARM_CA9 folder.
-      - Enabled float context saving in IAR for Cortex-A7. Added configUSE_TASK_FPU_SUPPORT macros. Modified port.c and portmacro.h in portable/IAR/ARM_CA9 folder.
-    - Other changes:
-      - Transformed ARM_CM core specific tickless low power support into generic form under freertos/Source/portable/low_power_tickless/.
-
-  - 9.0.0_rev2
-    - New features:
-      - Enabled MCUXpresso thread aware debugging. Add freertos_tasks_c_additions.h and configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H and configFRTOS_MEMORY_SCHEME macros.
-
-  - 9.0.0_rev1
-    - New features:
-      - Enabled -flto optimization in GCC by adding __attribute__((used)) for vTaskSwitchContext.
-      - Enabled KDS Task Aware Debugger. Apply FreeRTOS patch to enable configRECORD_STACK_HIGH_ADDRESS macro. Modified files are task.c and FreeRTOS.h.
-
-  - 9.0.0_rev0
-    - New features:
-      - Example freertos_sem_static.
-      - Static allocation support RTOS driver wrappers.
-    - Other changes:
-      - Tickless idle rework. Support for different timers is in separated files (fsl_tickless_systick.c, fsl_tickless_lptmr.c).
-      - Removed configuration option configSYSTICK_USE_LOW_POWER_TIMER. Low power timer is now selected by linking of apropriate file fsl_tickless_lptmr.c.
-      - Removed configOVERRIDE_DEFAULT_TICK_CONFIGURATION in RVDS port. Use of __attribute__((weak)) is the preferred solution. Not same as _weak!
-
-  - 8.2.3
-    - New features:
-      - Tickless idle mode support.
-      - Added template application for Kinetis Expert (KEx) tool (template_application).
-    - Other changes:
-      - Folder structure reduction. Keep only Kinetis related parts.
-
-*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/README.md b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/README.md
deleted file mode 100644
index 1cc1b84..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/README.md
+++ /dev/null
@@ -1,39 +0,0 @@
-## Getting started
-This repository contains FreeRTOS kernel source/header files and kernel ports only. This repository is referenced as a submodule in [FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS) repository, which contains pre-configured demo application projects under ```FreeRTOS/Demo``` directory. 
-
-The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects.  That way you will have the correct FreeRTOS source files included, and the correct include paths configured.  Once a demo application is building and executing you can remove the demo application files, and start to add in your own application source files.  See the [FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html) for detailed instructions and other useful links.
-
-Additionally, for FreeRTOS kernel feature information refer to the [Developer Documentation](https://www.FreeRTOS.org/features.html), and [API Reference](https://www.FreeRTOS.org/a00106.html).
-
-### Getting help
-If you have any questions or need assistance troubleshooting your FreeRTOS project, we have an active community that can help on the [FreeRTOS Community Support Forum](https://forums.freertos.org).
-
-## Cloning this repository
-
-To clone using HTTPS:
-```
-git clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git
-```
-Using SSH:
-```
-git clone git@github.com:FreeRTOS/FreeRTOS-Kernel.git
-```
-
-## Repository structure
-- The root of this repository contains the three files that are common to 
-every port - list.c, queue.c and tasks.c.  The kernel is contained within these 
-three files.  croutine.c implements the optional co-routine functionality - which
-is normally only used on very memory limited systems.
-
-- The ```./portable``` directory contains the files that are specific to a particular microcontroller and/or compiler. 
-See the readme file in the ```./portable``` directory for more information.
-
-- The ```./include``` directory contains the real time kernel header files.
-
-### Code Formatting
-FreeRTOS files are formatted using the "uncrustify" tool. The configuration file used by uncrustify can be found in the [FreeRTOS/FreeRTOS repository](https://github.com/FreeRTOS/FreeRTOS/blob/master/tools/uncrustify.cfg). 
-
-### Spelling
-*lexicon.txt* contains words that are not traditionally found in an English dictionary. It is used by the spellchecker to verify the various jargon, variable names, and other odd words used in the FreeRTOS code base. If your pull request fails to pass the spelling and you believe this is a mistake, then add the word to *lexicon.txt*. 
-Note that only the FreeRTOS Kernel source files are checked for proper spelling, the portable section is ignored.
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/croutine.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/croutine.c
deleted file mode 100644
index 271f4b8..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/croutine.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "croutine.h"
-
-/* Remove the whole file is co-routines are not being used. */
-#if ( configUSE_CO_ROUTINES != 0 )
-
-/*
- * Some kernel aware debuggers require data to be viewed to be global, rather
- * than file scope.
- */
-    #ifdef portREMOVE_STATIC_QUALIFIER
-        #define static
-    #endif
-
-
-/* Lists for ready and blocked co-routines. --------------------*/
-    static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */
-    static List_t xDelayedCoRoutineList1;                                   /*< Delayed co-routines. */
-    static List_t xDelayedCoRoutineList2;                                   /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
-    static List_t * pxDelayedCoRoutineList = NULL;                          /*< Points to the delayed co-routine list currently being used. */
-    static List_t * pxOverflowDelayedCoRoutineList = NULL;                  /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
-    static List_t xPendingReadyCoRoutineList;                               /*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
-
-/* Other file private variables. --------------------------------*/
-    CRCB_t * pxCurrentCoRoutine = NULL;
-    static UBaseType_t uxTopCoRoutineReadyPriority = 0;
-    static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
-
-/* The initial state of the co-routine when it is created. */
-    #define corINITIAL_STATE    ( 0 )
-
-/*
- * Place the co-routine represented by pxCRCB into the appropriate ready queue
- * for the priority.  It is inserted at the end of the list.
- *
- * This macro accesses the co-routine ready lists and therefore must not be
- * used from within an ISR.
- */
-    #define prvAddCoRoutineToReadyQueue( pxCRCB )                                                                       \
-    {                                                                                                                   \
-        if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority )                                                          \
-        {                                                                                                               \
-            uxTopCoRoutineReadyPriority = pxCRCB->uxPriority;                                                           \
-        }                                                                                                               \
-        vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \
-    }
-
-/*
- * Utility to ready all the lists used by the scheduler.  This is called
- * automatically upon the creation of the first co-routine.
- */
-    static void prvInitialiseCoRoutineLists( void );
-
-/*
- * Co-routines that are readied by an interrupt cannot be placed directly into
- * the ready lists (there is no mutual exclusion).  Instead they are placed in
- * in the pending ready list in order that they can later be moved to the ready
- * list by the co-routine scheduler.
- */
-    static void prvCheckPendingReadyList( void );
-
-/*
- * Macro that looks at the list of co-routines that are currently delayed to
- * see if any require waking.
- *
- * Co-routines are stored in the queue in the order of their wake time -
- * meaning once one co-routine has been found whose timer has not expired
- * we need not look any further down the list.
- */
-    static void prvCheckDelayedList( void );
-
-/*-----------------------------------------------------------*/
-
-    BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,
-                                 UBaseType_t uxPriority,
-                                 UBaseType_t uxIndex )
-    {
-        BaseType_t xReturn;
-        CRCB_t * pxCoRoutine;
-
-        /* Allocate the memory that will store the co-routine control block. */
-        pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
-
-        if( pxCoRoutine )
-        {
-            /* If pxCurrentCoRoutine is NULL then this is the first co-routine to
-            * be created and the co-routine data structures need initialising. */
-            if( pxCurrentCoRoutine == NULL )
-            {
-                pxCurrentCoRoutine = pxCoRoutine;
-                prvInitialiseCoRoutineLists();
-            }
-
-            /* Check the priority is within limits. */
-            if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
-            {
-                uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
-            }
-
-            /* Fill out the co-routine control block from the function parameters. */
-            pxCoRoutine->uxState = corINITIAL_STATE;
-            pxCoRoutine->uxPriority = uxPriority;
-            pxCoRoutine->uxIndex = uxIndex;
-            pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
-
-            /* Initialise all the other co-routine control block parameters. */
-            vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
-            vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
-
-            /* Set the co-routine control block as a link back from the ListItem_t.
-             * This is so we can get back to the containing CRCB from a generic item
-             * in a list. */
-            listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
-            listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
-
-            /* Event lists are always in priority order. */
-            listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
-
-            /* Now the co-routine has been initialised it can be added to the ready
-             * list at the correct priority. */
-            prvAddCoRoutineToReadyQueue( pxCoRoutine );
-
-            xReturn = pdPASS;
-        }
-        else
-        {
-            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
-        }
-
-        return xReturn;
-    }
-/*-----------------------------------------------------------*/
-
-    void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
-                                     List_t * pxEventList )
-    {
-        TickType_t xTimeToWake;
-
-        /* Calculate the time to wake - this may overflow but this is
-         * not a problem. */
-        xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
-
-        /* We must remove ourselves from the ready list before adding
-         * ourselves to the blocked list as the same list item is used for
-         * both lists. */
-        ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
-
-        /* The list item will be inserted in wake time order. */
-        listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
-
-        if( xTimeToWake < xCoRoutineTickCount )
-        {
-            /* Wake time has overflowed.  Place this item in the
-             * overflow list. */
-            vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
-        }
-        else
-        {
-            /* The wake time has not overflowed, so we can use the
-             * current block list. */
-            vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
-        }
-
-        if( pxEventList )
-        {
-            /* Also add the co-routine to an event list.  If this is done then the
-             * function must be called with interrupts disabled. */
-            vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
-        }
-    }
-/*-----------------------------------------------------------*/
-
-    static void prvCheckPendingReadyList( void )
-    {
-        /* Are there any co-routines waiting to get moved to the ready list?  These
-         * are co-routines that have been readied by an ISR.  The ISR cannot access
-         * the ready lists itself. */
-        while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
-        {
-            CRCB_t * pxUnblockedCRCB;
-
-            /* The pending ready list can be accessed by an ISR. */
-            portDISABLE_INTERRUPTS();
-            {
-                pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyCoRoutineList ) );
-                ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
-            }
-            portENABLE_INTERRUPTS();
-
-            ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
-            prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
-        }
-    }
-/*-----------------------------------------------------------*/
-
-    static void prvCheckDelayedList( void )
-    {
-        CRCB_t * pxCRCB;
-
-        xPassedTicks = xTaskGetTickCount() - xLastTickCount;
-
-        while( xPassedTicks )
-        {
-            xCoRoutineTickCount++;
-            xPassedTicks--;
-
-            /* If the tick count has overflowed we need to swap the ready lists. */
-            if( xCoRoutineTickCount == 0 )
-            {
-                List_t * pxTemp;
-
-                /* Tick count has overflowed so we need to swap the delay lists.  If there are
-                 * any items in pxDelayedCoRoutineList here then there is an error! */
-                pxTemp = pxDelayedCoRoutineList;
-                pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
-                pxOverflowDelayedCoRoutineList = pxTemp;
-            }
-
-            /* See if this tick has made a timeout expire. */
-            while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
-            {
-                pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
-
-                if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
-                {
-                    /* Timeout not yet expired. */
-                    break;
-                }
-
-                portDISABLE_INTERRUPTS();
-                {
-                    /* The event could have occurred just before this critical
-                     *  section.  If this is the case then the generic list item will
-                     *  have been moved to the pending ready list and the following
-                     *  line is still valid.  Also the pvContainer parameter will have
-                     *  been set to NULL so the following lines are also valid. */
-                    ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
-
-                    /* Is the co-routine waiting on an event also? */
-                    if( pxCRCB->xEventListItem.pxContainer )
-                    {
-                        ( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
-                    }
-                }
-                portENABLE_INTERRUPTS();
-
-                prvAddCoRoutineToReadyQueue( pxCRCB );
-            }
-        }
-
-        xLastTickCount = xCoRoutineTickCount;
-    }
-/*-----------------------------------------------------------*/
-
-    void vCoRoutineSchedule( void )
-    {
-        /* Only run a co-routine after prvInitialiseCoRoutineLists() has been
-         * called.  prvInitialiseCoRoutineLists() is called automatically when a
-         * co-routine is created. */
-        if( pxDelayedCoRoutineList != NULL )
-        {
-            /* See if any co-routines readied by events need moving to the ready lists. */
-            prvCheckPendingReadyList();
-
-            /* See if any delayed co-routines have timed out. */
-            prvCheckDelayedList();
-
-            /* Find the highest priority queue that contains ready co-routines. */
-            while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
-            {
-                if( uxTopCoRoutineReadyPriority == 0 )
-                {
-                    /* No more co-routines to check. */
-                    return;
-                }
-
-                --uxTopCoRoutineReadyPriority;
-            }
-
-            /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
-             * of the same priority get an equal share of the processor time. */
-            listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
-
-            /* Call the co-routine. */
-            ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
-        }
-    }
-/*-----------------------------------------------------------*/
-
-    static void prvInitialiseCoRoutineLists( void )
-    {
-        UBaseType_t uxPriority;
-
-        for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
-        {
-            vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
-        }
-
-        vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
-        vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
-        vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
-
-        /* Start with pxDelayedCoRoutineList using list1 and the
-         * pxOverflowDelayedCoRoutineList using list2. */
-        pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
-        pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
-    }
-/*-----------------------------------------------------------*/
-
-    BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList )
-    {
-        CRCB_t * pxUnblockedCRCB;
-        BaseType_t xReturn;
-
-        /* This function is called from within an interrupt.  It can only access
-         * event lists and the pending ready list.  This function assumes that a
-         * check has already been made to ensure pxEventList is not empty. */
-        pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
-        ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
-        vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
-
-        if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
-        {
-            xReturn = pdTRUE;
-        }
-        else
-        {
-            xReturn = pdFALSE;
-        }
-
-        return xReturn;
-    }
-
-#endif /* configUSE_CO_ROUTINES == 0 */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/event_groups.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/event_groups.c
deleted file mode 100644
index 31e2e3f..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/event_groups.c
+++ /dev/null
@@ -1,771 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers.  That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* FreeRTOS includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "timers.h"
-#include "event_groups.h"
-
-/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
- * for the header files above, but not in this file, in order to generate the
- * correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */
-
-/* The following bit fields convey control information in a task's event list
- * item value.  It is important they don't clash with the
- * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
-#if configUSE_16_BIT_TICKS == 1
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x0100U
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x0200U
-    #define eventWAIT_FOR_ALL_BITS           0x0400U
-    #define eventEVENT_BITS_CONTROL_BYTES    0xff00U
-#else
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x01000000UL
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x02000000UL
-    #define eventWAIT_FOR_ALL_BITS           0x04000000UL
-    #define eventEVENT_BITS_CONTROL_BYTES    0xff000000UL
-#endif
-
-typedef struct EventGroupDef_t
-{
-    EventBits_t uxEventBits;
-    List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */
-
-    #if ( configUSE_TRACE_FACILITY == 1 )
-        UBaseType_t uxEventGroupNumber;
-    #endif
-
-    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-        uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
-    #endif
-} EventGroup_t;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Test the bits set in uxCurrentEventBits to see if the wait condition is met.
- * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is
- * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor
- * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the
- * wait condition is met if any of the bits set in uxBitsToWait for are also set
- * in uxCurrentEventBits.
- */
-static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
-                                        const EventBits_t uxBitsToWaitFor,
-                                        const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-    EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer )
-    {
-        EventGroup_t * pxEventBits;
-
-        /* A StaticEventGroup_t object must be provided. */
-        configASSERT( pxEventGroupBuffer );
-
-        #if ( configASSERT_DEFINED == 1 )
-            {
-                /* Sanity check that the size of the structure used to declare a
-                 * variable of type StaticEventGroup_t equals the size of the real
-                 * event group structure. */
-                volatile size_t xSize = sizeof( StaticEventGroup_t );
-                configASSERT( xSize == sizeof( EventGroup_t ) );
-            } /*lint !e529 xSize is referenced if configASSERT() is defined. */
-        #endif /* configASSERT_DEFINED */
-
-        /* The user has provided a statically allocated event group - use it. */
-        pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
-
-        if( pxEventBits != NULL )
-        {
-            pxEventBits->uxEventBits = 0;
-            vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
-
-            #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-                {
-                    /* Both static and dynamic allocation can be used, so note that
-                     * this event group was created statically in case the event group
-                     * is later deleted. */
-                    pxEventBits->ucStaticallyAllocated = pdTRUE;
-                }
-            #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-
-            traceEVENT_GROUP_CREATE( pxEventBits );
-        }
-        else
-        {
-            /* xEventGroupCreateStatic should only ever be called with
-             * pxEventGroupBuffer pointing to a pre-allocated (compile time
-             * allocated) StaticEventGroup_t variable. */
-            traceEVENT_GROUP_CREATE_FAILED();
-        }
-
-        return pxEventBits;
-    }
-
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-    EventGroupHandle_t xEventGroupCreate( void )
-    {
-        EventGroup_t * pxEventBits;
-
-        /* Allocate the event group.  Justification for MISRA deviation as
-         * follows:  pvPortMalloc() always ensures returned memory blocks are
-         * aligned per the requirements of the MCU stack.  In this case
-         * pvPortMalloc() must return a pointer that is guaranteed to meet the
-         * alignment requirements of the EventGroup_t structure - which (if you
-         * follow it through) is the alignment requirements of the TickType_t type
-         * (EventBits_t being of TickType_t itself).  Therefore, whenever the
-         * stack alignment requirements are greater than or equal to the
-         * TickType_t alignment requirements the cast is safe.  In other cases,
-         * where the natural word size of the architecture is less than
-         * sizeof( TickType_t ), the TickType_t variables will be accessed in two
-         * or more reads operations, and the alignment requirements is only that
-         * of each individual read. */
-        pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */
-
-        if( pxEventBits != NULL )
-        {
-            pxEventBits->uxEventBits = 0;
-            vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
-
-            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-                {
-                    /* Both static and dynamic allocation can be used, so note this
-                     * event group was allocated statically in case the event group is
-                     * later deleted. */
-                    pxEventBits->ucStaticallyAllocated = pdFALSE;
-                }
-            #endif /* configSUPPORT_STATIC_ALLOCATION */
-
-            traceEVENT_GROUP_CREATE( pxEventBits );
-        }
-        else
-        {
-            traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */
-        }
-
-        return pxEventBits;
-    }
-
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
-                             const EventBits_t uxBitsToSet,
-                             const EventBits_t uxBitsToWaitFor,
-                             TickType_t xTicksToWait )
-{
-    EventBits_t uxOriginalBitValue, uxReturn;
-    EventGroup_t * pxEventBits = xEventGroup;
-    BaseType_t xAlreadyYielded;
-    BaseType_t xTimeoutOccurred = pdFALSE;
-
-    configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
-    configASSERT( uxBitsToWaitFor != 0 );
-    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-        {
-            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-        }
-    #endif
-
-    vTaskSuspendAll();
-    {
-        uxOriginalBitValue = pxEventBits->uxEventBits;
-
-        ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
-
-        if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
-        {
-            /* All the rendezvous bits are now set - no need to block. */
-            uxReturn = ( uxOriginalBitValue | uxBitsToSet );
-
-            /* Rendezvous always clear the bits.  They will have been cleared
-             * already unless this is the only task in the rendezvous. */
-            pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
-
-            xTicksToWait = 0;
-        }
-        else
-        {
-            if( xTicksToWait != ( TickType_t ) 0 )
-            {
-                traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
-
-                /* Store the bits that the calling task is waiting for in the
-                 * task's event list item so the kernel knows when a match is
-                 * found.  Then enter the blocked state. */
-                vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
-
-                /* This assignment is obsolete as uxReturn will get set after
-                 * the task unblocks, but some compilers mistakenly generate a
-                 * warning about uxReturn being returned without being set if the
-                 * assignment is omitted. */
-                uxReturn = 0;
-            }
-            else
-            {
-                /* The rendezvous bits were not set, but no block time was
-                 * specified - just return the current event bit value. */
-                uxReturn = pxEventBits->uxEventBits;
-                xTimeoutOccurred = pdTRUE;
-            }
-        }
-    }
-    xAlreadyYielded = xTaskResumeAll();
-
-    if( xTicksToWait != ( TickType_t ) 0 )
-    {
-        if( xAlreadyYielded == pdFALSE )
-        {
-            portYIELD_WITHIN_API();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        /* The task blocked to wait for its required bits to be set - at this
-         * point either the required bits were set or the block time expired.  If
-         * the required bits were set they will have been stored in the task's
-         * event list item, and they should now be retrieved then cleared. */
-        uxReturn = uxTaskResetEventItemValue();
-
-        if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
-        {
-            /* The task timed out, just return the current event bit value. */
-            taskENTER_CRITICAL();
-            {
-                uxReturn = pxEventBits->uxEventBits;
-
-                /* Although the task got here because it timed out before the
-                 * bits it was waiting for were set, it is possible that since it
-                 * unblocked another task has set the bits.  If this is the case
-                 * then it needs to clear the bits before exiting. */
-                if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
-                {
-                    pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            taskEXIT_CRITICAL();
-
-            xTimeoutOccurred = pdTRUE;
-        }
-        else
-        {
-            /* The task unblocked because the bits were set. */
-        }
-
-        /* Control bits might be set as the task had blocked should not be
-         * returned. */
-        uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
-    }
-
-    traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
-
-    /* Prevent compiler warnings when trace macros are not used. */
-    ( void ) xTimeoutOccurred;
-
-    return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 const BaseType_t xClearOnExit,
-                                 const BaseType_t xWaitForAllBits,
-                                 TickType_t xTicksToWait )
-{
-    EventGroup_t * pxEventBits = xEventGroup;
-    EventBits_t uxReturn, uxControlBits = 0;
-    BaseType_t xWaitConditionMet, xAlreadyYielded;
-    BaseType_t xTimeoutOccurred = pdFALSE;
-
-    /* Check the user is not attempting to wait on the bits used by the kernel
-     * itself, and that at least one bit is being requested. */
-    configASSERT( xEventGroup );
-    configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
-    configASSERT( uxBitsToWaitFor != 0 );
-    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-        {
-            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-        }
-    #endif
-
-    vTaskSuspendAll();
-    {
-        const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
-
-        /* Check to see if the wait condition is already met or not. */
-        xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
-
-        if( xWaitConditionMet != pdFALSE )
-        {
-            /* The wait condition has already been met so there is no need to
-             * block. */
-            uxReturn = uxCurrentEventBits;
-            xTicksToWait = ( TickType_t ) 0;
-
-            /* Clear the wait bits if requested to do so. */
-            if( xClearOnExit != pdFALSE )
-            {
-                pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else if( xTicksToWait == ( TickType_t ) 0 )
-        {
-            /* The wait condition has not been met, but no block time was
-             * specified, so just return the current value. */
-            uxReturn = uxCurrentEventBits;
-            xTimeoutOccurred = pdTRUE;
-        }
-        else
-        {
-            /* The task is going to block to wait for its required bits to be
-             * set.  uxControlBits are used to remember the specified behaviour of
-             * this call to xEventGroupWaitBits() - for use when the event bits
-             * unblock the task. */
-            if( xClearOnExit != pdFALSE )
-            {
-                uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            if( xWaitForAllBits != pdFALSE )
-            {
-                uxControlBits |= eventWAIT_FOR_ALL_BITS;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            /* Store the bits that the calling task is waiting for in the
-             * task's event list item so the kernel knows when a match is
-             * found.  Then enter the blocked state. */
-            vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
-
-            /* This is obsolete as it will get set after the task unblocks, but
-             * some compilers mistakenly generate a warning about the variable
-             * being returned without being set if it is not done. */
-            uxReturn = 0;
-
-            traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
-        }
-    }
-    xAlreadyYielded = xTaskResumeAll();
-
-    if( xTicksToWait != ( TickType_t ) 0 )
-    {
-        if( xAlreadyYielded == pdFALSE )
-        {
-            portYIELD_WITHIN_API();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        /* The task blocked to wait for its required bits to be set - at this
-         * point either the required bits were set or the block time expired.  If
-         * the required bits were set they will have been stored in the task's
-         * event list item, and they should now be retrieved then cleared. */
-        uxReturn = uxTaskResetEventItemValue();
-
-        if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
-        {
-            taskENTER_CRITICAL();
-            {
-                /* The task timed out, just return the current event bit value. */
-                uxReturn = pxEventBits->uxEventBits;
-
-                /* It is possible that the event bits were updated between this
-                 * task leaving the Blocked state and running again. */
-                if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
-                {
-                    if( xClearOnExit != pdFALSE )
-                    {
-                        pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                xTimeoutOccurred = pdTRUE;
-            }
-            taskEXIT_CRITICAL();
-        }
-        else
-        {
-            /* The task unblocked because the bits were set. */
-        }
-
-        /* The task blocked so control bits may have been set. */
-        uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
-    }
-
-    traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
-
-    /* Prevent compiler warnings when trace macros are not used. */
-    ( void ) xTimeoutOccurred;
-
-    return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                  const EventBits_t uxBitsToClear )
-{
-    EventGroup_t * pxEventBits = xEventGroup;
-    EventBits_t uxReturn;
-
-    /* Check the user is not attempting to clear the bits used by the kernel
-     * itself. */
-    configASSERT( xEventGroup );
-    configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
-
-    taskENTER_CRITICAL();
-    {
-        traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
-
-        /* The value returned is the event group value prior to the bits being
-         * cleared. */
-        uxReturn = pxEventBits->uxEventBits;
-
-        /* Clear the bits. */
-        pxEventBits->uxEventBits &= ~uxBitsToClear;
-    }
-    taskEXIT_CRITICAL();
-
-    return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
-
-    BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
-                                            const EventBits_t uxBitsToClear )
-    {
-        BaseType_t xReturn;
-
-        traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
-        xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
-
-        return xReturn;
-    }
-
-#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
-{
-    UBaseType_t uxSavedInterruptStatus;
-    EventGroup_t const * const pxEventBits = xEventGroup;
-    EventBits_t uxReturn;
-
-    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-    {
-        uxReturn = pxEventBits->uxEventBits;
-    }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-    return uxReturn;
-} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                const EventBits_t uxBitsToSet )
-{
-    ListItem_t * pxListItem, * pxNext;
-    ListItem_t const * pxListEnd;
-    List_t const * pxList;
-    EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
-    EventGroup_t * pxEventBits = xEventGroup;
-    BaseType_t xMatchFound = pdFALSE;
-
-    /* Check the user is not attempting to set the bits used by the kernel
-     * itself. */
-    configASSERT( xEventGroup );
-    configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
-
-    pxList = &( pxEventBits->xTasksWaitingForBits );
-    pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-    vTaskSuspendAll();
-    {
-        traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
-
-        pxListItem = listGET_HEAD_ENTRY( pxList );
-
-        /* Set the bits. */
-        pxEventBits->uxEventBits |= uxBitsToSet;
-
-        /* See if the new bit value should unblock any tasks. */
-        while( pxListItem != pxListEnd )
-        {
-            pxNext = listGET_NEXT( pxListItem );
-            uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
-            xMatchFound = pdFALSE;
-
-            /* Split the bits waited for from the control bits. */
-            uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
-            uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
-
-            if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
-            {
-                /* Just looking for single bit being set. */
-                if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
-                {
-                    xMatchFound = pdTRUE;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
-            {
-                /* All bits are set. */
-                xMatchFound = pdTRUE;
-            }
-            else
-            {
-                /* Need all bits to be set, but not all the bits were set. */
-            }
-
-            if( xMatchFound != pdFALSE )
-            {
-                /* The bits match.  Should the bits be cleared on exit? */
-                if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
-                {
-                    uxBitsToClear |= uxBitsWaitedFor;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                /* Store the actual event flag value in the task's event list
-                 * item before removing the task from the event list.  The
-                 * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
-                 * that is was unblocked due to its required bits matching, rather
-                 * than because it timed out. */
-                vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
-            }
-
-            /* Move onto the next list item.  Note pxListItem->pxNext is not
-             * used here as the list item may have been removed from the event list
-             * and inserted into the ready/pending reading list. */
-            pxListItem = pxNext;
-        }
-
-        /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
-         * bit was set in the control word. */
-        pxEventBits->uxEventBits &= ~uxBitsToClear;
-    }
-    ( void ) xTaskResumeAll();
-
-    return pxEventBits->uxEventBits;
-}
-/*-----------------------------------------------------------*/
-
-void vEventGroupDelete( EventGroupHandle_t xEventGroup )
-{
-    EventGroup_t * pxEventBits = xEventGroup;
-    const List_t * pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
-
-    vTaskSuspendAll();
-    {
-        traceEVENT_GROUP_DELETE( xEventGroup );
-
-        while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
-        {
-            /* Unblock the task, returning 0 as the event list is being deleted
-             * and cannot therefore have any bits set. */
-            configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
-            vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
-        }
-
-        #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
-            {
-                /* The event group can only have been allocated dynamically - free
-                 * it again. */
-                vPortFree( pxEventBits );
-            }
-        #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-            {
-                /* The event group could have been allocated statically or
-                 * dynamically, so check before attempting to free the memory. */
-                if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
-                {
-                    vPortFree( pxEventBits );
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-    }
-    ( void ) xTaskResumeAll();
-}
-/*-----------------------------------------------------------*/
-
-/* For internal use only - execute a 'set bits' command that was pended from
- * an interrupt. */
-void vEventGroupSetBitsCallback( void * pvEventGroup,
-                                 const uint32_t ulBitsToSet )
-{
-    ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
-}
-/*-----------------------------------------------------------*/
-
-/* For internal use only - execute a 'clear bits' command that was pended from
- * an interrupt. */
-void vEventGroupClearBitsCallback( void * pvEventGroup,
-                                   const uint32_t ulBitsToClear )
-{
-    ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
-}
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
-                                        const EventBits_t uxBitsToWaitFor,
-                                        const BaseType_t xWaitForAllBits )
-{
-    BaseType_t xWaitConditionMet = pdFALSE;
-
-    if( xWaitForAllBits == pdFALSE )
-    {
-        /* Task only has to wait for one bit within uxBitsToWaitFor to be
-         * set.  Is one already set? */
-        if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
-        {
-            xWaitConditionMet = pdTRUE;
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    else
-    {
-        /* Task has to wait for all the bits in uxBitsToWaitFor to be set.
-         * Are they set already? */
-        if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
-        {
-            xWaitConditionMet = pdTRUE;
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-
-    return xWaitConditionMet;
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
-
-    BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToSet,
-                                          BaseType_t * pxHigherPriorityTaskWoken )
-    {
-        BaseType_t xReturn;
-
-        traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
-        xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
-
-        return xReturn;
-    }
-
-#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    UBaseType_t uxEventGroupGetNumber( void * xEventGroup )
-    {
-        UBaseType_t xReturn;
-        EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
-
-        if( xEventGroup == NULL )
-        {
-            xReturn = 0;
-        }
-        else
-        {
-            xReturn = pxEventBits->uxEventGroupNumber;
-        }
-
-        return xReturn;
-    }
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    void vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber )
-    {
-        ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
-    }
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/FreeRTOS.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/FreeRTOS.h
deleted file mode 100644
index 941aaf2..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/FreeRTOS.h
+++ /dev/null
@@ -1,1380 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * Copyright 2019-2020 MicroEJ Corp. This file has been modified by MicroEJ Corp.
- * 1. Patch for SystemView support
- *
- */
-
-#ifndef INC_FREERTOS_H
-#define INC_FREERTOS_H
-
-/*
- * Include the generic headers required for the FreeRTOS port being used.
- */
-#include 
-
-/*
- * If stdint.h cannot be located then:
- *   + If using GCC ensure the -nostdint options is *not* being used.
- *   + Ensure the project's include path includes the directory in which your
- *     compiler stores stdint.h.
- *   + Set any compiler options necessary for it to support C99, as technically
- *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any
- *     other way).
- *   + The FreeRTOS download includes a simple stdint.h definition that can be
- *     used in cases where none is provided by the compiler.  The files only
- *     contains the typedefs required to build FreeRTOS.  Read the instructions
- *     in FreeRTOS/source/stdint.readme for more information.
- */
-#include      /* READ COMMENT ABOVE. */
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/* Application specific configuration options. */
-#include "FreeRTOSConfig.h"
-
-/* Basic FreeRTOS definitions. */
-#include "projdefs.h"
-
-/* Definitions specific to the port being used. */
-#include "portable.h"
-
-/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */
-#ifndef configUSE_NEWLIB_REENTRANT
-    #define configUSE_NEWLIB_REENTRANT    0
-#endif
-
-/* Required if struct _reent is used. */
-#if ( configUSE_NEWLIB_REENTRANT == 1 )
-    #include 
-#endif
-
-/*
- * Check all the required application specific macros have been defined.
- * These macros are application specific and (as downloaded) are defined
- * within FreeRTOSConfig.h.
- */
-
-#ifndef configMINIMAL_STACK_SIZE
-    #error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.
-#endif
-
-#ifndef configMAX_PRIORITIES
-    #error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#if configMAX_PRIORITIES < 1
-    #error configMAX_PRIORITIES must be defined to be greater than or equal to 1.
-#endif
-
-#ifndef configUSE_PREEMPTION
-    #error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef configUSE_IDLE_HOOK
-    #error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef configUSE_TICK_HOOK
-    #error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef configUSE_16_BIT_TICKS
-    #error Missing definition:  configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef configUSE_CO_ROUTINES
-    #define configUSE_CO_ROUTINES    0
-#endif
-
-#ifndef INCLUDE_vTaskPrioritySet
-    #define INCLUDE_vTaskPrioritySet    0
-#endif
-
-#ifndef INCLUDE_uxTaskPriorityGet
-    #define INCLUDE_uxTaskPriorityGet    0
-#endif
-
-#ifndef INCLUDE_vTaskDelete
-    #define INCLUDE_vTaskDelete    0
-#endif
-
-#ifndef INCLUDE_vTaskSuspend
-    #define INCLUDE_vTaskSuspend    0
-#endif
-
-#ifdef INCLUDE_xTaskDelayUntil
-    #ifdef INCLUDE_vTaskDelayUntil
-        /* INCLUDE_vTaskDelayUntil was replaced by INCLUDE_xTaskDelayUntil.  Backward
-         * compatibility is maintained if only one or the other is defined, but
-         * there is a conflict if both are defined. */
-        #error INCLUDE_vTaskDelayUntil and INCLUDE_xTaskDelayUntil are both defined.  INCLUDE_vTaskDelayUntil is no longer required and should be removed
-    #endif
-#endif
-
-#ifndef INCLUDE_xTaskDelayUntil
-    #ifdef INCLUDE_vTaskDelayUntil
-        /* If INCLUDE_vTaskDelayUntil is set but INCLUDE_xTaskDelayUntil is not then
-         * the project's FreeRTOSConfig.h probably pre-dates the introduction of
-         * xTaskDelayUntil and setting INCLUDE_xTaskDelayUntil to whatever
-         * INCLUDE_vTaskDelayUntil is set to will ensure backward compatibility.
-         */
-        #define INCLUDE_xTaskDelayUntil INCLUDE_vTaskDelayUntil
-    #endif
-#endif
-
-#ifndef INCLUDE_xTaskDelayUntil
-    #define INCLUDE_xTaskDelayUntil    0
-#endif
-
-#ifndef INCLUDE_vTaskDelay
-    #define INCLUDE_vTaskDelay    0
-#endif
-
-#ifndef INCLUDE_xTaskGetIdleTaskHandle
-    #define INCLUDE_xTaskGetIdleTaskHandle    0
-#endif
-
-#ifndef INCLUDE_xTaskAbortDelay
-    #define INCLUDE_xTaskAbortDelay    0
-#endif
-
-#ifndef INCLUDE_xQueueGetMutexHolder
-    #define INCLUDE_xQueueGetMutexHolder    0
-#endif
-
-#ifndef INCLUDE_xSemaphoreGetMutexHolder
-    #define INCLUDE_xSemaphoreGetMutexHolder    INCLUDE_xQueueGetMutexHolder
-#endif
-
-#ifndef INCLUDE_xTaskGetHandle
-    #define INCLUDE_xTaskGetHandle    0
-#endif
-
-#ifndef INCLUDE_uxTaskGetStackHighWaterMark
-    #define INCLUDE_uxTaskGetStackHighWaterMark    0
-#endif
-
-#ifndef INCLUDE_uxTaskGetStackHighWaterMark2
-    #define INCLUDE_uxTaskGetStackHighWaterMark2    0
-#endif
-
-#ifndef INCLUDE_pxTaskGetStackStart
-    #define INCLUDE_pxTaskGetStackStart 0
-#endif
-
-#ifndef INCLUDE_eTaskGetState
-    #define INCLUDE_eTaskGetState    0
-#endif
-
-#ifndef INCLUDE_xTaskResumeFromISR
-    #define INCLUDE_xTaskResumeFromISR    1
-#endif
-
-#ifndef INCLUDE_xTimerPendFunctionCall
-    #define INCLUDE_xTimerPendFunctionCall    0
-#endif
-
-#ifndef INCLUDE_xTaskGetSchedulerState
-    #define INCLUDE_xTaskGetSchedulerState    0
-#endif
-
-#ifndef INCLUDE_xTaskGetCurrentTaskHandle
-    #define INCLUDE_xTaskGetCurrentTaskHandle    0
-#endif
-
-#if configUSE_CO_ROUTINES != 0
-    #ifndef configMAX_CO_ROUTINE_PRIORITIES
-        #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.
-    #endif
-#endif
-
-#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
-    #define configUSE_DAEMON_TASK_STARTUP_HOOK    0
-#endif
-
-#ifndef configUSE_APPLICATION_TASK_TAG
-    #define configUSE_APPLICATION_TASK_TAG    0
-#endif
-
-#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS
-    #define configNUM_THREAD_LOCAL_STORAGE_POINTERS    0
-#endif
-
-#ifndef configUSE_RECURSIVE_MUTEXES
-    #define configUSE_RECURSIVE_MUTEXES    0
-#endif
-
-#ifndef configUSE_MUTEXES
-    #define configUSE_MUTEXES    0
-#endif
-
-#ifndef configUSE_TIMERS
-    #define configUSE_TIMERS    0
-#endif
-
-#ifndef configUSE_COUNTING_SEMAPHORES
-    #define configUSE_COUNTING_SEMAPHORES    0
-#endif
-
-#ifndef configUSE_ALTERNATIVE_API
-    #define configUSE_ALTERNATIVE_API    0
-#endif
-
-#ifndef portCRITICAL_NESTING_IN_TCB
-    #define portCRITICAL_NESTING_IN_TCB    0
-#endif
-
-#ifndef configMAX_TASK_NAME_LEN
-    #define configMAX_TASK_NAME_LEN    16
-#endif
-
-#ifndef configIDLE_SHOULD_YIELD
-    #define configIDLE_SHOULD_YIELD    1
-#endif
-
-#if configMAX_TASK_NAME_LEN < 1
-    #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h
-#endif
-
-#ifndef configASSERT
-    #define configASSERT( x )
-    #define configASSERT_DEFINED    0
-#else
-    #define configASSERT_DEFINED    1
-#endif
-
-/* configPRECONDITION should be defined as configASSERT.
- * The CBMC proofs need a way to track assumptions and assertions.
- * A configPRECONDITION statement should express an implicit invariant or
- * assumption made.  A configASSERT statement should express an invariant that must
- * hold explicit before calling the code. */
-#ifndef configPRECONDITION
-    #define configPRECONDITION( X )    configASSERT( X )
-    #define configPRECONDITION_DEFINED    0
-#else
-    #define configPRECONDITION_DEFINED    1
-#endif
-
-#ifndef portMEMORY_BARRIER
-    #define portMEMORY_BARRIER()
-#endif
-
-#ifndef portSOFTWARE_BARRIER
-    #define portSOFTWARE_BARRIER()
-#endif
-
-/* The timers module relies on xTaskGetSchedulerState(). */
-#if configUSE_TIMERS == 1
-
-    #ifndef configTIMER_TASK_PRIORITY
-        #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.
-    #endif /* configTIMER_TASK_PRIORITY */
-
-    #ifndef configTIMER_QUEUE_LENGTH
-        #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.
-    #endif /* configTIMER_QUEUE_LENGTH */
-
-    #ifndef configTIMER_TASK_STACK_DEPTH
-        #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.
-    #endif /* configTIMER_TASK_STACK_DEPTH */
-
-#endif /* configUSE_TIMERS */
-
-#ifndef portSET_INTERRUPT_MASK_FROM_ISR
-    #define portSET_INTERRUPT_MASK_FROM_ISR()    0
-#endif
-
-#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )    ( void ) uxSavedStatusValue
-#endif
-
-#ifndef portCLEAN_UP_TCB
-    #define portCLEAN_UP_TCB( pxTCB )    ( void ) pxTCB
-#endif
-
-#ifndef portPRE_TASK_DELETE_HOOK
-    #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )
-#endif
-
-#ifndef portSETUP_TCB
-    #define portSETUP_TCB( pxTCB )    ( void ) pxTCB
-#endif
-
-#ifndef configQUEUE_REGISTRY_SIZE
-    #define configQUEUE_REGISTRY_SIZE    0U
-#endif
-
-#if ( configQUEUE_REGISTRY_SIZE < 1 )
-    #define vQueueAddToRegistry( xQueue, pcName )
-    #define vQueueUnregisterQueue( xQueue )
-    #define pcQueueGetName( xQueue )
-#endif
-
-#ifndef portPOINTER_SIZE_TYPE
-    #define portPOINTER_SIZE_TYPE    uint32_t
-#endif
-
-/* Remove any unused trace macros. */
-#ifndef traceSTART
-
-/* Used to perform any necessary initialisation - for example, open a file
- * into which trace is to be written. */
-    #define traceSTART()
-#endif
-
-#ifndef traceEND
-
-/* Use to close a trace, for example close a file into which trace has been
- * written. */
-    #define traceEND()
-#endif
-
-#ifndef traceTASK_SWITCHED_IN
-
-/* Called after a task has been selected to run.  pxCurrentTCB holds a pointer
- * to the task control block of the selected task. */
-    #define traceTASK_SWITCHED_IN()
-#endif
-
-#ifndef traceINCREASE_TICK_COUNT
-
-/* Called before stepping the tick count after waking from tickless idle
- * sleep. */
-    #define traceINCREASE_TICK_COUNT( x )
-#endif
-
-#ifndef traceLOW_POWER_IDLE_BEGIN
-    /* Called immediately before entering tickless idle. */
-    #define traceLOW_POWER_IDLE_BEGIN()
-#endif
-
-#ifndef traceLOW_POWER_IDLE_END
-    /* Called when returning to the Idle task after a tickless idle. */
-    #define traceLOW_POWER_IDLE_END()
-#endif
-
-#ifndef traceTASK_SWITCHED_OUT
-
-/* Called before a task has been selected to run.  pxCurrentTCB holds a pointer
- * to the task control block of the task being switched out. */
-    #define traceTASK_SWITCHED_OUT()
-#endif
-
-#ifndef traceTASK_PRIORITY_INHERIT
-
-/* Called when a task attempts to take a mutex that is already held by a
- * lower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task
- * that holds the mutex.  uxInheritedPriority is the priority the mutex holder
- * will inherit (the priority of the task that is attempting to obtain the
- * muted. */
-    #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )
-#endif
-
-#ifndef traceTASK_PRIORITY_DISINHERIT
-
-/* Called when a task releases a mutex, the holding of which had resulted in
- * the task inheriting the priority of a higher priority task.
- * pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the
- * mutex.  uxOriginalPriority is the task's configured (base) priority. */
-    #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )
-#endif
-
-#ifndef traceBLOCKING_ON_QUEUE_RECEIVE
-
-/* Task is about to block because it cannot read from a
- * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
- * upon which the read was attempted.  pxCurrentTCB points to the TCB of the
- * task that attempted the read. */
-    #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )
-#endif
-
-#ifndef traceBLOCKING_ON_QUEUE_PEEK
-
-/* Task is about to block because it cannot read from a
- * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
- * upon which the read was attempted.  pxCurrentTCB points to the TCB of the
- * task that attempted the read. */
-    #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue )
-#endif
-
-#ifndef traceBLOCKING_ON_QUEUE_SEND
-
-/* Task is about to block because it cannot write to a
- * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
- * upon which the write was attempted.  pxCurrentTCB points to the TCB of the
- * task that attempted the write. */
-    #define traceBLOCKING_ON_QUEUE_SEND( pxQueue )
-#endif
-
-#ifndef configCHECK_FOR_STACK_OVERFLOW
-    #define configCHECK_FOR_STACK_OVERFLOW    0
-#endif
-
-#ifndef configRECORD_STACK_HIGH_ADDRESS
-    #define configRECORD_STACK_HIGH_ADDRESS    0
-#endif
-
-#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H
-    #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H    0
-#endif
-
-/* The following event macros are embedded in the kernel API calls. */
-
-#ifndef traceMOVED_TASK_TO_READY_STATE
-    #define traceMOVED_TASK_TO_READY_STATE( pxTCB )
-#endif
-
-#ifndef tracePOST_MOVED_TASK_TO_READY_STATE
-    #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
-#endif
-
-#ifndef traceREADDED_TASK_TO_READY_STATE
-    #define traceREADDED_TASK_TO_READY_STATE( pxTCB )       traceMOVED_TASK_TO_READY_STATE( pxTCB )
-#endif
-
-#ifndef traceMOVED_TASK_TO_DELAYED_LIST
-    #define traceMOVED_TASK_TO_DELAYED_LIST()
-#endif
-
-#ifndef traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST
-    #define traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST()
-#endif
-
-#ifndef traceMOVED_TASK_TO_SUSPENDED_LIST
-    #define traceMOVED_TASK_TO_SUSPENDED_LIST( pxTCB )
-#endif
-
-#ifndef traceQUEUE_CREATE
-    #define traceQUEUE_CREATE( pxNewQueue )
-#endif
-
-#ifndef traceQUEUE_CREATE_FAILED
-    #define traceQUEUE_CREATE_FAILED( ucQueueType )
-#endif
-
-#ifndef traceCREATE_MUTEX
-    #define traceCREATE_MUTEX( pxNewQueue )
-#endif
-
-#ifndef traceCREATE_MUTEX_FAILED
-    #define traceCREATE_MUTEX_FAILED()
-#endif
-
-#ifndef traceGIVE_MUTEX_RECURSIVE
-    #define traceGIVE_MUTEX_RECURSIVE( pxMutex )
-#endif
-
-#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED
-    #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )
-#endif
-
-#ifndef traceTAKE_MUTEX_RECURSIVE
-    #define traceTAKE_MUTEX_RECURSIVE( pxMutex )
-#endif
-
-#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED
-    #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )
-#endif
-
-#ifndef traceCREATE_COUNTING_SEMAPHORE
-    #define traceCREATE_COUNTING_SEMAPHORE()
-#endif
-
-#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED
-    #define traceCREATE_COUNTING_SEMAPHORE_FAILED()
-#endif
-
-#ifndef traceQUEUE_SET_SEND
-    #define traceQUEUE_SET_SEND    traceQUEUE_SEND
-#endif
-
-#ifndef traceQUEUE_SEND
-    #define traceQUEUE_SEND( pxQueue )
-#endif
-
-#ifndef traceQUEUE_SEND_FAILED
-    #define traceQUEUE_SEND_FAILED( pxQueue )
-#endif
-
-#ifndef traceQUEUE_RECEIVE
-    #define traceQUEUE_RECEIVE( pxQueue )
-#endif
-
-#ifndef traceQUEUE_PEEK
-    #define traceQUEUE_PEEK( pxQueue )
-#endif
-
-#ifndef traceQUEUE_PEEK_FAILED
-    #define traceQUEUE_PEEK_FAILED( pxQueue )
-#endif
-
-#ifndef traceQUEUE_PEEK_FROM_ISR
-    #define traceQUEUE_PEEK_FROM_ISR( pxQueue )
-#endif
-
-#ifndef traceQUEUE_RECEIVE_FAILED
-    #define traceQUEUE_RECEIVE_FAILED( pxQueue )
-#endif
-
-#ifndef traceQUEUE_SEND_FROM_ISR
-    #define traceQUEUE_SEND_FROM_ISR( pxQueue )
-#endif
-
-#ifndef traceQUEUE_SEND_FROM_ISR_FAILED
-    #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )
-#endif
-
-#ifndef traceQUEUE_RECEIVE_FROM_ISR
-    #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )
-#endif
-
-#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED
-    #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )
-#endif
-
-#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED
-    #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )
-#endif
-
-#ifndef traceQUEUE_DELETE
-    #define traceQUEUE_DELETE( pxQueue )
-#endif
-
-#ifndef traceTASK_CREATE
-    #define traceTASK_CREATE( pxNewTCB )
-#endif
-
-#ifndef traceTASK_CREATE_FAILED
-    #define traceTASK_CREATE_FAILED()
-#endif
-
-#ifndef traceTASK_DELETE
-    #define traceTASK_DELETE( pxTaskToDelete )
-#endif
-
-#ifndef traceTASK_DELAY_UNTIL
-    #define traceTASK_DELAY_UNTIL( x )
-#endif
-
-#ifndef traceTASK_DELAY
-    #define traceTASK_DELAY()
-#endif
-
-#ifndef traceTASK_PRIORITY_SET
-    #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )
-#endif
-
-#ifndef traceTASK_SUSPEND
-    #define traceTASK_SUSPEND( pxTaskToSuspend )
-#endif
-
-#ifndef traceTASK_RESUME
-    #define traceTASK_RESUME( pxTaskToResume )
-#endif
-
-#ifndef traceTASK_RESUME_FROM_ISR
-    #define traceTASK_RESUME_FROM_ISR( pxTaskToResume )
-#endif
-
-#ifndef traceTASK_INCREMENT_TICK
-    #define traceTASK_INCREMENT_TICK( xTickCount )
-#endif
-
-#ifndef traceTIMER_CREATE
-    #define traceTIMER_CREATE( pxNewTimer )
-#endif
-
-#ifndef traceTIMER_CREATE_FAILED
-    #define traceTIMER_CREATE_FAILED()
-#endif
-
-#ifndef traceTIMER_COMMAND_SEND
-    #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )
-#endif
-
-#ifndef traceTIMER_EXPIRED
-    #define traceTIMER_EXPIRED( pxTimer )
-#endif
-
-#ifndef traceTIMER_COMMAND_RECEIVED
-    #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )
-#endif
-
-#ifndef traceMALLOC
-    #define traceMALLOC( pvAddress, uiSize )
-#endif
-
-#ifndef traceFREE
-    #define traceFREE( pvAddress, uiSize )
-#endif
-
-#ifndef traceEVENT_GROUP_CREATE
-    #define traceEVENT_GROUP_CREATE( xEventGroup )
-#endif
-
-#ifndef traceEVENT_GROUP_CREATE_FAILED
-    #define traceEVENT_GROUP_CREATE_FAILED()
-#endif
-
-#ifndef traceEVENT_GROUP_SYNC_BLOCK
-    #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )
-#endif
-
-#ifndef traceEVENT_GROUP_SYNC_END
-    #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred )    ( void ) xTimeoutOccurred
-#endif
-
-#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK
-    #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )
-#endif
-
-#ifndef traceEVENT_GROUP_WAIT_BITS_END
-    #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred )    ( void ) xTimeoutOccurred
-#endif
-
-#ifndef traceEVENT_GROUP_CLEAR_BITS
-    #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )
-#endif
-
-#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR
-    #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )
-#endif
-
-#ifndef traceEVENT_GROUP_SET_BITS
-    #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )
-#endif
-
-#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR
-    #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )
-#endif
-
-#ifndef traceEVENT_GROUP_DELETE
-    #define traceEVENT_GROUP_DELETE( xEventGroup )
-#endif
-
-#ifndef tracePEND_FUNC_CALL
-    #define tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, ret )
-#endif
-
-#ifndef tracePEND_FUNC_CALL_FROM_ISR
-    #define tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, ret )
-#endif
-
-#ifndef traceQUEUE_REGISTRY_ADD
-    #define traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName )
-#endif
-
-#ifndef traceTASK_NOTIFY_TAKE_BLOCK
-    #define traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait )
-#endif
-
-#ifndef traceTASK_NOTIFY_TAKE
-    #define traceTASK_NOTIFY_TAKE( uxIndexToWait )
-#endif
-
-#ifndef traceTASK_NOTIFY_WAIT_BLOCK
-    #define traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait )
-#endif
-
-#ifndef traceTASK_NOTIFY_WAIT
-    #define traceTASK_NOTIFY_WAIT( uxIndexToWait )
-#endif
-
-#ifndef traceTASK_NOTIFY
-    #define traceTASK_NOTIFY( uxIndexToNotify )
-#endif
-
-#ifndef traceTASK_NOTIFY_FROM_ISR
-    #define traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify )
-#endif
-
-#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR
-    #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify )
-#endif
-
-#ifndef traceISR_EXIT_TO_SCHEDULER
-    #define traceISR_EXIT_TO_SCHEDULER()
-#endif
-
-#ifndef traceISR_EXIT
-    #define traceISR_EXIT()
-#endif
-
-#ifndef traceISR_ENTER
-    #define traceISR_ENTER()
-#endif
-
-#ifndef traceSTREAM_BUFFER_CREATE_FAILED
-    #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer )
-#endif
-
-#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED
-    #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer )
-#endif
-
-#ifndef traceSTREAM_BUFFER_CREATE
-    #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer )
-#endif
-
-#ifndef traceSTREAM_BUFFER_DELETE
-    #define traceSTREAM_BUFFER_DELETE( xStreamBuffer )
-#endif
-
-#ifndef traceSTREAM_BUFFER_RESET
-    #define traceSTREAM_BUFFER_RESET( xStreamBuffer )
-#endif
-
-#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND
-    #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer )
-#endif
-
-#ifndef traceSTREAM_BUFFER_SEND
-    #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent )
-#endif
-
-#ifndef traceSTREAM_BUFFER_SEND_FAILED
-    #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer )
-#endif
-
-#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR
-    #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent )
-#endif
-
-#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE
-    #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer )
-#endif
-
-#ifndef traceSTREAM_BUFFER_RECEIVE
-    #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength )
-#endif
-
-#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED
-    #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer )
-#endif
-
-#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR
-    #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength )
-#endif
-
-#ifndef configGENERATE_RUN_TIME_STATS
-    #define configGENERATE_RUN_TIME_STATS    0
-#endif
-
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
-
-    #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
-        #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.
-    #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */
-
-    #ifndef portGET_RUN_TIME_COUNTER_VALUE
-        #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE
-            #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.
-        #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */
-    #endif /* portGET_RUN_TIME_COUNTER_VALUE */
-
-#endif /* configGENERATE_RUN_TIME_STATS */
-
-#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
-    #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
-#endif
-
-#ifndef configUSE_MALLOC_FAILED_HOOK
-    #define configUSE_MALLOC_FAILED_HOOK    0
-#endif
-
-#ifndef portPRIVILEGE_BIT
-    #define portPRIVILEGE_BIT    ( ( UBaseType_t ) 0x00 )
-#endif
-
-#ifndef portYIELD_WITHIN_API
-    #define portYIELD_WITHIN_API    portYIELD
-#endif
-
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )
-#endif
-
-#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP
-    #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP    2
-#endif
-
-#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2
-    #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2
-#endif
-
-#ifndef configUSE_TICKLESS_IDLE
-    #define configUSE_TICKLESS_IDLE    0
-#endif
-
-#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING
-    #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x )
-#endif
-
-#ifndef configPRE_SLEEP_PROCESSING
-    #define configPRE_SLEEP_PROCESSING( x )
-#endif
-
-#ifndef configPOST_SLEEP_PROCESSING
-    #define configPOST_SLEEP_PROCESSING( x )
-#endif
-
-#ifndef configUSE_QUEUE_SETS
-    #define configUSE_QUEUE_SETS    0
-#endif
-
-#ifndef portTASK_USES_FLOATING_POINT
-    #define portTASK_USES_FLOATING_POINT()
-#endif
-
-#ifndef portALLOCATE_SECURE_CONTEXT
-    #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-#endif
-
-#ifndef portDONT_DISCARD
-    #define portDONT_DISCARD
-#endif
-
-#ifndef configUSE_TIME_SLICING
-    #define configUSE_TIME_SLICING    1
-#endif
-
-#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
-    #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS    0
-#endif
-
-#ifndef configUSE_STATS_FORMATTING_FUNCTIONS
-    #define configUSE_STATS_FORMATTING_FUNCTIONS    0
-#endif
-
-#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()
-#endif
-
-#ifndef configUSE_TRACE_FACILITY
-    #define configUSE_TRACE_FACILITY    0
-#endif
-
-#ifndef mtCOVERAGE_TEST_MARKER
-    #define mtCOVERAGE_TEST_MARKER()
-#endif
-
-#ifndef mtCOVERAGE_TEST_DELAY
-    #define mtCOVERAGE_TEST_DELAY()
-#endif
-
-#ifndef portASSERT_IF_IN_ISR
-    #define portASSERT_IF_IN_ISR()
-#endif
-
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
-#endif
-
-#ifndef configAPPLICATION_ALLOCATED_HEAP
-    #define configAPPLICATION_ALLOCATED_HEAP    0
-#endif
-
-#ifndef configUSE_TASK_NOTIFICATIONS
-    #define configUSE_TASK_NOTIFICATIONS    1
-#endif
-
-#ifndef configTASK_NOTIFICATION_ARRAY_ENTRIES
-    #define configTASK_NOTIFICATION_ARRAY_ENTRIES    1
-#endif
-
-#if configTASK_NOTIFICATION_ARRAY_ENTRIES < 1
-    #error configTASK_NOTIFICATION_ARRAY_ENTRIES must be at least 1
-#endif
-
-#ifndef configUSE_POSIX_ERRNO
-    #define configUSE_POSIX_ERRNO    0
-#endif
-
-#ifndef portTICK_TYPE_IS_ATOMIC
-    #define portTICK_TYPE_IS_ATOMIC    0
-#endif
-
-#ifndef configSUPPORT_STATIC_ALLOCATION
-    /* Defaults to 0 for backward compatibility. */
-    #define configSUPPORT_STATIC_ALLOCATION    0
-#endif
-
-#ifndef configSUPPORT_DYNAMIC_ALLOCATION
-    /* Defaults to 1 for backward compatibility. */
-    #define configSUPPORT_DYNAMIC_ALLOCATION    1
-#endif
-
-#ifndef configSTACK_DEPTH_TYPE
-
-/* Defaults to uint16_t for backward compatibility, but can be overridden
- * in FreeRTOSConfig.h if uint16_t is too restrictive. */
-    #define configSTACK_DEPTH_TYPE    uint16_t
-#endif
-
-#ifndef configMESSAGE_BUFFER_LENGTH_TYPE
-
-/* Defaults to size_t for backward compatibility, but can be overridden
- * in FreeRTOSConfig.h if lengths will always be less than the number of bytes
- * in a size_t. */
-    #define configMESSAGE_BUFFER_LENGTH_TYPE    size_t
-#endif
-
-/* Sanity check the configuration. */
-#if ( configUSE_TICKLESS_IDLE != 0 )
-    #if ( INCLUDE_vTaskSuspend != 1 )
-        #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0
-    #endif /* INCLUDE_vTaskSuspend */
-#endif /* configUSE_TICKLESS_IDLE */
-
-#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
-    #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.
-#endif
-
-#if ( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) )
-    #error configUSE_MUTEXES must be set to 1 to use recursive mutexes
-#endif
-
-#ifndef configINITIAL_TICK_COUNT
-    #define configINITIAL_TICK_COUNT    0
-#endif
-
-#if ( portTICK_TYPE_IS_ATOMIC == 0 )
-
-/* Either variables of tick type cannot be read atomically, or
- * portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when
- * the tick count is returned to the standard critical section macros. */
-    #define portTICK_TYPE_ENTER_CRITICAL()                      portENTER_CRITICAL()
-    #define portTICK_TYPE_EXIT_CRITICAL()                       portEXIT_CRITICAL()
-    #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR()         portSET_INTERRUPT_MASK_FROM_ISR()
-    #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x )    portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )
-#else
-
-/* The tick type can be read atomically, so critical sections used when the
- * tick count is returned can be defined away. */
-    #define portTICK_TYPE_ENTER_CRITICAL()
-    #define portTICK_TYPE_EXIT_CRITICAL()
-    #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR()         0
-    #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x )    ( void ) x
-#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */
-
-/* Definitions to allow backward compatibility with FreeRTOS versions prior to
- * V8 if desired. */
-#ifndef configENABLE_BACKWARD_COMPATIBILITY
-    #define configENABLE_BACKWARD_COMPATIBILITY    1
-#endif
-
-#ifndef configPRINTF
-
-/* configPRINTF() was not defined, so define it away to nothing.  To use
- * configPRINTF() then define it as follows (where MyPrintFunction() is
- * provided by the application writer):
- *
- * void MyPrintFunction(const char *pcFormat, ... );
- #define configPRINTF( X )   MyPrintFunction X
- *
- * Then call like a standard printf() function, but placing brackets around
- * all parameters so they are passed as a single parameter.  For example:
- * configPRINTF( ("Value = %d", MyVariable) ); */
-    #define configPRINTF( X )
-#endif
-
-#ifndef configMAX
-
-/* The application writer has not provided their own MAX macro, so define
- * the following generic implementation. */
-    #define configMAX( a, b )    ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )
-#endif
-
-#ifndef configMIN
-
-/* The application writer has not provided their own MAX macro, so define
- * the following generic implementation. */
-    #define configMIN( a, b )    ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )
-#endif
-
-#if configENABLE_BACKWARD_COMPATIBILITY == 1
-    #define eTaskStateGet                 eTaskGetState
-    #define portTickType                  TickType_t
-    #define xTaskHandle                   TaskHandle_t
-    #define xQueueHandle                  QueueHandle_t
-    #define xSemaphoreHandle              SemaphoreHandle_t
-    #define xQueueSetHandle               QueueSetHandle_t
-    #define xQueueSetMemberHandle         QueueSetMemberHandle_t
-    #define xTimeOutType                  TimeOut_t
-    #define xMemoryRegion                 MemoryRegion_t
-    #define xTaskParameters               TaskParameters_t
-    #define xTaskStatusType               TaskStatus_t
-    #define xTimerHandle                  TimerHandle_t
-    #define xCoRoutineHandle              CoRoutineHandle_t
-    #define pdTASK_HOOK_CODE              TaskHookFunction_t
-    #define portTICK_RATE_MS              portTICK_PERIOD_MS
-    #define pcTaskGetTaskName             pcTaskGetName
-    #define pcTimerGetTimerName           pcTimerGetName
-    #define pcQueueGetQueueName           pcQueueGetName
-    #define vTaskGetTaskInfo              vTaskGetInfo
-    #define xTaskGetIdleRunTimeCounter    ulTaskGetIdleRunTimeCounter
-
-/* Backward compatibility within the scheduler code only - these definitions
- * are not really required but are included for completeness. */
-    #define tmrTIMER_CALLBACK             TimerCallbackFunction_t
-    #define pdTASK_CODE                   TaskFunction_t
-    #define xListItem                     ListItem_t
-    #define xList                         List_t
-
-/* For libraries that break the list data hiding, and access list structure
- * members directly (which is not supposed to be done). */
-    #define pxContainer                   pvContainer
-#endif /* configENABLE_BACKWARD_COMPATIBILITY */
-
-#if ( configUSE_ALTERNATIVE_API != 0 )
-    #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0
-#endif
-
-/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even
- * if floating point hardware is otherwise supported by the FreeRTOS port in use.
- * This constant is not supported by all FreeRTOS ports that include floating
- * point support. */
-#ifndef configUSE_TASK_FPU_SUPPORT
-    #define configUSE_TASK_FPU_SUPPORT    1
-#endif
-
-/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is
- * currently used in ARMv8M ports. */
-#ifndef configENABLE_MPU
-    #define configENABLE_MPU    0
-#endif
-
-/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is
- * currently used in ARMv8M ports. */
-#ifndef configENABLE_FPU
-    #define configENABLE_FPU    1
-#endif
-
-/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.
- * This is currently used in ARMv8M ports. */
-#ifndef configENABLE_TRUSTZONE
-    #define configENABLE_TRUSTZONE    1
-#endif
-
-/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on
- * the Secure Side only. */
-#ifndef configRUN_FREERTOS_SECURE_ONLY
-    #define configRUN_FREERTOS_SECURE_ONLY    0
-#endif
-
-/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
- * dynamically allocated RAM, in which case when any task is deleted it is known
- * that both the task's stack and TCB need to be freed.  Sometimes the
- * FreeRTOSConfig.h settings only allow a task to be created using statically
- * allocated RAM, in which case when any task is deleted it is known that neither
- * the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h
- * settings allow a task to be created using either statically or dynamically
- * allocated RAM, in which case a member of the TCB is used to record whether the
- * stack and/or TCB were allocated statically or dynamically, so when a task is
- * deleted the RAM that was allocated dynamically is freed again and no attempt is
- * made to free the RAM that was allocated statically.
- * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
- * task to be created using either statically or dynamically allocated RAM.  Note
- * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
- * a statically allocated stack and a dynamically allocated TCB.
- *
- * The following table lists various combinations of portUSING_MPU_WRAPPERS,
- * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and
- * when it is possible to have both static and dynamic allocation:
- *  +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
- * | MPU | Dynamic | Static |     Available Functions     |       Possible Allocations        | Both Dynamic and | Need Free |
- * |     |         |        |                             |                                   | Static Possible  |           |
- * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
- * | 0   | 0       | 1      | xTaskCreateStatic           | TCB - Static, Stack - Static      | No               | No        |
- * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
- * | 0   | 1       | 0      | xTaskCreate                 | TCB - Dynamic, Stack - Dynamic    | No               | Yes       |
- * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
- * | 0   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
- * |     |         |        | xTaskCreateStatic           | 2. TCB - Static, Stack - Static   |                  |           |
- * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
- * | 1   | 0       | 1      | xTaskCreateStatic,          | TCB - Static, Stack - Static      | No               | No        |
- * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
- * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
- * | 1   | 1       | 0      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
- * |     |         |        | xTaskCreateRestricted       | 2. TCB - Dynamic, Stack - Static  |                  |           |
- * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
- * | 1   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
- * |     |         |        | xTaskCreateStatic,          | 2. TCB - Dynamic, Stack - Static  |                  |           |
- * |     |         |        | xTaskCreateRestricted,      | 3. TCB - Static, Stack - Static   |                  |           |
- * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
- * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
- */
-#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE                                                                                     \
-    ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \
-      ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )
-
-/*
- * In line with software engineering best practice, FreeRTOS implements a strict
- * data hiding policy, so the real structures used by FreeRTOS to maintain the
- * state of tasks, queues, semaphores, etc. are not accessible to the application
- * code.  However, if the application writer wants to statically allocate such
- * an object then the size of the object needs to be know.  Dummy structures
- * that are guaranteed to have the same size and alignment requirements of the
- * real objects are used for this purpose.  The dummy list and list item
- * structures below are used for inclusion in such a dummy structure.
- */
-struct xSTATIC_LIST_ITEM
-{
-    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
-        TickType_t xDummy1;
-    #endif
-    TickType_t xDummy2;
-    void * pvDummy3[ 4 ];
-    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
-        TickType_t xDummy4;
-    #endif
-};
-typedef struct xSTATIC_LIST_ITEM StaticListItem_t;
-
-/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
-struct xSTATIC_MINI_LIST_ITEM
-{
-    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
-        TickType_t xDummy1;
-    #endif
-    TickType_t xDummy2;
-    void * pvDummy3[ 2 ];
-};
-typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
-
-/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
-typedef struct xSTATIC_LIST
-{
-    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
-        TickType_t xDummy1;
-    #endif
-    UBaseType_t uxDummy2;
-    void * pvDummy3;
-    StaticMiniListItem_t xDummy4;
-    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
-        TickType_t xDummy5;
-    #endif
-} StaticList_t;
-
-/*
- * In line with software engineering best practice, especially when supplying a
- * library that is likely to change in future versions, FreeRTOS implements a
- * strict data hiding policy.  This means the Task structure used internally by
- * FreeRTOS is not accessible to application code.  However, if the application
- * writer wants to statically allocate the memory required to create a task then
- * the size of the task object needs to be know.  The StaticTask_t structure
- * below is provided for this purpose.  Its sizes and alignment requirements are
- * guaranteed to match those of the genuine structure, no matter which
- * architecture is being used, and no matter how the values in FreeRTOSConfig.h
- * are set.  Its contents are somewhat obfuscated in the hope users will
- * recognise that it would be unwise to make direct use of the structure members.
- */
-typedef struct xSTATIC_TCB
-{
-    void * pxDummy1;
-    #if ( portUSING_MPU_WRAPPERS == 1 )
-        xMPU_SETTINGS xDummy2;
-    #endif
-    StaticListItem_t xDummy3[ 2 ];
-    UBaseType_t uxDummy5;
-    void * pxDummy6;
-    uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ];
-    #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
-        void * pxDummy8;
-    #endif
-    #if ( portCRITICAL_NESTING_IN_TCB == 1 )
-        UBaseType_t uxDummy9;
-    #endif
-    #if ( configUSE_TRACE_FACILITY == 1 )
-        UBaseType_t uxDummy10[ 2 ];
-    #endif
-    #if ( configUSE_MUTEXES == 1 )
-        UBaseType_t uxDummy12[ 2 ];
-    #endif
-    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
-        void * pxDummy14;
-    #endif
-    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
-        void * pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
-    #endif
-    #if ( configGENERATE_RUN_TIME_STATS == 1 )
-        uint32_t ulDummy16;
-    #endif
-    #if ( configUSE_NEWLIB_REENTRANT == 1 )
-        struct  _reent xDummy17;
-    #endif
-    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
-        uint32_t ulDummy18[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
-        uint8_t ucDummy19[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
-    #endif
-    #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
-        uint8_t uxDummy20;
-    #endif
-
-    #if ( INCLUDE_xTaskAbortDelay == 1 )
-        uint8_t ucDummy21;
-    #endif
-    #if ( configUSE_POSIX_ERRNO == 1 )
-        int iDummy22;
-    #endif
-} StaticTask_t;
-
-/*
- * In line with software engineering best practice, especially when supplying a
- * library that is likely to change in future versions, FreeRTOS implements a
- * strict data hiding policy.  This means the Queue structure used internally by
- * FreeRTOS is not accessible to application code.  However, if the application
- * writer wants to statically allocate the memory required to create a queue
- * then the size of the queue object needs to be know.  The StaticQueue_t
- * structure below is provided for this purpose.  Its sizes and alignment
- * requirements are guaranteed to match those of the genuine structure, no
- * matter which architecture is being used, and no matter how the values in
- * FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in the hope
- * users will recognise that it would be unwise to make direct use of the
- * structure members.
- */
-typedef struct xSTATIC_QUEUE
-{
-    void * pvDummy1[ 3 ];
-
-    union
-    {
-        void * pvDummy2;
-        UBaseType_t uxDummy2;
-    } u;
-
-    StaticList_t xDummy3[ 2 ];
-    UBaseType_t uxDummy4[ 3 ];
-    uint8_t ucDummy5[ 2 ];
-
-    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-        uint8_t ucDummy6;
-    #endif
-
-    #if ( configUSE_QUEUE_SETS == 1 )
-        void * pvDummy7;
-    #endif
-
-    #if ( configUSE_TRACE_FACILITY == 1 )
-        UBaseType_t uxDummy8;
-        uint8_t ucDummy9;
-    #endif
-} StaticQueue_t;
-typedef StaticQueue_t StaticSemaphore_t;
-
-/*
- * In line with software engineering best practice, especially when supplying a
- * library that is likely to change in future versions, FreeRTOS implements a
- * strict data hiding policy.  This means the event group structure used
- * internally by FreeRTOS is not accessible to application code.  However, if
- * the application writer wants to statically allocate the memory required to
- * create an event group then the size of the event group object needs to be
- * know.  The StaticEventGroup_t structure below is provided for this purpose.
- * Its sizes and alignment requirements are guaranteed to match those of the
- * genuine structure, no matter which architecture is being used, and no matter
- * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
- * obfuscated in the hope users will recognise that it would be unwise to make
- * direct use of the structure members.
- */
-typedef struct xSTATIC_EVENT_GROUP
-{
-    TickType_t xDummy1;
-    StaticList_t xDummy2;
-
-    #if ( configUSE_TRACE_FACILITY == 1 )
-        UBaseType_t uxDummy3;
-    #endif
-
-    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-        uint8_t ucDummy4;
-    #endif
-} StaticEventGroup_t;
-
-/*
- * In line with software engineering best practice, especially when supplying a
- * library that is likely to change in future versions, FreeRTOS implements a
- * strict data hiding policy.  This means the software timer structure used
- * internally by FreeRTOS is not accessible to application code.  However, if
- * the application writer wants to statically allocate the memory required to
- * create a software timer then the size of the queue object needs to be know.
- * The StaticTimer_t structure below is provided for this purpose.  Its sizes
- * and alignment requirements are guaranteed to match those of the genuine
- * structure, no matter which architecture is being used, and no matter how the
- * values in FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in
- * the hope users will recognise that it would be unwise to make direct use of
- * the structure members.
- */
-typedef struct xSTATIC_TIMER
-{
-    void * pvDummy1;
-    StaticListItem_t xDummy2;
-    TickType_t xDummy3;
-    void * pvDummy5;
-    TaskFunction_t pvDummy6;
-    #if ( configUSE_TRACE_FACILITY == 1 )
-        UBaseType_t uxDummy7;
-    #endif
-    uint8_t ucDummy8;
-} StaticTimer_t;
-
-/*
- * In line with software engineering best practice, especially when supplying a
- * library that is likely to change in future versions, FreeRTOS implements a
- * strict data hiding policy.  This means the stream buffer structure used
- * internally by FreeRTOS is not accessible to application code.  However, if
- * the application writer wants to statically allocate the memory required to
- * create a stream buffer then the size of the stream buffer object needs to be
- * know.  The StaticStreamBuffer_t structure below is provided for this purpose.
- * Its size and alignment requirements are guaranteed to match those of the
- * genuine structure, no matter which architecture is being used, and no matter
- * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
- * obfuscated in the hope users will recognise that it would be unwise to make
- * direct use of the structure members.
- */
-typedef struct xSTATIC_STREAM_BUFFER
-{
-    size_t uxDummy1[ 4 ];
-    void * pvDummy2[ 3 ];
-    uint8_t ucDummy3;
-    #if ( configUSE_TRACE_FACILITY == 1 )
-        UBaseType_t uxDummy4;
-    #endif
-} StaticStreamBuffer_t;
-
-/* Message buffers are built on stream buffers. */
-typedef StaticStreamBuffer_t StaticMessageBuffer_t;
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    }
-#endif
-/* *INDENT-ON* */
-
-#endif /* INC_FREERTOS_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/atomic.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/atomic.h
deleted file mode 100644
index 74abbe0..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/atomic.h
+++ /dev/null
@@ -1,417 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/**
- * @file atomic.h
- * @brief FreeRTOS atomic operation support.
- *
- * This file implements atomic functions by disabling interrupts globally.
- * Implementations with architecture specific atomic instructions can be
- * provided under each compiler directory.
- */
-
-#ifndef ATOMIC_H
-#define ATOMIC_H
-
-#ifndef INC_FREERTOS_H
-    #error "include FreeRTOS.h must appear in source files before include atomic.h"
-#endif
-
-/* Standard includes. */
-#include 
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/*
- * Port specific definitions -- entering/exiting critical section.
- * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h
- *
- * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with
- * ATOMIC_ENTER_CRITICAL().
- *
- */
-#if defined( portSET_INTERRUPT_MASK_FROM_ISR )
-
-/* Nested interrupt scheme is supported in this port. */
-    #define ATOMIC_ENTER_CRITICAL() \
-    UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR()
-
-    #define ATOMIC_EXIT_CRITICAL() \
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType )
-
-#else
-
-/* Nested interrupt scheme is NOT supported in this port. */
-    #define ATOMIC_ENTER_CRITICAL()    portENTER_CRITICAL()
-    #define ATOMIC_EXIT_CRITICAL()     portEXIT_CRITICAL()
-
-#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */
-
-/*
- * Port specific definition -- "always inline".
- * Inline is compiler specific, and may not always get inlined depending on your
- * optimization level.  Also, inline is considered as performance optimization
- * for atomic.  Thus, if portFORCE_INLINE is not provided by portmacro.h,
- * instead of resulting error, simply define it away.
- */
-#ifndef portFORCE_INLINE
-    #define portFORCE_INLINE
-#endif
-
-#define ATOMIC_COMPARE_AND_SWAP_SUCCESS    0x1U     /**< Compare and swap succeeded, swapped. */
-#define ATOMIC_COMPARE_AND_SWAP_FAILURE    0x0U     /**< Compare and swap failed, did not swap. */
-
-/*----------------------------- Swap && CAS ------------------------------*/
-
-/**
- * Atomic compare-and-swap
- *
- * @brief Performs an atomic compare-and-swap operation on the specified values.
- *
- * @param[in, out] pulDestination  Pointer to memory location from where value is
- *                               to be loaded and checked.
- * @param[in] ulExchange         If condition meets, write this value to memory.
- * @param[in] ulComparand        Swap condition.
- *
- * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
- *
- * @note This function only swaps *pulDestination with ulExchange, if previous
- *       *pulDestination value equals ulComparand.
- */
-static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination,
-                                                            uint32_t ulExchange,
-                                                            uint32_t ulComparand )
-{
-    uint32_t ulReturnValue;
-
-    ATOMIC_ENTER_CRITICAL();
-    {
-        if( *pulDestination == ulComparand )
-        {
-            *pulDestination = ulExchange;
-            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
-        }
-        else
-        {
-            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
-        }
-    }
-    ATOMIC_EXIT_CRITICAL();
-
-    return ulReturnValue;
-}
-/*-----------------------------------------------------------*/
-
-/**
- * Atomic swap (pointers)
- *
- * @brief Atomically sets the address pointed to by *ppvDestination to the value
- *        of *pvExchange.
- *
- * @param[in, out] ppvDestination  Pointer to memory location from where a pointer
- *                                 value is to be loaded and written back to.
- * @param[in] pvExchange           Pointer value to be written to *ppvDestination.
- *
- * @return The initial value of *ppvDestination.
- */
-static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination,
-                                                        void * pvExchange )
-{
-    void * pReturnValue;
-
-    ATOMIC_ENTER_CRITICAL();
-    {
-        pReturnValue = *ppvDestination;
-        *ppvDestination = pvExchange;
-    }
-    ATOMIC_EXIT_CRITICAL();
-
-    return pReturnValue;
-}
-/*-----------------------------------------------------------*/
-
-/**
- * Atomic compare-and-swap (pointers)
- *
- * @brief Performs an atomic compare-and-swap operation on the specified pointer
- *        values.
- *
- * @param[in, out] ppvDestination  Pointer to memory location from where a pointer
- *                                 value is to be loaded and checked.
- * @param[in] pvExchange           If condition meets, write this value to memory.
- * @param[in] pvComparand          Swap condition.
- *
- * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
- *
- * @note This function only swaps *ppvDestination with pvExchange, if previous
- *       *ppvDestination value equals pvComparand.
- */
-static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination,
-                                                                    void * pvExchange,
-                                                                    void * pvComparand )
-{
-    uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
-
-    ATOMIC_ENTER_CRITICAL();
-    {
-        if( *ppvDestination == pvComparand )
-        {
-            *ppvDestination = pvExchange;
-            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
-        }
-    }
-    ATOMIC_EXIT_CRITICAL();
-
-    return ulReturnValue;
-}
-
-
-/*----------------------------- Arithmetic ------------------------------*/
-
-/**
- * Atomic add
- *
- * @brief Atomically adds count to the value of the specified pointer points to.
- *
- * @param[in,out] pulAddend  Pointer to memory location from where value is to be
- *                         loaded and written back to.
- * @param[in] ulCount      Value to be added to *pulAddend.
- *
- * @return previous *pulAddend value.
- */
-static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend,
-                                                 uint32_t ulCount )
-{
-    uint32_t ulCurrent;
-
-    ATOMIC_ENTER_CRITICAL();
-    {
-        ulCurrent = *pulAddend;
-        *pulAddend += ulCount;
-    }
-    ATOMIC_EXIT_CRITICAL();
-
-    return ulCurrent;
-}
-/*-----------------------------------------------------------*/
-
-/**
- * Atomic subtract
- *
- * @brief Atomically subtracts count from the value of the specified pointer
- *        pointers to.
- *
- * @param[in,out] pulAddend  Pointer to memory location from where value is to be
- *                         loaded and written back to.
- * @param[in] ulCount      Value to be subtract from *pulAddend.
- *
- * @return previous *pulAddend value.
- */
-static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend,
-                                                      uint32_t ulCount )
-{
-    uint32_t ulCurrent;
-
-    ATOMIC_ENTER_CRITICAL();
-    {
-        ulCurrent = *pulAddend;
-        *pulAddend -= ulCount;
-    }
-    ATOMIC_EXIT_CRITICAL();
-
-    return ulCurrent;
-}
-/*-----------------------------------------------------------*/
-
-/**
- * Atomic increment
- *
- * @brief Atomically increments the value of the specified pointer points to.
- *
- * @param[in,out] pulAddend  Pointer to memory location from where value is to be
- *                         loaded and written back to.
- *
- * @return *pulAddend value before increment.
- */
-static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend )
-{
-    uint32_t ulCurrent;
-
-    ATOMIC_ENTER_CRITICAL();
-    {
-        ulCurrent = *pulAddend;
-        *pulAddend += 1;
-    }
-    ATOMIC_EXIT_CRITICAL();
-
-    return ulCurrent;
-}
-/*-----------------------------------------------------------*/
-
-/**
- * Atomic decrement
- *
- * @brief Atomically decrements the value of the specified pointer points to
- *
- * @param[in,out] pulAddend  Pointer to memory location from where value is to be
- *                         loaded and written back to.
- *
- * @return *pulAddend value before decrement.
- */
-static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend )
-{
-    uint32_t ulCurrent;
-
-    ATOMIC_ENTER_CRITICAL();
-    {
-        ulCurrent = *pulAddend;
-        *pulAddend -= 1;
-    }
-    ATOMIC_EXIT_CRITICAL();
-
-    return ulCurrent;
-}
-
-/*----------------------------- Bitwise Logical ------------------------------*/
-
-/**
- * Atomic OR
- *
- * @brief Performs an atomic OR operation on the specified values.
- *
- * @param [in, out] pulDestination  Pointer to memory location from where value is
- *                                to be loaded and written back to.
- * @param [in] ulValue            Value to be ORed with *pulDestination.
- *
- * @return The original value of *pulDestination.
- */
-static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination,
-                                                uint32_t ulValue )
-{
-    uint32_t ulCurrent;
-
-    ATOMIC_ENTER_CRITICAL();
-    {
-        ulCurrent = *pulDestination;
-        *pulDestination |= ulValue;
-    }
-    ATOMIC_EXIT_CRITICAL();
-
-    return ulCurrent;
-}
-/*-----------------------------------------------------------*/
-
-/**
- * Atomic AND
- *
- * @brief Performs an atomic AND operation on the specified values.
- *
- * @param [in, out] pulDestination  Pointer to memory location from where value is
- *                                to be loaded and written back to.
- * @param [in] ulValue            Value to be ANDed with *pulDestination.
- *
- * @return The original value of *pulDestination.
- */
-static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination,
-                                                 uint32_t ulValue )
-{
-    uint32_t ulCurrent;
-
-    ATOMIC_ENTER_CRITICAL();
-    {
-        ulCurrent = *pulDestination;
-        *pulDestination &= ulValue;
-    }
-    ATOMIC_EXIT_CRITICAL();
-
-    return ulCurrent;
-}
-/*-----------------------------------------------------------*/
-
-/**
- * Atomic NAND
- *
- * @brief Performs an atomic NAND operation on the specified values.
- *
- * @param [in, out] pulDestination  Pointer to memory location from where value is
- *                                to be loaded and written back to.
- * @param [in] ulValue            Value to be NANDed with *pulDestination.
- *
- * @return The original value of *pulDestination.
- */
-static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination,
-                                                  uint32_t ulValue )
-{
-    uint32_t ulCurrent;
-
-    ATOMIC_ENTER_CRITICAL();
-    {
-        ulCurrent = *pulDestination;
-        *pulDestination = ~( ulCurrent & ulValue );
-    }
-    ATOMIC_EXIT_CRITICAL();
-
-    return ulCurrent;
-}
-/*-----------------------------------------------------------*/
-
-/**
- * Atomic XOR
- *
- * @brief Performs an atomic XOR operation on the specified values.
- *
- * @param [in, out] pulDestination  Pointer to memory location from where value is
- *                                to be loaded and written back to.
- * @param [in] ulValue            Value to be XORed with *pulDestination.
- *
- * @return The original value of *pulDestination.
- */
-static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination,
-                                                 uint32_t ulValue )
-{
-    uint32_t ulCurrent;
-
-    ATOMIC_ENTER_CRITICAL();
-    {
-        ulCurrent = *pulDestination;
-        *pulDestination ^= ulValue;
-    }
-    ATOMIC_EXIT_CRITICAL();
-
-    return ulCurrent;
-}
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    }
-#endif
-/* *INDENT-ON* */
-
-#endif /* ATOMIC_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/croutine.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/croutine.h
deleted file mode 100644
index 4d30a83..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/croutine.h
+++ /dev/null
@@ -1,751 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef CO_ROUTINE_H
-#define CO_ROUTINE_H
-
-#ifndef INC_FREERTOS_H
-    #error "include FreeRTOS.h must appear in source files before include croutine.h"
-#endif
-
-#include "list.h"
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/* Used to hide the implementation of the co-routine control block.  The
- * control block structure however has to be included in the header due to
- * the macro implementation of the co-routine functionality. */
-typedef void * CoRoutineHandle_t;
-
-/* Defines the prototype to which co-routine functions must conform. */
-typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t,
-                                   UBaseType_t );
-
-typedef struct corCoRoutineControlBlock
-{
-    crCOROUTINE_CODE pxCoRoutineFunction;
-    ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */
-    ListItem_t xEventListItem;   /*< List item used to place the CRCB in event lists. */
-    UBaseType_t uxPriority;      /*< The priority of the co-routine in relation to other co-routines. */
-    UBaseType_t uxIndex;         /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
-    uint16_t uxState;            /*< Used internally by the co-routine implementation. */
-} CRCB_t;                        /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */
-
-/**
- * croutine. h
- * 
- * BaseType_t xCoRoutineCreate(
- *                               crCOROUTINE_CODE pxCoRoutineCode,
- *                               UBaseType_t uxPriority,
- *                               UBaseType_t uxIndex
- *                             ); 
- * 

- *
- * Create a new co-routine and add it to the list of co-routines that are
- * ready to run.
- *
- * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine
- * functions require special syntax - see the co-routine section of the WEB
- * documentation for more information.
- *
- * @param uxPriority The priority with respect to other co-routines at which
- *  the co-routine will run.
- *
- * @param uxIndex Used to distinguish between different co-routines that
- * execute the same function.  See the example below and the co-routine section
- * of the WEB documentation for further information.
- *
- * @return pdPASS if the co-routine was successfully created and added to a ready
- * list, otherwise an error code defined with ProjDefs.h.
- *
- * Example usage:
- * 
- * // Co-routine to be created.
- * void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- * {
- * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- * // This may not be necessary for const variables.
- * static const char cLedToFlash[ 2 ] = { 5, 6 };
- * static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
- *
- *   // Must start every co-routine with a call to crSTART();
- *   crSTART( xHandle );
- *
- *   for( ;; )
- *   {
- *       // This co-routine just delays for a fixed period, then toggles
- *       // an LED.  Two co-routines are created using this function, so
- *       // the uxIndex parameter is used to tell the co-routine which
- *       // LED to flash and how int32_t to delay.  This assumes xQueue has
- *       // already been created.
- *       vParTestToggleLED( cLedToFlash[ uxIndex ] );
- *       crDELAY( xHandle, uxFlashRates[ uxIndex ] );
- *   }
- *
- *   // Must end every co-routine with a call to crEND();
- *   crEND();
- * }
- *
- * // Function that creates two co-routines.
- * void vOtherFunction( void )
- * {
- * uint8_t ucParameterToPass;
- * TaskHandle_t xHandle;
- *
- *   // Create two co-routines at priority 0.  The first is given index 0
- *   // so (from the code above) toggles LED 5 every 200 ticks.  The second
- *   // is given index 1 so toggles LED 6 every 400 ticks.
- *   for( uxIndex = 0; uxIndex < 2; uxIndex++ )
- *   {
- *       xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
- *   }
- * }
- * 

- * \defgroup xCoRoutineCreate xCoRoutineCreate
- * \ingroup Tasks
- */
-BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,
-                             UBaseType_t uxPriority,
-                             UBaseType_t uxIndex );
-
-
-/**
- * croutine. h
- * 
- * void vCoRoutineSchedule( void );
- * 

- *
- * Run a co-routine.
- *
- * vCoRoutineSchedule() executes the highest priority co-routine that is able
- * to run.  The co-routine will execute until it either blocks, yields or is
- * preempted by a task.  Co-routines execute cooperatively so one
- * co-routine cannot be preempted by another, but can be preempted by a task.
- *
- * If an application comprises of both tasks and co-routines then
- * vCoRoutineSchedule should be called from the idle task (in an idle task
- * hook).
- *
- * Example usage:
- * 
- * // This idle task hook will schedule a co-routine each time it is called.
- * // The rest of the idle task will execute between co-routine calls.
- * void vApplicationIdleHook( void )
- * {
- *  vCoRoutineSchedule();
- * }
- *
- * // Alternatively, if you do not require any other part of the idle task to
- * // execute, the idle task hook can call vCoRoutineSchedule() within an
- * // infinite loop.
- * void vApplicationIdleHook( void )
- * {
- *  for( ;; )
- *  {
- *      vCoRoutineSchedule();
- *  }
- * }
- * 

- * \defgroup vCoRoutineSchedule vCoRoutineSchedule
- * \ingroup Tasks
- */
-void vCoRoutineSchedule( void );
-
-/**
- * croutine. h
- * 
- * crSTART( CoRoutineHandle_t xHandle );
- * 

- *
- * This macro MUST always be called at the start of a co-routine function.
- *
- * Example usage:
- * 
- * // Co-routine to be created.
- * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- * {
- * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- * static int32_t ulAVariable;
- *
- *   // Must start every co-routine with a call to crSTART();
- *   crSTART( xHandle );
- *
- *   for( ;; )
- *   {
- *        // Co-routine functionality goes here.
- *   }
- *
- *   // Must end every co-routine with a call to crEND();
- *   crEND();
- * }
- * 

- * \defgroup crSTART crSTART
- * \ingroup Tasks
- */
-#define crSTART( pxCRCB )                            \
-    switch( ( ( CRCB_t * ) ( pxCRCB ) )->uxState ) { \
-        case 0:
-
-/**
- * croutine. h
- * 
- * crEND();
- * 

- *
- * This macro MUST always be called at the end of a co-routine function.
- *
- * Example usage:
- * 
- * // Co-routine to be created.
- * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- * {
- * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- * static int32_t ulAVariable;
- *
- *   // Must start every co-routine with a call to crSTART();
- *   crSTART( xHandle );
- *
- *   for( ;; )
- *   {
- *        // Co-routine functionality goes here.
- *   }
- *
- *   // Must end every co-routine with a call to crEND();
- *   crEND();
- * }
- * 

- * \defgroup crSTART crSTART
- * \ingroup Tasks
- */
-#define crEND()    }
-
-/*
- * These macros are intended for internal use by the co-routine implementation
- * only.  The macros should not be used directly by application writers.
- */
-#define crSET_STATE0( xHandle )                                       \
-    ( ( CRCB_t * ) ( xHandle ) )->uxState = ( __LINE__ * 2 ); return; \
-    case ( __LINE__ * 2 ):
-#define crSET_STATE1( xHandle )                                               \
-    ( ( CRCB_t * ) ( xHandle ) )->uxState = ( ( __LINE__ * 2 ) + 1 ); return; \
-    case ( ( __LINE__ * 2 ) + 1 ):
-
-/**
- * croutine. h
- * 
- * crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
- * 

- *
- * Delay a co-routine for a fixed period of time.
- *
- * crDELAY can only be called from the co-routine function itself - not
- * from within a function called by the co-routine function.  This is because
- * co-routines do not maintain their own stack.
- *
- * @param xHandle The handle of the co-routine to delay.  This is the xHandle
- * parameter of the co-routine function.
- *
- * @param xTickToDelay The number of ticks that the co-routine should delay
- * for.  The actual amount of time this equates to is defined by
- * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS
- * can be used to convert ticks to milliseconds.
- *
- * Example usage:
- * 
- * // Co-routine to be created.
- * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- * {
- * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- * // This may not be necessary for const variables.
- * // We are to delay for 200ms.
- * static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
- *
- *   // Must start every co-routine with a call to crSTART();
- *   crSTART( xHandle );
- *
- *   for( ;; )
- *   {
- *      // Delay for 200ms.
- *      crDELAY( xHandle, xDelayTime );
- *
- *      // Do something here.
- *   }
- *
- *   // Must end every co-routine with a call to crEND();
- *   crEND();
- * }
- * 

- * \defgroup crDELAY crDELAY
- * \ingroup Tasks
- */
-#define crDELAY( xHandle, xTicksToDelay )                      \
-    if( ( xTicksToDelay ) > 0 )                                \
-    {                                                          \
-        vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \
-    }                                                          \
-    crSET_STATE0( ( xHandle ) );
-
-/**
- * 
- * crQUEUE_SEND(
- *                CoRoutineHandle_t xHandle,
- *                QueueHandle_t pxQueue,
- *                void *pvItemToQueue,
- *                TickType_t xTicksToWait,
- *                BaseType_t *pxResult
- *           )
- * 

- *
- * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
- * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
- *
- * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
- * xQueueSend() and xQueueReceive() can only be used from tasks.
- *
- * crQUEUE_SEND can only be called from the co-routine function itself - not
- * from within a function called by the co-routine function.  This is because
- * co-routines do not maintain their own stack.
- *
- * See the co-routine section of the WEB documentation for information on
- * passing data between tasks and co-routines and between ISR's and
- * co-routines.
- *
- * @param xHandle The handle of the calling co-routine.  This is the xHandle
- * parameter of the co-routine function.
- *
- * @param pxQueue The handle of the queue on which the data will be posted.
- * The handle is obtained as the return value when the queue is created using
- * the xQueueCreate() API function.
- *
- * @param pvItemToQueue A pointer to the data being posted onto the queue.
- * The number of bytes of each queued item is specified when the queue is
- * created.  This number of bytes is copied from pvItemToQueue into the queue
- * itself.
- *
- * @param xTickToDelay The number of ticks that the co-routine should block
- * to wait for space to become available on the queue, should space not be
- * available immediately. The actual amount of time this equates to is defined
- * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
- * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
- * below).
- *
- * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
- * data was successfully posted onto the queue, otherwise it will be set to an
- * error defined within ProjDefs.h.
- *
- * Example usage:
- * 
- * // Co-routine function that blocks for a fixed period then posts a number onto
- * // a queue.
- * static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- * {
- * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- * static BaseType_t xNumberToPost = 0;
- * static BaseType_t xResult;
- *
- *  // Co-routines must begin with a call to crSTART().
- *  crSTART( xHandle );
- *
- *  for( ;; )
- *  {
- *      // This assumes the queue has already been created.
- *      crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
- *
- *      if( xResult != pdPASS )
- *      {
- *          // The message was not posted!
- *      }
- *
- *      // Increment the number to be posted onto the queue.
- *      xNumberToPost++;
- *
- *      // Delay for 100 ticks.
- *      crDELAY( xHandle, 100 );
- *  }
- *
- *  // Co-routines must end with a call to crEND().
- *  crEND();
- * }
- * 

- * \defgroup crQUEUE_SEND crQUEUE_SEND
- * \ingroup Tasks
- */
-#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )           \
-    {                                                                                     \
-        *( pxResult ) = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), ( xTicksToWait ) ); \
-        if( *( pxResult ) == errQUEUE_BLOCKED )                                           \
-        {                                                                                 \
-            crSET_STATE0( ( xHandle ) );                                                  \
-            *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );                \
-        }                                                                                 \
-        if( *pxResult == errQUEUE_YIELD )                                                 \
-        {                                                                                 \
-            crSET_STATE1( ( xHandle ) );                                                  \
-            *pxResult = pdPASS;                                                           \
-        }                                                                                 \
-    }
-
-/**
- * croutine. h
- * 
- * crQUEUE_RECEIVE(
- *                   CoRoutineHandle_t xHandle,
- *                   QueueHandle_t pxQueue,
- *                   void *pvBuffer,
- *                   TickType_t xTicksToWait,
- *                   BaseType_t *pxResult
- *               )
- * 

- *
- * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
- * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
- *
- * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
- * xQueueSend() and xQueueReceive() can only be used from tasks.
- *
- * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
- * from within a function called by the co-routine function.  This is because
- * co-routines do not maintain their own stack.
- *
- * See the co-routine section of the WEB documentation for information on
- * passing data between tasks and co-routines and between ISR's and
- * co-routines.
- *
- * @param xHandle The handle of the calling co-routine.  This is the xHandle
- * parameter of the co-routine function.
- *
- * @param pxQueue The handle of the queue from which the data will be received.
- * The handle is obtained as the return value when the queue is created using
- * the xQueueCreate() API function.
- *
- * @param pvBuffer The buffer into which the received item is to be copied.
- * The number of bytes of each queued item is specified when the queue is
- * created.  This number of bytes is copied into pvBuffer.
- *
- * @param xTickToDelay The number of ticks that the co-routine should block
- * to wait for data to become available from the queue, should data not be
- * available immediately. The actual amount of time this equates to is defined
- * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
- * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
- * crQUEUE_SEND example).
- *
- * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
- * data was successfully retrieved from the queue, otherwise it will be set to
- * an error code as defined within ProjDefs.h.
- *
- * Example usage:
- * 
- * // A co-routine receives the number of an LED to flash from a queue.  It
- * // blocks on the queue until the number is received.
- * static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- * {
- * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- * static BaseType_t xResult;
- * static UBaseType_t uxLEDToFlash;
- *
- *  // All co-routines must start with a call to crSTART().
- *  crSTART( xHandle );
- *
- *  for( ;; )
- *  {
- *      // Wait for data to become available on the queue.
- *      crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
- *
- *      if( xResult == pdPASS )
- *      {
- *          // We received the LED to flash - flash it!
- *          vParTestToggleLED( uxLEDToFlash );
- *      }
- *  }
- *
- *  crEND();
- * }
- * 

- * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
- * \ingroup Tasks
- */
-#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )           \
-    {                                                                                   \
-        *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), ( xTicksToWait ) ); \
-        if( *( pxResult ) == errQUEUE_BLOCKED )                                         \
-        {                                                                               \
-            crSET_STATE0( ( xHandle ) );                                                \
-            *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), 0 );            \
-        }                                                                               \
-        if( *( pxResult ) == errQUEUE_YIELD )                                           \
-        {                                                                               \
-            crSET_STATE1( ( xHandle ) );                                                \
-            *( pxResult ) = pdPASS;                                                     \
-        }                                                                               \
-    }
-
-/**
- * croutine. h
- * 
- * crQUEUE_SEND_FROM_ISR(
- *                          QueueHandle_t pxQueue,
- *                          void *pvItemToQueue,
- *                          BaseType_t xCoRoutinePreviouslyWoken
- *                     )
- * 

- *
- * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
- * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
- * functions used by tasks.
- *
- * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
- * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
- * xQueueReceiveFromISR() can only be used to pass data between a task and and
- * ISR.
- *
- * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
- * that is being used from within a co-routine.
- *
- * See the co-routine section of the WEB documentation for information on
- * passing data between tasks and co-routines and between ISR's and
- * co-routines.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
- * the same queue multiple times from a single interrupt.  The first call
- * should always pass in pdFALSE.  Subsequent calls should pass in
- * the value returned from the previous call.
- *
- * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is
- * used by the ISR to determine if a context switch may be required following
- * the ISR.
- *
- * Example usage:
- * 
- * // A co-routine that blocks on a queue waiting for characters to be received.
- * static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- * {
- * char cRxedChar;
- * BaseType_t xResult;
- *
- *   // All co-routines must start with a call to crSTART().
- *   crSTART( xHandle );
- *
- *   for( ;; )
- *   {
- *       // Wait for data to become available on the queue.  This assumes the
- *       // queue xCommsRxQueue has already been created!
- *       crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
- *
- *       // Was a character received?
- *       if( xResult == pdPASS )
- *       {
- *           // Process the character here.
- *       }
- *   }
- *
- *   // All co-routines must end with a call to crEND().
- *   crEND();
- * }
- *
- * // An ISR that uses a queue to send characters received on a serial port to
- * // a co-routine.
- * void vUART_ISR( void )
- * {
- * char cRxedChar;
- * BaseType_t xCRWokenByPost = pdFALSE;
- *
- *   // We loop around reading characters until there are none left in the UART.
- *   while( UART_RX_REG_NOT_EMPTY() )
- *   {
- *       // Obtain the character from the UART.
- *       cRxedChar = UART_RX_REG;
- *
- *       // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
- *       // the first time around the loop.  If the post causes a co-routine
- *       // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
- *       // In this manner we can ensure that if more than one co-routine is
- *       // blocked on the queue only one is woken by this ISR no matter how
- *       // many characters are posted to the queue.
- *       xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
- *   }
- * }
- * 

- * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
- * \ingroup Tasks
- */
-#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) \
-    xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
-
-
-/**
- * croutine. h
- * 
- * crQUEUE_SEND_FROM_ISR(
- *                          QueueHandle_t pxQueue,
- *                          void *pvBuffer,
- *                          BaseType_t * pxCoRoutineWoken
- *                     )
- * 

- *
- * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
- * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
- * functions used by tasks.
- *
- * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
- * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
- * xQueueReceiveFromISR() can only be used to pass data between a task and and
- * ISR.
- *
- * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
- * from a queue that is being used from within a co-routine (a co-routine
- * posted to the queue).
- *
- * See the co-routine section of the WEB documentation for information on
- * passing data between tasks and co-routines and between ISR's and
- * co-routines.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvBuffer A pointer to a buffer into which the received item will be
- * placed.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from the queue into
- * pvBuffer.
- *
- * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
- * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a
- * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
- * *pxCoRoutineWoken will remain unchanged.
- *
- * @return pdTRUE an item was successfully received from the queue, otherwise
- * pdFALSE.
- *
- * Example usage:
- * 
- * // A co-routine that posts a character to a queue then blocks for a fixed
- * // period.  The character is incremented each time.
- * static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- * {
- * // cChar holds its value while this co-routine is blocked and must therefore
- * // be declared static.
- * static char cCharToTx = 'a';
- * BaseType_t xResult;
- *
- *   // All co-routines must start with a call to crSTART().
- *   crSTART( xHandle );
- *
- *   for( ;; )
- *   {
- *       // Send the next character to the queue.
- *       crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
- *
- *       if( xResult == pdPASS )
- *       {
- *           // The character was successfully posted to the queue.
- *       }
- *       else
- *       {
- *          // Could not post the character to the queue.
- *       }
- *
- *       // Enable the UART Tx interrupt to cause an interrupt in this
- *       // hypothetical UART.  The interrupt will obtain the character
- *       // from the queue and send it.
- *       ENABLE_RX_INTERRUPT();
- *
- *       // Increment to the next character then block for a fixed period.
- *       // cCharToTx will maintain its value across the delay as it is
- *       // declared static.
- *       cCharToTx++;
- *       if( cCharToTx > 'x' )
- *       {
- *          cCharToTx = 'a';
- *       }
- *       crDELAY( 100 );
- *   }
- *
- *   // All co-routines must end with a call to crEND().
- *   crEND();
- * }
- *
- * // An ISR that uses a queue to receive characters to send on a UART.
- * void vUART_ISR( void )
- * {
- * char cCharToTx;
- * BaseType_t xCRWokenByPost = pdFALSE;
- *
- *   while( UART_TX_REG_EMPTY() )
- *   {
- *       // Are there any characters in the queue waiting to be sent?
- *       // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
- *       // is woken by the post - ensuring that only a single co-routine is
- *       // woken no matter how many times we go around this loop.
- *       if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
- *       {
- *           SEND_CHARACTER( cCharToTx );
- *       }
- *   }
- * }
- * 

- * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
- * \ingroup Tasks
- */
-#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) \
-    xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
-
-/*
- * This function is intended for internal use by the co-routine macros only.
- * The macro nature of the co-routine implementation requires that the
- * prototype appears here.  The function should not be used by application
- * writers.
- *
- * Removes the current co-routine from its ready list and places it in the
- * appropriate delayed list.
- */
-void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
-                                 List_t * pxEventList );
-
-/*
- * This function is intended for internal use by the queue implementation only.
- * The function should not be used by application writers.
- *
- * Removes the highest priority co-routine from the event list and places it in
- * the pending ready list.
- */
-BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList );
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    }
-#endif
-/* *INDENT-ON* */
-
-#endif /* CO_ROUTINE_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/deprecated_definitions.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/deprecated_definitions.h
deleted file mode 100644
index 6adc5d0..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/deprecated_definitions.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef DEPRECATED_DEFINITIONS_H
-#define DEPRECATED_DEFINITIONS_H
-
-
-/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
- * pre-processor definition was used to ensure the pre-processor found the correct
- * portmacro.h file for the port being used.  That scheme was deprecated in favour
- * of setting the compiler's include path such that it found the correct
- * portmacro.h file - removing the need for the constant and allowing the
- * portmacro.h file to be located anywhere in relation to the port being used.  The
- * definitions below remain in the code for backward compatibility only.  New
- * projects should not use them. */
-
-#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
-    #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
-    typedef void ( __interrupt __far * pxISR )();
-#endif
-
-#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
-    #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
-    typedef void ( __interrupt __far * pxISR )();
-#endif
-
-#ifdef GCC_MEGA_AVR
-    #include "../portable/GCC/ATMega323/portmacro.h"
-#endif
-
-#ifdef IAR_MEGA_AVR
-    #include "../portable/IAR/ATMega323/portmacro.h"
-#endif
-
-#ifdef MPLAB_PIC24_PORT
-    #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
-#endif
-
-#ifdef MPLAB_DSPIC_PORT
-    #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
-#endif
-
-#ifdef MPLAB_PIC18F_PORT
-    #include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
-#endif
-
-#ifdef MPLAB_PIC32MX_PORT
-    #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
-#endif
-
-#ifdef _FEDPICC
-    #include "libFreeRTOS/Include/portmacro.h"
-#endif
-
-#ifdef SDCC_CYGNAL
-    #include "../../Source/portable/SDCC/Cygnal/portmacro.h"
-#endif
-
-#ifdef GCC_ARM7
-    #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
-#endif
-
-#ifdef GCC_ARM7_ECLIPSE
-    #include "portmacro.h"
-#endif
-
-#ifdef ROWLEY_LPC23xx
-    #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
-#endif
-
-#ifdef IAR_MSP430
-    #include "..\..\Source\portable\IAR\MSP430\portmacro.h"
-#endif
-
-#ifdef GCC_MSP430
-    #include "../../Source/portable/GCC/MSP430F449/portmacro.h"
-#endif
-
-#ifdef ROWLEY_MSP430
-    #include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
-#endif
-
-#ifdef ARM7_LPC21xx_KEIL_RVDS
-    #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
-#endif
-
-#ifdef SAM7_GCC
-    #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
-#endif
-
-#ifdef SAM7_IAR
-    #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
-#endif
-
-#ifdef SAM9XE_IAR
-    #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
-#endif
-
-#ifdef LPC2000_IAR
-    #include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
-#endif
-
-#ifdef STR71X_IAR
-    #include "..\..\Source\portable\IAR\STR71x\portmacro.h"
-#endif
-
-#ifdef STR75X_IAR
-    #include "..\..\Source\portable\IAR\STR75x\portmacro.h"
-#endif
-
-#ifdef STR75X_GCC
-    #include "..\..\Source\portable\GCC\STR75x\portmacro.h"
-#endif
-
-#ifdef STR91X_IAR
-    #include "..\..\Source\portable\IAR\STR91x\portmacro.h"
-#endif
-
-#ifdef GCC_H8S
-    #include "../../Source/portable/GCC/H8S2329/portmacro.h"
-#endif
-
-#ifdef GCC_AT91FR40008
-    #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
-#endif
-
-#ifdef RVDS_ARMCM3_LM3S102
-    #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
-#endif
-
-#ifdef GCC_ARMCM3_LM3S102
-    #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
-#endif
-
-#ifdef GCC_ARMCM3
-    #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
-#endif
-
-#ifdef IAR_ARM_CM3
-    #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
-#endif
-
-#ifdef IAR_ARMCM3_LM
-    #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
-#endif
-
-#ifdef HCS12_CODE_WARRIOR
-    #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
-#endif
-
-#ifdef MICROBLAZE_GCC
-    #include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
-#endif
-
-#ifdef TERN_EE
-    #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
-#endif
-
-#ifdef GCC_HCS12
-    #include "../../Source/portable/GCC/HCS12/portmacro.h"
-#endif
-
-#ifdef GCC_MCF5235
-    #include "../../Source/portable/GCC/MCF5235/portmacro.h"
-#endif
-
-#ifdef COLDFIRE_V2_GCC
-    #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
-#endif
-
-#ifdef COLDFIRE_V2_CODEWARRIOR
-    #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
-#endif
-
-#ifdef GCC_PPC405
-    #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
-#endif
-
-#ifdef GCC_PPC440
-    #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
-#endif
-
-#ifdef _16FX_SOFTUNE
-    #include "..\..\Source\portable\Softune\MB96340\portmacro.h"
-#endif
-
-#ifdef BCC_INDUSTRIAL_PC_PORT
-
-/* A short file name has to be used in place of the normal
- * FreeRTOSConfig.h when using the Borland compiler. */
-    #include "frconfig.h"
-    #include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
-    typedef void ( __interrupt __far * pxISR )();
-#endif
-
-#ifdef BCC_FLASH_LITE_186_PORT
-
-/* A short file name has to be used in place of the normal
- * FreeRTOSConfig.h when using the Borland compiler. */
-    #include "frconfig.h"
-    #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
-    typedef void ( __interrupt __far * pxISR )();
-#endif
-
-#ifdef __GNUC__
-    #ifdef __AVR32_AVR32A__
-        #include "portmacro.h"
-    #endif
-#endif
-
-#ifdef __ICCAVR32__
-    #ifdef __CORE__
-        #if __CORE__ == __AVR32A__
-            #include "portmacro.h"
-        #endif
-    #endif
-#endif
-
-#ifdef __91467D
-    #include "portmacro.h"
-#endif
-
-#ifdef __96340
-    #include "portmacro.h"
-#endif
-
-
-#ifdef __IAR_V850ES_Fx3__
-    #include "../../Source/portable/IAR/V850ES/portmacro.h"
-#endif
-
-#ifdef __IAR_V850ES_Jx3__
-    #include "../../Source/portable/IAR/V850ES/portmacro.h"
-#endif
-
-#ifdef __IAR_V850ES_Jx3_L__
-    #include "../../Source/portable/IAR/V850ES/portmacro.h"
-#endif
-
-#ifdef __IAR_V850ES_Jx2__
-    #include "../../Source/portable/IAR/V850ES/portmacro.h"
-#endif
-
-#ifdef __IAR_V850ES_Hx2__
-    #include "../../Source/portable/IAR/V850ES/portmacro.h"
-#endif
-
-#ifdef __IAR_78K0R_Kx3__
-    #include "../../Source/portable/IAR/78K0R/portmacro.h"
-#endif
-
-#ifdef __IAR_78K0R_Kx3L__
-    #include "../../Source/portable/IAR/78K0R/portmacro.h"
-#endif
-
-#endif /* DEPRECATED_DEFINITIONS_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/event_groups.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/event_groups.h
deleted file mode 100644
index 036ef8e..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/event_groups.h
+++ /dev/null
@@ -1,775 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef EVENT_GROUPS_H
-#define EVENT_GROUPS_H
-
-#ifndef INC_FREERTOS_H
-    #error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
-#endif
-
-/* FreeRTOS includes. */
-#include "timers.h"
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/**
- * An event group is a collection of bits to which an application can assign a
- * meaning.  For example, an application may create an event group to convey
- * the status of various CAN bus related events in which bit 0 might mean "A CAN
- * message has been received and is ready for processing", bit 1 might mean "The
- * application has queued a message that is ready for sending onto the CAN
- * network", and bit 2 might mean "It is time to send a SYNC message onto the
- * CAN network" etc.  A task can then test the bit values to see which events
- * are active, and optionally enter the Blocked state to wait for a specified
- * bit or a group of specified bits to be active.  To continue the CAN bus
- * example, a CAN controlling task can enter the Blocked state (and therefore
- * not consume any processing time) until either bit 0, bit 1 or bit 2 are
- * active, at which time the bit that was actually active would inform the task
- * which action it had to take (process a received message, send a message, or
- * send a SYNC).
- *
- * The event groups implementation contains intelligence to avoid race
- * conditions that would otherwise occur were an application to use a simple
- * variable for the same purpose.  This is particularly important with respect
- * to when a bit within an event group is to be cleared, and when bits have to
- * be set and then tested atomically - as is the case where event groups are
- * used to create a synchronisation point between multiple tasks (a
- * 'rendezvous').
- *
- * \defgroup EventGroup
- */
-
-
-
-/**
- * event_groups.h
- *
- * Type by which event groups are referenced.  For example, a call to
- * xEventGroupCreate() returns an EventGroupHandle_t variable that can then
- * be used as a parameter to other event group functions.
- *
- * \defgroup EventGroupHandle_t EventGroupHandle_t
- * \ingroup EventGroup
- */
-struct EventGroupDef_t;
-typedef struct EventGroupDef_t   * EventGroupHandle_t;
-
-/*
- * The type that holds event bits always matches TickType_t - therefore the
- * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,
- * 32 bits if set to 0.
- *
- * \defgroup EventBits_t EventBits_t
- * \ingroup EventGroup
- */
-typedef TickType_t               EventBits_t;
-
-/**
- * event_groups.h
- * 
- * EventGroupHandle_t xEventGroupCreate( void );
- * 

- *
- * Create a new event group.
- *
- * Internally, within the FreeRTOS implementation, event groups use a [small]
- * block of memory, in which the event group's structure is stored.  If an event
- * groups is created using xEventGropuCreate() then the required memory is
- * automatically dynamically allocated inside the xEventGroupCreate() function.
- * (see https://www.FreeRTOS.org/a00111.html).  If an event group is created
- * using xEventGropuCreateStatic() then the application writer must instead
- * provide the memory that will get used by the event group.
- * xEventGroupCreateStatic() therefore allows an event group to be created
- * without using any dynamic memory allocation.
- *
- * Although event groups are not related to ticks, for internal implementation
- * reasons the number of bits available for use in an event group is dependent
- * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
- * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
- * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
- * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
- * event bits within an event group.
- *
- * @return If the event group was created then a handle to the event group is
- * returned.  If there was insufficient FreeRTOS heap available to create the
- * event group then NULL is returned.  See https://www.FreeRTOS.org/a00111.html
- *
- * Example usage:
- * 
- *  // Declare a variable to hold the created event group.
- *  EventGroupHandle_t xCreatedEventGroup;
- *
- *  // Attempt to create the event group.
- *  xCreatedEventGroup = xEventGroupCreate();
- *
- *  // Was the event group created successfully?
- *  if( xCreatedEventGroup == NULL )
- *  {
- *      // The event group was not created because there was insufficient
- *      // FreeRTOS heap available.
- *  }
- *  else
- *  {
- *      // The event group was created.
- *  }
- * 

- * \defgroup xEventGroupCreate xEventGroupCreate
- * \ingroup EventGroup
- */
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * event_groups.h
- * 
- * EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
- * 

- *
- * Create a new event group.
- *
- * Internally, within the FreeRTOS implementation, event groups use a [small]
- * block of memory, in which the event group's structure is stored.  If an event
- * groups is created using xEventGropuCreate() then the required memory is
- * automatically dynamically allocated inside the xEventGroupCreate() function.
- * (see https://www.FreeRTOS.org/a00111.html).  If an event group is created
- * using xEventGropuCreateStatic() then the application writer must instead
- * provide the memory that will get used by the event group.
- * xEventGroupCreateStatic() therefore allows an event group to be created
- * without using any dynamic memory allocation.
- *
- * Although event groups are not related to ticks, for internal implementation
- * reasons the number of bits available for use in an event group is dependent
- * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
- * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
- * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
- * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
- * event bits within an event group.
- *
- * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
- * StaticEventGroup_t, which will be then be used to hold the event group's data
- * structures, removing the need for the memory to be allocated dynamically.
- *
- * @return If the event group was created then a handle to the event group is
- * returned.  If pxEventGroupBuffer was NULL then NULL is returned.
- *
- * Example usage:
- * 
- *  // StaticEventGroup_t is a publicly accessible structure that has the same
- *  // size and alignment requirements as the real event group structure.  It is
- *  // provided as a mechanism for applications to know the size of the event
- *  // group (which is dependent on the architecture and configuration file
- *  // settings) without breaking the strict data hiding policy by exposing the
- *  // real event group internals.  This StaticEventGroup_t variable is passed
- *  // into the xSemaphoreCreateEventGroupStatic() function and is used to store
- *  // the event group's data structures
- *  StaticEventGroup_t xEventGroupBuffer;
- *
- *  // Create the event group without dynamically allocating any memory.
- *  xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
- * 

- */
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * event_groups.h
- * 
- *  EventBits_t xEventGroupWaitBits(    EventGroupHandle_t xEventGroup,
- *                                      const EventBits_t uxBitsToWaitFor,
- *                                      const BaseType_t xClearOnExit,
- *                                      const BaseType_t xWaitForAllBits,
- *                                      const TickType_t xTicksToWait );
- * 

- *
- * [Potentially] block to wait for one or more bits to be set within a
- * previously created event group.
- *
- * This function cannot be called from an interrupt.
- *
- * @param xEventGroup The event group in which the bits are being tested.  The
- * event group must have previously been created using a call to
- * xEventGroupCreate().
- *
- * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
- * inside the event group.  For example, to wait for bit 0 and/or bit 2 set
- * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set
- * uxBitsToWaitFor to 0x07.  Etc.
- *
- * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within
- * uxBitsToWaitFor that are set within the event group will be cleared before
- * xEventGroupWaitBits() returns if the wait condition was met (if the function
- * returns for a reason other than a timeout).  If xClearOnExit is set to
- * pdFALSE then the bits set in the event group are not altered when the call to
- * xEventGroupWaitBits() returns.
- *
- * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then
- * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
- * are set or the specified block time expires.  If xWaitForAllBits is set to
- * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set
- * in uxBitsToWaitFor is set or the specified block time expires.  The block
- * time is specified by the xTicksToWait parameter.
- *
- * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
- * for one/all (depending on the xWaitForAllBits value) of the bits specified by
- * uxBitsToWaitFor to become set.
- *
- * @return The value of the event group at the time either the bits being waited
- * for became set, or the block time expired.  Test the return value to know
- * which bits were set.  If xEventGroupWaitBits() returned because its timeout
- * expired then not all the bits being waited for will be set.  If
- * xEventGroupWaitBits() returned because the bits it was waiting for were set
- * then the returned value is the event group value before any bits were
- * automatically cleared in the case that xClearOnExit parameter was set to
- * pdTRUE.
- *
- * Example usage:
- * 
- #define BIT_0 ( 1 << 0 )
- #define BIT_4 ( 1 << 4 )
- *
- * void aFunction( EventGroupHandle_t xEventGroup )
- * {
- * EventBits_t uxBits;
- * const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
- *
- *      // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
- *      // the event group.  Clear the bits before exiting.
- *      uxBits = xEventGroupWaitBits(
- *                  xEventGroup,    // The event group being tested.
- *                  BIT_0 | BIT_4,  // The bits within the event group to wait for.
- *                  pdTRUE,         // BIT_0 and BIT_4 should be cleared before returning.
- *                  pdFALSE,        // Don't wait for both bits, either bit will do.
- *                  xTicksToWait ); // Wait a maximum of 100ms for either bit to be set.
- *
- *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
- *      {
- *          // xEventGroupWaitBits() returned because both bits were set.
- *      }
- *      else if( ( uxBits & BIT_0 ) != 0 )
- *      {
- *          // xEventGroupWaitBits() returned because just BIT_0 was set.
- *      }
- *      else if( ( uxBits & BIT_4 ) != 0 )
- *      {
- *          // xEventGroupWaitBits() returned because just BIT_4 was set.
- *      }
- *      else
- *      {
- *          // xEventGroupWaitBits() returned because xTicksToWait ticks passed
- *          // without either BIT_0 or BIT_4 becoming set.
- *      }
- * }
- * 

- * \defgroup xEventGroupWaitBits xEventGroupWaitBits
- * \ingroup EventGroup
- */
-EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 const BaseType_t xClearOnExit,
-                                 const BaseType_t xWaitForAllBits,
-                                 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * event_groups.h
- * 
- *  EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
- * 

- *
- * Clear bits within an event group.  This function cannot be called from an
- * interrupt.
- *
- * @param xEventGroup The event group in which the bits are to be cleared.
- *
- * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
- * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to
- * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
- *
- * @return The value of the event group before the specified bits were cleared.
- *
- * Example usage:
- * 
- #define BIT_0 ( 1 << 0 )
- #define BIT_4 ( 1 << 4 )
- *
- * void aFunction( EventGroupHandle_t xEventGroup )
- * {
- * EventBits_t uxBits;
- *
- *      // Clear bit 0 and bit 4 in xEventGroup.
- *      uxBits = xEventGroupClearBits(
- *                              xEventGroup,    // The event group being updated.
- *                              BIT_0 | BIT_4 );// The bits being cleared.
- *
- *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
- *      {
- *          // Both bit 0 and bit 4 were set before xEventGroupClearBits() was
- *          // called.  Both will now be clear (not set).
- *      }
- *      else if( ( uxBits & BIT_0 ) != 0 )
- *      {
- *          // Bit 0 was set before xEventGroupClearBits() was called.  It will
- *          // now be clear.
- *      }
- *      else if( ( uxBits & BIT_4 ) != 0 )
- *      {
- *          // Bit 4 was set before xEventGroupClearBits() was called.  It will
- *          // now be clear.
- *      }
- *      else
- *      {
- *          // Neither bit 0 nor bit 4 were set in the first place.
- *      }
- * }
- * 

- * \defgroup xEventGroupClearBits xEventGroupClearBits
- * \ingroup EventGroup
- */
-EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                  const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
-
-/**
- * event_groups.h
- * 
- *  BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
- * 

- *
- * A version of xEventGroupClearBits() that can be called from an interrupt.
- *
- * Setting bits in an event group is not a deterministic operation because there
- * are an unknown number of tasks that may be waiting for the bit or bits being
- * set.  FreeRTOS does not allow nondeterministic operations to be performed
- * while interrupts are disabled, so protects event groups that are accessed
- * from tasks by suspending the scheduler rather than disabling interrupts.  As
- * a result event groups cannot be accessed directly from an interrupt service
- * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the
- * timer task to have the clear operation performed in the context of the timer
- * task.
- *
- * @param xEventGroup The event group in which the bits are to be cleared.
- *
- * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
- * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3
- * and bit 0 set uxBitsToClear to 0x09.
- *
- * @return If the request to execute the function was posted successfully then
- * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
- * if the timer service queue was full.
- *
- * Example usage:
- * 
- #define BIT_0 ( 1 << 0 )
- #define BIT_4 ( 1 << 4 )
- *
- * // An event group which it is assumed has already been created by a call to
- * // xEventGroupCreate().
- * EventGroupHandle_t xEventGroup;
- *
- * void anInterruptHandler( void )
- * {
- *      // Clear bit 0 and bit 4 in xEventGroup.
- *      xResult = xEventGroupClearBitsFromISR(
- *                          xEventGroup,     // The event group being updated.
- *                          BIT_0 | BIT_4 ); // The bits being set.
- *
- *      if( xResult == pdPASS )
- *      {
- *          // The message was posted successfully.
- *      }
- * }
- * 

- * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
- * \ingroup EventGroup
- */
-#if ( configUSE_TRACE_FACILITY == 1 )
-    BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
-                                            const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
-#else
-    #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) \
-    xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
-#endif
-
-/**
- * event_groups.h
- * 
- *  EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
- * 

- *
- * Set bits within an event group.
- * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()
- * is a version that can be called from an interrupt.
- *
- * Setting bits in an event group will automatically unblock tasks that are
- * blocked waiting for the bits.
- *
- * @param xEventGroup The event group in which the bits are to be set.
- *
- * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
- * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
- * and bit 0 set uxBitsToSet to 0x09.
- *
- * @return The value of the event group at the time the call to
- * xEventGroupSetBits() returns.  There are two reasons why the returned value
- * might have the bits specified by the uxBitsToSet parameter cleared.  First,
- * if setting a bit results in a task that was waiting for the bit leaving the
- * blocked state then it is possible the bit will be cleared automatically
- * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any
- * unblocked (or otherwise Ready state) task that has a priority above that of
- * the task that called xEventGroupSetBits() will execute and may change the
- * event group value before the call to xEventGroupSetBits() returns.
- *
- * Example usage:
- * 
- #define BIT_0 ( 1 << 0 )
- #define BIT_4 ( 1 << 4 )
- *
- * void aFunction( EventGroupHandle_t xEventGroup )
- * {
- * EventBits_t uxBits;
- *
- *      // Set bit 0 and bit 4 in xEventGroup.
- *      uxBits = xEventGroupSetBits(
- *                          xEventGroup,    // The event group being updated.
- *                          BIT_0 | BIT_4 );// The bits being set.
- *
- *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
- *      {
- *          // Both bit 0 and bit 4 remained set when the function returned.
- *      }
- *      else if( ( uxBits & BIT_0 ) != 0 )
- *      {
- *          // Bit 0 remained set when the function returned, but bit 4 was
- *          // cleared.  It might be that bit 4 was cleared automatically as a
- *          // task that was waiting for bit 4 was removed from the Blocked
- *          // state.
- *      }
- *      else if( ( uxBits & BIT_4 ) != 0 )
- *      {
- *          // Bit 4 remained set when the function returned, but bit 0 was
- *          // cleared.  It might be that bit 0 was cleared automatically as a
- *          // task that was waiting for bit 0 was removed from the Blocked
- *          // state.
- *      }
- *      else
- *      {
- *          // Neither bit 0 nor bit 4 remained set.  It might be that a task
- *          // was waiting for both of the bits to be set, and the bits were
- *          // cleared as the task left the Blocked state.
- *      }
- * }
- * 

- * \defgroup xEventGroupSetBits xEventGroupSetBits
- * \ingroup EventGroup
- */
-EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
-
-/**
- * event_groups.h
- * 
- *  BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
- * 

- *
- * A version of xEventGroupSetBits() that can be called from an interrupt.
- *
- * Setting bits in an event group is not a deterministic operation because there
- * are an unknown number of tasks that may be waiting for the bit or bits being
- * set.  FreeRTOS does not allow nondeterministic operations to be performed in
- * interrupts or from critical sections.  Therefore xEventGroupSetBitsFromISR()
- * sends a message to the timer task to have the set operation performed in the
- * context of the timer task - where a scheduler lock is used in place of a
- * critical section.
- *
- * @param xEventGroup The event group in which the bits are to be set.
- *
- * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
- * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
- * and bit 0 set uxBitsToSet to 0x09.
- *
- * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
- * will result in a message being sent to the timer daemon task.  If the
- * priority of the timer daemon task is higher than the priority of the
- * currently running task (the task the interrupt interrupted) then
- * *pxHigherPriorityTaskWoken will be set to pdTRUE by
- * xEventGroupSetBitsFromISR(), indicating that a context switch should be
- * requested before the interrupt exits.  For that reason
- * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
- * example code below.
- *
- * @return If the request to execute the function was posted successfully then
- * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
- * if the timer service queue was full.
- *
- * Example usage:
- * 
- #define BIT_0 ( 1 << 0 )
- #define BIT_4 ( 1 << 4 )
- *
- * // An event group which it is assumed has already been created by a call to
- * // xEventGroupCreate().
- * EventGroupHandle_t xEventGroup;
- *
- * void anInterruptHandler( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken, xResult;
- *
- *      // xHigherPriorityTaskWoken must be initialised to pdFALSE.
- *      xHigherPriorityTaskWoken = pdFALSE;
- *
- *      // Set bit 0 and bit 4 in xEventGroup.
- *      xResult = xEventGroupSetBitsFromISR(
- *                          xEventGroup,    // The event group being updated.
- *                          BIT_0 | BIT_4   // The bits being set.
- *                          &xHigherPriorityTaskWoken );
- *
- *      // Was the message posted successfully?
- *      if( xResult == pdPASS )
- *      {
- *          // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
- *          // switch should be requested.  The macro used is port specific and
- *          // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
- *          // refer to the documentation page for the port being used.
- *          portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
- *      }
- * }
- * 

- * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
- * \ingroup EventGroup
- */
-#if ( configUSE_TRACE_FACILITY == 1 )
-    BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToSet,
-                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-#else
-    #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) \
-    xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )
-#endif
-
-/**
- * event_groups.h
- * 
- *  EventBits_t xEventGroupSync(    EventGroupHandle_t xEventGroup,
- *                                  const EventBits_t uxBitsToSet,
- *                                  const EventBits_t uxBitsToWaitFor,
- *                                  TickType_t xTicksToWait );
- * 

- *
- * Atomically set bits within an event group, then wait for a combination of
- * bits to be set within the same event group.  This functionality is typically
- * used to synchronise multiple tasks, where each task has to wait for the other
- * tasks to reach a synchronisation point before proceeding.
- *
- * This function cannot be used from an interrupt.
- *
- * The function will return before its block time expires if the bits specified
- * by the uxBitsToWait parameter are set, or become set within that time.  In
- * this case all the bits specified by uxBitsToWait will be automatically
- * cleared before the function returns.
- *
- * @param xEventGroup The event group in which the bits are being tested.  The
- * event group must have previously been created using a call to
- * xEventGroupCreate().
- *
- * @param uxBitsToSet The bits to set in the event group before determining
- * if, and possibly waiting for, all the bits specified by the uxBitsToWait
- * parameter are set.
- *
- * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
- * inside the event group.  For example, to wait for bit 0 and bit 2 set
- * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set
- * uxBitsToWaitFor to 0x07.  Etc.
- *
- * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
- * for all of the bits specified by uxBitsToWaitFor to become set.
- *
- * @return The value of the event group at the time either the bits being waited
- * for became set, or the block time expired.  Test the return value to know
- * which bits were set.  If xEventGroupSync() returned because its timeout
- * expired then not all the bits being waited for will be set.  If
- * xEventGroupSync() returned because all the bits it was waiting for were
- * set then the returned value is the event group value before any bits were
- * automatically cleared.
- *
- * Example usage:
- * 
- * // Bits used by the three tasks.
- #define TASK_0_BIT     ( 1 << 0 )
- #define TASK_1_BIT     ( 1 << 1 )
- #define TASK_2_BIT     ( 1 << 2 )
- *
- #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
- *
- * // Use an event group to synchronise three tasks.  It is assumed this event
- * // group has already been created elsewhere.
- * EventGroupHandle_t xEventBits;
- *
- * void vTask0( void *pvParameters )
- * {
- * EventBits_t uxReturn;
- * TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
- *
- *   for( ;; )
- *   {
- *      // Perform task functionality here.
- *
- *      // Set bit 0 in the event flag to note this task has reached the
- *      // sync point.  The other two tasks will set the other two bits defined
- *      // by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
- *      // point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
- *      // for this to happen.
- *      uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
- *
- *      if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
- *      {
- *          // All three tasks reached the synchronisation point before the call
- *          // to xEventGroupSync() timed out.
- *      }
- *  }
- * }
- *
- * void vTask1( void *pvParameters )
- * {
- *   for( ;; )
- *   {
- *      // Perform task functionality here.
- *
- *      // Set bit 1 in the event flag to note this task has reached the
- *      // synchronisation point.  The other two tasks will set the other two
- *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the
- *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait
- *      // indefinitely for this to happen.
- *      xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
- *
- *      // xEventGroupSync() was called with an indefinite block time, so
- *      // this task will only reach here if the synchronisation was made by all
- *      // three tasks, so there is no need to test the return value.
- *   }
- * }
- *
- * void vTask2( void *pvParameters )
- * {
- *   for( ;; )
- *   {
- *      // Perform task functionality here.
- *
- *      // Set bit 2 in the event flag to note this task has reached the
- *      // synchronisation point.  The other two tasks will set the other two
- *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the
- *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait
- *      // indefinitely for this to happen.
- *      xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
- *
- *      // xEventGroupSync() was called with an indefinite block time, so
- *      // this task will only reach here if the synchronisation was made by all
- *      // three tasks, so there is no need to test the return value.
- *  }
- * }
- *
- * 

- * \defgroup xEventGroupSync xEventGroupSync
- * \ingroup EventGroup
- */
-EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
-                             const EventBits_t uxBitsToSet,
-                             const EventBits_t uxBitsToWaitFor,
-                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-
-/**
- * event_groups.h
- * 
- *  EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
- * 

- *
- * Returns the current value of the bits in an event group.  This function
- * cannot be used from an interrupt.
- *
- * @param xEventGroup The event group being queried.
- *
- * @return The event group bits at the time xEventGroupGetBits() was called.
- *
- * \defgroup xEventGroupGetBits xEventGroupGetBits
- * \ingroup EventGroup
- */
-#define xEventGroupGetBits( xEventGroup )    xEventGroupClearBits( xEventGroup, 0 )
-
-/**
- * event_groups.h
- * 
- *  EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
- * 

- *
- * A version of xEventGroupGetBits() that can be called from an ISR.
- *
- * @param xEventGroup The event group being queried.
- *
- * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
- *
- * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR
- * \ingroup EventGroup
- */
-EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
-
-/**
- * event_groups.h
- * 
- *  void xEventGroupDelete( EventGroupHandle_t xEventGroup );
- * 

- *
- * Delete an event group that was previously created by a call to
- * xEventGroupCreate().  Tasks that are blocked on the event group will be
- * unblocked and obtain 0 as the event group's value.
- *
- * @param xEventGroup The event group being deleted.
- */
-void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
-
-/* For internal use only. */
-void vEventGroupSetBitsCallback( void * pvEventGroup,
-                                 const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
-void vEventGroupClearBitsCallback( void * pvEventGroup,
-                                   const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
-
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-    UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) PRIVILEGED_FUNCTION;
-    void vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;
-#endif
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    }
-#endif
-/* *INDENT-ON* */
-
-#endif /* EVENT_GROUPS_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/list.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/list.h
deleted file mode 100644
index f1e0f3c..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/list.h
+++ /dev/null
@@ -1,417 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * This is the list implementation used by the scheduler.  While it is tailored
- * heavily for the schedulers needs, it is also available for use by
- * application code.
- *
- * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a
- * numeric value (xItemValue).  Most of the time the lists are sorted in
- * descending item value order.
- *
- * Lists are created already containing one list item.  The value of this
- * item is the maximum possible that can be stored, it is therefore always at
- * the end of the list and acts as a marker.  The list member pxHead always
- * points to this marker - even though it is at the tail of the list.  This
- * is because the tail contains a wrap back pointer to the true head of
- * the list.
- *
- * In addition to it's value, each list item contains a pointer to the next
- * item in the list (pxNext), a pointer to the list it is in (pxContainer)
- * and a pointer to back to the object that contains it.  These later two
- * pointers are included for efficiency of list manipulation.  There is
- * effectively a two way link between the object containing the list item and
- * the list item itself.
- *
- *
- * \page ListIntroduction List Implementation
- * \ingroup FreeRTOSIntro
- */
-
-
-#ifndef LIST_H
-#define LIST_H
-
-#ifndef INC_FREERTOS_H
-    #error "FreeRTOS.h must be included before list.h"
-#endif
-
-/*
- * The list structure members are modified from within interrupts, and therefore
- * by rights should be declared volatile.  However, they are only modified in a
- * functionally atomic way (within critical sections of with the scheduler
- * suspended) and are either passed by reference into a function or indexed via
- * a volatile variable.  Therefore, in all use cases tested so far, the volatile
- * qualifier can be omitted in order to provide a moderate performance
- * improvement without adversely affecting functional behaviour.  The assembly
- * instructions generated by the IAR, ARM and GCC compilers when the respective
- * compiler's options were set for maximum optimisation has been inspected and
- * deemed to be as intended.  That said, as compiler technology advances, and
- * especially if aggressive cross module optimisation is used (a use case that
- * has not been exercised to any great extend) then it is feasible that the
- * volatile qualifier will be needed for correct optimisation.  It is expected
- * that a compiler removing essential code because, without the volatile
- * qualifier on the list structure members and with aggressive cross module
- * optimisation, the compiler deemed the code unnecessary will result in
- * complete and obvious failure of the scheduler.  If this is ever experienced
- * then the volatile qualifier can be inserted in the relevant places within the
- * list structures by simply defining configLIST_VOLATILE to volatile in
- * FreeRTOSConfig.h (as per the example at the bottom of this comment block).
- * If configLIST_VOLATILE is not defined then the preprocessor directives below
- * will simply #define configLIST_VOLATILE away completely.
- *
- * To use volatile list structure members then add the following line to
- * FreeRTOSConfig.h (without the quotes):
- * "#define configLIST_VOLATILE volatile"
- */
-#ifndef configLIST_VOLATILE
-    #define configLIST_VOLATILE
-#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/* Macros that can be used to place known values within the list structures,
- * then check that the known values do not get corrupted during the execution of
- * the application.   These may catch the list data structures being overwritten in
- * memory.  They will not catch data errors caused by incorrect configuration or
- * use of FreeRTOS.*/
-#if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
-    /* Define the macros to do nothing. */
-    #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
-    #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
-    #define listFIRST_LIST_INTEGRITY_CHECK_VALUE
-    #define listSECOND_LIST_INTEGRITY_CHECK_VALUE
-    #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
-    #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
-    #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
-    #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
-    #define listTEST_LIST_ITEM_INTEGRITY( pxItem )
-    #define listTEST_LIST_INTEGRITY( pxList )
-#else /* if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) */
-    /* Define macros that add new members into the list structures. */
-    #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE     TickType_t xListItemIntegrityValue1;
-    #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE    TickType_t xListItemIntegrityValue2;
-    #define listFIRST_LIST_INTEGRITY_CHECK_VALUE          TickType_t xListIntegrityValue1;
-    #define listSECOND_LIST_INTEGRITY_CHECK_VALUE         TickType_t xListIntegrityValue2;
-
-/* Define macros that set the new structure members to known values. */
-    #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )     ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
-    #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )    ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
-    #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )              ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
-    #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )              ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
-
-/* Define macros that will assert if one of the structure members does not
- * contain its expected value. */
-    #define listTEST_LIST_ITEM_INTEGRITY( pxItem )                      configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
-    #define listTEST_LIST_INTEGRITY( pxList )                           configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
-#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */
-
-
-/*
- * Definition of the only type of object that a list can contain.
- */
-struct xLIST;
-struct xLIST_ITEM
-{
-    listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE               /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-    configLIST_VOLATILE TickType_t xItemValue;              /*< The value being listed.  In most cases this is used to sort the list in descending order. */
-    struct xLIST_ITEM * configLIST_VOLATILE pxNext;         /*< Pointer to the next ListItem_t in the list. */
-    struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;     /*< Pointer to the previous ListItem_t in the list. */
-    void * pvOwner;                                         /*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */
-    struct xLIST * configLIST_VOLATILE pxContainer;         /*< Pointer to the list in which this list item is placed (if any). */
-    listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE              /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-};
-typedef struct xLIST_ITEM ListItem_t;                       /* For some reason lint wants this as two separate definitions. */
-
-struct xMINI_LIST_ITEM
-{
-    listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE     /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-    configLIST_VOLATILE TickType_t xItemValue;
-    struct xLIST_ITEM * configLIST_VOLATILE pxNext;
-    struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
-};
-typedef struct xMINI_LIST_ITEM MiniListItem_t;
-
-/*
- * Definition of the type of queue used by the scheduler.
- */
-typedef struct xLIST
-{
-    listFIRST_LIST_INTEGRITY_CHECK_VALUE          /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-    volatile UBaseType_t uxNumberOfItems;
-    ListItem_t * configLIST_VOLATILE pxIndex;     /*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
-    MiniListItem_t xListEnd;                      /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
-    listSECOND_LIST_INTEGRITY_CHECK_VALUE         /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-} List_t;
-
-/*
- * Access macro to set the owner of a list item.  The owner of a list item
- * is the object (usually a TCB) that contains the list item.
- *
- * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
- * \ingroup LinkedList
- */
-#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )    ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
-
-/*
- * Access macro to get the owner of a list item.  The owner of a list item
- * is the object (usually a TCB) that contains the list item.
- *
- * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
- * \ingroup LinkedList
- */
-#define listGET_LIST_ITEM_OWNER( pxListItem )             ( ( pxListItem )->pvOwner )
-
-/*
- * Access macro to set the value of the list item.  In most cases the value is
- * used to sort the list in descending order.
- *
- * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
- * \ingroup LinkedList
- */
-#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )     ( ( pxListItem )->xItemValue = ( xValue ) )
-
-/*
- * Access macro to retrieve the value of the list item.  The value can
- * represent anything - for example the priority of a task, or the time at
- * which a task should be unblocked.
- *
- * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
- * \ingroup LinkedList
- */
-#define listGET_LIST_ITEM_VALUE( pxListItem )             ( ( pxListItem )->xItemValue )
-
-/*
- * Access macro to retrieve the value of the list item at the head of a given
- * list.
- *
- * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
- * \ingroup LinkedList
- */
-#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )        ( ( ( pxList )->xListEnd ).pxNext->xItemValue )
-
-/*
- * Return the list item at the head of the list.
- *
- * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
- * \ingroup LinkedList
- */
-#define listGET_HEAD_ENTRY( pxList )                      ( ( ( pxList )->xListEnd ).pxNext )
-
-/*
- * Return the next list item.
- *
- * \page listGET_NEXT listGET_NEXT
- * \ingroup LinkedList
- */
-#define listGET_NEXT( pxListItem )                        ( ( pxListItem )->pxNext )
-
-/*
- * Return the list item that marks the end of the list
- *
- * \page listGET_END_MARKER listGET_END_MARKER
- * \ingroup LinkedList
- */
-#define listGET_END_MARKER( pxList )                      ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
-
-/*
- * Access macro to determine if a list contains any items.  The macro will
- * only have the value true if the list is empty.
- *
- * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
- * \ingroup LinkedList
- */
-#define listLIST_IS_EMPTY( pxList )                       ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )
-
-/*
- * Access macro to return the number of items in the list.
- */
-#define listCURRENT_LIST_LENGTH( pxList )                 ( ( pxList )->uxNumberOfItems )
-
-/*
- * Access function to obtain the owner of the next entry in a list.
- *
- * The list member pxIndex is used to walk through a list.  Calling
- * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
- * and returns that entry's pxOwner parameter.  Using multiple calls to this
- * function it is therefore possible to move through every item contained in
- * a list.
- *
- * The pxOwner parameter of a list item is a pointer to the object that owns
- * the list item.  In the scheduler this is normally a task control block.
- * The pxOwner parameter effectively creates a two way link between the list
- * item and its owner.
- *
- * @param pxTCB pxTCB is set to the address of the owner of the next list item.
- * @param pxList The list from which the next item owner is to be returned.
- *
- * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
- * \ingroup LinkedList
- */
-#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )                                           \
-    {                                                                                          \
-        List_t * const pxConstList = ( pxList );                                               \
-        /* Increment the index to the next item and return the item, ensuring */               \
-        /* we don't return the marker used at the end of the list.  */                         \
-        ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;                           \
-        if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \
-        {                                                                                      \
-            ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;                       \
-        }                                                                                      \
-        ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;                                         \
-    }
-
-
-/*
- * Access function to obtain the owner of the first entry in a list.  Lists
- * are normally sorted in ascending item value order.
- *
- * This function returns the pxOwner member of the first item in the list.
- * The pxOwner parameter of a list item is a pointer to the object that owns
- * the list item.  In the scheduler this is normally a task control block.
- * The pxOwner parameter effectively creates a two way link between the list
- * item and its owner.
- *
- * @param pxList The list from which the owner of the head item is to be
- * returned.
- *
- * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
- * \ingroup LinkedList
- */
-#define listGET_OWNER_OF_HEAD_ENTRY( pxList )            ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner )
-
-/*
- * Check to see if a list item is within a list.  The list item maintains a
- * "container" pointer that points to the list it is in.  All this macro does
- * is check to see if the container and the list match.
- *
- * @param pxList The list we want to know if the list item is within.
- * @param pxListItem The list item we want to know if is in the list.
- * @return pdTRUE if the list item is in the list, otherwise pdFALSE.
- */
-#define listIS_CONTAINED_WITHIN( pxList, pxListItem )    ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )
-
-/*
- * Return the list a list item is contained within (referenced from).
- *
- * @param pxListItem The list item being queried.
- * @return A pointer to the List_t object that references the pxListItem
- */
-#define listLIST_ITEM_CONTAINER( pxListItem )            ( ( pxListItem )->pxContainer )
-
-/*
- * This provides a crude means of knowing if a list has been initialised, as
- * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
- * function.
- */
-#define listLIST_IS_INITIALISED( pxList )                ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
-
-/*
- * Must be called before a list is used!  This initialises all the members
- * of the list structure and inserts the xListEnd item into the list as a
- * marker to the back of the list.
- *
- * @param pxList Pointer to the list being initialised.
- *
- * \page vListInitialise vListInitialise
- * \ingroup LinkedList
- */
-void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;
-
-/*
- * Must be called before a list item is used.  This sets the list container to
- * null so the item does not think that it is already contained in a list.
- *
- * @param pxItem Pointer to the list item being initialised.
- *
- * \page vListInitialiseItem vListInitialiseItem
- * \ingroup LinkedList
- */
-void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;
-
-/*
- * Insert a list item into a list.  The item will be inserted into the list in
- * a position determined by its item value (descending item value order).
- *
- * @param pxList The list into which the item is to be inserted.
- *
- * @param pxNewListItem The item that is to be placed in the list.
- *
- * \page vListInsert vListInsert
- * \ingroup LinkedList
- */
-void vListInsert( List_t * const pxList,
-                  ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
-
-/*
- * Insert a list item into a list.  The item will be inserted in a position
- * such that it will be the last item within the list returned by multiple
- * calls to listGET_OWNER_OF_NEXT_ENTRY.
- *
- * The list member pxIndex is used to walk through a list.  Calling
- * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
- * Placing an item in a list using vListInsertEnd effectively places the item
- * in the list position pointed to by pxIndex.  This means that every other
- * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
- * the pxIndex parameter again points to the item being inserted.
- *
- * @param pxList The list into which the item is to be inserted.
- *
- * @param pxNewListItem The list item to be inserted into the list.
- *
- * \page vListInsertEnd vListInsertEnd
- * \ingroup LinkedList
- */
-void vListInsertEnd( List_t * const pxList,
-                     ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
-
-/*
- * Remove an item from a list.  The list item has a pointer to the list that
- * it is in, so only the list item need be passed into the function.
- *
- * @param uxListRemove The item to be removed.  The item will remove itself from
- * the list pointed to by it's pxContainer parameter.
- *
- * @return The number of items that remain in the list after the list item has
- * been removed.
- *
- * \page uxListRemove uxListRemove
- * \ingroup LinkedList
- */
-UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    }
-#endif
-/* *INDENT-ON* */
-
-#endif /* ifndef LIST_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/message_buffer.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/message_buffer.h
deleted file mode 100644
index 10762e6..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/message_buffer.h
+++ /dev/null
@@ -1,821 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-/*
- * Message buffers build functionality on top of FreeRTOS stream buffers.
- * Whereas stream buffers are used to send a continuous stream of data from one
- * task or interrupt to another, message buffers are used to send variable
- * length discrete messages from one task or interrupt to another.  Their
- * implementation is light weight, making them particularly suited for interrupt
- * to task and core to core communication scenarios.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * timeout to 0.
- *
- * Message buffers hold variable length messages.  To enable that, when a
- * message is written to the message buffer an additional sizeof( size_t ) bytes
- * are also written to store the message's length (that happens internally, with
- * the API function).  sizeof( size_t ) is typically 4 bytes on a 32-bit
- * architecture, so writing a 10 byte message to a message buffer on a 32-bit
- * architecture will actually reduce the available space in the message buffer
- * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length
- * of the message).
- */
-
-#ifndef FREERTOS_MESSAGE_BUFFER_H
-#define FREERTOS_MESSAGE_BUFFER_H
-
-#ifndef INC_FREERTOS_H
-    #error "include FreeRTOS.h must appear in source files before include message_buffer.h"
-#endif
-
-/* Message buffers are built onto of stream buffers. */
-#include "stream_buffer.h"
-
-/* *INDENT-OFF* */
-#if defined( __cplusplus )
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/**
- * Type by which message buffers are referenced.  For example, a call to
- * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can
- * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),
- * etc.
- */
-typedef void * MessageBufferHandle_t;
-
-/*-----------------------------------------------------------*/
-
-/**
- * message_buffer.h
- *
- * 
- * MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
- * 

- *
- * Creates a new message buffer using dynamically allocated memory.  See
- * xMessageBufferCreateStatic() for a version that uses statically allocated
- * memory (memory that is allocated at compile time).
- *
- * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
- * FreeRTOSConfig.h for xMessageBufferCreate() to be available.
- *
- * @param xBufferSizeBytes The total number of bytes (not messages) the message
- * buffer will be able to hold at any one time.  When a message is written to
- * the message buffer an additional sizeof( size_t ) bytes are also written to
- * store the message's length.  sizeof( size_t ) is typically 4 bytes on a
- * 32-bit architecture, so on most 32-bit architectures a 10 byte message will
- * take up 14 bytes of message buffer space.
- *
- * @return If NULL is returned, then the message buffer cannot be created
- * because there is insufficient heap memory available for FreeRTOS to allocate
- * the message buffer data structures and storage area.  A non-NULL value being
- * returned indicates that the message buffer has been created successfully -
- * the returned value should be stored as the handle to the created message
- * buffer.
- *
- * Example use:
- * 
- *
- * void vAFunction( void )
- * {
- * MessageBufferHandle_t xMessageBuffer;
- * const size_t xMessageBufferSizeBytes = 100;
- *
- *  // Create a message buffer that can hold 100 bytes.  The memory used to hold
- *  // both the message buffer structure and the messages themselves is allocated
- *  // dynamically.  Each message added to the buffer consumes an additional 4
- *  // bytes which are used to hold the lengh of the message.
- *  xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
- *
- *  if( xMessageBuffer == NULL )
- *  {
- *      // There was not enough heap memory space available to create the
- *      // message buffer.
- *  }
- *  else
- *  {
- *      // The message buffer was created successfully and can now be used.
- *  }
- *
- * 

- * \defgroup xMessageBufferCreate xMessageBufferCreate
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferCreate( xBufferSizeBytes ) \
-    ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE )
-
-/**
- * message_buffer.h
- *
- * 
- * MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
- *                                                uint8_t *pucMessageBufferStorageArea,
- *                                                StaticMessageBuffer_t *pxStaticMessageBuffer );
- * 

- * Creates a new message buffer using statically allocated memory.  See
- * xMessageBufferCreate() for a version that uses dynamically allocated memory.
- *
- * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
- * pucMessageBufferStorageArea parameter.  When a message is written to the
- * message buffer an additional sizeof( size_t ) bytes are also written to store
- * the message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
- * architecture, so on most 32-bit architecture a 10 byte message will take up
- * 14 bytes of message buffer space.  The maximum number of bytes that can be
- * stored in the message buffer is actually (xBufferSizeBytes - 1).
- *
- * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at
- * least xBufferSizeBytes + 1 big.  This is the array to which messages are
- * copied when they are written to the message buffer.
- *
- * @param pxStaticMessageBuffer Must point to a variable of type
- * StaticMessageBuffer_t, which will be used to hold the message buffer's data
- * structure.
- *
- * @return If the message buffer is created successfully then a handle to the
- * created message buffer is returned. If either pucMessageBufferStorageArea or
- * pxStaticmessageBuffer are NULL then NULL is returned.
- *
- * Example use:
- * 
- *
- * // Used to dimension the array used to hold the messages.  The available space
- * // will actually be one less than this, so 999.
- #define STORAGE_SIZE_BYTES 1000
- *
- * // Defines the memory that will actually hold the messages within the message
- * // buffer.
- * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
- *
- * // The variable used to hold the message buffer structure.
- * StaticMessageBuffer_t xMessageBufferStruct;
- *
- * void MyFunction( void )
- * {
- * MessageBufferHandle_t xMessageBuffer;
- *
- *  xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
- *                                               ucBufferStorage,
- *                                               &xMessageBufferStruct );
- *
- *  // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
- *  // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
- *  // reference the created message buffer in other message buffer API calls.
- *
- *  // Other code that uses the message buffer can go here.
- * }
- *
- * 

- * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \
-    ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer )
-
-/**
- * message_buffer.h
- *
- * 
- * size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
- *                         const void *pvTxData,
- *                         size_t xDataLengthBytes,
- *                         TickType_t xTicksToWait );
- * 

- *
- * Sends a discrete message to the message buffer.  The message can be any
- * length that fits within the buffer's free space, and is copied into the
- * buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xMessageBufferSend() to write to a message buffer from a task.  Use
- * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
- * service routine (ISR).
- *
- * @param xMessageBuffer The handle of the message buffer to which a message is
- * being sent.
- *
- * @param pvTxData A pointer to the message that is to be copied into the
- * message buffer.
- *
- * @param xDataLengthBytes The length of the message.  That is, the number of
- * bytes to copy from pvTxData into the message buffer.  When a message is
- * written to the message buffer an additional sizeof( size_t ) bytes are also
- * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
- * on a 32-bit architecture, so on most 32-bit architecture setting
- * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
- * bytes (20 bytes of message data and 4 bytes to hold the message length).
- *
- * @param xTicksToWait The maximum amount of time the calling task should remain
- * in the Blocked state to wait for enough space to become available in the
- * message buffer, should the message buffer have insufficient space when
- * xMessageBufferSend() is called.  The calling task will never block if
- * xTicksToWait is zero.  The block time is specified in tick periods, so the
- * absolute time it represents is dependent on the tick frequency.  The macro
- * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
- * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
- * the task to wait indefinitely (without timing out), provided
- * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
- * CPU time when they are in the Blocked state.
- *
- * @return The number of bytes written to the message buffer.  If the call to
- * xMessageBufferSend() times out before there was enough space to write the
- * message into the message buffer then zero is returned.  If the call did not
- * time out then xDataLengthBytes is returned.
- *
- * Example use:
- * 
- * void vAFunction( MessageBufferHandle_t xMessageBuffer )
- * {
- * size_t xBytesSent;
- * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
- * char *pcStringToSend = "String to send";
- * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
- *
- *  // Send an array to the message buffer, blocking for a maximum of 100ms to
- *  // wait for enough space to be available in the message buffer.
- *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
- *
- *  if( xBytesSent != sizeof( ucArrayToSend ) )
- *  {
- *      // The call to xMessageBufferSend() times out before there was enough
- *      // space in the buffer for the data to be written.
- *  }
- *
- *  // Send the string to the message buffer.  Return immediately if there is
- *  // not enough space in the buffer.
- *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
- *
- *  if( xBytesSent != strlen( pcStringToSend ) )
- *  {
- *      // The string could not be added to the message buffer because there was
- *      // not enough free space in the buffer.
- *  }
- * }
- * 

- * \defgroup xMessageBufferSend xMessageBufferSend
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) \
-    xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
-
-/**
- * message_buffer.h
- *
- * 
- * size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
- *                                const void *pvTxData,
- *                                size_t xDataLengthBytes,
- *                                BaseType_t *pxHigherPriorityTaskWoken );
- * 

- *
- * Interrupt safe version of the API function that sends a discrete message to
- * the message buffer.  The message can be any length that fits within the
- * buffer's free space, and is copied into the buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xMessageBufferSend() to write to a message buffer from a task.  Use
- * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
- * service routine (ISR).
- *
- * @param xMessageBuffer The handle of the message buffer to which a message is
- * being sent.
- *
- * @param pvTxData A pointer to the message that is to be copied into the
- * message buffer.
- *
- * @param xDataLengthBytes The length of the message.  That is, the number of
- * bytes to copy from pvTxData into the message buffer.  When a message is
- * written to the message buffer an additional sizeof( size_t ) bytes are also
- * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
- * on a 32-bit architecture, so on most 32-bit architecture setting
- * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
- * bytes (20 bytes of message data and 4 bytes to hold the message length).
- *
- * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
- * have a task blocked on it waiting for data.  Calling
- * xMessageBufferSendFromISR() can make data available, and so cause a task that
- * was waiting for data to leave the Blocked state.  If calling
- * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently executing task (the
- * task that was interrupted), then, internally, xMessageBufferSendFromISR()
- * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
- * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
- * context switch should be performed before the interrupt is exited.  This will
- * ensure that the interrupt returns directly to the highest priority Ready
- * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
- * is passed into the function.  See the code example below for an example.
- *
- * @return The number of bytes actually written to the message buffer.  If the
- * message buffer didn't have enough free space for the message to be stored
- * then 0 is returned, otherwise xDataLengthBytes is returned.
- *
- * Example use:
- * 
- * // A message buffer that has already been created.
- * MessageBufferHandle_t xMessageBuffer;
- *
- * void vAnInterruptServiceRoutine( void )
- * {
- * size_t xBytesSent;
- * char *pcStringToSend = "String to send";
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
- *
- *  // Attempt to send the string to the message buffer.
- *  xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
- *                                          ( void * ) pcStringToSend,
- *                                          strlen( pcStringToSend ),
- *                                          &xHigherPriorityTaskWoken );
- *
- *  if( xBytesSent != strlen( pcStringToSend ) )
- *  {
- *      // The string could not be added to the message buffer because there was
- *      // not enough free space in the buffer.
- *  }
- *
- *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
- *  // xMessageBufferSendFromISR() then a task that has a priority above the
- *  // priority of the currently executing task was unblocked and a context
- *  // switch should be performed to ensure the ISR returns to the unblocked
- *  // task.  In most FreeRTOS ports this is done by simply passing
- *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
- *  // variables value, and perform the context switch if necessary.  Check the
- *  // documentation for the port in use for port specific instructions.
- *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
- * }
- * 

- * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) \
-    xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
-
-/**
- * message_buffer.h
- *
- * 
- * size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
- *                            void *pvRxData,
- *                            size_t xBufferLengthBytes,
- *                            TickType_t xTicksToWait );
- * 

- *
- * Receives a discrete message from a message buffer.  Messages can be of
- * variable length and are copied out of the buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
- * xMessageBufferReceiveFromISR() to read from a message buffer from an
- * interrupt service routine (ISR).
- *
- * @param xMessageBuffer The handle of the message buffer from which a message
- * is being received.
- *
- * @param pvRxData A pointer to the buffer into which the received message is
- * to be copied.
- *
- * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
- * parameter.  This sets the maximum length of the message that can be received.
- * If xBufferLengthBytes is too small to hold the next message then the message
- * will be left in the message buffer and 0 will be returned.
- *
- * @param xTicksToWait The maximum amount of time the task should remain in the
- * Blocked state to wait for a message, should the message buffer be empty.
- * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
- * the message buffer is empty.  The block time is specified in tick periods, so
- * the absolute time it represents is dependent on the tick frequency.  The
- * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
- * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
- * cause the task to wait indefinitely (without timing out), provided
- * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
- * CPU time when they are in the Blocked state.
- *
- * @return The length, in bytes, of the message read from the message buffer, if
- * any.  If xMessageBufferReceive() times out before a message became available
- * then zero is returned.  If the length of the message is greater than
- * xBufferLengthBytes then the message will be left in the message buffer and
- * zero is returned.
- *
- * Example use:
- * 
- * void vAFunction( MessageBuffer_t xMessageBuffer )
- * {
- * uint8_t ucRxData[ 20 ];
- * size_t xReceivedBytes;
- * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
- *
- *  // Receive the next message from the message buffer.  Wait in the Blocked
- *  // state (so not using any CPU processing time) for a maximum of 100ms for
- *  // a message to become available.
- *  xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
- *                                          ( void * ) ucRxData,
- *                                          sizeof( ucRxData ),
- *                                          xBlockTime );
- *
- *  if( xReceivedBytes > 0 )
- *  {
- *      // A ucRxData contains a message that is xReceivedBytes long.  Process
- *      // the message here....
- *  }
- * }
- * 

- * \defgroup xMessageBufferReceive xMessageBufferReceive
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) \
-    xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
-
-
-/**
- * message_buffer.h
- *
- * 
- * size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
- *                                   void *pvRxData,
- *                                   size_t xBufferLengthBytes,
- *                                   BaseType_t *pxHigherPriorityTaskWoken );
- * 

- *
- * An interrupt safe version of the API function that receives a discrete
- * message from a message buffer.  Messages can be of variable length and are
- * copied out of the buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
- * xMessageBufferReceiveFromISR() to read from a message buffer from an
- * interrupt service routine (ISR).
- *
- * @param xMessageBuffer The handle of the message buffer from which a message
- * is being received.
- *
- * @param pvRxData A pointer to the buffer into which the received message is
- * to be copied.
- *
- * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
- * parameter.  This sets the maximum length of the message that can be received.
- * If xBufferLengthBytes is too small to hold the next message then the message
- * will be left in the message buffer and 0 will be returned.
- *
- * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
- * have a task blocked on it waiting for space to become available.  Calling
- * xMessageBufferReceiveFromISR() can make space available, and so cause a task
- * that is waiting for space to leave the Blocked state.  If calling
- * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
- * the unblocked task has a priority higher than the currently executing task
- * (the task that was interrupted), then, internally,
- * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
- * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
- * context switch should be performed before the interrupt is exited.  That will
- * ensure the interrupt returns directly to the highest priority Ready state
- * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
- * passed into the function.  See the code example below for an example.
- *
- * @return The length, in bytes, of the message read from the message buffer, if
- * any.
- *
- * Example use:
- * 
- * // A message buffer that has already been created.
- * MessageBuffer_t xMessageBuffer;
- *
- * void vAnInterruptServiceRoutine( void )
- * {
- * uint8_t ucRxData[ 20 ];
- * size_t xReceivedBytes;
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
- *
- *  // Receive the next message from the message buffer.
- *  xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
- *                                                ( void * ) ucRxData,
- *                                                sizeof( ucRxData ),
- *                                                &xHigherPriorityTaskWoken );
- *
- *  if( xReceivedBytes > 0 )
- *  {
- *      // A ucRxData contains a message that is xReceivedBytes long.  Process
- *      // the message here....
- *  }
- *
- *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
- *  // xMessageBufferReceiveFromISR() then a task that has a priority above the
- *  // priority of the currently executing task was unblocked and a context
- *  // switch should be performed to ensure the ISR returns to the unblocked
- *  // task.  In most FreeRTOS ports this is done by simply passing
- *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
- *  // variables value, and perform the context switch if necessary.  Check the
- *  // documentation for the port in use for port specific instructions.
- *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
- * }
- * 

- * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) \
-    xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
-
-/**
- * message_buffer.h
- *
- * 
- * void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
- * 

- *
- * Deletes a message buffer that was previously created using a call to
- * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
- * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
- * then the allocated memory is freed.
- *
- * A message buffer handle must not be used after the message buffer has been
- * deleted.
- *
- * @param xMessageBuffer The handle of the message buffer to be deleted.
- *
- */
-#define vMessageBufferDelete( xMessageBuffer ) \
-    vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
-
-/**
- * message_buffer.h
- * 
- * BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
- * 

- *
- * Tests to see if a message buffer is full.  A message buffer is full if it
- * cannot accept any more messages, of any size, until space is made available
- * by a message being removed from the message buffer.
- *
- * @param xMessageBuffer The handle of the message buffer being queried.
- *
- * @return If the message buffer referenced by xMessageBuffer is full then
- * pdTRUE is returned.  Otherwise pdFALSE is returned.
- */
-#define xMessageBufferIsFull( xMessageBuffer ) \
-    xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
-
-/**
- * message_buffer.h
- * 
- * BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
- * 

- *
- * Tests to see if a message buffer is empty (does not contain any messages).
- *
- * @param xMessageBuffer The handle of the message buffer being queried.
- *
- * @return If the message buffer referenced by xMessageBuffer is empty then
- * pdTRUE is returned.  Otherwise pdFALSE is returned.
- *
- */
-#define xMessageBufferIsEmpty( xMessageBuffer ) \
-    xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
-
-/**
- * message_buffer.h
- * 
- * BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
- * 

- *
- * Resets a message buffer to its initial empty state, discarding any message it
- * contained.
- *
- * A message buffer can only be reset if there are no tasks blocked on it.
- *
- * @param xMessageBuffer The handle of the message buffer being reset.
- *
- * @return If the message buffer was reset then pdPASS is returned.  If the
- * message buffer could not be reset because either there was a task blocked on
- * the message queue to wait for space to become available, or to wait for a
- * a message to be available, then pdFAIL is returned.
- *
- * \defgroup xMessageBufferReset xMessageBufferReset
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferReset( xMessageBuffer ) \
-    xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
-
-
-/**
- * message_buffer.h
- * 
- * size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
- * 

- * Returns the number of bytes of free space in the message buffer.
- *
- * @param xMessageBuffer The handle of the message buffer being queried.
- *
- * @return The number of bytes that can be written to the message buffer before
- * the message buffer would be full.  When a message is written to the message
- * buffer an additional sizeof( size_t ) bytes are also written to store the
- * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
- * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
- * of the largest message that can be written to the message buffer is 6 bytes.
- *
- * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferSpaceAvailable( xMessageBuffer ) \
-    xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
-#define xMessageBufferSpacesAvailable( xMessageBuffer ) \
-    xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
-
-/**
- * message_buffer.h
- * 
- * size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
- * 

- * Returns the length (in bytes) of the next message in a message buffer.
- * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
- * passed into xMessageBufferReceive() was too small to hold the next message.
- *
- * @param xMessageBuffer The handle of the message buffer being queried.
- *
- * @return The length (in bytes) of the next message in the message buffer, or 0
- * if the message buffer is empty.
- *
- * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferNextLengthBytes( xMessageBuffer ) \
-    xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * message_buffer.h
- *
- * 
- * BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
- * 

- *
- * For advanced users only.
- *
- * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
- * data is sent to a message buffer or stream buffer.  If there was a task that
- * was blocked on the message or stream buffer waiting for data to arrive then
- * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
- * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
- * thing.  It is provided to enable application writers to implement their own
- * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
- *
- * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
- * additional information.
- *
- * @param xStreamBuffer The handle of the stream buffer to which data was
- * written.
- *
- * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
- * initialised to pdFALSE before it is passed into
- * xMessageBufferSendCompletedFromISR().  If calling
- * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
- * and the task has a priority above the priority of the currently running task,
- * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
- * context switch should be performed before exiting the ISR.
- *
- * @return If a task was removed from the Blocked state then pdTRUE is returned.
- * Otherwise pdFALSE is returned.
- *
- * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
- * \ingroup StreamBufferManagement
- */
-#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
-    xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
-
-/**
- * message_buffer.h
- *
- * 
- * BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
- * 

- *
- * For advanced users only.
- *
- * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
- * data is read out of a message buffer or stream buffer.  If there was a task
- * that was blocked on the message or stream buffer waiting for data to arrive
- * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
- * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
- * does the same thing.  It is provided to enable application writers to
- * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
- * ANY OTHER TIME.
- *
- * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
- * additional information.
- *
- * @param xStreamBuffer The handle of the stream buffer from which data was
- * read.
- *
- * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
- * initialised to pdFALSE before it is passed into
- * xMessageBufferReceiveCompletedFromISR().  If calling
- * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
- * and the task has a priority above the priority of the currently running task,
- * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
- * context switch should be performed before exiting the ISR.
- *
- * @return If a task was removed from the Blocked state then pdTRUE is returned.
- * Otherwise pdFALSE is returned.
- *
- * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
- * \ingroup StreamBufferManagement
- */
-#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
-    xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
-
-/* *INDENT-OFF* */
-#if defined( __cplusplus )
-    } /* extern "C" */
-#endif
-/* *INDENT-ON* */
-
-#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/mpu_prototypes.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/mpu_prototypes.h
deleted file mode 100644
index 7667953..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/mpu_prototypes.h
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * When the MPU is used the standard (non MPU) API functions are mapped to
- * equivalents that start "MPU_", the prototypes for which are defined in this
- * header files.  This will cause the application code to call the MPU_ version
- * which wraps the non-MPU version with privilege promoting then demoting code,
- * so the kernel code always runs will full privileges.
- */
-
-
-#ifndef MPU_PROTOTYPES_H
-#define MPU_PROTOTYPES_H
-
-/* MPU versions of tasks.h API functions. */
-BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
-                            const char * const pcName,
-                            const uint16_t usStackDepth,
-                            void * const pvParameters,
-                            UBaseType_t uxPriority,
-                            TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
-                                    const char * const pcName,
-                                    const uint32_t ulStackDepth,
-                                    void * const pvParameters,
-                                    UBaseType_t uxPriority,
-                                    StackType_t * const puxStackBuffer,
-                                    StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                          const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskPrioritySet( TaskHandle_t xTask,
-                           UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) FREERTOS_SYSTEM_CALL;
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
-                                             void * pvParameter ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
-uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL;
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of queue.h API functions. */
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
-                                           StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
-                                                 const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
-                                                       const UBaseType_t uxInitialCount,
-                                                       StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength,
-                                       const UBaseType_t uxItemSize,
-                                       const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
-                                             const UBaseType_t uxItemSize,
-                                             uint8_t * pucQueueStorage,
-                                             StaticQueue_t * pxStaticQueue,
-                                             const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                                    QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
-                                   BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue,
-                               UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of timers.h API functions. */
-TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
-                                const TickType_t xTimerPeriodInTicks,
-                                const UBaseType_t uxAutoReload,
-                                void * const pvTimerID,
-                                TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
-TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
-                                      const TickType_t xTimerPeriodInTicks,
-                                      const UBaseType_t uxAutoReload,
-                                      void * const pvTimerID,
-                                      TimerCallbackFunction_t pxCallbackFunction,
-                                      StaticTimer_t * pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
-                                       void * pvParameter1,
-                                       uint32_t ulParameter2,
-                                       TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of event_group.h API functions. */
-EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
-EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of message/stream_buffer.h API functions. */
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
-StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
-                                                     size_t xTriggerLevelBytes,
-                                                     BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
-StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
-                                                           size_t xTriggerLevelBytes,
-                                                           BaseType_t xIsMessageBuffer,
-                                                           uint8_t * const pucStreamBufferStorageArea,
-                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
-
-
-
-#endif /* MPU_PROTOTYPES_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/mpu_wrappers.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/mpu_wrappers.h
deleted file mode 100644
index ba63846..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/mpu_wrappers.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef MPU_WRAPPERS_H
-#define MPU_WRAPPERS_H
-
-/* This file redefines API functions to be called through a wrapper macro, but
- * only for ports that are using the MPU. */
-#ifdef portUSING_MPU_WRAPPERS
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
- * included from queue.c or task.c to prevent it from having an effect within
- * those files. */
-    #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/*
- * Map standard (non MPU) API functions to equivalents that start
- * "MPU_".  This will cause the application code to call the MPU_
- * version, which wraps the non-MPU version with privilege promoting
- * then demoting code, so the kernel code always runs will full
- * privileges.
- */
-
-/* Map standard tasks.h API functions to the MPU equivalents. */
-        #define xTaskCreate                            MPU_xTaskCreate
-        #define xTaskCreateStatic                      MPU_xTaskCreateStatic
-        #define vTaskDelete                            MPU_vTaskDelete
-        #define vTaskDelay                             MPU_vTaskDelay
-        #define xTaskDelayUntil                        MPU_xTaskDelayUntil
-        #define xTaskAbortDelay                        MPU_xTaskAbortDelay
-        #define uxTaskPriorityGet                      MPU_uxTaskPriorityGet
-        #define eTaskGetState                          MPU_eTaskGetState
-        #define vTaskGetInfo                           MPU_vTaskGetInfo
-        #define vTaskPrioritySet                       MPU_vTaskPrioritySet
-        #define vTaskSuspend                           MPU_vTaskSuspend
-        #define vTaskResume                            MPU_vTaskResume
-        #define vTaskSuspendAll                        MPU_vTaskSuspendAll
-        #define xTaskResumeAll                         MPU_xTaskResumeAll
-        #define xTaskGetTickCount                      MPU_xTaskGetTickCount
-        #define uxTaskGetNumberOfTasks                 MPU_uxTaskGetNumberOfTasks
-        #define pcTaskGetName                          MPU_pcTaskGetName
-        #define xTaskGetHandle                         MPU_xTaskGetHandle
-        #define uxTaskGetStackHighWaterMark            MPU_uxTaskGetStackHighWaterMark
-        #define uxTaskGetStackHighWaterMark2           MPU_uxTaskGetStackHighWaterMark2
-        #define vTaskSetApplicationTaskTag             MPU_vTaskSetApplicationTaskTag
-        #define xTaskGetApplicationTaskTag             MPU_xTaskGetApplicationTaskTag
-        #define vTaskSetThreadLocalStoragePointer      MPU_vTaskSetThreadLocalStoragePointer
-        #define pvTaskGetThreadLocalStoragePointer     MPU_pvTaskGetThreadLocalStoragePointer
-        #define xTaskCallApplicationTaskHook           MPU_xTaskCallApplicationTaskHook
-        #define xTaskGetIdleTaskHandle                 MPU_xTaskGetIdleTaskHandle
-        #define uxTaskGetSystemState                   MPU_uxTaskGetSystemState
-        #define vTaskList                              MPU_vTaskList
-        #define vTaskGetRunTimeStats                   MPU_vTaskGetRunTimeStats
-        #define ulTaskGetIdleRunTimeCounter            MPU_ulTaskGetIdleRunTimeCounter
-        #define xTaskGenericNotify                     MPU_xTaskGenericNotify
-        #define xTaskGenericNotifyWait                 MPU_xTaskGenericNotifyWait
-        #define ulTaskGenericNotifyTake                MPU_ulTaskGenericNotifyTake
-        #define xTaskGenericNotifyStateClear           MPU_xTaskGenericNotifyStateClear
-        #define ulTaskGenericNotifyValueClear          MPU_ulTaskGenericNotifyValueClear
-        #define xTaskCatchUpTicks                      MPU_xTaskCatchUpTicks
-
-        #define xTaskGetCurrentTaskHandle              MPU_xTaskGetCurrentTaskHandle
-        #define vTaskSetTimeOutState                   MPU_vTaskSetTimeOutState
-        #define xTaskCheckForTimeOut                   MPU_xTaskCheckForTimeOut
-        #define xTaskGetSchedulerState                 MPU_xTaskGetSchedulerState
-
-/* Map standard queue.h API functions to the MPU equivalents. */
-        #define xQueueGenericSend                      MPU_xQueueGenericSend
-        #define xQueueReceive                          MPU_xQueueReceive
-        #define xQueuePeek                             MPU_xQueuePeek
-        #define xQueueSemaphoreTake                    MPU_xQueueSemaphoreTake
-        #define uxQueueMessagesWaiting                 MPU_uxQueueMessagesWaiting
-        #define uxQueueSpacesAvailable                 MPU_uxQueueSpacesAvailable
-        #define vQueueDelete                           MPU_vQueueDelete
-        #define xQueueCreateMutex                      MPU_xQueueCreateMutex
-        #define xQueueCreateMutexStatic                MPU_xQueueCreateMutexStatic
-        #define xQueueCreateCountingSemaphore          MPU_xQueueCreateCountingSemaphore
-        #define xQueueCreateCountingSemaphoreStatic    MPU_xQueueCreateCountingSemaphoreStatic
-        #define xQueueGetMutexHolder                   MPU_xQueueGetMutexHolder
-        #define xQueueTakeMutexRecursive               MPU_xQueueTakeMutexRecursive
-        #define xQueueGiveMutexRecursive               MPU_xQueueGiveMutexRecursive
-        #define xQueueGenericCreate                    MPU_xQueueGenericCreate
-        #define xQueueGenericCreateStatic              MPU_xQueueGenericCreateStatic
-        #define xQueueCreateSet                        MPU_xQueueCreateSet
-        #define xQueueAddToSet                         MPU_xQueueAddToSet
-        #define xQueueRemoveFromSet                    MPU_xQueueRemoveFromSet
-        #define xQueueSelectFromSet                    MPU_xQueueSelectFromSet
-        #define xQueueGenericReset                     MPU_xQueueGenericReset
-
-        #if ( configQUEUE_REGISTRY_SIZE > 0 )
-            #define vQueueAddToRegistry                MPU_vQueueAddToRegistry
-            #define vQueueUnregisterQueue              MPU_vQueueUnregisterQueue
-            #define pcQueueGetName                     MPU_pcQueueGetName
-        #endif
-
-/* Map standard timer.h API functions to the MPU equivalents. */
-        #define xTimerCreate                           MPU_xTimerCreate
-        #define xTimerCreateStatic                     MPU_xTimerCreateStatic
-        #define pvTimerGetTimerID                      MPU_pvTimerGetTimerID
-        #define vTimerSetTimerID                       MPU_vTimerSetTimerID
-        #define xTimerIsTimerActive                    MPU_xTimerIsTimerActive
-        #define xTimerGetTimerDaemonTaskHandle         MPU_xTimerGetTimerDaemonTaskHandle
-        #define xTimerPendFunctionCall                 MPU_xTimerPendFunctionCall
-        #define pcTimerGetName                         MPU_pcTimerGetName
-        #define vTimerSetReloadMode                    MPU_vTimerSetReloadMode
-        #define uxTimerGetReloadMode                   MPU_uxTimerGetReloadMode
-        #define xTimerGetPeriod                        MPU_xTimerGetPeriod
-        #define xTimerGetExpiryTime                    MPU_xTimerGetExpiryTime
-        #define xTimerGenericCommand                   MPU_xTimerGenericCommand
-
-/* Map standard event_group.h API functions to the MPU equivalents. */
-        #define xEventGroupCreate                      MPU_xEventGroupCreate
-        #define xEventGroupCreateStatic                MPU_xEventGroupCreateStatic
-        #define xEventGroupWaitBits                    MPU_xEventGroupWaitBits
-        #define xEventGroupClearBits                   MPU_xEventGroupClearBits
-        #define xEventGroupSetBits                     MPU_xEventGroupSetBits
-        #define xEventGroupSync                        MPU_xEventGroupSync
-        #define vEventGroupDelete                      MPU_vEventGroupDelete
-
-/* Map standard message/stream_buffer.h API functions to the MPU
- * equivalents. */
-        #define xStreamBufferSend                      MPU_xStreamBufferSend
-        #define xStreamBufferReceive                   MPU_xStreamBufferReceive
-        #define xStreamBufferNextMessageLengthBytes    MPU_xStreamBufferNextMessageLengthBytes
-        #define vStreamBufferDelete                    MPU_vStreamBufferDelete
-        #define xStreamBufferIsFull                    MPU_xStreamBufferIsFull
-        #define xStreamBufferIsEmpty                   MPU_xStreamBufferIsEmpty
-        #define xStreamBufferReset                     MPU_xStreamBufferReset
-        #define xStreamBufferSpacesAvailable           MPU_xStreamBufferSpacesAvailable
-        #define xStreamBufferBytesAvailable            MPU_xStreamBufferBytesAvailable
-        #define xStreamBufferSetTriggerLevel           MPU_xStreamBufferSetTriggerLevel
-        #define xStreamBufferGenericCreate             MPU_xStreamBufferGenericCreate
-        #define xStreamBufferGenericCreateStatic       MPU_xStreamBufferGenericCreateStatic
-
-
-/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
- * macro so applications can place data in privileged access sections
- * (useful when using statically allocated objects). */
-        #define PRIVILEGED_FUNCTION
-        #define PRIVILEGED_DATA    __attribute__( ( section( "privileged_data" ) ) )
-        #define FREERTOS_SYSTEM_CALL
-
-    #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
-
-        /* Ensure API functions go in the privileged execution section. */
-        #define PRIVILEGED_FUNCTION     __attribute__( ( section( "privileged_functions" ) ) )
-        #define PRIVILEGED_DATA         __attribute__( ( section( "privileged_data" ) ) )
-        #define FREERTOS_SYSTEM_CALL    __attribute__( ( section( "freertos_system_calls" ) ) )
-
-        /**
-         * @brief Calls the port specific code to raise the privilege.
-         *
-         * Sets xRunningPrivileged to pdFALSE if privilege was raised, else sets
-         * it to pdTRUE.
-         */
-        #define xPortRaisePrivilege( xRunningPrivileged )                      \
-        {                                                                      \
-            /* Check whether the processor is already privileged. */           \
-            xRunningPrivileged = portIS_PRIVILEGED();                          \
-                                                                               \
-            /* If the processor is not already privileged, raise privilege. */ \
-            if( xRunningPrivileged == pdFALSE )                                \
-            {                                                                  \
-                portRAISE_PRIVILEGE();                                         \
-            }                                                                  \
-        }
-
-        /**
-         * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
-         * code to reset the privilege, otherwise does nothing.
-         */
-        #define vPortResetPrivilege( xRunningPrivileged )   \
-        {                                                   \
-            if( xRunningPrivileged == pdFALSE )             \
-            {                                               \
-                portRESET_PRIVILEGE();                      \
-            }                                               \
-        }
-
-    #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
-
-#else /* portUSING_MPU_WRAPPERS */
-
-    #define PRIVILEGED_FUNCTION
-    #define PRIVILEGED_DATA
-    #define FREERTOS_SYSTEM_CALL
-    #define portUSING_MPU_WRAPPERS    0
-
-#endif /* portUSING_MPU_WRAPPERS */
-
-
-#endif /* MPU_WRAPPERS_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/portable.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/portable.h
deleted file mode 100644
index 2d52cf2..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/portable.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
-* Portable layer API.  Each function must be defined for each port.
-*----------------------------------------------------------*/
-
-#ifndef PORTABLE_H
-#define PORTABLE_H
-
-/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
- * pre-processor definition was used to ensure the pre-processor found the correct
- * portmacro.h file for the port being used.  That scheme was deprecated in favour
- * of setting the compiler's include path such that it found the correct
- * portmacro.h file - removing the need for the constant and allowing the
- * portmacro.h file to be located anywhere in relation to the port being used.
- * Purely for reasons of backward compatibility the old method is still valid, but
- * to make it clear that new projects should not use it, support for the port
- * specific constants has been moved into the deprecated_definitions.h header
- * file. */
-#include "deprecated_definitions.h"
-
-/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
- * did not result in a portmacro.h header file being included - and it should be
- * included here.  In this case the path to the correct portmacro.h header file
- * must be set in the compiler's include path. */
-#ifndef portENTER_CRITICAL
-    #include "portmacro.h"
-#endif
-
-#if portBYTE_ALIGNMENT == 32
-    #define portBYTE_ALIGNMENT_MASK    ( 0x001f )
-#endif
-
-#if portBYTE_ALIGNMENT == 16
-    #define portBYTE_ALIGNMENT_MASK    ( 0x000f )
-#endif
-
-#if portBYTE_ALIGNMENT == 8
-    #define portBYTE_ALIGNMENT_MASK    ( 0x0007 )
-#endif
-
-#if portBYTE_ALIGNMENT == 4
-    #define portBYTE_ALIGNMENT_MASK    ( 0x0003 )
-#endif
-
-#if portBYTE_ALIGNMENT == 2
-    #define portBYTE_ALIGNMENT_MASK    ( 0x0001 )
-#endif
-
-#if portBYTE_ALIGNMENT == 1
-    #define portBYTE_ALIGNMENT_MASK    ( 0x0000 )
-#endif
-
-#ifndef portBYTE_ALIGNMENT_MASK
-    #error "Invalid portBYTE_ALIGNMENT definition"
-#endif
-
-#ifndef portNUM_CONFIGURABLE_REGIONS
-    #define portNUM_CONFIGURABLE_REGIONS    1
-#endif
-
-#ifndef portHAS_STACK_OVERFLOW_CHECKING
-    #define portHAS_STACK_OVERFLOW_CHECKING    0
-#endif
-
-#ifndef portARCH_NAME
-    #define portARCH_NAME    NULL
-#endif
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
-#include "mpu_wrappers.h"
-
-/*
- * Setup the stack of a new task so it is ready to be placed under the
- * scheduler control.  The registers have to be placed on the stack in
- * the order that the port expects to find them.
- *
- */
-#if ( portUSING_MPU_WRAPPERS == 1 )
-    #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                             StackType_t * pxEndOfStack,
-                                             TaskFunction_t pxCode,
-                                             void * pvParameters,
-                                             BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
-    #else
-        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                             TaskFunction_t pxCode,
-                                             void * pvParameters,
-                                             BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
-    #endif
-#else /* if ( portUSING_MPU_WRAPPERS == 1 ) */
-    #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                             StackType_t * pxEndOfStack,
-                                             TaskFunction_t pxCode,
-                                             void * pvParameters ) PRIVILEGED_FUNCTION;
-    #else
-        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                             TaskFunction_t pxCode,
-                                             void * pvParameters ) PRIVILEGED_FUNCTION;
-    #endif
-#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */
-
-/* Used by heap_5.c to define the start address and size of each memory region
- * that together comprise the total FreeRTOS heap space. */
-typedef struct HeapRegion
-{
-    uint8_t * pucStartAddress;
-    size_t xSizeInBytes;
-} HeapRegion_t;
-
-/* Used to pass information about the heap out of vPortGetHeapStats(). */
-typedef struct xHeapStats
-{
-    size_t xAvailableHeapSpaceInBytes;          /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
-    size_t xSizeOfLargestFreeBlockInBytes;      /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
-    size_t xSizeOfSmallestFreeBlockInBytes;     /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
-    size_t xNumberOfFreeBlocks;                 /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
-    size_t xMinimumEverFreeBytesRemaining;      /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
-    size_t xNumberOfSuccessfulAllocations;      /* The number of calls to pvPortMalloc() that have returned a valid memory block. */
-    size_t xNumberOfSuccessfulFrees;            /* The number of calls to vPortFree() that has successfully freed a block of memory. */
-} HeapStats_t;
-
-/*
- * Used to define multiple heap regions for use by heap_5.c.  This function
- * must be called before any calls to pvPortMalloc() - not creating a task,
- * queue, semaphore, mutex, software timer, event group, etc. will result in
- * pvPortMalloc being called.
- *
- * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
- * defines a region of memory that can be used as the heap.  The array is
- * terminated by a HeapRegions_t structure that has a size of 0.  The region
- * with the lowest start address must appear first in the array.
- */
-void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
-
-/*
- * Returns a HeapStats_t structure filled with information about the current
- * heap state.
- */
-void vPortGetHeapStats( HeapStats_t * pxHeapStats );
-
-/*
- * Map to the memory management routines required for the port.
- */
-void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
-void vPortFree( void * pv ) PRIVILEGED_FUNCTION;
-void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
-size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
-size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Setup the hardware ready for the scheduler to take control.  This generally
- * sets up a tick interrupt and sets timers for the correct tick frequency.
- */
-BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
- * the hardware is left in its original condition after the scheduler stops
- * executing.
- */
-void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
-
-/*
- * The structures and methods of manipulating the MPU are contained within the
- * port layer.
- *
- * Fills the xMPUSettings structure with the memory region information
- * contained in xRegions.
- */
-#if ( portUSING_MPU_WRAPPERS == 1 )
-    struct xMEMORY_REGION;
-    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
-                                    const struct xMEMORY_REGION * const xRegions,
-                                    StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
-#endif
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    }
-#endif
-/* *INDENT-ON* */
-
-#endif /* PORTABLE_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/projdefs.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/projdefs.h
deleted file mode 100644
index 878d5e2..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/projdefs.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PROJDEFS_H
-#define PROJDEFS_H
-
-/*
- * Defines the prototype to which task functions must conform.  Defined in this
- * file to ensure the type is known before portable.h is included.
- */
-typedef void (* TaskFunction_t)( void * );
-
-/* Converts a time in milliseconds to a time in ticks.  This macro can be
- * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
- * definition here is not suitable for your application. */
-#ifndef pdMS_TO_TICKS
-    #define pdMS_TO_TICKS( xTimeInMs )    ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) )
-#endif
-
-#define pdFALSE                                  ( ( BaseType_t ) 0 )
-#define pdTRUE                                   ( ( BaseType_t ) 1 )
-
-#define pdPASS                                   ( pdTRUE )
-#define pdFAIL                                   ( pdFALSE )
-#define errQUEUE_EMPTY                           ( ( BaseType_t ) 0 )
-#define errQUEUE_FULL                            ( ( BaseType_t ) 0 )
-
-/* FreeRTOS error definitions. */
-#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY    ( -1 )
-#define errQUEUE_BLOCKED                         ( -4 )
-#define errQUEUE_YIELD                           ( -5 )
-
-/* Macros used for basic data corruption checks. */
-#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
-    #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES    0
-#endif
-
-#if ( configUSE_16_BIT_TICKS == 1 )
-    #define pdINTEGRITY_CHECK_VALUE    0x5a5a
-#else
-    #define pdINTEGRITY_CHECK_VALUE    0x5a5a5a5aUL
-#endif
-
-/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
- * itself. */
-#define pdFREERTOS_ERRNO_NONE             0   /* No errors */
-#define pdFREERTOS_ERRNO_ENOENT           2   /* No such file or directory */
-#define pdFREERTOS_ERRNO_EINTR            4   /* Interrupted system call */
-#define pdFREERTOS_ERRNO_EIO              5   /* I/O error */
-#define pdFREERTOS_ERRNO_ENXIO            6   /* No such device or address */
-#define pdFREERTOS_ERRNO_EBADF            9   /* Bad file number */
-#define pdFREERTOS_ERRNO_EAGAIN           11  /* No more processes */
-#define pdFREERTOS_ERRNO_EWOULDBLOCK      11  /* Operation would block */
-#define pdFREERTOS_ERRNO_ENOMEM           12  /* Not enough memory */
-#define pdFREERTOS_ERRNO_EACCES           13  /* Permission denied */
-#define pdFREERTOS_ERRNO_EFAULT           14  /* Bad address */
-#define pdFREERTOS_ERRNO_EBUSY            16  /* Mount device busy */
-#define pdFREERTOS_ERRNO_EEXIST           17  /* File exists */
-#define pdFREERTOS_ERRNO_EXDEV            18  /* Cross-device link */
-#define pdFREERTOS_ERRNO_ENODEV           19  /* No such device */
-#define pdFREERTOS_ERRNO_ENOTDIR          20  /* Not a directory */
-#define pdFREERTOS_ERRNO_EISDIR           21  /* Is a directory */
-#define pdFREERTOS_ERRNO_EINVAL           22  /* Invalid argument */
-#define pdFREERTOS_ERRNO_ENOSPC           28  /* No space left on device */
-#define pdFREERTOS_ERRNO_ESPIPE           29  /* Illegal seek */
-#define pdFREERTOS_ERRNO_EROFS            30  /* Read only file system */
-#define pdFREERTOS_ERRNO_EUNATCH          42  /* Protocol driver not attached */
-#define pdFREERTOS_ERRNO_EBADE            50  /* Invalid exchange */
-#define pdFREERTOS_ERRNO_EFTYPE           79  /* Inappropriate file type or format */
-#define pdFREERTOS_ERRNO_ENMFILE          89  /* No more files */
-#define pdFREERTOS_ERRNO_ENOTEMPTY        90  /* Directory not empty */
-#define pdFREERTOS_ERRNO_ENAMETOOLONG     91  /* File or path name too long */
-#define pdFREERTOS_ERRNO_EOPNOTSUPP       95  /* Operation not supported on transport endpoint */
-#define pdFREERTOS_ERRNO_ENOBUFS          105 /* No buffer space available */
-#define pdFREERTOS_ERRNO_ENOPROTOOPT      109 /* Protocol not available */
-#define pdFREERTOS_ERRNO_EADDRINUSE       112 /* Address already in use */
-#define pdFREERTOS_ERRNO_ETIMEDOUT        116 /* Connection timed out */
-#define pdFREERTOS_ERRNO_EINPROGRESS      119 /* Connection already in progress */
-#define pdFREERTOS_ERRNO_EALREADY         120 /* Socket already connected */
-#define pdFREERTOS_ERRNO_EADDRNOTAVAIL    125 /* Address not available */
-#define pdFREERTOS_ERRNO_EISCONN          127 /* Socket is already connected */
-#define pdFREERTOS_ERRNO_ENOTCONN         128 /* Socket is not connected */
-#define pdFREERTOS_ERRNO_ENOMEDIUM        135 /* No medium inserted */
-#define pdFREERTOS_ERRNO_EILSEQ           138 /* An invalid UTF-16 sequence was encountered. */
-#define pdFREERTOS_ERRNO_ECANCELED        140 /* Operation canceled. */
-
-/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
- * itself. */
-#define pdFREERTOS_LITTLE_ENDIAN          0
-#define pdFREERTOS_BIG_ENDIAN             1
-
-/* Re-defining endian values for generic naming. */
-#define pdLITTLE_ENDIAN                   pdFREERTOS_LITTLE_ENDIAN
-#define pdBIG_ENDIAN                      pdFREERTOS_BIG_ENDIAN
-
-
-#endif /* PROJDEFS_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/queue.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/queue.h
deleted file mode 100644
index bc0f6f0..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/queue.h
+++ /dev/null
@@ -1,1716 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef QUEUE_H
-#define QUEUE_H
-
-#ifndef INC_FREERTOS_H
-    #error "include FreeRTOS.h" must appear in source files before "include queue.h"
-#endif
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
-#include "task.h"
-
-/**
- * Type by which queues are referenced.  For example, a call to xQueueCreate()
- * returns an QueueHandle_t variable that can then be used as a parameter to
- * xQueueSend(), xQueueReceive(), etc.
- */
-struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
-typedef struct QueueDefinition   * QueueHandle_t;
-
-/**
- * Type by which queue sets are referenced.  For example, a call to
- * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
- * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
- */
-typedef struct QueueDefinition   * QueueSetHandle_t;
-
-/**
- * Queue sets can contain both queues and semaphores, so the
- * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
- * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
- */
-typedef struct QueueDefinition   * QueueSetMemberHandle_t;
-
-/* For internal use only. */
-#define queueSEND_TO_BACK                     ( ( BaseType_t ) 0 )
-#define queueSEND_TO_FRONT                    ( ( BaseType_t ) 1 )
-#define queueOVERWRITE                        ( ( BaseType_t ) 2 )
-
-/* For internal use only.  These definitions *must* match those in queue.c. */
-#define queueQUEUE_TYPE_BASE                  ( ( uint8_t ) 0U )
-#define queueQUEUE_TYPE_SET                   ( ( uint8_t ) 0U )
-#define queueQUEUE_TYPE_MUTEX                 ( ( uint8_t ) 1U )
-#define queueQUEUE_TYPE_COUNTING_SEMAPHORE    ( ( uint8_t ) 2U )
-#define queueQUEUE_TYPE_BINARY_SEMAPHORE      ( ( uint8_t ) 3U )
-#define queueQUEUE_TYPE_RECURSIVE_MUTEX       ( ( uint8_t ) 4U )
-
-/**
- * queue. h
- * 
- * QueueHandle_t xQueueCreate(
- *                            UBaseType_t uxQueueLength,
- *                            UBaseType_t uxItemSize
- *                        );
- * 

- *
- * Creates a new queue instance, and returns a handle by which the new queue
- * can be referenced.
- *
- * Internally, within the FreeRTOS implementation, queues use two blocks of
- * memory.  The first block is used to hold the queue's data structures.  The
- * second block is used to hold items placed into the queue.  If a queue is
- * created using xQueueCreate() then both blocks of memory are automatically
- * dynamically allocated inside the xQueueCreate() function.  (see
- * https://www.FreeRTOS.org/a00111.html).  If a queue is created using
- * xQueueCreateStatic() then the application writer must provide the memory that
- * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
- * be created without using any dynamic memory allocation.
- *
- * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
- *
- * @param uxQueueLength The maximum number of items that the queue can contain.
- *
- * @param uxItemSize The number of bytes each item in the queue will require.
- * Items are queued by copy, not by reference, so this is the number of bytes
- * that will be copied for each posted item.  Each item on the queue must be
- * the same size.
- *
- * @return If the queue is successfully create then a handle to the newly
- * created queue is returned.  If the queue cannot be created then 0 is
- * returned.
- *
- * Example usage:
- * 
- * struct AMessage
- * {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- * };
- *
- * void vATask( void *pvParameters )
- * {
- * QueueHandle_t xQueue1, xQueue2;
- *
- *  // Create a queue capable of containing 10 uint32_t values.
- *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
- *  if( xQueue1 == 0 )
- *  {
- *      // Queue was not created and must not be used.
- *  }
- *
- *  // Create a queue capable of containing 10 pointers to AMessage structures.
- *  // These should be passed by pointer as they contain a lot of data.
- *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *  if( xQueue2 == 0 )
- *  {
- *      // Queue was not created and must not be used.
- *  }
- *
- *  // ... Rest of task code.
- * }
- * 

- * \defgroup xQueueCreate xQueueCreate
- * \ingroup QueueManagement
- */
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    #define xQueueCreate( uxQueueLength, uxItemSize )    xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
-#endif
-
-/**
- * queue. h
- * 
- * QueueHandle_t xQueueCreateStatic(
- *                            UBaseType_t uxQueueLength,
- *                            UBaseType_t uxItemSize,
- *                            uint8_t *pucQueueStorageBuffer,
- *                            StaticQueue_t *pxQueueBuffer
- *                        );
- * 

- *
- * Creates a new queue instance, and returns a handle by which the new queue
- * can be referenced.
- *
- * Internally, within the FreeRTOS implementation, queues use two blocks of
- * memory.  The first block is used to hold the queue's data structures.  The
- * second block is used to hold items placed into the queue.  If a queue is
- * created using xQueueCreate() then both blocks of memory are automatically
- * dynamically allocated inside the xQueueCreate() function.  (see
- * https://www.FreeRTOS.org/a00111.html).  If a queue is created using
- * xQueueCreateStatic() then the application writer must provide the memory that
- * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
- * be created without using any dynamic memory allocation.
- *
- * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
- *
- * @param uxQueueLength The maximum number of items that the queue can contain.
- *
- * @param uxItemSize The number of bytes each item in the queue will require.
- * Items are queued by copy, not by reference, so this is the number of bytes
- * that will be copied for each posted item.  Each item on the queue must be
- * the same size.
- *
- * @param pucQueueStorageBuffer If uxItemSize is not zero then
- * pucQueueStorageBuffer must point to a uint8_t array that is at least large
- * enough to hold the maximum number of items that can be in the queue at any
- * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
- * zero then pucQueueStorageBuffer can be NULL.
- *
- * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
- * will be used to hold the queue's data structure.
- *
- * @return If the queue is created then a handle to the created queue is
- * returned.  If pxQueueBuffer is NULL then NULL is returned.
- *
- * Example usage:
- * 
- * struct AMessage
- * {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- * };
- *
- #define QUEUE_LENGTH 10
- #define ITEM_SIZE sizeof( uint32_t )
- *
- * // xQueueBuffer will hold the queue structure.
- * StaticQueue_t xQueueBuffer;
- *
- * // ucQueueStorage will hold the items posted to the queue.  Must be at least
- * // [(queue length) * ( queue item size)] bytes long.
- * uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
- *
- * void vATask( void *pvParameters )
- * {
- * QueueHandle_t xQueue1;
- *
- *  // Create a queue capable of containing 10 uint32_t values.
- *  xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
- *                          ITEM_SIZE     // The size of each item in the queue
- *                          &( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
- *                          &xQueueBuffer ); // The buffer that will hold the queue structure.
- *
- *  // The queue is guaranteed to be created successfully as no dynamic memory
- *  // allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
- *
- *  // ... Rest of task code.
- * }
- * 

- * \defgroup xQueueCreateStatic xQueueCreateStatic
- * \ingroup QueueManagement
- */
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    #define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer )    xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * queue. h
- * 
- * BaseType_t xQueueSendToToFront(
- *                                 QueueHandle_t    xQueue,
- *                                 const void       *pvItemToQueue,
- *                                 TickType_t       xTicksToWait
- *                             );
- * 

- *
- * Post an item to the front of a queue.  The item is queued by copy, not by
- * reference.  This function must not be called from an interrupt service
- * routine.  See xQueueSendFromISR () for an alternative which may be used
- * in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the
- * queue is full.  The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
- * 
- * struct AMessage
- * {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- * } xMessage;
- *
- * uint32_t ulVar = 10UL;
- *
- * void vATask( void *pvParameters )
- * {
- * QueueHandle_t xQueue1, xQueue2;
- * struct AMessage *pxMessage;
- *
- *  // Create a queue capable of containing 10 uint32_t values.
- *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
- *
- *  // Create a queue capable of containing 10 pointers to AMessage structures.
- *  // These should be passed by pointer as they contain a lot of data.
- *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *
- *  // ...
- *
- *  if( xQueue1 != 0 )
- *  {
- *      // Send an uint32_t.  Wait for 10 ticks for space to become
- *      // available if necessary.
- *      if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
- *      {
- *          // Failed to post the message, even after 10 ticks.
- *      }
- *  }
- *
- *  if( xQueue2 != 0 )
- *  {
- *      // Send a pointer to a struct AMessage object.  Don't block if the
- *      // queue is already full.
- *      pxMessage = & xMessage;
- *      xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
- *  }
- *
- *  // ... Rest of task code.
- * }
- * 

- * \defgroup xQueueSend xQueueSend
- * \ingroup QueueManagement
- */
-#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) \
-    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
-
-/**
- * queue. h
- * 
- * BaseType_t xQueueSendToBack(
- *                                 QueueHandle_t    xQueue,
- *                                 const void       *pvItemToQueue,
- *                                 TickType_t       xTicksToWait
- *                             );
- * 

- *
- * This is a macro that calls xQueueGenericSend().
- *
- * Post an item to the back of a queue.  The item is queued by copy, not by
- * reference.  This function must not be called from an interrupt service
- * routine.  See xQueueSendFromISR () for an alternative which may be used
- * in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the queue
- * is full.  The  time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
- * 
- * struct AMessage
- * {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- * } xMessage;
- *
- * uint32_t ulVar = 10UL;
- *
- * void vATask( void *pvParameters )
- * {
- * QueueHandle_t xQueue1, xQueue2;
- * struct AMessage *pxMessage;
- *
- *  // Create a queue capable of containing 10 uint32_t values.
- *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
- *
- *  // Create a queue capable of containing 10 pointers to AMessage structures.
- *  // These should be passed by pointer as they contain a lot of data.
- *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *
- *  // ...
- *
- *  if( xQueue1 != 0 )
- *  {
- *      // Send an uint32_t.  Wait for 10 ticks for space to become
- *      // available if necessary.
- *      if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
- *      {
- *          // Failed to post the message, even after 10 ticks.
- *      }
- *  }
- *
- *  if( xQueue2 != 0 )
- *  {
- *      // Send a pointer to a struct AMessage object.  Don't block if the
- *      // queue is already full.
- *      pxMessage = & xMessage;
- *      xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
- *  }
- *
- *  // ... Rest of task code.
- * }
- * 

- * \defgroup xQueueSend xQueueSend
- * \ingroup QueueManagement
- */
-#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) \
-    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
-
-/**
- * queue. h
- * 
- * BaseType_t xQueueSend(
- *                            QueueHandle_t xQueue,
- *                            const void * pvItemToQueue,
- *                            TickType_t xTicksToWait
- *                       );
- * 

- *
- * This is a macro that calls xQueueGenericSend().  It is included for
- * backward compatibility with versions of FreeRTOS.org that did not
- * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
- * equivalent to xQueueSendToBack().
- *
- * Post an item on a queue.  The item is queued by copy, not by reference.
- * This function must not be called from an interrupt service routine.
- * See xQueueSendFromISR () for an alternative which may be used in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the
- * queue is full.  The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
- * 
- * struct AMessage
- * {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- * } xMessage;
- *
- * uint32_t ulVar = 10UL;
- *
- * void vATask( void *pvParameters )
- * {
- * QueueHandle_t xQueue1, xQueue2;
- * struct AMessage *pxMessage;
- *
- *  // Create a queue capable of containing 10 uint32_t values.
- *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
- *
- *  // Create a queue capable of containing 10 pointers to AMessage structures.
- *  // These should be passed by pointer as they contain a lot of data.
- *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *
- *  // ...
- *
- *  if( xQueue1 != 0 )
- *  {
- *      // Send an uint32_t.  Wait for 10 ticks for space to become
- *      // available if necessary.
- *      if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
- *      {
- *          // Failed to post the message, even after 10 ticks.
- *      }
- *  }
- *
- *  if( xQueue2 != 0 )
- *  {
- *      // Send a pointer to a struct AMessage object.  Don't block if the
- *      // queue is already full.
- *      pxMessage = & xMessage;
- *      xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
- *  }
- *
- *  // ... Rest of task code.
- * }
- * 

- * \defgroup xQueueSend xQueueSend
- * \ingroup QueueManagement
- */
-#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) \
-    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
-
-/**
- * queue. h
- * 
- * BaseType_t xQueueOverwrite(
- *                            QueueHandle_t xQueue,
- *                            const void * pvItemToQueue
- *                       );
- * 

- *
- * Only for use with queues that have a length of one - so the queue is either
- * empty or full.
- *
- * Post an item on a queue.  If the queue is already full then overwrite the
- * value held in the queue.  The item is queued by copy, not by reference.
- *
- * This function must not be called from an interrupt service routine.
- * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
- *
- * @param xQueue The handle of the queue to which the data is being sent.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
- * therefore has the same return values as xQueueSendToFront().  However, pdPASS
- * is the only value that can be returned because xQueueOverwrite() will write
- * to the queue even when the queue is already full.
- *
- * Example usage:
- * 
- *
- * void vFunction( void *pvParameters )
- * {
- * QueueHandle_t xQueue;
- * uint32_t ulVarToSend, ulValReceived;
- *
- *  // Create a queue to hold one uint32_t value.  It is strongly
- *  // recommended *not* to use xQueueOverwrite() on queues that can
- *  // contain more than one value, and doing so will trigger an assertion
- *  // if configASSERT() is defined.
- *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
- *
- *  // Write the value 10 to the queue using xQueueOverwrite().
- *  ulVarToSend = 10;
- *  xQueueOverwrite( xQueue, &ulVarToSend );
- *
- *  // Peeking the queue should now return 10, but leave the value 10 in
- *  // the queue.  A block time of zero is used as it is known that the
- *  // queue holds a value.
- *  ulValReceived = 0;
- *  xQueuePeek( xQueue, &ulValReceived, 0 );
- *
- *  if( ulValReceived != 10 )
- *  {
- *      // Error unless the item was removed by a different task.
- *  }
- *
- *  // The queue is still full.  Use xQueueOverwrite() to overwrite the
- *  // value held in the queue with 100.
- *  ulVarToSend = 100;
- *  xQueueOverwrite( xQueue, &ulVarToSend );
- *
- *  // This time read from the queue, leaving the queue empty once more.
- *  // A block time of 0 is used again.
- *  xQueueReceive( xQueue, &ulValReceived, 0 );
- *
- *  // The value read should be the last value written, even though the
- *  // queue was already full when the value was written.
- *  if( ulValReceived != 100 )
- *  {
- *      // Error!
- *  }
- *
- *  // ...
- * }
- * 

- * \defgroup xQueueOverwrite xQueueOverwrite
- * \ingroup QueueManagement
- */
-#define xQueueOverwrite( xQueue, pvItemToQueue ) \
-    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
-
-
-/**
- * queue. h
- * 
- * BaseType_t xQueueGenericSend(
- *                                  QueueHandle_t xQueue,
- *                                  const void * pvItemToQueue,
- *                                  TickType_t xTicksToWait
- *                                  BaseType_t xCopyPosition
- *                              );
- * 

- *
- * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
- * xQueueSendToBack() are used in place of calling this function directly.
- *
- * Post an item on a queue.  The item is queued by copy, not by reference.
- * This function must not be called from an interrupt service routine.
- * See xQueueSendFromISR () for an alternative which may be used in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the
- * queue is full.  The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
- * item at the back of the queue, or queueSEND_TO_FRONT to place the item
- * at the front of the queue (for high priority messages).
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
- * 
- * struct AMessage
- * {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- * } xMessage;
- *
- * uint32_t ulVar = 10UL;
- *
- * void vATask( void *pvParameters )
- * {
- * QueueHandle_t xQueue1, xQueue2;
- * struct AMessage *pxMessage;
- *
- *  // Create a queue capable of containing 10 uint32_t values.
- *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
- *
- *  // Create a queue capable of containing 10 pointers to AMessage structures.
- *  // These should be passed by pointer as they contain a lot of data.
- *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *
- *  // ...
- *
- *  if( xQueue1 != 0 )
- *  {
- *      // Send an uint32_t.  Wait for 10 ticks for space to become
- *      // available if necessary.
- *      if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
- *      {
- *          // Failed to post the message, even after 10 ticks.
- *      }
- *  }
- *
- *  if( xQueue2 != 0 )
- *  {
- *      // Send a pointer to a struct AMessage object.  Don't block if the
- *      // queue is already full.
- *      pxMessage = & xMessage;
- *      xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
- *  }
- *
- *  // ... Rest of task code.
- * }
- * 

- * \defgroup xQueueSend xQueueSend
- * \ingroup QueueManagement
- */
-BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
-                              const void * const pvItemToQueue,
-                              TickType_t xTicksToWait,
-                              const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- * BaseType_t xQueuePeek(
- *                           QueueHandle_t xQueue,
- *                           void * const pvBuffer,
- *                           TickType_t xTicksToWait
- *                       );
- * 

- *
- * Receive an item from a queue without removing the item from the queue.
- * The item is received by copy so a buffer of adequate size must be
- * provided.  The number of bytes copied into the buffer was defined when
- * the queue was created.
- *
- * Successfully received items remain on the queue so will be returned again
- * by the next call, or a call to xQueueReceive().
- *
- * This macro must not be used in an interrupt service routine.  See
- * xQueuePeekFromISR() for an alternative that can be called from an interrupt
- * service routine.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for an item to receive should the queue be empty at the time
- * of the call. The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
- * is empty.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
- * 
- * struct AMessage
- * {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- * } xMessage;
- *
- * QueueHandle_t xQueue;
- *
- * // Task to create a queue and post a value.
- * void vATask( void *pvParameters )
- * {
- * struct AMessage *pxMessage;
- *
- *  // Create a queue capable of containing 10 pointers to AMessage structures.
- *  // These should be passed by pointer as they contain a lot of data.
- *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *  if( xQueue == 0 )
- *  {
- *      // Failed to create the queue.
- *  }
- *
- *  // ...
- *
- *  // Send a pointer to a struct AMessage object.  Don't block if the
- *  // queue is already full.
- *  pxMessage = & xMessage;
- *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
- *
- *  // ... Rest of task code.
- * }
- *
- * // Task to peek the data from the queue.
- * void vADifferentTask( void *pvParameters )
- * {
- * struct AMessage *pxRxedMessage;
- *
- *  if( xQueue != 0 )
- *  {
- *      // Peek a message on the created queue.  Block for 10 ticks if a
- *      // message is not immediately available.
- *      if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
- *      {
- *          // pcRxedMessage now points to the struct AMessage variable posted
- *          // by vATask, but the item still remains on the queue.
- *      }
- *  }
- *
- *  // ... Rest of task code.
- * }
- * 

- * \defgroup xQueuePeek xQueuePeek
- * \ingroup QueueManagement
- */
-BaseType_t xQueuePeek( QueueHandle_t xQueue,
-                       void * const pvBuffer,
-                       TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- * BaseType_t xQueuePeekFromISR(
- *                                  QueueHandle_t xQueue,
- *                                  void *pvBuffer,
- *                              );
- * 

- *
- * A version of xQueuePeek() that can be called from an interrupt service
- * routine (ISR).
- *
- * Receive an item from a queue without removing the item from the queue.
- * The item is received by copy so a buffer of adequate size must be
- * provided.  The number of bytes copied into the buffer was defined when
- * the queue was created.
- *
- * Successfully received items remain on the queue so will be returned again
- * by the next call, or a call to xQueueReceive().
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * \defgroup xQueuePeekFromISR xQueuePeekFromISR
- * \ingroup QueueManagement
- */
-BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
-                              void * const pvBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- * BaseType_t xQueueReceive(
- *                               QueueHandle_t xQueue,
- *                               void *pvBuffer,
- *                               TickType_t xTicksToWait
- *                          );
- * 

- *
- * Receive an item from a queue.  The item is received by copy so a buffer of
- * adequate size must be provided.  The number of bytes copied into the buffer
- * was defined when the queue was created.
- *
- * Successfully received items are removed from the queue.
- *
- * This function must not be used in an interrupt service routine.  See
- * xQueueReceiveFromISR for an alternative that can.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for an item to receive should the queue be empty at the time
- * of the call. xQueueReceive() will return immediately if xTicksToWait
- * is zero and the queue is empty.  The time is defined in tick periods so the
- * constant portTICK_PERIOD_MS should be used to convert to real time if this is
- * required.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
- * 
- * struct AMessage
- * {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- * } xMessage;
- *
- * QueueHandle_t xQueue;
- *
- * // Task to create a queue and post a value.
- * void vATask( void *pvParameters )
- * {
- * struct AMessage *pxMessage;
- *
- *  // Create a queue capable of containing 10 pointers to AMessage structures.
- *  // These should be passed by pointer as they contain a lot of data.
- *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *  if( xQueue == 0 )
- *  {
- *      // Failed to create the queue.
- *  }
- *
- *  // ...
- *
- *  // Send a pointer to a struct AMessage object.  Don't block if the
- *  // queue is already full.
- *  pxMessage = & xMessage;
- *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
- *
- *  // ... Rest of task code.
- * }
- *
- * // Task to receive from the queue.
- * void vADifferentTask( void *pvParameters )
- * {
- * struct AMessage *pxRxedMessage;
- *
- *  if( xQueue != 0 )
- *  {
- *      // Receive a message on the created queue.  Block for 10 ticks if a
- *      // message is not immediately available.
- *      if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
- *      {
- *          // pcRxedMessage now points to the struct AMessage variable posted
- *          // by vATask.
- *      }
- *  }
- *
- *  // ... Rest of task code.
- * }
- * 

- * \defgroup xQueueReceive xQueueReceive
- * \ingroup QueueManagement
- */
-BaseType_t xQueueReceive( QueueHandle_t xQueue,
-                          void * const pvBuffer,
-                          TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- * UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );
- * 

- *
- * Return the number of messages stored in a queue.
- *
- * @param xQueue A handle to the queue being queried.
- *
- * @return The number of messages available in the queue.
- *
- * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
- * \ingroup QueueManagement
- */
-UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- * UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );
- * 

- *
- * Return the number of free spaces available in a queue.  This is equal to the
- * number of items that can be sent to the queue before the queue becomes full
- * if no items are removed.
- *
- * @param xQueue A handle to the queue being queried.
- *
- * @return The number of spaces available in the queue.
- *
- * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
- * \ingroup QueueManagement
- */
-UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- * void vQueueDelete( QueueHandle_t xQueue );
- * 

- *
- * Delete a queue - freeing all the memory allocated for storing of items
- * placed on the queue.
- *
- * @param xQueue A handle to the queue to be deleted.
- *
- * \defgroup vQueueDelete vQueueDelete
- * \ingroup QueueManagement
- */
-void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- * BaseType_t xQueueSendToFrontFromISR(
- *                                       QueueHandle_t xQueue,
- *                                       const void *pvItemToQueue,
- *                                       BaseType_t *pxHigherPriorityTaskWoken
- *                                    );
- * 

- *
- * This is a macro that calls xQueueGenericSendFromISR().
- *
- * Post an item to the front of a queue.  It is safe to use this macro from
- * within an interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
- * 
- * void vBufferISR( void )
- * {
- * char cIn;
- * BaseType_t xHigherPrioritTaskWoken;
- *
- *  // We have not woken a task at the start of the ISR.
- *  xHigherPriorityTaskWoken = pdFALSE;
- *
- *  // Loop until the buffer is empty.
- *  do
- *  {
- *      // Obtain a byte from the buffer.
- *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
- *
- *      // Post the byte.
- *      xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
- *
- *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
- *
- *  // Now the buffer is empty we can switch context if necessary.
- *  if( xHigherPriorityTaskWoken )
- *  {
- *      taskYIELD ();
- *  }
- * }
- * 

- *
- * \defgroup xQueueSendFromISR xQueueSendFromISR
- * \ingroup QueueManagement
- */
-#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
-    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
-
-
-/**
- * queue. h
- * 
- * BaseType_t xQueueSendToBackFromISR(
- *                                       QueueHandle_t xQueue,
- *                                       const void *pvItemToQueue,
- *                                       BaseType_t *pxHigherPriorityTaskWoken
- *                                    );
- * 

- *
- * This is a macro that calls xQueueGenericSendFromISR().
- *
- * Post an item to the back of a queue.  It is safe to use this macro from
- * within an interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
- * 
- * void vBufferISR( void )
- * {
- * char cIn;
- * BaseType_t xHigherPriorityTaskWoken;
- *
- *  // We have not woken a task at the start of the ISR.
- *  xHigherPriorityTaskWoken = pdFALSE;
- *
- *  // Loop until the buffer is empty.
- *  do
- *  {
- *      // Obtain a byte from the buffer.
- *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
- *
- *      // Post the byte.
- *      xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
- *
- *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
- *
- *  // Now the buffer is empty we can switch context if necessary.
- *  if( xHigherPriorityTaskWoken )
- *  {
- *      taskYIELD ();
- *  }
- * }
- * 

- *
- * \defgroup xQueueSendFromISR xQueueSendFromISR
- * \ingroup QueueManagement
- */
-#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
-    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
-
-/**
- * queue. h
- * 
- * BaseType_t xQueueOverwriteFromISR(
- *                            QueueHandle_t xQueue,
- *                            const void * pvItemToQueue,
- *                            BaseType_t *pxHigherPriorityTaskWoken
- *                       );
- * 

- *
- * A version of xQueueOverwrite() that can be used in an interrupt service
- * routine (ISR).
- *
- * Only for use with queues that can hold a single item - so the queue is either
- * empty or full.
- *
- * Post an item on a queue.  If the queue is already full then overwrite the
- * value held in the queue.  The item is queued by copy, not by reference.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return xQueueOverwriteFromISR() is a macro that calls
- * xQueueGenericSendFromISR(), and therefore has the same return values as
- * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
- * returned because xQueueOverwriteFromISR() will write to the queue even when
- * the queue is already full.
- *
- * Example usage:
- * 
- *
- * QueueHandle_t xQueue;
- *
- * void vFunction( void *pvParameters )
- * {
- *  // Create a queue to hold one uint32_t value.  It is strongly
- *  // recommended *not* to use xQueueOverwriteFromISR() on queues that can
- *  // contain more than one value, and doing so will trigger an assertion
- *  // if configASSERT() is defined.
- *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
- * }
- *
- * void vAnInterruptHandler( void )
- * {
- * // xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- * uint32_t ulVarToSend, ulValReceived;
- *
- *  // Write the value 10 to the queue using xQueueOverwriteFromISR().
- *  ulVarToSend = 10;
- *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
- *
- *  // The queue is full, but calling xQueueOverwriteFromISR() again will still
- *  // pass because the value held in the queue will be overwritten with the
- *  // new value.
- *  ulVarToSend = 100;
- *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
- *
- *  // Reading from the queue will now return 100.
- *
- *  // ...
- *
- *  if( xHigherPrioritytaskWoken == pdTRUE )
- *  {
- *      // Writing to the queue caused a task to unblock and the unblocked task
- *      // has a priority higher than or equal to the priority of the currently
- *      // executing task (the task this interrupt interrupted).  Perform a context
- *      // switch so this interrupt returns directly to the unblocked task.
- *      portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
- *  }
- * }
- * 

- * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
- * \ingroup QueueManagement
- */
-#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
-    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
-
-/**
- * queue. h
- * 
- * BaseType_t xQueueSendFromISR(
- *                                   QueueHandle_t xQueue,
- *                                   const void *pvItemToQueue,
- *                                   BaseType_t *pxHigherPriorityTaskWoken
- *                              );
- * 

- *
- * This is a macro that calls xQueueGenericSendFromISR().  It is included
- * for backward compatibility with versions of FreeRTOS.org that did not
- * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
- * macros.
- *
- * Post an item to the back of a queue.  It is safe to use this function from
- * within an interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
- * 
- * void vBufferISR( void )
- * {
- * char cIn;
- * BaseType_t xHigherPriorityTaskWoken;
- *
- *  // We have not woken a task at the start of the ISR.
- *  xHigherPriorityTaskWoken = pdFALSE;
- *
- *  // Loop until the buffer is empty.
- *  do
- *  {
- *      // Obtain a byte from the buffer.
- *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
- *
- *      // Post the byte.
- *      xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
- *
- *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
- *
- *  // Now the buffer is empty we can switch context if necessary.
- *  if( xHigherPriorityTaskWoken )
- *  {
- *      // Actual macro used here is port specific.
- *      portYIELD_FROM_ISR ();
- *  }
- * }
- * 

- *
- * \defgroup xQueueSendFromISR xQueueSendFromISR
- * \ingroup QueueManagement
- */
-#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
-    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
-
-/**
- * queue. h
- * 
- * BaseType_t xQueueGenericSendFromISR(
- *                                         QueueHandle_t    xQueue,
- *                                         const    void    *pvItemToQueue,
- *                                         BaseType_t  *pxHigherPriorityTaskWoken,
- *                                         BaseType_t  xCopyPosition
- *                                     );
- * 

- *
- * It is preferred that the macros xQueueSendFromISR(),
- * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
- * of calling this function directly.  xQueueGiveFromISR() is an
- * equivalent for use by semaphores that don't actually copy any data.
- *
- * Post an item on a queue.  It is safe to use this function from within an
- * interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
- * item at the back of the queue, or queueSEND_TO_FRONT to place the item
- * at the front of the queue (for high priority messages).
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
- * 
- * void vBufferISR( void )
- * {
- * char cIn;
- * BaseType_t xHigherPriorityTaskWokenByPost;
- *
- *  // We have not woken a task at the start of the ISR.
- *  xHigherPriorityTaskWokenByPost = pdFALSE;
- *
- *  // Loop until the buffer is empty.
- *  do
- *  {
- *      // Obtain a byte from the buffer.
- *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
- *
- *      // Post each byte.
- *      xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
- *
- *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
- *
- *  // Now the buffer is empty we can switch context if necessary.  Note that the
- *  // name of the yield function required is port specific.
- *  if( xHigherPriorityTaskWokenByPost )
- *  {
- *      portYIELD_FROM_ISR();
- *  }
- * }
- * 

- *
- * \defgroup xQueueSendFromISR xQueueSendFromISR
- * \ingroup QueueManagement
- */
-BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
-                                     const void * const pvItemToQueue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
-                              BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- * BaseType_t xQueueReceiveFromISR(
- *                                     QueueHandle_t    xQueue,
- *                                     void             *pvBuffer,
- *                                     BaseType_t       *pxTaskWoken
- *                                 );
- * 

- *
- * Receive an item from a queue.  It is safe to use this function from within an
- * interrupt service routine.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param pxTaskWoken A task may be blocked waiting for space to become
- * available on the queue.  If xQueueReceiveFromISR causes such a task to
- * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
- * remain unchanged.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
- * 
- *
- * QueueHandle_t xQueue;
- *
- * // Function to create a queue and post some values.
- * void vAFunction( void *pvParameters )
- * {
- * char cValueToPost;
- * const TickType_t xTicksToWait = ( TickType_t )0xff;
- *
- *  // Create a queue capable of containing 10 characters.
- *  xQueue = xQueueCreate( 10, sizeof( char ) );
- *  if( xQueue == 0 )
- *  {
- *      // Failed to create the queue.
- *  }
- *
- *  // ...
- *
- *  // Post some characters that will be used within an ISR.  If the queue
- *  // is full then this task will block for xTicksToWait ticks.
- *  cValueToPost = 'a';
- *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
- *  cValueToPost = 'b';
- *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
- *
- *  // ... keep posting characters ... this task may block when the queue
- *  // becomes full.
- *
- *  cValueToPost = 'c';
- *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
- * }
- *
- * // ISR that outputs all the characters received on the queue.
- * void vISR_Routine( void )
- * {
- * BaseType_t xTaskWokenByReceive = pdFALSE;
- * char cRxedChar;
- *
- *  while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
- *  {
- *      // A character was received.  Output the character now.
- *      vOutputCharacter( cRxedChar );
- *
- *      // If removing the character from the queue woke the task that was
- *      // posting onto the queue cTaskWokenByReceive will have been set to
- *      // pdTRUE.  No matter how many times this loop iterates only one
- *      // task will be woken.
- *  }
- *
- *  if( cTaskWokenByPost != ( char ) pdFALSE;
- *  {
- *      taskYIELD ();
- *  }
- * }
- * 

- * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
- * \ingroup QueueManagement
- */
-BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
-                                 void * const pvBuffer,
-                                 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/*
- * Utilities to query queues that are safe to use from an ISR.  These utilities
- * should be used only from witin an ISR, or within a critical section.
- */
-BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * The functions defined above are for passing data to and from tasks.  The
- * functions below are the equivalents for passing data to and from
- * co-routines.
- *
- * These functions are called from the co-routine macro implementation and
- * should not be called directly from application code.  Instead use the macro
- * wrappers defined within croutine.h.
- */
-BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
-                                const void * pvItemToQueue,
-                                BaseType_t xCoRoutinePreviouslyWoken );
-BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
-                                   void * pvBuffer,
-                                   BaseType_t * pxTaskWoken );
-BaseType_t xQueueCRSend( QueueHandle_t xQueue,
-                         const void * pvItemToQueue,
-                         TickType_t xTicksToWait );
-BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
-                            void * pvBuffer,
-                            TickType_t xTicksToWait );
-
-/*
- * For internal use only.  Use xSemaphoreCreateMutex(),
- * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
- * these functions directly.
- */
-QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
-                                       StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
-                                             const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
-                                                   const UBaseType_t uxInitialCount,
-                                                   StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
-TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
-
-/*
- * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
- * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
- */
-BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                     TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
-
-/*
- * Reset a queue back to its original empty state.  The return value is now
- * obsolete and is always set to pdPASS.
- */
-#define xQueueReset( xQueue )    xQueueGenericReset( xQueue, pdFALSE )
-
-/*
- * The registry is provided as a means for kernel aware debuggers to
- * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
- * a queue, semaphore or mutex handle to the registry if you want the handle
- * to be available to a kernel aware debugger.  If you are not using a kernel
- * aware debugger then this function can be ignored.
- *
- * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
- * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
- * within FreeRTOSConfig.h for the registry to be available.  Its value
- * does not effect the number of queues, semaphores and mutexes that can be
- * created - just the number that the registry can hold.
- *
- * @param xQueue The handle of the queue being added to the registry.  This
- * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
- * handles can also be passed in here.
- *
- * @param pcName The name to be associated with the handle.  This is the
- * name that the kernel aware debugger will display.  The queue registry only
- * stores a pointer to the string - so the string must be persistent (global or
- * preferably in ROM/Flash), not on the stack.
- */
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-    void vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-#endif
-
-/*
- * The registry is provided as a means for kernel aware debuggers to
- * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
- * a queue, semaphore or mutex handle to the registry if you want the handle
- * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
- * remove the queue, semaphore or mutex from the register.  If you are not using
- * a kernel aware debugger then this function can be ignored.
- *
- * @param xQueue The handle of the queue being removed from the registry.
- */
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-    void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-#endif
-
-/*
- * The queue registry is provided as a means for kernel aware debuggers to
- * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
- * up and return the name of a queue in the queue registry from the queue's
- * handle.
- *
- * @param xQueue The handle of the queue the name of which will be returned.
- * @return If the queue is in the registry then a pointer to the name of the
- * queue is returned.  If the queue is not in the registry then NULL is
- * returned.
- */
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-    const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-#endif
-
-/*
- * Generic version of the function used to create a queue using dynamic memory
- * allocation.  This is called by other functions and macros that create other
- * RTOS objects that use the queue structure as their base.
- */
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength,
-                                       const UBaseType_t uxItemSize,
-                                       const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-#endif
-
-/*
- * Generic version of the function used to create a queue using dynamic memory
- * allocation.  This is called by other functions and macros that create other
- * RTOS objects that use the queue structure as their base.
- */
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
-                                             const UBaseType_t uxItemSize,
-                                             uint8_t * pucQueueStorage,
-                                             StaticQueue_t * pxStaticQueue,
-                                             const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-#endif
-
-/*
- * Queue sets provide a mechanism to allow a task to block (pend) on a read
- * operation from multiple queues or semaphores simultaneously.
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * A queue set must be explicitly created using a call to xQueueCreateSet()
- * before it can be used.  Once created, standard FreeRTOS queues and semaphores
- * can be added to the set using calls to xQueueAddToSet().
- * xQueueSelectFromSet() is then used to determine which, if any, of the queues
- * or semaphores contained in the set is in a state where a queue read or
- * semaphore take operation would be successful.
- *
- * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
- * for reasons why queue sets are very rarely needed in practice as there are
- * simpler methods of blocking on multiple objects.
- *
- * Note 2:  Blocking on a queue set that contains a mutex will not cause the
- * mutex holder to inherit the priority of the blocked task.
- *
- * Note 3:  An additional 4 bytes of RAM is required for each space in a every
- * queue added to a queue set.  Therefore counting semaphores that have a high
- * maximum count value should not be added to a queue set.
- *
- * Note 4:  A receive (in the case of a queue) or take (in the case of a
- * semaphore) operation must not be performed on a member of a queue set unless
- * a call to xQueueSelectFromSet() has first returned a handle to that set member.
- *
- * @param uxEventQueueLength Queue sets store events that occur on
- * the queues and semaphores contained in the set.  uxEventQueueLength specifies
- * the maximum number of events that can be queued at once.  To be absolutely
- * certain that events are not lost uxEventQueueLength should be set to the
- * total sum of the length of the queues added to the set, where binary
- * semaphores and mutexes have a length of 1, and counting semaphores have a
- * length set by their maximum count value.  Examples:
- *  + If a queue set is to hold a queue of length 5, another queue of length 12,
- *    and a binary semaphore, then uxEventQueueLength should be set to
- *    (5 + 12 + 1), or 18.
- *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
- *    should be set to (1 + 1 + 1 ), or 3.
- *  + If a queue set is to hold a counting semaphore that has a maximum count of
- *    5, and a counting semaphore that has a maximum count of 3, then
- *    uxEventQueueLength should be set to (5 + 3), or 8.
- *
- * @return If the queue set is created successfully then a handle to the created
- * queue set is returned.  Otherwise NULL is returned.
- */
-QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
-
-/*
- * Adds a queue or semaphore to a queue set that was previously created by a
- * call to xQueueCreateSet().
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * Note 1:  A receive (in the case of a queue) or take (in the case of a
- * semaphore) operation must not be performed on a member of a queue set unless
- * a call to xQueueSelectFromSet() has first returned a handle to that set member.
- *
- * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
- * the queue set (cast to an QueueSetMemberHandle_t type).
- *
- * @param xQueueSet The handle of the queue set to which the queue or semaphore
- * is being added.
- *
- * @return If the queue or semaphore was successfully added to the queue set
- * then pdPASS is returned.  If the queue could not be successfully added to the
- * queue set because it is already a member of a different queue set then pdFAIL
- * is returned.
- */
-BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                           QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-
-/*
- * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
- * be removed from a set if the queue or semaphore is empty.
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
- * from the queue set (cast to an QueueSetMemberHandle_t type).
- *
- * @param xQueueSet The handle of the queue set in which the queue or semaphore
- * is included.
- *
- * @return If the queue or semaphore was successfully removed from the queue set
- * then pdPASS is returned.  If the queue was not in the queue set, or the
- * queue (or semaphore) was not empty, then pdFAIL is returned.
- */
-BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                                QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-
-/*
- * xQueueSelectFromSet() selects from the members of a queue set a queue or
- * semaphore that either contains data (in the case of a queue) or is available
- * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
- * allows a task to block (pend) on a read operation on all the queues and
- * semaphores in a queue set simultaneously.
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
- * for reasons why queue sets are very rarely needed in practice as there are
- * simpler methods of blocking on multiple objects.
- *
- * Note 2:  Blocking on a queue set that contains a mutex will not cause the
- * mutex holder to inherit the priority of the blocked task.
- *
- * Note 3:  A receive (in the case of a queue) or take (in the case of a
- * semaphore) operation must not be performed on a member of a queue set unless
- * a call to xQueueSelectFromSet() has first returned a handle to that set member.
- *
- * @param xQueueSet The queue set on which the task will (potentially) block.
- *
- * @param xTicksToWait The maximum time, in ticks, that the calling task will
- * remain in the Blocked state (with other tasks executing) to wait for a member
- * of the queue set to be ready for a successful queue read or semaphore take
- * operation.
- *
- * @return xQueueSelectFromSet() will return the handle of a queue (cast to
- * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
- * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
- * in the queue set that is available, or NULL if no such queue or semaphore
- * exists before before the specified block time expires.
- */
-QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/*
- * A version of xQueueSelectFromSet() that can be used from an ISR.
- */
-QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-
-/* Not public API functions. */
-void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
-                                     TickType_t xTicksToWait,
-                                     const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
-                               BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
-void vQueueSetQueueNumber( QueueHandle_t xQueue,
-                           UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
-UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    }
-#endif
-/* *INDENT-ON* */
-
-#endif /* QUEUE_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/semphr.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/semphr.h
deleted file mode 100644
index a3b1ab4..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/semphr.h
+++ /dev/null
@@ -1,1173 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef SEMAPHORE_H
-#define SEMAPHORE_H
-
-#ifndef INC_FREERTOS_H
-    #error "include FreeRTOS.h" must appear in source files before "include semphr.h"
-#endif
-
-#include "queue.h"
-
-typedef QueueHandle_t SemaphoreHandle_t;
-
-#define semBINARY_SEMAPHORE_QUEUE_LENGTH    ( ( uint8_t ) 1U )
-#define semSEMAPHORE_QUEUE_ITEM_LENGTH      ( ( uint8_t ) 0U )
-#define semGIVE_BLOCK_TIME                  ( ( TickType_t ) 0U )
-
-
-/**
- * semphr. h
- * 
- * vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore );
- * 

- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a binary semaphore!
- * https://www.FreeRTOS.org/RTOS-task-notifications.html
- *
- * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
- * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
- * the vSemaphoreCreateBinary() macro are created in a state such that the
- * first call to 'take' the semaphore would pass, whereas binary semaphores
- * created using xSemaphoreCreateBinary() are created in a state such that the
- * the semaphore must first be 'given' before it can be 'taken'.
- *
- * Macro that implements a semaphore by using the existing queue mechanism.
- * The queue length is 1 as this is a binary semaphore.  The data size is 0
- * as we don't want to actually store any data - we just want to know if the
- * queue is empty or full.
- *
- * This type of semaphore can be used for pure synchronisation between tasks or
- * between an interrupt and a task.  The semaphore need not be given back once
- * obtained, so one task/interrupt can continuously 'give' the semaphore while
- * another continuously 'takes' the semaphore.  For this reason this type of
- * semaphore does not use a priority inheritance mechanism.  For an alternative
- * that does use priority inheritance see xSemaphoreCreateMutex().
- *
- * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
- *
- * Example usage:
- * 
- * SemaphoreHandle_t xSemaphore = NULL;
- *
- * void vATask( void * pvParameters )
- * {
- *  // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
- *  // This is a macro so pass the variable in directly.
- *  vSemaphoreCreateBinary( xSemaphore );
- *
- *  if( xSemaphore != NULL )
- *  {
- *      // The semaphore was created successfully.
- *      // The semaphore can now be used.
- *  }
- * }
- * 

- * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
- * \ingroup Semaphores
- */
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    #define vSemaphoreCreateBinary( xSemaphore )                                                                                     \
-    {                                                                                                                                \
-        ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \
-        if( ( xSemaphore ) != NULL )                                                                                                 \
-        {                                                                                                                            \
-            ( void ) xSemaphoreGive( ( xSemaphore ) );                                                                               \
-        }                                                                                                                            \
-    }
-#endif
-
-/**
- * semphr. h
- * 
- * SemaphoreHandle_t xSemaphoreCreateBinary( void );
- * 

- *
- * Creates a new binary semaphore instance, and returns a handle by which the
- * new semaphore can be referenced.
- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a binary semaphore!
- * https://www.FreeRTOS.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, binary semaphores use a block
- * of memory, in which the semaphore structure is stored.  If a binary semaphore
- * is created using xSemaphoreCreateBinary() then the required memory is
- * automatically dynamically allocated inside the xSemaphoreCreateBinary()
- * function.  (see https://www.FreeRTOS.org/a00111.html).  If a binary semaphore
- * is created using xSemaphoreCreateBinaryStatic() then the application writer
- * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
- * binary semaphore to be created without using any dynamic memory allocation.
- *
- * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
- * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
- * the vSemaphoreCreateBinary() macro are created in a state such that the
- * first call to 'take' the semaphore would pass, whereas binary semaphores
- * created using xSemaphoreCreateBinary() are created in a state such that the
- * the semaphore must first be 'given' before it can be 'taken'.
- *
- * This type of semaphore can be used for pure synchronisation between tasks or
- * between an interrupt and a task.  The semaphore need not be given back once
- * obtained, so one task/interrupt can continuously 'give' the semaphore while
- * another continuously 'takes' the semaphore.  For this reason this type of
- * semaphore does not use a priority inheritance mechanism.  For an alternative
- * that does use priority inheritance see xSemaphoreCreateMutex().
- *
- * @return Handle to the created semaphore, or NULL if the memory required to
- * hold the semaphore's data structures could not be allocated.
- *
- * Example usage:
- * 
- * SemaphoreHandle_t xSemaphore = NULL;
- *
- * void vATask( void * pvParameters )
- * {
- *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
- *  // This is a macro so pass the variable in directly.
- *  xSemaphore = xSemaphoreCreateBinary();
- *
- *  if( xSemaphore != NULL )
- *  {
- *      // The semaphore was created successfully.
- *      // The semaphore can now be used.
- *  }
- * }
- * 

- * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
- * \ingroup Semaphores
- */
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    #define xSemaphoreCreateBinary()    xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
-#endif
-
-/**
- * semphr. h
- * 
- * SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer );
- * 

- *
- * Creates a new binary semaphore instance, and returns a handle by which the
- * new semaphore can be referenced.
- *
- * NOTE: In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a binary semaphore!
- * https://www.FreeRTOS.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, binary semaphores use a block
- * of memory, in which the semaphore structure is stored.  If a binary semaphore
- * is created using xSemaphoreCreateBinary() then the required memory is
- * automatically dynamically allocated inside the xSemaphoreCreateBinary()
- * function.  (see https://www.FreeRTOS.org/a00111.html).  If a binary semaphore
- * is created using xSemaphoreCreateBinaryStatic() then the application writer
- * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
- * binary semaphore to be created without using any dynamic memory allocation.
- *
- * This type of semaphore can be used for pure synchronisation between tasks or
- * between an interrupt and a task.  The semaphore need not be given back once
- * obtained, so one task/interrupt can continuously 'give' the semaphore while
- * another continuously 'takes' the semaphore.  For this reason this type of
- * semaphore does not use a priority inheritance mechanism.  For an alternative
- * that does use priority inheritance see xSemaphoreCreateMutex().
- *
- * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
- * which will then be used to hold the semaphore's data structure, removing the
- * need for the memory to be allocated dynamically.
- *
- * @return If the semaphore is created then a handle to the created semaphore is
- * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
- *
- * Example usage:
- * 
- * SemaphoreHandle_t xSemaphore = NULL;
- * StaticSemaphore_t xSemaphoreBuffer;
- *
- * void vATask( void * pvParameters )
- * {
- *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
- *  // The semaphore's data structures will be placed in the xSemaphoreBuffer
- *  // variable, the address of which is passed into the function.  The
- *  // function's parameter is not NULL, so the function will not attempt any
- *  // dynamic memory allocation, and therefore the function will not return
- *  // return NULL.
- *  xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
- *
- *  // Rest of task code goes here.
- * }
- * 

- * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
- * \ingroup Semaphores
- */
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore )    xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * semphr. h
- * 
- * xSemaphoreTake(
- *                   SemaphoreHandle_t xSemaphore,
- *                   TickType_t xBlockTime
- *               );
- * 

- *
- * Macro to obtain a semaphore.  The semaphore must have previously been
- * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
- * xSemaphoreCreateCounting().
- *
- * @param xSemaphore A handle to the semaphore being taken - obtained when
- * the semaphore was created.
- *
- * @param xBlockTime The time in ticks to wait for the semaphore to become
- * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
- * real time.  A block time of zero can be used to poll the semaphore.  A block
- * time of portMAX_DELAY can be used to block indefinitely (provided
- * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
- *
- * @return pdTRUE if the semaphore was obtained.  pdFALSE
- * if xBlockTime expired without the semaphore becoming available.
- *
- * Example usage:
- * 
- * SemaphoreHandle_t xSemaphore = NULL;
- *
- * // A task that creates a semaphore.
- * void vATask( void * pvParameters )
- * {
- *  // Create the semaphore to guard a shared resource.
- *  xSemaphore = xSemaphoreCreateBinary();
- * }
- *
- * // A task that uses the semaphore.
- * void vAnotherTask( void * pvParameters )
- * {
- *  // ... Do other things.
- *
- *  if( xSemaphore != NULL )
- *  {
- *      // See if we can obtain the semaphore.  If the semaphore is not available
- *      // wait 10 ticks to see if it becomes free.
- *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
- *      {
- *          // We were able to obtain the semaphore and can now access the
- *          // shared resource.
- *
- *          // ...
- *
- *          // We have finished accessing the shared resource.  Release the
- *          // semaphore.
- *          xSemaphoreGive( xSemaphore );
- *      }
- *      else
- *      {
- *          // We could not obtain the semaphore and can therefore not access
- *          // the shared resource safely.
- *      }
- *  }
- * }
- * 

- * \defgroup xSemaphoreTake xSemaphoreTake
- * \ingroup Semaphores
- */
-#define xSemaphoreTake( xSemaphore, xBlockTime )    xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
-
-/**
- * semphr. h
- * 
- * xSemaphoreTakeRecursive(
- *                          SemaphoreHandle_t xMutex,
- *                          TickType_t xBlockTime
- *                        );
- * 

- *
- * Macro to recursively obtain, or 'take', a mutex type semaphore.
- * The mutex must have previously been created using a call to
- * xSemaphoreCreateRecursiveMutex();
- *
- * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
- * macro to be available.
- *
- * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * @param xMutex A handle to the mutex being obtained.  This is the
- * handle returned by xSemaphoreCreateRecursiveMutex();
- *
- * @param xBlockTime The time in ticks to wait for the semaphore to become
- * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
- * real time.  A block time of zero can be used to poll the semaphore.  If
- * the task already owns the semaphore then xSemaphoreTakeRecursive() will
- * return immediately no matter what the value of xBlockTime.
- *
- * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
- * expired without the semaphore becoming available.
- *
- * Example usage:
- * 
- * SemaphoreHandle_t xMutex = NULL;
- *
- * // A task that creates a mutex.
- * void vATask( void * pvParameters )
- * {
- *  // Create the mutex to guard a shared resource.
- *  xMutex = xSemaphoreCreateRecursiveMutex();
- * }
- *
- * // A task that uses the mutex.
- * void vAnotherTask( void * pvParameters )
- * {
- *  // ... Do other things.
- *
- *  if( xMutex != NULL )
- *  {
- *      // See if we can obtain the mutex.  If the mutex is not available
- *      // wait 10 ticks to see if it becomes free.
- *      if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
- *      {
- *          // We were able to obtain the mutex and can now access the
- *          // shared resource.
- *
- *          // ...
- *          // For some reason due to the nature of the code further calls to
- *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real
- *          // code these would not be just sequential calls as this would make
- *          // no sense.  Instead the calls are likely to be buried inside
- *          // a more complex call structure.
- *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
- *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
- *
- *          // The mutex has now been 'taken' three times, so will not be
- *          // available to another task until it has also been given back
- *          // three times.  Again it is unlikely that real code would have
- *          // these calls sequentially, but instead buried in a more complex
- *          // call structure.  This is just for illustrative purposes.
- *          xSemaphoreGiveRecursive( xMutex );
- *          xSemaphoreGiveRecursive( xMutex );
- *          xSemaphoreGiveRecursive( xMutex );
- *
- *          // Now the mutex can be taken by other tasks.
- *      }
- *      else
- *      {
- *          // We could not obtain the mutex and can therefore not access
- *          // the shared resource safely.
- *      }
- *  }
- * }
- * 

- * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
- * \ingroup Semaphores
- */
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-    #define xSemaphoreTakeRecursive( xMutex, xBlockTime )    xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
-#endif
-
-/**
- * semphr. h
- * 
- * xSemaphoreGive( SemaphoreHandle_t xSemaphore );
- * 

- *
- * Macro to release a semaphore.  The semaphore must have previously been
- * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
- * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
- *
- * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
- * an alternative which can be used from an ISR.
- *
- * This macro must also not be used on semaphores created using
- * xSemaphoreCreateRecursiveMutex().
- *
- * @param xSemaphore A handle to the semaphore being released.  This is the
- * handle returned when the semaphore was created.
- *
- * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
- * Semaphores are implemented using queues.  An error can occur if there is
- * no space on the queue to post a message - indicating that the
- * semaphore was not first obtained correctly.
- *
- * Example usage:
- * 
- * SemaphoreHandle_t xSemaphore = NULL;
- *
- * void vATask( void * pvParameters )
- * {
- *  // Create the semaphore to guard a shared resource.
- *  xSemaphore = vSemaphoreCreateBinary();
- *
- *  if( xSemaphore != NULL )
- *  {
- *      if( xSemaphoreGive( xSemaphore ) != pdTRUE )
- *      {
- *          // We would expect this call to fail because we cannot give
- *          // a semaphore without first "taking" it!
- *      }
- *
- *      // Obtain the semaphore - don't block if the semaphore is not
- *      // immediately available.
- *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
- *      {
- *          // We now have the semaphore and can access the shared resource.
- *
- *          // ...
- *
- *          // We have finished accessing the shared resource so can free the
- *          // semaphore.
- *          if( xSemaphoreGive( xSemaphore ) != pdTRUE )
- *          {
- *              // We would not expect this call to fail because we must have
- *              // obtained the semaphore to get here.
- *          }
- *      }
- *  }
- * }
- * 

- * \defgroup xSemaphoreGive xSemaphoreGive
- * \ingroup Semaphores
- */
-#define xSemaphoreGive( xSemaphore )    xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
-
-/**
- * semphr. h
- * 
- * xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex );
- * 

- *
- * Macro to recursively release, or 'give', a mutex type semaphore.
- * The mutex must have previously been created using a call to
- * xSemaphoreCreateRecursiveMutex();
- *
- * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
- * macro to be available.
- *
- * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * @param xMutex A handle to the mutex being released, or 'given'.  This is the
- * handle returned by xSemaphoreCreateMutex();
- *
- * @return pdTRUE if the semaphore was given.
- *
- * Example usage:
- * 
- * SemaphoreHandle_t xMutex = NULL;
- *
- * // A task that creates a mutex.
- * void vATask( void * pvParameters )
- * {
- *  // Create the mutex to guard a shared resource.
- *  xMutex = xSemaphoreCreateRecursiveMutex();
- * }
- *
- * // A task that uses the mutex.
- * void vAnotherTask( void * pvParameters )
- * {
- *  // ... Do other things.
- *
- *  if( xMutex != NULL )
- *  {
- *      // See if we can obtain the mutex.  If the mutex is not available
- *      // wait 10 ticks to see if it becomes free.
- *      if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
- *      {
- *          // We were able to obtain the mutex and can now access the
- *          // shared resource.
- *
- *          // ...
- *          // For some reason due to the nature of the code further calls to
- *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real
- *          // code these would not be just sequential calls as this would make
- *          // no sense.  Instead the calls are likely to be buried inside
- *          // a more complex call structure.
- *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
- *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
- *
- *          // The mutex has now been 'taken' three times, so will not be
- *          // available to another task until it has also been given back
- *          // three times.  Again it is unlikely that real code would have
- *          // these calls sequentially, it would be more likely that the calls
- *          // to xSemaphoreGiveRecursive() would be called as a call stack
- *          // unwound.  This is just for demonstrative purposes.
- *          xSemaphoreGiveRecursive( xMutex );
- *          xSemaphoreGiveRecursive( xMutex );
- *          xSemaphoreGiveRecursive( xMutex );
- *
- *          // Now the mutex can be taken by other tasks.
- *      }
- *      else
- *      {
- *          // We could not obtain the mutex and can therefore not access
- *          // the shared resource safely.
- *      }
- *  }
- * }
- * 

- * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
- * \ingroup Semaphores
- */
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-    #define xSemaphoreGiveRecursive( xMutex )    xQueueGiveMutexRecursive( ( xMutex ) )
-#endif
-
-/**
- * semphr. h
- * 
- * xSemaphoreGiveFromISR(
- *                        SemaphoreHandle_t xSemaphore,
- *                        BaseType_t *pxHigherPriorityTaskWoken
- *                    );
- * 

- *
- * Macro to  release a semaphore.  The semaphore must have previously been
- * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
- *
- * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
- * must not be used with this macro.
- *
- * This macro can be used from an ISR.
- *
- * @param xSemaphore A handle to the semaphore being released.  This is the
- * handle returned when the semaphore was created.
- *
- * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
- *
- * Example usage:
- * 
- \#define LONG_TIME 0xffff
- \#define TICKS_TO_WAIT 10
- * SemaphoreHandle_t xSemaphore = NULL;
- *
- * // Repetitive task.
- * void vATask( void * pvParameters )
- * {
- *  for( ;; )
- *  {
- *      // We want this task to run every 10 ticks of a timer.  The semaphore
- *      // was created before this task was started.
- *
- *      // Block waiting for the semaphore to become available.
- *      if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
- *      {
- *          // It is time to execute.
- *
- *          // ...
- *
- *          // We have finished our task.  Return to the top of the loop where
- *          // we will block on the semaphore until it is time to execute
- *          // again.  Note when using the semaphore for synchronisation with an
- *          // ISR in this manner there is no need to 'give' the semaphore back.
- *      }
- *  }
- * }
- *
- * // Timer ISR
- * void vTimerISR( void * pvParameters )
- * {
- * static uint8_t ucLocalTickCount = 0;
- * static BaseType_t xHigherPriorityTaskWoken;
- *
- *  // A timer tick has occurred.
- *
- *  // ... Do other time functions.
- *
- *  // Is it time for vATask () to run?
- *  xHigherPriorityTaskWoken = pdFALSE;
- *  ucLocalTickCount++;
- *  if( ucLocalTickCount >= TICKS_TO_WAIT )
- *  {
- *      // Unblock the task by releasing the semaphore.
- *      xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
- *
- *      // Reset the count so we release the semaphore again in 10 ticks time.
- *      ucLocalTickCount = 0;
- *  }
- *
- *  if( xHigherPriorityTaskWoken != pdFALSE )
- *  {
- *      // We can force a context switch here.  Context switching from an
- *      // ISR uses port specific syntax.  Check the demo task for your port
- *      // to find the syntax required.
- *  }
- * }
- * 

- * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
- * \ingroup Semaphores
- */
-#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )    xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
-
-/**
- * semphr. h
- * 
- * xSemaphoreTakeFromISR(
- *                        SemaphoreHandle_t xSemaphore,
- *                        BaseType_t *pxHigherPriorityTaskWoken
- *                    );
- * 

- *
- * Macro to  take a semaphore from an ISR.  The semaphore must have
- * previously been created with a call to xSemaphoreCreateBinary() or
- * xSemaphoreCreateCounting().
- *
- * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
- * must not be used with this macro.
- *
- * This macro can be used from an ISR, however taking a semaphore from an ISR
- * is not a common operation.  It is likely to only be useful when taking a
- * counting semaphore when an interrupt is obtaining an object from a resource
- * pool (when the semaphore count indicates the number of resources available).
- *
- * @param xSemaphore A handle to the semaphore being taken.  This is the
- * handle returned when the semaphore was created.
- *
- * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the semaphore was successfully taken, otherwise
- * pdFALSE
- */
-#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )    xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
-
-/**
- * semphr. h
- * 
- * SemaphoreHandle_t xSemaphoreCreateMutex( void );
- * 

- *
- * Creates a new mutex type semaphore instance, and returns a handle by which
- * the new mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, mutex semaphores use a block
- * of memory, in which the mutex structure is stored.  If a mutex is created
- * using xSemaphoreCreateMutex() then the required memory is automatically
- * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
- * https://www.FreeRTOS.org/a00111.html).  If a mutex is created using
- * xSemaphoreCreateMutexStatic() then the application writer must provided the
- * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
- * without using any dynamic memory allocation.
- *
- * Mutexes created using this function can be accessed using the xSemaphoreTake()
- * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
- * xSemaphoreGiveRecursive() macros must not be used.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @return If the mutex was successfully created then a handle to the created
- * semaphore is returned.  If there was not enough heap to allocate the mutex
- * data structures then NULL is returned.
- *
- * Example usage:
- * 
- * SemaphoreHandle_t xSemaphore;
- *
- * void vATask( void * pvParameters )
- * {
- *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
- *  // This is a macro so pass the variable in directly.
- *  xSemaphore = xSemaphoreCreateMutex();
- *
- *  if( xSemaphore != NULL )
- *  {
- *      // The semaphore was created successfully.
- *      // The semaphore can now be used.
- *  }
- * }
- * 

- * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
- * \ingroup Semaphores
- */
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    #define xSemaphoreCreateMutex()    xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
-#endif
-
-/**
- * semphr. h
- * 
- * SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer );
- * 

- *
- * Creates a new mutex type semaphore instance, and returns a handle by which
- * the new mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, mutex semaphores use a block
- * of memory, in which the mutex structure is stored.  If a mutex is created
- * using xSemaphoreCreateMutex() then the required memory is automatically
- * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
- * https://www.FreeRTOS.org/a00111.html).  If a mutex is created using
- * xSemaphoreCreateMutexStatic() then the application writer must provided the
- * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
- * without using any dynamic memory allocation.
- *
- * Mutexes created using this function can be accessed using the xSemaphoreTake()
- * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
- * xSemaphoreGiveRecursive() macros must not be used.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
- * which will be used to hold the mutex's data structure, removing the need for
- * the memory to be allocated dynamically.
- *
- * @return If the mutex was successfully created then a handle to the created
- * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
- *
- * Example usage:
- * 
- * SemaphoreHandle_t xSemaphore;
- * StaticSemaphore_t xMutexBuffer;
- *
- * void vATask( void * pvParameters )
- * {
- *  // A mutex cannot be used before it has been created.  xMutexBuffer is
- *  // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
- *  // attempted.
- *  xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
- *
- *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
- *  // so there is no need to check it.
- * }
- * 

- * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
- * \ingroup Semaphores
- */
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    #define xSemaphoreCreateMutexStatic( pxMutexBuffer )    xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-
-/**
- * semphr. h
- * 
- * SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void );
- * 

- *
- * Creates a new recursive mutex type semaphore instance, and returns a handle
- * by which the new recursive mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, recursive mutexs use a block
- * of memory, in which the mutex structure is stored.  If a recursive mutex is
- * created using xSemaphoreCreateRecursiveMutex() then the required memory is
- * automatically dynamically allocated inside the
- * xSemaphoreCreateRecursiveMutex() function.  (see
- * https://www.FreeRTOS.org/a00111.html).  If a recursive mutex is created using
- * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
- * provide the memory that will get used by the mutex.
- * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
- * be created without using any dynamic memory allocation.
- *
- * Mutexes created using this macro can be accessed using the
- * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
- * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
- * SemaphoreHandle_t.
- *
- * Example usage:
- * 
- * SemaphoreHandle_t xSemaphore;
- *
- * void vATask( void * pvParameters )
- * {
- *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
- *  // This is a macro so pass the variable in directly.
- *  xSemaphore = xSemaphoreCreateRecursiveMutex();
- *
- *  if( xSemaphore != NULL )
- *  {
- *      // The semaphore was created successfully.
- *      // The semaphore can now be used.
- *  }
- * }
- * 

- * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
- * \ingroup Semaphores
- */
-#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
-    #define xSemaphoreCreateRecursiveMutex()    xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
-#endif
-
-/**
- * semphr. h
- * 
- * SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer );
- * 

- *
- * Creates a new recursive mutex type semaphore instance, and returns a handle
- * by which the new recursive mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, recursive mutexs use a block
- * of memory, in which the mutex structure is stored.  If a recursive mutex is
- * created using xSemaphoreCreateRecursiveMutex() then the required memory is
- * automatically dynamically allocated inside the
- * xSemaphoreCreateRecursiveMutex() function.  (see
- * https://www.FreeRTOS.org/a00111.html).  If a recursive mutex is created using
- * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
- * provide the memory that will get used by the mutex.
- * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
- * be created without using any dynamic memory allocation.
- *
- * Mutexes created using this macro can be accessed using the
- * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
- * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
- * which will then be used to hold the recursive mutex's data structure,
- * removing the need for the memory to be allocated dynamically.
- *
- * @return If the recursive mutex was successfully created then a handle to the
- * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
- * returned.
- *
- * Example usage:
- * 
- * SemaphoreHandle_t xSemaphore;
- * StaticSemaphore_t xMutexBuffer;
- *
- * void vATask( void * pvParameters )
- * {
- *  // A recursive semaphore cannot be used before it is created.  Here a
- *  // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
- *  // The address of xMutexBuffer is passed into the function, and will hold
- *  // the mutexes data structures - so no dynamic memory allocation will be
- *  // attempted.
- *  xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
- *
- *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
- *  // so there is no need to check it.
- * }
- * 

- * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
- * \ingroup Semaphores
- */
-#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
-    #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore )    xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * semphr. h
- * 
- * SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount );
- * 

- *
- * Creates a new counting semaphore instance, and returns a handle by which the
- * new counting semaphore can be referenced.
- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a counting semaphore!
- * https://www.FreeRTOS.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, counting semaphores use a
- * block of memory, in which the counting semaphore structure is stored.  If a
- * counting semaphore is created using xSemaphoreCreateCounting() then the
- * required memory is automatically dynamically allocated inside the
- * xSemaphoreCreateCounting() function.  (see
- * https://www.FreeRTOS.org/a00111.html).  If a counting semaphore is created
- * using xSemaphoreCreateCountingStatic() then the application writer can
- * instead optionally provide the memory that will get used by the counting
- * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
- * semaphore to be created without using any dynamic memory allocation.
- *
- * Counting semaphores are typically used for two things:
- *
- * 1) Counting events.
- *
- *    In this usage scenario an event handler will 'give' a semaphore each time
- *    an event occurs (incrementing the semaphore count value), and a handler
- *    task will 'take' a semaphore each time it processes an event
- *    (decrementing the semaphore count value).  The count value is therefore
- *    the difference between the number of events that have occurred and the
- *    number that have been processed.  In this case it is desirable for the
- *    initial count value to be zero.
- *
- * 2) Resource management.
- *
- *    In this usage scenario the count value indicates the number of resources
- *    available.  To obtain control of a resource a task must first obtain a
- *    semaphore - decrementing the semaphore count value.  When the count value
- *    reaches zero there are no free resources.  When a task finishes with the
- *    resource it 'gives' the semaphore back - incrementing the semaphore count
- *    value.  In this case it is desirable for the initial count value to be
- *    equal to the maximum count value, indicating that all resources are free.
- *
- * @param uxMaxCount The maximum count value that can be reached.  When the
- *        semaphore reaches this value it can no longer be 'given'.
- *
- * @param uxInitialCount The count value assigned to the semaphore when it is
- *        created.
- *
- * @return Handle to the created semaphore.  Null if the semaphore could not be
- *         created.
- *
- * Example usage:
- * 
- * SemaphoreHandle_t xSemaphore;
- *
- * void vATask( void * pvParameters )
- * {
- * SemaphoreHandle_t xSemaphore = NULL;
- *
- *  // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
- *  // The max value to which the semaphore can count should be 10, and the
- *  // initial value assigned to the count should be 0.
- *  xSemaphore = xSemaphoreCreateCounting( 10, 0 );
- *
- *  if( xSemaphore != NULL )
- *  {
- *      // The semaphore was created successfully.
- *      // The semaphore can now be used.
- *  }
- * }
- * 

- * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
- * \ingroup Semaphores
- */
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    #define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount )    xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
-#endif
-
-/**
- * semphr. h
- * 
- * SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer );
- * 

- *
- * Creates a new counting semaphore instance, and returns a handle by which the
- * new counting semaphore can be referenced.
- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a counting semaphore!
- * https://www.FreeRTOS.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, counting semaphores use a
- * block of memory, in which the counting semaphore structure is stored.  If a
- * counting semaphore is created using xSemaphoreCreateCounting() then the
- * required memory is automatically dynamically allocated inside the
- * xSemaphoreCreateCounting() function.  (see
- * https://www.FreeRTOS.org/a00111.html).  If a counting semaphore is created
- * using xSemaphoreCreateCountingStatic() then the application writer must
- * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
- * counting semaphore to be created without using any dynamic memory allocation.
- *
- * Counting semaphores are typically used for two things:
- *
- * 1) Counting events.
- *
- *    In this usage scenario an event handler will 'give' a semaphore each time
- *    an event occurs (incrementing the semaphore count value), and a handler
- *    task will 'take' a semaphore each time it processes an event
- *    (decrementing the semaphore count value).  The count value is therefore
- *    the difference between the number of events that have occurred and the
- *    number that have been processed.  In this case it is desirable for the
- *    initial count value to be zero.
- *
- * 2) Resource management.
- *
- *    In this usage scenario the count value indicates the number of resources
- *    available.  To obtain control of a resource a task must first obtain a
- *    semaphore - decrementing the semaphore count value.  When the count value
- *    reaches zero there are no free resources.  When a task finishes with the
- *    resource it 'gives' the semaphore back - incrementing the semaphore count
- *    value.  In this case it is desirable for the initial count value to be
- *    equal to the maximum count value, indicating that all resources are free.
- *
- * @param uxMaxCount The maximum count value that can be reached.  When the
- *        semaphore reaches this value it can no longer be 'given'.
- *
- * @param uxInitialCount The count value assigned to the semaphore when it is
- *        created.
- *
- * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
- * which will then be used to hold the semaphore's data structure, removing the
- * need for the memory to be allocated dynamically.
- *
- * @return If the counting semaphore was successfully created then a handle to
- * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
- * then NULL is returned.
- *
- * Example usage:
- * 
- * SemaphoreHandle_t xSemaphore;
- * StaticSemaphore_t xSemaphoreBuffer;
- *
- * void vATask( void * pvParameters )
- * {
- * SemaphoreHandle_t xSemaphore = NULL;
- *
- *  // Counting semaphore cannot be used before they have been created.  Create
- *  // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
- *  // value to which the semaphore can count is 10, and the initial value
- *  // assigned to the count will be 0.  The address of xSemaphoreBuffer is
- *  // passed in and will be used to hold the semaphore structure, so no dynamic
- *  // memory allocation will be used.
- *  xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
- *
- *  // No memory allocation was attempted so xSemaphore cannot be NULL, so there
- *  // is no need to check its value.
- * }
- * 

- * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
- * \ingroup Semaphores
- */
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    #define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer )    xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * semphr. h
- * 
- * void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );
- * 

- *
- * Delete a semaphore.  This function must be used with care.  For example,
- * do not delete a mutex type semaphore if the mutex is held by a task.
- *
- * @param xSemaphore A handle to the semaphore to be deleted.
- *
- * \defgroup vSemaphoreDelete vSemaphoreDelete
- * \ingroup Semaphores
- */
-#define vSemaphoreDelete( xSemaphore )                   vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
-
-/**
- * semphr.h
- * 
- * TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );
- * 

- *
- * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
- * If xMutex is not a mutex type semaphore, or the mutex is available (not held
- * by a task), return NULL.
- *
- * Note: This is a good way of determining if the calling task is the mutex
- * holder, but not a good way of determining the identity of the mutex holder as
- * the holder may change between the function exiting and the returned value
- * being tested.
- */
-#define xSemaphoreGetMutexHolder( xSemaphore )           xQueueGetMutexHolder( ( xSemaphore ) )
-
-/**
- * semphr.h
- * 
- * TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );
- * 

- *
- * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
- * If xMutex is not a mutex type semaphore, or the mutex is available (not held
- * by a task), return NULL.
- *
- */
-#define xSemaphoreGetMutexHolderFromISR( xSemaphore )    xQueueGetMutexHolderFromISR( ( xSemaphore ) )
-
-/**
- * semphr.h
- * 
- * UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );
- * 

- *
- * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
- * its current count value.  If the semaphore is a binary semaphore then
- * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
- * semaphore is not available.
- *
- */
-#define uxSemaphoreGetCount( xSemaphore )                uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
-
-#endif /* SEMAPHORE_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/stack_macros.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/stack_macros.h
deleted file mode 100644
index 3eabe21..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/stack_macros.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef STACK_MACROS_H
-#define STACK_MACROS_H
-
-/*
- * Call the stack overflow hook function if the stack of the task being swapped
- * out is currently overflowed, or looks like it might have overflowed in the
- * past.
- *
- * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
- * the current stack state only - comparing the current top of stack value to
- * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
- * will also cause the last few stack bytes to be checked to ensure the value
- * to which the bytes were set when the task was created have not been
- * overwritten.  Note this second test does not guarantee that an overflowed
- * stack will always be recognised.
- */
-
-/*-----------------------------------------------------------*/
-
-#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
-
-/* Only the current stack state is to be checked. */
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
-    {                                                                                                 \
-        /* Is the currently saved stack pointer within the stack limit? */                            \
-        if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )                                     \
-        {                                                                                             \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
-        }                                                                                             \
-    }
-
-#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
-/*-----------------------------------------------------------*/
-
-#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
-
-/* Only the current stack state is to be checked. */
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
-    {                                                                                                 \
-                                                                                                      \
-        /* Is the currently saved stack pointer within the stack limit? */                            \
-        if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )                                \
-        {                                                                                             \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
-        }                                                                                             \
-    }
-
-#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
-/*-----------------------------------------------------------*/
-
-#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
-
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
-    {                                                                                                 \
-        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                       \
-        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;                                        \
-                                                                                                      \
-        if( ( pulStack[ 0 ] != ulCheckValue ) ||                                                      \
-            ( pulStack[ 1 ] != ulCheckValue ) ||                                                      \
-            ( pulStack[ 2 ] != ulCheckValue ) ||                                                      \
-            ( pulStack[ 3 ] != ulCheckValue ) )                                                       \
-        {                                                                                             \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
-        }                                                                                             \
-    }
-
-#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
-
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                                                                \
-    {                                                                                                                                     \
-        int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;                                                                  \
-        static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
-                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
-                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
-                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
-                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
-                                                                                                                                          \
-                                                                                                                                          \
-        pcEndOfStack -= sizeof( ucExpectedStackBytes );                                                                                   \
-                                                                                                                                          \
-        /* Has the extremity of the task stack ever been written over? */                                                                 \
-        if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )                     \
-        {                                                                                                                                 \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );                                     \
-        }                                                                                                                                 \
-    }
-
-#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
-/*-----------------------------------------------------------*/
-
-/* Remove stack overflow macro if not being used. */
-#ifndef taskCHECK_FOR_STACK_OVERFLOW
-    #define taskCHECK_FOR_STACK_OVERFLOW()
-#endif
-
-
-
-#endif /* STACK_MACROS_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/stream_buffer.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/stream_buffer.h
deleted file mode 100644
index 282f4db..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/stream_buffer.h
+++ /dev/null
@@ -1,867 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * Stream buffers are used to send a continuous stream of data from one task or
- * interrupt to another.  Their implementation is light weight, making them
- * particularly suited for interrupt to task and core to core communication
- * scenarios.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section section and set the
- * receive block time to 0.
- *
- */
-
-#ifndef STREAM_BUFFER_H
-#define STREAM_BUFFER_H
-
-#ifndef INC_FREERTOS_H
-    #error "include FreeRTOS.h must appear in source files before include stream_buffer.h"
-#endif
-
-/* *INDENT-OFF* */
-#if defined( __cplusplus )
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/**
- * Type by which stream buffers are referenced.  For example, a call to
- * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
- * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
- * etc.
- */
-struct StreamBufferDef_t;
-typedef struct StreamBufferDef_t * StreamBufferHandle_t;
-
-
-/**
- * message_buffer.h
- *
- * 
- * StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
- * 

- *
- * Creates a new stream buffer using dynamically allocated memory.  See
- * xStreamBufferCreateStatic() for a version that uses statically allocated
- * memory (memory that is allocated at compile time).
- *
- * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
- * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
- *
- * @param xBufferSizeBytes The total number of bytes the stream buffer will be
- * able to hold at any one time.
- *
- * @param xTriggerLevelBytes The number of bytes that must be in the stream
- * buffer before a task that is blocked on the stream buffer to wait for data is
- * moved out of the blocked state.  For example, if a task is blocked on a read
- * of an empty stream buffer that has a trigger level of 1 then the task will be
- * unblocked when a single byte is written to the buffer or the task's block
- * time expires.  As another example, if a task is blocked on a read of an empty
- * stream buffer that has a trigger level of 10 then the task will not be
- * unblocked until the stream buffer contains at least 10 bytes or the task's
- * block time expires.  If a reading task's block time expires before the
- * trigger level is reached then the task will still receive however many bytes
- * are actually available.  Setting a trigger level of 0 will result in a
- * trigger level of 1 being used.  It is not valid to specify a trigger level
- * that is greater than the buffer size.
- *
- * @return If NULL is returned, then the stream buffer cannot be created
- * because there is insufficient heap memory available for FreeRTOS to allocate
- * the stream buffer data structures and storage area.  A non-NULL value being
- * returned indicates that the stream buffer has been created successfully -
- * the returned value should be stored as the handle to the created stream
- * buffer.
- *
- * Example use:
- * 
- *
- * void vAFunction( void )
- * {
- * StreamBufferHandle_t xStreamBuffer;
- * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
- *
- *  // Create a stream buffer that can hold 100 bytes.  The memory used to hold
- *  // both the stream buffer structure and the data in the stream buffer is
- *  // allocated dynamically.
- *  xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
- *
- *  if( xStreamBuffer == NULL )
- *  {
- *      // There was not enough heap memory space available to create the
- *      // stream buffer.
- *  }
- *  else
- *  {
- *      // The stream buffer was created successfully and can now be used.
- *  }
- * }
- * 

- * \defgroup xStreamBufferCreate xStreamBufferCreate
- * \ingroup StreamBufferManagement
- */
-#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes )    xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
-
-/**
- * stream_buffer.h
- *
- * 
- * StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
- *                                              size_t xTriggerLevelBytes,
- *                                              uint8_t *pucStreamBufferStorageArea,
- *                                              StaticStreamBuffer_t *pxStaticStreamBuffer );
- * 

- * Creates a new stream buffer using statically allocated memory.  See
- * xStreamBufferCreate() for a version that uses dynamically allocated memory.
- *
- * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
- * xStreamBufferCreateStatic() to be available.
- *
- * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
- * pucStreamBufferStorageArea parameter.
- *
- * @param xTriggerLevelBytes The number of bytes that must be in the stream
- * buffer before a task that is blocked on the stream buffer to wait for data is
- * moved out of the blocked state.  For example, if a task is blocked on a read
- * of an empty stream buffer that has a trigger level of 1 then the task will be
- * unblocked when a single byte is written to the buffer or the task's block
- * time expires.  As another example, if a task is blocked on a read of an empty
- * stream buffer that has a trigger level of 10 then the task will not be
- * unblocked until the stream buffer contains at least 10 bytes or the task's
- * block time expires.  If a reading task's block time expires before the
- * trigger level is reached then the task will still receive however many bytes
- * are actually available.  Setting a trigger level of 0 will result in a
- * trigger level of 1 being used.  It is not valid to specify a trigger level
- * that is greater than the buffer size.
- *
- * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
- * least xBufferSizeBytes + 1 big.  This is the array to which streams are
- * copied when they are written to the stream buffer.
- *
- * @param pxStaticStreamBuffer Must point to a variable of type
- * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
- * structure.
- *
- * @return If the stream buffer is created successfully then a handle to the
- * created stream buffer is returned. If either pucStreamBufferStorageArea or
- * pxStaticstreamBuffer are NULL then NULL is returned.
- *
- * Example use:
- * 
- *
- * // Used to dimension the array used to hold the streams.  The available space
- * // will actually be one less than this, so 999.
- #define STORAGE_SIZE_BYTES 1000
- *
- * // Defines the memory that will actually hold the streams within the stream
- * // buffer.
- * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
- *
- * // The variable used to hold the stream buffer structure.
- * StaticStreamBuffer_t xStreamBufferStruct;
- *
- * void MyFunction( void )
- * {
- * StreamBufferHandle_t xStreamBuffer;
- * const size_t xTriggerLevel = 1;
- *
- *  xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
- *                                             xTriggerLevel,
- *                                             ucBufferStorage,
- *                                             &xStreamBufferStruct );
- *
- *  // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
- *  // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
- *  // reference the created stream buffer in other stream buffer API calls.
- *
- *  // Other code that uses the stream buffer can go here.
- * }
- *
- * 

- * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
- * \ingroup StreamBufferManagement
- */
-#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
-    xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
-
-/**
- * stream_buffer.h
- *
- * 
- * size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- *                        const void *pvTxData,
- *                        size_t xDataLengthBytes,
- *                        TickType_t xTicksToWait );
- * 

- *
- * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
- * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
- * service routine (ISR).
- *
- * @param xStreamBuffer The handle of the stream buffer to which a stream is
- * being sent.
- *
- * @param pvTxData A pointer to the buffer that holds the bytes to be copied
- * into the stream buffer.
- *
- * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
- * into the stream buffer.
- *
- * @param xTicksToWait The maximum amount of time the task should remain in the
- * Blocked state to wait for enough space to become available in the stream
- * buffer, should the stream buffer contain too little space to hold the
- * another xDataLengthBytes bytes.  The block time is specified in tick periods,
- * so the absolute time it represents is dependent on the tick frequency.  The
- * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
- * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
- * cause the task to wait indefinitely (without timing out), provided
- * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
- * before it can write all xDataLengthBytes into the buffer it will still write
- * as many bytes as possible.  A task does not use any CPU time when it is in
- * the blocked state.
- *
- * @return The number of bytes written to the stream buffer.  If a task times
- * out before it can write all xDataLengthBytes into the buffer it will still
- * write as many bytes as possible.
- *
- * Example use:
- * 
- * void vAFunction( StreamBufferHandle_t xStreamBuffer )
- * {
- * size_t xBytesSent;
- * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
- * char *pcStringToSend = "String to send";
- * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
- *
- *  // Send an array to the stream buffer, blocking for a maximum of 100ms to
- *  // wait for enough space to be available in the stream buffer.
- *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
- *
- *  if( xBytesSent != sizeof( ucArrayToSend ) )
- *  {
- *      // The call to xStreamBufferSend() times out before there was enough
- *      // space in the buffer for the data to be written, but it did
- *      // successfully write xBytesSent bytes.
- *  }
- *
- *  // Send the string to the stream buffer.  Return immediately if there is not
- *  // enough space in the buffer.
- *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
- *
- *  if( xBytesSent != strlen( pcStringToSend ) )
- *  {
- *      // The entire string could not be added to the stream buffer because
- *      // there was not enough free space in the buffer, but xBytesSent bytes
- *      // were sent.  Could try again to send the remaining bytes.
- *  }
- * }
- * 

- * \defgroup xStreamBufferSend xStreamBufferSend
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                          const void * pvTxData,
-                          size_t xDataLengthBytes,
-                          TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
- * 
- * size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
- *                               const void *pvTxData,
- *                               size_t xDataLengthBytes,
- *                               BaseType_t *pxHigherPriorityTaskWoken );
- * 

- *
- * Interrupt safe version of the API function that sends a stream of bytes to
- * the stream buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
- * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
- * service routine (ISR).
- *
- * @param xStreamBuffer The handle of the stream buffer to which a stream is
- * being sent.
- *
- * @param pvTxData A pointer to the data that is to be copied into the stream
- * buffer.
- *
- * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
- * into the stream buffer.
- *
- * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
- * have a task blocked on it waiting for data.  Calling
- * xStreamBufferSendFromISR() can make data available, and so cause a task that
- * was waiting for data to leave the Blocked state.  If calling
- * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently executing task (the
- * task that was interrupted), then, internally, xStreamBufferSendFromISR()
- * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
- * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
- * context switch should be performed before the interrupt is exited.  This will
- * ensure that the interrupt returns directly to the highest priority Ready
- * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
- * is passed into the function.  See the example code below for an example.
- *
- * @return The number of bytes actually written to the stream buffer, which will
- * be less than xDataLengthBytes if the stream buffer didn't have enough free
- * space for all the bytes to be written.
- *
- * Example use:
- * 
- * // A stream buffer that has already been created.
- * StreamBufferHandle_t xStreamBuffer;
- *
- * void vAnInterruptServiceRoutine( void )
- * {
- * size_t xBytesSent;
- * char *pcStringToSend = "String to send";
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
- *
- *  // Attempt to send the string to the stream buffer.
- *  xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
- *                                         ( void * ) pcStringToSend,
- *                                         strlen( pcStringToSend ),
- *                                         &xHigherPriorityTaskWoken );
- *
- *  if( xBytesSent != strlen( pcStringToSend ) )
- *  {
- *      // There was not enough free space in the stream buffer for the entire
- *      // string to be written, ut xBytesSent bytes were written.
- *  }
- *
- *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
- *  // xStreamBufferSendFromISR() then a task that has a priority above the
- *  // priority of the currently executing task was unblocked and a context
- *  // switch should be performed to ensure the ISR returns to the unblocked
- *  // task.  In most FreeRTOS ports this is done by simply passing
- *  // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
- *  // variables value, and perform the context switch if necessary.  Check the
- *  // documentation for the port in use for port specific instructions.
- *  taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
- * }
- * 

- * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
-                                 const void * pvTxData,
-                                 size_t xDataLengthBytes,
-                                 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
- * 
- * size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- *                           void *pvRxData,
- *                           size_t xBufferLengthBytes,
- *                           TickType_t xTicksToWait );
- * 

- *
- * Receives bytes from a stream buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
- * xStreamBufferReceiveFromISR() to read from a stream buffer from an
- * interrupt service routine (ISR).
- *
- * @param xStreamBuffer The handle of the stream buffer from which bytes are to
- * be received.
- *
- * @param pvRxData A pointer to the buffer into which the received bytes will be
- * copied.
- *
- * @param xBufferLengthBytes The length of the buffer pointed to by the
- * pvRxData parameter.  This sets the maximum number of bytes to receive in one
- * call.  xStreamBufferReceive will return as many bytes as possible up to a
- * maximum set by xBufferLengthBytes.
- *
- * @param xTicksToWait The maximum amount of time the task should remain in the
- * Blocked state to wait for data to become available if the stream buffer is
- * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
- * zero.  The block time is specified in tick periods, so the absolute time it
- * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
- * be used to convert a time specified in milliseconds into a time specified in
- * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
- * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
- * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
- * Blocked state.
- *
- * @return The number of bytes actually read from the stream buffer, which will
- * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
- * out before xBufferLengthBytes were available.
- *
- * Example use:
- * 
- * void vAFunction( StreamBuffer_t xStreamBuffer )
- * {
- * uint8_t ucRxData[ 20 ];
- * size_t xReceivedBytes;
- * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
- *
- *  // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
- *  // Wait in the Blocked state (so not using any CPU processing time) for a
- *  // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
- *  // available.
- *  xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
- *                                         ( void * ) ucRxData,
- *                                         sizeof( ucRxData ),
- *                                         xBlockTime );
- *
- *  if( xReceivedBytes > 0 )
- *  {
- *      // A ucRxData contains another xRecievedBytes bytes of data, which can
- *      // be processed here....
- *  }
- * }
- * 

- * \defgroup xStreamBufferReceive xStreamBufferReceive
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                             void * pvRxData,
-                             size_t xBufferLengthBytes,
-                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
- * 
- * size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
- *                                  void *pvRxData,
- *                                  size_t xBufferLengthBytes,
- *                                  BaseType_t *pxHigherPriorityTaskWoken );
- * 

- *
- * An interrupt safe version of the API function that receives bytes from a
- * stream buffer.
- *
- * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
- * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
- * interrupt service routine (ISR).
- *
- * @param xStreamBuffer The handle of the stream buffer from which a stream
- * is being received.
- *
- * @param pvRxData A pointer to the buffer into which the received bytes are
- * copied.
- *
- * @param xBufferLengthBytes The length of the buffer pointed to by the
- * pvRxData parameter.  This sets the maximum number of bytes to receive in one
- * call.  xStreamBufferReceive will return as many bytes as possible up to a
- * maximum set by xBufferLengthBytes.
- *
- * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
- * have a task blocked on it waiting for space to become available.  Calling
- * xStreamBufferReceiveFromISR() can make space available, and so cause a task
- * that is waiting for space to leave the Blocked state.  If calling
- * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
- * the unblocked task has a priority higher than the currently executing task
- * (the task that was interrupted), then, internally,
- * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
- * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
- * context switch should be performed before the interrupt is exited.  That will
- * ensure the interrupt returns directly to the highest priority Ready state
- * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
- * passed into the function.  See the code example below for an example.
- *
- * @return The number of bytes read from the stream buffer, if any.
- *
- * Example use:
- * 
- * // A stream buffer that has already been created.
- * StreamBuffer_t xStreamBuffer;
- *
- * void vAnInterruptServiceRoutine( void )
- * {
- * uint8_t ucRxData[ 20 ];
- * size_t xReceivedBytes;
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
- *
- *  // Receive the next stream from the stream buffer.
- *  xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
- *                                                ( void * ) ucRxData,
- *                                                sizeof( ucRxData ),
- *                                                &xHigherPriorityTaskWoken );
- *
- *  if( xReceivedBytes > 0 )
- *  {
- *      // ucRxData contains xReceivedBytes read from the stream buffer.
- *      // Process the stream here....
- *  }
- *
- *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
- *  // xStreamBufferReceiveFromISR() then a task that has a priority above the
- *  // priority of the currently executing task was unblocked and a context
- *  // switch should be performed to ensure the ISR returns to the unblocked
- *  // task.  In most FreeRTOS ports this is done by simply passing
- *  // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
- *  // variables value, and perform the context switch if necessary.  Check the
- *  // documentation for the port in use for port specific instructions.
- *  taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
- * }
- * 

- * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
-                                    void * pvRxData,
-                                    size_t xBufferLengthBytes,
-                                    BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
- * 
- * void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
- * 

- *
- * Deletes a stream buffer that was previously created using a call to
- * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
- * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
- * then the allocated memory is freed.
- *
- * A stream buffer handle must not be used after the stream buffer has been
- * deleted.
- *
- * @param xStreamBuffer The handle of the stream buffer to be deleted.
- *
- * \defgroup vStreamBufferDelete vStreamBufferDelete
- * \ingroup StreamBufferManagement
- */
-void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
- * 
- * BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
- * 

- *
- * Queries a stream buffer to see if it is full.  A stream buffer is full if it
- * does not have any free space, and therefore cannot accept any more data.
- *
- * @param xStreamBuffer The handle of the stream buffer being queried.
- *
- * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
- * pdFALSE is returned.
- *
- * \defgroup xStreamBufferIsFull xStreamBufferIsFull
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
- * 
- * BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
- * 

- *
- * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
- * it does not contain any data.
- *
- * @param xStreamBuffer The handle of the stream buffer being queried.
- *
- * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
- * pdFALSE is returned.
- *
- * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
- * 
- * BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
- * 

- *
- * Resets a stream buffer to its initial, empty, state.  Any data that was in
- * the stream buffer is discarded.  A stream buffer can only be reset if there
- * are no tasks blocked waiting to either send to or receive from the stream
- * buffer.
- *
- * @param xStreamBuffer The handle of the stream buffer being reset.
- *
- * @return If the stream buffer is reset then pdPASS is returned.  If there was
- * a task blocked waiting to send to or read from the stream buffer then the
- * stream buffer is not reset and pdFAIL is returned.
- *
- * \defgroup xStreamBufferReset xStreamBufferReset
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
- * 
- * size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
- * 

- *
- * Queries a stream buffer to see how much free space it contains, which is
- * equal to the amount of data that can be sent to the stream buffer before it
- * is full.
- *
- * @param xStreamBuffer The handle of the stream buffer being queried.
- *
- * @return The number of bytes that can be written to the stream buffer before
- * the stream buffer would be full.
- *
- * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
- * 
- * size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
- * 

- *
- * Queries a stream buffer to see how much data it contains, which is equal to
- * the number of bytes that can be read from the stream buffer before the stream
- * buffer would be empty.
- *
- * @param xStreamBuffer The handle of the stream buffer being queried.
- *
- * @return The number of bytes that can be read from the stream buffer before
- * the stream buffer would be empty.
- *
- * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
- * 
- * BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
- * 

- *
- * A stream buffer's trigger level is the number of bytes that must be in the
- * stream buffer before a task that is blocked on the stream buffer to
- * wait for data is moved out of the blocked state.  For example, if a task is
- * blocked on a read of an empty stream buffer that has a trigger level of 1
- * then the task will be unblocked when a single byte is written to the buffer
- * or the task's block time expires.  As another example, if a task is blocked
- * on a read of an empty stream buffer that has a trigger level of 10 then the
- * task will not be unblocked until the stream buffer contains at least 10 bytes
- * or the task's block time expires.  If a reading task's block time expires
- * before the trigger level is reached then the task will still receive however
- * many bytes are actually available.  Setting a trigger level of 0 will result
- * in a trigger level of 1 being used.  It is not valid to specify a trigger
- * level that is greater than the buffer size.
- *
- * A trigger level is set when the stream buffer is created, and can be modified
- * using xStreamBufferSetTriggerLevel().
- *
- * @param xStreamBuffer The handle of the stream buffer being updated.
- *
- * @param xTriggerLevel The new trigger level for the stream buffer.
- *
- * @return If xTriggerLevel was less than or equal to the stream buffer's length
- * then the trigger level will be updated and pdTRUE is returned.  Otherwise
- * pdFALSE is returned.
- *
- * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                         size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
- * 
- * BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
- * 

- *
- * For advanced users only.
- *
- * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
- * data is sent to a message buffer or stream buffer.  If there was a task that
- * was blocked on the message or stream buffer waiting for data to arrive then
- * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
- * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
- * thing.  It is provided to enable application writers to implement their own
- * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
- *
- * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
- * additional information.
- *
- * @param xStreamBuffer The handle of the stream buffer to which data was
- * written.
- *
- * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
- * initialised to pdFALSE before it is passed into
- * xStreamBufferSendCompletedFromISR().  If calling
- * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
- * and the task has a priority above the priority of the currently running task,
- * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
- * context switch should be performed before exiting the ISR.
- *
- * @return If a task was removed from the Blocked state then pdTRUE is returned.
- * Otherwise pdFALSE is returned.
- *
- * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
-                                              BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
- * 
- * BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
- * 

- *
- * For advanced users only.
- *
- * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
- * data is read out of a message buffer or stream buffer.  If there was a task
- * that was blocked on the message or stream buffer waiting for data to arrive
- * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
- * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
- * does the same thing.  It is provided to enable application writers to
- * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
- * ANY OTHER TIME.
- *
- * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
- * additional information.
- *
- * @param xStreamBuffer The handle of the stream buffer from which data was
- * read.
- *
- * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
- * initialised to pdFALSE before it is passed into
- * xStreamBufferReceiveCompletedFromISR().  If calling
- * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
- * and the task has a priority above the priority of the currently running task,
- * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
- * context switch should be performed before exiting the ISR.
- *
- * @return If a task was removed from the Blocked state then pdTRUE is returned.
- * Otherwise pdFALSE is returned.
- *
- * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
-                                                 BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/* Functions below here are not part of the public API. */
-StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
-                                                 size_t xTriggerLevelBytes,
-                                                 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
-
-StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
-                                                       size_t xTriggerLevelBytes,
-                                                       BaseType_t xIsMessageBuffer,
-                                                       uint8_t * const pucStreamBufferStorageArea,
-                                                       StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
-
-size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-    void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,
-                                             UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
-    UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-    uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-#endif
-
-/* *INDENT-OFF* */
-#if defined( __cplusplus )
-    }
-#endif
-/* *INDENT-ON* */
-
-#endif /* !defined( STREAM_BUFFER_H ) */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/task.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/task.h
deleted file mode 100644
index d89bba0..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/task.h
+++ /dev/null
@@ -1,3075 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * Copyright 2019-2020 MicroEJ Corp. This file has been modified by MicroEJ Corp.
- * 1. Patch for SystemView support
- *
- */
-
-
-#ifndef INC_TASK_H
-#define INC_TASK_H
-
-#ifndef INC_FREERTOS_H
-    #error "include FreeRTOS.h must appear in source files before include task.h"
-#endif
-
-#include "list.h"
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/*-----------------------------------------------------------
-* MACROS AND DEFINITIONS
-*----------------------------------------------------------*/
-
-#define tskKERNEL_VERSION_NUMBER       "V10.4.3 LTS Patch 2"
-#define tskKERNEL_VERSION_MAJOR        10
-#define tskKERNEL_VERSION_MINOR        4
-#define tskKERNEL_VERSION_BUILD        3
-
-/* MPU region parameters passed in ulParameters
- * of MemoryRegion_t struct. */
-#define tskMPU_REGION_READ_ONLY        ( 1UL << 0UL )
-#define tskMPU_REGION_READ_WRITE       ( 1UL << 1UL )
-#define tskMPU_REGION_EXECUTE_NEVER    ( 1UL << 2UL )
-#define tskMPU_REGION_NORMAL_MEMORY    ( 1UL << 3UL )
-#define tskMPU_REGION_DEVICE_MEMORY    ( 1UL << 4UL )
-
-/* The direct to task notification feature used to have only a single notification
- * per task.  Now there is an array of notifications per task that is dimensioned by
- * configTASK_NOTIFICATION_ARRAY_ENTRIES.  For backward compatibility, any use of the
- * original direct to task notification defaults to using the first index in the
- * array. */
-#define tskDEFAULT_INDEX_TO_NOTIFY     ( 0 )
-
-/**
- * task. h
- *
- * Type by which tasks are referenced.  For example, a call to xTaskCreate
- * returns (via a pointer parameter) an TaskHandle_t variable that can then
- * be used as a parameter to vTaskDelete to delete the task.
- *
- * \defgroup TaskHandle_t TaskHandle_t
- * \ingroup Tasks
- */
-struct tskTaskControlBlock;     /* The old naming convention is used to prevent breaking kernel aware debuggers. */
-typedef struct tskTaskControlBlock * TaskHandle_t;
-
-/*
- * Defines the prototype to which the application task hook function must
- * conform.
- */
-typedef BaseType_t (* TaskHookFunction_t)( void * );
-
-/* Task states returned by eTaskGetState. */
-typedef enum
-{
-    eRunning = 0,     /* A task is querying the state of itself, so must be running. */
-    eReady,           /* The task being queried is in a read or pending ready list. */
-    eBlocked,         /* The task being queried is in the Blocked state. */
-    eSuspended,       /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
-    eDeleted,         /* The task being queried has been deleted, but its TCB has not yet been freed. */
-    eInvalid          /* Used as an 'invalid state' value. */
-} eTaskState;
-
-/* Actions that can be performed when vTaskNotify() is called. */
-typedef enum
-{
-    eNoAction = 0,                /* Notify the task without updating its notify value. */
-    eSetBits,                     /* Set bits in the task's notification value. */
-    eIncrement,                   /* Increment the task's notification value. */
-    eSetValueWithOverwrite,       /* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
-    eSetValueWithoutOverwrite     /* Set the task's notification value if the previous value has been read by the task. */
-} eNotifyAction;
-
-/*
- * Used internally only.
- */
-typedef struct xTIME_OUT
-{
-    BaseType_t xOverflowCount;
-    TickType_t xTimeOnEntering;
-} TimeOut_t;
-
-/*
- * Defines the memory ranges allocated to the task when an MPU is used.
- */
-typedef struct xMEMORY_REGION
-{
-    void * pvBaseAddress;
-    uint32_t ulLengthInBytes;
-    uint32_t ulParameters;
-} MemoryRegion_t;
-
-/*
- * Parameters required to create an MPU protected task.
- */
-typedef struct xTASK_PARAMETERS
-{
-    TaskFunction_t pvTaskCode;
-    const char * pcName;     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-    configSTACK_DEPTH_TYPE usStackDepth;
-    void * pvParameters;
-    UBaseType_t uxPriority;
-    StackType_t * puxStackBuffer;
-    MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
-    #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-        StaticTask_t * const pxTaskBuffer;
-    #endif
-} TaskParameters_t;
-
-/* Used with the uxTaskGetSystemState() function to return the state of each task
- * in the system. */
-typedef struct xTASK_STATUS
-{
-    TaskHandle_t xHandle;                            /* The handle of the task to which the rest of the information in the structure relates. */
-    const char * pcTaskName;                         /* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-    UBaseType_t xTaskNumber;                         /* A number unique to the task. */
-    eTaskState eCurrentState;                        /* The state in which the task existed when the structure was populated. */
-    UBaseType_t uxCurrentPriority;                   /* The priority at which the task was running (may be inherited) when the structure was populated. */
-    UBaseType_t uxBasePriority;                      /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
-    uint32_t ulRunTimeCounter;                       /* The total run time allocated to the task so far, as defined by the run time stats clock.  See https://www.FreeRTOS.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
-    StackType_t * pxStackBase;                       /* Points to the lowest address of the task's stack area. */
-    configSTACK_DEPTH_TYPE usStackHighWaterMark;     /* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
-} TaskStatus_t;
-
-/* Possible return values for eTaskConfirmSleepModeStatus(). */
-typedef enum
-{
-    eAbortSleep = 0,           /* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
-    eStandardSleep,            /* Enter a sleep mode that will not last any longer than the expected idle time. */
-    eNoTasksWaitingTimeout     /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
-} eSleepModeStatus;
-
-/**
- * Defines the priority used by the idle task.  This must not be modified.
- *
- * \ingroup TaskUtils
- */
-#define tskIDLE_PRIORITY    ( ( UBaseType_t ) 0U )
-
-/**
- * task. h
- *
- * Macro for forcing a context switch.
- *
- * \defgroup taskYIELD taskYIELD
- * \ingroup SchedulerControl
- */
-#define taskYIELD()                        portYIELD()
-
-/**
- * task. h
- *
- * Macro to mark the start of a critical code region.  Preemptive context
- * switches cannot occur when in a critical region.
- *
- * NOTE: This may alter the stack (depending on the portable implementation)
- * so must be used with care!
- *
- * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
- * \ingroup SchedulerControl
- */
-#define taskENTER_CRITICAL()               portENTER_CRITICAL()
-#define taskENTER_CRITICAL_FROM_ISR()      portSET_INTERRUPT_MASK_FROM_ISR()
-
-/**
- * task. h
- *
- * Macro to mark the end of a critical code region.  Preemptive context
- * switches cannot occur when in a critical region.
- *
- * NOTE: This may alter the stack (depending on the portable implementation)
- * so must be used with care!
- *
- * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
- * \ingroup SchedulerControl
- */
-#define taskEXIT_CRITICAL()                portEXIT_CRITICAL()
-#define taskEXIT_CRITICAL_FROM_ISR( x )    portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
-
-/**
- * task. h
- *
- * Macro to disable all maskable interrupts.
- *
- * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
- * \ingroup SchedulerControl
- */
-#define taskDISABLE_INTERRUPTS()           portDISABLE_INTERRUPTS()
-
-/**
- * task. h
- *
- * Macro to enable microcontroller interrupts.
- *
- * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
- * \ingroup SchedulerControl
- */
-#define taskENABLE_INTERRUPTS()            portENABLE_INTERRUPTS()
-
-/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
- * 0 to generate more optimal code when configASSERT() is defined as the constant
- * is used in assert() statements. */
-#define taskSCHEDULER_SUSPENDED      ( ( BaseType_t ) 0 )
-#define taskSCHEDULER_NOT_STARTED    ( ( BaseType_t ) 1 )
-#define taskSCHEDULER_RUNNING        ( ( BaseType_t ) 2 )
-
-
-/*-----------------------------------------------------------
-* TASK CREATION API
-*----------------------------------------------------------*/
-
-/**
- * task. h
- * 
- * BaseType_t xTaskCreate(
- *                            TaskFunction_t pvTaskCode,
- *                            const char * const pcName,
- *                            configSTACK_DEPTH_TYPE usStackDepth,
- *                            void *pvParameters,
- *                            UBaseType_t uxPriority,
- *                            TaskHandle_t *pvCreatedTask
- *                        );
- * 

- *
- * Create a new task and add it to the list of tasks that are ready to run.
- *
- * Internally, within the FreeRTOS implementation, tasks use two blocks of
- * memory.  The first block is used to hold the task's data structures.  The
- * second block is used by the task as its stack.  If a task is created using
- * xTaskCreate() then both blocks of memory are automatically dynamically
- * allocated inside the xTaskCreate() function.  (see
- * https://www.FreeRTOS.org/a00111.html).  If a task is created using
- * xTaskCreateStatic() then the application writer must provide the required
- * memory.  xTaskCreateStatic() therefore allows a task to be created without
- * using any dynamic memory allocation.
- *
- * See xTaskCreateStatic() for a version that does not use any dynamic memory
- * allocation.
- *
- * xTaskCreate() can only be used to create a task that has unrestricted
- * access to the entire microcontroller memory map.  Systems that include MPU
- * support can alternatively create an MPU constrained task using
- * xTaskCreateRestricted().
- *
- * @param pvTaskCode Pointer to the task entry function.  Tasks
- * must be implemented to never return (i.e. continuous loop).
- *
- * @param pcName A descriptive name for the task.  This is mainly used to
- * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
- * is 16.
- *
- * @param usStackDepth The size of the task stack specified as the number of
- * variables the stack can hold - not the number of bytes.  For example, if
- * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
- * will be allocated for stack storage.
- *
- * @param pvParameters Pointer that will be used as the parameter for the task
- * being created.
- *
- * @param uxPriority The priority at which the task should run.  Systems that
- * include MPU support can optionally create tasks in a privileged (system)
- * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
- * example, to create a privileged task at priority 2 the uxPriority parameter
- * should be set to ( 2 | portPRIVILEGE_BIT ).
- *
- * @param pvCreatedTask Used to pass back a handle by which the created task
- * can be referenced.
- *
- * @return pdPASS if the task was successfully created and added to a ready
- * list, otherwise an error code defined in the file projdefs.h
- *
- * Example usage:
- * 
- * // Task to be created.
- * void vTaskCode( void * pvParameters )
- * {
- *   for( ;; )
- *   {
- *       // Task code goes here.
- *   }
- * }
- *
- * // Function that creates a task.
- * void vOtherFunction( void )
- * {
- * static uint8_t ucParameterToPass;
- * TaskHandle_t xHandle = NULL;
- *
- *   // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
- *   // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
- *   // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
- *   // the new task attempts to access it.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
- *   configASSERT( xHandle );
- *
- *   // Use the handle to delete the task.
- *   if( xHandle != NULL )
- *   {
- *      vTaskDelete( xHandle );
- *   }
- * }
- * 

- * \defgroup xTaskCreate xTaskCreate
- * \ingroup Tasks
- */
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
-                            const char * const pcName,     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                            const configSTACK_DEPTH_TYPE usStackDepth,
-                            void * const pvParameters,
-                            UBaseType_t uxPriority,
-                            TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * task. h
- * 
- * TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
- *                               const char * const pcName,
- *                               uint32_t ulStackDepth,
- *                               void *pvParameters,
- *                               UBaseType_t uxPriority,
- *                               StackType_t *pxStackBuffer,
- *                               StaticTask_t *pxTaskBuffer );
- * 

- *
- * Create a new task and add it to the list of tasks that are ready to run.
- *
- * Internally, within the FreeRTOS implementation, tasks use two blocks of
- * memory.  The first block is used to hold the task's data structures.  The
- * second block is used by the task as its stack.  If a task is created using
- * xTaskCreate() then both blocks of memory are automatically dynamically
- * allocated inside the xTaskCreate() function.  (see
- * https://www.FreeRTOS.org/a00111.html).  If a task is created using
- * xTaskCreateStatic() then the application writer must provide the required
- * memory.  xTaskCreateStatic() therefore allows a task to be created without
- * using any dynamic memory allocation.
- *
- * @param pvTaskCode Pointer to the task entry function.  Tasks
- * must be implemented to never return (i.e. continuous loop).
- *
- * @param pcName A descriptive name for the task.  This is mainly used to
- * facilitate debugging.  The maximum length of the string is defined by
- * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
- *
- * @param ulStackDepth The size of the task stack specified as the number of
- * variables the stack can hold - not the number of bytes.  For example, if
- * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
- * will be allocated for stack storage.
- *
- * @param pvParameters Pointer that will be used as the parameter for the task
- * being created.
- *
- * @param uxPriority The priority at which the task will run.
- *
- * @param pxStackBuffer Must point to a StackType_t array that has at least
- * ulStackDepth indexes - the array will then be used as the task's stack,
- * removing the need for the stack to be allocated dynamically.
- *
- * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
- * then be used to hold the task's data structures, removing the need for the
- * memory to be allocated dynamically.
- *
- * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
- * be created and a handle to the created task is returned.  If either
- * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
- * NULL is returned.
- *
- * Example usage:
- * 
- *
- *  // Dimensions the buffer that the task being created will use as its stack.
- *  // NOTE:  This is the number of words the stack will hold, not the number of
- *  // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
- *  // then 400 bytes (100 * 32-bits) will be allocated.
- #define STACK_SIZE 200
- *
- *  // Structure that will hold the TCB of the task being created.
- *  StaticTask_t xTaskBuffer;
- *
- *  // Buffer that the task being created will use as its stack.  Note this is
- *  // an array of StackType_t variables.  The size of StackType_t is dependent on
- *  // the RTOS port.
- *  StackType_t xStack[ STACK_SIZE ];
- *
- *  // Function that implements the task being created.
- *  void vTaskCode( void * pvParameters )
- *  {
- *      // The parameter value is expected to be 1 as 1 is passed in the
- *      // pvParameters value in the call to xTaskCreateStatic().
- *      configASSERT( ( uint32_t ) pvParameters == 1UL );
- *
- *      for( ;; )
- *      {
- *          // Task code goes here.
- *      }
- *  }
- *
- *  // Function that creates a task.
- *  void vOtherFunction( void )
- *  {
- *      TaskHandle_t xHandle = NULL;
- *
- *      // Create the task without using any dynamic memory allocation.
- *      xHandle = xTaskCreateStatic(
- *                    vTaskCode,       // Function that implements the task.
- *                    "NAME",          // Text name for the task.
- *                    STACK_SIZE,      // Stack size in words, not bytes.
- *                    ( void * ) 1,    // Parameter passed into the task.
- *                    tskIDLE_PRIORITY,// Priority at which the task is created.
- *                    xStack,          // Array to use as the task's stack.
- *                    &xTaskBuffer );  // Variable to hold the task's data structure.
- *
- *      // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
- *      // been created, and xHandle will be the task's handle.  Use the handle
- *      // to suspend the task.
- *      vTaskSuspend( xHandle );
- *  }
- * 

- * \defgroup xTaskCreateStatic xTaskCreateStatic
- * \ingroup Tasks
- */
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
-                                    const char * const pcName,     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                                    const uint32_t ulStackDepth,
-                                    void * const pvParameters,
-                                    UBaseType_t uxPriority,
-                                    StackType_t * const puxStackBuffer,
-                                    StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * task. h
- * 
- * BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
- * 

- *
- * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
- *
- * xTaskCreateRestricted() should only be used in systems that include an MPU
- * implementation.
- *
- * Create a new task and add it to the list of tasks that are ready to run.
- * The function parameters define the memory regions and associated access
- * permissions allocated to the task.
- *
- * See xTaskCreateRestrictedStatic() for a version that does not use any
- * dynamic memory allocation.
- *
- * @param pxTaskDefinition Pointer to a structure that contains a member
- * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
- * documentation) plus an optional stack buffer and the memory region
- * definitions.
- *
- * @param pxCreatedTask Used to pass back a handle by which the created task
- * can be referenced.
- *
- * @return pdPASS if the task was successfully created and added to a ready
- * list, otherwise an error code defined in the file projdefs.h
- *
- * Example usage:
- * 
- * // Create an TaskParameters_t structure that defines the task to be created.
- * static const TaskParameters_t xCheckTaskParameters =
- * {
- *  vATask,     // pvTaskCode - the function that implements the task.
- *  "ATask",    // pcName - just a text name for the task to assist debugging.
- *  100,        // usStackDepth - the stack size DEFINED IN WORDS.
- *  NULL,       // pvParameters - passed into the task function as the function parameters.
- *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
- *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
- *
- *  // xRegions - Allocate up to three separate memory regions for access by
- *  // the task, with appropriate access permissions.  Different processors have
- *  // different memory alignment requirements - refer to the FreeRTOS documentation
- *  // for full information.
- *  {
- *      // Base address                 Length  Parameters
- *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },
- *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },
- *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }
- *  }
- * };
- *
- * int main( void )
- * {
- * TaskHandle_t xHandle;
- *
- *  // Create a task from the const structure defined above.  The task handle
- *  // is requested (the second parameter is not NULL) but in this case just for
- *  // demonstration purposes as its not actually used.
- *  xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
- *
- *  // Start the scheduler.
- *  vTaskStartScheduler();
- *
- *  // Will only get here if there was insufficient memory to create the idle
- *  // and/or timer task.
- *  for( ;; );
- * }
- * 

- * \defgroup xTaskCreateRestricted xTaskCreateRestricted
- * \ingroup Tasks
- */
-#if ( portUSING_MPU_WRAPPERS == 1 )
-    BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
-                                      TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * task. h
- * 
- * BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
- * 

- *
- * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
- *
- * xTaskCreateRestrictedStatic() should only be used in systems that include an
- * MPU implementation.
- *
- * Internally, within the FreeRTOS implementation, tasks use two blocks of
- * memory.  The first block is used to hold the task's data structures.  The
- * second block is used by the task as its stack.  If a task is created using
- * xTaskCreateRestricted() then the stack is provided by the application writer,
- * and the memory used to hold the task's data structure is automatically
- * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
- * is created using xTaskCreateRestrictedStatic() then the application writer
- * must provide the memory used to hold the task's data structures too.
- * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
- * created without using any dynamic memory allocation.
- *
- * @param pxTaskDefinition Pointer to a structure that contains a member
- * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
- * documentation) plus an optional stack buffer and the memory region
- * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
- * contains an additional member, which is used to point to a variable of type
- * StaticTask_t - which is then used to hold the task's data structure.
- *
- * @param pxCreatedTask Used to pass back a handle by which the created task
- * can be referenced.
- *
- * @return pdPASS if the task was successfully created and added to a ready
- * list, otherwise an error code defined in the file projdefs.h
- *
- * Example usage:
- * 
- * // Create an TaskParameters_t structure that defines the task to be created.
- * // The StaticTask_t variable is only included in the structure when
- * // configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
- * // be used to force the variable into the RTOS kernel's privileged data area.
- * static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
- * static const TaskParameters_t xCheckTaskParameters =
- * {
- *  vATask,     // pvTaskCode - the function that implements the task.
- *  "ATask",    // pcName - just a text name for the task to assist debugging.
- *  100,        // usStackDepth - the stack size DEFINED IN WORDS.
- *  NULL,       // pvParameters - passed into the task function as the function parameters.
- *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
- *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
- *
- *  // xRegions - Allocate up to three separate memory regions for access by
- *  // the task, with appropriate access permissions.  Different processors have
- *  // different memory alignment requirements - refer to the FreeRTOS documentation
- *  // for full information.
- *  {
- *      // Base address                 Length  Parameters
- *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },
- *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },
- *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }
- *  }
- *
- *  &xTaskBuffer; // Holds the task's data structure.
- * };
- *
- * int main( void )
- * {
- * TaskHandle_t xHandle;
- *
- *  // Create a task from the const structure defined above.  The task handle
- *  // is requested (the second parameter is not NULL) but in this case just for
- *  // demonstration purposes as its not actually used.
- *  xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
- *
- *  // Start the scheduler.
- *  vTaskStartScheduler();
- *
- *  // Will only get here if there was insufficient memory to create the idle
- *  // and/or timer task.
- *  for( ;; );
- * }
- * 

- * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
- * \ingroup Tasks
- */
-#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-    BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
-                                            TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * task. h
- * 
- * void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
- * 

- *
- * Memory regions are assigned to a restricted task when the task is created by
- * a call to xTaskCreateRestricted().  These regions can be redefined using
- * vTaskAllocateMPURegions().
- *
- * @param xTask The handle of the task being updated.
- *
- * @param xRegions A pointer to an MemoryRegion_t structure that contains the
- * new memory region definitions.
- *
- * Example usage:
- * 
- * // Define an array of MemoryRegion_t structures that configures an MPU region
- * // allowing read/write access for 1024 bytes starting at the beginning of the
- * // ucOneKByte array.  The other two of the maximum 3 definable regions are
- * // unused so set to zero.
- * static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
- * {
- *  // Base address     Length      Parameters
- *  { ucOneKByte,       1024,       portMPU_REGION_READ_WRITE },
- *  { 0,                0,          0 },
- *  { 0,                0,          0 }
- * };
- *
- * void vATask( void *pvParameters )
- * {
- *  // This task was created such that it has access to certain regions of
- *  // memory as defined by the MPU configuration.  At some point it is
- *  // desired that these MPU regions are replaced with that defined in the
- *  // xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
- *  // for this purpose.  NULL is used as the task handle to indicate that this
- *  // function should modify the MPU regions of the calling task.
- *  vTaskAllocateMPURegions( NULL, xAltRegions );
- *
- *  // Now the task can continue its function, but from this point on can only
- *  // access its stack and the ucOneKByte array (unless any other statically
- *  // defined or shared regions have been declared elsewhere).
- * }
- * 

- * \defgroup xTaskCreateRestricted xTaskCreateRestricted
- * \ingroup Tasks
- */
-void vTaskAllocateMPURegions( TaskHandle_t xTask,
-                              const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
- * void vTaskDelete( TaskHandle_t xTask );
- * 

- *
- * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Remove a task from the RTOS real time kernel's management.  The task being
- * deleted will be removed from all ready, blocked, suspended and event lists.
- *
- * NOTE:  The idle task is responsible for freeing the kernel allocated
- * memory from tasks that have been deleted.  It is therefore important that
- * the idle task is not starved of microcontroller processing time if your
- * application makes any calls to vTaskDelete ().  Memory allocated by the
- * task code is not automatically freed, and should be freed before the task
- * is deleted.
- *
- * See the demo application file death.c for sample code that utilises
- * vTaskDelete ().
- *
- * @param xTask The handle of the task to be deleted.  Passing NULL will
- * cause the calling task to be deleted.
- *
- * Example usage:
- * 
- * void vOtherFunction( void )
- * {
- * TaskHandle_t xHandle;
- *
- *   // Create the task, storing the handle.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
- *
- *   // Use the handle to delete the task.
- *   vTaskDelete( xHandle );
- * }
- * 

- * \defgroup vTaskDelete vTaskDelete
- * \ingroup Tasks
- */
-void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------
-* TASK CONTROL API
-*----------------------------------------------------------*/
-
-/**
- * task. h
- * 
- * void vTaskDelay( const TickType_t xTicksToDelay );
- * 

- *
- * Delay a task for a given number of ticks.  The actual time that the
- * task remains blocked depends on the tick rate.  The constant
- * portTICK_PERIOD_MS can be used to calculate real time from the tick
- * rate - with the resolution of one tick period.
- *
- * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- *
- * vTaskDelay() specifies a time at which the task wishes to unblock relative to
- * the time at which vTaskDelay() is called.  For example, specifying a block
- * period of 100 ticks will cause the task to unblock 100 ticks after
- * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
- * of controlling the frequency of a periodic task as the path taken through the
- * code, as well as other task and interrupt activity, will effect the frequency
- * at which vTaskDelay() gets called and therefore the time at which the task
- * next executes.  See xTaskDelayUntil() for an alternative API function designed
- * to facilitate fixed frequency execution.  It does this by specifying an
- * absolute time (rather than a relative time) at which the calling task should
- * unblock.
- *
- * @param xTicksToDelay The amount of time, in tick periods, that
- * the calling task should block.
- *
- * Example usage:
- *
- * void vTaskFunction( void * pvParameters )
- * {
- * // Block for 500ms.
- * const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
- *
- *   for( ;; )
- *   {
- *       // Simply toggle the LED every 500ms, blocking between each toggle.
- *       vToggleLED();
- *       vTaskDelay( xDelay );
- *   }
- * }
- *
- * \defgroup vTaskDelay vTaskDelay
- * \ingroup TaskCtrl
- */
-void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
- * BaseType_t xTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );
- * 

- *
- * INCLUDE_xTaskDelayUntil must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Delay a task until a specified time.  This function can be used by periodic
- * tasks to ensure a constant execution frequency.
- *
- * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
- * cause a task to block for the specified number of ticks from the time vTaskDelay () is
- * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
- * execution frequency as the time between a task starting to execute and that task
- * calling vTaskDelay () may not be fixed [the task may take a different path though the
- * code between calls, or may get interrupted or preempted a different number of times
- * each time it executes].
- *
- * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
- * is called, xTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
- * unblock.
- *
- * The macro pdMS_TO_TICKS() can be used to calculate the number of ticks from a
- * time specified in milliseconds with a resolution of one tick period.
- *
- * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
- * task was last unblocked.  The variable must be initialised with the current time
- * prior to its first use (see the example below).  Following this the variable is
- * automatically updated within xTaskDelayUntil ().
- *
- * @param xTimeIncrement The cycle time period.  The task will be unblocked at
- * time *pxPreviousWakeTime + xTimeIncrement.  Calling xTaskDelayUntil with the
- * same xTimeIncrement parameter value will cause the task to execute with
- * a fixed interface period.
- *
- * @return Value which can be used to check whether the task was actually delayed.
- * Will be pdTRUE if the task way delayed and pdFALSE otherwise.  A task will not
- * be delayed if the next expected wake time is in the past.
- *
- * Example usage:
- * 
- * // Perform an action every 10 ticks.
- * void vTaskFunction( void * pvParameters )
- * {
- * TickType_t xLastWakeTime;
- * const TickType_t xFrequency = 10;
- * BaseType_t xWasDelayed;
- *
- *     // Initialise the xLastWakeTime variable with the current time.
- *     xLastWakeTime = xTaskGetTickCount ();
- *     for( ;; )
- *     {
- *         // Wait for the next cycle.
- *         xWasDelayed = xTaskDelayUntil( &xLastWakeTime, xFrequency );
- *
- *         // Perform action here. xWasDelayed value can be used to determine
- *         // whether a deadline was missed if the code here took too long.
- *     }
- * }
- * 

- * \defgroup xTaskDelayUntil xTaskDelayUntil
- * \ingroup TaskCtrl
- */
-BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                            const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
-
-/*
- * vTaskDelayUntil() is the older version of xTaskDelayUntil() and does not
- * return a value.
- */
-#define vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement )       \
-{                                                                   \
-    ( void ) xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); \
-}
-
-
-/**
- * task. h
- * 
- * BaseType_t xTaskAbortDelay( TaskHandle_t xTask );
- * 

- *
- * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
- * function to be available.
- *
- * A task will enter the Blocked state when it is waiting for an event.  The
- * event it is waiting for can be a temporal event (waiting for a time), such
- * as when vTaskDelay() is called, or an event on an object, such as when
- * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
- * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
- * task will leave the Blocked state, and return from whichever function call
- * placed the task into the Blocked state.
- *
- * There is no 'FromISR' version of this function as an interrupt would need to
- * know which object a task was blocked on in order to know which actions to
- * take.  For example, if the task was blocked on a queue the interrupt handler
- * would then need to know if the queue was locked.
- *
- * @param xTask The handle of the task to remove from the Blocked state.
- *
- * @return If the task referenced by xTask was not in the Blocked state then
- * pdFAIL is returned.  Otherwise pdPASS is returned.
- *
- * \defgroup xTaskAbortDelay xTaskAbortDelay
- * \ingroup TaskCtrl
- */
-BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
- * UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );
- * 

- *
- * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Obtain the priority of any task.
- *
- * @param xTask Handle of the task to be queried.  Passing a NULL
- * handle results in the priority of the calling task being returned.
- *
- * @return The priority of xTask.
- *
- * Example usage:
- * 
- * void vAFunction( void )
- * {
- * TaskHandle_t xHandle;
- *
- *   // Create a task, storing the handle.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
- *
- *   // ...
- *
- *   // Use the handle to obtain the priority of the created task.
- *   // It was created with tskIDLE_PRIORITY, but may have changed
- *   // it itself.
- *   if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
- *   {
- *       // The task has changed it's priority.
- *   }
- *
- *   // ...
- *
- *   // Is our priority higher than the created task?
- *   if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
- *   {
- *       // Our priority (obtained using NULL handle) is higher.
- *   }
- * }
- * 

- * \defgroup uxTaskPriorityGet uxTaskPriorityGet
- * \ingroup TaskCtrl
- */
-UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
- * UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );
- * 

- *
- * A version of uxTaskPriorityGet() that can be used from an ISR.
- */
-UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
- * eTaskState eTaskGetState( TaskHandle_t xTask );
- * 

- *
- * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Obtain the state of any task.  States are encoded by the eTaskState
- * enumerated type.
- *
- * @param xTask Handle of the task to be queried.
- *
- * @return The state of xTask at the time the function was called.  Note the
- * state of the task might change between the function being called, and the
- * functions return value being tested by the calling task.
- */
-eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
- * void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
- * 

- *
- * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
- * available.  See the configuration section for more information.
- *
- * Populates a TaskStatus_t structure with information about a task.
- *
- * @param xTask Handle of the task being queried.  If xTask is NULL then
- * information will be returned about the calling task.
- *
- * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
- * filled with information about the task referenced by the handle passed using
- * the xTask parameter.
- *
- * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
- * the stack high water mark of the task being queried.  Calculating the stack
- * high water mark takes a relatively long time, and can make the system
- * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
- * allow the high water mark checking to be skipped.  The high watermark value
- * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
- * not set to pdFALSE;
- *
- * @param eState The TaskStatus_t structure contains a member to report the
- * state of the task being queried.  Obtaining the task state is not as fast as
- * a simple assignment - so the eState parameter is provided to allow the state
- * information to be omitted from the TaskStatus_t structure.  To obtain state
- * information then set eState to eInvalid - otherwise the value passed in
- * eState will be reported as the task state in the TaskStatus_t structure.
- *
- * Example usage:
- * 
- * void vAFunction( void )
- * {
- * TaskHandle_t xHandle;
- * TaskStatus_t xTaskDetails;
- *
- *  // Obtain the handle of a task from its name.
- *  xHandle = xTaskGetHandle( "Task_Name" );
- *
- *  // Check the handle is not NULL.
- *  configASSERT( xHandle );
- *
- *  // Use the handle to obtain further information about the task.
- *  vTaskGetInfo( xHandle,
- *                &xTaskDetails,
- *                pdTRUE, // Include the high water mark in xTaskDetails.
- *                eInvalid ); // Include the task state in xTaskDetails.
- * }
- * 

- * \defgroup vTaskGetInfo vTaskGetInfo
- * \ingroup TaskCtrl
- */
-void vTaskGetInfo( TaskHandle_t xTask,
-                   TaskStatus_t * pxTaskStatus,
-                   BaseType_t xGetFreeStackSpace,
-                   eTaskState eState ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
- * void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
- * 

- *
- * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Set the priority of any task.
- *
- * A context switch will occur before the function returns if the priority
- * being set is higher than the currently executing task.
- *
- * @param xTask Handle to the task for which the priority is being set.
- * Passing a NULL handle results in the priority of the calling task being set.
- *
- * @param uxNewPriority The priority to which the task will be set.
- *
- * Example usage:
- * 
- * void vAFunction( void )
- * {
- * TaskHandle_t xHandle;
- *
- *   // Create a task, storing the handle.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
- *
- *   // ...
- *
- *   // Use the handle to raise the priority of the created task.
- *   vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
- *
- *   // ...
- *
- *   // Use a NULL handle to raise our priority to the same value.
- *   vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
- * }
- * 

- * \defgroup vTaskPrioritySet vTaskPrioritySet
- * \ingroup TaskCtrl
- */
-void vTaskPrioritySet( TaskHandle_t xTask,
-                       UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
- * void vTaskSuspend( TaskHandle_t xTaskToSuspend );
- * 

- *
- * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Suspend any task.  When suspended a task will never get any microcontroller
- * processing time, no matter what its priority.
- *
- * Calls to vTaskSuspend are not accumulative -
- * i.e. calling vTaskSuspend () twice on the same task still only requires one
- * call to vTaskResume () to ready the suspended task.
- *
- * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
- * handle will cause the calling task to be suspended.
- *
- * Example usage:
- * 
- * void vAFunction( void )
- * {
- * TaskHandle_t xHandle;
- *
- *   // Create a task, storing the handle.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
- *
- *   // ...
- *
- *   // Use the handle to suspend the created task.
- *   vTaskSuspend( xHandle );
- *
- *   // ...
- *
- *   // The created task will not run during this period, unless
- *   // another task calls vTaskResume( xHandle ).
- *
- *   //...
- *
- *
- *   // Suspend ourselves.
- *   vTaskSuspend( NULL );
- *
- *   // We cannot get here unless another task calls vTaskResume
- *   // with our handle as the parameter.
- * }
- * 

- * \defgroup vTaskSuspend vTaskSuspend
- * \ingroup TaskCtrl
- */
-void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
- * void vTaskResume( TaskHandle_t xTaskToResume );
- * 

- *
- * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Resumes a suspended task.
- *
- * A task that has been suspended by one or more calls to vTaskSuspend ()
- * will be made available for running again by a single call to
- * vTaskResume ().
- *
- * @param xTaskToResume Handle to the task being readied.
- *
- * Example usage:
- * 
- * void vAFunction( void )
- * {
- * TaskHandle_t xHandle;
- *
- *   // Create a task, storing the handle.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
- *
- *   // ...
- *
- *   // Use the handle to suspend the created task.
- *   vTaskSuspend( xHandle );
- *
- *   // ...
- *
- *   // The created task will not run during this period, unless
- *   // another task calls vTaskResume( xHandle ).
- *
- *   //...
- *
- *
- *   // Resume the suspended task ourselves.
- *   vTaskResume( xHandle );
- *
- *   // The created task will once again get microcontroller processing
- *   // time in accordance with its priority within the system.
- * }
- * 

- * \defgroup vTaskResume vTaskResume
- * \ingroup TaskCtrl
- */
-void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
- * void xTaskResumeFromISR( TaskHandle_t xTaskToResume );
- * 

- *
- * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
- * available.  See the configuration section for more information.
- *
- * An implementation of vTaskResume() that can be called from within an ISR.
- *
- * A task that has been suspended by one or more calls to vTaskSuspend ()
- * will be made available for running again by a single call to
- * xTaskResumeFromISR ().
- *
- * xTaskResumeFromISR() should not be used to synchronise a task with an
- * interrupt if there is a chance that the interrupt could arrive prior to the
- * task being suspended - as this can lead to interrupts being missed. Use of a
- * semaphore as a synchronisation mechanism would avoid this eventuality.
- *
- * @param xTaskToResume Handle to the task being readied.
- *
- * @return pdTRUE if resuming the task should result in a context switch,
- * otherwise pdFALSE. This is used by the ISR to determine if a context switch
- * may be required following the ISR.
- *
- * \defgroup vTaskResumeFromISR vTaskResumeFromISR
- * \ingroup TaskCtrl
- */
-BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------
-* SCHEDULER CONTROL
-*----------------------------------------------------------*/
-
-/**
- * task. h
- * 
- * void vTaskStartScheduler( void );
- * 

- *
- * Starts the real time kernel tick processing.  After calling the kernel
- * has control over which tasks are executed and when.
- *
- * See the demo application file main.c for an example of creating
- * tasks and starting the kernel.
- *
- * Example usage:
- * 
- * void vAFunction( void )
- * {
- *   // Create at least one task before starting the kernel.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
- *
- *   // Start the real time kernel with preemption.
- *   vTaskStartScheduler ();
- *
- *   // Will not get here unless a task calls vTaskEndScheduler ()
- * }
- * 

- *
- * \defgroup vTaskStartScheduler vTaskStartScheduler
- * \ingroup SchedulerControl
- */
-void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
- * void vTaskEndScheduler( void );
- * 

- *
- * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
- * in place of DOS, implements this function.
- *
- * Stops the real time kernel tick.  All created tasks will be automatically
- * deleted and multitasking (either preemptive or cooperative) will
- * stop.  Execution then resumes from the point where vTaskStartScheduler ()
- * was called, as if vTaskStartScheduler () had just returned.
- *
- * See the demo application file main. c in the demo/PC directory for an
- * example that uses vTaskEndScheduler ().
- *
- * vTaskEndScheduler () requires an exit function to be defined within the
- * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
- * performs hardware specific operations such as stopping the kernel tick.
- *
- * vTaskEndScheduler () will cause all of the resources allocated by the
- * kernel to be freed - but will not free resources allocated by application
- * tasks.
- *
- * Example usage:
- * 
- * void vTaskCode( void * pvParameters )
- * {
- *   for( ;; )
- *   {
- *       // Task code goes here.
- *
- *       // At some point we want to end the real time kernel processing
- *       // so call ...
- *       vTaskEndScheduler ();
- *   }
- * }
- *
- * void vAFunction( void )
- * {
- *   // Create at least one task before starting the kernel.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
- *
- *   // Start the real time kernel with preemption.
- *   vTaskStartScheduler ();
- *
- *   // Will only get here when the vTaskCode () task has called
- *   // vTaskEndScheduler ().  When we get here we are back to single task
- *   // execution.
- * }
- * 

- *
- * \defgroup vTaskEndScheduler vTaskEndScheduler
- * \ingroup SchedulerControl
- */
-void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
- * void vTaskSuspendAll( void );
- * 

- *
- * Suspends the scheduler without disabling interrupts.  Context switches will
- * not occur while the scheduler is suspended.
- *
- * After calling vTaskSuspendAll () the calling task will continue to execute
- * without risk of being swapped out until a call to xTaskResumeAll () has been
- * made.
- *
- * API functions that have the potential to cause a context switch (for example,
- * xTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
- * is suspended.
- *
- * Example usage:
- * 
- * void vTask1( void * pvParameters )
- * {
- *   for( ;; )
- *   {
- *       // Task code goes here.
- *
- *       // ...
- *
- *       // At some point the task wants to perform a long operation during
- *       // which it does not want to get swapped out.  It cannot use
- *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
- *       // operation may cause interrupts to be missed - including the
- *       // ticks.
- *
- *       // Prevent the real time kernel swapping out the task.
- *       vTaskSuspendAll ();
- *
- *       // Perform the operation here.  There is no need to use critical
- *       // sections as we have all the microcontroller processing time.
- *       // During this time interrupts will still operate and the kernel
- *       // tick count will be maintained.
- *
- *       // ...
- *
- *       // The operation is complete.  Restart the kernel.
- *       xTaskResumeAll ();
- *   }
- * }
- * 

- * \defgroup vTaskSuspendAll vTaskSuspendAll
- * \ingroup SchedulerControl
- */
-void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
- * BaseType_t xTaskResumeAll( void );
- * 

- *
- * Resumes scheduler activity after it was suspended by a call to
- * vTaskSuspendAll().
- *
- * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
- * that were previously suspended by a call to vTaskSuspend().
- *
- * @return If resuming the scheduler caused a context switch then pdTRUE is
- *         returned, otherwise pdFALSE is returned.
- *
- * Example usage:
- * 
- * void vTask1( void * pvParameters )
- * {
- *   for( ;; )
- *   {
- *       // Task code goes here.
- *
- *       // ...
- *
- *       // At some point the task wants to perform a long operation during
- *       // which it does not want to get swapped out.  It cannot use
- *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
- *       // operation may cause interrupts to be missed - including the
- *       // ticks.
- *
- *       // Prevent the real time kernel swapping out the task.
- *       vTaskSuspendAll ();
- *
- *       // Perform the operation here.  There is no need to use critical
- *       // sections as we have all the microcontroller processing time.
- *       // During this time interrupts will still operate and the real
- *       // time kernel tick count will be maintained.
- *
- *       // ...
- *
- *       // The operation is complete.  Restart the kernel.  We want to force
- *       // a context switch - but there is no point if resuming the scheduler
- *       // caused a context switch already.
- *       if( !xTaskResumeAll () )
- *       {
- *            taskYIELD ();
- *       }
- *   }
- * }
- * 

- * \defgroup xTaskResumeAll xTaskResumeAll
- * \ingroup SchedulerControl
- */
-BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------
-* TASK UTILITIES
-*----------------------------------------------------------*/
-
-/**
- * task. h
- * 
TickType_t xTaskGetTickCount( void );

- *
- * @return The count of ticks since vTaskStartScheduler was called.
- *
- * \defgroup xTaskGetTickCount xTaskGetTickCount
- * \ingroup TaskUtils
- */
-TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
TickType_t xTaskGetTickCountFromISR( void );

- *
- * @return The count of ticks since vTaskStartScheduler was called.
- *
- * This is a version of xTaskGetTickCount() that is safe to be called from an
- * ISR - provided that TickType_t is the natural word size of the
- * microcontroller being used or interrupt nesting is either not supported or
- * not being used.
- *
- * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
- * \ingroup TaskUtils
- */
-TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
uint16_t uxTaskGetNumberOfTasks( void );

- *
- * @return The number of tasks that the real time kernel is currently managing.
- * This includes all ready, blocked and suspended tasks.  A task that
- * has been deleted but not yet freed by the idle task will also be
- * included in the count.
- *
- * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
- * \ingroup TaskUtils
- */
-UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
char *pcTaskGetName( TaskHandle_t xTaskToQuery );

- *
- * @return The text (human readable) name of the task referenced by the handle
- * xTaskToQuery.  A task can query its own name by either passing in its own
- * handle, or by setting xTaskToQuery to NULL.
- *
- * \defgroup pcTaskGetName pcTaskGetName
- * \ingroup TaskUtils
- */
-char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * task. h
- * 
TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );

- *
- * NOTE:  This function takes a relatively long time to complete and should be
- * used sparingly.
- *
- * @return The handle of the task that has the human readable name pcNameToQuery.
- * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
- * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
- *
- * \defgroup pcTaskGetHandle pcTaskGetHandle
- * \ingroup TaskUtils
- */
-TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION;     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * task.h
- * 
UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );

- *
- * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
- * this function to be available.
- *
- * Returns the high water mark of the stack associated with xTask.  That is,
- * the minimum free stack space there has been (in words, so on a 32 bit machine
- * a value of 1 means 4 bytes) since the task started.  The smaller the returned
- * number the closer the task has come to overflowing its stack.
- *
- * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
- * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
- * user to determine the return type.  It gets around the problem of the value
- * overflowing on 8-bit types without breaking backward compatibility for
- * applications that expect an 8-bit return type.
- *
- * @param xTask Handle of the task associated with the stack to be checked.
- * Set xTask to NULL to check the stack of the calling task.
- *
- * @return The smallest amount of free stack space there has been (in words, so
- * actual spaces on the stack rather than bytes) since the task referenced by
- * xTask was created.
- */
-UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task.h
- * 
configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );

- *
- * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
- * this function to be available.
- *
- * Returns the high water mark of the stack associated with xTask.  That is,
- * the minimum free stack space there has been (in words, so on a 32 bit machine
- * a value of 1 means 4 bytes) since the task started.  The smaller the returned
- * number the closer the task has come to overflowing its stack.
- *
- * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
- * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
- * user to determine the return type.  It gets around the problem of the value
- * overflowing on 8-bit types without breaking backward compatibility for
- * applications that expect an 8-bit return type.
- *
- * @param xTask Handle of the task associated with the stack to be checked.
- * Set xTask to NULL to check the stack of the calling task.
- *
- * @return The smallest amount of free stack space there has been (in words, so
- * actual spaces on the stack rather than bytes) since the task referenced by
- * xTask was created.
- */
-configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task.h
- * 
uint8_t* pxTaskGetStackStart( TaskHandle_t xTask);

- *
- * INCLUDE_pxTaskGetStackStart must be set to 1 in FreeRTOSConfig.h for
- * this function to be available.
- *
- * Returns the start of the stack associated with xTask.  That is,
- * the highest stack memory address on architectures where the stack grows down
- * from high memory, and the lowest memory address on architectures where the
- * stack grows up from low memory.
- *
- * @param xTask Handle of the task associated with the stack returned.
- * Set xTask to NULL to return the stack of the calling task.
- *
- * @return A pointer to the start of the stack.
- */
-uint8_t* pxTaskGetStackStart( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/* When using trace macros it is sometimes necessary to include task.h before
- * FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
- * so the following two prototypes will cause a compilation error.  This can be
- * fixed by simply guarding against the inclusion of these two prototypes unless
- * they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
- * constant. */
-#ifdef configUSE_APPLICATION_TASK_TAG
-    #if configUSE_APPLICATION_TASK_TAG == 1
-
-/**
- * task.h
- * 
- * void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
- * 

- *
- * Sets pxHookFunction to be the task hook function used by the task xTask.
- * Passing xTask as NULL has the effect of setting the calling tasks hook
- * function.
- */
-        void vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                         TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
-
-/**
- * task.h
- * 
- * void xTaskGetApplicationTaskTag( TaskHandle_t xTask );
- * 

- *
- * Returns the pxHookFunction value assigned to the task xTask.  Do not
- * call from an interrupt service routine - call
- * xTaskGetApplicationTaskTagFromISR() instead.
- */
-        TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task.h
- * 
- * void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );
- * 

- *
- * Returns the pxHookFunction value assigned to the task xTask.  Can
- * be called from an interrupt service routine.
- */
-        TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-    #endif /* configUSE_APPLICATION_TASK_TAG ==1 */
-#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
-
-/* Each task contains an array of pointers that is dimensioned by the
- * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
- * kernel does not use the pointers itself, so the application writer can use
- * the pointers for any purpose they wish.  The following two functions are
- * used to set and query a pointer respectively. */
-    void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) PRIVILEGED_FUNCTION;
-    void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) PRIVILEGED_FUNCTION;
-
-#endif
-
-#if ( configCHECK_FOR_STACK_OVERFLOW > 0 )
-
-     /**
-      * task.h
-      * 
void vApplicationStackOverflowHook( TaskHandle_t xTask char *pcTaskName); 

-      *
-      * The application stack overflow hook is called when a stack overflow is detected for a task.
-      *
-      * Details on stack overflow detection can be found here: https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html
-      *
-      * @param xTask the task that just exceeded its stack boundaries.
-      * @param pcTaskName A character string containing the name of the offending task.
-      */
-     void vApplicationStackOverflowHook( TaskHandle_t xTask,
-                                               char * pcTaskName );
-
-#endif
-
-#if  (  configUSE_TICK_HOOK > 0 )
-    /**
-     *  task.h
-     *  
void vApplicationTickHook( void ); 

-     *
-     * This hook function is called in the system tick handler after any OS work is completed.
-     */
-    void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
-
-#endif
-
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    /**
-     * task.h
-     * 
void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) 

-     *
-     * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Task TCB.  This function is required when
-     * configSUPPORT_STATIC_ALLOCATION is set.  For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION
-     *
-     * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer
-     * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for thie idle task
-     * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
-     */
-    void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
-                                               StackType_t ** ppxIdleTaskStackBuffer,
-                                               uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
-#endif
-
-/**
- * task.h
- * 
- * BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
- * 

- *
- * Calls the hook function associated with xTask.  Passing xTask as NULL has
- * the effect of calling the Running tasks (the calling task) hook function.
- *
- * pvParameter is passed to the hook function for the task to interpret as it
- * wants.  The return value is the value returned by the task hook function
- * registered by the user.
- */
-BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
-                                         void * pvParameter ) PRIVILEGED_FUNCTION;
-
-/**
- * xTaskGetIdleTaskHandle() is only available if
- * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
- *
- * Simply returns the handle of the idle task.  It is not valid to call
- * xTaskGetIdleTaskHandle() before the scheduler has been started.
- */
-TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
-
-/**
- * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
- * uxTaskGetSystemState() to be available.
- *
- * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
- * the system.  TaskStatus_t structures contain, among other things, members
- * for the task handle, task name, task priority, task state, and total amount
- * of run time consumed by the task.  See the TaskStatus_t structure
- * definition in this file for the full member list.
- *
- * NOTE:  This function is intended for debugging use only as its use results in
- * the scheduler remaining suspended for an extended period.
- *
- * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
- * The array must contain at least one TaskStatus_t structure for each task
- * that is under the control of the RTOS.  The number of tasks under the control
- * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
- *
- * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
- * parameter.  The size is specified as the number of indexes in the array, or
- * the number of TaskStatus_t structures contained in the array, not by the
- * number of bytes in the array.
- *
- * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
- * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
- * total run time (as defined by the run time stats clock, see
- * https://www.FreeRTOS.org/rtos-run-time-stats.html) since the target booted.
- * pulTotalRunTime can be set to NULL to omit the total run time information.
- *
- * @return The number of TaskStatus_t structures that were populated by
- * uxTaskGetSystemState().  This should equal the number returned by the
- * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
- * in the uxArraySize parameter was too small.
- *
- * Example usage:
- * 
- *  // This example demonstrates how a human readable table of run time stats
- *  // information is generated from raw data provided by uxTaskGetSystemState().
- *  // The human readable table is written to pcWriteBuffer
- *  void vTaskGetRunTimeStats( char *pcWriteBuffer )
- *  {
- *  TaskStatus_t *pxTaskStatusArray;
- *  volatile UBaseType_t uxArraySize, x;
- *  uint32_t ulTotalRunTime, ulStatsAsPercentage;
- *
- *      // Make sure the write buffer does not contain a string.
- * pcWriteBuffer = 0x00;
- *
- *      // Take a snapshot of the number of tasks in case it changes while this
- *      // function is executing.
- *      uxArraySize = uxTaskGetNumberOfTasks();
- *
- *      // Allocate a TaskStatus_t structure for each task.  An array could be
- *      // allocated statically at compile time.
- *      pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
- *
- *      if( pxTaskStatusArray != NULL )
- *      {
- *          // Generate raw status information about each task.
- *          uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
- *
- *          // For percentage calculations.
- *          ulTotalRunTime /= 100UL;
- *
- *          // Avoid divide by zero errors.
- *          if( ulTotalRunTime > 0 )
- *          {
- *              // For each populated position in the pxTaskStatusArray array,
- *              // format the raw data as human readable ASCII data
- *              for( x = 0; x < uxArraySize; x++ )
- *              {
- *                  // What percentage of the total run time has the task used?
- *                  // This will always be rounded down to the nearest integer.
- *                  // ulTotalRunTimeDiv100 has already been divided by 100.
- *                  ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
- *
- *                  if( ulStatsAsPercentage > 0UL )
- *                  {
- *                      sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
- *                  }
- *                  else
- *                  {
- *                      // If the percentage is zero here then the task has
- *                      // consumed less than 1% of the total run time.
- *                      sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
- *                  }
- *
- *                  pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
- *              }
- *          }
- *
- *          // The array is no longer needed, free the memory it consumes.
- *          vPortFree( pxTaskStatusArray );
- *      }
- *  }
- *  

- */
-UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                  const UBaseType_t uxArraySize,
-                                  uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskList( char *pcWriteBuffer );

- *
- * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
- * both be defined as 1 for this function to be available.  See the
- * configuration section of the FreeRTOS.org website for more information.
- *
- * NOTE 1: This function will disable interrupts for its duration.  It is
- * not intended for normal application runtime use but as a debug aid.
- *
- * Lists all the current tasks, along with their current state and stack
- * usage high water mark.
- *
- * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
- * suspended ('S').
- *
- * PLEASE NOTE:
- *
- * This function is provided for convenience only, and is used by many of the
- * demo applications.  Do not consider it to be part of the scheduler.
- *
- * vTaskList() calls uxTaskGetSystemState(), then formats part of the
- * uxTaskGetSystemState() output into a human readable table that displays task
- * names, states and stack usage.
- *
- * vTaskList() has a dependency on the sprintf() C library function that might
- * bloat the code size, use a lot of stack, and provide different results on
- * different platforms.  An alternative, tiny, third party, and limited
- * functionality implementation of sprintf() is provided in many of the
- * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
- * printf-stdarg.c does not provide a full snprintf() implementation!).
- *
- * It is recommended that production systems call uxTaskGetSystemState()
- * directly to get access to raw stats data, rather than indirectly through a
- * call to vTaskList().
- *
- * @param pcWriteBuffer A buffer into which the above mentioned details
- * will be written, in ASCII form.  This buffer is assumed to be large
- * enough to contain the generated report.  Approximately 40 bytes per
- * task should be sufficient.
- *
- * \defgroup vTaskList vTaskList
- * \ingroup TaskUtils
- */
-void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION;     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * task. h
- * 
void vTaskGetRunTimeStats( char *pcWriteBuffer );

- *
- * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
- * must both be defined as 1 for this function to be available.  The application
- * must also then provide definitions for
- * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
- * to configure a peripheral timer/counter and return the timers current count
- * value respectively.  The counter should be at least 10 times the frequency of
- * the tick count.
- *
- * NOTE 1: This function will disable interrupts for its duration.  It is
- * not intended for normal application runtime use but as a debug aid.
- *
- * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
- * accumulated execution time being stored for each task.  The resolution
- * of the accumulated time value depends on the frequency of the timer
- * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
- * Calling vTaskGetRunTimeStats() writes the total execution time of each
- * task into a buffer, both as an absolute count value and as a percentage
- * of the total system execution time.
- *
- * NOTE 2:
- *
- * This function is provided for convenience only, and is used by many of the
- * demo applications.  Do not consider it to be part of the scheduler.
- *
- * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
- * uxTaskGetSystemState() output into a human readable table that displays the
- * amount of time each task has spent in the Running state in both absolute and
- * percentage terms.
- *
- * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
- * that might bloat the code size, use a lot of stack, and provide different
- * results on different platforms.  An alternative, tiny, third party, and
- * limited functionality implementation of sprintf() is provided in many of the
- * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
- * printf-stdarg.c does not provide a full snprintf() implementation!).
- *
- * It is recommended that production systems call uxTaskGetSystemState() directly
- * to get access to raw stats data, rather than indirectly through a call to
- * vTaskGetRunTimeStats().
- *
- * @param pcWriteBuffer A buffer into which the execution times will be
- * written, in ASCII form.  This buffer is assumed to be large enough to
- * contain the generated report.  Approximately 40 bytes per task should
- * be sufficient.
- *
- * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
- * \ingroup TaskUtils
- */
-void vTaskGetRunTimeStats( char * pcWriteBuffer ) PRIVILEGED_FUNCTION;     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * task. h
- * 
uint32_t ulTaskGetIdleRunTimeCounter( void );

- *
- * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
- * must both be defined as 1 for this function to be available.  The application
- * must also then provide definitions for
- * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
- * to configure a peripheral timer/counter and return the timers current count
- * value respectively.  The counter should be at least 10 times the frequency of
- * the tick count.
- *
- * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
- * accumulated execution time being stored for each task.  The resolution
- * of the accumulated time value depends on the frequency of the timer
- * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
- * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
- * execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter()
- * returns the total execution time of just the idle task.
- *
- * @return The total run time of the idle task.  This is the amount of time the
- * idle task has actually been executing.  The unit of time is dependent on the
- * frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
- * portGET_RUN_TIME_COUNTER_VALUE() macros.
- *
- * \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
- * \ingroup TaskUtils
- */
-uint32_t ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
BaseType_t xTaskNotifyIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction );

- * 
BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );

- *
- * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
- * functions to be available.
- *
- * Sends a direct to task notification to a task, with an optional value and
- * action.
- *
- * Each task has a private array of "notification values" (or 'notifications'),
- * each of which is a 32-bit unsigned integer (uint32_t).  The constant
- * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
- * array, and (for backward compatibility) defaults to 1 if left undefined.
- * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment one of the task's notification values.  In
- * that way task notifications can be used to send data to a task, or be used as
- * light weight and fast binary or counting semaphores.
- *
- * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a
- * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block
- * to wait for a notification value to have a non-zero value.  The task does
- * not consume any CPU time while it is in the Blocked state.
- *
- * A notification sent to a task will remain pending until it is cleared by the
- * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their
- * un-indexed equivalents).  If the task was already in the Blocked state to
- * wait for a notification when the notification arrives then the task will
- * automatically be removed from the Blocked state (unblocked) and the
- * notification cleared.
- *
- * **NOTE** Each notification within the array operates independently - a task
- * can only block on one notification within the array at a time and will not be
- * unblocked by a notification sent to any other array index.
- *
- * Backward compatibility information:
- * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
- * all task notification API functions operated on that value. Replacing the
- * single notification value with an array of notification values necessitated a
- * new set of API functions that could address specific notifications within the
- * array.  xTaskNotify() is the original API function, and remains backward
- * compatible by always operating on the notification value at index 0 in the
- * array. Calling xTaskNotify() is equivalent to calling xTaskNotifyIndexed()
- * with the uxIndexToNotify parameter set to 0.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @param uxIndexToNotify The index within the target task's array of
- * notification values to which the notification is to be sent.  uxIndexToNotify
- * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotify() does
- * not have this parameter and always sends notifications to index 0.
- *
- * @param ulValue Data that can be sent with the notification.  How the data is
- * used depends on the value of the eAction parameter.
- *
- * @param eAction Specifies how the notification updates the task's notification
- * value, if at all.  Valid values for eAction are as follows:
- *
- * eSetBits -
- * The target notification value is bitwise ORed with ulValue.
- * xTaskNofifyIndexed() always returns pdPASS in this case.
- *
- * eIncrement -
- * The target notification value is incremented.  ulValue is not used and
- * xTaskNotifyIndexed() always returns pdPASS in this case.
- *
- * eSetValueWithOverwrite -
- * The target notification value is set to the value of ulValue, even if the
- * task being notified had not yet processed the previous notification at the
- * same array index (the task already had a notification pending at that index).
- * xTaskNotifyIndexed() always returns pdPASS in this case.
- *
- * eSetValueWithoutOverwrite -
- * If the task being notified did not already have a notification pending at the
- * same array index then the target notification value is set to ulValue and
- * xTaskNotifyIndexed() will return pdPASS.  If the task being notified already
- * had a notification pending at the same array index then no action is
- * performed and pdFAIL is returned.
- *
- * eNoAction -
- * The task receives a notification at the specified array index without the
- * notification value at that index being updated.  ulValue is not used and
- * xTaskNotifyIndexed() always returns pdPASS in this case.
- *
- * pulPreviousNotificationValue -
- * Can be used to pass out the subject task's notification value before any
- * bits are modified by the notify function.
- *
- * @return Dependent on the value of eAction.  See the description of the
- * eAction parameter.
- *
- * \defgroup xTaskNotifyIndexed xTaskNotifyIndexed
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                               UBaseType_t uxIndexToNotify,
-                               uint32_t ulValue,
-                               eNotifyAction eAction,
-                               uint32_t * pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
-#define xTaskNotify( xTaskToNotify, ulValue, eAction ) \
-    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL )
-#define xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction ) \
-    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL )
-
-/**
- * task. h
- * 
BaseType_t xTaskNotifyAndQueryIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );

- * 
BaseType_t xTaskNotifyAndQuery( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );

- *
- * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * xTaskNotifyAndQueryIndexed() performs the same operation as
- * xTaskNotifyIndexed() with the addition that it also returns the subject
- * task's prior notification value (the notification value at the time the
- * function is called rather than when the function returns) in the additional
- * pulPreviousNotifyValue parameter.
- *
- * xTaskNotifyAndQuery() performs the same operation as xTaskNotify() with the
- * addition that it also returns the subject task's prior notification value
- * (the notification value as it was at the time the function is called, rather
- * than when the function returns) in the additional pulPreviousNotifyValue
- * parameter.
- *
- * \defgroup xTaskNotifyAndQueryIndexed xTaskNotifyAndQueryIndexed
- * \ingroup TaskNotifications
- */
-#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) \
-    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
-#define xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotifyValue ) \
-    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
-
-/**
- * task. h
- * 
BaseType_t xTaskNotifyIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );

- * 
BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );

- *
- * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
- * functions to be available.
- *
- * A version of xTaskNotifyIndexed() that can be used from an interrupt service
- * routine (ISR).
- *
- * Each task has a private array of "notification values" (or 'notifications'),
- * each of which is a 32-bit unsigned integer (uint32_t).  The constant
- * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
- * array, and (for backward compatibility) defaults to 1 if left undefined.
- * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment one of the task's notification values.  In
- * that way task notifications can be used to send data to a task, or be used as
- * light weight and fast binary or counting semaphores.
- *
- * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a
- * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block
- * to wait for a notification value to have a non-zero value.  The task does
- * not consume any CPU time while it is in the Blocked state.
- *
- * A notification sent to a task will remain pending until it is cleared by the
- * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their
- * un-indexed equivalents).  If the task was already in the Blocked state to
- * wait for a notification when the notification arrives then the task will
- * automatically be removed from the Blocked state (unblocked) and the
- * notification cleared.
- *
- * **NOTE** Each notification within the array operates independently - a task
- * can only block on one notification within the array at a time and will not be
- * unblocked by a notification sent to any other array index.
- *
- * Backward compatibility information:
- * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
- * all task notification API functions operated on that value. Replacing the
- * single notification value with an array of notification values necessitated a
- * new set of API functions that could address specific notifications within the
- * array.  xTaskNotifyFromISR() is the original API function, and remains
- * backward compatible by always operating on the notification value at index 0
- * within the array. Calling xTaskNotifyFromISR() is equivalent to calling
- * xTaskNotifyIndexedFromISR() with the uxIndexToNotify parameter set to 0.
- *
- * @param uxIndexToNotify The index within the target task's array of
- * notification values to which the notification is to be sent.  uxIndexToNotify
- * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyFromISR()
- * does not have this parameter and always sends notifications to index 0.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @param ulValue Data that can be sent with the notification.  How the data is
- * used depends on the value of the eAction parameter.
- *
- * @param eAction Specifies how the notification updates the task's notification
- * value, if at all.  Valid values for eAction are as follows:
- *
- * eSetBits -
- * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
- * always returns pdPASS in this case.
- *
- * eIncrement -
- * The task's notification value is incremented.  ulValue is not used and
- * xTaskNotify() always returns pdPASS in this case.
- *
- * eSetValueWithOverwrite -
- * The task's notification value is set to the value of ulValue, even if the
- * task being notified had not yet processed the previous notification (the
- * task already had a notification pending).  xTaskNotify() always returns
- * pdPASS in this case.
- *
- * eSetValueWithoutOverwrite -
- * If the task being notified did not already have a notification pending then
- * the task's notification value is set to ulValue and xTaskNotify() will
- * return pdPASS.  If the task being notified already had a notification
- * pending then no action is performed and pdFAIL is returned.
- *
- * eNoAction -
- * The task receives a notification without its notification value being
- * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
- * this case.
- *
- * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
- * task to which the notification was sent to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently running task.  If
- * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
- * be requested before the interrupt is exited.  How a context switch is
- * requested from an ISR is dependent on the port - see the documentation page
- * for the port in use.
- *
- * @return Dependent on the value of eAction.  See the description of the
- * eAction parameter.
- *
- * \defgroup xTaskNotifyIndexedFromISR xTaskNotifyIndexedFromISR
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
-                                      UBaseType_t uxIndexToNotify,
-                                      uint32_t ulValue,
-                                      eNotifyAction eAction,
-                                      uint32_t * pulPreviousNotificationValue,
-                                      BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \
-    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
-#define xTaskNotifyIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \
-    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
-
-/**
- * task. h
- * 
BaseType_t xTaskNotifyAndQueryIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );

- * 
BaseType_t xTaskNotifyAndQueryFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );

- *
- * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * xTaskNotifyAndQueryIndexedFromISR() performs the same operation as
- * xTaskNotifyIndexedFromISR() with the addition that it also returns the
- * subject task's prior notification value (the notification value at the time
- * the function is called rather than at the time the function returns) in the
- * additional pulPreviousNotifyValue parameter.
- *
- * xTaskNotifyAndQueryFromISR() performs the same operation as
- * xTaskNotifyFromISR() with the addition that it also returns the subject
- * task's prior notification value (the notification value at the time the
- * function is called rather than at the time the function returns) in the
- * additional pulPreviousNotifyValue parameter.
- *
- * \defgroup xTaskNotifyAndQueryIndexedFromISR xTaskNotifyAndQueryIndexedFromISR
- * \ingroup TaskNotifications
- */
-#define xTaskNotifyAndQueryIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \
-    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
-#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \
-    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
-
-/**
- * task. h
- * 
- * BaseType_t xTaskNotifyWaitIndexed( UBaseType_t uxIndexToWaitOn, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
- *
- * BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
- * 

- *
- * Waits for a direct to task notification to be pending at a given index within
- * an array of direct to task notifications.
- *
- * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * Each task has a private array of "notification values" (or 'notifications'),
- * each of which is a 32-bit unsigned integer (uint32_t).  The constant
- * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
- * array, and (for backward compatibility) defaults to 1 if left undefined.
- * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment one of the task's notification values.  In
- * that way task notifications can be used to send data to a task, or be used as
- * light weight and fast binary or counting semaphores.
- *
- * A notification sent to a task will remain pending until it is cleared by the
- * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their
- * un-indexed equivalents).  If the task was already in the Blocked state to
- * wait for a notification when the notification arrives then the task will
- * automatically be removed from the Blocked state (unblocked) and the
- * notification cleared.
- *
- * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a
- * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block
- * to wait for a notification value to have a non-zero value.  The task does
- * not consume any CPU time while it is in the Blocked state.
- *
- * **NOTE** Each notification within the array operates independently - a task
- * can only block on one notification within the array at a time and will not be
- * unblocked by a notification sent to any other array index.
- *
- * Backward compatibility information:
- * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
- * all task notification API functions operated on that value. Replacing the
- * single notification value with an array of notification values necessitated a
- * new set of API functions that could address specific notifications within the
- * array.  xTaskNotifyWait() is the original API function, and remains backward
- * compatible by always operating on the notification value at index 0 in the
- * array. Calling xTaskNotifyWait() is equivalent to calling
- * xTaskNotifyWaitIndexed() with the uxIndexToWaitOn parameter set to 0.
- *
- * @param uxIndexToWaitOn The index within the calling task's array of
- * notification values on which the calling task will wait for a notification to
- * be received.  uxIndexToWaitOn must be less than
- * configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyWait() does
- * not have this parameter and always waits for notifications on index 0.
- *
- * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
- * will be cleared in the calling task's notification value before the task
- * checks to see if any notifications are pending, and optionally blocks if no
- * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
- * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
- * the effect of resetting the task's notification value to 0.  Setting
- * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
- *
- * @param ulBitsToClearOnExit If a notification is pending or received before
- * the calling task exits the xTaskNotifyWait() function then the task's
- * notification value (see the xTaskNotify() API function) is passed out using
- * the pulNotificationValue parameter.  Then any bits that are set in
- * ulBitsToClearOnExit will be cleared in the task's notification value (note
- * *pulNotificationValue is set before any bits are cleared).  Setting
- * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
- * (if limits.h is not included) will have the effect of resetting the task's
- * notification value to 0 before the function exits.  Setting
- * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
- * when the function exits (in which case the value passed out in
- * pulNotificationValue will match the task's notification value).
- *
- * @param pulNotificationValue Used to pass the task's notification value out
- * of the function.  Note the value passed out will not be effected by the
- * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
- *
- * @param xTicksToWait The maximum amount of time that the task should wait in
- * the Blocked state for a notification to be received, should a notification
- * not already be pending when xTaskNotifyWait() was called.  The task
- * will not consume any processing time while it is in the Blocked state.  This
- * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
- * used to convert a time specified in milliseconds to a time specified in
- * ticks.
- *
- * @return If a notification was received (including notifications that were
- * already pending when xTaskNotifyWait was called) then pdPASS is
- * returned.  Otherwise pdFAIL is returned.
- *
- * \defgroup xTaskNotifyWaitIndexed xTaskNotifyWaitIndexed
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                   uint32_t ulBitsToClearOnEntry,
-                                   uint32_t ulBitsToClearOnExit,
-                                   uint32_t * pulNotificationValue,
-                                   TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-#define xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \
-    xTaskGenericNotifyWait( tskDEFAULT_INDEX_TO_NOTIFY, ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )
-#define xTaskNotifyWaitIndexed( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \
-    xTaskGenericNotifyWait( ( uxIndexToWaitOn ), ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )
-
-/**
- * task. h
- * 
BaseType_t xTaskNotifyGiveIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify );

- * 
BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );

- *
- * Sends a direct to task notification to a particular index in the target
- * task's notification array in a manner similar to giving a counting semaphore.
- *
- * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
- * macros to be available.
- *
- * Each task has a private array of "notification values" (or 'notifications'),
- * each of which is a 32-bit unsigned integer (uint32_t).  The constant
- * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
- * array, and (for backward compatibility) defaults to 1 if left undefined.
- * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment one of the task's notification values.  In
- * that way task notifications can be used to send data to a task, or be used as
- * light weight and fast binary or counting semaphores.
- *
- * xTaskNotifyGiveIndexed() is a helper macro intended for use when task
- * notifications are used as light weight and faster binary or counting
- * semaphore equivalents.  Actual FreeRTOS semaphores are given using the
- * xSemaphoreGive() API function, the equivalent action that instead uses a task
- * notification is xTaskNotifyGiveIndexed().
- *
- * When task notifications are being used as a binary or counting semaphore
- * equivalent then the task being notified should wait for the notification
- * using the ulTaskNotificationTakeIndexed() API function rather than the
- * xTaskNotifyWaitIndexed() API function.
- *
- * **NOTE** Each notification within the array operates independently - a task
- * can only block on one notification within the array at a time and will not be
- * unblocked by a notification sent to any other array index.
- *
- * Backward compatibility information:
- * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
- * all task notification API functions operated on that value. Replacing the
- * single notification value with an array of notification values necessitated a
- * new set of API functions that could address specific notifications within the
- * array.  xTaskNotifyGive() is the original API function, and remains backward
- * compatible by always operating on the notification value at index 0 in the
- * array. Calling xTaskNotifyGive() is equivalent to calling
- * xTaskNotifyGiveIndexed() with the uxIndexToNotify parameter set to 0.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @param uxIndexToNotify The index within the target task's array of
- * notification values to which the notification is to be sent.  uxIndexToNotify
- * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyGive()
- * does not have this parameter and always sends notifications to index 0.
- *
- * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
- * eAction parameter set to eIncrement - so pdPASS is always returned.
- *
- * \defgroup xTaskNotifyGiveIndexed xTaskNotifyGiveIndexed
- * \ingroup TaskNotifications
- */
-#define xTaskNotifyGive( xTaskToNotify ) \
-    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( 0 ), eIncrement, NULL )
-#define xTaskNotifyGiveIndexed( xTaskToNotify, uxIndexToNotify ) \
-    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( 0 ), eIncrement, NULL )
-
-/**
- * task. h
- * 
void vTaskNotifyGiveIndexedFromISR( TaskHandle_t xTaskHandle, UBaseType_t uxIndexToNotify, BaseType_t *pxHigherPriorityTaskWoken );

- * 
void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );

- *
- * A version of xTaskNotifyGiveIndexed() that can be called from an interrupt
- * service routine (ISR).
- *
- * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
- * to be available.
- *
- * Each task has a private array of "notification values" (or 'notifications'),
- * each of which is a 32-bit unsigned integer (uint32_t).  The constant
- * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
- * array, and (for backward compatibility) defaults to 1 if left undefined.
- * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment one of the task's notification values.  In
- * that way task notifications can be used to send data to a task, or be used as
- * light weight and fast binary or counting semaphores.
- *
- * vTaskNotifyGiveIndexedFromISR() is intended for use when task notifications
- * are used as light weight and faster binary or counting semaphore equivalents.
- * Actual FreeRTOS semaphores are given from an ISR using the
- * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
- * a task notification is vTaskNotifyGiveIndexedFromISR().
- *
- * When task notifications are being used as a binary or counting semaphore
- * equivalent then the task being notified should wait for the notification
- * using the ulTaskNotificationTakeIndexed() API function rather than the
- * xTaskNotifyWaitIndexed() API function.
- *
- * **NOTE** Each notification within the array operates independently - a task
- * can only block on one notification within the array at a time and will not be
- * unblocked by a notification sent to any other array index.
- *
- * Backward compatibility information:
- * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
- * all task notification API functions operated on that value. Replacing the
- * single notification value with an array of notification values necessitated a
- * new set of API functions that could address specific notifications within the
- * array.  xTaskNotifyFromISR() is the original API function, and remains
- * backward compatible by always operating on the notification value at index 0
- * within the array. Calling xTaskNotifyGiveFromISR() is equivalent to calling
- * xTaskNotifyGiveIndexedFromISR() with the uxIndexToNotify parameter set to 0.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @param uxIndexToNotify The index within the target task's array of
- * notification values to which the notification is to be sent.  uxIndexToNotify
- * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.
- * xTaskNotifyGiveFromISR() does not have this parameter and always sends
- * notifications to index 0.
- *
- * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
- * task to which the notification was sent to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently running task.  If
- * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
- * should be requested before the interrupt is exited.  How a context switch is
- * requested from an ISR is dependent on the port - see the documentation page
- * for the port in use.
- *
- * \defgroup vTaskNotifyGiveIndexedFromISR vTaskNotifyGiveIndexedFromISR
- * \ingroup TaskNotifications
- */
-void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,
-                                    UBaseType_t uxIndexToNotify,
-                                    BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-#define vTaskNotifyGiveFromISR( xTaskToNotify, pxHigherPriorityTaskWoken ) \
-    vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) );
-#define vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ) \
-    vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) );
-
-/**
- * task. h
- * 
- * uint32_t ulTaskNotifyTakeIndexed( UBaseType_t uxIndexToWaitOn, BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
- *
- * uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
- * 

- *
- * Waits for a direct to task notification on a particular index in the calling
- * task's notification array in a manner similar to taking a counting semaphore.
- *
- * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * Each task has a private array of "notification values" (or 'notifications'),
- * each of which is a 32-bit unsigned integer (uint32_t).  The constant
- * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
- * array, and (for backward compatibility) defaults to 1 if left undefined.
- * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment one of the task's notification values.  In
- * that way task notifications can be used to send data to a task, or be used as
- * light weight and fast binary or counting semaphores.
- *
- * ulTaskNotifyTakeIndexed() is intended for use when a task notification is
- * used as a faster and lighter weight binary or counting semaphore alternative.
- * Actual FreeRTOS semaphores are taken using the xSemaphoreTake() API function,
- * the equivalent action that instead uses a task notification is
- * ulTaskNotifyTakeIndexed().
- *
- * When a task is using its notification value as a binary or counting semaphore
- * other tasks should send notifications to it using the xTaskNotifyGiveIndexed()
- * macro, or xTaskNotifyIndex() function with the eAction parameter set to
- * eIncrement.
- *
- * ulTaskNotifyTakeIndexed() can either clear the task's notification value at
- * the array index specified by the uxIndexToWaitOn parameter to zero on exit,
- * in which case the notification value acts like a binary semaphore, or
- * decrement the notification value on exit, in which case the notification
- * value acts like a counting semaphore.
- *
- * A task can use ulTaskNotifyTakeIndexed() to [optionally] block to wait for
- * the task's notification value to be non-zero.  The task does not consume any
- * CPU time while it is in the Blocked state.
- *
- * Where as xTaskNotifyWaitIndexed() will return when a notification is pending,
- * ulTaskNotifyTakeIndexed() will return when the task's notification value is
- * not zero.
- *
- * **NOTE** Each notification within the array operates independently - a task
- * can only block on one notification within the array at a time and will not be
- * unblocked by a notification sent to any other array index.
- *
- * Backward compatibility information:
- * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
- * all task notification API functions operated on that value. Replacing the
- * single notification value with an array of notification values necessitated a
- * new set of API functions that could address specific notifications within the
- * array.  ulTaskNotifyTake() is the original API function, and remains backward
- * compatible by always operating on the notification value at index 0 in the
- * array. Calling ulTaskNotifyTake() is equivalent to calling
- * ulTaskNotifyTakeIndexed() with the uxIndexToWaitOn parameter set to 0.
- *
- * @param uxIndexToWaitOn The index within the calling task's array of
- * notification values on which the calling task will wait for a notification to
- * be non-zero.  uxIndexToWaitOn must be less than
- * configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyTake() does
- * not have this parameter and always waits for notifications on index 0.
- *
- * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
- * notification value is decremented when the function exits.  In this way the
- * notification value acts like a counting semaphore.  If xClearCountOnExit is
- * not pdFALSE then the task's notification value is cleared to zero when the
- * function exits.  In this way the notification value acts like a binary
- * semaphore.
- *
- * @param xTicksToWait The maximum amount of time that the task should wait in
- * the Blocked state for the task's notification value to be greater than zero,
- * should the count not already be greater than zero when
- * ulTaskNotifyTake() was called.  The task will not consume any processing
- * time while it is in the Blocked state.  This is specified in kernel ticks,
- * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
- * specified in milliseconds to a time specified in ticks.
- *
- * @return The task's notification count before it is either cleared to zero or
- * decremented (see the xClearCountOnExit parameter).
- *
- * \defgroup ulTaskNotifyTakeIndexed ulTaskNotifyTakeIndexed
- * \ingroup TaskNotifications
- */
-uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                  BaseType_t xClearCountOnExit,
-                                  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-#define ulTaskNotifyTake( xClearCountOnExit, xTicksToWait ) \
-    ulTaskGenericNotifyTake( ( tskDEFAULT_INDEX_TO_NOTIFY ), ( xClearCountOnExit ), ( xTicksToWait ) )
-#define ulTaskNotifyTakeIndexed( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ) \
-    ulTaskGenericNotifyTake( ( uxIndexToWaitOn ), ( xClearCountOnExit ), ( xTicksToWait ) )
-
-/**
- * task. h
- * 
- * BaseType_t xTaskNotifyStateClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToCLear );
- *
- * BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
- * 

- *
- * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
- * functions to be available.
- *
- * Each task has a private array of "notification values" (or 'notifications'),
- * each of which is a 32-bit unsigned integer (uint32_t).  The constant
- * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
- * array, and (for backward compatibility) defaults to 1 if left undefined.
- * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
- *
- * If a notification is sent to an index within the array of notifications then
- * the notification at that index is said to be 'pending' until it is read or
- * explicitly cleared by the receiving task.  xTaskNotifyStateClearIndexed()
- * is the function that clears a pending notification without reading the
- * notification value.  The notification value at the same array index is not
- * altered.  Set xTask to NULL to clear the notification state of the calling
- * task.
- *
- * Backward compatibility information:
- * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
- * all task notification API functions operated on that value. Replacing the
- * single notification value with an array of notification values necessitated a
- * new set of API functions that could address specific notifications within the
- * array.  xTaskNotifyStateClear() is the original API function, and remains
- * backward compatible by always operating on the notification value at index 0
- * within the array. Calling xTaskNotifyStateClear() is equivalent to calling
- * xTaskNotifyStateClearIndexed() with the uxIndexToNotify parameter set to 0.
- *
- * @param xTask The handle of the RTOS task that will have a notification state
- * cleared.  Set xTask to NULL to clear a notification state in the calling
- * task.  To obtain a task's handle create the task using xTaskCreate() and
- * make use of the pxCreatedTask parameter, or create the task using
- * xTaskCreateStatic() and store the returned value, or use the task's name in
- * a call to xTaskGetHandle().
- *
- * @param uxIndexToClear The index within the target task's array of
- * notification values to act upon.  For example, setting uxIndexToClear to 1
- * will clear the state of the notification at index 1 within the array.
- * uxIndexToClear must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.
- * ulTaskNotifyStateClear() does not have this parameter and always acts on the
- * notification at index 0.
- *
- * @return pdTRUE if the task's notification state was set to
- * eNotWaitingNotification, otherwise pdFALSE.
- *
- * \defgroup xTaskNotifyStateClearIndexed xTaskNotifyStateClearIndexed
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                         UBaseType_t uxIndexToClear ) PRIVILEGED_FUNCTION;
-#define xTaskNotifyStateClear( xTask ) \
-    xTaskGenericNotifyStateClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ) )
-#define xTaskNotifyStateClearIndexed( xTask, uxIndexToClear ) \
-    xTaskGenericNotifyStateClear( ( xTask ), ( uxIndexToClear ) )
-
-/**
- * task. h
- * 
- * uint32_t ulTaskNotifyValueClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToClear, uint32_t ulBitsToClear );
- *
- * uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );
- * 

- *
- * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
- * functions to be available.
- *
- * Each task has a private array of "notification values" (or 'notifications'),
- * each of which is a 32-bit unsigned integer (uint32_t).  The constant
- * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
- * array, and (for backward compatibility) defaults to 1 if left undefined.
- * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
- *
- * ulTaskNotifyValueClearIndexed() clears the bits specified by the
- * ulBitsToClear bit mask in the notification value at array index uxIndexToClear
- * of the task referenced by xTask.
- *
- * Backward compatibility information:
- * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
- * all task notification API functions operated on that value. Replacing the
- * single notification value with an array of notification values necessitated a
- * new set of API functions that could address specific notifications within the
- * array.  ulTaskNotifyValueClear() is the original API function, and remains
- * backward compatible by always operating on the notification value at index 0
- * within the array. Calling ulTaskNotifyValueClear() is equivalent to calling
- * ulTaskNotifyValueClearIndexed() with the uxIndexToClear parameter set to 0.
- *
- * @param xTask The handle of the RTOS task that will have bits in one of its
- * notification values cleared. Set xTask to NULL to clear bits in a
- * notification value of the calling task.  To obtain a task's handle create the
- * task using xTaskCreate() and make use of the pxCreatedTask parameter, or
- * create the task using xTaskCreateStatic() and store the returned value, or
- * use the task's name in a call to xTaskGetHandle().
- *
- * @param uxIndexToClear The index within the target task's array of
- * notification values in which to clear the bits.  uxIndexToClear
- * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.
- * ulTaskNotifyValueClear() does not have this parameter and always clears bits
- * in the notification value at index 0.
- *
- * @param ulBitsToClear Bit mask of the bits to clear in the notification value of
- * xTask. Set a bit to 1 to clear the corresponding bits in the task's notification
- * value. Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear
- * the notification value to 0.  Set ulBitsToClear to 0 to query the task's
- * notification value without clearing any bits.
- *
- *
- * @return The value of the target task's notification value before the bits
- * specified by ulBitsToClear were cleared.
- * \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear
- * \ingroup TaskNotifications
- */
-uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                        UBaseType_t uxIndexToClear,
-                                        uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
-#define ulTaskNotifyValueClear( xTask, ulBitsToClear ) \
-    ulTaskGenericNotifyValueClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulBitsToClear ) )
-#define ulTaskNotifyValueClearIndexed( xTask, uxIndexToClear, ulBitsToClear ) \
-    ulTaskGenericNotifyValueClear( ( xTask ), ( uxIndexToClear ), ( ulBitsToClear ) )
-
-/**
- * task.h
- * 
- * void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );
- * 

- *
- * Capture the current time for future use with xTaskCheckForTimeOut().
- *
- * @param pxTimeOut Pointer to a timeout object into which the current time
- * is to be captured.  The captured time includes the tick count and the number
- * of times the tick count has overflowed since the system first booted.
- * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState
- * \ingroup TaskCtrl
- */
-void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
-
-/**
- * task.h
- * 
- * BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
- * 

- *
- * Determines if pxTicksToWait ticks has passed since a time was captured
- * using a call to vTaskSetTimeOutState().  The captured time includes the tick
- * count and the number of times the tick count has overflowed.
- *
- * @param pxTimeOut The time status as captured previously using
- * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated
- * to reflect the current time status.
- * @param pxTicksToWait The number of ticks to check for timeout i.e. if
- * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by
- * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred.
- * If the timeout has not occurred, pxTIcksToWait is updated to reflect the
- * number of remaining ticks.
- *
- * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is
- * returned and pxTicksToWait is updated to reflect the number of remaining
- * ticks.
- *
- * @see https://www.FreeRTOS.org/xTaskCheckForTimeOut.html
- *
- * Example Usage:
- * 
- *  // Driver library function used to receive uxWantedBytes from an Rx buffer
- *  // that is filled by a UART interrupt. If there are not enough bytes in the
- *  // Rx buffer then the task enters the Blocked state until it is notified that
- *  // more data has been placed into the buffer. If there is still not enough
- *  // data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()
- *  // is used to re-calculate the Block time to ensure the total amount of time
- *  // spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
- *  // continues until either the buffer contains at least uxWantedBytes bytes,
- *  // or the total amount of time spent in the Blocked state reaches
- *  // MAX_TIME_TO_WAIT - at which point the task reads however many bytes are
- *  // available up to a maximum of uxWantedBytes.
- *
- *  size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
- *  {
- *  size_t uxReceived = 0;
- *  TickType_t xTicksToWait = MAX_TIME_TO_WAIT;
- *  TimeOut_t xTimeOut;
- *
- *      // Initialize xTimeOut.  This records the time at which this function
- *      // was entered.
- *      vTaskSetTimeOutState( &xTimeOut );
- *
- *      // Loop until the buffer contains the wanted number of bytes, or a
- *      // timeout occurs.
- *      while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )
- *      {
- *          // The buffer didn't contain enough data so this task is going to
- *          // enter the Blocked state. Adjusting xTicksToWait to account for
- *          // any time that has been spent in the Blocked state within this
- *          // function so far to ensure the total amount of time spent in the
- *          // Blocked state does not exceed MAX_TIME_TO_WAIT.
- *          if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )
- *          {
- *              //Timed out before the wanted number of bytes were available,
- *              // exit the loop.
- *              break;
- *          }
- *
- *          // Wait for a maximum of xTicksToWait ticks to be notified that the
- *          // receive interrupt has placed more data into the buffer.
- *          ulTaskNotifyTake( pdTRUE, xTicksToWait );
- *      }
- *
- *      // Attempt to read uxWantedBytes from the receive buffer into pucBuffer.
- *      // The actual number of bytes read (which might be less than
- *      // uxWantedBytes) is returned.
- *      uxReceived = UART_read_from_receive_buffer( pxUARTInstance,
- *                                                  pucBuffer,
- *                                                  uxWantedBytes );
- *
- *      return uxReceived;
- *  }
- * 

- * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut
- * \ingroup TaskCtrl
- */
-BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                 TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * task.h
- * 
- * BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp );
- * 

- *
- * This function corrects the tick count value after the application code has held
- * interrupts disabled for an extended period resulting in tick interrupts having
- * been missed.
- *
- * This function is similar to vTaskStepTick(), however, unlike
- * vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a
- * time at which a task should be removed from the blocked state.  That means
- * tasks may have to be removed from the blocked state as the tick count is
- * moved.
- *
- * @param xTicksToCatchUp The number of tick interrupts that have been missed due to
- * interrupts being disabled.  Its value is not computed automatically, so must be
- * computed by the application writer.
- *
- * @return pdTRUE if moving the tick count forward resulted in a task leaving the
- * blocked state and a context switch being performed.  Otherwise pdFALSE.
- *
- * \defgroup xTaskCatchUpTicks xTaskCatchUpTicks
- * \ingroup TaskCtrl
- */
-BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;
-
-
-/*-----------------------------------------------------------
-* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
-*----------------------------------------------------------*/
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
- * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
- * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * Called from the real time kernel tick (either preemptive or cooperative),
- * this increments the tick count and checks if any tasks that are blocked
- * for a finite period required removing from a blocked list and placing on
- * a ready list.  If a non-zero value is returned then a context switch is
- * required because either:
- *   + A task was removed from a blocked list because its timeout had expired,
- *     or
- *   + Time slicing is in use and there is a task of equal priority to the
- *     currently running task.
- */
-BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * Removes the calling task from the ready list and places it both
- * on the list of tasks waiting for a particular event, and the
- * list of delayed tasks.  The task will be removed from both lists
- * and replaced on the ready list should either the event occur (and
- * there be no higher priority tasks waiting on the same event) or
- * the delay period expires.
- *
- * The 'unordered' version replaces the event list item value with the
- * xItemValue value, and inserts the list item at the end of the list.
- *
- * The 'ordered' version uses the existing event list item value (which is the
- * owning tasks priority) to insert the list item into the event list is task
- * priority order.
- *
- * @param pxEventList The list containing tasks that are blocked waiting
- * for the event to occur.
- *
- * @param xItemValue The item value to use for the event list item when the
- * event list is not ordered by task priority.
- *
- * @param xTicksToWait The maximum amount of time that the task should wait
- * for the event to occur.  This is specified in kernel ticks,the constant
- * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
- * period.
- */
-void vTaskPlaceOnEventList( List_t * const pxEventList,
-                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-void vTaskPlaceOnUnorderedEventList( List_t * pxEventList,
-                                     const TickType_t xItemValue,
-                                     const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * This function performs nearly the same function as vTaskPlaceOnEventList().
- * The difference being that this function does not permit tasks to block
- * indefinitely, whereas vTaskPlaceOnEventList() does.
- *
- */
-void vTaskPlaceOnEventListRestricted( List_t * const pxEventList,
-                                      TickType_t xTicksToWait,
-                                      const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * Removes a task from both the specified event list and the list of blocked
- * tasks, and places it on a ready queue.
- *
- * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
- * if either an event occurs to unblock a task, or the block timeout period
- * expires.
- *
- * xTaskRemoveFromEventList() is used when the event list is in task priority
- * order.  It removes the list item from the head of the event list as that will
- * have the highest priority owning task of all the tasks on the event list.
- * vTaskRemoveFromUnorderedEventList() is used when the event list is not
- * ordered and the event list items hold something other than the owning tasks
- * priority.  In this case the event list item value is updated to the value
- * passed in the xItemValue parameter.
- *
- * @return pdTRUE if the task being removed has a higher priority than the task
- * making the call, otherwise pdFALSE.
- */
-BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
-void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
-                                        const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
- * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
- * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * Sets the pointer to the current TCB to the TCB of the highest priority task
- * that is ready to run.
- */
-portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
-
-/*
- * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
- * THE EVENT BITS MODULE.
- */
-TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Return the handle of the calling task.
- */
-TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Shortcut used by the queue implementation to prevent unnecessary call to
- * taskYIELD();
- */
-void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Returns the scheduler state as taskSCHEDULER_RUNNING,
- * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
- */
-BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Raises the priority of the mutex holder to that of the calling task should
- * the mutex holder have a priority less than the calling task.
- */
-BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
-
-/*
- * Set the priority of a task back to its proper priority in the case that it
- * inherited a higher priority while it was holding a semaphore.
- */
-BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
-
-/*
- * If a higher priority task attempting to obtain a mutex caused a lower
- * priority task to inherit the higher priority task's priority - but the higher
- * priority task then timed out without obtaining the mutex, then the lower
- * priority task will disinherit the priority again - but only down as far as
- * the highest priority task that is still waiting for the mutex (if there were
- * more than one task waiting for the mutex).
- */
-void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder,
-                                          UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
-
-/*
- * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
- */
-UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/*
- * Set the uxTaskNumber of the task referenced by the xTask parameter to
- * uxHandle.
- */
-void vTaskSetTaskNumber( TaskHandle_t xTask,
-                         const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
-
-/*
- * Only available when configUSE_TICKLESS_IDLE is set to 1.
- * If tickless mode is being used, or a low power mode is implemented, then
- * the tick interrupt will not execute during idle periods.  When this is the
- * case, the tick count value maintained by the scheduler needs to be kept up
- * to date with the actual execution time by being skipped forward by a time
- * equal to the idle period.
- */
-void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
-
-/*
- * Only available when configUSE_TICKLESS_IDLE is set to 1.
- * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
- * specific sleep function to determine if it is ok to proceed with the sleep,
- * and if it is ok to proceed, if it is ok to sleep indefinitely.
- *
- * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
- * called with the scheduler suspended, not from within a critical section.  It
- * is therefore possible for an interrupt to request a context switch between
- * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
- * entered.  eTaskConfirmSleepModeStatus() should be called from a short
- * critical section between the timer being stopped and the sleep mode being
- * entered to ensure it is ok to proceed into the sleep mode.
- */
-eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
-
-/*
- * For internal use only.  Increment the mutex held count when a mutex is
- * taken and return the handle of the task that has taken the mutex.
- */
-TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
-
-/*
- * For internal use only.  Same as vTaskSetTimeOutState(), but without a critical
- * section.
- */
-void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
-
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    }
-#endif
-/* *INDENT-ON* */
-#endif /* INC_TASK_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/timers.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/timers.h
deleted file mode 100644
index 9a19c83..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/include/timers.h
+++ /dev/null
@@ -1,1351 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef TIMERS_H
-#define TIMERS_H
-
-#ifndef INC_FREERTOS_H
-    #error "include FreeRTOS.h must appear in source files before include timers.h"
-#endif
-
-/*lint -save -e537 This headers are only multiply included if the application code
- * happens to also be including task.h. */
-#include "task.h"
-/*lint -restore */
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/*-----------------------------------------------------------
-* MACROS AND DEFINITIONS
-*----------------------------------------------------------*/
-
-/* IDs for commands that can be sent/received on the timer queue.  These are to
- * be used solely through the macros that make up the public software timer API,
- * as defined below.  The commands that are sent from interrupts must use the
- * highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
- * or interrupt version of the queue send function should be used. */
-#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR    ( ( BaseType_t ) -2 )
-#define tmrCOMMAND_EXECUTE_CALLBACK             ( ( BaseType_t ) -1 )
-#define tmrCOMMAND_START_DONT_TRACE             ( ( BaseType_t ) 0 )
-#define tmrCOMMAND_START                        ( ( BaseType_t ) 1 )
-#define tmrCOMMAND_RESET                        ( ( BaseType_t ) 2 )
-#define tmrCOMMAND_STOP                         ( ( BaseType_t ) 3 )
-#define tmrCOMMAND_CHANGE_PERIOD                ( ( BaseType_t ) 4 )
-#define tmrCOMMAND_DELETE                       ( ( BaseType_t ) 5 )
-
-#define tmrFIRST_FROM_ISR_COMMAND               ( ( BaseType_t ) 6 )
-#define tmrCOMMAND_START_FROM_ISR               ( ( BaseType_t ) 6 )
-#define tmrCOMMAND_RESET_FROM_ISR               ( ( BaseType_t ) 7 )
-#define tmrCOMMAND_STOP_FROM_ISR                ( ( BaseType_t ) 8 )
-#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR       ( ( BaseType_t ) 9 )
-
-
-/**
- * Type by which software timers are referenced.  For example, a call to
- * xTimerCreate() returns an TimerHandle_t variable that can then be used to
- * reference the subject timer in calls to other software timer API functions
- * (for example, xTimerStart(), xTimerReset(), etc.).
- */
-struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
-typedef struct tmrTimerControl * TimerHandle_t;
-
-/*
- * Defines the prototype to which timer callback functions must conform.
- */
-typedef void (* TimerCallbackFunction_t)( TimerHandle_t xTimer );
-
-/*
- * Defines the prototype to which functions used with the
- * xTimerPendFunctionCallFromISR() function must conform.
- */
-typedef void (* PendedFunction_t)( void *,
-                                   uint32_t );
-
-/**
- * TimerHandle_t xTimerCreate(  const char * const pcTimerName,
- *                              TickType_t xTimerPeriodInTicks,
- *                              UBaseType_t uxAutoReload,
- *                              void * pvTimerID,
- *                              TimerCallbackFunction_t pxCallbackFunction );
- *
- * Creates a new software timer instance, and returns a handle by which the
- * created software timer can be referenced.
- *
- * Internally, within the FreeRTOS implementation, software timers use a block
- * of memory, in which the timer data structure is stored.  If a software timer
- * is created using xTimerCreate() then the required memory is automatically
- * dynamically allocated inside the xTimerCreate() function.  (see
- * https://www.FreeRTOS.org/a00111.html).  If a software timer is created using
- * xTimerCreateStatic() then the application writer must provide the memory that
- * will get used by the software timer.  xTimerCreateStatic() therefore allows a
- * software timer to be created without using any dynamic memory allocation.
- *
- * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
- * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
- * xTimerChangePeriodFromISR() API functions can all be used to transition a
- * timer into the active state.
- *
- * @param pcTimerName A text name that is assigned to the timer.  This is done
- * purely to assist debugging.  The kernel itself only ever references a timer
- * by its handle, and never by its name.
- *
- * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
- * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
- * has been specified in milliseconds.  For example, if the timer must expire
- * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
- * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
- * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
- * equal to 1000.  Time timer period must be greater than 0.
- *
- * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
- * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
- * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
- * enter the dormant state after it expires.
- *
- * @param pvTimerID An identifier that is assigned to the timer being created.
- * Typically this would be used in the timer callback function to identify which
- * timer expired when the same callback function is assigned to more than one
- * timer.
- *
- * @param pxCallbackFunction The function to call when the timer expires.
- * Callback functions must have the prototype defined by TimerCallbackFunction_t,
- * which is "void vCallbackFunction( TimerHandle_t xTimer );".
- *
- * @return If the timer is successfully created then a handle to the newly
- * created timer is returned.  If the timer cannot be created because there is
- * insufficient FreeRTOS heap remaining to allocate the timer
- * structures then NULL is returned.
- *
- * Example usage:
- * @verbatim
- * #define NUM_TIMERS 5
- *
- * // An array to hold handles to the created timers.
- * TimerHandle_t xTimers[ NUM_TIMERS ];
- *
- * // An array to hold a count of the number of times each timer expires.
- * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
- *
- * // Define a callback function that will be used by multiple timer instances.
- * // The callback function does nothing but count the number of times the
- * // associated timer expires, and stop the timer once the timer has expired
- * // 10 times.
- * void vTimerCallback( TimerHandle_t pxTimer )
- * {
- * int32_t lArrayIndex;
- * const int32_t xMaxExpiryCountBeforeStopping = 10;
- *
- *     // Optionally do something if the pxTimer parameter is NULL.
- *     configASSERT( pxTimer );
- *
- *     // Which timer expired?
- *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
- *
- *     // Increment the number of times that pxTimer has expired.
- *     lExpireCounters[ lArrayIndex ] += 1;
- *
- *     // If the timer has expired 10 times then stop it from running.
- *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
- *     {
- *         // Do not use a block time if calling a timer API function from a
- *         // timer callback function, as doing so could cause a deadlock!
- *         xTimerStop( pxTimer, 0 );
- *     }
- * }
- *
- * void main( void )
- * {
- * int32_t x;
- *
- *     // Create then start some timers.  Starting the timers before the scheduler
- *     // has been started means the timers will start running immediately that
- *     // the scheduler starts.
- *     for( x = 0; x < NUM_TIMERS; x++ )
- *     {
- *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
- *                                         ( 100 * x ),   // The timer period in ticks.
- *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
- *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
- *                                         vTimerCallback // Each timer calls the same callback when it expires.
- *                                     );
- *
- *         if( xTimers[ x ] == NULL )
- *         {
- *             // The timer was not created.
- *         }
- *         else
- *         {
- *             // Start the timer.  No block time is specified, and even if one was
- *             // it would be ignored because the scheduler has not yet been
- *             // started.
- *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
- *             {
- *                 // The timer could not be set into the Active state.
- *             }
- *         }
- *     }
- *
- *     // ...
- *     // Create tasks here.
- *     // ...
- *
- *     // Starting the scheduler will start the timers running as they have already
- *     // been set into the active state.
- *     vTaskStartScheduler();
- *
- *     // Should not reach here.
- *     for( ;; );
- * }
- * @endverbatim
- */
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                                const TickType_t xTimerPeriodInTicks,
-                                const UBaseType_t uxAutoReload,
-                                void * const pvTimerID,
-                                TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
- *                                  TickType_t xTimerPeriodInTicks,
- *                                  UBaseType_t uxAutoReload,
- *                                  void * pvTimerID,
- *                                  TimerCallbackFunction_t pxCallbackFunction,
- *                                  StaticTimer_t *pxTimerBuffer );
- *
- * Creates a new software timer instance, and returns a handle by which the
- * created software timer can be referenced.
- *
- * Internally, within the FreeRTOS implementation, software timers use a block
- * of memory, in which the timer data structure is stored.  If a software timer
- * is created using xTimerCreate() then the required memory is automatically
- * dynamically allocated inside the xTimerCreate() function.  (see
- * https://www.FreeRTOS.org/a00111.html).  If a software timer is created using
- * xTimerCreateStatic() then the application writer must provide the memory that
- * will get used by the software timer.  xTimerCreateStatic() therefore allows a
- * software timer to be created without using any dynamic memory allocation.
- *
- * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
- * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
- * xTimerChangePeriodFromISR() API functions can all be used to transition a
- * timer into the active state.
- *
- * @param pcTimerName A text name that is assigned to the timer.  This is done
- * purely to assist debugging.  The kernel itself only ever references a timer
- * by its handle, and never by its name.
- *
- * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
- * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
- * has been specified in milliseconds.  For example, if the timer must expire
- * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
- * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
- * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
- * equal to 1000.  The timer period must be greater than 0.
- *
- * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
- * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
- * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
- * enter the dormant state after it expires.
- *
- * @param pvTimerID An identifier that is assigned to the timer being created.
- * Typically this would be used in the timer callback function to identify which
- * timer expired when the same callback function is assigned to more than one
- * timer.
- *
- * @param pxCallbackFunction The function to call when the timer expires.
- * Callback functions must have the prototype defined by TimerCallbackFunction_t,
- * which is "void vCallbackFunction( TimerHandle_t xTimer );".
- *
- * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
- * will be then be used to hold the software timer's data structures, removing
- * the need for the memory to be allocated dynamically.
- *
- * @return If the timer is created then a handle to the created timer is
- * returned.  If pxTimerBuffer was NULL then NULL is returned.
- *
- * Example usage:
- * @verbatim
- *
- * // The buffer used to hold the software timer's data structure.
- * static StaticTimer_t xTimerBuffer;
- *
- * // A variable that will be incremented by the software timer's callback
- * // function.
- * UBaseType_t uxVariableToIncrement = 0;
- *
- * // A software timer callback function that increments a variable passed to
- * // it when the software timer was created.  After the 5th increment the
- * // callback function stops the software timer.
- * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
- * {
- * UBaseType_t *puxVariableToIncrement;
- * BaseType_t xReturned;
- *
- *     // Obtain the address of the variable to increment from the timer ID.
- *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
- *
- *     // Increment the variable to show the timer callback has executed.
- *     ( *puxVariableToIncrement )++;
- *
- *     // If this callback has executed the required number of times, stop the
- *     // timer.
- *     if( *puxVariableToIncrement == 5 )
- *     {
- *         // This is called from a timer callback so must not block.
- *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
- *     }
- * }
- *
- *
- * void main( void )
- * {
- *     // Create the software time.  xTimerCreateStatic() has an extra parameter
- *     // than the normal xTimerCreate() API function.  The parameter is a pointer
- *     // to the StaticTimer_t structure that will hold the software timer
- *     // structure.  If the parameter is passed as NULL then the structure will be
- *     // allocated dynamically, just as if xTimerCreate() had been called.
- *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
- *                                  xTimerPeriod,     // The period of the timer in ticks.
- *                                  pdTRUE,           // This is an auto-reload timer.
- *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
- *                                  prvTimerCallback, // The function to execute when the timer expires.
- *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
- *
- *     // The scheduler has not started yet so a block time is not used.
- *     xReturned = xTimerStart( xTimer, 0 );
- *
- *     // ...
- *     // Create tasks here.
- *     // ...
- *
- *     // Starting the scheduler will start the timers running as they have already
- *     // been set into the active state.
- *     vTaskStartScheduler();
- *
- *     // Should not reach here.
- *     for( ;; );
- * }
- * @endverbatim
- */
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                                      const TickType_t xTimerPeriodInTicks,
-                                      const UBaseType_t uxAutoReload,
-                                      void * const pvTimerID,
-                                      TimerCallbackFunction_t pxCallbackFunction,
-                                      StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION;
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * void *pvTimerGetTimerID( TimerHandle_t xTimer );
- *
- * Returns the ID assigned to the timer.
- *
- * IDs are assigned to timers using the pvTimerID parameter of the call to
- * xTimerCreated() that was used to create the timer, and by calling the
- * vTimerSetTimerID() API function.
- *
- * If the same callback function is assigned to multiple timers then the timer
- * ID can be used as time specific (timer local) storage.
- *
- * @param xTimer The timer being queried.
- *
- * @return The ID assigned to the timer being queried.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- */
-void * pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
- * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
- *
- * Sets the ID assigned to the timer.
- *
- * IDs are assigned to timers using the pvTimerID parameter of the call to
- * xTimerCreated() that was used to create the timer.
- *
- * If the same callback function is assigned to multiple timers then the timer
- * ID can be used as time specific (timer local) storage.
- *
- * @param xTimer The timer being updated.
- *
- * @param pvNewID The ID to assign to the timer.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- */
-void vTimerSetTimerID( TimerHandle_t xTimer,
-                       void * pvNewID ) PRIVILEGED_FUNCTION;
-
-/**
- * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
- *
- * Queries a timer to see if it is active or dormant.
- *
- * A timer will be dormant if:
- *     1) It has been created but not started, or
- *     2) It is an expired one-shot timer that has not been restarted.
- *
- * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
- * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
- * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
- * active state.
- *
- * @param xTimer The timer being queried.
- *
- * @return pdFALSE will be returned if the timer is dormant.  A value other than
- * pdFALSE will be returned if the timer is active.
- *
- * Example usage:
- * @verbatim
- * // This function assumes xTimer has already been created.
- * void vAFunction( TimerHandle_t xTimer )
- * {
- *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
- *     {
- *         // xTimer is active, do something.
- *     }
- *     else
- *     {
- *         // xTimer is not active, do something else.
- *     }
- * }
- * @endverbatim
- */
-BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
- * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
- *
- * Simply returns the handle of the timer service/daemon task.  It it not valid
- * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
- */
-TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
-
-/**
- * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerStart() starts a timer that was previously created using the
- * xTimerCreate() API function.  If the timer had already been started and was
- * already in the active state, then xTimerStart() has equivalent functionality
- * to the xTimerReset() API function.
- *
- * Starting a timer ensures the timer is in the active state.  If the timer
- * is not stopped, deleted, or reset in the mean time, the callback function
- * associated with the timer will get called 'n' ticks after xTimerStart() was
- * called, where 'n' is the timers defined period.
- *
- * It is valid to call xTimerStart() before the scheduler has been started, but
- * when this is done the timer will not actually start until the scheduler is
- * started, and the timers expiry time will be relative to when the scheduler is
- * started, not relative to when xTimerStart() was called.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
- * to be available.
- *
- * @param xTimer The handle of the timer being started/restarted.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the start command to be successfully
- * sent to the timer command queue, should the queue already be full when
- * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
- * before the scheduler is started.
- *
- * @return pdFAIL will be returned if the start command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system, although the
- * timers expiry time is relative to when xTimerStart() is actually called.  The
- * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- *
- */
-#define xTimerStart( xTimer, xTicksToWait ) \
-    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerStop() stops a timer that was previously started using either of the
- * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
- * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
- *
- * Stopping a timer ensures the timer is not in the active state.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
- * to be available.
- *
- * @param xTimer The handle of the timer being stopped.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the stop command to be successfully
- * sent to the timer command queue, should the queue already be full when
- * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
- * before the scheduler is started.
- *
- * @return pdFAIL will be returned if the stop command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system.  The timer
- * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- *
- */
-#define xTimerStop( xTimer, xTicksToWait ) \
-    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerChangePeriod(   TimerHandle_t xTimer,
- *                                  TickType_t xNewPeriod,
- *                                  TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerChangePeriod() changes the period of a timer that was previously
- * created using the xTimerCreate() API function.
- *
- * xTimerChangePeriod() can be called to change the period of an active or
- * dormant state timer.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for
- * xTimerChangePeriod() to be available.
- *
- * @param xTimer The handle of the timer that is having its period changed.
- *
- * @param xNewPeriod The new period for xTimer. Timer periods are specified in
- * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
- * that has been specified in milliseconds.  For example, if the timer must
- * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
- * if the timer must expire after 500ms, then xNewPeriod can be set to
- * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
- * or equal to 1000.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the change period command to be
- * successfully sent to the timer command queue, should the queue already be
- * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
- * xTimerChangePeriod() is called before the scheduler is started.
- *
- * @return pdFAIL will be returned if the change period command could not be
- * sent to the timer command queue even after xTicksToWait ticks had passed.
- * pdPASS will be returned if the command was successfully sent to the timer
- * command queue.  When the command is actually processed will depend on the
- * priority of the timer service/daemon task relative to other tasks in the
- * system.  The timer service/daemon task priority is set by the
- * configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This function assumes xTimer has already been created.  If the timer
- * // referenced by xTimer is already active when it is called, then the timer
- * // is deleted.  If the timer referenced by xTimer is not active when it is
- * // called, then the period of the timer is set to 500ms and the timer is
- * // started.
- * void vAFunction( TimerHandle_t xTimer )
- * {
- *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
- *     {
- *         // xTimer is already active - delete it.
- *         xTimerDelete( xTimer );
- *     }
- *     else
- *     {
- *         // xTimer is not active, change its period to 500ms.  This will also
- *         // cause the timer to start.  Block for a maximum of 100 ticks if the
- *         // change period command cannot immediately be sent to the timer
- *         // command queue.
- *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
- *         {
- *             // The command was successfully sent.
- *         }
- *         else
- *         {
- *             // The command could not be sent, even after waiting for 100 ticks
- *             // to pass.  Take appropriate action here.
- *         }
- *     }
- * }
- * @endverbatim
- */
-#define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) \
-    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerDelete() deletes a timer that was previously created using the
- * xTimerCreate() API function.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for
- * xTimerDelete() to be available.
- *
- * @param xTimer The handle of the timer being deleted.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the delete command to be
- * successfully sent to the timer command queue, should the queue already be
- * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
- * is called before the scheduler is started.
- *
- * @return pdFAIL will be returned if the delete command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system.  The timer
- * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- *
- * See the xTimerChangePeriod() API function example usage scenario.
- */
-#define xTimerDelete( xTimer, xTicksToWait ) \
-    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerReset() re-starts a timer that was previously created using the
- * xTimerCreate() API function.  If the timer had already been started and was
- * already in the active state, then xTimerReset() will cause the timer to
- * re-evaluate its expiry time so that it is relative to when xTimerReset() was
- * called.  If the timer was in the dormant state then xTimerReset() has
- * equivalent functionality to the xTimerStart() API function.
- *
- * Resetting a timer ensures the timer is in the active state.  If the timer
- * is not stopped, deleted, or reset in the mean time, the callback function
- * associated with the timer will get called 'n' ticks after xTimerReset() was
- * called, where 'n' is the timers defined period.
- *
- * It is valid to call xTimerReset() before the scheduler has been started, but
- * when this is done the timer will not actually start until the scheduler is
- * started, and the timers expiry time will be relative to when the scheduler is
- * started, not relative to when xTimerReset() was called.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
- * to be available.
- *
- * @param xTimer The handle of the timer being reset/started/restarted.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the reset command to be successfully
- * sent to the timer command queue, should the queue already be full when
- * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
- * before the scheduler is started.
- *
- * @return pdFAIL will be returned if the reset command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system, although the
- * timers expiry time is relative to when xTimerStart() is actually called.  The
- * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- * @verbatim
- * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
- * // without a key being pressed, then the LCD back-light is switched off.  In
- * // this case, the timer is a one-shot timer.
- *
- * TimerHandle_t xBacklightTimer = NULL;
- *
- * // The callback function assigned to the one-shot timer.  In this case the
- * // parameter is not used.
- * void vBacklightTimerCallback( TimerHandle_t pxTimer )
- * {
- *     // The timer expired, therefore 5 seconds must have passed since a key
- *     // was pressed.  Switch off the LCD back-light.
- *     vSetBacklightState( BACKLIGHT_OFF );
- * }
- *
- * // The key press event handler.
- * void vKeyPressEventHandler( char cKey )
- * {
- *     // Ensure the LCD back-light is on, then reset the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
- *     // if it cannot be sent immediately.
- *     vSetBacklightState( BACKLIGHT_ON );
- *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
- *     {
- *         // The reset command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // Perform the rest of the key processing here.
- * }
- *
- * void main( void )
- * {
- * int32_t x;
- *
- *     // Create then start the one-shot timer that is responsible for turning
- *     // the back-light off if no keys are pressed within a 5 second period.
- *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
- *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
- *                                     pdFALSE,                    // The timer is a one-shot timer.
- *                                     0,                          // The id is not used by the callback so can take any value.
- *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
- *                                   );
- *
- *     if( xBacklightTimer == NULL )
- *     {
- *         // The timer was not created.
- *     }
- *     else
- *     {
- *         // Start the timer.  No block time is specified, and even if one was
- *         // it would be ignored because the scheduler has not yet been
- *         // started.
- *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
- *         {
- *             // The timer could not be set into the Active state.
- *         }
- *     }
- *
- *     // ...
- *     // Create tasks here.
- *     // ...
- *
- *     // Starting the scheduler will start the timer running as it has already
- *     // been set into the active state.
- *     vTaskStartScheduler();
- *
- *     // Should not reach here.
- *     for( ;; );
- * }
- * @endverbatim
- */
-#define xTimerReset( xTimer, xTicksToWait ) \
-    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerStartFromISR(   TimerHandle_t xTimer,
- *                                  BaseType_t *pxHigherPriorityTaskWoken );
- *
- * A version of xTimerStart() that can be called from an interrupt service
- * routine.
- *
- * @param xTimer The handle of the timer being started/restarted.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerStartFromISR() writes a message to the timer
- * command queue, so has the potential to transition the timer service/daemon
- * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
- * timer service/daemon task to leave the Blocked state, and the timer service/
- * daemon task has a priority equal to or greater than the currently executing
- * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
- * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
- * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
- * be performed before the interrupt exits.
- *
- * @return pdFAIL will be returned if the start command could not be sent to
- * the timer command queue.  pdPASS will be returned if the command was
- * successfully sent to the timer command queue.  When the command is actually
- * processed will depend on the priority of the timer service/daemon task
- * relative to other tasks in the system, although the timers expiry time is
- * relative to when xTimerStartFromISR() is actually called.  The timer
- * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This scenario assumes xBacklightTimer has already been created.  When a
- * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
- * // without a key being pressed, then the LCD back-light is switched off.  In
- * // this case, the timer is a one-shot timer, and unlike the example given for
- * // the xTimerReset() function, the key press event handler is an interrupt
- * // service routine.
- *
- * // The callback function assigned to the one-shot timer.  In this case the
- * // parameter is not used.
- * void vBacklightTimerCallback( TimerHandle_t pxTimer )
- * {
- *     // The timer expired, therefore 5 seconds must have passed since a key
- *     // was pressed.  Switch off the LCD back-light.
- *     vSetBacklightState( BACKLIGHT_OFF );
- * }
- *
- * // The key press interrupt service routine.
- * void vKeyPressEventInterruptHandler( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // Ensure the LCD back-light is on, then restart the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  This is an interrupt service routine so can only
- *     // call FreeRTOS API functions that end in "FromISR".
- *     vSetBacklightState( BACKLIGHT_ON );
- *
- *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
- *     // as both cause the timer to re-calculate its expiry time.
- *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
- *     // declared (in this function).
- *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The start command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // Perform the rest of the key processing here.
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endverbatim
- */
-#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) \
-    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
-
-/**
- * BaseType_t xTimerStopFromISR(    TimerHandle_t xTimer,
- *                                  BaseType_t *pxHigherPriorityTaskWoken );
- *
- * A version of xTimerStop() that can be called from an interrupt service
- * routine.
- *
- * @param xTimer The handle of the timer being stopped.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerStopFromISR() writes a message to the timer
- * command queue, so has the potential to transition the timer service/daemon
- * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
- * timer service/daemon task to leave the Blocked state, and the timer service/
- * daemon task has a priority equal to or greater than the currently executing
- * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
- * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
- * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
- * be performed before the interrupt exits.
- *
- * @return pdFAIL will be returned if the stop command could not be sent to
- * the timer command queue.  pdPASS will be returned if the command was
- * successfully sent to the timer command queue.  When the command is actually
- * processed will depend on the priority of the timer service/daemon task
- * relative to other tasks in the system.  The timer service/daemon task
- * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This scenario assumes xTimer has already been created and started.  When
- * // an interrupt occurs, the timer should be simply stopped.
- *
- * // The interrupt service routine that stops the timer.
- * void vAnExampleInterruptServiceRoutine( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // The interrupt has occurred - simply stop the timer.
- *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
- *     // (within this function).  As this is an interrupt service routine, only
- *     // FreeRTOS API functions that end in "FromISR" can be used.
- *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The stop command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endverbatim
- */
-#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) \
-    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
-
-/**
- * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
- *                                       TickType_t xNewPeriod,
- *                                       BaseType_t *pxHigherPriorityTaskWoken );
- *
- * A version of xTimerChangePeriod() that can be called from an interrupt
- * service routine.
- *
- * @param xTimer The handle of the timer that is having its period changed.
- *
- * @param xNewPeriod The new period for xTimer. Timer periods are specified in
- * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
- * that has been specified in milliseconds.  For example, if the timer must
- * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
- * if the timer must expire after 500ms, then xNewPeriod can be set to
- * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
- * or equal to 1000.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
- * timer command queue, so has the potential to transition the timer service/
- * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
- * causes the timer service/daemon task to leave the Blocked state, and the
- * timer service/daemon task has a priority equal to or greater than the
- * currently executing task (the task that was interrupted), then
- * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
- * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
- * this value to pdTRUE then a context switch should be performed before the
- * interrupt exits.
- *
- * @return pdFAIL will be returned if the command to change the timers period
- * could not be sent to the timer command queue.  pdPASS will be returned if the
- * command was successfully sent to the timer command queue.  When the command
- * is actually processed will depend on the priority of the timer service/daemon
- * task relative to other tasks in the system.  The timer service/daemon task
- * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This scenario assumes xTimer has already been created and started.  When
- * // an interrupt occurs, the period of xTimer should be changed to 500ms.
- *
- * // The interrupt service routine that changes the period of xTimer.
- * void vAnExampleInterruptServiceRoutine( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // The interrupt has occurred - change the period of xTimer to 500ms.
- *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
- *     // (within this function).  As this is an interrupt service routine, only
- *     // FreeRTOS API functions that end in "FromISR" can be used.
- *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The command to change the timers period was not executed
- *         // successfully.  Take appropriate action here.
- *     }
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endverbatim
- */
-#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) \
-    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
-
-/**
- * BaseType_t xTimerResetFromISR(   TimerHandle_t xTimer,
- *                                  BaseType_t *pxHigherPriorityTaskWoken );
- *
- * A version of xTimerReset() that can be called from an interrupt service
- * routine.
- *
- * @param xTimer The handle of the timer that is to be started, reset, or
- * restarted.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerResetFromISR() writes a message to the timer
- * command queue, so has the potential to transition the timer service/daemon
- * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
- * timer service/daemon task to leave the Blocked state, and the timer service/
- * daemon task has a priority equal to or greater than the currently executing
- * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
- * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
- * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
- * be performed before the interrupt exits.
- *
- * @return pdFAIL will be returned if the reset command could not be sent to
- * the timer command queue.  pdPASS will be returned if the command was
- * successfully sent to the timer command queue.  When the command is actually
- * processed will depend on the priority of the timer service/daemon task
- * relative to other tasks in the system, although the timers expiry time is
- * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
- * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This scenario assumes xBacklightTimer has already been created.  When a
- * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
- * // without a key being pressed, then the LCD back-light is switched off.  In
- * // this case, the timer is a one-shot timer, and unlike the example given for
- * // the xTimerReset() function, the key press event handler is an interrupt
- * // service routine.
- *
- * // The callback function assigned to the one-shot timer.  In this case the
- * // parameter is not used.
- * void vBacklightTimerCallback( TimerHandle_t pxTimer )
- * {
- *     // The timer expired, therefore 5 seconds must have passed since a key
- *     // was pressed.  Switch off the LCD back-light.
- *     vSetBacklightState( BACKLIGHT_OFF );
- * }
- *
- * // The key press interrupt service routine.
- * void vKeyPressEventInterruptHandler( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // Ensure the LCD back-light is on, then reset the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  This is an interrupt service routine so can only
- *     // call FreeRTOS API functions that end in "FromISR".
- *     vSetBacklightState( BACKLIGHT_ON );
- *
- *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
- *     // as both cause the timer to re-calculate its expiry time.
- *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
- *     // declared (in this function).
- *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The reset command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // Perform the rest of the key processing here.
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endverbatim
- */
-#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) \
-    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
-
-
-/**
- * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
- *                                          void *pvParameter1,
- *                                          uint32_t ulParameter2,
- *                                          BaseType_t *pxHigherPriorityTaskWoken );
- *
- *
- * Used from application interrupt service routines to defer the execution of a
- * function to the RTOS daemon task (the timer service task, hence this function
- * is implemented in timers.c and is prefixed with 'Timer').
- *
- * Ideally an interrupt service routine (ISR) is kept as short as possible, but
- * sometimes an ISR either has a lot of processing to do, or needs to perform
- * processing that is not deterministic.  In these cases
- * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
- * to the RTOS daemon task.
- *
- * A mechanism is provided that allows the interrupt to return directly to the
- * task that will subsequently execute the pended callback function.  This
- * allows the callback function to execute contiguously in time with the
- * interrupt - just as if the callback had executed in the interrupt itself.
- *
- * @param xFunctionToPend The function to execute from the timer service/
- * daemon task.  The function must conform to the PendedFunction_t
- * prototype.
- *
- * @param pvParameter1 The value of the callback function's first parameter.
- * The parameter has a void * type to allow it to be used to pass any type.
- * For example, unsigned longs can be cast to a void *, or the void * can be
- * used to point to a structure.
- *
- * @param ulParameter2 The value of the callback function's second parameter.
- *
- * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
- * will result in a message being sent to the timer daemon task.  If the
- * priority of the timer daemon task (which is set using
- * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
- * the currently running task (the task the interrupt interrupted) then
- * *pxHigherPriorityTaskWoken will be set to pdTRUE within
- * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
- * requested before the interrupt exits.  For that reason
- * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
- * example code below.
- *
- * @return pdPASS is returned if the message was successfully sent to the
- * timer daemon task, otherwise pdFALSE is returned.
- *
- * Example usage:
- * @verbatim
- *
- *  // The callback function that will execute in the context of the daemon task.
- *  // Note callback functions must all use this same prototype.
- *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
- *  {
- *      BaseType_t xInterfaceToService;
- *
- *      // The interface that requires servicing is passed in the second
- *      // parameter.  The first parameter is not used in this case.
- *      xInterfaceToService = ( BaseType_t ) ulParameter2;
- *
- *      // ...Perform the processing here...
- *  }
- *
- *  // An ISR that receives data packets from multiple interfaces
- *  void vAnISR( void )
- *  {
- *      BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
- *
- *      // Query the hardware to determine which interface needs processing.
- *      xInterfaceToService = prvCheckInterfaces();
- *
- *      // The actual processing is to be deferred to a task.  Request the
- *      // vProcessInterface() callback function is executed, passing in the
- *      // number of the interface that needs processing.  The interface to
- *      // service is passed in the second parameter.  The first parameter is
- *      // not used in this case.
- *      xHigherPriorityTaskWoken = pdFALSE;
- *      xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
- *
- *      // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
- *      // switch should be requested.  The macro used is port specific and will
- *      // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
- *      // the documentation page for the port being used.
- *      portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
- *
- *  }
- * @endverbatim
- */
-BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
-                                          void * pvParameter1,
-                                          uint32_t ulParameter2,
-                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
- *                                    void *pvParameter1,
- *                                    uint32_t ulParameter2,
- *                                    TickType_t xTicksToWait );
- *
- *
- * Used to defer the execution of a function to the RTOS daemon task (the timer
- * service task, hence this function is implemented in timers.c and is prefixed
- * with 'Timer').
- *
- * @param xFunctionToPend The function to execute from the timer service/
- * daemon task.  The function must conform to the PendedFunction_t
- * prototype.
- *
- * @param pvParameter1 The value of the callback function's first parameter.
- * The parameter has a void * type to allow it to be used to pass any type.
- * For example, unsigned longs can be cast to a void *, or the void * can be
- * used to point to a structure.
- *
- * @param ulParameter2 The value of the callback function's second parameter.
- *
- * @param xTicksToWait Calling this function will result in a message being
- * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
- * time the calling task should remain in the Blocked state (so not using any
- * processing time) for space to become available on the timer queue if the
- * queue is found to be full.
- *
- * @return pdPASS is returned if the message was successfully sent to the
- * timer daemon task, otherwise pdFALSE is returned.
- *
- */
-BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
-                                   void * pvParameter1,
-                                   uint32_t ulParameter2,
-                                   TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * const char * const pcTimerGetName( TimerHandle_t xTimer );
- *
- * Returns the name that was assigned to a timer when the timer was created.
- *
- * @param xTimer The handle of the timer being queried.
- *
- * @return The name assigned to the timer specified by the xTimer parameter.
- */
-const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
- *
- * Updates a timer to be either an auto-reload timer, in which case the timer
- * automatically resets itself each time it expires, or a one-shot timer, in
- * which case the timer will only expire once unless it is manually restarted.
- *
- * @param xTimer The handle of the timer being updated.
- *
- * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
- * expire repeatedly with a frequency set by the timer's period (see the
- * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
- * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
- * enter the dormant state after it expires.
- */
-void vTimerSetReloadMode( TimerHandle_t xTimer,
-                          const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
-
-/**
- * UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer );
- *
- * Queries a timer to determine if it is an auto-reload timer, in which case the timer
- * automatically resets itself each time it expires, or a one-shot timer, in
- * which case the timer will only expire once unless it is manually restarted.
- *
- * @param xTimer The handle of the timer being queried.
- *
- * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise
- * pdFALSE is returned.
- */
-UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
- * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
- *
- * Returns the period of a timer.
- *
- * @param xTimer The handle of the timer being queried.
- *
- * @return The period of the timer in ticks.
- */
-TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
- * TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
- *
- * Returns the time in ticks at which the timer will expire.  If this is less
- * than the current tick count then the expiry time has overflowed from the
- * current time.
- *
- * @param xTimer The handle of the timer being queried.
- *
- * @return If the timer is running then the time in ticks at which the timer
- * will next expire is returned.  If the timer is not running then the return
- * value is undefined.
- */
-TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/*
- * Functions beyond this part are not part of the public API and are intended
- * for use by the kernel only.
- */
-BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
-BaseType_t xTimerGenericCommand( TimerHandle_t xTimer,
-                                 const BaseType_t xCommandID,
-                                 const TickType_t xOptionalValue,
-                                 BaseType_t * const pxHigherPriorityTaskWoken,
-                                 const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-    void vTimerSetTimerNumber( TimerHandle_t xTimer,
-                               UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
-    UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-#endif
-
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-    /**
-     * task.h
-     * 
void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) 

-     * 
-     * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB.  This function is required when 
-     * configSUPPORT_STATIC_ALLOCATION is set.  For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION
-     * 
-     * @param ppxTimerTaskTCBBuffer   A handle to a statically allocated TCB buffer
-     * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for thie idle task
-     * @param pulTimerTaskStackSize   A pointer to the number of elements that will fit in the allocated stack buffer
-     */
-    void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
-                                          StackType_t ** ppxTimerTaskStackBuffer,
-                                              uint32_t * pulTimerTaskStackSize );
-
-#endif
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    }
-#endif
-/* *INDENT-ON* */
-#endif /* TIMERS_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/list.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/list.c
deleted file mode 100644
index a84b1f3..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/list.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers.  That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "list.h"
-
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be
- * defined for the header files above, but not in this file, in order to
- * generate the correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
-
-/*-----------------------------------------------------------
-* PUBLIC LIST API documented in list.h
-*----------------------------------------------------------*/
-
-void vListInitialise( List_t * const pxList )
-{
-    /* The list structure contains a list item which is used to mark the
-     * end of the list.  To initialise the list the list end is inserted
-     * as the only list entry. */
-    pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-
-    /* The list end value is the highest possible value in the list to
-     * ensure it remains at the end of the list. */
-    pxList->xListEnd.xItemValue = portMAX_DELAY;
-
-    /* The list end next and previous pointers point to itself so we know
-     * when the list is empty. */
-    pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );     /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-    pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-
-    pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
-
-    /* Write known values into the list if
-     * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-    listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
-    listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
-}
-/*-----------------------------------------------------------*/
-
-void vListInitialiseItem( ListItem_t * const pxItem )
-{
-    /* Make sure the list item is not recorded as being on a list. */
-    pxItem->pxContainer = NULL;
-
-    /* Write known values into the list item if
-     * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-    listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
-    listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
-}
-/*-----------------------------------------------------------*/
-
-void vListInsertEnd( List_t * const pxList,
-                     ListItem_t * const pxNewListItem )
-{
-    ListItem_t * const pxIndex = pxList->pxIndex;
-
-    /* Only effective when configASSERT() is also defined, these tests may catch
-     * the list data structures being overwritten in memory.  They will not catch
-     * data errors caused by incorrect configuration or use of FreeRTOS. */
-    listTEST_LIST_INTEGRITY( pxList );
-    listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
-
-    /* Insert a new list item into pxList, but rather than sort the list,
-     * makes the new list item the last item to be removed by a call to
-     * listGET_OWNER_OF_NEXT_ENTRY(). */
-    pxNewListItem->pxNext = pxIndex;
-    pxNewListItem->pxPrevious = pxIndex->pxPrevious;
-
-    /* Only used during decision coverage testing. */
-    mtCOVERAGE_TEST_DELAY();
-
-    pxIndex->pxPrevious->pxNext = pxNewListItem;
-    pxIndex->pxPrevious = pxNewListItem;
-
-    /* Remember which list the item is in. */
-    pxNewListItem->pxContainer = pxList;
-
-    ( pxList->uxNumberOfItems )++;
-}
-/*-----------------------------------------------------------*/
-
-void vListInsert( List_t * const pxList,
-                  ListItem_t * const pxNewListItem )
-{
-    ListItem_t * pxIterator;
-    const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
-
-    /* Only effective when configASSERT() is also defined, these tests may catch
-     * the list data structures being overwritten in memory.  They will not catch
-     * data errors caused by incorrect configuration or use of FreeRTOS. */
-    listTEST_LIST_INTEGRITY( pxList );
-    listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
-
-    /* Insert the new list item into the list, sorted in xItemValue order.
-     *
-     * If the list already contains a list item with the same item value then the
-     * new list item should be placed after it.  This ensures that TCBs which are
-     * stored in ready lists (all of which have the same xItemValue value) get a
-     * share of the CPU.  However, if the xItemValue is the same as the back marker
-     * the iteration loop below will not end.  Therefore the value is checked
-     * first, and the algorithm slightly modified if necessary. */
-    if( xValueOfInsertion == portMAX_DELAY )
-    {
-        pxIterator = pxList->xListEnd.pxPrevious;
-    }
-    else
-    {
-        /* *** NOTE ***********************************************************
-        *  If you find your application is crashing here then likely causes are
-        *  listed below.  In addition see https://www.FreeRTOS.org/FAQHelp.html for
-        *  more tips, and ensure configASSERT() is defined!
-        *  https://www.FreeRTOS.org/a00110.html#configASSERT
-        *
-        *   1) Stack overflow -
-        *      see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html
-        *   2) Incorrect interrupt priority assignment, especially on Cortex-M
-        *      parts where numerically high priority values denote low actual
-        *      interrupt priorities, which can seem counter intuitive.  See
-        *      https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition
-        *      of configMAX_SYSCALL_INTERRUPT_PRIORITY on
-        *      https://www.FreeRTOS.org/a00110.html
-        *   3) Calling an API function from within a critical section or when
-        *      the scheduler is suspended, or calling an API function that does
-        *      not end in "FromISR" from an interrupt.
-        *   4) Using a queue or semaphore before it has been initialised or
-        *      before the scheduler has been started (are interrupts firing
-        *      before vTaskStartScheduler() has been called?).
-        **********************************************************************/
-
-        for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
-        {
-            /* There is nothing to do here, just iterating to the wanted
-             * insertion position. */
-        }
-    }
-
-    pxNewListItem->pxNext = pxIterator->pxNext;
-    pxNewListItem->pxNext->pxPrevious = pxNewListItem;
-    pxNewListItem->pxPrevious = pxIterator;
-    pxIterator->pxNext = pxNewListItem;
-
-    /* Remember which list the item is in.  This allows fast removal of the
-     * item later. */
-    pxNewListItem->pxContainer = pxList;
-
-    ( pxList->uxNumberOfItems )++;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
-{
-/* The list item knows which list it is in.  Obtain the list from the list
- * item. */
-    List_t * const pxList = pxItemToRemove->pxContainer;
-
-    pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
-    pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
-
-    /* Only used during decision coverage testing. */
-    mtCOVERAGE_TEST_DELAY();
-
-    /* Make sure the index is left pointing to a valid item. */
-    if( pxList->pxIndex == pxItemToRemove )
-    {
-        pxList->pxIndex = pxItemToRemove->pxPrevious;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    pxItemToRemove->pxContainer = NULL;
-    ( pxList->uxNumberOfItems )--;
-
-    return pxList->uxNumberOfItems;
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_extension_MIMXRT1176_cm4.cmake b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_extension_MIMXRT1176_cm4.cmake
deleted file mode 100644
index a8772ad..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_extension_MIMXRT1176_cm4.cmake
+++ /dev/null
@@ -1,8 +0,0 @@
-include_guard()
-message("middleware_freertos-kernel_extension component is included.")
-
-
-target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
-    ${CMAKE_CURRENT_LIST_DIR}/include
-)
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_extension_MIMXRT1176_cm7.cmake b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_extension_MIMXRT1176_cm7.cmake
deleted file mode 100644
index a8772ad..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_extension_MIMXRT1176_cm7.cmake
+++ /dev/null
@@ -1,8 +0,0 @@
-include_guard()
-message("middleware_freertos-kernel_extension component is included.")
-
-
-target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
-    ${CMAKE_CURRENT_LIST_DIR}/include
-)
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_heap_3_MIMXRT1176_cm4.cmake b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_heap_3_MIMXRT1176_cm4.cmake
deleted file mode 100644
index 41cb203..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_heap_3_MIMXRT1176_cm4.cmake
+++ /dev/null
@@ -1,10 +0,0 @@
-include_guard()
-message("middleware_freertos-kernel_heap_3 component is included.")
-
-target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
-    ${CMAKE_CURRENT_LIST_DIR}/portable/MemMang/heap_3.c
-)
-
-
-include(middleware_freertos-kernel_MIMXRT1176_cm4)
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_heap_3_MIMXRT1176_cm7.cmake b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_heap_3_MIMXRT1176_cm7.cmake
deleted file mode 100644
index 7a57d9f..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_heap_3_MIMXRT1176_cm7.cmake
+++ /dev/null
@@ -1,10 +0,0 @@
-include_guard()
-message("middleware_freertos-kernel_heap_3 component is included.")
-
-target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
-    ${CMAKE_CURRENT_LIST_DIR}/portable/MemMang/heap_3.c
-)
-
-
-include(middleware_freertos-kernel_MIMXRT1176_cm7)
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_heap_4_MIMXRT1176_cm4.cmake b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_heap_4_MIMXRT1176_cm4.cmake
deleted file mode 100644
index 56638a9..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_heap_4_MIMXRT1176_cm4.cmake
+++ /dev/null
@@ -1,10 +0,0 @@
-include_guard()
-message("middleware_freertos-kernel_heap_4 component is included.")
-
-target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
-    ${CMAKE_CURRENT_LIST_DIR}/portable/MemMang/heap_4.c
-)
-
-
-include(middleware_freertos-kernel_MIMXRT1176_cm4)
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_heap_4_MIMXRT1176_cm7.cmake b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_heap_4_MIMXRT1176_cm7.cmake
deleted file mode 100644
index 33bb53c..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/middleware_freertos-kernel_heap_4_MIMXRT1176_cm7.cmake
+++ /dev/null
@@ -1,10 +0,0 @@
-include_guard()
-message("middleware_freertos-kernel_heap_4 component is included.")
-
-target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
-    ${CMAKE_CURRENT_LIST_DIR}/portable/MemMang/heap_4.c
-)
-
-
-include(middleware_freertos-kernel_MIMXRT1176_cm7)
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/ReadMe.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/ReadMe.txt
deleted file mode 100644
index 9b12e54..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/ReadMe.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
-Do not use the files located here!  These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
-FreeRTOS release.
-
-If your Cortex-M33 application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
-
-If your Cortex-M33 application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/copy_files.py b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/copy_files.py
deleted file mode 100644
index 717ec0d..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/copy_files.py
+++ /dev/null
@@ -1,103 +0,0 @@
-#/*
-# * FreeRTOS Kernel V10.4.3 LTS Patch 2
-# * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-# *
-# * Permission is hereby granted, free of charge, to any person obtaining a copy of
-# * this software and associated documentation files (the "Software"), to deal in
-# * the Software without restriction, including without limitation the rights to
-# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-# * the Software, and to permit persons to whom the Software is furnished to do so,
-# * subject to the following conditions:
-# *
-# * The above copyright notice and this permission notice shall be included in all
-# * copies or substantial portions of the Software.
-# *
-# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-# *
-# * https://www.FreeRTOS.org
-# * https://github.com/FreeRTOS
-# *
-# * 1 tab == 4 spaces!
-# */
-
-import os
-import shutil
-
-_THIS_FILE_DIRECTORY_ = os.path.dirname(os.path.realpath(__file__))
-_FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_)
-
-_COMPILERS_ = ['GCC', 'IAR']
-_ARCH_NS_ = ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
-_ARCH_S_ = ['ARM_CM33', 'ARM_CM23']
-
-_SUPPORTED_CONFIGS_ =   {
-                            'GCC' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ'],
-                            'IAR' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
-                        }
-
-# Files to be complied in the Secure Project
-_SECURE_FILE_PATHS_ = [
-    os.path.join('secure', 'context'),
-    os.path.join('secure', 'context', 'portable', '_COMPILER_ARCH_'),
-    os.path.join('secure', 'heap'),
-    os.path.join('secure', 'init'),
-    os.path.join('secure', 'macros')
-]
-
-# Files to be complied in the Non-Secure Project
-_NONSECURE_FILE_PATHS_ = [
-    'non_secure',
-    os.path.join('non_secure', 'portable', '_COMPILER_ARCH_')
-]
-
-
-def is_supported_config(compiler, arch):
-    return arch in _SUPPORTED_CONFIGS_[compiler]
-
-
-def copy_files_in_dir(src_abs_path, dst_abs_path):
-    for src_file in os.listdir(src_abs_path):
-        src_file_abs_path = os.path.join(src_abs_path, src_file)
-        if os.path.isfile(src_file_abs_path) and src_file != 'ReadMe.txt':
-            if not os.path.exists(dst_abs_path):
-                os.makedirs(dst_abs_path)
-            print('Copying {}...'.format(os.path.basename(src_file_abs_path)))
-            shutil.copy2(src_file_abs_path, dst_abs_path)
-
-
-def copy_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path):
-    _COMPILER_ARCH_ = os.path.join(compiler, arch)
-    for src_path in src_paths:
-        src_path_sanitized = src_path.replace('_COMPILER_ARCH_', _COMPILER_ARCH_ )
-
-        src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path_sanitized)
-        dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, _COMPILER_ARCH_, dst_path)
-
-        copy_files_in_dir(src_abs_path, dst_abs_path)
-
-
-def copy_files():
-    # Copy Secure Files
-    for compiler in _COMPILERS_:
-        for arch in _ARCH_S_:
-            if is_supported_config(compiler, arch):
-                copy_files_for_compiler_and_arch(compiler, arch, _SECURE_FILE_PATHS_, 'secure')
-
-    # Copy Non-Secure Files
-    for compiler in _COMPILERS_:
-        for arch in _ARCH_NS_:
-            if is_supported_config(compiler, arch):
-                copy_files_for_compiler_and_arch(compiler, arch, _NONSECURE_FILE_PATHS_, 'non_secure')
-
-
-def main():
-    copy_files()
-
-
-if __name__ == '__main__':
-    main()
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/ReadMe.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/ReadMe.txt
deleted file mode 100644
index c74a534..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/ReadMe.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
-Do not use the files located here!  These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
-FreeRTOS release.
-
-If your Cortex-M33 application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
-
-If your Cortex-M33 application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/port.c
deleted file mode 100644
index c2b5b6d..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/port.c
+++ /dev/null
@@ -1,1195 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if ( configENABLE_TRUSTZONE == 1 )
-    /* Secure components includes. */
-    #include "secure_context.h"
-    #include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
-#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
-#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
-#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
-#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
-#ifndef configSYSTICK_CLOCK_HZ
-    #define configSYSTICK_CLOCK_HZ            configCPU_CLOCK_HZ
-    /* Ensure the SysTick is clocked at the same frequency as the core. */
-    #define portNVIC_SYSTICK_CLK_BIT          ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the
- * same a the core. */
-    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE    ( 3UL )
-#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS      ( 20UL )
-#define portCPACR_CP11_POS      ( 22UL )
-
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS     ( 31UL )
-#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS     ( 30UL )
-#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The maximum 24-bit number.
- *
- * It is needed because the systick is a 24-bit counter.
- */
-#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )
-
-/**
- * @brief A fiddle factor to estimate the number of SysTick counts that would
- * have occurred while the SysTick counter is stopped during tickless idle
- * calculations.
- */
-#define portMISSED_COUNTS_FACTOR    ( 45UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR    ( 0x01000000 )
-
-#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
-
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
-    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
-#else
-
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
-    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
-#else
-    #define portTASK_RETURN_ADDRESS    prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS    1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT    0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if ( configENABLE_MPU == 1 )
-
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
-    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_FPU == 1 )
-
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
-    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- *
- * The implementation in this file is weak to allow application writers to
- * change the timer used to generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether the current execution context is interrupt.
- *
- * @return pdTRUE if the current execution context is interrupt, pdFALSE
- * otherwise.
- */
-BaseType_t xPortIsInsideInterrupt( void );
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if ( configENABLE_TRUSTZONE == 1 )
-
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
-    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-
-#if ( configUSE_TICKLESS_IDLE == 1 )
-
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
-    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
-
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
-    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
-
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
-    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TICKLESS_IDLE == 1 )
-    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-    {
-        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-        TickType_t xModifiableIdleTime;
-
-        /* Make sure the SysTick reload value does not overflow the counter. */
-        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-        {
-            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-        }
-
-        /* Stop the SysTick momentarily. The time the SysTick is stopped for is
-         * accounted for as best it can be, but using the tickless mode will
-         * inevitably result in some tiny drift of the time maintained by the
-         * kernel with respect to calendar time. */
-        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-        /* Calculate the reload value required to wait xExpectedIdleTime
-         * tick periods. -1 is used because this code will execute part way
-         * through one of the tick periods. */
-        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
-        if( ulReloadValue > ulStoppedTimerCompensation )
-        {
-            ulReloadValue -= ulStoppedTimerCompensation;
-        }
-
-        /* Enter a critical section but don't use the taskENTER_CRITICAL()
-         * method as that will mask interrupts that should exit sleep mode. */
-        __asm volatile ( "cpsid i" ::: "memory" );
-        __asm volatile ( "dsb" );
-        __asm volatile ( "isb" );
-
-        /* If a context switch is pending or a task is waiting for the scheduler
-         * to be un-suspended then abandon the low power entry. */
-        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-        {
-            /* Restart from whatever is left in the count register to complete
-             * this tick period. */
-            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-            /* Restart SysTick. */
-            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-            /* Reset the reload register to the value required for normal tick
-             * periods. */
-            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-            /* Re-enable interrupts - see comments above the cpsid instruction()
-             * above. */
-            __asm volatile ( "cpsie i" ::: "memory" );
-        }
-        else
-        {
-            /* Set the new reload value. */
-            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-            /* Clear the SysTick count flag and set the count value back to
-             * zero. */
-            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-            /* Restart SysTick. */
-            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-            /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
-             * set its parameter to 0 to indicate that its implementation
-             * contains its own wait for interrupt or wait for event
-             * instruction, and so wfi should not be executed again. However,
-             * the original expected idle time variable must remain unmodified,
-             * so a copy is taken. */
-            xModifiableIdleTime = xExpectedIdleTime;
-            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-
-            if( xModifiableIdleTime > 0 )
-            {
-                __asm volatile ( "dsb" ::: "memory" );
-                __asm volatile ( "wfi" );
-                __asm volatile ( "isb" );
-            }
-
-            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-            /* Re-enable interrupts to allow the interrupt that brought the MCU
-             * out of sleep mode to execute immediately. See comments above
-             * the cpsid instruction above. */
-            __asm volatile ( "cpsie i" ::: "memory" );
-            __asm volatile ( "dsb" );
-            __asm volatile ( "isb" );
-
-            /* Disable interrupts again because the clock is about to be stopped
-             * and interrupts that execute while the clock is stopped will
-             * increase any slippage between the time maintained by the RTOS and
-             * calendar time. */
-            __asm volatile ( "cpsid i" ::: "memory" );
-            __asm volatile ( "dsb" );
-            __asm volatile ( "isb" );
-
-            /* Disable the SysTick clock without reading the
-             * portNVIC_SYSTICK_CTRL_REG register to ensure the
-             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
-             * Again, the time the SysTick is stopped for is accounted for as
-             * best it can be, but using the tickless mode will inevitably
-             * result in some tiny drift of the time maintained by the kernel
-             * with respect to calendar time*/
-            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-            /* Determine if the SysTick clock has already counted to zero and
-             * been set back to the current reload value (the reload back being
-             * correct for the entire expected idle time) or if the SysTick is
-             * yet to count to zero (in which case an interrupt other than the
-             * SysTick must have brought the system out of sleep mode). */
-            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-            {
-                uint32_t ulCalculatedLoadValue;
-
-                /* The tick interrupt is already pending, and the SysTick count
-                 * reloaded with ulReloadValue.  Reset the
-                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-                 * period. */
-                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-                /* Don't allow a tiny value, or values that have somehow
-                 * underflowed because the post sleep hook did something
-                 * that took too long. */
-                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-                {
-                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-                }
-
-                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-                /* As the pending tick will be processed as soon as this
-                 * function exits, the tick value maintained by the tick is
-                 * stepped forward by one less than the time spent waiting. */
-                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-            }
-            else
-            {
-                /* Something other than the tick interrupt ended the sleep.
-                 * Work out how long the sleep lasted rounded to complete tick
-                 * periods (not the ulReload value which accounted for part
-                 * ticks). */
-                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-                /* How many complete tick periods passed while the processor
-                 * was waiting? */
-                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-                /* The reload value is set to whatever fraction of a single tick
-                 * period remains. */
-                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-            }
-
-            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-             * value. */
-            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-            vTaskStepTick( ulCompleteTickPeriods );
-            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-            /* Exit with interrupts enabled. */
-            __asm volatile ( "cpsie i" ::: "memory" );
-        }
-    }
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-    /* Calculate the constants required to configure the tick interrupt. */
-    #if ( configUSE_TICKLESS_IDLE == 1 )
-        {
-            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-        }
-    #endif /* configUSE_TICKLESS_IDLE */
-
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
-    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-    /* Configure SysTick to interrupt at the requested rate. */
-    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-    volatile uint32_t ulDummy = 0UL;
-
-    /* A function that implements a task must not exit or attempt to return to
-     * its caller as there is nothing to return to. If a task wants to exit it
-     * should instead call vTaskDelete( NULL ). Artificially force an assert()
-     * to be triggered if configASSERT() is defined, then stop here so
-     * application writers can catch the error. */
-    configASSERT( ulCriticalNesting == ~0UL );
-    portDISABLE_INTERRUPTS();
-
-    while( ulDummy == 0 )
-    {
-        /* This file calls prvTaskExitError() after the scheduler has been
-         * started to remove a compiler warning about the function being
-         * defined but never called.  ulDummy is used purely to quieten other
-         * warnings about code appearing after this function is called - making
-         * ulDummy volatile makes the compiler think the function could return
-         * and therefore not output an 'unreachable code' warning for code that
-         * appears after it. */
-    }
-}
-/*-----------------------------------------------------------*/
-
-#if ( configENABLE_MPU == 1 )
-    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-    {
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __privileged_functions_start__;
-            extern uint32_t * __privileged_functions_end__;
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-            extern uint32_t * __unprivileged_flash_start__;
-            extern uint32_t * __unprivileged_flash_end__;
-            extern uint32_t * __privileged_sram_start__;
-            extern uint32_t * __privileged_sram_end__;
-        #else /* if defined( __ARMCC_VERSION ) */
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __privileged_functions_start__[];
-            extern uint32_t __privileged_functions_end__[];
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-            extern uint32_t __unprivileged_flash_start__[];
-            extern uint32_t __unprivileged_flash_end__[];
-            extern uint32_t __privileged_sram_start__[];
-            extern uint32_t __privileged_sram_end__[];
-        #endif /* defined( __ARMCC_VERSION ) */
-
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
-
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
-
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
-
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
-
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
-    }
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if ( configENABLE_FPU == 1 )
-    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-    {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            {
-                /* Enable non-secure access to the FPU. */
-                SecureInit_EnableNSFPUAccess();
-            }
-        #endif /* configENABLE_TRUSTZONE */
-
-        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-         * unprivileged code should be able to access FPU. CP11 should be
-         * programmed to the same value as CP10. */
-        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-                            );
-
-        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
-         * context on exception entry and restore on exception return.
-         * LSPEN = 1 ==> Enable lazy context save of FP state. */
-        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-    }
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-    /* Set a PendSV to request a context switch. */
-    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-
-    /* Barriers are normally not required but do ensure the code is
-     * completely within the specified behaviour for the architecture. */
-    __asm volatile ( "dsb" ::: "memory" );
-    __asm volatile ( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-    portDISABLE_INTERRUPTS();
-    ulCriticalNesting++;
-
-    /* Barriers are normally not required but do ensure the code is
-     * completely within the specified behaviour for the architecture. */
-    __asm volatile ( "dsb" ::: "memory" );
-    __asm volatile ( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-    configASSERT( ulCriticalNesting );
-    ulCriticalNesting--;
-
-    if( ulCriticalNesting == 0 )
-    {
-        portENABLE_INTERRUPTS();
-    }
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulPreviousMask;
-
-    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-    {
-        /* Increment the RTOS tick. */
-        if( xTaskIncrementTick() != pdFALSE )
-        {
-            /* Pend a context switch. */
-            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-        }
-    }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-    #if ( configENABLE_MPU == 1 )
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* defined( __ARMCC_VERSION ) */
-    #endif /* configENABLE_MPU */
-
-    uint32_t ulPC;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
-        uint32_t ulR0, ulR1;
-        extern TaskHandle_t pxCurrentTCB;
-        #if ( configENABLE_MPU == 1 )
-            uint32_t ulControl, ulIsTaskPrivileged;
-        #endif /* configENABLE_MPU */
-    #endif /* configENABLE_TRUSTZONE */
-    uint8_t ucSVCNumber;
-
-    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
-     * R12, LR, PC, xPSR. */
-    ulPC = pulCallerStackAddress[ 6 ];
-    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
-
-    switch( ucSVCNumber )
-    {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
-
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-
-                #if ( configENABLE_MPU == 1 )
-                    {
-                        /* Read the CONTROL register value. */
-                        __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-                        /* The task that raised the SVC is privileged if Bit[0]
-                         * in the CONTROL register is 0. */
-                        ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-                        /* Allocate and load a context for the secure task. */
-                        xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                    }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                    {
-                        /* Allocate and load a context for the secure task. */
-                        xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                    }
-                #endif /* configENABLE_MPU */
-
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
-
-            case portSVC_FREE_SECURE_CONTEXT:
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
-
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
-
-        case portSVC_START_SCHEDULER:
-            #if ( configENABLE_TRUSTZONE == 1 )
-                {
-                    /* De-prioritize the non-secure exceptions so that the
-                     * non-secure pendSV runs at the lowest priority. */
-                    SecureInit_DePrioritizeNSExceptions();
-
-                    /* Initialize the secure context management system. */
-                    SecureContext_Init();
-                }
-            #endif /* configENABLE_TRUSTZONE */
-
-            #if ( configENABLE_FPU == 1 )
-                {
-                    /* Setup the Floating Point Unit (FPU). */
-                    prvSetupFPU();
-                }
-            #endif /* configENABLE_FPU */
-
-            /* Setup the context of the first task so that the first task starts
-             * executing. */
-            vRestoreContextOfFirstTask();
-            break;
-
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_RAISE_PRIVILEGE:
-
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* configENABLE_MPU */
-
-        default:
-            /* Incorrect SVC call. */
-            configASSERT( pdFALSE );
-    }
-}
-/*-----------------------------------------------------------*/
-/* *INDENT-OFF* */
-#if ( configENABLE_MPU == 1 )
-    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                         StackType_t * pxEndOfStack,
-                                         TaskFunction_t pxCode,
-                                         void * pvParameters,
-                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                         StackType_t * pxEndOfStack,
-                                         TaskFunction_t pxCode,
-                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-/* *INDENT-ON* */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
-        {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-            *pxTopOfStack = portINITIAL_EXC_RETURN;
-
-            #if ( configENABLE_MPU == 1 )
-                {
-                    pxTopOfStack--;
-
-                    if( xRunPrivileged == pdTRUE )
-                    {
-                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
-                    }
-                    else
-                    {
-                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
-                    }
-                }
-            #endif /* configENABLE_MPU */
-
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-            #if ( configENABLE_TRUSTZONE == 1 )
-                {
-                    pxTopOfStack--;
-                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-                }
-            #endif /* configENABLE_TRUSTZONE */
-        }
-    #else /* portPRELOAD_REGISTERS */
-        {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */
-            pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */
-
-            #if ( configENABLE_MPU == 1 )
-                {
-                    pxTopOfStack--;
-
-                    if( xRunPrivileged == pdTRUE )
-                    {
-                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
-                    }
-                    else
-                    {
-                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
-                    }
-                }
-            #endif /* configENABLE_MPU */
-
-            pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-            #if ( configENABLE_TRUSTZONE == 1 )
-                {
-                    pxTopOfStack--;
-                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-                }
-            #endif /* configENABLE_TRUSTZONE */
-        }
-    #endif /* portPRELOAD_REGISTERS */
-
-    return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
-    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
-
-    #if ( configENABLE_MPU == 1 )
-        {
-            /* Setup the Memory Protection Unit (MPU). */
-            prvSetupMPU();
-        }
-    #endif /* configENABLE_MPU */
-
-    /* Start the timer that generates the tick ISR. Interrupts are disabled
-     * here already. */
-    vPortSetupTimerInterrupt();
-
-    /* Initialize the critical nesting count ready for the first task. */
-    ulCriticalNesting = 0;
-
-    /* Start the first task. */
-    vStartFirstTask();
-
-    /* Should never get here as the tasks will now be executing. Call the task
-     * exit error function to prevent compiler warnings about a static function
-     * not being called in the case that the application writer overrides this
-     * functionality by defining configTASK_RETURN_ADDRESS. Call
-     * vTaskSwitchContext() so link time optimization does not remove the
-     * symbol. */
-    vTaskSwitchContext();
-    prvTaskExitError();
-
-    /* Should not get here. */
-    return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-    /* Not implemented in ports where there is nothing to return to.
-     * Artificially force an assert. */
-    configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if ( configENABLE_MPU == 1 )
-    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
-                                    const struct xMEMORY_REGION * const xRegions,
-                                    StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
-    {
-        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-        int32_t lIndex = 0;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __privileged_sram_start__;
-            extern uint32_t * __privileged_sram_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __privileged_sram_start__[];
-            extern uint32_t __privileged_sram_end__[];
-        #endif /* defined( __ARMCC_VERSION ) */
-
-        /* Setup MAIR0. */
-        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-        /* This function is called automatically when the task is created - in
-         * which case the stack region parameters will be valid.  At all other
-         * times the stack parameters will not be valid and it is assumed that
-         * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
-        {
-            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-
-            /* If the stack is within the privileged SRAM, do not protect it
-             * using a separate MPU region. This is needed because privileged
-             * SRAM is already protected using an MPU region and ARMv8-M does
-             * not allow overlapping MPU regions. */
-            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
-                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
-            {
-                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
-                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
-            }
-            else
-            {
-                /* Define the region that allows access to the stack. */
-                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
-                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
-
-                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
-                                                             ( portMPU_REGION_NON_SHAREABLE ) |
-                                                             ( portMPU_REGION_READ_WRITE ) |
-                                                             ( portMPU_REGION_EXECUTE_NEVER );
-
-                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
-                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |
-                                                             ( portMPU_RLAR_REGION_ENABLE );
-            }
-        }
-
-        /* User supplied configurable regions. */
-        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-        {
-            /* If xRegions is NULL i.e. the task has not specified any MPU
-             * region, the else part ensures that all the configurable MPU
-             * regions are invalidated. */
-            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-            {
-                /* Translate the generic region definition contained in xRegions
-                 * into the ARMv8 specific MPU settings that are then stored in
-                 * xMPUSettings. */
-                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
-
-                /* Start address. */
-                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
-                                                                          ( portMPU_REGION_NON_SHAREABLE );
-
-                /* RO/RW. */
-                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-                {
-                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-                }
-                else
-                {
-                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-                }
-
-                /* XN. */
-                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-                {
-                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-                }
-
-                /* End Address. */
-                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
-                                                                          ( portMPU_RLAR_REGION_ENABLE );
-
-                /* Normal memory/ Device memory. */
-                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-                {
-                    /* Attr1 in MAIR0 is configured as device memory. */
-                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-                }
-                else
-                {
-                    /* Attr1 in MAIR0 is configured as normal memory. */
-                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-                }
-            }
-            else
-            {
-                /* Invalidate the region. */
-                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-            }
-
-            lIndex++;
-        }
-    }
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortIsInsideInterrupt( void )
-{
-    uint32_t ulCurrentInterrupt;
-    BaseType_t xReturn;
-
-    /* Obtain the number of the currently executing interrupt. Interrupt Program
-     * Status Register (IPSR) holds the exception number of the currently-executing
-     * exception or zero for Thread mode.*/
-    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
-    if( ulCurrentInterrupt == 0 )
-    {
-        xReturn = pdFALSE;
-    }
-    else
-    {
-        xReturn = pdTRUE;
-    }
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
deleted file mode 100644
index 4cbfa22..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	.syntax unified									\n"
-        "													\n"
-        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr  r3, [r2]									\n"/* Read pxCurrentTCB. */
-        "	ldr  r0, [r3]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "													\n"
-        #if ( configENABLE_MPU == 1 )
-            "	dmb											\n"/* Complete outstanding transfers before disabling MPU. */
-            "	ldr r2, xMPUCTRLConst2						\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-            "	ldr r4, [r2]								\n"/* Read the value of MPU_CTRL. */
-            "	bic r4, #1									\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-            "	str r4, [r2]								\n"/* Disable MPU. */
-            "												\n"
-            "	adds r3, #4									\n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-            "	ldr  r4, [r3]								\n"/* r4 = *r3 i.e. r4 = MAIR0. */
-            "	ldr  r2, xMAIR0Const2						\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
-            "	str  r4, [r2]								\n"/* Program MAIR0. */
-            "	ldr  r2, xRNRConst2							\n"/* r2 = 0xe000ed98 [Location of RNR]. */
-            "	movs r4, #4									\n"/* r4 = 4. */
-            "	str  r4, [r2]								\n"/* Program RNR = 4. */
-            "	adds r3, #4									\n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-            "	ldr  r2, xRBARConst2						\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
-            "	ldmia r3!, {r4-r11}							\n"/* Read 4 set of RBAR/RLAR registers from TCB. */
-            "	stmia r2!, {r4-r11}							\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
-            "												\n"
-            "	ldr r2, xMPUCTRLConst2						\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-            "	ldr r4, [r2]								\n"/* Read the value of MPU_CTRL. */
-            "	orr r4, #1									\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-            "	str r4, [r2]								\n"/* Enable MPU. */
-            "	dsb											\n"/* Force memory writes before continuing. */
-        #endif /* configENABLE_MPU */
-        "													\n"
-        #if ( configENABLE_MPU == 1 )
-            "	ldm  r0!, {r1-r4}							\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-            "	ldr  r5, xSecureContextConst2				\n"
-            "	str  r1, [r5]								\n"/* Set xSecureContext to this task's value for the same. */
-            "	msr  psplim, r2								\n"/* Set this task's PSPLIM value. */
-            "	msr  control, r3							\n"/* Set this task's CONTROL value. */
-            "	adds r0, #32								\n"/* Discard everything up to r0. */
-            "	msr  psp, r0								\n"/* This is now the new top of stack to use in the task. */
-            "	isb											\n"
-            "	mov  r0, #0									\n"
-            "	msr  basepri, r0							\n"/* Ensure that interrupts are enabled when the first task starts. */
-            "	bx   r4										\n"/* Finally, branch to EXC_RETURN. */
-        #else /* configENABLE_MPU */
-            "	ldm  r0!, {r1-r3}							\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-            "	ldr  r4, xSecureContextConst2				\n"
-            "	str  r1, [r4]								\n"/* Set xSecureContext to this task's value for the same. */
-            "	msr  psplim, r2								\n"/* Set this task's PSPLIM value. */
-            "	movs r1, #2									\n"/* r1 = 2. */
-            "	msr  CONTROL, r1							\n"/* Switch to use PSP in the thread mode. */
-            "	adds r0, #32								\n"/* Discard everything up to r0. */
-            "	msr  psp, r0								\n"/* This is now the new top of stack to use in the task. */
-            "	isb											\n"
-            "	mov  r0, #0									\n"
-            "	msr  basepri, r0							\n"/* Ensure that interrupts are enabled when the first task starts. */
-            "	bx   r3										\n"/* Finally, branch to EXC_RETURN. */
-        #endif /* configENABLE_MPU */
-        "													\n"
-        "	.align 4										\n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-        "xSecureContextConst2: .word xSecureContext			\n"
-        #if ( configENABLE_MPU == 1 )
-            "xMPUCTRLConst2: .word 0xe000ed94				\n"
-            "xMAIR0Const2: .word 0xe000edc0					\n"
-            "xRNRConst2: .word 0xe000ed98					\n"
-            "xRBARConst2: .word 0xe000ed9c					\n"
-        #endif /* configENABLE_MPU */
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-    __asm volatile
-    (
-        "	mrs r0, control									\n"/* r0 = CONTROL. */
-        "	tst r0, #1										\n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-        "	ite ne											\n"
-        "	movne r0, #0									\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "	moveq r0, #1									\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "	bx lr											\n"/* Return. */
-        "													\n"
-        "	.align 4										\n"
-        ::: "r0", "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	mrs r0, control									\n"/* Read the CONTROL register. */
-        "	bic r0, #1										\n"/* Clear the bit 0. */
-        "	msr control, r0									\n"/* Write back the new CONTROL value. */
-        "	bx lr											\n"/* Return to the caller. */
-        ::: "r0", "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-    __asm volatile
-    (
-        "	mrs r0, control									\n"/* r0 = CONTROL. */
-        "	orr r0, #1										\n"/* r0 = r0 | 1. */
-        "	msr control, r0									\n"/* CONTROL = r0. */
-        "	bx lr											\n"/* Return to the caller. */
-        ::: "r0", "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
-        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
-        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
-        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
-        "	cpsie i											\n"/* Globally enable interrupts. */
-        "	cpsie f											\n"
-        "	dsb												\n"
-        "	isb												\n"
-        "	svc %0											\n"/* System call to start the first task. */
-        "	nop												\n"
-        "													\n"
-        "   .align 4										\n"
-        "xVTORConst: .word 0xe000ed08						\n"
-        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	mrs r0, basepri									\n"/* r0 = basepri. Return original basepri value. */
-        "	mov r1, %0										\n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "	msr basepri, r1									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "	dsb												\n"
-        "	isb												\n"
-        "	bx lr											\n"/* Return. */
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	msr basepri, r0									\n"/* basepri = ulMask. */
-        "	dsb												\n"
-        "	isb												\n"
-        "	bx lr											\n"/* Return. */
-        ::: "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	.syntax unified									\n"
-        "	.extern SecureContext_SaveContext				\n"
-        "	.extern SecureContext_LoadContext				\n"
-        "													\n"
-        "	ldr r3, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "	ldr r0, [r3]									\n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-        "	mrs r2, psp										\n"/* Read PSP in r2. */
-        "													\n"
-        "	cbz r0, save_ns_context							\n"/* No secure context to save. */
-        "	push {r0-r2, r14}								\n"
-        "	bl SecureContext_SaveContext					\n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "	pop {r0-r3}										\n"/* LR is now in r3. */
-        "	mov lr, r3										\n"/* LR = r3. */
-        "	lsls r1, r3, #25								\n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "	bpl save_ns_context								\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "													\n"
-        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB.*/
-        #if ( configENABLE_MPU == 1 )
-            "	subs r2, r2, #16							\n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
-            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
-            "	mrs r3, control								\n"/* r3 = CONTROL. */
-            "	mov r4, lr									\n"/* r4 = LR/EXC_RETURN. */
-            "	stmia r2!, {r0, r1, r3, r4}					\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-        #else /* configENABLE_MPU */
-            "	subs r2, r2, #12							\n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
-            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
-            "	mov r3, lr									\n"/* r3 = LR/EXC_RETURN. */
-            "	stmia r2!, {r0, r1, r3}						\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        #endif /* configENABLE_MPU */
-        "	b select_next_task								\n"
-        "													\n"
-        " save_ns_context:									\n"
-        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB. */
-        #if ( configENABLE_FPU == 1 )
-            "	tst lr, #0x10								\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-            "	it eq										\n"
-            "	vstmdbeq r2!, {s16-s31}						\n"/* Store the FPU registers which are not saved automatically. */
-        #endif /* configENABLE_FPU */
-        #if ( configENABLE_MPU == 1 )
-            "	subs r2, r2, #48							\n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
-            "	adds r2, r2, #16							\n"/* r2 = r2 + 16. */
-            "	stm r2, {r4-r11}							\n"/* Store the registers that are not saved automatically. */
-            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
-            "	mrs r3, control								\n"/* r3 = CONTROL. */
-            "	mov r4, lr									\n"/* r4 = LR/EXC_RETURN. */
-            "	subs r2, r2, #16							\n"/* r2 = r2 - 16. */
-            "	stmia r2!, {r0, r1, r3, r4}					\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-        #else /* configENABLE_MPU */
-            "	subs r2, r2, #44							\n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
-            "	adds r2, r2, #12							\n"/* r2 = r2 + 12. */
-            "	stm r2, {r4-r11}							\n"/* Store the registers that are not saved automatically. */
-            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
-            "	mov r3, lr									\n"/* r3 = LR/EXC_RETURN. */
-            "	subs r2, r2, #12							\n"/* r2 = r2 - 12. */
-            "	stmia r2!, {r0, r1, r3}						\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        #endif /* configENABLE_MPU */
-        "													\n"
-        " select_next_task:									\n"
-        "	mov r0, %0										\n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "	msr basepri, r0									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "	dsb												\n"
-        "	isb												\n"
-        "	bl vTaskSwitchContext							\n"
-        "	mov r0, #0										\n"/* r0 = 0. */
-        "	msr basepri, r0									\n"/* Enable interrupts. */
-        "													\n"
-        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB. */
-        "	ldr r2, [r1]									\n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-        "													\n"
-        #if ( configENABLE_MPU == 1 )
-            "	dmb											\n"/* Complete outstanding transfers before disabling MPU. */
-            "	ldr r3, xMPUCTRLConst						\n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
-            "	ldr r4, [r3]								\n"/* Read the value of MPU_CTRL. */
-            "	bic r4, #1									\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-            "	str r4, [r3]								\n"/* Disable MPU. */
-            "												\n"
-            "	adds r1, #4									\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-            "	ldr r4, [r1]								\n"/* r4 = *r1 i.e. r4 = MAIR0. */
-            "	ldr r3, xMAIR0Const							\n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
-            "	str r4, [r3]								\n"/* Program MAIR0. */
-            "	ldr r3, xRNRConst							\n"/* r3 = 0xe000ed98 [Location of RNR]. */
-            "	movs r4, #4									\n"/* r4 = 4. */
-            "	str r4, [r3]								\n"/* Program RNR = 4. */
-            "	adds r1, #4									\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-            "	ldr r3, xRBARConst							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
-            "	ldmia r1!, {r4-r11}							\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
-            "	stmia r3!, {r4-r11}							\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
-            "												\n"
-            "	ldr r3, xMPUCTRLConst						\n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
-            "	ldr r4, [r3]								\n"/* Read the value of MPU_CTRL. */
-            "	orr r4, #1									\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-            "	str r4, [r3]								\n"/* Enable MPU. */
-            "	dsb											\n"/* Force memory writes before continuing. */
-        #endif /* configENABLE_MPU */
-        "													\n"
-        #if ( configENABLE_MPU == 1 )
-            "	ldmia r2!, {r0, r1, r3, r4}					\n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
-            "	msr psplim, r1								\n"/* Restore the PSPLIM register value for the task. */
-            "	msr control, r3								\n"/* Restore the CONTROL register value for the task. */
-            "	mov lr, r4									\n"/* LR = r4. */
-            "	ldr r3, xSecureContextConst					\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "	str r0, [r3]								\n"/* Restore the task's xSecureContext. */
-            "	cbz r0, restore_ns_context					\n"/* If there is no secure context for the task, restore the non-secure context. */
-            "	ldr r3, pxCurrentTCBConst					\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "	ldr r1, [r3]								\n"/* Read pxCurrentTCB. */
-            "	push {r2, r4}								\n"
-            "	bl SecureContext_LoadContext				\n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "	pop {r2, r4}								\n"
-            "	mov lr, r4									\n"/* LR = r4. */
-            "	lsls r1, r4, #25							\n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "	bpl restore_ns_context						\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "	msr psp, r2									\n"/* Remember the new top of stack for the task. */
-            "	bx lr										\n"
-        #else /* configENABLE_MPU */
-            "	ldmia r2!, {r0, r1, r4}						\n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-            "	msr psplim, r1								\n"/* Restore the PSPLIM register value for the task. */
-            "	mov lr, r4									\n"/* LR = r4. */
-            "	ldr r3, xSecureContextConst					\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "	str r0, [r3]								\n"/* Restore the task's xSecureContext. */
-            "	cbz r0, restore_ns_context					\n"/* If there is no secure context for the task, restore the non-secure context. */
-            "	ldr r3, pxCurrentTCBConst					\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "	ldr r1, [r3]								\n"/* Read pxCurrentTCB. */
-            "	push {r2, r4}								\n"
-            "	bl SecureContext_LoadContext				\n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "	pop {r2, r4}								\n"
-            "	mov lr, r4									\n"/* LR = r4. */
-            "	lsls r1, r4, #25							\n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "	bpl restore_ns_context						\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "	msr psp, r2									\n"/* Remember the new top of stack for the task. */
-            "	bx lr										\n"
-        #endif /* configENABLE_MPU */
-        "													\n"
-        " restore_ns_context:								\n"
-        "	ldmia r2!, {r4-r11}								\n"/* Restore the registers that are not automatically restored. */
-        #if ( configENABLE_FPU == 1 )
-            "	tst lr, #0x10								\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-            "	it eq										\n"
-            "	vldmiaeq r2!, {s16-s31}						\n"/* Restore the FPU registers which are not restored automatically. */
-        #endif /* configENABLE_FPU */
-        "	msr psp, r2										\n"/* Remember the new top of stack for the task. */
-        "	bx lr											\n"
-        "													\n"
-        "	.align 4										\n"
-        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
-        "xSecureContextConst: .word xSecureContext			\n"
-        #if ( configENABLE_MPU == 1 )
-            "xMPUCTRLConst: .word 0xe000ed94				\n"
-            "xMAIR0Const: .word 0xe000edc0					\n"
-            "xRNRConst: .word 0xe000ed98					\n"
-            "xRBARConst: .word 0xe000ed9c					\n"
-        #endif /* configENABLE_MPU */
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	tst lr, #4										\n"
-        "	ite eq											\n"
-        "	mrseq r0, msp									\n"
-        "	mrsne r0, psp									\n"
-        "	ldr r1, svchandler_address_const				\n"
-        "	bx r1											\n"
-        "													\n"
-        "	.align 4										\n"
-        "svchandler_address_const: .word vPortSVCHandler_C	\n"
-    );
-}
-/*-----------------------------------------------------------*/
-
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
-{
-    __asm volatile
-    (
-        "	svc %0											\n"/* Secure context is allocated in the supervisor call. */
-        "	bx lr											\n"/* Return. */
-        ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	ldr r2, [r0]									\n"/* The first item in the TCB is the top of the stack. */
-        "	ldr r1, [r2]									\n"/* The first item on the stack is the task's xSecureContext. */
-        "	cmp r1, #0										\n"/* Raise svc if task's xSecureContext is not NULL. */
-        "	it ne											\n"
-        "	svcne %0										\n"/* Secure context is freed in the supervisor call. */
-        "	bx lr											\n"/* Return. */
-        ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
deleted file mode 100644
index 6131ac8..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-    #define PORTMACRO_H
-
-    #ifdef __cplusplus
-        extern "C" {
-    #endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-    #ifndef configENABLE_FPU
-        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-    #endif /* configENABLE_FPU */
-
-    #ifndef configENABLE_MPU
-        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-    #endif /* configENABLE_MPU */
-
-    #ifndef configENABLE_TRUSTZONE
-        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-    #endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
-
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
-
-    #if ( configUSE_16_BIT_TICKS == 1 )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #else
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-    #define portARCH_NAME                      "Cortex-M33"
-    #define portSTACK_GROWTH                   ( -1 )
-    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT                 8
-    #define portNOP()
-    #define portINLINE                         __inline
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
-    #endif
-    #define portHAS_STACK_OVERFLOW_CHECKING    1
-    #define portDONT_DISCARD                   __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-    extern BaseType_t xPortIsInsideInterrupt( void );
-
-    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
-        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-    #endif /* configENABLE_TRUSTZONE */
-
-    #if ( configENABLE_MPU == 1 )
-        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-    #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-    #if ( configENABLE_MPU == 1 )
-        #define portUSING_MPU_WRAPPERS    1
-        #define portPRIVILEGE_BIT         ( 0x80000000UL )
-    #else
-        #define portPRIVILEGE_BIT         ( 0x0UL )
-    #endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
-    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
-    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
-    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
-    #define portSTACK_REGION                              ( 4UL )
-    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
-    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
-    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
-    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
-    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
-    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
-    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
-    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
-    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
-
-    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
-    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
-    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
-    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
-
-    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-    typedef struct MPURegionSettings
-    {
-        uint32_t ulRBAR; /**< RBAR for the region. */
-        uint32_t ulRLAR; /**< RLAR for the region. */
-    } MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-    typedef struct MPU_SETTINGS
-    {
-        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-    } xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
-    #define portSVC_FREE_SECURE_CONTEXT        1
-    #define portSVC_START_SCHEDULER            2
-    #define portSVC_RAISE_PRIVILEGE            3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-    #define portYIELD()                                 vPortYield()
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
-    #define portDISABLE_INTERRUPTS()                  ulSetInterruptMask()
-    #define portENABLE_INTERRUPTS()                   vClearInterruptMask( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Tickless idle/low power functionality.
- */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
-    #if ( configENABLE_TRUSTZONE == 1 )
-
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
-        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
-
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
-        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-    #else
-        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-        #define portCLEAN_UP_TCB( pxTCB )
-    #endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-    #if ( configENABLE_MPU == 1 )
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-        #define portIS_PRIVILEGED()      xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
-        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
-        #define portRESET_PRIVILEGE()    vResetPrivilege()
-    #else
-        #define portIS_PRIVILEGED()
-        #define portRAISE_PRIVILEGE()
-        #define portRESET_PRIVILEGE()
-    #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-    #ifdef __cplusplus
-        }
-    #endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
deleted file mode 100644
index 4a4cc05..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	.syntax unified									\n"
-        "													\n"
-        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr  r1, [r2]									\n"/* Read pxCurrentTCB. */
-        "	ldr  r0, [r1]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "													\n"
-        #if ( configENABLE_MPU == 1 )
-            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
-            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
-            "	bic r4, #1										\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-            "	str r4, [r2]									\n"/* Disable MPU. */
-            "													\n"
-            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-            "	ldr  r3, [r1]									\n"/* r3 = *r1 i.e. r3 = MAIR0. */
-            "	ldr  r2, xMAIR0Const2							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
-            "	str  r3, [r2]									\n"/* Program MAIR0. */
-            "	ldr  r2, xRNRConst2								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
-            "	movs r3, #4										\n"/* r3 = 4. */
-            "	str  r3, [r2]									\n"/* Program RNR = 4. */
-            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-            "	ldr  r2, xRBARConst2							\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
-            "	ldmia r1!, {r4-r11}								\n"/* Read 4 set of RBAR/RLAR registers from TCB. */
-            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
-            "													\n"
-            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
-            "	orr r4, #1										\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-            "	str r4, [r2]									\n"/* Enable MPU. */
-            "	dsb												\n"/* Force memory writes before continuing. */
-        #endif /* configENABLE_MPU */
-        "													\n"
-        #if ( configENABLE_MPU == 1 )
-            "	ldm  r0!, {r1-r3}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
-            "	msr  control, r2								\n"/* Set this task's CONTROL value. */
-            "	adds r0, #32									\n"/* Discard everything up to r0. */
-            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
-            "	isb												\n"
-            "	mov  r0, #0										\n"
-            "	msr  basepri, r0								\n"/* Ensure that interrupts are enabled when the first task starts. */
-            "	bx   r3											\n"/* Finally, branch to EXC_RETURN. */
-        #else /* configENABLE_MPU */
-            "	ldm  r0!, {r1-r2}								\n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
-            "	movs r1, #2										\n"/* r1 = 2. */
-            "	msr  CONTROL, r1								\n"/* Switch to use PSP in the thread mode. */
-            "	adds r0, #32									\n"/* Discard everything up to r0. */
-            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
-            "	isb												\n"
-            "	mov  r0, #0										\n"
-            "	msr  basepri, r0								\n"/* Ensure that interrupts are enabled when the first task starts. */
-            "	bx   r2											\n"/* Finally, branch to EXC_RETURN. */
-        #endif /* configENABLE_MPU */
-        "													\n"
-        "	.align 4										\n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-        #if ( configENABLE_MPU == 1 )
-            "xMPUCTRLConst2: .word 0xe000ed94					\n"
-            "xMAIR0Const2: .word 0xe000edc0						\n"
-            "xRNRConst2: .word 0xe000ed98						\n"
-            "xRBARConst2: .word 0xe000ed9c						\n"
-        #endif /* configENABLE_MPU */
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-    __asm volatile
-    (
-        "	mrs r0, control									\n"/* r0 = CONTROL. */
-        "	tst r0, #1										\n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-        "	ite ne											\n"
-        "	movne r0, #0									\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "	moveq r0, #1									\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "	bx lr											\n"/* Return. */
-        "													\n"
-        "	.align 4										\n"
-        ::: "r0", "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	mrs  r0, control								\n"/* Read the CONTROL register. */
-        "	bic r0, #1										\n"/* Clear the bit 0. */
-        "	msr  control, r0								\n"/* Write back the new CONTROL value. */
-        "	bx lr											\n"/* Return to the caller. */
-        ::: "r0", "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-    __asm volatile
-    (
-        "	mrs r0, control									\n"/* r0 = CONTROL. */
-        "	orr r0, #1										\n"/* r0 = r0 | 1. */
-        "	msr control, r0									\n"/* CONTROL = r0. */
-        "	bx lr											\n"/* Return to the caller. */
-        ::: "r0", "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
-        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
-        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
-        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
-        "	cpsie i											\n"/* Globally enable interrupts. */
-        "	cpsie f											\n"
-        "	dsb												\n"
-        "	isb												\n"
-        "	svc %0											\n"/* System call to start the first task. */
-        "	nop												\n"
-        "													\n"
-        "   .align 4										\n"
-        "xVTORConst: .word 0xe000ed08						\n"
-        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	mrs r0, basepri									\n"/* r0 = basepri. Return original basepri value. */
-        "	mov r1, %0										\n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "	msr basepri, r1									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "	dsb												\n"
-        "	isb												\n"
-        "	bx lr											\n"/* Return. */
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	msr basepri, r0									\n"/* basepri = ulMask. */
-        "	dsb												\n"
-        "	isb												\n"
-        "	bx lr											\n"/* Return. */
-        ::: "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	.syntax unified									\n"
-        "													\n"
-        "	mrs r0, psp										\n"/* Read PSP in r0. */
-        #if ( configENABLE_FPU == 1 )
-            "	tst lr, #0x10									\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-            "	it eq											\n"
-            "	vstmdbeq r0!, {s16-s31}							\n"/* Store the FPU registers which are not saved automatically. */
-        #endif /* configENABLE_FPU */
-        #if ( configENABLE_MPU == 1 )
-            "	mrs r1, psplim									\n"/* r1 = PSPLIM. */
-            "	mrs r2, control									\n"/* r2 = CONTROL. */
-            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
-            "	stmdb r0!, {r1-r11}								\n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
-        #else /* configENABLE_MPU */
-            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
-            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
-            "	stmdb r0!, {r2-r11}								\n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
-        #endif /* configENABLE_MPU */
-        "													\n"
-        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
-        "	str r0, [r1]									\n"/* Save the new top of stack in TCB. */
-        "													\n"
-        "	mov r0, %0										\n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "	msr basepri, r0									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "	dsb												\n"
-        "	isb												\n"
-        "	bl vTaskSwitchContext							\n"
-        "	mov r0, #0										\n"/* r0 = 0. */
-        "	msr basepri, r0									\n"/* Enable interrupts. */
-        "													\n"
-        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
-        "	ldr r0, [r1]									\n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-        "													\n"
-        #if ( configENABLE_MPU == 1 )
-            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
-            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
-            "	bic r4, #1										\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-            "	str r4, [r2]									\n"/* Disable MPU. */
-            "													\n"
-            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-            "	ldr r3, [r1]									\n"/* r3 = *r1 i.e. r3 = MAIR0. */
-            "	ldr r2, xMAIR0Const								\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
-            "	str r3, [r2]									\n"/* Program MAIR0. */
-            "	ldr r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
-            "	movs r3, #4										\n"/* r3 = 4. */
-            "	str r3, [r2]									\n"/* Program RNR = 4. */
-            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-            "	ldr r2, xRBARConst								\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
-            "	ldmia r1!, {r4-r11}								\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
-            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
-            "													\n"
-            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
-            "	orr r4, #1										\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-            "	str r4, [r2]									\n"/* Enable MPU. */
-            "	dsb												\n"/* Force memory writes before continuing. */
-        #endif /* configENABLE_MPU */
-        "													\n"
-        #if ( configENABLE_MPU == 1 )
-            "	ldmia r0!, {r1-r11}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
-        #else /* configENABLE_MPU */
-            "	ldmia r0!, {r2-r11}								\n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-        #endif /* configENABLE_MPU */
-        "													\n"
-        #if ( configENABLE_FPU == 1 )
-            "	tst r3, #0x10									\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-            "	it eq											\n"
-            "	vldmiaeq r0!, {s16-s31}							\n"/* Restore the FPU registers which are not restored automatically. */
-        #endif /* configENABLE_FPU */
-        "													\n"
-        #if ( configENABLE_MPU == 1 )
-            "	msr psplim, r1									\n"/* Restore the PSPLIM register value for the task. */
-            "	msr control, r2									\n"/* Restore the CONTROL register value for the task. */
-        #else /* configENABLE_MPU */
-            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
-        #endif /* configENABLE_MPU */
-        "	msr psp, r0										\n"/* Remember the new top of stack for the task. */
-        "	bx r3											\n"
-        "													\n"
-        "	.align 4										\n"
-        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
-        #if ( configENABLE_MPU == 1 )
-            "xMPUCTRLConst: .word 0xe000ed94					\n"
-            "xMAIR0Const: .word 0xe000edc0						\n"
-            "xRNRConst: .word 0xe000ed98						\n"
-            "xRBARConst: .word 0xe000ed9c						\n"
-        #endif /* configENABLE_MPU */
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "	tst lr, #4										\n"
-        "	ite eq											\n"
-        "	mrseq r0, msp									\n"
-        "	mrsne r0, psp									\n"
-        "	ldr r1, svchandler_address_const				\n"
-        "	bx r1											\n"
-        "													\n"
-        "	.align 4										\n"
-        "svchandler_address_const: .word vPortSVCHandler_C	\n"
-    );
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
deleted file mode 100644
index 6131ac8..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-    #define PORTMACRO_H
-
-    #ifdef __cplusplus
-        extern "C" {
-    #endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-    #ifndef configENABLE_FPU
-        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-    #endif /* configENABLE_FPU */
-
-    #ifndef configENABLE_MPU
-        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-    #endif /* configENABLE_MPU */
-
-    #ifndef configENABLE_TRUSTZONE
-        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-    #endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
-
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
-
-    #if ( configUSE_16_BIT_TICKS == 1 )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #else
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-    #define portARCH_NAME                      "Cortex-M33"
-    #define portSTACK_GROWTH                   ( -1 )
-    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT                 8
-    #define portNOP()
-    #define portINLINE                         __inline
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
-    #endif
-    #define portHAS_STACK_OVERFLOW_CHECKING    1
-    #define portDONT_DISCARD                   __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-    extern BaseType_t xPortIsInsideInterrupt( void );
-
-    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
-        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-    #endif /* configENABLE_TRUSTZONE */
-
-    #if ( configENABLE_MPU == 1 )
-        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-    #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-    #if ( configENABLE_MPU == 1 )
-        #define portUSING_MPU_WRAPPERS    1
-        #define portPRIVILEGE_BIT         ( 0x80000000UL )
-    #else
-        #define portPRIVILEGE_BIT         ( 0x0UL )
-    #endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
-    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
-    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
-    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
-    #define portSTACK_REGION                              ( 4UL )
-    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
-    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
-    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
-    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
-    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
-    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
-    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
-    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
-    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
-
-    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
-    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
-    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
-    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
-
-    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-    typedef struct MPURegionSettings
-    {
-        uint32_t ulRBAR; /**< RBAR for the region. */
-        uint32_t ulRLAR; /**< RLAR for the region. */
-    } MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-    typedef struct MPU_SETTINGS
-    {
-        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-    } xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
-    #define portSVC_FREE_SECURE_CONTEXT        1
-    #define portSVC_START_SCHEDULER            2
-    #define portSVC_RAISE_PRIVILEGE            3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-    #define portYIELD()                                 vPortYield()
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
-    #define portDISABLE_INTERRUPTS()                  ulSetInterruptMask()
-    #define portENABLE_INTERRUPTS()                   vClearInterruptMask( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Tickless idle/low power functionality.
- */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
-    #if ( configENABLE_TRUSTZONE == 1 )
-
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
-        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
-
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
-        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-    #else
-        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-        #define portCLEAN_UP_TCB( pxTCB )
-    #endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-    #if ( configENABLE_MPU == 1 )
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-        #define portIS_PRIVILEGED()      xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
-        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
-        #define portRESET_PRIVILEGE()    vResetPrivilege()
-    #else
-        #define portIS_PRIVILEGED()
-        #define portRAISE_PRIVILEGE()
-        #define portRESET_PRIVILEGE()
-    #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-    #ifdef __cplusplus
-        }
-    #endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
deleted file mode 100644
index 93110a5..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-/* Including FreeRTOSConfig.h here will cause build errors if the header file
-contains code not understood by the assembler - for example the 'extern' keyword.
-To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
-the code is included in C files but excluded by the preprocessor in assembly
-files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
-#include "FreeRTOSConfig.h"
-
-	EXTERN pxCurrentTCB
-	EXTERN xSecureContext
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-	EXTERN SecureContext_SaveContext
-	EXTERN SecureContext_LoadContext
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vPortAllocateSecureContext
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMask
-	PUBLIC vClearInterruptMask
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-	PUBLIC vPortFreeSecureContext
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	ite ne
-	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	orr r0, r0, #1							/* r0 = r0 | 1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vPortAllocateSecureContext:
-	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r3, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
-	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str  r4, [r2]							/* Program MAIR0. */
-	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r4, #4								/* r4 = 4. */
-	str  r4, [r2]							/* Program RNR = 4. */
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	ldr  r2, =0xe000ed9c					/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r3!, {r4-r11}						/* Read 4 set of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	ldr  r5, =xSecureContext
-	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	msr  control, r3						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	mov  r0, #0
-	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
-	bx   r4									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	ldr  r4, =xSecureContext
-	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	mov  r0, #0
-	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs  r0, control						/* Read the CONTROL register. */
-	bic r0, r0, #1							/* Clear the bit 0. */
-	msr  control, r0						/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	cpsie f
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMask:
-	mrs r0, basepri							/* r0 = basepri. Return original basepri value. */
-	mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-	msr basepri, r1							/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	dsb
-	isb
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-vClearInterruptMask:
-	msr basepri, r0							/* basepri = ulMask. */
-	dsb
-	isb
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	ldr r3, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	ldr r0, [r3]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r3]							/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-	mrs r2, psp								/* Read PSP in r2. */
-
-	cbz r0, save_ns_context					/* No secure context to save. */
-	push {r0-r2, r14}
-	bl SecureContext_SaveContext			/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-	pop {r0-r3}								/* LR is now in r3. */
-	mov lr, r3								/* LR = r3. */
-	lsls r1, r3, #25						/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	bpl save_ns_context						/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-
-	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r3]							/* Read pxCurrentTCB. */
-#if ( configENABLE_MPU == 1 )
-	subs r2, r2, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	str r2, [r1]							/* Save the new top of stack in TCB. */
-	mrs r1, psplim							/* r1 = PSPLIM. */
-	mrs r3, control							/* r3 = CONTROL. */
-	mov r4, lr								/* r4 = LR/EXC_RETURN. */
-	stmia r2!, {r0, r1, r3, r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-#else /* configENABLE_MPU */
-	subs r2, r2, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	str r2, [r1]							/* Save the new top of stack in TCB. */
-	mrs r1, psplim							/* r1 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r2!, {r0, r1, r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
-#endif /* configENABLE_MPU */
-	b select_next_task
-
-	save_ns_context:
-		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r1, [r3]						/* Read pxCurrentTCB. */
-	#if ( configENABLE_FPU == 1 )
-		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-		it eq
-		vstmdbeq r2!, {s16-s31}				/* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if ( configENABLE_MPU == 1 )
-		subs r2, r2, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-		str r2, [r1]						/* Save the new top of stack in TCB. */
-		adds r2, r2, #16					/* r2 = r2 + 16. */
-		stm r2, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r1, psplim						/* r1 = PSPLIM. */
-		mrs r3, control						/* r3 = CONTROL. */
-		mov r4, lr							/* r4 = LR/EXC_RETURN. */
-		subs r2, r2, #16					/* r2 = r2 - 16. */
-		stmia r2!, {r0, r1, r3, r4}			/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-		subs r2, r2, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-		str r2, [r1]						/* Save the new top of stack in TCB. */
-		adds r2, r2, #12					/* r2 = r2 + 12. */
-		stm r2, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r1, psplim						/* r1 = PSPLIM. */
-		mov r3, lr							/* r3 = LR/EXC_RETURN. */
-		subs r2, r2, #12					/* r2 = r2 - 12. */
-		stmia r2!, {r0, r1, r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-
-	select_next_task:
-		mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-		msr basepri, r0						/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-		dsb
-		isb
-		bl vTaskSwitchContext
-		mov r0, #0							/* r0 = 0. */
-		msr basepri, r0						/* Enable interrupts. */
-
-		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r1, [r3]						/* Read pxCurrentTCB. */
-		ldr r2, [r1]						/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-
-	#if ( configENABLE_MPU == 1 )
-		dmb									/* Complete outstanding transfers before disabling MPU. */
-		ldr r3, =0xe000ed94					/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r3]						/* Read the value of MPU_CTRL. */
-		bic r4, r4, #1						/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-		str r4, [r3]						/* Disable MPU. */
-
-		adds r1, #4							/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-		ldr r4, [r1]						/* r4 = *r1 i.e. r4 = MAIR0. */
-		ldr r3, =0xe000edc0					/* r3 = 0xe000edc0 [Location of MAIR0]. */
-		str r4, [r3]						/* Program MAIR0. */
-		ldr r3, =0xe000ed98					/* r3 = 0xe000ed98 [Location of RNR]. */
-		movs r4, #4							/* r4 = 4. */
-		str r4, [r3]						/* Program RNR = 4. */
-		adds r1, #4							/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-		ldr  r3, =0xe000ed9c				/* r3 = 0xe000ed9c [Location of RBAR]. */
-		ldmia r1!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
-		stmia r3!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-		ldr r3, =0xe000ed94					/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r3]						/* Read the value of MPU_CTRL. */
-		orr r4, r4, #1						/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-		str r4, [r3]						/* Enable MPU. */
-		dsb									/* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-
-	#if ( configENABLE_MPU == 1 )
-		ldmia r2!, {r0, r1, r3, r4}			/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
-		msr psplim, r1						/* Restore the PSPLIM register value for the task. */
-		msr control, r3						/* Restore the CONTROL register value for the task. */
-		mov lr, r4							/* LR = r4. */
-		ldr r3, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r3]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r1, [r3]						/* Read pxCurrentTCB. */
-		push {r2, r4}
-		bl SecureContext_LoadContext		/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-		pop {r2, r4}
-		mov lr, r4							/* LR = r4. */
-		lsls r1, r4, #25					/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r2							/* Remember the new top of stack for the task. */
-		bx lr
-	#else /* configENABLE_MPU */
-		ldmia r2!, {r0, r1, r4}				/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-		msr psplim, r1						/* Restore the PSPLIM register value for the task. */
-		mov lr, r4							/* LR = r4. */
-		ldr r3, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r3]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r1, [r3]						/* Read pxCurrentTCB. */
-		push {r2, r4}
-		bl SecureContext_LoadContext		/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-		pop {r2, r4}
-		mov lr, r4							/* LR = r4. */
-		lsls r1, r4, #25					/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r2							/* Remember the new top of stack for the task. */
-		bx lr
-	#endif /* configENABLE_MPU */
-
-	restore_ns_context:
-		ldmia r2!, {r4-r11}					/* Restore the registers that are not automatically restored. */
-	#if ( configENABLE_FPU == 1 )
-		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-		it eq
-		vldmiaeq r2!, {s16-s31}				/* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-		msr psp, r2							/* Remember the new top of stack for the task. */
-		bx lr
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	tst lr, #4
-	ite eq
-	mrseq r0, msp
-	mrsne r0, psp
-	b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-vPortFreeSecureContext:
-	/* r0 = uint32_t *pulTCB. */
-	ldr r2, [r0]							/* The first item in the TCB is the top of the stack. */
-	ldr r1, [r2]							/* The first item on the stack is the task's xSecureContext. */
-	cmp r1, #0								/* Raise svc if task's xSecureContext is not NULL. */
-	it ne
-	svcne 1									/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
deleted file mode 100644
index 10977bf..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-    #define PORTMACRO_H
-
-    #ifdef __cplusplus
-        extern "C" {
-    #endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-    #ifndef configENABLE_FPU
-        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-    #endif /* configENABLE_FPU */
-
-    #ifndef configENABLE_MPU
-        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-    #endif /* configENABLE_MPU */
-
-    #ifndef configENABLE_TRUSTZONE
-        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-    #endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
-
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
-
-    #if ( configUSE_16_BIT_TICKS == 1 )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #else
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-    #define portARCH_NAME                      "Cortex-M33"
-    #define portSTACK_GROWTH                   ( -1 )
-    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT                 8
-    #define portNOP()
-    #define portINLINE                         __inline
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
-    #endif
-    #define portHAS_STACK_OVERFLOW_CHECKING    1
-    #define portDONT_DISCARD                   __root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-    extern BaseType_t xPortIsInsideInterrupt( void );
-
-    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
-        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-    #endif /* configENABLE_TRUSTZONE */
-
-    #if ( configENABLE_MPU == 1 )
-        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-    #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-    #if ( configENABLE_MPU == 1 )
-        #define portUSING_MPU_WRAPPERS    1
-        #define portPRIVILEGE_BIT         ( 0x80000000UL )
-    #else
-        #define portPRIVILEGE_BIT         ( 0x0UL )
-    #endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
-    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
-    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
-    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
-    #define portSTACK_REGION                              ( 4UL )
-    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
-    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
-    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
-    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
-    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
-    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
-    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
-    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
-    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
-
-    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
-    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
-    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
-    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
-
-    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-    typedef struct MPURegionSettings
-    {
-        uint32_t ulRBAR; /**< RBAR for the region. */
-        uint32_t ulRLAR; /**< RLAR for the region. */
-    } MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-    typedef struct MPU_SETTINGS
-    {
-        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-    } xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
-    #define portSVC_FREE_SECURE_CONTEXT        1
-    #define portSVC_START_SCHEDULER            2
-    #define portSVC_RAISE_PRIVILEGE            3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-    #define portYIELD()                                 vPortYield()
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
-    #define portDISABLE_INTERRUPTS()                  ulSetInterruptMask()
-    #define portENABLE_INTERRUPTS()                   vClearInterruptMask( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Tickless idle/low power functionality.
- */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
-    #if ( configENABLE_TRUSTZONE == 1 )
-
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
-        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
-
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
-        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-    #else
-        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-        #define portCLEAN_UP_TCB( pxTCB )
-    #endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-    #if ( configENABLE_MPU == 1 )
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-        #define portIS_PRIVILEGED()      xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
-        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
-        #define portRESET_PRIVILEGE()    vResetPrivilege()
-    #else
-        #define portIS_PRIVILEGED()
-        #define portRAISE_PRIVILEGE()
-        #define portRESET_PRIVILEGE()
-    #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
- * the source code because to do so would cause other compilers to generate
- * warnings. */
-    #pragma diag_suppress=Be006
-    #pragma diag_suppress=Pa082
-/*-----------------------------------------------------------*/
-
-    #ifdef __cplusplus
-        }
-    #endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
deleted file mode 100644
index 6252531..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-/* Including FreeRTOSConfig.h here will cause build errors if the header file
-contains code not understood by the assembler - for example the 'extern' keyword.
-To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
-the code is included in C files but excluded by the preprocessor in assembly
-files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
-#include "FreeRTOSConfig.h"
-
-	EXTERN pxCurrentTCB
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMask
-	PUBLIC vClearInterruptMask
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	ite ne
-	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	orr r0, r0, #1							/* r0 = r0 | 1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r1, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
-	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str r3, [r2]							/* Program MAIR0. */
-	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r3, #4								/* r3 = 4. */
-	str r3, [r2]							/* Program RNR = 4. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	msr  control, r2						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	mov  r0, #0
-	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	mov  r0, #0
-	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
-	bx   r2									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs  r0, control						/* Read the CONTROL register. */
-	bic r0, r0, #1							/* Clear the bit 0. */
-	msr  control, r0						/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	cpsie f
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMask:
-	mrs r0, basepri							/* r0 = basepri. Return original basepri value. */
-	mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-	msr basepri, r1							/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	dsb
-	isb
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-vClearInterruptMask:
-	msr basepri, r0							/* basepri = ulMask. */
-	dsb
-	isb
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	mrs r0, psp								/* Read PSP in r0. */
-#if ( configENABLE_FPU == 1 )
-	tst lr, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	it eq
-	vstmdbeq r0!, {s16-s31}					/* Store the FPU registers which are not saved automatically. */
-#endif /* configENABLE_FPU */
-#if ( configENABLE_MPU == 1 )
-	mrs r1, psplim							/* r1 = PSPLIM. */
-	mrs r2, control							/* r2 = CONTROL. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmdb r0!, {r1-r11}						/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
-#else /* configENABLE_MPU */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmdb r0!, {r2-r11}						/* Store on the stack - PSPLIM, LR and registers that are not automatically. */
-#endif /* configENABLE_MPU */
-
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-	str r0, [r1]							/* Save the new top of stack in TCB. */
-
-	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-	msr basepri, r0							/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	dsb
-	isb
-	bl vTaskSwitchContext
-	mov r0, #0								/* r0 = 0. */
-	msr basepri, r0							/* Enable interrupts. */
-
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
-	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str r3, [r2]							/* Program MAIR0. */
-	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r3, #4								/* r3 = 4. */
-	str r3, [r2]							/* Program RNR = 4. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldmia r0!, {r1-r11}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
-#else /* configENABLE_MPU */
-	ldmia r0!, {r2-r11}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_FPU == 1 )
-	tst r3, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	it eq
-	vldmiaeq r0!, {s16-s31}					/* Restore the FPU registers which are not restored automatically. */
-#endif /* configENABLE_FPU */
-
- #if ( configENABLE_MPU == 1 )
-	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
-	msr control, r2							/* Restore the CONTROL register value for the task. */
-#else /* configENABLE_MPU */
-	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
-#endif /* configENABLE_MPU */
-	msr psp, r0								/* Remember the new top of stack for the task. */
-	bx r3
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	tst lr, #4
-	ite eq
-	mrseq r0, msp
-	mrsne r0, psp
-	b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
deleted file mode 100644
index 1d3c883..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- *
- * Copyright 2019-2020 MicroEJ Corp. This file has been modified by MicroEJ Corp.
- * 1. Patch for SystemView support
- */
-
-#ifndef PORTMACRO_H
-    #define PORTMACRO_H
-
-    #ifdef __cplusplus
-        extern "C" {
-    #endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-    #ifndef configENABLE_FPU
-        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-    #endif /* configENABLE_FPU */
-
-    #ifndef configENABLE_MPU
-        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-    #endif /* configENABLE_MPU */
-
-    #ifndef configENABLE_TRUSTZONE
-        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-    #endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
-
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
-
-    #if ( configUSE_16_BIT_TICKS == 1 )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #else
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-    #define portARCH_NAME                      "Cortex-M33"
-    #define portSTACK_GROWTH                   ( -1 )
-    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT                 8
-    #define portNOP()
-    #define portINLINE                         __inline
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
-    #endif
-    #define portHAS_STACK_OVERFLOW_CHECKING    1
-    #define portDONT_DISCARD                   __root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-    extern BaseType_t xPortIsInsideInterrupt( void );
-
-    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
-        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-    #endif /* configENABLE_TRUSTZONE */
-
-    #if ( configENABLE_MPU == 1 )
-        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-    #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-    #if ( configENABLE_MPU == 1 )
-        #define portUSING_MPU_WRAPPERS    1
-        #define portPRIVILEGE_BIT         ( 0x80000000UL )
-    #else
-        #define portPRIVILEGE_BIT         ( 0x0UL )
-    #endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
-    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
-    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
-    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
-    #define portSTACK_REGION                              ( 4UL )
-    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
-    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
-    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
-    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
-    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
-    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
-    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
-    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
-    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
-
-    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
-    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
-    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
-    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
-
-    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-    typedef struct MPURegionSettings
-    {
-        uint32_t ulRBAR; /**< RBAR for the region. */
-        uint32_t ulRLAR; /**< RLAR for the region. */
-    } MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-    typedef struct MPU_SETTINGS
-    {
-        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-    } xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
-    #define portSVC_FREE_SECURE_CONTEXT        1
-    #define portSVC_START_SCHEDULER            2
-    #define portSVC_RAISE_PRIVILEGE            3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-    #define portYIELD()                                 vPortYield()
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired ) { if( xSwitchRequired ) { traceISR_EXIT_TO_SCHEDULER(); portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } else { traceISR_EXIT(); } }
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
-    #define portDISABLE_INTERRUPTS()                  ulSetInterruptMask()
-    #define portENABLE_INTERRUPTS()                   vClearInterruptMask( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Tickless idle/low power functionality.
- */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
-    #if ( configENABLE_TRUSTZONE == 1 )
-
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
-        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
-
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
-        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-    #else
-        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-        #define portCLEAN_UP_TCB( pxTCB )
-    #endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-    #if ( configENABLE_MPU == 1 )
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-        #define portIS_PRIVILEGED()      xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
-        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
-        #define portRESET_PRIVILEGE()    vResetPrivilege()
-    #else
-        #define portIS_PRIVILEGED()
-        #define portRAISE_PRIVILEGE()
-        #define portRESET_PRIVILEGE()
-    #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
- * the source code because to do so would cause other compilers to generate
- * warnings. */
-    #pragma diag_suppress=Be006
-    #pragma diag_suppress=Pa082
-/*-----------------------------------------------------------*/
-
-    #ifdef __cplusplus
-        }
-    #endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portasm.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portasm.h
deleted file mode 100644
index 89a3cee..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/ReadMe.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/ReadMe.txt
deleted file mode 100644
index 9b12e54..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/ReadMe.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
-Do not use the files located here!  These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
-FreeRTOS release.
-
-If your Cortex-M33 application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
-
-If your Cortex-M33 application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
deleted file mode 100644
index 7c0de79..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
-void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
-
-void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
-{
-    /* pxSecureContext value is in r0. */
-    __asm volatile
-    (
-        " .syntax unified                   \n"
-        "                                   \n"
-        " mrs r1, ipsr                      \n" /* r1 = IPSR. */
-        " cbz r1, load_ctx_therad_mode      \n" /* Do nothing if the processor is running in the Thread Mode. */
-        " ldmia r0!, {r1, r2}               \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
-        "                                   \n"
-        #if ( configENABLE_MPU == 1 )
-            " ldmia r1!, {r3}               \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
-            " msr control, r3               \n" /* CONTROL = r3. */
-        #endif /* configENABLE_MPU */
-        "                                   \n"
-        " msr psplim, r2                    \n" /* PSPLIM = r2. */
-        " msr psp, r1                       \n" /* PSP = r1. */
-        "                                   \n"
-        " load_ctx_therad_mode:             \n"
-        "    bx lr                          \n"
-        "                                   \n"
-        ::: "r0", "r1", "r2"
-    );
-}
-/*-----------------------------------------------------------*/
-
-void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
-{
-    /* pxSecureContext value is in r0. */
-    __asm volatile
-    (
-        " .syntax unified                   \n"
-        "                                   \n"
-        " mrs r1, ipsr                      \n" /* r1 = IPSR. */
-        " cbz r1, save_ctx_therad_mode      \n" /* Do nothing if the processor is running in the Thread Mode. */
-        " mrs r1, psp                       \n" /* r1 = PSP. */
-        "                                   \n"
-        #if ( configENABLE_FPU == 1 )
-            " vstmdb r1!, {s0}              \n" /* Trigger the defferred stacking of FPU registers. */
-            " vldmia r1!, {s0}              \n" /* Nullify the effect of the pervious statement. */
-        #endif /* configENABLE_FPU */
-        "                                   \n"
-        #if ( configENABLE_MPU == 1 )
-            " mrs r2, control               \n" /* r2 = CONTROL. */
-            " stmdb r1!, {r2}               \n" /* Store CONTROL value on the stack. */
-        #endif /* configENABLE_MPU */
-        "                                   \n"
-        " str r1, [r0]                      \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
-        " movs r1, %0                       \n" /* r1 = securecontextNO_STACK. */
-        " msr psplim, r1                    \n" /* PSPLIM = securecontextNO_STACK. */
-        " msr psp, r1                       \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-        "                                   \n"
-        " save_ctx_therad_mode:             \n"
-        "    bx lr                          \n"
-        "                                   \n"
-        ::"i" ( securecontextNO_STACK ) : "r1", "memory"
-    );
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
deleted file mode 100644
index 6d7b8b3..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-    SECTION .text:CODE:NOROOT(2)
-    THUMB
-
-/* Including FreeRTOSConfig.h here will cause build errors if the header file
-contains code not understood by the assembler - for example the 'extern' keyword.
-To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
-the code is included in C files but excluded by the preprocessor in assembly
-files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
-#include "FreeRTOSConfig.h"
-
-    PUBLIC SecureContext_LoadContextAsm
-    PUBLIC SecureContext_SaveContextAsm
-/*-----------------------------------------------------------*/
-
-SecureContext_LoadContextAsm:
-    /* pxSecureContext value is in r0. */
-    mrs r1, ipsr                        /* r1 = IPSR. */
-    cbz r1, load_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */
-    ldmia r0!, {r1, r2}                 /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
-
-#if ( configENABLE_MPU == 1 )
-    ldmia r1!, {r3}                     /* Read CONTROL register value from task's stack. r3 = CONTROL. */
-    msr control, r3                     /* CONTROL = r3. */
-#endif /* configENABLE_MPU */
-
-    msr psplim, r2                      /* PSPLIM = r2. */
-    msr psp, r1                         /* PSP = r1. */
-
-    load_ctx_therad_mode:
-        bx lr
-/*-----------------------------------------------------------*/
-
-SecureContext_SaveContextAsm:
-    /* pxSecureContext value is in r0. */
-    mrs r1, ipsr                        /* r1 = IPSR. */
-    cbz r1, save_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */
-    mrs r1, psp                         /* r1 = PSP. */
-
-#if ( configENABLE_FPU == 1 )
-    vstmdb r1!, {s0}                    /* Trigger the defferred stacking of FPU registers. */
-    vldmia r1!, {s0}                    /* Nullify the effect of the pervious statement. */
-#endif /* configENABLE_FPU */
-
-#if ( configENABLE_MPU == 1 )
-    mrs r2, control                     /* r2 = CONTROL. */
-    stmdb r1!, {r2}                     /* Store CONTROL value on the stack. */
-#endif /* configENABLE_MPU */
-
-    str r1, [r0]                        /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
-    movs r1, #0                         /* r1 = securecontextNO_STACK. */
-    msr psplim, r1                      /* PSPLIM = securecontextNO_STACK. */
-    msr psp, r1                         /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-
-    save_ctx_therad_mode:
-        bx lr
-/*-----------------------------------------------------------*/
-
-    END
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/context/secure_context.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/context/secure_context.c
deleted file mode 100644
index d89d837..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/context/secure_context.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief CONTROL value for privileged tasks.
- *
- * Bit[0] - 0 --> Thread mode is privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_PRIVILEGED      0x02
-
-/**
- * @brief CONTROL value for un-privileged tasks.
- *
- * Bit[0] - 1 --> Thread mode is un-privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03
-
-/**
- * @brief Size of stack seal values in bytes.
- */
-#define securecontextSTACK_SEAL_SIZE               8
-
-/**
- * @brief Stack seal value as recommended by ARM.
- */
-#define securecontextSTACK_SEAL_VALUE              0xFEF5EDA5
-
-/**
- * @brief Maximum number of secure contexts.
- */
-#ifndef secureconfigMAX_SECURE_CONTEXTS
-    #define secureconfigMAX_SECURE_CONTEXTS        8UL
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Pre-allocated array of secure contexts.
- */
-SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).
- *
- * This function ensures that only one secure context is allocated for a task.
- *
- * @param[in] pvTaskHandle The task handle for which the secure context is allocated.
- *
- * @return Index of a free secure context in the xSecureContexts array.
- */
-static uint32_t ulGetSecureContext( void * pvTaskHandle );
-
-/**
- * @brief Return the secure context to the secure context pool (xSecureContexts).
- *
- * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.
- */
-static void vReturnSecureContext( uint32_t ulSecureContextIndex );
-
-/* These are implemented in assembly. */
-extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );
-extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );
-/*-----------------------------------------------------------*/
-
-static uint32_t ulGetSecureContext( void * pvTaskHandle )
-{
-    /* Start with invalid index. */
-    uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
-
-    for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
-    {
-        if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&
-            ( xSecureContexts[ i ].pucStackLimit == NULL ) &&
-            ( xSecureContexts[ i ].pucStackStart == NULL ) &&
-            ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&
-            ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )
-        {
-            ulSecureContextIndex = i;
-        }
-        else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )
-        {
-            /* A task can only have one secure context. Do not allocate a second
-             * context for the same task. */
-            ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
-            break;
-        }
-    }
-
-    return ulSecureContextIndex;
-}
-/*-----------------------------------------------------------*/
-
-static void vReturnSecureContext( uint32_t ulSecureContextIndex )
-{
-    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;
-    xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;
-    xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;
-    xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
-{
-    uint32_t ulIPSR, i;
-    static uint32_t ulSecureContextsInitialized = 0;
-
-    /* Read the Interrupt Program Status Register (IPSR) value. */
-    secureportREAD_IPSR( ulIPSR );
-
-    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-     * when the processor is running in the Thread Mode. */
-    if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )
-    {
-        /* Ensure to initialize secure contexts only once. */
-        ulSecureContextsInitialized = 1;
-
-        /* No stack for thread mode until a task's context is loaded. */
-        secureportSET_PSPLIM( securecontextNO_STACK );
-        secureportSET_PSP( securecontextNO_STACK );
-
-        /* Initialize all secure contexts. */
-        for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
-        {
-            xSecureContexts[ i ].pucCurrentStackPointer = NULL;
-            xSecureContexts[ i ].pucStackLimit = NULL;
-            xSecureContexts[ i ].pucStackStart = NULL;
-            xSecureContexts[ i ].pvTaskHandle = NULL;
-        }
-
-        #if ( configENABLE_MPU == 1 )
-            {
-                /* Configure thread mode to use PSP and to be unprivileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-            }
-        #else /* configENABLE_MPU */
-            {
-                /* Configure thread mode to use PSP and to be privileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-            }
-        #endif /* configENABLE_MPU */
-    }
-}
-/*-----------------------------------------------------------*/
-
-#if ( configENABLE_MPU == 1 )
-    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
-                                                                                       uint32_t ulIsTaskPrivileged,
-                                                                                       void * pvTaskHandle )
-#else /* configENABLE_MPU */
-    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
-                                                                                       void * pvTaskHandle )
-#endif /* configENABLE_MPU */
-{
-    uint8_t * pucStackMemory = NULL;
-    uint8_t * pucStackLimit;
-    uint32_t ulIPSR, ulSecureContextIndex;
-    SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;
-
-    #if ( configENABLE_MPU == 1 )
-        uint32_t * pulCurrentStackPointer = NULL;
-    #endif /* configENABLE_MPU */
-
-    /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit
-     * Register (PSPLIM) value. */
-    secureportREAD_IPSR( ulIPSR );
-    secureportREAD_PSPLIM( pucStackLimit );
-
-    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-     * when the processor is running in the Thread Mode.
-     * Also do nothing, if a secure context us already loaded. PSPLIM is set to
-     * securecontextNO_STACK when no secure context is loaded. */
-    if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
-    {
-        /* Ontain a free secure context. */
-        ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
-
-        /* Were we able to get a free context? */
-        if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )
-        {
-            /* Allocate the stack space. */
-            pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );
-
-            if( pucStackMemory != NULL )
-            {
-                /* Since stack grows down, the starting point will be the last
-                 * location. Note that this location is next to the last
-                 * allocated byte for stack (excluding the space for seal values)
-                 * because the hardware decrements the stack pointer before
-                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * decrement the stack pointer to 0x1 and then write at 0x1. */
-                xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
-
-                /* Seal the created secure process stack. */
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
-
-                /* The stack cannot go beyond this location. This value is
-                 * programmed in the PSPLIM register on context switch.*/
-                xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;
-
-                xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
-
-                #if ( configENABLE_MPU == 1 )
-                    {
-                        /* Store the correct CONTROL value for the task on the stack.
-                         * This value is programmed in the CONTROL register on
-                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                        pulCurrentStackPointer--;
-
-                        if( ulIsTaskPrivileged )
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-                        }
-                        else
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-                        }
-
-                        /* Store the current stack pointer. This value is programmed in
-                         * the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
-                    }
-                #else /* configENABLE_MPU */
-                    {
-                        /* Current SP is set to the starting of the stack. This
-                         * value programmed in the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                    }
-                #endif /* configENABLE_MPU */
-
-                /* Ensure to never return 0 as a valid context handle. */
-                xSecureContextHandle = ulSecureContextIndex + 1UL;
-            }
-        }
-    }
-
-    return xSecureContextHandle;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
-{
-    uint32_t ulIPSR, ulSecureContextIndex;
-
-    /* Read the Interrupt Program Status Register (IPSR) value. */
-    secureportREAD_IPSR( ulIPSR );
-
-    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-     * when the processor is running in the Thread Mode. */
-    if( ulIPSR != 0 )
-    {
-        /* Only free if a valid context handle is passed. */
-        if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
-        {
-            ulSecureContextIndex = xSecureContextHandle - 1UL;
-
-            /* Ensure that the secure context being deleted is associated with
-             * the task. */
-            if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )
-            {
-                /* Free the stack space. */
-                vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );
-
-                /* Return the secure context back to the free secure contexts pool. */
-                vReturnSecureContext( ulSecureContextIndex );
-            }
-        }
-    }
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
-{
-    uint8_t * pucStackLimit;
-    uint32_t ulSecureContextIndex;
-
-    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
-    {
-        ulSecureContextIndex = xSecureContextHandle - 1UL;
-
-        secureportREAD_PSPLIM( pucStackLimit );
-
-        /* Ensure that no secure context is loaded and the task is loading it's
-         * own context. */
-        if( ( pucStackLimit == securecontextNO_STACK ) &&
-            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
-        {
-            SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
-        }
-    }
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
-{
-    uint8_t * pucStackLimit;
-    uint32_t ulSecureContextIndex;
-
-    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
-    {
-        ulSecureContextIndex = xSecureContextHandle - 1UL;
-
-        secureportREAD_PSPLIM( pucStackLimit );
-
-        /* Ensure that task's context is loaded and the task is saving it's own
-         * context. */
-        if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
-            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
-        {
-            SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
-        }
-    }
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/context/secure_context.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/context/secure_context.h
deleted file mode 100644
index 6e6dbc8..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/context/secure_context.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_CONTEXT_H__
-#define __SECURE_CONTEXT_H__
-
-/* Standard includes. */
-#include 
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/**
- * @brief PSP value when no secure context is loaded.
- */
-#define securecontextNO_STACK               0x0
-
-/**
- * @brief Invalid context ID.
- */
-#define securecontextINVALID_CONTEXT_ID     0UL
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Structure to represent a secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first address of the allocated memory.
- */
-typedef struct SecureContext
-{
-    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
-    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */
-    uint8_t * pucStackStart;          /**< First location of the stack memory. */
-    void * pvTaskHandle;              /**< Task handle of the task this context is associated with. */
-} SecureContext_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Opaque handle for a secure context.
- */
-typedef uint32_t SecureContextHandle_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Initializes the secure context management system.
- *
- * PSP is set to NULL and therefore a task must allocate and load a context
- * before calling any secure side function in the thread mode.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureContext_Init( void );
-
-/**
- * @brief Allocates a context on the secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
- * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
- *
- * @return Opaque context handle if context is successfully allocated, NULL
- * otherwise.
- */
-#if ( configENABLE_MPU == 1 )
-    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
-                                                         uint32_t ulIsTaskPrivileged,
-                                                         void * pvTaskHandle );
-#else /* configENABLE_MPU */
-    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
-                                                         void * pvTaskHandle );
-#endif /* configENABLE_MPU */
-
-/**
- * @brief Frees the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the
- * context to be freed.
- */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
-
-/**
- * @brief Loads the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be loaded.
- */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
-
-/**
- * @brief Saves the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be saved.
- */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
-
-#endif /* __SECURE_CONTEXT_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/heap/secure_heap.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/heap/secure_heap.c
deleted file mode 100644
index 8f2999d..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/heap/secure_heap.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure context heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Total heap size.
- */
-#ifndef secureconfigTOTAL_HEAP_SIZE
-    #define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )
-#endif
-
-/* No test marker by default. */
-#ifndef mtCOVERAGE_TEST_MARKER
-    #define mtCOVERAGE_TEST_MARKER()
-#endif
-
-/* No tracing by default. */
-#ifndef traceMALLOC
-    #define traceMALLOC( pvReturn, xWantedSize )
-#endif
-
-/* No tracing by default. */
-#ifndef traceFREE
-    #define traceFREE( pv, xBlockSize )
-#endif
-
-/* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
-/*-----------------------------------------------------------*/
-
-/* Allocate the memory for the heap. */
-#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
-
-/* The application writer has already defined the array used for the RTOS
-* heap - probably so it can be placed in a special segment or address. */
-    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#else /* configAPPLICATION_ALLOCATED_HEAP */
-    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/**
- * @brief The linked list structure.
- *
- * This is used to link free blocks in order of their memory address.
- */
-typedef struct A_BLOCK_LINK
-{
-    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
-    size_t xBlockSize;                     /**< The size of the free block. */
-} BlockLink_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Called automatically to setup the required heap structures the first
- * time pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/**
- * @brief Inserts a block of memory that is being freed into the correct
- * position in the list of free memory blocks.
- *
- * The block being freed will be merged with the block in front it and/or the
- * block behind it if the memory blocks are adjacent to each other.
- *
- * @param[in] pxBlockToInsert The block being freed.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The size of the structure placed at the beginning of each allocated
- * memory block must by correctly byte aligned.
- */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-
-/**
- * @brief Create a couple of list links to mark the start and end of the list.
- */
-static BlockLink_t xStart, * pxEnd = NULL;
-
-/**
- * @brief Keeps track of the number of free bytes remaining, but says nothing
- * about fragmentation.
- */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-    BlockLink_t * pxFirstFreeBlock;
-    uint8_t * pucAlignedHeap;
-    size_t uxAddress;
-    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
-
-    /* Ensure the heap starts on a correctly aligned boundary. */
-    uxAddress = ( size_t ) ucHeap;
-
-    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
-    {
-        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
-        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-    }
-
-    pucAlignedHeap = ( uint8_t * ) uxAddress;
-
-    /* xStart is used to hold a pointer to the first item in the list of free
-     * blocks.  The void cast is used to prevent compiler warnings. */
-    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-    xStart.xBlockSize = ( size_t ) 0;
-
-    /* pxEnd is used to mark the end of the list of free blocks and is inserted
-     * at the end of the heap space. */
-    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-    uxAddress -= xHeapStructSize;
-    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-    pxEnd = ( void * ) uxAddress;
-    pxEnd->xBlockSize = 0;
-    pxEnd->pxNextFreeBlock = NULL;
-
-    /* To start with there is a single free block that is sized to take up the
-     * entire heap space, minus the space taken by pxEnd. */
-    pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
-    /* Only one block exists - and it covers the entire usable heap space. */
-    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
-{
-    BlockLink_t * pxIterator;
-    uint8_t * puc;
-
-    /* Iterate through the list until a block is found that has a higher address
-     * than the block being inserted. */
-    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-    {
-        /* Nothing to do here, just iterate to the right position. */
-    }
-
-    /* Do the block being inserted, and the block it is being inserted after
-     * make a contiguous block of memory? */
-    puc = ( uint8_t * ) pxIterator;
-
-    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-    {
-        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-        pxBlockToInsert = pxIterator;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    /* Do the block being inserted, and the block it is being inserted before
-     * make a contiguous block of memory? */
-    puc = ( uint8_t * ) pxBlockToInsert;
-
-    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-    {
-        if( pxIterator->pxNextFreeBlock != pxEnd )
-        {
-            /* Form one big block from the two blocks. */
-            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-        }
-        else
-        {
-            pxBlockToInsert->pxNextFreeBlock = pxEnd;
-        }
-    }
-    else
-    {
-        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-    }
-
-    /* If the block being inserted plugged a gab, so was merged with the block
-     * before and the block after, then it's pxNextFreeBlock pointer will have
-     * already been set, and should not be set here as that would make it point
-     * to itself. */
-    if( pxIterator != pxBlockToInsert )
-    {
-        pxIterator->pxNextFreeBlock = pxBlockToInsert;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-}
-/*-----------------------------------------------------------*/
-
-void * pvPortMalloc( size_t xWantedSize )
-{
-    BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
-    void * pvReturn = NULL;
-
-    /* If this is the first call to malloc then the heap will require
-     * initialisation to setup the list of free blocks. */
-    if( pxEnd == NULL )
-    {
-        prvHeapInit();
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    /* Check the requested block size is not so large that the top bit is set.
-     * The top bit of the block size member of the BlockLink_t structure is used
-     * to determine who owns the block - the application or the kernel, so it
-     * must be free. */
-    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-    {
-        /* The wanted size is increased so it can contain a BlockLink_t
-         * structure in addition to the requested amount of bytes. */
-        if( xWantedSize > 0 )
-        {
-            xWantedSize += xHeapStructSize;
-
-            /* Ensure that blocks are always aligned to the required number of
-             * bytes. */
-            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
-            {
-                /* Byte alignment required. */
-                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-        {
-            /* Traverse the list from the start (lowest address) block until
-             * one of adequate size is found. */
-            pxPreviousBlock = &xStart;
-            pxBlock = xStart.pxNextFreeBlock;
-
-            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-            {
-                pxPreviousBlock = pxBlock;
-                pxBlock = pxBlock->pxNextFreeBlock;
-            }
-
-            /* If the end marker was reached then a block of adequate size was
-             * not found. */
-            if( pxBlock != pxEnd )
-            {
-                /* Return the memory space pointed to - jumping over the
-                 * BlockLink_t structure at its start. */
-                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-                /* This block is being returned for use so must be taken out
-                 * of the list of free blocks. */
-                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-                /* If the block is larger than required it can be split into
-                 * two. */
-                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
-                {
-                    /* This block is to be split into two.  Create a new
-                     * block following the number of bytes requested. The void
-                     * cast is used to prevent byte alignment warnings from the
-                     * compiler. */
-                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-
-                    /* Calculate the sizes of two blocks split from the single
-                     * block. */
-                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-                    pxBlock->xBlockSize = xWantedSize;
-
-                    /* Insert the new block into the list of free blocks. */
-                    prvInsertBlockIntoFreeList( pxNewBlockLink );
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-                {
-                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                /* The block is being returned - it is allocated and owned by
-                 * the application and has no "next" block. */
-                pxBlock->xBlockSize |= xBlockAllocatedBit;
-                pxBlock->pxNextFreeBlock = NULL;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    traceMALLOC( pvReturn, xWantedSize );
-
-    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
-        {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
-
-    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
-    return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void * pv )
-{
-    uint8_t * puc = ( uint8_t * ) pv;
-    BlockLink_t * pxLink;
-
-    if( pv != NULL )
-    {
-        /* The memory being freed will have an BlockLink_t structure immediately
-         * before it. */
-        puc -= xHeapStructSize;
-
-        /* This casting is to keep the compiler from issuing warnings. */
-        pxLink = ( void * ) puc;
-
-        /* Check the block is actually allocated. */
-        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-        secureportASSERT( pxLink->pxNextFreeBlock == NULL );
-
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-        {
-            if( pxLink->pxNextFreeBlock == NULL )
-            {
-                /* The block is being returned to the heap - it is no longer
-                 * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-                secureportDISABLE_NON_SECURE_INTERRUPTS();
-                {
-                    /* Add this block to the list of free blocks. */
-                    xFreeBytesRemaining += pxLink->xBlockSize;
-                    traceFREE( pv, pxLink->xBlockSize );
-                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-                }
-                secureportENABLE_NON_SECURE_INTERRUPTS();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-    return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-    return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/heap/secure_heap.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/heap/secure_heap.h
deleted file mode 100644
index 4fccdfe..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/heap/secure_heap.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_HEAP_H__
-#define __SECURE_HEAP_H__
-
-/* Standard includes. */
-#include 
-
-/**
- * @brief Allocates memory from heap.
- *
- * @param[in] xWantedSize The size of the memory to be allocated.
- *
- * @return Pointer to the memory region if the allocation is successful, NULL
- * otherwise.
- */
-void * pvPortMalloc( size_t xWantedSize );
-
-/**
- * @brief Frees the previously allocated memory.
- *
- * @param[in] pv Pointer to the memory to be freed.
- */
-void vPortFree( void * pv );
-
-/**
- * @brief Get the free heap size.
- *
- * @return Free heap size.
- */
-size_t xPortGetFreeHeapSize( void );
-
-/**
- * @brief Get the minimum ever free heap size.
- *
- * @return Minimum ever free heap size.
- */
-size_t xPortGetMinimumEverFreeHeapSize( void );
-
-#endif /* __SECURE_HEAP_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/init/secure_init.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/init/secure_init.c
deleted file mode 100644
index 0165b1d..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/init/secure_init.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure init includes. */
-#include "secure_init.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS          ( 29UL )
-#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS              ( 26UL )
-#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )
-
-#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS            ( 10UL )
-#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS            ( 11UL )
-#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
-{
-    uint32_t ulIPSR;
-
-    /* Read the Interrupt Program Status Register (IPSR) value. */
-    secureportREAD_IPSR( ulIPSR );
-
-    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-     * when the processor is running in the Thread Mode. */
-    if( ulIPSR != 0 )
-    {
-        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
-                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
-                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
-    }
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
-{
-    uint32_t ulIPSR;
-
-    /* Read the Interrupt Program Status Register (IPSR) value. */
-    secureportREAD_IPSR( ulIPSR );
-
-    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-     * when the processor is running in the Thread Mode. */
-    if( ulIPSR != 0 )
-    {
-        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
-         * permitted. CP11 should be programmed to the same value as CP10. */
-        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
-
-        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
-         * that we can enable/disable lazy stacking in port.c file. */
-        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
-
-        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
-         * registers (S16-S31) are also pushed to stack on exception entry and
-         * restored on exception return. */
-        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
-    }
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/init/secure_init.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/init/secure_init.h
deleted file mode 100644
index e5278d7..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/init/secure_init.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_INIT_H__
-#define __SECURE_INIT_H__
-
-/**
- * @brief De-prioritizes the non-secure exceptions.
- *
- * This is needed to ensure that the non-secure PendSV runs at the lowest
- * priority. Context switch is done in the non-secure PendSV handler.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_DePrioritizeNSExceptions( void );
-
-/**
- * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
- *
- * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
- * Registers are not leaked to the non-secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_EnableNSFPUAccess( void );
-
-#endif /* __SECURE_INIT_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/macros/secure_port_macros.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/macros/secure_port_macros.h
deleted file mode 100644
index 441868e..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/ARMv8M/secure/macros/secure_port_macros.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_PORT_MACROS_H__
-#define __SECURE_PORT_MACROS_H__
-
-/**
- * @brief Byte alignment requirements.
- */
-#define secureportBYTE_ALIGNMENT         8
-#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )
-
-/**
- * @brief Macro to declare a function as non-secure callable.
- */
-#if defined( __IAR_SYSTEMS_ICC__ )
-    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root
-#else
-    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
-#endif
-
-/**
- * @brief Set the secure PRIMASK value.
- */
-#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
-    __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Set the non-secure PRIMASK value.
- */
-#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
-    __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Read the PSP value in the given variable.
- */
-#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
-    __asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
-
-/**
- * @brief Set the PSP to the given value.
- */
-#define secureportSET_PSP( pucCurrentStackPointer ) \
-    __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
-
-/**
- * @brief Read the PSPLIM value in the given variable.
- */
-#define secureportREAD_PSPLIM( pucOutStackLimit ) \
-    __asm volatile ( "mrs %0, psplim"  : "=r" ( pucOutStackLimit ) )
-
-/**
- * @brief Set the PSPLIM to the given value.
- */
-#define secureportSET_PSPLIM( pucStackLimit ) \
-    __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
-
-/**
- * @brief Set the NonSecure MSP to the given value.
- */
-#define secureportSET_MSP_NS( pucMainStackPointer ) \
-    __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
-
-/**
- * @brief Set the CONTROL register to the given value.
- */
-#define secureportSET_CONTROL( ulControl ) \
-    __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
-
-/**
- * @brief Read the Interrupt Program Status Register (IPSR) value in the given
- * variable.
- */
-#define secureportREAD_IPSR( ulIPSR ) \
-    __asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
-
-/**
- * @brief PRIMASK value to enable interrupts.
- */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0
-
-/**
- * @brief PRIMASK value to disable interrupts.
- */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1
-
-/**
- * @brief Disable secure interrupts.
- */
-#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Disable non-secure interrupts.
- *
- * This effectively disables context switches.
- */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Enable non-secure interrupts.
- */
-#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Assert definition.
- */
-#define secureportASSERT( x )                      \
-    if( ( x ) == 0 )                               \
-    {                                              \
-        secureportDISABLE_SECURE_INTERRUPTS();     \
-        secureportDISABLE_NON_SECURE_INTERRUPTS(); \
-        for( ; ; ) {; }                            \
-    }
-
-#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/Common/mpu_wrappers.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/Common/mpu_wrappers.c
deleted file mode 100644
index e7d26b7..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/Common/mpu_wrappers.c
+++ /dev/null
@@ -1,1465 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * Implementation of the wrapper functions used to raise the processor privilege
- * before calling a standard FreeRTOS API function.
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers.  That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-#include "timers.h"
-#include "event_groups.h"
-#include "stream_buffer.h"
-#include "mpu_prototypes.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode,
-                                const char * const pcName,
-                                uint16_t usStackDepth,
-                                void * pvParameters,
-                                UBaseType_t uxPriority,
-                                TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn, xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
-                                        const char * const pcName,
-                                        const uint32_t ulStackDepth,
-                                        void * const pvParameters,
-                                        UBaseType_t uxPriority,
-                                        StackType_t * const puxStackBuffer,
-                                        StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        TaskHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelete == 1 )
-    void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vTaskDelete( pxTaskToDelete );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskDelayUntil == 1 )
-    BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                    TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged, xReturn;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskAbortDelay == 1 )
-    BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn, xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTaskAbortDelay( xTask );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelay == 1 )
-    void MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vTaskDelay( xTicksToDelay );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
-    UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
-    {
-        UBaseType_t uxReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        uxReturn = uxTaskPriorityGet( pxTask );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return uxReturn;
-    }
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskPrioritySet == 1 )
-    void MPU_vTaskPrioritySet( TaskHandle_t pxTask,
-                               UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vTaskPrioritySet( pxTask, uxNewPriority );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif /* if ( INCLUDE_vTaskPrioritySet == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_eTaskGetState == 1 )
-    eTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
-    {
-        eTaskState eReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        eReturn = eTaskGetState( pxTask );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return eReturn;
-    }
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-    void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                           TaskStatus_t * pxTaskStatus,
-                           BaseType_t xGetFreeStackSpace,
-                           eTaskState eState ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
-    TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-    {
-        TaskHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTaskGetIdleTaskHandle();
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-    void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vTaskSuspend( pxTaskToSuspend );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-    void MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vTaskResume( pxTaskToResume );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif
-/*-----------------------------------------------------------*/
-
-void MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    vTaskSuspendAll();
-    vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xReturn, xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xTaskResumeAll();
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
-{
-    TickType_t xReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xTaskGetTickCount();
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
-{
-    UBaseType_t uxReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    uxReturn = uxTaskGetNumberOfTasks();
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */
-{
-    char * pcReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    pcReturn = pcTaskGetName( xTaskToQuery );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return pcReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetHandle == 1 )
-    TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */
-    {
-        TaskHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTaskGetHandle( pcNameToQuery );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( INCLUDE_xTaskGetHandle == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-    void MPU_vTaskList( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vTaskList( pcWriteBuffer );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-    void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vTaskGetRunTimeStats( pcWriteBuffer );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
-    uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */
-    {
-        uint32_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = ulTaskGetIdleRunTimeCounter();
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-    void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                         TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vTaskSetApplicationTaskTag( xTask, pxTagValue );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-    TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-    {
-        TaskHookFunction_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTaskGetApplicationTaskTag( xTask );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-    void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                                BaseType_t xIndex,
-                                                void * pvValue ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-    void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                                   BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */
-    {
-        void * pvReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return pvReturn;
-    }
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-    BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
-                                                 void * pvParameter ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn, xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-    UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * pxTaskStatusArray,
-                                          UBaseType_t uxArraySize,
-                                          uint32_t * pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */
-    {
-        UBaseType_t uxReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return uxReturn;
-    }
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xReturn, xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xTaskCatchUpTicks( xTicksToCatchUp );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
-    UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-    {
-        UBaseType_t uxReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        uxReturn = uxTaskGetStackHighWaterMark( xTask );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return uxReturn;
-    }
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
-    configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-    {
-        configSTACK_DEPTH_TYPE uxReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        uxReturn = uxTaskGetStackHighWaterMark2( xTask );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return uxReturn;
-    }
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
-    TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-    {
-        TaskHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTaskGetCurrentTaskHandle();
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
-    BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn, xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTaskGetSchedulerState();
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
-/*-----------------------------------------------------------*/
-
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    vTaskSetTimeOutState( pxTimeOut );
-    vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xReturn, xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-    BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                       UBaseType_t uxIndexToNotify,
-                                       uint32_t ulValue,
-                                       eNotifyAction eAction,
-                                       uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn, xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-    BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                           uint32_t ulBitsToClearOnEntry,
-                                           uint32_t ulBitsToClearOnExit,
-                                           uint32_t * pulNotificationValue,
-                                           TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn, xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-    uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                          BaseType_t xClearCountOnExit,
-                                          TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        uint32_t ulReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return ulReturn;
-    }
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-    BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                                 UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn, xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-    uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                                UBaseType_t uxIndexToClear,
-                                                uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */
-    {
-        uint32_t ulReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return ulReturn;
-    }
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength,
-                                           UBaseType_t uxItemSize,
-                                           uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
-    {
-        QueueHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
-                                                 const UBaseType_t uxItemSize,
-                                                 uint8_t * pucQueueStorage,
-                                                 StaticQueue_t * pxStaticQueue,
-                                                 const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
-    {
-        QueueHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue,
-                                   BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xReturn, xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xQueueGenericReset( pxQueue, xNewQueue );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xReturn, xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-    UBaseType_t uxReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    uxReturn = uxQueueMessagesWaiting( pxQueue );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-    UBaseType_t uxReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    uxReturn = uxQueueSpacesAvailable( xQueue );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xReturn, xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xReturn, xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xReturn, xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
-    TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */
-    {
-        void * xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xQueueGetMutexHolder( xSemaphore );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-    QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
-    {
-        QueueHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xQueueCreateMutex( ucQueueType );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-    QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
-                                               StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
-    {
-        QueueHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-    QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue,
-                                                     UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */
-    {
-        QueueHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
-    QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
-                                                           const UBaseType_t uxInitialCount,
-                                                           StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
-    {
-        QueueHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-    BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                             TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn, xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-    BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn, xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xQueueGiveMutexRecursive( xMutex );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-    QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */
-    {
-        QueueSetHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xQueueCreateSet( uxEventQueueLength );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-    QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                    TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */
-    {
-        QueueSetMemberHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-    BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                                   QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn, xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-    BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                                        QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn, xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if configQUEUE_REGISTRY_SIZE > 0
-    void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                                  const char * pcName ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vQueueAddToRegistry( xQueue, pcName );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif /* if configQUEUE_REGISTRY_SIZE > 0 */
-/*-----------------------------------------------------------*/
-
-#if configQUEUE_REGISTRY_SIZE > 0
-    void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vQueueUnregisterQueue( xQueue );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif /* if configQUEUE_REGISTRY_SIZE > 0 */
-/*-----------------------------------------------------------*/
-
-#if configQUEUE_REGISTRY_SIZE > 0
-    const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-    {
-        const char * pcReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        pcReturn = pcQueueGetName( xQueue );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return pcReturn;
-    }
-#endif /* if configQUEUE_REGISTRY_SIZE > 0 */
-/*-----------------------------------------------------------*/
-
-void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    vQueueDelete( xQueue );
-    vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
-    TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
-                                    const TickType_t xTimerPeriodInTicks,
-                                    const UBaseType_t uxAutoReload,
-                                    void * const pvTimerID,
-                                    TimerCallbackFunction_t pxCallbackFunction ) /* FREERTOS_SYSTEM_CALL */
-    {
-        TimerHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTimerCreate( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
-    TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
-                                          const TickType_t xTimerPeriodInTicks,
-                                          const UBaseType_t uxAutoReload,
-                                          void * const pvTimerID,
-                                          TimerCallbackFunction_t pxCallbackFunction,
-                                          StaticTimer_t * pxTimerBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        TimerHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-    void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        void * pvReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        pvReturn = pvTimerGetTimerID( xTimer );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return pvReturn;
-    }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-    void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                               void * pvNewID ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vTimerSetTimerID( xTimer, pvNewID );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-    BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn, xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTimerIsTimerActive( xTimer );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-    TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-    {
-        TaskHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTimerGetTimerDaemonTaskHandle();
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
-    BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
-                                           void * pvParameter1,
-                                           uint32_t ulParameter2,
-                                           TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn, xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-    void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                  const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        vTimerSetReloadMode( xTimer, uxAutoReload );
-        vPortResetPrivilege( xRunningPrivileged );
-    }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-    UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer )
-    {
-        UBaseType_t uxReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        uxReturn = uxTimerGetReloadMode( xTimer );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return uxReturn;
-    }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-    const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        const char * pcReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        pcReturn = pcTimerGetName( xTimer );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return pcReturn;
-    }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-    TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        TickType_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTimerGetPeriod( xTimer );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-    TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        TickType_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTimerGetExpiryTime( xTimer );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-    BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                         const BaseType_t xCommandID,
-                                         const TickType_t xOptionalValue,
-                                         BaseType_t * const pxHigherPriorityTaskWoken,
-                                         const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */
-    {
-        EventGroupHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xEventGroupCreate();
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        EventGroupHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xEventGroupCreateStatic( pxEventGroupBuffer );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    EventBits_t xReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
-{
-    EventBits_t xReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
-{
-    EventBits_t xReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    EventBits_t xReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    vEventGroupDelete( xEventGroup );
-    vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    size_t xReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-    size_t xReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    size_t xReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    vStreamBufferDelete( xStreamBuffer );
-    vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xReturn, xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xStreamBufferIsFull( xStreamBuffer );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xReturn, xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xStreamBufferIsEmpty( xStreamBuffer );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xReturn, xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xStreamBufferReset( xStreamBuffer );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-    size_t xReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-    size_t xReturn;
-    BaseType_t xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
-{
-    BaseType_t xReturn, xRunningPrivileged;
-
-    xPortRaisePrivilege( xRunningPrivileged );
-    xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
-    vPortResetPrivilege( xRunningPrivileged );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
-                                                         size_t xTriggerLevelBytes,
-                                                         BaseType_t xIsMessageBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        StreamBufferHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
-                                                               size_t xTriggerLevelBytes,
-                                                               BaseType_t xIsMessageBuffer,
-                                                               uint8_t * const pucStreamBufferStorageArea,
-                                                               StaticStreamBuffer_t * const pxStaticStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        StreamBufferHandle_t xReturn;
-        BaseType_t xRunningPrivileged;
-
-        xPortRaisePrivilege( xRunningPrivileged );
-        xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer );
-        vPortResetPrivilege( xRunningPrivileged );
-
-        return xReturn;
-    }
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-
-/* Functions that the application writer wants to execute in privileged mode
- * can be defined in application_defined_privileged_functions.h.  The functions
- * must take the same format as those above whereby the privilege state on exit
- * equals the privilege state on entry.  For example:
- *
- * void MPU_FunctionName( [parameters ] ) FREERTOS_SYSTEM_CALL;
- * void MPU_FunctionName( [parameters ] )
- * {
- * BaseType_t xRunningPrivileged;
- *
- * xPortRaisePrivilege( xRunningPrivileged );
- * FunctionName( [parameters ] );
- * vPortResetPrivilege( xRunningPrivileged );
- * }
- */
-
-#if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1
-    #include "application_defined_privileged_functions.h"
-#endif
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/port.c
deleted file mode 100644
index 108eb52..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/port.c
+++ /dev/null
@@ -1,933 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- *
- * The implementation in this file is weak to allow application writers to
- * change the timer used to generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether the current execution context is interrupt.
- *
- * @return pdTRUE if the current execution context is interrupt, pdFALSE
- * otherwise.
- */
-BaseType_t xPortIsInsideInterrupt( void );
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortIsInsideInterrupt( void )
-{
-uint32_t ulCurrentInterrupt;
-BaseType_t xReturn;
-
-	/* Obtain the number of the currently executing interrupt. Interrupt Program
-	 * Status Register (IPSR) holds the exception number of the currently-executing
-	 * exception or zero for Thread mode.*/
-	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-	if( ulCurrentInterrupt == 0 )
-	{
-		xReturn = pdFALSE;
-	}
-	else
-	{
-		xReturn = pdTRUE;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
\ No newline at end of file
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portasm.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portasm.c
deleted file mode 100644
index ea216bd..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portasm.c
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str  r4, [r2]									\n" /* Program RNR = 4. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r3!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	"	ldr  r5, xSecureContextConst2					\n"
-	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	"	ldr  r4, xSecureContextConst2					\n"
-	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	"xSecureContextConst2: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne											\n"
-	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs r0, control									\n" /* Read the CONTROL register. */
-	"	bic r0, #1										\n" /* Clear the bit 0. */
-	"	msr control, r0									\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	orr r0, #1										\n" /* r0 = r0 | 1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	cpsie f											\n"
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, basepri									\n" /* r0 = basepri. Return original basepri value. */
-	"	mov r1, %0										\n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	"	msr basepri, r1									\n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	bx lr											\n" /* Return. */
-	:: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr basepri, r0									\n" /* basepri = ulMask. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	bx lr											\n" /* Return. */
-	::: "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"	.extern SecureContext_SaveContext				\n"
-	"	.extern SecureContext_LoadContext				\n"
-	"													\n"
-	"	mrs r1, psp										\n" /* Read PSP in r1. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-	"													\n"
-	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
-	"	push {r0-r2, r14}								\n"
-	"	bl SecureContext_SaveContext					\n"
-	"	pop {r0-r3}										\n" /* LR is now in r3. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"	b select_next_task								\n"
-	"													\n"
-	" save_ns_context:									\n"
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vstmdbeq r1!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
-	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	subs r1, r1, #16								\n" /* r1 = r1 - 16. */
-	"	stm r1, {r0, r2-r4}								\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #12								\n" /* r1 = r1 + 12. */
-	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	subs r1, r1, #12								\n" /* r1 = r1 - 12. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" select_next_task:									\n"
-	"	mov r0, %0										\n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-	"	msr basepri, r0									\n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	bl vTaskSwitchContext							\n"
-	"	mov r0, #0										\n" /* r0 = 0. */
-	"	msr basepri, r0									\n" /* Enable interrupts. */
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str r4, [r2]									\n" /* Program RNR = 4. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r3!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r4}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r4}										\n"
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#else /* configENABLE_MPU */
-	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r3}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r3}										\n"
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" restore_ns_context:								\n"
-	"	ldmia r1!, {r4-r11}								\n" /* Restore the registers that are not automatically restored. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vldmiaeq r1!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	"xSecureContextConst: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	:: "i"( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	tst lr, #4										\n"
-	"	ite eq											\n"
-	"	mrseq r0, msp									\n"
-	"	mrsne r0, psp									\n"
-	"	ldr r1, svchandler_address_const				\n"
-	"	bx r1											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
-	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
-	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
-	"	it ne											\n"
-	"	svcne %0										\n" /* Secure context is freed in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portasm.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portasm.h
deleted file mode 100644
index cc2562f..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMask( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portmacro.h
deleted file mode 100644
index 8d1ab81..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern BaseType_t xPortIsInsideInterrupt( void );
-
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )				vClearInterruptMask( x )
-#define portDISABLE_INTERRUPTS()							ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()								vClearInterruptMask( 0 )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context.c
deleted file mode 100644
index 586e133..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief CONTROL value for privileged tasks.
- *
- * Bit[0] - 0 --> Thread mode is privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
-
-/**
- * @brief CONTROL value for un-privileged tasks.
- *
- * Bit[0] - 1 --> Thread mode is un-privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Structure to represent secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first addess of the allocated memory.
- */
-typedef struct SecureContext
-{
-	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
-	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
-	uint8_t *pucStackStart;				/**< First location of the stack memory. */
-} SecureContext_t;
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* No stack for thread mode until a task's context is loaded. */
-		secureportSET_PSPLIM( securecontextNO_STACK );
-		secureportSET_PSP( securecontextNO_STACK );
-
-		#if( configENABLE_MPU == 1 )
-		{
-			/* Configure thread mode to use PSP and to be unprivileged. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-		}
-		#else /* configENABLE_MPU */
-		{
-			/* Configure thread mode to use PSP and to be privileged.. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-		}
-		#endif /* configENABLE_MPU */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
-#else /* configENABLE_MPU */
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
-#endif /* configENABLE_MPU */
-{
-	uint8_t *pucStackMemory = NULL;
-	uint32_t ulIPSR;
-	SecureContextHandle_t xSecureContextHandle = NULL;
-	#if( configENABLE_MPU == 1 )
-		uint32_t *pulCurrentStackPointer = NULL;
-	#endif /* configENABLE_MPU */
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Allocate the context structure. */
-		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
-
-		if( xSecureContextHandle != NULL )
-		{
-			/* Allocate the stack space. */
-			pucStackMemory = pvPortMalloc( ulSecureStackSize );
-
-			if( pucStackMemory != NULL )
-			{
-				/* Since stack grows down, the starting point will be the last
-				 * location. Note that this location is next to the last
-				 * allocated byte because the hardware decrements the stack
-				 * pointer before writing i.e. if stack pointer is 0x2, a push
-				 * operation will decrement the stack pointer to 0x1 and then
-				 * write at 0x1. */
-				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
-
-				/* The stack cannot go beyond this location. This value is
-				 * programmed in the PSPLIM register on context switch.*/
-				xSecureContextHandle->pucStackLimit = pucStackMemory;
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Store the correct CONTROL value for the task on the stack.
-					 * This value is programmed in the CONTROL register on
-					 * context switch. */
-					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
-					pulCurrentStackPointer--;
-					if( ulIsTaskPrivileged )
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-					}
-					else
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-					}
-
-					/* Store the current stack pointer. This value is programmed in
-					 * the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
-				}
-				#else /* configENABLE_MPU */
-				{
-					/* Current SP is set to the starting of the stack. This
-					 * value programmed in the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
-
-				}
-				#endif /* configENABLE_MPU */
-			}
-			else
-			{
-				/* Free the context to avoid memory leak and make sure to return
-				 * NULL to indicate failure. */
-				vPortFree( xSecureContextHandle );
-				xSecureContextHandle = NULL;
-			}
-		}
-	}
-
-	return xSecureContextHandle;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Ensure that valid parameters are passed. */
-		secureportASSERT( xSecureContextHandle != NULL );
-
-		/* Free the stack space. */
-		vPortFree( xSecureContextHandle->pucStackLimit );
-
-		/* Free the context itself. */
-		vPortFree( xSecureContextHandle );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context.h
deleted file mode 100644
index 77db8b6..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_CONTEXT_H__
-#define __SECURE_CONTEXT_H__
-
-/* Standard includes. */
-#include 
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/**
- * @brief PSP value when no task's context is loaded.
- */
-#define securecontextNO_STACK	0x0
-
-/**
- * @brief Opaque handle.
- */
-struct SecureContext;
-typedef struct SecureContext*	SecureContextHandle_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Initializes the secure context management system.
- *
- * PSP is set to NULL and therefore a task must allocate and load a context
- * before calling any secure side function in the thread mode.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureContext_Init( void );
-
-/**
- * @brief Allocates a context on the secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
- * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
- *
- * @return Opaque context handle if context is successfully allocated, NULL
- * otherwise.
- */
-#if( configENABLE_MPU == 1 )
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
-#else /* configENABLE_MPU */
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
-#endif /* configENABLE_MPU */
-
-/**
- * @brief Frees the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the
- * context to be freed.
- */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Loads the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be loaded.
- */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Saves the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be saved.
- */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
-
-#endif /* __SECURE_CONTEXT_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context_port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context_port.c
deleted file mode 100644
index 8d9c8c6..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_context_port.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	"	msr control, r3							\n" /* CONTROL = r3. */
-	#endif /* configENABLE_MPU */
-	"	msr psplim, r2							\n" /* PSPLIM = r2. */
-	"	msr psp, r1								\n" /* PSP = r1. */
-	"											\n"
-	" load_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:::"r0", "r1", "r2"
-	);
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	mrs r1, psp								\n" /* r1 = PSP. */
-	#if( configENABLE_FPU == 1 )
-	"	vstmdb r1!, {s0}						\n" /* Trigger the defferred stacking of FPU registers. */
-	"	vldmia r1!, {s0}						\n" /* Nullify the effect of the pervious statement. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r2, control							\n" /* r2 = CONTROL. */
-	"	stmdb r1!, {r2}							\n" /* Store CONTROL value on the stack. */
-	#endif /* configENABLE_MPU */
-	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
-	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
-	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-	"											\n"
-	" save_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_heap.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_heap.c
deleted file mode 100644
index ab167ab..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_heap.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure context heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Total heap size.
- */
-#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
-
-/* No test marker by default. */
-#ifndef mtCOVERAGE_TEST_MARKER
-	#define mtCOVERAGE_TEST_MARKER()
-#endif
-
-/* No tracing by default. */
-#ifndef traceMALLOC
-	#define traceMALLOC( pvReturn, xWantedSize )
-#endif
-
-/* No tracing by default. */
-#ifndef traceFREE
-	#define traceFREE( pv, xBlockSize )
-#endif
-
-/* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
-/*-----------------------------------------------------------*/
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	 * heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#else /* configAPPLICATION_ALLOCATED_HEAP */
-	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/**
- * @brief The linked list structure.
- *
- * This is used to link free blocks in order of their memory address.
- */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
-	size_t xBlockSize;						/**< The size of the free block. */
-} BlockLink_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Called automatically to setup the required heap structures the first
- * time pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/**
- * @brief Inserts a block of memory that is being freed into the correct
- * position in the list of free memory blocks.
- *
- * The block being freed will be merged with the block in front it and/or the
- * block behind it if the memory blocks are adjacent to each other.
- *
- * @param[in] pxBlockToInsert The block being freed.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The size of the structure placed at the beginning of each allocated
- * memory block must by correctly byte aligned.
- */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-
-/**
- * @brief Create a couple of list links to mark the start and end of the list.
- */
-static BlockLink_t xStart, *pxEnd = NULL;
-
-/**
- * @brief Keeps track of the number of free bytes remaining, but says nothing
- * about fragmentation.
- */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-size_t uxAddress;
-size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
-
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	uxAddress = ( size_t ) ucHeap;
-
-	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
-	{
-		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
-		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-	}
-
-	pucAlignedHeap = ( uint8_t * ) uxAddress;
-
-	/* xStart is used to hold a pointer to the first item in the list of free
-	 * blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
-
-	/* pxEnd is used to mark the end of the list of free blocks and is inserted
-	 * at the end of the heap space. */
-	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-	uxAddress -= xHeapStructSize;
-	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-	pxEnd = ( void * ) uxAddress;
-	pxEnd->xBlockSize = 0;
-	pxEnd->pxNextFreeBlock = NULL;
-
-	/* To start with there is a single free block that is sized to take up the
-	 * entire heap space, minus the space taken by pxEnd. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
-	/* Only one block exists - and it covers the entire usable heap space. */
-	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
-{
-BlockLink_t *pxIterator;
-uint8_t *puc;
-
-	/* Iterate through the list until a block is found that has a higher address
-	 * than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
-
-	/* Do the block being inserted, and the block it is being inserted after
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Do the block being inserted, and the block it is being inserted before
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
-
-	/* If the block being inserted plugged a gab, so was merged with the block
-	 * before and the block after, then it's pxNextFreeBlock pointer will have
-	 * already been set, and should not be set here as that would make it point
-	 * to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
-
-	/* If this is the first call to malloc then the heap will require
-	 * initialisation to setup the list of free blocks. */
-	if( pxEnd == NULL )
-	{
-		prvHeapInit();
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Check the requested block size is not so large that the top bit is set.
-	 * The top bit of the block size member of the BlockLink_t structure is used
-	 * to determine who owns the block - the application or the kernel, so it
-	 * must be free. */
-	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-	{
-		/* The wanted size is increased so it can contain a BlockLink_t
-		 * structure in addition to the requested amount of bytes. */
-		if( xWantedSize > 0 )
-		{
-			xWantedSize += xHeapStructSize;
-
-			/* Ensure that blocks are always aligned to the required number of
-			 * bytes. */
-			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
-			{
-				/* Byte alignment required. */
-				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-		{
-			/* Traverse the list from the start (lowest address) block until
-			 * one of adequate size is found. */
-			pxPreviousBlock = &xStart;
-			pxBlock = xStart.pxNextFreeBlock;
-			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-			{
-				pxPreviousBlock = pxBlock;
-				pxBlock = pxBlock->pxNextFreeBlock;
-			}
-
-			/* If the end marker was reached then a block of adequate size was
-			 * not found. */
-			if( pxBlock != pxEnd )
-			{
-				/* Return the memory space pointed to - jumping over the
-				 * BlockLink_t structure at its start. */
-				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-				/* This block is being returned for use so must be taken out
-				 * of the list of free blocks. */
-				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-				/* If the block is larger than required it can be split into
-				 * two. */
-				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
-				{
-					/* This block is to be split into two.  Create a new
-					 * block following the number of bytes requested. The void
-					 * cast is used to prevent byte alignment warnings from the
-					 * compiler. */
-					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-
-					/* Calculate the sizes of two blocks split from the single
-					 * block. */
-					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-					pxBlock->xBlockSize = xWantedSize;
-
-					/* Insert the new block into the list of free blocks. */
-					prvInsertBlockIntoFreeList( pxNewBlockLink );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-				{
-					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* The block is being returned - it is allocated and owned by
-				 * the application and has no "next" block. */
-				pxBlock->xBlockSize |= xBlockAllocatedBit;
-				pxBlock->pxNextFreeBlock = NULL;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	traceMALLOC( pvReturn, xWantedSize );
-
-	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
-
-	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		 * before it. */
-		puc -= xHeapStructSize;
-
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
-
-		/* Check the block is actually allocated. */
-		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
-
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				 * allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-				secureportDISABLE_NON_SECURE_INTERRUPTS();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				secureportENABLE_NON_SECURE_INTERRUPTS();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_heap.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_heap.h
deleted file mode 100644
index 6a8452b..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_heap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_HEAP_H__
-#define __SECURE_HEAP_H__
-
-/* Standard includes. */
-#include 
-
-/**
- * @brief Allocates memory from heap.
- *
- * @param[in] xWantedSize The size of the memory to be allocated.
- *
- * @return Pointer to the memory region if the allocation is successful, NULL
- * otherwise.
- */
-void *pvPortMalloc( size_t xWantedSize );
-
-/**
- * @brief Frees the previously allocated memory.
- *
- * @param[in] pv Pointer to the memory to be freed.
- */
-void vPortFree( void *pv );
-
-#endif /* __SECURE_HEAP_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_init.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_init.c
deleted file mode 100644
index d46a936..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_init.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure init includes. */
-#include "secure_init.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS			( 29UL )
-#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS				( 26UL )
-#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
-
-#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS			( 10UL )
-#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS			( 11UL )
-#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
-									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
-									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
-		 * permitted. CP11 should be programmed to the same value as CP10. */
-		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
-
-		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
-		 * that we can enable/disable lazy stacking in port.c file. */
-		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
-
-		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
-		 * registers (S16-S31) are also pushed to stack on exception entry and
-		 * restored on exception return. */
-		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_init.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_init.h
deleted file mode 100644
index a8c2090..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_init.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_INIT_H__
-#define __SECURE_INIT_H__
-
-/**
- * @brief De-prioritizes the non-secure exceptions.
- *
- * This is needed to ensure that the non-secure PendSV runs at the lowest
- * priority. Context switch is done in the non-secure PendSV handler.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_DePrioritizeNSExceptions( void );
-
-/**
- * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
- *
- * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
- * Registers are not leaked to the non-secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_EnableNSFPUAccess( void );
-
-#endif /* __SECURE_INIT_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_port_macros.h
deleted file mode 100644
index 40e1864..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33/secure/secure_port_macros.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_PORT_MACROS_H__
-#define __SECURE_PORT_MACROS_H__
-
-/**
- * @brief Byte alignment requirements.
- */
-#define secureportBYTE_ALIGNMENT					8
-#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
-
-/**
- * @brief Macro to declare a function as non-secure callable.
- */
-#if defined( __IAR_SYSTEMS_ICC__ )
-	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
-#else
-	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
-#endif
-
-/**
- * @brief Set the secure PRIMASK value.
- */
-#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Set the non-secure PRIMASK value.
- */
-#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Read the PSP value in the given variable.
- */
-#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
-	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
-
-/**
- * @brief Set the PSP to the given value.
- */
-#define secureportSET_PSP( pucCurrentStackPointer ) \
-	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
-
-/**
- * @brief Set the PSPLIM to the given value.
- */
-#define secureportSET_PSPLIM( pucStackLimit ) \
-	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
-
-/**
- * @brief Set the NonSecure MSP to the given value.
- */
-#define secureportSET_MSP_NS( pucMainStackPointer ) \
-	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
-
-/**
- * @brief Set the CONTROL register to the given value.
- */
-#define secureportSET_CONTROL( ulControl ) \
-	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
-
-/**
- * @brief Read the Interrupt Program Status Register (IPSR) value in the given
- * variable.
- */
-#define secureportREAD_IPSR( ulIPSR ) \
-	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
-
-/**
- * @brief PRIMASK value to enable interrupts.
- */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
-
-/**
- * @brief PRIMASK value to disable interrupts.
- */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
-
-/**
- * @brief Disable secure interrupts.
- */
-#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Disable non-secure interrupts.
- *
- * This effectively disables context switches.
- */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Enable non-secure interrupts.
- */
-#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Assert definition.
- */
-#define secureportASSERT( x )						\
-	if( ( x ) == 0 )								\
-	{												\
-		secureportDISABLE_SECURE_INTERRUPTS();		\
-		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
-		for( ;; );									\
-	}
-
-#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
deleted file mode 100644
index 108eb52..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ /dev/null
@@ -1,933 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- *
- * The implementation in this file is weak to allow application writers to
- * change the timer used to generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether the current execution context is interrupt.
- *
- * @return pdTRUE if the current execution context is interrupt, pdFALSE
- * otherwise.
- */
-BaseType_t xPortIsInsideInterrupt( void );
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortIsInsideInterrupt( void )
-{
-uint32_t ulCurrentInterrupt;
-BaseType_t xReturn;
-
-	/* Obtain the number of the currently executing interrupt. Interrupt Program
-	 * Status Register (IPSR) holds the exception number of the currently-executing
-	 * exception or zero for Thread mode.*/
-	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-	if( ulCurrentInterrupt == 0 )
-	{
-		xReturn = pdFALSE;
-	}
-	else
-	{
-		xReturn = pdTRUE;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
\ No newline at end of file
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
deleted file mode 100644
index 2a9f214..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr  r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r3, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r3, #4										\n" /* r3 = 4. */
-	"	str  r3, [r2]									\n" /* Program RNR = 4. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r1!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne											\n"
-	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs  r0, control								\n" /* Read the CONTROL register. */
-	"	bic r0, #1										\n" /* Clear the bit 0. */
-	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	orr r0, #1										\n" /* r0 = r0 | 1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	cpsie f											\n"
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, basepri									\n" /* r0 = basepri. Return original basepri value. */
-	"	mov r1, %0										\n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	"	msr basepri, r1									\n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	bx lr											\n" /* Return. */
-	:: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr basepri, r0									\n" /* basepri = ulMask. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	bx lr											\n" /* Return. */
-	::: "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	mrs r0, psp										\n" /* Read PSP in r0. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vstmdbeq r0!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
-	"	mrs r2, control									\n" /* r2 = CONTROL. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmdb r0!, {r1-r11}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
-	#else /* configENABLE_MPU */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmdb r0!, {r2-r11}								\n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
-	"													\n"
-	"	mov r0, %0										\n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-	"	msr basepri, r0									\n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	bl vTaskSwitchContext							\n"
-	"	mov r0, #0										\n" /* r0 = 0. */
-	"	msr basepri, r0									\n" /* Enable interrupts. */
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r3, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r3, #4										\n" /* r3 = 4. */
-	"	str r3, [r2]									\n" /* Program RNR = 4. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	ldr r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r1!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r0!, {r1-r11}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
-	#else /* configENABLE_MPU */
-	"	ldmia r0!, {r2-r11}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_FPU == 1 )
-	"	tst r3, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vldmiaeq r0!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
-	#else /* configENABLE_MPU */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	#endif /* configENABLE_MPU */
-	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
-	"	bx r3											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	:: "i"( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	tst lr, #4										\n"
-	"	ite eq											\n"
-	"	mrseq r0, msp									\n"
-	"	mrsne r0, psp									\n"
-	"	ldr r1, svchandler_address_const				\n"
-	"	bx r1											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
deleted file mode 100644
index cc2562f..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMask( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
deleted file mode 100644
index cf979d2..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * FreeRTOS Kernel V10.3.0
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern BaseType_t xPortIsInsideInterrupt( void );
-
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMask( x )
-#define portDISABLE_INTERRUPTS()							ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()								vClearInterruptMask( 0 )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM4F/port.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM4F/port.c
deleted file mode 100644
index 5a7c4b6..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM4F/port.c
+++ /dev/null
@@ -1,783 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM CM4F port.
-*----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __VFP_FP__
-    #error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
-    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
-    /* Ensure the SysTick is clocked at the same frequency as the core. */
-    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
-    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
-
-/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
- * r0p1 port. */
-#define portCPUID                             ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
-#define portCORTEX_M7_r0p1_ID                 ( 0x410FC271UL )
-#define portCORTEX_M7_r0p0_ID                 ( 0x410FC270UL )
-
-#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
-#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT                    ( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK                   ( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR                      ( 0x01000000 )
-#define portINITIAL_EXC_RETURN                ( 0xfffffffd )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
- * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
- * occurred while the SysTick counter is stopped during tickless idle
- * calculations. */
-#define portMISSED_COUNTS_FACTOR              ( 45UL )
-
-/* Let the user override the pre-loading of the initial LR with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
-#else
-    #define portTASK_RETURN_ADDRESS    prvTaskExitError
-#endif
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__( ( naked ) );
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void ) __attribute__( ( naked ) );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvPortStartFirstTask( void ) __attribute__( ( naked ) );
-
-/*
- * Function to enable the VFP.
- */
-static void vPortEnableVFP( void ) __attribute__( ( naked ) );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
- * variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
-    static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
-    static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
-    static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
-    static uint8_t ucMaxSysCallPriority = 0;
-    static uint32_t ulMaxPRIGROUPValue = 0;
-    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-
-    /* Offset added to account for the way the MCU uses the stack on entry/exit
-     * of interrupts, and to ensure alignment. */
-    pxTopOfStack--;
-
-    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
-    pxTopOfStack--;
-    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;             /* LR */
-
-    /* Save code space by skipping register initialisation. */
-    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */
-    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-
-    /* A save method is being used that requires each task to maintain its
-     * own exec return value. */
-    pxTopOfStack--;
-    *pxTopOfStack = portINITIAL_EXC_RETURN;
-
-    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-    return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-    volatile uint32_t ulDummy = 0;
-
-    /* A function that implements a task must not exit or attempt to return to
-     * its caller as there is nothing to return to.  If a task wants to exit it
-     * should instead call vTaskDelete( NULL ).
-     *
-     * Artificially force an assert() to be triggered if configASSERT() is
-     * defined, then stop here so application writers can catch the error. */
-    configASSERT( uxCriticalNesting == ~0UL );
-    portDISABLE_INTERRUPTS();
-
-    while( ulDummy == 0 )
-    {
-        /* This file calls prvTaskExitError() after the scheduler has been
-         * started to remove a compiler warning about the function being defined
-         * but never called.  ulDummy is used purely to quieten other warnings
-         * about code appearing after this function is called - making ulDummy
-         * volatile makes the compiler think the function could return and
-         * therefore not output an 'unreachable code' warning for code that appears
-         * after it. */
-    }
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
-    __asm volatile (
-        "	ldr	r3, pxCurrentTCBConst2		\n"/* Restore the context. */
-        "	ldr r1, [r3]					\n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
-        "	ldr r0, [r1]					\n"/* The first item in pxCurrentTCB is the task top of stack. */
-        "	ldmia r0!, {r4-r11, r14}		\n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
-        "	msr psp, r0						\n"/* Restore the task stack pointer. */
-        "	isb								\n"
-        "	mov r0, #0 						\n"
-        "	msr	basepri, r0					\n"
-        "	bx r14							\n"
-        "									\n"
-        "	.align 4						\n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-        );
-}
-/*-----------------------------------------------------------*/
-
-static void prvPortStartFirstTask( void )
-{
-    /* Start the first task.  This also clears the bit that indicates the FPU is
-     * in use in case the FPU was used before the scheduler was started - which
-     * would otherwise result in the unnecessary leaving of space in the SVC stack
-     * for lazy saving of FPU registers. */
-    __asm volatile (
-        " ldr r0, =0xE000ED08 	\n"/* Use the NVIC offset register to locate the stack. */
-        " ldr r0, [r0] 			\n"
-        " ldr r0, [r0] 			\n"
-        " msr msp, r0			\n"/* Set the msp back to the start of the stack. */
-        " mov r0, #0			\n"/* Clear the bit that indicates the FPU is in use, see comment above. */
-        " msr control, r0		\n"
-        " cpsie i				\n"/* Globally enable interrupts. */
-        " cpsie f				\n"
-        " dsb					\n"
-        " isb					\n"
-        " svc 0					\n"/* System call to start first task. */
-        " nop					\n"
-        " .ltorg				\n"
-        );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
-    /* This port can be used on all revisions of the Cortex-M7 core other than
-     * the r0p1 parts.  r0p1 parts should use the port from the
-     * /source/portable/GCC/ARM_CM7/r0p1 directory. */
-    configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
-    configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
-
-    #if ( configASSERT_DEFINED == 1 )
-        {
-            volatile uint32_t ulOriginalPriority;
-            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-            volatile uint8_t ucMaxPriorityValue;
-
-            /* Determine the maximum priority from which ISR safe FreeRTOS API
-             * functions can be called.  ISR safe functions are those that end in
-             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-             * ensure interrupt entry is as fast and simple as possible.
-             *
-             * Save the interrupt priority value that is about to be clobbered. */
-            ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-            /* Determine the number of priority bits available.  First write to all
-             * possible bits. */
-            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-            /* Read the value back to see how many bits stuck. */
-            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-            /* Use the same mask on the maximum system call priority. */
-            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-            /* Calculate the maximum acceptable priority group value for the number
-             * of bits read back. */
-            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
-            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-            {
-                ulMaxPRIGROUPValue--;
-                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-            }
-
-            #ifdef __NVIC_PRIO_BITS
-                {
-                    /* Check the CMSIS configuration that defines the number of
-                     * priority bits matches the number of priority bits actually queried
-                     * from the hardware. */
-                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-                }
-            #endif
-
-            #ifdef configPRIO_BITS
-                {
-                    /* Check the FreeRTOS configuration that defines the number of
-                     * priority bits matches the number of priority bits actually queried
-                     * from the hardware. */
-                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-                }
-            #endif
-
-            /* Shift the priority group value back to its position within the AIRCR
-             * register. */
-            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-            /* Restore the clobbered interrupt priority register to its original
-             * value. */
-            *pucFirstUserPriorityRegister = ulOriginalPriority;
-        }
-    #endif /* conifgASSERT_DEFINED */
-
-    /* Make PendSV and SysTick the lowest priority interrupts. */
-    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
-    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
-
-    /* Start the timer that generates the tick ISR.  Interrupts are disabled
-     * here already. */
-    vPortSetupTimerInterrupt();
-
-    /* Initialise the critical nesting count ready for the first task. */
-    uxCriticalNesting = 0;
-
-    /* Ensure the VFP is enabled - it should be anyway. */
-    vPortEnableVFP();
-
-    /* Lazy save always. */
-    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
-    /* Start the first task. */
-    prvPortStartFirstTask();
-
-    /* Should never get here as the tasks will now be executing!  Call the task
-     * exit error function to prevent compiler warnings about a static function
-     * not being called in the case that the application writer overrides this
-     * functionality by defining configTASK_RETURN_ADDRESS.  Call
-     * vTaskSwitchContext() so link time optimisation does not remove the
-     * symbol. */
-    vTaskSwitchContext();
-    prvTaskExitError();
-
-    /* Should not get here! */
-    return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-    /* Not implemented in ports where there is nothing to return to.
-     * Artificially force an assert. */
-    configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-    portDISABLE_INTERRUPTS();
-    uxCriticalNesting++;
-
-    /* This is not the interrupt safe version of the enter critical function so
-     * assert() if it is being called from an interrupt context.  Only API
-     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
-     * the critical nesting count is 1 to protect against recursive calls if the
-     * assert function also uses a critical section. */
-    if( uxCriticalNesting == 1 )
-    {
-        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-    }
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-    configASSERT( uxCriticalNesting );
-    uxCriticalNesting--;
-
-    if( uxCriticalNesting == 0 )
-    {
-        portENABLE_INTERRUPTS();
-    }
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
-    /* This is a naked function. */
-
-    __asm volatile
-    (
-        "	mrs r0, psp							\n"
-        "	isb									\n"
-        "										\n"
-        "	ldr	r3, pxCurrentTCBConst			\n"/* Get the location of the current TCB. */
-        "	ldr	r2, [r3]						\n"
-        "										\n"
-        "	tst r14, #0x10						\n"/* Is the task using the FPU context?  If so, push high vfp registers. */
-        "	it eq								\n"
-        "	vstmdbeq r0!, {s16-s31}				\n"
-        "										\n"
-        "	stmdb r0!, {r4-r11, r14}			\n"/* Save the core registers. */
-        "	str r0, [r2]						\n"/* Save the new top of stack into the first member of the TCB. */
-        "										\n"
-        "	stmdb sp!, {r0, r3}					\n"
-        "	mov r0, %0 							\n"
-        "	msr basepri, r0						\n"
-        "	dsb									\n"
-        "	isb									\n"
-        "	bl vTaskSwitchContext				\n"
-        "	mov r0, #0							\n"
-        "	msr basepri, r0						\n"
-        "	ldmia sp!, {r0, r3}					\n"
-        "										\n"
-        "	ldr r1, [r3]						\n"/* The first item in pxCurrentTCB is the task top of stack. */
-        "	ldr r0, [r1]						\n"
-        "										\n"
-        "	ldmia r0!, {r4-r11, r14}			\n"/* Pop the core registers. */
-        "										\n"
-        "	tst r14, #0x10						\n"/* Is the task using the FPU context?  If so, pop the high vfp registers too. */
-        "	it eq								\n"
-        "	vldmiaeq r0!, {s16-s31}				\n"
-        "										\n"
-        "	msr psp, r0							\n"
-        "	isb									\n"
-        "										\n"
-        #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
-            #if WORKAROUND_PMU_CM001 == 1
-                "			push { r14 }				\n"
-                "			pop { pc }					\n"
-            #endif
-        #endif
-        "										\n"
-        "	bx r14								\n"
-        "										\n"
-        "	.align 4							\n"
-        "pxCurrentTCBConst: .word pxCurrentTCB	\n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
-     * executes all interrupts must be unmasked.  There is therefore no need to
-     * save and then restore the interrupt mask value as its value is already
-     * known. */
-    portDISABLE_INTERRUPTS();
-    {
-        /* Increment the RTOS tick. */
-        if( xTaskIncrementTick() != pdFALSE )
-        {
-            /* A context switch is required.  Context switching is performed in
-             * the PendSV interrupt.  Pend the PendSV interrupt. */
-            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-        }
-    }
-    portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TICKLESS_IDLE == 1 )
-
-    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-    {
-        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-        TickType_t xModifiableIdleTime;
-
-        /* Make sure the SysTick reload value does not overflow the counter. */
-        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-        {
-            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-        }
-
-        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
-         * is accounted for as best it can be, but using the tickless mode will
-         * inevitably result in some tiny drift of the time maintained by the
-         * kernel with respect to calendar time. */
-        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-        /* Calculate the reload value required to wait xExpectedIdleTime
-         * tick periods.  -1 is used because this code will execute part way
-         * through one of the tick periods. */
-        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
-        if( ulReloadValue > ulStoppedTimerCompensation )
-        {
-            ulReloadValue -= ulStoppedTimerCompensation;
-        }
-
-        /* Enter a critical section but don't use the taskENTER_CRITICAL()
-         * method as that will mask interrupts that should exit sleep mode. */
-        __asm volatile ( "cpsid i" ::: "memory" );
-        __asm volatile ( "dsb" );
-        __asm volatile ( "isb" );
-
-        /* If a context switch is pending or a task is waiting for the scheduler
-         * to be unsuspended then abandon the low power entry. */
-        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-        {
-            /* Restart from whatever is left in the count register to complete
-             * this tick period. */
-            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-            /* Restart SysTick. */
-            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-            /* Reset the reload register to the value required for normal tick
-             * periods. */
-            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-            /* Re-enable interrupts - see comments above the cpsid instruction()
-             * above. */
-            __asm volatile ( "cpsie i" ::: "memory" );
-        }
-        else
-        {
-            /* Set the new reload value. */
-            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-            /* Clear the SysTick count flag and set the count value back to
-             * zero. */
-            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-            /* Restart SysTick. */
-            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-             * set its parameter to 0 to indicate that its implementation contains
-             * its own wait for interrupt or wait for event instruction, and so wfi
-             * should not be executed again.  However, the original expected idle
-             * time variable must remain unmodified, so a copy is taken. */
-            xModifiableIdleTime = xExpectedIdleTime;
-            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-
-            if( xModifiableIdleTime > 0 )
-            {
-                __asm volatile ( "dsb" ::: "memory" );
-                __asm volatile ( "wfi" );
-                __asm volatile ( "isb" );
-            }
-
-            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-            /* Re-enable interrupts to allow the interrupt that brought the MCU
-             * out of sleep mode to execute immediately.  see comments above
-             * __disable_interrupt() call above. */
-            __asm volatile ( "cpsie i" ::: "memory" );
-            __asm volatile ( "dsb" );
-            __asm volatile ( "isb" );
-
-            /* Disable interrupts again because the clock is about to be stopped
-             * and interrupts that execute while the clock is stopped will increase
-             * any slippage between the time maintained by the RTOS and calendar
-             * time. */
-            __asm volatile ( "cpsid i" ::: "memory" );
-            __asm volatile ( "dsb" );
-            __asm volatile ( "isb" );
-
-            /* Disable the SysTick clock without reading the
-             * portNVIC_SYSTICK_CTRL_REG register to ensure the
-             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
-             * the time the SysTick is stopped for is accounted for as best it can
-             * be, but using the tickless mode will inevitably result in some tiny
-             * drift of the time maintained by the kernel with respect to calendar
-             * time*/
-            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-            /* Determine if the SysTick clock has already counted to zero and
-             * been set back to the current reload value (the reload back being
-             * correct for the entire expected idle time) or if the SysTick is yet
-             * to count to zero (in which case an interrupt other than the SysTick
-             * must have brought the system out of sleep mode). */
-            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-            {
-                uint32_t ulCalculatedLoadValue;
-
-                /* The tick interrupt is already pending, and the SysTick count
-                 * reloaded with ulReloadValue.  Reset the
-                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-                 * period. */
-                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-                /* Don't allow a tiny value, or values that have somehow
-                 * underflowed because the post sleep hook did something
-                 * that took too long. */
-                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-                {
-                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-                }
-
-                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-                /* As the pending tick will be processed as soon as this
-                 * function exits, the tick value maintained by the tick is stepped
-                 * forward by one less than the time spent waiting. */
-                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-            }
-            else
-            {
-                /* Something other than the tick interrupt ended the sleep.
-                 * Work out how long the sleep lasted rounded to complete tick
-                 * periods (not the ulReload value which accounted for part
-                 * ticks). */
-                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-                /* How many complete tick periods passed while the processor
-                 * was waiting? */
-                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-                /* The reload value is set to whatever fraction of a single tick
-                 * period remains. */
-                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-            }
-
-            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-             * value. */
-            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-            vTaskStepTick( ulCompleteTickPeriods );
-            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-            /* Exit with interrupts enabled. */
-            __asm volatile ( "cpsie i" ::: "memory" );
-        }
-    }
-
-#endif /* #if configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
-{
-    /* Calculate the constants required to configure the tick interrupt. */
-    #if ( configUSE_TICKLESS_IDLE == 1 )
-        {
-            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-        }
-    #endif /* configUSE_TICKLESS_IDLE */
-
-    /* Stop and clear the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
-    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-    /* Configure SysTick to interrupt at the requested rate. */
-    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-/* This is a naked function. */
-static void vPortEnableVFP( void )
-{
-    __asm volatile
-    (
-        "	ldr.w r0, =0xE000ED88		\n"/* The FPU enable bits are in the CPACR. */
-        "	ldr r1, [r0]				\n"
-        "								\n"
-        "	orr r1, r1, #( 0xf << 20 )	\n"/* Enable CP10 and CP11 coprocessors, then save back. */
-        "	str r1, [r0]				\n"
-        "	bx r14						\n"
-        "	.ltorg						\n"
-    );
-}
-/*-----------------------------------------------------------*/
-
-#if ( configASSERT_DEFINED == 1 )
-
-    void vPortValidateInterruptPriority( void )
-    {
-        uint32_t ulCurrentInterrupt;
-        uint8_t ucCurrentPriority;
-
-        /* Obtain the number of the currently executing interrupt. */
-        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
-        /* Is the interrupt number a user defined interrupt? */
-        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-        {
-            /* Look up the interrupt's priority. */
-            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-            /* The following assertion will fail if a service routine (ISR) for
-             * an interrupt that has been assigned a priority above
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-             * function.  ISR safe FreeRTOS API functions must *only* be called
-             * from interrupts that have been assigned a priority at or below
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
-             *
-             * Numerically low interrupt priority numbers represent logically high
-             * interrupt priorities, therefore the priority of the interrupt must
-             * be set to a value equal to or numerically *higher* than
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
-             *
-             * Interrupts that	use the FreeRTOS API must not be left at their
-             * default priority of	zero as that is the highest possible priority,
-             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-             * and	therefore also guaranteed to be invalid.
-             *
-             * FreeRTOS maintains separate thread and ISR API functions to ensure
-             * interrupt entry is as fast and simple as possible.
-             *
-             * The following links provide detailed information:
-             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
-            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-        }
-
-        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
-         * that define each interrupt's priority to be split between bits that
-         * define the interrupt's pre-emption priority bits and bits that define
-         * the interrupt's sub-priority.  For simplicity all bits must be defined
-         * to be pre-emption priority bits.  The following assertion will fail if
-         * this is not the case (if some bits represent a sub-priority).
-         *
-         * If the application only uses CMSIS libraries for interrupt
-         * configuration then the correct setting can be achieved on all Cortex-M
-         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-         * scheduler.  Note however that some vendor specific peripheral libraries
-         * assume a non-zero priority group setting, in which cases using a value
-         * of zero will result in unpredictable behaviour. */
-        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-    }
-
-#endif /* configASSERT_DEFINED */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM4F/portmacro.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM4F/portmacro.h
deleted file mode 100644
index 0e2cdae..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/GCC/ARM_CM4F/portmacro.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-    #define PORTMACRO_H
-
-    #ifdef __cplusplus
-        extern "C" {
-    #endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
-
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
-
-    #if ( configUSE_16_BIT_TICKS == 1 )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #else
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    8
-    #define portDONT_DISCARD      __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-    #define portYIELD()                                 \
-    {                                                   \
-        /* Set a PendSV to request a context switch. */ \
-        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
-                                                        \
-        /* Barriers are normally not required but do ensure the code is completely \
-         * within the specified behaviour for the architecture. */ \
-        __asm volatile ( "dsb" ::: "memory" );                     \
-        __asm volatile ( "isb" );                                  \
-    }
-
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD()
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
-    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
-    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
- * not necessary for to use this port.  They are defined so the common demo files
- * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
-
-    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-/* Generic helper function. */
-        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-        {
-            uint8_t ucReturn;
-
-            __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
-
-            return ucReturn;
-        }
-
-/* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
-
-/* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-/*-----------------------------------------------------------*/
-
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-    #endif
-
-/* portNOP() is not required by this port. */
-    #define portNOP()
-
-    #define portINLINE              __inline
-
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
-    #endif
-
-    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
-    {
-        uint32_t ulCurrentInterrupt;
-        BaseType_t xReturn;
-
-        /* Obtain the number of the currently executing interrupt. */
-        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
-        if( ulCurrentInterrupt == 0 )
-        {
-            xReturn = pdFALSE;
-        }
-        else
-        {
-            xReturn = pdTRUE;
-        }
-
-        return xReturn;
-    }
-
-/*-----------------------------------------------------------*/
-
-    portFORCE_INLINE static void vPortRaiseBASEPRI( void )
-    {
-        uint32_t ulNewBASEPRI;
-
-        __asm volatile
-        (
-            "	mov %0, %1												\n"\
-            "	msr basepri, %0											\n"\
-            "	isb														\n"\
-            "	dsb														\n"\
-            : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-        );
-    }
-
-/*-----------------------------------------------------------*/
-
-    portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
-    {
-        uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
-
-        __asm volatile
-        (
-            "	mrs %0, basepri											\n"\
-            "	mov %1, %2												\n"\
-            "	msr basepri, %1											\n"\
-            "	isb														\n"\
-            "	dsb														\n"\
-            : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-        );
-
-        /* This return will not be reached but is necessary to prevent compiler
-         * warnings. */
-        return ulOriginalBASEPRI;
-    }
-/*-----------------------------------------------------------*/
-
-    portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
-    {
-        __asm volatile
-        (
-            "	msr basepri, %0	"::"r" ( ulNewMaskValue ) : "memory"
-        );
-    }
-/*-----------------------------------------------------------*/
-
-    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
-
-    #ifdef __cplusplus
-        }
-    #endif
-
-#endif /* PORTMACRO_H */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/ReadMe.url b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/ReadMe.url
deleted file mode 100644
index 28c9937..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/ReadMe.url
+++ /dev/null
@@ -1,5 +0,0 @@
-[{000214A0-0000-0000-C000-000000000046}]
-Prop3=19,2
-[InternetShortcut]
-URL=https://www.FreeRTOS.org/a00111.html
-IDList=
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_1.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_1.c
deleted file mode 100644
index c3278ec..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_1.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-/*
- * The simplest possible implementation of pvPortMalloc().  Note that this
- * implementation does NOT allow allocated memory to be freed again.
- *
- * See heap_2.c, heap_3.c and heap_4.c for alternative implementations, and the
- * memory management pages of https://www.FreeRTOS.org for more information.
- */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers.  That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/* A few bytes might be lost to byte aligning the heap start address. */
-#define configADJUSTED_HEAP_SIZE    ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
-
-/* Allocate the memory for the heap. */
-#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
-
-/* The application writer has already defined the array used for the RTOS
-* heap - probably so it can be placed in a special segment or address. */
-    extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#else
-    static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/* Index into the ucHeap array. */
-static size_t xNextFreeByte = ( size_t ) 0;
-
-/*-----------------------------------------------------------*/
-
-void * pvPortMalloc( size_t xWantedSize )
-{
-    void * pvReturn = NULL;
-    static uint8_t * pucAlignedHeap = NULL;
-
-    /* Ensure that blocks are always aligned. */
-    #if ( portBYTE_ALIGNMENT != 1 )
-        {
-            if( xWantedSize & portBYTE_ALIGNMENT_MASK )
-            {
-                /* Byte alignment required. Check for overflow. */
-                if ( (xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) )) > xWantedSize )
-                {
-                    xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
-                } 
-                else 
-                {
-                    xWantedSize = 0;
-                }
-            }
-        }
-    #endif
-
-    vTaskSuspendAll();
-    {
-        if( pucAlignedHeap == NULL )
-        {
-            /* Ensure the heap starts on a correctly aligned boundary. */
-            pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) & ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
-        }
-
-        /* Check there is enough room left for the allocation and. */
-        if( ( xWantedSize > 0 ) && /* valid size */
-            ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) &&
-            ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) ) /* Check for overflow. */
-        {
-            /* Return the next free byte then increment the index past this
-             * block. */
-            pvReturn = pucAlignedHeap + xNextFreeByte;
-            xNextFreeByte += xWantedSize;
-        }
-
-        traceMALLOC( pvReturn, xWantedSize );
-    }
-    ( void ) xTaskResumeAll();
-
-    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
-        {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-        }
-    #endif
-
-    return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void * pv )
-{
-    /* Memory cannot be freed using this scheme.  See heap_2.c, heap_3.c and
-     * heap_4.c for alternative implementations, and the memory management pages of
-     * https://www.FreeRTOS.org for more information. */
-    ( void ) pv;
-
-    /* Force an assert as it is invalid to call this function. */
-    configASSERT( pv == NULL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-    /* Only required when static memory is not cleared. */
-    xNextFreeByte = ( size_t ) 0;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-    return( configADJUSTED_HEAP_SIZE - xNextFreeByte );
-}
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_2.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_2.c
deleted file mode 100644
index 552e69f..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_2.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * A sample implementation of pvPortMalloc() and vPortFree() that permits
- * allocated blocks to be freed, but does not combine adjacent free blocks
- * into a single larger block (and so will fragment memory).  See heap_4.c for
- * an equivalent that does combine adjacent blocks into single larger blocks.
- *
- * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the
- * memory management pages of https://www.FreeRTOS.org for more information.
- */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers.  That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/* A few bytes might be lost to byte aligning the heap start address. */
-#define configADJUSTED_HEAP_SIZE    ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
-
-/*
- * Initialises the heap structures before their first use.
- */
-static void prvHeapInit( void );
-
-/* Allocate the memory for the heap. */
-#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
-
-/* The application writer has already defined the array used for the RTOS
-* heap - probably so it can be placed in a special segment or address. */
-    extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#else
-    static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-
-/* Define the linked list structure.  This is used to link free blocks in order
- * of their size. */
-typedef struct A_BLOCK_LINK
-{
-    struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */
-    size_t xBlockSize;                     /*<< The size of the free block. */
-} BlockLink_t;
-
-
-static const uint16_t heapSTRUCT_SIZE = ( ( sizeof( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );
-#define heapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )
-
-/* Create a couple of list links to mark the start and end of the list. */
-static BlockLink_t xStart, xEnd;
-
-/* Keeps track of the number of free bytes remaining, but says nothing about
- * fragmentation. */
-static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
-
-/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */
-
-/*
- * Insert a block into the list of free blocks - which is ordered by size of
- * the block.  Small blocks at the start of the list and large blocks at the end
- * of the list.
- */
-#define prvInsertBlockIntoFreeList( pxBlockToInsert )                                                                               \
-    {                                                                                                                               \
-        BlockLink_t * pxIterator;                                                                                                   \
-        size_t xBlockSize;                                                                                                          \
-                                                                                                                                    \
-        xBlockSize = pxBlockToInsert->xBlockSize;                                                                                   \
-                                                                                                                                    \
-        /* Iterate through the list until a block is found that has a larger size */                                                \
-        /* than the block we are inserting. */                                                                                      \
-        for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \
-        {                                                                                                                           \
-            /* There is nothing to do here - just iterate to the correct position. */                                               \
-        }                                                                                                                           \
-                                                                                                                                    \
-        /* Update the list to include the block being inserted in the correct */                                                    \
-        /* position. */                                                                                                             \
-        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;                                                             \
-        pxIterator->pxNextFreeBlock = pxBlockToInsert;                                                                              \
-    }
-/*-----------------------------------------------------------*/
-
-void * pvPortMalloc( size_t xWantedSize )
-{
-    BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
-    static BaseType_t xHeapHasBeenInitialised = pdFALSE;
-    void * pvReturn = NULL;
-
-    vTaskSuspendAll();
-    {
-        /* If this is the first call to malloc then the heap will require
-         * initialisation to setup the list of free blocks. */
-        if( xHeapHasBeenInitialised == pdFALSE )
-        {
-            prvHeapInit();
-            xHeapHasBeenInitialised = pdTRUE;
-        }
-
-        /* The wanted size must be increased so it can contain a BlockLink_t
-         * structure in addition to the requested amount of bytes. */
-        if( ( xWantedSize > 0 ) && 
-            ( ( xWantedSize + heapSTRUCT_SIZE ) >  xWantedSize ) ) /* Overflow check */
-        {
-            xWantedSize += heapSTRUCT_SIZE;
-
-            /* Byte alignment required. Check for overflow. */
-            if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) 
-                    > xWantedSize )
-            {
-                xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
-                configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
-            }
-            else
-            {
-                xWantedSize = 0;
-            }       
-        }
-        else 
-        {
-            xWantedSize = 0; 
-        }
-
-
-        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-        {
-            /* Blocks are stored in byte order - traverse the list from the start
-             * (smallest) block until one of adequate size is found. */
-            pxPreviousBlock = &xStart;
-            pxBlock = xStart.pxNextFreeBlock;
-
-            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-            {
-                pxPreviousBlock = pxBlock;
-                pxBlock = pxBlock->pxNextFreeBlock;
-            }
-
-            /* If we found the end marker then a block of adequate size was not found. */
-            if( pxBlock != &xEnd )
-            {
-                /* Return the memory space - jumping over the BlockLink_t structure
-                 * at its start. */
-                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );
-
-                /* This block is being returned for use so must be taken out of the
-                 * list of free blocks. */
-                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-                /* If the block is larger than required it can be split into two. */
-                if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
-                {
-                    /* This block is to be split into two.  Create a new block
-                     * following the number of bytes requested. The void cast is
-                     * used to prevent byte alignment warnings from the compiler. */
-                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-
-                    /* Calculate the sizes of two blocks split from the single
-                     * block. */
-                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-                    pxBlock->xBlockSize = xWantedSize;
-
-                    /* Insert the new block into the list of free blocks. */
-                    prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
-                }
-
-                xFreeBytesRemaining -= pxBlock->xBlockSize;
-            }
-        }
-
-        traceMALLOC( pvReturn, xWantedSize );
-    }
-    ( void ) xTaskResumeAll();
-
-    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
-        {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-        }
-    #endif
-
-    return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void * pv )
-{
-    uint8_t * puc = ( uint8_t * ) pv;
-    BlockLink_t * pxLink;
-
-    if( pv != NULL )
-    {
-        /* The memory being freed will have an BlockLink_t structure immediately
-         * before it. */
-        puc -= heapSTRUCT_SIZE;
-
-        /* This unexpected casting is to keep some compilers from issuing
-         * byte alignment warnings. */
-        pxLink = ( void * ) puc;
-
-        vTaskSuspendAll();
-        {
-            /* Add this block to the list of free blocks. */
-            prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-            xFreeBytesRemaining += pxLink->xBlockSize;
-            traceFREE( pv, pxLink->xBlockSize );
-        }
-        ( void ) xTaskResumeAll();
-    }
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-    return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-    /* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-    BlockLink_t * pxFirstFreeBlock;
-    uint8_t * pucAlignedHeap;
-
-    /* Ensure the heap starts on a correctly aligned boundary. */
-    pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) & ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
-
-    /* xStart is used to hold a pointer to the first item in the list of free
-     * blocks.  The void cast is used to prevent compiler warnings. */
-    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-    xStart.xBlockSize = ( size_t ) 0;
-
-    /* xEnd is used to mark the end of the list of free blocks. */
-    xEnd.xBlockSize = configADJUSTED_HEAP_SIZE;
-    xEnd.pxNextFreeBlock = NULL;
-
-    /* To start with there is a single free block that is sized to take up the
-     * entire heap space. */
-    pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-    pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;
-    pxFirstFreeBlock->pxNextFreeBlock = &xEnd;
-}
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_3.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_3.c
deleted file mode 100644
index 9ab9b7b..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_3.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*
- * Implementation of pvPortMalloc() and vPortFree() that relies on the
- * compilers own malloc() and free() implementations.
- *
- * This file can only be used if the linker is configured to to generate
- * a heap memory area.
- *
- * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the
- * memory management pages of https://www.FreeRTOS.org for more information.
- */
-
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers.  That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/*-----------------------------------------------------------*/
-
-void * pvPortMalloc( size_t xWantedSize )
-{
-    void * pvReturn;
-
-    vTaskSuspendAll();
-    {
-        pvReturn = malloc( xWantedSize );
-        traceMALLOC( pvReturn, xWantedSize );
-    }
-    ( void ) xTaskResumeAll();
-
-    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
-        {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-        }
-    #endif
-
-    return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void * pv )
-{
-    if( pv )
-    {
-        vTaskSuspendAll();
-        {
-            free( pv );
-            traceFREE( pv, 0 );
-        }
-        ( void ) xTaskResumeAll();
-    }
-}
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_4.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_4.c
deleted file mode 100644
index fb8e035..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_4.c
+++ /dev/null
@@ -1,502 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * A sample implementation of pvPortMalloc() and vPortFree() that combines
- * (coalescences) adjacent memory blocks as they are freed, and in so doing
- * limits memory fragmentation.
- *
- * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
- * memory management pages of https://www.FreeRTOS.org for more information.
- */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers.  That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/* Block sizes must not get too small. */
-#define heapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define heapBITS_PER_BYTE         ( ( size_t ) 8 )
-
-/* Allocate the memory for the heap. */
-#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
-
-/* The application writer has already defined the array used for the RTOS
-* heap - probably so it can be placed in a special segment or address. */
-    extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#else
-    PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/* Define the linked list structure.  This is used to link free blocks in order
- * of their memory address. */
-typedef struct A_BLOCK_LINK
-{
-    struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */
-    size_t xBlockSize;                     /*<< The size of the free block. */
-} BlockLink_t;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Inserts a block of memory that is being freed into the correct position in
- * the list of free memory blocks.  The block being freed will be merged with
- * the block in front it and/or the block behind it if the memory blocks are
- * adjacent to each other.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION;
-
-/*
- * Called automatically to setup the required heap structures the first time
- * pvPortMalloc() is called.
- */
-static void prvHeapInit( void ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------*/
-
-/* The size of the structure placed at the beginning of each allocated memory
- * block must by correctly byte aligned. */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
-
-/* Create a couple of list links to mark the start and end of the list. */
-PRIVILEGED_DATA static BlockLink_t xStart, * pxEnd = NULL;
-
-/* Keeps track of the number of calls to allocate and free memory as well as the
- * number of free bytes remaining, but says nothing about fragmentation. */
-PRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U;
-PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U;
-PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0;
-PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0;
-
-/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
- * member of an BlockLink_t structure is set then the block belongs to the
- * application.  When the bit is free the block is still part of the free heap
- * space. */
-PRIVILEGED_DATA static size_t xBlockAllocatedBit = 0;
-
-/*-----------------------------------------------------------*/
-
-void * pvPortMalloc( size_t xWantedSize )
-{
-    BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
-    void * pvReturn = NULL;
-
-    vTaskSuspendAll();
-    {
-        /* If this is the first call to malloc then the heap will require
-         * initialisation to setup the list of free blocks. */
-        if( pxEnd == NULL )
-        {
-            prvHeapInit();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        /* Check the requested block size is not so large that the top bit is
-         * set.  The top bit of the block size member of the BlockLink_t structure
-         * is used to determine who owns the block - the application or the
-         * kernel, so it must be free. */
-        if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-        {
-            /* The wanted size must be increased so it can contain a BlockLink_t
-             * structure in addition to the requested amount of bytes. */
-            if( ( xWantedSize > 0 ) && 
-                ( ( xWantedSize + xHeapStructSize ) >  xWantedSize ) ) /* Overflow check */
-            {
-                xWantedSize += xHeapStructSize;
-
-                /* Ensure that blocks are always aligned. */
-                if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
-                {
-                    /* Byte alignment required. Check for overflow. */
-                    if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) 
-                            > xWantedSize )
-                    {
-                        xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
-                        configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
-                    }
-                    else
-                    {
-                        xWantedSize = 0;
-                    }  
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            } 
-            else 
-            {
-                xWantedSize = 0;
-            }
-
-            if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-            {
-                /* Traverse the list from the start	(lowest address) block until
-                 * one of adequate size is found. */
-                pxPreviousBlock = &xStart;
-                pxBlock = xStart.pxNextFreeBlock;
-
-                while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-                {
-                    pxPreviousBlock = pxBlock;
-                    pxBlock = pxBlock->pxNextFreeBlock;
-                }
-
-                /* If the end marker was reached then a block of adequate size
-                 * was not found. */
-                if( pxBlock != pxEnd )
-                {
-                    /* Return the memory space pointed to - jumping over the
-                     * BlockLink_t structure at its start. */
-                    pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-                    /* This block is being returned for use so must be taken out
-                     * of the list of free blocks. */
-                    pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-                    /* If the block is larger than required it can be split into
-                     * two. */
-                    if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
-                    {
-                        /* This block is to be split into two.  Create a new
-                         * block following the number of bytes requested. The void
-                         * cast is used to prevent byte alignment warnings from the
-                         * compiler. */
-                        pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-                        configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
-
-                        /* Calculate the sizes of two blocks split from the
-                         * single block. */
-                        pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-                        pxBlock->xBlockSize = xWantedSize;
-
-                        /* Insert the new block into the list of free blocks. */
-                        prvInsertBlockIntoFreeList( pxNewBlockLink );
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-
-                    xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-                    if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-                    {
-                        xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-
-                    /* The block is being returned - it is allocated and owned
-                     * by the application and has no "next" block. */
-                    pxBlock->xBlockSize |= xBlockAllocatedBit;
-                    pxBlock->pxNextFreeBlock = NULL;
-                    xNumberOfSuccessfulAllocations++;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        traceMALLOC( pvReturn, xWantedSize );
-    }
-    ( void ) xTaskResumeAll();
-
-    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
-        {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-    #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */
-
-    configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
-    return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void * pv )
-{
-    uint8_t * puc = ( uint8_t * ) pv;
-    BlockLink_t * pxLink;
-
-    if( pv != NULL )
-    {
-        /* The memory being freed will have an BlockLink_t structure immediately
-         * before it. */
-        puc -= xHeapStructSize;
-
-        /* This casting is to keep the compiler from issuing warnings. */
-        pxLink = ( void * ) puc;
-
-        /* Check the block is actually allocated. */
-        configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-        configASSERT( pxLink->pxNextFreeBlock == NULL );
-
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-        {
-            if( pxLink->pxNextFreeBlock == NULL )
-            {
-                /* The block is being returned to the heap - it is no longer
-                 * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-                vTaskSuspendAll();
-                {
-                    /* Add this block to the list of free blocks. */
-                    xFreeBytesRemaining += pxLink->xBlockSize;
-                    traceFREE( pv, pxLink->xBlockSize );
-                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-                    xNumberOfSuccessfulFrees++;
-                }
-                ( void ) xTaskResumeAll();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-    return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-    return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-    /* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
-{
-    BlockLink_t * pxFirstFreeBlock;
-    uint8_t * pucAlignedHeap;
-    size_t uxAddress;
-    size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
-
-    /* Ensure the heap starts on a correctly aligned boundary. */
-    uxAddress = ( size_t ) ucHeap;
-
-    if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
-    {
-        uxAddress += ( portBYTE_ALIGNMENT - 1 );
-        uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
-        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-    }
-
-    pucAlignedHeap = ( uint8_t * ) uxAddress;
-
-    /* xStart is used to hold a pointer to the first item in the list of free
-     * blocks.  The void cast is used to prevent compiler warnings. */
-    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-    xStart.xBlockSize = ( size_t ) 0;
-
-    /* pxEnd is used to mark the end of the list of free blocks and is inserted
-     * at the end of the heap space. */
-    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-    uxAddress -= xHeapStructSize;
-    uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
-    pxEnd = ( void * ) uxAddress;
-    pxEnd->xBlockSize = 0;
-    pxEnd->pxNextFreeBlock = NULL;
-
-    /* To start with there is a single free block that is sized to take up the
-     * entire heap space, minus the space taken by pxEnd. */
-    pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
-    /* Only one block exists - and it covers the entire usable heap space. */
-    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */
-{
-    BlockLink_t * pxIterator;
-    uint8_t * puc;
-
-    /* Iterate through the list until a block is found that has a higher address
-     * than the block being inserted. */
-    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-    {
-        /* Nothing to do here, just iterate to the right position. */
-    }
-
-    /* Do the block being inserted, and the block it is being inserted after
-     * make a contiguous block of memory? */
-    puc = ( uint8_t * ) pxIterator;
-
-    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-    {
-        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-        pxBlockToInsert = pxIterator;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    /* Do the block being inserted, and the block it is being inserted before
-     * make a contiguous block of memory? */
-    puc = ( uint8_t * ) pxBlockToInsert;
-
-    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-    {
-        if( pxIterator->pxNextFreeBlock != pxEnd )
-        {
-            /* Form one big block from the two blocks. */
-            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-        }
-        else
-        {
-            pxBlockToInsert->pxNextFreeBlock = pxEnd;
-        }
-    }
-    else
-    {
-        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-    }
-
-    /* If the block being inserted plugged a gab, so was merged with the block
-     * before and the block after, then it's pxNextFreeBlock pointer will have
-     * already been set, and should not be set here as that would make it point
-     * to itself. */
-    if( pxIterator != pxBlockToInsert )
-    {
-        pxIterator->pxNextFreeBlock = pxBlockToInsert;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-}
-/*-----------------------------------------------------------*/
-
-void vPortGetHeapStats( HeapStats_t * pxHeapStats )
-{
-    BlockLink_t * pxBlock;
-    size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
-
-    vTaskSuspendAll();
-    {
-        pxBlock = xStart.pxNextFreeBlock;
-
-        /* pxBlock will be NULL if the heap has not been initialised.  The heap
-         * is initialised automatically when the first allocation is made. */
-        if( pxBlock != NULL )
-        {
-            do
-            {
-                /* Increment the number of blocks and record the largest block seen
-                 * so far. */
-                xBlocks++;
-
-                if( pxBlock->xBlockSize > xMaxSize )
-                {
-                    xMaxSize = pxBlock->xBlockSize;
-                }
-
-                if( pxBlock->xBlockSize < xMinSize )
-                {
-                    xMinSize = pxBlock->xBlockSize;
-                }
-
-                /* Move to the next block in the chain until the last block is
-                 * reached. */
-                pxBlock = pxBlock->pxNextFreeBlock;
-            } while( pxBlock != pxEnd );
-        }
-    }
-    ( void ) xTaskResumeAll();
-
-    pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;
-    pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;
-    pxHeapStats->xNumberOfFreeBlocks = xBlocks;
-
-    taskENTER_CRITICAL();
-    {
-        pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;
-        pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;
-        pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;
-        pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;
-    }
-    taskEXIT_CRITICAL();
-}
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_5.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_5.c
deleted file mode 100644
index 6bf72fa..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_5.c
+++ /dev/null
@@ -1,557 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * A sample implementation of pvPortMalloc() that allows the heap to be defined
- * across multiple non-contigous blocks and combines (coalescences) adjacent
- * memory blocks as they are freed.
- *
- * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative
- * implementations, and the memory management pages of https://www.FreeRTOS.org
- * for more information.
- *
- * Usage notes:
- *
- * vPortDefineHeapRegions() ***must*** be called before pvPortMalloc().
- * pvPortMalloc() will be called if any task objects (tasks, queues, event
- * groups, etc.) are created, therefore vPortDefineHeapRegions() ***must*** be
- * called before any other objects are defined.
- *
- * vPortDefineHeapRegions() takes a single parameter.  The parameter is an array
- * of HeapRegion_t structures.  HeapRegion_t is defined in portable.h as
- *
- * typedef struct HeapRegion
- * {
- *	uint8_t *pucStartAddress; << Start address of a block of memory that will be part of the heap.
- *	size_t xSizeInBytes;	  << Size of the block of memory.
- * } HeapRegion_t;
- *
- * The array is terminated using a NULL zero sized region definition, and the
- * memory regions defined in the array ***must*** appear in address order from
- * low address to high address.  So the following is a valid example of how
- * to use the function.
- *
- * HeapRegion_t xHeapRegions[] =
- * {
- *  { ( uint8_t * ) 0x80000000UL, 0x10000 }, << Defines a block of 0x10000 bytes starting at address 0x80000000
- *  { ( uint8_t * ) 0x90000000UL, 0xa0000 }, << Defines a block of 0xa0000 bytes starting at address of 0x90000000
- *  { NULL, 0 }                << Terminates the array.
- * };
- *
- * vPortDefineHeapRegions( xHeapRegions ); << Pass the array into vPortDefineHeapRegions().
- *
- * Note 0x80000000 is the lower address so appears in the array first.
- *
- */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers.  That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/* Block sizes must not get too small. */
-#define heapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define heapBITS_PER_BYTE         ( ( size_t ) 8 )
-
-/* Define the linked list structure.  This is used to link free blocks in order
- * of their memory address. */
-typedef struct A_BLOCK_LINK
-{
-    struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */
-    size_t xBlockSize;                     /*<< The size of the free block. */
-} BlockLink_t;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Inserts a block of memory that is being freed into the correct position in
- * the list of free memory blocks.  The block being freed will be merged with
- * the block in front it and/or the block behind it if the memory blocks are
- * adjacent to each other.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
-
-/*-----------------------------------------------------------*/
-
-/* The size of the structure placed at the beginning of each allocated memory
- * block must by correctly byte aligned. */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
-
-/* Create a couple of list links to mark the start and end of the list. */
-static BlockLink_t xStart, * pxEnd = NULL;
-
-/* Keeps track of the number of calls to allocate and free memory as well as the
- * number of free bytes remaining, but says nothing about fragmentation. */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-static size_t xNumberOfSuccessfulAllocations = 0;
-static size_t xNumberOfSuccessfulFrees = 0;
-
-/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
- * member of an BlockLink_t structure is set then the block belongs to the
- * application.  When the bit is free the block is still part of the free heap
- * space. */
-static size_t xBlockAllocatedBit = 0;
-
-/*-----------------------------------------------------------*/
-
-void * pvPortMalloc( size_t xWantedSize )
-{
-    BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
-    void * pvReturn = NULL;
-
-    /* The heap must be initialised before the first call to
-     * prvPortMalloc(). */
-    configASSERT( pxEnd );
-
-    vTaskSuspendAll();
-    {
-        /* Check the requested block size is not so large that the top bit is
-         * set.  The top bit of the block size member of the BlockLink_t structure
-         * is used to determine who owns the block - the application or the
-         * kernel, so it must be free. */
-        if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-        {
-            /* The wanted size is increased so it can contain a BlockLink_t
-             * structure in addition to the requested amount of bytes. */
-            if( ( xWantedSize > 0 ) && 
-                ( ( xWantedSize + xHeapStructSize ) >  xWantedSize ) ) /* Overflow check */
-            {
-                xWantedSize += xHeapStructSize;
-
-                /* Ensure that blocks are always aligned */
-                if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
-                {
-                    /* Byte alignment required. Check for overflow */
-                    if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) >
-                         xWantedSize )
-                    {
-                        xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
-                    } 
-                    else 
-                    {
-                        xWantedSize = 0;
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                xWantedSize = 0;
-            }
-
-            if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-            {
-                /* Traverse the list from the start	(lowest address) block until
-                 * one of adequate size is found. */
-                pxPreviousBlock = &xStart;
-                pxBlock = xStart.pxNextFreeBlock;
-
-                while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-                {
-                    pxPreviousBlock = pxBlock;
-                    pxBlock = pxBlock->pxNextFreeBlock;
-                }
-
-                /* If the end marker was reached then a block of adequate size
-                 * was not found. */
-                if( pxBlock != pxEnd )
-                {
-                    /* Return the memory space pointed to - jumping over the
-                     * BlockLink_t structure at its start. */
-                    pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-                    /* This block is being returned for use so must be taken out
-                     * of the list of free blocks. */
-                    pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-                    /* If the block is larger than required it can be split into
-                     * two. */
-                    if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
-                    {
-                        /* This block is to be split into two.  Create a new
-                         * block following the number of bytes requested. The void
-                         * cast is used to prevent byte alignment warnings from the
-                         * compiler. */
-                        pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-
-                        /* Calculate the sizes of two blocks split from the
-                         * single block. */
-                        pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-                        pxBlock->xBlockSize = xWantedSize;
-
-                        /* Insert the new block into the list of free blocks. */
-                        prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-
-                    xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-                    if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-                    {
-                        xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-
-                    /* The block is being returned - it is allocated and owned
-                     * by the application and has no "next" block. */
-                    pxBlock->xBlockSize |= xBlockAllocatedBit;
-                    pxBlock->pxNextFreeBlock = NULL;
-                    xNumberOfSuccessfulAllocations++;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        traceMALLOC( pvReturn, xWantedSize );
-    }
-    ( void ) xTaskResumeAll();
-
-    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
-        {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-    #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */
-
-    return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void * pv )
-{
-    uint8_t * puc = ( uint8_t * ) pv;
-    BlockLink_t * pxLink;
-
-    if( pv != NULL )
-    {
-        /* The memory being freed will have an BlockLink_t structure immediately
-         * before it. */
-        puc -= xHeapStructSize;
-
-        /* This casting is to keep the compiler from issuing warnings. */
-        pxLink = ( void * ) puc;
-
-        /* Check the block is actually allocated. */
-        configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-        configASSERT( pxLink->pxNextFreeBlock == NULL );
-
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-        {
-            if( pxLink->pxNextFreeBlock == NULL )
-            {
-                /* The block is being returned to the heap - it is no longer
-                 * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-                vTaskSuspendAll();
-                {
-                    /* Add this block to the list of free blocks. */
-                    xFreeBytesRemaining += pxLink->xBlockSize;
-                    traceFREE( pv, pxLink->xBlockSize );
-                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-                    xNumberOfSuccessfulFrees++;
-                }
-                ( void ) xTaskResumeAll();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-    return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-    return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
-{
-    BlockLink_t * pxIterator;
-    uint8_t * puc;
-
-    /* Iterate through the list until a block is found that has a higher address
-     * than the block being inserted. */
-    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-    {
-        /* Nothing to do here, just iterate to the right position. */
-    }
-
-    /* Do the block being inserted, and the block it is being inserted after
-     * make a contiguous block of memory? */
-    puc = ( uint8_t * ) pxIterator;
-
-    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-    {
-        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-        pxBlockToInsert = pxIterator;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    /* Do the block being inserted, and the block it is being inserted before
-     * make a contiguous block of memory? */
-    puc = ( uint8_t * ) pxBlockToInsert;
-
-    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-    {
-        if( pxIterator->pxNextFreeBlock != pxEnd )
-        {
-            /* Form one big block from the two blocks. */
-            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-        }
-        else
-        {
-            pxBlockToInsert->pxNextFreeBlock = pxEnd;
-        }
-    }
-    else
-    {
-        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-    }
-
-    /* If the block being inserted plugged a gab, so was merged with the block
-     * before and the block after, then it's pxNextFreeBlock pointer will have
-     * already been set, and should not be set here as that would make it point
-     * to itself. */
-    if( pxIterator != pxBlockToInsert )
-    {
-        pxIterator->pxNextFreeBlock = pxBlockToInsert;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-}
-/*-----------------------------------------------------------*/
-
-void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
-{
-    BlockLink_t * pxFirstFreeBlockInRegion = NULL, * pxPreviousFreeBlock;
-    size_t xAlignedHeap;
-    size_t xTotalRegionSize, xTotalHeapSize = 0;
-    BaseType_t xDefinedRegions = 0;
-    size_t xAddress;
-    const HeapRegion_t * pxHeapRegion;
-
-    /* Can only call once! */
-    configASSERT( pxEnd == NULL );
-
-    pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
-
-    while( pxHeapRegion->xSizeInBytes > 0 )
-    {
-        xTotalRegionSize = pxHeapRegion->xSizeInBytes;
-
-        /* Ensure the heap region starts on a correctly aligned boundary. */
-        xAddress = ( size_t ) pxHeapRegion->pucStartAddress;
-
-        if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
-        {
-            xAddress += ( portBYTE_ALIGNMENT - 1 );
-            xAddress &= ~portBYTE_ALIGNMENT_MASK;
-
-            /* Adjust the size for the bytes lost to alignment. */
-            xTotalRegionSize -= xAddress - ( size_t ) pxHeapRegion->pucStartAddress;
-        }
-
-        xAlignedHeap = xAddress;
-
-        /* Set xStart if it has not already been set. */
-        if( xDefinedRegions == 0 )
-        {
-            /* xStart is used to hold a pointer to the first item in the list of
-             *  free blocks.  The void cast is used to prevent compiler warnings. */
-            xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap;
-            xStart.xBlockSize = ( size_t ) 0;
-        }
-        else
-        {
-            /* Should only get here if one region has already been added to the
-             * heap. */
-            configASSERT( pxEnd != NULL );
-
-            /* Check blocks are passed in with increasing start addresses. */
-            configASSERT( xAddress > ( size_t ) pxEnd );
-        }
-
-        /* Remember the location of the end marker in the previous region, if
-         * any. */
-        pxPreviousFreeBlock = pxEnd;
-
-        /* pxEnd is used to mark the end of the list of free blocks and is
-         * inserted at the end of the region space. */
-        xAddress = xAlignedHeap + xTotalRegionSize;
-        xAddress -= xHeapStructSize;
-        xAddress &= ~portBYTE_ALIGNMENT_MASK;
-        pxEnd = ( BlockLink_t * ) xAddress;
-        pxEnd->xBlockSize = 0;
-        pxEnd->pxNextFreeBlock = NULL;
-
-        /* To start with there is a single free block in this region that is
-         * sized to take up the entire heap region minus the space taken by the
-         * free block structure. */
-        pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap;
-        pxFirstFreeBlockInRegion->xBlockSize = xAddress - ( size_t ) pxFirstFreeBlockInRegion;
-        pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;
-
-        /* If this is not the first region that makes up the entire heap space
-         * then link the previous region to this region. */
-        if( pxPreviousFreeBlock != NULL )
-        {
-            pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion;
-        }
-
-        xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize;
-
-        /* Move onto the next HeapRegion_t structure. */
-        xDefinedRegions++;
-        pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
-    }
-
-    xMinimumEverFreeBytesRemaining = xTotalHeapSize;
-    xFreeBytesRemaining = xTotalHeapSize;
-
-    /* Check something was actually defined before it is accessed. */
-    configASSERT( xTotalHeapSize );
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-void vPortGetHeapStats( HeapStats_t * pxHeapStats )
-{
-    BlockLink_t * pxBlock;
-    size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
-
-    vTaskSuspendAll();
-    {
-        pxBlock = xStart.pxNextFreeBlock;
-
-        /* pxBlock will be NULL if the heap has not been initialised.  The heap
-         * is initialised automatically when the first allocation is made. */
-        if( pxBlock != NULL )
-        {
-            do
-            {
-                /* Increment the number of blocks and record the largest block seen
-                 * so far. */
-                xBlocks++;
-
-                if( pxBlock->xBlockSize > xMaxSize )
-                {
-                    xMaxSize = pxBlock->xBlockSize;
-                }
-
-                /* Heap five will have a zero sized block at the end of each
-                 * each region - the block is only used to link to the next
-                 * heap region so it not a real block. */
-                if( pxBlock->xBlockSize != 0 )
-                {
-                    if( pxBlock->xBlockSize < xMinSize )
-                    {
-                        xMinSize = pxBlock->xBlockSize;
-                    }
-                }
-
-                /* Move to the next block in the chain until the last block is
-                 * reached. */
-                pxBlock = pxBlock->pxNextFreeBlock;
-            } while( pxBlock != pxEnd );
-        }
-    }
-    ( void ) xTaskResumeAll();
-
-    pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;
-    pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;
-    pxHeapStats->xNumberOfFreeBlocks = xBlocks;
-
-    taskENTER_CRITICAL();
-    {
-        pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;
-        pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;
-        pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;
-        pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;
-    }
-    taskEXIT_CRITICAL();
-}
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_useNewlib.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_useNewlib.c
deleted file mode 100644
index 47ebfa7..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/MemMang/heap_useNewlib.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/**
- * \file heap_useNewlib.c
- * \brief Wrappers required to use newlib malloc-family within FreeRTOS.
- *
- * \par Overview
- * Route FreeRTOS memory management functions to newlib's malloc family.
- * Thus newlib and FreeRTOS share memory-management routines and memory pool,
- * and all newlib's internal memory-management requirements are supported.
- *
- * \author Dave Nadler
- * \date 2-July-2017
- * \version 23-Sep-2019 malloc accounting, comments, newlib version check
- *
- * \see http://www.nadler.com/embedded/newlibAndFreeRTOS.html
- * \see https://sourceware.org/newlib/libc.html#Reentrancy
- * \see https://sourceware.org/newlib/libc.html#malloc
- * \see https://sourceware.org/newlib/libc.html#index-_005f_005fenv_005flock
- * \see https://sourceware.org/newlib/libc.html#index-_005f_005fmalloc_005flock
- * \see https://sourceforge.net/p/freertos/feature-requests/72/
- * \see http://www.billgatliff.com/newlib.html
- * \see http://wiki.osdev.org/Porting_Newlib
- * \see http://www.embecosm.com/appnotes/ean9/ean9-howto-newlib-1.0.html
- *
- *
- * \copyright
- * (c) Dave Nadler 2017-2019, All Rights Reserved.
- * Web:         http://www.nadler.com
- * email:       drn@nadler.com
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * - Use or redistributions of source code must retain the above copyright notice,
- *   this list of conditions, ALL ORIGINAL COMMENTS, and the following disclaimer.
- *
- * - Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include  // maps to newlib...
-#include  // mallinfo...
-#include   // ENOMEM
-#include 
-#include 
-
-#include "newlib.h"
-#if (__NEWLIB__ != 3) || (__NEWLIB_MINOR__ != 1)
-  #warning "This wrapper was verified for newlib version 3.1.0; please ensure newlib's external requirements for malloc-family are unchanged!"
-#endif
-
-#include "FreeRTOS.h" // defines public interface we're implementing here
-#if !defined(configUSE_NEWLIB_REENTRANT) ||  (configUSE_NEWLIB_REENTRANT!=1)
-  #warning "#define configUSE_NEWLIB_REENTRANT 1 // Required for thread-safety of newlib sprintf, strtok, etc..."
-  // If you're *REALLY* sure you don't need FreeRTOS's newlib reentrancy support, remove this warning...
-#endif
-#include "task.h"
-
-// ================================================================================================
-// External routines required by newlib's malloc (sbrk/_sbrk, __malloc_lock/unlock)
-// ================================================================================================
-
-#ifndef NDEBUG
-    static int totalBytesProvidedBySBRK = 0;
-#endif
-
-// Simplistic sbrk implementations assume stack grows downwards from top of memory,
-// and heap grows upwards starting just after BSS.
-// FreeRTOS normally allocates task stacks from a pool placed within BSS or DATA.
-// Thus within a FreeRTOS task, stack pointer is always below end of BSS.
-// When using this module, stacks are allocated from malloc pool, still always prior
-// current unused heap area...
-#if defined(__MCUXPRESSO)
-  #define configLINKER_HEAP_BASE_SYMBOL _pvHeapStart
-  #define configLINKER_HEAP_LIMIT_SYMBOL _pvHeapLimit
-  #define configLINKER_HEAP_SIZE_SYMBOL _HeapSize
-#elif defined(__GNUC__)
-  #define configLINKER_HEAP_BASE_SYMBOL end
-  #define configLINKER_HEAP_LIMIT_SYMBOL __HeapLimit
-  #define configLINKER_HEAP_SIZE_SYMBOL HEAP_SIZE
-#endif
-extern char configLINKER_HEAP_BASE_SYMBOL;
-extern char configLINKER_HEAP_LIMIT_SYMBOL;
-extern char configLINKER_HEAP_SIZE_SYMBOL;
-
-static int heapBytesRemaining = (int)&configLINKER_HEAP_SIZE_SYMBOL; // that's (&__HeapLimit)-(&__HeapBase)
-
-//! sbrk/_sbrk version supporting reentrant newlib (depends upon above symbols defined by linker control file).
-char * sbrk(int incr) {
-    static char *currentHeapEnd = &configLINKER_HEAP_BASE_SYMBOL;
-    vTaskSuspendAll(); // Note: safe to use before FreeRTOS scheduler started
-    char *previousHeapEnd = currentHeapEnd;
-    if (currentHeapEnd + incr > &configLINKER_HEAP_LIMIT_SYMBOL) {
-        #if( configUSE_MALLOC_FAILED_HOOK == 1 )
-        {
-            extern void vApplicationMallocFailedHook( void );
-            vApplicationMallocFailedHook();
-        }
-        #elif 1 // safest default when user doesn't explicitly code configUSE_MALLOC_FAILED_HOOK
-            // If you want to alert debugger or halt...
-            // WARNING: bkpt instruction may prevent watchdog operation...
-            while(1) { __asm("bkpt #0"); }; // Stop in GUI as if at a breakpoint (if debugging, otherwise loop forever)
-        #else
-            // If you prefer to believe your application will gracefully trap out-of-memory...
-            _impure_ptr->_errno = ENOMEM; // newlib's thread-specific errno
-            xTaskResumeAll();
-        #endif
-        return (char *)-1; // the malloc-family routine that called sbrk will return 0
-    }
-    // 'incr' of memory is available: update accounting and return it.
-    currentHeapEnd += incr;
-    heapBytesRemaining -= incr;
-    #ifndef NDEBUG
-        totalBytesProvidedBySBRK += incr;
-    #endif
-    xTaskResumeAll();
-    return (char *) previousHeapEnd;
-}
-//! Synonym for sbrk.
-char * _sbrk(int incr) { return sbrk(incr); };
-
-void __malloc_lock(struct _reent *p)   { configASSERT( !xPortIsInsideInterrupt() ); // Make damn sure no mallocs inside ISRs!!
-                                               vTaskSuspendAll(); };
-void __malloc_unlock(struct _reent *p) { (void)xTaskResumeAll();  };
-
-// newlib also requires implementing locks for the application's environment memory space,
-// accessed by newlib's setenv() and getenv() functions.
-// As these are trivial functions, momentarily suspend task switching (rather than semaphore).
-// ToDo: Move __env_lock/unlock to a separate newlib helper file.
-void __env_lock()    {       vTaskSuspendAll(); };
-void __env_unlock()  { (void)xTaskResumeAll();  };
-
-#if 1 // Provide malloc debug and accounting wrappers
-  /// /brief  Wrap malloc/malloc_r to help debug who requests memory and why.
-  /// To use these, add linker options: -Xlinker --wrap=malloc -Xlinker --wrap=_malloc_r
-  // Note: These functions are normally unused and stripped by linker.
-  int TotalMallocdBytes;
-  int MallocCallCnt;
-  static bool inside_malloc;
-  void *__wrap_malloc(size_t nbytes) {
-    extern void * __real_malloc(size_t nbytes);
-    MallocCallCnt++;
-    TotalMallocdBytes += nbytes;
-    inside_malloc = true;
-      void *p = __real_malloc(nbytes); // will call malloc_r...
-    inside_malloc = false;
-    return p;
-  };
-  void *__wrap__malloc_r(void *reent, size_t nbytes) {
-    extern void * __real__malloc_r(size_t nbytes);
-    if(!inside_malloc) {
-      MallocCallCnt++;
-      TotalMallocdBytes += nbytes;
-    };
-    void *p = __real__malloc_r(nbytes);
-    return p;
-  };
-#endif
-
-// ================================================================================================
-// Implement FreeRTOS's memory API using newlib-provided malloc family.
-// ================================================================================================
-
-void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION {
-    void *p = malloc(xSize);
-    return p;
-}
-void vPortFree( void *pv ) PRIVILEGED_FUNCTION {
-    free(pv);
-};
-
-size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION {
-    struct mallinfo mi = mallinfo(); // available space now managed by newlib
-    return mi.fordblks + heapBytesRemaining; // plus space not yet handed to newlib by sbrk
-}
-
-// GetMinimumEverFree is not available in newlib's malloc implementation.
-// So, no implementation is provided: size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
-
-//! No implementation needed, but stub provided in case application already calls vPortInitialiseBlocks
-void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION {};
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/readme.txt b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/readme.txt
deleted file mode 100644
index 89f6b09..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/portable/readme.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Each real time kernel port consists of three files that contain the core kernel
-components and are common to every port, and one or more files that are
-specific to a particular microcontroller and/or compiler.
-
-
-+ The FreeRTOS/Source/Portable/MemMang directory contains the five sample
-memory allocators as described on the https://www.FreeRTOS.org WEB site.
-
-+ The other directories each contain files specific to a particular
-microcontroller or compiler, where the directory name denotes the compiler
-specific files the directory contains.
-
-
-
-For example, if you are interested in the [compiler] port for the [architecture]
-microcontroller, then the port specific files are contained in
-FreeRTOS/Source/Portable/[compiler]/[architecture] directory.  If this is the
-only port you are interested in then all the other directories can be
-ignored.
-
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/queue.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/queue.c
deleted file mode 100644
index ea5c99c..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/queue.c
+++ /dev/null
@@ -1,3018 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#include 
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers.  That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-
-#if ( configUSE_CO_ROUTINES == 1 )
-    #include "croutine.h"
-#endif
-
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
- * for the header files above, but not in this file, in order to generate the
- * correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
-
-
-/* Constants used with the cRxLock and cTxLock structure members. */
-#define queueUNLOCKED             ( ( int8_t ) -1 )
-#define queueLOCKED_UNMODIFIED    ( ( int8_t ) 0 )
-#define queueINT8_MAX             ( ( int8_t ) 127 )
-
-/* When the Queue_t structure is used to represent a base queue its pcHead and
- * pcTail members are used as pointers into the queue storage area.  When the
- * Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
- * not necessary, and the pcHead pointer is set to NULL to indicate that the
- * structure instead holds a pointer to the mutex holder (if any).  Map alternative
- * names to the pcHead and structure member to ensure the readability of the code
- * is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
- * a union as their usage is mutually exclusive dependent on what the queue is
- * being used for. */
-#define uxQueueType               pcHead
-#define queueQUEUE_IS_MUTEX       NULL
-
-typedef struct QueuePointers
-{
-    int8_t * pcTail;     /*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
-    int8_t * pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */
-} QueuePointers_t;
-
-typedef struct SemaphoreData
-{
-    TaskHandle_t xMutexHolder;        /*< The handle of the task that holds the mutex. */
-    UBaseType_t uxRecursiveCallCount; /*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
-} SemaphoreData_t;
-
-/* Semaphores do not actually store or copy data, so have an item size of
- * zero. */
-#define queueSEMAPHORE_QUEUE_ITEM_LENGTH    ( ( UBaseType_t ) 0 )
-#define queueMUTEX_GIVE_BLOCK_TIME          ( ( TickType_t ) 0U )
-
-#if ( configUSE_PREEMPTION == 0 )
-
-/* If the cooperative scheduler is being used then a yield should not be
- * performed just because a higher priority task has been woken. */
-    #define queueYIELD_IF_USING_PREEMPTION()
-#else
-    #define queueYIELD_IF_USING_PREEMPTION()    portYIELD_WITHIN_API()
-#endif
-
-/*
- * Definition of the queue used by the scheduler.
- * Items are queued by copy, not reference.  See the following link for the
- * rationale: https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
- */
-typedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */
-{
-    int8_t * pcHead;           /*< Points to the beginning of the queue storage area. */
-    int8_t * pcWriteTo;        /*< Points to the free next place in the storage area. */
-
-    union
-    {
-        QueuePointers_t xQueue;     /*< Data required exclusively when this structure is used as a queue. */
-        SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
-    } u;
-
-    List_t xTasksWaitingToSend;             /*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
-    List_t xTasksWaitingToReceive;          /*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
-
-    volatile UBaseType_t uxMessagesWaiting; /*< The number of items currently in the queue. */
-    UBaseType_t uxLength;                   /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
-    UBaseType_t uxItemSize;                 /*< The size of each items that the queue will hold. */
-
-    volatile int8_t cRxLock;                /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
-    volatile int8_t cTxLock;                /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
-
-    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-        uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
-    #endif
-
-    #if ( configUSE_QUEUE_SETS == 1 )
-        struct QueueDefinition * pxQueueSetContainer;
-    #endif
-
-    #if ( configUSE_TRACE_FACILITY == 1 )
-        UBaseType_t uxQueueNumber;
-        uint8_t ucQueueType;
-    #endif
-} xQUEUE;
-
-/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
- * name below to enable the use of older kernel aware debuggers. */
-typedef xQUEUE Queue_t;
-
-/*-----------------------------------------------------------*/
-
-/*
- * The queue registry is just a means for kernel aware debuggers to locate
- * queue structures.  It has no other purpose so is an optional component.
- */
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-/* The type stored within the queue registry array.  This allows a name
- * to be assigned to each queue making kernel aware debugging a little
- * more user friendly. */
-    typedef struct QUEUE_REGISTRY_ITEM
-    {
-        const char * pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-        QueueHandle_t xHandle;
-    } xQueueRegistryItem;
-
-/* The old xQueueRegistryItem name is maintained above then typedefed to the
- * new xQueueRegistryItem name below to enable the use of older kernel aware
- * debuggers. */
-    typedef xQueueRegistryItem QueueRegistryItem_t;
-
-/* The queue registry is simply an array of QueueRegistryItem_t structures.
- * The pcQueueName member of a structure being NULL is indicative of the
- * array position being vacant. */
-    PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
-
-#endif /* configQUEUE_REGISTRY_SIZE */
-
-/*
- * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
- * prevent an ISR from adding or removing items to the queue, but does prevent
- * an ISR from removing tasks from the queue event lists.  If an ISR finds a
- * queue is locked it will instead increment the appropriate queue lock count
- * to indicate that a task may require unblocking.  When the queue in unlocked
- * these lock counts are inspected, and the appropriate action taken.
- */
-static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * Uses a critical section to determine if there is any data in a queue.
- *
- * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
- */
-static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * Uses a critical section to determine if there is any space in a queue.
- *
- * @return pdTRUE if there is no space, otherwise pdFALSE;
- */
-static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * Copies an item into the queue, either at the front of the queue or the
- * back of the queue.
- */
-static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,
-                                      const void * pvItemToQueue,
-                                      const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
-
-/*
- * Copies an item out of a queue.
- */
-static void prvCopyDataFromQueue( Queue_t * const pxQueue,
-                                  void * const pvBuffer ) PRIVILEGED_FUNCTION;
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-/*
- * Checks to see if a queue is a member of a queue set, and if so, notifies
- * the queue set that the queue contains data.
- */
-    static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
-#endif
-
-/*
- * Called after a Queue_t structure has been allocated either statically or
- * dynamically to fill in the structure's members.
- */
-static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
-                                   const UBaseType_t uxItemSize,
-                                   uint8_t * pucQueueStorage,
-                                   const uint8_t ucQueueType,
-                                   Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * Mutexes are a special type of queue.  When a mutex is created, first the
- * queue is created, then prvInitialiseMutex() is called to configure the queue
- * as a mutex.
- */
-#if ( configUSE_MUTEXES == 1 )
-    static void prvInitialiseMutex( Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION;
-#endif
-
-#if ( configUSE_MUTEXES == 1 )
-
-/*
- * If a task waiting for a mutex causes the mutex holder to inherit a
- * priority, but the waiting task times out, then the holder should
- * disinherit the priority - but only down to the highest priority of any
- * other tasks that are waiting for the same mutex.  This function returns
- * that priority.
- */
-    static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
-#endif
-/*-----------------------------------------------------------*/
-
-/*
- * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
- * accessing the queue event lists.
- */
-#define prvLockQueue( pxQueue )                            \
-    taskENTER_CRITICAL();                                  \
-    {                                                      \
-        if( ( pxQueue )->cRxLock == queueUNLOCKED )        \
-        {                                                  \
-            ( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED; \
-        }                                                  \
-        if( ( pxQueue )->cTxLock == queueUNLOCKED )        \
-        {                                                  \
-            ( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED; \
-        }                                                  \
-    }                                                      \
-    taskEXIT_CRITICAL()
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
-                               BaseType_t xNewQueue )
-{
-    Queue_t * const pxQueue = xQueue;
-
-    configASSERT( pxQueue );
-
-    taskENTER_CRITICAL();
-    {
-        pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
-        pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
-        pxQueue->pcWriteTo = pxQueue->pcHead;
-        pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
-        pxQueue->cRxLock = queueUNLOCKED;
-        pxQueue->cTxLock = queueUNLOCKED;
-
-        if( xNewQueue == pdFALSE )
-        {
-            /* If there are tasks blocked waiting to read from the queue, then
-             * the tasks will remain blocked as after this function exits the queue
-             * will still be empty.  If there are tasks blocked waiting to write to
-             * the queue, then one should be unblocked as after this function exits
-             * it will be possible to write to it. */
-            if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-            {
-                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-                {
-                    queueYIELD_IF_USING_PREEMPTION();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            /* Ensure the event queues start in the correct state. */
-            vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
-            vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
-        }
-    }
-    taskEXIT_CRITICAL();
-
-    /* A value is returned for calling semantic consistency with previous
-     * versions. */
-    return pdPASS;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-    QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
-                                             const UBaseType_t uxItemSize,
-                                             uint8_t * pucQueueStorage,
-                                             StaticQueue_t * pxStaticQueue,
-                                             const uint8_t ucQueueType )
-    {
-        Queue_t * pxNewQueue;
-
-        configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
-
-        /* The StaticQueue_t structure and the queue storage area must be
-         * supplied. */
-        configASSERT( pxStaticQueue != NULL );
-
-        /* A queue storage area should be provided if the item size is not 0, and
-         * should not be provided if the item size is 0. */
-        configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
-        configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
-
-        #if ( configASSERT_DEFINED == 1 )
-            {
-                /* Sanity check that the size of the structure used to declare a
-                 * variable of type StaticQueue_t or StaticSemaphore_t equals the size of
-                 * the real queue and semaphore structures. */
-                volatile size_t xSize = sizeof( StaticQueue_t );
-                configASSERT( xSize == sizeof( Queue_t ) );
-                ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
-            }
-        #endif /* configASSERT_DEFINED */
-
-        /* The address of a statically allocated queue was passed in, use it.
-         * The address of a statically allocated storage area was also passed in
-         * but is already set. */
-        pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
-
-        if( pxNewQueue != NULL )
-        {
-            #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-                {
-                    /* Queues can be allocated wither statically or dynamically, so
-                     * note this queue was allocated statically in case the queue is
-                     * later deleted. */
-                    pxNewQueue->ucStaticallyAllocated = pdTRUE;
-                }
-            #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-
-            prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
-        }
-        else
-        {
-            traceQUEUE_CREATE_FAILED( ucQueueType );
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        return pxNewQueue;
-    }
-
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-    QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength,
-                                       const UBaseType_t uxItemSize,
-                                       const uint8_t ucQueueType )
-    {
-        Queue_t * pxNewQueue;
-        size_t xQueueSizeInBytes;
-        uint8_t * pucQueueStorage;
-
-        configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
-
-        /* Allocate enough space to hold the maximum number of items that
-         * can be in the queue at any time.  It is valid for uxItemSize to be
-         * zero in the case the queue is used as a semaphore. */
-        xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
-        /* Check for multiplication overflow. */
-        configASSERT( ( uxItemSize == 0 ) || ( uxQueueLength == ( xQueueSizeInBytes / uxItemSize ) ) );
-
-        /* Check for addition overflow. */
-        configASSERT( ( sizeof( Queue_t ) + xQueueSizeInBytes ) >  xQueueSizeInBytes );
-
-        /* Allocate the queue and storage area.  Justification for MISRA
-         * deviation as follows:  pvPortMalloc() always ensures returned memory
-         * blocks are aligned per the requirements of the MCU stack.  In this case
-         * pvPortMalloc() must return a pointer that is guaranteed to meet the
-         * alignment requirements of the Queue_t structure - which in this case
-         * is an int8_t *.  Therefore, whenever the stack alignment requirements
-         * are greater than or equal to the pointer to char requirements the cast
-         * is safe.  In other cases alignment requirements are not strict (one or
-         * two bytes). */
-        pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
-
-        if( pxNewQueue != NULL )
-        {
-            /* Jump past the queue structure to find the location of the queue
-             * storage area. */
-            pucQueueStorage = ( uint8_t * ) pxNewQueue;
-            pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
-
-            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-                {
-                    /* Queues can be created either statically or dynamically, so
-                     * note this task was created dynamically in case it is later
-                     * deleted. */
-                    pxNewQueue->ucStaticallyAllocated = pdFALSE;
-                }
-            #endif /* configSUPPORT_STATIC_ALLOCATION */
-
-            prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
-        }
-        else
-        {
-            traceQUEUE_CREATE_FAILED( ucQueueType );
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        return pxNewQueue;
-    }
-
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
-                                   const UBaseType_t uxItemSize,
-                                   uint8_t * pucQueueStorage,
-                                   const uint8_t ucQueueType,
-                                   Queue_t * pxNewQueue )
-{
-    /* Remove compiler warnings about unused parameters should
-     * configUSE_TRACE_FACILITY not be set to 1. */
-    ( void ) ucQueueType;
-
-    if( uxItemSize == ( UBaseType_t ) 0 )
-    {
-        /* No RAM was allocated for the queue storage area, but PC head cannot
-         * be set to NULL because NULL is used as a key to say the queue is used as
-         * a mutex.  Therefore just set pcHead to point to the queue as a benign
-         * value that is known to be within the memory map. */
-        pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
-    }
-    else
-    {
-        /* Set the head to the start of the queue storage area. */
-        pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
-    }
-
-    /* Initialise the queue members as described where the queue type is
-     * defined. */
-    pxNewQueue->uxLength = uxQueueLength;
-    pxNewQueue->uxItemSize = uxItemSize;
-    ( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
-
-    #if ( configUSE_TRACE_FACILITY == 1 )
-        {
-            pxNewQueue->ucQueueType = ucQueueType;
-        }
-    #endif /* configUSE_TRACE_FACILITY */
-
-    #if ( configUSE_QUEUE_SETS == 1 )
-        {
-            pxNewQueue->pxQueueSetContainer = NULL;
-        }
-    #endif /* configUSE_QUEUE_SETS */
-
-    traceQUEUE_CREATE( pxNewQueue );
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-    static void prvInitialiseMutex( Queue_t * pxNewQueue )
-    {
-        if( pxNewQueue != NULL )
-        {
-            /* The queue create function will set all the queue structure members
-            * correctly for a generic queue, but this function is creating a
-            * mutex.  Overwrite those members that need to be set differently -
-            * in particular the information required for priority inheritance. */
-            pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
-            pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
-
-            /* In case this is a recursive mutex. */
-            pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
-
-            traceCREATE_MUTEX( pxNewQueue );
-
-            /* Start with the semaphore in the expected state. */
-            ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
-        }
-        else
-        {
-            traceCREATE_MUTEX_FAILED();
-        }
-    }
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-    QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
-    {
-        QueueHandle_t xNewQueue;
-        const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
-
-        xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
-        prvInitialiseMutex( ( Queue_t * ) xNewQueue );
-
-        return xNewQueue;
-    }
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
-    QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
-                                           StaticQueue_t * pxStaticQueue )
-    {
-        QueueHandle_t xNewQueue;
-        const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
-
-        /* Prevent compiler warnings about unused parameters if
-         * configUSE_TRACE_FACILITY does not equal 1. */
-        ( void ) ucQueueType;
-
-        xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
-        prvInitialiseMutex( ( Queue_t * ) xNewQueue );
-
-        return xNewQueue;
-    }
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
-
-    TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
-    {
-        TaskHandle_t pxReturn;
-        Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
-
-        /* This function is called by xSemaphoreGetMutexHolder(), and should not
-         * be called directly.  Note:  This is a good way of determining if the
-         * calling task is the mutex holder, but not a good way of determining the
-         * identity of the mutex holder, as the holder may change between the
-         * following critical section exiting and the function returning. */
-        taskENTER_CRITICAL();
-        {
-            if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
-            {
-                pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
-            }
-            else
-            {
-                pxReturn = NULL;
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        return pxReturn;
-    } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
-
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
-
-    TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
-    {
-        TaskHandle_t pxReturn;
-
-        configASSERT( xSemaphore );
-
-        /* Mutexes cannot be used in interrupt service routines, so the mutex
-         * holder should not change in an ISR, and therefore a critical section is
-         * not required here. */
-        if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
-        {
-            pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
-        }
-        else
-        {
-            pxReturn = NULL;
-        }
-
-        return pxReturn;
-    } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
-
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-
-    BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
-    {
-        BaseType_t xReturn;
-        Queue_t * const pxMutex = ( Queue_t * ) xMutex;
-
-        configASSERT( pxMutex );
-
-        /* If this is the task that holds the mutex then xMutexHolder will not
-         * change outside of this task.  If this task does not hold the mutex then
-         * pxMutexHolder can never coincidentally equal the tasks handle, and as
-         * this is the only condition we are interested in it does not matter if
-         * pxMutexHolder is accessed simultaneously by another task.  Therefore no
-         * mutual exclusion is required to test the pxMutexHolder variable. */
-        if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
-        {
-            traceGIVE_MUTEX_RECURSIVE( pxMutex );
-
-            /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
-             * the task handle, therefore no underflow check is required.  Also,
-             * uxRecursiveCallCount is only modified by the mutex holder, and as
-             * there can only be one, no mutual exclusion is required to modify the
-             * uxRecursiveCallCount member. */
-            ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
-
-            /* Has the recursive call count unwound to 0? */
-            if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
-            {
-                /* Return the mutex.  This will automatically unblock any other
-                 * task that might be waiting to access the mutex. */
-                ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            xReturn = pdPASS;
-        }
-        else
-        {
-            /* The mutex cannot be given because the calling task is not the
-             * holder. */
-            xReturn = pdFAIL;
-
-            traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
-        }
-
-        return xReturn;
-    }
-
-#endif /* configUSE_RECURSIVE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-
-    BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait )
-    {
-        BaseType_t xReturn;
-        Queue_t * const pxMutex = ( Queue_t * ) xMutex;
-
-        configASSERT( pxMutex );
-
-        /* Comments regarding mutual exclusion as per those within
-         * xQueueGiveMutexRecursive(). */
-
-        traceTAKE_MUTEX_RECURSIVE( pxMutex );
-
-        if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
-        {
-            ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
-            xReturn = pdPASS;
-        }
-        else
-        {
-            xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
-
-            /* pdPASS will only be returned if the mutex was successfully
-             * obtained.  The calling task may have entered the Blocked state
-             * before reaching here. */
-            if( xReturn != pdFAIL )
-            {
-                ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
-            }
-            else
-            {
-                traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
-            }
-        }
-
-        return xReturn;
-    }
-
-#endif /* configUSE_RECURSIVE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
-    QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
-                                                       const UBaseType_t uxInitialCount,
-                                                       StaticQueue_t * pxStaticQueue )
-    {
-        QueueHandle_t xHandle;
-
-        configASSERT( uxMaxCount != 0 );
-        configASSERT( uxInitialCount <= uxMaxCount );
-
-        xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
-
-        if( xHandle != NULL )
-        {
-            ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
-
-            traceCREATE_COUNTING_SEMAPHORE();
-        }
-        else
-        {
-            traceCREATE_COUNTING_SEMAPHORE_FAILED();
-        }
-
-        return xHandle;
-    }
-
-#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-    QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
-                                                 const UBaseType_t uxInitialCount )
-    {
-        QueueHandle_t xHandle;
-
-        configASSERT( uxMaxCount != 0 );
-        configASSERT( uxInitialCount <= uxMaxCount );
-
-        xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
-
-        if( xHandle != NULL )
-        {
-            ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
-
-            traceCREATE_COUNTING_SEMAPHORE();
-        }
-        else
-        {
-            traceCREATE_COUNTING_SEMAPHORE_FAILED();
-        }
-
-        return xHandle;
-    }
-
-#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
-                              const void * const pvItemToQueue,
-                              TickType_t xTicksToWait,
-                              const BaseType_t xCopyPosition )
-{
-    BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
-    TimeOut_t xTimeOut;
-    Queue_t * const pxQueue = xQueue;
-
-    configASSERT( pxQueue );
-    configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-    configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
-    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-        {
-            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-        }
-    #endif
-
-    /*lint -save -e904 This function relaxes the coding standard somewhat to
-     * allow return statements within the function itself.  This is done in the
-     * interest of execution time efficiency. */
-    for( ; ; )
-    {
-        taskENTER_CRITICAL();
-        {
-            /* Is there room on the queue now?  The running task must be the
-             * highest priority task wanting to access the queue.  If the head item
-             * in the queue is to be overwritten then it does not matter if the
-             * queue is full. */
-            if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
-            {
-                traceQUEUE_SEND( pxQueue );
-
-                #if ( configUSE_QUEUE_SETS == 1 )
-                    {
-                        const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-                        xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
-
-                        if( pxQueue->pxQueueSetContainer != NULL )
-                        {
-                            if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
-                            {
-                                /* Do not notify the queue set as an existing item
-                                 * was overwritten in the queue so the number of items
-                                 * in the queue has not changed. */
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                            else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
-                            {
-                                /* The queue is a member of a queue set, and posting
-                                 * to the queue set caused a higher priority task to
-                                 * unblock. A context switch is required. */
-                                queueYIELD_IF_USING_PREEMPTION();
-                            }
-                            else
-                            {
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                        }
-                        else
-                        {
-                            /* If there was a task waiting for data to arrive on the
-                             * queue then unblock it now. */
-                            if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-                            {
-                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-                                {
-                                    /* The unblocked task has a priority higher than
-                                     * our own so yield immediately.  Yes it is ok to
-                                     * do this from within the critical section - the
-                                     * kernel takes care of that. */
-                                    queueYIELD_IF_USING_PREEMPTION();
-                                }
-                                else
-                                {
-                                    mtCOVERAGE_TEST_MARKER();
-                                }
-                            }
-                            else if( xYieldRequired != pdFALSE )
-                            {
-                                /* This path is a special case that will only get
-                                 * executed if the task was holding multiple mutexes
-                                 * and the mutexes were given back in an order that is
-                                 * different to that in which they were taken. */
-                                queueYIELD_IF_USING_PREEMPTION();
-                            }
-                            else
-                            {
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                        }
-                    }
-                #else /* configUSE_QUEUE_SETS */
-                    {
-                        xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
-
-                        /* If there was a task waiting for data to arrive on the
-                         * queue then unblock it now. */
-                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-                        {
-                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-                            {
-                                /* The unblocked task has a priority higher than
-                                 * our own so yield immediately.  Yes it is ok to do
-                                 * this from within the critical section - the kernel
-                                 * takes care of that. */
-                                queueYIELD_IF_USING_PREEMPTION();
-                            }
-                            else
-                            {
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                        }
-                        else if( xYieldRequired != pdFALSE )
-                        {
-                            /* This path is a special case that will only get
-                             * executed if the task was holding multiple mutexes and
-                             * the mutexes were given back in an order that is
-                             * different to that in which they were taken. */
-                            queueYIELD_IF_USING_PREEMPTION();
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                #endif /* configUSE_QUEUE_SETS */
-
-                taskEXIT_CRITICAL();
-                return pdPASS;
-            }
-            else
-            {
-                if( xTicksToWait == ( TickType_t ) 0 )
-                {
-                    /* The queue was full and no block time is specified (or
-                     * the block time has expired) so leave now. */
-                    taskEXIT_CRITICAL();
-
-                    /* Return to the original privilege level before exiting
-                     * the function. */
-                    traceQUEUE_SEND_FAILED( pxQueue );
-                    return errQUEUE_FULL;
-                }
-                else if( xEntryTimeSet == pdFALSE )
-                {
-                    /* The queue was full and a block time was specified so
-                     * configure the timeout structure. */
-                    vTaskInternalSetTimeOutState( &xTimeOut );
-                    xEntryTimeSet = pdTRUE;
-                }
-                else
-                {
-                    /* Entry time was already set. */
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        /* Interrupts and other tasks can send to and receive from the queue
-         * now the critical section has been exited. */
-
-        vTaskSuspendAll();
-        prvLockQueue( pxQueue );
-
-        /* Update the timeout state to see if it has expired yet. */
-        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
-        {
-            if( prvIsQueueFull( pxQueue ) != pdFALSE )
-            {
-                traceBLOCKING_ON_QUEUE_SEND( pxQueue );
-                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
-
-                /* Unlocking the queue means queue events can effect the
-                 * event list.  It is possible that interrupts occurring now
-                 * remove this task from the event list again - but as the
-                 * scheduler is suspended the task will go onto the pending
-                 * ready last instead of the actual ready list. */
-                prvUnlockQueue( pxQueue );
-
-                /* Resuming the scheduler will move tasks from the pending
-                 * ready list into the ready list - so it is feasible that this
-                 * task is already in a ready list before it yields - in which
-                 * case the yield will not cause a context switch unless there
-                 * is also a higher priority task in the pending ready list. */
-                if( xTaskResumeAll() == pdFALSE )
-                {
-                    portYIELD_WITHIN_API();
-                }
-            }
-            else
-            {
-                /* Try again. */
-                prvUnlockQueue( pxQueue );
-                ( void ) xTaskResumeAll();
-            }
-        }
-        else
-        {
-            /* The timeout has expired. */
-            prvUnlockQueue( pxQueue );
-            ( void ) xTaskResumeAll();
-
-            traceQUEUE_SEND_FAILED( pxQueue );
-            return errQUEUE_FULL;
-        }
-    } /*lint -restore */
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
-                                     const void * const pvItemToQueue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const BaseType_t xCopyPosition )
-{
-    BaseType_t xReturn;
-    UBaseType_t uxSavedInterruptStatus;
-    Queue_t * const pxQueue = xQueue;
-
-    configASSERT( pxQueue );
-    configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-    configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
-
-    /* RTOS ports that support interrupt nesting have the concept of a maximum
-     * system call (or maximum API call) interrupt priority.  Interrupts that are
-     * above the maximum system call priority are kept permanently enabled, even
-     * when the RTOS kernel is in a critical section, but cannot make any calls to
-     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-     * failure if a FreeRTOS API function is called from an interrupt that has been
-     * assigned a priority above the configured maximum system call priority.
-     * Only FreeRTOS functions that end in FromISR can be called from interrupts
-     * that have been assigned a priority at or (logically) below the maximum
-     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
-     * safe API to ensure interrupt entry is as fast and as simple as possible.
-     * More information (albeit Cortex-M specific) is provided on the following
-     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-    /* Similar to xQueueGenericSend, except without blocking if there is no room
-     * in the queue.  Also don't directly wake a task that was blocked on a queue
-     * read, instead return a flag to say whether a context switch is required or
-     * not (i.e. has a task with a higher priority than us been woken by this
-     * post). */
-    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-    {
-        if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
-        {
-            const int8_t cTxLock = pxQueue->cTxLock;
-            const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-            traceQUEUE_SEND_FROM_ISR( pxQueue );
-
-            /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
-             *  semaphore or mutex.  That means prvCopyDataToQueue() cannot result
-             *  in a task disinheriting a priority and prvCopyDataToQueue() can be
-             *  called here even though the disinherit function does not check if
-             *  the scheduler is suspended before accessing the ready lists. */
-            ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
-
-            /* The event list is not altered if the queue is locked.  This will
-             * be done when the queue is unlocked later. */
-            if( cTxLock == queueUNLOCKED )
-            {
-                #if ( configUSE_QUEUE_SETS == 1 )
-                    {
-                        if( pxQueue->pxQueueSetContainer != NULL )
-                        {
-                            if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
-                            {
-                                /* Do not notify the queue set as an existing item
-                                 * was overwritten in the queue so the number of items
-                                 * in the queue has not changed. */
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                            else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
-                            {
-                                /* The queue is a member of a queue set, and posting
-                                 * to the queue set caused a higher priority task to
-                                 * unblock.  A context switch is required. */
-                                if( pxHigherPriorityTaskWoken != NULL )
-                                {
-                                    *pxHigherPriorityTaskWoken = pdTRUE;
-                                }
-                                else
-                                {
-                                    mtCOVERAGE_TEST_MARKER();
-                                }
-                            }
-                            else
-                            {
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                        }
-                        else
-                        {
-                            if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-                            {
-                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-                                {
-                                    /* The task waiting has a higher priority so
-                                     *  record that a context switch is required. */
-                                    if( pxHigherPriorityTaskWoken != NULL )
-                                    {
-                                        *pxHigherPriorityTaskWoken = pdTRUE;
-                                    }
-                                    else
-                                    {
-                                        mtCOVERAGE_TEST_MARKER();
-                                    }
-                                }
-                                else
-                                {
-                                    mtCOVERAGE_TEST_MARKER();
-                                }
-                            }
-                            else
-                            {
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                        }
-                    }
-                #else /* configUSE_QUEUE_SETS */
-                    {
-                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-                        {
-                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-                            {
-                                /* The task waiting has a higher priority so record that a
-                                 * context switch is required. */
-                                if( pxHigherPriorityTaskWoken != NULL )
-                                {
-                                    *pxHigherPriorityTaskWoken = pdTRUE;
-                                }
-                                else
-                                {
-                                    mtCOVERAGE_TEST_MARKER();
-                                }
-                            }
-                            else
-                            {
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-
-                        /* Not used in this path. */
-                        ( void ) uxPreviousMessagesWaiting;
-                    }
-                #endif /* configUSE_QUEUE_SETS */
-            }
-            else
-            {
-                /* Increment the lock count so the task that unlocks the queue
-                 * knows that data was posted while it was locked. */
-                configASSERT( cTxLock != queueINT8_MAX );
-
-                pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
-            }
-
-            xReturn = pdPASS;
-        }
-        else
-        {
-            traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
-            xReturn = errQUEUE_FULL;
-        }
-    }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
-                              BaseType_t * const pxHigherPriorityTaskWoken )
-{
-    BaseType_t xReturn;
-    UBaseType_t uxSavedInterruptStatus;
-    Queue_t * const pxQueue = xQueue;
-
-    /* Similar to xQueueGenericSendFromISR() but used with semaphores where the
-     * item size is 0.  Don't directly wake a task that was blocked on a queue
-     * read, instead return a flag to say whether a context switch is required or
-     * not (i.e. has a task with a higher priority than us been woken by this
-     * post). */
-
-    configASSERT( pxQueue );
-
-    /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
-     * if the item size is not 0. */
-    configASSERT( pxQueue->uxItemSize == 0 );
-
-    /* Normally a mutex would not be given from an interrupt, especially if
-     * there is a mutex holder, as priority inheritance makes no sense for an
-     * interrupts, only tasks. */
-    configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
-
-    /* RTOS ports that support interrupt nesting have the concept of a maximum
-     * system call (or maximum API call) interrupt priority.  Interrupts that are
-     * above the maximum system call priority are kept permanently enabled, even
-     * when the RTOS kernel is in a critical section, but cannot make any calls to
-     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-     * failure if a FreeRTOS API function is called from an interrupt that has been
-     * assigned a priority above the configured maximum system call priority.
-     * Only FreeRTOS functions that end in FromISR can be called from interrupts
-     * that have been assigned a priority at or (logically) below the maximum
-     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
-     * safe API to ensure interrupt entry is as fast and as simple as possible.
-     * More information (albeit Cortex-M specific) is provided on the following
-     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-    {
-        const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-        /* When the queue is used to implement a semaphore no data is ever
-         * moved through the queue but it is still valid to see if the queue 'has
-         * space'. */
-        if( uxMessagesWaiting < pxQueue->uxLength )
-        {
-            const int8_t cTxLock = pxQueue->cTxLock;
-
-            traceQUEUE_SEND_FROM_ISR( pxQueue );
-
-            /* A task can only have an inherited priority if it is a mutex
-             * holder - and if there is a mutex holder then the mutex cannot be
-             * given from an ISR.  As this is the ISR version of the function it
-             * can be assumed there is no mutex holder and no need to determine if
-             * priority disinheritance is needed.  Simply increase the count of
-             * messages (semaphores) available. */
-            pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
-
-            /* The event list is not altered if the queue is locked.  This will
-             * be done when the queue is unlocked later. */
-            if( cTxLock == queueUNLOCKED )
-            {
-                #if ( configUSE_QUEUE_SETS == 1 )
-                    {
-                        if( pxQueue->pxQueueSetContainer != NULL )
-                        {
-                            if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
-                            {
-                                /* The semaphore is a member of a queue set, and
-                                 * posting to the queue set caused a higher priority
-                                 * task to unblock.  A context switch is required. */
-                                if( pxHigherPriorityTaskWoken != NULL )
-                                {
-                                    *pxHigherPriorityTaskWoken = pdTRUE;
-                                }
-                                else
-                                {
-                                    mtCOVERAGE_TEST_MARKER();
-                                }
-                            }
-                            else
-                            {
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                        }
-                        else
-                        {
-                            if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-                            {
-                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-                                {
-                                    /* The task waiting has a higher priority so
-                                     *  record that a context switch is required. */
-                                    if( pxHigherPriorityTaskWoken != NULL )
-                                    {
-                                        *pxHigherPriorityTaskWoken = pdTRUE;
-                                    }
-                                    else
-                                    {
-                                        mtCOVERAGE_TEST_MARKER();
-                                    }
-                                }
-                                else
-                                {
-                                    mtCOVERAGE_TEST_MARKER();
-                                }
-                            }
-                            else
-                            {
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                        }
-                    }
-                #else /* configUSE_QUEUE_SETS */
-                    {
-                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-                        {
-                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-                            {
-                                /* The task waiting has a higher priority so record that a
-                                 * context switch is required. */
-                                if( pxHigherPriorityTaskWoken != NULL )
-                                {
-                                    *pxHigherPriorityTaskWoken = pdTRUE;
-                                }
-                                else
-                                {
-                                    mtCOVERAGE_TEST_MARKER();
-                                }
-                            }
-                            else
-                            {
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                #endif /* configUSE_QUEUE_SETS */
-            }
-            else
-            {
-                /* Increment the lock count so the task that unlocks the queue
-                 * knows that data was posted while it was locked. */
-                configASSERT( cTxLock != queueINT8_MAX );
-
-                pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
-            }
-
-            xReturn = pdPASS;
-        }
-        else
-        {
-            traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
-            xReturn = errQUEUE_FULL;
-        }
-    }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueReceive( QueueHandle_t xQueue,
-                          void * const pvBuffer,
-                          TickType_t xTicksToWait )
-{
-    BaseType_t xEntryTimeSet = pdFALSE;
-    TimeOut_t xTimeOut;
-    Queue_t * const pxQueue = xQueue;
-
-    /* Check the pointer is not NULL. */
-    configASSERT( ( pxQueue ) );
-
-    /* The buffer into which data is received can only be NULL if the data size
-     * is zero (so no data is copied into the buffer). */
-    configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
-
-    /* Cannot block if the scheduler is suspended. */
-    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-        {
-            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-        }
-    #endif
-
-    /*lint -save -e904  This function relaxes the coding standard somewhat to
-     * allow return statements within the function itself.  This is done in the
-     * interest of execution time efficiency. */
-    for( ; ; )
-    {
-        taskENTER_CRITICAL();
-        {
-            const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-            /* Is there data in the queue now?  To be running the calling task
-             * must be the highest priority task wanting to access the queue. */
-            if( uxMessagesWaiting > ( UBaseType_t ) 0 )
-            {
-                /* Data available, remove one item. */
-                prvCopyDataFromQueue( pxQueue, pvBuffer );
-                traceQUEUE_RECEIVE( pxQueue );
-                pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
-
-                /* There is now space in the queue, were any tasks waiting to
-                 * post to the queue?  If so, unblock the highest priority waiting
-                 * task. */
-                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-                {
-                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-                    {
-                        queueYIELD_IF_USING_PREEMPTION();
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                taskEXIT_CRITICAL();
-                return pdPASS;
-            }
-            else
-            {
-                if( xTicksToWait == ( TickType_t ) 0 )
-                {
-                    /* The queue was empty and no block time is specified (or
-                     * the block time has expired) so leave now. */
-                    taskEXIT_CRITICAL();
-                    traceQUEUE_RECEIVE_FAILED( pxQueue );
-                    return errQUEUE_EMPTY;
-                }
-                else if( xEntryTimeSet == pdFALSE )
-                {
-                    /* The queue was empty and a block time was specified so
-                     * configure the timeout structure. */
-                    vTaskInternalSetTimeOutState( &xTimeOut );
-                    xEntryTimeSet = pdTRUE;
-                }
-                else
-                {
-                    /* Entry time was already set. */
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        /* Interrupts and other tasks can send to and receive from the queue
-         * now the critical section has been exited. */
-
-        vTaskSuspendAll();
-        prvLockQueue( pxQueue );
-
-        /* Update the timeout state to see if it has expired yet. */
-        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
-        {
-            /* The timeout has not expired.  If the queue is still empty place
-             * the task on the list of tasks waiting to receive from the queue. */
-            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-            {
-                traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
-                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
-                prvUnlockQueue( pxQueue );
-
-                if( xTaskResumeAll() == pdFALSE )
-                {
-                    portYIELD_WITHIN_API();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                /* The queue contains data again.  Loop back to try and read the
-                 * data. */
-                prvUnlockQueue( pxQueue );
-                ( void ) xTaskResumeAll();
-            }
-        }
-        else
-        {
-            /* Timed out.  If there is no data in the queue exit, otherwise loop
-             * back and attempt to read the data. */
-            prvUnlockQueue( pxQueue );
-            ( void ) xTaskResumeAll();
-
-            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-            {
-                traceQUEUE_RECEIVE_FAILED( pxQueue );
-                return errQUEUE_EMPTY;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-    } /*lint -restore */
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                TickType_t xTicksToWait )
-{
-    BaseType_t xEntryTimeSet = pdFALSE;
-    TimeOut_t xTimeOut;
-    Queue_t * const pxQueue = xQueue;
-    void *pvBuffer = NULL;
-    (void)pvBuffer;
-
-    #if ( configUSE_MUTEXES == 1 )
-        BaseType_t xInheritanceOccurred = pdFALSE;
-    #endif
-
-    /* Check the queue pointer is not NULL. */
-    configASSERT( ( pxQueue ) );
-
-    /* Check this really is a semaphore, in which case the item size will be
-     * 0. */
-    configASSERT( pxQueue->uxItemSize == 0 );
-
-    /* Cannot block if the scheduler is suspended. */
-    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-        {
-            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-        }
-    #endif
-
-    /*lint -save -e904 This function relaxes the coding standard somewhat to allow return
-     * statements within the function itself.  This is done in the interest
-     * of execution time efficiency. */
-    for( ; ; )
-    {
-        taskENTER_CRITICAL();
-        {
-            /* Semaphores are queues with an item size of 0, and where the
-             * number of messages in the queue is the semaphore's count value. */
-            const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
-
-            /* Is there data in the queue now?  To be running the calling task
-             * must be the highest priority task wanting to access the queue. */
-            if( uxSemaphoreCount > ( UBaseType_t ) 0 )
-            {
-                traceQUEUE_RECEIVE( pxQueue );
-
-                /* Semaphores are queues with a data size of zero and where the
-                 * messages waiting is the semaphore's count.  Reduce the count. */
-                pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
-
-                #if ( configUSE_MUTEXES == 1 )
-                    {
-                        if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
-                        {
-                            /* Record the information required to implement
-                             * priority inheritance should it become necessary. */
-                            pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                #endif /* configUSE_MUTEXES */
-
-                /* Check to see if other tasks are blocked waiting to give the
-                 * semaphore, and if so, unblock the highest priority such task. */
-                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-                {
-                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-                    {
-                        queueYIELD_IF_USING_PREEMPTION();
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                taskEXIT_CRITICAL();
-                return pdPASS;
-            }
-            else
-            {
-                if( xTicksToWait == ( TickType_t ) 0 )
-                {
-                    /* For inheritance to have occurred there must have been an
-                     * initial timeout, and an adjusted timeout cannot become 0, as
-                     * if it were 0 the function would have exited. */
-                    #if ( configUSE_MUTEXES == 1 )
-                        {
-                            configASSERT( xInheritanceOccurred == pdFALSE );
-                        }
-                    #endif /* configUSE_MUTEXES */
-
-                    /* The semaphore count was 0 and no block time is specified
-                     * (or the block time has expired) so exit now. */
-                    taskEXIT_CRITICAL();
-                    traceQUEUE_RECEIVE_FAILED( pxQueue );
-                    return errQUEUE_EMPTY;
-                }
-                else if( xEntryTimeSet == pdFALSE )
-                {
-                    /* The semaphore count was 0 and a block time was specified
-                     * so configure the timeout structure ready to block. */
-                    vTaskInternalSetTimeOutState( &xTimeOut );
-                    xEntryTimeSet = pdTRUE;
-                }
-                else
-                {
-                    /* Entry time was already set. */
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        /* Interrupts and other tasks can give to and take from the semaphore
-         * now the critical section has been exited. */
-
-        vTaskSuspendAll();
-        prvLockQueue( pxQueue );
-
-        /* Update the timeout state to see if it has expired yet. */
-        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
-        {
-            /* A block time is specified and not expired.  If the semaphore
-             * count is 0 then enter the Blocked state to wait for a semaphore to
-             * become available.  As semaphores are implemented with queues the
-             * queue being empty is equivalent to the semaphore count being 0. */
-            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-            {
-                traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
-
-                #if ( configUSE_MUTEXES == 1 )
-                    {
-                        if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
-                        {
-                            taskENTER_CRITICAL();
-                            {
-                                xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
-                            }
-                            taskEXIT_CRITICAL();
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                #endif /* if ( configUSE_MUTEXES == 1 ) */
-
-                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
-                prvUnlockQueue( pxQueue );
-
-                if( xTaskResumeAll() == pdFALSE )
-                {
-                    portYIELD_WITHIN_API();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                /* There was no timeout and the semaphore count was not 0, so
-                 * attempt to take the semaphore again. */
-                prvUnlockQueue( pxQueue );
-                ( void ) xTaskResumeAll();
-            }
-        }
-        else
-        {
-            /* Timed out. */
-            prvUnlockQueue( pxQueue );
-            ( void ) xTaskResumeAll();
-
-            /* If the semaphore count is 0 exit now as the timeout has
-             * expired.  Otherwise return to attempt to take the semaphore that is
-             * known to be available.  As semaphores are implemented by queues the
-             * queue being empty is equivalent to the semaphore count being 0. */
-            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-            {
-                #if ( configUSE_MUTEXES == 1 )
-                    {
-                        /* xInheritanceOccurred could only have be set if
-                         * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
-                         * test the mutex type again to check it is actually a mutex. */
-                        if( xInheritanceOccurred != pdFALSE )
-                        {
-                            taskENTER_CRITICAL();
-                            {
-                                UBaseType_t uxHighestWaitingPriority;
-
-                                /* This task blocking on the mutex caused another
-                                 * task to inherit this task's priority.  Now this task
-                                 * has timed out the priority should be disinherited
-                                 * again, but only as low as the next highest priority
-                                 * task that is waiting for the same mutex. */
-                                uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
-                                vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
-                            }
-                            taskEXIT_CRITICAL();
-                        }
-                    }
-                #endif /* configUSE_MUTEXES */
-
-                traceQUEUE_RECEIVE_FAILED( pxQueue );
-                return errQUEUE_EMPTY;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-    } /*lint -restore */
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueuePeek( QueueHandle_t xQueue,
-                       void * const pvBuffer,
-                       TickType_t xTicksToWait )
-{
-    BaseType_t xEntryTimeSet = pdFALSE;
-    TimeOut_t xTimeOut;
-    int8_t * pcOriginalReadPosition;
-    Queue_t * const pxQueue = xQueue;
-
-    /* Check the pointer is not NULL. */
-    configASSERT( ( pxQueue ) );
-
-    /* The buffer into which data is received can only be NULL if the data size
-     * is zero (so no data is copied into the buffer. */
-    configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
-
-    /* Cannot block if the scheduler is suspended. */
-    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-        {
-            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-        }
-    #endif
-
-    /*lint -save -e904  This function relaxes the coding standard somewhat to
-     * allow return statements within the function itself.  This is done in the
-     * interest of execution time efficiency. */
-    for( ; ; )
-    {
-        taskENTER_CRITICAL();
-        {
-            const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-            /* Is there data in the queue now?  To be running the calling task
-             * must be the highest priority task wanting to access the queue. */
-            if( uxMessagesWaiting > ( UBaseType_t ) 0 )
-            {
-                /* Remember the read position so it can be reset after the data
-                 * is read from the queue as this function is only peeking the
-                 * data, not removing it. */
-                pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
-
-                prvCopyDataFromQueue( pxQueue, pvBuffer );
-                traceQUEUE_PEEK( pxQueue );
-
-                /* The data is not being removed, so reset the read pointer. */
-                pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
-
-                /* The data is being left in the queue, so see if there are
-                 * any other tasks waiting for the data. */
-                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-                {
-                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-                    {
-                        /* The task waiting has a higher priority than this task. */
-                        queueYIELD_IF_USING_PREEMPTION();
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                taskEXIT_CRITICAL();
-                return pdPASS;
-            }
-            else
-            {
-                if( xTicksToWait == ( TickType_t ) 0 )
-                {
-                    /* The queue was empty and no block time is specified (or
-                     * the block time has expired) so leave now. */
-                    taskEXIT_CRITICAL();
-                    traceQUEUE_PEEK_FAILED( pxQueue );
-                    return errQUEUE_EMPTY;
-                }
-                else if( xEntryTimeSet == pdFALSE )
-                {
-                    /* The queue was empty and a block time was specified so
-                     * configure the timeout structure ready to enter the blocked
-                     * state. */
-                    vTaskInternalSetTimeOutState( &xTimeOut );
-                    xEntryTimeSet = pdTRUE;
-                }
-                else
-                {
-                    /* Entry time was already set. */
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        /* Interrupts and other tasks can send to and receive from the queue
-         * now the critical section has been exited. */
-
-        vTaskSuspendAll();
-        prvLockQueue( pxQueue );
-
-        /* Update the timeout state to see if it has expired yet. */
-        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
-        {
-            /* Timeout has not expired yet, check to see if there is data in the
-            * queue now, and if not enter the Blocked state to wait for data. */
-            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-            {
-                traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
-                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
-                prvUnlockQueue( pxQueue );
-
-                if( xTaskResumeAll() == pdFALSE )
-                {
-                    portYIELD_WITHIN_API();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                /* There is data in the queue now, so don't enter the blocked
-                 * state, instead return to try and obtain the data. */
-                prvUnlockQueue( pxQueue );
-                ( void ) xTaskResumeAll();
-            }
-        }
-        else
-        {
-            /* The timeout has expired.  If there is still no data in the queue
-             * exit, otherwise go back and try to read the data again. */
-            prvUnlockQueue( pxQueue );
-            ( void ) xTaskResumeAll();
-
-            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-            {
-                traceQUEUE_PEEK_FAILED( pxQueue );
-                return errQUEUE_EMPTY;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-    } /*lint -restore */
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
-                                 void * const pvBuffer,
-                                 BaseType_t * const pxHigherPriorityTaskWoken )
-{
-    BaseType_t xReturn;
-    UBaseType_t uxSavedInterruptStatus;
-    Queue_t * const pxQueue = xQueue;
-
-    configASSERT( pxQueue );
-    configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-
-    /* RTOS ports that support interrupt nesting have the concept of a maximum
-     * system call (or maximum API call) interrupt priority.  Interrupts that are
-     * above the maximum system call priority are kept permanently enabled, even
-     * when the RTOS kernel is in a critical section, but cannot make any calls to
-     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-     * failure if a FreeRTOS API function is called from an interrupt that has been
-     * assigned a priority above the configured maximum system call priority.
-     * Only FreeRTOS functions that end in FromISR can be called from interrupts
-     * that have been assigned a priority at or (logically) below the maximum
-     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
-     * safe API to ensure interrupt entry is as fast and as simple as possible.
-     * More information (albeit Cortex-M specific) is provided on the following
-     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-    {
-        const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-        /* Cannot block in an ISR, so check there is data available. */
-        if( uxMessagesWaiting > ( UBaseType_t ) 0 )
-        {
-            const int8_t cRxLock = pxQueue->cRxLock;
-
-            traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
-
-            prvCopyDataFromQueue( pxQueue, pvBuffer );
-            pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
-
-            /* If the queue is locked the event list will not be modified.
-             * Instead update the lock count so the task that unlocks the queue
-             * will know that an ISR has removed data while the queue was
-             * locked. */
-            if( cRxLock == queueUNLOCKED )
-            {
-                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-                {
-                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-                    {
-                        /* The task waiting has a higher priority than us so
-                         * force a context switch. */
-                        if( pxHigherPriorityTaskWoken != NULL )
-                        {
-                            *pxHigherPriorityTaskWoken = pdTRUE;
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                /* Increment the lock count so the task that unlocks the queue
-                 * knows that data was removed while it was locked. */
-                configASSERT( cRxLock != queueINT8_MAX );
-
-                pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
-            }
-
-            xReturn = pdPASS;
-        }
-        else
-        {
-            xReturn = pdFAIL;
-            traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
-        }
-    }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
-                              void * const pvBuffer )
-{
-    BaseType_t xReturn;
-    UBaseType_t uxSavedInterruptStatus;
-    int8_t * pcOriginalReadPosition;
-    Queue_t * const pxQueue = xQueue;
-
-    configASSERT( pxQueue );
-    configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-    configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
-
-    /* RTOS ports that support interrupt nesting have the concept of a maximum
-     * system call (or maximum API call) interrupt priority.  Interrupts that are
-     * above the maximum system call priority are kept permanently enabled, even
-     * when the RTOS kernel is in a critical section, but cannot make any calls to
-     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-     * failure if a FreeRTOS API function is called from an interrupt that has been
-     * assigned a priority above the configured maximum system call priority.
-     * Only FreeRTOS functions that end in FromISR can be called from interrupts
-     * that have been assigned a priority at or (logically) below the maximum
-     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
-     * safe API to ensure interrupt entry is as fast and as simple as possible.
-     * More information (albeit Cortex-M specific) is provided on the following
-     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-    {
-        /* Cannot block in an ISR, so check there is data available. */
-        if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
-        {
-            traceQUEUE_PEEK_FROM_ISR( pxQueue );
-
-            /* Remember the read position so it can be reset as nothing is
-             * actually being removed from the queue. */
-            pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
-            prvCopyDataFromQueue( pxQueue, pvBuffer );
-            pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
-
-            xReturn = pdPASS;
-        }
-        else
-        {
-            xReturn = pdFAIL;
-            traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
-        }
-    }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
-{
-    UBaseType_t uxReturn;
-
-    configASSERT( xQueue );
-
-    taskENTER_CRITICAL();
-    {
-        uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
-    }
-    taskEXIT_CRITICAL();
-
-    return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
-{
-    UBaseType_t uxReturn;
-    Queue_t * const pxQueue = xQueue;
-
-    configASSERT( pxQueue );
-
-    taskENTER_CRITICAL();
-    {
-        uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
-    }
-    taskEXIT_CRITICAL();
-
-    return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
-{
-    UBaseType_t uxReturn;
-    Queue_t * const pxQueue = xQueue;
-
-    configASSERT( pxQueue );
-    uxReturn = pxQueue->uxMessagesWaiting;
-
-    return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
-/*-----------------------------------------------------------*/
-
-void vQueueDelete( QueueHandle_t xQueue )
-{
-    Queue_t * const pxQueue = xQueue;
-
-    configASSERT( pxQueue );
-    traceQUEUE_DELETE( pxQueue );
-
-    #if ( configQUEUE_REGISTRY_SIZE > 0 )
-        {
-            vQueueUnregisterQueue( pxQueue );
-        }
-    #endif
-
-    #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
-        {
-            /* The queue can only have been allocated dynamically - free it
-             * again. */
-            vPortFree( pxQueue );
-        }
-    #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-        {
-            /* The queue could have been allocated statically or dynamically, so
-             * check before attempting to free the memory. */
-            if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
-            {
-                vPortFree( pxQueue );
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-    #else /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) */
-        {
-            /* The queue must have been statically allocated, so is not going to be
-             * deleted.  Avoid compiler warnings about the unused parameter. */
-            ( void ) pxQueue;
-        }
-    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
-    {
-        return ( ( Queue_t * ) xQueue )->uxQueueNumber;
-    }
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    void vQueueSetQueueNumber( QueueHandle_t xQueue,
-                               UBaseType_t uxQueueNumber )
-    {
-        ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
-    }
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
-    {
-        return ( ( Queue_t * ) xQueue )->ucQueueType;
-    }
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-    static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
-    {
-        UBaseType_t uxHighestPriorityOfWaitingTasks;
-
-        /* If a task waiting for a mutex causes the mutex holder to inherit a
-         * priority, but the waiting task times out, then the holder should
-         * disinherit the priority - but only down to the highest priority of any
-         * other tasks that are waiting for the same mutex.  For this purpose,
-         * return the priority of the highest priority task that is waiting for the
-         * mutex. */
-        if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
-        {
-            uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
-        }
-        else
-        {
-            uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
-        }
-
-        return uxHighestPriorityOfWaitingTasks;
-    }
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,
-                                      const void * pvItemToQueue,
-                                      const BaseType_t xPosition )
-{
-    BaseType_t xReturn = pdFALSE;
-    UBaseType_t uxMessagesWaiting;
-
-    /* This function is called from a critical section. */
-
-    uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-    if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
-    {
-        #if ( configUSE_MUTEXES == 1 )
-            {
-                if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
-                {
-                    /* The mutex is no longer being held. */
-                    xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
-                    pxQueue->u.xSemaphore.xMutexHolder = NULL;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        #endif /* configUSE_MUTEXES */
-    }
-    else if( xPosition == queueSEND_TO_BACK )
-    {
-        ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
-        pxQueue->pcWriteTo += pxQueue->uxItemSize;                                                       /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
-
-        if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail )                                             /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
-        {
-            pxQueue->pcWriteTo = pxQueue->pcHead;
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    else
-    {
-        ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
-        pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
-
-        if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
-        {
-            pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        if( xPosition == queueOVERWRITE )
-        {
-            if( uxMessagesWaiting > ( UBaseType_t ) 0 )
-            {
-                /* An item is not being added but overwritten, so subtract
-                 * one from the recorded number of items in the queue so when
-                 * one is added again below the number of recorded items remains
-                 * correct. */
-                --uxMessagesWaiting;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-
-    pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static void prvCopyDataFromQueue( Queue_t * const pxQueue,
-                                  void * const pvBuffer )
-{
-    if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
-    {
-        pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;           /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
-
-        if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
-        {
-            pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
-    }
-}
-/*-----------------------------------------------------------*/
-
-static void prvUnlockQueue( Queue_t * const pxQueue )
-{
-    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
-
-    /* The lock counts contains the number of extra data items placed or
-     * removed from the queue while the queue was locked.  When a queue is
-     * locked items can be added or removed, but the event lists cannot be
-     * updated. */
-    taskENTER_CRITICAL();
-    {
-        int8_t cTxLock = pxQueue->cTxLock;
-
-        /* See if data was added to the queue while it was locked. */
-        while( cTxLock > queueLOCKED_UNMODIFIED )
-        {
-            /* Data was posted while the queue was locked.  Are any tasks
-             * blocked waiting for data to become available? */
-            #if ( configUSE_QUEUE_SETS == 1 )
-                {
-                    if( pxQueue->pxQueueSetContainer != NULL )
-                    {
-                        if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
-                        {
-                            /* The queue is a member of a queue set, and posting to
-                             * the queue set caused a higher priority task to unblock.
-                             * A context switch is required. */
-                            vTaskMissedYield();
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                    else
-                    {
-                        /* Tasks that are removed from the event list will get
-                         * added to the pending ready list as the scheduler is still
-                         * suspended. */
-                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-                        {
-                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-                            {
-                                /* The task waiting has a higher priority so record that a
-                                 * context switch is required. */
-                                vTaskMissedYield();
-                            }
-                            else
-                            {
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                        }
-                        else
-                        {
-                            break;
-                        }
-                    }
-                }
-            #else /* configUSE_QUEUE_SETS */
-                {
-                    /* Tasks that are removed from the event list will get added to
-                     * the pending ready list as the scheduler is still suspended. */
-                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-                    {
-                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-                        {
-                            /* The task waiting has a higher priority so record that
-                             * a context switch is required. */
-                            vTaskMissedYield();
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                    else
-                    {
-                        break;
-                    }
-                }
-            #endif /* configUSE_QUEUE_SETS */
-
-            --cTxLock;
-        }
-
-        pxQueue->cTxLock = queueUNLOCKED;
-    }
-    taskEXIT_CRITICAL();
-
-    /* Do the same for the Rx lock. */
-    taskENTER_CRITICAL();
-    {
-        int8_t cRxLock = pxQueue->cRxLock;
-
-        while( cRxLock > queueLOCKED_UNMODIFIED )
-        {
-            if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-            {
-                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-                {
-                    vTaskMissedYield();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                --cRxLock;
-            }
-            else
-            {
-                break;
-            }
-        }
-
-        pxQueue->cRxLock = queueUNLOCKED;
-    }
-    taskEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue )
-{
-    BaseType_t xReturn;
-
-    taskENTER_CRITICAL();
-    {
-        if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
-        {
-            xReturn = pdTRUE;
-        }
-        else
-        {
-            xReturn = pdFALSE;
-        }
-    }
-    taskEXIT_CRITICAL();
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
-{
-    BaseType_t xReturn;
-    Queue_t * const pxQueue = xQueue;
-
-    configASSERT( pxQueue );
-
-    if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
-    {
-        xReturn = pdTRUE;
-    }
-    else
-    {
-        xReturn = pdFALSE;
-    }
-
-    return xReturn;
-} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvIsQueueFull( const Queue_t * pxQueue )
-{
-    BaseType_t xReturn;
-
-    taskENTER_CRITICAL();
-    {
-        if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
-        {
-            xReturn = pdTRUE;
-        }
-        else
-        {
-            xReturn = pdFALSE;
-        }
-    }
-    taskEXIT_CRITICAL();
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
-{
-    BaseType_t xReturn;
-    Queue_t * const pxQueue = xQueue;
-
-    configASSERT( pxQueue );
-
-    if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
-    {
-        xReturn = pdTRUE;
-    }
-    else
-    {
-        xReturn = pdFALSE;
-    }
-
-    return xReturn;
-} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_CO_ROUTINES == 1 )
-
-    BaseType_t xQueueCRSend( QueueHandle_t xQueue,
-                             const void * pvItemToQueue,
-                             TickType_t xTicksToWait )
-    {
-        BaseType_t xReturn;
-        Queue_t * const pxQueue = xQueue;
-
-        /* If the queue is already full we may have to block.  A critical section
-         * is required to prevent an interrupt removing something from the queue
-         * between the check to see if the queue is full and blocking on the queue. */
-        portDISABLE_INTERRUPTS();
-        {
-            if( prvIsQueueFull( pxQueue ) != pdFALSE )
-            {
-                /* The queue is full - do we want to block or just leave without
-                 * posting? */
-                if( xTicksToWait > ( TickType_t ) 0 )
-                {
-                    /* As this is called from a coroutine we cannot block directly, but
-                     * return indicating that we need to block. */
-                    vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
-                    portENABLE_INTERRUPTS();
-                    return errQUEUE_BLOCKED;
-                }
-                else
-                {
-                    portENABLE_INTERRUPTS();
-                    return errQUEUE_FULL;
-                }
-            }
-        }
-        portENABLE_INTERRUPTS();
-
-        portDISABLE_INTERRUPTS();
-        {
-            if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
-            {
-                /* There is room in the queue, copy the data into the queue. */
-                prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
-                xReturn = pdPASS;
-
-                /* Were any co-routines waiting for data to become available? */
-                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-                {
-                    /* In this instance the co-routine could be placed directly
-                     * into the ready list as we are within a critical section.
-                     * Instead the same pending ready list mechanism is used as if
-                     * the event were caused from within an interrupt. */
-                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-                    {
-                        /* The co-routine waiting has a higher priority so record
-                         * that a yield might be appropriate. */
-                        xReturn = errQUEUE_YIELD;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                xReturn = errQUEUE_FULL;
-            }
-        }
-        portENABLE_INTERRUPTS();
-
-        return xReturn;
-    }
-
-#endif /* configUSE_CO_ROUTINES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_CO_ROUTINES == 1 )
-
-    BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
-                                void * pvBuffer,
-                                TickType_t xTicksToWait )
-    {
-        BaseType_t xReturn;
-        Queue_t * const pxQueue = xQueue;
-
-        /* If the queue is already empty we may have to block.  A critical section
-         * is required to prevent an interrupt adding something to the queue
-         * between the check to see if the queue is empty and blocking on the queue. */
-        portDISABLE_INTERRUPTS();
-        {
-            if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
-            {
-                /* There are no messages in the queue, do we want to block or just
-                 * leave with nothing? */
-                if( xTicksToWait > ( TickType_t ) 0 )
-                {
-                    /* As this is a co-routine we cannot block directly, but return
-                     * indicating that we need to block. */
-                    vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
-                    portENABLE_INTERRUPTS();
-                    return errQUEUE_BLOCKED;
-                }
-                else
-                {
-                    portENABLE_INTERRUPTS();
-                    return errQUEUE_FULL;
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        portENABLE_INTERRUPTS();
-
-        portDISABLE_INTERRUPTS();
-        {
-            if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
-            {
-                /* Data is available from the queue. */
-                pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
-
-                if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
-                {
-                    pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                --( pxQueue->uxMessagesWaiting );
-                ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
-
-                xReturn = pdPASS;
-
-                /* Were any co-routines waiting for space to become available? */
-                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-                {
-                    /* In this instance the co-routine could be placed directly
-                     * into the ready list as we are within a critical section.
-                     * Instead the same pending ready list mechanism is used as if
-                     * the event were caused from within an interrupt. */
-                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-                    {
-                        xReturn = errQUEUE_YIELD;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                xReturn = pdFAIL;
-            }
-        }
-        portENABLE_INTERRUPTS();
-
-        return xReturn;
-    }
-
-#endif /* configUSE_CO_ROUTINES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_CO_ROUTINES == 1 )
-
-    BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
-                                    const void * pvItemToQueue,
-                                    BaseType_t xCoRoutinePreviouslyWoken )
-    {
-        Queue_t * const pxQueue = xQueue;
-
-        /* Cannot block within an ISR so if there is no space on the queue then
-         * exit without doing anything. */
-        if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
-        {
-            prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
-
-            /* We only want to wake one co-routine per ISR, so check that a
-             * co-routine has not already been woken. */
-            if( xCoRoutinePreviouslyWoken == pdFALSE )
-            {
-                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-                {
-                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-                    {
-                        return pdTRUE;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        return xCoRoutinePreviouslyWoken;
-    }
-
-#endif /* configUSE_CO_ROUTINES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_CO_ROUTINES == 1 )
-
-    BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
-                                       void * pvBuffer,
-                                       BaseType_t * pxCoRoutineWoken )
-    {
-        BaseType_t xReturn;
-        Queue_t * const pxQueue = xQueue;
-
-        /* We cannot block from an ISR, so check there is data available. If
-         * not then just leave without doing anything. */
-        if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
-        {
-            /* Copy the data from the queue. */
-            pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
-
-            if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
-            {
-                pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            --( pxQueue->uxMessagesWaiting );
-            ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
-
-            if( ( *pxCoRoutineWoken ) == pdFALSE )
-            {
-                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-                {
-                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-                    {
-                        *pxCoRoutineWoken = pdTRUE;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            xReturn = pdPASS;
-        }
-        else
-        {
-            xReturn = pdFAIL;
-        }
-
-        return xReturn;
-    }
-
-#endif /* configUSE_CO_ROUTINES */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-    void vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-    {
-        UBaseType_t ux;
-
-        /* See if there is an empty space in the registry.  A NULL name denotes
-         * a free slot. */
-        for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
-        {
-            if( xQueueRegistry[ ux ].pcQueueName == NULL )
-            {
-                /* Store the information on this queue. */
-                xQueueRegistry[ ux ].pcQueueName = pcQueueName;
-                xQueueRegistry[ ux ].xHandle = xQueue;
-
-                traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
-                break;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-    }
-
-#endif /* configQUEUE_REGISTRY_SIZE */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-    const char * pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-    {
-        UBaseType_t ux;
-        const char * pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-        /* Note there is nothing here to protect against another task adding or
-         * removing entries from the registry while it is being searched. */
-
-        for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
-        {
-            if( xQueueRegistry[ ux ].xHandle == xQueue )
-            {
-                pcReturn = xQueueRegistry[ ux ].pcQueueName;
-                break;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-
-        return pcReturn;
-    } /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
-
-#endif /* configQUEUE_REGISTRY_SIZE */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-    void vQueueUnregisterQueue( QueueHandle_t xQueue )
-    {
-        UBaseType_t ux;
-
-        /* See if the handle of the queue being unregistered in actually in the
-         * registry. */
-        for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
-        {
-            if( xQueueRegistry[ ux ].xHandle == xQueue )
-            {
-                /* Set the name to NULL to show that this slot if free again. */
-                xQueueRegistry[ ux ].pcQueueName = NULL;
-
-                /* Set the handle to NULL to ensure the same queue handle cannot
-                 * appear in the registry twice if it is added, removed, then
-                 * added again. */
-                xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
-                break;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-    } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
-
-#endif /* configQUEUE_REGISTRY_SIZE */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-    void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
-                                         TickType_t xTicksToWait,
-                                         const BaseType_t xWaitIndefinitely )
-    {
-        Queue_t * const pxQueue = xQueue;
-
-        /* This function should not be called by application code hence the
-         * 'Restricted' in its name.  It is not part of the public API.  It is
-         * designed for use by kernel code, and has special calling requirements.
-         * It can result in vListInsert() being called on a list that can only
-         * possibly ever have one item in it, so the list will be fast, but even
-         * so it should be called with the scheduler locked and not from a critical
-         * section. */
-
-        /* Only do anything if there are no messages in the queue.  This function
-         *  will not actually cause the task to block, just place it on a blocked
-         *  list.  It will not block until the scheduler is unlocked - at which
-         *  time a yield will be performed.  If an item is added to the queue while
-         *  the queue is locked, and the calling task blocks on the queue, then the
-         *  calling task will be immediately unblocked when the queue is unlocked. */
-        prvLockQueue( pxQueue );
-
-        if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
-        {
-            /* There is nothing in the queue, block for the specified period. */
-            vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        prvUnlockQueue( pxQueue );
-    }
-
-#endif /* configUSE_TIMERS */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-    QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
-    {
-        QueueSetHandle_t pxQueue;
-
-        pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
-
-        return pxQueue;
-    }
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-    BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet )
-    {
-        BaseType_t xReturn;
-
-        taskENTER_CRITICAL();
-        {
-            if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
-            {
-                /* Cannot add a queue/semaphore to more than one queue set. */
-                xReturn = pdFAIL;
-            }
-            else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
-            {
-                /* Cannot add a queue/semaphore to a queue set if there are already
-                 * items in the queue/semaphore. */
-                xReturn = pdFAIL;
-            }
-            else
-            {
-                ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
-                xReturn = pdPASS;
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        return xReturn;
-    }
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-    BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                                    QueueSetHandle_t xQueueSet )
-    {
-        BaseType_t xReturn;
-        Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
-
-        if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
-        {
-            /* The queue was not a member of the set. */
-            xReturn = pdFAIL;
-        }
-        else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
-        {
-            /* It is dangerous to remove a queue from a set when the queue is
-             * not empty because the queue set will still hold pending events for
-             * the queue. */
-            xReturn = pdFAIL;
-        }
-        else
-        {
-            taskENTER_CRITICAL();
-            {
-                /* The queue is no longer contained in the set. */
-                pxQueueOrSemaphore->pxQueueSetContainer = NULL;
-            }
-            taskEXIT_CRITICAL();
-            xReturn = pdPASS;
-        }
-
-        return xReturn;
-    } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-    QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                TickType_t const xTicksToWait )
-    {
-        QueueSetMemberHandle_t xReturn = NULL;
-
-        ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
-        return xReturn;
-    }
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-    QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
-    {
-        QueueSetMemberHandle_t xReturn = NULL;
-
-        ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
-        return xReturn;
-    }
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-    static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue )
-    {
-        Queue_t * pxQueueSetContainer = pxQueue->pxQueueSetContainer;
-        BaseType_t xReturn = pdFALSE;
-
-        /* This function must be called form a critical section. */
-
-        configASSERT( pxQueueSetContainer );
-        configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
-
-        if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
-        {
-            const int8_t cTxLock = pxQueueSetContainer->cTxLock;
-
-            traceQUEUE_SET_SEND( pxQueueSetContainer );
-
-            /* The data copied is the handle of the queue that contains data. */
-            xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK );
-
-            if( cTxLock == queueUNLOCKED )
-            {
-                if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
-                {
-                    if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
-                    {
-                        /* The task waiting has a higher priority. */
-                        xReturn = pdTRUE;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                configASSERT( cTxLock != queueINT8_MAX );
-
-                pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        return xReturn;
-    }
-
-#endif /* configUSE_QUEUE_SETS */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/stream_buffer.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/stream_buffer.c
deleted file mode 100644
index f2f43d8..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/stream_buffer.c
+++ /dev/null
@@ -1,1314 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers.  That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* FreeRTOS includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "stream_buffer.h"
-
-#if ( configUSE_TASK_NOTIFICATIONS != 1 )
-    #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
-#endif
-
-/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
- * for the header files above, but not in this file, in order to generate the
- * correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
-
-/* If the user has not provided application specific Rx notification macros,
- * or #defined the notification macros away, them provide default implementations
- * that uses task notifications. */
-/*lint -save -e9026 Function like macros allowed and needed here so they can be overridden. */
-#ifndef sbRECEIVE_COMPLETED
-    #define sbRECEIVE_COMPLETED( pxStreamBuffer )                         \
-    vTaskSuspendAll();                                                    \
-    {                                                                     \
-        if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )              \
-        {                                                                 \
-            ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \
-                                  ( uint32_t ) 0,                         \
-                                  eNoAction );                            \
-            ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                \
-        }                                                                 \
-    }                                                                     \
-    ( void ) xTaskResumeAll();
-#endif /* sbRECEIVE_COMPLETED */
-
-#ifndef sbRECEIVE_COMPLETED_FROM_ISR
-    #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                            \
-                                          pxHigherPriorityTaskWoken )                \
-    {                                                                                \
-        UBaseType_t uxSavedInterruptStatus;                                          \
-                                                                                     \
-        uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();  \
-        {                                                                            \
-            if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )                     \
-            {                                                                        \
-                ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \
-                                             ( uint32_t ) 0,                         \
-                                             eNoAction,                              \
-                                             pxHigherPriorityTaskWoken );            \
-                ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                       \
-            }                                                                        \
-        }                                                                            \
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );                 \
-    }
-#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
-
-/* If the user has not provided an application specific Tx notification macro,
- * or #defined the notification macro away, them provide a default implementation
- * that uses task notifications. */
-#ifndef sbSEND_COMPLETED
-    #define sbSEND_COMPLETED( pxStreamBuffer )                               \
-    vTaskSuspendAll();                                                       \
-    {                                                                        \
-        if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )              \
-        {                                                                    \
-            ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive, \
-                                  ( uint32_t ) 0,                            \
-                                  eNoAction );                               \
-            ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                \
-        }                                                                    \
-    }                                                                        \
-    ( void ) xTaskResumeAll();
-#endif /* sbSEND_COMPLETED */
-
-#ifndef sbSEND_COMPLETE_FROM_ISR
-    #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )       \
-    {                                                                                   \
-        UBaseType_t uxSavedInterruptStatus;                                             \
-                                                                                        \
-        uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();     \
-        {                                                                               \
-            if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )                     \
-            {                                                                           \
-                ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \
-                                             ( uint32_t ) 0,                            \
-                                             eNoAction,                                 \
-                                             pxHigherPriorityTaskWoken );               \
-                ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                       \
-            }                                                                           \
-        }                                                                               \
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );                    \
-    }
-#endif /* sbSEND_COMPLETE_FROM_ISR */
-/*lint -restore (9026) */
-
-/* The number of bytes used to hold the length of a message in the buffer. */
-#define sbBYTES_TO_STORE_MESSAGE_LENGTH    ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
-
-/* Bits stored in the ucFlags field of the stream buffer. */
-#define sbFLAGS_IS_MESSAGE_BUFFER          ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
-#define sbFLAGS_IS_STATICALLY_ALLOCATED    ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
-
-/*-----------------------------------------------------------*/
-
-/* Structure that hold state information on the buffer. */
-typedef struct StreamBufferDef_t                 /*lint !e9058 Style convention uses tag. */
-{
-    volatile size_t xTail;                       /* Index to the next item to read within the buffer. */
-    volatile size_t xHead;                       /* Index to the next item to write within the buffer. */
-    size_t xLength;                              /* The length of the buffer pointed to by pucBuffer. */
-    size_t xTriggerLevelBytes;                   /* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
-    volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
-    volatile TaskHandle_t xTaskWaitingToSend;    /* Holds the handle of a task waiting to send data to a message buffer that is full. */
-    uint8_t * pucBuffer;                         /* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
-    uint8_t ucFlags;
-
-    #if ( configUSE_TRACE_FACILITY == 1 )
-        UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */
-    #endif
-} StreamBuffer_t;
-
-/*
- * The number of bytes available to be read from the buffer.
- */
-static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/*
- * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
- * Returns the number of bytes written, which will either equal xCount in the
- * success case, or 0 if there was not enough space in the buffer (in which case
- * no data is written into the buffer).
- */
-static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer,
-                                     const uint8_t * pucData,
-                                     size_t xCount ) PRIVILEGED_FUNCTION;
-
-/*
- * If the stream buffer is being used as a message buffer, then reads an entire
- * message out of the buffer.  If the stream buffer is being used as a stream
- * buffer then read as many bytes as possible from the buffer.
- * prvReadBytesFromBuffer() is called to actually extract the bytes from the
- * buffer's data storage area.
- */
-static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer,
-                                        void * pvRxData,
-                                        size_t xBufferLengthBytes,
-                                        size_t xBytesAvailable,
-                                        size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
-
-/*
- * If the stream buffer is being used as a message buffer, then writes an entire
- * message to the buffer.  If the stream buffer is being used as a stream
- * buffer then write as many bytes as possible to the buffer.
- * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
- * data storage area.
- */
-static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
-                                       const void * pvTxData,
-                                       size_t xDataLengthBytes,
-                                       size_t xSpace,
-                                       size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
-
-/*
- * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
- * to pucData.
- */
-static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer,
-                                      uint8_t * pucData,
-                                      size_t xMaxCount,
-                                      size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
-
-/*
- * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
- * initialise the members of the newly created stream buffer structure.
- */
-static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
-                                          uint8_t * const pucBuffer,
-                                          size_t xBufferSizeBytes,
-                                          size_t xTriggerLevelBytes,
-                                          uint8_t ucFlags ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-    StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
-                                                     size_t xTriggerLevelBytes,
-                                                     BaseType_t xIsMessageBuffer )
-    {
-        uint8_t * pucAllocatedMemory;
-        uint8_t ucFlags;
-
-        /* In case the stream buffer is going to be used as a message buffer
-         * (that is, it will hold discrete messages with a little meta data that
-         * says how big the next message is) check the buffer will be large enough
-         * to hold at least one message. */
-        if( xIsMessageBuffer == pdTRUE )
-        {
-            /* Is a message buffer but not statically allocated. */
-            ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
-            configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
-        }
-        else
-        {
-            /* Not a message buffer and not statically allocated. */
-            ucFlags = 0;
-            configASSERT( xBufferSizeBytes > 0 );
-        }
-
-        configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
-
-        /* A trigger level of 0 would cause a waiting task to unblock even when
-         * the buffer was empty. */
-        if( xTriggerLevelBytes == ( size_t ) 0 )
-        {
-            xTriggerLevelBytes = ( size_t ) 1;
-        }
-
-        /* A stream buffer requires a StreamBuffer_t structure and a buffer.
-         * Both are allocated in a single call to pvPortMalloc().  The
-         * StreamBuffer_t structure is placed at the start of the allocated memory
-         * and the buffer follows immediately after.  The requested size is
-         * incremented so the free space is returned as the user would expect -
-         * this is a quirk of the implementation that means otherwise the free
-         * space would be reported as one byte smaller than would be logically
-         * expected. */
-        if( xBufferSizeBytes < ( xBufferSizeBytes + 1 + sizeof( StreamBuffer_t ) ) )
-        {
-            xBufferSizeBytes++;
-            pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
-        }
-        else
-        {
-            pucAllocatedMemory = NULL;
-        }
-        
-
-        if( pucAllocatedMemory != NULL )
-        {
-            prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory,       /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
-                                          pucAllocatedMemory + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
-                                          xBufferSizeBytes,
-                                          xTriggerLevelBytes,
-                                          ucFlags );
-
-            traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
-        }
-        else
-        {
-            traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
-        }
-
-        return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
-    }
-
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-    StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
-                                                           size_t xTriggerLevelBytes,
-                                                           BaseType_t xIsMessageBuffer,
-                                                           uint8_t * const pucStreamBufferStorageArea,
-                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer )
-    {
-        StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
-        StreamBufferHandle_t xReturn;
-        uint8_t ucFlags;
-
-        configASSERT( pucStreamBufferStorageArea );
-        configASSERT( pxStaticStreamBuffer );
-        configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
-
-        /* A trigger level of 0 would cause a waiting task to unblock even when
-         * the buffer was empty. */
-        if( xTriggerLevelBytes == ( size_t ) 0 )
-        {
-            xTriggerLevelBytes = ( size_t ) 1;
-        }
-
-        if( xIsMessageBuffer != pdFALSE )
-        {
-            /* Statically allocated message buffer. */
-            ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
-        }
-        else
-        {
-            /* Statically allocated stream buffer. */
-            ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
-        }
-
-        /* In case the stream buffer is going to be used as a message buffer
-         * (that is, it will hold discrete messages with a little meta data that
-         * says how big the next message is) check the buffer will be large enough
-         * to hold at least one message. */
-        configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
-
-        #if ( configASSERT_DEFINED == 1 )
-            {
-                /* Sanity check that the size of the structure used to declare a
-                 * variable of type StaticStreamBuffer_t equals the size of the real
-                 * message buffer structure. */
-                volatile size_t xSize = sizeof( StaticStreamBuffer_t );
-                configASSERT( xSize == sizeof( StreamBuffer_t ) );
-            } /*lint !e529 xSize is referenced is configASSERT() is defined. */
-        #endif /* configASSERT_DEFINED */
-
-        if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
-        {
-            prvInitialiseNewStreamBuffer( pxStreamBuffer,
-                                          pucStreamBufferStorageArea,
-                                          xBufferSizeBytes,
-                                          xTriggerLevelBytes,
-                                          ucFlags );
-
-            /* Remember this was statically allocated in case it is ever deleted
-             * again. */
-            pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
-
-            traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
-
-            xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
-        }
-        else
-        {
-            xReturn = NULL;
-            traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
-        }
-
-        return xReturn;
-    }
-
-#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-/*-----------------------------------------------------------*/
-
-void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
-{
-    StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
-
-    configASSERT( pxStreamBuffer );
-
-    traceSTREAM_BUFFER_DELETE( xStreamBuffer );
-
-    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
-    {
-        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-            {
-                /* Both the structure and the buffer were allocated using a single call
-                * to pvPortMalloc(), hence only one call to vPortFree() is required. */
-                vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
-            }
-        #else
-            {
-                /* Should not be possible to get here, ucFlags must be corrupt.
-                 * Force an assert. */
-                configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
-            }
-        #endif
-    }
-    else
-    {
-        /* The structure and buffer were not allocated dynamically and cannot be
-         * freed - just scrub the structure so future use will assert. */
-        ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
-    }
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
-{
-    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-    BaseType_t xReturn = pdFAIL;
-
-    #if ( configUSE_TRACE_FACILITY == 1 )
-        UBaseType_t uxStreamBufferNumber;
-    #endif
-
-    configASSERT( pxStreamBuffer );
-
-    #if ( configUSE_TRACE_FACILITY == 1 )
-        {
-            /* Store the stream buffer number so it can be restored after the
-             * reset. */
-            uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
-        }
-    #endif
-
-    /* Can only reset a message buffer if there are no tasks blocked on it. */
-    taskENTER_CRITICAL();
-    {
-        if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
-        {
-            if( pxStreamBuffer->xTaskWaitingToSend == NULL )
-            {
-                prvInitialiseNewStreamBuffer( pxStreamBuffer,
-                                              pxStreamBuffer->pucBuffer,
-                                              pxStreamBuffer->xLength,
-                                              pxStreamBuffer->xTriggerLevelBytes,
-                                              pxStreamBuffer->ucFlags );
-                xReturn = pdPASS;
-
-                #if ( configUSE_TRACE_FACILITY == 1 )
-                    {
-                        pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
-                    }
-                #endif
-
-                traceSTREAM_BUFFER_RESET( xStreamBuffer );
-            }
-        }
-    }
-    taskEXIT_CRITICAL();
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                         size_t xTriggerLevel )
-{
-    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-    BaseType_t xReturn;
-
-    configASSERT( pxStreamBuffer );
-
-    /* It is not valid for the trigger level to be 0. */
-    if( xTriggerLevel == ( size_t ) 0 )
-    {
-        xTriggerLevel = ( size_t ) 1;
-    }
-
-    /* The trigger level is the number of bytes that must be in the stream
-     * buffer before a task that is waiting for data is unblocked. */
-    if( xTriggerLevel <= pxStreamBuffer->xLength )
-    {
-        pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
-        xReturn = pdPASS;
-    }
-    else
-    {
-        xReturn = pdFALSE;
-    }
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
-{
-    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-    size_t xSpace;
-
-    configASSERT( pxStreamBuffer );
-
-    xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
-    xSpace -= pxStreamBuffer->xHead;
-    xSpace -= ( size_t ) 1;
-
-    if( xSpace >= pxStreamBuffer->xLength )
-    {
-        xSpace -= pxStreamBuffer->xLength;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    return xSpace;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
-{
-    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-    size_t xReturn;
-
-    configASSERT( pxStreamBuffer );
-
-    xReturn = prvBytesInBuffer( pxStreamBuffer );
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                          const void * pvTxData,
-                          size_t xDataLengthBytes,
-                          TickType_t xTicksToWait )
-{
-    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-    size_t xReturn, xSpace = 0;
-    size_t xRequiredSpace = xDataLengthBytes;
-    TimeOut_t xTimeOut;
-
-    /* The maximum amount of space a stream buffer will ever report is its length
-     * minus 1. */
-    const size_t xMaxReportedSpace = pxStreamBuffer->xLength - ( size_t ) 1;
-
-    configASSERT( pvTxData );
-    configASSERT( pxStreamBuffer );
-
-    /* This send function is used to write to both message buffers and stream
-     * buffers.  If this is a message buffer then the space needed must be
-     * increased by the amount of bytes needed to store the length of the
-     * message. */
-    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-    {
-        xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
-
-        /* Overflow? */
-        configASSERT( xRequiredSpace > xDataLengthBytes );
-
-        /* If this is a message buffer then it must be possible to write the
-         * whole message. */
-        if( xRequiredSpace > xMaxReportedSpace )
-        {
-            /* The message would not fit even if the entire buffer was empty,
-             * so don't wait for space. */
-            xTicksToWait = ( TickType_t ) 0;
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    else
-    {
-        /* If this is a stream buffer then it is acceptable to write only part
-         * of the message to the buffer.  Cap the length to the total length of
-         * the buffer. */
-        if( xRequiredSpace > xMaxReportedSpace )
-        {
-            xRequiredSpace = xMaxReportedSpace;
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-
-    if( xTicksToWait != ( TickType_t ) 0 )
-    {
-        vTaskSetTimeOutState( &xTimeOut );
-
-        do
-        {
-            /* Wait until the required number of bytes are free in the message
-             * buffer. */
-            taskENTER_CRITICAL();
-            {
-                xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
-
-                if( xSpace < xRequiredSpace )
-                {
-                    /* Clear notification state as going to wait for space. */
-                    ( void ) xTaskNotifyStateClear( NULL );
-
-                    /* Should only be one writer. */
-                    configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
-                    pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
-                }
-                else
-                {
-                    taskEXIT_CRITICAL();
-                    break;
-                }
-            }
-            taskEXIT_CRITICAL();
-
-            traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
-            ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
-            pxStreamBuffer->xTaskWaitingToSend = NULL;
-        } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    if( xSpace == ( size_t ) 0 )
-    {
-        xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
-
-    if( xReturn > ( size_t ) 0 )
-    {
-        traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
-
-        /* Was a task waiting for the data? */
-        if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
-        {
-            sbSEND_COMPLETED( pxStreamBuffer );
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-        traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
-    }
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
-                                 const void * pvTxData,
-                                 size_t xDataLengthBytes,
-                                 BaseType_t * const pxHigherPriorityTaskWoken )
-{
-    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-    size_t xReturn, xSpace;
-    size_t xRequiredSpace = xDataLengthBytes;
-
-    configASSERT( pvTxData );
-    configASSERT( pxStreamBuffer );
-
-    /* This send function is used to write to both message buffers and stream
-     * buffers.  If this is a message buffer then the space needed must be
-     * increased by the amount of bytes needed to store the length of the
-     * message. */
-    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-    {
-        xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
-    xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
-
-    if( xReturn > ( size_t ) 0 )
-    {
-        /* Was a task waiting for the data? */
-        if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
-        {
-            sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
-                                       const void * pvTxData,
-                                       size_t xDataLengthBytes,
-                                       size_t xSpace,
-                                       size_t xRequiredSpace )
-{
-    BaseType_t xShouldWrite;
-    size_t xReturn;
-
-    if( xSpace == ( size_t ) 0 )
-    {
-        /* Doesn't matter if this is a stream buffer or a message buffer, there
-         * is no space to write. */
-        xShouldWrite = pdFALSE;
-    }
-    else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
-    {
-        /* This is a stream buffer, as opposed to a message buffer, so writing a
-         * stream of bytes rather than discrete messages.  Write as many bytes as
-         * possible. */
-        xShouldWrite = pdTRUE;
-        xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
-    }
-    else if( xSpace >= xRequiredSpace )
-    {
-        /* This is a message buffer, as opposed to a stream buffer, and there
-         * is enough space to write both the message length and the message itself
-         * into the buffer.  Start by writing the length of the data, the data
-         * itself will be written later in this function. */
-        xShouldWrite = pdTRUE;
-        ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
-    }
-    else
-    {
-        /* There is space available, but not enough space. */
-        xShouldWrite = pdFALSE;
-    }
-
-    if( xShouldWrite != pdFALSE )
-    {
-        /* Writes the data itself. */
-        xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alignment and access. */
-    }
-    else
-    {
-        xReturn = 0;
-    }
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                             void * pvRxData,
-                             size_t xBufferLengthBytes,
-                             TickType_t xTicksToWait )
-{
-    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-    size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
-
-    configASSERT( pvRxData );
-    configASSERT( pxStreamBuffer );
-
-    /* This receive function is used by both message buffers, which store
-     * discrete messages, and stream buffers, which store a continuous stream of
-     * bytes.  Discrete messages include an additional
-     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
-     * message. */
-    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-    {
-        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
-    }
-    else
-    {
-        xBytesToStoreMessageLength = 0;
-    }
-
-    if( xTicksToWait != ( TickType_t ) 0 )
-    {
-        /* Checking if there is data and clearing the notification state must be
-         * performed atomically. */
-        taskENTER_CRITICAL();
-        {
-            xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-
-            /* If this function was invoked by a message buffer read then
-             * xBytesToStoreMessageLength holds the number of bytes used to hold
-             * the length of the next discrete message.  If this function was
-             * invoked by a stream buffer read then xBytesToStoreMessageLength will
-             * be 0. */
-            if( xBytesAvailable <= xBytesToStoreMessageLength )
-            {
-                /* Clear notification state as going to wait for data. */
-                ( void ) xTaskNotifyStateClear( NULL );
-
-                /* Should only be one reader. */
-                configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
-                pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        if( xBytesAvailable <= xBytesToStoreMessageLength )
-        {
-            /* Wait for data to be available. */
-            traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
-            ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
-            pxStreamBuffer->xTaskWaitingToReceive = NULL;
-
-            /* Recheck the data available after blocking. */
-            xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    else
-    {
-        xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-    }
-
-    /* Whether receiving a discrete message (where xBytesToStoreMessageLength
-     * holds the number of bytes used to store the message length) or a stream of
-     * bytes (where xBytesToStoreMessageLength is zero), the number of bytes
-     * available must be greater than xBytesToStoreMessageLength to be able to
-     * read bytes from the buffer. */
-    if( xBytesAvailable > xBytesToStoreMessageLength )
-    {
-        xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
-
-        /* Was a task waiting for space in the buffer? */
-        if( xReceivedLength != ( size_t ) 0 )
-        {
-            traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
-            sbRECEIVE_COMPLETED( pxStreamBuffer );
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    else
-    {
-        traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    return xReceivedLength;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
-{
-    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-    size_t xReturn, xBytesAvailable, xOriginalTail;
-    configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
-
-    configASSERT( pxStreamBuffer );
-
-    /* Ensure the stream buffer is being used as a message buffer. */
-    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-    {
-        xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-
-        if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
-        {
-            /* The number of bytes available is greater than the number of bytes
-             * required to hold the length of the next message, so another message
-             * is available.  Return its length without removing the length bytes
-             * from the buffer.  A copy of the tail is stored so the buffer can be
-             * returned to its prior state as the message is not actually being
-             * removed from the buffer. */
-            xOriginalTail = pxStreamBuffer->xTail;
-            ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
-            xReturn = ( size_t ) xTempReturn;
-            pxStreamBuffer->xTail = xOriginalTail;
-        }
-        else
-        {
-            /* The minimum amount of bytes in a message buffer is
-             * ( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
-             * less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
-             * value is 0. */
-            configASSERT( xBytesAvailable == 0 );
-            xReturn = 0;
-        }
-    }
-    else
-    {
-        xReturn = 0;
-    }
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
-                                    void * pvRxData,
-                                    size_t xBufferLengthBytes,
-                                    BaseType_t * const pxHigherPriorityTaskWoken )
-{
-    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-    size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
-
-    configASSERT( pvRxData );
-    configASSERT( pxStreamBuffer );
-
-    /* This receive function is used by both message buffers, which store
-     * discrete messages, and stream buffers, which store a continuous stream of
-     * bytes.  Discrete messages include an additional
-     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
-     * message. */
-    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-    {
-        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
-    }
-    else
-    {
-        xBytesToStoreMessageLength = 0;
-    }
-
-    xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-
-    /* Whether receiving a discrete message (where xBytesToStoreMessageLength
-     * holds the number of bytes used to store the message length) or a stream of
-     * bytes (where xBytesToStoreMessageLength is zero), the number of bytes
-     * available must be greater than xBytesToStoreMessageLength to be able to
-     * read bytes from the buffer. */
-    if( xBytesAvailable > xBytesToStoreMessageLength )
-    {
-        xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
-
-        /* Was a task waiting for space in the buffer? */
-        if( xReceivedLength != ( size_t ) 0 )
-        {
-            sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
-
-    return xReceivedLength;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer,
-                                        void * pvRxData,
-                                        size_t xBufferLengthBytes,
-                                        size_t xBytesAvailable,
-                                        size_t xBytesToStoreMessageLength )
-{
-    size_t xOriginalTail, xReceivedLength, xNextMessageLength;
-    configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
-
-    if( xBytesToStoreMessageLength != ( size_t ) 0 )
-    {
-        /* A discrete message is being received.  First receive the length
-         * of the message.  A copy of the tail is stored so the buffer can be
-         * returned to its prior state if the length of the message is too
-         * large for the provided buffer. */
-        xOriginalTail = pxStreamBuffer->xTail;
-        ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
-        xNextMessageLength = ( size_t ) xTempNextMessageLength;
-
-        /* Reduce the number of bytes available by the number of bytes just
-         * read out. */
-        xBytesAvailable -= xBytesToStoreMessageLength;
-
-        /* Check there is enough space in the buffer provided by the
-         * user. */
-        if( xNextMessageLength > xBufferLengthBytes )
-        {
-            /* The user has provided insufficient space to read the message
-             * so return the buffer to its previous state (so the length of
-             * the message is in the buffer again). */
-            pxStreamBuffer->xTail = xOriginalTail;
-            xNextMessageLength = 0;
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    else
-    {
-        /* A stream of bytes is being received (as opposed to a discrete
-         * message), so read as many bytes as possible. */
-        xNextMessageLength = xBufferLengthBytes;
-    }
-
-    /* Read the actual data. */
-    xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
-
-    return xReceivedLength;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
-{
-    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-    BaseType_t xReturn;
-    size_t xTail;
-
-    configASSERT( pxStreamBuffer );
-
-    /* True if no bytes are available. */
-    xTail = pxStreamBuffer->xTail;
-
-    if( pxStreamBuffer->xHead == xTail )
-    {
-        xReturn = pdTRUE;
-    }
-    else
-    {
-        xReturn = pdFALSE;
-    }
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
-{
-    BaseType_t xReturn;
-    size_t xBytesToStoreMessageLength;
-    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-
-    configASSERT( pxStreamBuffer );
-
-    /* This generic version of the receive function is used by both message
-     * buffers, which store discrete messages, and stream buffers, which store a
-     * continuous stream of bytes.  Discrete messages include an additional
-     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
-    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-    {
-        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
-    }
-    else
-    {
-        xBytesToStoreMessageLength = 0;
-    }
-
-    /* True if the available space equals zero. */
-    if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
-    {
-        xReturn = pdTRUE;
-    }
-    else
-    {
-        xReturn = pdFALSE;
-    }
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
-                                              BaseType_t * pxHigherPriorityTaskWoken )
-{
-    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-    BaseType_t xReturn;
-    UBaseType_t uxSavedInterruptStatus;
-
-    configASSERT( pxStreamBuffer );
-
-    uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
-    {
-        if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
-        {
-            ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
-                                         ( uint32_t ) 0,
-                                         eNoAction,
-                                         pxHigherPriorityTaskWoken );
-            ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
-            xReturn = pdTRUE;
-        }
-        else
-        {
-            xReturn = pdFALSE;
-        }
-    }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
-                                                 BaseType_t * pxHigherPriorityTaskWoken )
-{
-    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-    BaseType_t xReturn;
-    UBaseType_t uxSavedInterruptStatus;
-
-    configASSERT( pxStreamBuffer );
-
-    uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
-    {
-        if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
-        {
-            ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
-                                         ( uint32_t ) 0,
-                                         eNoAction,
-                                         pxHigherPriorityTaskWoken );
-            ( pxStreamBuffer )->xTaskWaitingToSend = NULL;
-            xReturn = pdTRUE;
-        }
-        else
-        {
-            xReturn = pdFALSE;
-        }
-    }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer,
-                                     const uint8_t * pucData,
-                                     size_t xCount )
-{
-    size_t xNextHead, xFirstLength;
-
-    configASSERT( xCount > ( size_t ) 0 );
-
-    xNextHead = pxStreamBuffer->xHead;
-
-    /* Calculate the number of bytes that can be added in the first write -
-     * which may be less than the total number of bytes that need to be added if
-     * the buffer will wrap back to the beginning. */
-    xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
-
-    /* Write as many bytes as can be written in the first write. */
-    configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
-    ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
-
-    /* If the number of bytes written was less than the number that could be
-     * written in the first write... */
-    if( xCount > xFirstLength )
-    {
-        /* ...then write the remaining bytes to the start of the buffer. */
-        configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
-        ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    xNextHead += xCount;
-
-    if( xNextHead >= pxStreamBuffer->xLength )
-    {
-        xNextHead -= pxStreamBuffer->xLength;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    pxStreamBuffer->xHead = xNextHead;
-
-    return xCount;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer,
-                                      uint8_t * pucData,
-                                      size_t xMaxCount,
-                                      size_t xBytesAvailable )
-{
-    size_t xCount, xFirstLength, xNextTail;
-
-    /* Use the minimum of the wanted bytes and the available bytes. */
-    xCount = configMIN( xBytesAvailable, xMaxCount );
-
-    if( xCount > ( size_t ) 0 )
-    {
-        xNextTail = pxStreamBuffer->xTail;
-
-        /* Calculate the number of bytes that can be read - which may be
-         * less than the number wanted if the data wraps around to the start of
-         * the buffer. */
-        xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
-
-        /* Obtain the number of bytes it is possible to obtain in the first
-         * read.  Asserts check bounds of read and write. */
-        configASSERT( xFirstLength <= xMaxCount );
-        configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
-        ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
-
-        /* If the total number of wanted bytes is greater than the number
-         * that could be read in the first read... */
-        if( xCount > xFirstLength )
-        {
-            /*...then read the remaining bytes from the start of the buffer. */
-            configASSERT( xCount <= xMaxCount );
-            ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        /* Move the tail pointer to effectively remove the data read from
-         * the buffer. */
-        xNextTail += xCount;
-
-        if( xNextTail >= pxStreamBuffer->xLength )
-        {
-            xNextTail -= pxStreamBuffer->xLength;
-        }
-
-        pxStreamBuffer->xTail = xNextTail;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    return xCount;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
-{
-/* Returns the distance between xTail and xHead. */
-    size_t xCount;
-
-    xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
-    xCount -= pxStreamBuffer->xTail;
-
-    if( xCount >= pxStreamBuffer->xLength )
-    {
-        xCount -= pxStreamBuffer->xLength;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    return xCount;
-}
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
-                                          uint8_t * const pucBuffer,
-                                          size_t xBufferSizeBytes,
-                                          size_t xTriggerLevelBytes,
-                                          uint8_t ucFlags )
-{
-    /* Assert here is deliberately writing to the entire buffer to ensure it can
-     * be written to without generating exceptions, and is setting the buffer to a
-     * known value to assist in development/debugging. */
-    #if ( configASSERT_DEFINED == 1 )
-        {
-            /* The value written just has to be identifiable when looking at the
-             * memory.  Don't use 0xA5 as that is the stack fill value and could
-             * result in confusion as to what is actually being observed. */
-            const BaseType_t xWriteValue = 0x55;
-            configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
-        } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
-    #endif
-
-    ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
-    pxStreamBuffer->pucBuffer = pucBuffer;
-    pxStreamBuffer->xLength = xBufferSizeBytes;
-    pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
-    pxStreamBuffer->ucFlags = ucFlags;
-}
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
-    {
-        return xStreamBuffer->uxStreamBufferNumber;
-    }
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,
-                                             UBaseType_t uxStreamBufferNumber )
-    {
-        xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
-    }
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
-    {
-        return( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
-    }
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/tasks.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/tasks.c
deleted file mode 100644
index 37ea996..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/tasks.c
+++ /dev/null
@@ -1,5402 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers.  That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* FreeRTOS includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "timers.h"
-#include "stack_macros.h"
-
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
- * for the header files above, but not in this file, in order to generate the
- * correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
-
-/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
- * functions but without including stdio.h here. */
-#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
-
-/* At the bottom of this file are two optional functions that can be used
- * to generate human readable text from the raw data generated by the
- * uxTaskGetSystemState() function.  Note the formatting functions are provided
- * for convenience only, and are NOT considered part of the kernel. */
-    #include 
-#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
-
-#if ( configUSE_PREEMPTION == 0 )
-
-/* If the cooperative scheduler is being used then a yield should not be
- * performed just because a higher priority task has been woken. */
-    #define taskYIELD_IF_USING_PREEMPTION()
-#else
-    #define taskYIELD_IF_USING_PREEMPTION()    portYIELD_WITHIN_API()
-#endif
-
-/* Values that can be assigned to the ucNotifyState member of the TCB. */
-#define taskNOT_WAITING_NOTIFICATION              ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */
-#define taskWAITING_NOTIFICATION                  ( ( uint8_t ) 1 )
-#define taskNOTIFICATION_RECEIVED                 ( ( uint8_t ) 2 )
-
-/*
- * The value used to fill the stack of a task when the task is created.  This
- * is used purely for checking the high water mark for tasks.
- */
-#define tskSTACK_FILL_BYTE                        ( 0xa5U )
-
-/* Bits used to recored how a task's stack and TCB were allocated. */
-#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB    ( ( uint8_t ) 0 )
-#define tskSTATICALLY_ALLOCATED_STACK_ONLY        ( ( uint8_t ) 1 )
-#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB     ( ( uint8_t ) 2 )
-
-/* If any of the following are set then task stacks are filled with a known
- * value so the high water mark can be determined.  If none of the following are
- * set then don't fill the stack so there is no unnecessary dependency on memset. */
-#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
-    #define tskSET_NEW_STACKS_TO_KNOWN_VALUE    1
-#else
-    #define tskSET_NEW_STACKS_TO_KNOWN_VALUE    0
-#endif
-
-/*
- * Macros used by vListTask to indicate which state a task is in.
- */
-#define tskRUNNING_CHAR      ( 'X' )
-#define tskBLOCKED_CHAR      ( 'B' )
-#define tskREADY_CHAR        ( 'R' )
-#define tskDELETED_CHAR      ( 'D' )
-#define tskSUSPENDED_CHAR    ( 'S' )
-
-/*
- * Some kernel aware debuggers require the data the debugger needs access to be
- * global, rather than file scope.
- */
-#ifdef portREMOVE_STATIC_QUALIFIER
-    #define static
-#endif
-
-/* The name allocated to the Idle task.  This can be overridden by defining
- * configIDLE_TASK_NAME in FreeRTOSConfig.h. */
-#ifndef configIDLE_TASK_NAME
-    #define configIDLE_TASK_NAME    "IDLE"
-#endif
-
-#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
-
-/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
- * performed in a generic way that is not optimised to any particular
- * microcontroller architecture. */
-
-/* uxTopReadyPriority holds the priority of the highest priority ready
- * state task. */
-    #define taskRECORD_READY_PRIORITY( uxPriority ) \
-    {                                               \
-        if( ( uxPriority ) > uxTopReadyPriority )   \
-        {                                           \
-            uxTopReadyPriority = ( uxPriority );    \
-        }                                           \
-    } /* taskRECORD_READY_PRIORITY */
-
-/*-----------------------------------------------------------*/
-
-    #define taskSELECT_HIGHEST_PRIORITY_TASK()                                \
-    {                                                                         \
-        UBaseType_t uxTopPriority = uxTopReadyPriority;                       \
-                                                                              \
-        /* Find the highest priority queue that contains ready tasks. */      \
-        while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) ) \
-        {                                                                     \
-            configASSERT( uxTopPriority );                                    \
-            --uxTopPriority;                                                  \
-        }                                                                     \
-                                                                              \
-        /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \
-         * the  same priority get an equal share of the processor time. */                    \
-        listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \
-        uxTopReadyPriority = uxTopPriority;                                                   \
-    } /* taskSELECT_HIGHEST_PRIORITY_TASK */
-
-/*-----------------------------------------------------------*/
-
-/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
- * they are only required when a port optimised method of task selection is
- * being used. */
-    #define taskRESET_READY_PRIORITY( uxPriority )
-    #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
-
-#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
- * performed in a way that is tailored to the particular microcontroller
- * architecture being used. */
-
-/* A port optimised version is provided.  Call the port defined macros. */
-    #define taskRECORD_READY_PRIORITY( uxPriority )    portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
-
-/*-----------------------------------------------------------*/
-
-    #define taskSELECT_HIGHEST_PRIORITY_TASK()                                                  \
-    {                                                                                           \
-        UBaseType_t uxTopPriority;                                                              \
-                                                                                                \
-        /* Find the highest priority list that contains ready tasks. */                         \
-        portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );                          \
-        configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \
-        listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );   \
-    } /* taskSELECT_HIGHEST_PRIORITY_TASK() */
-
-/*-----------------------------------------------------------*/
-
-/* A port optimised version is provided, call it only if the TCB being reset
- * is being referenced from a ready list.  If it is referenced from a delayed
- * or suspended list then it won't be in a ready list. */
-    #define taskRESET_READY_PRIORITY( uxPriority )                                                     \
-    {                                                                                                  \
-        if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \
-        {                                                                                              \
-            portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );                        \
-        }                                                                                              \
-    }
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
- * count overflows. */
-#define taskSWITCH_DELAYED_LISTS()                                                \
-    {                                                                             \
-        List_t * pxTemp;                                                          \
-                                                                                  \
-        /* The delayed tasks list should be empty when the lists are switched. */ \
-        configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );               \
-                                                                                  \
-        pxTemp = pxDelayedTaskList;                                               \
-        pxDelayedTaskList = pxOverflowDelayedTaskList;                            \
-        pxOverflowDelayedTaskList = pxTemp;                                       \
-        xNumOfOverflows++;                                                        \
-        prvResetNextTaskUnblockTime();                                            \
-    }
-
-/*-----------------------------------------------------------*/
-
-/*
- * Place the task represented by pxTCB into the appropriate ready list for
- * the task.  It is inserted at the end of the list.
- */
-#define prvAddTaskToReadyList( pxTCB )                                                                 \
-    traceMOVED_TASK_TO_READY_STATE( pxTCB );                                                           \
-    taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );                                                \
-    vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
-    tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
-/*-----------------------------------------------------------*/
-
-/*
- * Several functions take an TaskHandle_t parameter that can optionally be NULL,
- * where NULL is used to indicate that the handle of the currently executing
- * task should be used in place of the parameter.  This macro simply checks to
- * see if the parameter is NULL and returns a pointer to the appropriate TCB.
- */
-#define prvGetTCBFromHandle( pxHandle )    ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
-
-/* The item value of the event list item is normally used to hold the priority
- * of the task to which it belongs (coded to allow it to be held in reverse
- * priority order).  However, it is occasionally borrowed for other purposes.  It
- * is important its value is not updated due to a task priority change while it is
- * being used for another purpose.  The following bit definition is used to inform
- * the scheduler that the value should not be changed - in which case it is the
- * responsibility of whichever module is using the value to ensure it gets set back
- * to its original value when it is released. */
-#if ( configUSE_16_BIT_TICKS == 1 )
-    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    0x8000U
-#else
-    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    0x80000000UL
-#endif
-
-/*
- * Task control block.  A task control block (TCB) is allocated for each task,
- * and stores task state information, including a pointer to the task's context
- * (the task's run time environment, including register values)
- */
-typedef struct tskTaskControlBlock       /* The old naming convention is used to prevent breaking kernel aware debuggers. */
-{
-    volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
-
-    #if ( portUSING_MPU_WRAPPERS == 1 )
-        xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
-    #endif
-
-    ListItem_t xStateListItem;                  /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
-    ListItem_t xEventListItem;                  /*< Used to reference a task from an event list. */
-    UBaseType_t uxPriority;                     /*< The priority of the task.  0 is the lowest priority. */
-    StackType_t * pxStack;                      /*< Points to the start of the stack. */
-    char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-    #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
-        StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */
-    #endif
-
-    #if ( portCRITICAL_NESTING_IN_TCB == 1 )
-        UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
-    #endif
-
-    #if ( configUSE_TRACE_FACILITY == 1 )
-        UBaseType_t uxTCBNumber;  /*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
-        UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */
-    #endif
-
-    #if ( configUSE_MUTEXES == 1 )
-        UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */
-        UBaseType_t uxMutexesHeld;
-    #endif
-
-    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
-        TaskHookFunction_t pxTaskTag;
-    #endif
-
-    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
-        void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
-    #endif
-
-    #if ( configGENERATE_RUN_TIME_STATS == 1 )
-        uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */
-    #endif
-
-    #if ( configUSE_NEWLIB_REENTRANT == 1 )
-
-        /* Allocate a Newlib reent structure that is specific to this task.
-         * Note Newlib support has been included by popular demand, but is not
-         * used by the FreeRTOS maintainers themselves.  FreeRTOS is not
-         * responsible for resulting newlib operation.  User must be familiar with
-         * newlib and must provide system-wide implementations of the necessary
-         * stubs. Be warned that (at the time of writing) the current newlib design
-         * implements a system-wide malloc() that must be provided with locks.
-         *
-         * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
-         * for additional information. */
-        struct  _reent xNewLib_reent;
-    #endif
-
-    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
-        volatile uint32_t ulNotifiedValue[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
-        volatile uint8_t ucNotifyState[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
-    #endif
-
-    /* See the comments in FreeRTOS.h with the definition of
-     * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
-    #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
-        uint8_t ucStaticallyAllocated;                     /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
-    #endif
-
-    #if ( INCLUDE_xTaskAbortDelay == 1 )
-        uint8_t ucDelayAborted;
-    #endif
-
-    #if ( configUSE_POSIX_ERRNO == 1 )
-        int iTaskErrno;
-    #endif
-} tskTCB;
-
-/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
- * below to enable the use of older kernel aware debuggers. */
-typedef tskTCB TCB_t;
-
-/*lint -save -e956 A manual analysis and inspection has been used to determine
- * which static variables must be declared volatile. */
-PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
-
-/* Lists for ready and blocked tasks. --------------------
- * xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
- * doing so breaks some kernel aware debuggers and debuggers that rely on removing
- * the static qualifier. */
-PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */
-PRIVILEGED_DATA static List_t xDelayedTaskList1;                         /*< Delayed tasks. */
-PRIVILEGED_DATA static List_t xDelayedTaskList2;                         /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
-PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;              /*< Points to the delayed task list currently being used. */
-PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;      /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
-PRIVILEGED_DATA static List_t xPendingReadyList;                         /*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
-
-#if ( INCLUDE_vTaskDelete == 1 )
-
-    PRIVILEGED_DATA static List_t xTasksWaitingTermination; /*< Tasks that have been deleted - but their memory not yet freed. */
-    PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
-
-#endif
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-    PRIVILEGED_DATA static List_t xSuspendedTaskList; /*< Tasks that are currently suspended. */
-
-#endif
-
-/* Global POSIX errno. Its value is changed upon context switching to match
- * the errno of the currently running task. */
-#if ( configUSE_POSIX_ERRNO == 1 )
-    int FreeRTOS_errno = 0;
-#endif
-
-/* Other file private variables. --------------------------------*/
-PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U;
-PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
-PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY;
-PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE;
-PRIVILEGED_DATA static volatile TickType_t xPendedTicks = ( TickType_t ) 0U;
-PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE;
-PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0;
-PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U;
-PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
-PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL;                          /*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
-
-/* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists.
- * For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority
- * to determine the number of priority lists to read back from the remote target. */
-const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U;
-
-/* Context switches are held pending while the scheduler is suspended.  Also,
- * interrupts must not manipulate the xStateListItem of a TCB, or any of the
- * lists the xStateListItem can be referenced from, if the scheduler is suspended.
- * If an interrupt needs to unblock a task while the scheduler is suspended then it
- * moves the task's event list item into the xPendingReadyList, ready for the
- * kernel to move the task from the pending ready list into the real ready list
- * when the scheduler is unsuspended.  The pending ready list itself can only be
- * accessed from a critical section. */
-PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) pdFALSE;
-
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
-
-/* Do not move these variables to function scope as doing so prevents the
- * code working with debuggers that need to remove the static qualifier. */
-    PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;    /*< Holds the value of a timer/counter the last time a task was switched in. */
-    PRIVILEGED_DATA static volatile uint32_t ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */
-
-#endif
-
-/*lint -restore */
-
-/*-----------------------------------------------------------*/
-
-/* File private functions. --------------------------------*/
-
-/**
- * Utility task that simply returns pdTRUE if the task referenced by xTask is
- * currently in the Suspended state, or pdFALSE if the task referenced by xTask
- * is in any other state.
- */
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-    static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-#endif /* INCLUDE_vTaskSuspend */
-
-/*
- * Utility to ready all the lists used by the scheduler.  This is called
- * automatically upon the creation of the first task.
- */
-static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
-
-/*
- * The idle task, which as all tasks is implemented as a never ending loop.
- * The idle task is automatically created and added to the ready lists upon
- * creation of the first user task.
- *
- * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
- * language extensions.  The equivalent prototype for this function is:
- *
- * void prvIdleTask( void *pvParameters );
- *
- */
-static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ) PRIVILEGED_FUNCTION;
-
-/*
- * Utility to free all memory allocated by the scheduler to hold a TCB,
- * including the stack pointed to by the TCB.
- *
- * This does not free memory allocated by the task itself (i.e. memory
- * allocated by calls to pvPortMalloc from within the tasks application code).
- */
-#if ( INCLUDE_vTaskDelete == 1 )
-
-    static void prvDeleteTCB( TCB_t * pxTCB ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Used only by the idle task.  This checks to see if anything has been placed
- * in the list of tasks waiting to be deleted.  If so the task is cleaned up
- * and its TCB deleted.
- */
-static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
-
-/*
- * The currently executing task is entering the Blocked state.  Add the task to
- * either the current or the overflow delayed task list.
- */
-static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
-                                            const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
-
-/*
- * Fills an TaskStatus_t structure with information on each task that is
- * referenced from the pxList list (which may be a ready list, a delayed list,
- * a suspended list, etc.).
- *
- * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
- * NORMAL APPLICATION CODE.
- */
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray,
-                                                     List_t * pxList,
-                                                     eTaskState eState ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Searches pxList for a task with name pcNameToQuery - returning a handle to
- * the task if it is found, or NULL if the task is not found.
- */
-#if ( INCLUDE_xTaskGetHandle == 1 )
-
-    static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
-                                                     const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * When a task is created, the stack of the task is filled with a known value.
- * This function determines the 'high water mark' of the task stack by
- * determining how much of the stack remains at the original preset value.
- */
-#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
-
-    static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Return the amount of time, in ticks, that will pass before the kernel will
- * next move a task from the Blocked state to the Running state.
- *
- * This conditional compilation should use inequality to 0, not equality to 1.
- * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
- * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
- * set to a value other than 1.
- */
-#if ( configUSE_TICKLESS_IDLE != 0 )
-
-    static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Set xNextTaskUnblockTime to the time at which the next Blocked state task
- * will exit the Blocked state.
- */
-static void prvResetNextTaskUnblockTime( void ) PRIVILEGED_FUNCTION;
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
-
-/*
- * Helper function used to pad task names with spaces when printing out
- * human readable tables of task information.
- */
-    static char * prvWriteNameToBuffer( char * pcBuffer,
-                                        const char * pcTaskName ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Called after a Task_t structure has been allocated either statically or
- * dynamically to fill in the structure's members.
- */
-static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
-                                  const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                                  const uint32_t ulStackDepth,
-                                  void * const pvParameters,
-                                  UBaseType_t uxPriority,
-                                  TaskHandle_t * const pxCreatedTask,
-                                  TCB_t * pxNewTCB,
-                                  const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
-
-/*
- * Called after a new task has been created and initialised to place the task
- * under the control of the scheduler.
- */
-static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
-
-/*
- * freertos_tasks_c_additions_init() should only be called if the user definable
- * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
- * called by the function.
- */
-#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
-
-    static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-    TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
-                                    const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                                    const uint32_t ulStackDepth,
-                                    void * const pvParameters,
-                                    UBaseType_t uxPriority,
-                                    StackType_t * const puxStackBuffer,
-                                    StaticTask_t * const pxTaskBuffer )
-    {
-        TCB_t * pxNewTCB;
-        TaskHandle_t xReturn;
-
-        configASSERT( puxStackBuffer != NULL );
-        configASSERT( pxTaskBuffer != NULL );
-
-        #if ( configASSERT_DEFINED == 1 )
-            {
-                /* Sanity check that the size of the structure used to declare a
-                 * variable of type StaticTask_t equals the size of the real task
-                 * structure. */
-                volatile size_t xSize = sizeof( StaticTask_t );
-                configASSERT( xSize == sizeof( TCB_t ) );
-                ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
-            }
-        #endif /* configASSERT_DEFINED */
-
-        if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
-        {
-            /* The memory used for the task's TCB and stack are passed into this
-             * function - use them. */
-            pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
-            pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
-
-            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
-                {
-                    /* Tasks can be created statically or dynamically, so note this
-                     * task was created statically in case the task is later deleted. */
-                    pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
-                }
-            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
-
-            prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
-            prvAddNewTaskToReadyList( pxNewTCB );
-        }
-        else
-        {
-            xReturn = NULL;
-        }
-
-        return xReturn;
-    }
-
-#endif /* SUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
-    BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
-                                            TaskHandle_t * pxCreatedTask )
-    {
-        TCB_t * pxNewTCB;
-        BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
-
-        configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
-        configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
-
-        if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
-        {
-            /* Allocate space for the TCB.  Where the memory comes from depends
-             * on the implementation of the port malloc function and whether or
-             * not static allocation is being used. */
-            pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
-
-            /* Store the stack location in the TCB. */
-            pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
-
-            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
-                {
-                    /* Tasks can be created statically or dynamically, so note this
-                     * task was created statically in case the task is later deleted. */
-                    pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
-                }
-            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
-
-            prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
-                                  pxTaskDefinition->pcName,
-                                  ( uint32_t ) pxTaskDefinition->usStackDepth,
-                                  pxTaskDefinition->pvParameters,
-                                  pxTaskDefinition->uxPriority,
-                                  pxCreatedTask, pxNewTCB,
-                                  pxTaskDefinition->xRegions );
-
-            prvAddNewTaskToReadyList( pxNewTCB );
-            xReturn = pdPASS;
-        }
-
-        return xReturn;
-    }
-
-#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-    BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
-                                      TaskHandle_t * pxCreatedTask )
-    {
-        TCB_t * pxNewTCB;
-        BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
-
-        configASSERT( pxTaskDefinition->puxStackBuffer );
-
-        if( pxTaskDefinition->puxStackBuffer != NULL )
-        {
-            /* Allocate space for the TCB.  Where the memory comes from depends
-             * on the implementation of the port malloc function and whether or
-             * not static allocation is being used. */
-            pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
-
-            if( pxNewTCB != NULL )
-            {
-                /* Store the stack location in the TCB. */
-                pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
-
-                #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
-                    {
-                        /* Tasks can be created statically or dynamically, so note
-                         * this task had a statically allocated stack in case it is
-                         * later deleted.  The TCB was allocated dynamically. */
-                        pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
-                    }
-                #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
-
-                prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
-                                      pxTaskDefinition->pcName,
-                                      ( uint32_t ) pxTaskDefinition->usStackDepth,
-                                      pxTaskDefinition->pvParameters,
-                                      pxTaskDefinition->uxPriority,
-                                      pxCreatedTask, pxNewTCB,
-                                      pxTaskDefinition->xRegions );
-
-                prvAddNewTaskToReadyList( pxNewTCB );
-                xReturn = pdPASS;
-            }
-        }
-
-        return xReturn;
-    }
-
-#endif /* portUSING_MPU_WRAPPERS */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-    BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
-                            const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                            const configSTACK_DEPTH_TYPE usStackDepth,
-                            void * const pvParameters,
-                            UBaseType_t uxPriority,
-                            TaskHandle_t * const pxCreatedTask )
-    {
-        TCB_t * pxNewTCB;
-        BaseType_t xReturn;
-
-        /* If the stack grows down then allocate the stack then the TCB so the stack
-         * does not grow into the TCB.  Likewise if the stack grows up then allocate
-         * the TCB then the stack. */
-        #if ( portSTACK_GROWTH > 0 )
-            {
-                /* Allocate space for the TCB.  Where the memory comes from depends on
-                 * the implementation of the port malloc function and whether or not static
-                 * allocation is being used. */
-                pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
-
-                if( pxNewTCB != NULL )
-                {
-                    /* Allocate space for the stack used by the task being created.
-                     * The base of the stack memory stored in the TCB so the task can
-                     * be deleted later if required. */
-                    pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
-                    if( pxNewTCB->pxStack == NULL )
-                    {
-                        /* Could not allocate the stack.  Delete the allocated TCB. */
-                        vPortFree( pxNewTCB );
-                        pxNewTCB = NULL;
-                    }
-                }
-            }
-        #else /* portSTACK_GROWTH */
-            {
-                StackType_t * pxStack;
-
-                /* Allocate space for the stack used by the task being created. */
-                pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
-
-                if( pxStack != NULL )
-                {
-                    /* Allocate space for the TCB. */
-                    pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
-
-                    if( pxNewTCB != NULL )
-                    {
-                        /* Store the stack location in the TCB. */
-                        pxNewTCB->pxStack = pxStack;
-                    }
-                    else
-                    {
-                        /* The stack cannot be used as the TCB was not created.  Free
-                         * it again. */
-                        vPortFree( pxStack );
-                    }
-                }
-                else
-                {
-                    pxNewTCB = NULL;
-                }
-            }
-        #endif /* portSTACK_GROWTH */
-
-        if( pxNewTCB != NULL )
-        {
-            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
-                {
-                    /* Tasks can be created statically or dynamically, so note this
-                     * task was created dynamically in case it is later deleted. */
-                    pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
-                }
-            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
-
-            prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
-            prvAddNewTaskToReadyList( pxNewTCB );
-            xReturn = pdPASS;
-        }
-        else
-        {
-            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
-        }
-
-        return xReturn;
-    }
-
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
-                                  const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                                  const uint32_t ulStackDepth,
-                                  void * const pvParameters,
-                                  UBaseType_t uxPriority,
-                                  TaskHandle_t * const pxCreatedTask,
-                                  TCB_t * pxNewTCB,
-                                  const MemoryRegion_t * const xRegions )
-{
-    StackType_t * pxTopOfStack;
-    UBaseType_t x;
-
-    #if ( portUSING_MPU_WRAPPERS == 1 )
-        /* Should the task be created in privileged mode? */
-        BaseType_t xRunPrivileged;
-
-        if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
-        {
-            xRunPrivileged = pdTRUE;
-        }
-        else
-        {
-            xRunPrivileged = pdFALSE;
-        }
-        uxPriority &= ~portPRIVILEGE_BIT;
-    #endif /* portUSING_MPU_WRAPPERS == 1 */
-
-    /* Avoid dependency on memset() if it is not required. */
-    #if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
-        {
-            /* Fill the stack with a known value to assist debugging. */
-            ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
-        }
-    #endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
-
-    /* Calculate the top of stack address.  This depends on whether the stack
-     * grows from high memory to low (as per the 80x86) or vice versa.
-     * portSTACK_GROWTH is used to make the result positive or negative as required
-     * by the port. */
-    #if ( portSTACK_GROWTH < 0 )
-        {
-            pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
-            pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
-
-            /* Check the alignment of the calculated top of stack is correct. */
-            configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
-
-            #if ( configRECORD_STACK_HIGH_ADDRESS == 1 )
-                {
-                    /* Also record the stack's high address, which may assist
-                     * debugging. */
-                    pxNewTCB->pxEndOfStack = pxTopOfStack;
-                }
-            #endif /* configRECORD_STACK_HIGH_ADDRESS */
-        }
-    #else /* portSTACK_GROWTH */
-        {
-            pxTopOfStack = pxNewTCB->pxStack;
-
-            /* Check the alignment of the stack buffer is correct. */
-            configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
-
-            /* The other extreme of the stack space is required if stack checking is
-             * performed. */
-            pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
-        }
-    #endif /* portSTACK_GROWTH */
-
-    /* Store the task name in the TCB. */
-    if( pcName != NULL )
-    {
-        for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
-        {
-            pxNewTCB->pcTaskName[ x ] = pcName[ x ];
-
-            /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
-             * configMAX_TASK_NAME_LEN characters just in case the memory after the
-             * string is not accessible (extremely unlikely). */
-            if( pcName[ x ] == ( char ) 0x00 )
-            {
-                break;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-
-        /* Ensure the name string is terminated in the case that the string length
-         * was greater or equal to configMAX_TASK_NAME_LEN. */
-        pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
-    }
-    else
-    {
-        /* The task has not been given a name, so just ensure there is a NULL
-         * terminator when it is read out. */
-        pxNewTCB->pcTaskName[ 0 ] = 0x00;
-    }
-
-    /* This is used as an array index so must ensure it's not too large.  First
-     * remove the privilege bit if one is present. */
-    if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
-    {
-        uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    pxNewTCB->uxPriority = uxPriority;
-    #if ( configUSE_MUTEXES == 1 )
-        {
-            pxNewTCB->uxBasePriority = uxPriority;
-            pxNewTCB->uxMutexesHeld = 0;
-        }
-    #endif /* configUSE_MUTEXES */
-
-    vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
-    vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
-
-    /* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
-     * back to  the containing TCB from a generic item in a list. */
-    listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
-
-    /* Event lists are always in priority order. */
-    listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-    listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
-
-    #if ( portCRITICAL_NESTING_IN_TCB == 1 )
-        {
-            pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
-        }
-    #endif /* portCRITICAL_NESTING_IN_TCB */
-
-    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
-        {
-            pxNewTCB->pxTaskTag = NULL;
-        }
-    #endif /* configUSE_APPLICATION_TASK_TAG */
-
-    #if ( configGENERATE_RUN_TIME_STATS == 1 )
-        {
-            pxNewTCB->ulRunTimeCounter = 0UL;
-        }
-    #endif /* configGENERATE_RUN_TIME_STATS */
-
-    #if ( portUSING_MPU_WRAPPERS == 1 )
-        {
-            vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
-        }
-    #else
-        {
-            /* Avoid compiler warning about unreferenced parameter. */
-            ( void ) xRegions;
-        }
-    #endif
-
-    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-        {
-            memset( ( void * ) &( pxNewTCB->pvThreadLocalStoragePointers[ 0 ] ), 0x00, sizeof( pxNewTCB->pvThreadLocalStoragePointers ) );
-        }
-    #endif
-
-    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
-        {
-            memset( ( void * ) &( pxNewTCB->ulNotifiedValue[ 0 ] ), 0x00, sizeof( pxNewTCB->ulNotifiedValue ) );
-            memset( ( void * ) &( pxNewTCB->ucNotifyState[ 0 ] ), 0x00, sizeof( pxNewTCB->ucNotifyState ) );
-        }
-    #endif
-
-    #if ( configUSE_NEWLIB_REENTRANT == 1 )
-        {
-            /* Initialise this task's Newlib reent structure.
-             * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
-             * for additional information. */
-            _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
-        }
-    #endif
-
-    #if ( INCLUDE_xTaskAbortDelay == 1 )
-        {
-            pxNewTCB->ucDelayAborted = pdFALSE;
-        }
-    #endif
-
-    /* Initialize the TCB stack to look as if the task was already running,
-     * but had been interrupted by the scheduler.  The return address is set
-     * to the start of the task function. Once the stack has been initialised
-     * the top of stack variable is updated. */
-    #if ( portUSING_MPU_WRAPPERS == 1 )
-        {
-            /* If the port has capability to detect stack overflow,
-             * pass the stack end address to the stack initialization
-             * function as well. */
-            #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-                {
-                    #if ( portSTACK_GROWTH < 0 )
-                        {
-                            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
-                        }
-                    #else /* portSTACK_GROWTH */
-                        {
-                            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
-                        }
-                    #endif /* portSTACK_GROWTH */
-                }
-            #else /* portHAS_STACK_OVERFLOW_CHECKING */
-                {
-                    pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
-                }
-            #endif /* portHAS_STACK_OVERFLOW_CHECKING */
-        }
-    #else /* portUSING_MPU_WRAPPERS */
-        {
-            /* If the port has capability to detect stack overflow,
-             * pass the stack end address to the stack initialization
-             * function as well. */
-            #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-                {
-                    #if ( portSTACK_GROWTH < 0 )
-                        {
-                            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
-                        }
-                    #else /* portSTACK_GROWTH */
-                        {
-                            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
-                        }
-                    #endif /* portSTACK_GROWTH */
-                }
-            #else /* portHAS_STACK_OVERFLOW_CHECKING */
-                {
-                    pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
-                }
-            #endif /* portHAS_STACK_OVERFLOW_CHECKING */
-        }
-    #endif /* portUSING_MPU_WRAPPERS */
-
-    if( pxCreatedTask != NULL )
-    {
-        /* Pass the handle out in an anonymous way.  The handle can be used to
-         * change the created task's priority, delete the created task, etc.*/
-        *pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-}
-/*-----------------------------------------------------------*/
-
-static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
-{
-    /* Ensure interrupts don't access the task lists while the lists are being
-     * updated. */
-    taskENTER_CRITICAL();
-    {
-        uxCurrentNumberOfTasks++;
-
-        if( pxCurrentTCB == NULL )
-        {
-            /* There are no other tasks, or all the other tasks are in
-             * the suspended state - make this the current task. */
-            pxCurrentTCB = pxNewTCB;
-
-            if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
-            {
-                /* This is the first task to be created so do the preliminary
-                 * initialisation required.  We will not recover if this call
-                 * fails, but we will report the failure. */
-                prvInitialiseTaskLists();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            /* If the scheduler is not already running, make this task the
-             * current task if it is the highest priority task to be created
-             * so far. */
-            if( xSchedulerRunning == pdFALSE )
-            {
-                if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
-                {
-                    pxCurrentTCB = pxNewTCB;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-
-        uxTaskNumber++;
-
-        #if ( configUSE_TRACE_FACILITY == 1 )
-            {
-                /* Add a counter into the TCB for tracing only. */
-                pxNewTCB->uxTCBNumber = uxTaskNumber;
-            }
-        #endif /* configUSE_TRACE_FACILITY */
-        traceTASK_CREATE( pxNewTCB );
-
-        prvAddTaskToReadyList( pxNewTCB );
-
-        portSETUP_TCB( pxNewTCB );
-    }
-    taskEXIT_CRITICAL();
-
-    if( xSchedulerRunning != pdFALSE )
-    {
-        /* If the created task is of a higher priority than the current task
-         * then it should run now. */
-        if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
-        {
-            taskYIELD_IF_USING_PREEMPTION();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelete == 1 )
-
-    void vTaskDelete( TaskHandle_t xTaskToDelete )
-    {
-        TCB_t * pxTCB;
-
-        taskENTER_CRITICAL();
-        {
-            /* If null is passed in here then it is the calling task that is
-             * being deleted. */
-            pxTCB = prvGetTCBFromHandle( xTaskToDelete );
-
-            /* Remove task from the ready/delayed list. */
-            if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-            {
-                taskRESET_READY_PRIORITY( pxTCB->uxPriority );
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            /* Is the task waiting on an event also? */
-            if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-            {
-                ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            /* Increment the uxTaskNumber also so kernel aware debuggers can
-             * detect that the task lists need re-generating.  This is done before
-             * portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
-             * not return. */
-            uxTaskNumber++;
-
-            if( pxTCB == pxCurrentTCB )
-            {
-                /* A task is deleting itself.  This cannot complete within the
-                 * task itself, as a context switch to another task is required.
-                 * Place the task in the termination list.  The idle task will
-                 * check the termination list and free up any memory allocated by
-                 * the scheduler for the TCB and stack of the deleted task. */
-                vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
-
-                /* Increment the ucTasksDeleted variable so the idle task knows
-                 * there is a task that has been deleted and that it should therefore
-                 * check the xTasksWaitingTermination list. */
-                ++uxDeletedTasksWaitingCleanUp;
-
-                /* Call the delete hook before portPRE_TASK_DELETE_HOOK() as
-                 * portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */
-                traceTASK_DELETE( pxTCB );
-
-                /* The pre-delete hook is primarily for the Windows simulator,
-                 * in which Windows specific clean up operations are performed,
-                 * after which it is not possible to yield away from this task -
-                 * hence xYieldPending is used to latch that a context switch is
-                 * required. */
-                portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
-            }
-            else
-            {
-                --uxCurrentNumberOfTasks;
-                traceTASK_DELETE( pxTCB );
-
-                /* Reset the next expected unblock time in case it referred to
-                 * the task that has just been deleted. */
-                prvResetNextTaskUnblockTime();
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        /* If the task is not deleting itself, call prvDeleteTCB from outside of
-         * critical section. If a task deletes itself, prvDeleteTCB is called
-         * from prvCheckTasksWaitingTermination which is called from Idle task. */
-        if( pxTCB != pxCurrentTCB )
-        {
-            prvDeleteTCB( pxTCB );
-        }
-
-        /* Force a reschedule if it is the currently running task that has just
-         * been deleted. */
-        if( xSchedulerRunning != pdFALSE )
-        {
-            if( pxTCB == pxCurrentTCB )
-            {
-                configASSERT( uxSchedulerSuspended == 0 );
-                portYIELD_WITHIN_API();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-    }
-
-#endif /* INCLUDE_vTaskDelete */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskDelayUntil == 1 )
-
-    BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement )
-    {
-        TickType_t xTimeToWake;
-        BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
-
-        configASSERT( pxPreviousWakeTime );
-        configASSERT( ( xTimeIncrement > 0U ) );
-        configASSERT( uxSchedulerSuspended == 0 );
-
-        vTaskSuspendAll();
-        {
-            /* Minor optimisation.  The tick count cannot change in this
-             * block. */
-            const TickType_t xConstTickCount = xTickCount;
-
-            /* Generate the tick time at which the task wants to wake. */
-            xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
-
-            if( xConstTickCount < *pxPreviousWakeTime )
-            {
-                /* The tick count has overflowed since this function was
-                 * lasted called.  In this case the only time we should ever
-                 * actually delay is if the wake time has also  overflowed,
-                 * and the wake time is greater than the tick time.  When this
-                 * is the case it is as if neither time had overflowed. */
-                if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
-                {
-                    xShouldDelay = pdTRUE;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                /* The tick time has not overflowed.  In this case we will
-                 * delay if either the wake time has overflowed, and/or the
-                 * tick time is less than the wake time. */
-                if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
-                {
-                    xShouldDelay = pdTRUE;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-
-            /* Update the wake time ready for the next call. */
-            *pxPreviousWakeTime = xTimeToWake;
-
-            if( xShouldDelay != pdFALSE )
-            {
-                traceTASK_DELAY_UNTIL( xTimeToWake );
-
-                /* prvAddCurrentTaskToDelayedList() needs the block time, not
-                 * the time to wake, so subtract the current tick count. */
-                prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        xAlreadyYielded = xTaskResumeAll();
-
-        /* Force a reschedule if xTaskResumeAll has not already done so, we may
-         * have put ourselves to sleep. */
-        if( xAlreadyYielded == pdFALSE )
-        {
-            portYIELD_WITHIN_API();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        return xShouldDelay;
-    }
-
-#endif /* INCLUDE_xTaskDelayUntil */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelay == 1 )
-
-    void vTaskDelay( const TickType_t xTicksToDelay )
-    {
-        BaseType_t xAlreadyYielded = pdFALSE;
-
-        /* A delay time of zero just forces a reschedule. */
-        if( xTicksToDelay > ( TickType_t ) 0U )
-        {
-            configASSERT( uxSchedulerSuspended == 0 );
-            vTaskSuspendAll();
-            {
-                traceTASK_DELAY();
-
-                /* A task that is removed from the event list while the
-                 * scheduler is suspended will not get placed in the ready
-                 * list or removed from the blocked list until the scheduler
-                 * is resumed.
-                 *
-                 * This task cannot be in an event list as it is the currently
-                 * executing task. */
-                prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
-            }
-            xAlreadyYielded = xTaskResumeAll();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        /* Force a reschedule if xTaskResumeAll has not already done so, we may
-         * have put ourselves to sleep. */
-        if( xAlreadyYielded == pdFALSE )
-        {
-            portYIELD_WITHIN_API();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-
-#endif /* INCLUDE_vTaskDelay */
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
-
-    eTaskState eTaskGetState( TaskHandle_t xTask )
-    {
-        eTaskState eReturn;
-        List_t const * pxStateList, * pxDelayedList, * pxOverflowedDelayedList;
-        const TCB_t * const pxTCB = xTask;
-
-        configASSERT( pxTCB );
-
-        if( pxTCB == pxCurrentTCB )
-        {
-            /* The task calling this function is querying its own state. */
-            eReturn = eRunning;
-        }
-        else
-        {
-            taskENTER_CRITICAL();
-            {
-                pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
-                pxDelayedList = pxDelayedTaskList;
-                pxOverflowedDelayedList = pxOverflowDelayedTaskList;
-            }
-            taskEXIT_CRITICAL();
-
-            if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
-            {
-                /* The task being queried is referenced from one of the Blocked
-                 * lists. */
-                eReturn = eBlocked;
-            }
-
-            #if ( INCLUDE_vTaskSuspend == 1 )
-                else if( pxStateList == &xSuspendedTaskList )
-                {
-                    /* The task being queried is referenced from the suspended
-                     * list.  Is it genuinely suspended or is it blocked
-                     * indefinitely? */
-                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
-                    {
-                        #if ( configUSE_TASK_NOTIFICATIONS == 1 )
-                            {
-                                BaseType_t x;
-
-                                /* The task does not appear on the event list item of
-                                 * and of the RTOS objects, but could still be in the
-                                 * blocked state if it is waiting on its notification
-                                 * rather than waiting on an object.  If not, is
-                                 * suspended. */
-                                eReturn = eSuspended;
-
-                                for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
-                                {
-                                    if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
-                                    {
-                                        eReturn = eBlocked;
-                                        break;
-                                    }
-                                }
-                            }
-                        #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
-                            {
-                                eReturn = eSuspended;
-                            }
-                        #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
-                    }
-                    else
-                    {
-                        eReturn = eBlocked;
-                    }
-                }
-            #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
-
-            #if ( INCLUDE_vTaskDelete == 1 )
-                else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
-                {
-                    /* The task being queried is referenced from the deleted
-                     * tasks list, or it is not referenced from any lists at
-                     * all. */
-                    eReturn = eDeleted;
-                }
-            #endif
-
-            else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
-            {
-                /* If the task is not in any other state, it must be in the
-                 * Ready (including pending ready) state. */
-                eReturn = eReady;
-            }
-        }
-
-        return eReturn;
-    } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
-
-#endif /* INCLUDE_eTaskGetState */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
-
-    UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
-    {
-        TCB_t const * pxTCB;
-        UBaseType_t uxReturn;
-
-        taskENTER_CRITICAL();
-        {
-            /* If null is passed in here then it is the priority of the task
-             * that called uxTaskPriorityGet() that is being queried. */
-            pxTCB = prvGetTCBFromHandle( xTask );
-            uxReturn = pxTCB->uxPriority;
-        }
-        taskEXIT_CRITICAL();
-
-        return uxReturn;
-    }
-
-#endif /* INCLUDE_uxTaskPriorityGet */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
-
-    UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
-    {
-        TCB_t const * pxTCB;
-        UBaseType_t uxReturn, uxSavedInterruptState;
-
-        /* RTOS ports that support interrupt nesting have the concept of a
-         * maximum  system call (or maximum API call) interrupt priority.
-         * Interrupts that are  above the maximum system call priority are keep
-         * permanently enabled, even when the RTOS kernel is in a critical section,
-         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
-         * is defined in FreeRTOSConfig.h then
-         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-         * failure if a FreeRTOS API function is called from an interrupt that has
-         * been assigned a priority above the configured maximum system call
-         * priority.  Only FreeRTOS functions that end in FromISR can be called
-         * from interrupts  that have been assigned a priority at or (logically)
-         * below the maximum system call interrupt priority.  FreeRTOS maintains a
-         * separate interrupt safe API to ensure interrupt entry is as fast and as
-         * simple as possible.  More information (albeit Cortex-M specific) is
-         * provided on the following link:
-         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-        uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
-        {
-            /* If null is passed in here then it is the priority of the calling
-             * task that is being queried. */
-            pxTCB = prvGetTCBFromHandle( xTask );
-            uxReturn = pxTCB->uxPriority;
-        }
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
-
-        return uxReturn;
-    }
-
-#endif /* INCLUDE_uxTaskPriorityGet */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskPrioritySet == 1 )
-
-    void vTaskPrioritySet( TaskHandle_t xTask,
-                           UBaseType_t uxNewPriority )
-    {
-        TCB_t * pxTCB;
-        UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
-        BaseType_t xYieldRequired = pdFALSE;
-
-        configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
-
-        /* Ensure the new priority is valid. */
-        if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
-        {
-            uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        taskENTER_CRITICAL();
-        {
-            /* If null is passed in here then it is the priority of the calling
-             * task that is being changed. */
-            pxTCB = prvGetTCBFromHandle( xTask );
-
-            traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
-
-            #if ( configUSE_MUTEXES == 1 )
-                {
-                    uxCurrentBasePriority = pxTCB->uxBasePriority;
-                }
-            #else
-                {
-                    uxCurrentBasePriority = pxTCB->uxPriority;
-                }
-            #endif
-
-            if( uxCurrentBasePriority != uxNewPriority )
-            {
-                /* The priority change may have readied a task of higher
-                 * priority than the calling task. */
-                if( uxNewPriority > uxCurrentBasePriority )
-                {
-                    if( pxTCB != pxCurrentTCB )
-                    {
-                        /* The priority of a task other than the currently
-                         * running task is being raised.  Is the priority being
-                         * raised above that of the running task? */
-                        if( uxNewPriority >= pxCurrentTCB->uxPriority )
-                        {
-                            xYieldRequired = pdTRUE;
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                    else
-                    {
-                        /* The priority of the running task is being raised,
-                         * but the running task must already be the highest
-                         * priority task able to run so no yield is required. */
-                    }
-                }
-                else if( pxTCB == pxCurrentTCB )
-                {
-                    /* Setting the priority of the running task down means
-                     * there may now be another task of higher priority that
-                     * is ready to execute. */
-                    xYieldRequired = pdTRUE;
-                }
-                else
-                {
-                    /* Setting the priority of any other task down does not
-                     * require a yield as the running task must be above the
-                     * new priority of the task being modified. */
-                }
-
-                /* Remember the ready list the task might be referenced from
-                 * before its uxPriority member is changed so the
-                 * taskRESET_READY_PRIORITY() macro can function correctly. */
-                uxPriorityUsedOnEntry = pxTCB->uxPriority;
-
-                #if ( configUSE_MUTEXES == 1 )
-                    {
-                        /* Only change the priority being used if the task is not
-                         * currently using an inherited priority. */
-                        if( pxTCB->uxBasePriority == pxTCB->uxPriority )
-                        {
-                            pxTCB->uxPriority = uxNewPriority;
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-
-                        /* The base priority gets set whatever. */
-                        pxTCB->uxBasePriority = uxNewPriority;
-                    }
-                #else /* if ( configUSE_MUTEXES == 1 ) */
-                    {
-                        pxTCB->uxPriority = uxNewPriority;
-                    }
-                #endif /* if ( configUSE_MUTEXES == 1 ) */
-
-                /* Only reset the event list item value if the value is not
-                 * being used for anything else. */
-                if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
-                {
-                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                /* If the task is in the blocked or suspended list we need do
-                 * nothing more than change its priority variable. However, if
-                 * the task is in a ready list it needs to be removed and placed
-                 * in the list appropriate to its new priority. */
-                if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
-                {
-                    /* The task is currently in its ready list - remove before
-                     * adding it to it's new ready list.  As we are in a critical
-                     * section we can do this even if the scheduler is suspended. */
-                    if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-                    {
-                        /* It is known that the task is in its ready list so
-                         * there is no need to check again and the port level
-                         * reset macro can be called directly. */
-                        portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-
-                    prvAddTaskToReadyList( pxTCB );
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                if( xYieldRequired != pdFALSE )
-                {
-                    taskYIELD_IF_USING_PREEMPTION();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                /* Remove compiler warning about unused variables when the port
-                 * optimised task selection is not being used. */
-                ( void ) uxPriorityUsedOnEntry;
-            }
-        }
-        taskEXIT_CRITICAL();
-    }
-
-#endif /* INCLUDE_vTaskPrioritySet */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-    void vTaskSuspend( TaskHandle_t xTaskToSuspend )
-    {
-        TCB_t * pxTCB;
-
-        taskENTER_CRITICAL();
-        {
-            /* If null is passed in here then it is the running task that is
-             * being suspended. */
-            pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
-
-            traceTASK_SUSPEND( pxTCB );
-
-            /* Remove task from the ready/delayed list and place in the
-             * suspended list. */
-            if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-            {
-                taskRESET_READY_PRIORITY( pxTCB->uxPriority );
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            /* Is the task waiting on an event also? */
-            if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-            {
-                ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
-
-            #if ( configUSE_TASK_NOTIFICATIONS == 1 )
-                {
-                    BaseType_t x;
-
-                    for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
-                    {
-                        if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
-                        {
-                            /* The task was blocked to wait for a notification, but is
-                             * now suspended, so no notification was received. */
-                            pxTCB->ucNotifyState[ x ] = taskNOT_WAITING_NOTIFICATION;
-                        }
-                    }
-                }
-            #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
-        }
-        taskEXIT_CRITICAL();
-
-        if( xSchedulerRunning != pdFALSE )
-        {
-            /* Reset the next expected unblock time in case it referred to the
-             * task that is now in the Suspended state. */
-            taskENTER_CRITICAL();
-            {
-                prvResetNextTaskUnblockTime();
-            }
-            taskEXIT_CRITICAL();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        if( pxTCB == pxCurrentTCB )
-        {
-            if( xSchedulerRunning != pdFALSE )
-            {
-                /* The current task has just been suspended. */
-                configASSERT( uxSchedulerSuspended == 0 );
-                portYIELD_WITHIN_API();
-            }
-            else
-            {
-                /* The scheduler is not running, but the task that was pointed
-                 * to by pxCurrentTCB has just been suspended and pxCurrentTCB
-                 * must be adjusted to point to a different task. */
-                if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
-                {
-                    /* No other tasks are ready, so set pxCurrentTCB back to
-                     * NULL so when the next task is created pxCurrentTCB will
-                     * be set to point to it no matter what its relative priority
-                     * is. */
-                    pxCurrentTCB = NULL;
-                }
-                else
-                {
-                    vTaskSwitchContext();
-                }
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-
-#endif /* INCLUDE_vTaskSuspend */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-    static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
-    {
-        BaseType_t xReturn = pdFALSE;
-        const TCB_t * const pxTCB = xTask;
-
-        /* Accesses xPendingReadyList so must be called from a critical
-         * section. */
-
-        /* It does not make sense to check if the calling task is suspended. */
-        configASSERT( xTask );
-
-        /* Is the task being resumed actually in the suspended list? */
-        if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
-        {
-            /* Has the task already been resumed from within an ISR? */
-            if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
-            {
-                /* Is it in the suspended list because it is in the Suspended
-                 * state, or because is is blocked with no timeout? */
-                if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
-                {
-                    xReturn = pdTRUE;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        return xReturn;
-    } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
-
-#endif /* INCLUDE_vTaskSuspend */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-    void vTaskResume( TaskHandle_t xTaskToResume )
-    {
-        TCB_t * const pxTCB = xTaskToResume;
-
-        /* It does not make sense to resume the calling task. */
-        configASSERT( xTaskToResume );
-
-        /* The parameter cannot be NULL as it is impossible to resume the
-         * currently executing task. */
-        if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
-        {
-            taskENTER_CRITICAL();
-            {
-                if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
-                {
-                    traceTASK_RESUME( pxTCB );
-
-                    /* The ready list can be accessed even if the scheduler is
-                     * suspended because this is inside a critical section. */
-                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-                    prvAddTaskToReadyList( pxTCB );
-
-                    /* A higher priority task may have just been resumed. */
-                    if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
-                    {
-                        /* This yield may not cause the task just resumed to run,
-                         * but will leave the lists in the correct state for the
-                         * next yield. */
-                        taskYIELD_IF_USING_PREEMPTION();
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            taskEXIT_CRITICAL();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-
-#endif /* INCLUDE_vTaskSuspend */
-
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
-
-    BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
-    {
-        BaseType_t xYieldRequired = pdFALSE;
-        TCB_t * const pxTCB = xTaskToResume;
-        UBaseType_t uxSavedInterruptStatus;
-
-        configASSERT( xTaskToResume );
-
-        /* RTOS ports that support interrupt nesting have the concept of a
-         * maximum  system call (or maximum API call) interrupt priority.
-         * Interrupts that are  above the maximum system call priority are keep
-         * permanently enabled, even when the RTOS kernel is in a critical section,
-         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
-         * is defined in FreeRTOSConfig.h then
-         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-         * failure if a FreeRTOS API function is called from an interrupt that has
-         * been assigned a priority above the configured maximum system call
-         * priority.  Only FreeRTOS functions that end in FromISR can be called
-         * from interrupts  that have been assigned a priority at or (logically)
-         * below the maximum system call interrupt priority.  FreeRTOS maintains a
-         * separate interrupt safe API to ensure interrupt entry is as fast and as
-         * simple as possible.  More information (albeit Cortex-M specific) is
-         * provided on the following link:
-         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-        {
-            if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
-            {
-                traceTASK_RESUME_FROM_ISR( pxTCB );
-
-                /* Check the ready lists can be accessed. */
-                if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-                {
-                    /* Ready lists can be accessed so move the task from the
-                     * suspended list to the ready list directly. */
-                    if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
-                    {
-                        xYieldRequired = pdTRUE;
-
-                        /* Mark that a yield is pending in case the user is not
-                         * using the return value to initiate a context switch
-                         * from the ISR using portYIELD_FROM_ISR. */
-                        xYieldPending = pdTRUE;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-
-                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-                    prvAddTaskToReadyList( pxTCB );
-                }
-                else
-                {
-                    /* The delayed or ready lists cannot be accessed so the task
-                     * is held in the pending ready list until the scheduler is
-                     * unsuspended. */
-                    vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-        return xYieldRequired;
-    }
-
-#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-void vTaskStartScheduler( void )
-{
-    BaseType_t xReturn;
-
-    /* Add the idle task at the lowest priority. */
-    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-        {
-            StaticTask_t * pxIdleTaskTCBBuffer = NULL;
-            StackType_t * pxIdleTaskStackBuffer = NULL;
-            uint32_t ulIdleTaskStackSize;
-
-            /* The Idle task is created using user provided RAM - obtain the
-             * address of the RAM then create the idle task. */
-            vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
-            xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
-                                                 configIDLE_TASK_NAME,
-                                                 ulIdleTaskStackSize,
-                                                 ( void * ) NULL,       /*lint !e961.  The cast is not redundant for all compilers. */
-                                                 portPRIVILEGE_BIT,     /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-                                                 pxIdleTaskStackBuffer,
-                                                 pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-
-            if( xIdleTaskHandle != NULL )
-            {
-                xReturn = pdPASS;
-            }
-            else
-            {
-                xReturn = pdFAIL;
-            }
-        }
-    #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-        {
-            /* The Idle task is being created using dynamically allocated RAM. */
-            xReturn = xTaskCreate( prvIdleTask,
-                                   configIDLE_TASK_NAME,
-                                   configMINIMAL_STACK_SIZE,
-                                   ( void * ) NULL,
-                                   portPRIVILEGE_BIT,  /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-                                   &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-        }
-    #endif /* configSUPPORT_STATIC_ALLOCATION */
-
-    #if ( configUSE_TIMERS == 1 )
-        {
-            if( xReturn == pdPASS )
-            {
-                xReturn = xTimerCreateTimerTask();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-    #endif /* configUSE_TIMERS */
-
-    if( xReturn == pdPASS )
-    {
-        /* freertos_tasks_c_additions_init() should only be called if the user
-         * definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
-         * the only macro called by the function. */
-        #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
-            {
-                freertos_tasks_c_additions_init();
-            }
-        #endif
-
-        /* Interrupts are turned off here, to ensure a tick does not occur
-         * before or during the call to xPortStartScheduler().  The stacks of
-         * the created tasks contain a status word with interrupts switched on
-         * so interrupts will automatically get re-enabled when the first task
-         * starts to run. */
-        portDISABLE_INTERRUPTS();
-
-        #if ( configUSE_NEWLIB_REENTRANT == 1 )
-            {
-                /* Switch Newlib's _impure_ptr variable to point to the _reent
-                 * structure specific to the task that will run first.
-                 * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
-                 * for additional information. */
-                _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
-            }
-        #endif /* configUSE_NEWLIB_REENTRANT */
-
-        xNextTaskUnblockTime = portMAX_DELAY;
-        xSchedulerRunning = pdTRUE;
-        xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
-
-        /* If configGENERATE_RUN_TIME_STATS is defined then the following
-         * macro must be defined to configure the timer/counter used to generate
-         * the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
-         * is set to 0 and the following line fails to build then ensure you do not
-         * have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
-         * FreeRTOSConfig.h file. */
-        portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
-
-        traceTASK_SWITCHED_IN();
-
-        /* Setting up the timer tick is hardware specific and thus in the
-         * portable interface. */
-        if( xPortStartScheduler() != pdFALSE )
-        {
-            /* Should not reach here as if the scheduler is running the
-             * function will not return. */
-        }
-        else
-        {
-            /* Should only reach here if a task calls xTaskEndScheduler(). */
-        }
-    }
-    else
-    {
-        /* This line will only be reached if the kernel could not be started,
-         * because there was not enough FreeRTOS heap to create the idle task
-         * or the timer task. */
-        configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
-    }
-
-    /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
-     * meaning xIdleTaskHandle is not used anywhere else. */
-    ( void ) xIdleTaskHandle;
-
-    /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority
-     * from getting optimized out as it is no longer used by the kernel. */
-    ( void ) uxTopUsedPriority;
-}
-/*-----------------------------------------------------------*/
-
-void vTaskEndScheduler( void )
-{
-    /* Stop the scheduler interrupts and call the portable scheduler end
-     * routine so the original ISRs can be restored if necessary.  The port
-     * layer must ensure interrupts enable  bit is left in the correct state. */
-    portDISABLE_INTERRUPTS();
-    xSchedulerRunning = pdFALSE;
-    vPortEndScheduler();
-}
-/*----------------------------------------------------------*/
-
-void vTaskSuspendAll( void )
-{
-    /* A critical section is not required as the variable is of type
-     * BaseType_t.  Please read Richard Barry's reply in the following link to a
-     * post in the FreeRTOS support forum before reporting this as a bug! -
-     * https://goo.gl/wu4acr */
-
-    /* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that
-     * do not otherwise exhibit real time behaviour. */
-    portSOFTWARE_BARRIER();
-
-    /* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
-     * is used to allow calls to vTaskSuspendAll() to nest. */
-    ++uxSchedulerSuspended;
-
-    /* Enforces ordering for ports and optimised compilers that may otherwise place
-     * the above increment elsewhere. */
-    portMEMORY_BARRIER();
-}
-/*----------------------------------------------------------*/
-
-#if ( configUSE_TICKLESS_IDLE != 0 )
-
-    static TickType_t prvGetExpectedIdleTime( void )
-    {
-        TickType_t xReturn;
-        UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
-
-        /* uxHigherPriorityReadyTasks takes care of the case where
-         * configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
-         * task that are in the Ready state, even though the idle task is
-         * running. */
-        #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
-            {
-                if( uxTopReadyPriority > tskIDLE_PRIORITY )
-                {
-                    uxHigherPriorityReadyTasks = pdTRUE;
-                }
-            }
-        #else
-            {
-                const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
-
-                /* When port optimised task selection is used the uxTopReadyPriority
-                 * variable is used as a bit map.  If bits other than the least
-                 * significant bit are set then there are tasks that have a priority
-                 * above the idle priority that are in the Ready state.  This takes
-                 * care of the case where the co-operative scheduler is in use. */
-                if( uxTopReadyPriority > uxLeastSignificantBit )
-                {
-                    uxHigherPriorityReadyTasks = pdTRUE;
-                }
-            }
-        #endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */
-
-        if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
-        {
-            xReturn = 0;
-        }
-        else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
-        {
-            /* There are other idle priority tasks in the ready state.  If
-             * time slicing is used then the very next tick interrupt must be
-             * processed. */
-            xReturn = 0;
-        }
-        else if( uxHigherPriorityReadyTasks != pdFALSE )
-        {
-            /* There are tasks in the Ready state that have a priority above the
-             * idle priority.  This path can only be reached if
-             * configUSE_PREEMPTION is 0. */
-            xReturn = 0;
-        }
-        else
-        {
-            xReturn = xNextTaskUnblockTime - xTickCount;
-        }
-
-        return xReturn;
-    }
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*----------------------------------------------------------*/
-
-BaseType_t xTaskResumeAll( void )
-{
-    TCB_t * pxTCB = NULL;
-    BaseType_t xAlreadyYielded = pdFALSE;
-
-    /* If uxSchedulerSuspended is zero then this function does not match a
-     * previous call to vTaskSuspendAll(). */
-    configASSERT( uxSchedulerSuspended );
-
-    /* It is possible that an ISR caused a task to be removed from an event
-     * list while the scheduler was suspended.  If this was the case then the
-     * removed task will have been added to the xPendingReadyList.  Once the
-     * scheduler has been resumed it is safe to move all the pending ready
-     * tasks from this list into their appropriate ready list. */
-    taskENTER_CRITICAL();
-    {
-        --uxSchedulerSuspended;
-
-        if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-        {
-            if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
-            {
-                /* Move any readied tasks from the pending list into the
-                 * appropriate ready list. */
-                while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
-                {
-                    pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-                    ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-                    prvAddTaskToReadyList( pxTCB );
-
-                    /* If the moved task has a priority higher than the current
-                     * task then a yield must be performed. */
-                    if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
-                    {
-                        xYieldPending = pdTRUE;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-
-                if( pxTCB != NULL )
-                {
-                    /* A task was unblocked while the scheduler was suspended,
-                     * which may have prevented the next unblock time from being
-                     * re-calculated, in which case re-calculate it now.  Mainly
-                     * important for low power tickless implementations, where
-                     * this can prevent an unnecessary exit from low power
-                     * state. */
-                    prvResetNextTaskUnblockTime();
-                }
-
-                /* If any ticks occurred while the scheduler was suspended then
-                 * they should be processed now.  This ensures the tick count does
-                 * not  slip, and that any delayed tasks are resumed at the correct
-                 * time. */
-                {
-                    TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
-
-                    if( xPendedCounts > ( TickType_t ) 0U )
-                    {
-                        do
-                        {
-                            if( xTaskIncrementTick() != pdFALSE )
-                            {
-                                xYieldPending = pdTRUE;
-                            }
-                            else
-                            {
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-
-                            --xPendedCounts;
-                        } while( xPendedCounts > ( TickType_t ) 0U );
-
-                        xPendedTicks = 0;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-
-                if( xYieldPending != pdFALSE )
-                {
-                    #if ( configUSE_PREEMPTION != 0 )
-                        {
-                            xAlreadyYielded = pdTRUE;
-                        }
-                    #endif
-                    taskYIELD_IF_USING_PREEMPTION();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    taskEXIT_CRITICAL();
-
-    return xAlreadyYielded;
-}
-/*-----------------------------------------------------------*/
-
-TickType_t xTaskGetTickCount( void )
-{
-    TickType_t xTicks;
-
-    /* Critical section required if running on a 16 bit processor. */
-    portTICK_TYPE_ENTER_CRITICAL();
-    {
-        xTicks = xTickCount;
-    }
-    portTICK_TYPE_EXIT_CRITICAL();
-
-    return xTicks;
-}
-/*-----------------------------------------------------------*/
-
-TickType_t xTaskGetTickCountFromISR( void )
-{
-    TickType_t xReturn;
-    UBaseType_t uxSavedInterruptStatus;
-
-    /* RTOS ports that support interrupt nesting have the concept of a maximum
-     * system call (or maximum API call) interrupt priority.  Interrupts that are
-     * above the maximum system call priority are kept permanently enabled, even
-     * when the RTOS kernel is in a critical section, but cannot make any calls to
-     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-     * failure if a FreeRTOS API function is called from an interrupt that has been
-     * assigned a priority above the configured maximum system call priority.
-     * Only FreeRTOS functions that end in FromISR can be called from interrupts
-     * that have been assigned a priority at or (logically) below the maximum
-     * system call  interrupt priority.  FreeRTOS maintains a separate interrupt
-     * safe API to ensure interrupt entry is as fast and as simple as possible.
-     * More information (albeit Cortex-M specific) is provided on the following
-     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-    uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
-    {
-        xReturn = xTickCount;
-    }
-    portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxTaskGetNumberOfTasks( void )
-{
-    /* A critical section is not required because the variables are of type
-     * BaseType_t. */
-    return uxCurrentNumberOfTasks;
-}
-/*-----------------------------------------------------------*/
-
-char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-{
-    TCB_t * pxTCB;
-
-    /* If null is passed in here then the name of the calling task is being
-     * queried. */
-    pxTCB = prvGetTCBFromHandle( xTaskToQuery );
-    configASSERT( pxTCB );
-    return &( pxTCB->pcTaskName[ 0 ] );
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetHandle == 1 )
-
-    static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
-                                                     const char pcNameToQuery[] )
-    {
-        TCB_t * pxNextTCB, * pxFirstTCB, * pxReturn = NULL;
-        UBaseType_t x;
-        char cNextChar;
-        BaseType_t xBreakLoop;
-
-        /* This function is called with the scheduler suspended. */
-
-        if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
-        {
-            listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
-            do
-            {
-                listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
-                /* Check each character in the name looking for a match or
-                 * mismatch. */
-                xBreakLoop = pdFALSE;
-
-                for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
-                {
-                    cNextChar = pxNextTCB->pcTaskName[ x ];
-
-                    if( cNextChar != pcNameToQuery[ x ] )
-                    {
-                        /* Characters didn't match. */
-                        xBreakLoop = pdTRUE;
-                    }
-                    else if( cNextChar == ( char ) 0x00 )
-                    {
-                        /* Both strings terminated, a match must have been
-                         * found. */
-                        pxReturn = pxNextTCB;
-                        xBreakLoop = pdTRUE;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-
-                    if( xBreakLoop != pdFALSE )
-                    {
-                        break;
-                    }
-                }
-
-                if( pxReturn != NULL )
-                {
-                    /* The handle has been found. */
-                    break;
-                }
-            } while( pxNextTCB != pxFirstTCB );
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        return pxReturn;
-    }
-
-#endif /* INCLUDE_xTaskGetHandle */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetHandle == 1 )
-
-    TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-    {
-        UBaseType_t uxQueue = configMAX_PRIORITIES;
-        TCB_t * pxTCB;
-
-        /* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
-        configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
-
-        vTaskSuspendAll();
-        {
-            /* Search the ready lists. */
-            do
-            {
-                uxQueue--;
-                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
-
-                if( pxTCB != NULL )
-                {
-                    /* Found the handle. */
-                    break;
-                }
-            } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
-            /* Search the delayed lists. */
-            if( pxTCB == NULL )
-            {
-                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
-            }
-
-            if( pxTCB == NULL )
-            {
-                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
-            }
-
-            #if ( INCLUDE_vTaskSuspend == 1 )
-                {
-                    if( pxTCB == NULL )
-                    {
-                        /* Search the suspended list. */
-                        pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
-                    }
-                }
-            #endif
-
-            #if ( INCLUDE_vTaskDelete == 1 )
-                {
-                    if( pxTCB == NULL )
-                    {
-                        /* Search the deleted list. */
-                        pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
-                    }
-                }
-            #endif
-        }
-        ( void ) xTaskResumeAll();
-
-        return pxTCB;
-    }
-
-#endif /* INCLUDE_xTaskGetHandle */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      uint32_t * const pulTotalRunTime )
-    {
-        UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
-
-        vTaskSuspendAll();
-        {
-            /* Is there a space in the array for each task in the system? */
-            if( uxArraySize >= uxCurrentNumberOfTasks )
-            {
-                /* Fill in an TaskStatus_t structure with information on each
-                 * task in the Ready state. */
-                do
-                {
-                    uxQueue--;
-                    uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
-                } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
-                /* Fill in an TaskStatus_t structure with information on each
-                 * task in the Blocked state. */
-                uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
-                uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
-
-                #if ( INCLUDE_vTaskDelete == 1 )
-                    {
-                        /* Fill in an TaskStatus_t structure with information on
-                         * each task that has been deleted but not yet cleaned up. */
-                        uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
-                    }
-                #endif
-
-                #if ( INCLUDE_vTaskSuspend == 1 )
-                    {
-                        /* Fill in an TaskStatus_t structure with information on
-                         * each task in the Suspended state. */
-                        uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
-                    }
-                #endif
-
-                #if ( configGENERATE_RUN_TIME_STATS == 1 )
-                    {
-                        if( pulTotalRunTime != NULL )
-                        {
-                            #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
-                                portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
-                            #else
-                                *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
-                            #endif
-                        }
-                    }
-                #else /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
-                    {
-                        if( pulTotalRunTime != NULL )
-                        {
-                            *pulTotalRunTime = 0;
-                        }
-                    }
-                #endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        ( void ) xTaskResumeAll();
-
-        return uxTask;
-    }
-
-#endif /* configUSE_TRACE_FACILITY */
-/*----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
-
-    TaskHandle_t xTaskGetIdleTaskHandle( void )
-    {
-        /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
-         * started, then xIdleTaskHandle will be NULL. */
-        configASSERT( ( xIdleTaskHandle != NULL ) );
-        return xIdleTaskHandle;
-    }
-
-#endif /* INCLUDE_xTaskGetIdleTaskHandle */
-/*----------------------------------------------------------*/
-
-/* This conditional compilation should use inequality to 0, not equality to 1.
- * This is to ensure vTaskStepTick() is available when user defined low power mode
- * implementations require configUSE_TICKLESS_IDLE to be set to a value other than
- * 1. */
-#if ( configUSE_TICKLESS_IDLE != 0 )
-
-    void vTaskStepTick( const TickType_t xTicksToJump )
-    {
-        /* Correct the tick count value after a period during which the tick
-         * was suppressed.  Note this does *not* call the tick hook function for
-         * each stepped tick. */
-        configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
-        xTickCount += xTicksToJump;
-        traceINCREASE_TICK_COUNT( xTicksToJump );
-    }
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*----------------------------------------------------------*/
-
-BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
-{
-    BaseType_t xYieldOccurred;
-
-    /* Must not be called with the scheduler suspended as the implementation
-     * relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */
-    configASSERT( uxSchedulerSuspended == 0 );
-
-    /* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when
-     * the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */
-    vTaskSuspendAll();
-    xPendedTicks += xTicksToCatchUp;
-    xYieldOccurred = xTaskResumeAll();
-
-    return xYieldOccurred;
-}
-/*----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskAbortDelay == 1 )
-
-    BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
-    {
-        TCB_t * pxTCB = xTask;
-        BaseType_t xReturn;
-
-        configASSERT( pxTCB );
-
-        vTaskSuspendAll();
-        {
-            /* A task can only be prematurely removed from the Blocked state if
-             * it is actually in the Blocked state. */
-            if( eTaskGetState( xTask ) == eBlocked )
-            {
-                xReturn = pdPASS;
-
-                /* Remove the reference to the task from the blocked list.  An
-                 * interrupt won't touch the xStateListItem because the
-                 * scheduler is suspended. */
-                ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-
-                /* Is the task waiting on an event also?  If so remove it from
-                 * the event list too.  Interrupts can touch the event list item,
-                 * even though the scheduler is suspended, so a critical section
-                 * is used. */
-                taskENTER_CRITICAL();
-                {
-                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-                    {
-                        ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-
-                        /* This lets the task know it was forcibly removed from the
-                         * blocked state so it should not re-evaluate its block time and
-                         * then block again. */
-                        pxTCB->ucDelayAborted = pdTRUE;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                taskEXIT_CRITICAL();
-
-                /* Place the unblocked task into the appropriate ready list. */
-                prvAddTaskToReadyList( pxTCB );
-
-                /* A task being unblocked cannot cause an immediate context
-                 * switch if preemption is turned off. */
-                #if ( configUSE_PREEMPTION == 1 )
-                    {
-                        /* Preemption is on, but a context switch should only be
-                         *  performed if the unblocked task has a priority that is
-                         *  equal to or higher than the currently executing task. */
-                        if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-                        {
-                            /* Pend the yield to be performed when the scheduler
-                             * is unsuspended. */
-                            xYieldPending = pdTRUE;
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                #endif /* configUSE_PREEMPTION */
-            }
-            else
-            {
-                xReturn = pdFAIL;
-            }
-        }
-        ( void ) xTaskResumeAll();
-
-        return xReturn;
-    }
-
-#endif /* INCLUDE_xTaskAbortDelay */
-/*----------------------------------------------------------*/
-
-BaseType_t xTaskIncrementTick( void )
-{
-    TCB_t * pxTCB;
-    TickType_t xItemValue;
-    BaseType_t xSwitchRequired = pdFALSE;
-
-    /* Called by the portable layer each time a tick interrupt occurs.
-     * Increments the tick then checks to see if the new tick value will cause any
-     * tasks to be unblocked. */
-    traceTASK_INCREMENT_TICK( xTickCount );
-
-    if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-    {
-        /* Minor optimisation.  The tick count cannot change in this
-         * block. */
-        const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
-
-        /* Increment the RTOS tick, switching the delayed and overflowed
-         * delayed lists if it wraps to 0. */
-        xTickCount = xConstTickCount;
-
-        if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
-        {
-            taskSWITCH_DELAYED_LISTS();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        /* See if this tick has made a timeout expire.  Tasks are stored in
-         * the  queue in the order of their wake time - meaning once one task
-         * has been found whose block time has not expired there is no need to
-         * look any further down the list. */
-        if( xConstTickCount >= xNextTaskUnblockTime )
-        {
-            for( ; ; )
-            {
-                if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
-                {
-                    /* The delayed list is empty.  Set xNextTaskUnblockTime
-                     * to the maximum possible value so it is extremely
-                     * unlikely that the
-                     * if( xTickCount >= xNextTaskUnblockTime ) test will pass
-                     * next time through. */
-                    xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-                    break;
-                }
-                else
-                {
-                    /* The delayed list is not empty, get the value of the
-                     * item at the head of the delayed list.  This is the time
-                     * at which the task at the head of the delayed list must
-                     * be removed from the Blocked state. */
-                    pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-                    xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
-
-                    if( xConstTickCount < xItemValue )
-                    {
-                        /* It is not time to unblock this item yet, but the
-                         * item value is the time at which the task at the head
-                         * of the blocked list must be removed from the Blocked
-                         * state -  so record the item value in
-                         * xNextTaskUnblockTime. */
-                        xNextTaskUnblockTime = xItemValue;
-                        break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-
-                    /* It is time to remove the item from the Blocked state. */
-                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-
-                    /* Is the task waiting on an event also?  If so remove
-                     * it from the event list. */
-                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-                    {
-                        ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-
-                    /* Place the unblocked task into the appropriate ready
-                     * list. */
-                    prvAddTaskToReadyList( pxTCB );
-
-                    /* A task being unblocked cannot cause an immediate
-                     * context switch if preemption is turned off. */
-                    #if ( configUSE_PREEMPTION == 1 )
-                        {
-                            /* Preemption is on, but a context switch should
-                             * only be performed if the unblocked task has a
-                             * priority that is equal to or higher than the
-                             * currently executing task. */
-                            if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
-                            {
-                                xSwitchRequired = pdTRUE;
-                            }
-                            else
-                            {
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                        }
-                    #endif /* configUSE_PREEMPTION */
-                }
-            }
-        }
-
-        /* Tasks of equal priority to the currently running task will share
-         * processing time (time slice) if preemption is on, and the application
-         * writer has not explicitly turned time slicing off. */
-        #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
-            {
-                if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
-                {
-                    xSwitchRequired = pdTRUE;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
-
-        #if ( configUSE_TICK_HOOK == 1 )
-            {
-                /* Guard against the tick hook being called when the pended tick
-                 * count is being unwound (when the scheduler is being unlocked). */
-                if( xPendedTicks == ( TickType_t ) 0 )
-                {
-                    vApplicationTickHook();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        #endif /* configUSE_TICK_HOOK */
-
-        #if ( configUSE_PREEMPTION == 1 )
-            {
-                if( xYieldPending != pdFALSE )
-                {
-                    xSwitchRequired = pdTRUE;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        #endif /* configUSE_PREEMPTION */
-    }
-    else
-    {
-        ++xPendedTicks;
-
-        /* The tick hook gets called at regular intervals, even if the
-         * scheduler is locked. */
-        #if ( configUSE_TICK_HOOK == 1 )
-            {
-                vApplicationTickHook();
-            }
-        #endif
-    }
-
-    return xSwitchRequired;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-
-    void vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction )
-    {
-        TCB_t * xTCB;
-
-        /* If xTask is NULL then it is the task hook of the calling task that is
-         * getting set. */
-        if( xTask == NULL )
-        {
-            xTCB = ( TCB_t * ) pxCurrentTCB;
-        }
-        else
-        {
-            xTCB = xTask;
-        }
-
-        /* Save the hook function in the TCB.  A critical section is required as
-         * the value can be accessed from an interrupt. */
-        taskENTER_CRITICAL();
-        {
-            xTCB->pxTaskTag = pxHookFunction;
-        }
-        taskEXIT_CRITICAL();
-    }
-
-#endif /* configUSE_APPLICATION_TASK_TAG */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-
-    TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
-    {
-        TCB_t * pxTCB;
-        TaskHookFunction_t xReturn;
-
-        /* If xTask is NULL then set the calling task's hook. */
-        pxTCB = prvGetTCBFromHandle( xTask );
-
-        /* Save the hook function in the TCB.  A critical section is required as
-         * the value can be accessed from an interrupt. */
-        taskENTER_CRITICAL();
-        {
-            xReturn = pxTCB->pxTaskTag;
-        }
-        taskEXIT_CRITICAL();
-
-        return xReturn;
-    }
-
-#endif /* configUSE_APPLICATION_TASK_TAG */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-
-    TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
-    {
-        TCB_t * pxTCB;
-        TaskHookFunction_t xReturn;
-        UBaseType_t uxSavedInterruptStatus;
-
-        /* If xTask is NULL then set the calling task's hook. */
-        pxTCB = prvGetTCBFromHandle( xTask );
-
-        /* Save the hook function in the TCB.  A critical section is required as
-         * the value can be accessed from an interrupt. */
-        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-        {
-            xReturn = pxTCB->pxTaskTag;
-        }
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-        return xReturn;
-    }
-
-#endif /* configUSE_APPLICATION_TASK_TAG */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-
-    BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
-                                             void * pvParameter )
-    {
-        TCB_t * xTCB;
-        BaseType_t xReturn;
-
-        /* If xTask is NULL then we are calling our own task hook. */
-        if( xTask == NULL )
-        {
-            xTCB = pxCurrentTCB;
-        }
-        else
-        {
-            xTCB = xTask;
-        }
-
-        if( xTCB->pxTaskTag != NULL )
-        {
-            xReturn = xTCB->pxTaskTag( pvParameter );
-        }
-        else
-        {
-            xReturn = pdFAIL;
-        }
-
-        return xReturn;
-    }
-
-#endif /* configUSE_APPLICATION_TASK_TAG */
-/*-----------------------------------------------------------*/
-
-void vTaskSwitchContext( void )
-{
-    if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
-    {
-        /* The scheduler is currently suspended - do not allow a context
-         * switch. */
-        xYieldPending = pdTRUE;
-    }
-    else
-    {
-        xYieldPending = pdFALSE;
-        traceTASK_SWITCHED_OUT();
-
-        #if ( configGENERATE_RUN_TIME_STATS == 1 )
-            {
-                #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
-                    portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
-                #else
-                    ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
-                #endif
-
-                /* Add the amount of time the task has been running to the
-                 * accumulated time so far.  The time the task started running was
-                 * stored in ulTaskSwitchedInTime.  Note that there is no overflow
-                 * protection here so count values are only valid until the timer
-                 * overflows.  The guard against negative values is to protect
-                 * against suspect run time stat counter implementations - which
-                 * are provided by the application, not the kernel. */
-                if( ulTotalRunTime > ulTaskSwitchedInTime )
-                {
-                    pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                ulTaskSwitchedInTime = ulTotalRunTime;
-            }
-        #endif /* configGENERATE_RUN_TIME_STATS */
-
-        /* Check for stack overflow, if configured. */
-        taskCHECK_FOR_STACK_OVERFLOW();
-
-        /* Before the currently running task is switched out, save its errno. */
-        #if ( configUSE_POSIX_ERRNO == 1 )
-            {
-                pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
-            }
-        #endif
-
-        /* Select a new task to run using either the generic C or port
-         * optimised asm code. */
-        taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-        traceTASK_SWITCHED_IN();
-
-        /* After the new task is switched in, update the global errno. */
-        #if ( configUSE_POSIX_ERRNO == 1 )
-            {
-                FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
-            }
-        #endif
-
-        #if ( configUSE_NEWLIB_REENTRANT == 1 )
-            {
-                /* Switch Newlib's _impure_ptr variable to point to the _reent
-                 * structure specific to this task.
-                 * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
-                 * for additional information. */
-                _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
-            }
-        #endif /* configUSE_NEWLIB_REENTRANT */
-    }
-}
-/*-----------------------------------------------------------*/
-
-void vTaskPlaceOnEventList( List_t * const pxEventList,
-                            const TickType_t xTicksToWait )
-{
-    configASSERT( pxEventList );
-
-    /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
-     * SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
-
-    /* Place the event list item of the TCB in the appropriate event list.
-     * This is placed in the list in priority order so the highest priority task
-     * is the first to be woken by the event.  The queue that contains the event
-     * list is locked, preventing simultaneous access from interrupts. */
-    vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
-
-    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-}
-/*-----------------------------------------------------------*/
-
-void vTaskPlaceOnUnorderedEventList( List_t * pxEventList,
-                                     const TickType_t xItemValue,
-                                     const TickType_t xTicksToWait )
-{
-    configASSERT( pxEventList );
-
-    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
-     * the event groups implementation. */
-    configASSERT( uxSchedulerSuspended != 0 );
-
-    /* Store the item value in the event list item.  It is safe to access the
-     * event list item here as interrupts won't access the event list item of a
-     * task that is not in the Blocked state. */
-    listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
-
-    /* Place the event list item of the TCB at the end of the appropriate event
-     * list.  It is safe to access the event list here because it is part of an
-     * event group implementation - and interrupts don't access event groups
-     * directly (instead they access them indirectly by pending function calls to
-     * the task level). */
-    vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
-
-    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-    void vTaskPlaceOnEventListRestricted( List_t * const pxEventList,
-                                          TickType_t xTicksToWait,
-                                          const BaseType_t xWaitIndefinitely )
-    {
-        configASSERT( pxEventList );
-
-        /* This function should not be called by application code hence the
-         * 'Restricted' in its name.  It is not part of the public API.  It is
-         * designed for use by kernel code, and has special calling requirements -
-         * it should be called with the scheduler suspended. */
-
-
-        /* Place the event list item of the TCB in the appropriate event list.
-         * In this case it is assume that this is the only task that is going to
-         * be waiting on this event list, so the faster vListInsertEnd() function
-         * can be used in place of vListInsert. */
-        vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
-
-        /* If the task should block indefinitely then set the block time to a
-         * value that will be recognised as an indefinite delay inside the
-         * prvAddCurrentTaskToDelayedList() function. */
-        if( xWaitIndefinitely != pdFALSE )
-        {
-            xTicksToWait = portMAX_DELAY;
-        }
-
-        traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
-        prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
-    }
-
-#endif /* configUSE_TIMERS */
-/*-----------------------------------------------------------*/
-
-BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
-{
-    TCB_t * pxUnblockedTCB;
-    BaseType_t xReturn;
-
-    /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
-     * called from a critical section within an ISR. */
-
-    /* The event list is sorted in priority order, so the first in the list can
-     * be removed as it is known to be the highest priority.  Remove the TCB from
-     * the delayed list, and add it to the ready list.
-     *
-     * If an event is for a queue that is locked then this function will never
-     * get called - the lock count on the queue will get modified instead.  This
-     * means exclusive access to the event list is guaranteed here.
-     *
-     * This function assumes that a check has already been made to ensure that
-     * pxEventList is not empty. */
-    pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-    configASSERT( pxUnblockedTCB );
-    ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
-
-    if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-    {
-        ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
-        prvAddTaskToReadyList( pxUnblockedTCB );
-
-        #if ( configUSE_TICKLESS_IDLE != 0 )
-            {
-                /* If a task is blocked on a kernel object then xNextTaskUnblockTime
-                 * might be set to the blocked task's time out time.  If the task is
-                 * unblocked for a reason other than a timeout xNextTaskUnblockTime is
-                 * normally left unchanged, because it is automatically reset to a new
-                 * value when the tick count equals xNextTaskUnblockTime.  However if
-                 * tickless idling is used it might be more important to enter sleep mode
-                 * at the earliest possible time - so reset xNextTaskUnblockTime here to
-                 * ensure it is updated at the earliest possible time. */
-                prvResetNextTaskUnblockTime();
-            }
-        #endif
-    }
-    else
-    {
-        /* The delayed and ready lists cannot be accessed, so hold this task
-         * pending until the scheduler is resumed. */
-        vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
-    }
-
-    if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
-    {
-        /* Return true if the task removed from the event list has a higher
-         * priority than the calling task.  This allows the calling task to know if
-         * it should force a context switch now. */
-        xReturn = pdTRUE;
-
-        /* Mark that a yield is pending in case the user is not using the
-         * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
-        xYieldPending = pdTRUE;
-    }
-    else
-    {
-        xReturn = pdFALSE;
-    }
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
-                                        const TickType_t xItemValue )
-{
-    TCB_t * pxUnblockedTCB;
-
-    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
-     * the event flags implementation. */
-    configASSERT( uxSchedulerSuspended != pdFALSE );
-
-    /* Store the new item value in the event list. */
-    listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
-
-    /* Remove the event list form the event flag.  Interrupts do not access
-     * event flags. */
-    pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-    configASSERT( pxUnblockedTCB );
-    ( void ) uxListRemove( pxEventListItem );
-
-    #if ( configUSE_TICKLESS_IDLE != 0 )
-        {
-            /* If a task is blocked on a kernel object then xNextTaskUnblockTime
-             * might be set to the blocked task's time out time.  If the task is
-             * unblocked for a reason other than a timeout xNextTaskUnblockTime is
-             * normally left unchanged, because it is automatically reset to a new
-             * value when the tick count equals xNextTaskUnblockTime.  However if
-             * tickless idling is used it might be more important to enter sleep mode
-             * at the earliest possible time - so reset xNextTaskUnblockTime here to
-             * ensure it is updated at the earliest possible time. */
-            prvResetNextTaskUnblockTime();
-        }
-    #endif
-
-    /* Remove the task from the delayed list and add it to the ready list.  The
-     * scheduler is suspended so interrupts will not be accessing the ready
-     * lists. */
-    ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
-    prvAddTaskToReadyList( pxUnblockedTCB );
-
-    if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
-    {
-        /* The unblocked task has a priority above that of the calling task, so
-         * a context switch is required.  This function is called with the
-         * scheduler suspended so xYieldPending is set so the context switch
-         * occurs immediately that the scheduler is resumed (unsuspended). */
-        xYieldPending = pdTRUE;
-    }
-}
-/*-----------------------------------------------------------*/
-
-void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
-{
-    configASSERT( pxTimeOut );
-    taskENTER_CRITICAL();
-    {
-        pxTimeOut->xOverflowCount = xNumOfOverflows;
-        pxTimeOut->xTimeOnEntering = xTickCount;
-    }
-    taskEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
-{
-    /* For internal use only as it does not use a critical section. */
-    pxTimeOut->xOverflowCount = xNumOfOverflows;
-    pxTimeOut->xTimeOnEntering = xTickCount;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                 TickType_t * const pxTicksToWait )
-{
-    BaseType_t xReturn;
-
-    configASSERT( pxTimeOut );
-    configASSERT( pxTicksToWait );
-
-    taskENTER_CRITICAL();
-    {
-        /* Minor optimisation.  The tick count cannot change in this block. */
-        const TickType_t xConstTickCount = xTickCount;
-        const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
-
-        #if ( INCLUDE_xTaskAbortDelay == 1 )
-            if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
-            {
-                /* The delay was aborted, which is not the same as a time out,
-                 * but has the same result. */
-                pxCurrentTCB->ucDelayAborted = pdFALSE;
-                xReturn = pdTRUE;
-            }
-            else
-        #endif
-
-        #if ( INCLUDE_vTaskSuspend == 1 )
-            if( *pxTicksToWait == portMAX_DELAY )
-            {
-                /* If INCLUDE_vTaskSuspend is set to 1 and the block time
-                 * specified is the maximum block time then the task should block
-                 * indefinitely, and therefore never time out. */
-                xReturn = pdFALSE;
-            }
-            else
-        #endif
-
-        if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
-        {
-            /* The tick count is greater than the time at which
-             * vTaskSetTimeout() was called, but has also overflowed since
-             * vTaskSetTimeOut() was called.  It must have wrapped all the way
-             * around and gone past again. This passed since vTaskSetTimeout()
-             * was called. */
-            xReturn = pdTRUE;
-            *pxTicksToWait = ( TickType_t ) 0;
-        }
-        else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
-        {
-            /* Not a genuine timeout. Adjust parameters for time remaining. */
-            *pxTicksToWait -= xElapsedTime;
-            vTaskInternalSetTimeOutState( pxTimeOut );
-            xReturn = pdFALSE;
-        }
-        else
-        {
-            *pxTicksToWait = ( TickType_t ) 0;
-            xReturn = pdTRUE;
-        }
-    }
-    taskEXIT_CRITICAL();
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vTaskMissedYield( void )
-{
-    xYieldPending = pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
-    {
-        UBaseType_t uxReturn;
-        TCB_t const * pxTCB;
-
-        if( xTask != NULL )
-        {
-            pxTCB = xTask;
-            uxReturn = pxTCB->uxTaskNumber;
-        }
-        else
-        {
-            uxReturn = 0U;
-        }
-
-        return uxReturn;
-    }
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    void vTaskSetTaskNumber( TaskHandle_t xTask,
-                             const UBaseType_t uxHandle )
-    {
-        TCB_t * pxTCB;
-
-        if( xTask != NULL )
-        {
-            pxTCB = xTask;
-            pxTCB->uxTaskNumber = uxHandle;
-        }
-    }
-
-#endif /* configUSE_TRACE_FACILITY */
-
-/*
- * -----------------------------------------------------------
- * The Idle task.
- * ----------------------------------------------------------
- *
- * The portTASK_FUNCTION() macro is used to allow port/compiler specific
- * language extensions.  The equivalent prototype for this function is:
- *
- * void prvIdleTask( void *pvParameters );
- *
- */
-static portTASK_FUNCTION( prvIdleTask, pvParameters )
-{
-    /* Stop warnings. */
-    ( void ) pvParameters;
-
-    /** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
-     * SCHEDULER IS STARTED. **/
-
-    /* In case a task that has a secure context deletes itself, in which case
-     * the idle task is responsible for deleting the task's secure context, if
-     * any. */
-    portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
-
-    for( ; ; )
-    {
-        /* See if any tasks have deleted themselves - if so then the idle task
-         * is responsible for freeing the deleted task's TCB and stack. */
-        prvCheckTasksWaitingTermination();
-
-        #if ( configUSE_PREEMPTION == 0 )
-            {
-                /* If we are not using preemption we keep forcing a task switch to
-                 * see if any other task has become available.  If we are using
-                 * preemption we don't need to do this as any task becoming available
-                 * will automatically get the processor anyway. */
-                taskYIELD();
-            }
-        #endif /* configUSE_PREEMPTION */
-
-        #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
-            {
-                /* When using preemption tasks of equal priority will be
-                 * timesliced.  If a task that is sharing the idle priority is ready
-                 * to run then the idle task should yield before the end of the
-                 * timeslice.
-                 *
-                 * A critical region is not required here as we are just reading from
-                 * the list, and an occasional incorrect value will not matter.  If
-                 * the ready list at the idle priority contains more than one task
-                 * then a task other than the idle task is ready to execute. */
-                if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
-                {
-                    taskYIELD();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
-
-        #if ( configUSE_IDLE_HOOK == 1 )
-            {
-                extern void vApplicationIdleHook( void );
-
-                /* Call the user defined function from within the idle task.  This
-                 * allows the application designer to add background functionality
-                 * without the overhead of a separate task.
-                 * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
-                 * CALL A FUNCTION THAT MIGHT BLOCK. */
-                vApplicationIdleHook();
-            }
-        #endif /* configUSE_IDLE_HOOK */
-
-        /* This conditional compilation should use inequality to 0, not equality
-         * to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
-         * user defined low power mode  implementations require
-         * configUSE_TICKLESS_IDLE to be set to a value other than 1. */
-        #if ( configUSE_TICKLESS_IDLE != 0 )
-            {
-                TickType_t xExpectedIdleTime;
-
-                /* It is not desirable to suspend then resume the scheduler on
-                 * each iteration of the idle task.  Therefore, a preliminary
-                 * test of the expected idle time is performed without the
-                 * scheduler suspended.  The result here is not necessarily
-                 * valid. */
-                xExpectedIdleTime = prvGetExpectedIdleTime();
-
-                if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
-                {
-                    vTaskSuspendAll();
-                    {
-                        /* Now the scheduler is suspended, the expected idle
-                         * time can be sampled again, and this time its value can
-                         * be used. */
-                        configASSERT( xNextTaskUnblockTime >= xTickCount );
-                        xExpectedIdleTime = prvGetExpectedIdleTime();
-
-                        /* Define the following macro to set xExpectedIdleTime to 0
-                         * if the application does not want
-                         * portSUPPRESS_TICKS_AND_SLEEP() to be called. */
-                        configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
-
-                        if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
-                        {
-                            traceLOW_POWER_IDLE_BEGIN();
-                            portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
-                            traceLOW_POWER_IDLE_END();
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                    ( void ) xTaskResumeAll();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        #endif /* configUSE_TICKLESS_IDLE */
-    }
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TICKLESS_IDLE != 0 )
-
-    eSleepModeStatus eTaskConfirmSleepModeStatus( void )
-    {
-        /* The idle task exists in addition to the application tasks. */
-        const UBaseType_t uxNonApplicationTasks = 1;
-        eSleepModeStatus eReturn = eStandardSleep;
-
-        /* This function must be called from a critical section. */
-
-        if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
-        {
-            /* A task was made ready while the scheduler was suspended. */
-            eReturn = eAbortSleep;
-        }
-        else if( xYieldPending != pdFALSE )
-        {
-            /* A yield was pended while the scheduler was suspended. */
-            eReturn = eAbortSleep;
-        }
-        else if( xPendedTicks != 0 )
-        {
-            /* A tick interrupt has already occurred but was held pending
-             * because the scheduler is suspended. */
-            eReturn = eAbortSleep;
-        }
-        else
-        {
-            /* If all the tasks are in the suspended list (which might mean they
-             * have an infinite block time rather than actually being suspended)
-             * then it is safe to turn all clocks off and just wait for external
-             * interrupts. */
-            if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
-            {
-                eReturn = eNoTasksWaitingTimeout;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-
-        return eReturn;
-    }
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-
-    void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue )
-    {
-        TCB_t * pxTCB;
-
-        if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
-        {
-            pxTCB = prvGetTCBFromHandle( xTaskToSet );
-            configASSERT( pxTCB != NULL );
-            pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
-        }
-    }
-
-#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-
-    void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex )
-    {
-        void * pvReturn = NULL;
-        TCB_t * pxTCB;
-
-        if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
-        {
-            pxTCB = prvGetTCBFromHandle( xTaskToQuery );
-            pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
-        }
-        else
-        {
-            pvReturn = NULL;
-        }
-
-        return pvReturn;
-    }
-
-#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
-/*-----------------------------------------------------------*/
-
-#if ( portUSING_MPU_WRAPPERS == 1 )
-
-    void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
-                                  const MemoryRegion_t * const xRegions )
-    {
-        TCB_t * pxTCB;
-
-        /* If null is passed in here then we are modifying the MPU settings of
-         * the calling task. */
-        pxTCB = prvGetTCBFromHandle( xTaskToModify );
-
-        vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
-    }
-
-#endif /* portUSING_MPU_WRAPPERS */
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseTaskLists( void )
-{
-    UBaseType_t uxPriority;
-
-    for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
-    {
-        vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
-    }
-
-    vListInitialise( &xDelayedTaskList1 );
-    vListInitialise( &xDelayedTaskList2 );
-    vListInitialise( &xPendingReadyList );
-
-    #if ( INCLUDE_vTaskDelete == 1 )
-        {
-            vListInitialise( &xTasksWaitingTermination );
-        }
-    #endif /* INCLUDE_vTaskDelete */
-
-    #if ( INCLUDE_vTaskSuspend == 1 )
-        {
-            vListInitialise( &xSuspendedTaskList );
-        }
-    #endif /* INCLUDE_vTaskSuspend */
-
-    /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
-     * using list2. */
-    pxDelayedTaskList = &xDelayedTaskList1;
-    pxOverflowDelayedTaskList = &xDelayedTaskList2;
-}
-/*-----------------------------------------------------------*/
-
-static void prvCheckTasksWaitingTermination( void )
-{
-    /** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
-
-    #if ( INCLUDE_vTaskDelete == 1 )
-        {
-            TCB_t * pxTCB;
-
-            /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
-             * being called too often in the idle task. */
-            while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
-            {
-                taskENTER_CRITICAL();
-                {
-                    pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-                    --uxCurrentNumberOfTasks;
-                    --uxDeletedTasksWaitingCleanUp;
-                }
-                taskEXIT_CRITICAL();
-
-                prvDeleteTCB( pxTCB );
-            }
-        }
-    #endif /* INCLUDE_vTaskDelete */
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    void vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState )
-    {
-        TCB_t * pxTCB;
-
-        /* xTask is NULL then get the state of the calling task. */
-        pxTCB = prvGetTCBFromHandle( xTask );
-
-        pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
-        pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] );
-        pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
-        pxTaskStatus->pxStackBase = pxTCB->pxStack;
-        pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
-
-        #if ( configUSE_MUTEXES == 1 )
-            {
-                pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
-            }
-        #else
-            {
-                pxTaskStatus->uxBasePriority = 0;
-            }
-        #endif
-
-        #if ( configGENERATE_RUN_TIME_STATS == 1 )
-            {
-                pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
-            }
-        #else
-            {
-                pxTaskStatus->ulRunTimeCounter = 0;
-            }
-        #endif
-
-        /* Obtaining the task state is a little fiddly, so is only done if the
-         * value of eState passed into this function is eInvalid - otherwise the
-         * state is just set to whatever is passed in. */
-        if( eState != eInvalid )
-        {
-            if( pxTCB == pxCurrentTCB )
-            {
-                pxTaskStatus->eCurrentState = eRunning;
-            }
-            else
-            {
-                pxTaskStatus->eCurrentState = eState;
-
-                #if ( INCLUDE_vTaskSuspend == 1 )
-                    {
-                        /* If the task is in the suspended list then there is a
-                         *  chance it is actually just blocked indefinitely - so really
-                         *  it should be reported as being in the Blocked state. */
-                        if( eState == eSuspended )
-                        {
-                            vTaskSuspendAll();
-                            {
-                                if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-                                {
-                                    pxTaskStatus->eCurrentState = eBlocked;
-                                }
-                            }
-                            ( void ) xTaskResumeAll();
-                        }
-                    }
-                #endif /* INCLUDE_vTaskSuspend */
-            }
-        }
-        else
-        {
-            pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
-        }
-
-        /* Obtaining the stack space takes some time, so the xGetFreeStackSpace
-         * parameter is provided to allow it to be skipped. */
-        if( xGetFreeStackSpace != pdFALSE )
-        {
-            #if ( portSTACK_GROWTH > 0 )
-                {
-                    pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
-                }
-            #else
-                {
-                    pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
-                }
-            #endif
-        }
-        else
-        {
-            pxTaskStatus->usStackHighWaterMark = 0;
-        }
-    }
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray,
-                                                     List_t * pxList,
-                                                     eTaskState eState )
-    {
-        configLIST_VOLATILE TCB_t * pxNextTCB, * pxFirstTCB;
-        UBaseType_t uxTask = 0;
-
-        if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
-        {
-            listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
-            /* Populate an TaskStatus_t structure within the
-             * pxTaskStatusArray array for each task that is referenced from
-             * pxList.  See the definition of TaskStatus_t in task.h for the
-             * meaning of each TaskStatus_t structure member. */
-            do
-            {
-                listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-                vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
-                uxTask++;
-            } while( pxNextTCB != pxFirstTCB );
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        return uxTask;
-    }
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
-
-    static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
-    {
-        uint32_t ulCount = 0U;
-
-        while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
-        {
-            pucStackByte -= portSTACK_GROWTH;
-            ulCount++;
-        }
-
-        ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
-
-        return ( configSTACK_DEPTH_TYPE ) ulCount;
-    }
-
-#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
-
-/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
- * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
- * user to determine the return type.  It gets around the problem of the value
- * overflowing on 8-bit types without breaking backward compatibility for
- * applications that expect an 8-bit return type. */
-    configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
-    {
-        TCB_t * pxTCB;
-        uint8_t * pucEndOfStack;
-        configSTACK_DEPTH_TYPE uxReturn;
-
-        /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
-         * the same except for their return type.  Using configSTACK_DEPTH_TYPE
-         * allows the user to determine the return type.  It gets around the
-         * problem of the value overflowing on 8-bit types without breaking
-         * backward compatibility for applications that expect an 8-bit return
-         * type. */
-
-        pxTCB = prvGetTCBFromHandle( xTask );
-
-        #if portSTACK_GROWTH < 0
-            {
-                pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
-            }
-        #else
-            {
-                pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
-            }
-        #endif
-
-        uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
-
-        return uxReturn;
-    }
-
-#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
-
-    UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
-    {
-        TCB_t * pxTCB;
-        uint8_t * pucEndOfStack;
-        UBaseType_t uxReturn;
-
-        pxTCB = prvGetTCBFromHandle( xTask );
-
-        #if portSTACK_GROWTH < 0
-            {
-                pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
-            }
-        #else
-            {
-                pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
-            }
-        #endif
-
-        uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
-
-        return uxReturn;
-    }
-
-#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelete == 1 )
-
-    static void prvDeleteTCB( TCB_t * pxTCB )
-    {
-        /* This call is required specifically for the TriCore port.  It must be
-         * above the vPortFree() calls.  The call is also used by ports/demos that
-         * want to allocate and clean RAM statically. */
-        portCLEAN_UP_TCB( pxTCB );
-
-        /* Free up the memory allocated by the scheduler for the task.  It is up
-         * to the task to free any memory allocated at the application level.
-         * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
-         * for additional information. */
-        #if ( configUSE_NEWLIB_REENTRANT == 1 )
-            {
-                _reclaim_reent( &( pxTCB->xNewLib_reent ) );
-            }
-        #endif /* configUSE_NEWLIB_REENTRANT */
-
-        #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
-            {
-                /* The task can only have been allocated dynamically - free both
-                 * the stack and TCB. */
-                vPortFree( pxTCB->pxStack );
-                vPortFree( pxTCB );
-            }
-        #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
-            {
-                /* The task could have been allocated statically or dynamically, so
-                 * check what was statically allocated before trying to free the
-                 * memory. */
-                if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
-                {
-                    /* Both the stack and TCB were allocated dynamically, so both
-                     * must be freed. */
-                    vPortFree( pxTCB->pxStack );
-                    vPortFree( pxTCB );
-                }
-                else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
-                {
-                    /* Only the stack was statically allocated, so the TCB is the
-                     * only memory that must be freed. */
-                    vPortFree( pxTCB );
-                }
-                else
-                {
-                    /* Neither the stack nor the TCB were allocated dynamically, so
-                     * nothing needs to be freed. */
-                    configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-    }
-
-#endif /* INCLUDE_vTaskDelete */
-/*-----------------------------------------------------------*/
-
-static void prvResetNextTaskUnblockTime( void )
-{
-    if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
-    {
-        /* The new current delayed list is empty.  Set xNextTaskUnblockTime to
-         * the maximum possible value so it is  extremely unlikely that the
-         * if( xTickCount >= xNextTaskUnblockTime ) test will pass until
-         * there is an item in the delayed list. */
-        xNextTaskUnblockTime = portMAX_DELAY;
-    }
-    else
-    {
-        /* The new current delayed list is not empty, get the value of
-         * the item at the head of the delayed list.  This is the time at
-         * which the task at the head of the delayed list should be removed
-         * from the Blocked state. */
-        xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList );
-    }
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
-
-    TaskHandle_t xTaskGetCurrentTaskHandle( void )
-    {
-        TaskHandle_t xReturn;
-
-        /* A critical section is not required as this is not called from
-         * an interrupt and the current TCB will always be the same for any
-         * individual execution thread. */
-        xReturn = pxCurrentTCB;
-
-        return xReturn;
-    }
-
-#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-
-    BaseType_t xTaskGetSchedulerState( void )
-    {
-        BaseType_t xReturn;
-
-        if( xSchedulerRunning == pdFALSE )
-        {
-            xReturn = taskSCHEDULER_NOT_STARTED;
-        }
-        else
-        {
-            if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-            {
-                xReturn = taskSCHEDULER_RUNNING;
-            }
-            else
-            {
-                xReturn = taskSCHEDULER_SUSPENDED;
-            }
-        }
-
-        return xReturn;
-    }
-
-#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-    BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
-    {
-        TCB_t * const pxMutexHolderTCB = pxMutexHolder;
-        BaseType_t xReturn = pdFALSE;
-
-        /* If the mutex was given back by an interrupt while the queue was
-         * locked then the mutex holder might now be NULL.  _RB_ Is this still
-         * needed as interrupts can no longer use mutexes? */
-        if( pxMutexHolder != NULL )
-        {
-            /* If the holder of the mutex has a priority below the priority of
-             * the task attempting to obtain the mutex then it will temporarily
-             * inherit the priority of the task attempting to obtain the mutex. */
-            if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
-            {
-                /* Adjust the mutex holder state to account for its new
-                 * priority.  Only reset the event list item value if the value is
-                 * not being used for anything else. */
-                if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
-                {
-                    listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                /* If the task being modified is in the ready state it will need
-                 * to be moved into a new list. */
-                if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
-                {
-                    if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-                    {
-                        /* It is known that the task is in its ready list so
-                         * there is no need to check again and the port level
-                         * reset macro can be called directly. */
-                        portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority );
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-
-                    /* Inherit the priority before being moved into the new list. */
-                    pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
-                    prvAddTaskToReadyList( pxMutexHolderTCB );
-                }
-                else
-                {
-                    /* Just inherit the priority. */
-                    pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
-                }
-
-                traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
-
-                /* Inheritance occurred. */
-                xReturn = pdTRUE;
-            }
-            else
-            {
-                if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
-                {
-                    /* The base priority of the mutex holder is lower than the
-                     * priority of the task attempting to take the mutex, but the
-                     * current priority of the mutex holder is not lower than the
-                     * priority of the task attempting to take the mutex.
-                     * Therefore the mutex holder must have already inherited a
-                     * priority, but inheritance would have occurred if that had
-                     * not been the case. */
-                    xReturn = pdTRUE;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        return xReturn;
-    }
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-    BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
-    {
-        TCB_t * const pxTCB = pxMutexHolder;
-        BaseType_t xReturn = pdFALSE;
-
-        if( pxMutexHolder != NULL )
-        {
-            /* A task can only have an inherited priority if it holds the mutex.
-             * If the mutex is held by a task then it cannot be given from an
-             * interrupt, and if a mutex is given by the holding task then it must
-             * be the running state task. */
-            configASSERT( pxTCB == pxCurrentTCB );
-            configASSERT( pxTCB->uxMutexesHeld );
-            ( pxTCB->uxMutexesHeld )--;
-
-            /* Has the holder of the mutex inherited the priority of another
-             * task? */
-            if( pxTCB->uxPriority != pxTCB->uxBasePriority )
-            {
-                /* Only disinherit if no other mutexes are held. */
-                if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
-                {
-                    /* A task can only have an inherited priority if it holds
-                     * the mutex.  If the mutex is held by a task then it cannot be
-                     * given from an interrupt, and if a mutex is given by the
-                     * holding task then it must be the running state task.  Remove
-                     * the holding task from the ready list. */
-                    if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-                    {
-                        portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-
-                    /* Disinherit the priority before adding the task into the
-                     * new  ready list. */
-                    traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
-                    pxTCB->uxPriority = pxTCB->uxBasePriority;
-
-                    /* Reset the event list item value.  It cannot be in use for
-                     * any other purpose if this task is running, and it must be
-                     * running to give back the mutex. */
-                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-                    prvAddTaskToReadyList( pxTCB );
-
-                    /* Return true to indicate that a context switch is required.
-                     * This is only actually required in the corner case whereby
-                     * multiple mutexes were held and the mutexes were given back
-                     * in an order different to that in which they were taken.
-                     * If a context switch did not occur when the first mutex was
-                     * returned, even if a task was waiting on it, then a context
-                     * switch should occur when the last mutex is returned whether
-                     * a task is waiting on it or not. */
-                    xReturn = pdTRUE;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        return xReturn;
-    }
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-    void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder,
-                                              UBaseType_t uxHighestPriorityWaitingTask )
-    {
-        TCB_t * const pxTCB = pxMutexHolder;
-        UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
-        const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
-
-        if( pxMutexHolder != NULL )
-        {
-            /* If pxMutexHolder is not NULL then the holder must hold at least
-             * one mutex. */
-            configASSERT( pxTCB->uxMutexesHeld );
-
-            /* Determine the priority to which the priority of the task that
-             * holds the mutex should be set.  This will be the greater of the
-             * holding task's base priority and the priority of the highest
-             * priority task that is waiting to obtain the mutex. */
-            if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
-            {
-                uxPriorityToUse = uxHighestPriorityWaitingTask;
-            }
-            else
-            {
-                uxPriorityToUse = pxTCB->uxBasePriority;
-            }
-
-            /* Does the priority need to change? */
-            if( pxTCB->uxPriority != uxPriorityToUse )
-            {
-                /* Only disinherit if no other mutexes are held.  This is a
-                 * simplification in the priority inheritance implementation.  If
-                 * the task that holds the mutex is also holding other mutexes then
-                 * the other mutexes may have caused the priority inheritance. */
-                if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
-                {
-                    /* If a task has timed out because it already holds the
-                     * mutex it was trying to obtain then it cannot of inherited
-                     * its own priority. */
-                    configASSERT( pxTCB != pxCurrentTCB );
-
-                    /* Disinherit the priority, remembering the previous
-                     * priority to facilitate determining the subject task's
-                     * state. */
-                    traceTASK_PRIORITY_DISINHERIT( pxTCB, uxPriorityToUse );
-                    uxPriorityUsedOnEntry = pxTCB->uxPriority;
-                    pxTCB->uxPriority = uxPriorityToUse;
-
-                    /* Only reset the event list item value if the value is not
-                     * being used for anything else. */
-                    if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
-                    {
-                        listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-
-                    /* If the running task is not the task that holds the mutex
-                     * then the task that holds the mutex could be in either the
-                     * Ready, Blocked or Suspended states.  Only remove the task
-                     * from its current state list if it is in the Ready state as
-                     * the task's priority is going to change and there is one
-                     * Ready list per priority. */
-                    if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
-                    {
-                        if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-                        {
-                            /* It is known that the task is in its ready list so
-                             * there is no need to check again and the port level
-                             * reset macro can be called directly. */
-                            portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-
-                        prvAddTaskToReadyList( pxTCB );
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( portCRITICAL_NESTING_IN_TCB == 1 )
-
-    void vTaskEnterCritical( void )
-    {
-        portDISABLE_INTERRUPTS();
-
-        if( xSchedulerRunning != pdFALSE )
-        {
-            ( pxCurrentTCB->uxCriticalNesting )++;
-
-            /* This is not the interrupt safe version of the enter critical
-             * function so  assert() if it is being called from an interrupt
-             * context.  Only API functions that end in "FromISR" can be used in an
-             * interrupt.  Only assert if the critical nesting count is 1 to
-             * protect against recursive calls if the assert function also uses a
-             * critical section. */
-            if( pxCurrentTCB->uxCriticalNesting == 1 )
-            {
-                portASSERT_IF_IN_ISR();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-
-#endif /* portCRITICAL_NESTING_IN_TCB */
-/*-----------------------------------------------------------*/
-
-#if ( portCRITICAL_NESTING_IN_TCB == 1 )
-
-    void vTaskExitCritical( void )
-    {
-        if( xSchedulerRunning != pdFALSE )
-        {
-            if( pxCurrentTCB->uxCriticalNesting > 0U )
-            {
-                ( pxCurrentTCB->uxCriticalNesting )--;
-
-                if( pxCurrentTCB->uxCriticalNesting == 0U )
-                {
-                    portENABLE_INTERRUPTS();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-
-#endif /* portCRITICAL_NESTING_IN_TCB */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
-
-    static char * prvWriteNameToBuffer( char * pcBuffer,
-                                        const char * pcTaskName )
-    {
-        size_t x;
-
-        /* Start by copying the entire string. */
-        strcpy( pcBuffer, pcTaskName );
-
-        /* Pad the end of the string with spaces to ensure columns line up when
-         * printed out. */
-        for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
-        {
-            pcBuffer[ x ] = ' ';
-        }
-
-        /* Terminate. */
-        pcBuffer[ x ] = ( char ) 0x00;
-
-        /* Return the new end of string. */
-        return &( pcBuffer[ x ] );
-    }
-
-#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-    void vTaskList( char * pcWriteBuffer )
-    {
-        TaskStatus_t * pxTaskStatusArray;
-        UBaseType_t uxArraySize, x;
-        char cStatus;
-
-        /*
-         * PLEASE NOTE:
-         *
-         * This function is provided for convenience only, and is used by many
-         * of the demo applications.  Do not consider it to be part of the
-         * scheduler.
-         *
-         * vTaskList() calls uxTaskGetSystemState(), then formats part of the
-         * uxTaskGetSystemState() output into a human readable table that
-         * displays task names, states and stack usage.
-         *
-         * vTaskList() has a dependency on the sprintf() C library function that
-         * might bloat the code size, use a lot of stack, and provide different
-         * results on different platforms.  An alternative, tiny, third party,
-         * and limited functionality implementation of sprintf() is provided in
-         * many of the FreeRTOS/Demo sub-directories in a file called
-         * printf-stdarg.c (note printf-stdarg.c does not provide a full
-         * snprintf() implementation!).
-         *
-         * It is recommended that production systems call uxTaskGetSystemState()
-         * directly to get access to raw stats data, rather than indirectly
-         * through a call to vTaskList().
-         */
-
-
-        /* Make sure the write buffer does not contain a string. */
-        *pcWriteBuffer = ( char ) 0x00;
-
-        /* Take a snapshot of the number of tasks in case it changes while this
-         * function is executing. */
-        uxArraySize = uxCurrentNumberOfTasks;
-
-        /* Allocate an array index for each task.  NOTE!  if
-         * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
-         * equate to NULL. */
-        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
-
-        if( pxTaskStatusArray != NULL )
-        {
-            /* Generate the (binary) data. */
-            uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
-
-            /* Create a human readable table from the binary data. */
-            for( x = 0; x < uxArraySize; x++ )
-            {
-                switch( pxTaskStatusArray[ x ].eCurrentState )
-                {
-                    case eRunning:
-                        cStatus = tskRUNNING_CHAR;
-                        break;
-
-                    case eReady:
-                        cStatus = tskREADY_CHAR;
-                        break;
-
-                    case eBlocked:
-                        cStatus = tskBLOCKED_CHAR;
-                        break;
-
-                    case eSuspended:
-                        cStatus = tskSUSPENDED_CHAR;
-                        break;
-
-                    case eDeleted:
-                        cStatus = tskDELETED_CHAR;
-                        break;
-
-                    case eInvalid: /* Fall through. */
-                    default:       /* Should not get here, but it is included
-                                    * to prevent static checking errors. */
-                        cStatus = ( char ) 0x00;
-                        break;
-                }
-
-                /* Write the task name to the string, padding with spaces so it
-                 * can be printed in tabular form more easily. */
-                pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
-
-                /* Write the rest of the string. */
-                sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
-                pcWriteBuffer += strlen( pcWriteBuffer );                                                                                                                                                                                                /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
-            }
-
-            /* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
-             * is 0 then vPortFree() will be #defined to nothing. */
-            vPortFree( pxTaskStatusArray );
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-
-#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*----------------------------------------------------------*/
-
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-    void vTaskGetRunTimeStats( char * pcWriteBuffer )
-    {
-        TaskStatus_t * pxTaskStatusArray;
-        UBaseType_t uxArraySize, x;
-        uint32_t ulTotalTime, ulStatsAsPercentage;
-
-        #if ( configUSE_TRACE_FACILITY != 1 )
-            {
-                #error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
-            }
-        #endif
-
-        /*
-         * PLEASE NOTE:
-         *
-         * This function is provided for convenience only, and is used by many
-         * of the demo applications.  Do not consider it to be part of the
-         * scheduler.
-         *
-         * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
-         * of the uxTaskGetSystemState() output into a human readable table that
-         * displays the amount of time each task has spent in the Running state
-         * in both absolute and percentage terms.
-         *
-         * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
-         * function that might bloat the code size, use a lot of stack, and
-         * provide different results on different platforms.  An alternative,
-         * tiny, third party, and limited functionality implementation of
-         * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
-         * a file called printf-stdarg.c (note printf-stdarg.c does not provide
-         * a full snprintf() implementation!).
-         *
-         * It is recommended that production systems call uxTaskGetSystemState()
-         * directly to get access to raw stats data, rather than indirectly
-         * through a call to vTaskGetRunTimeStats().
-         */
-
-        /* Make sure the write buffer does not contain a string. */
-        *pcWriteBuffer = ( char ) 0x00;
-
-        /* Take a snapshot of the number of tasks in case it changes while this
-         * function is executing. */
-        uxArraySize = uxCurrentNumberOfTasks;
-
-        /* Allocate an array index for each task.  NOTE!  If
-         * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
-         * equate to NULL. */
-        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
-
-        if( pxTaskStatusArray != NULL )
-        {
-            /* Generate the (binary) data. */
-            uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
-
-            /* For percentage calculations. */
-            ulTotalTime /= 100UL;
-
-            /* Avoid divide by zero errors. */
-            if( ulTotalTime > 0UL )
-            {
-                /* Create a human readable table from the binary data. */
-                for( x = 0; x < uxArraySize; x++ )
-                {
-                    /* What percentage of the total run time has the task used?
-                     * This will always be rounded down to the nearest integer.
-                     * ulTotalRunTimeDiv100 has already been divided by 100. */
-                    ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
-
-                    /* Write the task name to the string, padding with
-                     * spaces so it can be printed in tabular form more
-                     * easily. */
-                    pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
-
-                    if( ulStatsAsPercentage > 0UL )
-                    {
-                        #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
-                            {
-                                sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
-                            }
-                        #else
-                            {
-                                /* sizeof( int ) == sizeof( long ) so a smaller
-                                 * printf() library can be used. */
-                                sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
-                            }
-                        #endif
-                    }
-                    else
-                    {
-                        /* If the percentage is zero here then the task has
-                         * consumed less than 1% of the total run time. */
-                        #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
-                            {
-                                sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
-                            }
-                        #else
-                            {
-                                /* sizeof( int ) == sizeof( long ) so a smaller
-                                 * printf() library can be used. */
-                                sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
-                            }
-                        #endif
-                    }
-
-                    pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            /* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
-             * is 0 then vPortFree() will be #defined to nothing. */
-            vPortFree( pxTaskStatusArray );
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-
-#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-TickType_t uxTaskResetEventItemValue( void )
-{
-    TickType_t uxReturn;
-
-    uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
-
-    /* Reset the event list item to its normal value - so it can be used with
-     * queues and semaphores. */
-    listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
-    return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-    TaskHandle_t pvTaskIncrementMutexHeldCount( void )
-    {
-        /* If xSemaphoreCreateMutex() is called before any tasks have been created
-         * then pxCurrentTCB will be NULL. */
-        if( pxCurrentTCB != NULL )
-        {
-            ( pxCurrentTCB->uxMutexesHeld )++;
-        }
-
-        return pxCurrentTCB;
-    }
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-
-    uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWait,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait )
-    {
-        uint32_t ulReturn;
-
-        configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );
-
-        taskENTER_CRITICAL();
-        {
-            /* Only block if the notification count is not already non-zero. */
-            if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] == 0UL )
-            {
-                /* Mark this task as waiting for a notification. */
-                pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;
-
-                if( xTicksToWait > ( TickType_t ) 0 )
-                {
-                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-                    traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait );
-
-                    /* All ports are written to allow a yield in a critical
-                     * section (some will yield immediately, others wait until the
-                     * critical section exits) - but it is not something that
-                     * application code should ever do. */
-                    portYIELD_WITHIN_API();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        taskENTER_CRITICAL();
-        {
-            traceTASK_NOTIFY_TAKE( uxIndexToWait );
-            ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];
-
-            if( ulReturn != 0UL )
-            {
-                if( xClearCountOnExit != pdFALSE )
-                {
-                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = 0UL;
-                }
-                else
-                {
-                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = ulReturn - ( uint32_t ) 1;
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;
-        }
-        taskEXIT_CRITICAL();
-
-        return ulReturn;
-    }
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-
-    BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWait,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait )
-    {
-        BaseType_t xReturn;
-
-        configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );
-
-        taskENTER_CRITICAL();
-        {
-            /* Only block if a notification is not already pending. */
-            if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )
-            {
-                /* Clear bits in the task's notification value as bits may get
-                 * set  by the notifying task or interrupt.  This can be used to
-                 * clear the value to zero. */
-                pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnEntry;
-
-                /* Mark this task as waiting for a notification. */
-                pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;
-
-                if( xTicksToWait > ( TickType_t ) 0 )
-                {
-                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-                    traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait );
-
-                    /* All ports are written to allow a yield in a critical
-                     * section (some will yield immediately, others wait until the
-                     * critical section exits) - but it is not something that
-                     * application code should ever do. */
-                    portYIELD_WITHIN_API();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        taskENTER_CRITICAL();
-        {
-            traceTASK_NOTIFY_WAIT( uxIndexToWait );
-
-            if( pulNotificationValue != NULL )
-            {
-                /* Output the current notification value, which may or may not
-                 * have changed. */
-                *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];
-            }
-
-            /* If ucNotifyValue is set then either the task never entered the
-             * blocked state (because a notification was already pending) or the
-             * task unblocked because of a notification.  Otherwise the task
-             * unblocked because of a timeout. */
-            if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )
-            {
-                /* A notification was not received. */
-                xReturn = pdFALSE;
-            }
-            else
-            {
-                /* A notification was already pending or a notification was
-                 * received while the task was waiting. */
-                pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnExit;
-                xReturn = pdTRUE;
-            }
-
-            pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;
-        }
-        taskEXIT_CRITICAL();
-
-        return xReturn;
-    }
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-
-    BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue )
-    {
-        TCB_t * pxTCB;
-        BaseType_t xReturn = pdPASS;
-        uint8_t ucOriginalNotifyState;
-
-        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
-        configASSERT( xTaskToNotify );
-        pxTCB = xTaskToNotify;
-
-        taskENTER_CRITICAL();
-        {
-            if( pulPreviousNotificationValue != NULL )
-            {
-                *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];
-            }
-
-            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
-
-            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
-
-            switch( eAction )
-            {
-                case eSetBits:
-                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;
-                    break;
-
-                case eIncrement:
-                    ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
-                    break;
-
-                case eSetValueWithOverwrite:
-                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
-                    break;
-
-                case eSetValueWithoutOverwrite:
-
-                    if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
-                    {
-                        pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
-                    }
-                    else
-                    {
-                        /* The value could not be written to the task. */
-                        xReturn = pdFAIL;
-                    }
-
-                    break;
-
-                case eNoAction:
-
-                    /* The task is being notified without its notify value being
-                     * updated. */
-                    break;
-
-                default:
-
-                    /* Should not get here if all enums are handled.
-                     * Artificially force an assert by testing a value the
-                     * compiler can't assume is const. */
-                    configASSERT( xTickCount == ( TickType_t ) 0 );
-
-                    break;
-            }
-
-            traceTASK_NOTIFY( uxIndexToNotify );
-
-            /* If the task is in the blocked state specifically to wait for a
-             * notification then unblock it now. */
-            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
-            {
-                ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-                prvAddTaskToReadyList( pxTCB );
-
-                /* The task should not have been on an event list. */
-                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
-
-                #if ( configUSE_TICKLESS_IDLE != 0 )
-                    {
-                        /* If a task is blocked waiting for a notification then
-                         * xNextTaskUnblockTime might be set to the blocked task's time
-                         * out time.  If the task is unblocked for a reason other than
-                         * a timeout xNextTaskUnblockTime is normally left unchanged,
-                         * because it will automatically get reset to a new value when
-                         * the tick count equals xNextTaskUnblockTime.  However if
-                         * tickless idling is used it might be more important to enter
-                         * sleep mode at the earliest possible time - so reset
-                         * xNextTaskUnblockTime here to ensure it is updated at the
-                         * earliest possible time. */
-                        prvResetNextTaskUnblockTime();
-                    }
-                #endif
-
-                if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-                {
-                    /* The notified task has a priority above the currently
-                     * executing task so a yield is required. */
-                    taskYIELD_IF_USING_PREEMPTION();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        return xReturn;
-    }
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-
-    BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
-                                          UBaseType_t uxIndexToNotify,
-                                          uint32_t ulValue,
-                                          eNotifyAction eAction,
-                                          uint32_t * pulPreviousNotificationValue,
-                                          BaseType_t * pxHigherPriorityTaskWoken )
-    {
-        TCB_t * pxTCB;
-        uint8_t ucOriginalNotifyState;
-        BaseType_t xReturn = pdPASS;
-        UBaseType_t uxSavedInterruptStatus;
-
-        configASSERT( xTaskToNotify );
-        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
-
-        /* RTOS ports that support interrupt nesting have the concept of a
-         * maximum  system call (or maximum API call) interrupt priority.
-         * Interrupts that are  above the maximum system call priority are keep
-         * permanently enabled, even when the RTOS kernel is in a critical section,
-         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
-         * is defined in FreeRTOSConfig.h then
-         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-         * failure if a FreeRTOS API function is called from an interrupt that has
-         * been assigned a priority above the configured maximum system call
-         * priority.  Only FreeRTOS functions that end in FromISR can be called
-         * from interrupts  that have been assigned a priority at or (logically)
-         * below the maximum system call interrupt priority.  FreeRTOS maintains a
-         * separate interrupt safe API to ensure interrupt entry is as fast and as
-         * simple as possible.  More information (albeit Cortex-M specific) is
-         * provided on the following link:
-         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-        pxTCB = xTaskToNotify;
-
-        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-        {
-            if( pulPreviousNotificationValue != NULL )
-            {
-                *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];
-            }
-
-            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
-            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
-
-            switch( eAction )
-            {
-                case eSetBits:
-                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;
-                    break;
-
-                case eIncrement:
-                    ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
-                    break;
-
-                case eSetValueWithOverwrite:
-                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
-                    break;
-
-                case eSetValueWithoutOverwrite:
-
-                    if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
-                    {
-                        pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
-                    }
-                    else
-                    {
-                        /* The value could not be written to the task. */
-                        xReturn = pdFAIL;
-                    }
-
-                    break;
-
-                case eNoAction:
-
-                    /* The task is being notified without its notify value being
-                     * updated. */
-                    break;
-
-                default:
-
-                    /* Should not get here if all enums are handled.
-                     * Artificially force an assert by testing a value the
-                     * compiler can't assume is const. */
-                    configASSERT( xTickCount == ( TickType_t ) 0 );
-                    break;
-            }
-
-            traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify );
-
-            /* If the task is in the blocked state specifically to wait for a
-             * notification then unblock it now. */
-            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
-            {
-                /* The task should not have been on an event list. */
-                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
-
-                if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-                {
-                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-                    prvAddTaskToReadyList( pxTCB );
-                }
-                else
-                {
-                    /* The delayed and ready lists cannot be accessed, so hold
-                     * this task pending until the scheduler is resumed. */
-                    vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
-                }
-
-                if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-                {
-                    /* The notified task has a priority above the currently
-                     * executing task so a yield is required. */
-                    if( pxHigherPriorityTaskWoken != NULL )
-                    {
-                        *pxHigherPriorityTaskWoken = pdTRUE;
-                    }
-
-                    /* Mark that a yield is pending in case the user is not
-                     * using the "xHigherPriorityTaskWoken" parameter to an ISR
-                     * safe FreeRTOS function. */
-                    xYieldPending = pdTRUE;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        }
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-        return xReturn;
-    }
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-
-    void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,
-                                        UBaseType_t uxIndexToNotify,
-                                        BaseType_t * pxHigherPriorityTaskWoken )
-    {
-        TCB_t * pxTCB;
-        uint8_t ucOriginalNotifyState;
-        UBaseType_t uxSavedInterruptStatus;
-
-        configASSERT( xTaskToNotify );
-        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
-
-        /* RTOS ports that support interrupt nesting have the concept of a
-         * maximum  system call (or maximum API call) interrupt priority.
-         * Interrupts that are  above the maximum system call priority are keep
-         * permanently enabled, even when the RTOS kernel is in a critical section,
-         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
-         * is defined in FreeRTOSConfig.h then
-         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-         * failure if a FreeRTOS API function is called from an interrupt that has
-         * been assigned a priority above the configured maximum system call
-         * priority.  Only FreeRTOS functions that end in FromISR can be called
-         * from interrupts  that have been assigned a priority at or (logically)
-         * below the maximum system call interrupt priority.  FreeRTOS maintains a
-         * separate interrupt safe API to ensure interrupt entry is as fast and as
-         * simple as possible.  More information (albeit Cortex-M specific) is
-         * provided on the following link:
-         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-        pxTCB = xTaskToNotify;
-
-        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-        {
-            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
-            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
-
-            /* 'Giving' is equivalent to incrementing a count in a counting
-             * semaphore. */
-            ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
-
-            traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify );
-
-            /* If the task is in the blocked state specifically to wait for a
-             * notification then unblock it now. */
-            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
-            {
-                /* The task should not have been on an event list. */
-                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
-
-                if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-                {
-                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-                    prvAddTaskToReadyList( pxTCB );
-                }
-                else
-                {
-                    /* The delayed and ready lists cannot be accessed, so hold
-                     * this task pending until the scheduler is resumed. */
-                    vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
-                }
-
-                if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-                {
-                    /* The notified task has a priority above the currently
-                     * executing task so a yield is required. */
-                    if( pxHigherPriorityTaskWoken != NULL )
-                    {
-                        *pxHigherPriorityTaskWoken = pdTRUE;
-                    }
-
-                    /* Mark that a yield is pending in case the user is not
-                     * using the "xHigherPriorityTaskWoken" parameter in an ISR
-                     * safe FreeRTOS function. */
-                    xYieldPending = pdTRUE;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-        }
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-    }
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-
-    BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear )
-    {
-        TCB_t * pxTCB;
-        BaseType_t xReturn;
-
-        configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES );
-
-        /* If null is passed in here then it is the calling task that is having
-         * its notification state cleared. */
-        pxTCB = prvGetTCBFromHandle( xTask );
-
-        taskENTER_CRITICAL();
-        {
-            if( pxTCB->ucNotifyState[ uxIndexToClear ] == taskNOTIFICATION_RECEIVED )
-            {
-                pxTCB->ucNotifyState[ uxIndexToClear ] = taskNOT_WAITING_NOTIFICATION;
-                xReturn = pdPASS;
-            }
-            else
-            {
-                xReturn = pdFAIL;
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        return xReturn;
-    }
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-
-    uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear )
-    {
-        TCB_t * pxTCB;
-        uint32_t ulReturn;
-
-        /* If null is passed in here then it is the calling task that is having
-         * its notification state cleared. */
-        pxTCB = prvGetTCBFromHandle( xTask );
-
-        taskENTER_CRITICAL();
-        {
-            /* Return the notification as it was before the bits were cleared,
-             * then clear the bit mask. */
-            ulReturn = pxTCB->ulNotifiedValue[ uxIndexToClear ];
-            pxTCB->ulNotifiedValue[ uxIndexToClear ] &= ~ulBitsToClear;
-        }
-        taskEXIT_CRITICAL();
-
-        return ulReturn;
-    }
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
-
-    uint32_t ulTaskGetIdleRunTimeCounter( void )
-    {
-        return xIdleTaskHandle->ulRunTimeCounter;
-    }
-
-#endif
-/*-----------------------------------------------------------*/
-
-static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
-                                            const BaseType_t xCanBlockIndefinitely )
-{
-    TickType_t xTimeToWake;
-    const TickType_t xConstTickCount = xTickCount;
-
-    #if ( INCLUDE_xTaskAbortDelay == 1 )
-        {
-            /* About to enter a delayed list, so ensure the ucDelayAborted flag is
-             * reset to pdFALSE so it can be detected as having been set to pdTRUE
-             * when the task leaves the Blocked state. */
-            pxCurrentTCB->ucDelayAborted = pdFALSE;
-        }
-    #endif
-
-    /* Remove the task from the ready list before adding it to the blocked list
-     * as the same list item is used for both lists. */
-    if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-    {
-        /* The current task must be in a ready list, so there is no need to
-         * check, and the port reset macro can be called directly. */
-        portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
-    }
-    else
-    {
-        mtCOVERAGE_TEST_MARKER();
-    }
-
-    #if ( INCLUDE_vTaskSuspend == 1 )
-        {
-            if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
-            {
-                /* Add the task to the suspended task list instead of a delayed task
-                 * list to ensure it is not woken by a timing event.  It will block
-                 * indefinitely. */
-                vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
-            }
-            else
-            {
-                /* Calculate the time at which the task should be woken if the event
-                 * does not occur.  This may overflow but this doesn't matter, the
-                 * kernel will manage it correctly. */
-                xTimeToWake = xConstTickCount + xTicksToWait;
-
-                /* The list item will be inserted in wake time order. */
-                listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
-
-                if( xTimeToWake < xConstTickCount )
-                {
-                    /* Wake time has overflowed.  Place this item in the overflow
-                     * list. */
-                    vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
-                }
-                else
-                {
-                    /* The wake time has not overflowed, so the current block list
-                     * is used. */
-                    vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
-
-                    /* If the task entering the blocked state was placed at the
-                     * head of the list of blocked tasks then xNextTaskUnblockTime
-                     * needs to be updated too. */
-                    if( xTimeToWake < xNextTaskUnblockTime )
-                    {
-                        xNextTaskUnblockTime = xTimeToWake;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-            }
-        }
-    #else /* INCLUDE_vTaskSuspend */
-        {
-            /* Calculate the time at which the task should be woken if the event
-             * does not occur.  This may overflow but this doesn't matter, the kernel
-             * will manage it correctly. */
-            xTimeToWake = xConstTickCount + xTicksToWait;
-
-            /* The list item will be inserted in wake time order. */
-            listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
-
-            if( xTimeToWake < xConstTickCount )
-            {
-                /* Wake time has overflowed.  Place this item in the overflow list. */
-                vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
-            }
-            else
-            {
-                /* The wake time has not overflowed, so the current block list is used. */
-                vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
-
-                /* If the task entering the blocked state was placed at the head of the
-                 * list of blocked tasks then xNextTaskUnblockTime needs to be updated
-                 * too. */
-                if( xTimeToWake < xNextTaskUnblockTime )
-                {
-                    xNextTaskUnblockTime = xTimeToWake;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-
-            /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
-            ( void ) xCanBlockIndefinitely;
-        }
-    #endif /* INCLUDE_vTaskSuspend */
-}
-
-/* Code below here allows additional code to be inserted into this source file,
- * especially where access to file scope functions and data is needed (for example
- * when performing module tests). */
-
-#ifdef FREERTOS_MODULE_TEST
-    #include "tasks_test_access_functions.h"
-#endif
-
-
-#if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
-
-    #include "freertos_tasks_c_additions.h"
-
-    #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
-        static void freertos_tasks_c_additions_init( void )
-        {
-            FREERTOS_TASKS_C_ADDITIONS_INIT();
-        }
-    #endif
-
-#endif /* if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/timers.c b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/timers.c
deleted file mode 100644
index 3153341..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/freertos_kernel/timers.c
+++ /dev/null
@@ -1,1144 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.3 LTS Patch 2
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers.  That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-#include "timers.h"
-
-#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
-    #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
-#endif
-
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
- * for the header files above, but not in this file, in order to generate the
- * correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
-
-
-/* This entire source file will be skipped if the application is not configured
- * to include software timer functionality.  This #if is closed at the very bottom
- * of this file.  If you want to include software timer functionality then ensure
- * configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
-#if ( configUSE_TIMERS == 1 )
-
-/* Misc definitions. */
-    #define tmrNO_DELAY    ( TickType_t ) 0U
-
-/* The name assigned to the timer service task.  This can be overridden by
- * defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
-    #ifndef configTIMER_SERVICE_TASK_NAME
-        #define configTIMER_SERVICE_TASK_NAME    "Tmr Svc"
-    #endif
-
-/* Bit definitions used in the ucStatus member of a timer structure. */
-    #define tmrSTATUS_IS_ACTIVE                  ( ( uint8_t ) 0x01 )
-    #define tmrSTATUS_IS_STATICALLY_ALLOCATED    ( ( uint8_t ) 0x02 )
-    #define tmrSTATUS_IS_AUTORELOAD              ( ( uint8_t ) 0x04 )
-
-/* The definition of the timers themselves. */
-    typedef struct tmrTimerControl                  /* The old naming convention is used to prevent breaking kernel aware debuggers. */
-    {
-        const char * pcTimerName;                   /*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-        ListItem_t xTimerListItem;                  /*<< Standard linked list item as used by all kernel features for event management. */
-        TickType_t xTimerPeriodInTicks;             /*<< How quickly and often the timer expires. */
-        void * pvTimerID;                           /*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
-        TimerCallbackFunction_t pxCallbackFunction; /*<< The function that will be called when the timer expires. */
-        #if ( configUSE_TRACE_FACILITY == 1 )
-            UBaseType_t uxTimerNumber;              /*<< An ID assigned by trace tools such as FreeRTOS+Trace */
-        #endif
-        uint8_t ucStatus;                           /*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
-    } xTIMER;
-
-/* The old xTIMER name is maintained above then typedefed to the new Timer_t
- * name below to enable the use of older kernel aware debuggers. */
-    typedef xTIMER Timer_t;
-
-/* The definition of messages that can be sent and received on the timer queue.
- * Two types of message can be queued - messages that manipulate a software timer,
- * and messages that request the execution of a non-timer related callback.  The
- * two message types are defined in two separate structures, xTimerParametersType
- * and xCallbackParametersType respectively. */
-    typedef struct tmrTimerParameters
-    {
-        TickType_t xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
-        Timer_t * pxTimer;        /*<< The timer to which the command will be applied. */
-    } TimerParameter_t;
-
-
-    typedef struct tmrCallbackParameters
-    {
-        PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */
-        void * pvParameter1;                 /* << The value that will be used as the callback functions first parameter. */
-        uint32_t ulParameter2;               /* << The value that will be used as the callback functions second parameter. */
-    } CallbackParameters_t;
-
-/* The structure that contains the two message types, along with an identifier
- * that is used to determine which message type is valid. */
-    typedef struct tmrTimerQueueMessage
-    {
-        BaseType_t xMessageID; /*<< The command being sent to the timer service task. */
-        union
-        {
-            TimerParameter_t xTimerParameters;
-
-            /* Don't include xCallbackParameters if it is not going to be used as
-             * it makes the structure (and therefore the timer queue) larger. */
-            #if ( INCLUDE_xTimerPendFunctionCall == 1 )
-                CallbackParameters_t xCallbackParameters;
-            #endif /* INCLUDE_xTimerPendFunctionCall */
-        } u;
-    } DaemonTaskMessage_t;
-
-/*lint -save -e956 A manual analysis and inspection has been used to determine
- * which static variables must be declared volatile. */
-
-/* The list in which active timers are stored.  Timers are referenced in expire
- * time order, with the nearest expiry time at the front of the list.  Only the
- * timer service task is allowed to access these lists.
- * xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
- * breaks some kernel aware debuggers, and debuggers that reply on removing the
- * static qualifier. */
-    PRIVILEGED_DATA static List_t xActiveTimerList1;
-    PRIVILEGED_DATA static List_t xActiveTimerList2;
-    PRIVILEGED_DATA static List_t * pxCurrentTimerList;
-    PRIVILEGED_DATA static List_t * pxOverflowTimerList;
-
-/* A queue that is used to send commands to the timer service task. */
-    PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
-    PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
-
-/*lint -restore */
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the infrastructure used by the timer service task if it has not
- * been initialised already.
- */
-    static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
-
-/*
- * The timer service task (daemon).  Timer functionality is controlled by this
- * task.  Other tasks communicate with the timer service task using the
- * xTimerQueue queue.
- */
-    static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
-
-/*
- * Called by the timer service task to interpret and process a command it
- * received on the timer queue.
- */
-    static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
- * depending on if the expire time causes a timer counter overflow.
- */
-    static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer,
-                                                  const TickType_t xNextExpiryTime,
-                                                  const TickType_t xTimeNow,
-                                                  const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
-
-/*
- * An active timer has reached its expire time.  Reload the timer if it is an
- * auto-reload timer, then call its callback.
- */
-    static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,
-                                        const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
-
-/*
- * The tick count has overflowed.  Switch the timer lists after ensuring the
- * current timer list does not still reference some timers.
- */
-    static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
- * if a tick count overflow occurred since prvSampleTimeNow() was last called.
- */
-    static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
-
-/*
- * If the timer list contains any active timers then return the expire time of
- * the timer that will expire first and set *pxListWasEmpty to false.  If the
- * timer list does not contain any timers then return 0 and set *pxListWasEmpty
- * to pdTRUE.
- */
-    static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
-
-/*
- * If a timer has expired, process it.  Otherwise, block the timer service task
- * until either a timer does expire or a command is received.
- */
-    static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime,
-                                            BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
-
-/*
- * Called after a Timer_t structure has been allocated either statically or
- * dynamically to fill in the structure's members.
- */
-    static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                                       const TickType_t xTimerPeriodInTicks,
-                                       const UBaseType_t uxAutoReload,
-                                       void * const pvTimerID,
-                                       TimerCallbackFunction_t pxCallbackFunction,
-                                       Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-    BaseType_t xTimerCreateTimerTask( void )
-    {
-        BaseType_t xReturn = pdFAIL;
-
-        /* This function is called when the scheduler is started if
-         * configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
-         * timer service task has been created/initialised.  If timers have already
-         * been created then the initialisation will already have been performed. */
-        prvCheckForValidListAndQueue();
-
-        if( xTimerQueue != NULL )
-        {
-            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-                {
-                    StaticTask_t * pxTimerTaskTCBBuffer = NULL;
-                    StackType_t * pxTimerTaskStackBuffer = NULL;
-                    uint32_t ulTimerTaskStackSize;
-
-                    vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
-                    xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
-                                                          configTIMER_SERVICE_TASK_NAME,
-                                                          ulTimerTaskStackSize,
-                                                          NULL,
-                                                          ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
-                                                          pxTimerTaskStackBuffer,
-                                                          pxTimerTaskTCBBuffer );
-
-                    if( xTimerTaskHandle != NULL )
-                    {
-                        xReturn = pdPASS;
-                    }
-                }
-            #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-                {
-                    xReturn = xTaskCreate( prvTimerTask,
-                                           configTIMER_SERVICE_TASK_NAME,
-                                           configTIMER_TASK_STACK_DEPTH,
-                                           NULL,
-                                           ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
-                                           &xTimerTaskHandle );
-                }
-            #endif /* configSUPPORT_STATIC_ALLOCATION */
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        configASSERT( xReturn );
-        return xReturn;
-    }
-/*-----------------------------------------------------------*/
-
-    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-        TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                                    const TickType_t xTimerPeriodInTicks,
-                                    const UBaseType_t uxAutoReload,
-                                    void * const pvTimerID,
-                                    TimerCallbackFunction_t pxCallbackFunction )
-        {
-            Timer_t * pxNewTimer;
-
-            pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
-
-            if( pxNewTimer != NULL )
-            {
-                /* Status is thus far zero as the timer is not created statically
-                 * and has not been started.  The auto-reload bit may get set in
-                 * prvInitialiseNewTimer. */
-                pxNewTimer->ucStatus = 0x00;
-                prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
-            }
-
-            return pxNewTimer;
-        }
-
-    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-        TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                                          const TickType_t xTimerPeriodInTicks,
-                                          const UBaseType_t uxAutoReload,
-                                          void * const pvTimerID,
-                                          TimerCallbackFunction_t pxCallbackFunction,
-                                          StaticTimer_t * pxTimerBuffer )
-        {
-            Timer_t * pxNewTimer;
-
-            #if ( configASSERT_DEFINED == 1 )
-                {
-                    /* Sanity check that the size of the structure used to declare a
-                     * variable of type StaticTimer_t equals the size of the real timer
-                     * structure. */
-                    volatile size_t xSize = sizeof( StaticTimer_t );
-                    configASSERT( xSize == sizeof( Timer_t ) );
-                    ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
-                }
-            #endif /* configASSERT_DEFINED */
-
-            /* A pointer to a StaticTimer_t structure MUST be provided, use it. */
-            configASSERT( pxTimerBuffer );
-            pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
-
-            if( pxNewTimer != NULL )
-            {
-                /* Timers can be created statically or dynamically so note this
-                 * timer was created statically in case it is later deleted.  The
-                 * auto-reload bit may get set in prvInitialiseNewTimer(). */
-                pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
-
-                prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
-            }
-
-            return pxNewTimer;
-        }
-
-    #endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-    static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                                       const TickType_t xTimerPeriodInTicks,
-                                       const UBaseType_t uxAutoReload,
-                                       void * const pvTimerID,
-                                       TimerCallbackFunction_t pxCallbackFunction,
-                                       Timer_t * pxNewTimer )
-    {
-        /* 0 is not a valid value for xTimerPeriodInTicks. */
-        configASSERT( ( xTimerPeriodInTicks > 0 ) );
-
-        if( pxNewTimer != NULL )
-        {
-            /* Ensure the infrastructure used by the timer service task has been
-             * created/initialised. */
-            prvCheckForValidListAndQueue();
-
-            /* Initialise the timer structure members using the function
-             * parameters. */
-            pxNewTimer->pcTimerName = pcTimerName;
-            pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
-            pxNewTimer->pvTimerID = pvTimerID;
-            pxNewTimer->pxCallbackFunction = pxCallbackFunction;
-            vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
-
-            if( uxAutoReload != pdFALSE )
-            {
-                pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
-            }
-
-            traceTIMER_CREATE( pxNewTimer );
-        }
-    }
-/*-----------------------------------------------------------*/
-
-    BaseType_t xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait )
-    {
-        BaseType_t xReturn = pdFAIL;
-        DaemonTaskMessage_t xMessage;
-
-        configASSERT( xTimer );
-
-        /* Send a message to the timer service task to perform a particular action
-         * on a particular timer definition. */
-        if( xTimerQueue != NULL )
-        {
-            /* Send a command to the timer service task to start the xTimer timer. */
-            xMessage.xMessageID = xCommandID;
-            xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
-            xMessage.u.xTimerParameters.pxTimer = xTimer;
-
-            if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
-            {
-                if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
-                {
-                    xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
-                }
-                else
-                {
-                    xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
-                }
-            }
-            else
-            {
-                xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
-            }
-
-            traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        return xReturn;
-    }
-/*-----------------------------------------------------------*/
-
-    TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
-    {
-        /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
-         * started, then xTimerTaskHandle will be NULL. */
-        configASSERT( ( xTimerTaskHandle != NULL ) );
-        return xTimerTaskHandle;
-    }
-/*-----------------------------------------------------------*/
-
-    TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
-    {
-        Timer_t * pxTimer = xTimer;
-
-        configASSERT( xTimer );
-        return pxTimer->xTimerPeriodInTicks;
-    }
-/*-----------------------------------------------------------*/
-
-    void vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const UBaseType_t uxAutoReload )
-    {
-        Timer_t * pxTimer = xTimer;
-
-        configASSERT( xTimer );
-        taskENTER_CRITICAL();
-        {
-            if( uxAutoReload != pdFALSE )
-            {
-                pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
-            }
-            else
-            {
-                pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
-            }
-        }
-        taskEXIT_CRITICAL();
-    }
-/*-----------------------------------------------------------*/
-
-    UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
-    {
-        Timer_t * pxTimer = xTimer;
-        UBaseType_t uxReturn;
-
-        configASSERT( xTimer );
-        taskENTER_CRITICAL();
-        {
-            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 )
-            {
-                /* Not an auto-reload timer. */
-                uxReturn = ( UBaseType_t ) pdFALSE;
-            }
-            else
-            {
-                /* Is an auto-reload timer. */
-                uxReturn = ( UBaseType_t ) pdTRUE;
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        return uxReturn;
-    }
-/*-----------------------------------------------------------*/
-
-    TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
-    {
-        Timer_t * pxTimer = xTimer;
-        TickType_t xReturn;
-
-        configASSERT( xTimer );
-        xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
-        return xReturn;
-    }
-/*-----------------------------------------------------------*/
-
-    const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-    {
-        Timer_t * pxTimer = xTimer;
-
-        configASSERT( xTimer );
-        return pxTimer->pcTimerName;
-    }
-/*-----------------------------------------------------------*/
-
-    static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,
-                                        const TickType_t xTimeNow )
-    {
-        BaseType_t xResult;
-        Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
-        /* Remove the timer from the list of active timers.  A check has already
-         * been performed to ensure the list is not empty. */
-
-        ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
-        traceTIMER_EXPIRED( pxTimer );
-
-        /* If the timer is an auto-reload timer then calculate the next
-         * expiry time and re-insert the timer in the list of active timers. */
-        if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
-        {
-            /* The timer is inserted into a list using a time relative to anything
-             * other than the current time.  It will therefore be inserted into the
-             * correct list relative to the time this task thinks it is now. */
-            if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
-            {
-                /* The timer expired before it was added to the active timer
-                 * list.  Reload it now.  */
-                xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
-                configASSERT( xResult );
-                ( void ) xResult;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        /* Call the timer callback. */
-        pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
-    }
-/*-----------------------------------------------------------*/
-
-    static portTASK_FUNCTION( prvTimerTask, pvParameters )
-    {
-        TickType_t xNextExpireTime;
-        BaseType_t xListWasEmpty;
-
-        /* Just to avoid compiler warnings. */
-        ( void ) pvParameters;
-
-        #if ( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
-            {
-                extern void vApplicationDaemonTaskStartupHook( void );
-
-                /* Allow the application writer to execute some code in the context of
-                 * this task at the point the task starts executing.  This is useful if the
-                 * application includes initialisation code that would benefit from
-                 * executing after the scheduler has been started. */
-                vApplicationDaemonTaskStartupHook();
-            }
-        #endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
-
-        for( ; ; )
-        {
-            /* Query the timers list to see if it contains any timers, and if so,
-             * obtain the time at which the next timer will expire. */
-            xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
-
-            /* If a timer has expired, process it.  Otherwise, block this task
-             * until either a timer does expire, or a command is received. */
-            prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
-
-            /* Empty the command queue. */
-            prvProcessReceivedCommands();
-        }
-    }
-/*-----------------------------------------------------------*/
-
-    static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime,
-                                            BaseType_t xListWasEmpty )
-    {
-        TickType_t xTimeNow;
-        BaseType_t xTimerListsWereSwitched;
-
-        vTaskSuspendAll();
-        {
-            /* Obtain the time now to make an assessment as to whether the timer
-             * has expired or not.  If obtaining the time causes the lists to switch
-             * then don't process this timer as any timers that remained in the list
-             * when the lists were switched will have been processed within the
-             * prvSampleTimeNow() function. */
-            xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
-
-            if( xTimerListsWereSwitched == pdFALSE )
-            {
-                /* The tick count has not overflowed, has the timer expired? */
-                if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
-                {
-                    ( void ) xTaskResumeAll();
-                    prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
-                }
-                else
-                {
-                    /* The tick count has not overflowed, and the next expire
-                     * time has not been reached yet.  This task should therefore
-                     * block to wait for the next expire time or a command to be
-                     * received - whichever comes first.  The following line cannot
-                     * be reached unless xNextExpireTime > xTimeNow, except in the
-                     * case when the current timer list is empty. */
-                    if( xListWasEmpty != pdFALSE )
-                    {
-                        /* The current timer list is empty - is the overflow list
-                         * also empty? */
-                        xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
-                    }
-
-                    vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
-
-                    if( xTaskResumeAll() == pdFALSE )
-                    {
-                        /* Yield to wait for either a command to arrive, or the
-                         * block time to expire.  If a command arrived between the
-                         * critical section being exited and this yield then the yield
-                         * will not cause the task to block. */
-                        portYIELD_WITHIN_API();
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-            }
-            else
-            {
-                ( void ) xTaskResumeAll();
-            }
-        }
-    }
-/*-----------------------------------------------------------*/
-
-    static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
-    {
-        TickType_t xNextExpireTime;
-
-        /* Timers are listed in expiry time order, with the head of the list
-         * referencing the task that will expire first.  Obtain the time at which
-         * the timer with the nearest expiry time will expire.  If there are no
-         * active timers then just set the next expire time to 0.  That will cause
-         * this task to unblock when the tick count overflows, at which point the
-         * timer lists will be switched and the next expiry time can be
-         * re-assessed.  */
-        *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
-
-        if( *pxListWasEmpty == pdFALSE )
-        {
-            xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
-        }
-        else
-        {
-            /* Ensure the task unblocks when the tick count rolls over. */
-            xNextExpireTime = ( TickType_t ) 0U;
-        }
-
-        return xNextExpireTime;
-    }
-/*-----------------------------------------------------------*/
-
-    static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
-    {
-        TickType_t xTimeNow;
-        PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
-
-        xTimeNow = xTaskGetTickCount();
-
-        if( xTimeNow < xLastTime )
-        {
-            prvSwitchTimerLists();
-            *pxTimerListsWereSwitched = pdTRUE;
-        }
-        else
-        {
-            *pxTimerListsWereSwitched = pdFALSE;
-        }
-
-        xLastTime = xTimeNow;
-
-        return xTimeNow;
-    }
-/*-----------------------------------------------------------*/
-
-    static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer,
-                                                  const TickType_t xNextExpiryTime,
-                                                  const TickType_t xTimeNow,
-                                                  const TickType_t xCommandTime )
-    {
-        BaseType_t xProcessTimerNow = pdFALSE;
-
-        listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
-        listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
-
-        if( xNextExpiryTime <= xTimeNow )
-        {
-            /* Has the expiry time elapsed between the command to start/reset a
-             * timer was issued, and the time the command was processed? */
-            if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-            {
-                /* The time between a command being issued and the command being
-                 * processed actually exceeds the timers period.  */
-                xProcessTimerNow = pdTRUE;
-            }
-            else
-            {
-                vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
-            }
-        }
-        else
-        {
-            if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
-            {
-                /* If, since the command was issued, the tick count has overflowed
-                 * but the expiry time has not, then the timer must have already passed
-                 * its expiry time and should be processed immediately. */
-                xProcessTimerNow = pdTRUE;
-            }
-            else
-            {
-                vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
-            }
-        }
-
-        return xProcessTimerNow;
-    }
-/*-----------------------------------------------------------*/
-
-    static void prvProcessReceivedCommands( void )
-    {
-        DaemonTaskMessage_t xMessage;
-        Timer_t * pxTimer;
-        BaseType_t xTimerListsWereSwitched, xResult;
-        TickType_t xTimeNow;
-
-        while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
-        {
-            #if ( INCLUDE_xTimerPendFunctionCall == 1 )
-                {
-                    /* Negative commands are pended function calls rather than timer
-                     * commands. */
-                    if( xMessage.xMessageID < ( BaseType_t ) 0 )
-                    {
-                        const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
-
-                        /* The timer uses the xCallbackParameters member to request a
-                         * callback be executed.  Check the callback is not NULL. */
-                        configASSERT( pxCallback );
-
-                        /* Call the function. */
-                        pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-            #endif /* INCLUDE_xTimerPendFunctionCall */
-
-            /* Commands that are positive are timer commands rather than pended
-             * function calls. */
-            if( xMessage.xMessageID >= ( BaseType_t ) 0 )
-            {
-                /* The messages uses the xTimerParameters member to work on a
-                 * software timer. */
-                pxTimer = xMessage.u.xTimerParameters.pxTimer;
-
-                if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
-                {
-                    /* The timer is in a list, remove it. */
-                    ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-
-                traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
-
-                /* In this case the xTimerListsWereSwitched parameter is not used, but
-                 *  it must be present in the function call.  prvSampleTimeNow() must be
-                 *  called after the message is received from xTimerQueue so there is no
-                 *  possibility of a higher priority task adding a message to the message
-                 *  queue with a time that is ahead of the timer daemon task (because it
-                 *  pre-empted the timer daemon task after the xTimeNow value was set). */
-                xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
-
-                switch( xMessage.xMessageID )
-                {
-                    case tmrCOMMAND_START:
-                    case tmrCOMMAND_START_FROM_ISR:
-                    case tmrCOMMAND_RESET:
-                    case tmrCOMMAND_RESET_FROM_ISR:
-                    case tmrCOMMAND_START_DONT_TRACE:
-                        /* Start or restart a timer. */
-                        pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
-
-                        if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
-                        {
-                            /* The timer expired before it was added to the active
-                             * timer list.  Process it now. */
-                            pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
-                            traceTIMER_EXPIRED( pxTimer );
-
-                            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
-                            {
-                                xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
-                                configASSERT( xResult );
-                                ( void ) xResult;
-                            }
-                            else
-                            {
-                                mtCOVERAGE_TEST_MARKER();
-                            }
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-
-                        break;
-
-                    case tmrCOMMAND_STOP:
-                    case tmrCOMMAND_STOP_FROM_ISR:
-                        /* The timer has already been removed from the active list. */
-                        pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
-                        break;
-
-                    case tmrCOMMAND_CHANGE_PERIOD:
-                    case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR:
-                        pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
-                        pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
-                        configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
-
-                        /* The new period does not really have a reference, and can
-                         * be longer or shorter than the old one.  The command time is
-                         * therefore set to the current time, and as the period cannot
-                         * be zero the next expiry time can only be in the future,
-                         * meaning (unlike for the xTimerStart() case above) there is
-                         * no fail case that needs to be handled here. */
-                        ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
-                        break;
-
-                    case tmrCOMMAND_DELETE:
-                        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-                            {
-                                /* The timer has already been removed from the active list,
-                                 * just free up the memory if the memory was dynamically
-                                 * allocated. */
-                                if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
-                                {
-                                    vPortFree( pxTimer );
-                                }
-                                else
-                                {
-                                    pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
-                                }
-                            }
-                        #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
-                            {
-                                /* If dynamic allocation is not enabled, the memory
-                                 * could not have been dynamically allocated. So there is
-                                 * no need to free the memory - just mark the timer as
-                                 * "not active". */
-                                pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
-                            }
-                        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-                        break;
-
-                    default:
-                        /* Don't expect to get here. */
-                        break;
-                }
-            }
-        }
-    }
-/*-----------------------------------------------------------*/
-
-    static void prvSwitchTimerLists( void )
-    {
-        TickType_t xNextExpireTime, xReloadTime;
-        List_t * pxTemp;
-        Timer_t * pxTimer;
-        BaseType_t xResult;
-
-        /* The tick count has overflowed.  The timer lists must be switched.
-         * If there are any timers still referenced from the current timer list
-         * then they must have expired and should be processed before the lists
-         * are switched. */
-        while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
-        {
-            xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
-
-            /* Remove the timer from the list. */
-            pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-            ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
-            traceTIMER_EXPIRED( pxTimer );
-
-            /* Execute its callback, then send a command to restart the timer if
-             * it is an auto-reload timer.  It cannot be restarted here as the lists
-             * have not yet been switched. */
-            pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
-
-            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
-            {
-                /* Calculate the reload value, and if the reload value results in
-                 * the timer going into the same timer list then it has already expired
-                 * and the timer should be re-inserted into the current list so it is
-                 * processed again within this loop.  Otherwise a command should be sent
-                 * to restart the timer to ensure it is only inserted into a list after
-                 * the lists have been swapped. */
-                xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
-
-                if( xReloadTime > xNextExpireTime )
-                {
-                    listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
-                    listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
-                    vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
-                }
-                else
-                {
-                    xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
-                    configASSERT( xResult );
-                    ( void ) xResult;
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-
-        pxTemp = pxCurrentTimerList;
-        pxCurrentTimerList = pxOverflowTimerList;
-        pxOverflowTimerList = pxTemp;
-    }
-/*-----------------------------------------------------------*/
-
-    static void prvCheckForValidListAndQueue( void )
-    {
-        /* Check that the list from which active timers are referenced, and the
-         * queue used to communicate with the timer service, have been
-         * initialised. */
-        taskENTER_CRITICAL();
-        {
-            if( xTimerQueue == NULL )
-            {
-                vListInitialise( &xActiveTimerList1 );
-                vListInitialise( &xActiveTimerList2 );
-                pxCurrentTimerList = &xActiveTimerList1;
-                pxOverflowTimerList = &xActiveTimerList2;
-
-                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-                    {
-                        /* The timer queue is allocated statically in case
-                         * configSUPPORT_DYNAMIC_ALLOCATION is 0. */
-                        PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue;                                                                          /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
-                        PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
-
-                        xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
-                    }
-                #else
-                    {
-                        xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
-                    }
-                #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-
-                #if ( configQUEUE_REGISTRY_SIZE > 0 )
-                    {
-                        if( xTimerQueue != NULL )
-                        {
-                            vQueueAddToRegistry( xTimerQueue, "TmrQ" );
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                #endif /* configQUEUE_REGISTRY_SIZE */
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        taskEXIT_CRITICAL();
-    }
-/*-----------------------------------------------------------*/
-
-    BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
-    {
-        BaseType_t xReturn;
-        Timer_t * pxTimer = xTimer;
-
-        configASSERT( xTimer );
-
-        /* Is the timer in the list of active timers? */
-        taskENTER_CRITICAL();
-        {
-            if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
-            {
-                xReturn = pdFALSE;
-            }
-            else
-            {
-                xReturn = pdTRUE;
-            }
-        }
-        taskEXIT_CRITICAL();
-
-        return xReturn;
-    } /*lint !e818 Can't be pointer to const due to the typedef. */
-/*-----------------------------------------------------------*/
-
-    void * pvTimerGetTimerID( const TimerHandle_t xTimer )
-    {
-        Timer_t * const pxTimer = xTimer;
-        void * pvReturn;
-
-        configASSERT( xTimer );
-
-        taskENTER_CRITICAL();
-        {
-            pvReturn = pxTimer->pvTimerID;
-        }
-        taskEXIT_CRITICAL();
-
-        return pvReturn;
-    }
-/*-----------------------------------------------------------*/
-
-    void vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID )
-    {
-        Timer_t * const pxTimer = xTimer;
-
-        configASSERT( xTimer );
-
-        taskENTER_CRITICAL();
-        {
-            pxTimer->pvTimerID = pvNewID;
-        }
-        taskEXIT_CRITICAL();
-    }
-/*-----------------------------------------------------------*/
-
-    #if ( INCLUDE_xTimerPendFunctionCall == 1 )
-
-        BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
-                                                  void * pvParameter1,
-                                                  uint32_t ulParameter2,
-                                                  BaseType_t * pxHigherPriorityTaskWoken )
-        {
-            DaemonTaskMessage_t xMessage;
-            BaseType_t xReturn;
-
-            /* Complete the message with the function parameters and post it to the
-             * daemon task. */
-            xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
-            xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
-            xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
-            xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
-
-            xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
-
-            tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
-
-            return xReturn;
-        }
-
-    #endif /* INCLUDE_xTimerPendFunctionCall */
-/*-----------------------------------------------------------*/
-
-    #if ( INCLUDE_xTimerPendFunctionCall == 1 )
-
-        BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
-                                           void * pvParameter1,
-                                           uint32_t ulParameter2,
-                                           TickType_t xTicksToWait )
-        {
-            DaemonTaskMessage_t xMessage;
-            BaseType_t xReturn;
-
-            /* This function can only be called after a timer has been created or
-             * after the scheduler has been started because, until then, the timer
-             * queue does not exist. */
-            configASSERT( xTimerQueue );
-
-            /* Complete the message with the function parameters and post it to the
-             * daemon task. */
-            xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
-            xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
-            xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
-            xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
-
-            xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
-
-            tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
-
-            return xReturn;
-        }
-
-    #endif /* INCLUDE_xTimerPendFunctionCall */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TRACE_FACILITY == 1 )
-
-        UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
-        {
-            return ( ( Timer_t * ) xTimer )->uxTimerNumber;
-        }
-
-    #endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TRACE_FACILITY == 1 )
-
-        void vTimerSetTimerNumber( TimerHandle_t xTimer,
-                                   UBaseType_t uxTimerNumber )
-        {
-            ( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
-        }
-
-    #endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-/* This entire source file will be skipped if the application is not configured
- * to include software timer functionality.  If you want to include software timer
- * functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
-#endif /* configUSE_TIMERS == 1 */
diff --git a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/template/ARM_CM33/FreeRTOSConfig.h b/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/template/ARM_CM33/FreeRTOSConfig.h
deleted file mode 100644
index 8f4fa23..0000000
--- a/nxpvee-mimxrt595-evk-round-bsp/sdk_overlay/rtos/freertos/template/ARM_CM33/FreeRTOSConfig.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://aws.amazon.com/freertos
- * http://www.FreeRTOS.org
- */
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
-    /* Clock manager provides in this variable system core clock frequency */
-    #include 
-    extern uint32_t SystemCoreClock;
-#endif
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *
- * See http://www.freertos.org/a00110.html.
- *----------------------------------------------------------*/
-#ifndef configENABLE_FPU
-  #define configENABLE_FPU                      0
-#endif
-#ifndef configENABLE_MPU
-  #define configENABLE_MPU                      0
-#endif
-#ifndef configENABLE_TRUSTZONE
-  #define configENABLE_TRUSTZONE                0
-#endif
-#ifndef configRUN_FREERTOS_SECURE_ONLY
-  #define configRUN_FREERTOS_SECURE_ONLY        1
-#endif
-
-#define configUSE_PREEMPTION                    1
-#define configUSE_TICKLESS_IDLE                 0
-#define configCPU_CLOCK_HZ                      (SystemCoreClock)
-#define configTICK_RATE_HZ                      ((TickType_t)200)
-#define configMAX_PRIORITIES                    5
-#define configMINIMAL_STACK_SIZE                ((unsigned short)90)
-#define configMAX_TASK_NAME_LEN                 20
-#define configUSE_16_BIT_TICKS                  0
-#define configIDLE_SHOULD_YIELD                 1
-#define configUSE_TASK_NOTIFICATIONS            1
-#define configUSE_MUTEXES                       1
-#define configUSE_RECURSIVE_MUTEXES             1
-#define configUSE_COUNTING_SEMAPHORES           1
-#define configUSE_ALTERNATIVE_API               0 /* Deprecated! */
-#define configQUEUE_REGISTRY_SIZE               8
-#define configUSE_QUEUE_SETS                    0
-#define configUSE_TIME_SLICING                  0
-#define configUSE_NEWLIB_REENTRANT              0
-#define configENABLE_BACKWARD_COMPATIBILITY     1
-#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
-#define configUSE_APPLICATION_TASK_TAG          0
-
-/* Memory allocation related definitions. */
-#define configSUPPORT_STATIC_ALLOCATION         0
-#define configSUPPORT_DYNAMIC_ALLOCATION        1
-#define configTOTAL_HEAP_SIZE                   ((size_t)(10240))
-#define configAPPLICATION_ALLOCATED_HEAP        0
-
-/* Hook function related definitions. */
-#define configUSE_IDLE_HOOK                     0
-#define configUSE_TICK_HOOK                     0
-#define configCHECK_FOR_STACK_OVERFLOW          0
-#define configUSE_MALLOC_FAILED_HOOK            0
-#define configUSE_DAEMON_TASK_STARTUP_HOOK      0
-
-/* Run time and task stats gathering related definitions. */
-#define configGENERATE_RUN_TIME_STATS           0
-#define configUSE_TRACE_FACILITY                1
-#define configUSE_STATS_FORMATTING_FUNCTIONS    0
-
-/* Co-routine related definitions. */
-#define configUSE_CO_ROUTINES                   0
-#define configMAX_CO_ROUTINE_PRIORITIES         2
-
-/* Software timer related definitions. */
-#define configUSE_TIMERS                        1
-#define configTIMER_TASK_PRIORITY               (configMAX_PRIORITIES - 1)
-#define configTIMER_QUEUE_LENGTH                10
-#define configTIMER_TASK_STACK_DEPTH            (configMINIMAL_STACK_SIZE * 2)
-
-/* Define to trap errors during development. */
-#define configASSERT(x) if((x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
-
-/* Optional functions - most linkers will remove unused functions anyway. */
-#define INCLUDE_vTaskPrioritySet                1
-#define INCLUDE_uxTaskPriorityGet               1
-#define INCLUDE_vTaskDelete                     1
-#define INCLUDE_vTaskSuspend                    1
-#define INCLUDE_vTaskDelayUntil                 1
-#define INCLUDE_vTaskDelay                      1
-#define INCLUDE_xTaskGetSchedulerState          1
-#define INCLUDE_xTaskGetCurrentTaskHandle       1
-#define INCLUDE_uxTaskGetStackHighWaterMark     0
-#define INCLUDE_xTaskGetIdleTaskHandle          0
-#define INCLUDE_eTaskGetState                   0
-#define INCLUDE_xTimerPendFunctionCall          1
-#define INCLUDE_xTaskAbortDelay                 0
-#define INCLUDE_xTaskGetHandle                  0
-#define INCLUDE_xTaskResumeFromISR              1
-
-#ifdef __NVIC_PRIO_BITS
-/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
-#define configPRIO_BITS __NVIC_PRIO_BITS
-#else
-#define configPRIO_BITS 4 /* 15 priority levels */
-#endif
-
-/* The lowest interrupt priority that can be used in a call to a "set priority"
-function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
-
-/* The highest interrupt priority that can be used by any interrupt service
-routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
-
-/* Interrupt priorities used by the kernel port layer itself.  These are generic
-to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
-
-/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
-standard names. */
-#define vPortSVCHandler SVC_Handler
-#define xPortPendSVHandler PendSV_Handler
-#define xPortSysTickHandler SysTick_Handler
-
-#endif /* FREERTOS_CONFIG_H */
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/CHANGELOG.md b/nxpvee-mimxrt595-evk-round-configuration/build/CHANGELOG.md
deleted file mode 100644
index da75565..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/build/CHANGELOG.md
+++ /dev/null
@@ -1,106 +0,0 @@
-# Changelog
-
-All notable changes to this project will be documented in this file.
-
-The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
-and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
-
-## [2.1.0] - [unreleased]
-
-This version requires SDK `5.8.0` or higher.
-
-### Added
-
-- Add support for Architecture version `8.1.0`.
-  The _Multi Applications_ (`kf`) module has been removed and replaced by the property `com.microej.runtime.capability`.
-  This property can be set either in the configuration project (in `mjvm/mjvm.properties` file) or as an MMM property to override the configuration project.
-  The MMM property `com.microej.platformbuilder.module.multi.enabled` is deprecated but still supported when `com.microej.runtime.capability` is not set.
-- Add execution of artifact checker for `CHANGELOG.rst` and `LICENSE.txt` (`README.rst` is ignored).
-- Add publication of `NOTICE.txt` and `MICROEJ_SDK_EULA.txt` files. The notice describes the list of files licensed under SDK EULA.
-- Add include/exclude pattern when copying the BSP project.
-- Rename Platform to VEE Port in module.ivy.
-
-### Fixed
-
-- Fix execution of artifact checker on `-configuration` project instead of `-fp` project.
-- Fix build and run Linux scripts end-of-line (EOL) characters if the VEE port was built on Windows.
-- Fix update in some cases of The _Multi Applications_ (`kf`) module in the `.platform` file (only when `com.microej.platformbuilder.module.multi.enabled` was set to `true`).
-
-## [2.0.0] - [2023-06-29]
-
-### Added
-
-- Add support to execute the optional RIP scripts that configure the RIP's module during the build of the VEE Port (`build/autoConfigurationXXX.xml` or `build/platform-XXX.ant`).
-
-### Changed
-
-- Separate files required for SDK version `5.x` from files required for Architecture version `7.x`.
-
-### Fixed
-
-- Fix new empty line generated in  the `.platform` file when `com.microej.platformbuilder.module.multi.enabled` is set to `true`. This prevents a useless change in the VCS.
-
-## [1.4.0] - [2021-07-07]
-
-### Changed
-
-- Copy the files LICENSE.txt, README.rst, RELEASE_NOTES.rst and CHANGELOG.rst to the artifact published if the files are available.
-- Plug the artifact checker to allow the check the artifact published (disabled by default).
-
-## [1.3.1] - [2021-06-30]
-
-### Changed
-
-- Moved `module.ivy` examples of dependencies in comments with description
-
-## [1.3.0] - [2021-05-11]
-
-### Added
-
-- Add MicroEJ SDK tool to deploy an executable file on device using the BSP run script
-- Add an option to check if the platform project exists
-
-### Changed
-
-- Execute bash script file (`.sh`) with `/bin/bash`.  This ensure the build and run scripts are properly executed regardless of their file permissions.
-- Use placeholders for platform name and platform version in `default.platform` to make it obvious it is generated automatically.
-
-### Fixed
-
-- Execute `.bat` scripts on Windows 11 instead of `.sh` scripts.
-
-## [1.2.0] - 2021-04-16
-
-### Added
-
-- Add `default.platform` to allow any empty project to be converted as a Platform project (no longer need to import a MicroEJ Architecture first).
-- Set default module version to `0.1.0` as other MicroEJ SDK skeletons.
-- Set default module organization to `com.mycompany` as other MicroEJ SDK skeletons.
-- Use a new private configuration `embedded` as the default for the platform dependencies.  This prevents an instance of "Too many loaded Platforms" error in `platform-loader`.
-
-### Fixed
-
-- Fix documentation in `bsp.properties`:
-
-  - The variable `${project.prefix}` is no longer supported.
-  - The variables `*.relative.dir` are relative to the BSP root directory.
-
-- Fix execution of `run.[bat|sh]` in the directory where is defined `application.out`.
-- Fix module configurations for correct Platform module import (especially in a module repository)
-- Fix module build crash when no README file is declared (optional)
-
-## [1.1.0] - 2021-01-08
-
-### Changed
-
- - Added scripts and `module.ivy` file for Platform module build and publication.
-
-## [1.0.0] - 2020-06-24
-
-### Added
-
-  - Initial version with scripts for BSP connection.
-  
----
-_Copyright 2020-2023 MicroEJ Corp. All rights reserved._
-_Use of this source code is governed by a BSD-style license that can be found with this software._
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins.ant b/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins.ant
deleted file mode 100644
index 0a8af6c..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins.ant
+++ /dev/null
@@ -1,25 +0,0 @@
-
-
-
-	
-
-	
-	
-	
-	
-	
-	
-		
-			
-		
-	
-
-
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployInBSP.xml b/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployInBSP.xml
deleted file mode 100644
index 7f995a6..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployInBSP.xml
+++ /dev/null
@@ -1,243 +0,0 @@
-
-
-
-
-	
-	
-	
-	
-	
-	
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-			
-			    
-			
-		
-				
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-
-		
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-				
-		
-
-	
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-			
-				
-					
-					 	
-					
-			   	
-			
-		
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-		
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-			
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-				
-
-	
-		
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-	
-
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployInBSPCommon.xml b/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployInBSPCommon.xml
deleted file mode 100644
index 12dbc9b..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployInBSPCommon.xml
+++ /dev/null
@@ -1,61 +0,0 @@
-
-
-
-
-	
-	
-		
-		
-		
-			
-						
-			
-				
-					 
-					 
-					 
-					 
-				
-			
-
-			
-			
-				
-					 
-					 
-					 
-				
-				
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-			
-				
-					
-				         
-						
-							
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-					
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-				 
-			
-			
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-
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployToolBSPRun.microejTool b/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployToolBSPRun.microejTool
deleted file mode 100644
index 8e7a1af..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployToolBSPRun.microejTool
+++ /dev/null
@@ -1,67 +0,0 @@
-
-
-
-	
-
-	
-	
-
-	
-
-	
-	
-	
-	
-	
-	
-
-	
-		
-			
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-				
-					
-						
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-        
-        
-        
-          
-          
-        
-
-		
-	
-
-
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployToolBSPRun.microejTool.properties b/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployToolBSPRun.microejTool.properties
deleted file mode 100644
index 96e28ff..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployToolBSPRun.microejTool.properties
+++ /dev/null
@@ -1,8 +0,0 @@
-# 
-# Properties file
-#
-# Copyright 2021 MicroEJ Corp. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be found with this software.
-#
-name=Deploy with the BSP run script
-description=Deploy an executable file on device using the BSP run script (run.[bat|sh]). 
\ No newline at end of file
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployToolBSPRunExtension.jar b/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployToolBSPRunExtension.jar
deleted file mode 100644
index 49d5ce4..0000000
Binary files a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/deployToolBSPRunExtension.jar and /dev/null differ
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/fullLink.microejLaunch b/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/fullLink.microejLaunch
deleted file mode 100644
index d78e76e..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/fullLink.microejLaunch
+++ /dev/null
@@ -1,14 +0,0 @@
-
-
-
-
-	
-	
-	
-
-
\ No newline at end of file
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/fullLink.microejLaunch.properties b/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/fullLink.microejLaunch.properties
deleted file mode 100644
index 0eba8da..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/fullLink.microejLaunch.properties
+++ /dev/null
@@ -1,10 +0,0 @@
-# properties
-	
-# Copyright 2015-2020 MicroEJ Corp. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be found with this software.
-
-target=board
-name=Build & Deploy
-description=The application is generated, linked and deployed.
-default=true
-standalone=true
\ No newline at end of file
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/init-bsp/init.xml b/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/init-bsp/init.xml
deleted file mode 100644
index 4c2f24a..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/init-bsp/init.xml
+++ /dev/null
@@ -1,147 +0,0 @@
-
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\ No newline at end of file
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/init-license-checker/init.xml b/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/init-license-checker/init.xml
deleted file mode 100644
index 6a6b0a9..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/scripts/init-license-checker/init.xml
+++ /dev/null
@@ -1,29 +0,0 @@
-
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\ No newline at end of file
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/tools/license-checker.jar b/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/tools/license-checker.jar
deleted file mode 100644
index 9ccfff2..0000000
Binary files a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/tools/license-checker.jar and /dev/null differ
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/workbenchExtension_launchScriptFramework.jar b/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/workbenchExtension_launchScriptFramework.jar
deleted file mode 100644
index 8d5ea45..0000000
Binary files a/nxpvee-mimxrt595-evk-round-configuration/build/module/module-dropins/workbenchExtension_launchScriptFramework.jar and /dev/null differ
diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/platform/platform-deploy.ant b/nxpvee-mimxrt595-evk-round-configuration/build/platform/platform-deploy.ant
deleted file mode 100644
index e0cf045..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/build/platform/platform-deploy.ant
+++ /dev/null
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-
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diff --git a/nxpvee-mimxrt595-evk-round-configuration/build/platform/platform-kf.ant b/nxpvee-mimxrt595-evk-round-configuration/build/platform/platform-kf.ant
deleted file mode 100644
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--- a/nxpvee-mimxrt595-evk-round-configuration/build/platform/platform-kf.ant
+++ /dev/null
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diff --git a/nxpvee-mimxrt595-evk-round-configuration/imxrt595evk.platform b/nxpvee-mimxrt595-evk-round-configuration/imxrt595evk.platform
deleted file mode 100644
index b4a4004..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/imxrt595evk.platform
+++ /dev/null
@@ -1,41 +0,0 @@
-
-        
-    
-            
-    
-    
-            
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-            
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-                        
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diff --git a/nxpvee-mimxrt595-evk-round-configuration/mjvm/mjvm.properties b/nxpvee-mimxrt595-evk-round-configuration/mjvm/mjvm.properties
deleted file mode 100644
index 9cc9aa1..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/mjvm/mjvm.properties
+++ /dev/null
@@ -1,4 +0,0 @@
-# Copyright 2022 MicroEJ Corp. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be found with this software.
-
-sni.nonimmortal.access=true
diff --git a/nxpvee-mimxrt595-evk-round-configuration/module.ivy b/nxpvee-mimxrt595-evk-round-configuration/module.ivy
deleted file mode 100644
index 0496a94..0000000
--- a/nxpvee-mimxrt595-evk-round-configuration/module.ivy
+++ /dev/null
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diff --git a/nxpvee-mimxrt595-evk-round-fp/module.ivy b/nxpvee-mimxrt595-evk-round-fp/module.ivy
deleted file mode 100644
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--- a/nxpvee-mimxrt595-evk-round-fp/module.ivy
+++ /dev/null
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diff --git a/nxpvee-mimxrt595-evk-round-imageGenerator/module.ivy b/nxpvee-mimxrt595-evk-round-imageGenerator/module.ivy
deleted file mode 100644
index 40a465e..0000000
--- a/nxpvee-mimxrt595-evk-round-imageGenerator/module.ivy
+++ /dev/null
@@ -1,34 +0,0 @@
-
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diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/CHANGELOG.rst b/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/CHANGELOG.rst
deleted file mode 100644
index 06aad73..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/CHANGELOG.rst
+++ /dev/null
@@ -1,110 +0,0 @@
-CHANGELOG
-=========
-
-The format is based on `Keep a
-Changelog `__, and this project
-adheres to `Semantic
-Versioning `__.
-
-.. _310--Unreleased:
-
-[3.1.0] - 2022-07-23
---------------------
-
-Added
-~~~~~
-
-- Add check for ``LLMJVM_IMPL_setApplicationTime``.
-- Test Thread.sleep() with max number of milliseconds (Long.MAX_VALUE) does not cause an infinite loop in the MicroEJ Core due to time conversion overflow.
-- Add check for ``LLMJVM_IMPL_getCurrentTime``, which should not go back in time.
-- Add check for C malloc heap configuration which can be used when parsing float.
-- Add check of ``LLMJVM_IMPL_scheduleRequest``, ``LLMJVM_IMPL_getCurrentTime``, and ``LLMJVM_IMPL_getTimeNanos`` precision
-
-Changed
-~~~~~~~
-
-- Split floating-point tests into 3 JUnit tests (FPU, parser, formatter)
-  to allow for fine-grained ignored tests list.
-- Reformat to use standard MicroEJ Test Suite flow.
-- Add tolerance on floating-point parsing.
-
-Fixed
-~~~~~
-
-- Fix assertions to conform with JUnit semantic of expected/actual.
-
-.. _302--2021-04-14:
-
-[3.0.2] - 2021-04-14
---------------------
-
-Fixed
-~~~~~
-
-- Ensure an error message is shown when the Round Robin test fails.
-
-.. _301--2021-02-12:
-
-[3.0.1] - 2021-02-12
---------------------
-
-Fixed
-~~~~~
-
-- Removed a comment about ``testFloat`` and ``testDouble`` functions
-  in ``MicroEJCoreValidation.java``.  This is documented in the README
-  of the project.
-
-.. _300---2020-06-02:
-
-[3.0.0] - 2020-06-02
---------------------
-
-Changed
-~~~~~~~
-
--  Previous test functions are now JUnit test cases
-
-.. _240---2019-12-18:
-
-[2.4.0] - 2019-12-18
---------------------
-
-Added
-~~~~~
-
--  New floating-point related tests: parse/toString for float/double
-
-.. _changed-1:
-
-Changed
-~~~~~~~
-
--  Review round robin check test
--  Update license
-
-.. _230---2019-10-01:
-
-[2.3.0] - 2019-10-01
---------------------
-
-Initial revision with Changelog.
-
-.. _added-1:
-
-Added
-~~~~~
-
--  Property ``MJVMPortValidation.clock.seconds`` to configure the time
-   in seconds of the visible clock test (default to 10s).
-
-.. _100---2017-09-29:
-
-[1.0.0] - 2017-09-29
---------------------
-
-Features : - Initial revision
-
-..
-    Copyright 2020-2022 MicroEJ Corp. All rights reserved.
-    Use of this source code is governed by a BSD-style license that can be found with this software.
diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/README.rst b/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/README.rst
deleted file mode 100644
index 3412856..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/README.rst
+++ /dev/null
@@ -1,182 +0,0 @@
-MicroEJ Core Validation
-=======================
-
-Overview
---------
-
-This project contains test cases aimed at validating the correct runtime execution 
-of a MicroEJ Platform connected to a Board Support Package (BSP).
- 
-Tests are written as JUnit test cases, thus the main entry point is automatically generated by MicroEJ SDK.
-
-Tests can be launched:
-
--  as a standard Application by using a local launcher.
--  as a Platform Test Suite by building the module.
-
-Requirements
-------------
-
--  MicroEJ SDK version ``5.1.0`` (included in MicroEJ SDK dist. ``19.05``).
--  MicroEJ Platform built from a MicroEJ Architecture version ``7.0.0`` or higher.
--  See Platform Test Suites `documentation <../../README.rst>`_.
-
-Usage
------
-
-Launcher Mode
-~~~~~~~~~~~~~
-
-In MicroEJ SDK,
-
--  Select ``Run > Run Configurations...``. A launcher named
-   ``java-testsuite-runner-core`` should be available under
-   ``MicroEJ Application``.
-   
--  In ``Execution`` tab, select the target MicroEJ Platform.
-
--  Click on ``Run`` button to compile the MicroEJ Application.
-
--  Before linking the application against the MicroEJ Platform, add the
-   following code in your BSP to test the FPU configuration:
-
-.. code:: c
-
-   #include "sni.h"
-   jfloat Java_com_microej_core_tests_MicroejCoreValidation_testFloat (jfloat a, jfloat b) {return a * b;}
-   jdouble Java_com_microej_core_tests_MicroejCoreValidation_testDouble (jdouble a, jdouble b) {return a * b;}
-
--  For a best result in the Java Round Robin test, disable all the C
-   native tasks except the MicroEJ task.
-
--  Link the BSP project with the MicroEJ Application (``microejapp.o``), 
-   the MicroEJ Platform runtime (``microejruntime.a``) and the MicroEJ Platform header files (``*.h``).
-
--  Once all the tests have passed successfully, MicroEJ Core is validated.
-
--  See below for an output example of a successful validation.
-
-::
-
-   VM START
-   *****************************************************************************************************
-   *                                  MicroEJ Core Validation - 3.1.0                                  *
-   *****************************************************************************************************
-   * Copyright 2013-2022 MicroEJ Corp. All rights reserved.                                            *
-   * Use of this source code is governed by a BSD-style license that can be found with this software.  *
-   *****************************************************************************************************
-   
-   -> Check visible clock (LLMJVM_IMPL_getCurrentTime validation)...
-   Property 'com.microej.core.tests.clock.seconds' is not set (default to '10' seconds)
-   1
-   2
-   3
-   4
-   5
-   6
-   7
-   8
-   9
-   10
-   OK: testVisibleClock
-   -> Check schedule request and wakeup (LLMJVM_IMPL_scheduleRequest and LLMJVM_IMPL_wakeupVM validation)...
-   Waiting for 5s...
-   ...done
-   OK: testTime
-   -> Check monotonic time (LLMJVM_IMPL_getCurrentTime, LLMJVM_IMPL_setApplicationTime validation)...
-   Waiting for 5s...
-   ...done
-   OK: testMonotonicTime
-   -> Check Java round robin (LLMJVM_IMPL_scheduleRequest validation)...
-   For a best result, please disable all the C native tasks except the MicroEJ task.
-   Task 3 is waiting for start...
-   Task 2 is waiting for start...
-   Task 1 is waiting for start...
-   Task 0 is waiting for start...
-   Starting tasks and wait for 10 seconds...
-   Task 2 ends.
-   Task 3 ends.
-   Task 0 ends.
-   Task 1 ends.
-   ...done.
-   OK: testJavaRoundRobin
-   Main thread starts sleeping for 1s..
-   WaitMaxTimeThread starts sleeping for `Long.MAX_VALUE` milliseconds
-   Main thread woke up!
-   OK: testScheduleMaxTime
-   -> Check isInReadOnlyMemory (LLBSP_IMPL_isInReadOnlyMemory validation)...
-   Test synchronize on literal string
-   Test synchronize on class
-   Test multiple synchronize
-   OK: testIsInReadOnlyMemory
-   -> Check FPU (soft/hard FP option)...
-   OK: testFPU
-   -> Check floating-point parser...
-   OK: testParseFP
-   -> Check floating-point formatter...
-   OK: testFormatFP
-   -> Check parsing a string as a double ; in some systems such operations may allocate memory in the C heap (strtod, strtof, malloc implementation)...
-   OK: testParseDoubleStringHeap
-   Property 'com.microej.core.tests.monotonic.time.check.seconds' is not set (default to '60' seconds)
-   -> Check monotonic time consistency for 60 seconds (LLMJVM_IMPL_getCurrentTime)...
-   .............................
-   OK: testMonotonicTimeIncreases
-   -> Check current time clock tick duration (LLMJVM_IMPL_getCurrentTime, LLMJVM_IMPL_getTimeNanos)...
-   Property 'com.microej.core.tests.max.allowed.clock.tick.duration.milliseconds' is not set (default to '20' millisecondss)
-   Estimated LLMJVM_IMPL_getCurrentTime clock tick is 1 ms.
-   Estimated LLMJVM_IMPL_getTimeNanos clock tick is lower than 30518 ns.
-   OK: testSystemCurrentTimeClockTick
-   -> Check schedule request clock tick duration (LLMJVM_IMPL_scheduleRequest)...
-   Property 'com.microej.core.tests.max.allowed.clock.tick.duration.milliseconds' is not set (default to '20' millisecondss)
-   Estimated LLMJVM_IMPL_scheduleRequest clock tick is 1 ms.
-   OK: testScheduleRequestClockTick
-   PASSED: 13
-   VM END (exit code = 0)
-
-
-Platform Test Suite Mode
-~~~~~~~~~~~~~~~~~~~~~~~~
-
--  In MicroEJ SDK, import the ``java-testsuite-runner-core`` project in your workspace.
-
--  Follow the configuration and execution steps described in Platform Test Suites `documentation <../../README.rst>`_.
-
-Dependencies
-------------
-
-*All dependencies are retrieved transitively by MicroEJ Module Manager*.
-
-Troubleshooting
----------------
-
-The test blocks during the Java round robin test under FreeRTOS
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-Issue: 
-
-- The test of ``LLMJVM_IMPL_scheduleRequest`` blocks at the following
-  step: ``Starting tasks and wait for 10 seconds...``.
-
-Solution: 
-
-- Ensure the JVM native C task has a priority lower than the FreeRTOS
-  timer task defined in ``FreeRTOSConfig.h`` (``configTIMER_TASK_PRIORITY``).
-
-Platform Test Suite issues
-~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-See Platform Test Suites `documentation <../../README.rst>`_.
-
-Source
-------
-
-N/A
-
-Restrictions
-------------
-
-None.
-
-..
-    Copyright 2020-2022 MicroEJ Corp. All rights reserved.
-    Use of this source code is governed by a BSD-style license that can be found with this software.
diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/config.properties b/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/config.properties
deleted file mode 100644
index fe45ad7..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/config.properties
+++ /dev/null
@@ -1,100 +0,0 @@
-# Properties
-#
-# Copyright 2021-2022 MicroEJ Corp. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be found with this software.
-
-###############################################################################
-# 						Testsuite Configuration Options
-#
-# Usage: 
-#   Uncomment and set options marked '[required]'. 
-#   Other options are set with a value that shall not be changed by default.
-# 
-# Each option can be declared outside this file as a system property:
-# In MicroEJ SDK, select 'Window' > 'Preferences' > 'Ant' > 'Runtime' > 'Properties'
-# This can be useful to avoid to share absolute file-system locations in this file.
-# In this case, it overrides the option defined in this file if any.
-# Moreover, options related to local setup (absolute file-system locations, trace ip & port)
-# can be extracted to the file 'local.properties' which is ignored for source control.   
-#
-# This file respects the Java properties file convention: the OS path
-# must use the UNIX path convention (path separator is '/'). The WINDOWS
-# paths must have been converted manually replacing '\' by '/' or by '\\'.
-###############################################################################
-
-###############################################################################
-# Target Platform 
-###############################################################################
-
-# defined in module.ant
-#target.platform.dir=
-
-###############################################################################
-# BSP Connection [required]
-# Uncomment one and only one option block depending on how the target Platform is connected to BSP.  
-# See https://docs.microej.com/en/latest/PlatformDeveloperGuide/platformCreation.html
-###############################################################################
-
-# No BSP Connection
-#microej.testsuite.properties.deploy.dir.microejapp=[absolute_path]
-#microej.testsuite.properties.deploy.dir.microejlib=[absolute_path]
-#microej.testsuite.properties.deploy.dir.microejinc=[absolute_path]
-#microej.testsuite.properties.deploy.bsp.microejscript=[absolute_path]
-
-# Partial BSP Connection
-#microej.testsuite.properties.deploy.bsp.root.dir=[absolute_path]
-#microej.testsuite.properties.deploy.bsp.microejscript=true
-
-# Full BSP Connection
-microej.testsuite.properties.deploy.bsp.microejscript=true
-
-###############################################################################
-# Trace Redirection (System.out)
-# [required] when trace is redirected by 'Serial to Socket Transmitter' tool,
-# otherwise the trace is assumed to be redirected by 'run.bat' or 'run.sh' script.
-###############################################################################
-
-microej.testsuite.properties.testsuite.trace.ip=localhost
-microej.testsuite.properties.testsuite.trace.port=5555
-
-# Platform specific option to redirect trace on dedicated UART
-#microej.testsuite.properties.debug.traces.uart=SET
-
-###############################################################################
-# Tests to run
-###############################################################################
-
-# Comma separated list of patterns of files that must be included	
-test.run.includes.pattern=**/_AllTests_*.class
-# Comma separated list of patterns of files that must be excluded (defaults to inner classes)
-test.run.excludes.pattern=**/*$*.class
-
-#######################################################################
-# Advanced Options
-# These options shall not be changed by default.
-###############################################################################
-
-# The execution target (`MICROJVM` to execute on Device, `S3` to execute on Simulator)
-target.vm.name=MICROJVM
-
-# The deploy tool to run after the build of the microejapp.o (defaults to 'Platform Configuration Additions')
-microej.testsuite.properties.microejtool.deploy.name=deployToolBSPRun
-
-# Set the verbose or not. Possible values: `true` or `false`
-# When this option is set to `true`, the harness will output the execution trace.
-microej.testsuite.verbose=true
-
-# The testsuite timeout (in seconds)
-microej.testsuite.timeout=600
-
-# The number of times we'll retry a test if it fails
-microej.testsuite.retry.count=1
-
-# Retry a test unless this pattern is shown
-microej.testsuite.retry.unless=VM START
-
-# A jvm args to pass to the testsuite harness
-microej.testsuite.jvmArgs=-Xmx768m
-
-# A jvm args to pass to launch scripts forked vm
-microej.testsuite.properties.launch.properties.jvm=-Xmx2048M
diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/launchers/java-testsuite-runner-core.launch b/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/launchers/java-testsuite-runner-core.launch
deleted file mode 100644
index c36d9b6..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/launchers/java-testsuite-runner-core.launch
+++ /dev/null
@@ -1,145 +0,0 @@
-
-
-
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diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/module.ant b/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/module.ant
deleted file mode 100644
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--- a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/module.ant
+++ /dev/null
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diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/module.ivy b/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/module.ivy
deleted file mode 100644
index b45ca58..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/module.ivy
+++ /dev/null
@@ -1,34 +0,0 @@
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diff --git a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/src/test/java/com/microej/core/tests/MicroejCoreValidation.java b/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/src/test/java/com/microej/core/tests/MicroejCoreValidation.java
deleted file mode 100644
index 2906181..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/core/java-testsuite-runner-core/src/test/java/com/microej/core/tests/MicroejCoreValidation.java
+++ /dev/null
@@ -1,810 +0,0 @@
-/*
- * Java
- *
- * Copyright 2013-2022 MicroEJ Corp. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be found with this software.
- */
-package com.microej.core.tests;
-
-import static org.junit.Assert.assertEquals;
-import static org.junit.Assert.assertTrue;
-import static org.junit.Assert.fail;
-
-import java.io.InputStream;
-import java.io.OutputStream;
-import java.io.Reader;
-import java.io.Writer;
-import java.util.ArrayList;
-import java.util.Calendar;
-import java.util.HashMap;
-import java.util.Hashtable;
-import java.util.Iterator;
-import java.util.List;
-import java.util.Map;
-import java.util.NoSuchElementException;
-
-import org.junit.BeforeClass;
-import org.junit.Test;
-
-import ej.bon.Immortals;
-import ej.bon.Immutables;
-import ej.bon.Util;
-
-/**
- * MicroEJ Core Validation tests.
- */
-public class MicroejCoreValidation {
-
-	private static final String VERSION = "3.1.0";
-
-	private static final String PROPERTY_SUFFIX = "com.microej.core.tests.";
-	private static final String OPTION_CLOCK_NB_SECONDS = "clock.seconds";
-	private static final String OPTION_MONOTONIC_CHECK_NB_SECONDS = "monotonic.time.check.seconds";
-	/**
-	 * Option that specifies the maximum allowed value for the duration of a clock tick. The higher this value is the
-	 * lower the allowed clock resolution will be.
-	 */
-	private static final String OPTION_MAX_ALLOWED_CLOCK_TICK_DURATION_MS = "max.allowed.clock.tick.duration.milliseconds";
-	private static final int DEFAULT_MAX_ALLOWED_CLOCK_TICK_DURATION_MS = 20;
-
-	private static final String INVALID_C_FUNCTION_MESSAGE = "C function not correctly implemented (check your libc configuration)";
-	private static final String INCOHERENT_FPU_MESSAGE = "FPU option is not coherent between MicroEJ Platform and BSP";
-
-	private static Class THIS_CLASS = MicroejCoreValidation.class;
-
-	// Round Robin constants
-	private static final int NB_THREADS = 4;
-	private static final int ROUND_ROBIN_TEST_DURATION = 10000;
-	private static final int ROUND_ROBIN_MIN_COUNTER_REQUIRED = 500;
-	private static final int ROUND_ROBIN_MAX_DELTA_PERCENTAGE_ALLOWED = 5;
-
-	private static volatile boolean ROUND_ROBIN_IS_RUNNING;
-	private static Object ROUND_ROBIN_LOCK = new Object();
-	private static long[] ROUND_ROBIN_TASK_COUNTERS;
-
-	// Set this fields volatile so we are sure accesses are not optimized
-	volatile private static double double3 = 3d;
-	volatile private static double double4 = 4d;
-	volatile private static float float3 = 3f;
-	volatile private static float float4 = 4f;
-
-	// testParseDoubleStringHeap: tolerance value for float comparison
-	private static final float FLOAT_COMPARISON_TOLERANCE_PERCENT = 0.01f;
-
-	private static void printProduct() {
-		final String sep = "*****************************************************************************************************";
-		System.out.println(sep);
-		System.out.println("*                                  MicroEJ Core Validation - " + VERSION
-				+ "                                  *");
-		System.out.println(sep);
-		System.out.println(
-				"* Copyright 2013-2022 MicroEJ Corp. All rights reserved.                                            *");
-		System.out.println(
-				"* Use of this source code is governed by a BSD-style license that can be found with this software.  *");
-		System.out.println(sep);
-		System.out.println();
-	}
-
-	private static int getOptionAsInt(String optionName, int defaultValue, String unit) {
-		String propertyName = PROPERTY_SUFFIX + optionName;
-		String valueStr = System.getProperty(propertyName);
-		int value;
-		if (valueStr == null) {
-			value = defaultValue;
-			System.out.println("Property '" + propertyName + "' is not set (default to '" + value + "' " + unit
-					+ (value > 1 ? "s" : "") + ")");
-		} else {
-			try {
-				value = Integer.parseInt(valueStr);
-				System.out.println(
-						"Property '" + propertyName + "' is set to '" + value + "' " + unit + (value > 1 ? "s" : ""));
-			} catch (NumberFormatException e) {
-				value = defaultValue;
-				System.out.println("Property '" + propertyName + "' is invalid (set to '" + valueStr + "', default to '"
-						+ value + "' " + unit + (value > 1 ? "s" : "") + ")");
-			}
-		}
-		return value;
-	}
-
-	private static void tryToSynchronizeOn(List objects, boolean mustFail) {
-		MonitorKeeper.errorCount = 0;
-		Thread[] threads = new Thread[MonitorKeeper.THREAD_COUNT];
-
-		try {
-			for (int i = 0; i < threads.length; i++) {
-				threads[i] = new Thread(new MonitorKeeper(objects.get(i)));
-			}
-
-			for (Thread thread : threads) {
-				thread.start();
-			}
-
-			for (Thread thread : threads) {
-				try {
-					thread.join();
-				} catch (InterruptedException e) {
-					// Nothing to do here.
-				}
-			}
-
-			boolean success;
-			if (mustFail) {
-				success = MonitorKeeper.errorCount > 0;
-			} else {
-				success = MonitorKeeper.errorCount == 0;
-			}
-			assertTrue("Too many synchronized monitors.", success);
-		} catch (IndexOutOfBoundsException ioobe) {
-			fail("No objects to synchronize on, aborting.");
-		}
-	}
-
-	private static List objectsFromRam() {
-		List objects = new ArrayList<>();
-
-		for (int i = 0; i < MonitorKeeper.THREAD_COUNT; i++) {
-			Object[] objects2 = new Object[MonitorKeeper.MONITOR_PER_THREAD_COUNT];
-			for (int j = 0; j < objects2.length; j++) {
-				objects2[j] = new Object();
-			}
-			objects.add(objects2);
-		}
-
-		return objects;
-	}
-
-	private static List objectsFromImmortals() {
-		List objects = new ArrayList<>();
-
-		for (int i = 0; i < MonitorKeeper.THREAD_COUNT; i++) {
-			Object[] objects2 = new Object[MonitorKeeper.MONITOR_PER_THREAD_COUNT];
-			for (int j = 0; j < objects2.length; j++) {
-				Object object = new Object();
-				Immortals.setImmortal(object);
-				objects2[j] = object;
-			}
-			objects.add(objects2);
-		}
-
-		return objects;
-	}
-
-	private static List objectsFromImmutables() {
-		List objects = new ArrayList<>();
-		int objectID = 0;
-
-		try {
-			for (int i = 0; i < MonitorKeeper.THREAD_COUNT; i++) {
-				Object[] objects2 = new Object[MonitorKeeper.MONITOR_PER_THREAD_COUNT];
-				for (int j = 0; j < objects2.length; j++) {
-					Object object = Immutables.get("array" + objectID++);
-					objects2[j] = object;
-				}
-				objects.add(objects2);
-			}
-		} catch (NoSuchElementException nsee) {
-			System.out.println("Can't find the requested object in the immutables, check your launch configuration.");
-		}
-
-		return objects;
-	}
-
-	private static List stringsFromImmutables() {
-		List objects = new ArrayList<>();
-
-		objects.add(new String[] { "0", "1", "2", "3", "4", "5", "6" });
-		objects.add(new String[] { "7", "8", "9", "10", "11", "12", "13" });
-		objects.add(new String[] { "14", "15", "16", "17", "18", "19", "20" });
-		objects.add(new String[] { "21", "22", "23", "24", "25", "26", "27" });
-		objects.add(new String[] { "28", "29", "30", "31", "32", "33", "34" });
-
-		return objects;
-	}
-
-	private static List classes() {
-		List objects = new ArrayList<>();
-
-		objects.add(new Class[] { Integer.class, Boolean.class, Long.class, Float.class, Double.class, Thread.class,
-				Object.class });
-		objects.add(new Class[] { Byte.class, Character.class, Calendar.class, ArrayList.class, List.class, Class.class,
-				Exception.class });
-		objects.add(new Class[] { InputStream.class, OutputStream.class, Map.class, HashMap.class, Hashtable.class,
-				Reader.class, Writer.class });
-		objects.add(new Class[] { Number.class, Throwable.class, String.class, Short.class, Enum.class, Runtime.class,
-				Package.class });
-		objects.add(new Class[] { System.class, Math.class, StringBuilder.class, StringBuffer.class, Runnable.class,
-				Iterable.class, Iterator.class });
-
-		return objects;
-	}
-
-	private static native float testFloat(float a, float b);
-
-	private static native double testDouble(double a, double b);
-
-	private static float testFPUJava(float a, float b) {
-		return a * b;
-	}
-
-	private static double testFPUJava(double a, double b) {
-		return a * b;
-	}
-
-	/**
-	 * @throws java.lang.Exception
-	 *             If an error occurred.
-	 */
-	@BeforeClass
-	public static void setUpBeforeClass() throws Exception {
-		printProduct();
-	}
-
-	/**
-	 * Tests the LLMJVM_IMPL_getCurrentTime implementation.
-	 */
-	@Test
-	public void testVisibleClock() {
-		System.out.println("-> Check visible clock (LLMJVM_IMPL_getCurrentTime validation)...");
-		final long precisionLimit = getOptionAsInt(OPTION_MAX_ALLOWED_CLOCK_TICK_DURATION_MS,
-				DEFAULT_MAX_ALLOWED_CLOCK_TICK_DURATION_MS, "milliseconds");
-		int defaultNbSeconds = 10;
-		int nbSeconds = getOptionAsInt(OPTION_CLOCK_NB_SECONDS, defaultNbSeconds, "second");
-
-		// Check if a message is printed every seconds in terminal:
-		long timeStart = System.currentTimeMillis();
-		int seconds = 0;
-		long nbMilliSeconds = nbSeconds * 1000;
-		while (true) {
-			long time = System.currentTimeMillis();
-			long delta = time - timeStart;
-			int newSecond = (int) (delta / 1000);
-			if (newSecond > seconds) {
-				System.out.println(newSecond);
-				seconds = newSecond;
-			}
-
-			if (delta > nbMilliSeconds) {
-				break; // end of test
-			}
-		}
-
-		// ensure both API returns same value
-		long timeEnd1 = System.currentTimeMillis();
-		long timeEnd2 = Util.platformTimeMillis();
-		long delta = timeEnd2 - timeEnd1;
-		assertTrue("Util.platformTimeMillis() != System.currentTimeMillis()", delta <= precisionLimit);
-
-		// ensure nano time is valid
-		delta = (Util.platformTimeNanos() / 1000000) - Util.platformTimeMillis();
-		assertTrue("Util.platformTimeNanos()/1000000 != Util.platformTimeMillis()", delta <= precisionLimit);
-	}
-
-	/**
-	 * Tests LLMJVM_IMPL_scheduleRequest and LLMJVM_IMPL_wakeupVM implementations.
-	 */
-	@Test
-	public void testTime() {
-		System.out.println(
-				"-> Check schedule request and wakeup (LLMJVM_IMPL_scheduleRequest and LLMJVM_IMPL_wakeupVM validation)...");
-		final long precisionLimit = getOptionAsInt(OPTION_MAX_ALLOWED_CLOCK_TICK_DURATION_MS,
-				DEFAULT_MAX_ALLOWED_CLOCK_TICK_DURATION_MS, "milliseconds");
-		long delay = 5 * 1000;
-		System.out.println("Waiting for " + delay / 1000 + "s...");
-		long timeBefore = System.currentTimeMillis();
-		try {
-			Thread.sleep(delay);
-		} catch (InterruptedException e) {
-			throw new Error();
-		}
-		long timeAfter = System.currentTimeMillis();
-		System.out.println("...done");
-		long realDelay = timeAfter - timeBefore;
-		assertTrue("realDelay>=delay", realDelay >= delay);
-		long delta = realDelay - delay;
-		assertTrue("delta(=" + delta + ")<=" + precisionLimit, delta <= precisionLimit);
-	}
-
-	/**
-	 * Tests the LLMJVM_IMPL_setApplicationTime implementation.
-	 */
-	@Test
-	public void testMonotonicTime() {
-		System.out.println(
-				"-> Check monotonic time (LLMJVM_IMPL_getCurrentTime, LLMJVM_IMPL_setApplicationTime validation)...");
-		long delay = 5 * 1000;
-		long elapsedTime = 100;
-		long timeOffset = 50_000;
-		System.out.println("Waiting for " + delay / 1000 + "s...");
-		long monotonicTimeBefore = Util.platformTimeMillis();
-		long applicationTimeBefore = System.currentTimeMillis();
-
-		Util.setCurrentTimeMillis(applicationTimeBefore + timeOffset);
-		long applicationTimeAfter = System.currentTimeMillis();
-
-		try {
-			Thread.sleep(delay);
-		} catch (InterruptedException e) {
-			throw new Error();
-		}
-		long montonicTimeAfter = Util.platformTimeMillis();
-		System.out.println("...done");
-		assertTrue("application time not set", applicationTimeAfter >= applicationTimeBefore + timeOffset
-				&& applicationTimeAfter <= applicationTimeBefore + timeOffset + elapsedTime);
-		assertTrue("monotonic time not set", montonicTimeAfter >= monotonicTimeBefore + delay
-				&& montonicTimeAfter <= monotonicTimeBefore + delay + elapsedTime);
-	}
-
-	/**
-	 * Tests the LLMJVM_IMPL_scheduleRequest implementation.
-	 */
-	@Test
-	public void testJavaRoundRobin() {
-		System.out.println("-> Check Java round robin (LLMJVM_IMPL_scheduleRequest validation)...");
-		System.out.println("For a best result, please disable all the C native tasks except the MicroEJ task.");
-		int nbThreads = NB_THREADS;
-		assertTrue("nbThreads >= 2", nbThreads >= 2);
-
-		ROUND_ROBIN_TASK_COUNTERS = new long[nbThreads];
-		int priority = Thread.currentThread().getPriority() - 1;
-		Thread[] threads = new Thread[nbThreads];
-		for (int i = threads.length; --i >= 0;) {
-			Thread t = new Thread(new RoundRobinTestTask(i));
-			threads[i] = t;
-			t.setPriority(priority);
-			t.start();
-		}
-
-		// Poll until all threads are waiting on the monitor
-		while (RoundRobinTestTask.COUNTER < NB_THREADS) {
-			try {
-				Thread.sleep(500);
-			} catch (InterruptedException e) {
-				e.printStackTrace();
-			}
-		}
-
-		System.out.println("Starting tasks and wait for " + (ROUND_ROBIN_TEST_DURATION / 1000) + " seconds...");
-		synchronized (ROUND_ROBIN_LOCK) {
-			ROUND_ROBIN_IS_RUNNING = true;
-			ROUND_ROBIN_LOCK.notifyAll(); // start !
-		}
-
-		try {
-			Thread.sleep(ROUND_ROBIN_TEST_DURATION);
-		} catch (InterruptedException e1) {
-			assertTrue("Unexpected InterruptedException", false);
-		}
-
-		// stop threads
-		ROUND_ROBIN_IS_RUNNING = false;
-		for (int i = threads.length; --i >= 0;) {
-			try {
-				threads[i].join();
-			} catch (InterruptedException e) {
-				throw new Error();
-			}
-		}
-		System.out.println("...done.");
-
-		long totalCounter = 0;
-		long minCounter = Long.MAX_VALUE;
-		long maxCounter = 0;
-		for (int i = threads.length; --i >= 0;) {
-			long counter = ROUND_ROBIN_TASK_COUNTERS[i];
-			totalCounter += counter;
-			maxCounter = Math.max(maxCounter, counter);
-			minCounter = Math.min(minCounter, counter);
-		}
-
-		long deltaCounter = maxCounter - minCounter;
-		long averageCounter = totalCounter / threads.length;
-		long deltaPercentage;
-		if (minCounter > 0) {
-			deltaPercentage = (deltaCounter * 100) / minCounter;
-		} else {
-			deltaPercentage = 100;
-		}
-
-		if (deltaPercentage > ROUND_ROBIN_MAX_DELTA_PERCENTAGE_ALLOWED) {
-			// Print some information when the test fails
-			System.out.println("Min counter = " + minCounter);
-			System.out.println("Max counter = " + maxCounter);
-			System.out.println("Average = " + averageCounter);
-			System.out.println("Delta = " + deltaCounter);
-			System.out.println("Delta Percentage = " + deltaPercentage);
-		}
-
-		assertTrue("counter increments < " + ROUND_ROBIN_MIN_COUNTER_REQUIRED + " (actually " + minCounter + ")",
-				minCounter >= ROUND_ROBIN_MIN_COUNTER_REQUIRED);
-
-		assertTrue("delta percentage > " + ROUND_ROBIN_MAX_DELTA_PERCENTAGE_ALLOWED + " (actually " + deltaPercentage
-				+ ")", deltaPercentage <= ROUND_ROBIN_MAX_DELTA_PERCENTAGE_ALLOWED);
-	}
-
-	/**
-	 * Tests the LLMJVM_IMPL_scheduleRequest implementation with a max schedule request time
-	 * (Long.MAX_VALUE milliseconds).
-	 *
-	 * Tests Thread.sleep() with max number of milliseconds (Long.MAX_VALUE) does not cause an infinite loop in the
-	 * MicroEJ Core.
-	 *
-	 * This test will check if the time conversion overflow is correctly handled in the LLMJVM_scheduleRequest()
-	 * implementation. A correct implementation should saturate the time to the max value of microseconds or ticks in
-	 * case of overflow.
-	 */
-	@Test
-	public void testScheduleMaxTime() {
-		Thread waitMaxTimeThread = new Thread(new Runnable() {
-			@Override
-			public void run() {
-				try {
-					System.out.println("WaitMaxTimeThread starts sleeping for `Long.MAX_VALUE` milliseconds");
-					Thread.sleep(Long.MAX_VALUE);
-					assertTrue("Max sleep time reached!", false);
-				} catch (InterruptedException e) {
-					// interrupted
-				}
-			}
-		});
-
-		waitMaxTimeThread.start();
-
-		System.out.println("Main thread starts sleeping for 1s..");
-		try {
-			Thread.sleep(1000);
-			System.out.println("Main thread woke up!");
-			waitMaxTimeThread.interrupt();
-			waitMaxTimeThread.join();
-			assertTrue("Main thread woke up and continued its execution: MicroEJ Core does not loop indefinitely",
-					true);
-		} catch (InterruptedException e) {
-			throw new Error();
-		}
-
-	}
-
-	/**
-	 * Tests the LLBSP_IMPL_isInReadOnlyMemory implementation.
-	 */
-	@Test
-	public void testIsInReadOnlyMemory() {
-		System.out.println("-> Check isInReadOnlyMemory (LLBSP_IMPL_isInReadOnlyMemory validation)...");
-
-		try {
-			String s = "literal string";
-			synchronized (s) {
-				System.out.println("Test synchronize on literal string");
-			}
-		} catch (IllegalMonitorStateException e) {
-			fail("IllegalMonitorStateException during synchronization on immutable object (literal string)");
-		}
-
-		try {
-			synchronized (MicroejCoreValidation.class) {
-				System.out.println("Test synchronize on class");
-			}
-		} catch (IllegalMonitorStateException e) {
-			fail("IllegalMonitorStateException during synchronization on immutable object (class)");
-		}
-
-		/*
-		 * There is a limit of the number of the synchronized monitors in flash but not in ram. We test this limit is
-		 * reached for the objects in flash but not for the objects in ram. If the LLBSP_IMPL_isInReadOnlyMemory
-		 * function is not correctly implemented this test can highlight it.
-		 */
-		System.out.println("Test multiple synchronize");
-		tryToSynchronizeOn(objectsFromRam(), false);
-		tryToSynchronizeOn(stringsFromImmutables(), true);
-		tryToSynchronizeOn(classes(), true);
-		tryToSynchronizeOn(objectsFromImmortals(), false);
-		tryToSynchronizeOn(objectsFromImmutables(), true);
-	}
-
-	/**
-	 * Tests the platform FPU configuration.
-	 */
-	@Test
-	public void testFPU() {
-		System.out.println("-> Check FPU (soft/hard FP option)...");
-
-		assertEquals("test 'float * float' in Java: " + INCOHERENT_FPU_MESSAGE, new Float(12f),
-				new Float(testFPUJava(float3, float4)));
-		assertEquals("test 'double * double' in Java: " + INCOHERENT_FPU_MESSAGE, new Double(12),
-				new Double(testFPUJava(double3, double4)));
-		assertEquals("test 'float * float' in C: " + INCOHERENT_FPU_MESSAGE, new Float(12f),
-				new Float(testFloat(float3, float4)));
-		assertEquals("test 'double * double' in C: " + INCOHERENT_FPU_MESSAGE, new Double(12),
-				new Double(testDouble(double3, double4)));
-	}
-
-	/**
-	 * Tests the platform FP parser.
-	 */
-	@Test
-	public void testParseFP() {
-		System.out.println("-> Check floating-point parser...");
-
-		float parsedFloat = Float.parseFloat("1234.5");
-		float expectedFloat = 1234.5f;
-		assertEquals("test 'parse float string': strtof " + INVALID_C_FUNCTION_MESSAGE, expectedFloat, parsedFloat,
-				getAssertFloatDelta(expectedFloat));
-
-		double parsedDouble = Double.parseDouble("1234.5");
-		double expectedDouble = 1234.5;
-		assertEquals("test 'parse double string': strtod " + INVALID_C_FUNCTION_MESSAGE, expectedDouble, parsedDouble,
-				getAssertDoubleDelta(expectedDouble));
-	}
-
-	/**
-	 * Tests the platform FP formatter.
-	 */
-	@Test
-	public void testFormatFP() {
-		System.out.println("-> Check floating-point formatter...");
-
-		String floatToString = Float.toString(1234.5f);
-		assertEquals("test 'float to string': snprintf " + INVALID_C_FUNCTION_MESSAGE, "1234.5", floatToString);
-
-		String doubleToString = Double.toString(1234.5d);
-		assertEquals("test 'double to string': snprintf " + INVALID_C_FUNCTION_MESSAGE, "1234.5", doubleToString);
-	}
-
-	/**
-	 * Tests parse double/float with potential dynamic allocation.
-	 */
-	@Test
-	public void testParseDoubleStringHeap() {
-		System.out.println(
-				"-> Check parsing a string as a double ; in some systems such operations may allocate memory in the C heap (strtod, strtof, malloc implementation)...");
-
-		double parsedDouble;
-		double expectedDouble;
-		float parsedFloat;
-		float expectedFloat;
-		parsedDouble = Double.parseDouble("1.7976931348623157E308");
-		expectedDouble = 1.7976931348623157E308;
-		assertEquals("test 'parse float/double string (1/10)': strtod " + INVALID_C_FUNCTION_MESSAGE, expectedDouble,
-				parsedDouble, getAssertDoubleDelta(expectedDouble));
-
-		parsedDouble = Double.parseDouble("4.9E-324");
-		expectedDouble = 4.9E-324;
-		assertEquals("test 'parse float/double string (2/10)': strtod " + INVALID_C_FUNCTION_MESSAGE, expectedDouble,
-				parsedDouble, getAssertDoubleDelta(expectedDouble));
-
-		parsedDouble = Double.parseDouble(
-				"8456452315484210000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009999999999999999999999999999999999999999999999999999999999999999040.005460000000000E-512");
-		expectedDouble = 8.4E-323d;
-		assertEquals("test 'parse float/double string (3/10)': strtod " + INVALID_C_FUNCTION_MESSAGE, expectedDouble,
-				parsedDouble, getAssertDoubleDelta(expectedDouble));
-
-		parsedFloat = Float.parseFloat("7.56042114E-33");
-		expectedFloat = 7.56042114E-33f;
-		assertEquals("test 'parse float/double string (4/10)': strtof " + INVALID_C_FUNCTION_MESSAGE, expectedFloat,
-				parsedFloat, getAssertFloatDelta(expectedFloat));
-
-		parsedFloat = Float.parseFloat("3.71806751E-19");
-		expectedFloat = 3.71806751E-19f;
-		assertEquals("test 'parse float/double string (5/10)': strtof " + INVALID_C_FUNCTION_MESSAGE, expectedFloat,
-				parsedFloat, getAssertFloatDelta(expectedFloat));
-
-		parsedFloat = Float.parseFloat("7.99279006E37");
-		expectedFloat = 7.99279006E37f;
-		assertEquals("test 'parse float/double string (6/10)': strtof " + INVALID_C_FUNCTION_MESSAGE, expectedFloat,
-				parsedFloat, getAssertFloatDelta(expectedFloat));
-
-		parsedFloat = Float.parseFloat("2.27187279E-38");
-		expectedFloat = 2.27187279E-38f;
-		assertEquals("test 'parse float/double string (7/10)': strtof " + INVALID_C_FUNCTION_MESSAGE, expectedFloat,
-				parsedFloat, getAssertFloatDelta(expectedFloat));
-
-		parsedDouble = Double.parseDouble("1.7976931348623157E308");
-		expectedDouble = 1.7976931348623157E308;
-		assertEquals("test 'parse float/double string (8/10)': strtod " + INVALID_C_FUNCTION_MESSAGE, expectedDouble,
-				parsedDouble, getAssertDoubleDelta(expectedDouble));
-
-		String strDouble = Double.toString(2.4375d);
-		assertEquals("test 'double to string (9/10)': sprintf " + INVALID_C_FUNCTION_MESSAGE, "2.4375", strDouble);
-
-		parsedDouble = Double.parseDouble("4.9E-324");
-		expectedDouble = 4.9E-324;
-		assertEquals("test 'parse float/double string (10/10)': strtod " + INVALID_C_FUNCTION_MESSAGE, expectedDouble,
-				parsedDouble, getAssertDoubleDelta(expectedDouble));
-
-	}
-
-	/**
-	 * From expected double value, returns the delta value to use when comparing two doubles.
-	 */
-	private static double getAssertDoubleDelta(double expectedResult) {
-		return expectedResult * FLOAT_COMPARISON_TOLERANCE_PERCENT;
-	}
-
-	/**
-	 * From expected float value, returns the delta value to use when comparing two floats.
-	 */
-	private static float getAssertFloatDelta(float expectedResult) {
-		return expectedResult * FLOAT_COMPARISON_TOLERANCE_PERCENT;
-	}
-
-	/**
-	 * Tests that the LLMJVM_IMPL_getCurrentTime implementation always increases.
-	 */
-	@Test
-	public void testMonotonicTimeIncreases() {
-		final long testDurationS = getOptionAsInt(OPTION_MONOTONIC_CHECK_NB_SECONDS, 60, "second");
-		System.out.println("-> Check monotonic time consistency for " + testDurationS
-				+ " seconds (LLMJVM_IMPL_getCurrentTime)...");
-
-		final long printDotPeriodMs = 2000;
-		long startTime = Util.platformTimeMillis();
-		long endTime = startTime + (testDurationS * 1000);
-		long printDotTime = startTime + printDotPeriodMs;
-		long previousTime = startTime;
-		long currentTime;
-		while (endTime > (currentTime = Util.platformTimeMillis())) {
-			if (printDotTime < currentTime) {
-				System.out.print('.');
-				printDotTime = currentTime + printDotPeriodMs;
-			}
-			if (currentTime < previousTime) {
-				System.out.println();
-				assertTrue("Monotonic time goes back in time (currentTime = " + currentTime + " previousTime="
-						+ previousTime + ").\nThis issue is usually caused by a non-atomic calculation of the time.",
-						false);
-				return;
-			}
-			previousTime = currentTime;
-		}
-		System.out.println();
-
-	}
-
-	/**
-	 * Checks {@code LLMJVM_IMPL_getCurrentTime()} and {@code LLMJVM_IMPL_getTimeNanos()} clock tick duration.
-	 */
-	@Test
-	public void testSystemCurrentTimeClockTick() {
-		System.out.println(
-				"-> Check current time clock tick duration (LLMJVM_IMPL_getCurrentTime, LLMJVM_IMPL_getTimeNanos)...");
-		final long precisionLimitMs = getOptionAsInt(OPTION_MAX_ALLOWED_CLOCK_TICK_DURATION_MS,
-				DEFAULT_MAX_ALLOWED_CLOCK_TICK_DURATION_MS, "milliseconds");
-
-		long t0;
-		long t1;
-		long precision;
-
-		// Check LLMJVM_IMPL_getCurrentTime
-		t0 = System.currentTimeMillis();
-		while ((t1 = System.currentTimeMillis()) == t0) {
-		}
-		precision = t1 - t0;
-		System.out.println("Estimated LLMJVM_IMPL_getCurrentTime clock tick is " + precision + " ms.");
-		assertTrue("LLMJVM_IMPL_getCurrentTime timer precision (" + precision
-				+ " ms) is lower than the expected limit (" + precisionLimitMs + " ms)", precision <= precisionLimitMs);
-
-		// Check LLMJVM_IMPL_getTimeNanos
-		t0 = System.nanoTime();
-		t1 = System.nanoTime();
-		if (t0 != t1) {
-			// Time to call nanoTime is longer than the clock tick.
-			// Cannot compute exact precision, just print this result
-			System.out.println("Estimated LLMJVM_IMPL_getTimeNanos clock tick is lower than " + (t1 - t0) + " ns.");
-		} else {
-			t0 = System.nanoTime();
-			while ((t1 = System.nanoTime()) == t0) {
-
-			}
-			precision = t1 - t0;
-			long precisionLimitNs = precisionLimitMs * 1000000l;
-			System.out.println("Estimated LLMJVM_IMPL_getTimeNanos clock tick is " + precision + " ns.");
-			assertTrue("LLMJVM_IMPL_getTimeNanos timer precision (" + precision
-					+ " ns) is lower than the expected limit (" + precisionLimitMs + " ns)",
-					precision <= precisionLimitNs);
-		}
-
-	}
-
-	/**
-	 * Checks {@code LLMJVM_IMPL_scheduleRequest()} clock tick duration.
-	 */
-	@Test
-	public void testScheduleRequestClockTick() {
-		System.out.println("-> Check schedule request clock tick duration (LLMJVM_IMPL_scheduleRequest)...");
-		final long precisionLimit = getOptionAsInt(OPTION_MAX_ALLOWED_CLOCK_TICK_DURATION_MS,
-				DEFAULT_MAX_ALLOWED_CLOCK_TICK_DURATION_MS, "milliseconds");
-		try {
-			// Execute a first sleep just to end the current clock cycle.
-			// Following operations will start at the beginning of the next clock cycle.
-			Thread.sleep(1);
-			long t0 = System.currentTimeMillis();
-			Thread.sleep(1);
-			long t1 = System.currentTimeMillis();
-
-			long precision = t1 - t0;
-			System.out.println("Estimated LLMJVM_IMPL_scheduleRequest clock tick is " + precision + " ms.");
-			assertTrue(
-					"LLMJVM_IMPL_scheduleRequest timer precision (" + precision
-							+ " ms) is lower than the expected limit (" + precisionLimit + " ms)",
-					precision <= precisionLimit);
-
-		} catch (InterruptedException e) {
-			throw new Error();
-		}
-	}
-
-	/**
-	 * Task class for the round robin test.
-	 */
-	private static class RoundRobinTestTask implements Runnable {
-
-		public static int COUNTER = 0;
-
-		private final int id;
-
-		public RoundRobinTestTask(int id) {
-			this.id = id;
-		}
-
-		@Override
-		public void run() {
-			synchronized (MicroejCoreValidation.ROUND_ROBIN_LOCK) {
-				if (!MicroejCoreValidation.ROUND_ROBIN_IS_RUNNING) {
-					++COUNTER;
-					System.out.println("Task " + this.id + " is waiting for start...");
-					try {
-						MicroejCoreValidation.ROUND_ROBIN_LOCK.wait();
-					} catch (InterruptedException e) {
-						throw new Error();
-					}
-				}
-			}
-			while (MicroejCoreValidation.ROUND_ROBIN_IS_RUNNING) {
-				++MicroejCoreValidation.ROUND_ROBIN_TASK_COUNTERS[this.id];
-			}
-			System.out.println("Task " + this.id + " ends.");
-		}
-
-	}
-
-	/**
-	 * Synchronizes on a list of monitors and sleeps for a while.
-	 */
-	private static class MonitorKeeper implements Runnable {
-		static final int THREAD_COUNT = 5;
-		static final int MONITOR_PER_THREAD_COUNT = 7;
-		static final int SLEEP_TIME = 5_000;
-		public static int errorCount;
-
-		private final Object[] monitors;
-
-		public MonitorKeeper(Object[] monitors) {
-			this.monitors = monitors;
-		}
-
-		@Override
-		public void run() {
-			try {
-				synchronizeAll(0);
-			} catch (Error e) {
-				errorCount++;
-			}
-		}
-
-		private void synchronizeAll(int monitorIndex) {
-			if (monitorIndex < this.monitors.length) {
-				synchronized (this.monitors[monitorIndex]) {
-					synchronizeAll(monitorIndex + 1);
-				}
-			} else {
-				try {
-					Thread.sleep(SLEEP_TIME);
-				} catch (InterruptedException e) {
-					// Nothing to do here.
-				}
-			}
-		}
-
-	}
-
-}
diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/.gitignore b/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/.gitignore
deleted file mode 100644
index 662cb8d..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/.gitignore
+++ /dev/null
@@ -1,4 +0,0 @@
-target~/
-bin/
-src-adpgenerated/
-com.microej.ui.tests.*/
\ No newline at end of file
diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/CHANGELOG.rst b/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/CHANGELOG.rst
deleted file mode 100644
index d50b05d..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/CHANGELOG.rst
+++ /dev/null
@@ -1,39 +0,0 @@
-CHANGELOG
-=========
-
-The format is based on `Keep a
-Changelog `__, and this project
-adheres to `Semantic
-Versioning `__.
-
-
-.. _110--Unreleased:
-
-[1.1.0] - 2022-07-23
---------------------
-
-Added
-~~~~~
-
-- Add test `testFlushTime`.
-
-Changed
-~~~~~~~
-
-- Reformat to use standard MicroEJ Test Suite flow.
-- Update the test ``testBackBufferRestore`` to be compliant with round displays and displays with specific pixels on corners.
-
-.. _100---2021-04-20:
-
-[1.0.0] - 2021-04-20
---------------------
-
-Added
-~~~~~
-
--  Tearing tests: show LCD tearing effect with full screen and black band.
--  Drawing time: retrieve the maximum drawing time to have the better framerate.
-
-..
-    Copyright 2021-2022 MicroEJ Corp. All rights reserved.
-    Use of this source code is governed by a BSD-style license that can be found with this software.
diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/README.rst b/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/README.rst
deleted file mode 100644
index 9d28265..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/README.rst
+++ /dev/null
@@ -1,147 +0,0 @@
-MicroEJ UI Validation
-=====================
-
-Overview
---------
-
-This project contains test cases aimed at validating the correct runtime execution 
-of UI Pack on a MicroEJ Platform connected to a Board Support Package (BSP).
- 
-Tests are written as JUnit test cases, thus the main entry point is automatically generated by MicroEJ SDK.
-
-Tests can be launched:
-
--  as a standard Application by using a `local launcher`_.
--  as a Platform Test Suite by `building the module`_.
-
-Requirements
-------------
-
--  MicroEJ SDK version ``5.1.0`` (included in MicroEJ SDK dist. ``19.05``).
--  MicroEJ Platform built from a MicroEJ UI Pack version ``13.0.0`` or higher.
--  See Platform Test Suites `documentation <../../README.rst>`_.
-
-Usage
------
-
-Launcher Mode
-~~~~~~~~~~~~~
-
-In MicroEJ SDK,
-
--  Select ``Run > Run Configurations...``. A launcher named
-   ``java-testsuite-runner-ui3`` should be available under
-   ``MicroEJ Application``.
-   
--  In ``Execution`` tab, select the target MicroEJ Platform.
-
--  Click on ``Run`` button to compile the MicroEJ Application.
-
--  Link the BSP project with the MicroEJ Application (``microejapp.o``), 
-   the MicroEJ Platform runtime (``microejruntime.a``) and the MicroEJ Platform header files (``*.h``).
-
--  See below for an output example
-
-::
-
-    *****************************************************************************************************
-    *                                  MicroEJ UI Validation - 1.0.0                                  *
-    *****************************************************************************************************
-    * Copyright 2021-2022 MicroEJ Corp. All rights reserved.                                            *
-    * Use of this source code is governed by a BSD-style license that can be found with this software.  *
-    *****************************************************************************************************
-    
-    -> Check LCD tearing: full screen (LLUI_DISPLAY_IMPL_flush validation)...
-    Property 'com.microej.ui.tests.clock.seconds' is not set (default to '10' second(s))
-    OK: testTearingFullScreen
-    -> Check LCD tearing: black band (LLUI_DISPLAY_IMPL_flush validation)...
-    Property 'com.microej.ui.tests.clock.seconds' is not set (default to '10' second(s))
-    OK: testTearingVerticalBand
-    Property 'com.microej.ui.tests.flush.tolerance.us' is not set (default to '200' us)
-    LCD framerate time is 17528 us (57.051579 Hz)
-    Retrieve the maximal drawing time (this will take several seconds)...
-    The flush time is 7.708000 us
-    To have an animation at 57.051579 Hz, the drawing time cannot be higher than 9.820000 ms.
-    To have an animation at 28.525789 Hz, the drawing time cannot be higher than 27.348000 ms.
-    To have an animation at 19.017193 Hz, the drawing time cannot be higher than 44.875999 ms.
-    OK: testDrawingTime
-    OK: testBackBufferRestore
-    flush time (several iterations): 0
-    wait flush time (several iterations): 295
-    OK: testFlushTime
-    PASSED: 5
-
-Platform Test Suite Mode
-~~~~~~~~~~~~~~~~~~~~~~~~
-
--  In MicroEJ SDK, import the ``java-testsuite-runner-ui3`` project in your workspace.
-
--  Follow the configuration and execution steps described in Platform Test Suites `documentation <../../README.rst>`_.
-
-Tests Suite Description
------------------------
-
-All tests can be run in one step: all tests will be executed one by one
-and are run in a specific order, *next one* expects *previous one* is
-passed.
-
-Tearing
-~~~~~~~
-
-A tearing effect (flickering) visible on LCD indicates a synchronization issue with
-the LCD tearing signal (TE).
-
-* "Full screen" test toggles black and white screens. If the flush job is properly synchronized and quite
-fast, the LCD is gray. The LCD being cut in multiple parts indicates a synchronization issue of the flush job.
-* "Black band" test moves a black band on a white background. The band being cut in multiple parts indicates a synchronization issue of the flush job.
-
-Drawing Time
-~~~~~~~~~~~~
-
-"Drawing time" test determinates the maximum drawing time (in milliseconds) for a given
-framerate. The possible framerates depend on the LCD and on the post-flush copy step. When the
-drawing time exceeds the maximum drawing time, the framerate is divided by two when the flush
-job is synchronized on LCD tearing signal.
-
-Back Buffer Restore
-~~~~~~~~~~~~~~~~~~~
-
-This test is useful when the implementation of ``LLUI_DISPLAY_IMPL_flush`` uses the  `SWITCH mode `_.
-In that case, after each call to ``LLUI_DISPLAY_IMPL_flush``, the implementation has to copy the content of the new frame buffer in the new back buffer before calling ``LLUI_DISPLAY_flushDone`` (post-flush-copy).
-The MicroUI Graphics Engine automatically waits this signal before performing the next application drawing.
-This copy is often performed by a hardware DMA.
-
-If the copy is not performed or if the MicroUI Graphics Engine is notified too early (before or during the copy), this test fails: the new back buffer content does not contain the previous drawing.
-
-This test may fail because the display is round or has irrelevant pixels in the corners. In this case, please set the ``area.offset`` property to avoid unwanted areas of the frame buffer.
-This property can be set in a file `System.properties.list` with the prefix ``com.microej.ui.tests.``. For example ``com.microej.ui.tests.area.offset=30``.
-
-Flush Time
-~~~~~~~~~~
-
-The implementation of the function ``LLUI_DISPLAY_IMPL_flush`` must be as fast as possible: it is not a blocking function (see function specification).
-The implementation has to launch a third-party process (software task or hardware process) to perform the operation and returns.
-Once the third-party process has finished, the callback has to call the function ``LLUI_DISPLAY_flushDone``.
-
-This test checks that the implementation of ``LLUI_DISPLAY_IMPL_flush`` is not a blocking function.
-
-Dependencies
-------------
-
-*All dependencies are retrieved transitively by MicroEJ Module Manager*.
-
-Source
-------
-
-N/A
-
-Restrictions
-------------
-
-None.
-
-..
-    Copyright 2021-2022 MicroEJ Corp. All rights reserved.
-    Use of this source code is governed by a BSD-style license that can be found with this software.
-
-
diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/config.properties b/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/config.properties
deleted file mode 100644
index 2d6e2bf..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/config.properties
+++ /dev/null
@@ -1,100 +0,0 @@
-# Properties
-#
-# Copyright 2021-2022 MicroEJ Corp. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be found with this software.
-
-###############################################################################
-# 						Testsuite Configuration Options
-#
-# Usage: 
-#   Uncomment and set options marked '[required]'. 
-#   Other options are set with a value that shall not be changed by default.
-# 
-# Each option can be declared outside this file as a system property:
-# In MicroEJ SDK, select 'Window' > 'Preferences' > 'Ant' > 'Runtime' > 'Properties'
-# This can be useful to avoid to share absolute file-system locations in this file.
-# In this case, it overrides the option defined in this file if any.
-# Moreover, options related to local setup (absolute file-system locations, trace ip & port)
-# can be extracted to the file 'local.properties' which is ignored for source control.   
-#
-# This file respects the Java properties file convention: the OS path
-# must use the UNIX path convention (path separator is '/'). The WINDOWS
-# paths must have been converted manually replacing '\' by '/' or by '\\'.
-###############################################################################
-
-###############################################################################
-# Target Platform [required]
-###############################################################################
-
-# defined in module.ant
-#target.platform.dir=
-
-###############################################################################
-# BSP Connection [required]
-# Uncomment one and only one option block depending on how the target Platform is connected to BSP.  
-# See https://docs.microej.com/en/latest/PlatformDeveloperGuide/platformCreation.html
-###############################################################################
-
-# No BSP Connection
-#microej.testsuite.properties.deploy.dir.microejapp=[absolute_path]
-#microej.testsuite.properties.deploy.dir.microejlib=[absolute_path]
-#microej.testsuite.properties.deploy.dir.microejinc=[absolute_path]
-#microej.testsuite.properties.deploy.bsp.microejscript=[absolute_path]
-
-# Partial BSP Connection
-#microej.testsuite.properties.deploy.bsp.root.dir=[absolute_path]
-#microej.testsuite.properties.deploy.bsp.microejscript=true
-
-# Full BSP Connection
-microej.testsuite.properties.deploy.bsp.microejscript=true
-
-###############################################################################
-# Trace Redirection (System.out)
-# [required] when trace is redirected by 'Serial to Socket Transmitter' tool,
-# otherwise the trace is assumed to be redirected by 'run.bat' or 'run.sh' script.
-###############################################################################
-
-microej.testsuite.properties.testsuite.trace.ip=localhost
-microej.testsuite.properties.testsuite.trace.port=5555
-
-# Platform specific option to redirect trace on dedicated UART
-#microej.testsuite.properties.debug.traces.uart=SET
-
-###############################################################################
-# Tests to run
-###############################################################################
-
-# Comma separated list of patterns of files that must be included	
-test.run.includes.pattern=**/_AllTests_*.class
-# Comma separated list of patterns of files that must be excluded (defaults to inner classes)
-test.run.excludes.pattern=**/*$*.class
-
-#######################################################################
-# Advanced Options
-# These options shall not be changed by default.
-###############################################################################
-
-# The execution target (`MICROJVM` to execute on Device, `S3` to execute on Simulator)
-target.vm.name=MICROJVM
-
-# The deploy tool to run after the build of the microejapp.o (defaults to 'Platform Configuration Additions')
-microej.testsuite.properties.microejtool.deploy.name=deployToolBSPRun
-
-# Set the verbose or not. Possible values: `true` or `false`
-# When this option is set to `true`, the harness will output the execution trace.
-microej.testsuite.verbose=true
-
-# The testsuite timeout (in seconds)
-microej.testsuite.timeout=600
-
-# The number of times we'll retry a test if it fails
-microej.testsuite.retry.count=1
-
-# Retry a test unless this pattern is shown
-microej.testsuite.retry.unless=VM START
-
-# A jvm args to pass to the testsuite harness
-microej.testsuite.jvmArgs=-Xmx768m
-
-# A jvm args to pass to launch scripts forked vm
-microej.testsuite.properties.launch.properties.jvm=-Xmx2048M
diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/launchers/java-testsuite-runner-ui3.launch b/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/launchers/java-testsuite-runner-ui3.launch
deleted file mode 100644
index 38d25ff..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/launchers/java-testsuite-runner-ui3.launch
+++ /dev/null
@@ -1,163 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
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diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/module.ant b/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/module.ant
deleted file mode 100644
index af03c84..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/module.ant
+++ /dev/null
@@ -1,30 +0,0 @@
-
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diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/module.ivy b/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/module.ivy
deleted file mode 100644
index 69833a1..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/module.ivy
+++ /dev/null
@@ -1,34 +0,0 @@
-
- 
-	
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-		
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diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/src/test/java/com/microej/ui/tests/MicroejUiValidation.java b/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/src/test/java/com/microej/ui/tests/MicroejUiValidation.java
deleted file mode 100644
index 4d45257..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/src/test/java/com/microej/ui/tests/MicroejUiValidation.java
+++ /dev/null
@@ -1,435 +0,0 @@
-/*
- * Java
- *
- * Copyright 2021-2022 MicroEJ Corp. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be found with this software.
- */
-package com.microej.ui.tests;
-
-import static org.junit.Assert.assertEquals;
-import static org.junit.Assert.assertTrue;
-
-import org.junit.BeforeClass;
-import org.junit.Test;
-
-import ej.bon.Constants;
-import ej.bon.Util;
-import ej.microui.MicroUI;
-import ej.microui.display.Colors;
-import ej.microui.display.Display;
-import ej.microui.display.GraphicsContext;
-import ej.microui.display.Painter;
-
-/**
- * MicroEJ UI Validation tests.
- */
-public class MicroejUiValidation {
-
-	private static final String VERSION = "1.1.0";
-
-	/**
-	 * Properties suffix: add "-Dcom.microej.ui.tests.xxx=xxx" in your JRE tab
-	 */
-	private static final String PROPERTY_SUFFIX = "com.microej.ui.tests.";
-
-	/**
-	 * Property to fix each test time; default value is 10s.
-	 */
-	private static final String OPTION_CLOCK_NB_SECONDS = "clock.seconds";
-	private static final int DEFAULT_TIME_TEST_SECONDS = 10;
-
-	/**
-	 * Property to define a test area smaller than the size of the display. Relevant if it is a round display or if the
-	 * pixels at the corners have been given special treatment. The default value is 0.
-	 *
-	 * @see testBackBufferRestore
-	 */
-	private static final String OPTION_TEST_AREA_OFFSET = "area.offset";
-	private static final int DEFAULT_TEST_AREA_OFFSET = 0;
-
-	/**
-	 * Property to fix the flush time tolerance. This value must be lower than hardware flush time.
-	 */
-	private static final String OPTION_FLUSH_TOLERANCE_NB_US = "flush.tolerance.us";
-	private static final int DEFAULT_TIME_TOLERANCE_US = 200;
-
-	private static void printProduct() {
-		final String sep = "*****************************************************************************************************";
-		System.out.println(sep);
-		System.out.println("*                                  MicroEJ UI Validation - " + VERSION
-				+ "                                  *");
-		System.out.println(sep);
-		System.out.println(
-				"* Copyright 2021-2022 MicroEJ Corp. All rights reserved.                                            *");
-		System.out.println(
-				"* Use of this source code is governed by a BSD-style license that can be found with this software.  *");
-		System.out.println(sep);
-		System.out.println();
-	}
-
-	private static int getOptionAsInt(String optionName, int defaultValue, String unit) {
-		String propertyName = PROPERTY_SUFFIX + optionName;
-		String valueStr = System.getProperty(propertyName);
-		int value;
-		if (valueStr == null) {
-			value = defaultValue;
-			System.out.println("Property '" + propertyName + "' is not set (default to '" + value + "' " + unit + ")");
-		} else {
-			try {
-				value = Integer.parseInt(valueStr);
-				System.out.println("Property '" + propertyName + "' is set to '" + value + "' " + unit);
-			} catch (NumberFormatException e) {
-				value = defaultValue;
-				System.out.println("Property '" + propertyName + "' is invalid (set to '" + valueStr + "', default to '"
-						+ value + "' " + unit + ")");
-			}
-		}
-		return value;
-	}
-
-	/**
-	 * @throws java.lang.Exception
-	 *             If an error occurred.
-	 */
-	@BeforeClass
-	public static void setUpBeforeClass() throws Exception {
-		MicroUI.start();
-		printProduct();
-	}
-
-	/**
-	 * Tests the LLUI_DISPLAY_IMPL_flush implementation: the LCD tearing (flickering).
-	 * 

-	 * Shows alternately black and white screens. The tearing effect is visible when the screen is cut in two or more
-	 * parts.
-	 */
-	@Test
-	public void testTearingFullScreen() {
-		System.out.println("-> Check LCD tearing: full screen (LLUI_DISPLAY_IMPL_flush validation)...");
-		int nbSeconds = getOptionAsInt(OPTION_CLOCK_NB_SECONDS, DEFAULT_TIME_TEST_SECONDS, "second(s)");
-
-		Display display = Display.getDisplay();
-		GraphicsContext gc = display.getGraphicsContext();
-
-		// Check if a message is printed every seconds in terminal:
-		long timeStart = System.currentTimeMillis();
-		long nbMilliSeconds = nbSeconds * 1000;
-		while (true) {
-			gc.setColor(Colors.WHITE);
-			Painter.fillRectangle(gc, 0, 0, display.getWidth(), display.getHeight());
-			display.flush();
-			gc.setColor(Colors.BLACK);
-			Painter.fillRectangle(gc, 0, 0, display.getWidth(), display.getHeight());
-			display.flush();
-			long time = System.currentTimeMillis();
-			long delta = time - timeStart;
-			if (delta > nbMilliSeconds) {
-				break; // end of test
-			}
-		}
-	}
-
-	/**
-	 * Tests the LLUI_DISPLAY_IMPL_flush implementation: the LCD tearing (flickering).
-	 * 

-	 * Shows a vertical black band that moves as fast as possible on a white background. The tearing effect is visible
-	 * when the vertical band is cut in two or more parts.
-	 */
-	@Test
-	public void testTearingVerticalBand() {
-		System.out.println("-> Check LCD tearing: black band (LLUI_DISPLAY_IMPL_flush validation)...");
-
-		Display display = Display.getDisplay();
-		GraphicsContext g = display.getGraphicsContext();
-		int displayWidth = display.getWidth();
-		int displayHeight = display.getHeight();
-
-		// retrieve test time
-		int nbSeconds = getOptionAsInt(OPTION_CLOCK_NB_SECONDS, DEFAULT_TIME_TEST_SECONDS, "second(s)");
-
-		long timeStart = System.currentTimeMillis();
-		long nbMilliSeconds = nbSeconds * 1000;
-		int bandWidth = displayWidth / 10;
-		int bandX = 0;
-		int bandXIncrement = 4;
-
-		do {
-
-			// draw background
-			g.setColor(Colors.WHITE);
-			Painter.fillRectangle(g, 0, 0, displayWidth, displayHeight);
-
-			// draw band
-			g.setColor(Colors.BLACK);
-			Painter.fillRectangle(g, bandX, 0, bandWidth, displayHeight);
-
-			// flush content
-			display.flush();
-
-			// get next band position
-			bandX += bandXIncrement;
-			if (bandX + bandWidth >= displayWidth || bandX <= 0) {
-				bandXIncrement = -bandXIncrement;
-			}
-
-		} while (System.currentTimeMillis() - timeStart < nbMilliSeconds);
-	}
-
-	/**
-	 * Called by {@link #testDrawingTime()} to force a flush and wait the end of this flush.
-	 */
-	private void forceFlushAndWait() {
-		Display display = Display.getDisplay();
-		GraphicsContext gc = display.getGraphicsContext();
-
-		// have to draw something to "enable" the flush
-		Painter.writePixel(gc, 0, 0);
-		Painter.writePixel(gc, display.getWidth() - 1, display.getHeight() - 1);
-
-		display.flush();
-		display.waitFlushCompleted();
-	}
-
-	/**
-	 * Called by {@link #testDrawingTime()} to get the framerate time according a given drawing time.
-	 */
-	private int getFramerateTimeUs(int drawingTimeUs) {
-
-		int nbLoops = 20;
-		long timeCounter = 0;
-		long drawingTimeNs = drawingTimeUs * 1000;
-
-		forceFlushAndWait();
-
-		for (int i = nbLoops; --i >= 0;) {
-
-			long t0 = Util.platformTimeNanos();
-
-			// simulate some drawings
-			while (Util.platformTimeNanos() - t0 < drawingTimeNs) {
-				;
-			}
-
-			forceFlushAndWait();
-
-			long t1 = Util.platformTimeNanos();
-			timeCounter += (t1 - t0);
-		}
-		return (int) (timeCounter / 1000 / nbLoops);
-	}
-
-	/**
-	 * Called by {@link #testDrawingTime()} to find the maximum drawing time without exceed framerate time.
-	 */
-	private int adjustDrawingTime(int drawingTimeUs, int drawingTimeStepUs, int framerateTimeRefUs,
-			int framerateTimeToleranceUs) {
-
-		int framerateWithDrawingTimeUs = framerateTimeRefUs;
-		while (framerateWithDrawingTimeUs < framerateTimeRefUs + framerateTimeToleranceUs) {
-			drawingTimeUs += drawingTimeStepUs;
-			framerateWithDrawingTimeUs = getFramerateTimeUs(drawingTimeUs);
-			// System.out.println(drawingTimeUs + " " + framerateWithDrawingTimeUs);
-		}
-		return drawingTimeUs - drawingTimeStepUs;
-	}
-
-	/**
-	 * Called by {@link #testDrawingTime()} to print a report
-	 */
-	private void printFramerateReport(float frequency, int div, int framerateTimeUs, int flushTimeMs) {
-		System.out.print("To have an animation at ");
-		System.out.print(frequency / div);
-		System.out.print(" Hz, the drawing time cannot be higher than ");
-		System.out.print(((float) (framerateTimeUs * div - flushTimeMs)) / 1000);
-		System.out.print(" ms.\n");
-	}
-
-	/**
-	 * Tests the LLUI_DISPLAY_IMPL_flush implementation: the drawing time.
-	 * 

-	 * Determinates the maximum drawing time to have the better framerate as possible.
-	 */
-	@Test
-	public void testDrawingTime() {
-
-		// retrieve flush time tolereance
-		int framerateTimeToleranceUs = getOptionAsInt(OPTION_FLUSH_TOLERANCE_NB_US, DEFAULT_TIME_TOLERANCE_US, "us");
-
-		// retrieve LCD framerate time and frequency
-		int framerateTimeUs = getFramerateTimeUs(0);
-		float framerateHz = 1000000 / (float) framerateTimeUs;
-		System.out.println("LCD framerate time is " + framerateTimeUs + " us (" + framerateHz + " Hz)");
-
-		// retrieve maximum drawing time to have better framerate
-		System.out.println("Retrieve the maximal drawing time (this will take several seconds)...");
-		int drawingTimeUs = 0;
-		for (int drawingTimeStepUs = 1000; drawingTimeStepUs >= 10; drawingTimeStepUs /= 10) {
-			drawingTimeUs = adjustDrawingTime(drawingTimeUs, drawingTimeStepUs, framerateTimeUs,
-					framerateTimeToleranceUs);
-		}
-
-		// retrieve flush time thanks to LCD framerate and maximum drawing time
-		int flushTimeUs = framerateTimeUs - drawingTimeUs;
-
-		// print reports
-		System.out.println("The flush time is " + flushTimeUs + " us");
-		printFramerateReport(framerateHz, 1, framerateTimeUs, flushTimeUs);
-		printFramerateReport(framerateHz, 2, framerateTimeUs, flushTimeUs);
-		printFramerateReport(framerateHz, 3, framerateTimeUs, flushTimeUs);
-	}
-
-	/**
-	 * Tests the LLUI_DISPLAY_IMPL_flush implementation: the post-flush copy.
-	 * 

-	 * This test is only useful when the implementation of LLUI_DISPLAY_IMPL_flush uses the "Switch" mode
-	 * (and not "Copy" or "Direct" modes, see Platform Development Guide). In that case, the post-flush copy restores
-	 * the "past": the previous application drawings made before the flush.
-	 * 

-	 * After the flush step, the LLUI_DISPLAY_IMPL_flush implementation has to restore the content of
-	 * returned backbuffer with the content of flushed back buffer (MicroUI specification). This prevent to the MicroUI
-	 * application to draw again the old content.
-	 */
-	@Test
-	public void testBackBufferRestore() {
-
-		Display display = Display.getDisplay();
-		GraphicsContext g = display.getGraphicsContext();
-		int displayWidth = display.getWidth();
-		int displayHeight = display.getHeight();
-
-		int areaOffset = getOptionAsInt(OPTION_TEST_AREA_OFFSET, DEFAULT_TEST_AREA_OFFSET, " pixel(s)");
-
-		// draw in all back buffer and flush it
-		g.setColor(Colors.WHITE);
-		Painter.fillRectangle(g, 0, 0, displayWidth, displayHeight);
-		display.flush();
-
-		// draw in all back buffer and flush it
-		g.setColor(Colors.BLACK);
-		Painter.fillRectangle(g, 0, 0, displayWidth, displayHeight);
-		display.flush();
-
-		// here: the copy after a flush has to restore the content of
-		// flushed backbuffer: a black rectangle. If the color is not black,
-		// it means the post copy has not been performed or not fully done.
-
-		checkAreaCorners(g, "[A] testBackBufferRestore at ", areaOffset, areaOffset, displayWidth - areaOffset - 1,
-				displayHeight - areaOffset - 1, Colors.BLACK);
-
-		// draw in all back buffer and flush it
-		g.setColor(Colors.WHITE);
-		Painter.fillRectangle(g, 0, 0, displayWidth, displayHeight);
-		display.flush();
-
-		// draw in the middle of back buffer and flush it
-		int offset = 10;
-		g.setColor(Colors.BLACK);
-		g.setClip(offset + areaOffset, offset + areaOffset, displayWidth - 2 * (offset + areaOffset),
-				displayHeight - 2 * (offset + areaOffset));
-		Painter.fillRectangle(g, 0, 0, displayWidth, displayHeight);
-		display.flush();
-
-		// here: the copy after a flush has to restore the content of
-		// flushed backbuffer: a black rectangle in the middle of white background.
-
-		checkAreaCorners(g, "[B] testBackBufferRestore at ", areaOffset, areaOffset, displayWidth - areaOffset - 1,
-				displayHeight - areaOffset - 1, Colors.WHITE);
-
-		checkAreaCorners(g, "[C] testBackBufferRestore at ", areaOffset + offset, areaOffset + offset,
-				displayWidth - areaOffset - offset - 1, displayHeight - areaOffset - offset - 1, Colors.BLACK);
-
-	}
-
-	/**
-	 * Compares the color of pixels at each corner of a rectangle with coordinates given in parameters.
-	 */
-	private void checkAreaCorners(GraphicsContext g, String msgTest, int recStartX, int recStartY, int recEndX,
-			int recEndY, int expectedColor) {
-
-		Display display = Display.getDisplay();
-		int displayColor = display.getDisplayColor(expectedColor);
-
-		boolean successful = false;
-		try {
-			String assertMessage = msgTest + String.valueOf(recStartX) + "," + String.valueOf(recStartY);
-			assertEquals(assertMessage, displayColor, g.readPixel(recStartX, recStartY) & 0xffffff);
-
-			assertMessage = msgTest + String.valueOf(recEndX) + "," + String.valueOf(recStartY);
-			assertEquals(assertMessage, displayColor, g.readPixel(recEndX, recStartY) & 0xffffff);
-
-			assertMessage = msgTest + String.valueOf(recStartX) + "," + String.valueOf(recEndY);
-			assertEquals(assertMessage, displayColor, g.readPixel(recStartX, recEndY) & 0xffffff);
-
-			assertMessage = msgTest + String.valueOf(recEndX) + "," + String.valueOf(recEndY);
-			assertEquals(assertMessage, displayColor, g.readPixel(recEndX, recEndY) & 0xffffff);
-			successful = true;
-		} finally {
-			if (!successful) {
-				System.out.println(
-						"If an exception occurs here, it is because you may have a round display or irrelevant corners on your display. \nPlease, configure the property \""
-								+ PROPERTY_SUFFIX + OPTION_TEST_AREA_OFFSET + "\".");
-			}
-		}
-
-	}
-
-	/**
-	 * Tests the LLUI_DISPLAY_IMPL_flush implementation: this function should be as fast as possible.
-	 * 

-	 * The "flush" consists to update the content of the display frame buffer with the content of the application buffer
-	 * (back buffer). This update may be instantaneous ("Switch" mode) or can take some time ("Copy" mode): memory copy,
-	 * serial data sent, etc. The implementation has to delegate the "flush" to another asynchronous task (hardware or
-	 * software) in order to return as soon as possible. This allows the application to do other work during this
-	 * update.
-	 * 

-	 * The Graphics Engine has the responsability to wait the end of this asynchronous task before allowing a new
-	 * drawing in the application buffer. This waiting is automatic (first call to a drawing method after a flush is
-	 * blocker) or explicit (call to {@link Display#waitFlushCompleted()}).
-	 * 

-	 * The LLUI_DISPLAY_impl.h implementation must call LLUI_DISPLAY_flushDone() to unlock the
-	 * Graphics Engine.
-	 * 

-	 * This test has no meaning on the simulator. It is automatically disabled.
-	 */
-	@Test
-	public void testFlushTime() {
-
-		if (isRunningOnSimulator()) {
-			// see method comment
-			return;
-		}
-
-		Display display = Display.getDisplay();
-		GraphicsContext g = display.getGraphicsContext();
-		int displayWidth = display.getWidth();
-		int displayHeight = display.getHeight();
-
-		long tFlush = 0;
-		long tWait = 0;
-
-		// perform several tests
-		for (int i = 10; --i >= 0;) {
-
-			// draw in all back buffer
-			g.setColor(Colors.WHITE);
-			Painter.fillRectangle(g, 0, 0, displayWidth, displayHeight);
-
-			long t0 = System.currentTimeMillis();
-			display.flush();
-			long t1 = System.currentTimeMillis();
-			display.waitFlushCompleted();
-			long t2 = System.currentTimeMillis();
-
-			tFlush += (t1 - t0);
-			tWait += (t2 - t1);
-		}
-
-		System.out.println("flush time (several iterations): " + tFlush);
-		System.out.println("wait flush time (several iterations): " + tWait);
-		assertTrue("flush time must be smaller than waitFlush time", tFlush < tWait);
-	}
-
-	private boolean isRunningOnSimulator() {
-		return Constants.getBoolean("com.microej.library.microui.onS3");
-	}
-}
diff --git a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/validation/microej-testsuite-common.properties b/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/validation/microej-testsuite-common.properties
deleted file mode 100644
index eee5738..0000000
--- a/nxpvee-mimxrt595-evk-round-validation/ui/ui3/java-testsuite-runner-ui3/validation/microej-testsuite-common.properties
+++ /dev/null
@@ -1,17 +0,0 @@
-# Testsuite Application Options
-#
-# Copyright 2021-2022 MicroEJ Corp. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be found with this software.
-
-# Java memory settings
-core.memory.immortal.memory=RAM
-core.memory.immortal.size=4096
-core.memory.javaheap.memory=RAM
-core.memory.javaheap.size=65536
-core.memory.javaheapsum.size=65536
-core.memory.thread.block.size=512
-core.memory.thread.max.size=10
-core.memory.threads.memory=RAM
-core.memory.threads.pool.memory=RAM
-core.memory.threads.pool.size=30
-core.memory.threads.size=18
diff --git a/west.yml b/west.yml
index 0dfcb89..6296562 100644
--- a/west.yml
+++ b/west.yml
@@ -8,11 +8,15 @@ manifest:
   projects:
     - name: mcux-sdk
       remote: nxp-mcuxpresso
-      revision: MCUX_2.12.0
-      path: nxp-vee-rt595/nxpvee-mimxrt595-evk-round-bsp/mcux-sdk/core
+      revision: 5fb76f2d51ac20
+      path: nxp-vee-rt595/bsp/mcux-sdk/core
+    - name: CMSIS_5
+      revision: MCUX_2.15.000
+      remote: nxp-mcuxpresso
+      path: nxp-vee-rt595/bsp/mcux-sdk/core/CMSIS
     - name: FreeRTOS-Kernel
-      revision: MCUX_2.12.0
+      revision: MCUX_2.15.100
       remote: nxp-mcuxpresso
-      path: nxp-vee-rt595/nxpvee-mimxrt595-evk-round-bsp/mcux-sdk/rtos/freertos/freertos-kernel
+      path: nxp-vee-rt595/bsp/mcux-sdk/rtos/freertos/freertos-kernel
   self:
     path: nxp-vee-rt595